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09cae750 | 1 | /* Definition of RISC-V target for GNU compiler. |
7adcbafe | 2 | Copyright (C) 2011-2022 Free Software Foundation, Inc. |
09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
4 | Based on MIPS target for GNU compiler. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef GCC_RISCV_PROTOS_H | |
23 | #define GCC_RISCV_PROTOS_H | |
24 | ||
25 | /* Symbol types we understand. The order of this list must match that of | |
26 | the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ | |
27 | enum riscv_symbol_type { | |
28 | SYMBOL_ABSOLUTE, | |
29 | SYMBOL_PCREL, | |
30 | SYMBOL_GOT_DISP, | |
31 | SYMBOL_TLS, | |
32 | SYMBOL_TLS_LE, | |
33 | SYMBOL_TLS_IE, | |
34 | SYMBOL_TLS_GD | |
35 | }; | |
36 | #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1) | |
37 | ||
e53b6e56 | 38 | /* Routines implemented in riscv.cc. */ |
09cae750 PD |
39 | extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); |
40 | extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); | |
b8506a8a | 41 | extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool); |
b8506a8a | 42 | extern int riscv_address_insns (rtx, machine_mode, bool); |
09cae750 PD |
43 | extern int riscv_const_insns (rtx); |
44 | extern int riscv_split_const_insns (rtx); | |
45 | extern int riscv_load_store_insns (rtx, rtx_insn *); | |
46 | extern rtx riscv_emit_move (rtx, rtx); | |
a923a463 | 47 | extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *, bool); |
09cae750 PD |
48 | extern bool riscv_split_symbol_type (enum riscv_symbol_type); |
49 | extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type); | |
a923a463 | 50 | extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode, bool); |
b8506a8a | 51 | extern bool riscv_legitimize_move (machine_mode, rtx, rtx); |
09cae750 PD |
52 | extern rtx riscv_subword (rtx, bool); |
53 | extern bool riscv_split_64bit_move_p (rtx, rtx); | |
54 | extern void riscv_split_doubleword_move (rtx, rtx); | |
55 | extern const char *riscv_output_move (rtx, rtx); | |
8cad5b14 | 56 | extern const char *riscv_output_return (); |
09cae750 PD |
57 | #ifdef RTX_CODE |
58 | extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx); | |
59 | extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx); | |
60 | extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx); | |
4f475391 | 61 | extern void riscv_expand_conditional_move (rtx, rtx, rtx, rtx_code, rtx, rtx); |
09cae750 PD |
62 | #endif |
63 | extern rtx riscv_legitimize_call_address (rtx); | |
64 | extern void riscv_set_return_address (rtx, rtx); | |
65 | extern bool riscv_expand_block_move (rtx, rtx, rtx); | |
66 | extern rtx riscv_return_addr (int, rtx); | |
3496ca4e | 67 | extern poly_int64 riscv_initial_elimination_offset (int, int); |
09cae750 | 68 | extern void riscv_expand_prologue (void); |
fd1e52dc | 69 | extern void riscv_expand_epilogue (int); |
d0ebdd9f | 70 | extern bool riscv_epilogue_uses (unsigned int); |
09cae750 | 71 | extern bool riscv_can_use_return_insn (void); |
6ed01e6b | 72 | extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode); |
6ed01e6b | 73 | extern bool riscv_expand_block_move (rtx, rtx, rtx); |
88108b27 | 74 | extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *); |
d0e0c130 KC |
75 | extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *); |
76 | extern bool riscv_gpr_save_operation_p (rtx); | |
b4feb49c | 77 | extern void riscv_reinit (void); |
03f33657 | 78 | extern bool riscv_v_ext_enabled_vector_mode_p (machine_mode); |
09cae750 | 79 | |
e53b6e56 | 80 | /* Routines implemented in riscv-c.cc. */ |
09cae750 | 81 | void riscv_cpu_cpp_builtins (cpp_reader *); |
7d935cdd | 82 | void riscv_register_pragmas (void); |
09cae750 | 83 | |
e53b6e56 | 84 | /* Routines implemented in riscv-builtins.cc. */ |
09cae750 | 85 | extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *); |
b8506a8a | 86 | extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int); |
09cae750 PD |
87 | extern tree riscv_builtin_decl (unsigned int, bool); |
88 | extern void riscv_init_builtins (void); | |
89 | ||
e53b6e56 | 90 | /* Routines implemented in riscv-common.cc. */ |
f908b69c | 91 | extern std::string riscv_arch_str (bool version_p = true); |
b4feb49c | 92 | extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t); |
8e966210 | 93 | |
e0a5b313 KC |
94 | extern bool riscv_hard_regno_rename_ok (unsigned, unsigned); |
95 | ||
de6320a8 CB |
96 | rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt); |
97 | ||
72eb8335 KC |
98 | /* Information about one CPU we know about. */ |
99 | struct riscv_cpu_info { | |
100 | /* This CPU's canonical name. */ | |
101 | const char *name; | |
102 | ||
103 | /* Default arch for this CPU, could be NULL if no default arch. */ | |
104 | const char *arch; | |
105 | ||
106 | /* Which automaton to use for tuning. */ | |
107 | const char *tune; | |
108 | }; | |
109 | ||
110 | extern const riscv_cpu_info *riscv_find_cpu (const char *); | |
111 | ||
b4feb49c | 112 | /* Routines implemented in riscv-selftests.cc. */ |
113 | #if CHECKING_P | |
114 | namespace selftest { | |
115 | extern void riscv_run_selftests (void); | |
116 | } // namespace selftest | |
117 | #endif | |
118 | ||
7d935cdd JZZ |
119 | namespace riscv_vector { |
120 | /* Routines implemented in riscv-vector-builtins.cc. */ | |
121 | extern void init_builtins (void); | |
122 | extern const char *mangle_builtin_type (const_tree); | |
123 | #ifdef GCC_TARGET_H | |
124 | extern bool verify_type_context (location_t, type_context_kind, const_tree, bool); | |
125 | #endif | |
126 | extern void handle_pragma_vector (void); | |
cbd50570 JZZ |
127 | extern tree builtin_decl (unsigned, bool); |
128 | extern rtx expand_builtin (unsigned int, tree, rtx); | |
7d935cdd JZZ |
129 | } |
130 | ||
cbd50570 JZZ |
131 | /* We classify builtin types into two classes: |
132 | 1. General builtin class which is defined in riscv_builtins. | |
133 | 2. Vector builtin class which is a special builtin architecture | |
134 | that implement intrinsic short into "pragma". */ | |
135 | enum riscv_builtin_class | |
136 | { | |
137 | RISCV_BUILTIN_GENERAL, | |
138 | RISCV_BUILTIN_VECTOR | |
139 | }; | |
140 | ||
141 | const unsigned int RISCV_BUILTIN_SHIFT = 1; | |
142 | ||
143 | /* Mask that selects the riscv_builtin_class part of a function code. */ | |
144 | const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1; | |
145 | ||
09cae750 | 146 | #endif /* ! GCC_RISCV_PROTOS_H */ |