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09cae750 1/* Definition of RISC-V target for GNU compiler.
83ffe9cd 2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
09cae750
PD
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 3, or (at your option)
11any later version.
12
13GCC is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
21
22#ifndef GCC_RISCV_PROTOS_H
23#define GCC_RISCV_PROTOS_H
24
942ab49b
PN
25#include "memmodel.h"
26
09cae750
PD
27/* Symbol types we understand. The order of this list must match that of
28 the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */
29enum riscv_symbol_type {
30 SYMBOL_ABSOLUTE,
31 SYMBOL_PCREL,
32 SYMBOL_GOT_DISP,
33 SYMBOL_TLS,
34 SYMBOL_TLS_LE,
35 SYMBOL_TLS_IE,
36 SYMBOL_TLS_GD
37};
38#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
39
96ad6ab2
CM
40/* Classifies an address.
41
42 ADDRESS_REG
43 A natural register + offset address. The register satisfies
44 riscv_valid_base_register_p and the offset is a const_arith_operand.
45
46 ADDRESS_LO_SUM
47 A LO_SUM rtx. The first operand is a valid base register and
48 the second operand is a symbolic address.
49
50 ADDRESS_CONST_INT
51 A signed 16-bit constant address.
52
53 ADDRESS_SYMBOLIC:
54 A constant symbolic address. */
55enum riscv_address_type {
56 ADDRESS_REG,
57 ADDRESS_LO_SUM,
58 ADDRESS_CONST_INT,
59 ADDRESS_SYMBOLIC
60};
61
62/* Information about an address described by riscv_address_type.
63
64 ADDRESS_CONST_INT
65 No fields are used.
66
67 ADDRESS_REG
68 REG is the base register and OFFSET is the constant offset.
69
70 ADDRESS_LO_SUM
71 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
72 is the type of symbol it references.
73
74 ADDRESS_SYMBOLIC
75 SYMBOL_TYPE is the type of symbol that the address references. */
76struct riscv_address_info {
77 enum riscv_address_type type;
78 rtx reg;
79 rtx offset;
80 enum riscv_symbol_type symbol_type;
81};
82
e53b6e56 83/* Routines implemented in riscv.cc. */
09cae750
PD
84extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
85extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
b8506a8a 86extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
42360427
CM
87extern enum reg_class riscv_index_reg_class ();
88extern int riscv_regno_ok_for_index_p (int);
b8506a8a 89extern int riscv_address_insns (rtx, machine_mode, bool);
09cae750
PD
90extern int riscv_const_insns (rtx);
91extern int riscv_split_const_insns (rtx);
92extern int riscv_load_store_insns (rtx, rtx_insn *);
93extern rtx riscv_emit_move (rtx, rtx);
05302544 94extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);
09cae750
PD
95extern bool riscv_split_symbol_type (enum riscv_symbol_type);
96extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
05302544 97extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode);
b8506a8a 98extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
09cae750
PD
99extern rtx riscv_subword (rtx, bool);
100extern bool riscv_split_64bit_move_p (rtx, rtx);
101extern void riscv_split_doubleword_move (rtx, rtx);
102extern const char *riscv_output_move (rtx, rtx);
8cad5b14 103extern const char *riscv_output_return ();
02fcaf41 104
09cae750 105#ifdef RTX_CODE
8ae83274 106extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0);
09cae750
PD
107extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
108extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
99bfdb07 109extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y);
09cae750 110#endif
8e7ffe12 111extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
09cae750
PD
112extern rtx riscv_legitimize_call_address (rtx);
113extern void riscv_set_return_address (rtx, rtx);
114extern bool riscv_expand_block_move (rtx, rtx, rtx);
115extern rtx riscv_return_addr (int, rtx);
3496ca4e 116extern poly_int64 riscv_initial_elimination_offset (int, int);
09cae750 117extern void riscv_expand_prologue (void);
fd1e52dc 118extern void riscv_expand_epilogue (int);
d0ebdd9f 119extern bool riscv_epilogue_uses (unsigned int);
09cae750 120extern bool riscv_can_use_return_insn (void);
6ed01e6b 121extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
6ed01e6b 122extern bool riscv_expand_block_move (rtx, rtx, rtx);
88108b27 123extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
d0e0c130
KC
124extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
125extern bool riscv_gpr_save_operation_p (rtx);
b4feb49c 126extern void riscv_reinit (void);
f556cd8b 127extern poly_uint64 riscv_regmode_natural_size (machine_mode);
7e924ba3 128extern bool riscv_v_ext_vector_mode_p (machine_mode);
12847288 129extern bool riscv_v_ext_tuple_mode_p (machine_mode);
33b153ff 130extern bool riscv_v_ext_vls_mode_p (machine_mode);
6ae5565e 131extern int riscv_get_v_regno_alignment (machine_mode);
787ac959 132extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
f797260a
PN
133extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
134extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
942ab49b 135extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel);
09cae750 136
e53b6e56 137/* Routines implemented in riscv-c.cc. */
09cae750 138void riscv_cpu_cpp_builtins (cpp_reader *);
7d935cdd 139void riscv_register_pragmas (void);
09cae750 140
e53b6e56 141/* Routines implemented in riscv-builtins.cc. */
09cae750 142extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
60bd33bc 143extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *);
b8506a8a 144extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
09cae750
PD
145extern tree riscv_builtin_decl (unsigned int, bool);
146extern void riscv_init_builtins (void);
147
e53b6e56 148/* Routines implemented in riscv-common.cc. */
f908b69c 149extern std::string riscv_arch_str (bool version_p = true);
b4feb49c 150extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t);
8e966210 151
e0a5b313
KC
152extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
153
de6320a8 154rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt);
9243c3d1 155rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt);
de6320a8 156
72eb8335
KC
157/* Information about one CPU we know about. */
158struct riscv_cpu_info {
159 /* This CPU's canonical name. */
160 const char *name;
161
162 /* Default arch for this CPU, could be NULL if no default arch. */
163 const char *arch;
164
165 /* Which automaton to use for tuning. */
166 const char *tune;
167};
168
169extern const riscv_cpu_info *riscv_find_cpu (const char *);
170
b4feb49c 171/* Routines implemented in riscv-selftests.cc. */
172#if CHECKING_P
173namespace selftest {
3b6d44f4 174void riscv_run_selftests (void);
b4feb49c 175} // namespace selftest
176#endif
177
7d935cdd 178namespace riscv_vector {
fa144175 179#define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
272e119d 180#define RVV_VUNDEF(MODE) \
7caa1ae5
JZZ
181 gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \
182 UNSPEC_VUNDEF)
51fd69ec
JZ
183enum insn_type
184{
185 RVV_MISC_OP = 1,
186 RVV_UNOP = 2,
92f2ec41
LD
187 RVV_UNOP_M = RVV_UNOP + 2,
188 RVV_UNOP_MU = RVV_UNOP + 2,
189 RVV_UNOP_TU = RVV_UNOP + 2,
190 RVV_UNOP_TUMU = RVV_UNOP + 2,
51fd69ec 191 RVV_BINOP = 3,
bf9eee73 192 RVV_BINOP_MU = RVV_BINOP + 2,
44f244e4 193 RVV_BINOP_TU = RVV_BINOP + 2,
6ae5565e 194 RVV_BINOP_TUMU = RVV_BINOP + 2,
e0600a02
JZ
195 RVV_MERGE_OP = 4,
196 RVV_CMP_OP = 4,
197 RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand. */
c48d7a6e 198 RVV_TERNOP = 5,
6ae5565e 199 RVV_TERNOP_MU = RVV_TERNOP + 1,
0d2673e9 200 RVV_TERNOP_TU = RVV_TERNOP + 1,
6ae5565e 201 RVV_TERNOP_TUMU = RVV_TERNOP + 1,
88604bd1 202 RVV_WIDEN_TERNOP = 4,
a99dc11f 203 RVV_SCALAR_MOV_OP = 4, /* +1 for VUNDEF according to vector.md. */
51795b91 204 RVV_SLIDE_OP = 4, /* Dest, VUNDEF, source and offset. */
9aabf81f 205 RVV_COMPRESS_OP = 4,
f048af2a
JZZ
206 RVV_GATHER_M_OP = 5,
207 RVV_SCATTER_M_OP = 4,
da93c41c 208 RVV_REDUCTION_OP = 3,
8390a2af 209 RVV_REDUCTION_TU_OP = RVV_REDUCTION_OP + 2,
51fd69ec 210};
3b16afeb
JZZ
211enum vlmul_type
212{
213 LMUL_1 = 0,
214 LMUL_2 = 1,
215 LMUL_4 = 2,
216 LMUL_8 = 3,
217 LMUL_RESERVED = 4,
218 LMUL_F8 = 5,
219 LMUL_F4 = 6,
220 LMUL_F2 = 7,
ec99ffab 221 NUM_LMUL = 8
3b16afeb 222};
9243c3d1
JZZ
223
224enum avl_type
225{
226 NONVLMAX,
227 VLMAX,
228};
7d935cdd 229/* Routines implemented in riscv-vector-builtins.cc. */
3b6d44f4
JZZ
230void init_builtins (void);
231const char *mangle_builtin_type (const_tree);
7d935cdd 232#ifdef GCC_TARGET_H
3b6d44f4 233bool verify_type_context (location_t, type_context_kind, const_tree, bool);
631e86b7
JZ
234bool expand_vec_perm_const (machine_mode, machine_mode, rtx, rtx, rtx,
235 const vec_perm_indices &);
7d935cdd 236#endif
3b6d44f4
JZZ
237void handle_pragma_vector (void);
238tree builtin_decl (unsigned, bool);
60bd33bc 239gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *);
3b6d44f4 240rtx expand_builtin (unsigned int, tree, rtx);
7caa1ae5
JZZ
241bool check_builtin_call (location_t, vec<location_t>, unsigned int,
242 tree, unsigned int, tree *);
3b6d44f4 243bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
51fd69ec 244bool legitimize_move (rtx, rtx);
cd0c433e 245void emit_vlmax_vsetvl (machine_mode, rtx);
40fc8e3d 246void emit_hard_vlmax_vsetvl (machine_mode, rtx);
2203da51 247void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
47ffabaf 248void emit_vlmax_fp_insn (unsigned, int, rtx *, rtx = 0);
c48d7a6e 249void emit_vlmax_ternary_insn (unsigned, int, rtx *, rtx = 0);
0a3b1a09 250void emit_vlmax_fp_ternary_insn (unsigned, int, rtx *, rtx = 0);
2203da51 251void emit_nonvlmax_insn (unsigned, int, rtx *, rtx);
51795b91
RD
252void emit_vlmax_slide_insn (unsigned, rtx *);
253void emit_nonvlmax_slide_tu_insn (unsigned, rtx *, rtx);
e0600a02
JZ
254void emit_vlmax_merge_insn (unsigned, int, rtx *);
255void emit_vlmax_cmp_insn (unsigned, rtx *);
256void emit_vlmax_cmp_mu_insn (unsigned, rtx *);
a1b23dcf 257void emit_vlmax_masked_mu_insn (unsigned, int, rtx *);
8390a2af 258void emit_scalar_move_insn (unsigned, rtx *, rtx = 0);
51795b91 259void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx);
3b6d44f4
JZZ
260enum vlmul_type get_vlmul (machine_mode);
261unsigned int get_ratio (machine_mode);
12847288
JZZ
262unsigned int get_nf (machine_mode);
263machine_mode get_subpart_mode (machine_mode);
3b6d44f4
JZZ
264int get_ta (rtx);
265int get_ma (rtx);
266int get_avl_type (rtx);
267unsigned int calculate_ratio (unsigned int, enum vlmul_type);
f556cd8b
JZZ
268enum tail_policy
269{
270 TAIL_UNDISTURBED = 0,
271 TAIL_AGNOSTIC = 1,
9243c3d1 272 TAIL_ANY = 2,
f556cd8b
JZZ
273};
274
275enum mask_policy
276{
277 MASK_UNDISTURBED = 0,
278 MASK_AGNOSTIC = 1,
9243c3d1 279 MASK_ANY = 2,
f556cd8b 280};
8390a2af
JZ
281
282enum class reduction_type
283{
284 UNORDERED,
285 FOLD_LEFT,
286 MASK_LEN_FOLD_LEFT,
287};
9243c3d1
JZZ
288enum tail_policy get_prefer_tail_policy ();
289enum mask_policy get_prefer_mask_policy ();
a143c3f7 290rtx get_avl_type_rtx (enum avl_type);
6c9bcb6c 291opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
12847288 292opt_machine_mode get_tuple_mode (machine_mode, unsigned int);
3b6d44f4
JZZ
293bool simm5_p (rtx);
294bool neg_simm5_p (rtx);
a035d133 295#ifdef RTX_CODE
3b6d44f4 296bool has_vi_variant_p (rtx_code, rtx);
e0600a02
JZ
297void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
298bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
92f2ec41 299void expand_cond_len_unop (rtx_code, rtx *);
44f244e4 300void expand_cond_len_binop (rtx_code, rtx *);
8390a2af
JZ
301void expand_reduction (rtx_code, rtx *, rtx,
302 reduction_type = reduction_type::UNORDERED);
a035d133 303#endif
51fd69ec 304bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode,
3cb0fa12 305 bool, void (*)(rtx *, rtx));
ec99ffab 306rtx gen_scalar_move_mask (machine_mode);
1bff101b
JZZ
307
308/* RVV vector register sizes.
309 TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to
310 support other values in the future. */
311enum vlen_enum
312{
313 RVV_32 = 32,
314 RVV_64 = 64,
315 RVV_65536 = 65536
316};
317bool slide1_sew64_helper (int, machine_mode, machine_mode,
318 machine_mode, rtx *);
db4f7a9b 319rtx gen_avl_for_scalar_move (rtx);
51fd69ec 320void expand_tuple_move (rtx *);
2d76f2b4 321machine_mode preferred_simd_mode (scalar_mode);
1349f530 322machine_mode get_mask_mode (machine_mode);
003f388c 323void expand_vec_series (rtx, rtx, rtx);
1c1a9d8e 324void expand_vec_init (rtx, rtx);
2418cdfc 325void expand_vec_perm (rtx, rtx, rtx, rtx);
55dcf277 326void expand_select_vl (rtx *);
d42d199e 327void expand_load_store (rtx *, bool);
f048af2a 328void expand_gather_scatter (rtx *, bool);
0d2673e9 329void expand_cond_len_ternop (unsigned, rtx *);
6ae5565e 330void prepare_ternary_operands (rtx *, bool = false);
fe578886 331void expand_lanes_load_store (rtx *, bool);
47ffabaf 332
5ed88078 333/* Rounding mode bitfield for fixed point VXRM. */
47ffabaf 334enum fixed_point_rounding_mode
5ed88078
JZ
335{
336 VXRM_RNU,
337 VXRM_RNE,
338 VXRM_RDN,
339 VXRM_ROD
340};
47ffabaf 341
7f4644f8
PL
342/* Rounding mode bitfield for floating point FRM. The value of enum comes
343 from the below link.
344 https://github.com/riscv/riscv-isa-manual/blob/main/src/f-st-ext.adoc#floating-point-control-and-status-register
345 */
47ffabaf 346enum floating_point_rounding_mode
8cd140d3 347{
7f4644f8
PL
348 FRM_RNE = 0, /* Aka 0b000. */
349 FRM_RTZ = 1, /* Aka 0b001. */
350 FRM_RDN = 2, /* Aka 0b010. */
351 FRM_RUP = 3, /* Aka 0b011. */
352 FRM_RMM = 4, /* Aka 0b100. */
353 FRM_DYN = 7, /* Aka 0b111. */
4d1e97f5
PL
354 FRM_STATIC_MIN = FRM_RNE,
355 FRM_STATIC_MAX = FRM_RMM,
4cede0de
PL
356 FRM_DYN_EXIT = 8,
357 FRM_DYN_CALL = 9,
358 FRM_NONE = 10,
8cd140d3 359};
25907509 360
4cede0de 361enum floating_point_rounding_mode get_frm_mode (rtx);
25907509
RD
362opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
363 poly_uint64);
364unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
7d935cdd
JZZ
365}
366
cbd50570
JZZ
367/* We classify builtin types into two classes:
368 1. General builtin class which is defined in riscv_builtins.
369 2. Vector builtin class which is a special builtin architecture
370 that implement intrinsic short into "pragma". */
371enum riscv_builtin_class
372{
373 RISCV_BUILTIN_GENERAL,
374 RISCV_BUILTIN_VECTOR
375};
376
377const unsigned int RISCV_BUILTIN_SHIFT = 1;
378
379/* Mask that selects the riscv_builtin_class part of a function code. */
380const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;
381
02fcaf41
CM
382/* Routines implemented in thead.cc. */
383extern bool th_mempair_operands_p (rtx[4], bool, machine_mode);
384extern void th_mempair_order_operands (rtx[4], bool, machine_mode);
385extern void th_mempair_prepare_save_restore_operands (rtx[4], bool,
386 machine_mode,
387 int, HOST_WIDE_INT,
388 int, HOST_WIDE_INT);
389extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode);
390#ifdef RTX_CODE
391extern const char*
392th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
393#endif
394
065be0ff 395extern bool riscv_use_divmod_expander (void);
1d4d302a
YW
396void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
397
09cae750 398#endif /* ! GCC_RISCV_PROTOS_H */