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09cae750 | 1 | /* Definition of RISC-V target for GNU compiler. |
83ffe9cd | 2 | Copyright (C) 2011-2023 Free Software Foundation, Inc. |
09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
4 | Based on MIPS target for GNU compiler. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef GCC_RISCV_PROTOS_H | |
23 | #define GCC_RISCV_PROTOS_H | |
24 | ||
942ab49b PN |
25 | #include "memmodel.h" |
26 | ||
09cae750 PD |
27 | /* Symbol types we understand. The order of this list must match that of |
28 | the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ | |
29 | enum riscv_symbol_type { | |
30 | SYMBOL_ABSOLUTE, | |
31 | SYMBOL_PCREL, | |
32 | SYMBOL_GOT_DISP, | |
33 | SYMBOL_TLS, | |
34 | SYMBOL_TLS_LE, | |
35 | SYMBOL_TLS_IE, | |
36 | SYMBOL_TLS_GD | |
37 | }; | |
38 | #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1) | |
39 | ||
96ad6ab2 CM |
40 | /* Classifies an address. |
41 | ||
42 | ADDRESS_REG | |
43 | A natural register + offset address. The register satisfies | |
44 | riscv_valid_base_register_p and the offset is a const_arith_operand. | |
45 | ||
46 | ADDRESS_LO_SUM | |
47 | A LO_SUM rtx. The first operand is a valid base register and | |
48 | the second operand is a symbolic address. | |
49 | ||
50 | ADDRESS_CONST_INT | |
51 | A signed 16-bit constant address. | |
52 | ||
53 | ADDRESS_SYMBOLIC: | |
54 | A constant symbolic address. */ | |
55 | enum riscv_address_type { | |
56 | ADDRESS_REG, | |
57 | ADDRESS_LO_SUM, | |
58 | ADDRESS_CONST_INT, | |
59 | ADDRESS_SYMBOLIC | |
60 | }; | |
61 | ||
62 | /* Information about an address described by riscv_address_type. | |
63 | ||
64 | ADDRESS_CONST_INT | |
65 | No fields are used. | |
66 | ||
67 | ADDRESS_REG | |
68 | REG is the base register and OFFSET is the constant offset. | |
69 | ||
70 | ADDRESS_LO_SUM | |
71 | REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE | |
72 | is the type of symbol it references. | |
73 | ||
74 | ADDRESS_SYMBOLIC | |
75 | SYMBOL_TYPE is the type of symbol that the address references. */ | |
76 | struct riscv_address_info { | |
77 | enum riscv_address_type type; | |
78 | rtx reg; | |
79 | rtx offset; | |
80 | enum riscv_symbol_type symbol_type; | |
81 | }; | |
82 | ||
e53b6e56 | 83 | /* Routines implemented in riscv.cc. */ |
09cae750 PD |
84 | extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); |
85 | extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); | |
b8506a8a | 86 | extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool); |
42360427 CM |
87 | extern enum reg_class riscv_index_reg_class (); |
88 | extern int riscv_regno_ok_for_index_p (int); | |
b8506a8a | 89 | extern int riscv_address_insns (rtx, machine_mode, bool); |
09cae750 PD |
90 | extern int riscv_const_insns (rtx); |
91 | extern int riscv_split_const_insns (rtx); | |
92 | extern int riscv_load_store_insns (rtx, rtx_insn *); | |
93 | extern rtx riscv_emit_move (rtx, rtx); | |
05302544 | 94 | extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *); |
09cae750 PD |
95 | extern bool riscv_split_symbol_type (enum riscv_symbol_type); |
96 | extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type); | |
05302544 | 97 | extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode); |
b8506a8a | 98 | extern bool riscv_legitimize_move (machine_mode, rtx, rtx); |
09cae750 PD |
99 | extern rtx riscv_subword (rtx, bool); |
100 | extern bool riscv_split_64bit_move_p (rtx, rtx); | |
101 | extern void riscv_split_doubleword_move (rtx, rtx); | |
102 | extern const char *riscv_output_move (rtx, rtx); | |
8cad5b14 | 103 | extern const char *riscv_output_return (); |
02fcaf41 | 104 | |
09cae750 | 105 | #ifdef RTX_CODE |
8ae83274 | 106 | extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0); |
09cae750 PD |
107 | extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx); |
108 | extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx); | |
99bfdb07 | 109 | extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y); |
09cae750 | 110 | #endif |
8e7ffe12 | 111 | extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx); |
09cae750 PD |
112 | extern rtx riscv_legitimize_call_address (rtx); |
113 | extern void riscv_set_return_address (rtx, rtx); | |
114 | extern bool riscv_expand_block_move (rtx, rtx, rtx); | |
115 | extern rtx riscv_return_addr (int, rtx); | |
3496ca4e | 116 | extern poly_int64 riscv_initial_elimination_offset (int, int); |
09cae750 | 117 | extern void riscv_expand_prologue (void); |
fd1e52dc | 118 | extern void riscv_expand_epilogue (int); |
d0ebdd9f | 119 | extern bool riscv_epilogue_uses (unsigned int); |
09cae750 | 120 | extern bool riscv_can_use_return_insn (void); |
6ed01e6b | 121 | extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode); |
6ed01e6b | 122 | extern bool riscv_expand_block_move (rtx, rtx, rtx); |
88108b27 | 123 | extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *); |
d0e0c130 KC |
124 | extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *); |
125 | extern bool riscv_gpr_save_operation_p (rtx); | |
b4feb49c | 126 | extern void riscv_reinit (void); |
f556cd8b | 127 | extern poly_uint64 riscv_regmode_natural_size (machine_mode); |
7e924ba3 | 128 | extern bool riscv_v_ext_vector_mode_p (machine_mode); |
12847288 | 129 | extern bool riscv_v_ext_tuple_mode_p (machine_mode); |
33b153ff | 130 | extern bool riscv_v_ext_vls_mode_p (machine_mode); |
6ae5565e | 131 | extern int riscv_get_v_regno_alignment (machine_mode); |
787ac959 | 132 | extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); |
f797260a PN |
133 | extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); |
134 | extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); | |
942ab49b | 135 | extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); |
09cae750 | 136 | |
e53b6e56 | 137 | /* Routines implemented in riscv-c.cc. */ |
09cae750 | 138 | void riscv_cpu_cpp_builtins (cpp_reader *); |
7d935cdd | 139 | void riscv_register_pragmas (void); |
09cae750 | 140 | |
e53b6e56 | 141 | /* Routines implemented in riscv-builtins.cc. */ |
09cae750 | 142 | extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *); |
60bd33bc | 143 | extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *); |
b8506a8a | 144 | extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int); |
09cae750 PD |
145 | extern tree riscv_builtin_decl (unsigned int, bool); |
146 | extern void riscv_init_builtins (void); | |
147 | ||
e53b6e56 | 148 | /* Routines implemented in riscv-common.cc. */ |
f908b69c | 149 | extern std::string riscv_arch_str (bool version_p = true); |
b4feb49c | 150 | extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t); |
8e966210 | 151 | |
e0a5b313 KC |
152 | extern bool riscv_hard_regno_rename_ok (unsigned, unsigned); |
153 | ||
de6320a8 | 154 | rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt); |
9243c3d1 | 155 | rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt); |
de6320a8 | 156 | |
72eb8335 KC |
157 | /* Information about one CPU we know about. */ |
158 | struct riscv_cpu_info { | |
159 | /* This CPU's canonical name. */ | |
160 | const char *name; | |
161 | ||
162 | /* Default arch for this CPU, could be NULL if no default arch. */ | |
163 | const char *arch; | |
164 | ||
165 | /* Which automaton to use for tuning. */ | |
166 | const char *tune; | |
167 | }; | |
168 | ||
169 | extern const riscv_cpu_info *riscv_find_cpu (const char *); | |
170 | ||
b4feb49c | 171 | /* Routines implemented in riscv-selftests.cc. */ |
172 | #if CHECKING_P | |
173 | namespace selftest { | |
3b6d44f4 | 174 | void riscv_run_selftests (void); |
b4feb49c | 175 | } // namespace selftest |
176 | #endif | |
177 | ||
7d935cdd | 178 | namespace riscv_vector { |
fa144175 | 179 | #define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM) |
272e119d | 180 | #define RVV_VUNDEF(MODE) \ |
7caa1ae5 JZZ |
181 | gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \ |
182 | UNSPEC_VUNDEF) | |
51fd69ec JZ |
183 | enum insn_type |
184 | { | |
185 | RVV_MISC_OP = 1, | |
186 | RVV_UNOP = 2, | |
187 | RVV_BINOP = 3, | |
bf9eee73 | 188 | RVV_BINOP_MU = RVV_BINOP + 2, |
44f244e4 | 189 | RVV_BINOP_TU = RVV_BINOP + 2, |
6ae5565e | 190 | RVV_BINOP_TUMU = RVV_BINOP + 2, |
e0600a02 JZ |
191 | RVV_MERGE_OP = 4, |
192 | RVV_CMP_OP = 4, | |
193 | RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand. */ | |
a1b23dcf | 194 | RVV_UNOP_MU = RVV_UNOP + 2, /* Likewise. */ |
d42d199e | 195 | RVV_UNOP_M = RVV_UNOP + 2, /* Likewise. */ |
c48d7a6e | 196 | RVV_TERNOP = 5, |
6ae5565e | 197 | RVV_TERNOP_MU = RVV_TERNOP + 1, |
0d2673e9 | 198 | RVV_TERNOP_TU = RVV_TERNOP + 1, |
6ae5565e | 199 | RVV_TERNOP_TUMU = RVV_TERNOP + 1, |
88604bd1 | 200 | RVV_WIDEN_TERNOP = 4, |
a99dc11f | 201 | RVV_SCALAR_MOV_OP = 4, /* +1 for VUNDEF according to vector.md. */ |
51795b91 | 202 | RVV_SLIDE_OP = 4, /* Dest, VUNDEF, source and offset. */ |
9aabf81f | 203 | RVV_COMPRESS_OP = 4, |
f048af2a JZZ |
204 | RVV_GATHER_M_OP = 5, |
205 | RVV_SCATTER_M_OP = 4, | |
da93c41c | 206 | RVV_REDUCTION_OP = 3, |
8390a2af | 207 | RVV_REDUCTION_TU_OP = RVV_REDUCTION_OP + 2, |
51fd69ec | 208 | }; |
3b16afeb JZZ |
209 | enum vlmul_type |
210 | { | |
211 | LMUL_1 = 0, | |
212 | LMUL_2 = 1, | |
213 | LMUL_4 = 2, | |
214 | LMUL_8 = 3, | |
215 | LMUL_RESERVED = 4, | |
216 | LMUL_F8 = 5, | |
217 | LMUL_F4 = 6, | |
218 | LMUL_F2 = 7, | |
ec99ffab | 219 | NUM_LMUL = 8 |
3b16afeb | 220 | }; |
9243c3d1 JZZ |
221 | |
222 | enum avl_type | |
223 | { | |
224 | NONVLMAX, | |
225 | VLMAX, | |
226 | }; | |
7d935cdd | 227 | /* Routines implemented in riscv-vector-builtins.cc. */ |
3b6d44f4 JZZ |
228 | void init_builtins (void); |
229 | const char *mangle_builtin_type (const_tree); | |
7d935cdd | 230 | #ifdef GCC_TARGET_H |
3b6d44f4 | 231 | bool verify_type_context (location_t, type_context_kind, const_tree, bool); |
631e86b7 JZ |
232 | bool expand_vec_perm_const (machine_mode, machine_mode, rtx, rtx, rtx, |
233 | const vec_perm_indices &); | |
7d935cdd | 234 | #endif |
3b6d44f4 JZZ |
235 | void handle_pragma_vector (void); |
236 | tree builtin_decl (unsigned, bool); | |
60bd33bc | 237 | gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *); |
3b6d44f4 | 238 | rtx expand_builtin (unsigned int, tree, rtx); |
7caa1ae5 JZZ |
239 | bool check_builtin_call (location_t, vec<location_t>, unsigned int, |
240 | tree, unsigned int, tree *); | |
3b6d44f4 | 241 | bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
51fd69ec | 242 | bool legitimize_move (rtx, rtx); |
cd0c433e | 243 | void emit_vlmax_vsetvl (machine_mode, rtx); |
40fc8e3d | 244 | void emit_hard_vlmax_vsetvl (machine_mode, rtx); |
2203da51 | 245 | void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0); |
47ffabaf | 246 | void emit_vlmax_fp_insn (unsigned, int, rtx *, rtx = 0); |
c48d7a6e | 247 | void emit_vlmax_ternary_insn (unsigned, int, rtx *, rtx = 0); |
0a3b1a09 | 248 | void emit_vlmax_fp_ternary_insn (unsigned, int, rtx *, rtx = 0); |
2203da51 | 249 | void emit_nonvlmax_insn (unsigned, int, rtx *, rtx); |
51795b91 RD |
250 | void emit_vlmax_slide_insn (unsigned, rtx *); |
251 | void emit_nonvlmax_slide_tu_insn (unsigned, rtx *, rtx); | |
e0600a02 JZ |
252 | void emit_vlmax_merge_insn (unsigned, int, rtx *); |
253 | void emit_vlmax_cmp_insn (unsigned, rtx *); | |
254 | void emit_vlmax_cmp_mu_insn (unsigned, rtx *); | |
a1b23dcf | 255 | void emit_vlmax_masked_mu_insn (unsigned, int, rtx *); |
8390a2af | 256 | void emit_scalar_move_insn (unsigned, rtx *, rtx = 0); |
51795b91 | 257 | void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx); |
3b6d44f4 JZZ |
258 | enum vlmul_type get_vlmul (machine_mode); |
259 | unsigned int get_ratio (machine_mode); | |
12847288 JZZ |
260 | unsigned int get_nf (machine_mode); |
261 | machine_mode get_subpart_mode (machine_mode); | |
3b6d44f4 JZZ |
262 | int get_ta (rtx); |
263 | int get_ma (rtx); | |
264 | int get_avl_type (rtx); | |
265 | unsigned int calculate_ratio (unsigned int, enum vlmul_type); | |
f556cd8b JZZ |
266 | enum tail_policy |
267 | { | |
268 | TAIL_UNDISTURBED = 0, | |
269 | TAIL_AGNOSTIC = 1, | |
9243c3d1 | 270 | TAIL_ANY = 2, |
f556cd8b JZZ |
271 | }; |
272 | ||
273 | enum mask_policy | |
274 | { | |
275 | MASK_UNDISTURBED = 0, | |
276 | MASK_AGNOSTIC = 1, | |
9243c3d1 | 277 | MASK_ANY = 2, |
f556cd8b | 278 | }; |
8390a2af JZ |
279 | |
280 | enum class reduction_type | |
281 | { | |
282 | UNORDERED, | |
283 | FOLD_LEFT, | |
284 | MASK_LEN_FOLD_LEFT, | |
285 | }; | |
9243c3d1 JZZ |
286 | enum tail_policy get_prefer_tail_policy (); |
287 | enum mask_policy get_prefer_mask_policy (); | |
a143c3f7 | 288 | rtx get_avl_type_rtx (enum avl_type); |
6c9bcb6c | 289 | opt_machine_mode get_vector_mode (scalar_mode, poly_uint64); |
12847288 | 290 | opt_machine_mode get_tuple_mode (machine_mode, unsigned int); |
3b6d44f4 JZZ |
291 | bool simm5_p (rtx); |
292 | bool neg_simm5_p (rtx); | |
a035d133 | 293 | #ifdef RTX_CODE |
3b6d44f4 | 294 | bool has_vi_variant_p (rtx_code, rtx); |
e0600a02 JZ |
295 | void expand_vec_cmp (rtx, rtx_code, rtx, rtx); |
296 | bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); | |
44f244e4 | 297 | void expand_cond_len_binop (rtx_code, rtx *); |
8390a2af JZ |
298 | void expand_reduction (rtx_code, rtx *, rtx, |
299 | reduction_type = reduction_type::UNORDERED); | |
a035d133 | 300 | #endif |
51fd69ec | 301 | bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, |
3cb0fa12 | 302 | bool, void (*)(rtx *, rtx)); |
ec99ffab | 303 | rtx gen_scalar_move_mask (machine_mode); |
1bff101b JZZ |
304 | |
305 | /* RVV vector register sizes. | |
306 | TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to | |
307 | support other values in the future. */ | |
308 | enum vlen_enum | |
309 | { | |
310 | RVV_32 = 32, | |
311 | RVV_64 = 64, | |
312 | RVV_65536 = 65536 | |
313 | }; | |
314 | bool slide1_sew64_helper (int, machine_mode, machine_mode, | |
315 | machine_mode, rtx *); | |
db4f7a9b | 316 | rtx gen_avl_for_scalar_move (rtx); |
51fd69ec | 317 | void expand_tuple_move (rtx *); |
2d76f2b4 | 318 | machine_mode preferred_simd_mode (scalar_mode); |
1349f530 | 319 | machine_mode get_mask_mode (machine_mode); |
003f388c | 320 | void expand_vec_series (rtx, rtx, rtx); |
1c1a9d8e | 321 | void expand_vec_init (rtx, rtx); |
2418cdfc | 322 | void expand_vec_perm (rtx, rtx, rtx, rtx); |
55dcf277 | 323 | void expand_select_vl (rtx *); |
d42d199e | 324 | void expand_load_store (rtx *, bool); |
f048af2a | 325 | void expand_gather_scatter (rtx *, bool); |
0d2673e9 | 326 | void expand_cond_len_ternop (unsigned, rtx *); |
6ae5565e | 327 | void prepare_ternary_operands (rtx *, bool = false); |
47ffabaf | 328 | |
5ed88078 | 329 | /* Rounding mode bitfield for fixed point VXRM. */ |
47ffabaf | 330 | enum fixed_point_rounding_mode |
5ed88078 JZ |
331 | { |
332 | VXRM_RNU, | |
333 | VXRM_RNE, | |
334 | VXRM_RDN, | |
335 | VXRM_ROD | |
336 | }; | |
47ffabaf | 337 | |
7f4644f8 PL |
338 | /* Rounding mode bitfield for floating point FRM. The value of enum comes |
339 | from the below link. | |
340 | https://github.com/riscv/riscv-isa-manual/blob/main/src/f-st-ext.adoc#floating-point-control-and-status-register | |
341 | */ | |
47ffabaf | 342 | enum floating_point_rounding_mode |
8cd140d3 | 343 | { |
7f4644f8 PL |
344 | FRM_RNE = 0, /* Aka 0b000. */ |
345 | FRM_RTZ = 1, /* Aka 0b001. */ | |
346 | FRM_RDN = 2, /* Aka 0b010. */ | |
347 | FRM_RUP = 3, /* Aka 0b011. */ | |
348 | FRM_RMM = 4, /* Aka 0b100. */ | |
349 | FRM_DYN = 7, /* Aka 0b111. */ | |
4d1e97f5 PL |
350 | FRM_STATIC_MIN = FRM_RNE, |
351 | FRM_STATIC_MAX = FRM_RMM, | |
4cede0de PL |
352 | FRM_DYN_EXIT = 8, |
353 | FRM_DYN_CALL = 9, | |
354 | FRM_NONE = 10, | |
8cd140d3 | 355 | }; |
25907509 | 356 | |
4cede0de | 357 | enum floating_point_rounding_mode get_frm_mode (rtx); |
25907509 RD |
358 | opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode, |
359 | poly_uint64); | |
360 | unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool); | |
7d935cdd JZZ |
361 | } |
362 | ||
cbd50570 JZZ |
363 | /* We classify builtin types into two classes: |
364 | 1. General builtin class which is defined in riscv_builtins. | |
365 | 2. Vector builtin class which is a special builtin architecture | |
366 | that implement intrinsic short into "pragma". */ | |
367 | enum riscv_builtin_class | |
368 | { | |
369 | RISCV_BUILTIN_GENERAL, | |
370 | RISCV_BUILTIN_VECTOR | |
371 | }; | |
372 | ||
373 | const unsigned int RISCV_BUILTIN_SHIFT = 1; | |
374 | ||
375 | /* Mask that selects the riscv_builtin_class part of a function code. */ | |
376 | const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1; | |
377 | ||
02fcaf41 CM |
378 | /* Routines implemented in thead.cc. */ |
379 | extern bool th_mempair_operands_p (rtx[4], bool, machine_mode); | |
380 | extern void th_mempair_order_operands (rtx[4], bool, machine_mode); | |
381 | extern void th_mempair_prepare_save_restore_operands (rtx[4], bool, | |
382 | machine_mode, | |
383 | int, HOST_WIDE_INT, | |
384 | int, HOST_WIDE_INT); | |
385 | extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode); | |
386 | #ifdef RTX_CODE | |
387 | extern const char* | |
388 | th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); | |
389 | #endif | |
390 | ||
065be0ff | 391 | extern bool riscv_use_divmod_expander (void); |
1d4d302a YW |
392 | void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); |
393 | ||
09cae750 | 394 | #endif /* ! GCC_RISCV_PROTOS_H */ |