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09cae750 1/* Definition of RISC-V target for GNU compiler.
83ffe9cd 2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
09cae750
PD
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 3, or (at your option)
11any later version.
12
13GCC is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
21
22#ifndef GCC_RISCV_PROTOS_H
23#define GCC_RISCV_PROTOS_H
24
942ab49b
PN
25#include "memmodel.h"
26
09cae750
PD
27/* Symbol types we understand. The order of this list must match that of
28 the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */
29enum riscv_symbol_type {
30 SYMBOL_ABSOLUTE,
31 SYMBOL_PCREL,
32 SYMBOL_GOT_DISP,
33 SYMBOL_TLS,
34 SYMBOL_TLS_LE,
35 SYMBOL_TLS_IE,
36 SYMBOL_TLS_GD
37};
38#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
39
e53b6e56 40/* Routines implemented in riscv.cc. */
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PD
41extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
42extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
b8506a8a 43extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
b8506a8a 44extern int riscv_address_insns (rtx, machine_mode, bool);
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PD
45extern int riscv_const_insns (rtx);
46extern int riscv_split_const_insns (rtx);
47extern int riscv_load_store_insns (rtx, rtx_insn *);
48extern rtx riscv_emit_move (rtx, rtx);
05302544 49extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);
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PD
50extern bool riscv_split_symbol_type (enum riscv_symbol_type);
51extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
05302544 52extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode);
b8506a8a 53extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
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PD
54extern rtx riscv_subword (rtx, bool);
55extern bool riscv_split_64bit_move_p (rtx, rtx);
56extern void riscv_split_doubleword_move (rtx, rtx);
57extern const char *riscv_output_move (rtx, rtx);
8cad5b14 58extern const char *riscv_output_return ();
02fcaf41 59
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60#ifdef RTX_CODE
61extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
62extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
63extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
64#endif
8e7ffe12 65extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
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PD
66extern rtx riscv_legitimize_call_address (rtx);
67extern void riscv_set_return_address (rtx, rtx);
68extern bool riscv_expand_block_move (rtx, rtx, rtx);
69extern rtx riscv_return_addr (int, rtx);
3496ca4e 70extern poly_int64 riscv_initial_elimination_offset (int, int);
09cae750 71extern void riscv_expand_prologue (void);
fd1e52dc 72extern void riscv_expand_epilogue (int);
d0ebdd9f 73extern bool riscv_epilogue_uses (unsigned int);
09cae750 74extern bool riscv_can_use_return_insn (void);
6ed01e6b 75extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
6ed01e6b 76extern bool riscv_expand_block_move (rtx, rtx, rtx);
88108b27 77extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
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78extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
79extern bool riscv_gpr_save_operation_p (rtx);
b4feb49c 80extern void riscv_reinit (void);
f556cd8b 81extern poly_uint64 riscv_regmode_natural_size (machine_mode);
7e924ba3 82extern bool riscv_v_ext_vector_mode_p (machine_mode);
12847288 83extern bool riscv_v_ext_tuple_mode_p (machine_mode);
787ac959 84extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
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PN
85extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
86extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
942ab49b 87extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel);
09cae750 88
e53b6e56 89/* Routines implemented in riscv-c.cc. */
09cae750 90void riscv_cpu_cpp_builtins (cpp_reader *);
7d935cdd 91void riscv_register_pragmas (void);
09cae750 92
e53b6e56 93/* Routines implemented in riscv-builtins.cc. */
09cae750 94extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
60bd33bc 95extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *);
b8506a8a 96extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
09cae750
PD
97extern tree riscv_builtin_decl (unsigned int, bool);
98extern void riscv_init_builtins (void);
99
e53b6e56 100/* Routines implemented in riscv-common.cc. */
f908b69c 101extern std::string riscv_arch_str (bool version_p = true);
b4feb49c 102extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t);
8e966210 103
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104extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
105
de6320a8 106rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt);
9243c3d1 107rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt);
de6320a8 108
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KC
109/* Information about one CPU we know about. */
110struct riscv_cpu_info {
111 /* This CPU's canonical name. */
112 const char *name;
113
114 /* Default arch for this CPU, could be NULL if no default arch. */
115 const char *arch;
116
117 /* Which automaton to use for tuning. */
118 const char *tune;
119};
120
121extern const riscv_cpu_info *riscv_find_cpu (const char *);
122
b4feb49c 123/* Routines implemented in riscv-selftests.cc. */
124#if CHECKING_P
125namespace selftest {
3b6d44f4 126void riscv_run_selftests (void);
b4feb49c 127} // namespace selftest
128#endif
129
7d935cdd 130namespace riscv_vector {
fa144175 131#define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
272e119d 132#define RVV_VUNDEF(MODE) \
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133 gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \
134 UNSPEC_VUNDEF)
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135enum insn_type
136{
137 RVV_MISC_OP = 1,
138 RVV_UNOP = 2,
139 RVV_BINOP = 3,
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140 RVV_MERGE_OP = 4,
141 RVV_CMP_OP = 4,
142 RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand. */
51fd69ec 143};
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144enum vlmul_type
145{
146 LMUL_1 = 0,
147 LMUL_2 = 1,
148 LMUL_4 = 2,
149 LMUL_8 = 3,
150 LMUL_RESERVED = 4,
151 LMUL_F8 = 5,
152 LMUL_F4 = 6,
153 LMUL_F2 = 7,
ec99ffab 154 NUM_LMUL = 8
3b16afeb 155};
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156
157enum avl_type
158{
159 NONVLMAX,
160 VLMAX,
161};
7d935cdd 162/* Routines implemented in riscv-vector-builtins.cc. */
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163void init_builtins (void);
164const char *mangle_builtin_type (const_tree);
7d935cdd 165#ifdef GCC_TARGET_H
3b6d44f4 166bool verify_type_context (location_t, type_context_kind, const_tree, bool);
7d935cdd 167#endif
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168void handle_pragma_vector (void);
169tree builtin_decl (unsigned, bool);
60bd33bc 170gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *);
3b6d44f4 171rtx expand_builtin (unsigned int, tree, rtx);
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172bool check_builtin_call (location_t, vec<location_t>, unsigned int,
173 tree, unsigned int, tree *);
3b6d44f4 174bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
51fd69ec 175bool legitimize_move (rtx, rtx);
cd0c433e 176void emit_vlmax_vsetvl (machine_mode, rtx);
40fc8e3d 177void emit_hard_vlmax_vsetvl (machine_mode, rtx);
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178void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
179void emit_nonvlmax_insn (unsigned, int, rtx *, rtx);
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180void emit_vlmax_merge_insn (unsigned, int, rtx *);
181void emit_vlmax_cmp_insn (unsigned, rtx *);
182void emit_vlmax_cmp_mu_insn (unsigned, rtx *);
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183enum vlmul_type get_vlmul (machine_mode);
184unsigned int get_ratio (machine_mode);
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185unsigned int get_nf (machine_mode);
186machine_mode get_subpart_mode (machine_mode);
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187int get_ta (rtx);
188int get_ma (rtx);
189int get_avl_type (rtx);
190unsigned int calculate_ratio (unsigned int, enum vlmul_type);
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191enum tail_policy
192{
193 TAIL_UNDISTURBED = 0,
194 TAIL_AGNOSTIC = 1,
9243c3d1 195 TAIL_ANY = 2,
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196};
197
198enum mask_policy
199{
200 MASK_UNDISTURBED = 0,
201 MASK_AGNOSTIC = 1,
9243c3d1 202 MASK_ANY = 2,
f556cd8b 203};
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204enum tail_policy get_prefer_tail_policy ();
205enum mask_policy get_prefer_mask_policy ();
a143c3f7 206rtx get_avl_type_rtx (enum avl_type);
6c9bcb6c 207opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
12847288 208opt_machine_mode get_tuple_mode (machine_mode, unsigned int);
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209bool simm5_p (rtx);
210bool neg_simm5_p (rtx);
a035d133 211#ifdef RTX_CODE
3b6d44f4 212bool has_vi_variant_p (rtx_code, rtx);
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213void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
214bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
a035d133 215#endif
51fd69ec 216bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode,
3cb0fa12 217 bool, void (*)(rtx *, rtx));
ec99ffab 218rtx gen_scalar_move_mask (machine_mode);
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219
220/* RVV vector register sizes.
221 TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to
222 support other values in the future. */
223enum vlen_enum
224{
225 RVV_32 = 32,
226 RVV_64 = 64,
227 RVV_65536 = 65536
228};
229bool slide1_sew64_helper (int, machine_mode, machine_mode,
230 machine_mode, rtx *);
db4f7a9b 231rtx gen_avl_for_scalar_move (rtx);
51fd69ec 232void expand_tuple_move (rtx *);
2d76f2b4 233machine_mode preferred_simd_mode (scalar_mode);
bf839c15 234opt_machine_mode get_mask_mode (machine_mode);
003f388c 235void expand_vec_series (rtx, rtx, rtx);
1c1a9d8e 236void expand_vec_init (rtx, rtx);
e0600a02 237void expand_vcond (rtx *);
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238/* Rounding mode bitfield for fixed point VXRM. */
239enum vxrm_field_enum
240{
241 VXRM_RNU,
242 VXRM_RNE,
243 VXRM_RDN,
244 VXRM_ROD
245};
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246/* Rounding mode bitfield for floating point FRM. */
247enum frm_field_enum
248{
249 FRM_RNE = 0b000,
250 FRM_RTZ = 0b001,
251 FRM_RDN = 0b010,
252 FRM_RUP = 0b011,
253 FRM_RMM = 0b100,
29a60c13 254 FRM_DYN = 0b111
8cd140d3 255};
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256}
257
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258/* We classify builtin types into two classes:
259 1. General builtin class which is defined in riscv_builtins.
260 2. Vector builtin class which is a special builtin architecture
261 that implement intrinsic short into "pragma". */
262enum riscv_builtin_class
263{
264 RISCV_BUILTIN_GENERAL,
265 RISCV_BUILTIN_VECTOR
266};
267
268const unsigned int RISCV_BUILTIN_SHIFT = 1;
269
270/* Mask that selects the riscv_builtin_class part of a function code. */
271const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;
272
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273/* Routines implemented in thead.cc. */
274extern bool th_mempair_operands_p (rtx[4], bool, machine_mode);
275extern void th_mempair_order_operands (rtx[4], bool, machine_mode);
276extern void th_mempair_prepare_save_restore_operands (rtx[4], bool,
277 machine_mode,
278 int, HOST_WIDE_INT,
279 int, HOST_WIDE_INT);
280extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode);
281#ifdef RTX_CODE
282extern const char*
283th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
284#endif
285
065be0ff 286extern bool riscv_use_divmod_expander (void);
09cae750 287#endif /* ! GCC_RISCV_PROTOS_H */