]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/riscv/riscv-vector-builtins.def
projects / thirdparty / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Update copyright years.
[thirdparty/gcc.git] / gcc / config / riscv / riscv-vector-builtins.def
CommitLineData
03f33657 1/* Builtins macros for RISC-V 'V' Extension for GNU compiler.
aeee4812 2 Copyright (C) 2022-2023 Free Software Foundation, Inc.
03f33657
JZZ		 3 Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 3, or (at your option)
10any later version.
11
12GCC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING3. If not see
19<http://www.gnu.org/licenses/>. */
20
21/* Use "DEF_RVV_TYPE" macro to define RVV datatype builtins.
cbd50570 22 1.The 'NAME' argument is the name exposed to users.
03f33657 23 For example, "vint32m1_t".
cbd50570 24 2.The 'NCHARS' argument is the length of ABI-name.
03f33657 25 For example, length of "__rvv_int32m1_t" is 15.
cbd50570
JZZ		 26 3.The 'ABI_NAME' argument is the ABI-name. For example, "__rvv_int32m1_t".
27 4.The 'SCALAR_TYPE' argument is associated scalar type which is used in
03f33657
JZZ		 28 "build_vector_type_for_mode". For "vint32m1_t", we use "intSI_type_node" in
29 RV64. Otherwise, we use "long_integer_type_node".
cbd50570
JZZ		 30 5.The 'VECTOR_MODE' is the machine modes of corresponding RVV type used
31 in "build_vector_type_for_mode" when TARGET_MIN_VLEN > 32.
32 For example: VECTOR_MODE = VNx2SI for "vint32m1_t".
33 6.The 'VECTOR_MODE_MIN_VLEN_32' is the machine modes of corresponding RVV
34 type used in "build_vector_type_for_mode" when TARGET_MIN_VLEN = 32. For
35 example: VECTOR_MODE_MIN_VLEN_32 = VNx1SI for "vint32m1_t".
36 7.The 'VECTOR_SUFFIX' define mode suffix for vector type.
37 For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vector = i32m1.
38 8.The 'SCALAR_SUFFIX' define mode suffix for scalar type.
39 For example: type_suffixes[VECTOR_TYPE_vin32m1_t].scalar = i32.
40 9.The 'VSETVL_SUFFIX' define mode suffix for vsetvli instruction.
41 For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vsetvl = e32m1.
42*/
03f33657
JZZ		 43
44#ifndef DEF_RVV_TYPE
0af2b2f2 45#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, \
cbd50570 46 VECTOR_MODE_MIN_VLEN_32, VECTOR_SUFFIX, SCALAR_SUFFIX, \
a143c3f7 47 VSETVL_SUFFIX, MASK_TYPE)
cbd50570
JZZ		 48#endif
49
50/* Use "DEF_RVV_OP_TYPE" macro to define RVV operand types.
51 The 'NAME' will be concatenated into intrinsic function name. */
52#ifndef DEF_RVV_OP_TYPE
53#define DEF_RVV_OP_TYPE(NAME)
54#endif
55
56/* Use "DEF_RVV_PRED_TYPE" macro to define RVV predication types.
57 The 'NAME' will be concatenated into intrinsic function name. */
58#ifndef DEF_RVV_PRED_TYPE
59#define DEF_RVV_PRED_TYPE(NAME)
03f33657
JZZ		 60#endif
61
62/* SEW/LMUL = 64:
63 Only enable when TARGET_MIN_VLEN > 32 and machine mode = VNx1BImode. */
a143c3f7 64DEF_RVV_TYPE (vbool64_t, 14, __rvv_bool64_t, boolean, VNx1BI, VOID, _b64, , , vbool64_t)
03f33657
JZZ		 65/* SEW/LMUL = 32:
66 Machine mode = VNx2BImode when TARGET_MIN_VLEN > 32.
67 Machine mode = VNx1BImode when TARGET_MIN_VLEN = 32. */
a143c3f7 68DEF_RVV_TYPE (vbool32_t, 14, __rvv_bool32_t, boolean, VNx2BI, VNx1BI, _b32, , , vbool32_t)
03f33657
JZZ		 69/* SEW/LMUL = 16:
70 Machine mode = VNx2BImode when TARGET_MIN_VLEN = 32.
71 Machine mode = VNx4BImode when TARGET_MIN_VLEN > 32. */
a143c3f7 72DEF_RVV_TYPE (vbool16_t, 14, __rvv_bool16_t, boolean, VNx4BI, VNx2BI, _b16, , , vbool16_t)
03f33657
JZZ		 73/* SEW/LMUL = 8:
74 Machine mode = VNx8BImode when TARGET_MIN_VLEN > 32.
75 Machine mode = VNx4BImode when TARGET_MIN_VLEN = 32. */
a143c3f7 76DEF_RVV_TYPE (vbool8_t, 13, __rvv_bool8_t, boolean, VNx8BI, VNx4BI, _b8, , , vbool8_t)
03f33657
JZZ		 77/* SEW/LMUL = 4:
78 Machine mode = VNx16BImode when TARGET_MIN_VLEN > 32.
79 Machine mode = VNx8BImode when TARGET_MIN_VLEN = 32. */
a143c3f7 80DEF_RVV_TYPE (vbool4_t, 13, __rvv_bool4_t, boolean, VNx16BI, VNx8BI, _b4, , , vbool4_t)
03f33657
JZZ		 81/* SEW/LMUL = 2:
82 Machine mode = VNx32BImode when TARGET_MIN_VLEN > 32.
83 Machine mode = VNx16BImode when TARGET_MIN_VLEN = 32. */
a143c3f7 84DEF_RVV_TYPE (vbool2_t, 13, __rvv_bool2_t, boolean, VNx32BI, VNx16BI, _b2, , , vbool2_t)
03f33657
JZZ		 85/* SEW/LMUL = 1:
86 Machine mode = VNx64BImode when TARGET_MIN_VLEN > 32.
87 Machine mode = VNx32BImode when TARGET_MIN_VLEN = 32. */
a143c3f7 88DEF_RVV_TYPE (vbool1_t, 13, __rvv_bool1_t, boolean, VNx64BI, VNx32BI, _b1, , , vbool1_t)
03f33657
JZZ		 89
90/* LMUL = 1/8:
91 Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1QImode. */
cbd50570 92DEF_RVV_TYPE (vint8mf8_t, 15, __rvv_int8mf8_t, intQI, VNx1QI, VOID, _i8mf8, _i8,
a143c3f7 93 _e8mf8, vbool64_t)
cbd50570 94DEF_RVV_TYPE (vuint8mf8_t, 16, __rvv_uint8mf8_t, unsigned_intQI, VNx1QI, VOID,
a143c3f7 95 _u8mf8, _u8, _e8mf8, vbool64_t)
03f33657
JZZ		 96/* LMUL = 1/4:
97 Machine mode = VNx2QImode when TARGET_MIN_VLEN > 32.
98 Machine mode = VNx1QImode when TARGET_MIN_VLEN = 32. */
cbd50570 99DEF_RVV_TYPE (vint8mf4_t, 15, __rvv_int8mf4_t, intQI, VNx2QI, VNx1QI, _i8mf4,
a143c3f7 100 _i8, _e8mf4, vbool32_t)
cbd50570 101DEF_RVV_TYPE (vuint8mf4_t, 16, __rvv_uint8mf4_t, unsigned_intQI, VNx2QI, VNx1QI,
a143c3f7 102 _u8mf4, _u8, _e8mf4, vbool32_t)
03f33657
JZZ		 103/* LMUL = 1/2:
104 Machine mode = VNx4QImode when TARGET_MIN_VLEN > 32.
105 Machine mode = VNx2QImode when TARGET_MIN_VLEN = 32. */
cbd50570 106DEF_RVV_TYPE (vint8mf2_t, 15, __rvv_int8mf2_t, intQI, VNx4QI, VNx2QI, _i8mf2,
a143c3f7 107 _i8, _e8mf2, vbool16_t)
cbd50570 108DEF_RVV_TYPE (vuint8mf2_t, 16, __rvv_uint8mf2_t, unsigned_intQI, VNx4QI, VNx2QI,
a143c3f7 109 _u8mf2, _u8, _e8mf2, vbool16_t)
03f33657
JZZ		 110/* LMUL = 1:
111 Machine mode = VNx8QImode when TARGET_MIN_VLEN > 32.
112 Machine mode = VNx4QImode when TARGET_MIN_VLEN = 32. */
cbd50570 113DEF_RVV_TYPE (vint8m1_t, 14, __rvv_int8m1_t, intQI, VNx8QI, VNx4QI, _i8m1, _i8,
a143c3f7 114 _e8m1, vbool8_t)
cbd50570 115DEF_RVV_TYPE (vuint8m1_t, 15, __rvv_uint8m1_t, unsigned_intQI, VNx8QI, VNx4QI,
a143c3f7 116 _u8m1, _u8, _e8m1, vbool8_t)
03f33657
JZZ		 117/* LMUL = 2:
118 Machine mode = VNx16QImode when TARGET_MIN_VLEN > 32.
119 Machine mode = VNx8QImode when TARGET_MIN_VLEN = 32. */
cbd50570 120DEF_RVV_TYPE (vint8m2_t, 14, __rvv_int8m2_t, intQI, VNx16QI, VNx8QI, _i8m2, _i8,
a143c3f7 121 _e8m2, vbool4_t)
cbd50570 122DEF_RVV_TYPE (vuint8m2_t, 15, __rvv_uint8m2_t, unsigned_intQI, VNx16QI, VNx8QI,
a143c3f7 123 _u8m2, _u8, _e8m2, vbool4_t)
03f33657
JZZ		 124/* LMUL = 4:
125 Machine mode = VNx32QImode when TARGET_MIN_VLEN > 32.
126 Machine mode = VNx16QImode when TARGET_MIN_VLEN = 32. */
cbd50570 127DEF_RVV_TYPE (vint8m4_t, 14, __rvv_int8m4_t, intQI, VNx32QI, VNx16QI, _i8m4,
a143c3f7 128 _i8, _e8m4, vbool2_t)
cbd50570 129DEF_RVV_TYPE (vuint8m4_t, 15, __rvv_uint8m4_t, unsigned_intQI, VNx32QI, VNx16QI,
a143c3f7 130 _u8m4, _u8, _e8m4, vbool2_t)
03f33657
JZZ		 131/* LMUL = 8:
132 Machine mode = VNx64QImode when TARGET_MIN_VLEN > 32.
133 Machine mode = VNx32QImode when TARGET_MIN_VLEN = 32. */
cbd50570 134DEF_RVV_TYPE (vint8m8_t, 14, __rvv_int8m8_t, intQI, VNx64QI, VNx32QI, _i8m8,
a143c3f7 135 _i8, _e8m8, vbool1_t)
cbd50570 136DEF_RVV_TYPE (vuint8m8_t, 15, __rvv_uint8m8_t, unsigned_intQI, VNx64QI, VNx32QI,
a143c3f7 137 _u8m8, _u8, _e8m8, vbool1_t)
03f33657
JZZ		 138
139/* LMUL = 1/4:
140 Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1HImode. */
cbd50570 141DEF_RVV_TYPE (vint16mf4_t, 16, __rvv_int16mf4_t, intHI, VNx1HI, VOID, _i16mf4,
a143c3f7 142 _i16, _e16mf4, vbool64_t)
cbd50570 143DEF_RVV_TYPE (vuint16mf4_t, 17, __rvv_uint16mf4_t, unsigned_intHI, VNx1HI, VOID,
a143c3f7 144 _u16mf4, _u16, _e16mf4, vbool64_t)
03f33657
JZZ		 145/* LMUL = 1/2:
146 Machine mode = VNx2HImode when TARGET_MIN_VLEN > 32.
147 Machine mode = VNx1HImode when TARGET_MIN_VLEN = 32. */
cbd50570 148DEF_RVV_TYPE (vint16mf2_t, 16, __rvv_int16mf2_t, intHI, VNx2HI, VNx1HI, _i16mf2,
a143c3f7 149 _i16, _e16mf2, vbool32_t)
03f33657 150DEF_RVV_TYPE (vuint16mf2_t, 17, __rvv_uint16mf2_t, unsigned_intHI, VNx2HI,
a143c3f7 151 VNx1HI, _u16mf2, _u16, _e16mf2, vbool32_t)
03f33657
JZZ		 152/* LMUL = 1:
153 Machine mode = VNx4HImode when TARGET_MIN_VLEN > 32.
154 Machine mode = VNx2HImode when TARGET_MIN_VLEN = 32. */
cbd50570 155DEF_RVV_TYPE (vint16m1_t, 15, __rvv_int16m1_t, intHI, VNx4HI, VNx2HI, _i16m1,
a143c3f7 156 _i16, _e16m1, vbool16_t)
cbd50570 157DEF_RVV_TYPE (vuint16m1_t, 16, __rvv_uint16m1_t, unsigned_intHI, VNx4HI, VNx2HI,
a143c3f7 158 _u16m1, _u16, _e16m1, vbool16_t)
03f33657
JZZ		 159/* LMUL = 2:
160 Machine mode = VNx8HImode when TARGET_MIN_VLEN > 32.
161 Machine mode = VNx4HImode when TARGET_MIN_VLEN = 32. */
cbd50570 162DEF_RVV_TYPE (vint16m2_t, 15, __rvv_int16m2_t, intHI, VNx8HI, VNx4HI, _i16m2,
a143c3f7 163 _i16, _e16m2, vbool8_t)
cbd50570 164DEF_RVV_TYPE (vuint16m2_t, 16, __rvv_uint16m2_t, unsigned_intHI, VNx8HI, VNx4HI,
a143c3f7 165 _u16m2, _u16, _e16m2, vbool8_t)
03f33657
JZZ		 166/* LMUL = 4:
167 Machine mode = VNx16HImode when TARGET_MIN_VLEN > 32.
168 Machine mode = VNx8HImode when TARGET_MIN_VLEN = 32. */
cbd50570 169DEF_RVV_TYPE (vint16m4_t, 15, __rvv_int16m4_t, intHI, VNx16HI, VNx8HI, _i16m4,
a143c3f7 170 _i16, _e16m4, vbool4_t)
03f33657 171DEF_RVV_TYPE (vuint16m4_t, 16, __rvv_uint16m4_t, unsigned_intHI, VNx16HI,
a143c3f7 172 VNx8HI, _u16m4, _u16, _e16m4, vbool4_t)
03f33657
JZZ		 173/* LMUL = 8:
174 Machine mode = VNx32HImode when TARGET_MIN_VLEN > 32.
175 Machine mode = VNx16HImode when TARGET_MIN_VLEN = 32. */
cbd50570 176DEF_RVV_TYPE (vint16m8_t, 15, __rvv_int16m8_t, intHI, VNx32HI, VNx16HI, _i16m8,
a143c3f7 177 _i16, _e16m8, vbool2_t)
03f33657 178DEF_RVV_TYPE (vuint16m8_t, 16, __rvv_uint16m8_t, unsigned_intHI, VNx32HI,
a143c3f7 179 VNx16HI, _u16m8, _u16, _e16m8, vbool2_t)
03f33657
JZZ		 180
181/* LMUL = 1/2:
182 Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1SImode. */
cbd50570 183DEF_RVV_TYPE (vint32mf2_t, 16, __rvv_int32mf2_t, int32, VNx1SI, VOID, _i32mf2,
a143c3f7 184 _i32, _e32mf2, vbool64_t)
cbd50570 185DEF_RVV_TYPE (vuint32mf2_t, 17, __rvv_uint32mf2_t, unsigned_int32, VNx1SI, VOID,
a143c3f7 186 _u32mf2, _u32, _e32mf2, vbool64_t)
03f33657
JZZ		 187/* LMUL = 1:
188 Machine mode = VNx2SImode when TARGET_MIN_VLEN > 32.
189 Machine mode = VNx1SImode when TARGET_MIN_VLEN = 32. */
cbd50570 190DEF_RVV_TYPE (vint32m1_t, 15, __rvv_int32m1_t, int32, VNx2SI, VNx1SI, _i32m1,
a143c3f7 191 _i32, _e32m1, vbool32_t)
cbd50570 192DEF_RVV_TYPE (vuint32m1_t, 16, __rvv_uint32m1_t, unsigned_int32, VNx2SI, VNx1SI,
a143c3f7 193 _u32m1, _u32, _e32m1, vbool32_t)
03f33657
JZZ		 194/* LMUL = 2:
195 Machine mode = VNx4SImode when TARGET_MIN_VLEN > 32.
196 Machine mode = VNx2SImode when TARGET_MIN_VLEN = 32. */
cbd50570 197DEF_RVV_TYPE (vint32m2_t, 15, __rvv_int32m2_t, int32, VNx4SI, VNx2SI, _i32m2,
a143c3f7 198 _i32, _e32m2, vbool16_t)
cbd50570 199DEF_RVV_TYPE (vuint32m2_t, 16, __rvv_uint32m2_t, unsigned_int32, VNx4SI, VNx2SI,
a143c3f7 200 _u32m2, _u32, _e32m2, vbool16_t)
03f33657
JZZ		 201/* LMUL = 4:
202 Machine mode = VNx8SImode when TARGET_MIN_VLEN > 32.
203 Machine mode = VNx4SImode when TARGET_MIN_VLEN = 32. */
cbd50570 204DEF_RVV_TYPE (vint32m4_t, 15, __rvv_int32m4_t, int32, VNx8SI, VNx4SI, _i32m4,
a143c3f7 205 _i32, _e32m4, vbool8_t)
cbd50570 206DEF_RVV_TYPE (vuint32m4_t, 16, __rvv_uint32m4_t, unsigned_int32, VNx8SI, VNx4SI,
a143c3f7 207 _u32m4, _u32, _e32m4, vbool8_t)
03f33657
JZZ		 208/* LMUL = 8:
209 Machine mode = VNx16SImode when TARGET_MIN_VLEN > 32.
210 Machine mode = VNx8SImode when TARGET_MIN_VLEN = 32. */
cbd50570 211DEF_RVV_TYPE (vint32m8_t, 15, __rvv_int32m8_t, int32, VNx16SI, VNx8SI, _i32m8,
a143c3f7 212 _i32, _e32m8, vbool4_t)
03f33657 213DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, unsigned_int32, VNx16SI,
a143c3f7 214 VNx8SI, _u32m8, _u32, _e32m8, vbool4_t)
03f33657
JZZ		 215
216/* SEW = 64:
217 Disable when TARGET_MIN_VLEN > 32. */
cbd50570 218DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, intDI, VNx1DI, VOID, _i64m1,
a143c3f7 219 _i64, _e64m1, vbool64_t)
cbd50570 220DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, unsigned_intDI, VNx1DI, VOID,
a143c3f7 221 _u64m1, _u64, _e64m1, vbool64_t)
cbd50570 222DEF_RVV_TYPE (vint64m2_t, 15, __rvv_int64m2_t, intDI, VNx2DI, VOID, _i64m2,
a143c3f7 223 _i64, _e64m2, vbool32_t)
cbd50570 224DEF_RVV_TYPE (vuint64m2_t, 16, __rvv_uint64m2_t, unsigned_intDI, VNx2DI, VOID,
a143c3f7 225 _u64m2, _u64, _e64m2, vbool32_t)
cbd50570 226DEF_RVV_TYPE (vint64m4_t, 15, __rvv_int64m4_t, intDI, VNx4DI, VOID, _i64m4,
a143c3f7 227 _i64, _e64m4, vbool16_t)
cbd50570 228DEF_RVV_TYPE (vuint64m4_t, 16, __rvv_uint64m4_t, unsigned_intDI, VNx4DI, VOID,
a143c3f7 229 _u64m4, _u64, _e64m4, vbool16_t)
cbd50570 230DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, intDI, VNx8DI, VOID, _i64m8,
a143c3f7 231 _i64, _e64m8, vbool8_t)
cbd50570 232DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, unsigned_intDI, VNx8DI, VOID,
a143c3f7 233 _u64m8, _u64, _e64m8, vbool8_t)
03f33657
JZZ		 234
235/* LMUL = 1/2:
236 Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1SFmode. */
cbd50570 237DEF_RVV_TYPE (vfloat32mf2_t, 18, __rvv_float32mf2_t, float, VNx1SF, VOID,
a143c3f7 238 _f32mf2, _f32, _e32mf2, vbool64_t)
03f33657
JZZ		 239/* LMUL = 1:
240 Machine mode = VNx2SFmode when TARGET_MIN_VLEN > 32.
241 Machine mode = VNx1SFmode when TARGET_MIN_VLEN = 32. */
cbd50570 242DEF_RVV_TYPE (vfloat32m1_t, 17, __rvv_float32m1_t, float, VNx2SF, VNx1SF,
a143c3f7 243 _f32m1, _f32, _e32m1, vbool32_t)
03f33657
JZZ		 244/* LMUL = 2:
245 Machine mode = VNx4SFmode when TARGET_MIN_VLEN > 32.
246 Machine mode = VNx2SFmode when TARGET_MIN_VLEN = 32. */
cbd50570 247DEF_RVV_TYPE (vfloat32m2_t, 17, __rvv_float32m2_t, float, VNx4SF, VNx2SF,
a143c3f7 248 _f32m2, _f32, _e32m2, vbool16_t)
03f33657
JZZ		 249/* LMUL = 4:
250 Machine mode = VNx8SFmode when TARGET_MIN_VLEN > 32.
251 Machine mode = VNx4SFmode when TARGET_MIN_VLEN = 32. */
cbd50570 252DEF_RVV_TYPE (vfloat32m4_t, 17, __rvv_float32m4_t, float, VNx8SF, VNx4SF,
a143c3f7 253 _f32m4, _f32, _e32m4, vbool8_t)
03f33657
JZZ		 254/* LMUL = 8:
255 Machine mode = VNx16SFmode when TARGET_MIN_VLEN > 32.
256 Machine mode = VNx8SFmode when TARGET_MIN_VLEN = 32. */
cbd50570 257DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF,
a143c3f7 258 _f32m8, _f32, _e32m8, vbool4_t)
03f33657
JZZ		 259
260/* SEW = 64:
261 Disable when TARGET_VECTOR_FP64. */
cbd50570 262DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID, _f64m1,
a143c3f7 263 _f64, _e64m1, vbool64_t)
cbd50570 264DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID, _f64m2,
a143c3f7 265 _f64, _e64m2, vbool32_t)
cbd50570 266DEF_RVV_TYPE (vfloat64m4_t, 17, __rvv_float64m4_t, double, VNx4DF, VOID, _f64m4,
a143c3f7 267 _f64, _e64m4, vbool16_t)
cbd50570 268DEF_RVV_TYPE (vfloat64m8_t, 17, __rvv_float64m8_t, double, VNx8DF, VOID, _f64m8,
a143c3f7 269 _f64, _e64m8, vbool8_t)
cbd50570
JZZ		 270
271DEF_RVV_OP_TYPE (vv)
272DEF_RVV_OP_TYPE (vx)
273DEF_RVV_OP_TYPE (v)
274DEF_RVV_OP_TYPE (wv)
275DEF_RVV_OP_TYPE (wx)
276DEF_RVV_OP_TYPE (x_x_v)
277DEF_RVV_OP_TYPE (vf2)
278DEF_RVV_OP_TYPE (vf4)
279DEF_RVV_OP_TYPE (vf8)
280DEF_RVV_OP_TYPE (vvm)
281DEF_RVV_OP_TYPE (vxm)
282DEF_RVV_OP_TYPE (x_x_w)
283DEF_RVV_OP_TYPE (v_v)
284DEF_RVV_OP_TYPE (v_x)
285DEF_RVV_OP_TYPE (vs)
286DEF_RVV_OP_TYPE (mm)
287DEF_RVV_OP_TYPE (m)
288DEF_RVV_OP_TYPE (vf)
289DEF_RVV_OP_TYPE (vm)
290DEF_RVV_OP_TYPE (wf)
291DEF_RVV_OP_TYPE (vfm)
292DEF_RVV_OP_TYPE (v_f)
293
294DEF_RVV_PRED_TYPE (ta)
295DEF_RVV_PRED_TYPE (tu)
296DEF_RVV_PRED_TYPE (ma)
297DEF_RVV_PRED_TYPE (mu)
298DEF_RVV_PRED_TYPE (tama)
299DEF_RVV_PRED_TYPE (tamu)
300DEF_RVV_PRED_TYPE (tuma)
301DEF_RVV_PRED_TYPE (tumu)
302DEF_RVV_PRED_TYPE (m)
303DEF_RVV_PRED_TYPE (tam)
304DEF_RVV_PRED_TYPE (tum)
03f33657 305
cbd50570
JZZ		 306#undef DEF_RVV_PRED_TYPE
307#undef DEF_RVV_OP_TYPE
03f33657 308#undef DEF_RVV_TYPE
Mirror of https://gcc.gnu.org/git/gcc.git