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09cae750 | 1 | /* Definition of RISC-V target for GNU compiler. |
7adcbafe | 2 | Copyright (C) 2011-2022 Free Software Foundation, Inc. |
09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
4 | Based on MIPS target for GNU compiler. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef GCC_RISCV_H | |
23 | #define GCC_RISCV_H | |
24 | ||
25 | #include "config/riscv/riscv-opts.h" | |
26 | ||
27 | /* Target CPU builtins. */ | |
28 | #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile) | |
29 | ||
3785d2b2 | 30 | /* Target hooks for D language. */ |
b4c522fa | 31 | #define TARGET_D_CPU_VERSIONS riscv_d_target_versions |
3785d2b2 | 32 | #define TARGET_D_REGISTER_CPU_TARGET_INFO riscv_d_register_target_info |
b4c522fa | 33 | |
cd1e2f63 MC |
34 | #ifdef TARGET_BIG_ENDIAN_DEFAULT |
35 | #define DEFAULT_ENDIAN_SPEC "b" | |
36 | #else | |
37 | #define DEFAULT_ENDIAN_SPEC "l" | |
38 | #endif | |
39 | ||
09cae750 PD |
40 | /* Default target_flags if no switches are specified */ |
41 | ||
42 | #ifndef TARGET_DEFAULT | |
43 | #define TARGET_DEFAULT 0 | |
44 | #endif | |
45 | ||
46 | #ifndef RISCV_TUNE_STRING_DEFAULT | |
47 | #define RISCV_TUNE_STRING_DEFAULT "rocket" | |
48 | #endif | |
49 | ||
f908b69c | 50 | extern const char *riscv_expand_arch (int argc, const char **argv); |
72eb8335 KC |
51 | extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv); |
52 | extern const char *riscv_default_mtune (int argc, const char **argv); | |
f908b69c KC |
53 | |
54 | # define EXTRA_SPEC_FUNCTIONS \ | |
72eb8335 KC |
55 | { "riscv_expand_arch", riscv_expand_arch }, \ |
56 | { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \ | |
57 | { "riscv_default_mtune", riscv_default_mtune }, | |
f908b69c | 58 | |
09cae750 | 59 | /* Support for a compile-time default CPU, et cetera. The rules are: |
72eb8335 | 60 | --with-arch is ignored if -march or -mcpu is specified. |
09cae750 | 61 | --with-abi is ignored if -mabi is specified. |
72eb8335 KC |
62 | --with-tune is ignored if -mtune or -mcpu is specified. |
63 | ||
64 | But using default -march/-mtune value if -mcpu don't have valid option. */ | |
09cae750 | 65 | #define OPTION_DEFAULT_SPECS \ |
72eb8335 KC |
66 | {"tune", "%{!mtune=*:" \ |
67 | " %{!mcpu=*:-mtune=%(VALUE)}" \ | |
68 | " %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" }, \ | |
69 | {"arch", "%{!march=*:" \ | |
70 | " %{!mcpu=*:-march=%(VALUE)}" \ | |
71 | " %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \ | |
09cae750 PD |
72 | {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ |
73 | ||
74 | #ifdef IN_LIBGCC2 | |
75 | #undef TARGET_64BIT | |
76 | /* Make this compile time constant for libgcc2 */ | |
77 | #define TARGET_64BIT (__riscv_xlen == 64) | |
78 | #endif /* IN_LIBGCC2 */ | |
79 | ||
4b815282 KC |
80 | #ifdef HAVE_AS_MISA_SPEC |
81 | #define ASM_MISA_SPEC "%{misa-spec=*}" | |
82 | #else | |
83 | #define ASM_MISA_SPEC "" | |
84 | #endif | |
85 | ||
a5ad5d5c KC |
86 | /* Reference: |
87 | https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing */ | |
88 | #define STRINGIZING(s) __STRINGIZING(s) | |
89 | #define __STRINGIZING(s) #s | |
90 | ||
91 | #define MULTILIB_DEFAULTS \ | |
92 | {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \ | |
93 | "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) } | |
94 | ||
09cae750 PD |
95 | #undef ASM_SPEC |
96 | #define ASM_SPEC "\ | |
97 | %(subtarget_asm_debugging_spec) \ | |
98 | %{" FPIE_OR_FPIC_SPEC ":-fpic} \ | |
f4670347 | 99 | %{march=*} \ |
09cae750 | 100 | %{mabi=*} \ |
3b0a7d62 | 101 | %{mno-relax} \ |
a9604fcb MC |
102 | %{mbig-endian} \ |
103 | %{mlittle-endian} \ | |
4b815282 KC |
104 | %(subtarget_asm_spec)" \ |
105 | ASM_MISA_SPEC | |
09cae750 | 106 | |
f4670347 | 107 | #undef DRIVER_SELF_SPECS |
72eb8335 KC |
108 | #define DRIVER_SELF_SPECS \ |
109 | "%{march=*:%:riscv_expand_arch(%*)} " \ | |
110 | "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} " | |
f4670347 | 111 | |
09cae750 PD |
112 | #define TARGET_DEFAULT_CMODEL CM_MEDLOW |
113 | ||
114 | #define LOCAL_LABEL_PREFIX "." | |
115 | #define USER_LABEL_PREFIX "" | |
116 | ||
117 | /* Offsets recorded in opcodes are a multiple of this alignment factor. | |
118 | The default for this in 64-bit mode is 8, which causes problems with | |
119 | SFmode register saves. */ | |
120 | #define DWARF_CIE_DATA_ALIGNMENT -4 | |
121 | ||
122 | /* The mapping from gcc register number to DWARF 2 CFA column number. */ | |
123 | #define DWARF_FRAME_REGNUM(REGNO) \ | |
124 | (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM) | |
125 | ||
126 | /* The DWARF 2 CFA column which tracks the return address. */ | |
127 | #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM | |
128 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM) | |
129 | ||
130 | /* Describe how we implement __builtin_eh_return. */ | |
131 | #define EH_RETURN_DATA_REGNO(N) \ | |
132 | ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM) | |
133 | ||
134 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4) | |
135 | ||
136 | /* Target machine storage layout */ | |
137 | ||
138 | #define BITS_BIG_ENDIAN 0 | |
a9604fcb MC |
139 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
140 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) | |
09cae750 PD |
141 | |
142 | #define MAX_BITS_PER_WORD 64 | |
143 | ||
144 | /* Width of a word, in units (bytes). */ | |
145 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
146 | #ifndef IN_LIBGCC2 | |
147 | #define MIN_UNITS_PER_WORD 4 | |
148 | #endif | |
149 | ||
e53b6e56 | 150 | /* Allows SImode op in builtin overflow pattern, see internal-fn.cc. */ |
6efd040c L |
151 | #undef TARGET_MIN_ARITHMETIC_PRECISION |
152 | #define TARGET_MIN_ARITHMETIC_PRECISION riscv_min_arithmetic_precision | |
153 | ||
09cae750 PD |
154 | /* The `Q' extension is not yet supported. */ |
155 | #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) | |
156 | ||
157 | /* The largest type that can be passed in floating-point registers. */ | |
09baee1a KC |
158 | #define UNITS_PER_FP_ARG \ |
159 | ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \ | |
160 | || riscv_abi == ABI_LP64) \ | |
161 | ? 0 \ | |
162 | : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8)) | |
09cae750 PD |
163 | |
164 | /* Set the sizes of the core types. */ | |
165 | #define SHORT_TYPE_SIZE 16 | |
166 | #define INT_TYPE_SIZE 32 | |
167 | #define LONG_LONG_TYPE_SIZE 64 | |
168 | #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32) | |
169 | #define LONG_TYPE_SIZE POINTER_SIZE | |
170 | ||
171 | #define FLOAT_TYPE_SIZE 32 | |
172 | #define DOUBLE_TYPE_SIZE 64 | |
173 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
174 | ||
175 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
176 | #define PARM_BOUNDARY BITS_PER_WORD | |
177 | ||
178 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
179 | #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32) | |
180 | ||
0ce42fe1 | 181 | /* The smallest supported stack boundary the calling convention supports. */ |
75902396 JW |
182 | #define STACK_BOUNDARY \ |
183 | (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD) | |
0ce42fe1 AW |
184 | |
185 | /* The ABI stack alignment. */ | |
75902396 | 186 | #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128) |
0ce42fe1 | 187 | |
09cae750 | 188 | /* There is no point aligning anything to a rounder boundary than this. */ |
c0d3d1b6 | 189 | #define BIGGEST_ALIGNMENT 128 |
09cae750 | 190 | |
82285692 AW |
191 | /* The user-level ISA permits unaligned accesses, but they are not required |
192 | of the privileged architecture. */ | |
193 | #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN | |
194 | ||
09cae750 PD |
195 | /* Define this if you wish to imitate the way many other C compilers |
196 | handle alignment of bitfields and the structures that contain | |
197 | them. | |
198 | ||
199 | The behavior is that the type written for a bit-field (`int', | |
200 | `short', or other integer type) imposes an alignment for the | |
201 | entire structure, as if the structure really did contain an | |
202 | ordinary field of that type. In addition, the bit-field is placed | |
203 | within the structure so that it would fit within such a field, | |
204 | not crossing a boundary for it. | |
205 | ||
206 | Thus, on most machines, a bit-field whose type is written as `int' | |
207 | would not cross a four-byte boundary, and would force four-byte | |
208 | alignment for the whole structure. (The alignment used may not | |
209 | be four bytes; it is controlled by the other alignment | |
210 | parameters.) | |
211 | ||
212 | If the macro is defined, its definition should be a C expression; | |
213 | a nonzero value for the expression enables this behavior. */ | |
214 | ||
215 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
216 | ||
d3f952c5 JW |
217 | /* An integer expression for the size in bits of the largest integer machine |
218 | mode that should actually be used. We allow pairs of registers. */ | |
219 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
220 | ||
ffbb9818 ID |
221 | /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition. */ |
222 | #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN) \ | |
223 | (((COND) && ((ALIGN) < BITS_PER_WORD) \ | |
224 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
225 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
226 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
227 | ||
09cae750 PD |
228 | /* If defined, a C expression to compute the alignment for a static |
229 | variable. TYPE is the data type, and ALIGN is the alignment that | |
230 | the object would ordinarily have. The value of this macro is used | |
231 | instead of that alignment to align the object. | |
232 | ||
233 | If this macro is not defined, then ALIGN is used. | |
234 | ||
235 | One use of this macro is to increase alignment of medium-size | |
236 | data to make it all fit in fewer cache lines. Another is to | |
237 | cause character arrays to be word-aligned so that `strcpy' calls | |
238 | that copy constants to character arrays can be done inline. */ | |
239 | ||
ffbb9818 ID |
240 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
241 | RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen, \ | |
242 | TYPE, ALIGN) | |
09cae750 PD |
243 | |
244 | /* We need this for the same reason as DATA_ALIGNMENT, namely to cause | |
245 | character arrays to be word-aligned so that `strcpy' calls that copy | |
246 | constants to character arrays can be done inline, and 'strcmp' can be | |
247 | optimised to use word loads. */ | |
248 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
ffbb9818 | 249 | RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN) |
09cae750 PD |
250 | |
251 | /* Define if operations between registers always perform the operation | |
252 | on the full register even if a narrower mode is specified. */ | |
253 | #define WORD_REGISTER_OPERATIONS 1 | |
254 | ||
255 | /* When in 64-bit mode, move insns will sign extend SImode and CCmode | |
256 | moves. All other references are zero extended. */ | |
257 | #define LOAD_EXTEND_OP(MODE) \ | |
258 | (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) | |
259 | ||
260 | /* Define this macro if it is advisable to hold scalars in registers | |
261 | in a wider mode than that declared by the program. In such cases, | |
262 | the value is constrained to be within the bounds of the declared | |
263 | type, but kept valid in the wider mode. The signedness of the | |
264 | extension may differ from that of the type. */ | |
265 | ||
266 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
267 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
268 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
269 | { \ | |
270 | if ((MODE) == SImode) \ | |
271 | (UNSIGNEDP) = 0; \ | |
272 | (MODE) = word_mode; \ | |
273 | } | |
274 | ||
275 | /* Pmode is always the same as ptr_mode, but not always the same as word_mode. | |
276 | Extensions of pointers to word_mode must be signed. */ | |
277 | #define POINTERS_EXTEND_UNSIGNED false | |
278 | ||
09cae750 PD |
279 | /* Define if loading short immediate values into registers sign extends. */ |
280 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 | |
281 | ||
282 | /* Standard register usage. */ | |
283 | ||
284 | /* Number of hardware registers. We have: | |
285 | ||
286 | - 32 integer registers | |
287 | - 32 floating point registers | |
288 | - 2 fake registers: | |
289 | - ARG_POINTER_REGNUM | |
290 | - FRAME_POINTER_REGNUM */ | |
291 | ||
292 | #define FIRST_PSEUDO_REGISTER 66 | |
293 | ||
294 | /* x0, sp, gp, and tp are fixed. */ | |
295 | ||
296 | #define FIXED_REGISTERS \ | |
297 | { /* General registers. */ \ | |
298 | 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
299 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
300 | /* Floating-point registers. */ \ | |
301 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
302 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
303 | /* Others. */ \ | |
304 | 1, 1 \ | |
305 | } | |
306 | ||
f3abed16 | 307 | /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls. |
09cae750 PD |
308 | The call RTLs themselves clobber ra. */ |
309 | ||
310 | #define CALL_USED_REGISTERS \ | |
311 | { /* General registers. */ \ | |
312 | 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ | |
313 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ | |
314 | /* Floating-point registers. */ \ | |
315 | 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ | |
316 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ | |
317 | /* Others. */ \ | |
318 | 1, 1 \ | |
319 | } | |
320 | ||
b780f68e JW |
321 | /* Select a register mode required for caller save of hard regno REGNO. |
322 | Contrary to what is documented, the default is not the smallest suitable | |
323 | mode but the largest suitable mode for the given (REGNO, NREGS) pair and | |
324 | it quickly creates paradoxical subregs that can be problematic. */ | |
325 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
326 | ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE)) | |
327 | ||
09cae750 PD |
328 | /* Internal macros to classify an ISA register's type. */ |
329 | ||
330 | #define GP_REG_FIRST 0 | |
09baee1a | 331 | #define GP_REG_LAST (TARGET_RVE ? 15 : 31) |
09cae750 PD |
332 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) |
333 | ||
334 | #define FP_REG_FIRST 32 | |
335 | #define FP_REG_LAST 63 | |
336 | #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
337 | ||
338 | /* The DWARF 2 CFA column which tracks the return address from a | |
339 | signal handler context. This means that to maintain backwards | |
340 | compatibility, no hard register can be assigned this column if it | |
341 | would need to be handled by the DWARF unwinder. */ | |
342 | #define DWARF_ALT_FRAME_RETURN_COLUMN 64 | |
343 | ||
344 | #define GP_REG_P(REGNO) \ | |
345 | ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
346 | #define FP_REG_P(REGNO) \ | |
347 | ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
348 | ||
e18a6d14 AB |
349 | /* True when REGNO is in SIBCALL_REGS set. */ |
350 | #define SIBCALL_REG_P(REGNO) \ | |
351 | TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO) | |
352 | ||
09cae750 PD |
353 | #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) |
354 | ||
09cae750 PD |
355 | /* Use s0 as the frame pointer if it is so requested. */ |
356 | #define HARD_FRAME_POINTER_REGNUM 8 | |
357 | #define STACK_POINTER_REGNUM 2 | |
358 | #define THREAD_POINTER_REGNUM 4 | |
359 | ||
360 | /* These two registers don't really exist: they get eliminated to either | |
361 | the stack or hard frame pointer. */ | |
362 | #define ARG_POINTER_REGNUM 64 | |
363 | #define FRAME_POINTER_REGNUM 65 | |
364 | ||
365 | /* Register in which static-chain is passed to a function. */ | |
366 | #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2) | |
367 | ||
368 | /* Registers used as temporaries in prologue/epilogue code. | |
369 | ||
370 | The prologue registers mustn't conflict with any | |
371 | incoming arguments, the static chain pointer, or the frame pointer. | |
372 | The epilogue temporary mustn't conflict with the return registers, | |
373 | the frame pointer, the EH stack adjustment, or the EH data registers. */ | |
374 | ||
207de839 | 375 | #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST) |
09cae750 PD |
376 | #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM) |
377 | ||
207de839 MC |
378 | #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1) |
379 | #define RISCV_CALL_ADDRESS_TEMP(MODE) \ | |
380 | gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM) | |
381 | ||
09cae750 PD |
382 | #define MCOUNT_NAME "_mcount" |
383 | ||
384 | #define NO_PROFILE_COUNTERS 1 | |
385 | ||
386 | /* Emit rtl for profiling. Output assembler code to FILE | |
387 | to call "_mcount" for profiling a function entry. */ | |
388 | #define PROFILE_HOOK(LABEL) \ | |
389 | { \ | |
390 | rtx fun, ra; \ | |
391 | ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \ | |
392 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ | |
db69559b | 393 | emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \ |
09cae750 PD |
394 | } |
395 | ||
396 | /* All the work done in PROFILE_HOOK, but still required. */ | |
397 | #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) | |
398 | ||
399 | /* Define this macro if it is as good or better to call a constant | |
400 | function address than to call an address kept in a register. */ | |
401 | #define NO_FUNCTION_CSE 1 | |
402 | ||
403 | /* Define the classes of registers for register constraints in the | |
404 | machine description. Also define ranges of constants. | |
405 | ||
406 | One of the classes must always be named ALL_REGS and include all hard regs. | |
407 | If there is more than one class, another class must be named NO_REGS | |
408 | and contain no registers. | |
409 | ||
410 | The name GENERAL_REGS must be the name of a class (or an alias for | |
411 | another name such as ALL_REGS). This is the class of registers | |
412 | that is allowed by "g" or "r" in a register constraint. | |
413 | Also, registers outside this class are allocated only when | |
414 | instructions express preferences for them. | |
415 | ||
416 | The classes must be numbered in nondecreasing order; that is, | |
417 | a larger-numbered class must never be contained completely | |
418 | in a smaller-numbered class. | |
419 | ||
420 | For any two classes, it is very desirable that there be another | |
421 | class that represents their union. */ | |
422 | ||
423 | enum reg_class | |
424 | { | |
425 | NO_REGS, /* no registers in set */ | |
426 | SIBCALL_REGS, /* registers used by indirect sibcalls */ | |
427 | JALR_REGS, /* registers used by indirect calls */ | |
428 | GR_REGS, /* integer registers */ | |
429 | FP_REGS, /* floating-point registers */ | |
430 | FRAME_REGS, /* arg pointer and frame pointer */ | |
431 | ALL_REGS, /* all registers */ | |
432 | LIM_REG_CLASSES /* max value + 1 */ | |
433 | }; | |
434 | ||
435 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
436 | ||
437 | #define GENERAL_REGS GR_REGS | |
438 | ||
439 | /* An initializer containing the names of the register classes as C | |
440 | string constants. These names are used in writing some of the | |
441 | debugging dumps. */ | |
442 | ||
443 | #define REG_CLASS_NAMES \ | |
444 | { \ | |
445 | "NO_REGS", \ | |
446 | "SIBCALL_REGS", \ | |
447 | "JALR_REGS", \ | |
448 | "GR_REGS", \ | |
449 | "FP_REGS", \ | |
450 | "FRAME_REGS", \ | |
451 | "ALL_REGS" \ | |
452 | } | |
453 | ||
454 | /* An initializer containing the contents of the register classes, | |
455 | as integers which are bit masks. The Nth integer specifies the | |
456 | contents of class N. The way the integer MASK is interpreted is | |
457 | that register R is in the class if `MASK & (1 << R)' is 1. | |
458 | ||
459 | When the machine has more than 32 registers, an integer does not | |
460 | suffice. Then the integers are replaced by sub-initializers, | |
461 | braced groupings containing several integers. Each | |
462 | sub-initializer must be suitable as an initializer for the type | |
463 | `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ | |
464 | ||
465 | #define REG_CLASS_CONTENTS \ | |
466 | { \ | |
467 | { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
3599dfba | 468 | { 0xf003fcc0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ |
09cae750 PD |
469 | { 0xffffffc0, 0x00000000, 0x00000000 }, /* JALR_REGS */ \ |
470 | { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \ | |
471 | { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ | |
472 | { 0x00000000, 0x00000000, 0x00000003 }, /* FRAME_REGS */ \ | |
473 | { 0xffffffff, 0xffffffff, 0x00000003 } /* ALL_REGS */ \ | |
474 | } | |
475 | ||
476 | /* A C expression whose value is a register class containing hard | |
477 | register REGNO. In general there is more that one such class; | |
478 | choose a class which is "minimal", meaning that no smaller class | |
479 | also contains the register. */ | |
480 | ||
481 | #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ] | |
482 | ||
483 | /* A macro whose definition is the name of the class to which a | |
484 | valid base register must belong. A base register is one used in | |
485 | an address which is the register value plus a displacement. */ | |
486 | ||
487 | #define BASE_REG_CLASS GR_REGS | |
488 | ||
489 | /* A macro whose definition is the name of the class to which a | |
490 | valid index register must belong. An index register is one used | |
491 | in an address where its value is either multiplied by a scale | |
492 | factor or added to another register (as well as added to a | |
493 | displacement). */ | |
494 | ||
495 | #define INDEX_REG_CLASS NO_REGS | |
496 | ||
497 | /* We generally want to put call-clobbered registers ahead of | |
498 | call-saved ones. (IRA expects this.) */ | |
499 | ||
500 | #define REG_ALLOC_ORDER \ | |
501 | { \ | |
502 | /* Call-clobbered GPRs. */ \ | |
503 | 15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1, \ | |
504 | /* Call-saved GPRs. */ \ | |
505 | 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ | |
506 | /* GPRs that can never be exposed to the register allocator. */ \ | |
507 | 0, 2, 3, 4, \ | |
508 | /* Call-clobbered FPRs. */ \ | |
509 | 47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49, \ | |
510 | 60, 61, 62, 63, \ | |
511 | /* Call-saved FPRs. */ \ | |
512 | 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ | |
513 | /* None of the remaining classes have defined call-saved \ | |
514 | registers. */ \ | |
515 | 64, 65 \ | |
516 | } | |
517 | ||
518 | /* True if VALUE is a signed 12-bit number. */ | |
519 | ||
520 | #define SMALL_OPERAND(VALUE) \ | |
521 | ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH) | |
522 | ||
523 | /* True if VALUE can be loaded into a register using LUI. */ | |
524 | ||
525 | #define LUI_OPERAND(VALUE) \ | |
526 | (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \ | |
527 | || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0) | |
528 | ||
4e1e0d79 JW |
529 | /* If this is a single bit mask, then we can load it with bseti. But this |
530 | is not useful for any of the low 31 bits because we can use addi or lui | |
531 | to load them. It is wrong for loading SImode 0x80000000 on rv64 because it | |
532 | needs to be sign-extended. So we restrict this to the upper 32-bits | |
533 | only. */ | |
534 | #define SINGLE_BIT_MASK_OPERAND(VALUE) \ | |
535 | (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32)) | |
536 | ||
09cae750 PD |
537 | /* Stack layout; function entry, exit and calling. */ |
538 | ||
539 | #define STACK_GROWS_DOWNWARD 1 | |
540 | ||
541 | #define FRAME_GROWS_DOWNWARD 1 | |
542 | ||
09cae750 PD |
543 | #define RETURN_ADDR_RTX riscv_return_addr |
544 | ||
545 | #define ELIMINABLE_REGS \ | |
546 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
547 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
548 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
549 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
550 | ||
551 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
552 | (OFFSET) = riscv_initial_elimination_offset (FROM, TO) | |
553 | ||
554 | /* Allocate stack space for arguments at the beginning of each function. */ | |
555 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
556 | ||
557 | /* The argument pointer always points to the first argument. */ | |
558 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
559 | ||
560 | #define REG_PARM_STACK_SPACE(FNDECL) 0 | |
561 | ||
562 | /* Define this if it is the responsibility of the caller to | |
563 | allocate the area reserved for arguments passed in registers. | |
564 | If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect | |
565 | of this macro is to determine whether the space is included in | |
566 | `crtl->outgoing_args_size'. */ | |
567 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 | |
568 | ||
c0d3d1b6 | 569 | #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary |
0ce42fe1 | 570 | |
09cae750 PD |
571 | /* Symbolic macros for the registers used to return integer and floating |
572 | point values. */ | |
573 | ||
574 | #define GP_RETURN GP_ARG_FIRST | |
575 | #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST) | |
576 | ||
75902396 | 577 | #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8) |
09cae750 PD |
578 | |
579 | /* Symbolic macros for the first/last argument registers. */ | |
580 | ||
581 | #define GP_ARG_FIRST (GP_REG_FIRST + 10) | |
582 | #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) | |
583 | #define GP_TEMP_FIRST (GP_REG_FIRST + 5) | |
584 | #define FP_ARG_FIRST (FP_REG_FIRST + 10) | |
585 | #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) | |
586 | ||
587 | #define CALLEE_SAVED_REG_NUMBER(REGNO) \ | |
588 | ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \ | |
589 | (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1) | |
590 | ||
591 | #define LIBCALL_VALUE(MODE) \ | |
592 | riscv_function_value (NULL_TREE, NULL_TREE, MODE) | |
593 | ||
594 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
595 | riscv_function_value (VALTYPE, FUNC, VOIDmode) | |
596 | ||
597 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) | |
598 | ||
599 | /* 1 if N is a possible register number for function argument passing. | |
1fb157cc | 600 | We have no FP argument registers when soft-float. */ |
09cae750 PD |
601 | |
602 | /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */ | |
603 | #define FUNCTION_ARG_REGNO_P(N) \ | |
604 | (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \ | |
605 | || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST))) | |
606 | ||
607 | typedef struct { | |
608 | /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */ | |
609 | unsigned int num_gprs; | |
610 | ||
611 | /* Number of floating-point registers used so far, likewise. */ | |
612 | unsigned int num_fprs; | |
613 | } CUMULATIVE_ARGS; | |
614 | ||
615 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
616 | for a call to a function whose data type is FNTYPE. | |
617 | For a library call, FNTYPE is 0. */ | |
618 | ||
619 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ | |
620 | memset (&(CUM), 0, sizeof (CUM)) | |
621 | ||
d0ebdd9f | 622 | #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO) |
09cae750 | 623 | |
0ce42fe1 AW |
624 | /* Align based on stack boundary, which might have been set by the user. */ |
625 | #define RISCV_STACK_ALIGN(LOC) \ | |
c0d3d1b6 | 626 | (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8)) |
09cae750 PD |
627 | |
628 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
629 | the stack pointer does not matter. The value is tested only in | |
630 | functions that have frame pointers. | |
631 | No definition is equivalent to always zero. */ | |
632 | ||
633 | #define EXIT_IGNORE_STACK 1 | |
634 | ||
635 | ||
636 | /* Trampolines are a block of code followed by two pointers. */ | |
637 | ||
638 | #define TRAMPOLINE_CODE_SIZE 16 | |
639 | #define TRAMPOLINE_SIZE \ | |
640 | ((Pmode == SImode) \ | |
641 | ? TRAMPOLINE_CODE_SIZE \ | |
642 | : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2)) | |
643 | #define TRAMPOLINE_ALIGNMENT POINTER_SIZE | |
644 | ||
645 | /* Addressing modes, and classification of registers for them. */ | |
646 | ||
647 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
648 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
649 | riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1) | |
650 | ||
651 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
652 | and check its validity for a certain class. | |
653 | We have two alternate definitions for each of them. | |
654 | The usual definition accepts all pseudo regs; the other rejects them all. | |
655 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
656 | ||
657 | Most source files want to accept pseudo regs in the hope that | |
658 | they will get allocated to the class that the insn wants them to be in. | |
659 | Some source files that are used after register allocation | |
660 | need to be strict. */ | |
661 | ||
662 | #ifndef REG_OK_STRICT | |
663 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
664 | riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) | |
665 | #else | |
666 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
667 | riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) | |
668 | #endif | |
669 | ||
670 | #define REG_OK_FOR_INDEX_P(X) 0 | |
671 | ||
672 | /* Maximum number of registers that can appear in a valid memory address. */ | |
673 | ||
674 | #define MAX_REGS_PER_ADDRESS 1 | |
675 | ||
676 | #define CONSTANT_ADDRESS_P(X) \ | |
677 | (CONSTANT_P (X) && memory_address_p (SImode, X)) | |
678 | ||
679 | /* This handles the magic '..CURRENT_FUNCTION' symbol, which means | |
680 | 'the start of the function that this code is output in'. */ | |
681 | ||
2041a23a TV |
682 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ |
683 | do { \ | |
684 | if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ | |
685 | asm_fprintf ((FILE), "%U%s", \ | |
686 | XSTR (XEXP (DECL_RTL (current_function_decl), \ | |
687 | 0), 0)); \ | |
688 | else \ | |
689 | asm_fprintf ((FILE), "%U%s", (NAME)); \ | |
690 | } while (0) | |
09cae750 PD |
691 | |
692 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
693 | #define CASE_VECTOR_MODE SImode | |
694 | #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW) | |
695 | ||
696 | /* The load-address macro is used for PC-relative addressing of symbols | |
697 | that bind locally. Don't use it for symbols that should be addressed | |
698 | via the GOT. Also, avoid it for CM_MEDLOW, where LUI addressing | |
699 | currently results in more opportunities for linker relaxation. */ | |
700 | #define USE_LOAD_ADDRESS_MACRO(sym) \ | |
701 | (!TARGET_EXPLICIT_RELOCS && \ | |
702 | ((flag_pic \ | |
703 | && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym)) \ | |
704 | || ((GET_CODE (sym) == CONST) \ | |
705 | && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0)) \ | |
706 | && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))) \ | |
707 | || riscv_cmodel == CM_MEDANY)) | |
708 | ||
709 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
710 | #define DEFAULT_SIGNED_CHAR 0 | |
711 | ||
712 | #define MOVE_MAX UNITS_PER_WORD | |
713 | #define MAX_MOVE_MAX 8 | |
714 | ||
ecc82a8d AW |
715 | /* The SPARC port says: |
716 | Nonzero if access to memory by bytes is slow and undesirable. | |
717 | For RISC chips, it means that access to memory by bytes is no | |
718 | better than access by words when possible, so grab a whole word | |
719 | and maybe make use of that. */ | |
720 | #define SLOW_BYTE_ACCESS 1 | |
09cae750 | 721 | |
b7ef9225 JW |
722 | /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns |
723 | in the md file instead. */ | |
724 | #define SHIFT_COUNT_TRUNCATED 0 | |
09cae750 | 725 | |
09cae750 PD |
726 | /* Specify the machine mode that pointers have. |
727 | After generation of rtl, the compiler makes no further distinction | |
728 | between pointers and any other objects of this machine mode. */ | |
729 | ||
730 | #define Pmode word_mode | |
731 | ||
732 | /* Give call MEMs SImode since it is the "most permissive" mode | |
733 | for both 32-bit and 64-bit targets. */ | |
734 | ||
735 | #define FUNCTION_MODE SImode | |
736 | ||
737 | /* A C expression for the cost of a branch instruction. A value of 2 | |
738 | seems to minimize code size. */ | |
739 | ||
740 | #define BRANCH_COST(speed_p, predictable_p) \ | |
741 | ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost) | |
742 | ||
4f475391 AW |
743 | /* True if the target optimizes short forward branches around integer |
744 | arithmetic instructions into predicated operations, e.g., for | |
745 | conditional-move operations. The macro assumes that all branch | |
746 | instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ) | |
747 | support this feature. The macro further assumes that any integer | |
748 | arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I], | |
749 | SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed | |
750 | counterparts, including C.MV and C.LI) can be in the branch shadow. */ | |
751 | ||
752 | #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7) | |
753 | ||
09cae750 PD |
754 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
755 | ||
756 | /* Control the assembler format that we output. */ | |
757 | ||
758 | /* Output to assembler file text saying following lines | |
759 | may contain character constants, extra white space, comments, etc. */ | |
760 | ||
761 | #ifndef ASM_APP_ON | |
762 | #define ASM_APP_ON " #APP\n" | |
763 | #endif | |
764 | ||
765 | /* Output to assembler file text saying following lines | |
766 | no longer contain unusual constructs. */ | |
767 | ||
768 | #ifndef ASM_APP_OFF | |
769 | #define ASM_APP_OFF " #NO_APP\n" | |
770 | #endif | |
771 | ||
772 | #define REGISTER_NAMES \ | |
773 | { "zero","ra", "sp", "gp", "tp", "t0", "t1", "t2", \ | |
774 | "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \ | |
775 | "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \ | |
776 | "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \ | |
777 | "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \ | |
778 | "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \ | |
779 | "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \ | |
780 | "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \ | |
781 | "arg", "frame", } | |
782 | ||
783 | #define ADDITIONAL_REGISTER_NAMES \ | |
784 | { \ | |
785 | { "x0", 0 + GP_REG_FIRST }, \ | |
786 | { "x1", 1 + GP_REG_FIRST }, \ | |
787 | { "x2", 2 + GP_REG_FIRST }, \ | |
788 | { "x3", 3 + GP_REG_FIRST }, \ | |
789 | { "x4", 4 + GP_REG_FIRST }, \ | |
790 | { "x5", 5 + GP_REG_FIRST }, \ | |
791 | { "x6", 6 + GP_REG_FIRST }, \ | |
792 | { "x7", 7 + GP_REG_FIRST }, \ | |
793 | { "x8", 8 + GP_REG_FIRST }, \ | |
794 | { "x9", 9 + GP_REG_FIRST }, \ | |
795 | { "x10", 10 + GP_REG_FIRST }, \ | |
796 | { "x11", 11 + GP_REG_FIRST }, \ | |
797 | { "x12", 12 + GP_REG_FIRST }, \ | |
798 | { "x13", 13 + GP_REG_FIRST }, \ | |
799 | { "x14", 14 + GP_REG_FIRST }, \ | |
800 | { "x15", 15 + GP_REG_FIRST }, \ | |
801 | { "x16", 16 + GP_REG_FIRST }, \ | |
802 | { "x17", 17 + GP_REG_FIRST }, \ | |
803 | { "x18", 18 + GP_REG_FIRST }, \ | |
804 | { "x19", 19 + GP_REG_FIRST }, \ | |
805 | { "x20", 20 + GP_REG_FIRST }, \ | |
806 | { "x21", 21 + GP_REG_FIRST }, \ | |
807 | { "x22", 22 + GP_REG_FIRST }, \ | |
808 | { "x23", 23 + GP_REG_FIRST }, \ | |
809 | { "x24", 24 + GP_REG_FIRST }, \ | |
810 | { "x25", 25 + GP_REG_FIRST }, \ | |
811 | { "x26", 26 + GP_REG_FIRST }, \ | |
812 | { "x27", 27 + GP_REG_FIRST }, \ | |
813 | { "x28", 28 + GP_REG_FIRST }, \ | |
814 | { "x29", 29 + GP_REG_FIRST }, \ | |
815 | { "x30", 30 + GP_REG_FIRST }, \ | |
816 | { "x31", 31 + GP_REG_FIRST }, \ | |
817 | { "f0", 0 + FP_REG_FIRST }, \ | |
818 | { "f1", 1 + FP_REG_FIRST }, \ | |
819 | { "f2", 2 + FP_REG_FIRST }, \ | |
820 | { "f3", 3 + FP_REG_FIRST }, \ | |
821 | { "f4", 4 + FP_REG_FIRST }, \ | |
822 | { "f5", 5 + FP_REG_FIRST }, \ | |
823 | { "f6", 6 + FP_REG_FIRST }, \ | |
824 | { "f7", 7 + FP_REG_FIRST }, \ | |
825 | { "f8", 8 + FP_REG_FIRST }, \ | |
826 | { "f9", 9 + FP_REG_FIRST }, \ | |
827 | { "f10", 10 + FP_REG_FIRST }, \ | |
828 | { "f11", 11 + FP_REG_FIRST }, \ | |
829 | { "f12", 12 + FP_REG_FIRST }, \ | |
830 | { "f13", 13 + FP_REG_FIRST }, \ | |
831 | { "f14", 14 + FP_REG_FIRST }, \ | |
832 | { "f15", 15 + FP_REG_FIRST }, \ | |
833 | { "f16", 16 + FP_REG_FIRST }, \ | |
834 | { "f17", 17 + FP_REG_FIRST }, \ | |
835 | { "f18", 18 + FP_REG_FIRST }, \ | |
836 | { "f19", 19 + FP_REG_FIRST }, \ | |
837 | { "f20", 20 + FP_REG_FIRST }, \ | |
838 | { "f21", 21 + FP_REG_FIRST }, \ | |
839 | { "f22", 22 + FP_REG_FIRST }, \ | |
840 | { "f23", 23 + FP_REG_FIRST }, \ | |
841 | { "f24", 24 + FP_REG_FIRST }, \ | |
842 | { "f25", 25 + FP_REG_FIRST }, \ | |
843 | { "f26", 26 + FP_REG_FIRST }, \ | |
844 | { "f27", 27 + FP_REG_FIRST }, \ | |
845 | { "f28", 28 + FP_REG_FIRST }, \ | |
846 | { "f29", 29 + FP_REG_FIRST }, \ | |
847 | { "f30", 30 + FP_REG_FIRST }, \ | |
848 | { "f31", 31 + FP_REG_FIRST }, \ | |
849 | } | |
850 | ||
851 | /* Globalizing directive for a label. */ | |
852 | #define GLOBAL_ASM_OP "\t.globl\t" | |
853 | ||
854 | /* This is how to store into the string LABEL | |
855 | the symbol_ref name of an internal numbered label where | |
856 | PREFIX is the class of label and NUM is the number within the class. | |
857 | This is suitable for output with `assemble_name'. */ | |
858 | ||
859 | #undef ASM_GENERATE_INTERNAL_LABEL | |
860 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
861 | sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) | |
862 | ||
863 | /* This is how to output an element of a case-vector that is absolute. */ | |
864 | ||
865 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
866 | fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE) | |
867 | ||
868 | /* This is how to output an element of a PIC case-vector. */ | |
869 | ||
870 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
871 | fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ | |
872 | LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL) | |
873 | ||
874 | /* This is how to output an assembler line | |
875 | that says to advance the location counter | |
876 | to a multiple of 2**LOG bytes. */ | |
877 | ||
878 | #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ | |
879 | fprintf (STREAM, "\t.align\t%d\n", (LOG)) | |
880 | ||
881 | /* Define the strings to put out for each section in the object file. */ | |
882 | #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ | |
883 | #define DATA_SECTION_ASM_OP "\t.data" /* large data */ | |
884 | #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" | |
885 | #define BSS_SECTION_ASM_OP "\t.bss" | |
886 | #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits" | |
887 | #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits" | |
888 | ||
889 | #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ | |
890 | do \ | |
891 | { \ | |
892 | fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ | |
893 | reg_names[STACK_POINTER_REGNUM], \ | |
894 | reg_names[STACK_POINTER_REGNUM], \ | |
895 | TARGET_64BIT ? "sd" : "sw", \ | |
896 | reg_names[REGNO], \ | |
897 | reg_names[STACK_POINTER_REGNUM]); \ | |
898 | } \ | |
899 | while (0) | |
900 | ||
901 | #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ | |
902 | do \ | |
903 | { \ | |
904 | fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \ | |
905 | TARGET_64BIT ? "ld" : "lw", \ | |
906 | reg_names[REGNO], \ | |
907 | reg_names[STACK_POINTER_REGNUM], \ | |
908 | reg_names[STACK_POINTER_REGNUM], \ | |
909 | reg_names[STACK_POINTER_REGNUM]); \ | |
910 | } \ | |
911 | while (0) | |
912 | ||
913 | #define ASM_COMMENT_START "#" | |
914 | ||
915 | #undef SIZE_TYPE | |
916 | #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") | |
917 | ||
918 | #undef PTRDIFF_TYPE | |
919 | #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") | |
920 | ||
76715c32 | 921 | /* The maximum number of bytes copied by one iteration of a cpymemsi loop. */ |
6ed01e6b AW |
922 | |
923 | #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4) | |
924 | ||
925 | /* The maximum number of bytes that can be copied by a straight-line | |
76715c32 | 926 | cpymemsi implementation. */ |
09cae750 | 927 | |
6ed01e6b AW |
928 | #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3) |
929 | ||
930 | /* If a memory-to-memory move would take MOVE_RATIO or more simple | |
76715c32 | 931 | move-instruction pairs, we will do a cpymem or libcall instead. |
6ed01e6b AW |
932 | Do not use move_by_pieces at all when strict alignment is not |
933 | in effect but the target has slow unaligned accesses; in this | |
76715c32 | 934 | case, cpymem or libcall is more efficient. */ |
6ed01e6b AW |
935 | |
936 | #define MOVE_RATIO(speed) \ | |
fb5621b1 | 937 | (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 : \ |
6ed01e6b AW |
938 | (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD : \ |
939 | CLEAR_RATIO (speed) / 2) | |
09cae750 PD |
940 | |
941 | /* For CLEAR_RATIO, when optimizing for size, give a better estimate | |
942 | of the length of a memset call, but use the default otherwise. */ | |
943 | ||
944 | #define CLEAR_RATIO(speed) ((speed) ? 16 : 6) | |
945 | ||
946 | /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
947 | optimizing for size adjust the ratio to account for the overhead of | |
948 | loading the constant and replicating it across the word. */ | |
949 | ||
950 | #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2)) | |
951 | ||
952 | #ifndef USED_FOR_TARGET | |
953 | extern const enum reg_class riscv_regno_to_class[]; | |
fb5621b1 KC |
954 | extern bool riscv_slow_unaligned_access_p; |
955 | extern unsigned riscv_stack_boundary; | |
09cae750 PD |
956 | #endif |
957 | ||
958 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
959 | (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) | |
960 | ||
961 | #define XLEN_SPEC \ | |
962 | "%{march=rv32*:32}" \ | |
963 | "%{march=rv64*:64}" \ | |
964 | ||
965 | #define ABI_SPEC \ | |
966 | "%{mabi=ilp32:ilp32}" \ | |
09baee1a | 967 | "%{mabi=ilp32e:ilp32e}" \ |
09cae750 PD |
968 | "%{mabi=ilp32f:ilp32f}" \ |
969 | "%{mabi=ilp32d:ilp32d}" \ | |
970 | "%{mabi=lp64:lp64}" \ | |
971 | "%{mabi=lp64f:lp64f}" \ | |
972 | "%{mabi=lp64d:lp64d}" \ | |
973 | ||
09cae750 PD |
974 | /* ISA constants needed for code generation. */ |
975 | #define OPCODE_LW 0x2003 | |
976 | #define OPCODE_LD 0x3003 | |
977 | #define OPCODE_AUIPC 0x17 | |
978 | #define OPCODE_JALR 0x67 | |
979 | #define OPCODE_LUI 0x37 | |
980 | #define OPCODE_ADDI 0x13 | |
981 | #define SHIFT_RD 7 | |
982 | #define SHIFT_RS1 15 | |
983 | #define SHIFT_IMM 20 | |
984 | #define IMM_BITS 12 | |
de6320a8 | 985 | #define C_S_BITS 5 |
10789329 | 986 | #define C_SxSP_BITS 6 |
09cae750 PD |
987 | |
988 | #define IMM_REACH (1LL << IMM_BITS) | |
989 | #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1)) | |
990 | #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) | |
991 | ||
10789329 JW |
992 | #define SWSP_REACH (4LL << C_SxSP_BITS) |
993 | #define SDSP_REACH (8LL << C_SxSP_BITS) | |
994 | ||
de6320a8 CB |
995 | /* This is the maximum value that can be represented in a compressed load/store |
996 | offset (an unsigned 5-bit value scaled by 4). */ | |
f95bd50b | 997 | #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3) |
de6320a8 | 998 | |
e53b6e56 | 999 | /* Called from RISCV_REORG, this is defined in riscv-sr.cc. */ |
e18a6d14 AB |
1000 | |
1001 | extern void riscv_remove_unneeded_save_restore_calls (void); | |
1002 | ||
e0a5b313 KC |
1003 | #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO) |
1004 | ||
09cae750 | 1005 | #endif /* ! GCC_RISCV_H */ |