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09cae750 | 1 | /* Definition of RISC-V target for GNU compiler. |
6441eb6d | 2 | Copyright (C) 2011-2025 Free Software Foundation, Inc. |
09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
4 | Based on MIPS target for GNU compiler. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef GCC_RISCV_H | |
23 | #define GCC_RISCV_H | |
24 | ||
94a4b932 | 25 | #include <stdbool.h> |
09cae750 PD |
26 | #include "config/riscv/riscv-opts.h" |
27 | ||
5f110561 KC |
28 | #define SWITCHABLE_TARGET 1 |
29 | ||
09cae750 PD |
30 | /* Target CPU builtins. */ |
31 | #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile) | |
32 | ||
cd1e2f63 MC |
33 | #ifdef TARGET_BIG_ENDIAN_DEFAULT |
34 | #define DEFAULT_ENDIAN_SPEC "b" | |
35 | #else | |
36 | #define DEFAULT_ENDIAN_SPEC "l" | |
37 | #endif | |
38 | ||
09cae750 PD |
39 | /* Default target_flags if no switches are specified */ |
40 | ||
41 | #ifndef TARGET_DEFAULT | |
42 | #define TARGET_DEFAULT 0 | |
43 | #endif | |
44 | ||
45 | #ifndef RISCV_TUNE_STRING_DEFAULT | |
20f59301 | 46 | #define RISCV_TUNE_STRING_DEFAULT "generic" |
09cae750 PD |
47 | #endif |
48 | ||
f908b69c | 49 | extern const char *riscv_expand_arch (int argc, const char **argv); |
72eb8335 KC |
50 | extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv); |
51 | extern const char *riscv_default_mtune (int argc, const char **argv); | |
d72ca12b | 52 | extern const char *riscv_multi_lib_check (int argc, const char **argv); |
7af0f1e1 | 53 | extern const char *riscv_arch_help (int argc, const char **argv); |
f908b69c KC |
54 | |
55 | # define EXTRA_SPEC_FUNCTIONS \ | |
72eb8335 KC |
56 | { "riscv_expand_arch", riscv_expand_arch }, \ |
57 | { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \ | |
d72ca12b | 58 | { "riscv_default_mtune", riscv_default_mtune }, \ |
7af0f1e1 KC |
59 | { "riscv_multi_lib_check", riscv_multi_lib_check }, \ |
60 | { "riscv_arch_help", riscv_arch_help }, | |
f908b69c | 61 | |
09cae750 | 62 | /* Support for a compile-time default CPU, et cetera. The rules are: |
72eb8335 | 63 | --with-arch is ignored if -march or -mcpu is specified. |
09cae750 | 64 | --with-abi is ignored if -mabi is specified. |
72eb8335 | 65 | --with-tune is ignored if -mtune or -mcpu is specified. |
06e32a5e | 66 | --with-isa-spec is ignored if -misa-spec is specified. |
97069657 | 67 | --with-tls is ignored if -mtls-dialect is specified. |
72eb8335 KC |
68 | |
69 | But using default -march/-mtune value if -mcpu don't have valid option. */ | |
09cae750 | 70 | #define OPTION_DEFAULT_SPECS \ |
72eb8335 KC |
71 | {"tune", "%{!mtune=*:" \ |
72 | " %{!mcpu=*:-mtune=%(VALUE)}" \ | |
73 | " %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" }, \ | |
74 | {"arch", "%{!march=*:" \ | |
75 | " %{!mcpu=*:-march=%(VALUE)}" \ | |
76 | " %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \ | |
97069657 TI |
77 | {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ |
78 | {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \ | |
79 | {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, \ | |
09cae750 PD |
80 | |
81 | #ifdef IN_LIBGCC2 | |
82 | #undef TARGET_64BIT | |
83 | /* Make this compile time constant for libgcc2 */ | |
84 | #define TARGET_64BIT (__riscv_xlen == 64) | |
85 | #endif /* IN_LIBGCC2 */ | |
86 | ||
4b815282 KC |
87 | #ifdef HAVE_AS_MISA_SPEC |
88 | #define ASM_MISA_SPEC "%{misa-spec=*}" | |
89 | #else | |
90 | #define ASM_MISA_SPEC "" | |
91 | #endif | |
92 | ||
a5ad5d5c KC |
93 | /* Reference: |
94 | https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing */ | |
95 | #define STRINGIZING(s) __STRINGIZING(s) | |
96 | #define __STRINGIZING(s) #s | |
97 | ||
98 | #define MULTILIB_DEFAULTS \ | |
99 | {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \ | |
100 | "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) } | |
101 | ||
09cae750 PD |
102 | #undef ASM_SPEC |
103 | #define ASM_SPEC "\ | |
104 | %(subtarget_asm_debugging_spec) \ | |
105 | %{" FPIE_OR_FPIC_SPEC ":-fpic} \ | |
f4670347 | 106 | %{march=*} \ |
09cae750 | 107 | %{mabi=*} \ |
3b0a7d62 | 108 | %{mno-relax} \ |
a9604fcb MC |
109 | %{mbig-endian} \ |
110 | %{mlittle-endian} \ | |
4b815282 KC |
111 | %(subtarget_asm_spec)" \ |
112 | ASM_MISA_SPEC | |
09cae750 | 113 | |
f4670347 | 114 | #undef DRIVER_SELF_SPECS |
72eb8335 | 115 | #define DRIVER_SELF_SPECS \ |
7af0f1e1 KC |
116 | "%{march=help:%:riscv_arch_help()} " \ |
117 | "%{print-supported-extensions:%:riscv_arch_help()} " \ | |
118 | "%{-print-supported-extensions:%:riscv_arch_help()} " \ | |
72eb8335 KC |
119 | "%{march=*:%:riscv_expand_arch(%*)} " \ |
120 | "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} " | |
f4670347 | 121 | |
09cae750 PD |
122 | #define LOCAL_LABEL_PREFIX "." |
123 | #define USER_LABEL_PREFIX "" | |
124 | ||
125 | /* Offsets recorded in opcodes are a multiple of this alignment factor. | |
126 | The default for this in 64-bit mode is 8, which causes problems with | |
127 | SFmode register saves. */ | |
128 | #define DWARF_CIE_DATA_ALIGNMENT -4 | |
129 | ||
130 | /* The mapping from gcc register number to DWARF 2 CFA column number. */ | |
31380d4b | 131 | #define DWARF_FRAME_REGNUM(REGNO) \ |
8cd140d3 JZ |
132 | (FRM_REG_P (REGNO) ? RISCV_DWARF_FRM \ |
133 | : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM \ | |
134 | : VL_REG_P (REGNO) ? RISCV_DWARF_VL \ | |
31380d4b | 135 | : VTYPE_REG_P (REGNO) \ |
136 | ? RISCV_DWARF_VTYPE \ | |
137 | : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO) \ | |
138 | ? REGNO \ | |
139 | : INVALID_REGNUM)) | |
09cae750 PD |
140 | |
141 | /* The DWARF 2 CFA column which tracks the return address. */ | |
142 | #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM | |
143 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM) | |
144 | ||
145 | /* Describe how we implement __builtin_eh_return. */ | |
146 | #define EH_RETURN_DATA_REGNO(N) \ | |
147 | ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM) | |
148 | ||
149 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4) | |
150 | ||
151 | /* Target machine storage layout */ | |
152 | ||
153 | #define BITS_BIG_ENDIAN 0 | |
a9604fcb MC |
154 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
155 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) | |
09cae750 PD |
156 | |
157 | #define MAX_BITS_PER_WORD 64 | |
158 | ||
159 | /* Width of a word, in units (bytes). */ | |
160 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
a99dc11f | 161 | #define BITS_PER_WORD (BITS_PER_UNIT * UNITS_PER_WORD) |
09cae750 PD |
162 | #ifndef IN_LIBGCC2 |
163 | #define MIN_UNITS_PER_WORD 4 | |
164 | #endif | |
165 | ||
e53b6e56 | 166 | /* Allows SImode op in builtin overflow pattern, see internal-fn.cc. */ |
6efd040c L |
167 | #undef TARGET_MIN_ARITHMETIC_PRECISION |
168 | #define TARGET_MIN_ARITHMETIC_PRECISION riscv_min_arithmetic_precision | |
169 | ||
09cae750 PD |
170 | /* The `Q' extension is not yet supported. */ |
171 | #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) | |
e9f827d7 | 172 | /* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */ |
31380d4b | 173 | #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk) |
09cae750 PD |
174 | |
175 | /* The largest type that can be passed in floating-point registers. */ | |
09baee1a KC |
176 | #define UNITS_PER_FP_ARG \ |
177 | ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \ | |
006e90e1 | 178 | || riscv_abi == ABI_LP64 || riscv_abi == ABI_LP64E) \ |
09baee1a KC |
179 | ? 0 \ |
180 | : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8)) | |
09cae750 PD |
181 | |
182 | /* Set the sizes of the core types. */ | |
183 | #define SHORT_TYPE_SIZE 16 | |
184 | #define INT_TYPE_SIZE 32 | |
185 | #define LONG_LONG_TYPE_SIZE 64 | |
186 | #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32) | |
187 | #define LONG_TYPE_SIZE POINTER_SIZE | |
188 | ||
09cae750 PD |
189 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
190 | #define PARM_BOUNDARY BITS_PER_WORD | |
191 | ||
192 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
805a052d | 193 | #define FUNCTION_BOUNDARY \ |
59a869d7 | 194 | (((TARGET_RVC || TARGET_ZCA) && !is_zicfilp_p ()) ? 16 : 32) |
09cae750 | 195 | |
0ce42fe1 | 196 | /* The smallest supported stack boundary the calling convention supports. */ |
75902396 | 197 | #define STACK_BOUNDARY \ |
006e90e1 TO |
198 | (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \ |
199 | ? BITS_PER_WORD \ | |
200 | : 2 * BITS_PER_WORD) | |
0ce42fe1 AW |
201 | |
202 | /* The ABI stack alignment. */ | |
006e90e1 TO |
203 | #define ABI_STACK_BOUNDARY \ |
204 | (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \ | |
205 | ? BITS_PER_WORD \ | |
206 | : 128) | |
0ce42fe1 | 207 | |
09cae750 | 208 | /* There is no point aligning anything to a rounder boundary than this. */ |
c0d3d1b6 | 209 | #define BIGGEST_ALIGNMENT 128 |
09cae750 | 210 | |
82285692 AW |
211 | /* The user-level ISA permits unaligned accesses, but they are not required |
212 | of the privileged architecture. */ | |
213 | #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN | |
214 | ||
09cae750 PD |
215 | /* Define this if you wish to imitate the way many other C compilers |
216 | handle alignment of bitfields and the structures that contain | |
217 | them. | |
218 | ||
219 | The behavior is that the type written for a bit-field (`int', | |
220 | `short', or other integer type) imposes an alignment for the | |
221 | entire structure, as if the structure really did contain an | |
222 | ordinary field of that type. In addition, the bit-field is placed | |
223 | within the structure so that it would fit within such a field, | |
224 | not crossing a boundary for it. | |
225 | ||
226 | Thus, on most machines, a bit-field whose type is written as `int' | |
227 | would not cross a four-byte boundary, and would force four-byte | |
228 | alignment for the whole structure. (The alignment used may not | |
229 | be four bytes; it is controlled by the other alignment | |
230 | parameters.) | |
231 | ||
232 | If the macro is defined, its definition should be a C expression; | |
233 | a nonzero value for the expression enables this behavior. */ | |
234 | ||
235 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
236 | ||
d3f952c5 JW |
237 | /* An integer expression for the size in bits of the largest integer machine |
238 | mode that should actually be used. We allow pairs of registers. */ | |
239 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
240 | ||
ffbb9818 ID |
241 | /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition. */ |
242 | #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN) \ | |
243 | (((COND) && ((ALIGN) < BITS_PER_WORD) \ | |
244 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
245 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
246 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
247 | ||
09cae750 PD |
248 | /* If defined, a C expression to compute the alignment for a static |
249 | variable. TYPE is the data type, and ALIGN is the alignment that | |
250 | the object would ordinarily have. The value of this macro is used | |
251 | instead of that alignment to align the object. | |
252 | ||
253 | If this macro is not defined, then ALIGN is used. | |
254 | ||
255 | One use of this macro is to increase alignment of medium-size | |
256 | data to make it all fit in fewer cache lines. Another is to | |
257 | cause character arrays to be word-aligned so that `strcpy' calls | |
258 | that copy constants to character arrays can be done inline. */ | |
259 | ||
ffbb9818 ID |
260 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
261 | RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen, \ | |
262 | TYPE, ALIGN) | |
09cae750 PD |
263 | |
264 | /* We need this for the same reason as DATA_ALIGNMENT, namely to cause | |
265 | character arrays to be word-aligned so that `strcpy' calls that copy | |
266 | constants to character arrays can be done inline, and 'strcmp' can be | |
267 | optimised to use word loads. */ | |
268 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
ffbb9818 | 269 | RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN) |
09cae750 PD |
270 | |
271 | /* Define if operations between registers always perform the operation | |
272 | on the full register even if a narrower mode is specified. */ | |
273 | #define WORD_REGISTER_OPERATIONS 1 | |
274 | ||
275 | /* When in 64-bit mode, move insns will sign extend SImode and CCmode | |
276 | moves. All other references are zero extended. */ | |
277 | #define LOAD_EXTEND_OP(MODE) \ | |
278 | (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) | |
279 | ||
280 | /* Define this macro if it is advisable to hold scalars in registers | |
281 | in a wider mode than that declared by the program. In such cases, | |
282 | the value is constrained to be within the bounds of the declared | |
283 | type, but kept valid in the wider mode. The signedness of the | |
284 | extension may differ from that of the type. */ | |
285 | ||
286 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
287 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
288 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
289 | { \ | |
290 | if ((MODE) == SImode) \ | |
291 | (UNSIGNEDP) = 0; \ | |
292 | (MODE) = word_mode; \ | |
293 | } | |
294 | ||
295 | /* Pmode is always the same as ptr_mode, but not always the same as word_mode. | |
296 | Extensions of pointers to word_mode must be signed. */ | |
297 | #define POINTERS_EXTEND_UNSIGNED false | |
298 | ||
09cae750 PD |
299 | /* Define if loading short immediate values into registers sign extends. */ |
300 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 | |
301 | ||
302 | /* Standard register usage. */ | |
303 | ||
304 | /* Number of hardware registers. We have: | |
305 | ||
306 | - 32 integer registers | |
307 | - 32 floating point registers | |
308 | - 2 fake registers: | |
309 | - ARG_POINTER_REGNUM | |
31380d4b | 310 | - FRAME_POINTER_REGNUM |
311 | - 1 vl register | |
312 | - 1 vtype register | |
467ca4a1 | 313 | - 28 unused registers for future expansion |
31380d4b | 314 | - 32 vector registers */ |
09cae750 | 315 | |
31380d4b | 316 | #define FIRST_PSEUDO_REGISTER 128 |
09cae750 | 317 | |
79a3d3da | 318 | /* x0, ra, sp, gp, and tp are fixed. */ |
09cae750 PD |
319 | |
320 | #define FIXED_REGISTERS \ | |
321 | { /* General registers. */ \ | |
71f90649 | 322 | 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
09cae750 PD |
323 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
324 | /* Floating-point registers. */ \ | |
325 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
326 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
327 | /* Others. */ \ | |
a035d133 | 328 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
31380d4b | 329 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
330 | /* Vector registers. */ \ | |
331 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
332 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ | |
09cae750 PD |
333 | } |
334 | ||
f3abed16 | 335 | /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls. |
09cae750 PD |
336 | The call RTLs themselves clobber ra. */ |
337 | ||
338 | #define CALL_USED_REGISTERS \ | |
339 | { /* General registers. */ \ | |
71f90649 | 340 | 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ |
09cae750 PD |
341 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ |
342 | /* Floating-point registers. */ \ | |
343 | 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ | |
344 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ | |
345 | /* Others. */ \ | |
31380d4b | 346 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
347 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
348 | /* Vector registers. */ \ | |
349 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
350 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ | |
09cae750 PD |
351 | } |
352 | ||
b780f68e JW |
353 | /* Select a register mode required for caller save of hard regno REGNO. |
354 | Contrary to what is documented, the default is not the smallest suitable | |
355 | mode but the largest suitable mode for the given (REGNO, NREGS) pair and | |
356 | it quickly creates paradoxical subregs that can be problematic. */ | |
357 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
358 | ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE)) | |
359 | ||
09cae750 PD |
360 | /* Internal macros to classify an ISA register's type. */ |
361 | ||
362 | #define GP_REG_FIRST 0 | |
09baee1a | 363 | #define GP_REG_LAST (TARGET_RVE ? 15 : 31) |
09cae750 PD |
364 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) |
365 | ||
366 | #define FP_REG_FIRST 32 | |
367 | #define FP_REG_LAST 63 | |
368 | #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
369 | ||
31380d4b | 370 | #define V_REG_FIRST 96 |
371 | #define V_REG_LAST 127 | |
372 | #define V_REG_NUM (V_REG_LAST - V_REG_FIRST + 1) | |
373 | ||
09cae750 PD |
374 | /* The DWARF 2 CFA column which tracks the return address from a |
375 | signal handler context. This means that to maintain backwards | |
376 | compatibility, no hard register can be assigned this column if it | |
377 | would need to be handled by the DWARF unwinder. */ | |
378 | #define DWARF_ALT_FRAME_RETURN_COLUMN 64 | |
379 | ||
380 | #define GP_REG_P(REGNO) \ | |
381 | ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
382 | #define FP_REG_P(REGNO) \ | |
383 | ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
60d6c63d CM |
384 | #define HARDFP_REG_P(REGNO) \ |
385 | ((REGNO) >= FP_REG_FIRST && (REGNO) <= FP_REG_LAST) | |
31380d4b | 386 | #define V_REG_P(REGNO) \ |
387 | ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM) | |
388 | #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM) | |
389 | #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM) | |
5ed88078 | 390 | #define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM) |
8cd140d3 | 391 | #define FRM_REG_P(REGNO) ((REGNO) == FRM_REGNUM) |
09cae750 | 392 | |
e18a6d14 AB |
393 | /* True when REGNO is in SIBCALL_REGS set. */ |
394 | #define SIBCALL_REG_P(REGNO) \ | |
395 | TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO) | |
396 | ||
09cae750 PD |
397 | #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) |
398 | ||
09cae750 PD |
399 | /* Use s0 as the frame pointer if it is so requested. */ |
400 | #define HARD_FRAME_POINTER_REGNUM 8 | |
401 | #define STACK_POINTER_REGNUM 2 | |
402 | #define THREAD_POINTER_REGNUM 4 | |
403 | ||
404 | /* These two registers don't really exist: they get eliminated to either | |
405 | the stack or hard frame pointer. */ | |
406 | #define ARG_POINTER_REGNUM 64 | |
407 | #define FRAME_POINTER_REGNUM 65 | |
408 | ||
31380d4b | 409 | /* Define Dwarf for RVV. */ |
8cd140d3 | 410 | #define RISCV_DWARF_FRM (4096 + 0x003) |
5ed88078 | 411 | #define RISCV_DWARF_VXRM (4096 + 0x00a) |
31380d4b | 412 | #define RISCV_DWARF_VL (4096 + 0xc20) |
413 | #define RISCV_DWARF_VTYPE (4096 + 0xc21) | |
5576518a | 414 | #define RISCV_DWARF_VLENB (4096 + 0xc22) |
31380d4b | 415 | |
09cae750 | 416 | /* Register in which static-chain is passed to a function. */ |
805a052d | 417 | #define STATIC_CHAIN_REGNUM \ |
59a869d7 | 418 | ((is_zicfilp_p ()) ? (GP_TEMP_FIRST + 23) : (GP_TEMP_FIRST + 2)) |
09cae750 PD |
419 | |
420 | /* Registers used as temporaries in prologue/epilogue code. | |
421 | ||
422 | The prologue registers mustn't conflict with any | |
423 | incoming arguments, the static chain pointer, or the frame pointer. | |
424 | The epilogue temporary mustn't conflict with the return registers, | |
425 | the frame pointer, the EH stack adjustment, or the EH data registers. */ | |
426 | ||
207de839 | 427 | #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST) |
09cae750 | 428 | #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM) |
5576518a JZZ |
429 | #define RISCV_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST + 1) |
430 | #define RISCV_PROLOGUE_TEMP2(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP2_REGNUM) | |
09cae750 | 431 | |
2862d99b RMZ |
432 | /* Both prologue temp registers are used in the vector probe loop for when |
433 | stack-clash protection is enabled, so we need to copy SP to a new register | |
434 | and set it as CFA during the loop, we are using T3 for that. */ | |
435 | #define RISCV_STACK_CLASH_VECTOR_CFA_REGNUM (GP_TEMP_FIRST + 23) | |
436 | ||
207de839 MC |
437 | #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1) |
438 | #define RISCV_CALL_ADDRESS_TEMP(MODE) \ | |
439 | gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM) | |
440 | ||
805a052d MC |
441 | #define RISCV_CALL_ADDRESS_LPAD_REGNUM (GP_TEMP_FIRST + 2) |
442 | #define RISCV_CALL_ADDRESS_LPAD(MODE) \ | |
443 | gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_LPAD_REGNUM) | |
444 | ||
3d1d3132 FG |
445 | #define RETURN_ADDR_MASK (1 << RETURN_ADDR_REGNUM) |
446 | #define S0_MASK (1 << S0_REGNUM) | |
447 | #define S1_MASK (1 << S1_REGNUM) | |
448 | #define S2_MASK (1 << S2_REGNUM) | |
449 | #define S3_MASK (1 << S3_REGNUM) | |
450 | #define S4_MASK (1 << S4_REGNUM) | |
451 | #define S5_MASK (1 << S5_REGNUM) | |
452 | #define S6_MASK (1 << S6_REGNUM) | |
453 | #define S7_MASK (1 << S7_REGNUM) | |
454 | #define S8_MASK (1 << S8_REGNUM) | |
455 | #define S9_MASK (1 << S9_REGNUM) | |
456 | #define S10_MASK (1 << S10_REGNUM) | |
457 | #define S11_MASK (1 << S11_REGNUM) | |
458 | ||
459 | #define MULTI_PUSH_GPR_MASK \ | |
460 | (RETURN_ADDR_MASK | S0_MASK | S1_MASK | S2_MASK | S3_MASK | S4_MASK \ | |
461 | | S5_MASK | S6_MASK | S7_MASK | S8_MASK | S9_MASK | S10_MASK | S11_MASK) | |
462 | #define ZCMP_MAX_SPIMM 3 | |
463 | #define ZCMP_SP_INC_STEP 16 | |
464 | #define ZCMP_INVALID_S0S10_SREGS_COUNTS 11 | |
465 | #define ZCMP_S0S11_SREGS_COUNTS 12 | |
466 | #define ZCMP_MAX_GRP_SLOTS 13 | |
467 | ||
09cae750 PD |
468 | #define MCOUNT_NAME "_mcount" |
469 | ||
470 | #define NO_PROFILE_COUNTERS 1 | |
471 | ||
472 | /* Emit rtl for profiling. Output assembler code to FILE | |
473 | to call "_mcount" for profiling a function entry. */ | |
474 | #define PROFILE_HOOK(LABEL) \ | |
475 | { \ | |
476 | rtx fun, ra; \ | |
477 | ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \ | |
478 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ | |
db69559b | 479 | emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \ |
09cae750 PD |
480 | } |
481 | ||
482 | /* All the work done in PROFILE_HOOK, but still required. */ | |
483 | #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) | |
484 | ||
485 | /* Define this macro if it is as good or better to call a constant | |
486 | function address than to call an address kept in a register. */ | |
487 | #define NO_FUNCTION_CSE 1 | |
488 | ||
489 | /* Define the classes of registers for register constraints in the | |
490 | machine description. Also define ranges of constants. | |
491 | ||
492 | One of the classes must always be named ALL_REGS and include all hard regs. | |
493 | If there is more than one class, another class must be named NO_REGS | |
494 | and contain no registers. | |
495 | ||
496 | The name GENERAL_REGS must be the name of a class (or an alias for | |
497 | another name such as ALL_REGS). This is the class of registers | |
498 | that is allowed by "g" or "r" in a register constraint. | |
499 | Also, registers outside this class are allocated only when | |
500 | instructions express preferences for them. | |
501 | ||
502 | The classes must be numbered in nondecreasing order; that is, | |
503 | a larger-numbered class must never be contained completely | |
504 | in a smaller-numbered class. | |
505 | ||
506 | For any two classes, it is very desirable that there be another | |
507 | class that represents their union. */ | |
508 | ||
509 | enum reg_class | |
510 | { | |
511 | NO_REGS, /* no registers in set */ | |
512 | SIBCALL_REGS, /* registers used by indirect sibcalls */ | |
46888571 | 513 | RVC_GR_REGS, /* RVC general registers */ |
09cae750 PD |
514 | JALR_REGS, /* registers used by indirect calls */ |
515 | GR_REGS, /* integer registers */ | |
46888571 | 516 | RVC_FP_REGS, /* RVC floating-point registers */ |
09cae750 PD |
517 | FP_REGS, /* floating-point registers */ |
518 | FRAME_REGS, /* arg pointer and frame pointer */ | |
31380d4b | 519 | VM_REGS, /* v0.t registers */ |
520 | VD_REGS, /* vector registers except v0.t */ | |
521 | V_REGS, /* vector registers */ | |
09cae750 PD |
522 | ALL_REGS, /* all registers */ |
523 | LIM_REG_CLASSES /* max value + 1 */ | |
524 | }; | |
525 | ||
526 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
527 | ||
528 | #define GENERAL_REGS GR_REGS | |
529 | ||
530 | /* An initializer containing the names of the register classes as C | |
531 | string constants. These names are used in writing some of the | |
532 | debugging dumps. */ | |
533 | ||
534 | #define REG_CLASS_NAMES \ | |
535 | { \ | |
536 | "NO_REGS", \ | |
537 | "SIBCALL_REGS", \ | |
46888571 | 538 | "RVC_GR_REGS", \ |
09cae750 PD |
539 | "JALR_REGS", \ |
540 | "GR_REGS", \ | |
46888571 | 541 | "RVC_FP_REGS", \ |
09cae750 PD |
542 | "FP_REGS", \ |
543 | "FRAME_REGS", \ | |
31380d4b | 544 | "VM_REGS", \ |
545 | "VD_REGS", \ | |
546 | "V_REGS", \ | |
09cae750 PD |
547 | "ALL_REGS" \ |
548 | } | |
549 | ||
550 | /* An initializer containing the contents of the register classes, | |
551 | as integers which are bit masks. The Nth integer specifies the | |
552 | contents of class N. The way the integer MASK is interpreted is | |
553 | that register R is in the class if `MASK & (1 << R)' is 1. | |
554 | ||
555 | When the machine has more than 32 registers, an integer does not | |
556 | suffice. Then the integers are replaced by sub-initializers, | |
557 | braced groupings containing several integers. Each | |
558 | sub-initializer must be suitable as an initializer for the type | |
559 | `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ | |
560 | ||
561 | #define REG_CLASS_CONTENTS \ | |
562 | { \ | |
31380d4b | 563 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ |
564 | { 0xf003fcc0, 0x00000000, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ | |
46888571 | 565 | { 0x0000ff00, 0x00000000, 0x00000000, 0x00000000 }, /* RVC_GR_REGS */ \ |
31380d4b | 566 | { 0xffffffc0, 0x00000000, 0x00000000, 0x00000000 }, /* JALR_REGS */ \ |
567 | { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ | |
46888571 | 568 | { 0x00000000, 0x0000ff00, 0x00000000, 0x00000000 }, /* RVC_FP_REGS */ \ |
31380d4b | 569 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FP_REGS */ \ |
570 | { 0x00000000, 0x00000000, 0x00000003, 0x00000000 }, /* FRAME_REGS */ \ | |
31380d4b | 571 | { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \ |
572 | { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe }, /* VNoV0_REGS */ \ | |
573 | { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* V_REGS */ \ | |
167b04b9 | 574 | { 0xffffffff, 0xffffffff, 0x00000003, 0xffffffff } /* ALL_REGS */ \ |
09cae750 PD |
575 | } |
576 | ||
577 | /* A C expression whose value is a register class containing hard | |
578 | register REGNO. In general there is more that one such class; | |
579 | choose a class which is "minimal", meaning that no smaller class | |
580 | also contains the register. */ | |
581 | ||
582 | #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ] | |
583 | ||
584 | /* A macro whose definition is the name of the class to which a | |
585 | valid base register must belong. A base register is one used in | |
586 | an address which is the register value plus a displacement. */ | |
587 | ||
588 | #define BASE_REG_CLASS GR_REGS | |
589 | ||
590 | /* A macro whose definition is the name of the class to which a | |
591 | valid index register must belong. An index register is one used | |
592 | in an address where its value is either multiplied by a scale | |
593 | factor or added to another register (as well as added to a | |
594 | displacement). */ | |
595 | ||
42360427 | 596 | #define INDEX_REG_CLASS riscv_index_reg_class() |
09cae750 PD |
597 | |
598 | /* We generally want to put call-clobbered registers ahead of | |
599 | call-saved ones. (IRA expects this.) */ | |
600 | ||
601 | #define REG_ALLOC_ORDER \ | |
602 | { \ | |
603 | /* Call-clobbered GPRs. */ \ | |
604 | 15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1, \ | |
605 | /* Call-saved GPRs. */ \ | |
606 | 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ | |
607 | /* GPRs that can never be exposed to the register allocator. */ \ | |
608 | 0, 2, 3, 4, \ | |
609 | /* Call-clobbered FPRs. */ \ | |
610 | 47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49, \ | |
611 | 60, 61, 62, 63, \ | |
612 | /* Call-saved FPRs. */ \ | |
613 | 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ | |
7b206ae7 JZ |
614 | /* v1 ~ v31 vector registers. */ \ |
615 | 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, \ | |
616 | 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \ | |
617 | 124, 125, 126, 127, \ | |
618 | /* The vector mask register. */ \ | |
619 | 96, \ | |
09cae750 PD |
620 | /* None of the remaining classes have defined call-saved \ |
621 | registers. */ \ | |
31380d4b | 622 | 64, 65, 66, 67 \ |
09cae750 PD |
623 | } |
624 | ||
625 | /* True if VALUE is a signed 12-bit number. */ | |
626 | ||
627 | #define SMALL_OPERAND(VALUE) \ | |
628 | ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH) | |
629 | ||
3496ca4e | 630 | #define POLY_SMALL_OPERAND_P(POLY_VALUE) \ |
631 | (POLY_VALUE.is_constant () ? \ | |
632 | SMALL_OPERAND (POLY_VALUE.to_constant ()) : false) | |
7b0073c6 | 633 | |
09cae750 PD |
634 | /* True if VALUE can be loaded into a register using LUI. */ |
635 | ||
636 | #define LUI_OPERAND(VALUE) \ | |
637 | (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \ | |
638 | || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0) | |
639 | ||
4bfc4585 VG |
640 | /* True if a VALUE (constant) can be expressed as sum of two S12 constants |
641 | (in range -2048 to 2047). | |
642 | Range check logic: | |
643 | from: min S12 + 1 (or -1 depending on what side of zero) | |
644 | to: two times the min S12 value (to max out S12 bits). */ | |
645 | ||
646 | #define SUM_OF_TWO_S12_N(VALUE) \ | |
647 | (((VALUE) >= (-2048 * 2)) && ((VALUE) <= (-2048 - 1))) | |
648 | ||
649 | #define SUM_OF_TWO_S12_P(VALUE) \ | |
650 | (((VALUE) >= (2047 + 1)) && ((VALUE) <= (2047 * 2))) | |
651 | ||
652 | #define SUM_OF_TWO_S12(VALUE) \ | |
653 | (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P (VALUE)) | |
654 | ||
f9cfc192 VG |
655 | /* Variant with first value 8 byte aligned if involving stack regs. */ |
656 | #define SUM_OF_TWO_S12_P_ALGN(VALUE) \ | |
657 | (((VALUE) >= (2032 + 1)) && ((VALUE) <= (2032 * 2))) | |
658 | ||
659 | #define SUM_OF_TWO_S12_ALGN(VALUE) \ | |
660 | (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P_ALGN (VALUE)) | |
661 | ||
4e72ccad PT |
662 | /* If this is a single bit mask, then we can load it with bseti. Special |
663 | handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ | |
664 | #define SINGLE_BIT_MASK_OPERAND(VALUE) \ | |
2c721ea9 AP |
665 | (pow2p_hwi (TARGET_64BIT \ |
666 | ? (VALUE) \ | |
667 | : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1)))) | |
4e1e0d79 | 668 | |
bc6beecb PT |
669 | /* True if VALUE can be represented as an immediate with 1 extra bit |
670 | set: we check that it is not a SMALL_OPERAND (as this would be true | |
671 | for all small operands) unmodified and turns into a small operand | |
672 | once we clear the top bit. */ | |
673 | #define UIMM_EXTRA_BIT_OPERAND(VALUE) \ | |
674 | (!SMALL_OPERAND (VALUE) \ | |
675 | && SMALL_OPERAND (VALUE & ~(HOST_WIDE_INT_1U << floor_log2 (VALUE)))) | |
676 | ||
52e809d5 JM |
677 | /* True if bit BIT is set in VALUE. */ |
678 | #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0) | |
679 | ||
c8957c87 JV |
680 | /* Returns the smaller (common) number of trailing zeros for VAL1 and VAL2. */ |
681 | #define COMMON_TRAILING_ZEROS(VAL1, VAL2) \ | |
682 | (ctz_hwi (VAL1) < ctz_hwi (VAL2) \ | |
683 | ? ctz_hwi (VAL1) \ | |
684 | : ctz_hwi (VAL2)) | |
685 | ||
686 | /* Returns true if both VAL1 and VAL2 are SMALL_OPERANDs after shifting by | |
687 | the common number of trailing zeros. */ | |
688 | #define SMALL_AFTER_COMMON_TRAILING_SHIFT(VAL1, VAL2) \ | |
689 | (SMALL_OPERAND ((VAL1) >> COMMON_TRAILING_ZEROS (VAL1, VAL2)) \ | |
690 | && SMALL_OPERAND ((VAL2) >> COMMON_TRAILING_ZEROS (VAL1, VAL2))) | |
691 | ||
09cae750 PD |
692 | /* Stack layout; function entry, exit and calling. */ |
693 | ||
694 | #define STACK_GROWS_DOWNWARD 1 | |
695 | ||
696 | #define FRAME_GROWS_DOWNWARD 1 | |
697 | ||
09cae750 PD |
698 | #define RETURN_ADDR_RTX riscv_return_addr |
699 | ||
700 | #define ELIMINABLE_REGS \ | |
701 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
702 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
703 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
704 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
705 | ||
706 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
707 | (OFFSET) = riscv_initial_elimination_offset (FROM, TO) | |
708 | ||
709 | /* Allocate stack space for arguments at the beginning of each function. */ | |
710 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
711 | ||
712 | /* The argument pointer always points to the first argument. */ | |
713 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
714 | ||
715 | #define REG_PARM_STACK_SPACE(FNDECL) 0 | |
716 | ||
717 | /* Define this if it is the responsibility of the caller to | |
718 | allocate the area reserved for arguments passed in registers. | |
719 | If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect | |
720 | of this macro is to determine whether the space is included in | |
721 | `crtl->outgoing_args_size'. */ | |
722 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 | |
723 | ||
c0d3d1b6 | 724 | #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary |
0ce42fe1 | 725 | |
09cae750 PD |
726 | /* Symbolic macros for the registers used to return integer and floating |
727 | point values. */ | |
728 | ||
729 | #define GP_RETURN GP_ARG_FIRST | |
730 | #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST) | |
e40a3d86 PL |
731 | #define V_RETURN V_REG_FIRST |
732 | ||
733 | #define GP_RETURN_FIRST GP_ARG_FIRST | |
734 | #define GP_RETURN_LAST GP_ARG_FIRST + 1 | |
735 | #define FP_RETURN_FIRST FP_RETURN | |
736 | #define FP_RETURN_LAST FP_RETURN + 1 | |
09cae750 | 737 | |
006e90e1 TO |
738 | #define MAX_ARGS_IN_REGISTERS \ |
739 | (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \ | |
740 | ? 6 \ | |
741 | : 8) | |
09cae750 | 742 | |
94a4b932 LD |
743 | #define MAX_ARGS_IN_VECTOR_REGISTERS (16) |
744 | #define MAX_ARGS_IN_MASK_REGISTERS (1) | |
745 | ||
09cae750 PD |
746 | /* Symbolic macros for the first/last argument registers. */ |
747 | ||
748 | #define GP_ARG_FIRST (GP_REG_FIRST + 10) | |
749 | #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) | |
750 | #define GP_TEMP_FIRST (GP_REG_FIRST + 5) | |
751 | #define FP_ARG_FIRST (FP_REG_FIRST + 10) | |
752 | #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) | |
94a4b932 LD |
753 | #define V_ARG_FIRST (V_REG_FIRST + 8) |
754 | #define V_ARG_LAST (V_ARG_FIRST + MAX_ARGS_IN_VECTOR_REGISTERS - 1) | |
09cae750 PD |
755 | |
756 | #define CALLEE_SAVED_REG_NUMBER(REGNO) \ | |
757 | ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \ | |
758 | (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1) | |
759 | ||
3d1d3132 FG |
760 | #define CALLEE_SAVED_FREG_NUMBER(REGNO) CALLEE_SAVED_REG_NUMBER (REGNO - 32) |
761 | ||
09cae750 PD |
762 | #define LIBCALL_VALUE(MODE) \ |
763 | riscv_function_value (NULL_TREE, NULL_TREE, MODE) | |
764 | ||
765 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
766 | riscv_function_value (VALTYPE, FUNC, VOIDmode) | |
767 | ||
09cae750 | 768 | /* 1 if N is a possible register number for function argument passing. |
1fb157cc | 769 | We have no FP argument registers when soft-float. */ |
09cae750 PD |
770 | |
771 | /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */ | |
772 | #define FUNCTION_ARG_REGNO_P(N) \ | |
773 | (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \ | |
774 | || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST))) | |
775 | ||
94a4b932 LD |
776 | /* Define the standard RISC-V calling convention and variants. */ |
777 | ||
778 | enum riscv_cc | |
779 | { | |
780 | RISCV_CC_BASE = 0, /* Base standard RISC-V ABI. */ | |
781 | RISCV_CC_V, /* For functions that pass or return values in V registers. */ | |
782 | RISCV_CC_UNKNOWN | |
783 | }; | |
784 | ||
09cae750 | 785 | typedef struct { |
94a4b932 LD |
786 | /* The calling convention that current function used. */ |
787 | enum riscv_cc variant_cc; | |
788 | ||
09cae750 PD |
789 | /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */ |
790 | unsigned int num_gprs; | |
791 | ||
792 | /* Number of floating-point registers used so far, likewise. */ | |
793 | unsigned int num_fprs; | |
1d4d302a | 794 | |
94a4b932 LD |
795 | /* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS. */ |
796 | unsigned int num_mrs; | |
797 | ||
798 | /* The used state of args in vector registers, true for used by prev arg, | |
799 | initial to false. */ | |
800 | bool used_vrs[MAX_ARGS_IN_VECTOR_REGISTERS]; | |
09cae750 PD |
801 | } CUMULATIVE_ARGS; |
802 | ||
fdd59c0f LD |
803 | /* Return riscv calling convention of call_insn. */ |
804 | extern enum riscv_cc get_riscv_cc (const rtx use); | |
805 | ||
09cae750 PD |
806 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
807 | for a call to a function whose data type is FNTYPE. | |
808 | For a library call, FNTYPE is 0. */ | |
809 | ||
810 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ | |
1d4d302a YW |
811 | riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \ |
812 | (N_NAMED_ARGS) != -1) | |
09cae750 | 813 | |
d0ebdd9f | 814 | #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO) |
09cae750 | 815 | |
0ce42fe1 AW |
816 | /* Align based on stack boundary, which might have been set by the user. */ |
817 | #define RISCV_STACK_ALIGN(LOC) \ | |
c0d3d1b6 | 818 | (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8)) |
09cae750 PD |
819 | |
820 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
821 | the stack pointer does not matter. The value is tested only in | |
822 | functions that have frame pointers. | |
823 | No definition is equivalent to always zero. */ | |
824 | ||
825 | #define EXIT_IGNORE_STACK 1 | |
826 | ||
827 | ||
828 | /* Trampolines are a block of code followed by two pointers. */ | |
829 | ||
59a869d7 | 830 | #define TRAMPOLINE_CODE_SIZE ((is_zicfilp_p ()) ? 24 : 16) |
805a052d | 831 | |
09cae750 PD |
832 | #define TRAMPOLINE_SIZE \ |
833 | ((Pmode == SImode) \ | |
834 | ? TRAMPOLINE_CODE_SIZE \ | |
835 | : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2)) | |
836 | #define TRAMPOLINE_ALIGNMENT POINTER_SIZE | |
837 | ||
838 | /* Addressing modes, and classification of registers for them. */ | |
839 | ||
42360427 CM |
840 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
841 | riscv_regno_ok_for_index_p (REGNO) | |
842 | ||
09cae750 PD |
843 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ |
844 | riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1) | |
845 | ||
846 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
847 | and check its validity for a certain class. | |
848 | We have two alternate definitions for each of them. | |
849 | The usual definition accepts all pseudo regs; the other rejects them all. | |
850 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
851 | ||
852 | Most source files want to accept pseudo regs in the hope that | |
853 | they will get allocated to the class that the insn wants them to be in. | |
854 | Some source files that are used after register allocation | |
855 | need to be strict. */ | |
856 | ||
857 | #ifndef REG_OK_STRICT | |
858 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
859 | riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) | |
860 | #else | |
861 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
862 | riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) | |
863 | #endif | |
864 | ||
865 | #define REG_OK_FOR_INDEX_P(X) 0 | |
866 | ||
867 | /* Maximum number of registers that can appear in a valid memory address. */ | |
868 | ||
869 | #define MAX_REGS_PER_ADDRESS 1 | |
870 | ||
871 | #define CONSTANT_ADDRESS_P(X) \ | |
872 | (CONSTANT_P (X) && memory_address_p (SImode, X)) | |
873 | ||
874 | /* This handles the magic '..CURRENT_FUNCTION' symbol, which means | |
875 | 'the start of the function that this code is output in'. */ | |
876 | ||
2041a23a TV |
877 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ |
878 | do { \ | |
879 | if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ | |
880 | asm_fprintf ((FILE), "%U%s", \ | |
881 | XSTR (XEXP (DECL_RTL (current_function_decl), \ | |
882 | 0), 0)); \ | |
883 | else \ | |
884 | asm_fprintf ((FILE), "%U%s", (NAME)); \ | |
885 | } while (0) | |
09cae750 | 886 | |
9a55cc62 JSJ |
887 | #undef ASM_OUTPUT_OPCODE |
888 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
889 | (PTR) = riscv_asm_output_opcode(STREAM, PTR) | |
890 | ||
1d9e02bb | 891 | #define JUMP_TABLES_IN_TEXT_SECTION (riscv_cmodel == CM_LARGE) |
09cae750 PD |
892 | #define CASE_VECTOR_MODE SImode |
893 | #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW) | |
894 | ||
7d4df630 VG |
895 | #define LOCAL_SYM_P(sym) \ |
896 | ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym)) \ | |
897 | || ((GET_CODE (sym) == CONST) \ | |
898 | && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0)) \ | |
899 | && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))) | |
900 | ||
09cae750 PD |
901 | /* The load-address macro is used for PC-relative addressing of symbols |
902 | that bind locally. Don't use it for symbols that should be addressed | |
903 | via the GOT. Also, avoid it for CM_MEDLOW, where LUI addressing | |
904 | currently results in more opportunities for linker relaxation. */ | |
905 | #define USE_LOAD_ADDRESS_MACRO(sym) \ | |
906 | (!TARGET_EXPLICIT_RELOCS && \ | |
7d4df630 | 907 | ((flag_pic && LOCAL_SYM_P (sym)) || riscv_cmodel == CM_MEDANY)) |
09cae750 PD |
908 | |
909 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
910 | #define DEFAULT_SIGNED_CHAR 0 | |
911 | ||
912 | #define MOVE_MAX UNITS_PER_WORD | |
913 | #define MAX_MOVE_MAX 8 | |
914 | ||
ecc82a8d AW |
915 | /* The SPARC port says: |
916 | Nonzero if access to memory by bytes is slow and undesirable. | |
917 | For RISC chips, it means that access to memory by bytes is no | |
918 | better than access by words when possible, so grab a whole word | |
919 | and maybe make use of that. */ | |
920 | #define SLOW_BYTE_ACCESS 1 | |
09cae750 | 921 | |
b7ef9225 JW |
922 | /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns |
923 | in the md file instead. */ | |
924 | #define SHIFT_COUNT_TRUNCATED 0 | |
09cae750 | 925 | |
09cae750 PD |
926 | /* Specify the machine mode that pointers have. |
927 | After generation of rtl, the compiler makes no further distinction | |
928 | between pointers and any other objects of this machine mode. */ | |
929 | ||
930 | #define Pmode word_mode | |
931 | ||
a3480aac CM |
932 | /* Specify the machine mode that registers have. */ |
933 | ||
934 | #define Xmode (TARGET_64BIT ? DImode : SImode) | |
935 | ||
09cae750 PD |
936 | /* Give call MEMs SImode since it is the "most permissive" mode |
937 | for both 32-bit and 64-bit targets. */ | |
938 | ||
939 | #define FUNCTION_MODE SImode | |
940 | ||
941 | /* A C expression for the cost of a branch instruction. A value of 2 | |
942 | seems to minimize code size. */ | |
943 | ||
944 | #define BRANCH_COST(speed_p, predictable_p) \ | |
945 | ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost) | |
946 | ||
4f475391 AW |
947 | /* True if the target optimizes short forward branches around integer |
948 | arithmetic instructions into predicated operations, e.g., for | |
949 | conditional-move operations. The macro assumes that all branch | |
950 | instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ) | |
951 | support this feature. The macro further assumes that any integer | |
952 | arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I], | |
953 | SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed | |
954 | counterparts, including C.MV and C.LI) can be in the branch shadow. */ | |
955 | ||
ec217f72 MC |
956 | #define TARGET_SFB_ALU \ |
957 | ((riscv_microarchitecture == sifive_7) \ | |
7c190f93 | 958 | || (riscv_microarchitecture == sifive_p400) \ |
ec217f72 | 959 | || (riscv_microarchitecture == sifive_p600)) |
4f475391 | 960 | |
68b0742a RD |
961 | /* True if the target supports misaligned vector loads and stores. */ |
962 | #define TARGET_VECTOR_MISALIGN_SUPPORTED \ | |
963 | riscv_vector_unaligned_access_p | |
964 | ||
09cae750 PD |
965 | /* Control the assembler format that we output. */ |
966 | ||
967 | /* Output to assembler file text saying following lines | |
968 | may contain character constants, extra white space, comments, etc. */ | |
969 | ||
970 | #ifndef ASM_APP_ON | |
971 | #define ASM_APP_ON " #APP\n" | |
972 | #endif | |
973 | ||
974 | /* Output to assembler file text saying following lines | |
975 | no longer contain unusual constructs. */ | |
976 | ||
977 | #ifndef ASM_APP_OFF | |
978 | #define ASM_APP_OFF " #NO_APP\n" | |
979 | #endif | |
980 | ||
981 | #define REGISTER_NAMES \ | |
982 | { "zero","ra", "sp", "gp", "tp", "t0", "t1", "t2", \ | |
983 | "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \ | |
984 | "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \ | |
985 | "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \ | |
986 | "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \ | |
987 | "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \ | |
988 | "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \ | |
989 | "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \ | |
f6d7ff47 | 990 | "arg", "frame", "vl", "vtype", "vxrm", "frm", "vxsat", "N/A", \ |
31380d4b | 991 | "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \ |
992 | "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \ | |
993 | "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \ | |
994 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ | |
995 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ | |
996 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ | |
997 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",} | |
09cae750 PD |
998 | |
999 | #define ADDITIONAL_REGISTER_NAMES \ | |
1000 | { \ | |
1001 | { "x0", 0 + GP_REG_FIRST }, \ | |
1002 | { "x1", 1 + GP_REG_FIRST }, \ | |
1003 | { "x2", 2 + GP_REG_FIRST }, \ | |
1004 | { "x3", 3 + GP_REG_FIRST }, \ | |
1005 | { "x4", 4 + GP_REG_FIRST }, \ | |
1006 | { "x5", 5 + GP_REG_FIRST }, \ | |
1007 | { "x6", 6 + GP_REG_FIRST }, \ | |
1008 | { "x7", 7 + GP_REG_FIRST }, \ | |
1009 | { "x8", 8 + GP_REG_FIRST }, \ | |
1010 | { "x9", 9 + GP_REG_FIRST }, \ | |
1011 | { "x10", 10 + GP_REG_FIRST }, \ | |
1012 | { "x11", 11 + GP_REG_FIRST }, \ | |
1013 | { "x12", 12 + GP_REG_FIRST }, \ | |
1014 | { "x13", 13 + GP_REG_FIRST }, \ | |
1015 | { "x14", 14 + GP_REG_FIRST }, \ | |
1016 | { "x15", 15 + GP_REG_FIRST }, \ | |
1017 | { "x16", 16 + GP_REG_FIRST }, \ | |
1018 | { "x17", 17 + GP_REG_FIRST }, \ | |
1019 | { "x18", 18 + GP_REG_FIRST }, \ | |
1020 | { "x19", 19 + GP_REG_FIRST }, \ | |
1021 | { "x20", 20 + GP_REG_FIRST }, \ | |
1022 | { "x21", 21 + GP_REG_FIRST }, \ | |
1023 | { "x22", 22 + GP_REG_FIRST }, \ | |
1024 | { "x23", 23 + GP_REG_FIRST }, \ | |
1025 | { "x24", 24 + GP_REG_FIRST }, \ | |
1026 | { "x25", 25 + GP_REG_FIRST }, \ | |
1027 | { "x26", 26 + GP_REG_FIRST }, \ | |
1028 | { "x27", 27 + GP_REG_FIRST }, \ | |
1029 | { "x28", 28 + GP_REG_FIRST }, \ | |
1030 | { "x29", 29 + GP_REG_FIRST }, \ | |
1031 | { "x30", 30 + GP_REG_FIRST }, \ | |
1032 | { "x31", 31 + GP_REG_FIRST }, \ | |
1033 | { "f0", 0 + FP_REG_FIRST }, \ | |
1034 | { "f1", 1 + FP_REG_FIRST }, \ | |
1035 | { "f2", 2 + FP_REG_FIRST }, \ | |
1036 | { "f3", 3 + FP_REG_FIRST }, \ | |
1037 | { "f4", 4 + FP_REG_FIRST }, \ | |
1038 | { "f5", 5 + FP_REG_FIRST }, \ | |
1039 | { "f6", 6 + FP_REG_FIRST }, \ | |
1040 | { "f7", 7 + FP_REG_FIRST }, \ | |
1041 | { "f8", 8 + FP_REG_FIRST }, \ | |
1042 | { "f9", 9 + FP_REG_FIRST }, \ | |
1043 | { "f10", 10 + FP_REG_FIRST }, \ | |
1044 | { "f11", 11 + FP_REG_FIRST }, \ | |
1045 | { "f12", 12 + FP_REG_FIRST }, \ | |
1046 | { "f13", 13 + FP_REG_FIRST }, \ | |
1047 | { "f14", 14 + FP_REG_FIRST }, \ | |
1048 | { "f15", 15 + FP_REG_FIRST }, \ | |
1049 | { "f16", 16 + FP_REG_FIRST }, \ | |
1050 | { "f17", 17 + FP_REG_FIRST }, \ | |
1051 | { "f18", 18 + FP_REG_FIRST }, \ | |
1052 | { "f19", 19 + FP_REG_FIRST }, \ | |
1053 | { "f20", 20 + FP_REG_FIRST }, \ | |
1054 | { "f21", 21 + FP_REG_FIRST }, \ | |
1055 | { "f22", 22 + FP_REG_FIRST }, \ | |
1056 | { "f23", 23 + FP_REG_FIRST }, \ | |
1057 | { "f24", 24 + FP_REG_FIRST }, \ | |
1058 | { "f25", 25 + FP_REG_FIRST }, \ | |
1059 | { "f26", 26 + FP_REG_FIRST }, \ | |
1060 | { "f27", 27 + FP_REG_FIRST }, \ | |
1061 | { "f28", 28 + FP_REG_FIRST }, \ | |
1062 | { "f29", 29 + FP_REG_FIRST }, \ | |
1063 | { "f30", 30 + FP_REG_FIRST }, \ | |
1064 | { "f31", 31 + FP_REG_FIRST }, \ | |
1065 | } | |
1066 | ||
1067 | /* Globalizing directive for a label. */ | |
1068 | #define GLOBAL_ASM_OP "\t.globl\t" | |
1069 | ||
1070 | /* This is how to store into the string LABEL | |
1071 | the symbol_ref name of an internal numbered label where | |
1072 | PREFIX is the class of label and NUM is the number within the class. | |
1073 | This is suitable for output with `assemble_name'. */ | |
1074 | ||
1075 | #undef ASM_GENERATE_INTERNAL_LABEL | |
1076 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
1077 | sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) | |
1078 | ||
1079 | /* This is how to output an element of a case-vector that is absolute. */ | |
1080 | ||
1081 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
1082 | fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE) | |
1083 | ||
1084 | /* This is how to output an element of a PIC case-vector. */ | |
1085 | ||
1086 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
1087 | fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ | |
1088 | LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL) | |
1089 | ||
1090 | /* This is how to output an assembler line | |
1091 | that says to advance the location counter | |
1092 | to a multiple of 2**LOG bytes. */ | |
1093 | ||
1094 | #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ | |
1095 | fprintf (STREAM, "\t.align\t%d\n", (LOG)) | |
1096 | ||
1097 | /* Define the strings to put out for each section in the object file. */ | |
1098 | #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ | |
1099 | #define DATA_SECTION_ASM_OP "\t.data" /* large data */ | |
1100 | #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" | |
1101 | #define BSS_SECTION_ASM_OP "\t.bss" | |
1102 | #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits" | |
1103 | #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits" | |
1104 | ||
1105 | #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ | |
1106 | do \ | |
1107 | { \ | |
1108 | fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ | |
1109 | reg_names[STACK_POINTER_REGNUM], \ | |
1110 | reg_names[STACK_POINTER_REGNUM], \ | |
1111 | TARGET_64BIT ? "sd" : "sw", \ | |
1112 | reg_names[REGNO], \ | |
1113 | reg_names[STACK_POINTER_REGNUM]); \ | |
1114 | } \ | |
1115 | while (0) | |
1116 | ||
1117 | #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ | |
1118 | do \ | |
1119 | { \ | |
1120 | fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \ | |
1121 | TARGET_64BIT ? "ld" : "lw", \ | |
1122 | reg_names[REGNO], \ | |
1123 | reg_names[STACK_POINTER_REGNUM], \ | |
1124 | reg_names[STACK_POINTER_REGNUM], \ | |
1125 | reg_names[STACK_POINTER_REGNUM]); \ | |
1126 | } \ | |
1127 | while (0) | |
1128 | ||
1129 | #define ASM_COMMENT_START "#" | |
1130 | ||
4abcc500 LD |
1131 | /* Add output .variant_cc directive for specific function definition. */ |
1132 | #undef ASM_DECLARE_FUNCTION_NAME | |
1133 | #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ | |
1134 | riscv_declare_function_name (STR, NAME, DECL) | |
1135 | ||
5f110561 KC |
1136 | #undef ASM_DECLARE_FUNCTION_SIZE |
1137 | #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ | |
1138 | riscv_declare_function_size (FILE, FNAME, DECL) | |
1139 | ||
4abcc500 LD |
1140 | /* Add output .variant_cc directive for specific alias definition. */ |
1141 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
1142 | #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ | |
1143 | riscv_asm_output_alias (STR, DECL, TARGET) | |
1144 | ||
1145 | /* Add output .variant_cc directive for specific extern function. */ | |
1146 | #undef ASM_OUTPUT_EXTERNAL | |
1147 | #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ | |
1148 | riscv_asm_output_external (STR, DECL, NAME) | |
1149 | ||
09cae750 PD |
1150 | #undef SIZE_TYPE |
1151 | #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") | |
1152 | ||
1153 | #undef PTRDIFF_TYPE | |
1154 | #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") | |
1155 | ||
76715c32 | 1156 | /* The maximum number of bytes copied by one iteration of a cpymemsi loop. */ |
6ed01e6b AW |
1157 | |
1158 | #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4) | |
1159 | ||
1160 | /* The maximum number of bytes that can be copied by a straight-line | |
76715c32 | 1161 | cpymemsi implementation. */ |
09cae750 | 1162 | |
6ed01e6b AW |
1163 | #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3) |
1164 | ||
1165 | /* If a memory-to-memory move would take MOVE_RATIO or more simple | |
76715c32 | 1166 | move-instruction pairs, we will do a cpymem or libcall instead. |
6ed01e6b AW |
1167 | Do not use move_by_pieces at all when strict alignment is not |
1168 | in effect but the target has slow unaligned accesses; in this | |
76715c32 | 1169 | case, cpymem or libcall is more efficient. */ |
6ed01e6b AW |
1170 | |
1171 | #define MOVE_RATIO(speed) \ | |
fb5621b1 | 1172 | (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 : \ |
6ed01e6b AW |
1173 | (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD : \ |
1174 | CLEAR_RATIO (speed) / 2) | |
09cae750 PD |
1175 | |
1176 | /* For CLEAR_RATIO, when optimizing for size, give a better estimate | |
1177 | of the length of a memset call, but use the default otherwise. */ | |
1178 | ||
1179 | #define CLEAR_RATIO(speed) ((speed) ? 16 : 6) | |
1180 | ||
1181 | /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
1182 | optimizing for size adjust the ratio to account for the overhead of | |
1183 | loading the constant and replicating it across the word. */ | |
1184 | ||
1185 | #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2)) | |
1186 | ||
1187 | #ifndef USED_FOR_TARGET | |
1188 | extern const enum reg_class riscv_regno_to_class[]; | |
fb5621b1 | 1189 | extern bool riscv_slow_unaligned_access_p; |
68b0742a | 1190 | extern bool riscv_vector_unaligned_access_p; |
6e23440b | 1191 | extern bool riscv_user_wants_strict_align; |
fb5621b1 | 1192 | extern unsigned riscv_stack_boundary; |
3496ca4e | 1193 | extern unsigned riscv_bytes_per_vector_chunk; |
1194 | extern poly_uint16 riscv_vector_chunks; | |
7e924ba3 | 1195 | extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); |
879c52c9 | 1196 | extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int); |
247cacc9 | 1197 | extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int); |
3a982e07 | 1198 | extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int); |
59a869d7 MC |
1199 | extern bool is_zicfiss_p (); |
1200 | extern bool is_zicfilp_p (); | |
dc76aa0e | 1201 | extern bool need_shadow_stack_push_pop_p (); |
3496ca4e | 1202 | /* The number of bits and bytes in a RVV vector. */ |
1203 | #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8)) | |
1204 | #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk)) | |
09cae750 PD |
1205 | #endif |
1206 | ||
1207 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
1208 | (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) | |
1209 | ||
1210 | #define XLEN_SPEC \ | |
1211 | "%{march=rv32*:32}" \ | |
1212 | "%{march=rv64*:64}" \ | |
1213 | ||
1214 | #define ABI_SPEC \ | |
1215 | "%{mabi=ilp32:ilp32}" \ | |
09baee1a | 1216 | "%{mabi=ilp32e:ilp32e}" \ |
09cae750 PD |
1217 | "%{mabi=ilp32f:ilp32f}" \ |
1218 | "%{mabi=ilp32d:ilp32d}" \ | |
1219 | "%{mabi=lp64:lp64}" \ | |
006e90e1 | 1220 | "%{mabi=lp64e:lp64e}" \ |
09cae750 PD |
1221 | "%{mabi=lp64f:lp64f}" \ |
1222 | "%{mabi=lp64d:lp64d}" \ | |
1223 | ||
09cae750 PD |
1224 | /* ISA constants needed for code generation. */ |
1225 | #define OPCODE_LW 0x2003 | |
1226 | #define OPCODE_LD 0x3003 | |
1227 | #define OPCODE_AUIPC 0x17 | |
1228 | #define OPCODE_JALR 0x67 | |
1229 | #define OPCODE_LUI 0x37 | |
1230 | #define OPCODE_ADDI 0x13 | |
1231 | #define SHIFT_RD 7 | |
1232 | #define SHIFT_RS1 15 | |
1233 | #define SHIFT_IMM 20 | |
1234 | #define IMM_BITS 12 | |
de6320a8 | 1235 | #define C_S_BITS 5 |
10789329 | 1236 | #define C_SxSP_BITS 6 |
09cae750 PD |
1237 | |
1238 | #define IMM_REACH (1LL << IMM_BITS) | |
1239 | #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1)) | |
1240 | #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) | |
1241 | ||
10789329 JW |
1242 | #define SWSP_REACH (4LL << C_SxSP_BITS) |
1243 | #define SDSP_REACH (8LL << C_SxSP_BITS) | |
1244 | ||
de6320a8 CB |
1245 | /* This is the maximum value that can be represented in a compressed load/store |
1246 | offset (an unsigned 5-bit value scaled by 4). */ | |
f95bd50b | 1247 | #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3) |
de6320a8 | 1248 | |
e53b6e56 | 1249 | /* Called from RISCV_REORG, this is defined in riscv-sr.cc. */ |
e18a6d14 AB |
1250 | |
1251 | extern void riscv_remove_unneeded_save_restore_calls (void); | |
1252 | ||
e0a5b313 KC |
1253 | #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO) |
1254 | ||
16f7fcad PT |
1255 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
1256 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) | |
1257 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
1258 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) | |
1259 | ||
ef85d150 VG |
1260 | #define TARGET_SUPPORTS_WIDE_INT 1 |
1261 | ||
7d935cdd JZZ |
1262 | #define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas () |
1263 | ||
f556cd8b JZZ |
1264 | #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE) |
1265 | ||
89367e79 KC |
1266 | #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */) |
1267 | ||
1268 | #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \ | |
1269 | ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO) | |
1270 | ||
3365956d PL |
1271 | /* Like s390, riscv also defined this macro for the vector comparision. Then |
1272 | the simplify-rtx relational_result will canonicalize the result to the | |
1273 | CONST1_RTX for the simplification. */ | |
1274 | #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) | |
1275 | ||
e682d300 JZ |
1276 | /* Mode switching (Lazy code motion) for RVV rounding mode instructions. */ |
1277 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR) | |
4cede0de | 1278 | #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE} |
e682d300 | 1279 | |
0f40e59f KC |
1280 | /* The size difference between different RVV modes can be up to 64 times. |
1281 | e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64]. */ | |
1282 | #define MAX_POLY_VARIANT 64 | |
1283 | ||
2d65622f CM |
1284 | #define HAVE_POST_MODIFY_DISP TARGET_XTHEADMEMIDX |
1285 | #define HAVE_PRE_MODIFY_DISP TARGET_XTHEADMEMIDX | |
1286 | ||
97069657 TI |
1287 | /* Check TLS Descriptors mechanism is selected. */ |
1288 | #define TARGET_TLSDESC (riscv_tls_dialect == TLS_DESCRIPTORS) | |
1289 | ||
b82d173d RMZ |
1290 | /* This value is the amount of bytes a caller is allowed to drop the stack |
1291 | before probing has to be done for stack clash protection. */ | |
1292 | #define STACK_CLASH_CALLER_GUARD 1024 | |
1293 | ||
1294 | /* This value controls how many pages we manually unroll the loop for when | |
1295 | generating stack clash probes. */ | |
1296 | #define STACK_CLASH_MAX_UNROLL_PAGES 4 | |
1297 | ||
180ede35 RMZ |
1298 | /* This value represents the minimum amount of bytes we expect the function's |
1299 | outgoing arguments to be when stack-clash is enabled. */ | |
1300 | #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8 | |
1301 | ||
1302 | /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the | |
1303 | outgoing arguments if stack clash protection is enabled. This is essential | |
1304 | as the extra arg space allows us to skip a check in alloca. */ | |
1305 | #undef STACK_DYNAMIC_OFFSET | |
1306 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
1307 | ((flag_stack_clash_protection \ | |
1308 | && cfun->calls_alloca \ | |
1309 | && known_lt (crtl->outgoing_args_size, \ | |
1310 | STACK_CLASH_MIN_BYTES_OUTGOING_ARGS)) \ | |
1311 | ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS, \ | |
1312 | STACK_BOUNDARY / BITS_PER_UNIT) \ | |
1313 | : (crtl->outgoing_args_size + STACK_POINTER_OFFSET)) | |
1314 | ||
9bf0dbe6 YC |
1315 | /* According to the RISC-V C API, the arch string may contains ','. To avoid |
1316 | the conflict with the default separator, we choose '#' as the separator for | |
1317 | the target attribute. */ | |
1318 | #define TARGET_CLONES_ATTR_SEPARATOR '#' | |
1319 | ||
bd975bd1 YC |
1320 | #define TARGET_HAS_FMV_TARGET_ATTRIBUTE 0 |
1321 | ||
09cae750 | 1322 | #endif /* ! GCC_RISCV_H */ |