]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/riscv/vector-iterators.md
projects / thirdparty / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
RISC-V: Support VLS floating-point extend/truncate
[thirdparty/gcc.git] / gcc / config / riscv / vector-iterators.md
CommitLineData
f556cd8b 1;; Iterators for RISC-V 'V' Extension for GNU compiler.
aeee4812 2;; Copyright (C) 2022-2023 Free Software Foundation, Inc.
f556cd8b
JZZ		 3;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
4
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11
12;; GCC is distributed in the hope that it will be useful,
13;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15;; GNU General Public License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
6c9bcb6c
JZZ		 21(define_c_enum "unspec" [
22 UNSPEC_VSETVL
23 UNSPEC_VUNDEF
24 UNSPEC_VPREDICATE
25 UNSPEC_VLMAX
6313b045 26 UNSPEC_UNIT_STRIDED
6c9bcb6c
JZZ		 27 UNSPEC_STRIDED
28
29 ;; It's used to specify ordered/unorderd operation.
30 UNSPEC_ORDERED
31 UNSPEC_UNORDERED
8340bbad
JZZ		 32
33 ;; vmulh/vmulhu/vmulhsu
34 UNSPEC_VMULHS
35 UNSPEC_VMULHU
36 UNSPEC_VMULHSU
cb44a16d
JZZ		 37
38 UNSPEC_VADC
39 UNSPEC_VSBC
dca23bf0
JZZ		 40 UNSPEC_VMADC
41 UNSPEC_VMSBC
42 UNSPEC_OVERFLOW
e09418f2
JZZ		 43
44 UNSPEC_VNCLIP
45 UNSPEC_VNCLIPU
46 UNSPEC_VSSRL
47 UNSPEC_VSSRA
48 UNSPEC_VAADDU
49 UNSPEC_VAADD
50 UNSPEC_VASUBU
51 UNSPEC_VASUB
52 UNSPEC_VSMUL
1ed93bc7
JZZ		 53
54 UNSPEC_VMSBF
55 UNSPEC_VMSIF
56 UNSPEC_VMSOF
57 UNSPEC_VIOTA
dc244cdc
JZZ		 58
59 UNSPEC_VFRSQRT7
60 UNSPEC_VFREC7
61 UNSPEC_VFCLASS
62
63 UNSPEC_VCOPYSIGN
dc244cdc
JZZ		 64 UNSPEC_VXORSIGN
65
66 UNSPEC_VFCVT
67 UNSPEC_UNSIGNED_VFCVT
68 UNSPEC_ROD
c878c658 69
1bff101b
JZZ		 70 UNSPEC_VSLIDEUP
71 UNSPEC_VSLIDEDOWN
72 UNSPEC_VSLIDE1UP
73 UNSPEC_VSLIDE1DOWN
74 UNSPEC_VFSLIDE1UP
75 UNSPEC_VFSLIDE1DOWN
76 UNSPEC_VRGATHER
77 UNSPEC_VRGATHEREI16
78 UNSPEC_VCOMPRESS
60bd33bc 79 UNSPEC_VLEFF
4eae76d1 80 UNSPEC_MODIFY_VL
3e37e823
PL		 81
82 UNSPEC_VFFMA
6223ea76
LD		 83
84 ;; Integer and Float Reduction
85 UNSPEC_REDUC
86 UNSPEC_REDUC_SUM
87 UNSPEC_REDUC_SUM_ORDERED
88 UNSPEC_REDUC_SUM_UNORDERED
89 UNSPEC_REDUC_MAXU
90 UNSPEC_REDUC_MAX
91 UNSPEC_REDUC_MINU
92 UNSPEC_REDUC_MIN
93 UNSPEC_REDUC_AND
94 UNSPEC_REDUC_OR
95 UNSPEC_REDUC_XOR
96
97 UNSPEC_WREDUC_SUM
98 UNSPEC_WREDUC_SUMU
99 UNSPEC_WREDUC_SUM_ORDERED
100 UNSPEC_WREDUC_SUM_UNORDERED
45dd1d91 101])
e714af12 102
45dd1d91
PL		 103(define_c_enum "unspecv" [
104 UNSPECV_FRM_RESTORE_EXIT
6c9bcb6c
JZZ		 105])
106
f556cd8b 107(define_mode_iterator V [
879c52c9
JZ		 108 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
109
110 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
111
112 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
113 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
114 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
115
116 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
117
118 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
119 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
120
121 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
122 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
123
124 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
125 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
f556cd8b
JZZ		 126])
127
33b153ff
JZ		 128(define_mode_iterator V_VLS [
129 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
130
131 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
132
133 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
134 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
135 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
136
137 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
138
139 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
140 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
141
142 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
143 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
144
145 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
146 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
147
148 ;; VLS modes.
149 (V1QI "TARGET_VECTOR_VLS")
150 (V2QI "TARGET_VECTOR_VLS")
151 (V4QI "TARGET_VECTOR_VLS")
152 (V8QI "TARGET_VECTOR_VLS")
153 (V16QI "TARGET_VECTOR_VLS")
154 (V32QI "TARGET_VECTOR_VLS")
155 (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
156 (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
157 (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
158 (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
159 (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
160 (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
161 (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
162 (V1HI "TARGET_VECTOR_VLS")
163 (V2HI "TARGET_VECTOR_VLS")
164 (V4HI "TARGET_VECTOR_VLS")
165 (V8HI "TARGET_VECTOR_VLS")
166 (V16HI "TARGET_VECTOR_VLS")
167 (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
168 (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
169 (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
170 (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
171 (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
172 (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
173 (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
174 (V1SI "TARGET_VECTOR_VLS")
175 (V2SI "TARGET_VECTOR_VLS")
176 (V4SI "TARGET_VECTOR_VLS")
177 (V8SI "TARGET_VECTOR_VLS")
178 (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
179 (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
180 (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
181 (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
182 (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
183 (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
184 (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
185 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
186 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
187 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
188 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
189 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
190 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
191 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
192 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
193 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
194 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
195 (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
196 (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
197 (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
198 (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
199 (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
200 (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
201 (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
202 (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
203 (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
204 (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
205 (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
206 (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
207 (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
208 (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
209 (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
210 (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
211 (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
212 (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
213 (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
214 (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
215 (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
216 (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
217 (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
218 (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
219 (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
220 (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
221 (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
222 (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
223 (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
224 (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
225 (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
226 (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
227 (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
228])
229
ab7bb445 230(define_mode_iterator VEEWEXT2 [
879c52c9
JZ		 231 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
232
233 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
234 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
235 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
236
237 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
238
239 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
240 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
241
242 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
243 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
244
245 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
246 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
ab7bb445
JZZ		 247])
248
249(define_mode_iterator VEEWEXT4 [
879c52c9
JZ		 250 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
251
252 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
253 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
254
255 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
256 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
257
258 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
259 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
ab7bb445
JZZ		 260])
261
262(define_mode_iterator VEEWEXT8 [
879c52c9
JZ		 263 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
264 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
265
266 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
267 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
ab7bb445
JZZ		 268])
269
270(define_mode_iterator VEEWTRUNC2 [
879c52c9
JZ		 271 RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
272
273 RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
274
275 (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
276 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
277 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
278
279 RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
280
281 (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
282 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
ab7bb445
JZZ		 283])
284
285(define_mode_iterator VEEWTRUNC4 [
879c52c9
JZ		 286 RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
287
288 RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
289
290 (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
291 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
ab7bb445
JZZ		 292])
293
294(define_mode_iterator VEEWTRUNC8 [
879c52c9 295 RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
ab7bb445
JZZ		 296])
297
7caa1ae5 298(define_mode_iterator VLMULEXT2 [
879c52c9
JZ		 299 RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
300
301 RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
302
303 (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
304 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
305 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
306
307 RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
308
309 (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
310 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
311
312 (RVVM4DI "TARGET_VECTOR_ELEN_64") (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
313
314 (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
7caa1ae5
JZZ		 315])
316
317(define_mode_iterator VLMULEXT4 [
879c52c9
JZ		 318 RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
319
320 RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
321
322 (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
323 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
324
325 RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
326
327 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
328
329 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
330
331 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
7caa1ae5
JZZ		 332])
333
334(define_mode_iterator VLMULEXT8 [
879c52c9
JZ		 335 RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
336
337 RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
338
339 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
340 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
341
342 RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
343
344 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
345
346 (RVVM1DI "TARGET_VECTOR_ELEN_64")
347
348 (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
7caa1ae5
JZZ		 349])
350
351(define_mode_iterator VLMULEXT16 [
879c52c9
JZ		 352 RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
353
354 RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
355
356 (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
357
358 (RVVMF2SI "TARGET_MIN_VLEN > 32")
359
360 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
7caa1ae5
JZZ		 361])
362
363(define_mode_iterator VLMULEXT32 [
879c52c9
JZ		 364 RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
365
366 (RVVMF4HI "TARGET_MIN_VLEN > 32")
367
368 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
7caa1ae5
JZZ		 369])
370
371(define_mode_iterator VLMULEXT64 [
879c52c9 372 (RVVMF8QI "TARGET_MIN_VLEN > 32")
7caa1ae5
JZZ		 373])
374
1bff101b 375(define_mode_iterator VEI16 [
879c52c9
JZ		 376 RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
377
378 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
379
380 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
381 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
382 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
383
384 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
385
386 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
387 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
388
389 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
390 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
391
392 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
393 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
d05aac04
JZ		 394
395 (V1QI "TARGET_VECTOR_VLS")
396 (V2QI "TARGET_VECTOR_VLS")
397 (V4QI "TARGET_VECTOR_VLS")
398 (V8QI "TARGET_VECTOR_VLS")
399 (V16QI "TARGET_VECTOR_VLS")
400 (V32QI "TARGET_VECTOR_VLS")
401 (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
402 (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
403 (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
404 (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
405 (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
406 (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
407 (V1HI "TARGET_VECTOR_VLS")
408 (V2HI "TARGET_VECTOR_VLS")
409 (V4HI "TARGET_VECTOR_VLS")
410 (V8HI "TARGET_VECTOR_VLS")
411 (V16HI "TARGET_VECTOR_VLS")
412 (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
413 (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
414 (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
415 (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
416 (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
417 (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
418 (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
419 (V1SI "TARGET_VECTOR_VLS")
420 (V2SI "TARGET_VECTOR_VLS")
421 (V4SI "TARGET_VECTOR_VLS")
422 (V8SI "TARGET_VECTOR_VLS")
423 (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
424 (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
425 (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
426 (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
427 (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
428 (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
429 (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
430 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
431 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
432 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
433 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
434 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
435 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
436 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
437 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
438 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
439 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
440 (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
441 (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
442 (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
443 (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
444 (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
445 (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
446 (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
447 (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
448 (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
449 (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
450 (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
451 (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
452 (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
453 (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
454 (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
455 (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
456 (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
457 (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
458 (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
459 (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
460 (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
461 (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
462 (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
463 (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
464 (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
465 (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
466 (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
467 (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
468 (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
469 (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
470 (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
471 (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
472 (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
1bff101b
JZZ		 473])
474
2a937fb5 475(define_mode_iterator VI [
879c52c9 476 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
9fdea28d 477
879c52c9
JZ		 478 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
479
480 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
481
482 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
483 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
9fdea28d
JZ		 484])
485
33b153ff
JZ		 486(define_mode_iterator V_VLSI [
487 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
488
489 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
490
491 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
492
493 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
494 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
495
496 (V1QI "TARGET_VECTOR_VLS")
497 (V2QI "TARGET_VECTOR_VLS")
498 (V4QI "TARGET_VECTOR_VLS")
499 (V8QI "TARGET_VECTOR_VLS")
500 (V16QI "TARGET_VECTOR_VLS")
501 (V32QI "TARGET_VECTOR_VLS")
502 (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
503 (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
504 (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
505 (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
506 (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
507 (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
508 (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
509 (V1HI "TARGET_VECTOR_VLS")
510 (V2HI "TARGET_VECTOR_VLS")
511 (V4HI "TARGET_VECTOR_VLS")
512 (V8HI "TARGET_VECTOR_VLS")
513 (V16HI "TARGET_VECTOR_VLS")
514 (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
515 (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
516 (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
517 (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
518 (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
519 (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
520 (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
521 (V1SI "TARGET_VECTOR_VLS")
522 (V2SI "TARGET_VECTOR_VLS")
523 (V4SI "TARGET_VECTOR_VLS")
524 (V8SI "TARGET_VECTOR_VLS")
525 (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
526 (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
527 (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
528 (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
529 (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
530 (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
531 (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
532 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
533 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
534 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
535 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
536 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
537 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
538 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
539 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
540 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
541 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
542])
543
ed60ffd8
PL		 544(define_mode_iterator V_VLSF [
545 (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH")
546 (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
547 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
548 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
549 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
550 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
551 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
552
df9a2538
JZ		 553 (V1HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
554 (V2HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
555 (V4HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
556 (V8HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
557 (V16HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
558 (V32HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
559 (V64HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
560 (V128HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
561 (V256HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
562 (V512HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
563 (V1024HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
564 (V2048HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096")
ed60ffd8
PL		 565 (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
566 (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
567 (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
568 (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
569 (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
570 (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
571 (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
572 (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
573 (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
574 (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
575 (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
576 (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
577 (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
578 (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
579 (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
580 (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
581 (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
582 (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
583 (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
584 (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
585 (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
586])
587
201c6c32 588(define_mode_iterator VF_ZVFHMIN [
879c52c9
JZ		 589 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
590 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
591 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
592
593 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
594 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
595
596 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
597 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
47ffabaf
RD		 598])
599
33b153ff
JZ		 600(define_mode_iterator V_VLSF_ZVFHMIN [
601 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
602 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
603 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
604
605 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
606 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
607
608 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
609 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
610
6bdbf172 611 (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
33b153ff
JZ		 612 (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
613 (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
614 (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
615 (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
616 (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
617 (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
618 (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
619 (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
620 (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
621 (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
622 (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
6bdbf172 623 (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
33b153ff
JZ		 624 (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
625 (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
626 (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
627 (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
628 (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
629 (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
630 (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
631 (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
632 (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
633 (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
6bdbf172 634 (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
33b153ff
JZ		 635 (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
636 (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
637 (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
638 (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
639 (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
640 (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
641 (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
642 (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
643 (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
644])
645
47ffabaf
RD		 646;; This iterator is the same as above but with TARGET_VECTOR_ELEN_FP_16
647;; changed to TARGET_ZVFH. TARGET_VECTOR_ELEN_FP_16 is also true for
201c6c32
RD		 648;; TARGET_ZVFHMIN while we actually want to disable all instructions apart
649;; from load, store and convert for it.
650;; It is not enough to set the "enabled" attribute to false
651;; since this will only disable insn alternatives in reload but still
652;; allow the instruction and mode to be matched during combine et al.
653(define_mode_iterator VF [
879c52c9
JZ		 654 (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH")
655 (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
656 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
657
658 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
659 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
660
661 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
662 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
9fdea28d
JZ		 663])
664
8340bbad 665(define_mode_iterator VFULLI [
879c52c9
JZ		 666 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
667
668 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
669
670 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
671
672 (RVVM8DI "TARGET_FULL_V") (RVVM4DI "TARGET_FULL_V") (RVVM2DI "TARGET_FULL_V") (RVVM1DI "TARGET_FULL_V")
8340bbad
JZZ		 673])
674
9b24611a 675(define_mode_iterator VI_QH [
879c52c9
JZ		 676 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
677
678 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
9b24611a
RD		 679])
680
a035d133 681(define_mode_iterator VI_QHS [
879c52c9
JZ		 682 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
683
684 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
685
686 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
a035d133
JZZ		 687])
688
68cb873f
LD		 689(define_mode_iterator VI_QHS_NO_M8 [
690 RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
691
692 RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
693
694 RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
695])
696
14c481f7
LD		 697(define_mode_iterator VF_HS [
698 (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH")
699 (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
700 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
701
702 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
703 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
704])
705
68cb873f
LD		 706(define_mode_iterator VF_HS_NO_M8 [
707 (RVVM4HF "TARGET_ZVFH")
708 (RVVM2HF "TARGET_ZVFH")
709 (RVVM1HF "TARGET_ZVFH")
710 (RVVMF2HF "TARGET_ZVFH")
711 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
712 (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
713 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
714 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
715 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
716])
717
718(define_mode_iterator VF_HS_M8 [
719 (RVVM8HF "TARGET_ZVFH")
720 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32")
721])
722
9cba4fce
JZ		 723(define_mode_iterator V_VLSI_QHS [
724 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
725
726 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
727
728 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
729
730 (V1QI "TARGET_VECTOR_VLS")
731 (V2QI "TARGET_VECTOR_VLS")
732 (V4QI "TARGET_VECTOR_VLS")
733 (V8QI "TARGET_VECTOR_VLS")
734 (V16QI "TARGET_VECTOR_VLS")
735 (V32QI "TARGET_VECTOR_VLS")
736 (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
737 (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
738 (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
739 (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
740 (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
741 (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
742 (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
743 (V1HI "TARGET_VECTOR_VLS")
744 (V2HI "TARGET_VECTOR_VLS")
745 (V4HI "TARGET_VECTOR_VLS")
746 (V8HI "TARGET_VECTOR_VLS")
747 (V16HI "TARGET_VECTOR_VLS")
748 (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
749 (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
750 (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
751 (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
752 (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
753 (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
754 (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
755 (V1SI "TARGET_VECTOR_VLS")
756 (V2SI "TARGET_VECTOR_VLS")
757 (V4SI "TARGET_VECTOR_VLS")
758 (V8SI "TARGET_VECTOR_VLS")
759 (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
760 (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
761 (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
762 (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
763 (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
764 (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
765 (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
766])
767
a035d133 768(define_mode_iterator VI_D [
879c52c9
JZ		 769 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
770 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
a035d133
JZZ		 771])
772
33b153ff
JZ		 773(define_mode_iterator V_VLSI_D [
774 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
775 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
776
d05aac04 777 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
33b153ff
JZ		 778 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
779 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
780 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
781 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
782 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
783 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
784 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
785 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
786 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
787])
788
8340bbad 789(define_mode_iterator VFULLI_D [
879c52c9
JZ		 790 (RVVM8DI "TARGET_FULL_V") (RVVM4DI "TARGET_FULL_V")
791 (RVVM2DI "TARGET_FULL_V") (RVVM1DI "TARGET_FULL_V")
8340bbad
JZZ		 792])
793
879c52c9
JZ		 794(define_mode_iterator RATIO64 [
795 (RVVMF8QI "TARGET_MIN_VLEN > 32")
796 (RVVMF4HI "TARGET_MIN_VLEN > 32")
797 (RVVMF2SI "TARGET_MIN_VLEN > 32")
798 (RVVM1DI "TARGET_VECTOR_ELEN_64")
799 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
800 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
801 (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
6c9bcb6c
JZZ		 802])
803
879c52c9
JZ		 804(define_mode_iterator RATIO32 [
805 RVVMF4QI
806 RVVMF2HI
807 RVVM1SI
808 (RVVM2DI "TARGET_VECTOR_ELEN_64")
809 (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
810 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
811 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64")
6c9bcb6c
JZZ		 812])
813
879c52c9
JZ		 814(define_mode_iterator RATIO16 [
815 RVVMF2QI
816 RVVM1HI
817 RVVM2SI
818 (RVVM4DI "TARGET_VECTOR_ELEN_64")
819 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16")
820 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
821 (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
6c9bcb6c
JZZ		 822])
823
879c52c9
JZ		 824(define_mode_iterator RATIO8 [
825 RVVM1QI
826 RVVM2HI
827 RVVM4SI
828 (RVVM8DI "TARGET_VECTOR_ELEN_64")
829 (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
830 (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
831 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64")
6c9bcb6c
JZZ		 832])
833
879c52c9
JZ		 834(define_mode_iterator RATIO4 [
835 RVVM2QI
836 RVVM4HI
837 RVVM8SI
838 (RVVM4HF "TARGET_VECTOR_ELEN_FP_16")
839 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32")
6c9bcb6c
JZZ		 840])
841
879c52c9
JZ		 842(define_mode_iterator RATIO2 [
843 RVVM4QI
844 RVVM8HI
845 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16")
6c9bcb6c
JZZ		 846])
847
879c52c9
JZ		 848(define_mode_iterator RATIO1 [
849 RVVM8QI
9fdea28d
JZ		 850])
851
879c52c9
JZ		 852(define_mode_iterator RATIO64I [
853 (RVVMF8QI "TARGET_MIN_VLEN > 32")
854 (RVVMF4HI "TARGET_MIN_VLEN > 32")
855 (RVVMF2SI "TARGET_MIN_VLEN > 32")
856 (RVVM1DI "TARGET_VECTOR_ELEN_64")
6c9bcb6c
JZZ		 857])
858
879c52c9
JZ		 859(define_mode_iterator RATIO32I [
860 RVVMF4QI
861 RVVMF2HI
862 RVVM1SI
863 (RVVM2DI "TARGET_VECTOR_ELEN_64")
6c9bcb6c
JZZ		 864])
865
879c52c9
JZ		 866(define_mode_iterator RATIO16I [
867 RVVMF2QI
868 RVVM1HI
869 RVVM2SI
870 (RVVM4DI "TARGET_VECTOR_ELEN_64")
6c9bcb6c
JZZ		 871])
872
879c52c9
JZ		 873(define_mode_iterator RATIO8I [
874 RVVM1QI
875 RVVM2HI
876 RVVM4SI
877 (RVVM8DI "TARGET_VECTOR_ELEN_64")
6c9bcb6c
JZZ		 878])
879
879c52c9
JZ		 880(define_mode_iterator RATIO4I [
881 RVVM2QI
882 RVVM4HI
883 RVVM8SI
6c9bcb6c
JZZ		 884])
885
879c52c9
JZ		 886(define_mode_iterator RATIO2I [
887 RVVM4QI
888 RVVM8HI
6c9bcb6c
JZZ		 889])
890
879c52c9
JZ		 891(define_mode_iterator V_WHOLE [
892 RVVM8QI RVVM4QI RVVM2QI RVVM1QI
9fdea28d 893
879c52c9 894 RVVM8HI RVVM4HI RVVM2HI RVVM1HI
6c9bcb6c 895
879c52c9
JZ		 896 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16")
897 (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16")
898
899 RVVM8SI RVVM4SI RVVM2SI RVVM1SI
900
901 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
902 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
903
904 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
905 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
906
907 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
908 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
5576518a
JZZ		 909])
910
911(define_mode_iterator V_FRACT [
879c52c9 912 RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
cb33116a 913
879c52c9 914 RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
cb33116a 915
879c52c9
JZ		 916 (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
917
918 (RVVMF2SI "TARGET_MIN_VLEN > 32")
919
920 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
5576518a
JZZ		 921])
922
f556cd8b 923(define_mode_iterator VB [
879c52c9 924 (RVVMF64BI "TARGET_MIN_VLEN > 32") RVVMF32BI RVVMF16BI RVVMF8BI RVVMF4BI RVVMF2BI RVVM1BI
f556cd8b
JZZ		 925])
926
6aba1fa7
JZ		 927(define_mode_iterator VB_VLS [
928 (RVVMF64BI "TARGET_MIN_VLEN > 32") RVVMF32BI RVVMF16BI RVVMF8BI RVVMF4BI RVVMF2BI RVVM1BI
929 (V1BI "TARGET_VECTOR_VLS")
930 (V2BI "TARGET_VECTOR_VLS")
931 (V4BI "TARGET_VECTOR_VLS")
932 (V8BI "TARGET_VECTOR_VLS")
933 (V16BI "TARGET_VECTOR_VLS")
934 (V32BI "TARGET_VECTOR_VLS")
935 (V64BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
936 (V128BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
937 (V256BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
938 (V512BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
939 (V1024BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
940 (V2048BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
941 (V4096BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
942])
943
99fa5d94 944(define_mode_iterator VWEXTI [
879c52c9
JZ		 945 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
946
947 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
948
949 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
950 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
bea89f78
JZ		 951
952 (V1HI "TARGET_VECTOR_VLS")
953 (V2HI "TARGET_VECTOR_VLS")
954 (V4HI "TARGET_VECTOR_VLS")
955 (V8HI "TARGET_VECTOR_VLS")
956 (V16HI "TARGET_VECTOR_VLS")
957 (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
958 (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
959 (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
960 (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
961 (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
962 (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
963 (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
964 (V1SI "TARGET_VECTOR_VLS")
965 (V2SI "TARGET_VECTOR_VLS")
966 (V4SI "TARGET_VECTOR_VLS")
967 (V8SI "TARGET_VECTOR_VLS")
968 (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
969 (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
970 (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
971 (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
972 (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
973 (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
974 (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
975 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
976 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
977 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
978 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
979 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
980 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
981 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
982 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
983 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
984 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
99fa5d94
JZZ		 985])
986
201c6c32
RD		 987;; Same iterator split reason as VF_ZVFHMIN and VF.
988(define_mode_iterator VWEXTF_ZVFHMIN [
879c52c9
JZ		 989 (RVVM8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
990 (RVVM4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
991 (RVVM2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
992 (RVVM1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
993 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
5c9cffa3 994
879c52c9
JZ		 995 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
996 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
b3439785
JZ		 997
998 (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
999 (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
1000 (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
1001 (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
1002 (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
1003 (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
1004 (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
1005 (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
1006 (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
1007 (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
1008 (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
1009 (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
1010 (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
1011 (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
1012 (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
1013 (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
1014 (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
1015 (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
1016 (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
1017 (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
1018 (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
dc244cdc
JZZ		 1019])
1020
201c6c32 1021(define_mode_iterator VWEXTF [
879c52c9
JZ		 1022 (RVVM8SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
1023 (RVVM4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
1024 (RVVM2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
1025 (RVVM1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
1026 (RVVMF2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
201c6c32 1027
879c52c9
JZ		 1028 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
1029 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
201c6c32
RD		 1030])
1031
dc244cdc 1032(define_mode_iterator VWCONVERTI [
879c52c9
JZ		 1033 (RVVM8SI "TARGET_ZVFH") (RVVM4SI "TARGET_ZVFH") (RVVM2SI "TARGET_ZVFH") (RVVM1SI "TARGET_ZVFH")
1034 (RVVMF2SI "TARGET_ZVFH")
71ea7a30 1035
879c52c9
JZ		 1036 (RVVM8DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1037 (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1038 (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1039 (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
dc244cdc
JZZ		 1040])
1041
99fa5d94 1042(define_mode_iterator VQEXTI [
879c52c9
JZ		 1043 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
1044
1045 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
1046 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
bea89f78
JZ		 1047
1048 (V1SI "TARGET_VECTOR_VLS")
1049 (V2SI "TARGET_VECTOR_VLS")
1050 (V4SI "TARGET_VECTOR_VLS")
1051 (V8SI "TARGET_VECTOR_VLS")
1052 (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
1053 (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
1054 (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
1055 (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
1056 (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
1057 (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
1058 (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
1059 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
1060 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
1061 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
1062 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
1063 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
1064 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
1065 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
1066 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
1067 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
1068 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
99fa5d94
JZZ		 1069])
1070
a9b40612 1071(define_mode_iterator VQEXTF [
879c52c9
JZ		 1072 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
1073 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
b3439785
JZ		 1074
1075 (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
1076 (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
1077 (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
1078 (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
1079 (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
1080 (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
1081 (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
1082 (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
1083 (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
1084 (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
a9b40612
RD		 1085])
1086
99fa5d94 1087(define_mode_iterator VOEXTI [
879c52c9
JZ		 1088 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
1089 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
bea89f78
JZ		 1090
1091 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
1092 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
1093 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
1094 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
1095 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
1096 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
1097 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
1098 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
1099 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
1100 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
99fa5d94
JZZ		 1101])
1102
12847288 1103(define_mode_iterator VT [
879c52c9
JZ		 1104 RVVM1x8QI RVVMF2x8QI RVVMF4x8QI (RVVMF8x8QI "TARGET_MIN_VLEN > 32")
1105 RVVM1x7QI RVVMF2x7QI RVVMF4x7QI (RVVMF8x7QI "TARGET_MIN_VLEN > 32")
1106 RVVM1x6QI RVVMF2x6QI RVVMF4x6QI (RVVMF8x6QI "TARGET_MIN_VLEN > 32")
1107 RVVM1x5QI RVVMF2x5QI RVVMF4x5QI (RVVMF8x5QI "TARGET_MIN_VLEN > 32")
1108 RVVM2x4QI RVVM1x4QI RVVMF2x4QI RVVMF4x4QI (RVVMF8x4QI "TARGET_MIN_VLEN > 32")
1109 RVVM2x3QI RVVM1x3QI RVVMF2x3QI RVVMF4x3QI (RVVMF8x3QI "TARGET_MIN_VLEN > 32")
1110 RVVM4x2QI RVVM2x2QI RVVM1x2QI RVVMF2x2QI RVVMF4x2QI (RVVMF8x2QI "TARGET_MIN_VLEN > 32")
1111
1112 RVVM1x8HI RVVMF2x8HI (RVVMF4x8HI "TARGET_MIN_VLEN > 32")
1113 RVVM1x7HI RVVMF2x7HI (RVVMF4x7HI "TARGET_MIN_VLEN > 32")
1114 RVVM1x6HI RVVMF2x6HI (RVVMF4x6HI "TARGET_MIN_VLEN > 32")
1115 RVVM1x5HI RVVMF2x5HI (RVVMF4x5HI "TARGET_MIN_VLEN > 32")
1116 RVVM2x4HI RVVM1x4HI RVVMF2x4HI (RVVMF4x4HI "TARGET_MIN_VLEN > 32")
1117 RVVM2x3HI RVVM1x3HI RVVMF2x3HI (RVVMF4x3HI "TARGET_MIN_VLEN > 32")
1118 RVVM4x2HI RVVM2x2HI RVVM1x2HI RVVMF2x2HI (RVVMF4x2HI "TARGET_MIN_VLEN > 32")
1119
1120 (RVVM1x8HF "TARGET_VECTOR_ELEN_FP_16")
1121 (RVVMF2x8HF "TARGET_VECTOR_ELEN_FP_16")
1122 (RVVMF4x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
1123 (RVVM1x7HF "TARGET_VECTOR_ELEN_FP_16")
1124 (RVVMF2x7HF "TARGET_VECTOR_ELEN_FP_16")
1125 (RVVMF4x7HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
1126 (RVVM1x6HF "TARGET_VECTOR_ELEN_FP_16")
1127 (RVVMF2x6HF "TARGET_VECTOR_ELEN_FP_16")
1128 (RVVMF4x6HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
1129 (RVVM1x5HF "TARGET_VECTOR_ELEN_FP_16")
1130 (RVVMF2x5HF "TARGET_VECTOR_ELEN_FP_16")
1131 (RVVMF4x5HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
1132 (RVVM2x4HF "TARGET_VECTOR_ELEN_FP_16")
1133 (RVVM1x4HF "TARGET_VECTOR_ELEN_FP_16")
1134 (RVVMF2x4HF "TARGET_VECTOR_ELEN_FP_16")
1135 (RVVMF4x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
1136 (RVVM2x3HF "TARGET_VECTOR_ELEN_FP_16")
1137 (RVVM1x3HF "TARGET_VECTOR_ELEN_FP_16")
1138 (RVVMF2x3HF "TARGET_VECTOR_ELEN_FP_16")
1139 (RVVMF4x3HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
1140 (RVVM4x2HF "TARGET_VECTOR_ELEN_FP_16")
1141 (RVVM2x2HF "TARGET_VECTOR_ELEN_FP_16")
1142 (RVVM1x2HF "TARGET_VECTOR_ELEN_FP_16")
1143 (RVVMF2x2HF "TARGET_VECTOR_ELEN_FP_16")
1144 (RVVMF4x2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
1145
1146 RVVM1x8SI (RVVMF2x8SI "TARGET_MIN_VLEN > 32")
1147 RVVM1x7SI (RVVMF2x7SI "TARGET_MIN_VLEN > 32")
1148 RVVM1x6SI (RVVMF2x6SI "TARGET_MIN_VLEN > 32")
1149 RVVM1x5SI (RVVMF2x5SI "TARGET_MIN_VLEN > 32")
1150 RVVM2x4SI RVVM1x4SI (RVVMF2x4SI "TARGET_MIN_VLEN > 32")
1151 RVVM2x3SI RVVM1x3SI (RVVMF2x3SI "TARGET_MIN_VLEN > 32")
1152 RVVM4x2SI RVVM2x2SI RVVM1x2SI (RVVMF2x2SI "TARGET_MIN_VLEN > 32")
1153
1154 (RVVM1x8SF "TARGET_VECTOR_ELEN_FP_32")
1155 (RVVMF2x8SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
1156 (RVVM1x7SF "TARGET_VECTOR_ELEN_FP_32")
1157 (RVVMF2x7SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
1158 (RVVM1x6SF "TARGET_VECTOR_ELEN_FP_32")
1159 (RVVMF2x6SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
1160 (RVVM1x5SF "TARGET_VECTOR_ELEN_FP_32")
1161 (RVVMF2x5SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
1162 (RVVM2x4SF "TARGET_VECTOR_ELEN_FP_32")
1163 (RVVM1x4SF "TARGET_VECTOR_ELEN_FP_32")
1164 (RVVMF2x4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
1165 (RVVM2x3SF "TARGET_VECTOR_ELEN_FP_32")
1166 (RVVM1x3SF "TARGET_VECTOR_ELEN_FP_32")
1167 (RVVMF2x3SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
1168 (RVVM4x2SF "TARGET_VECTOR_ELEN_FP_32")
1169 (RVVM2x2SF "TARGET_VECTOR_ELEN_FP_32")
1170 (RVVM1x2SF "TARGET_VECTOR_ELEN_FP_32")
1171 (RVVMF2x2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
1172
1173 (RVVM1x8DI "TARGET_VECTOR_ELEN_64")
1174 (RVVM1x7DI "TARGET_VECTOR_ELEN_64")
1175 (RVVM1x6DI "TARGET_VECTOR_ELEN_64")
1176 (RVVM1x5DI "TARGET_VECTOR_ELEN_64")
1177 (RVVM2x4DI "TARGET_VECTOR_ELEN_64")
1178 (RVVM1x4DI "TARGET_VECTOR_ELEN_64")
1179 (RVVM2x3DI "TARGET_VECTOR_ELEN_64")
1180 (RVVM1x3DI "TARGET_VECTOR_ELEN_64")
1181 (RVVM4x2DI "TARGET_VECTOR_ELEN_64")
1182 (RVVM2x2DI "TARGET_VECTOR_ELEN_64")
1183 (RVVM1x2DI "TARGET_VECTOR_ELEN_64")
1184
1185 (RVVM1x8DF "TARGET_VECTOR_ELEN_FP_64")
1186 (RVVM1x7DF "TARGET_VECTOR_ELEN_FP_64")
1187 (RVVM1x6DF "TARGET_VECTOR_ELEN_FP_64")
1188 (RVVM1x5DF "TARGET_VECTOR_ELEN_FP_64")
1189 (RVVM2x4DF "TARGET_VECTOR_ELEN_FP_64")
1190 (RVVM1x4DF "TARGET_VECTOR_ELEN_FP_64")
1191 (RVVM2x3DF "TARGET_VECTOR_ELEN_FP_64")
1192 (RVVM1x3DF "TARGET_VECTOR_ELEN_FP_64")
1193 (RVVM4x2DF "TARGET_VECTOR_ELEN_FP_64")
1194 (RVVM2x2DF "TARGET_VECTOR_ELEN_FP_64")
1195 (RVVM1x2DF "TARGET_VECTOR_ELEN_FP_64")
6313b045
JZZ		 1196])
1197
1198(define_mode_iterator V1T [
879c52c9
JZ		 1199 (RVVMF8x2QI "TARGET_MIN_VLEN > 32")
1200 (RVVMF8x3QI "TARGET_MIN_VLEN > 32")
1201 (RVVMF8x4QI "TARGET_MIN_VLEN > 32")
1202 (RVVMF8x5QI "TARGET_MIN_VLEN > 32")
1203 (RVVMF8x6QI "TARGET_MIN_VLEN > 32")
1204 (RVVMF8x7QI "TARGET_MIN_VLEN > 32")
1205 (RVVMF8x8QI "TARGET_MIN_VLEN > 32")
1206 (RVVMF4x2HI "TARGET_MIN_VLEN > 32")
1207 (RVVMF4x3HI "TARGET_MIN_VLEN > 32")
1208 (RVVMF4x4HI "TARGET_MIN_VLEN > 32")
1209 (RVVMF4x5HI "TARGET_MIN_VLEN > 32")
1210 (RVVMF4x6HI "TARGET_MIN_VLEN > 32")
1211 (RVVMF4x7HI "TARGET_MIN_VLEN > 32")
1212 (RVVMF4x8HI "TARGET_MIN_VLEN > 32")
1213 (RVVMF2x2SI "TARGET_MIN_VLEN > 32")
1214 (RVVMF2x3SI "TARGET_MIN_VLEN > 32")
1215 (RVVMF2x4SI "TARGET_MIN_VLEN > 32")
1216 (RVVMF2x5SI "TARGET_MIN_VLEN > 32")
1217 (RVVMF2x6SI "TARGET_MIN_VLEN > 32")
1218 (RVVMF2x7SI "TARGET_MIN_VLEN > 32")
1219 (RVVMF2x8SI "TARGET_MIN_VLEN > 32")
1220 (RVVM1x2DI "TARGET_VECTOR_ELEN_64")
1221 (RVVM1x3DI "TARGET_VECTOR_ELEN_64")
1222 (RVVM1x4DI "TARGET_VECTOR_ELEN_64")
1223 (RVVM1x5DI "TARGET_VECTOR_ELEN_64")
1224 (RVVM1x6DI "TARGET_VECTOR_ELEN_64")
1225 (RVVM1x7DI "TARGET_VECTOR_ELEN_64")
1226 (RVVM1x8DI "TARGET_VECTOR_ELEN_64")
1227 (RVVMF4x2HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1228 (RVVMF4x3HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1229 (RVVMF4x4HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1230 (RVVMF4x5HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1231 (RVVMF4x6HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1232 (RVVMF4x7HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1233 (RVVMF4x8HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1234 (RVVMF2x2SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1235 (RVVMF2x3SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1236 (RVVMF2x4SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1237 (RVVMF2x5SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1238 (RVVMF2x6SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1239 (RVVMF2x7SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1240 (RVVMF2x8SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1241 (RVVM1x2DF "TARGET_VECTOR_ELEN_FP_64")
1242 (RVVM1x3DF "TARGET_VECTOR_ELEN_FP_64")
1243 (RVVM1x4DF "TARGET_VECTOR_ELEN_FP_64")
1244 (RVVM1x5DF "TARGET_VECTOR_ELEN_FP_64")
1245 (RVVM1x6DF "TARGET_VECTOR_ELEN_FP_64")
1246 (RVVM1x7DF "TARGET_VECTOR_ELEN_FP_64")
1247 (RVVM1x8DF "TARGET_VECTOR_ELEN_FP_64")
6313b045
JZZ		 1248])
1249
1250(define_mode_iterator V2T [
879c52c9
JZ		 1251 RVVMF4x2QI
1252 RVVMF4x3QI
1253 RVVMF4x4QI
1254 RVVMF4x5QI
1255 RVVMF4x6QI
1256 RVVMF4x7QI
1257 RVVMF4x8QI
1258 RVVMF2x2HI
1259 RVVMF2x3HI
1260 RVVMF2x4HI
1261 RVVMF2x5HI
1262 RVVMF2x6HI
1263 RVVMF2x7HI
1264 RVVMF2x8HI
1265 RVVM1x2SI
1266 RVVM1x3SI
1267 RVVM1x4SI
1268 RVVM1x5SI
1269 RVVM1x6SI
1270 RVVM1x7SI
1271 RVVM1x8SI
1272 (RVVM2x2DI "TARGET_VECTOR_ELEN_64")
1273 (RVVM2x3DI "TARGET_VECTOR_ELEN_64")
1274 (RVVM2x4DI "TARGET_VECTOR_ELEN_64")
1275 (RVVMF2x2HF "TARGET_VECTOR_ELEN_FP_16")
1276 (RVVMF2x3HF "TARGET_VECTOR_ELEN_FP_16")
1277 (RVVMF2x4HF "TARGET_VECTOR_ELEN_FP_16")
1278 (RVVMF2x5HF "TARGET_VECTOR_ELEN_FP_16")
1279 (RVVMF2x6HF "TARGET_VECTOR_ELEN_FP_16")
1280 (RVVMF2x7HF "TARGET_VECTOR_ELEN_FP_16")
1281 (RVVMF2x8HF "TARGET_VECTOR_ELEN_FP_16")
1282 (RVVM1x2SF "TARGET_VECTOR_ELEN_FP_32")
1283 (RVVM1x3SF "TARGET_VECTOR_ELEN_FP_32")
1284 (RVVM1x4SF "TARGET_VECTOR_ELEN_FP_32")
1285 (RVVM1x5SF "TARGET_VECTOR_ELEN_FP_32")
1286 (RVVM1x6SF "TARGET_VECTOR_ELEN_FP_32")
1287 (RVVM1x7SF "TARGET_VECTOR_ELEN_FP_32")
1288 (RVVM1x8SF "TARGET_VECTOR_ELEN_FP_32")
1289 (RVVM2x2DF "TARGET_VECTOR_ELEN_FP_64")
1290 (RVVM2x3DF "TARGET_VECTOR_ELEN_FP_64")
1291 (RVVM2x4DF "TARGET_VECTOR_ELEN_FP_64")
6313b045
JZZ		 1292])
1293
1294(define_mode_iterator V4T [
879c52c9
JZ		 1295 RVVMF2x2QI
1296 RVVMF2x3QI
1297 RVVMF2x4QI
1298 RVVMF2x5QI
1299 RVVMF2x6QI
1300 RVVMF2x7QI
1301 RVVMF2x8QI
1302 RVVM1x2HI
1303 RVVM1x3HI
1304 RVVM1x4HI
1305 RVVM1x5HI
1306 RVVM1x6HI
1307 RVVM1x7HI
1308 RVVM1x8HI
1309 RVVM2x2SI
1310 RVVM2x3SI
1311 RVVM2x4SI
1312 (RVVM4x2DI "TARGET_VECTOR_ELEN_64")
1313 (RVVM1x2HF "TARGET_VECTOR_ELEN_FP_16")
1314 (RVVM1x3HF "TARGET_VECTOR_ELEN_FP_16")
1315 (RVVM1x4HF "TARGET_VECTOR_ELEN_FP_16")
1316 (RVVM1x5HF "TARGET_VECTOR_ELEN_FP_16")
1317 (RVVM1x6HF "TARGET_VECTOR_ELEN_FP_16")
1318 (RVVM1x7HF "TARGET_VECTOR_ELEN_FP_16")
1319 (RVVM1x8HF "TARGET_VECTOR_ELEN_FP_16")
1320 (RVVM2x2SF "TARGET_VECTOR_ELEN_FP_32")
1321 (RVVM2x3SF "TARGET_VECTOR_ELEN_FP_32")
1322 (RVVM2x4SF "TARGET_VECTOR_ELEN_FP_32")
adbac207 1323 (RVVM4x2DF "TARGET_VECTOR_ELEN_FP_64")
6313b045
JZZ		 1324])
1325
1326(define_mode_iterator V8T [
879c52c9
JZ		 1327 RVVM1x2QI
1328 RVVM1x3QI
1329 RVVM1x4QI
1330 RVVM1x5QI
1331 RVVM1x6QI
1332 RVVM1x7QI
1333 RVVM1x8QI
1334 RVVM2x2HI
1335 RVVM2x3HI
1336 RVVM2x4HI
1337 RVVM4x2SI
1338 (RVVM2x2HF "TARGET_VECTOR_ELEN_FP_16")
1339 (RVVM2x3HF "TARGET_VECTOR_ELEN_FP_16")
1340 (RVVM2x4HF "TARGET_VECTOR_ELEN_FP_16")
1341 (RVVM4x2SF "TARGET_VECTOR_ELEN_FP_32")
6313b045
JZZ		 1342])
1343
1344(define_mode_iterator V16T [
879c52c9
JZ		 1345 RVVM2x2QI
1346 RVVM2x3QI
1347 RVVM2x4QI
1348 RVVM4x2HI
1349 (RVVM4x2HF "TARGET_VECTOR_ELEN_FP_16")
6313b045
JZZ		 1350])
1351
1352(define_mode_iterator V32T [
879c52c9 1353 RVVM4x2QI
6313b045
JZZ		 1354])
1355
d0cf0c6c 1356(define_mode_iterator VQI [
879c52c9 1357 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
d0cf0c6c
PL		 1358])
1359
1360(define_mode_iterator VHI [
879c52c9 1361 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
d0cf0c6c
PL		 1362])
1363
1364(define_mode_iterator VSI [
879c52c9 1365 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
d0cf0c6c
PL		 1366])
1367
1368(define_mode_iterator VDI [
879c52c9
JZ		 1369 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
1370 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
d0cf0c6c
PL		 1371])
1372
2ba7347a 1373(define_mode_iterator VHF [
879c52c9
JZ		 1374 (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH")
1375 (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
1376 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
2ba7347a
PL		 1377])
1378
1379(define_mode_iterator VSF [
879c52c9
JZ		 1380 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
1381 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
2ba7347a
PL		 1382])
1383
1384(define_mode_iterator VDF [
879c52c9
JZ		 1385 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
1386 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
2ba7347a
PL		 1387])
1388
14c481f7
LD		 1389(define_mode_attr V_LMUL1 [
1390 (RVVM8QI "RVVM1QI") (RVVM4QI "RVVM1QI") (RVVM2QI "RVVM1QI") (RVVM1QI "RVVM1QI") (RVVMF2QI "RVVM1QI") (RVVMF4QI "RVVM1QI") (RVVMF8QI "RVVM1QI")
d0cf0c6c 1391
14c481f7 1392 (RVVM8HI "RVVM1HI") (RVVM4HI "RVVM1HI") (RVVM2HI "RVVM1HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVM1HI") (RVVMF4HI "RVVM1HI")
d0cf0c6c 1393
14c481f7 1394 (RVVM8SI "RVVM1SI") (RVVM4SI "RVVM1SI") (RVVM2SI "RVVM1SI") (RVVM1SI "RVVM1SI") (RVVMF2SI "RVVM1SI")
d0cf0c6c 1395
14c481f7 1396 (RVVM8DI "RVVM1DI") (RVVM4DI "RVVM1DI") (RVVM2DI "RVVM1DI") (RVVM1DI "RVVM1DI")
d0cf0c6c 1397
14c481f7 1398 (RVVM8HF "RVVM1HF") (RVVM4HF "RVVM1HF") (RVVM2HF "RVVM1HF") (RVVM1HF "RVVM1HF") (RVVMF2HF "RVVM1HF") (RVVMF4HF "RVVM1HF")
2ba7347a 1399
14c481f7
LD		 1400 (RVVM8SF "RVVM1SF") (RVVM4SF "RVVM1SF") (RVVM2SF "RVVM1SF") (RVVM1SF "RVVM1SF") (RVVMF2SF "RVVM1SF")
1401
1402 (RVVM8DF "RVVM1DF") (RVVM4DF "RVVM1DF") (RVVM2DF "RVVM1DF") (RVVM1DF "RVVM1DF")
71e0f38d
JZ		 1403
1404 (V1QI "RVVM1QI")
1405 (V2QI "RVVM1QI")
1406 (V4QI "RVVM1QI")
1407 (V8QI "RVVM1QI")
1408 (V16QI "RVVM1QI")
1409 (V32QI "RVVM1QI")
1410 (V64QI "RVVM1QI")
1411 (V128QI "RVVM1QI")
1412 (V256QI "RVVM1QI")
1413 (V512QI "RVVM1QI")
1414 (V1024QI "RVVM1QI")
1415 (V2048QI "RVVM1QI")
1416 (V4096QI "RVVM1QI")
1417 (V1HI "RVVM1HI")
1418 (V2HI "RVVM1HI")
1419 (V4HI "RVVM1HI")
1420 (V8HI "RVVM1HI")
1421 (V16HI "RVVM1HI")
1422 (V32HI "RVVM1HI")
1423 (V64HI "RVVM1HI")
1424 (V128HI "RVVM1HI")
1425 (V256HI "RVVM1HI")
1426 (V512HI "RVVM1HI")
1427 (V1024HI "RVVM1HI")
1428 (V2048HI "RVVM1HI")
1429 (V1SI "RVVM1SI")
1430 (V2SI "RVVM1SI")
1431 (V4SI "RVVM1SI")
1432 (V8SI "RVVM1SI")
1433 (V16SI "RVVM1SI")
1434 (V32SI "RVVM1SI")
1435 (V64SI "RVVM1SI")
1436 (V128SI "RVVM1SI")
1437 (V256SI "RVVM1SI")
1438 (V512SI "RVVM1SI")
1439 (V1024SI "RVVM1SI")
1440 (V1DI "RVVM1DI")
1441 (V2DI "RVVM1DI")
1442 (V4DI "RVVM1DI")
1443 (V8DI "RVVM1DI")
1444 (V16DI "RVVM1DI")
1445 (V32DI "RVVM1DI")
1446 (V64DI "RVVM1DI")
1447 (V128DI "RVVM1DI")
1448 (V256DI "RVVM1DI")
1449 (V512DI "RVVM1DI")
1450 (V1HF "RVVM1HF")
1451 (V2HF "RVVM1HF")
1452 (V4HF "RVVM1HF")
1453 (V8HF "RVVM1HF")
1454 (V16HF "RVVM1HF")
1455 (V32HF "RVVM1HF")
1456 (V64HF "RVVM1HF")
1457 (V128HF "RVVM1HF")
1458 (V256HF "RVVM1HF")
1459 (V512HF "RVVM1HF")
1460 (V1024HF "RVVM1HF")
1461 (V2048HF "RVVM1HF")
1462 (V1SF "RVVM1SF")
1463 (V2SF "RVVM1SF")
1464 (V4SF "RVVM1SF")
1465 (V8SF "RVVM1SF")
1466 (V16SF "RVVM1SF")
1467 (V32SF "RVVM1SF")
1468 (V64SF "RVVM1SF")
1469 (V128SF "RVVM1SF")
1470 (V256SF "RVVM1SF")
1471 (V512SF "RVVM1SF")
1472 (V1024SF "RVVM1SF")
1473 (V1DF "RVVM1DF")
1474 (V2DF "RVVM1DF")
1475 (V4DF "RVVM1DF")
1476 (V8DF "RVVM1DF")
1477 (V16DF "RVVM1DF")
1478 (V32DF "RVVM1DF")
1479 (V64DF "RVVM1DF")
1480 (V128DF "RVVM1DF")
1481 (V256DF "RVVM1DF")
1482 (V512DF "RVVM1DF")
2ba7347a
PL		 1483])
1484
14c481f7
LD		 1485(define_mode_attr V_EXT_LMUL1 [
1486 (RVVM8QI "RVVM1HI") (RVVM4QI "RVVM1HI") (RVVM2QI "RVVM1HI") (RVVM1QI "RVVM1HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVM1HI") (RVVMF8QI "RVVM1HI")
1487
1488 (RVVM8HI "RVVM1SI") (RVVM4HI "RVVM1SI") (RVVM2HI "RVVM1SI") (RVVM1HI "RVVM1SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVM1SI")
1489
1490 (RVVM8SI "RVVM1DI") (RVVM4SI "RVVM1DI") (RVVM2SI "RVVM1DI") (RVVM1SI "RVVM1DI") (RVVMF2SI "RVVM1DI")
1491
1492 (RVVM8HF "RVVM1SF") (RVVM4HF "RVVM1SF") (RVVM2HF "RVVM1SF") (RVVM1HF "RVVM1SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVM1SF")
1493
1494 (RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF")
2ba7347a
PL		 1495])
1496
6223ea76
LD		 1497(define_int_iterator ANY_REDUC [
1498 UNSPEC_REDUC_SUM UNSPEC_REDUC_MAXU UNSPEC_REDUC_MAX UNSPEC_REDUC_MINU
1499 UNSPEC_REDUC_MIN UNSPEC_REDUC_AND UNSPEC_REDUC_OR UNSPEC_REDUC_XOR
1500])
1501
1502(define_int_iterator ANY_WREDUC [
1503 UNSPEC_WREDUC_SUM UNSPEC_WREDUC_SUMU
1504])
1505
1506(define_int_iterator ANY_FREDUC [
1507 UNSPEC_REDUC_MAX UNSPEC_REDUC_MIN
1508])
1509
1510(define_int_iterator ANY_FREDUC_SUM [
1511 UNSPEC_REDUC_SUM_ORDERED UNSPEC_REDUC_SUM_UNORDERED
1512])
1513
1514(define_int_iterator ANY_FWREDUC_SUM [
1515 UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED
1516])
1517
1518(define_int_attr reduc_op [
1519 (UNSPEC_REDUC_SUM "redsum")
1520 (UNSPEC_REDUC_SUM_ORDERED "redosum") (UNSPEC_REDUC_SUM_UNORDERED "redusum")
1521 (UNSPEC_REDUC_MAXU "redmaxu") (UNSPEC_REDUC_MAX "redmax") (UNSPEC_REDUC_MINU "redminu") (UNSPEC_REDUC_MIN "redmin")
1522 (UNSPEC_REDUC_AND "redand") (UNSPEC_REDUC_OR "redor") (UNSPEC_REDUC_XOR "redxor")
1523 (UNSPEC_WREDUC_SUM "wredsum") (UNSPEC_WREDUC_SUMU "wredsumu")
1524 (UNSPEC_WREDUC_SUM_ORDERED "wredosum") (UNSPEC_WREDUC_SUM_UNORDERED "wredusum")
1525])
1526
68cb873f
LD		 1527(define_code_attr WREDUC_UNSPEC [(zero_extend "UNSPEC_WREDUC_SUMU") (sign_extend "UNSPEC_WREDUC_SUM")])
1528
879c52c9
JZ		 1529(define_mode_attr VINDEX [
1530 (RVVM8QI "RVVM8QI") (RVVM4QI "RVVM4QI") (RVVM2QI "RVVM2QI") (RVVM1QI "RVVM1QI")
1531 (RVVMF2QI "RVVMF2QI") (RVVMF4QI "RVVMF4QI") (RVVMF8QI "RVVMF8QI")
7caa1ae5 1532
879c52c9 1533 (RVVM8HI "RVVM8HI") (RVVM4HI "RVVM4HI") (RVVM2HI "RVVM2HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVMF2HI") (RVVMF4HI "RVVMF4HI")
7caa1ae5 1534
879c52c9 1535 (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI")
7caa1ae5 1536
879c52c9 1537 (RVVM8SI "RVVM8SI") (RVVM4SI "RVVM4SI") (RVVM2SI "RVVM2SI") (RVVM1SI "RVVM1SI") (RVVMF2SI "RVVMF2SI")
7caa1ae5 1538
879c52c9 1539 (RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI") (RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI")
7caa1ae5 1540
879c52c9 1541 (RVVM8DI "RVVM8DI") (RVVM4DI "RVVM4DI") (RVVM2DI "RVVM2DI") (RVVM1DI "RVVM1DI")
7caa1ae5 1542
879c52c9 1543 (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") (RVVM1DF "RVVM1DI")
d05aac04
JZ		 1544
1545 (V1QI "V1QI")
1546 (V2QI "V2QI")
1547 (V4QI "V4QI")
1548 (V8QI "V8QI")
1549 (V16QI "V16QI")
1550 (V32QI "V32QI")
1551 (V64QI "V64QI")
1552 (V128QI "V128QI")
1553 (V256QI "V256QI")
1554 (V512QI "V512QI")
1555 (V1024QI "V1024QI")
1556 (V2048QI "V2048QI")
1557 (V4096QI "V4096QI")
1558 (V1HI "V1HI")
1559 (V2HI "V2HI")
1560 (V4HI "V4HI")
1561 (V8HI "V8HI")
1562 (V16HI "V16HI")
1563 (V32HI "V32HI")
1564 (V64HI "V64HI")
1565 (V128HI "V128HI")
1566 (V256HI "V256HI")
1567 (V512HI "V512HI")
1568 (V1024HI "V1024HI")
1569 (V2048HI "V2048HI")
1570 (V1SI "V1SI")
1571 (V2SI "V2SI")
1572 (V4SI "V4SI")
1573 (V8SI "V8SI")
1574 (V16SI "V16SI")
1575 (V32SI "V32SI")
1576 (V64SI "V64SI")
1577 (V128SI "V128SI")
1578 (V256SI "V256SI")
1579 (V512SI "V512SI")
1580 (V1024SI "V1024SI")
1581 (V1DI "V1DI")
1582 (V2DI "V2DI")
1583 (V4DI "V4DI")
1584 (V8DI "V8DI")
1585 (V16DI "V16DI")
1586 (V32DI "V32DI")
1587 (V64DI "V64DI")
1588 (V128DI "V128DI")
1589 (V256DI "V256DI")
1590 (V512DI "V512DI")
1591 (V1HF "V1HI")
1592 (V2HF "V2HI")
1593 (V4HF "V4HI")
1594 (V8HF "V8HI")
1595 (V16HF "V16HI")
1596 (V32HF "V32HI")
1597 (V64HF "V64HI")
1598 (V128HF "V128HI")
1599 (V256HF "V256HI")
1600 (V512HF "V512HI")
1601 (V1024HF "V1024HI")
1602 (V2048HF "V2048HI")
1603 (V1SF "V1SI")
1604 (V2SF "V2SI")
1605 (V4SF "V4SI")
1606 (V8SF "V8SI")
1607 (V16SF "V16SI")
1608 (V32SF "V32SI")
1609 (V64SF "V64SI")
1610 (V128SF "V128SI")
1611 (V256SF "V256SI")
1612 (V512SF "V512SI")
1613 (V1024SF "V1024SI")
1614 (V1DF "V1DI")
1615 (V2DF "V2DI")
1616 (V4DF "V4DI")
1617 (V8DF "V8DI")
1618 (V16DF "V16DI")
1619 (V32DF "V32DI")
1620 (V64DF "V64DI")
1621 (V128DF "V128DI")
1622 (V256DF "V256DI")
1623 (V512DF "V512DI")
1bff101b
JZZ		 1624])
1625
1626(define_mode_attr VINDEXEI16 [
879c52c9
JZ		 1627 (RVVM4QI "RVVM8HI") (RVVM2QI "RVVM4HI") (RVVM1QI "RVVM2HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVMF2HI") (RVVMF8QI "RVVMF4HI")
1628
1629 (RVVM8HI "RVVM8HI") (RVVM4HI "RVVM4HI") (RVVM2HI "RVVM2HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVMF2HI") (RVVMF4HI "RVVMF4HI")
1630
1631 (RVVM8SI "RVVM4HI") (RVVM4SI "RVVM2HI") (RVVM2SI "RVVM1HI") (RVVM1SI "RVVMF2HI") (RVVMF2SI "RVVMF4HI")
1632
1633 (RVVM8DI "RVVM2HI") (RVVM4DI "RVVM1HI") (RVVM2DI "RVVMF2HI") (RVVM1DI "RVVMF4HI")
1634
1635 (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI")
1636
1637 (RVVM8SF "RVVM4HI") (RVVM4SF "RVVM2HI") (RVVM2SF "RVVM1HI") (RVVM1SF "RVVMF2HI") (RVVMF2SF "RVVMF4HI")
1638
1639 (RVVM8DF "RVVM2HI") (RVVM4DF "RVVM1HI") (RVVM2DF "RVVMF2HI") (RVVM1DF "RVVMF4HI")
d05aac04
JZ		 1640
1641 (V1QI "V1HI")
1642 (V2QI "V2HI")
1643 (V4QI "V4HI")
1644 (V8QI "V8HI")
1645 (V16QI "V16HI")
1646 (V32QI "V32HI")
1647 (V64QI "V64HI")
1648 (V128QI "V128HI")
1649 (V256QI "V256HI")
1650 (V512QI "V512HI")
1651 (V1024QI "V1024HI")
1652 (V2048QI "V2048HI")
1653 (V1HI "V1HI")
1654 (V2HI "V2HI")
1655 (V4HI "V4HI")
1656 (V8HI "V8HI")
1657 (V16HI "V16HI")
1658 (V32HI "V32HI")
1659 (V64HI "V64HI")
1660 (V128HI "V128HI")
1661 (V256HI "V256HI")
1662 (V512HI "V512HI")
1663 (V1024HI "V1024HI")
1664 (V2048HI "V2048HI")
1665 (V1SI "V1HI")
1666 (V2SI "V2HI")
1667 (V4SI "V4HI")
1668 (V8SI "V8HI")
1669 (V16SI "V16HI")
1670 (V32SI "V32HI")
1671 (V64SI "V64HI")
1672 (V128SI "V128HI")
1673 (V256SI "V256HI")
1674 (V512SI "V512HI")
1675 (V1024SI "V1024HI")
1676 (V1DI "V1HI")
1677 (V2DI "V2HI")
1678 (V4DI "V4HI")
1679 (V8DI "V8HI")
1680 (V16DI "V16HI")
1681 (V32DI "V32HI")
1682 (V64DI "V64HI")
1683 (V128DI "V128HI")
1684 (V256DI "V256HI")
1685 (V512DI "V512HI")
1686 (V1HF "V1HI")
1687 (V2HF "V2HI")
1688 (V4HF "V4HI")
1689 (V8HF "V8HI")
1690 (V16HF "V16HF")
1691 (V32HF "V32HI")
1692 (V64HF "V64HI")
1693 (V128HF "V128HI")
1694 (V256HF "V256HI")
1695 (V512HF "V512HI")
1696 (V1024HF "V1024HI")
1697 (V2048HF "V2048HI")
1698 (V1SF "V1HI")
1699 (V2SF "V2HI")
1700 (V4SF "V4HI")
1701 (V8SF "V8HI")
1702 (V16SF "V16HI")
1703 (V32SF "V32HI")
1704 (V64SF "V64HI")
1705 (V128SF "V128HI")
1706 (V256SF "V256HI")
1707 (V512SF "V512HI")
1708 (V1024SF "V1024HI")
1709 (V1DF "V1HI")
1710 (V2DF "V2HI")
1711 (V4DF "V4HI")
1712 (V8DF "V8HI")
1713 (V16DF "V16HI")
1714 (V32DF "V32HI")
1715 (V64DF "V64HI")
1716 (V128DF "V128HI")
1717 (V256DF "V256HI")
1718 (V512DF "V512HI")
1bff101b
JZZ		 1719])
1720
f556cd8b 1721(define_mode_attr VM [
879c52c9
JZ		 1722 (RVVM8QI "RVVM1BI") (RVVM4QI "RVVMF2BI") (RVVM2QI "RVVMF4BI") (RVVM1QI "RVVMF8BI") (RVVMF2QI "RVVMF16BI") (RVVMF4QI "RVVMF32BI") (RVVMF8QI "RVVMF64BI")
1723
1724 (RVVM8HI "RVVMF2BI") (RVVM4HI "RVVMF4BI") (RVVM2HI "RVVMF8BI") (RVVM1HI "RVVMF16BI") (RVVMF2HI "RVVMF32BI") (RVVMF4HI "RVVMF64BI")
1725
1726 (RVVM8HF "RVVMF2BI") (RVVM4HF "RVVMF4BI") (RVVM2HF "RVVMF8BI") (RVVM1HF "RVVMF16BI") (RVVMF2HF "RVVMF32BI") (RVVMF4HF "RVVMF64BI")
1727
1728 (RVVM8SI "RVVMF4BI") (RVVM4SI "RVVMF8BI") (RVVM2SI "RVVMF16BI") (RVVM1SI "RVVMF32BI") (RVVMF2SI "RVVMF64BI")
1729
1730 (RVVM8SF "RVVMF4BI") (RVVM4SF "RVVMF8BI") (RVVM2SF "RVVMF16BI") (RVVM1SF "RVVMF32BI") (RVVMF2SF "RVVMF64BI")
1731
1732 (RVVM8DI "RVVMF8BI") (RVVM4DI "RVVMF16BI") (RVVM2DI "RVVMF32BI") (RVVM1DI "RVVMF64BI")
1733
1734 (RVVM8DF "RVVMF8BI") (RVVM4DF "RVVMF16BI") (RVVM2DF "RVVMF32BI") (RVVM1DF "RVVMF64BI")
1735
1736 (RVVM1x8QI "RVVMF8BI") (RVVMF2x8QI "RVVMF16BI") (RVVMF4x8QI "RVVMF32BI") (RVVMF8x8QI "RVVMF64BI")
1737 (RVVM1x7QI "RVVMF8BI") (RVVMF2x7QI "RVVMF16BI") (RVVMF4x7QI "RVVMF32BI") (RVVMF8x7QI "RVVMF64BI")
1738 (RVVM1x6QI "RVVMF8BI") (RVVMF2x6QI "RVVMF16BI") (RVVMF4x6QI "RVVMF32BI") (RVVMF8x6QI "RVVMF64BI")
1739 (RVVM1x5QI "RVVMF8BI") (RVVMF2x5QI "RVVMF16BI") (RVVMF4x5QI "RVVMF32BI") (RVVMF8x5QI "RVVMF64BI")
1740 (RVVM2x4QI "RVVMF4BI") (RVVM1x4QI "RVVMF8BI") (RVVMF2x4QI "RVVMF16BI") (RVVMF4x4QI "RVVMF32BI") (RVVMF8x4QI "RVVMF64BI")
1741 (RVVM2x3QI "RVVMF4BI") (RVVM1x3QI "RVVMF8BI") (RVVMF2x3QI "RVVMF16BI") (RVVMF4x3QI "RVVMF32BI") (RVVMF8x3QI "RVVMF64BI")
1742 (RVVM4x2QI "RVVMF2BI") (RVVM2x2QI "RVVMF4BI") (RVVM1x2QI "RVVMF8BI") (RVVMF2x2QI "RVVMF16BI") (RVVMF4x2QI "RVVMF32BI") (RVVMF8x2QI "RVVMF64BI")
1743
1744 (RVVM1x8HI "RVVMF16BI") (RVVMF2x8HI "RVVMF32BI") (RVVMF4x8HI "RVVMF64BI")
1745 (RVVM1x7HI "RVVMF16BI") (RVVMF2x7HI "RVVMF32BI") (RVVMF4x7HI "RVVMF64BI")
1746 (RVVM1x6HI "RVVMF16BI") (RVVMF2x6HI "RVVMF32BI") (RVVMF4x6HI "RVVMF64BI")
1747 (RVVM1x5HI "RVVMF16BI") (RVVMF2x5HI "RVVMF32BI") (RVVMF4x5HI "RVVMF64BI")
1748 (RVVM2x4HI "RVVMF8BI") (RVVM1x4HI "RVVMF16BI") (RVVMF2x4HI "RVVMF32BI") (RVVMF4x4HI "RVVMF64BI")
1749 (RVVM2x3HI "RVVMF8BI") (RVVM1x3HI "RVVMF16BI") (RVVMF2x3HI "RVVMF32BI") (RVVMF4x3HI "RVVMF64BI")
1750 (RVVM4x2HI "RVVMF4BI") (RVVM2x2HI "RVVMF8BI") (RVVM1x2HI "RVVMF16BI") (RVVMF2x2HI "RVVMF32BI") (RVVMF4x2HI "RVVMF64BI")
1751
1752 (RVVM1x8HF "RVVMF16BI") (RVVMF2x8HF "RVVMF32BI") (RVVMF4x8HF "RVVMF64BI")
1753 (RVVM1x7HF "RVVMF16BI") (RVVMF2x7HF "RVVMF32BI") (RVVMF4x7HF "RVVMF64BI")
1754 (RVVM1x6HF "RVVMF16BI") (RVVMF2x6HF "RVVMF32BI") (RVVMF4x6HF "RVVMF64BI")
1755 (RVVM1x5HF "RVVMF16BI") (RVVMF2x5HF "RVVMF32BI") (RVVMF4x5HF "RVVMF64BI")
1756 (RVVM2x4HF "RVVMF8BI") (RVVM1x4HF "RVVMF16BI") (RVVMF2x4HF "RVVMF32BI") (RVVMF4x4HF "RVVMF64BI")
1757 (RVVM2x3HF "RVVMF8BI") (RVVM1x3HF "RVVMF16BI") (RVVMF2x3HF "RVVMF32BI") (RVVMF4x3HF "RVVMF64BI")
1758 (RVVM4x2HF "RVVMF4BI") (RVVM2x2HF "RVVMF8BI") (RVVM1x2HF "RVVMF16BI") (RVVMF2x2HF "RVVMF32BI") (RVVMF4x2HF "RVVMF64BI")
1759
1760 (RVVM1x8SI "RVVMF32BI") (RVVMF2x8SI "RVVMF64BI")
1761 (RVVM1x7SI "RVVMF32BI") (RVVMF2x7SI "RVVMF64BI")
1762 (RVVM1x6SI "RVVMF32BI") (RVVMF2x6SI "RVVMF64BI")
1763 (RVVM1x5SI "RVVMF32BI") (RVVMF2x5SI "RVVMF64BI")
1764 (RVVM2x4SI "RVVMF16BI") (RVVM1x4SI "RVVMF32BI") (RVVMF2x4SI "RVVMF64BI")
1765 (RVVM2x3SI "RVVMF16BI") (RVVM1x3SI "RVVMF32BI") (RVVMF2x3SI "RVVMF64BI")
1766 (RVVM4x2SI "RVVMF8BI") (RVVM2x2SI "RVVMF16BI") (RVVM1x2SI "RVVMF32BI") (RVVMF2x2SI "RVVMF64BI")
1767
1768 (RVVM1x8SF "RVVMF32BI") (RVVMF2x8SF "RVVMF64BI")
1769 (RVVM1x7SF "RVVMF32BI") (RVVMF2x7SF "RVVMF64BI")
1770 (RVVM1x6SF "RVVMF32BI") (RVVMF2x6SF "RVVMF64BI")
1771 (RVVM1x5SF "RVVMF32BI") (RVVMF2x5SF "RVVMF64BI")
1772 (RVVM2x4SF "RVVMF16BI") (RVVM1x4SF "RVVMF32BI") (RVVMF2x4SF "RVVMF64BI")
1773 (RVVM2x3SF "RVVMF16BI") (RVVM1x3SF "RVVMF32BI") (RVVMF2x3SF "RVVMF64BI")
1774 (RVVM4x2SF "RVVMF8BI") (RVVM2x2SF "RVVMF16BI") (RVVM1x2SF "RVVMF32BI") (RVVMF2x2SF "RVVMF64BI")
1775
1776 (RVVM1x8DI "RVVMF64BI")
1777 (RVVM1x7DI "RVVMF64BI")
1778 (RVVM1x6DI "RVVMF64BI")
1779 (RVVM1x5DI "RVVMF64BI")
1780 (RVVM2x4DI "RVVMF32BI")
1781 (RVVM1x4DI "RVVMF64BI")
1782 (RVVM2x3DI "RVVMF32BI")
1783 (RVVM1x3DI "RVVMF64BI")
1784 (RVVM4x2DI "RVVMF16BI")
1785 (RVVM2x2DI "RVVMF32BI")
1786 (RVVM1x2DI "RVVMF64BI")
1787
1788 (RVVM1x8DF "RVVMF64BI")
1789 (RVVM1x7DF "RVVMF64BI")
1790 (RVVM1x6DF "RVVMF64BI")
1791 (RVVM1x5DF "RVVMF64BI")
1792 (RVVM2x4DF "RVVMF32BI")
1793 (RVVM1x4DF "RVVMF64BI")
1794 (RVVM2x3DF "RVVMF32BI")
1795 (RVVM1x3DF "RVVMF64BI")
1796 (RVVM4x2DF "RVVMF16BI")
1797 (RVVM2x2DF "RVVMF32BI")
1798 (RVVM1x2DF "RVVMF64BI")
33b153ff
JZ		 1799
1800 ;; VLS modes.
1801 (V1QI "V1BI") (V2QI "V2BI") (V4QI "V4BI") (V8QI "V8BI") (V16QI "V16BI") (V32QI "V32BI")
1802 (V64QI "V64BI") (V128QI "V128BI") (V256QI "V256BI") (V512QI "V512BI")
1803 (V1024QI "V1024BI") (V2048QI "V2048BI") (V4096QI "V4096BI")
1804 (V1HI "V1BI") (V2HI "V2BI") (V4HI "V4BI") (V8HI "V8BI") (V16HI "V16BI")
1805 (V32HI "V32BI") (V64HI "V64BI") (V128HI "V128BI") (V256HI "V256BI")
1806 (V512HI "V512BI") (V1024HI "V1024BI") (V2048HI "V2048BI")
1807 (V1SI "V1BI") (V2SI "V2BI") (V4SI "V4BI") (V8SI "V8BI")
1808 (V16SI "V16BI") (V32SI "V32BI") (V64SI "V64BI")
1809 (V128SI "V128BI") (V256SI "V256BI") (V512SI "V512BI") (V1024SI "V1024BI")
1810 (V1DI "V1BI") (V2DI "V2BI") (V4DI "V4BI") (V8DI "V8BI") (V16DI "V16BI") (V32DI "V32BI")
1811 (V64DI "V64BI") (V128DI "V128BI") (V256DI "V256BI") (V512DI "V512BI")
1812 (V1HF "V1BI") (V2HF "V2BI") (V4HF "V4BI") (V8HF "V8BI") (V16HF "V16BI")
1813 (V32HF "V32BI") (V64HF "V64BI") (V128HF "V128BI") (V256HF "V256BI")
1814 (V512HF "V512BI") (V1024HF "V1024BI") (V2048HF "V2048BI")
1815 (V1SF "V1BI") (V2SF "V2BI") (V4SF "V4BI") (V8SF "V8BI")
1816 (V16SF "V16BI") (V32SF "V32BI") (V64SF "V64BI")
1817 (V128SF "V128BI") (V256SF "V256BI") (V512SF "V512BI") (V1024SF "V1024BI")
1818 (V1DF "V1BI") (V2DF "V2BI") (V4DF "V4BI") (V8DF "V8BI") (V16DF "V16BI") (V32DF "V32BI")
1819 (V64DF "V64BI") (V128DF "V128BI") (V256DF "V256BI") (V512DF "V512BI")
f556cd8b
JZZ		 1820])
1821
acb51b5c 1822(define_mode_attr vm [
879c52c9
JZ		 1823 (RVVM8QI "rvvm1bi") (RVVM4QI "rvvmf2bi") (RVVM2QI "rvvmf4bi") (RVVM1QI "rvvmf8bi") (RVVMF2QI "rvvmf16bi") (RVVMF4QI "rvvmf32bi") (RVVMF8QI "rvvmf64bi")
1824
1825 (RVVM8HI "rvvmf2bi") (RVVM4HI "rvvmf4bi") (RVVM2HI "rvvmf8bi") (RVVM1HI "rvvmf16bi") (RVVMF2HI "rvvmf32bi") (RVVMF4HI "rvvmf64bi")
1826
1827 (RVVM8HF "rvvmf2bi") (RVVM4HF "rvvmf4bi") (RVVM2HF "rvvmf8bi") (RVVM1HF "rvvmf16bi") (RVVMF2HF "rvvmf32bi") (RVVMF4HF "rvvmf64bi")
1828
1829 (RVVM8SI "rvvmf4bi") (RVVM4SI "rvvmf8bi") (RVVM2SI "rvvmf16bi") (RVVM1SI "rvvmf32bi") (RVVMF2SI "rvvmf64bi")
1830
1831 (RVVM8SF "rvvmf4bi") (RVVM4SF "rvvmf8bi") (RVVM2SF "rvvmf16bi") (RVVM1SF "rvvmf32bi") (RVVMF2SF "rvvmf64bi")
1832
1833 (RVVM8DI "rvvmf8bi") (RVVM4DI "rvvmf16bi") (RVVM2DI "rvvmf32bi") (RVVM1DI "rvvmf64bi")
1834
1835 (RVVM8DF "rvvmf8bi") (RVVM4DF "rvvmf16bi") (RVVM2DF "rvvmf32bi") (RVVM1DF "rvvmf64bi")
1836
1837 (RVVM1x8QI "rvvmf8bi") (RVVMF2x8QI "rvvmf16bi") (RVVMF4x8QI "rvvmf32bi") (RVVMF8x8QI "rvvmf64bi")
1838 (RVVM1x7QI "rvvmf8bi") (RVVMF2x7QI "rvvmf16bi") (RVVMF4x7QI "rvvmf32bi") (RVVMF8x7QI "rvvmf64bi")
1839 (RVVM1x6QI "rvvmf8bi") (RVVMF2x6QI "rvvmf16bi") (RVVMF4x6QI "rvvmf32bi") (RVVMF8x6QI "rvvmf64bi")
1840 (RVVM1x5QI "rvvmf8bi") (RVVMF2x5QI "rvvmf16bi") (RVVMF4x5QI "rvvmf32bi") (RVVMF8x5QI "rvvmf64bi")
1841 (RVVM2x4QI "rvvmf4bi") (RVVM1x4QI "rvvmf8bi") (RVVMF2x4QI "rvvmf16bi") (RVVMF4x4QI "rvvmf32bi") (RVVMF8x4QI "rvvmf64bi")
1842 (RVVM2x3QI "rvvmf4bi") (RVVM1x3QI "rvvmf8bi") (RVVMF2x3QI "rvvmf16bi") (RVVMF4x3QI "rvvmf32bi") (RVVMF8x3QI "rvvmf64bi")
1843 (RVVM4x2QI "rvvmf2bi") (RVVM2x2QI "rvvmf4bi") (RVVM1x2QI "rvvmf8bi") (RVVMF2x2QI "rvvmf16bi") (RVVMF4x2QI "rvvmf32bi") (RVVMF8x2QI "rvvmf64bi")
1844
1845 (RVVM1x8HI "rvvmf16bi") (RVVMF2x8HI "rvvmf32bi") (RVVMF4x8HI "rvvmf64bi")
1846 (RVVM1x7HI "rvvmf16bi") (RVVMF2x7HI "rvvmf32bi") (RVVMF4x7HI "rvvmf64bi")
1847 (RVVM1x6HI "rvvmf16bi") (RVVMF2x6HI "rvvmf32bi") (RVVMF4x6HI "rvvmf64bi")
1848 (RVVM1x5HI "rvvmf16bi") (RVVMF2x5HI "rvvmf32bi") (RVVMF4x5HI "rvvmf64bi")
1849 (RVVM2x4HI "rvvmf8bi") (RVVM1x4HI "rvvmf16bi") (RVVMF2x4HI "rvvmf32bi") (RVVMF4x4HI "rvvmf64bi")
1850 (RVVM2x3HI "rvvmf8bi") (RVVM1x3HI "rvvmf16bi") (RVVMF2x3HI "rvvmf32bi") (RVVMF4x3HI "rvvmf64bi")
1851 (RVVM4x2HI "rvvmf4bi") (RVVM2x2HI "rvvmf8bi") (RVVM1x2HI "rvvmf16bi") (RVVMF2x2HI "rvvmf32bi") (RVVMF4x2HI "rvvmf64bi")
1852
1853 (RVVM1x8HF "rvvmf16bi") (RVVMF2x8HF "rvvmf32bi") (RVVMF4x8HF "rvvmf64bi")
1854 (RVVM1x7HF "rvvmf16bi") (RVVMF2x7HF "rvvmf32bi") (RVVMF4x7HF "rvvmf64bi")
1855 (RVVM1x6HF "rvvmf16bi") (RVVMF2x6HF "rvvmf32bi") (RVVMF4x6HF "rvvmf64bi")
1856 (RVVM1x5HF "rvvmf16bi") (RVVMF2x5HF "rvvmf32bi") (RVVMF4x5HF "rvvmf64bi")
1857 (RVVM2x4HF "rvvmf8bi") (RVVM1x4HF "rvvmf16bi") (RVVMF2x4HF "rvvmf32bi") (RVVMF4x4HF "rvvmf64bi")
1858 (RVVM2x3HF "rvvmf8bi") (RVVM1x3HF "rvvmf16bi") (RVVMF2x3HF "rvvmf32bi") (RVVMF4x3HF "rvvmf64bi")
1859 (RVVM4x2HF "rvvmf4bi") (RVVM2x2HF "rvvmf8bi") (RVVM1x2HF "rvvmf16bi") (RVVMF2x2HF "rvvmf32bi") (RVVMF4x2HF "rvvmf64bi")
1860
1861 (RVVM1x8SI "rvvmf32bi") (RVVMF2x8SI "rvvmf64bi")
1862 (RVVM1x7SI "rvvmf32bi") (RVVMF2x7SI "rvvmf64bi")
1863 (RVVM1x6SI "rvvmf32bi") (RVVMF2x6SI "rvvmf64bi")
1864 (RVVM1x5SI "rvvmf32bi") (RVVMF2x5SI "rvvmf64bi")
1865 (RVVM2x4SI "rvvmf16bi") (RVVM1x4SI "rvvmf32bi") (RVVMF2x4SI "rvvmf64bi")
1866 (RVVM2x3SI "rvvmf16bi") (RVVM1x3SI "rvvmf32bi") (RVVMF2x3SI "rvvmf64bi")
1867 (RVVM4x2SI "rvvmf4bi") (RVVM2x2SI "rvvmf16bi") (RVVM1x2SI "rvvmf32bi") (RVVMF2x2SI "rvvmf64bi")
1868
1869 (RVVM1x8SF "rvvmf32bi") (RVVMF2x8SF "rvvmf64bi")
1870 (RVVM1x7SF "rvvmf32bi") (RVVMF2x7SF "rvvmf64bi")
1871 (RVVM1x6SF "rvvmf32bi") (RVVMF2x6SF "rvvmf64bi")
1872 (RVVM1x5SF "rvvmf32bi") (RVVMF2x5SF "rvvmf64bi")
1873 (RVVM2x4SF "rvvmf16bi") (RVVM1x4SF "rvvmf32bi") (RVVMF2x4SF "rvvmf64bi")
1874 (RVVM2x3SF "rvvmf16bi") (RVVM1x3SF "rvvmf32bi") (RVVMF2x3SF "rvvmf64bi")
1875 (RVVM4x2SF "rvvmf4bi") (RVVM2x2SF "rvvmf16bi") (RVVM1x2SF "rvvmf32bi") (RVVMF2x2SF "rvvmf64bi")
1876
1877 (RVVM1x8DI "rvvmf64bi")
1878 (RVVM1x7DI "rvvmf64bi")
1879 (RVVM1x6DI "rvvmf64bi")
1880 (RVVM1x5DI "rvvmf64bi")
1881 (RVVM2x4DI "rvvmf32bi")
1882 (RVVM1x4DI "rvvmf64bi")
1883 (RVVM2x3DI "rvvmf32bi")
1884 (RVVM1x3DI "rvvmf64bi")
1885 (RVVM4x2DI "rvvmf16bi")
1886 (RVVM2x2DI "rvvmf32bi")
1887 (RVVM1x2DI "rvvmf64bi")
1888
1889 (RVVM1x8DF "rvvmf64bi")
1890 (RVVM1x7DF "rvvmf64bi")
1891 (RVVM1x6DF "rvvmf64bi")
1892 (RVVM1x5DF "rvvmf64bi")
1893 (RVVM2x4DF "rvvmf32bi")
1894 (RVVM1x4DF "rvvmf64bi")
1895 (RVVM2x3DF "rvvmf32bi")
1896 (RVVM1x3DF "rvvmf64bi")
1897 (RVVM4x2DF "rvvmf16bi")
1898 (RVVM2x2DF "rvvmf32bi")
1899 (RVVM1x2DF "rvvmf64bi")
33b153ff
JZ		 1900
1901 ;; VLS modes.
1902 (V1QI "v1bi") (V2QI "v2bi") (V4QI "v4bi") (V8QI "v8bi") (V16QI "v16bi") (V32QI "v32bi")
1903 (V64QI "v64bi") (V128QI "v128bi") (V256QI "v256bi") (V512QI "v512bi")
1904 (V1024QI "v1024bi") (V2048QI "v2048bi") (V4096QI "v4096bi")
1905 (V1HI "v1bi") (V2HI "v2bi") (V4HI "v4bi") (V8HI "v8bi") (V16HI "v16bi")
1906 (V32HI "v32bi") (V64HI "v64bi") (V128HI "v128bi") (V256HI "v256bi")
1907 (V512HI "v512bi") (V1024HI "v1024bi") (V2048HI "v2048bi")
1908 (V1SI "v1bi") (V2SI "v2bi") (V4SI "v4bi") (V8SI "v8bi")
1909 (V16SI "v16bi") (V32SI "v32bi") (V64SI "v64bi")
1910 (V128SI "v128bi") (V256SI "v256bi") (V512SI "v512bi") (V1024SI "v1024bi")
1911 (V1DI "v1bi") (V2DI "v2bi") (V4DI "v4bi") (V8DI "v8bi") (V16DI "v16bi") (V32DI "v32bi")
1912 (V64DI "v64bi") (V128DI "v128bi") (V256DI "v256bi") (V512DI "v512bi")
1913 (V1HF "v1bi") (V2HF "v2bi") (V4HF "v4bi") (V8HF "v8bi") (V16HF "v16bi")
1914 (V32HF "v32bi") (V64HF "v64bi") (V128HF "v128bi") (V256HF "v256bi")
1915 (V512HF "v512bi") (V1024HF "v1024bi") (V2048HF "v2048bi")
1916 (V1SF "v1bi") (V2SF "v2bi") (V4SF "v4bi") (V8SF "v8bi")
1917 (V16SF "v16bi") (V32SF "v32bi") (V64SF "v64bi")
1918 (V128SF "v128bi") (V256SF "v256bi") (V512SF "v512bi") (V1024SF "v1024bi")
1919 (V1DF "v1bi") (V2DF "v2bi") (V4DF "v4bi") (V8DF "v8bi") (V16DF "v16bi") (V32DF "v32bi")
1920 (V64DF "v64bi") (V128DF "v128bi") (V256DF "v256bi") (V512DF "v512bi")
acb51b5c
JZZ		 1921])
1922
fa144175 1923(define_mode_attr VEL [
879c52c9
JZ		 1924 (RVVM8QI "QI") (RVVM4QI "QI") (RVVM2QI "QI") (RVVM1QI "QI") (RVVMF2QI "QI") (RVVMF4QI "QI") (RVVMF8QI "QI")
1925
1926 (RVVM8HI "HI") (RVVM4HI "HI") (RVVM2HI "HI") (RVVM1HI "HI") (RVVMF2HI "HI") (RVVMF4HI "HI")
1927
1928 (RVVM8HF "HF") (RVVM4HF "HF") (RVVM2HF "HF") (RVVM1HF "HF") (RVVMF2HF "HF") (RVVMF4HF "HF")
1929
1930 (RVVM8SI "SI") (RVVM4SI "SI") (RVVM2SI "SI") (RVVM1SI "SI") (RVVMF2SI "SI")
1931
1932 (RVVM8SF "SF") (RVVM4SF "SF") (RVVM2SF "SF") (RVVM1SF "SF") (RVVMF2SF "SF")
1933
1934 (RVVM8DI "DI") (RVVM4DI "DI") (RVVM2DI "DI") (RVVM1DI "DI")
1935
1936 (RVVM8DF "DF") (RVVM4DF "DF") (RVVM2DF "DF") (RVVM1DF "DF")
33b153ff
JZ		 1937
1938 ;; VLS modes.
1939 (V1QI "QI") (V2QI "QI") (V4QI "QI") (V8QI "QI") (V16QI "QI") (V32QI "QI") (V64QI "QI") (V128QI "QI") (V256QI "QI") (V512QI "QI")
1940 (V1024QI "QI") (V2048QI "QI") (V4096QI "QI")
1941 (V1HI "HI") (V2HI "HI") (V4HI "HI") (V8HI "HI") (V16HI "HI") (V32HI "HI") (V64HI "HI") (V128HI "HI") (V256HI "HI")
1942 (V512HI "HI") (V1024HI "HI") (V2048HI "HI")
1943 (V1SI "SI") (V2SI "SI") (V4SI "SI") (V8SI "SI") (V16SI "SI") (V32SI "SI") (V64SI "SI") (V128SI "SI") (V256SI "SI")
1944 (V512SI "SI") (V1024SI "SI")
1945 (V1DI "DI") (V2DI "DI") (V4DI "DI") (V8DI "DI") (V16DI "DI") (V32DI "DI") (V64DI "DI") (V128DI "DI") (V256DI "DI") (V512DI "DI")
1946 (V1HF "HF") (V2HF "HF") (V4HF "HF") (V8HF "HF") (V16HF "HF") (V32HF "HF") (V64HF "HF") (V128HF "HF") (V256HF "HF")
1947 (V512HF "HF") (V1024HF "HF") (V2048HF "HF")
1948 (V1SF "SF") (V2SF "SF") (V4SF "SF") (V8SF "SF") (V16SF "SF") (V32SF "SF") (V64SF "SF") (V128SF "SF") (V256SF "SF")
1949 (V512SF "SF") (V1024SF "SF")
1950 (V1DF "DF") (V2DF "DF") (V4DF "DF") (V8DF "DF") (V16DF "DF") (V32DF "DF") (V64DF "DF") (V128DF "DF") (V256DF "DF") (V512DF "DF")
fa144175
JZZ		 1951])
1952
68cb873f
LD		 1953(define_mode_attr V_DOUBLE_EXTEND_VEL [
1954 (RVVM4QI "HI") (RVVM2QI "HI") (RVVM1QI "HI") (RVVMF2QI "HI") (RVVMF4QI "HI") (RVVMF8QI "HI")
1955
1956 (RVVM4HI "SI") (RVVM2HI "SI") (RVVM1HI "SI") (RVVMF2HI "SI") (RVVMF4HI "SI")
1957
1958 (RVVM4SI "DI") (RVVM2SI "DI") (RVVM1SI "DI") (RVVMF2SI "DI")
1959
1960 (RVVM4HF "SF") (RVVM2HF "SF") (RVVM1HF "SF") (RVVMF2HF "SF") (RVVMF4HF "SF")
1961
1962 (RVVM4SF "DF") (RVVM2SF "DF") (RVVM1SF "DF") (RVVMF2SF "DF")
1963])
1964
1c1a9d8e 1965(define_mode_attr vel [
879c52c9
JZ		 1966 (RVVM8QI "qi") (RVVM4QI "qi") (RVVM2QI "qi") (RVVM1QI "qi") (RVVMF2QI "qi") (RVVMF4QI "qi") (RVVMF8QI "qi")
1967
1968 (RVVM8HI "hi") (RVVM4HI "hi") (RVVM2HI "hi") (RVVM1HI "hi") (RVVMF2HI "hi") (RVVMF4HI "hi")
1969
1970 (RVVM8HF "hf") (RVVM4HF "hf") (RVVM2HF "hf") (RVVM1HF "hf") (RVVMF2HF "hf") (RVVMF4HF "hf")
1971
1972 (RVVM8SI "si") (RVVM4SI "si") (RVVM2SI "si") (RVVM1SI "si") (RVVMF2SI "si")
1973
1974 (RVVM8SF "sf") (RVVM4SF "sf") (RVVM2SF "sf") (RVVM1SF "sf") (RVVMF2SF "sf")
1975
1976 (RVVM8DI "di") (RVVM4DI "di") (RVVM2DI "di") (RVVM1DI "di")
1977
1978 (RVVM8DF "df") (RVVM4DF "df") (RVVM2DF "df") (RVVM1DF "df")
33b153ff
JZ		 1979
1980 ;; VLS modes.
1981 (V1QI "qi") (V2QI "qi") (V4QI "qi") (V8QI "qi") (V16QI "qi") (V32QI "qi") (V64QI "qi") (V128QI "qi") (V256QI "qi") (V512QI "qi")
1982 (V1024QI "qi") (V2048QI "qi") (V4096QI "qi")
1983 (V1HI "hi") (V2HI "hi") (V4HI "hi") (V8HI "hi") (V16HI "hi") (V32HI "hi") (V64HI "hi") (V128HI "hi") (V256HI "hi")
1984 (V512HI "hi") (V1024HI "hi") (V2048HI "hi")
1985 (V1SI "si") (V2SI "si") (V4SI "si") (V8SI "si") (V16SI "si") (V32SI "si") (V64SI "si") (V128SI "si") (V256SI "si")
1986 (V512SI "si") (V1024SI "si")
1987 (V1DI "di") (V2DI "di") (V4DI "di") (V8DI "di") (V16DI "di") (V32DI "di") (V64DI "di") (V128DI "di") (V256DI "di") (V512DI "di")
1988 (V1HF "hf") (V2HF "hf") (V4HF "hf") (V8HF "hf") (V16HF "hf") (V32HF "hf") (V64HF "hf") (V128HF "hf") (V256HF "hf")
1989 (V512HF "hf") (V1024HF "hf") (V2048HF "hf")
1990 (V1SF "sf") (V2SF "sf") (V4SF "sf") (V8SF "sf") (V16SF "sf") (V32SF "sf") (V64SF "sf") (V128SF "sf") (V256SF "sf")
1991 (V512SF "sf") (V1024SF "sf")
1992 (V1DF "df") (V2DF "df") (V4DF "df") (V8DF "df") (V16DF "df") (V32DF "df") (V64DF "df") (V128DF "df") (V256DF "df") (V512DF "df")
1c1a9d8e
JZ		 1993])
1994
fe578886
JZ		 1995(define_mode_attr vsingle [
1996 (RVVM1x8QI "rvvm1qi") (RVVMF2x8QI "rvvmf2qi") (RVVMF4x8QI "rvvmf4qi") (RVVMF8x8QI "rvvmf8qi")
1997 (RVVM1x7QI "rvvm1qi") (RVVMF2x7QI "rvvmf2qi") (RVVMF4x7QI "rvvmf4qi") (RVVMF8x7QI "rvvmf8qi")
1998 (RVVM1x6QI "rvvm1qi") (RVVMF2x6QI "rvvmf2qi") (RVVMF4x6QI "rvvmf4qi") (RVVMF8x6QI "rvvmf8qi")
1999 (RVVM1x5QI "rvvm1qi") (RVVMF2x5QI "rvvmf2qi") (RVVMF4x5QI "rvvmf4qi") (RVVMF8x5QI "rvvmf8qi")
2000 (RVVM2x4QI "rvvm2qi") (RVVM1x4QI "rvvm1qi") (RVVMF2x4QI "rvvmf2qi") (RVVMF4x4QI "rvvmf4qi") (RVVMF8x4QI "rvvmf8qi")
2001 (RVVM2x3QI "rvvm2qi") (RVVM1x3QI "rvvm1qi") (RVVMF2x3QI "rvvmf2qi") (RVVMF4x3QI "rvvmf4qi") (RVVMF8x3QI "rvvmf8qi")
2002 (RVVM4x2QI "rvvm4qi") (RVVM2x2QI "rvvm1qi") (RVVM1x2QI "rvvm1qi") (RVVMF2x2QI "rvvmf2qi") (RVVMF4x2QI "rvvmf4qi") (RVVMF8x2QI "rvvmf8qi")
2003
2004 (RVVM1x8HI "rvvm1hi") (RVVMF2x8HI "rvvmf2hi") (RVVMF4x8HI "rvvmf4hi")
2005 (RVVM1x7HI "rvvm1hi") (RVVMF2x7HI "rvvmf2hi") (RVVMF4x7HI "rvvmf4hi")
2006 (RVVM1x6HI "rvvm1hi") (RVVMF2x6HI "rvvmf2hi") (RVVMF4x6HI "rvvmf4hi")
2007 (RVVM1x5HI "rvvm1hi") (RVVMF2x5HI "rvvmf2hi") (RVVMF4x5HI "rvvmf4hi")
2008 (RVVM2x4HI "rvvm2hi") (RVVM1x4HI "rvvm1hi") (RVVMF2x4HI "rvvmf2hi") (RVVMF4x4HI "rvvmf4hi")
2009 (RVVM2x3HI "rvvm2hi") (RVVM1x3HI "rvvm1hi") (RVVMF2x3HI "rvvmf2hi") (RVVMF4x3HI "rvvmf4hi")
2010 (RVVM4x2HI "rvvm4hi") (RVVM2x2HI "rvvm2hi") (RVVM1x2HI "rvvm1hi") (RVVMF2x2HI "rvvmf2hi") (RVVMF4x2HI "rvvmf4hi")
2011
2012 (RVVM1x8HF "rvvm1hf")
2013 (RVVMF2x8HF "rvvmf2hf")
2014 (RVVMF4x8HF "rvvmf4hf")
2015 (RVVM1x7HF "rvvm1hf")
2016 (RVVMF2x7HF "rvvmf2hf")
2017 (RVVMF4x7HF "rvvmf4hf")
2018 (RVVM1x6HF "rvvm1hf")
2019 (RVVMF2x6HF "rvvmf2hf")
2020 (RVVMF4x6HF "rvvmf4hf")
2021 (RVVM1x5HF "rvvm1hf")
2022 (RVVMF2x5HF "rvvmf2hf")
2023 (RVVMF4x5HF "rvvmf4hf")
2024 (RVVM2x4HF "rvvm2hf")
2025 (RVVM1x4HF "rvvm1hf")
2026 (RVVMF2x4HF "rvvmf2hf")
2027 (RVVMF4x4HF "rvvmf4hf")
2028 (RVVM2x3HF "rvvm2hf")
2029 (RVVM1x3HF "rvvm1hf")
2030 (RVVMF2x3HF "rvvmf2hf")
2031 (RVVMF4x3HF "rvvmf4hf")
2032 (RVVM4x2HF "rvvm4hf")
2033 (RVVM2x2HF "rvvm2hf")
2034 (RVVM1x2HF "rvvm1hf")
2035 (RVVMF2x2HF "rvvmf2hf")
2036 (RVVMF4x2HF "rvvmf4hf")
2037
2038 (RVVM1x8SI "rvvm1si") (RVVMF2x8SI "rvvmf2si")
2039 (RVVM1x7SI "rvvm1si") (RVVMF2x7SI "rvvmf2si")
2040 (RVVM1x6SI "rvvm1si") (RVVMF2x6SI "rvvmf2si")
2041 (RVVM1x5SI "rvvm1si") (RVVMF2x5SI "rvvmf2si")
2042 (RVVM2x4SI "rvvm2si") (RVVM1x4SI "rvvm1si") (RVVMF2x4SI "rvvmf2si")
2043 (RVVM2x3SI "rvvm2si") (RVVM1x3SI "rvvm1si") (RVVMF2x3SI "rvvmf2si")
2044 (RVVM4x2SI "rvvm4si") (RVVM2x2SI "rvvm2si") (RVVM1x2SI "rvvm1si") (RVVMF2x2SI "rvvmf2si")
2045
2046 (RVVM1x8SF "rvvm1sf")
2047 (RVVMF2x8SF "rvvmf2sf")
2048 (RVVM1x7SF "rvvm1sf")
2049 (RVVMF2x7SF "rvvmf2sf")
2050 (RVVM1x6SF "rvvm1sf")
2051 (RVVMF2x6SF "rvvmf2sf")
2052 (RVVM1x5SF "rvvm1sf")
2053 (RVVMF2x5SF "rvvmf2sf")
2054 (RVVM2x4SF "rvvm2sf")
2055 (RVVM1x4SF "rvvm1sf")
2056 (RVVMF2x4SF "rvvmf2sf")
2057 (RVVM2x3SF "rvvm2sf")
2058 (RVVM1x3SF "rvvm1sf")
2059 (RVVMF2x3SF "rvvmf2sf")
2060 (RVVM4x2SF "rvvm4sf")
2061 (RVVM2x2SF "rvvm2sf")
2062 (RVVM1x2SF "rvvm1sf")
2063 (RVVMF2x2SF "rvvmf2sf")
2064
2065 (RVVM1x8DI "rvvm1di")
2066 (RVVM1x7DI "rvvm1di")
2067 (RVVM1x6DI "rvvm1di")
2068 (RVVM1x5DI "rvvm1di")
2069 (RVVM2x4DI "rvvm2di")
2070 (RVVM1x4DI "rvvm1di")
2071 (RVVM2x3DI "rvvm2di")
2072 (RVVM1x3DI "rvvm1di")
2073 (RVVM4x2DI "rvvm4di")
2074 (RVVM2x2DI "rvvm2di")
2075 (RVVM1x2DI "rvvm1di")
2076
2077 (RVVM1x8DF "rvvm1df")
2078 (RVVM1x7DF "rvvm1df")
2079 (RVVM1x6DF "rvvm1df")
2080 (RVVM1x5DF "rvvm1df")
2081 (RVVM2x4DF "rvvm2df")
2082 (RVVM1x4DF "rvvm1df")
2083 (RVVM2x3DF "rvvm2df")
2084 (RVVM1x3DF "rvvm1df")
2085 (RVVM4x2DF "rvvm4df")
2086 (RVVM2x2DF "rvvm2df")
2087 (RVVM1x2DF "rvvm1df")
2088])
2089
a035d133 2090(define_mode_attr VSUBEL [
879c52c9
JZ		 2091 (RVVM8HI "QI") (RVVM4HI "QI") (RVVM2HI "QI") (RVVM1HI "QI") (RVVMF2HI "QI") (RVVMF4HI "QI")
2092
2093 (RVVM8SI "HI") (RVVM4SI "HI") (RVVM2SI "HI") (RVVM1SI "HI") (RVVMF2SI "HI")
2094
2095 (RVVM8SF "HF") (RVVM4SF "HF") (RVVM2SF "HF") (RVVM1SF "HF") (RVVMF2SF "HF")
2096
2097 (RVVM8DI "SI") (RVVM4DI "SI") (RVVM2DI "SI") (RVVM1DI "SI")
2098
2099 (RVVM8DF "SF") (RVVM4DF "SF") (RVVM2DF "SF") (RVVM1DF "SF")
33b153ff
JZ		 2100
2101 ;; VLS modes.
d05aac04 2102 (V1HI "QI") (V2HI "QI") (V4HI "QI") (V8HI "QI") (V16HI "QI") (V32HI "QI") (V64HI "QI") (V128HI "QI") (V256HI "QI")
33b153ff 2103 (V512HI "QI") (V1024HI "QI") (V2048HI "QI")
d05aac04 2104 (V1SI "HI") (V2SI "HI") (V4SI "HI") (V8SI "HI") (V16SI "HI") (V32SI "HI") (V64SI "HI") (V128SI "HI") (V256SI "HI")
33b153ff 2105 (V512SI "HI") (V1024SI "HI")
d05aac04 2106 (V1DI "SI") (V2DI "SI") (V4DI "SI") (V8DI "SI") (V16DI "SI") (V32DI "SI") (V64DI "SI") (V128DI "SI") (V256DI "SI") (V512DI "SI")
a035d133
JZZ		 2107])
2108
6313b045 2109(define_mode_attr nf [
879c52c9
JZ		 2110 (RVVM1x8QI "8") (RVVMF2x8QI "8") (RVVMF4x8QI "8") (RVVMF8x8QI "8")
2111 (RVVM1x7QI "7") (RVVMF2x7QI "7") (RVVMF4x7QI "7") (RVVMF8x7QI "7")
2112 (RVVM1x6QI "6") (RVVMF2x6QI "6") (RVVMF4x6QI "6") (RVVMF8x6QI "6")
2113 (RVVM1x5QI "5") (RVVMF2x5QI "5") (RVVMF4x5QI "5") (RVVMF8x5QI "5")
2114 (RVVM2x4QI "4") (RVVM1x4QI "4") (RVVMF2x4QI "4") (RVVMF4x4QI "4") (RVVMF8x4QI "4")
2115 (RVVM2x3QI "3") (RVVM1x3QI "3") (RVVMF2x3QI "3") (RVVMF4x3QI "3") (RVVMF8x3QI "3")
2116 (RVVM4x2QI "2") (RVVM2x2QI "2") (RVVM1x2QI "2") (RVVMF2x2QI "2") (RVVMF4x2QI "2") (RVVMF8x2QI "2")
2117
2118 (RVVM1x8HI "8") (RVVMF2x8HI "8") (RVVMF4x8HI "8")
2119 (RVVM1x7HI "7") (RVVMF2x7HI "7") (RVVMF4x7HI "7")
2120 (RVVM1x6HI "6") (RVVMF2x6HI "6") (RVVMF4x6HI "6")
2121 (RVVM1x5HI "5") (RVVMF2x5HI "5") (RVVMF4x5HI "5")
2122 (RVVM2x4HI "4") (RVVM1x4HI "4") (RVVMF2x4HI "4") (RVVMF4x4HI "4")
2123 (RVVM2x3HI "3") (RVVM1x3HI "3") (RVVMF2x3HI "3") (RVVMF4x3HI "3")
2124 (RVVM4x2HI "2") (RVVM2x2HI "2") (RVVM1x2HI "2") (RVVMF2x2HI "2") (RVVMF4x2HI "2")
2125
2126 (RVVM1x8HF "8") (RVVMF2x8HF "8") (RVVMF4x8HF "8")
2127 (RVVM1x7HF "7") (RVVMF2x7HF "7") (RVVMF4x7HF "7")
2128 (RVVM1x6HF "6") (RVVMF2x6HF "6") (RVVMF4x6HF "6")
2129 (RVVM1x5HF "5") (RVVMF2x5HF "5") (RVVMF4x5HF "5")
2130 (RVVM2x4HF "4") (RVVM1x4HF "4") (RVVMF2x4HF "4") (RVVMF4x4HF "4")
2131 (RVVM2x3HF "3") (RVVM1x3HF "3") (RVVMF2x3HF "3") (RVVMF4x3HF "3")
2132 (RVVM4x2HF "2") (RVVM2x2HF "2") (RVVM1x2HF "2") (RVVMF2x2HF "2") (RVVMF4x2HF "2")
2133
2134 (RVVM1x8SI "8") (RVVMF2x8SI "8")
2135 (RVVM1x7SI "7") (RVVMF2x7SI "7")
2136 (RVVM1x6SI "6") (RVVMF2x6SI "6")
2137 (RVVM1x5SI "5") (RVVMF2x5SI "5")
2138 (RVVM2x4SI "4") (RVVM1x4SI "4") (RVVMF2x4SI "4")
2139 (RVVM2x3SI "3") (RVVM1x3SI "3") (RVVMF2x3SI "3")
2140 (RVVM4x2SI "2") (RVVM2x2SI "2") (RVVM1x2SI "2") (RVVMF2x2SI "2")
2141
2142 (RVVM1x8SF "8") (RVVMF2x8SF "8")
2143 (RVVM1x7SF "7") (RVVMF2x7SF "7")
2144 (RVVM1x6SF "6") (RVVMF2x6SF "6")
2145 (RVVM1x5SF "5") (RVVMF2x5SF "5")
2146 (RVVM2x4SF "4") (RVVM1x4SF "4") (RVVMF2x4SF "4")
2147 (RVVM2x3SF "3") (RVVM1x3SF "3") (RVVMF2x3SF "3")
2148 (RVVM4x2SF "2") (RVVM2x2SF "2") (RVVM1x2SF "2") (RVVMF2x2SF "2")
2149
2150 (RVVM1x8DI "8")
2151 (RVVM1x7DI "7")
2152 (RVVM1x6DI "6")
2153 (RVVM1x5DI "5")
2154 (RVVM2x4DI "4")
2155 (RVVM1x4DI "4")
2156 (RVVM2x3DI "3")
2157 (RVVM1x3DI "3")
2158 (RVVM4x2DI "2")
2159 (RVVM2x2DI "2")
2160 (RVVM1x2DI "2")
2161
2162 (RVVM1x8DF "8")
2163 (RVVM1x7DF "7")
2164 (RVVM1x6DF "6")
2165 (RVVM1x5DF "5")
2166 (RVVM2x4DF "4")
2167 (RVVM1x4DF "4")
2168 (RVVM2x3DF "3")
2169 (RVVM1x3DF "3")
2170 (RVVM4x2DF "2")
2171 (RVVM2x2DF "2")
2172 (RVVM1x2DF "2")
6313b045
JZZ		 2173])
2174
f556cd8b 2175(define_mode_attr sew [
879c52c9
JZ		 2176 (RVVM8QI "8") (RVVM4QI "8") (RVVM2QI "8") (RVVM1QI "8") (RVVMF2QI "8") (RVVMF4QI "8") (RVVMF8QI "8")
2177
2178 (RVVM8HI "16") (RVVM4HI "16") (RVVM2HI "16") (RVVM1HI "16") (RVVMF2HI "16") (RVVMF4HI "16")
2179
2180 (RVVM8HF "16") (RVVM4HF "16") (RVVM2HF "16") (RVVM1HF "16") (RVVMF2HF "16") (RVVMF4HF "16")
2181
2182 (RVVM8SI "32") (RVVM4SI "32") (RVVM2SI "32") (RVVM1SI "32") (RVVMF2SI "32")
2183
2184 (RVVM8SF "32") (RVVM4SF "32") (RVVM2SF "32") (RVVM1SF "32") (RVVMF2SF "32")
2185
2186 (RVVM8DI "64") (RVVM4DI "64") (RVVM2DI "64") (RVVM1DI "64")
2187
2188 (RVVM8DF "64") (RVVM4DF "64") (RVVM2DF "64") (RVVM1DF "64")
2189
2190 (RVVM1x8QI "8") (RVVMF2x8QI "8") (RVVMF4x8QI "8") (RVVMF8x8QI "8")
2191 (RVVM1x7QI "8") (RVVMF2x7QI "8") (RVVMF4x7QI "8") (RVVMF8x7QI "8")
2192 (RVVM1x6QI "8") (RVVMF2x6QI "8") (RVVMF4x6QI "8") (RVVMF8x6QI "8")
2193 (RVVM1x5QI "8") (RVVMF2x5QI "8") (RVVMF4x5QI "8") (RVVMF8x5QI "8")
2194 (RVVM2x4QI "8") (RVVM1x4QI "8") (RVVMF2x4QI "8") (RVVMF4x4QI "8") (RVVMF8x4QI "8")
2195 (RVVM2x3QI "8") (RVVM1x3QI "8") (RVVMF2x3QI "8") (RVVMF4x3QI "8") (RVVMF8x3QI "8")
2196 (RVVM4x2QI "8") (RVVM2x2QI "8") (RVVM1x2QI "8") (RVVMF2x2QI "8") (RVVMF4x2QI "8") (RVVMF8x2QI "8")
2197
2198 (RVVM1x8HI "16") (RVVMF2x8HI "16") (RVVMF4x8HI "16")
2199 (RVVM1x7HI "16") (RVVMF2x7HI "16") (RVVMF4x7HI "16")
2200 (RVVM1x6HI "16") (RVVMF2x6HI "16") (RVVMF4x6HI "16")
2201 (RVVM1x5HI "16") (RVVMF2x5HI "16") (RVVMF4x5HI "16")
2202 (RVVM2x4HI "16") (RVVM1x4HI "16") (RVVMF2x4HI "16") (RVVMF4x4HI "16")
2203 (RVVM2x3HI "16") (RVVM1x3HI "16") (RVVMF2x3HI "16") (RVVMF4x3HI "16")
2204 (RVVM4x2HI "16") (RVVM2x2HI "16") (RVVM1x2HI "16") (RVVMF2x2HI "16") (RVVMF4x2HI "16")
2205
2206 (RVVM1x8HF "16") (RVVMF2x8HF "16") (RVVMF4x8HF "16")
2207 (RVVM1x7HF "16") (RVVMF2x7HF "16") (RVVMF4x7HF "16")
2208 (RVVM1x6HF "16") (RVVMF2x6HF "16") (RVVMF4x6HF "16")
2209 (RVVM1x5HF "16") (RVVMF2x5HF "16") (RVVMF4x5HF "16")
2210 (RVVM2x4HF "16") (RVVM1x4HF "16") (RVVMF2x4HF "16") (RVVMF4x4HF "16")
2211 (RVVM2x3HF "16") (RVVM1x3HF "16") (RVVMF2x3HF "16") (RVVMF4x3HF "16")
2212 (RVVM4x2HF "16") (RVVM2x2HF "16") (RVVM1x2HF "16") (RVVMF2x2HF "16") (RVVMF4x2HF "16")
2213
2214 (RVVM1x8SI "32") (RVVMF2x8SI "32")
2215 (RVVM1x7SI "32") (RVVMF2x7SI "32")
2216 (RVVM1x6SI "32") (RVVMF2x6SI "32")
2217 (RVVM1x5SI "32") (RVVMF2x5SI "32")
2218 (RVVM2x4SI "32") (RVVM1x4SI "32") (RVVMF2x4SI "32")
2219 (RVVM2x3SI "32") (RVVM1x3SI "32") (RVVMF2x3SI "32")
2220 (RVVM4x2SI "32") (RVVM2x2SI "32") (RVVM1x2SI "32") (RVVMF2x2SI "32")
2221
2222 (RVVM1x8SF "32") (RVVMF2x8SF "32")
2223 (RVVM1x7SF "32") (RVVMF2x7SF "32")
2224 (RVVM1x6SF "32") (RVVMF2x6SF "32")
2225 (RVVM1x5SF "32") (RVVMF2x5SF "32")
2226 (RVVM2x4SF "32") (RVVM1x4SF "32") (RVVMF2x4SF "32")
2227 (RVVM2x3SF "32") (RVVM1x3SF "32") (RVVMF2x3SF "32")
2228 (RVVM4x2SF "32") (RVVM2x2SF "32") (RVVM1x2SF "32") (RVVMF2x2SF "32")
2229
2230 (RVVM1x8DI "64")
2231 (RVVM1x7DI "64")
2232 (RVVM1x6DI "64")
2233 (RVVM1x5DI "64")
2234 (RVVM2x4DI "64")
2235 (RVVM1x4DI "64")
2236 (RVVM2x3DI "64")
2237 (RVVM1x3DI "64")
2238 (RVVM4x2DI "64")
2239 (RVVM2x2DI "64")
2240 (RVVM1x2DI "64")
2241
2242 (RVVM1x8DF "64")
2243 (RVVM1x7DF "64")
2244 (RVVM1x6DF "64")
2245 (RVVM1x5DF "64")
2246 (RVVM2x4DF "64")
2247 (RVVM1x4DF "64")
2248 (RVVM2x3DF "64")
2249 (RVVM1x3DF "64")
2250 (RVVM4x2DF "64")
2251 (RVVM2x2DF "64")
2252 (RVVM1x2DF "64")
33b153ff
JZ		 2253
2254 ;; VLS modes.
2255 (V1QI "8") (V2QI "8") (V4QI "8") (V8QI "8") (V16QI "8") (V32QI "8") (V64QI "8") (V128QI "8") (V256QI "8") (V512QI "8")
2256 (V1024QI "8") (V2048QI "8") (V4096QI "8")
2257 (V1HI "16") (V2HI "16") (V4HI "16") (V8HI "16") (V16HI "16") (V32HI "16") (V64HI "16") (V128HI "16") (V256HI "16")
2258 (V512HI "16") (V1024HI "16") (V2048HI "16")
2259 (V1SI "32") (V2SI "32") (V4SI "32") (V8SI "32") (V16SI "32") (V32SI "32") (V64SI "32") (V128SI "32") (V256SI "32")
2260 (V512SI "32") (V1024SI "32")
2261 (V1DI "64") (V2DI "64") (V4DI "64") (V8DI "64") (V16DI "64") (V32DI "64") (V64DI "64") (V128DI "64") (V256DI "64") (V512DI "64")
2262 (V1HF "16") (V2HF "16") (V4HF "16") (V8HF "16") (V16HF "16") (V32HF "16") (V64HF "16") (V128HF "16") (V256HF "16")
2263 (V512HF "16") (V1024HF "16") (V2048HF "16")
2264 (V1SF "32") (V2SF "32") (V4SF "32") (V8SF "32") (V16SF "32") (V32SF "32") (V64SF "32") (V128SF "32") (V256SF "32")
2265 (V512SF "32") (V1024SF "32")
2266 (V1DF "64") (V2DF "64") (V4DF "64") (V8DF "64") (V16DF "64") (V32DF "64") (V64DF "64") (V128DF "64") (V256DF "64") (V512DF "64")
f556cd8b 2267])
6c9bcb6c 2268
ab7bb445 2269(define_mode_attr double_trunc_sew [
879c52c9
JZ		 2270 (RVVM8HI "8") (RVVM4HI "8") (RVVM2HI "8") (RVVM1HI "8") (RVVMF2HI "8") (RVVMF4HI "8")
2271
2272 (RVVM8HF "8") (RVVM4HF "8") (RVVM2HF "8") (RVVM1HF "8") (RVVMF2HF "8") (RVVMF4HF "8")
2273
2274 (RVVM8SI "16") (RVVM4SI "16") (RVVM2SI "16") (RVVM1SI "16") (RVVMF2SI "16")
2275
2276 (RVVM8SF "16") (RVVM4SF "16") (RVVM2SF "16") (RVVM1SF "16") (RVVMF2SF "16")
2277
2278 (RVVM8DI "32") (RVVM4DI "32") (RVVM2DI "32") (RVVM1DI "32")
2279
2280 (RVVM8DF "32") (RVVM4DF "32") (RVVM2DF "32") (RVVM1DF "32")
ab7bb445
JZZ		 2281])
2282
2283(define_mode_attr quad_trunc_sew [
879c52c9
JZ		 2284 (RVVM8SI "8") (RVVM4SI "8") (RVVM2SI "8") (RVVM1SI "8") (RVVMF2SI "8")
2285
2286 (RVVM8SF "8") (RVVM4SF "8") (RVVM2SF "8") (RVVM1SF "8") (RVVMF2SF "8")
2287
2288 (RVVM8DI "16") (RVVM4DI "16") (RVVM2DI "16") (RVVM1DI "16")
2289
2290 (RVVM8DF "16") (RVVM4DF "16") (RVVM2DF "16") (RVVM1DF "16")
ab7bb445
JZZ		 2291])
2292
2293(define_mode_attr oct_trunc_sew [
879c52c9
JZ		 2294 (RVVM8DI "8") (RVVM4DI "8") (RVVM2DI "8") (RVVM1DI "8")
2295
2296 (RVVM8DF "8") (RVVM4DF "8") (RVVM2DF "8") (RVVM1DF "8")
ab7bb445
JZZ		 2297])
2298
2299(define_mode_attr double_ext_sew [
879c52c9
JZ		 2300 (RVVM4QI "16") (RVVM2QI "16") (RVVM1QI "16") (RVVMF2QI "16") (RVVMF4QI "16") (RVVMF8QI "16")
2301
2302 (RVVM4HI "32") (RVVM2HI "32") (RVVM1HI "32") (RVVMF2HI "32") (RVVMF4HI "32")
2303
2304 (RVVM4HF "32") (RVVM2HF "32") (RVVM1HF "32") (RVVMF2HF "32") (RVVMF4HF "32")
2305
2306 (RVVM4SI "64") (RVVM2SI "64") (RVVM1SI "64") (RVVMF2SI "64")
2307
2308 (RVVM4SF "64") (RVVM2SF "64") (RVVM1SF "64") (RVVMF2SF "64")
ab7bb445
JZZ		 2309])
2310
2311(define_mode_attr quad_ext_sew [
879c52c9
JZ		 2312 (RVVM2QI "32") (RVVM1QI "32") (RVVMF2QI "32") (RVVMF4QI "32") (RVVMF8QI "32")
2313
2314 (RVVM2HI "64") (RVVM1HI "64") (RVVMF2HI "64") (RVVMF4HI "64")
2315
2316 (RVVM2HF "64") (RVVM1HF "64") (RVVMF2HF "64") (RVVMF4HF "64")
ab7bb445
JZZ		 2317])
2318
2319(define_mode_attr oct_ext_sew [
879c52c9 2320 (RVVM1QI "64") (RVVMF2QI "64") (RVVMF4QI "64") (RVVMF8QI "64")
ab7bb445
JZZ		 2321])
2322
68cb873f
LD		 2323(define_mode_attr V_DOUBLE_EXTEND [
2324 (RVVM4QI "RVVM8HI") (RVVM2QI "RVVM4HI") (RVVM1QI "RVVM2HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVMF2HI") (RVVMF8QI "RVVMF4HI")
2325
2326 (RVVM4HI "RVVM8SI") (RVVM2HI "RVVM4SI") (RVVM1HI "RVVM2SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVMF2SI")
2327
2328 (RVVM4SI "RVVM8DI") (RVVM2SI "RVVM4DI") (RVVM1SI "RVVM2DI") (RVVMF2SI "RVVM1DI")
2329
2330 (RVVM4HF "RVVM8SF") (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVMF2SF")
2331
2332 (RVVM4SF "RVVM8DF") (RVVM2SF "RVVM4DF") (RVVM1SF "RVVM2DF") (RVVMF2SF "RVVM1DF")
2333])
2334
99fa5d94 2335(define_mode_attr V_DOUBLE_TRUNC [
879c52c9
JZ		 2336 (RVVM8HI "RVVM4QI") (RVVM4HI "RVVM2QI") (RVVM2HI "RVVM1QI") (RVVM1HI "RVVMF2QI") (RVVMF2HI "RVVMF4QI") (RVVMF4HI "RVVMF8QI")
2337
2338 (RVVM8SI "RVVM4HI") (RVVM4SI "RVVM2HI") (RVVM2SI "RVVM1HI") (RVVM1SI "RVVMF2HI") (RVVMF2SI "RVVMF4HI")
2339
2340 (RVVM8SF "RVVM4HF") (RVVM4SF "RVVM2HF") (RVVM2SF "RVVM1HF") (RVVM1SF "RVVMF2HF") (RVVMF2SF "RVVMF4HF")
5c9cffa3 2341
879c52c9
JZ		 2342 (RVVM8DI "RVVM4SI") (RVVM4DI "RVVM2SI") (RVVM2DI "RVVM1SI") (RVVM1DI "RVVMF2SI")
2343
2344 (RVVM8DF "RVVM4SF") (RVVM4DF "RVVM2SF") (RVVM2DF "RVVM1SF") (RVVM1DF "RVVMF2SF")
bea89f78
JZ		 2345
2346 (V1HI "V1QI")
2347 (V2HI "V2QI")
2348 (V4HI "V4QI")
2349 (V8HI "V8QI")
2350 (V16HI "V16QI")
2351 (V32HI "V32QI")
2352 (V64HI "V64QI")
2353 (V128HI "V128QI")
2354 (V256HI "V256QI")
2355 (V512HI "V512QI")
2356 (V1024HI "V1024QI")
2357 (V2048HI "V2048QI")
2358 (V1SI "V1HI")
2359 (V2SI "V2HI")
2360 (V4SI "V4HI")
2361 (V8SI "V8HI")
2362 (V16SI "V16HI")
2363 (V32SI "V32HI")
2364 (V64SI "V64HI")
2365 (V128SI "V128HI")
2366 (V256SI "V256HI")
2367 (V512SI "V512HI")
2368 (V1024SI "V1024HI")
2369 (V1DI "V1SI")
2370 (V2DI "V2SI")
2371 (V4DI "V4SI")
2372 (V8DI "V8SI")
2373 (V16DI "V16SI")
2374 (V32DI "V32SI")
2375 (V64DI "V64SI")
2376 (V128DI "V128SI")
2377 (V256DI "V256SI")
2378 (V512DI "V512SI")
b3439785
JZ		 2379 (V1SF "V1HF")
2380 (V2SF "V2HF")
2381 (V4SF "V4HF")
2382 (V8SF "V8HF")
2383 (V16SF "V16HF")
2384 (V32SF "V32HF")
2385 (V64SF "V64HF")
2386 (V128SF "V128HF")
2387 (V256SF "V256HF")
2388 (V512SF "V512HF")
2389 (V1024SF "V1024HF")
2390 (V1DF "V1SF")
2391 (V2DF "V2SF")
2392 (V4DF "V4SF")
2393 (V8DF "V8SF")
2394 (V16DF "V16SF")
2395 (V32DF "V32SF")
2396 (V64DF "V64SF")
2397 (V128DF "V128SF")
2398 (V256DF "V256SF")
2399 (V512DF "V512SF")
99fa5d94
JZZ		 2400])
2401
2402(define_mode_attr V_QUAD_TRUNC [
879c52c9
JZ		 2403 (RVVM8SI "RVVM2QI") (RVVM4SI "RVVM1QI") (RVVM2SI "RVVMF2QI") (RVVM1SI "RVVMF4QI") (RVVMF2SI "RVVMF8QI")
2404
2405 (RVVM8DI "RVVM2HI") (RVVM4DI "RVVM1HI") (RVVM2DI "RVVMF2HI") (RVVM1DI "RVVMF4HI")
a9b40612 2406
879c52c9 2407 (RVVM8DF "RVVM2HF") (RVVM4DF "RVVM1HF") (RVVM2DF "RVVMF2HF") (RVVM1DF "RVVMF4HF")
bea89f78
JZ		 2408
2409 (V1SI "V1QI")
2410 (V2SI "V2QI")
2411 (V4SI "V4QI")
2412 (V8SI "V8QI")
2413 (V16SI "V16QI")
2414 (V32SI "V32QI")
2415 (V64SI "V64QI")
2416 (V128SI "V128QI")
2417 (V256SI "V256QI")
2418 (V512SI "V512QI")
2419 (V1024SI "V1024QI")
2420 (V1DI "V1HI")
2421 (V2DI "V2HI")
2422 (V4DI "V4HI")
2423 (V8DI "V8HI")
2424 (V16DI "V16HI")
2425 (V32DI "V32HI")
2426 (V64DI "V64HI")
2427 (V128DI "V128HI")
2428 (V256DI "V256HI")
2429 (V512DI "V512HI")
b3439785
JZ		 2430 (V1DF "V1HF")
2431 (V2DF "V2HF")
2432 (V4DF "V4HF")
2433 (V8DF "V8HF")
2434 (V16DF "V16HF")
2435 (V32DF "V32HF")
2436 (V64DF "V64HF")
2437 (V128DF "V128HF")
2438 (V256DF "V256HF")
2439 (V512DF "V512HF")
99fa5d94
JZZ		 2440])
2441
2442(define_mode_attr V_OCT_TRUNC [
879c52c9 2443 (RVVM8DI "RVVM1QI") (RVVM4DI "RVVMF2QI") (RVVM2DI "RVVMF4QI") (RVVM1DI "RVVMF8QI")
bea89f78
JZ		 2444
2445 (V1DI "V1QI")
2446 (V2DI "V2QI")
2447 (V4DI "V4QI")
2448 (V8DI "V8QI")
2449 (V16DI "V16QI")
2450 (V32DI "V32QI")
2451 (V64DI "V64QI")
2452 (V128DI "V128QI")
2453 (V256DI "V256QI")
2454 (V512DI "V512QI")
25907509
RD		 2455])
2456
2457; Again in lower case.
2458(define_mode_attr v_double_trunc [
879c52c9
JZ		 2459 (RVVM8HI "rvvm4qi") (RVVM4HI "rvvm2qi") (RVVM2HI "rvvm1qi") (RVVM1HI "rvvmf2qi") (RVVMF2HI "rvvmf4qi") (RVVMF4HI "rvvmf8qi")
2460
2461 (RVVM8SI "rvvm4hi") (RVVM4SI "rvvm2hi") (RVVM2SI "rvvm1hi") (RVVM1SI "rvvmf2hi") (RVVMF2SI "rvvmf4hi")
2462
2463 (RVVM8SF "rvvm4hf") (RVVM4SF "rvvm2hf") (RVVM2SF "rvvm1hf") (RVVM1SF "rvvmf2hf") (RVVMF2SF "rvvmf4hf")
2464
2465 (RVVM8DI "rvvm4si") (RVVM4DI "rvvm2si") (RVVM2DI "rvvm1si") (RVVM1DI "rvvmf2si")
2466
2467 (RVVM8DF "rvvm4sf") (RVVM4DF "rvvm2sf") (RVVM2DF "rvvm1sf") (RVVM1DF "rvvmf2sf")
bea89f78
JZ		 2468
2469 (V1HI "v1qi")
2470 (V2HI "v2qi")
2471 (V4HI "v4qi")
2472 (V8HI "v8qi")
2473 (V16HI "v16qi")
2474 (V32HI "v32qi")
2475 (V64HI "v64qi")
2476 (V128HI "v128qi")
2477 (V256HI "v256qi")
2478 (V512HI "v512qi")
2479 (V1024HI "v1024qi")
2480 (V2048HI "v2048qi")
2481 (V1SI "v1hi")
2482 (V2SI "v2hi")
2483 (V4SI "v4hi")
2484 (V8SI "v8hi")
2485 (V16SI "v16hi")
2486 (V32SI "v32hi")
2487 (V64SI "v64hi")
2488 (V128SI "v128hi")
2489 (V256SI "v256hi")
2490 (V512SI "v512hi")
2491 (V1024SI "v1024hi")
2492 (V1DI "v1si")
2493 (V2DI "v2si")
2494 (V4DI "v4si")
2495 (V8DI "v8si")
2496 (V16DI "v16si")
2497 (V32DI "v32si")
2498 (V64DI "v64si")
2499 (V128DI "v128si")
2500 (V256DI "v256si")
2501 (V512DI "v512si")
b3439785
JZ		 2502 (V1SF "v1hf")
2503 (V2SF "v2hf")
2504 (V4SF "v4hf")
2505 (V8SF "v8hf")
2506 (V16SF "v16hf")
2507 (V32SF "v32hf")
2508 (V64SF "v64hf")
2509 (V128SF "v128hf")
2510 (V256SF "v256hf")
2511 (V512SF "v512hf")
2512 (V1024SF "v1024hf")
2513 (V1DF "v1sf")
2514 (V2DF "v2sf")
2515 (V4DF "v4sf")
2516 (V8DF "v8sf")
2517 (V16DF "v16sf")
2518 (V32DF "v32sf")
2519 (V64DF "v64sf")
2520 (V128DF "v128sf")
2521 (V256DF "v256sf")
2522 (V512DF "v512sf")
25907509
RD		 2523])
2524
2525(define_mode_attr v_quad_trunc [
879c52c9
JZ		 2526 (RVVM8SI "rvvm2qi") (RVVM4SI "rvvm1qi") (RVVM2SI "rvvmf2qi") (RVVM1SI "rvvmf4qi") (RVVMF2SI "rvvmf8qi")
2527
2528 (RVVM8DI "rvvm2hi") (RVVM4DI "rvvm1hi") (RVVM2DI "rvvmf2hi") (RVVM1DI "rvvmf4hi")
a9b40612 2529
879c52c9 2530 (RVVM8DF "rvvm2hf") (RVVM4DF "rvvm1hf") (RVVM2DF "rvvmf2hf") (RVVM1DF "rvvmf4hf")
bea89f78
JZ		 2531
2532 (V1SI "v1qi")
2533 (V2SI "v2qi")
2534 (V4SI "v4qi")
2535 (V8SI "v8qi")
2536 (V16SI "v16qi")
2537 (V32SI "v32qi")
2538 (V64SI "v64qi")
2539 (V128SI "v128qi")
2540 (V256SI "v256qi")
2541 (V512SI "v512qi")
2542 (V1024SI "v1024qi")
2543 (V1DI "v1hi")
2544 (V2DI "v2hi")
2545 (V4DI "v4hi")
2546 (V8DI "v8hi")
2547 (V16DI "v16hi")
2548 (V32DI "v32hi")
2549 (V64DI "v64hi")
2550 (V128DI "v128hi")
2551 (V256DI "v256hi")
2552 (V512DI "v512hi")
b3439785
JZ		 2553 (V1DF "v1hf")
2554 (V2DF "v2hf")
2555 (V4DF "v4hf")
2556 (V8DF "v8hf")
2557 (V16DF "v16hf")
2558 (V32DF "v32hf")
2559 (V64DF "v64hf")
2560 (V128DF "v128hf")
2561 (V256DF "v256hf")
2562 (V512DF "v512hf")
25907509
RD		 2563])
2564
2565(define_mode_attr v_oct_trunc [
879c52c9 2566 (RVVM8DI "rvvm1qi") (RVVM4DI "rvvmf2qi") (RVVM2DI "rvvmf4qi") (RVVM1DI "rvvmf8qi")
bea89f78
JZ		 2567
2568 (V1DI "v1qi")
2569 (V2DI "v2qi")
2570 (V4DI "v4qi")
2571 (V8DI "v8qi")
2572 (V16DI "v16qi")
2573 (V32DI "v32qi")
2574 (V64DI "v64qi")
2575 (V128DI "v128qi")
2576 (V256DI "v256qi")
2577 (V512DI "v512qi")
99fa5d94
JZZ		 2578])
2579
ab7bb445 2580(define_mode_attr VINDEX_DOUBLE_TRUNC [
879c52c9
JZ		 2581 (RVVM8HI "RVVM4QI") (RVVM4HI "RVVM2QI") (RVVM2HI "RVVM1QI") (RVVM1HI "RVVMF2QI") (RVVMF2HI "RVVMF4QI") (RVVMF4HI "RVVMF8QI")
2582
2583 (RVVM8HF "RVVM4QI") (RVVM4HF "RVVM2QI") (RVVM2HF "RVVM1QI") (RVVM1HF "RVVMF2QI") (RVVMF2HF "RVVMF4QI") (RVVMF4HF "RVVMF8QI")
2584
2585 (RVVM8SI "RVVM4HI") (RVVM4SI "RVVM2HI") (RVVM2SI "RVVM1HI") (RVVM1SI "RVVMF2HI") (RVVMF2SI "RVVMF4HI")
2586
2587 (RVVM8SF "RVVM4HI") (RVVM4SF "RVVM2HI") (RVVM2SF "RVVM1HI") (RVVM1SF "RVVMF2HI") (RVVMF2SF "RVVMF4HI")
2588
2589 (RVVM8DI "RVVM4SI") (RVVM4DI "RVVM2SI") (RVVM2DI "RVVM1SI") (RVVM1DI "RVVMF2SI")
2590
2591 (RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI") (RVVM1DF "RVVMF2SI")
ab7bb445
JZZ		 2592])
2593
2594(define_mode_attr VINDEX_QUAD_TRUNC [
879c52c9
JZ		 2595 (RVVM8SI "RVVM2QI") (RVVM4SI "RVVM1QI") (RVVM2SI "RVVMF2QI") (RVVM1SI "RVVMF4QI") (RVVMF2SI "RVVMF8QI")
2596
2597 (RVVM8SF "RVVM2QI") (RVVM4SF "RVVM1QI") (RVVM2SF "RVVMF2QI") (RVVM1SF "RVVMF4QI") (RVVMF2SF "RVVMF8QI")
2598
2599 (RVVM8DI "RVVM2HI") (RVVM4DI "RVVM1HI") (RVVM2DI "RVVMF2HI") (RVVM1DI "RVVMF4HI")
2600
2601 (RVVM8DF "RVVM2HI") (RVVM4DF "RVVM1HI") (RVVM2DF "RVVMF2HI") (RVVM1DF "RVVMF4HI")
ab7bb445
JZZ		 2602])
2603
2604(define_mode_attr VINDEX_OCT_TRUNC [
879c52c9
JZ		 2605 (RVVM8DI "RVVM1QI") (RVVM4DI "RVVMF2QI") (RVVM2DI "RVVMF4QI") (RVVM1DI "RVVMF8QI")
2606
2607 (RVVM8DF "RVVM1QI") (RVVM4DF "RVVMF2QI") (RVVM2DF "RVVMF4QI") (RVVM1DF "RVVMF8QI")
ab7bb445
JZZ		 2608])
2609
2610(define_mode_attr VINDEX_DOUBLE_EXT [
879c52c9
JZ		 2611 (RVVM4QI "RVVM8HI") (RVVM2QI "RVVM4HI") (RVVM1QI "RVVM2HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVMF2HI") (RVVMF8QI "RVVMF4HI")
2612
2613 (RVVM4HI "RVVM8SI") (RVVM2HI "RVVM4SI") (RVVM1HI "RVVM2SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVMF2SI")
2614
2615 (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI") (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI")
2616
2617 (RVVM4SI "RVVM8DI") (RVVM2SI "RVVM4DI") (RVVM1SI "RVVM2DI") (RVVMF2SI "RVVM1DI")
2618
2619 (RVVM4SF "RVVM8DI") (RVVM2SF "RVVM4DI") (RVVM1SF "RVVM2DI") (RVVMF2SF "RVVM1DI")
ab7bb445
JZZ		 2620])
2621
2622(define_mode_attr VINDEX_QUAD_EXT [
879c52c9
JZ		 2623 (RVVM2QI "RVVM8SI") (RVVM1QI "RVVM4SI") (RVVMF2QI "RVVM2SI") (RVVMF4QI "RVVM1SI") (RVVMF8QI "RVVMF2SI")
2624
2625 (RVVM2HI "RVVM8DI") (RVVM1HI "RVVM4DI") (RVVMF2HI "RVVM2DI") (RVVMF4HI "RVVM1DI")
2626
2627 (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI") (RVVMF4HF "RVVM1DI")
ab7bb445
JZZ		 2628])
2629
2630(define_mode_attr VINDEX_OCT_EXT [
879c52c9 2631 (RVVM1QI "RVVM8DI") (RVVMF2QI "RVVM4DI") (RVVMF4QI "RVVM2DI") (RVVMF8QI "RVVM1DI")
ab7bb445
JZZ		 2632])
2633
dc244cdc 2634(define_mode_attr VCONVERT [
879c52c9
JZ		 2635 (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI")
2636 (RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI") (RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI")
2637 (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") (RVVM1DF "RVVM1DI")
dc244cdc
JZZ		 2638])
2639
52577a30 2640(define_mode_attr vconvert [
879c52c9
JZ		 2641 (RVVM8HF "rvvm8hi") (RVVM4HF "rvvm4hi") (RVVM2HF "rvvm2hi") (RVVM1HF "rvvm1hi") (RVVMF2HF "rvvmf2hi") (RVVMF4HF "rvvmf4hi")
2642 (RVVM8SF "rvvm8si") (RVVM4SF "rvvm4si") (RVVM2SF "rvvm2si") (RVVM1SF "rvvm1si") (RVVMF2SF "rvvmf2si")
2643 (RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di") (RVVM1DF "rvvm1di")
52577a30
JZ		 2644])
2645
dc244cdc 2646(define_mode_attr VNCONVERT [
879c52c9
JZ		 2647 (RVVM8HF "RVVM4QI") (RVVM4HF "RVVM2QI") (RVVM2HF "RVVM1QI") (RVVM1HF "RVVMF2QI") (RVVMF2HF "RVVMF4QI") (RVVMF4HF "RVVMF8QI")
2648
2649 (RVVM8SI "RVVM4HF") (RVVM4SI "RVVM2HF") (RVVM2SI "RVVM1HF") (RVVM1SI "RVVMF2HF") (RVVMF2SI "RVVMF4HF")
2650 (RVVM8SF "RVVM4HI") (RVVM4SF "RVVM2HI") (RVVM2SF "RVVM1HI") (RVVM1SF "RVVMF2HI") (RVVMF2SF "RVVMF4HI")
2651
2652 (RVVM8DI "RVVM4SF") (RVVM4DI "RVVM2SF") (RVVM2DI "RVVM1SF") (RVVM1DI "RVVMF2SF")
2653 (RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI") (RVVM1DF "RVVMF2SI")
dc244cdc
JZZ		 2654])
2655
5fad4da8 2656(define_mode_attr vnconvert [
879c52c9
JZ		 2657 (RVVM8HF "rvvm4qi") (RVVM4HF "rvvm2qi") (RVVM2HF "rvvm1qi") (RVVM1HF "rvvmf2qi") (RVVMF2HF "rvvmf4qi") (RVVMF4HF "rvvmf8qi")
2658
2659 (RVVM8SI "rvvm4hf") (RVVM4SI "rvvm2hf") (RVVM2SI "rvvm1hf") (RVVM1SI "rvvmf2hf") (RVVMF2SI "rvvmf4hf")
2660 (RVVM8SF "rvvm4hi") (RVVM4SF "rvvm2hi") (RVVM2SF "rvvm1hi") (RVVM1SF "rvvmf2hi") (RVVMF2SF "rvvmf4hi")
2661
2662 (RVVM8DI "rvvm4sf") (RVVM4DI "rvvm2sf") (RVVM2DI "rvvm1sf") (RVVM1DI "rvvmf2sf")
2663 (RVVM8DF "rvvm4si") (RVVM4DF "rvvm2si") (RVVM2DF "rvvm1si") (RVVM1DF "rvvmf2si")
5fad4da8
RD		 2664])
2665
1bff101b 2666(define_mode_attr VDEMOTE [
879c52c9 2667 (RVVM8DI "RVVM8SI") (RVVM4DI "RVVM4SI") (RVVM2DI "RVVM2SI") (RVVM1DI "RVVM1SI")
d05aac04
JZ		 2668 (V1DI "V1SI")
2669 (V2DI "V2SI")
2670 (V4DI "V4SI")
2671 (V8DI "V8SI")
2672 (V16DI "V16SI")
2673 (V32DI "V32SI")
2674 (V64DI "V64SI")
2675 (V128DI "V128SI")
2676 (V256DI "V256SI")
2677 (V512DI "V512SI")
1bff101b
JZZ		 2678])
2679
2680(define_mode_attr VMDEMOTE [
879c52c9 2681 (RVVM8DI "RVVMF4BI") (RVVM4DI "RVVMF8BI") (RVVM2DI "RVVMF16BI") (RVVM1DI "RVVMF32BI")
d05aac04
JZ		 2682 (V1DI "V1BI")
2683 (V2DI "V2BI")
2684 (V4DI "V4BI")
2685 (V8DI "V8BI")
2686 (V16DI "V16BI")
2687 (V32DI "V32BI")
2688 (V64DI "V64BI")
2689 (V128DI "V128BI")
2690 (V256DI "V256BI")
2691 (V512DI "V512BI")
1bff101b
JZZ		 2692])
2693
f048af2a 2694(define_mode_attr gs_extension [
879c52c9
JZ		 2695 (RVVM8QI "const_1_operand") (RVVM4QI "vector_gs_extension_operand")
2696 (RVVM2QI "immediate_operand") (RVVM1QI "immediate_operand") (RVVMF2QI "immediate_operand")
2697 (RVVMF4QI "immediate_operand") (RVVMF8QI "immediate_operand")
2698
2699 (RVVM8HI "const_1_operand") (RVVM4HI "vector_gs_extension_operand")
2700 (RVVM2HI "immediate_operand") (RVVM1HI "immediate_operand")
2701 (RVVMF2HI "immediate_operand") (RVVMF4HI "immediate_operand")
f048af2a 2702
879c52c9
JZ		 2703 (RVVM8HF "const_1_operand") (RVVM4HF "vector_gs_extension_operand")
2704 (RVVM2HF "immediate_operand") (RVVM1HF "immediate_operand")
2705 (RVVMF2HF "immediate_operand") (RVVMF4HF "immediate_operand")
2706
2707 (RVVM8SI "vector_gs_extension_operand") (RVVM4SI "immediate_operand") (RVVM2SI "immediate_operand")
2708 (RVVM1SI "immediate_operand") (RVVMF2SI "immediate_operand")
2709
2710 (RVVM8SF "vector_gs_extension_operand") (RVVM4SF "immediate_operand") (RVVM2SF "immediate_operand")
2711 (RVVM1SF "immediate_operand") (RVVMF2SF "immediate_operand")
2712
2713 (RVVM8DI "immediate_operand") (RVVM4DI "immediate_operand")
2714 (RVVM2DI "immediate_operand") (RVVM1DI "immediate_operand")
2715
2716 (RVVM8DF "immediate_operand") (RVVM4DF "immediate_operand")
2717 (RVVM2DF "immediate_operand") (RVVM1DF "immediate_operand")
f048af2a
JZZ		 2718])
2719
2720(define_mode_attr gs_scale [
879c52c9
JZ		 2721 (RVVM8QI "const_1_operand") (RVVM4QI "const_1_operand")
2722 (RVVM2QI "const_1_operand") (RVVM1QI "const_1_operand") (RVVMF2QI "const_1_operand")
2723 (RVVMF4QI "const_1_operand") (RVVMF8QI "const_1_operand")
2724
2725 (RVVM8HI "const_1_operand") (RVVM4HI "vector_gs_scale_operand_16_rv32")
2726 (RVVM2HI "vector_gs_scale_operand_16") (RVVM1HI "vector_gs_scale_operand_16")
2727 (RVVMF2HI "vector_gs_scale_operand_16") (RVVMF4HI "vector_gs_scale_operand_16")
2728
2729 (RVVM8HF "const_1_operand") (RVVM4HF "vector_gs_scale_operand_16_rv32")
2730 (RVVM2HF "vector_gs_scale_operand_16") (RVVM1HF "vector_gs_scale_operand_16")
2731 (RVVMF2HF "vector_gs_scale_operand_16") (RVVMF4HF "vector_gs_scale_operand_16")
2732
2733 (RVVM8SI "vector_gs_scale_operand_32_rv32") (RVVM4SI "vector_gs_scale_operand_32") (RVVM2SI "vector_gs_scale_operand_32")
2734 (RVVM1SI "vector_gs_scale_operand_32") (RVVMF2SI "vector_gs_scale_operand_32")
2735
2736 (RVVM8SF "vector_gs_scale_operand_32_rv32") (RVVM4SF "vector_gs_scale_operand_32") (RVVM2SF "vector_gs_scale_operand_32")
2737 (RVVM1SF "vector_gs_scale_operand_32") (RVVMF2SF "vector_gs_scale_operand_32")
2738
2739 (RVVM8DI "vector_gs_scale_operand_64") (RVVM4DI "vector_gs_scale_operand_64")
2740 (RVVM2DI "vector_gs_scale_operand_64") (RVVM1DI "vector_gs_scale_operand_64")
2741
2742 (RVVM8DF "vector_gs_scale_operand_64") (RVVM4DF "vector_gs_scale_operand_64")
2743 (RVVM2DF "vector_gs_scale_operand_64") (RVVM1DF "vector_gs_scale_operand_64")
f048af2a
JZZ		 2744])
2745
6c9bcb6c
JZZ		 2746(define_int_iterator ORDER [UNSPEC_ORDERED UNSPEC_UNORDERED])
2747
8340bbad
JZZ		 2748(define_int_iterator VMULH [UNSPEC_VMULHS UNSPEC_VMULHU UNSPEC_VMULHSU])
2749
e09418f2
JZZ		 2750(define_int_iterator VNCLIP [UNSPEC_VNCLIP UNSPEC_VNCLIPU])
2751
1bff101b
JZZ		 2752(define_int_iterator VSLIDES [UNSPEC_VSLIDEUP UNSPEC_VSLIDEDOWN])
2753(define_int_iterator VSLIDES1 [UNSPEC_VSLIDE1UP UNSPEC_VSLIDE1DOWN])
2754(define_int_iterator VFSLIDES1 [UNSPEC_VFSLIDE1UP UNSPEC_VFSLIDE1DOWN])
2755
e09418f2
JZZ		 2756(define_int_iterator VSAT_OP [UNSPEC_VAADDU UNSPEC_VAADD
2757 UNSPEC_VASUBU UNSPEC_VASUB UNSPEC_VSMUL
2758 UNSPEC_VSSRL UNSPEC_VSSRA])
2759
2760(define_int_iterator VSAT_ARITH_OP [UNSPEC_VAADDU UNSPEC_VAADD
2761 UNSPEC_VASUBU UNSPEC_VASUB UNSPEC_VSMUL])
2762(define_int_iterator VSAT_SHIFT_OP [UNSPEC_VSSRL UNSPEC_VSSRA])
2763
1ed93bc7
JZZ		 2764(define_int_iterator VMISC [UNSPEC_VMSBF UNSPEC_VMSIF UNSPEC_VMSOF])
2765
469711f0
PL		 2766(define_int_iterator VFMISC [UNSPEC_VFRSQRT7])
2767
2768(define_int_iterator VFMISC_FRM [UNSPEC_VFREC7])
dc244cdc
JZZ		 2769
2770(define_int_iterator VFCVTS [UNSPEC_VFCVT UNSPEC_UNSIGNED_VFCVT])
2771
6c9bcb6c
JZZ		 2772(define_int_attr order [
2773 (UNSPEC_ORDERED "o") (UNSPEC_UNORDERED "u")
6223ea76
LD		 2774 (UNSPEC_REDUC_SUM_ORDERED "o") (UNSPEC_REDUC_SUM_UNORDERED "u")
2775 (UNSPEC_WREDUC_SUM_ORDERED "o") (UNSPEC_WREDUC_SUM_UNORDERED "u")
6c9bcb6c 2776])
8340bbad 2777
e09418f2 2778(define_int_attr v_su [(UNSPEC_VMULHS "") (UNSPEC_VMULHU "u") (UNSPEC_VMULHSU "su")
dc244cdc 2779 (UNSPEC_VNCLIP "") (UNSPEC_VNCLIPU "u")
6223ea76 2780 (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")])
e09418f2
JZZ		 2781(define_int_attr sat_op [(UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd")
2782 (UNSPEC_VASUBU "asubu") (UNSPEC_VASUB "asub")
2783 (UNSPEC_VSMUL "smul") (UNSPEC_VSSRL "ssrl")
2784 (UNSPEC_VSSRA "ssra")])
2785(define_int_attr sat_insn_type [(UNSPEC_VAADDU "vaalu") (UNSPEC_VAADD "vaalu")
2786 (UNSPEC_VASUBU "vaalu") (UNSPEC_VASUB "vaalu")
2787 (UNSPEC_VSMUL "vsmul") (UNSPEC_VSSRL "vsshift")
2788 (UNSPEC_VSSRA "vsshift") (UNSPEC_VNCLIP "vnclip")
2789 (UNSPEC_VNCLIPU "vnclip")])
2a937fb5 2790
dc244cdc 2791(define_int_attr misc_op [(UNSPEC_VMSBF "sbf") (UNSPEC_VMSIF "sif") (UNSPEC_VMSOF "sof")
469711f0
PL		 2792 (UNSPEC_VFRSQRT7 "rsqrt7")])
2793
2794(define_int_attr misc_frm_op [(UNSPEC_VFREC7 "rec7")])
2795
2796(define_int_attr float_insn_type [(UNSPEC_VFRSQRT7 "vfsqrt")])
dc244cdc 2797
469711f0 2798(define_int_attr float_frm_insn_type [(UNSPEC_VFREC7 "vfrecp")])
dc244cdc 2799
b95dcaa5 2800(define_int_iterator VCOPYSIGNS [UNSPEC_VCOPYSIGN UNSPEC_VXORSIGN])
dc244cdc 2801
b95dcaa5 2802(define_int_attr copysign [(UNSPEC_VCOPYSIGN "copysign") (UNSPEC_VXORSIGN "xorsign")])
dc244cdc 2803
b95dcaa5 2804(define_int_attr nx [(UNSPEC_VCOPYSIGN "") (UNSPEC_VXORSIGN "x")])
1ed93bc7 2805
1bff101b
JZZ		 2806(define_int_attr ud [(UNSPEC_VSLIDEUP "up") (UNSPEC_VSLIDEDOWN "down")
2807 (UNSPEC_VSLIDE1UP "1up") (UNSPEC_VSLIDE1DOWN "1down")
2808 (UNSPEC_VFSLIDE1UP "1up") (UNSPEC_VFSLIDE1DOWN "1down")])
2809
2219aed9
JZZ		 2810(define_int_attr ud_constraint [(UNSPEC_VSLIDEUP "=&vr,&vr,&vr,&vr") (UNSPEC_VSLIDEDOWN "=vd,vd,vr,vr")
2811 (UNSPEC_VSLIDE1UP "=&vr,&vr,&vr,&vr") (UNSPEC_VSLIDE1DOWN "=vd,vd,vr,vr")
2812 (UNSPEC_VFSLIDE1UP "=&vr,&vr,&vr,&vr") (UNSPEC_VFSLIDE1DOWN "=vd,vd,vr,vr")])
1bff101b
JZZ		 2813
2814(define_int_attr UNSPEC [(UNSPEC_VSLIDE1UP "UNSPEC_VSLIDE1UP")
2815 (UNSPEC_VSLIDE1DOWN "UNSPEC_VSLIDE1DOWN")])
2816
2a937fb5
JZZ		 2817(define_code_iterator any_int_binop [plus minus and ior xor ashift ashiftrt lshiftrt
2818 smax umax smin umin mult div udiv mod umod
2819])
2820
d7f8c79a
JZZ		 2821(define_code_iterator any_int_unop [neg not])
2822
a035d133
JZZ		 2823(define_code_iterator any_commutative_binop [plus and ior xor
2824 smax umax smin umin mult
2825])
2826
2827(define_code_iterator any_non_commutative_binop [minus div udiv mod umod])
2828
8c08201f
RD		 2829(define_code_iterator any_int_binop_no_shift
2830 [plus minus and ior xor smax umax smin umin mult div udiv mod umod
2831])
2832
7ad729a0
JZZ		 2833(define_code_iterator any_sat_int_binop [ss_plus ss_minus us_plus us_minus])
2834(define_code_iterator sat_int_plus_binop [ss_plus us_plus])
2835(define_code_iterator sat_int_minus_binop [ss_minus us_minus])
2836
c0a70df6
LD		 2837(define_code_iterator mulh [smul_highpart umul_highpart])
2838(define_code_attr mulh_table [(smul_highpart "smul") (umul_highpart "umul")])
2839(define_code_attr MULH_UNSPEC [(smul_highpart "UNSPEC_VMULHS") (umul_highpart "UNSPEC_VMULHU")])
2840
a1e42094
JZZ		 2841(define_code_iterator any_widen_binop [plus minus mult])
2842(define_code_iterator plus_minus [plus minus])
2843
0e271517
JZZ		 2844(define_code_attr madd_msub [(plus "madd") (minus "msub")])
2845(define_code_attr macc_msac [(plus "macc") (minus "msac")])
2846(define_code_attr nmsub_nmadd [(plus "nmsub") (minus "nmadd")])
2847(define_code_attr nmsac_nmacc [(plus "nmsac") (minus "nmacc")])
6271a072 2848
69424293
RD		 2849(define_code_attr ext_to_rshift [(sign_extend "ashiftrt")
2850 (zero_extend "lshiftrt")])
2851(define_code_attr EXT_TO_RSHIFT [(sign_extend "ASHIFTRT")
2852 (zero_extend "LSHIFTRT")])
2853
acb51b5c 2854(define_code_iterator and_ior [and ior])
dc244cdc 2855
8cd140d3
JZ		 2856(define_code_iterator any_float_binop [plus mult minus div])
2857(define_code_iterator any_float_binop_nofrm [smax smin])
2858(define_code_iterator commutative_float_binop [plus mult])
2859(define_code_iterator commutative_float_binop_nofrm [smax smin])
dc244cdc 2860(define_code_iterator non_commutative_float_binop [minus div])
8cd140d3
JZ		 2861(define_code_iterator any_float_unop [sqrt])
2862(define_code_iterator any_float_unop_nofrm [neg abs])
dc244cdc
JZZ		 2863
2864(define_code_iterator any_fix [fix unsigned_fix])
2865(define_code_iterator any_float [float unsigned_float])
c878c658 2866
dc244cdc
JZZ		 2867(define_code_attr fix_cvt [(fix "fix_trunc") (unsigned_fix "fixuns_trunc")])
2868(define_code_attr float_cvt [(float "float") (unsigned_float "floatuns")])
2869
acb51b5c
JZZ		 2870(define_code_attr ninsn [(and "nand") (ior "nor") (xor "xnor")])
2871
2a937fb5
JZZ		 2872(define_code_attr binop_rhs1_predicate [
2873 (plus "register_operand")
2874 (minus "vector_arith_operand")
2875 (ior "register_operand")
2876 (xor "register_operand")
2877 (and "register_operand")
2878 (ashift "register_operand")
2879 (ashiftrt "register_operand")
2880 (lshiftrt "register_operand")
2881 (smin "register_operand")
2882 (smax "register_operand")
2883 (umin "register_operand")
2884 (umax "register_operand")
2885 (mult "register_operand")
2886 (div "register_operand")
2887 (mod "register_operand")
2888 (udiv "register_operand")
7ad729a0
JZZ		 2889 (umod "register_operand")
2890 (ss_plus "register_operand")
2891 (us_plus "register_operand")
2892 (ss_minus "register_operand")
2893 (us_minus "register_operand")])
2a937fb5
JZZ		 2894
2895(define_code_attr binop_rhs2_predicate [
2896 (plus "vector_arith_operand")
2897 (minus "vector_neg_arith_operand")
2898 (ior "vector_arith_operand")
2899 (xor "vector_arith_operand")
2900 (and "vector_arith_operand")
2901 (ashift "vector_shift_operand")
2902 (ashiftrt "vector_shift_operand")
2903 (lshiftrt "vector_shift_operand")
2904 (smin "register_operand")
2905 (smax "register_operand")
2906 (umin "register_operand")
2907 (umax "register_operand")
2908 (mult "register_operand")
2909 (div "register_operand")
2910 (mod "register_operand")
2911 (udiv "register_operand")
7ad729a0
JZZ		 2912 (umod "register_operand")
2913 (ss_plus "vector_arith_operand")
2914 (us_plus "vector_arith_operand")
2915 (ss_minus "vector_neg_arith_operand")
2916 (us_minus "register_operand")])
2a937fb5
JZZ		 2917
2918(define_code_attr binop_rhs1_constraint [
ab7bb445
JZZ		 2919 (plus "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2920 (minus "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi")
2921 (ior "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2922 (xor "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2923 (and "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2924 (ashift "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2925 (ashiftrt "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2926 (lshiftrt "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2927 (smin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2928 (smax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2929 (umin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2930 (umax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2931 (mult "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2932 (div "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2933 (mod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2934 (udiv "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2935 (umod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")])
2a937fb5
JZZ		 2936
2937(define_code_attr binop_rhs2_constraint [
ab7bb445
JZZ		 2938 (plus "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
2939 (minus "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr")
2940 (ior "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
2941 (xor "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
2942 (and "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
2943 (ashift "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr")
2944 (ashiftrt "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr")
2945 (lshiftrt "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr")
2946 (smin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2947 (smax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2948 (umin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2949 (umax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2950 (mult "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2951 (div "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2952 (mod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2953 (udiv "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2954 (umod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
2955 (ss_plus "vr,vr,vr,vr,vi,vi,vi,vi")
2956 (us_plus "vr,vr,vr,vr,vi,vi,vi,vi")
2957 (ss_minus "vr,vr,vr,vr,vj,vj,vj,vj")
2958 (us_minus "vr,vr,vr,vr,vr,vr,vr,vr")])
2a937fb5
JZZ		 2959
2960(define_code_attr int_binop_insn_type [
2961 (plus "vialu")
2962 (minus "vialu")
2963 (ior "vialu")
2964 (xor "vialu")
2965 (and "vialu")
2966 (ashift "vshift")
2967 (ashiftrt "vshift")
2968 (lshiftrt "vshift")
acb51b5c
JZZ		 2969 (smin "viminmax")
2970 (smax "viminmax")
2971 (umin "viminmax")
2972 (umax "viminmax")
2a937fb5
JZZ		 2973 (mult "vimul")
2974 (div "vidiv")
2975 (mod "vidiv")
2976 (udiv "vidiv")
7ad729a0
JZZ		 2977 (umod "vidiv")
2978 (ss_plus "vsalu")
2979 (us_plus "vsalu")
2980 (ss_minus "vsalu")
2981 (us_minus "vsalu")])
2a937fb5 2982
a1e42094
JZZ		 2983(define_code_attr widen_binop_insn_type [
2984 (plus "walu")
2985 (minus "walu")
2986 (mult "wmul")])
2987
dc244cdc
JZZ		 2988(define_code_attr float_insn_type [
2989 (plus "vfalu")
2990 (mult "vfmul")
2991 (smax "vfminmax")
2992 (smin "vfminmax")
2993 (minus "vfalu")
2994 (div "vfdiv")
2995 (neg "vfsgnj")
2996 (abs "vfsgnj")
2997 (sqrt "vfsqrt")])
2998
7ad729a0 2999;; <binop_vi_variant_insn> expands to the insn name of binop matching constraint rhs1 is immediate.
2a937fb5 3000;; minus is negated as vadd and ss_minus is negated as vsadd, others remain <insn>.
7ad729a0 3001(define_code_attr binop_vi_variant_insn [(ashift "sll.vi")
2a937fb5
JZZ		 3002 (ashiftrt "sra.vi")
3003 (lshiftrt "srl.vi")
3004 (div "div.vv")
3005 (mod "rem.vv")
3006 (udiv "divu.vv")
3007 (umod "remu.vv")
a035d133
JZZ		 3008 (ior "or.vi")
3009 (xor "xor.vi")
3010 (and "and.vi")
2a937fb5
JZZ		 3011 (plus "add.vi")
3012 (minus "add.vi")
3013 (smin "min.vv")
3014 (smax "max.vv")
3015 (umin "minu.vv")
3016 (umax "maxu.vv")
7ad729a0
JZZ		 3017 (mult "mul.vv")
3018 (ss_plus "sadd.vi")
3019 (us_plus "saddu.vi")
3020 (ss_minus "sadd.vi")
3021 (us_minus "ssubu.vv")])
2a937fb5 3022
7ad729a0 3023;; <binop_reverse_vi_variant_insn> expands to the insn name of binop matching constraint rhs2 is immediate.
2a937fb5 3024;; minus is reversed as vrsub, others remain <insn>.
7ad729a0 3025(define_code_attr binop_reverse_vi_variant_insn [(ashift "sll.vv")
2a937fb5
JZZ		 3026 (ashiftrt "sra.vv")
3027 (lshiftrt "srl.vv")
3028 (div "div.vv")
3029 (mod "rem.vv")
3030 (udiv "divu.vv")
3031 (umod "remu.vv")
3032 (ior "or.vv")
3033 (xor "xor.vv")
3034 (and "and.vv")
3035 (plus "add.vv")
3036 (minus "rsub.vi")
3037 (smin "min.vv")
3038 (smax "max.vv")
3039 (umin "minu.vv")
3040 (umax "maxu.vv")
3041 (mult "mul.vv")])
3042
7ad729a0 3043(define_code_attr binop_vi_variant_op [(ashift "%3,%v4")
f3a10f4f
JZZ		 3044 (ashiftrt "%3,%v4")
3045 (lshiftrt "%3,%v4")
2a937fb5
JZZ		 3046 (div "%3,%4")
3047 (mod "%3,%4")
3048 (udiv "%3,%4")
3049 (umod "%3,%4")
a035d133
JZZ		 3050 (ior "%3,%v4")
3051 (xor "%3,%v4")
3052 (and "%3,%v4")
f3a10f4f 3053 (plus "%3,%v4")
2a937fb5
JZZ		 3054 (minus "%3,%V4")
3055 (smin "%3,%4")
3056 (smax "%3,%4")
3057 (umin "%3,%4")
3058 (umax "%3,%4")
7ad729a0
JZZ		 3059 (mult "%3,%4")
3060 (ss_plus "%3,%v4")
3061 (us_plus "%3,%v4")
3062 (ss_minus "%3,%V4")
3063 (us_minus "%3,%4")])
2a937fb5 3064
7ad729a0 3065(define_code_attr binop_reverse_vi_variant_op [(ashift "%3,%4")
2a937fb5
JZZ		 3066 (ashiftrt "%3,%4")
3067 (lshiftrt "%3,%4")
3068 (div "%3,%4")
3069 (mod "%3,%4")
3070 (udiv "%3,%4")
3071 (umod "%3,%4")
3072 (ior "%3,%4")
3073 (xor "%3,%4")
3074 (and "%3,%4")
3075 (plus "%3,%4")
3076 (minus "%4,%v3")
3077 (smin "%3,%4")
3078 (smax "%3,%4")
3079 (umin "%3,%4")
3080 (umax "%3,%4")
3081 (mult "%3,%4")])
99fa5d94
JZZ		 3082
3083(define_code_attr sz [(sign_extend "s") (zero_extend "z")])
33b153ff
JZ		 3084
3085;; VLS modes.
3086(define_mode_iterator VLS [
3087 (V1QI "TARGET_VECTOR_VLS")
3088 (V2QI "TARGET_VECTOR_VLS")
3089 (V4QI "TARGET_VECTOR_VLS")
3090 (V8QI "TARGET_VECTOR_VLS")
3091 (V16QI "TARGET_VECTOR_VLS")
3092 (V32QI "TARGET_VECTOR_VLS")
3093 (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3094 (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3095 (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3096 (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3097 (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3098 (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3099 (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
3100 (V1HI "TARGET_VECTOR_VLS")
3101 (V2HI "TARGET_VECTOR_VLS")
3102 (V4HI "TARGET_VECTOR_VLS")
3103 (V8HI "TARGET_VECTOR_VLS")
3104 (V16HI "TARGET_VECTOR_VLS")
3105 (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3106 (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3107 (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3108 (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3109 (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3110 (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3111 (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
3112 (V1SI "TARGET_VECTOR_VLS")
3113 (V2SI "TARGET_VECTOR_VLS")
3114 (V4SI "TARGET_VECTOR_VLS")
3115 (V8SI "TARGET_VECTOR_VLS")
3116 (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3117 (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3118 (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3119 (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3120 (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3121 (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3122 (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
3123 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
3124 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
3125 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
3126 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
3127 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
3128 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
3129 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
3130 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
3131 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
3132 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
3133 (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3134 (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3135 (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3136 (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3137 (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3138 (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
3139 (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
3140 (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
3141 (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
3142 (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
3143 (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
3144 (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
3145 (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3146 (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3147 (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3148 (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3149 (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
3150 (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
3151 (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
3152 (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
3153 (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
3154 (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
3155 (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
3156 (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
3157 (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
3158 (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
3159 (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
3160 (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
3161 (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
3162 (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
3163 (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
3164 (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
3165 (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")])
3166
4ab2520e
JZ		 3167(define_mode_iterator VLSB [
3168 (V1BI "TARGET_VECTOR_VLS")
3169 (V2BI "TARGET_VECTOR_VLS")
3170 (V4BI "TARGET_VECTOR_VLS")
3171 (V8BI "TARGET_VECTOR_VLS")
3172 (V16BI "TARGET_VECTOR_VLS")
3173 (V32BI "TARGET_VECTOR_VLS")
3174 (V64BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3175 (V128BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3176 (V256BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3177 (V512BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3178 (V1024BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3179 (V2048BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3180 (V4096BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")])
3181
33b153ff
JZ		 3182;; VLS modes that has NUNITS < 32.
3183(define_mode_iterator VLS_AVL_IMM [
3184 (V1QI "TARGET_VECTOR_VLS")
3185 (V2QI "TARGET_VECTOR_VLS")
3186 (V4QI "TARGET_VECTOR_VLS")
3187 (V8QI "TARGET_VECTOR_VLS")
3188 (V16QI "TARGET_VECTOR_VLS")
3189 (V1HI "TARGET_VECTOR_VLS")
3190 (V2HI "TARGET_VECTOR_VLS")
3191 (V4HI "TARGET_VECTOR_VLS")
3192 (V8HI "TARGET_VECTOR_VLS")
3193 (V16HI "TARGET_VECTOR_VLS")
3194 (V1SI "TARGET_VECTOR_VLS")
3195 (V2SI "TARGET_VECTOR_VLS")
3196 (V4SI "TARGET_VECTOR_VLS")
3197 (V8SI "TARGET_VECTOR_VLS")
3198 (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3199 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
3200 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
3201 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
3202 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
3203 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
3204 (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3205 (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3206 (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3207 (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3208 (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16")
3209 (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3210 (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3211 (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3212 (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3213 (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
3214 (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
3215 (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
3216 (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
3217 (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
6aba1fa7
JZ		 3218 (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
3219
3220 (V1BI "TARGET_VECTOR_VLS")
3221 (V2BI "TARGET_VECTOR_VLS")
3222 (V4BI "TARGET_VECTOR_VLS")
3223 (V8BI "TARGET_VECTOR_VLS")
3224 (V16BI "TARGET_VECTOR_VLS")])
33b153ff
JZ		 3225
3226;; VLS modes that has NUNITS >= 32.
3227(define_mode_iterator VLS_AVL_REG [
3228 (V32QI "TARGET_VECTOR_VLS")
3229 (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3230 (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3231 (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3232 (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3233 (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3234 (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3235 (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
3236 (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3237 (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3238 (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3239 (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3240 (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3241 (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3242 (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
3243 (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3244 (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3245 (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3246 (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3247 (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3248 (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
3249 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
3250 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
3251 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
3252 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
3253 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
3254 (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
3255 (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
3256 (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
3257 (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
3258 (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
3259 (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
3260 (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
3261 (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
3262 (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
3263 (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
3264 (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
3265 (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
3266 (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
3267 (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
3268 (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
3269 (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
3270 (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
6aba1fa7
JZ		 3271 (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
3272
3273 (V32BI "TARGET_VECTOR_VLS")
3274 (V64BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3275 (V128BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3276 (V256BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3277 (V512BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3278 (V1024BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3279 (V2048BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3280 (V4096BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")])
9cba4fce
JZ		 3281
3282(define_mode_iterator VLSI [
3283 (V1QI "TARGET_VECTOR_VLS")
3284 (V2QI "TARGET_VECTOR_VLS")
3285 (V4QI "TARGET_VECTOR_VLS")
3286 (V8QI "TARGET_VECTOR_VLS")
3287 (V16QI "TARGET_VECTOR_VLS")
3288 (V32QI "TARGET_VECTOR_VLS")
3289 (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3290 (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3291 (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3292 (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3293 (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3294 (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3295 (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
3296 (V1HI "TARGET_VECTOR_VLS")
3297 (V2HI "TARGET_VECTOR_VLS")
3298 (V4HI "TARGET_VECTOR_VLS")
3299 (V8HI "TARGET_VECTOR_VLS")
3300 (V16HI "TARGET_VECTOR_VLS")
3301 (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3302 (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3303 (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3304 (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3305 (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3306 (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3307 (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
3308 (V1SI "TARGET_VECTOR_VLS")
3309 (V2SI "TARGET_VECTOR_VLS")
3310 (V4SI "TARGET_VECTOR_VLS")
3311 (V8SI "TARGET_VECTOR_VLS")
3312 (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
3313 (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
3314 (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
3315 (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
3316 (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
3317 (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
3318 (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
3319 (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
3320 (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
3321 (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
3322 (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
3323 (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
3324 (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
3325 (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
3326 (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
3327 (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
3328 (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")])
ed60ffd8
PL		 3329
3330(define_mode_iterator VLSF [
d05aac04
JZ		 3331 (V1HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
3332 (V2HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
3333 (V4HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
3334 (V8HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
3335 (V16HF "TARGET_VECTOR_VLS && TARGET_ZVFH")
3336 (V32HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
3337 (V64HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
3338 (V128HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
3339 (V256HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
3340 (V512HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
3341 (V1024HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
3342 (V2048HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096")
ed60ffd8
PL		 3343 (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3344 (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3345 (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3346 (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")
3347 (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
3348 (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
3349 (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
3350 (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
3351 (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
3352 (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
3353 (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
3354 (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
3355 (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
3356 (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
3357 (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
3358 (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
3359 (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
3360 (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
3361 (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
3362 (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
3363 (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
3364])
Mirror of https://gcc.gnu.org/git/gcc.git