[thirdparty/gcc.git] / gcc / config / rl78 / rl78-real.md

;;  Machine Description for Renesas RL78 processors
;;  Copyright (C) 2011-2014 Free Software Foundation, Inc.
;;  Contributed by Red Hat.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.

;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.
\f
;; The insns in this file correspond to the actual opcodes the RL78
;; can issue with real registers.  All insns in here should be
;; conditional on rl78_real_insns_ok() returning true, and should
;; allow virtual registers in their predicates - the reorg pass that
;; allocates physical registers uses the constraints to select
;; registers, but insns with virtual registers MUST match one of these
;; patterns - other than the constraints - so that the operand info is
;; properly set up for the alloc pass.

;;---------- Moving ------------------------

(define_insn "movqi_es"
  [(set (reg:QI ES_REG)
	(match_operand:QI 0 "register_operand" "a"))]
  ""
  "mov\tes, %0"
)

(define_insn "movqi_cs"
  [(set (reg:QI CS_REG)
	(match_operand:QI 0 "register_operand" "a"))]
  ""
  "mov\tcs, %0"
)

(define_insn "*movqi_real"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=g,RaxbcWab,RaxbcWab,a,                          bcx,R, WabWd2WhlWh1WhbWbcWs1v, bcx")
	(match_operand    1 "general_operand"      "0,K,        M,       RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a,                      R"))]
  "rl78_real_insns_ok ()"
  "@
   ; mov\t%0, %1
   oneb\t%0
   clrb\t%0
   mov\t%0, %1
   mov\t%0, %1
   mov\t%0, %1
   mov\t%0, %1
   mov\t%0, %S1"
)

(define_insn "*movhi_real"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=g,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
	(match_operand:HI 1 "general_operand"      " 0,K, M, i,  BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS,  ABDT"))]
  "rl78_real_insns_ok ()"
  "@
   ; movw\t%0, %1
   onew\t%0
   clrw\t%0
   movw\t%0, %1
   movw\t%0, %1
   movw\t%0, %1
   movw\t%0, %S1
   movw\t%0, %1
   movw\t%0, %1"
)

;;---------- Conversions ------------------------

(define_insn "*zero_extendqihi2_real"
  [(set (match_operand:HI                 0 "nonimmediate_operand" "=rv,A")
	(zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))]
  "rl78_real_insns_ok ()"
  "@
   mov\t%Q0, #0
   mov\tx, a \;mov\ta, #0"
  )

(define_insn "*extendqihi2_real"
  [(set (match_operand:HI                 0 "nonimmediate_operand" "=A,A")
	(sign_extend:HI (match_operand:QI 1 "general_operand" "x,a")))]
  "rl78_real_insns_ok ()"
  "@
   shlw\t%0, 8 \;sarw\t%0, 8
   sarw\t%0, 8"
  )

;;---------- Arithmetic ------------------------

(define_insn "*addqi3_real"
  [(set (match_operand:QI          0 "nonimmediate_operand"  "=rvWabWhlWh1,rvWabWhlWh1,a,*bcdehl")
	(plus:QI (match_operand:QI 1 "general_operand"  "%0,0,0,0")
		 (match_operand:QI 2 "general_operand" "K,L,RWhlWh1i,a")))
   ]
  "rl78_real_insns_ok ()"
  "@
    inc\t%0
    dec\t%0
    add\t%0, %2
    add\t%0, %2"
)

(define_insn "*addhi3_real"
  [(set (match_operand:HI          0 "nonimmediate_operand"  "=vABDTWh1Wab,vABDTWh1Wab,v,v,A,S,S,A")
	(plus:HI (match_operand:HI 1 "general_operand"  "%0,0,0,0,0,0,0,S")
		 (match_operand:HI 2 "general_operand" "K,L,N,O,RWh1WhlWabiv,Int8,J,Ri")))
   ]
  "rl78_real_insns_ok ()"
  "@
   incw\t%0
   decw\t%0
   incw\t%0 \;incw\t%0
   decw\t%0 \;decw\t%0
   addw\t%0, %p2
   addw\t%0, %2
   subw\t%0, %m2
   movw\t%0, %1 \;addw\t%0, %2"
)

(define_insn "*addqihi3a_real"
  [(set (match_operand:HI          0 "register_operand"  "=r")
	(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand"  "%r"))
		 (match_operand:HI 2 "register_operand" "r")))
   ]
  "rl78_real_insns_ok ()"
  "add\t%q0, %q1 \;addc\t%Q0, #0"
)

(define_insn "*subqi3_real"
  [(set (match_operand:QI           0 "nonimmediate_operand"  "=a,R,v")
	(minus:QI (match_operand:QI 1 "general_operand"  "0,0,0")
		  (match_operand:QI 2 "general_operand" "RiWabWhbWh1Whl,a,i")))
   ]
  "rl78_real_insns_ok ()"
  "sub\t%0, %2"
)

(define_insn "*subhi3_real"
  [(set (match_operand:HI           0 "nonimmediate_operand"  "=A,S")
	(minus:HI (match_operand:HI 1 "general_operand"  "0,0")
		  (match_operand:HI 2 "general_operand" "iBDTWabWh1v,i")))
   ]
  "rl78_real_insns_ok ()"
  "subw\t%0, %2"
)

(define_insn "*umulhi3_shift_real"
  [(set (match_operand:HI 0 "register_operand" "=A,A")
        (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "0,0")
                 (match_operand:HI 2 "rl78_24_operand" "N,i")))]
  "rl78_real_insns_ok ()"
  "@
   shlw\t%0, 1
   shlw\t%0, 2"
)

(define_insn "*umulqihi3_real"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=A")
        (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%a"))
                 (zero_extend:HI (match_operand:QI 2 "general_operand" "x"))))]
  "rl78_real_insns_ok ()"
  "mulu\t%2"
)

(define_insn "*andqi3_real"
  [(set (match_operand:QI         0 "nonimmediate_operand"  "=A,R,v")
	(and:QI (match_operand:QI 1 "general_operand"       "%0,0,0")
		(match_operand:QI 2 "general_operand"       "iRvWabWhbWh1Whl,A,i")))
   ]
  "rl78_real_insns_ok ()"
  "and\t%0, %2"
)

(define_insn "*iorqi3_real"
  [(set (match_operand:QI         0 "nonimmediate_operand"  "=A,R,v")
	(ior:QI (match_operand:QI 1 "general_operand"       "%0,0,0")
		(match_operand:QI 2 "general_operand"       "iRvWabWhbWh1Whl,A,i")))
   ]
  "rl78_real_insns_ok ()"
  "or\t%0, %2"
)

(define_insn "*xorqi3_real"
  [(set (match_operand:QI         0 "nonimmediate_operand"  "=A,R,v")
	(xor:QI (match_operand:QI 1 "general_operand"       "%0,0,0")
		(match_operand    2 "general_operand"       "iRvWabWhbWh1Whl,A,i")))
   ]
  "rl78_real_insns_ok ()"
  "xor\t%0, %2"
)

;;---------- Shifts ------------------------

(define_insn "*ashlqi3_real"
  [(set (match_operand:QI            0 "nonimmediate_operand"  "=abc,a,a")
	(ashift:QI (match_operand:QI 1 "general_operand"  "0,0,0")
		   (match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   shl\t%0, %u2
   cmp0 %2\; bz $2f\; 1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:"
)

(define_insn "*ashlhi3_real"
  [(set (match_operand:HI            0 "nonimmediate_operand"  "=AB,A,A")
	(ashift:HI (match_operand:HI 1 "general_operand"  "0,0,0")
		   (match_operand:QI 2 "general_operand" "P,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   shlw\t%0, %u2
   cmp0 %2\; bz $2f\; 1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:"
)

;;----------

(define_insn "*ashrqi3_real"
  [(set (match_operand:QI              0 "nonimmediate_operand"  "=abc,a,a")
	(ashiftrt:QI (match_operand:QI 1 "general_operand"  "0,0,0")
		     (match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   sar\t%0, %u2
   cmp0 %2\; bz $2f\; 1: sar\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: sar\t%0, 1\;dec %2 \;bnz $1b\;2:"
)

(define_insn "*ashrhi3_real"
  [(set (match_operand:HI              0 "nonimmediate_operand"  "=AB,A,A")
	(ashiftrt:HI (match_operand:HI 1 "general_operand"  "0,0,0")
		     (match_operand:QI 2 "general_operand" "P,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   sarw\t%0, %u2
   cmp0 %2\; bz $2f\; 1: sarw\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: sarw\t%0, 1\;dec %2\;bnz $1b\;2:"
)

;;----------

(define_insn "*lshrqi3_real"
  [(set (match_operand:QI              0 "nonimmediate_operand"  "=abc,a,a")
	(lshiftrt:QI (match_operand:QI 1 "general_operand"  "0,0,0")
		     (match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   shr\t%0, %u2
   cmp0 %2\; bz $2f\; 1: shr\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: shr\t%0, 1\;dec %2\;bnz $1b\;2:"
)

(define_insn "*lshrhi3_real"
  [(set (match_operand:HI              0 "nonimmediate_operand"  "=AB,A,A")
	(lshiftrt:HI (match_operand:HI 1 "general_operand"  "0,0,0")
		     (match_operand:QI 2 "general_operand" "P,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   shrw\t%0, %u2
   cmp0 %2\; bz $2f\; 1: shrw\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: shrw\t%0, 1\;dec %2\;bnz $1b\;2:"
)

;;---------- Branching ------------------------

(define_insn "*indirect_jump_real"
  [(set (pc)
	(match_operand:HI 0 "nonimmediate_operand" "A"))]
  "rl78_real_insns_ok ()"
  "br\t%0"
)

(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  ;; $rel8, $!rel16, !abs16, !!abs20
  "br\t!!%0"
)

(define_insn "*call_real"
  [(call (match_operand:HI 0 "memory_operand" "Wab,Wca")
	 (match_operand 1 "" ""))]
  "rl78_real_insns_ok ()"
  "@
   call\t!!%A0
   call\t%A0"
  )

(define_insn "*call_value_real"
  [(set (match_operand 0 "register_operand" "=v,v")
	(call (match_operand:HI 1 "memory_operand" "Wab,Wca")
	      (match_operand 2 "" "")))]
  "rl78_real_insns_ok ()"
  "@
   call\t!!%A1
   call\t%A1"
  )

(define_insn "*cbranchqi4_real_signed"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_signed"
			      [(match_operand:QI 1 "general_operand" "A,A,A")
			       (match_operand:QI 2 "general_operand" "ISqi,i,v")])
              (label_ref (match_operand 3 "" ""))
	      (pc)))]
  "rl78_real_insns_ok ()"
  "@
   cmp\t%1, %2 \;xor1 CY,%1.7\;not1 CY\;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;xor1 CY,%1.7\;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;xor1 CY,%1.7\;xor1 CY,%2.7\;sk%C0 \;br\t!!%3"
  )

(define_insn "*cbranchqi4_real"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_real"
			      [(match_operand:QI 1 "general_operand" "Wabvaxbc,a,              v,bcdehl")
			       (match_operand:QI 2 "general_operand" "M,       irvWabWhlWh1Whb,i,a")])
              (label_ref (match_operand 3 "" ""))
	      (pc)))]
  "rl78_real_insns_ok ()"
  "@
   cmp0\t%1 \;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;sk%C0 \;br\t!!%3"
  )

(define_insn "*cbranchhi4_real_signed"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_signed"
			      [(match_operand:HI 1 "general_operand" "A,A,A,vR")
			       (match_operand:HI 2 "general_operand" "IShi,i,v,1")])
              (label_ref (match_operand 3))
	      (pc)))]
  "rl78_real_insns_ok ()"
  "@
   cmpw\t%1, %2 \;xor1 CY,%Q1.7\;not1 CY\;sk%C0 \;br\t!!%3
   cmpw\t%1, %2 \;xor1 CY,%Q1.7\;sk%C0 \;br\t!!%3
   cmpw\t%1, %2 \;xor1 CY,%Q1.7\;xor1 CY,%Q2.7\;sk%C0 \;br\t!!%3
   %z0\t!!%3"
  )

(define_insn "cbranchhi4_real"
  [(set (pc) (if_then_else
	      (match_operator                    0 "rl78_cmp_operator_real"
			      [(match_operand:HI 1 "general_operand" "A,vR")
			       (match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1,1")])
              (label_ref (match_operand          3 "" ""))
	      (pc)))]
  "rl78_real_insns_ok ()"
  "@
  cmpw\t%1, %2 \;sk%C0 \;br\t!!%3
  %z0\t!!%3"
  )

(define_insn "cbranchhi4_real_inverted"  
  [(set (pc) (if_then_else
	      (match_operator                    0 "rl78_cmp_operator_real"
			      [(match_operand:HI 1 "general_operand" "A")
			       (match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1")])
	      (pc)
              (label_ref (match_operand          3 "" ""))))]
  "rl78_real_insns_ok ()"
  "cmpw\t%1, %2 \;sk%C0 \;br\t!!%3"
  )

(define_insn "*cbranchsi4_real_lt"
  [(set (pc) (if_then_else
	      (lt (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
		  (const_int 0))
              (label_ref (match_operand 1 "" ""))
	      (pc)))
   (clobber (reg:HI AX_REG))
   ]
  "rl78_real_insns_ok ()"
  "@
   mov a, %E0 \;mov1 CY,a.7 \;sknc \;br\t!!%1
   mov1 CY,%E0.7 \;sknc \;br\t!!%1"
  )

(define_insn "*cbranchsi4_real_ge"
  [(set (pc) (if_then_else
	      (ge (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
		  (const_int 0))
              (label_ref (match_operand 1 "" ""))
	      (pc)))
   (clobber (reg:HI AX_REG))
   ]
  "rl78_real_insns_ok ()"
  "@
   mov a, %E0 \;mov1 CY,a.7 \;skc \;br\t!!%1
   mov1 CY,%E0.7 \;skc \;br\t!!%1"
  )

(define_insn "*cbranchsi4_real_signed"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_signed"
			      [(match_operand:SI 1 "nonimmediate_operand" "vU,vU,vU")
			       (match_operand:SI 2 "nonmemory_operand" "ISsi,i,v")])
              (label_ref (match_operand 3 "" ""))
	      (pc)))
   (clobber (reg:HI AX_REG))
   ]
  "rl78_real_insns_ok ()"
  "@
   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;not1 CY\;      movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3
   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;               movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3
   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3"
  )

(define_insn "*cbranchsi4_real"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_real"
			      [(match_operand:SI 1 "general_operand" "vUi")
			       (match_operand:SI 2 "general_operand" "iWhlWh1v")])
              (label_ref (match_operand 3 "" ""))
	      (pc)))
   (clobber (reg:HI AX_REG))
   ]
  "rl78_real_insns_ok ()"
  "movw ax,%H1 \;cmpw  ax, %H2 \;movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3"
  )

;; Peephole to match:
;;
;;     (set (mem (sp)) (ax))
;;     (set (ax) (mem (sp)))
;; or:
;;     (set (mem (plus (sp) (const)) (ax))
;;     (set (ax) (mem (plus (sp) (const))))
;;
;; which can be generated as the last instruction of the conversion
;; of one virtual insn into a real insn and the first instruction of
;; the conversion of the following virtual insn.

(define_peephole2
  [(set (match_operand:HI 0 "rl78_stack_based_mem")
	(reg:HI AX_REG))
   (set (reg:HI AX_REG)
	(match_dup 0))]
  ""
  [(set (match_dup 0) (reg:HI AX_REG))]
  )

;; Bit test and branch insns.

;; NOTE: These patterns will work for bits in other places, not just A.

(define_insn "bf"
  [(set (pc)
	(if_then_else (eq (and (reg:QI A_REG)
			       (match_operand 0 "immediate_operand" "n"))
			  (const_int 0))
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "bf\tA.%B0, $%1"
)

(define_insn "bt"
  [(set (pc)
	(if_then_else (ne (and (reg:QI A_REG)
			       (match_operand 0 "immediate_operand" "n"))
			  (const_int 0))
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "bt\tA.%B0, $%1"
)

;; NOTE: These peepholes are fragile.  They rely upon GCC generating
;; a specific sequence on insns, based upon examination of test code.
;; Improvements to GCC or using code other than the test code can result
;; in the peephole not matching and the optimization being missed.

(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (pc) (if_then_else (eq (match_dup 0) (const_int 0))
			   (label_ref (match_operand 2 ""))
			   (pc)))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))
   && exact_log2 (INTVAL (operands[1])) >= 0"
  [(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
			   (label_ref (match_dup 2))
			   (pc)))]
  )

(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
			   (label_ref (match_operand 2 ""))
			   (pc)))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))
   && exact_log2 (INTVAL (operands[1])) >= 0"
  [(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
			   (label_ref (match_dup 2))
			   (pc)))]
  )

;; Eliminate needless register copies.
(define_peephole2
  [(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand"))
   (set (match_operand:HI 2 "register_operand") (match_dup 0))]
  "peep2_regno_dead_p (2, REGNO (operands[0]))
   && (REGNO (operands[1]) < 8 || REGNO (operands[2]) < 8)"
  [(set (match_dup 2) (match_dup 1))]
  )

;; Eliminate needless register copying when performing bit manipulations.
(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (ior:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (reg:QI A_REG) (match_dup 0))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))"
  [(set (reg:QI A_REG) (ior:QI (reg:QI A_REG) (match_dup 1)))]
  )

(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (xor:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (reg:QI A_REG) (match_dup 0))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))"
  [(set (reg:QI A_REG) (xor:QI (reg:QI A_REG) (match_dup 1)))]
  )

(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (reg:QI A_REG) (match_dup 0))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))"
  [(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))]
  )
Commit	Line	Data
85b8555e	1	;; Machine Description for Renesas RL78 processors
23a5b65a	2	;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
85b8555e DD	3	;; Contributed by Red Hat.
	4
	5	;; This file is part of GCC.
	6
	7	;; GCC is free software; you can redistribute it and/or modify
	8	;; it under the terms of the GNU General Public License as published by
	9	;; the Free Software Foundation; either version 3, or (at your option)
	10	;; any later version.
	11
	12	;; GCC is distributed in the hope that it will be useful,
	13	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	;; GNU General Public License for more details.
	16
	17	;; You should have received a copy of the GNU General Public License
	18	;; along with GCC; see the file COPYING3. If not see
	19	;; <http://www.gnu.org/licenses/>.
	20	\f
	21	;; The insns in this file correspond to the actual opcodes the RL78
	22	;; can issue with real registers. All insns in here should be
	23	;; conditional on rl78_real_insns_ok() returning true, and should
	24	;; allow virtual registers in their predicates - the reorg pass that
	25	;; allocates physical registers uses the constraints to select
	26	;; registers, but insns with virtual registers MUST match one of these
	27	;; patterns - other than the constraints - so that the operand info is
	28	;; properly set up for the alloc pass.
	29
	30	;;---------- Moving ------------------------
	31
	32	(define_insn "movqi_es"
	33	[(set (reg:QI ES_REG)
	34	(match_operand:QI 0 "register_operand" "a"))]
	35	""
	36	"mov\tes, %0"
	37	)
	38
	39	(define_insn "movqi_cs"
	40	[(set (reg:QI CS_REG)
	41	(match_operand:QI 0 "register_operand" "a"))]
	42	""
	43	"mov\tcs, %0"
	44	)
	45
	46	(define_insn "*movqi_real"
	47	[(set (match_operand:QI 0 "nonimmediate_operand" "=g,RaxbcWab,RaxbcWab,a, bcx,R, WabWd2WhlWh1WhbWbcWs1v, bcx")
	48	(match_operand 1 "general_operand" "0,K, M, RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a, R"))]
	49	"rl78_real_insns_ok ()"
	50	"@
	51	; mov\t%0, %1
	52	oneb\t%0
	53	clrb\t%0
	54	mov\t%0, %1
	55	mov\t%0, %1
	56	mov\t%0, %1
	57	mov\t%0, %1
	58	mov\t%0, %S1"
	59	)
	60
	61	(define_insn "*movhi_real"
	62	[(set (match_operand:HI 0 "nonimmediate_operand" "=g,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
	63	(match_operand:HI 1 "general_operand" " 0,K, M, i, BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS, ABDT"))]
	64	"rl78_real_insns_ok ()"
	65	"@
	66	; movw\t%0, %1
67	onew\t%0
68	clrw\t%0
69	movw\t%0, %1
70	movw\t%0, %1
71	movw\t%0, %1
72	movw\t%0, %S1
73	movw\t%0, %1
74	movw\t%0, %1"
75	)
76
77	;;---------- Conversions ------------------------
78
79	(define_insn "*zero_extendqihi2_real"
80	[(set (match_operand:HI 0 "nonimmediate_operand" "=rv,A")
81	(zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))]
82	"rl78_real_insns_ok ()"
83	"@
84	mov\t%Q0, #0
85	mov\tx, a \;mov\ta, #0"
86	)
87
88	(define_insn "*extendqihi2_real"
89	[(set (match_operand:HI 0 "nonimmediate_operand" "=A,A")
90	(sign_extend:HI (match_operand:QI 1 "general_operand" "x,a")))]
91	"rl78_real_insns_ok ()"
92	"@
93	shlw\t%0, 8 \;sarw\t%0, 8
94	sarw\t%0, 8"
95	)
96
97	;;---------- Arithmetic ------------------------
98
99	(define_insn "*addqi3_real"
100	[(set (match_operand:QI 0 "nonimmediate_operand" "=rvWabWhlWh1,rvWabWhlWh1,a,*bcdehl")
101	(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
102	(match_operand:QI 2 "general_operand" "K,L,RWhlWh1i,a")))
103	]
104	"rl78_real_insns_ok ()"
105	"@
106	inc\t%0
107	dec\t%0
108	add\t%0, %2
109	add\t%0, %2"
110	)
111
112	(define_insn "*addhi3_real"
113	[(set (match_operand:HI 0 "nonimmediate_operand" "=vABDTWh1Wab,vABDTWh1Wab,v,v,A,S,S,A")
114	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0,0,0,S")
115	(match_operand:HI 2 "general_operand" "K,L,N,O,RWh1WhlWabiv,Int8,J,Ri")))
116	]
117	"rl78_real_insns_ok ()"
118	"@
119	incw\t%0
120	decw\t%0
121	incw\t%0 \;incw\t%0
122	decw\t%0 \;decw\t%0
123	addw\t%0, %p2
124	addw\t%0, %2
125	subw\t%0, %m2
126	movw\t%0, %1 \;addw\t%0, %2"
127	)
128
129	(define_insn "*addqihi3a_real"
130	[(set (match_operand:HI 0 "register_operand" "=r")
131	(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%r"))
132	(match_operand:HI 2 "register_operand" "r")))
133	]
134	"rl78_real_insns_ok ()"
135	"add\t%q0, %q1 \;addc\t%Q0, #0"
136	)
137
138	(define_insn "*subqi3_real"
139	[(set (match_operand:QI 0 "nonimmediate_operand" "=a,R,v")
140	(minus:QI (match_operand:QI 1 "general_operand" "0,0,0")
141	(match_operand:QI 2 "general_operand" "RiWabWhbWh1Whl,a,i")))
142	]
143	"rl78_real_insns_ok ()"
144	"sub\t%0, %2"
145	)
146
147	(define_insn "*subhi3_real"
148	[(set (match_operand:HI 0 "nonimmediate_operand" "=A,S")
149	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
150	(match_operand:HI 2 "general_operand" "iBDTWabWh1v,i")))
151	]
152	"rl78_real_insns_ok ()"
153	"subw\t%0, %2"
154	)
155
156	(define_insn "*umulhi3_shift_real"
157	[(set (match_operand:HI 0 "register_operand" "=A,A")
158	(mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "0,0")
159	(match_operand:HI 2 "rl78_24_operand" "N,i")))]
160	"rl78_real_insns_ok ()"
161	"@
162	shlw\t%0, 1
163	shlw\t%0, 2"
164	)
165
166	(define_insn "*umulqihi3_real"
167	[(set (match_operand:HI 0 "nonimmediate_operand" "=A")
168	(mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%a"))
169	(zero_extend:HI (match_operand:QI 2 "general_operand" "x"))))]
170	"rl78_real_insns_ok ()"
171	"mulu\t%2"
172	)
173
174	(define_insn "*andqi3_real"
175	[(set (match_operand:QI 0 "nonimmediate_operand" "=A,R,v")
176	(and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
177	(match_operand:QI 2 "general_operand" "iRvWabWhbWh1Whl,A,i")))
178	]
179	"rl78_real_insns_ok ()"
180	"and\t%0, %2"
181	)
182
183	(define_insn "*iorqi3_real"
184	[(set (match_operand:QI 0 "nonimmediate_operand" "=A,R,v")
185	(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0")
186	(match_operand:QI 2 "general_operand" "iRvWabWhbWh1Whl,A,i")))
187	]
188	"rl78_real_insns_ok ()"
189	"or\t%0, %2"
190	)
191
192	(define_insn "*xorqi3_real"
193	[(set (match_operand:QI 0 "nonimmediate_operand" "=A,R,v")
194	(xor:QI (match_operand:QI 1 "general_operand" "%0,0,0")
195	(match_operand 2 "general_operand" "iRvWabWhbWh1Whl,A,i")))
196	]
197	"rl78_real_insns_ok ()"
198	"xor\t%0, %2"
199	)
200
201	;;---------- Shifts ------------------------
202
203	(define_insn "*ashlqi3_real"
204	[(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
205	(ashift:QI (match_operand:QI 1 "general_operand" "0,0,0")
206	(match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
207	]
208	"rl78_real_insns_ok ()"
209	"@
210	shl\t%0, %u2
211	cmp0 %2\; bz $2f\; 1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:
212	inc %2\;dec %2\;bz $2f\;1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:"
213	)
214
215	(define_insn "*ashlhi3_real"
216	[(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
217	(ashift:HI (match_operand:HI 1 "general_operand" "0,0,0")
218	(match_operand:QI 2 "general_operand" "P,bc,dehl")))
219	]
220	"rl78_real_insns_ok ()"
221	"@
222	shlw\t%0, %u2
223	cmp0 %2\; bz $2f\; 1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:
224	inc %2\;dec %2\;bz $2f\;1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:"
225	)
226
227	;;----------
228
229	(define_insn "*ashrqi3_real"
230	[(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
231	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0")
232	(match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
233	]
234	"rl78_real_insns_ok ()"
235	"@
236	sar\t%0, %u2
237	cmp0 %2\; bz $2f\; 1: sar\t%0, 1 \;dec %2 \;bnz $1b\;2:
238	inc %2\;dec %2\;bz $2f\;1: sar\t%0, 1\;dec %2 \;bnz $1b\;2:"
239	)
240
241	(define_insn "*ashrhi3_real"
242	[(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
243	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0")
244	(match_operand:QI 2 "general_operand" "P,bc,dehl")))
245	]
246	"rl78_real_insns_ok ()"
247	"@
248	sarw\t%0, %u2
249	cmp0 %2\; bz $2f\; 1: sarw\t%0, 1 \;dec %2 \;bnz $1b\;2:
250	inc %2\;dec %2\;bz $2f\;1: sarw\t%0, 1\;dec %2\;bnz $1b\;2:"
251	)
252
253	;;----------
254
255	(define_insn "*lshrqi3_real"
256	[(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
257	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0")
258	(match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
259	]
260	"rl78_real_insns_ok ()"
261	"@
262	shr\t%0, %u2
263	cmp0 %2\; bz $2f\; 1: shr\t%0, 1 \;dec %2 \;bnz $1b\;2:
264	inc %2\;dec %2\;bz $2f\;1: shr\t%0, 1\;dec %2\;bnz $1b\;2:"
265	)
266
267	(define_insn "*lshrhi3_real"
268	[(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
269	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0")
270	(match_operand:QI 2 "general_operand" "P,bc,dehl")))
271	]
272	"rl78_real_insns_ok ()"
273	"@
274	shrw\t%0, %u2
275	cmp0 %2\; bz $2f\; 1: shrw\t%0, 1 \;dec %2 \;bnz $1b\;2:
276	inc %2\;dec %2\;bz $2f\;1: shrw\t%0, 1\;dec %2\;bnz $1b\;2:"
277	)
278
279	;;---------- Branching ------------------------
280
281	(define_insn "*indirect_jump_real"
282	[(set (pc)
283	(match_operand:HI 0 "nonimmediate_operand" "A"))]
284	"rl78_real_insns_ok ()"
285	"br\t%0"
286	)
287
288	(define_insn "jump"
289	[(set (pc)
290	(label_ref (match_operand 0 "" "")))]
291	""
292	;; $rel8, $!rel16, !abs16, !!abs20
293	"br\t!!%0"
294	)
295
296	(define_insn "*call_real"
297	[(call (match_operand:HI 0 "memory_operand" "Wab,Wca")
298	(match_operand 1 "" ""))]
299	"rl78_real_insns_ok ()"
300	"@
301	call\t!!%A0
302	call\t%A0"
303	)
304
305	(define_insn "*call_value_real"
306	[(set (match_operand 0 "register_operand" "=v,v")
307	(call (match_operand:HI 1 "memory_operand" "Wab,Wca")
308	(match_operand 2 "" "")))]
309	"rl78_real_insns_ok ()"
310	"@
311	call\t!!%A1
312	call\t%A1"
313	)
314
6fcd3a13	315	(define_insn "*cbranchqi4_real_signed"
3e3d9d17 DD	316	[(set (pc) (if_then_else
	317	(match_operator 0 "rl78_cmp_operator_signed"
	318	[(match_operand:QI 1 "general_operand" "A,A,A")
	319	(match_operand:QI 2 "general_operand" "ISqi,i,v")])
	320	(label_ref (match_operand 3 "" ""))
	321	(pc)))]
	322	"rl78_real_insns_ok ()"
	323	"@
59d96342 DD	324	cmp\t%1, %2 \;xor1 CY,%1.7\;not1 CY\;sk%C0 \;br\t!!%3
	325	cmp\t%1, %2 \;xor1 CY,%1.7\;sk%C0 \;br\t!!%3
	326	cmp\t%1, %2 \;xor1 CY,%1.7\;xor1 CY,%2.7\;sk%C0 \;br\t!!%3"
3e3d9d17 DD	327	)
3e3d9d17 DD	328
85b8555e DD	329	(define_insn "*cbranchqi4_real"
	330	[(set (pc) (if_then_else
	331	(match_operator 0 "rl78_cmp_operator_real"
3e3d9d17 DD	332	[(match_operand:QI 1 "general_operand" "Wabvaxbc,a, v,bcdehl")
3e3d9d17 DD	333	(match_operand:QI 2 "general_operand" "M, irvWabWhlWh1Whb,i,a")])
85b8555e DD	334	(label_ref (match_operand 3 "" ""))
	335	(pc)))]
	336	"rl78_real_insns_ok ()"
	337	"@
59d96342 DD	338	cmp0\t%1 \;sk%C0 \;br\t!!%3
	339	cmp\t%1, %2 \;sk%C0 \;br\t!!%3
	340	cmp\t%1, %2 \;sk%C0 \;br\t!!%3
	341	cmp\t%1, %2 \;sk%C0 \;br\t!!%3"
85b8555e DD	342	)
85b8555e DD	343
6fcd3a13	344	(define_insn "*cbranchhi4_real_signed"
85b8555e	345	[(set (pc) (if_then_else
3e3d9d17 DD	346	(match_operator 0 "rl78_cmp_operator_signed"
	347	[(match_operand:HI 1 "general_operand" "A,A,A,vR")
	348	(match_operand:HI 2 "general_operand" "IShi,i,v,1")])
	349	(label_ref (match_operand 3))
85b8555e DD	350	(pc)))]
85b8555e DD	351	"rl78_real_insns_ok ()"
3e3d9d17	352	"@
59d96342 DD	353	cmpw\t%1, %2 \;xor1 CY,%Q1.7\;not1 CY\;sk%C0 \;br\t!!%3
	354	cmpw\t%1, %2 \;xor1 CY,%Q1.7\;sk%C0 \;br\t!!%3
	355	cmpw\t%1, %2 \;xor1 CY,%Q1.7\;xor1 CY,%Q2.7\;sk%C0 \;br\t!!%3
3e3d9d17 DD	356	%z0\t!!%3"
	357	)
	358
	359	(define_insn "cbranchhi4_real"
	360	[(set (pc) (if_then_else
	361	(match_operator 0 "rl78_cmp_operator_real"
	362	[(match_operand:HI 1 "general_operand" "A,vR")
	363	(match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1,1")])
	364	(label_ref (match_operand 3 "" ""))
	365	(pc)))]
	366	"rl78_real_insns_ok ()"
	367	"@
59d96342	368	cmpw\t%1, %2 \;sk%C0 \;br\t!!%3
3e3d9d17 DD	369	%z0\t!!%3"
	370	)
	371
	372	(define_insn "cbranchhi4_real_inverted"
	373	[(set (pc) (if_then_else
	374	(match_operator 0 "rl78_cmp_operator_real"
	375	[(match_operand:HI 1 "general_operand" "A")
	376	(match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1")])
	377	(pc)
	378	(label_ref (match_operand 3 "" ""))))]
	379	"rl78_real_insns_ok ()"
59d96342	380	"cmpw\t%1, %2 \;sk%C0 \;br\t!!%3"
85b8555e	381	)
3e3d9d17	382
6fcd3a13	383	(define_insn "*cbranchsi4_real_lt"
3e3d9d17 DD	384	[(set (pc) (if_then_else
	385	(lt (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
	386	(const_int 0))
	387	(label_ref (match_operand 1 "" ""))
	388	(pc)))
	389	(clobber (reg:HI AX_REG))
	390	]
	391	"rl78_real_insns_ok ()"
	392	"@
	393	mov a, %E0 \;mov1 CY,a.7 \;sknc \;br\t!!%1
	394	mov1 CY,%E0.7 \;sknc \;br\t!!%1"
	395	)
	396
6fcd3a13	397	(define_insn "*cbranchsi4_real_ge"
3e3d9d17 DD	398	[(set (pc) (if_then_else
	399	(ge (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
	400	(const_int 0))
	401	(label_ref (match_operand 1 "" ""))
	402	(pc)))
	403	(clobber (reg:HI AX_REG))
	404	]
	405	"rl78_real_insns_ok ()"
	406	"@
	407	mov a, %E0 \;mov1 CY,a.7 \;skc \;br\t!!%1
	408	mov1 CY,%E0.7 \;skc \;br\t!!%1"
	409	)
	410
6fcd3a13	411	(define_insn "*cbranchsi4_real_signed"
3e3d9d17 DD	412	[(set (pc) (if_then_else
	413	(match_operator 0 "rl78_cmp_operator_signed"
	414	[(match_operand:SI 1 "nonimmediate_operand" "vU,vU,vU")
	415	(match_operand:SI 2 "nonmemory_operand" "ISsi,i,v")])
	416	(label_ref (match_operand 3 "" ""))
	417	(pc)))
	418	(clobber (reg:HI AX_REG))
	419	]
	420	"rl78_real_insns_ok ()"
	421	"@
59d96342 DD	422	movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;not1 CY\; movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3
	423	movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\; movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3
	424	movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3"
3e3d9d17 DD	425	)
3e3d9d17 DD	426
6fcd3a13	427	(define_insn "*cbranchsi4_real"
3e3d9d17 DD	428	[(set (pc) (if_then_else
	429	(match_operator 0 "rl78_cmp_operator_real"
	430	[(match_operand:SI 1 "general_operand" "vUi")
	431	(match_operand:SI 2 "general_operand" "iWhlWh1v")])
	432	(label_ref (match_operand 3 "" ""))
	433	(pc)))
	434	(clobber (reg:HI AX_REG))
	435	]
	436	"rl78_real_insns_ok ()"
59d96342	437	"movw ax,%H1 \;cmpw ax, %H2 \;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3"
3e3d9d17 DD	438	)
	439
	440	;; Peephole to match:
	441	;;
	442	;; (set (mem (sp)) (ax))
	443	;; (set (ax) (mem (sp)))
	444	;; or:
	445	;; (set (mem (plus (sp) (const)) (ax))
	446	;; (set (ax) (mem (plus (sp) (const))))
	447	;;
	448	;; which can be generated as the last instruction of the conversion
	449	;; of one virtual insn into a real insn and the first instruction of
	450	;; the conversion of the following virtual insn.
	451
	452	(define_peephole2
	453	[(set (match_operand:HI 0 "rl78_stack_based_mem")
	454	(reg:HI AX_REG))
	455	(set (reg:HI AX_REG)
	456	(match_dup 0))]
	457	""
	458	[(set (match_dup 0) (reg:HI AX_REG))]
	459	)
	460
b5ba3a9b NC	461	;; Bit test and branch insns.
	462
	463	;; NOTE: These patterns will work for bits in other places, not just A.
	464
	465	(define_insn "bf"
	466	[(set (pc)
	467	(if_then_else (eq (and (reg:QI A_REG)
	468	(match_operand 0 "immediate_operand" "n"))
	469	(const_int 0))
	470	(label_ref (match_operand 1 "" ""))
	471	(pc)))]
	472	""
	473	"bf\tA.%B0, $%1"
	474	)
	475
	476	(define_insn "bt"
	477	[(set (pc)
	478	(if_then_else (ne (and (reg:QI A_REG)
	479	(match_operand 0 "immediate_operand" "n"))
	480	(const_int 0))
	481	(label_ref (match_operand 1 "" ""))
	482	(pc)))]
	483	""
	484	"bt\tA.%B0, $%1"
	485	)
	486
	487	;; NOTE: These peepholes are fragile. They rely upon GCC generating
	488	;; a specific sequence on insns, based upon examination of test code.
	489	;; Improvements to GCC or using code other than the test code can result
	490	;; in the peephole not matching and the optimization being missed.
	491
	492	(define_peephole2
6fcd3a13 DD	493	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	494	(set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	495	(set (pc) (if_then_else (eq (match_dup 0) (const_int 0))
	496	(label_ref (match_operand 2 ""))
	497	(pc)))]
	498	"peep2_regno_dead_p (3, REGNO (operands[0]))
	499	&& exact_log2 (INTVAL (operands[1])) >= 0"
	500	[(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
	501	(label_ref (match_dup 2))
b5ba3a9b	502	(pc)))]
b5ba3a9b NC	503	)
	504
	505	(define_peephole2
6fcd3a13 DD	506	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	507	(set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	508	(set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
	509	(label_ref (match_operand 2 ""))
b5ba3a9b	510	(pc)))]
6fcd3a13 DD	511	"peep2_regno_dead_p (3, REGNO (operands[0]))
	512	&& exact_log2 (INTVAL (operands[1])) >= 0"
	513	[(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
	514	(label_ref (match_dup 2))
	515	(pc)))]
	516	)
	517
	518	;; Eliminate needless register copies.
	519	(define_peephole2
	520	[(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand"))
	521	(set (match_operand:HI 2 "register_operand") (match_dup 0))]
	522	"peep2_regno_dead_p (2, REGNO (operands[0]))
	523	&& (REGNO (operands[1]) < 8 \|\| REGNO (operands[2]) < 8)"
	524	[(set (match_dup 2) (match_dup 1))]
	525	)
	526
	527	;; Eliminate needless register copying when performing bit manipulations.
	528	(define_peephole2
	529	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	530	(set (match_dup 0) (ior:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	531	(set (reg:QI A_REG) (match_dup 0))]
	532	"peep2_regno_dead_p (3, REGNO (operands[0]))"
	533	[(set (reg:QI A_REG) (ior:QI (reg:QI A_REG) (match_dup 1)))]
	534	)
	535
	536	(define_peephole2
	537	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	538	(set (match_dup 0) (xor:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	539	(set (reg:QI A_REG) (match_dup 0))]
	540	"peep2_regno_dead_p (3, REGNO (operands[0]))"
	541	[(set (reg:QI A_REG) (xor:QI (reg:QI A_REG) (match_dup 1)))]
	542	)
	543
	544	(define_peephole2
	545	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	546	(set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	547	(set (reg:QI A_REG) (match_dup 0))]
	548	"peep2_regno_dead_p (3, REGNO (operands[0]))"
	549	[(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))]
b5ba3a9b NC	550	)
b5ba3a9b NC	551