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3e260c01 | 1 | ;; Scheduling description for PowerPC 603 processor. |
f1717362 | 2 | ;; Copyright (C) 2003-2016 Free Software Foundation, Inc. |
3e260c01 | 3 | ;; |
3a5a28e2 | 4 | ;; This file is part of GCC. |
5 | ||
6 | ;; GCC is free software; you can redistribute it and/or modify it | |
7 | ;; under the terms of the GNU General Public License as published | |
038d1e19 | 8 | ;; by the Free Software Foundation; either version 3, or (at your |
3a5a28e2 | 9 | ;; option) any later version. |
10 | ||
11 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
12 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | ;; License for more details. | |
15 | ||
3e260c01 | 16 | ;; You should have received a copy of the GNU General Public License |
038d1e19 | 17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
3e260c01 | 19 | |
e0c0a39e | 20 | (define_automaton "ppc603,ppc603fp") |
a0b98322 | 21 | (define_cpu_unit "iu_603" "ppc603") |
22 | (define_cpu_unit "fpu_603" "ppc603fp") | |
e0c0a39e | 23 | (define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603") |
a0b98322 | 24 | |
25 | ;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU | |
26 | ;; Max issue 3 insns/clock cycle (includes 1 branch) | |
27 | ||
28 | ;; Branches go straight to the BPU. All other insns are handled | |
29 | ;; by a dispatch unit which can issue a max of 2 insns per cycle. | |
30 | ||
31 | ;; The PPC603e user's manual recommends that to reduce branch mispredictions, | |
32 | ;; the insn that sets CR bits should be separated from the branch insn | |
33 | ;; that evaluates them; separation by more than 9 insns ensures that the CR | |
34 | ;; bits will be immediately available for execution. | |
2cecd772 | 35 | ;; This could be artificially achieved by exaggerating the latency of |
a0b98322 | 36 | ;; compare insns but at the expense of a poorer schedule. |
37 | ||
38 | ;; CR insns get executed in the SRU. Not modelled. | |
39 | ||
40 | (define_insn_reservation "ppc603-load" 2 | |
631c977b | 41 | (and (eq_attr "type" "load,load_l") |
a0b98322 | 42 | (eq_attr "cpu" "ppc603")) |
43 | "lsu_603") | |
44 | ||
dda067b9 | 45 | (define_insn_reservation "ppc603-store" 2 |
631c977b | 46 | (and (eq_attr "type" "store,fpstore") |
a0b98322 | 47 | (eq_attr "cpu" "ppc603")) |
5d42cb42 | 48 | "lsu_603*2") |
a0b98322 | 49 | |
50 | (define_insn_reservation "ppc603-fpload" 2 | |
631c977b | 51 | (and (eq_attr "type" "fpload") |
a0b98322 | 52 | (eq_attr "cpu" "ppc603")) |
53 | "lsu_603") | |
54 | ||
dda067b9 | 55 | (define_insn_reservation "ppc603-storec" 8 |
56 | (and (eq_attr "type" "store_c") | |
57 | (eq_attr "cpu" "ppc603")) | |
58 | "lsu_603") | |
59 | ||
a0b98322 | 60 | (define_insn_reservation "ppc603-integer" 1 |
88599a7a | 61 | (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel") |
62 | (and (eq_attr "type" "add,logical,shift,exts") | |
7d307a6a | 63 | (eq_attr "dot" "no"))) |
a0b98322 | 64 | (eq_attr "cpu" "ppc603")) |
65 | "iu_603") | |
66 | ||
c86a5c89 | 67 | (define_insn_reservation "ppc603-two" 1 |
68 | (and (eq_attr "type" "two") | |
69 | (eq_attr "cpu" "ppc603")) | |
70 | "iu_603,iu_603") | |
71 | ||
72 | (define_insn_reservation "ppc603-three" 1 | |
73 | (and (eq_attr "type" "three") | |
74 | (eq_attr "cpu" "ppc603")) | |
75 | "iu_603,iu_603,iu_603") | |
76 | ||
a0b98322 | 77 | ; This takes 2 or 3 cycles |
78 | (define_insn_reservation "ppc603-imul" 3 | |
86c149d4 | 79 | (and (eq_attr "type" "mul") |
80 | (eq_attr "size" "32") | |
a0b98322 | 81 | (eq_attr "cpu" "ppc603")) |
82 | "iu_603*2") | |
83 | ||
84 | (define_insn_reservation "ppc603-imul2" 2 | |
86c149d4 | 85 | (and (eq_attr "type" "mul") |
86 | (eq_attr "size" "8,16") | |
a0b98322 | 87 | (eq_attr "cpu" "ppc603")) |
88 | "iu_603*2") | |
89 | ||
90 | (define_insn_reservation "ppc603-idiv" 37 | |
90e4483f | 91 | (and (eq_attr "type" "div") |
a0b98322 | 92 | (eq_attr "cpu" "ppc603")) |
93 | "iu_603*37") | |
94 | ||
95 | (define_insn_reservation "ppc603-compare" 3 | |
cd1e80f3 | 96 | (and (ior (eq_attr "type" "cmp") |
88599a7a | 97 | (and (eq_attr "type" "add,logical,shift,exts") |
7d307a6a | 98 | (eq_attr "dot" "yes"))) |
a0b98322 | 99 | (eq_attr "cpu" "ppc603")) |
100 | "iu_603,nothing,bpu_603") | |
101 | ||
102 | (define_insn_reservation "ppc603-fpcompare" 3 | |
103 | (and (eq_attr "type" "fpcompare") | |
104 | (eq_attr "cpu" "ppc603")) | |
105 | "(fpu_603+iu_603*2),bpu_603") | |
106 | ||
107 | (define_insn_reservation "ppc603-fp" 3 | |
108 | (and (eq_attr "type" "fp") | |
109 | (eq_attr "cpu" "ppc603")) | |
110 | "fpu_603") | |
111 | ||
112 | (define_insn_reservation "ppc603-dmul" 4 | |
113 | (and (eq_attr "type" "dmul") | |
114 | (eq_attr "cpu" "ppc603")) | |
115 | "fpu_603*2") | |
116 | ||
117 | ; Divides are not pipelined | |
118 | (define_insn_reservation "ppc603-sdiv" 18 | |
119 | (and (eq_attr "type" "sdiv") | |
120 | (eq_attr "cpu" "ppc603")) | |
121 | "fpu_603*18") | |
122 | ||
123 | (define_insn_reservation "ppc603-ddiv" 33 | |
124 | (and (eq_attr "type" "ddiv") | |
125 | (eq_attr "cpu" "ppc603")) | |
126 | "fpu_603*33") | |
127 | ||
45d9c0fa | 128 | (define_insn_reservation "ppc603-crlogical" 2 |
129 | (and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr") | |
a0b98322 | 130 | (eq_attr "cpu" "ppc603")) |
131 | "sru_603") | |
132 | ||
45d9c0fa | 133 | (define_insn_reservation "ppc603-mtjmpr" 4 |
134 | (and (eq_attr "type" "mtjmpr") | |
a0b98322 | 135 | (eq_attr "cpu" "ppc603")) |
136 | "sru_603") | |
137 | ||
45d9c0fa | 138 | (define_insn_reservation "ppc603-mfjmpr" 2 |
dda067b9 | 139 | (and (eq_attr "type" "mfjmpr,isync,sync") |
a0b98322 | 140 | (eq_attr "cpu" "ppc603")) |
45d9c0fa | 141 | "sru_603") |
a0b98322 | 142 | |
143 | (define_insn_reservation "ppc603-jmpreg" 1 | |
144 | (and (eq_attr "type" "jmpreg,branch") | |
145 | (eq_attr "cpu" "ppc603")) | |
146 | "bpu_603") | |
147 |