[thirdparty/gcc.git] / gcc / config / rs6000 / darwin.md

/* Machine description patterns for PowerPC running Darwin (Mac OS X).
   Copyright (C) 2004-2019 Free Software Foundation, Inc.
   Contributed by Apple Computer Inc.

This file is part of GCC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.  */

(define_insn "adddi3_high"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
        (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
                 (high:DI (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_64BIT"
  "addis %0,%1,ha16(%2)")

(define_insn "movdf_low_si"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
        (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
{
  switch (which_alternative)
    {
      case 0:
	return "lfd %0,lo16(%2)(%1)";
      case 1:
	{
	  if (TARGET_POWERPC64 && TARGET_32BIT)
	    /* Note, old assemblers didn't support relocation here.  */
	    return "ld %0,lo16(%2)(%1)";
	  else
	    {
	      output_asm_insn ("la %0,lo16(%2)(%1)", operands);
	      output_asm_insn ("lwz %L0,4(%0)", operands);
	      return ("lwz %0,0(%0)");
	    }
	}
      default:
	gcc_unreachable ();
    }
}
  [(set_attr "type" "load")
   (set_attr "length" "4,12")])


(define_insn "movdf_low_di"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
        (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
  "@
   lfd %0,lo16(%2)(%1)
   ld %0,lo16(%2)(%1)"
  [(set_attr "type" "load")])

(define_insn "movdf_low_st_si"
  [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
                           (match_operand 2 "" "")))
	(match_operand:DF 0 "gpc_reg_operand" "f"))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
  "stfd %0,lo16(%2)(%1)"
  [(set_attr "type" "store")])

(define_insn "movdf_low_st_di"
  [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
                           (match_operand 2 "" "")))
	(match_operand:DF 0 "gpc_reg_operand" "f"))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
  "stfd %0,lo16(%2)(%1)"
  [(set_attr "type" "store")])

(define_insn "movsf_low_si"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
        (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
  "@
   lfs %0,lo16(%2)(%1)
   lwz %0,lo16(%2)(%1)"
  [(set_attr "type" "load")])

(define_insn "movsf_low_di"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
        (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
  "@
   lfs %0,lo16(%2)(%1)
   lwz %0,lo16(%2)(%1)"
  [(set_attr "type" "load")])

(define_insn "movsf_low_st_si"
  [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" "")))
	(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
  "@
   stfs %0,lo16(%2)(%1)
   stw %0,lo16(%2)(%1)"
  [(set_attr "type" "store")])

(define_insn "movsf_low_st_di"
  [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" "")))
	(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
  "@
   stfs %0,lo16(%2)(%1)
   stw %0,lo16(%2)(%1)"
  [(set_attr "type" "store")])

;; 64-bit MachO load/store support
(define_insn "movdi_low"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d")
        (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_64BIT"
  "@
   ld %0,lo16(%2)(%1)
   lfd %0,lo16(%2)(%1)"
  [(set_attr "type" "load")])

(define_insn "movsi_low_st"
  [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
                           (match_operand 2 "" "")))
	(match_operand:SI 0 "gpc_reg_operand" "r"))]
  "TARGET_MACHO && ! TARGET_64BIT"
  "stw %0,lo16(%2)(%1)"
  [(set_attr "type" "store")])

(define_insn "movdi_low_st"
  [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" "")))
	(match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
  "TARGET_MACHO && TARGET_64BIT"
  "@
   std %0,lo16(%2)(%1)
   stfd %0,lo16(%2)(%1)"
  [(set_attr "type" "store")])

;; Mach-O PIC trickery.
(define_expand "macho_high"
  [(set (match_operand 0 "")
	(high (match_operand 1 "")))]
  "TARGET_MACHO"
{
  if (TARGET_64BIT)
    emit_insn (gen_macho_high_di (operands[0], operands[1]));
  else
    emit_insn (gen_macho_high_si (operands[0], operands[1]));

  DONE;
})

(define_insn "macho_high_si"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
	(high:SI (match_operand 1 "" "")))]
  "TARGET_MACHO && ! TARGET_64BIT"
  "lis %0,ha16(%1)")
  

(define_insn "macho_high_di"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
	(high:DI (match_operand 1 "" "")))]
  "TARGET_MACHO && TARGET_64BIT"
  "lis %0,ha16(%1)")

(define_expand "macho_low"
  [(set (match_operand 0 "")
	(lo_sum (match_operand 1 "")
		   (match_operand 2 "")))]
   "TARGET_MACHO"
{
  if (TARGET_64BIT)
    emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
  else
    emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));

  DONE;
})

(define_insn "macho_low_si"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
		   (match_operand 2 "" "")))]
   "TARGET_MACHO && ! TARGET_64BIT"
   "la %0,lo16(%2)(%1)")

(define_insn "macho_low_di"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
		   (match_operand 2 "" "")))]
   "TARGET_MACHO && TARGET_64BIT"
   "la %0,lo16(%2)(%1)")

(define_split
  [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand")
			 (match_operand:DI 1 "short_cint_operand")))
	(match_operand:V4SI 2 "register_operand"))
   (clobber (match_operand:DI 3 "gpc_reg_operand"))]
  "TARGET_MACHO && TARGET_64BIT"
  [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
   (set (mem:V4SI (match_dup 3))
	(match_dup 2))]
  "")

(define_expand "load_macho_picbase"
  [(set (reg LR_REGNO)
        (unspec [(match_operand 0 "")]
                   UNSPEC_LD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
  if (TARGET_32BIT)
    emit_insn (gen_load_macho_picbase_si (operands[0]));
  else
    emit_insn (gen_load_macho_picbase_di (operands[0]));

  DONE;
})

(define_insn "load_macho_picbase_<mode>"
  [(set (reg:P LR_REGNO)
	(unspec:P [(match_operand:P 0 "immediate_operand" "s")
		    (pc)] UNSPEC_LD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
#if TARGET_MACHO
  machopic_should_output_picbase_label (); /* Update for new func.  */
#else
  gcc_unreachable ();
#endif
  return "bcl 20,31,%0\n%0:";
}
  [(set_attr "type" "branch")
   (set_attr "cannot_copy" "yes")])

(define_expand "macho_correct_pic"
  [(set (match_operand 0 "")
	(plus (match_operand 1 "")
		 (unspec [(match_operand 2 "")
			     (match_operand 3 "")]
			    UNSPEC_MPIC_CORRECT)))]
  "DEFAULT_ABI == ABI_DARWIN"
{
  if (TARGET_32BIT)
    emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
	       operands[3]));
  else
    emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
	       operands[3]));

  DONE;
})

(define_insn "macho_correct_pic_si"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
			     (match_operand:SI 3 "immediate_operand" "s")]
			    UNSPEC_MPIC_CORRECT)))]
  "DEFAULT_ABI == ABI_DARWIN"
  "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
  [(set_attr "length" "8")])

(define_insn "macho_correct_pic_di"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
		 (unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
			     (match_operand:DI 3 "immediate_operand" "s")]
			    16)))]
  "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
  "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
  [(set_attr "length" "8")])

(define_expand "reload_macho_picbase"
  [(set (reg LR_REGNO)
        (unspec [(match_operand 0 "")]
                   UNSPEC_RELD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
  if (TARGET_32BIT)
    emit_insn (gen_reload_macho_picbase_si (operands[0]));
  else
    emit_insn (gen_reload_macho_picbase_di (operands[0]));

  DONE;
})

(define_insn "reload_macho_picbase_<mode>"
  [(set (reg:P LR_REGNO)
        (unspec:P [(match_operand:P 0 "immediate_operand" "s")
		    (pc)] UNSPEC_RELD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
#if TARGET_MACHO
  if (machopic_should_output_picbase_label ())
    {
      static char tmp[64];
      const char *cnam = machopic_get_function_picbase ();
      snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam);
      return tmp;
    }
  else
#else
  gcc_unreachable ();
#endif
    return "bcl 20,31,%0\n%0:";
}
  [(set_attr "type" "branch")
   (set_attr "cannot_copy" "yes")])

;; We need to restore the PIC register, at the site of nonlocal label.

(define_insn_and_split "nonlocal_goto_receiver"
  [(unspec_volatile [(const_int 0)] UNSPECV_NLGR)]
  "TARGET_MACHO && flag_pic"
  "#"
  "&& reload_completed"
  [(const_int 0)]
{
#if TARGET_MACHO
  if (crtl->uses_pic_offset_table)
    {
      static unsigned n = 0;
      rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
      rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
      rtx tmplrtx;
      char tmplab[20];

      ASM_GENERATE_INTERNAL_LABEL(tmplab, "Lnlgr", ++n);
      tmplrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));

      emit_insn (gen_reload_macho_picbase (tmplrtx));
      emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
      emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplrtx));
    }
  else
    /* Not using PIC reg, no reload needed.  */
    emit_note (NOTE_INSN_DELETED);
#else
  gcc_unreachable ();
#endif
  DONE;
})
Commit	Line	Data
49bd1d27	1	/* Machine description patterns for PowerPC running Darwin (Mac OS X).
a5544970	2	Copyright (C) 2004-2019 Free Software Foundation, Inc.
49bd1d27 SS	3	Contributed by Apple Computer Inc.
49bd1d27 SS	4
713e31f4	5	This file is part of GCC.
49bd1d27 SS	6
	7	GNU CC is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
2f83c7d6	9	the Free Software Foundation; either version 3, or (at your option)
49bd1d27 SS	10	any later version.
	11
	12	GNU CC is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
2f83c7d6 NC	18	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	19	;; <http://www.gnu.org/licenses/>. */
49bd1d27 SS	20
	21	(define_insn "adddi3_high"
	22	[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
	23	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
	24	(high:DI (match_operand 2 "" ""))))]
	25	"TARGET_MACHO && TARGET_64BIT"
b24a46be	26	"addis %0,%1,ha16(%2)")
49bd1d27	27
b8a55285	28	(define_insn "movdf_low_si"
c5dce79b	29	[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
b8a55285 AP	30	(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
b8a55285 AP	31	(match_operand 2 "" ""))))]
11d8d07e	32	"TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
b8a55285 AP	33	{
	34	switch (which_alternative)
	35	{
	36	case 0:
6c332313	37	return "lfd %0,lo16(%2)(%1)";
b8a55285 AP	38	case 1:
b8a55285 AP	39	{
b8a55285 AP	40	if (TARGET_POWERPC64 && TARGET_32BIT)
b8a55285 AP	41	/* Note, old assemblers didn't support relocation here. */
6c332313	42	return "ld %0,lo16(%2)(%1)";
b8a55285	43	else
af8e8908	44	{
6c332313 SB	45	output_asm_insn ("la %0,lo16(%2)(%1)", operands);
	46	output_asm_insn ("lwz %L0,4(%0)", operands);
	47	return ("lwz %0,0(%0)");
af8e8908	48	}
b8a55285 AP	49	}
b8a55285 AP	50	default:
992d08b1	51	gcc_unreachable ();
b8a55285	52	}
6c332313	53	}
b8a55285 AP	54	[(set_attr "type" "load")
	55	(set_attr "length" "4,12")])
	56
	57
49bd1d27 SS	58	(define_insn "movdf_low_di"
	59	[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
	60	(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
	61	(match_operand 2 "" ""))))]
11d8d07e	62	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
07a38de7 SB	63	"@
	64	lfd %0,lo16(%2)(%1)
	65	ld %0,lo16(%2)(%1)"
b24a46be	66	[(set_attr "type" "load")])
49bd1d27	67
b8a55285 AP	68	(define_insn "movdf_low_st_si"
	69	[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
	70	(match_operand 2 "" "")))
	71	(match_operand:DF 0 "gpc_reg_operand" "f"))]
11d8d07e	72	"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
b8a55285	73	"stfd %0,lo16(%2)(%1)"
b24a46be	74	[(set_attr "type" "store")])
b8a55285	75
49bd1d27 SS	76	(define_insn "movdf_low_st_di"
	77	[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
	78	(match_operand 2 "" "")))
	79	(match_operand:DF 0 "gpc_reg_operand" "f"))]
11d8d07e	80	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
49bd1d27	81	"stfd %0,lo16(%2)(%1)"
b24a46be	82	[(set_attr "type" "store")])
49bd1d27	83
b8a55285 AP	84	(define_insn "movsf_low_si"
	85	[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
	86	(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
	87	(match_operand 2 "" ""))))]
11d8d07e	88	"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
b8a55285 AP	89	"@
b8a55285 AP	90	lfs %0,lo16(%2)(%1)
6b39bc38	91	lwz %0,lo16(%2)(%1)"
b24a46be	92	[(set_attr "type" "load")])
b8a55285	93
49bd1d27 SS	94	(define_insn "movsf_low_di"
	95	[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
	96	(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
	97	(match_operand 2 "" ""))))]
11d8d07e	98	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
49bd1d27 SS	99	"@
49bd1d27 SS	100	lfs %0,lo16(%2)(%1)
6b39bc38	101	lwz %0,lo16(%2)(%1)"
b24a46be	102	[(set_attr "type" "load")])
49bd1d27	103
b8a55285 AP	104	(define_insn "movsf_low_st_si"
	105	[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
	106	(match_operand 2 "" "")))
	107	(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
11d8d07e	108	"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
b8a55285 AP	109	"@
b8a55285 AP	110	stfs %0,lo16(%2)(%1)
6b39bc38	111	stw %0,lo16(%2)(%1)"
b24a46be	112	[(set_attr "type" "store")])
b8a55285	113
49bd1d27 SS	114	(define_insn "movsf_low_st_di"
	115	[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
	116	(match_operand 2 "" "")))
	117	(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
11d8d07e	118	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
49bd1d27 SS	119	"@
49bd1d27 SS	120	stfs %0,lo16(%2)(%1)
6b39bc38	121	stw %0,lo16(%2)(%1)"
b24a46be	122	[(set_attr "type" "store")])
49bd1d27 SS	123
	124	;; 64-bit MachO load/store support
	125	(define_insn "movdi_low"
f4becba8 MM	126	[(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d")
f4becba8 MM	127	(mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
49bd1d27 SS	128	(match_operand 2 "" ""))))]
49bd1d27 SS	129	"TARGET_MACHO && TARGET_64BIT"
f4becba8	130	"@
6b39bc38	131	ld %0,lo16(%2)(%1)
f4becba8	132	lfd %0,lo16(%2)(%1)"
b24a46be	133	[(set_attr "type" "load")])
49bd1d27	134
b8a55285 AP	135	(define_insn "movsi_low_st"
	136	[(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
	137	(match_operand 2 "" "")))
	138	(match_operand:SI 0 "gpc_reg_operand" "r"))]
	139	"TARGET_MACHO && ! TARGET_64BIT"
6b39bc38	140	"stw %0,lo16(%2)(%1)"
b24a46be	141	[(set_attr "type" "store")])
b8a55285	142
49bd1d27	143	(define_insn "movdi_low_st"
f4becba8	144	[(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
49bd1d27	145	(match_operand 2 "" "")))
f4becba8	146	(match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
49bd1d27	147	"TARGET_MACHO && TARGET_64BIT"
f4becba8	148	"@
6b39bc38	149	std %0,lo16(%2)(%1)
f4becba8	150	stfd %0,lo16(%2)(%1)"
b24a46be	151	[(set_attr "type" "store")])
49bd1d27	152
b8a55285 AP	153	;; Mach-O PIC trickery.
b8a55285 AP	154	(define_expand "macho_high"
ad18eed2 SB	155	[(set (match_operand 0 "")
ad18eed2 SB	156	(high (match_operand 1 "")))]
b8a55285 AP	157	"TARGET_MACHO"
	158	{
	159	if (TARGET_64BIT)
	160	emit_insn (gen_macho_high_di (operands[0], operands[1]));
	161	else
	162	emit_insn (gen_macho_high_si (operands[0], operands[1]));
	163
	164	DONE;
	165	})
	166
	167	(define_insn "macho_high_si"
	168	[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
	169	(high:SI (match_operand 1 "" "")))]
	170	"TARGET_MACHO && ! TARGET_64BIT"
6b39bc38	171	"lis %0,ha16(%1)")
b8a55285 AP	172
b8a55285 AP	173
49bd1d27 SS	174	(define_insn "macho_high_di"
	175	[(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
	176	(high:DI (match_operand 1 "" "")))]
	177	"TARGET_MACHO && TARGET_64BIT"
6b39bc38	178	"lis %0,ha16(%1)")
49bd1d27	179
b8a55285	180	(define_expand "macho_low"
ad18eed2 SB	181	[(set (match_operand 0 "")
	182	(lo_sum (match_operand 1 "")
	183	(match_operand 2 "")))]
b8a55285 AP	184	"TARGET_MACHO"
	185	{
	186	if (TARGET_64BIT)
	187	emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
	188	else
	189	emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
	190
	191	DONE;
	192	})
	193
	194	(define_insn "macho_low_si"
76f93d99 SB	195	[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
76f93d99 SB	196	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
b8a55285 AP	197	(match_operand 2 "" "")))]
b8a55285 AP	198	"TARGET_MACHO && ! TARGET_64BIT"
76f93d99	199	"la %0,lo16(%2)(%1)")
b8a55285	200
49bd1d27	201	(define_insn "macho_low_di"
76f93d99 SB	202	[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
76f93d99 SB	203	(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
49bd1d27 SS	204	(match_operand 2 "" "")))]
49bd1d27 SS	205	"TARGET_MACHO && TARGET_64BIT"
76f93d99	206	"la %0,lo16(%2)(%1)")
49bd1d27 SS	207
49bd1d27 SS	208	(define_split
ad18eed2 SB	209	[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand")
	210	(match_operand:DI 1 "short_cint_operand")))
	211	(match_operand:V4SI 2 "register_operand"))
	212	(clobber (match_operand:DI 3 "gpc_reg_operand"))]
49bd1d27 SS	213	"TARGET_MACHO && TARGET_64BIT"
	214	[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
	215	(set (mem:V4SI (match_dup 3))
	216	(match_dup 2))]
	217	"")
	218
b8a55285	219	(define_expand "load_macho_picbase"
dd9ed099	220	[(set (reg LR_REGNO)
ad18eed2	221	(unspec [(match_operand 0 "")]
b8a55285 AP	222	UNSPEC_LD_MPIC))]
	223	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
	224	{
	225	if (TARGET_32BIT)
316fbf19	226	emit_insn (gen_load_macho_picbase_si (operands[0]));
b8a55285	227	else
316fbf19	228	emit_insn (gen_load_macho_picbase_di (operands[0]));
b8a55285 AP	229
	230	DONE;
	231	})
	232
dd9ed099 IS	233	(define_insn "load_macho_picbase_<mode>"
	234	[(set (reg:P LR_REGNO)
	235	(unspec:P [(match_operand:P 0 "immediate_operand" "s")
d5b5b8bf	236	(pc)] UNSPEC_LD_MPIC))]
b8a55285	237	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
e1c5c877	238	{
bd9534e2	239	#if TARGET_MACHO
e1c5c877	240	machopic_should_output_picbase_label (); /* Update for new func. */
bd9534e2 IS	241	#else
	242	gcc_unreachable ();
	243	#endif
6c332313	244	return "bcl 20,31,%0\n%0:";
e1c5c877	245	}
b8a55285	246	[(set_attr "type" "branch")
a79db151	247	(set_attr "cannot_copy" "yes")])
b8a55285	248
b8a55285	249	(define_expand "macho_correct_pic"
ad18eed2 SB	250	[(set (match_operand 0 "")
	251	(plus (match_operand 1 "")
	252	(unspec [(match_operand 2 "")
	253	(match_operand 3 "")]
b8a55285 AP	254	UNSPEC_MPIC_CORRECT)))]
	255	"DEFAULT_ABI == ABI_DARWIN"
	256	{
	257	if (TARGET_32BIT)
	258	emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
	259	operands[3]));
	260	else
	261	emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
	262	operands[3]));
	263
	264	DONE;
	265	})
	266
	267	(define_insn "macho_correct_pic_si"
	268	[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	269	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
	270	(unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
	271	(match_operand:SI 3 "immediate_operand" "s")]
	272	UNSPEC_MPIC_CORRECT)))]
	273	"DEFAULT_ABI == ABI_DARWIN"
	274	"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
	275	[(set_attr "length" "8")])
	276
49bd1d27 SS	277	(define_insn "macho_correct_pic_di"
	278	[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	279	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
	280	(unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
	281	(match_operand:DI 3 "immediate_operand" "s")]
	282	16)))]
ac9e2cff	283	"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
49bd1d27 SS	284	"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
	285	[(set_attr "length" "8")])
	286
e1c5c877	287	(define_expand "reload_macho_picbase"
dd9ed099	288	[(set (reg LR_REGNO)
ad18eed2	289	(unspec [(match_operand 0 "")]
e1c5c877 IS	290	UNSPEC_RELD_MPIC))]
	291	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
	292	{
	293	if (TARGET_32BIT)
	294	emit_insn (gen_reload_macho_picbase_si (operands[0]));
	295	else
	296	emit_insn (gen_reload_macho_picbase_di (operands[0]));
	297
	298	DONE;
	299	})
	300
dd9ed099 IS	301	(define_insn "reload_macho_picbase_<mode>"
	302	[(set (reg:P LR_REGNO)
	303	(unspec:P [(match_operand:P 0 "immediate_operand" "s")
e1c5c877 IS	304	(pc)] UNSPEC_RELD_MPIC))]
	305	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
	306	{
bd9534e2	307	#if TARGET_MACHO
e1c5c877 IS	308	if (machopic_should_output_picbase_label ())
	309	{
	310	static char tmp[64];
	311	const char *cnam = machopic_get_function_picbase ();
6c332313	312	snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam);
e1c5c877 IS	313	return tmp;
	314	}
	315	else
bd9534e2 IS	316	#else
	317	gcc_unreachable ();
	318	#endif
6c332313	319	return "bcl 20,31,%0\n%0:";
e1c5c877 IS	320	}
e1c5c877 IS	321	[(set_attr "type" "branch")
a79db151	322	(set_attr "cannot_copy" "yes")])
e1c5c877 IS	323
	324	;; We need to restore the PIC register, at the site of nonlocal label.
	325
	326	(define_insn_and_split "nonlocal_goto_receiver"
	327	[(unspec_volatile [(const_int 0)] UNSPECV_NLGR)]
	328	"TARGET_MACHO && flag_pic"
	329	"#"
	330	"&& reload_completed"
	331	[(const_int 0)]
	332	{
bd9534e2	333	#if TARGET_MACHO
e1c5c877 IS	334	if (crtl->uses_pic_offset_table)
	335	{
	336	static unsigned n = 0;
	337	rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
	338	rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
	339	rtx tmplrtx;
	340	char tmplab[20];
	341
	342	ASM_GENERATE_INTERNAL_LABEL(tmplab, "Lnlgr", ++n);
	343	tmplrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
	344
	345	emit_insn (gen_reload_macho_picbase (tmplrtx));
	346	emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
	347	emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplrtx));
	348	}
	349	else
	350	/* Not using PIC reg, no reload needed. */
	351	emit_note (NOTE_INSN_DELETED);
bd9534e2 IS	352	#else
	353	gcc_unreachable ();
	354	#endif
e1c5c877 IS	355	DONE;
e1c5c877 IS	356	})