[thirdparty/gcc.git] / gcc / config / rs6000 / darwin.md

/* Machine description patterns for PowerPC running Darwin (Mac OS X).
   Copyright (C) 2004-2013 Free Software Foundation, Inc.
   Contributed by Apple Computer Inc.

This file is part of GCC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.  */

(define_insn "adddi3_high"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
        (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
                 (high:DI (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_64BIT"
  "addis %0,%1,ha16(%2)"
  [(set_attr "length" "4")])

(define_insn "movdf_low_si"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
        (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
  "*
{
  switch (which_alternative)
    {
      case 0:
	return \"lfd %0,lo16(%2)(%1)\";
      case 1:
	{
	  if (TARGET_POWERPC64 && TARGET_32BIT)
	    /* Note, old assemblers didn't support relocation here.  */
	    return \"ld %0,lo16(%2)(%1)\";
	  else
	    {
	      output_asm_insn (\"la %0,lo16(%2)(%1)\", operands);
	      output_asm_insn (\"lwz %L0,4(%0)\", operands);
	      return (\"lwz %0,0(%0)\");
	    }
	}
      default:
	gcc_unreachable ();
    }
}"
  [(set_attr "type" "load")
   (set_attr "length" "4,12")])


(define_insn "movdf_low_di"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
        (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  "*
{
  switch (which_alternative)
    {
      case 0:
	return \"lfd %0,lo16(%2)(%1)\";
      case 1:
	return \"ld %0,lo16(%2)(%1)\";
      default:
	gcc_unreachable ();
    }
}"
  [(set_attr "type" "load")
   (set_attr "length" "4,4")])

(define_insn "movdf_low_st_si"
  [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
                           (match_operand 2 "" "")))
	(match_operand:DF 0 "gpc_reg_operand" "f"))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
  "stfd %0,lo16(%2)(%1)"
  [(set_attr "type" "store")
   (set_attr "length" "4")])

(define_insn "movdf_low_st_di"
  [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
                           (match_operand 2 "" "")))
	(match_operand:DF 0 "gpc_reg_operand" "f"))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  "stfd %0,lo16(%2)(%1)"
  [(set_attr "type" "store")
   (set_attr "length" "4")])

(define_insn "movsf_low_si"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
        (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
  "@
   lfs %0,lo16(%2)(%1)
   lwz %0,lo16(%2)(%1)"
  [(set_attr "type" "load")
   (set_attr "length" "4")])

(define_insn "movsf_low_di"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
        (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  "@
   lfs %0,lo16(%2)(%1)
   lwz %0,lo16(%2)(%1)"
  [(set_attr "type" "load")
   (set_attr "length" "4")])

(define_insn "movsf_low_st_si"
  [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" "")))
	(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
  "@
   stfs %0,lo16(%2)(%1)
   stw %0,lo16(%2)(%1)"
  [(set_attr "type" "store")
   (set_attr "length" "4")])

(define_insn "movsf_low_st_di"
  [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" "")))
	(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
  "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  "@
   stfs %0,lo16(%2)(%1)
   stw %0,lo16(%2)(%1)"
  [(set_attr "type" "store")
   (set_attr "length" "4")])

;; 64-bit MachO load/store support
(define_insn "movdi_low"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d")
        (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" ""))))]
  "TARGET_MACHO && TARGET_64BIT"
  "@
   ld %0,lo16(%2)(%1)
   lfd %0,lo16(%2)(%1)"
  [(set_attr "type" "load")
   (set_attr "length" "4")])

(define_insn "movsi_low_st"
  [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
                           (match_operand 2 "" "")))
	(match_operand:SI 0 "gpc_reg_operand" "r"))]
  "TARGET_MACHO && ! TARGET_64BIT"
  "stw %0,lo16(%2)(%1)"
  [(set_attr "type" "store")
   (set_attr "length" "4")])

(define_insn "movdi_low_st"
  [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
                           (match_operand 2 "" "")))
	(match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
  "TARGET_MACHO && TARGET_64BIT"
  "@
   std %0,lo16(%2)(%1)
   stfd %0,lo16(%2)(%1)"
  [(set_attr "type" "store")
   (set_attr "length" "4")])

;; Mach-O PIC trickery.
(define_expand "macho_high"
  [(set (match_operand 0 "" "")
	(high (match_operand 1 "" "")))]
  "TARGET_MACHO"
{
  if (TARGET_64BIT)
    emit_insn (gen_macho_high_di (operands[0], operands[1]));
  else
    emit_insn (gen_macho_high_si (operands[0], operands[1]));

  DONE;
})

(define_insn "macho_high_si"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
	(high:SI (match_operand 1 "" "")))]
  "TARGET_MACHO && ! TARGET_64BIT"
  "lis %0,ha16(%1)")
  

(define_insn "macho_high_di"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
	(high:DI (match_operand 1 "" "")))]
  "TARGET_MACHO && TARGET_64BIT"
  "lis %0,ha16(%1)")

(define_expand "macho_low"
  [(set (match_operand 0 "" "")
	(lo_sum (match_operand 1 "" "")
		   (match_operand 2 "" "")))]
   "TARGET_MACHO"
{
  if (TARGET_64BIT)
    emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
  else
    emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));

  DONE;
})

(define_insn "macho_low_si"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
		   (match_operand 2 "" "")))]
   "TARGET_MACHO && ! TARGET_64BIT"
   "@
    la %0,lo16(%2)(%1)
    addic %0,%1,lo16(%2)")

(define_insn "macho_low_di"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
	(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
		   (match_operand 2 "" "")))]
   "TARGET_MACHO && TARGET_64BIT"
   "@
    la %0,lo16(%2)(%1)
    addic %0,%1,lo16(%2)")

(define_split
  [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
			 (match_operand:DI 1 "short_cint_operand" "")))
	(match_operand:V4SI 2 "register_operand" ""))
   (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
  "TARGET_MACHO && TARGET_64BIT"
  [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
   (set (mem:V4SI (match_dup 3))
	(match_dup 2))]
  "")

(define_expand "load_macho_picbase"
  [(set (reg:SI 65)
        (unspec [(match_operand 0 "" "")]
                   UNSPEC_LD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
  if (TARGET_32BIT)
    emit_insn (gen_load_macho_picbase_si (operands[0]));
  else
    emit_insn (gen_load_macho_picbase_di (operands[0]));

  DONE;
})

(define_insn "load_macho_picbase_si"
  [(set (reg:SI 65)
	(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
		    (pc)] UNSPEC_LD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
  machopic_should_output_picbase_label (); /* Update for new func.  */
  return "bcl 20,31,%0\\n%0:";
}
  [(set_attr "type" "branch")
   (set_attr "length" "4")])

(define_insn "load_macho_picbase_di"
  [(set (reg:DI 65)
	(unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
		    (pc)] UNSPEC_LD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
{
  machopic_should_output_picbase_label (); /* Update for new func.  */
  return "bcl 20,31,%0\\n%0:";
}
  [(set_attr "type" "branch")
   (set_attr "length" "4")])

(define_expand "macho_correct_pic"
  [(set (match_operand 0 "" "")
	(plus (match_operand 1 "" "")
		 (unspec [(match_operand 2 "" "")
			     (match_operand 3 "" "")]
			    UNSPEC_MPIC_CORRECT)))]
  "DEFAULT_ABI == ABI_DARWIN"
{
  if (TARGET_32BIT)
    emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
	       operands[3]));
  else
    emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
	       operands[3]));

  DONE;
})

(define_insn "macho_correct_pic_si"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
			     (match_operand:SI 3 "immediate_operand" "s")]
			    UNSPEC_MPIC_CORRECT)))]
  "DEFAULT_ABI == ABI_DARWIN"
  "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
  [(set_attr "length" "8")])

(define_insn "macho_correct_pic_di"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
		 (unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
			     (match_operand:DI 3 "immediate_operand" "s")]
			    16)))]
  "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
  "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
  [(set_attr "length" "8")])

(define_insn "*call_indirect_nonlocal_darwin64"
  [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
	 (match_operand 1 "" "g,g,g,g"))
   (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
   (clobber (reg:SI 65))]
  "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
{
  return "b%T0l";
}
  [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
   (set_attr "length" "4,4,8,8")])

(define_insn "*call_nonlocal_darwin64"
  [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
	 (match_operand 1 "" "g,g"))
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
   (clobber (reg:SI 65))]
  "(DEFAULT_ABI == ABI_DARWIN)
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
{
#if TARGET_MACHO
  return output_call(insn, operands, 0, 2);
#else
  gcc_unreachable ();
#endif
}
  [(set_attr "type" "branch,branch")
   (set_attr "length" "4,8")])

(define_insn "*call_value_indirect_nonlocal_darwin64"
  [(set (match_operand 0 "" "")
	(call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
	      (match_operand 2 "" "g,g,g,g")))
   (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
   (clobber (reg:SI 65))]
  "DEFAULT_ABI == ABI_DARWIN"
{
  return "b%T1l";
}
  [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
   (set_attr "length" "4,4,8,8")])

(define_insn "*call_value_nonlocal_darwin64"
  [(set (match_operand 0 "" "")
	(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
	      (match_operand 2 "" "g,g")))
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
   (clobber (reg:SI 65))]
  "(DEFAULT_ABI == ABI_DARWIN)
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
{
#if TARGET_MACHO
  return output_call(insn, operands, 1, 3);
#else
  gcc_unreachable ();
#endif
}
  [(set_attr "type" "branch,branch")
   (set_attr "length" "4,8")])

(define_expand "reload_macho_picbase"
  [(set (reg:SI 65)
        (unspec [(match_operand 0 "" "")]
                   UNSPEC_RELD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
  if (TARGET_32BIT)
    emit_insn (gen_reload_macho_picbase_si (operands[0]));
  else
    emit_insn (gen_reload_macho_picbase_di (operands[0]));

  DONE;
})

(define_insn "reload_macho_picbase_si"
  [(set (reg:SI 65)
        (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
		    (pc)] UNSPEC_RELD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
  if (machopic_should_output_picbase_label ())
    {
      static char tmp[64];
      const char *cnam = machopic_get_function_picbase ();
      snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
      return tmp;
    }
  else
    return "bcl 20,31,%0\\n%0:";
}
  [(set_attr "type" "branch")
   (set_attr "length" "4")])

(define_insn "reload_macho_picbase_di"
  [(set (reg:DI 65)
	(unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
		    (pc)] UNSPEC_RELD_MPIC))]
  "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
{
  if (machopic_should_output_picbase_label ())
    {
      static char tmp[64];
      const char *cnam = machopic_get_function_picbase ();
      snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
      return tmp;
    }
  else
    return "bcl 20,31,%0\\n%0:";
}
  [(set_attr "type" "branch")
   (set_attr "length" "4")])

;; We need to restore the PIC register, at the site of nonlocal label.

(define_insn_and_split "nonlocal_goto_receiver"
  [(unspec_volatile [(const_int 0)] UNSPECV_NLGR)]
  "TARGET_MACHO && flag_pic"
  "#"
  "&& reload_completed"
  [(const_int 0)]
{
  if (crtl->uses_pic_offset_table)
    {
      static unsigned n = 0;
      rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
      rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
      rtx tmplrtx;
      char tmplab[20];

      ASM_GENERATE_INTERNAL_LABEL(tmplab, "Lnlgr", ++n);
      tmplrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));

      emit_insn (gen_reload_macho_picbase (tmplrtx));
      emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
      emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplrtx));
    }
  else
    /* Not using PIC reg, no reload needed.  */
    emit_note (NOTE_INSN_DELETED);

  DONE;
})
Commit	Line	Data
49bd1d27	1	/* Machine description patterns for PowerPC running Darwin (Mac OS X).
d1e082c2	2	Copyright (C) 2004-2013 Free Software Foundation, Inc.
49bd1d27 SS	3	Contributed by Apple Computer Inc.
49bd1d27 SS	4
713e31f4	5	This file is part of GCC.
49bd1d27 SS	6
	7	GNU CC is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
2f83c7d6	9	the Free Software Foundation; either version 3, or (at your option)
49bd1d27 SS	10	any later version.
	11
	12	GNU CC is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
2f83c7d6 NC	18	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	19	;; <http://www.gnu.org/licenses/>. */
49bd1d27 SS	20
	21	(define_insn "adddi3_high"
	22	[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
	23	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
	24	(high:DI (match_operand 2 "" ""))))]
	25	"TARGET_MACHO && TARGET_64BIT"
6b39bc38	26	"addis %0,%1,ha16(%2)"
49bd1d27 SS	27	[(set_attr "length" "4")])
49bd1d27 SS	28
b8a55285	29	(define_insn "movdf_low_si"
c5dce79b	30	[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
b8a55285 AP	31	(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
b8a55285 AP	32	(match_operand 2 "" ""))))]
c5dce79b	33	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
b8a55285 AP	34	"*
	35	{
	36	switch (which_alternative)
	37	{
	38	case 0:
	39	return \"lfd %0,lo16(%2)(%1)\";
	40	case 1:
	41	{
b8a55285 AP	42	if (TARGET_POWERPC64 && TARGET_32BIT)
	43	/* Note, old assemblers didn't support relocation here. */
	44	return \"ld %0,lo16(%2)(%1)\";
	45	else
af8e8908	46	{
6b39bc38 SB	47	output_asm_insn (\"la %0,lo16(%2)(%1)\", operands);
	48	output_asm_insn (\"lwz %L0,4(%0)\", operands);
	49	return (\"lwz %0,0(%0)\");
af8e8908	50	}
b8a55285 AP	51	}
b8a55285 AP	52	default:
992d08b1	53	gcc_unreachable ();
b8a55285 AP	54	}
	55	}"
	56	[(set_attr "type" "load")
	57	(set_attr "length" "4,12")])
	58
	59
49bd1d27 SS	60	(define_insn "movdf_low_di"
	61	[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
	62	(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
	63	(match_operand 2 "" ""))))]
	64	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
	65	"*
	66	{
	67	switch (which_alternative)
	68	{
	69	case 0:
	70	return \"lfd %0,lo16(%2)(%1)\";
	71	case 1:
e87d92f4	72	return \"ld %0,lo16(%2)(%1)\";
49bd1d27	73	default:
992d08b1	74	gcc_unreachable ();
49bd1d27 SS	75	}
	76	}"
	77	[(set_attr "type" "load")
e87d92f4	78	(set_attr "length" "4,4")])
49bd1d27	79
b8a55285 AP	80	(define_insn "movdf_low_st_si"
	81	[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
	82	(match_operand 2 "" "")))
	83	(match_operand:DF 0 "gpc_reg_operand" "f"))]
	84	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
	85	"stfd %0,lo16(%2)(%1)"
	86	[(set_attr "type" "store")
	87	(set_attr "length" "4")])
	88
49bd1d27 SS	89	(define_insn "movdf_low_st_di"
	90	[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
	91	(match_operand 2 "" "")))
	92	(match_operand:DF 0 "gpc_reg_operand" "f"))]
	93	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
	94	"stfd %0,lo16(%2)(%1)"
	95	[(set_attr "type" "store")
	96	(set_attr "length" "4")])
	97
b8a55285 AP	98	(define_insn "movsf_low_si"
	99	[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
	100	(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
	101	(match_operand 2 "" ""))))]
	102	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
	103	"@
	104	lfs %0,lo16(%2)(%1)
6b39bc38	105	lwz %0,lo16(%2)(%1)"
b8a55285 AP	106	[(set_attr "type" "load")
	107	(set_attr "length" "4")])
	108
49bd1d27 SS	109	(define_insn "movsf_low_di"
	110	[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
	111	(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
	112	(match_operand 2 "" ""))))]
	113	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
	114	"@
	115	lfs %0,lo16(%2)(%1)
6b39bc38	116	lwz %0,lo16(%2)(%1)"
49bd1d27 SS	117	[(set_attr "type" "load")
	118	(set_attr "length" "4")])
	119
b8a55285 AP	120	(define_insn "movsf_low_st_si"
	121	[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
	122	(match_operand 2 "" "")))
	123	(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
	124	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
	125	"@
	126	stfs %0,lo16(%2)(%1)
6b39bc38	127	stw %0,lo16(%2)(%1)"
b8a55285 AP	128	[(set_attr "type" "store")
	129	(set_attr "length" "4")])
	130
49bd1d27 SS	131	(define_insn "movsf_low_st_di"
	132	[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
	133	(match_operand 2 "" "")))
	134	(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
	135	"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
	136	"@
	137	stfs %0,lo16(%2)(%1)
6b39bc38	138	stw %0,lo16(%2)(%1)"
49bd1d27 SS	139	[(set_attr "type" "store")
	140	(set_attr "length" "4")])
	141
	142	;; 64-bit MachO load/store support
	143	(define_insn "movdi_low"
f4becba8 MM	144	[(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d")
f4becba8 MM	145	(mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
49bd1d27 SS	146	(match_operand 2 "" ""))))]
49bd1d27 SS	147	"TARGET_MACHO && TARGET_64BIT"
f4becba8	148	"@
6b39bc38	149	ld %0,lo16(%2)(%1)
f4becba8	150	lfd %0,lo16(%2)(%1)"
49bd1d27 SS	151	[(set_attr "type" "load")
	152	(set_attr "length" "4")])
	153
b8a55285 AP	154	(define_insn "movsi_low_st"
	155	[(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
	156	(match_operand 2 "" "")))
	157	(match_operand:SI 0 "gpc_reg_operand" "r"))]
	158	"TARGET_MACHO && ! TARGET_64BIT"
6b39bc38	159	"stw %0,lo16(%2)(%1)"
b8a55285 AP	160	[(set_attr "type" "store")
	161	(set_attr "length" "4")])
	162
49bd1d27	163	(define_insn "movdi_low_st"
f4becba8	164	[(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
49bd1d27	165	(match_operand 2 "" "")))
f4becba8	166	(match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
49bd1d27	167	"TARGET_MACHO && TARGET_64BIT"
f4becba8	168	"@
6b39bc38	169	std %0,lo16(%2)(%1)
f4becba8	170	stfd %0,lo16(%2)(%1)"
49bd1d27 SS	171	[(set_attr "type" "store")
	172	(set_attr "length" "4")])
	173
b8a55285 AP	174	;; Mach-O PIC trickery.
	175	(define_expand "macho_high"
	176	[(set (match_operand 0 "" "")
	177	(high (match_operand 1 "" "")))]
	178	"TARGET_MACHO"
	179	{
	180	if (TARGET_64BIT)
	181	emit_insn (gen_macho_high_di (operands[0], operands[1]));
	182	else
	183	emit_insn (gen_macho_high_si (operands[0], operands[1]));
	184
	185	DONE;
	186	})
	187
	188	(define_insn "macho_high_si"
	189	[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
	190	(high:SI (match_operand 1 "" "")))]
	191	"TARGET_MACHO && ! TARGET_64BIT"
6b39bc38	192	"lis %0,ha16(%1)")
b8a55285 AP	193
b8a55285 AP	194
49bd1d27 SS	195	(define_insn "macho_high_di"
	196	[(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
	197	(high:DI (match_operand 1 "" "")))]
	198	"TARGET_MACHO && TARGET_64BIT"
6b39bc38	199	"lis %0,ha16(%1)")
49bd1d27	200
b8a55285 AP	201	(define_expand "macho_low"
	202	[(set (match_operand 0 "" "")
	203	(lo_sum (match_operand 1 "" "")
	204	(match_operand 2 "" "")))]
	205	"TARGET_MACHO"
	206	{
	207	if (TARGET_64BIT)
	208	emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
	209	else
	210	emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
	211
	212	DONE;
	213	})
	214
	215	(define_insn "macho_low_si"
	216	[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	217	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
	218	(match_operand 2 "" "")))]
	219	"TARGET_MACHO && ! TARGET_64BIT"
	220	"@
6b39bc38 SB	221	la %0,lo16(%2)(%1)
6b39bc38 SB	222	addic %0,%1,lo16(%2)")
b8a55285	223
49bd1d27 SS	224	(define_insn "macho_low_di"
	225	[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
	226	(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
	227	(match_operand 2 "" "")))]
	228	"TARGET_MACHO && TARGET_64BIT"
	229	"@
6b39bc38 SB	230	la %0,lo16(%2)(%1)
6b39bc38 SB	231	addic %0,%1,lo16(%2)")
49bd1d27 SS	232
	233	(define_split
	234	[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
	235	(match_operand:DI 1 "short_cint_operand" "")))
	236	(match_operand:V4SI 2 "register_operand" ""))
	237	(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
	238	"TARGET_MACHO && TARGET_64BIT"
	239	[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
	240	(set (mem:V4SI (match_dup 3))
	241	(match_dup 2))]
	242	"")
	243
b8a55285	244	(define_expand "load_macho_picbase"
316fbf19 EC	245	[(set (reg:SI 65)
316fbf19 EC	246	(unspec [(match_operand 0 "" "")]
b8a55285 AP	247	UNSPEC_LD_MPIC))]
	248	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
	249	{
	250	if (TARGET_32BIT)
316fbf19	251	emit_insn (gen_load_macho_picbase_si (operands[0]));
b8a55285	252	else
316fbf19	253	emit_insn (gen_load_macho_picbase_di (operands[0]));
b8a55285 AP	254
	255	DONE;
	256	})
	257
	258	(define_insn "load_macho_picbase_si"
e65a3857 DE	259	[(set (reg:SI 65)
e65a3857 DE	260	(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
d5b5b8bf	261	(pc)] UNSPEC_LD_MPIC))]
b8a55285	262	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
e1c5c877 IS	263	{
	264	machopic_should_output_picbase_label (); /* Update for new func. */
	265	return "bcl 20,31,%0\\n%0:";
	266	}
b8a55285 AP	267	[(set_attr "type" "branch")
	268	(set_attr "length" "4")])
	269
49bd1d27	270	(define_insn "load_macho_picbase_di"
e65a3857 DE	271	[(set (reg:DI 65)
e65a3857 DE	272	(unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
d5b5b8bf	273	(pc)] UNSPEC_LD_MPIC))]
ac9e2cff	274	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
e1c5c877 IS	275	{
	276	machopic_should_output_picbase_label (); /* Update for new func. */
	277	return "bcl 20,31,%0\\n%0:";
	278	}
49bd1d27 SS	279	[(set_attr "type" "branch")
	280	(set_attr "length" "4")])
	281
b8a55285 AP	282	(define_expand "macho_correct_pic"
	283	[(set (match_operand 0 "" "")
	284	(plus (match_operand 1 "" "")
	285	(unspec [(match_operand 2 "" "")
	286	(match_operand 3 "" "")]
	287	UNSPEC_MPIC_CORRECT)))]
	288	"DEFAULT_ABI == ABI_DARWIN"
	289	{
	290	if (TARGET_32BIT)
	291	emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
	292	operands[3]));
	293	else
	294	emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
	295	operands[3]));
	296
	297	DONE;
	298	})
	299
	300	(define_insn "macho_correct_pic_si"
	301	[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	302	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
	303	(unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
	304	(match_operand:SI 3 "immediate_operand" "s")]
	305	UNSPEC_MPIC_CORRECT)))]
	306	"DEFAULT_ABI == ABI_DARWIN"
	307	"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
	308	[(set_attr "length" "8")])
	309
49bd1d27 SS	310	(define_insn "macho_correct_pic_di"
	311	[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	312	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
	313	(unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
	314	(match_operand:DI 3 "immediate_operand" "s")]
	315	16)))]
ac9e2cff	316	"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
49bd1d27 SS	317	"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
	318	[(set_attr "length" "8")])
	319
	320	(define_insn "*call_indirect_nonlocal_darwin64"
	321	[(call (mem:SI (match_operand:DI 0 "register_operand" "c,l,c,l"))
	322	(match_operand 1 "" "g,g,g,g"))
	323	(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
e65a3857	324	(clobber (reg:SI 65))]
ac9e2cff	325	"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
49bd1d27 SS	326	{
	327	return "b%T0l";
	328	}
	329	[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
	330	(set_attr "length" "4,4,8,8")])
	331
	332	(define_insn "*call_nonlocal_darwin64"
	333	[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
	334	(match_operand 1 "" "g,g"))
	335	(use (match_operand:SI 2 "immediate_operand" "O,n"))
e65a3857	336	(clobber (reg:SI 65))]
49bd1d27 SS	337	"(DEFAULT_ABI == ABI_DARWIN)
	338	&& (INTVAL (operands[2]) & CALL_LONG) == 0"
	339	{
	340	#if TARGET_MACHO
	341	return output_call(insn, operands, 0, 2);
13a98f14	342	#else
992d08b1	343	gcc_unreachable ();
49bd1d27 SS	344	#endif
	345	}
	346	[(set_attr "type" "branch,branch")
	347	(set_attr "length" "4,8")])
	348
	349	(define_insn "*call_value_indirect_nonlocal_darwin64"
	350	[(set (match_operand 0 "" "")
	351	(call (mem:SI (match_operand:DI 1 "register_operand" "c,l,c,l"))
	352	(match_operand 2 "" "g,g,g,g")))
	353	(use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
e65a3857	354	(clobber (reg:SI 65))]
49bd1d27 SS	355	"DEFAULT_ABI == ABI_DARWIN"
	356	{
	357	return "b%T1l";
	358	}
	359	[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
	360	(set_attr "length" "4,4,8,8")])
	361
	362	(define_insn "*call_value_nonlocal_darwin64"
	363	[(set (match_operand 0 "" "")
	364	(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
	365	(match_operand 2 "" "g,g")))
	366	(use (match_operand:SI 3 "immediate_operand" "O,n"))
e65a3857	367	(clobber (reg:SI 65))]
49bd1d27 SS	368	"(DEFAULT_ABI == ABI_DARWIN)
	369	&& (INTVAL (operands[3]) & CALL_LONG) == 0"
	370	{
	371	#if TARGET_MACHO
	372	return output_call(insn, operands, 1, 3);
13a98f14	373	#else
992d08b1	374	gcc_unreachable ();
13a98f14	375	#endif
49bd1d27 SS	376	}
	377	[(set_attr "type" "branch,branch")
	378	(set_attr "length" "4,8")])
e1c5c877 IS	379
	380	(define_expand "reload_macho_picbase"
	381	[(set (reg:SI 65)
	382	(unspec [(match_operand 0 "" "")]
	383	UNSPEC_RELD_MPIC))]
	384	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
	385	{
	386	if (TARGET_32BIT)
	387	emit_insn (gen_reload_macho_picbase_si (operands[0]));
	388	else
	389	emit_insn (gen_reload_macho_picbase_di (operands[0]));
	390
	391	DONE;
	392	})
	393
	394	(define_insn "reload_macho_picbase_si"
	395	[(set (reg:SI 65)
	396	(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
	397	(pc)] UNSPEC_RELD_MPIC))]
	398	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
	399	{
	400	if (machopic_should_output_picbase_label ())
	401	{
	402	static char tmp[64];
	403	const char *cnam = machopic_get_function_picbase ();
	404	snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
	405	return tmp;
	406	}
	407	else
	408	return "bcl 20,31,%0\\n%0:";
	409	}
	410	[(set_attr "type" "branch")
	411	(set_attr "length" "4")])
	412
	413	(define_insn "reload_macho_picbase_di"
	414	[(set (reg:DI 65)
	415	(unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
	416	(pc)] UNSPEC_RELD_MPIC))]
	417	"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
	418	{
	419	if (machopic_should_output_picbase_label ())
	420	{
	421	static char tmp[64];
	422	const char *cnam = machopic_get_function_picbase ();
	423	snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
	424	return tmp;
	425	}
	426	else
	427	return "bcl 20,31,%0\\n%0:";
	428	}
	429	[(set_attr "type" "branch")
	430	(set_attr "length" "4")])
	431
	432	;; We need to restore the PIC register, at the site of nonlocal label.
	433
	434	(define_insn_and_split "nonlocal_goto_receiver"
	435	[(unspec_volatile [(const_int 0)] UNSPECV_NLGR)]
	436	"TARGET_MACHO && flag_pic"
	437	"#"
	438	"&& reload_completed"
	439	[(const_int 0)]
	440	{
	441	if (crtl->uses_pic_offset_table)
	442	{
443	static unsigned n = 0;
444	rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
445	rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
446	rtx tmplrtx;
447	char tmplab[20];
448
449	ASM_GENERATE_INTERNAL_LABEL(tmplab, "Lnlgr", ++n);
450	tmplrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
451
452	emit_insn (gen_reload_macho_picbase (tmplrtx));
453	emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
454	emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplrtx));
455	}
456	else
457	/* Not using PIC reg, no reload needed. */
458	emit_note (NOTE_INSN_DELETED);
459
460	DONE;
461	})