[thirdparty/gcc.git] / gcc / config / rs6000 / dfp.md

;; Decimal Floating Point (DFP) patterns.
;; Copyright (C) 2007-2019 Free Software Foundation, Inc.
;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
;; (bergner@vnet.ibm.com).

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;;
;; UNSPEC usage
;;

(define_c_enum "unspec"
  [UNSPEC_MOVSD_LOAD
   UNSPEC_MOVSD_STORE
  ])


(define_insn "movsd_store"
  [(set (match_operand:DD 0 "nonimmediate_operand" "=m")
	(unspec:DD [(match_operand:SD 1 "input_operand" "d")]
		   UNSPEC_MOVSD_STORE))]
  "(gpc_reg_operand (operands[0], DDmode)
   || gpc_reg_operand (operands[1], SDmode))
   && TARGET_HARD_FLOAT"
  "stfd%U0%X0 %1,%0"
  [(set_attr "type" "fpstore")])

(define_insn "movsd_load"
  [(set (match_operand:SD 0 "nonimmediate_operand" "=f")
	(unspec:SD [(match_operand:DD 1 "input_operand" "m")]
		   UNSPEC_MOVSD_LOAD))]
  "(gpc_reg_operand (operands[0], SDmode)
   || gpc_reg_operand (operands[1], DDmode))
   && TARGET_HARD_FLOAT"
  "lfd%U1%X1 %0,%1"
  [(set_attr "type" "fpload")])

;; Hardware support for decimal floating point operations.

(define_insn "extendsddd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
  "TARGET_DFP"
  "dctdp %0,%1"
  [(set_attr "type" "dfp")])

(define_expand "extendsdtd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
{
  rtx tmp = gen_reg_rtx (DDmode);
  emit_insn (gen_extendsddd2 (tmp, operands[1]));
  emit_insn (gen_extendddtd2 (operands[0], tmp));
  DONE;
})

(define_insn "truncddsd2"
  [(set (match_operand:SD 0 "gpc_reg_operand" "=f")
	(float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "drsp %0,%1"
  [(set_attr "type" "dfp")])

(define_insn "negdd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_HARD_FLOAT"
  "fneg %0,%1"
  [(set_attr "type" "fpsimple")])

(define_insn "absdd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_HARD_FLOAT"
  "fabs %0,%1"
  [(set_attr "type" "fpsimple")])

(define_insn "*nabsdd2_fpr"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
  "TARGET_HARD_FLOAT"
  "fnabs %0,%1"
  [(set_attr "type" "fpsimple")])

(define_insn "negtd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
	(neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
  "TARGET_HARD_FLOAT"
  "@
   fneg %0,%1
   fneg %0,%1\;fmr %L0,%L1"
  [(set_attr "type" "fpsimple")
   (set_attr "length" "4,8")])

(define_insn "abstd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
	(abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
  "TARGET_HARD_FLOAT"
  "@
   fabs %0,%1
   fabs %0,%1\;fmr %L0,%L1"
  [(set_attr "type" "fpsimple")
   (set_attr "length" "4,8")])

(define_insn "*nabstd2_fpr"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
	(neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
  "TARGET_HARD_FLOAT"
  "@
   fnabs %0,%1
   fnabs %0,%1\;fmr %L0,%L1"
  [(set_attr "type" "fpsimple")
   (set_attr "length" "4,8")])

;; Hardware support for decimal floating point operations.

(define_insn "extendddtd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dctqpq %0,%1"
  [(set_attr "type" "dfp")])

;; The result of drdpq is an even/odd register pair with the converted
;; value in the even register and zero in the odd register.
;; FIXME: Avoid the register move by using a reload constraint to ensure
;; that the result is the first of the pair receiving the result of drdpq.

(define_insn "trunctddd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
   (clobber (match_scratch:TD 2 "=d"))]
  "TARGET_DFP"
  "drdpq %2,%1\;fmr %0,%2"
  [(set_attr "type" "dfp")
   (set_attr "length" "8")])

(define_insn "adddd3"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
		 (match_operand:DD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dadd %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "addtd3"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
		 (match_operand:TD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "daddq %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "subdd3"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(minus:DD (match_operand:DD 1 "gpc_reg_operand" "d")
		  (match_operand:DD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dsub %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "subtd3"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(minus:TD (match_operand:TD 1 "gpc_reg_operand" "d")
		  (match_operand:TD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dsubq %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "muldd3"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
		 (match_operand:DD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dmul %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "multd3"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
		 (match_operand:TD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dmulq %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "divdd3"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(div:DD (match_operand:DD 1 "gpc_reg_operand" "d")
		(match_operand:DD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "ddiv %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "divtd3"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(div:TD (match_operand:TD 1 "gpc_reg_operand" "d")
		(match_operand:TD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "ddivq %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "*cmpdd_internal1"
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
	(compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d")
		      (match_operand:DD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dcmpu %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "*cmptd_internal1"
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
	(compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d")
		      (match_operand:TD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dcmpuq %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "floatdidd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP && TARGET_POPCNTD"
  "dcffix %0,%1"
  [(set_attr "type" "dfp")])

(define_insn "floatditd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dcffixq %0,%1"
  [(set_attr "type" "dfp")])

;; Convert a decimal64 to a decimal64 whose value is an integer.
;; This is the first stage of converting it to an integer type.

(define_insn "ftruncdd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "drintn. 0,%0,%1,1"
  [(set_attr "type" "dfp")])

;; Convert a decimal64 whose value is an integer to an actual integer.
;; This is the second stage of converting decimal float to integer type.

(define_insn "fixdddi2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
	(fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dctfix %0,%1"
  [(set_attr "type" "dfp")])

;; Convert a decimal128 to a decimal128 whose value is an integer.
;; This is the first stage of converting it to an integer type.

(define_insn "ftrunctd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "drintnq. 0,%0,%1,1"
  [(set_attr "type" "dfp")])

;; Convert a decimal128 whose value is an integer to an actual integer.
;; This is the second stage of converting decimal float to integer type.

(define_insn "fixtddi2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
	(fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dctfixq %0,%1"
  [(set_attr "type" "dfp")])

\f
;; Decimal builtin support

(define_c_enum "unspec"
  [UNSPEC_DDEDPD
   UNSPEC_DENBCD
   UNSPEC_DXEX
   UNSPEC_DIEX
   UNSPEC_DSCLI
   UNSPEC_DTSTSFI
   UNSPEC_DSCRI])

(define_code_iterator DFP_TEST [eq lt gt unordered])

(define_mode_iterator D64_D128 [DD TD])

(define_mode_attr dfp_suffix [(DD "")
			      (TD "q")])

(define_insn "dfp_ddedpd_<mode>"
  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
	(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")
			  (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
			 UNSPEC_DDEDPD))]
  "TARGET_DFP"
  "ddedpd<dfp_suffix> %1,%0,%2"
  [(set_attr "type" "dfp")])

(define_insn "dfp_denbcd_<mode>"
  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
	(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")
			  (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
			 UNSPEC_DENBCD))]
  "TARGET_DFP"
  "denbcd<dfp_suffix> %1,%0,%2"
  [(set_attr "type" "dfp")])

(define_insn "dfp_dxex_<mode>"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
	(unspec:DI [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]
		   UNSPEC_DXEX))]
  "TARGET_DFP"
  "dxex<dfp_suffix> %0,%1"
  [(set_attr "type" "dfp")])

(define_insn "dfp_diex_<mode>"
  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
	(unspec:D64_D128 [(match_operand:DI 1 "gpc_reg_operand" "d")
			  (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
			 UNSPEC_DXEX))]
  "TARGET_DFP"
  "diex<dfp_suffix> %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_expand "dfptstsfi_<code>_<mode>"
  [(set (match_dup 3)
	(compare:CCFP
         (unspec:D64_D128
	  [(match_operand:SI 1 "const_int_operand")
	   (match_operand:D64_D128 2 "gpc_reg_operand")]
	  UNSPEC_DTSTSFI)
	 (match_dup 4)))
   (set (match_operand:SI 0 "register_operand")
   	(DFP_TEST:SI (match_dup 3)
		     (const_int 0)))
  ]
  "TARGET_P9_MISC"
{
  operands[3] = gen_reg_rtx (CCFPmode);
  operands[4] = const0_rtx;
})

(define_insn "*dfp_sgnfcnc_<mode>"
  [(set (match_operand:CCFP 0 "" "=y")
        (compare:CCFP
	 (unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n")
	 	           (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
          UNSPEC_DTSTSFI)
	 (match_operand:SI 3 "zero_constant" "j")))]
  "TARGET_P9_MISC"
{
  /* If immediate operand is greater than 63, it will behave as if
     the value had been 63.  The code generator does not support
     immediate operand values greater than 63.  */
  if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
    operands[1] = GEN_INT (63);
  return "dtstsfi<dfp_suffix> %0,%1,%2";
}
  [(set_attr "type" "fp")])

(define_insn "dfp_dscli_<mode>"
  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
	(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
			  (match_operand:QI 2 "immediate_operand" "i")]
			 UNSPEC_DSCLI))]
  "TARGET_DFP"
  "dscli<dfp_suffix> %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "dfp_dscri_<mode>"
  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
	(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
			  (match_operand:QI 2 "immediate_operand" "i")]
			 UNSPEC_DSCRI))]
  "TARGET_DFP"
  "dscri<dfp_suffix> %0,%1,%2"
  [(set_attr "type" "dfp")])
Commit	Line	Data
7393f7f8	1	;; Decimal Floating Point (DFP) patterns.
a5544970	2	;; Copyright (C) 2007-2019 Free Software Foundation, Inc.
7393f7f8 BE	3	;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
	4	;; (bergner@vnet.ibm.com).
	5
	6	;; This file is part of GCC.
	7
	8	;; GCC is free software; you can redistribute it and/or modify it
	9	;; under the terms of the GNU General Public License as published
2f83c7d6	10	;; by the Free Software Foundation; either version 3, or (at your
7393f7f8 BE	11	;; option) any later version.
	12
	13	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	14	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	16	;; License for more details.
	17
	18	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	19	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	20	;; <http://www.gnu.org/licenses/>.
7393f7f8	21
e41b2a33 PB	22	;;
	23	;; UNSPEC usage
	24	;;
	25
f3c33d9d MM	26	(define_c_enum "unspec"
	27	[UNSPEC_MOVSD_LOAD
	28	UNSPEC_MOVSD_STORE
e41b2a33 PB	29	])
	30
	31
e41b2a33 PB	32	(define_insn "movsd_store"
e41b2a33 PB	33	[(set (match_operand:DD 0 "nonimmediate_operand" "=m")
799dbb0f	34	(unspec:DD [(match_operand:SD 1 "input_operand" "d")]
e41b2a33 PB	35	UNSPEC_MOVSD_STORE))]
	36	"(gpc_reg_operand (operands[0], DDmode)
	37	\|\| gpc_reg_operand (operands[1], SDmode))
11d8d07e	38	&& TARGET_HARD_FLOAT"
e41b2a33	39	"stfd%U0%X0 %1,%0"
b24a46be	40	[(set_attr "type" "fpstore")])
e41b2a33 PB	41
	42	(define_insn "movsd_load"
	43	[(set (match_operand:SD 0 "nonimmediate_operand" "=f")
	44	(unspec:SD [(match_operand:DD 1 "input_operand" "m")]
	45	UNSPEC_MOVSD_LOAD))]
	46	"(gpc_reg_operand (operands[0], SDmode)
	47	\|\| gpc_reg_operand (operands[1], DDmode))
11d8d07e	48	&& TARGET_HARD_FLOAT"
e41b2a33	49	"lfd%U1%X1 %0,%1"
b24a46be	50	[(set_attr "type" "fpload")])
e41b2a33 PB	51
	52	;; Hardware support for decimal floating point operations.
	53
	54	(define_insn "extendsddd2"
799dbb0f	55	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
e41b2a33 PB	56	(float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
	57	"TARGET_DFP"
	58	"dctdp %0,%1"
eda328bf	59	[(set_attr "type" "dfp")])
e41b2a33 PB	60
e41b2a33 PB	61	(define_expand "extendsdtd2"
799dbb0f ME	62	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
799dbb0f ME	63	(float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))]
e41b2a33 PB	64	"TARGET_DFP"
	65	{
	66	rtx tmp = gen_reg_rtx (DDmode);
	67	emit_insn (gen_extendsddd2 (tmp, operands[1]));
	68	emit_insn (gen_extendddtd2 (operands[0], tmp));
	69	DONE;
	70	})
	71
	72	(define_insn "truncddsd2"
	73	[(set (match_operand:SD 0 "gpc_reg_operand" "=f")
799dbb0f	74	(float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
e41b2a33 PB	75	"TARGET_DFP"
e41b2a33 PB	76	"drsp %0,%1"
eda328bf	77	[(set_attr "type" "dfp")])
e41b2a33	78
11d8d07e	79	(define_insn "negdd2"
799dbb0f ME	80	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
799dbb0f ME	81	(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
11d8d07e	82	"TARGET_HARD_FLOAT"
c092b045	83	"fneg %0,%1"
7c788ce2	84	[(set_attr "type" "fpsimple")])
c092b045	85
11d8d07e	86	(define_insn "absdd2"
799dbb0f ME	87	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
799dbb0f ME	88	(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
11d8d07e	89	"TARGET_HARD_FLOAT"
c092b045	90	"fabs %0,%1"
7c788ce2	91	[(set_attr "type" "fpsimple")])
c092b045 PB	92
c092b045 PB	93	(define_insn "*nabsdd2_fpr"
799dbb0f ME	94	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
799dbb0f ME	95	(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
11d8d07e	96	"TARGET_HARD_FLOAT"
c092b045	97	"fnabs %0,%1"
7c788ce2	98	[(set_attr "type" "fpsimple")])
c092b045	99
11d8d07e	100	(define_insn "negtd2"
e2323f5b PB	101	[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
e2323f5b PB	102	(neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
11d8d07e	103	"TARGET_HARD_FLOAT"
e2323f5b PB	104	"@
	105	fneg %0,%1
	106	fneg %0,%1\;fmr %L0,%L1"
7c788ce2	107	[(set_attr "type" "fpsimple")
e2323f5b	108	(set_attr "length" "4,8")])
c092b045	109
11d8d07e	110	(define_insn "abstd2"
e2323f5b PB	111	[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
e2323f5b PB	112	(abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
11d8d07e	113	"TARGET_HARD_FLOAT"
e2323f5b PB	114	"@
	115	fabs %0,%1
	116	fabs %0,%1\;fmr %L0,%L1"
7c788ce2	117	[(set_attr "type" "fpsimple")
e2323f5b	118	(set_attr "length" "4,8")])
c092b045 PB	119
c092b045 PB	120	(define_insn "*nabstd2_fpr"
e2323f5b PB	121	[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
e2323f5b PB	122	(neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
11d8d07e	123	"TARGET_HARD_FLOAT"
e2323f5b PB	124	"@
	125	fnabs %0,%1
	126	fnabs %0,%1\;fmr %L0,%L1"
7c788ce2	127	[(set_attr "type" "fpsimple")
e2323f5b	128	(set_attr "length" "4,8")])
c092b045	129
6ef9a246 JJ	130	;; Hardware support for decimal floating point operations.
	131
	132	(define_insn "extendddtd2"
799dbb0f ME	133	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
799dbb0f ME	134	(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
6ef9a246 JJ	135	"TARGET_DFP"
6ef9a246 JJ	136	"dctqpq %0,%1"
eda328bf	137	[(set_attr "type" "dfp")])
6ef9a246 JJ	138
	139	;; The result of drdpq is an even/odd register pair with the converted
	140	;; value in the even register and zero in the odd register.
	141	;; FIXME: Avoid the register move by using a reload constraint to ensure
	142	;; that the result is the first of the pair receiving the result of drdpq.
	143
	144	(define_insn "trunctddd2"
799dbb0f ME	145	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	146	(float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
	147	(clobber (match_scratch:TD 2 "=d"))]
6ef9a246 JJ	148	"TARGET_DFP"
6ef9a246 JJ	149	"drdpq %2,%1\;fmr %0,%2"
eda328bf	150	[(set_attr "type" "dfp")
521466e5	151	(set_attr "length" "8")])
6ef9a246 JJ	152
6ef9a246 JJ	153	(define_insn "adddd3"
799dbb0f ME	154	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	155	(plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
	156	(match_operand:DD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	157	"TARGET_DFP"
6ef9a246 JJ	158	"dadd %0,%1,%2"
eda328bf	159	[(set_attr "type" "dfp")])
6ef9a246 JJ	160
6ef9a246 JJ	161	(define_insn "addtd3"
799dbb0f ME	162	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	163	(plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
	164	(match_operand:TD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	165	"TARGET_DFP"
6ef9a246 JJ	166	"daddq %0,%1,%2"
eda328bf	167	[(set_attr "type" "dfp")])
6ef9a246 JJ	168
6ef9a246 JJ	169	(define_insn "subdd3"
799dbb0f ME	170	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	171	(minus:DD (match_operand:DD 1 "gpc_reg_operand" "d")
	172	(match_operand:DD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	173	"TARGET_DFP"
6ef9a246 JJ	174	"dsub %0,%1,%2"
eda328bf	175	[(set_attr "type" "dfp")])
6ef9a246 JJ	176
6ef9a246 JJ	177	(define_insn "subtd3"
799dbb0f ME	178	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	179	(minus:TD (match_operand:TD 1 "gpc_reg_operand" "d")
	180	(match_operand:TD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	181	"TARGET_DFP"
6ef9a246 JJ	182	"dsubq %0,%1,%2"
eda328bf	183	[(set_attr "type" "dfp")])
6ef9a246 JJ	184
6ef9a246 JJ	185	(define_insn "muldd3"
799dbb0f ME	186	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	187	(mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
	188	(match_operand:DD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	189	"TARGET_DFP"
6ef9a246 JJ	190	"dmul %0,%1,%2"
eda328bf	191	[(set_attr "type" "dfp")])
6ef9a246 JJ	192
6ef9a246 JJ	193	(define_insn "multd3"
799dbb0f ME	194	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	195	(mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
	196	(match_operand:TD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	197	"TARGET_DFP"
6ef9a246 JJ	198	"dmulq %0,%1,%2"
eda328bf	199	[(set_attr "type" "dfp")])
6ef9a246 JJ	200
6ef9a246 JJ	201	(define_insn "divdd3"
799dbb0f ME	202	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	203	(div:DD (match_operand:DD 1 "gpc_reg_operand" "d")
	204	(match_operand:DD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	205	"TARGET_DFP"
6ef9a246 JJ	206	"ddiv %0,%1,%2"
eda328bf	207	[(set_attr "type" "dfp")])
6ef9a246 JJ	208
6ef9a246 JJ	209	(define_insn "divtd3"
799dbb0f ME	210	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	211	(div:TD (match_operand:TD 1 "gpc_reg_operand" "d")
	212	(match_operand:TD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	213	"TARGET_DFP"
6ef9a246 JJ	214	"ddivq %0,%1,%2"
eda328bf	215	[(set_attr "type" "dfp")])
6ef9a246 JJ	216
	217	(define_insn "*cmpdd_internal1"
	218	[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
799dbb0f ME	219	(compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d")
799dbb0f ME	220	(match_operand:DD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	221	"TARGET_DFP"
6ef9a246 JJ	222	"dcmpu %0,%1,%2"
eda328bf	223	[(set_attr "type" "dfp")])
6ef9a246 JJ	224
	225	(define_insn "*cmptd_internal1"
	226	[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
799dbb0f ME	227	(compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d")
799dbb0f ME	228	(match_operand:TD 2 "gpc_reg_operand" "d")))]
6ef9a246 JJ	229	"TARGET_DFP"
6ef9a246 JJ	230	"dcmpuq %0,%1,%2"
eda328bf	231	[(set_attr "type" "dfp")])
6ef9a246	232
6f975f93 PB	233	(define_insn "floatdidd2"
	234	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	235	(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
	236	"TARGET_DFP && TARGET_POPCNTD"
	237	"dcffix %0,%1"
eda328bf	238	[(set_attr "type" "dfp")])
6f975f93	239
6ef9a246	240	(define_insn "floatditd2"
799dbb0f ME	241	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
799dbb0f ME	242	(float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
6ef9a246 JJ	243	"TARGET_DFP"
6ef9a246 JJ	244	"dcffixq %0,%1"
eda328bf	245	[(set_attr "type" "dfp")])
6ef9a246 JJ	246
	247	;; Convert a decimal64 to a decimal64 whose value is an integer.
	248	;; This is the first stage of converting it to an integer type.
	249
	250	(define_insn "ftruncdd2"
799dbb0f ME	251	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
799dbb0f ME	252	(fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
6ef9a246 JJ	253	"TARGET_DFP"
6ef9a246 JJ	254	"drintn. 0,%0,%1,1"
eda328bf	255	[(set_attr "type" "dfp")])
6ef9a246 JJ	256
	257	;; Convert a decimal64 whose value is an integer to an actual integer.
	258	;; This is the second stage of converting decimal float to integer type.
	259
	260	(define_insn "fixdddi2"
799dbb0f ME	261	[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
799dbb0f ME	262	(fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))]
6ef9a246 JJ	263	"TARGET_DFP"
6ef9a246 JJ	264	"dctfix %0,%1"
eda328bf	265	[(set_attr "type" "dfp")])
6ef9a246 JJ	266
	267	;; Convert a decimal128 to a decimal128 whose value is an integer.
	268	;; This is the first stage of converting it to an integer type.
	269
	270	(define_insn "ftrunctd2"
799dbb0f ME	271	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
799dbb0f ME	272	(fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
6ef9a246 JJ	273	"TARGET_DFP"
6ef9a246 JJ	274	"drintnq. 0,%0,%1,1"
eda328bf	275	[(set_attr "type" "dfp")])
6ef9a246 JJ	276
	277	;; Convert a decimal128 whose value is an integer to an actual integer.
	278	;; This is the second stage of converting decimal float to integer type.
	279
	280	(define_insn "fixtddi2"
799dbb0f ME	281	[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
799dbb0f ME	282	(fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))]
6ef9a246 JJ	283	"TARGET_DFP"
6ef9a246 JJ	284	"dctfixq %0,%1"
eda328bf	285	[(set_attr "type" "dfp")])
06b39289 MM	286
	287	\f
	288	;; Decimal builtin support
	289
	290	(define_c_enum "unspec"
	291	[UNSPEC_DDEDPD
	292	UNSPEC_DENBCD
	293	UNSPEC_DXEX
	294	UNSPEC_DIEX
	295	UNSPEC_DSCLI
5a3a6a5e	296	UNSPEC_DTSTSFI
06b39289 MM	297	UNSPEC_DSCRI])
06b39289 MM	298
5a3a6a5e KN	299	(define_code_iterator DFP_TEST [eq lt gt unordered])
5a3a6a5e KN	300
06b39289 MM	301	(define_mode_iterator D64_D128 [DD TD])
	302
	303	(define_mode_attr dfp_suffix [(DD "")
	304	(TD "q")])
	305
	306	(define_insn "dfp_ddedpd_<mode>"
	307	[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
	308	(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")
	309	(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
	310	UNSPEC_DDEDPD))]
	311	"TARGET_DFP"
	312	"ddedpd<dfp_suffix> %1,%0,%2"
eda328bf	313	[(set_attr "type" "dfp")])
06b39289 MM	314
	315	(define_insn "dfp_denbcd_<mode>"
	316	[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
	317	(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")
	318	(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
	319	UNSPEC_DENBCD))]
	320	"TARGET_DFP"
	321	"denbcd<dfp_suffix> %1,%0,%2"
eda328bf	322	[(set_attr "type" "dfp")])
06b39289 MM	323
06b39289 MM	324	(define_insn "dfp_dxex_<mode>"
05dc406d PB	325	[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
	326	(unspec:DI [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]
	327	UNSPEC_DXEX))]
06b39289 MM	328	"TARGET_DFP"
06b39289 MM	329	"dxex<dfp_suffix> %0,%1"
eda328bf	330	[(set_attr "type" "dfp")])
06b39289 MM	331
	332	(define_insn "dfp_diex_<mode>"
	333	[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
05dc406d	334	(unspec:D64_D128 [(match_operand:DI 1 "gpc_reg_operand" "d")
06b39289 MM	335	(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
	336	UNSPEC_DXEX))]
	337	"TARGET_DFP"
	338	"diex<dfp_suffix> %0,%1,%2"
eda328bf	339	[(set_attr "type" "dfp")])
06b39289	340
5a3a6a5e KN	341	(define_expand "dfptstsfi_<code>_<mode>"
	342	[(set (match_dup 3)
	343	(compare:CCFP
	344	(unspec:D64_D128
ad18eed2 SB	345	[(match_operand:SI 1 "const_int_operand")
ad18eed2 SB	346	(match_operand:D64_D128 2 "gpc_reg_operand")]
5a3a6a5e KN	347	UNSPEC_DTSTSFI)
5a3a6a5e KN	348	(match_dup 4)))
ad18eed2	349	(set (match_operand:SI 0 "register_operand")
5a3a6a5e KN	350	(DFP_TEST:SI (match_dup 3)
	351	(const_int 0)))
	352	]
	353	"TARGET_P9_MISC"
	354	{
	355	operands[3] = gen_reg_rtx (CCFPmode);
	356	operands[4] = const0_rtx;
	357	})
	358
	359	(define_insn "*dfp_sgnfcnc_<mode>"
	360	[(set (match_operand:CCFP 0 "" "=y")
	361	(compare:CCFP
	362	(unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n")
	363	(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
	364	UNSPEC_DTSTSFI)
	365	(match_operand:SI 3 "zero_constant" "j")))]
	366	"TARGET_P9_MISC"
	367	{
	368	/* If immediate operand is greater than 63, it will behave as if
	369	the value had been 63. The code generator does not support
	370	immediate operand values greater than 63. */
	371	if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
	372	operands[1] = GEN_INT (63);
	373	return "dtstsfi<dfp_suffix> %0,%1,%2";
	374	}
	375	[(set_attr "type" "fp")])
	376
06b39289 MM	377	(define_insn "dfp_dscli_<mode>"
	378	[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
	379	(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
	380	(match_operand:QI 2 "immediate_operand" "i")]
	381	UNSPEC_DSCLI))]
	382	"TARGET_DFP"
	383	"dscli<dfp_suffix> %0,%1,%2"
eda328bf	384	[(set_attr "type" "dfp")])
06b39289 MM	385
	386	(define_insn "dfp_dscri_<mode>"
	387	[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
	388	(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
	389	(match_operand:QI 2 "immediate_operand" "i")]
	390	UNSPEC_DSCRI))]
	391	"TARGET_DFP"
	392	"dscri<dfp_suffix> %0,%1,%2"
eda328bf	393	[(set_attr "type" "dfp")])