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73edc44b | 1 | ;; Pipeline description for Motorola PowerPC e300c3 core. |
f1717362 | 2 | ;; Copyright (C) 2008-2016 Free Software Foundation, Inc. |
73edc44b | 3 | ;; Contributed by Edmar Wienskoski (edmar@freescale.com) |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | (define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire") | |
22 | (define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most") | |
23 | ||
24 | ;; We don't simulate general issue queue (GIC). If we have SU insn | |
25 | ;; and then SU1 insn, they can not be issued on the same cycle | |
26 | ;; (although SU1 insn and then SU insn can be issued) because the SU | |
27 | ;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle | |
28 | ;; multipass insn scheduling will find the situation and issue the SU1 | |
29 | ;; insn and then the SU insn. | |
30 | (define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most") | |
31 | ||
32 | ;; We could describe completion buffers slots in combination with the | |
33 | ;; retirement units and the order of completion but the result | |
34 | ;; automaton would behave in the same way because we can not describe | |
35 | ;; real latency time with taking in order completion into account. | |
36 | ;; Actually we could define the real latency time by querying reserved | |
37 | ;; automaton units but the current scheduler uses latency time before | |
38 | ;; issuing insns and making any reservations. | |
39 | ;; | |
40 | ;; So our description is aimed to achieve a insn schedule in which the | |
41 | ;; insns would not wait in the completion buffer. | |
42 | (define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire") | |
43 | ||
44 | ;; Branch unit: | |
45 | (define_cpu_unit "ppce300c3_bu" "ppce300c3_most") | |
46 | ||
47 | ;; IU: | |
48 | (define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most") | |
49 | ||
50 | ;; IU: This used to describe non-pipelined division. | |
51 | (define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long") | |
52 | ||
53 | ;; SRU: | |
54 | (define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most") | |
55 | ||
56 | ;; Here we simplified LSU unit description not describing the stages. | |
57 | (define_cpu_unit "ppce300c3_lsu" "ppce300c3_most") | |
58 | ||
59 | ;; FPU: | |
60 | (define_cpu_unit "ppce300c3_fpu" "ppce300c3_most") | |
61 | ||
62 | ;; The following units are used to make automata deterministic | |
63 | (define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most") | |
64 | (define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most") | |
65 | (define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire") | |
66 | (define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most") | |
67 | ||
68 | ;; The following sets to make automata deterministic when option ndfa is used. | |
69 | (presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0") | |
70 | (presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0") | |
71 | (presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0") | |
72 | (presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0") | |
73 | ||
74 | ;; Some useful abbreviations. | |
75 | (define_reservation "ppce300c3_decode" | |
76 | "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0") | |
77 | (define_reservation "ppce300c3_issue" | |
78 | "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0") | |
79 | (define_reservation "ppce300c3_retire" | |
80 | "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0") | |
81 | (define_reservation "ppce300c3_iu_stage0" | |
82 | "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0") | |
83 | ||
84 | ;; Compares can be executed either one of the IU or SRU | |
85 | (define_insn_reservation "ppce300c3_cmp" 1 | |
cd1e80f3 | 86 | (and (ior (eq_attr "type" "cmp") |
88599a7a | 87 | (and (eq_attr "type" "add,logical,shift,exts") |
7d307a6a | 88 | (eq_attr "dot" "yes"))) |
73edc44b | 89 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) |
90 | "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \ | |
91 | +ppce300c3_retire") | |
92 | ||
93 | ;; Other one cycle IU insns | |
94 | (define_insn_reservation "ppce300c3_iu" 1 | |
7f15413b | 95 | (and (ior (eq_attr "type" "integer,insert,isel") |
88599a7a | 96 | (and (eq_attr "type" "add,logical,shift,exts") |
7f15413b | 97 | (eq_attr "dot" "no"))) |
73edc44b | 98 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) |
99 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire") | |
100 | ||
101 | ;; Branch. Actually this latency time is not used by the scheduler. | |
102 | (define_insn_reservation "ppce300c3_branch" 1 | |
103 | (and (eq_attr "type" "jmpreg,branch") | |
104 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | |
105 | "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire") | |
106 | ||
107 | ;; Multiply is non-pipelined but can be executed in any IU | |
108 | (define_insn_reservation "ppce300c3_multiply" 2 | |
86c149d4 | 109 | (and (eq_attr "type" "mul") |
73edc44b | 110 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) |
111 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \ | |
112 | ppce300c3_iu_stage0+ppce300c3_retire") | |
113 | ||
114 | ;; Divide. We use the average latency time here. We omit reserving a | |
115 | ;; retire unit because of the result automata will be huge. | |
116 | (define_insn_reservation "ppce300c3_divide" 20 | |
90e4483f | 117 | (and (eq_attr "type" "div") |
73edc44b | 118 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) |
119 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\ | |
120 | ppce300c3_mu_div*19") | |
121 | ||
122 | ;; CR logical | |
123 | (define_insn_reservation "ppce300c3_cr_logical" 1 | |
124 | (and (eq_attr "type" "cr_logical,delayed_cr") | |
125 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | |
126 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") | |
127 | ||
128 | ;; Mfcr | |
129 | (define_insn_reservation "ppce300c3_mfcr" 1 | |
130 | (and (eq_attr "type" "mfcr") | |
131 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | |
132 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") | |
133 | ||
134 | ;; Mtcrf | |
135 | (define_insn_reservation "ppce300c3_mtcrf" 1 | |
136 | (and (eq_attr "type" "mtcr") | |
137 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | |
138 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") | |
139 | ||
140 | ;; Mtjmpr | |
141 | (define_insn_reservation "ppce300c3_mtjmpr" 1 | |
142 | (and (eq_attr "type" "mtjmpr,mfjmpr") | |
143 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | |
144 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") | |
145 | ||
146 | ;; Float point instructions | |
147 | (define_insn_reservation "ppce300c3_fpcompare" 3 | |
148 | (and (eq_attr "type" "fpcompare") | |
149 | (eq_attr "cpu" "ppce300c3")) | |
150 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") | |
151 | ||
152 | (define_insn_reservation "ppce300c3_fp" 3 | |
153 | (and (eq_attr "type" "fp") | |
154 | (eq_attr "cpu" "ppce300c3")) | |
155 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") | |
156 | ||
157 | (define_insn_reservation "ppce300c3_dmul" 4 | |
158 | (and (eq_attr "type" "dmul") | |
159 | (eq_attr "cpu" "ppce300c3")) | |
160 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire") | |
161 | ||
162 | ; Divides are not pipelined | |
163 | (define_insn_reservation "ppce300c3_sdiv" 18 | |
164 | (and (eq_attr "type" "sdiv") | |
165 | (eq_attr "cpu" "ppce300c3")) | |
166 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17") | |
167 | ||
168 | (define_insn_reservation "ppce300c3_ddiv" 33 | |
169 | (and (eq_attr "type" "ddiv") | |
170 | (eq_attr "cpu" "ppce300c3")) | |
171 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32") | |
172 | ||
173 | ;; Loads | |
174 | (define_insn_reservation "ppce300c3_load" 2 | |
631c977b | 175 | (and (eq_attr "type" "load") |
73edc44b | 176 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) |
177 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") | |
178 | ||
179 | (define_insn_reservation "ppce300c3_fpload" 2 | |
631c977b | 180 | (and (eq_attr "type" "fpload") |
73edc44b | 181 | (eq_attr "cpu" "ppce300c3")) |
182 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") | |
183 | ||
184 | ;; Stores. | |
185 | (define_insn_reservation "ppce300c3_store" 2 | |
631c977b | 186 | (and (eq_attr "type" "store") |
73edc44b | 187 | (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) |
188 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") | |
189 | ||
190 | (define_insn_reservation "ppce300c3_fpstore" 2 | |
631c977b | 191 | (and (eq_attr "type" "fpstore") |
73edc44b | 192 | (eq_attr "cpu" "ppce300c3")) |
193 | "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") |