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683ed19e | 1 | ;; Pipeline description for Freescale PowerPC e5500 core. |
8d9254fc | 2 | ;; Copyright (C) 2012-2020 Free Software Foundation, Inc. |
683ed19e EW |
3 | ;; Contributed by Edmar Wienskoski (edmar@freescale.com) |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ;; | |
21 | ;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU | |
22 | ;; Max issue 3 insns/clock cycle (includes 1 branch) | |
23 | ||
24 | (define_automaton "e5500_most,e5500_long") | |
25 | (define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most") | |
26 | ||
27 | ;; SFX. | |
28 | (define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most") | |
29 | ||
30 | ;; CFX. | |
31 | (define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most") | |
32 | ||
33 | ;; Non-pipelined division. | |
34 | (define_cpu_unit "e5500_cfx_div" "e5500_long") | |
35 | ||
36 | ;; LSU. | |
37 | (define_cpu_unit "e5500_lsu" "e5500_most") | |
38 | ||
39 | ;; FPU. | |
40 | (define_cpu_unit "e5500_fpu" "e5500_long") | |
41 | ||
42 | ;; BU. | |
43 | (define_cpu_unit "e5500_bu" "e5500_most") | |
44 | ||
45 | ;; The following units are used to make the automata deterministic. | |
46 | (define_cpu_unit "present_e5500_decode_0" "e5500_most") | |
47 | (define_cpu_unit "present_e5500_sfx_0" "e5500_most") | |
48 | (presence_set "present_e5500_decode_0" "e5500_decode_0") | |
49 | (presence_set "present_e5500_sfx_0" "e5500_sfx_0") | |
50 | ||
51 | ;; Some useful abbreviations. | |
52 | (define_reservation "e5500_decode" | |
53 | "e5500_decode_0|e5500_decode_1+present_e5500_decode_0") | |
54 | (define_reservation "e5500_sfx" | |
55 | "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0") | |
56 | ||
57 | ;; SFX. | |
58 | (define_insn_reservation "e5500_sfx" 1 | |
79430730 SB |
59 | (and (ior (eq_attr "type" "integer,insert,cntlz") |
60 | (and (eq_attr "type" "add,logical,exts") | |
0cbb4f58 | 61 | (eq_attr "dot" "no")) |
892e7fa6 SB |
62 | (and (eq_attr "type" "shift") |
63 | (eq_attr "var_shift" "no"))) | |
683ed19e EW |
64 | (eq_attr "cpu" "ppce5500")) |
65 | "e5500_decode,e5500_sfx") | |
66 | ||
67 | (define_insn_reservation "e5500_sfx2" 2 | |
f5ae5a23 | 68 | (and (ior (eq_attr "type" "cmp,trap") |
79430730 | 69 | (and (eq_attr "type" "add,logical,exts") |
a35dd1fa SB |
70 | (eq_attr "dot" "yes")) |
71 | (and (eq_attr "type" "shift") | |
72 | (eq_attr "dot" "yes") | |
73 | (eq_attr "var_shift" "no"))) | |
683ed19e EW |
74 | (eq_attr "cpu" "ppce5500")) |
75 | "e5500_decode,e5500_sfx") | |
76 | ||
77 | (define_insn_reservation "e5500_delayed" 2 | |
892e7fa6 SB |
78 | (and (eq_attr "type" "shift") |
79 | (eq_attr "var_shift" "yes") | |
683ed19e EW |
80 | (eq_attr "cpu" "ppce5500")) |
81 | "e5500_decode,e5500_sfx*2") | |
82 | ||
83 | (define_insn_reservation "e5500_two" 2 | |
84 | (and (eq_attr "type" "two") | |
85 | (eq_attr "cpu" "ppce5500")) | |
86 | "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx") | |
87 | ||
88 | (define_insn_reservation "e5500_three" 3 | |
89 | (and (eq_attr "type" "three") | |
90 | (eq_attr "cpu" "ppce5500")) | |
91 | "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx") | |
92 | ||
93 | ;; SFX - Mfcr. | |
94 | (define_insn_reservation "e5500_mfcr" 4 | |
95 | (and (eq_attr "type" "mfcr") | |
96 | (eq_attr "cpu" "ppce5500")) | |
97 | "e5500_decode,e5500_sfx_0*4") | |
98 | ||
99 | ;; SFX - Mtcrf. | |
100 | (define_insn_reservation "e5500_mtcrf" 1 | |
101 | (and (eq_attr "type" "mtcr") | |
102 | (eq_attr "cpu" "ppce5500")) | |
103 | "e5500_decode,e5500_sfx_0") | |
104 | ||
105 | ;; SFX - Mtjmpr. | |
106 | (define_insn_reservation "e5500_mtjmpr" 1 | |
107 | (and (eq_attr "type" "mtjmpr,mfjmpr") | |
108 | (eq_attr "cpu" "ppce5500")) | |
109 | "e5500_decode,e5500_sfx") | |
110 | ||
111 | ;; CFX - Multiply. | |
112 | (define_insn_reservation "e5500_multiply" 4 | |
e0528ed9 SB |
113 | (and (eq_attr "type" "mul") |
114 | (eq_attr "dot" "no") | |
115 | (eq_attr "size" "32") | |
683ed19e EW |
116 | (eq_attr "cpu" "ppce5500")) |
117 | "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1") | |
118 | ||
119 | (define_insn_reservation "e5500_multiply_i" 5 | |
e0528ed9 SB |
120 | (and (eq_attr "type" "mul") |
121 | (ior (eq_attr "dot" "yes") | |
122 | (eq_attr "size" "8,16")) | |
683ed19e EW |
123 | (eq_attr "cpu" "ppce5500")) |
124 | "e5500_decode,e5500_cfx_stage0,\ | |
125 | e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1") | |
126 | ||
127 | ;; CFX - Divide. | |
128 | (define_insn_reservation "e5500_divide" 16 | |
441e02a5 SB |
129 | (and (eq_attr "type" "div") |
130 | (eq_attr "size" "32") | |
683ed19e EW |
131 | (eq_attr "cpu" "ppce5500")) |
132 | "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ | |
133 | e5500_cfx_div*15") | |
134 | ||
135 | (define_insn_reservation "e5500_divide_d" 26 | |
441e02a5 SB |
136 | (and (eq_attr "type" "div") |
137 | (eq_attr "size" "64") | |
683ed19e EW |
138 | (eq_attr "cpu" "ppce5500")) |
139 | "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ | |
140 | e5500_cfx_div*25") | |
141 | ||
142 | ;; LSU - Loads. | |
143 | (define_insn_reservation "e5500_load" 3 | |
d839f53b | 144 | (and (eq_attr "type" "load,load_l,sync") |
683ed19e EW |
145 | (eq_attr "cpu" "ppce5500")) |
146 | "e5500_decode,e5500_lsu") | |
147 | ||
148 | (define_insn_reservation "e5500_fpload" 4 | |
d839f53b | 149 | (and (eq_attr "type" "fpload") |
683ed19e EW |
150 | (eq_attr "cpu" "ppce5500")) |
151 | "e5500_decode,e5500_lsu") | |
152 | ||
153 | ;; LSU - Stores. | |
154 | (define_insn_reservation "e5500_store" 3 | |
d839f53b | 155 | (and (eq_attr "type" "store,store_c") |
683ed19e EW |
156 | (eq_attr "cpu" "ppce5500")) |
157 | "e5500_decode,e5500_lsu") | |
158 | ||
159 | (define_insn_reservation "e5500_fpstore" 3 | |
d839f53b | 160 | (and (eq_attr "type" "fpstore") |
683ed19e EW |
161 | (eq_attr "cpu" "ppce5500")) |
162 | "e5500_decode,e5500_lsu") | |
163 | ||
164 | ;; FP. | |
165 | (define_insn_reservation "e5500_float" 7 | |
166 | (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul") | |
167 | (eq_attr "cpu" "ppce5500")) | |
168 | "e5500_decode,e5500_fpu") | |
169 | ||
170 | (define_insn_reservation "e5500_sdiv" 20 | |
171 | (and (eq_attr "type" "sdiv") | |
172 | (eq_attr "cpu" "ppce5500")) | |
173 | "e5500_decode,e5500_fpu*20") | |
174 | ||
175 | (define_insn_reservation "e5500_ddiv" 35 | |
176 | (and (eq_attr "type" "ddiv") | |
177 | (eq_attr "cpu" "ppce5500")) | |
178 | "e5500_decode,e5500_fpu*35") | |
179 | ||
180 | ;; BU. | |
181 | (define_insn_reservation "e5500_branch" 1 | |
182 | (and (eq_attr "type" "jmpreg,branch,isync") | |
183 | (eq_attr "cpu" "ppce5500")) | |
184 | "e5500_decode,e5500_bu") | |
185 | ||
186 | ;; BU - CR logical. | |
187 | (define_insn_reservation "e5500_cr_logical" 1 | |
34ef0745 | 188 | (and (eq_attr "type" "cr_logical") |
683ed19e EW |
189 | (eq_attr "cpu" "ppce5500")) |
190 | "e5500_decode,e5500_bu") |