]>
Commit | Line | Data |
---|---|---|
b770074c | 1 | ;; Pipeline description for Freescale PowerPC e6500 core. |
fbd26352 | 2 | ;; Copyright (C) 2012-2019 Free Software Foundation, Inc. |
b770074c | 3 | ;; Contributed by Edmar Wienskoski (edmar@freescale.com) |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ;; | |
21 | ;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM | |
22 | ;; Max issue 3 insns/clock cycle (includes 1 branch) | |
23 | ||
24 | (define_automaton "e6500_most,e6500_long,e6500_vec") | |
25 | (define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most") | |
26 | ||
27 | ;; SFX. | |
28 | (define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most") | |
29 | ||
30 | ;; CFX. | |
31 | (define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most") | |
32 | ||
33 | ;; Non-pipelined division. | |
34 | (define_cpu_unit "e6500_cfx_div" "e6500_long") | |
35 | ||
36 | ;; LSU. | |
37 | (define_cpu_unit "e6500_lsu" "e6500_most") | |
38 | ||
39 | ;; FPU. | |
40 | (define_cpu_unit "e6500_fpu" "e6500_long") | |
41 | ||
42 | ;; BU. | |
43 | (define_cpu_unit "e6500_bu" "e6500_most") | |
44 | ||
45 | ;; Altivec unit | |
46 | (define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec") | |
47 | ||
48 | ;; The following units are used to make the automata deterministic. | |
49 | (define_cpu_unit "present_e6500_decode_0" "e6500_most") | |
50 | (define_cpu_unit "present_e6500_sfx_0" "e6500_most") | |
51 | (presence_set "present_e6500_decode_0" "e6500_decode_0") | |
52 | (presence_set "present_e6500_sfx_0" "e6500_sfx_0") | |
53 | ||
54 | ;; Some useful abbreviations. | |
55 | (define_reservation "e6500_decode" | |
56 | "e6500_decode_0|e6500_decode_1+present_e6500_decode_0") | |
57 | (define_reservation "e6500_sfx" | |
58 | "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0") | |
59 | ||
60 | ;; SFX. | |
61 | (define_insn_reservation "e6500_sfx" 1 | |
88599a7a | 62 | (and (ior (eq_attr "type" "integer,insert,cntlz") |
63 | (and (eq_attr "type" "add,logical,exts") | |
7f15413b | 64 | (eq_attr "dot" "no")) |
7d307a6a | 65 | (and (eq_attr "type" "shift") |
3c428170 | 66 | (eq_attr "dot" "no") |
7d307a6a | 67 | (eq_attr "var_shift" "no"))) |
b770074c | 68 | (eq_attr "cpu" "ppce6500")) |
69 | "e6500_decode,e6500_sfx") | |
70 | ||
71 | (define_insn_reservation "e6500_sfx2" 2 | |
cd1e80f3 | 72 | (and (ior (eq_attr "type" "cmp,trap") |
88599a7a | 73 | (and (eq_attr "type" "add,logical,exts") |
3c428170 | 74 | (eq_attr "dot" "yes")) |
75 | (and (eq_attr "type" "shift") | |
76 | (eq_attr "dot" "yes") | |
77 | (eq_attr "var_shift" "no"))) | |
b770074c | 78 | (eq_attr "cpu" "ppce6500")) |
79 | "e6500_decode,e6500_sfx") | |
80 | ||
81 | (define_insn_reservation "e6500_delayed" 2 | |
7d307a6a | 82 | (and (eq_attr "type" "shift") |
83 | (eq_attr "var_shift" "yes") | |
b770074c | 84 | (eq_attr "cpu" "ppce6500")) |
85 | "e6500_decode,e6500_sfx*2") | |
86 | ||
87 | (define_insn_reservation "e6500_two" 2 | |
88 | (and (eq_attr "type" "two") | |
89 | (eq_attr "cpu" "ppce6500")) | |
90 | "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx") | |
91 | ||
92 | (define_insn_reservation "e6500_three" 3 | |
93 | (and (eq_attr "type" "three") | |
94 | (eq_attr "cpu" "ppce6500")) | |
95 | "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx") | |
96 | ||
97 | ;; SFX - Mfcr. | |
98 | (define_insn_reservation "e6500_mfcr" 4 | |
99 | (and (eq_attr "type" "mfcr") | |
100 | (eq_attr "cpu" "ppce6500")) | |
101 | "e6500_decode,e6500_sfx_0*4") | |
102 | ||
103 | ;; SFX - Mtcrf. | |
104 | (define_insn_reservation "e6500_mtcrf" 1 | |
105 | (and (eq_attr "type" "mtcr") | |
106 | (eq_attr "cpu" "ppce6500")) | |
107 | "e6500_decode,e6500_sfx_0") | |
108 | ||
109 | ;; SFX - Mtjmpr. | |
110 | (define_insn_reservation "e6500_mtjmpr" 1 | |
111 | (and (eq_attr "type" "mtjmpr,mfjmpr") | |
112 | (eq_attr "cpu" "ppce6500")) | |
113 | "e6500_decode,e6500_sfx") | |
114 | ||
115 | ;; CFX - Multiply. | |
116 | (define_insn_reservation "e6500_multiply" 4 | |
86c149d4 | 117 | (and (eq_attr "type" "mul") |
118 | (eq_attr "dot" "no") | |
119 | (eq_attr "size" "32") | |
b770074c | 120 | (eq_attr "cpu" "ppce6500")) |
121 | "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1") | |
122 | ||
123 | (define_insn_reservation "e6500_multiply_i" 5 | |
86c149d4 | 124 | (and (eq_attr "type" "mul") |
125 | (ior (eq_attr "dot" "yes") | |
126 | (eq_attr "size" "8,16")) | |
b770074c | 127 | (eq_attr "cpu" "ppce6500")) |
128 | "e6500_decode,e6500_cfx_stage0,\ | |
129 | e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1") | |
130 | ||
131 | ;; CFX - Divide. | |
132 | (define_insn_reservation "e6500_divide" 16 | |
90e4483f | 133 | (and (eq_attr "type" "div") |
134 | (eq_attr "size" "32") | |
b770074c | 135 | (eq_attr "cpu" "ppce6500")) |
136 | "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\ | |
137 | e6500_cfx_div*15") | |
138 | ||
139 | (define_insn_reservation "e6500_divide_d" 26 | |
90e4483f | 140 | (and (eq_attr "type" "div") |
141 | (eq_attr "size" "64") | |
b770074c | 142 | (eq_attr "cpu" "ppce6500")) |
143 | "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\ | |
144 | e6500_cfx_div*25") | |
145 | ||
146 | ;; LSU - Loads. | |
147 | (define_insn_reservation "e6500_load" 3 | |
631c977b | 148 | (and (eq_attr "type" "load,load_l,sync") |
b770074c | 149 | (eq_attr "cpu" "ppce6500")) |
150 | "e6500_decode,e6500_lsu") | |
151 | ||
152 | (define_insn_reservation "e6500_fpload" 4 | |
631c977b | 153 | (and (eq_attr "type" "fpload") |
b770074c | 154 | (eq_attr "cpu" "ppce6500")) |
155 | "e6500_decode,e6500_lsu") | |
156 | ||
157 | (define_insn_reservation "e6500_vecload" 4 | |
158 | (and (eq_attr "type" "vecload") | |
159 | (eq_attr "cpu" "ppce6500")) | |
160 | "e6500_decode,e6500_lsu") | |
161 | ||
162 | ;; LSU - Stores. | |
163 | (define_insn_reservation "e6500_store" 3 | |
631c977b | 164 | (and (eq_attr "type" "store,store_c") |
b770074c | 165 | (eq_attr "cpu" "ppce6500")) |
166 | "e6500_decode,e6500_lsu") | |
167 | ||
168 | (define_insn_reservation "e6500_fpstore" 3 | |
631c977b | 169 | (and (eq_attr "type" "fpstore") |
b770074c | 170 | (eq_attr "cpu" "ppce6500")) |
171 | "e6500_decode,e6500_lsu") | |
172 | ||
173 | (define_insn_reservation "e6500_vecstore" 4 | |
174 | (and (eq_attr "type" "vecstore") | |
175 | (eq_attr "cpu" "ppce6500")) | |
176 | "e6500_decode,e6500_lsu") | |
177 | ||
178 | ;; FP. | |
179 | (define_insn_reservation "e6500_float" 7 | |
180 | (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul") | |
181 | (eq_attr "cpu" "ppce6500")) | |
182 | "e6500_decode,e6500_fpu") | |
183 | ||
184 | (define_insn_reservation "e6500_sdiv" 20 | |
185 | (and (eq_attr "type" "sdiv") | |
186 | (eq_attr "cpu" "ppce6500")) | |
187 | "e6500_decode,e6500_fpu*20") | |
188 | ||
189 | (define_insn_reservation "e6500_ddiv" 35 | |
190 | (and (eq_attr "type" "ddiv") | |
191 | (eq_attr "cpu" "ppce6500")) | |
192 | "e6500_decode,e6500_fpu*35") | |
193 | ||
194 | ;; BU. | |
195 | (define_insn_reservation "e6500_branch" 1 | |
196 | (and (eq_attr "type" "jmpreg,branch,isync") | |
197 | (eq_attr "cpu" "ppce6500")) | |
198 | "e6500_decode,e6500_bu") | |
199 | ||
200 | ;; BU - CR logical. | |
201 | (define_insn_reservation "e6500_cr_logical" 1 | |
0a06c399 | 202 | (and (eq_attr "type" "cr_logical") |
b770074c | 203 | (eq_attr "cpu" "ppce6500")) |
204 | "e6500_decode,e6500_bu") | |
205 | ||
206 | ;; VSFX. | |
207 | (define_insn_reservation "e6500_vecsimple" 1 | |
c3fa390a | 208 | (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx") |
b770074c | 209 | (eq_attr "cpu" "ppce6500")) |
210 | "e6500_decode,e6500_vec") | |
211 | ||
212 | ;; VCFX. | |
213 | (define_insn_reservation "e6500_veccomplex" 4 | |
214 | (and (eq_attr "type" "veccomplex") | |
215 | (eq_attr "cpu" "ppce6500")) | |
216 | "e6500_decode,e6500_vec") | |
217 | ||
218 | ;; VFPU. | |
219 | (define_insn_reservation "e6500_vecfloat" 6 | |
220 | (and (eq_attr "type" "vecfloat") | |
221 | (eq_attr "cpu" "ppce6500")) | |
222 | "e6500_decode,e6500_vec") | |
223 | ||
224 | ;; VPERM. | |
225 | (define_insn_reservation "e6500_vecperm" 2 | |
226 | (and (eq_attr "type" "vecperm") | |
227 | (eq_attr "cpu" "ppce6500")) | |
228 | "e6500_decode,e6500_vecperm") |