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aac77ea5 | 1 | ;; Scheduling description for Motorola PowerPC processor cores. |
23a5b65a | 2 | ;; Copyright (C) 2003-2014 Free Software Foundation, Inc. |
aac77ea5 | 3 | ;; |
5de601cf | 4 | ;; This file is part of GCC. |
aac77ea5 | 5 | ;; |
5de601cf NC |
6 | ;; GCC is free software; you can redistribute it and/or modify it |
7 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 8 | ;; by the Free Software Foundation; either version 3, or (at your |
5de601cf | 9 | ;; option) any later version. |
aac77ea5 | 10 | ;; |
5de601cf NC |
11 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | ;; License for more details. | |
aac77ea5 DE |
15 | ;; |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
aac77ea5 | 19 | |
b54cf83a DE |
20 | (define_automaton "mpc,mpcfp") |
21 | (define_cpu_unit "iu_mpc,mciu_mpc" "mpc") | |
22 | (define_cpu_unit "fpu_mpc" "mpcfp") | |
23 | (define_cpu_unit "lsu_mpc,bpu_mpc" "mpc") | |
24 | ||
25 | ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU | |
26 | ;; 505/801/821/823 | |
27 | ||
28 | (define_insn_reservation "mpccore-load" 2 | |
b52110d4 DE |
29 | (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ |
30 | load_l,store_c,sync") | |
b54cf83a DE |
31 | (eq_attr "cpu" "mpccore")) |
32 | "lsu_mpc") | |
33 | ||
9c6fdb46 | 34 | (define_insn_reservation "mpccore-store" 2 |
b54cf83a DE |
35 | (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") |
36 | (eq_attr "cpu" "mpccore")) | |
37 | "lsu_mpc") | |
38 | ||
39 | (define_insn_reservation "mpccore-fpload" 2 | |
40 | (and (eq_attr "type" "fpload,fpload_ux,fpload_u") | |
41 | (eq_attr "cpu" "mpccore")) | |
42 | "lsu_mpc") | |
43 | ||
44 | (define_insn_reservation "mpccore-integer" 1 | |
44cd321e | 45 | (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ |
47f67e51 | 46 | var_shift_rotate,cntlz,exts,isel") |
b54cf83a DE |
47 | (eq_attr "cpu" "mpccore")) |
48 | "iu_mpc") | |
49 | ||
943c15ed DE |
50 | (define_insn_reservation "mpccore-two" 1 |
51 | (and (eq_attr "type" "two") | |
52 | (eq_attr "cpu" "mpccore")) | |
53 | "iu_mpc,iu_mpc") | |
54 | ||
55 | (define_insn_reservation "mpccore-three" 1 | |
56 | (and (eq_attr "type" "three") | |
57 | (eq_attr "cpu" "mpccore")) | |
58 | "iu_mpc,iu_mpc,iu_mpc") | |
59 | ||
b54cf83a | 60 | (define_insn_reservation "mpccore-imul" 2 |
9259f3b0 | 61 | (and (eq_attr "type" "imul,imul2,imul3,imul_compare") |
b54cf83a DE |
62 | (eq_attr "cpu" "mpccore")) |
63 | "mciu_mpc") | |
64 | ||
65 | ; Divide latency varies greatly from 2-11, use 6 as average | |
66 | (define_insn_reservation "mpccore-idiv" 6 | |
67 | (and (eq_attr "type" "idiv") | |
68 | (eq_attr "cpu" "mpccore")) | |
69 | "mciu_mpc*6") | |
70 | ||
71 | (define_insn_reservation "mpccore-compare" 3 | |
44cd321e PS |
72 | (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\ |
73 | var_delayed_compare") | |
b54cf83a DE |
74 | (eq_attr "cpu" "mpccore")) |
75 | "iu_mpc,nothing,bpu_mpc") | |
76 | ||
77 | (define_insn_reservation "mpccore-fpcompare" 2 | |
78 | (and (eq_attr "type" "fpcompare") | |
79 | (eq_attr "cpu" "mpccore")) | |
80 | "fpu_mpc,bpu_mpc") | |
81 | ||
82 | (define_insn_reservation "mpccore-fp" 4 | |
83 | (and (eq_attr "type" "fp") | |
84 | (eq_attr "cpu" "mpccore")) | |
85 | "fpu_mpc*2") | |
86 | ||
87 | (define_insn_reservation "mpccore-dmul" 5 | |
88 | (and (eq_attr "type" "dmul") | |
89 | (eq_attr "cpu" "mpccore")) | |
90 | "fpu_mpc*5") | |
91 | ||
92 | (define_insn_reservation "mpccore-sdiv" 10 | |
93 | (and (eq_attr "type" "sdiv") | |
94 | (eq_attr "cpu" "mpccore")) | |
95 | "fpu_mpc*10") | |
96 | ||
97 | (define_insn_reservation "mpccore-ddiv" 17 | |
98 | (and (eq_attr "type" "ddiv") | |
99 | (eq_attr "cpu" "mpccore")) | |
100 | "fpu_mpc*17") | |
101 | ||
102 | (define_insn_reservation "mpccore-mtjmpr" 4 | |
02ca7595 | 103 | (and (eq_attr "type" "mtjmpr,mfjmpr") |
b54cf83a DE |
104 | (eq_attr "cpu" "mpccore")) |
105 | "bpu_mpc") | |
106 | ||
107 | (define_insn_reservation "mpccore-jmpreg" 1 | |
b52110d4 | 108 | (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync") |
b54cf83a DE |
109 | (eq_attr "cpu" "mpccore")) |
110 | "bpu_mpc") | |
111 |