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3e260c01 | 1 | ;; Scheduling description for Motorola PowerPC processor cores. |
fbd26352 | 2 | ;; Copyright (C) 2003-2019 Free Software Foundation, Inc. |
3e260c01 | 3 | ;; |
3a5a28e2 | 4 | ;; This file is part of GCC. |
3e260c01 | 5 | ;; |
3a5a28e2 | 6 | ;; GCC is free software; you can redistribute it and/or modify it |
7 | ;; under the terms of the GNU General Public License as published | |
038d1e19 | 8 | ;; by the Free Software Foundation; either version 3, or (at your |
3a5a28e2 | 9 | ;; option) any later version. |
3e260c01 | 10 | ;; |
3a5a28e2 | 11 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | ;; License for more details. | |
3e260c01 | 15 | ;; |
16 | ;; You should have received a copy of the GNU General Public License | |
038d1e19 | 17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
3e260c01 | 19 | |
a0b98322 | 20 | (define_automaton "mpc,mpcfp") |
21 | (define_cpu_unit "iu_mpc,mciu_mpc" "mpc") | |
22 | (define_cpu_unit "fpu_mpc" "mpcfp") | |
23 | (define_cpu_unit "lsu_mpc,bpu_mpc" "mpc") | |
24 | ||
25 | ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU | |
26 | ;; 505/801/821/823 | |
27 | ||
28 | (define_insn_reservation "mpccore-load" 2 | |
631c977b | 29 | (and (eq_attr "type" "load,load_l,store_c,sync") |
a0b98322 | 30 | (eq_attr "cpu" "mpccore")) |
31 | "lsu_mpc") | |
32 | ||
5d42cb42 | 33 | (define_insn_reservation "mpccore-store" 2 |
631c977b | 34 | (and (eq_attr "type" "store,fpstore") |
a0b98322 | 35 | (eq_attr "cpu" "mpccore")) |
36 | "lsu_mpc") | |
37 | ||
38 | (define_insn_reservation "mpccore-fpload" 2 | |
631c977b | 39 | (and (eq_attr "type" "fpload") |
a0b98322 | 40 | (eq_attr "cpu" "mpccore")) |
41 | "lsu_mpc") | |
42 | ||
43 | (define_insn_reservation "mpccore-integer" 1 | |
88599a7a | 44 | (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel") |
45 | (and (eq_attr "type" "add,logical,shift,exts") | |
7d307a6a | 46 | (eq_attr "dot" "no"))) |
a0b98322 | 47 | (eq_attr "cpu" "mpccore")) |
48 | "iu_mpc") | |
49 | ||
c86a5c89 | 50 | (define_insn_reservation "mpccore-two" 1 |
51 | (and (eq_attr "type" "two") | |
52 | (eq_attr "cpu" "mpccore")) | |
53 | "iu_mpc,iu_mpc") | |
54 | ||
55 | (define_insn_reservation "mpccore-three" 1 | |
56 | (and (eq_attr "type" "three") | |
57 | (eq_attr "cpu" "mpccore")) | |
58 | "iu_mpc,iu_mpc,iu_mpc") | |
59 | ||
a0b98322 | 60 | (define_insn_reservation "mpccore-imul" 2 |
86c149d4 | 61 | (and (eq_attr "type" "mul") |
a0b98322 | 62 | (eq_attr "cpu" "mpccore")) |
63 | "mciu_mpc") | |
64 | ||
65 | ; Divide latency varies greatly from 2-11, use 6 as average | |
66 | (define_insn_reservation "mpccore-idiv" 6 | |
90e4483f | 67 | (and (eq_attr "type" "div") |
a0b98322 | 68 | (eq_attr "cpu" "mpccore")) |
69 | "mciu_mpc*6") | |
70 | ||
71 | (define_insn_reservation "mpccore-compare" 3 | |
cd1e80f3 | 72 | (and (ior (eq_attr "type" "cmp") |
88599a7a | 73 | (and (eq_attr "type" "add,logical,shift,exts") |
7d307a6a | 74 | (eq_attr "dot" "yes"))) |
a0b98322 | 75 | (eq_attr "cpu" "mpccore")) |
76 | "iu_mpc,nothing,bpu_mpc") | |
77 | ||
78 | (define_insn_reservation "mpccore-fpcompare" 2 | |
79 | (and (eq_attr "type" "fpcompare") | |
80 | (eq_attr "cpu" "mpccore")) | |
81 | "fpu_mpc,bpu_mpc") | |
82 | ||
83 | (define_insn_reservation "mpccore-fp" 4 | |
c3fa390a | 84 | (and (eq_attr "type" "fp,fpsimple") |
a0b98322 | 85 | (eq_attr "cpu" "mpccore")) |
86 | "fpu_mpc*2") | |
87 | ||
88 | (define_insn_reservation "mpccore-dmul" 5 | |
89 | (and (eq_attr "type" "dmul") | |
90 | (eq_attr "cpu" "mpccore")) | |
91 | "fpu_mpc*5") | |
92 | ||
93 | (define_insn_reservation "mpccore-sdiv" 10 | |
94 | (and (eq_attr "type" "sdiv") | |
95 | (eq_attr "cpu" "mpccore")) | |
96 | "fpu_mpc*10") | |
97 | ||
98 | (define_insn_reservation "mpccore-ddiv" 17 | |
99 | (and (eq_attr "type" "ddiv") | |
100 | (eq_attr "cpu" "mpccore")) | |
101 | "fpu_mpc*17") | |
102 | ||
103 | (define_insn_reservation "mpccore-mtjmpr" 4 | |
45d9c0fa | 104 | (and (eq_attr "type" "mtjmpr,mfjmpr") |
a0b98322 | 105 | (eq_attr "cpu" "mpccore")) |
106 | "bpu_mpc") | |
107 | ||
108 | (define_insn_reservation "mpccore-jmpreg" 1 | |
0a06c399 | 109 | (and (eq_attr "type" "jmpreg,branch,cr_logical,mfcr,mtcr,isync") |
a0b98322 | 110 | (eq_attr "cpu" "mpccore")) |
111 | "bpu_mpc") | |
112 |