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aac77ea5 | 1 | ;; Scheduling description for IBM Power4 and PowerPC 970 processors. |
47f67e51 | 2 | ;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. |
aac77ea5 | 3 | ;; |
5de601cf | 4 | ;; This file is part of GCC. |
aac77ea5 | 5 | ;; |
5de601cf NC |
6 | ;; GCC is free software; you can redistribute it and/or modify it |
7 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 8 | ;; by the Free Software Foundation; either version 3, or (at your |
5de601cf | 9 | ;; option) any later version. |
aac77ea5 | 10 | ;; |
5de601cf NC |
11 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | ;; License for more details. | |
aac77ea5 DE |
15 | ;; |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
b54cf83a DE |
19 | |
20 | ;; Sources: IBM Red Book and White Paper on POWER4 | |
21 | ||
22 | ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). | |
23 | ;; Instructions that update more than one register get broken into two | |
24 | ;; (split) or more internal ops. The chip can issue up to 5 | |
25 | ;; internal ops per cycle. | |
26 | ||
02ca7595 | 27 | (define_automaton "power4iu,power4fpu,power4vec,power4misc") |
b54cf83a DE |
28 | |
29 | (define_cpu_unit "iu1_power4,iu2_power4" "power4iu") | |
02ca7595 | 30 | (define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc") |
b54cf83a DE |
31 | (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu") |
32 | (define_cpu_unit "bpu_power4,cru_power4" "power4misc") | |
33 | (define_cpu_unit "vec_power4,vecperm_power4" "power4vec") | |
34 | (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4" | |
02ca7595 | 35 | "power4misc") |
b54cf83a | 36 | |
9259f3b0 DE |
37 | (define_reservation "lsq_power4" |
38 | "(du1_power4,lsu1_power4)\ | |
39 | |(du2_power4,lsu2_power4)\ | |
4e596a09 DE |
40 | |(du3_power4,lsu2_power4)\ |
41 | |(du4_power4,lsu1_power4)") | |
b54cf83a DE |
42 | |
43 | (define_reservation "lsuq_power4" | |
1244a8b7 VM |
44 | "((du1_power4+du2_power4,lsu1_power4)\ |
45 | |(du2_power4+du3_power4,lsu2_power4)\ | |
46 | |(du3_power4+du4_power4,lsu2_power4))\ | |
47 | +(nothing,iu2_power4|nothing,iu1_power4)") | |
b54cf83a | 48 | |
9259f3b0 | 49 | (define_reservation "iq_power4" |
1244a8b7 VM |
50 | "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
51 | (iu1_power4|iu2_power4)") | |
b54cf83a | 52 | |
9259f3b0 | 53 | (define_reservation "fpq_power4" |
1244a8b7 VM |
54 | "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
55 | (fpu1_power4|fpu2_power4)") | |
b54cf83a DE |
56 | |
57 | (define_reservation "vq_power4" | |
9259f3b0 DE |
58 | "(du1_power4,vec_power4)\ |
59 | |(du2_power4,vec_power4)\ | |
4e596a09 DE |
60 | |(du3_power4,vec_power4)\ |
61 | |(du4_power4,vec_power4)") | |
9259f3b0 | 62 | |
b54cf83a | 63 | (define_reservation "vpq_power4" |
9259f3b0 DE |
64 | "(du1_power4,vecperm_power4)\ |
65 | |(du2_power4,vecperm_power4)\ | |
4e596a09 DE |
66 | |(du3_power4,vecperm_power4)\ |
67 | |(du4_power4,vecperm_power4)") | |
b54cf83a DE |
68 | |
69 | ||
70 | ; Dispatch slots are allocated in order conforming to program order. | |
71 | (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4") | |
72 | (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4") | |
73 | (absence_set "du3_power4" "du4_power4,du5_power4") | |
74 | (absence_set "du4_power4" "du5_power4") | |
75 | ||
76 | ||
77 | ; Load/store | |
9259f3b0 | 78 | (define_insn_reservation "power4-load" 4 ; 3 |
b54cf83a DE |
79 | (and (eq_attr "type" "load") |
80 | (eq_attr "cpu" "power4")) | |
81 | "lsq_power4") | |
82 | ||
83 | (define_insn_reservation "power4-load-ext" 5 | |
84 | (and (eq_attr "type" "load_ext") | |
85 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
86 | "(du1_power4+du2_power4,lsu1_power4\ |
87 | |du2_power4+du3_power4,lsu2_power4\ | |
88 | |du3_power4+du4_power4,lsu2_power4),\ | |
89 | nothing,nothing,\ | |
90 | (iu2_power4|iu1_power4)") | |
b54cf83a DE |
91 | |
92 | (define_insn_reservation "power4-load-ext-update" 5 | |
93 | (and (eq_attr "type" "load_ext_u") | |
94 | (eq_attr "cpu" "power4")) | |
02ca7595 DE |
95 | "du1_power4+du2_power4+du3_power4+du4_power4,\ |
96 | lsu1_power4+iu2_power4,nothing,nothing,iu2_power4") | |
b54cf83a DE |
97 | |
98 | (define_insn_reservation "power4-load-ext-update-indexed" 5 | |
99 | (and (eq_attr "type" "load_ext_ux") | |
100 | (eq_attr "cpu" "power4")) | |
02ca7595 | 101 | "du1_power4+du2_power4+du3_power4+du4_power4,\ |
9259f3b0 | 102 | iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4") |
b54cf83a | 103 | |
984e25ac | 104 | (define_insn_reservation "power4-load-update-indexed" 3 |
b54cf83a DE |
105 | (and (eq_attr "type" "load_ux") |
106 | (eq_attr "cpu" "power4")) | |
02ca7595 | 107 | "du1_power4+du2_power4+du3_power4+du4_power4,\ |
9259f3b0 | 108 | iu1_power4,lsu2_power4+iu2_power4") |
b54cf83a | 109 | |
9259f3b0 | 110 | (define_insn_reservation "power4-load-update" 4 ; 3 |
b54cf83a DE |
111 | (and (eq_attr "type" "load_u") |
112 | (eq_attr "cpu" "power4")) | |
113 | "lsuq_power4") | |
114 | ||
9259f3b0 | 115 | (define_insn_reservation "power4-fpload" 6 ; 5 |
b54cf83a DE |
116 | (and (eq_attr "type" "fpload") |
117 | (eq_attr "cpu" "power4")) | |
118 | "lsq_power4") | |
119 | ||
9259f3b0 DE |
120 | (define_insn_reservation "power4-fpload-update" 6 ; 5 |
121 | (and (eq_attr "type" "fpload_u,fpload_ux") | |
b54cf83a DE |
122 | (eq_attr "cpu" "power4")) |
123 | "lsuq_power4") | |
124 | ||
9259f3b0 | 125 | (define_insn_reservation "power4-vecload" 6 ; 5 |
b54cf83a DE |
126 | (and (eq_attr "type" "vecload") |
127 | (eq_attr "cpu" "power4")) | |
128 | "lsq_power4") | |
129 | ||
594a3565 | 130 | (define_insn_reservation "power4-store" 12 |
6d6ab190 | 131 | (and (eq_attr "type" "store") |
b54cf83a | 132 | (eq_attr "cpu" "power4")) |
1244a8b7 VM |
133 | "((du1_power4,lsu1_power4)\ |
134 | |(du2_power4,lsu2_power4)\ | |
135 | |(du3_power4,lsu2_power4)\ | |
136 | |(du4_power4,lsu1_power4)),\ | |
137 | (iu1_power4|iu2_power4)") | |
b54cf83a | 138 | |
594a3565 | 139 | (define_insn_reservation "power4-store-update" 12 |
b54cf83a DE |
140 | (and (eq_attr "type" "store_u") |
141 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
142 | "((du1_power4+du2_power4,lsu1_power4)\ |
143 | |(du2_power4+du3_power4,lsu2_power4)\ | |
144 | |(du3_power4+du4_power4,lsu2_power4)\ | |
145 | |(du3_power4+du4_power4,lsu2_power4))+\ | |
146 | ((nothing,iu2_power4,iu1_power4)\ | |
147 | |(nothing,iu2_power4,iu2_power4)\ | |
148 | |(nothing,iu1_power4,iu2_power4)\ | |
149 | |(nothing,iu1_power4,iu2_power4))") | |
b54cf83a | 150 | |
594a3565 | 151 | (define_insn_reservation "power4-store-update-indexed" 12 |
b54cf83a DE |
152 | (and (eq_attr "type" "store_ux") |
153 | (eq_attr "cpu" "power4")) | |
9259f3b0 DE |
154 | "du1_power4+du2_power4+du3_power4+du4_power4,\ |
155 | iu1_power4,lsu2_power4+iu2_power4,iu2_power4") | |
b54cf83a | 156 | |
594a3565 | 157 | (define_insn_reservation "power4-fpstore" 12 |
b54cf83a DE |
158 | (and (eq_attr "type" "fpstore") |
159 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
160 | "((du1_power4,lsu1_power4)\ |
161 | |(du2_power4,lsu2_power4)\ | |
162 | |(du3_power4,lsu2_power4)\ | |
163 | |(du4_power4,lsu1_power4)),\ | |
164 | (fpu1_power4|fpu2_power4)") | |
b54cf83a | 165 | |
594a3565 | 166 | (define_insn_reservation "power4-fpstore-update" 12 |
9259f3b0 | 167 | (and (eq_attr "type" "fpstore_u,fpstore_ux") |
b54cf83a | 168 | (eq_attr "cpu" "power4")) |
1244a8b7 VM |
169 | "((du1_power4+du2_power4,lsu1_power4)\ |
170 | |(du2_power4+du3_power4,lsu2_power4)\ | |
171 | |(du3_power4+du4_power4,lsu2_power4))\ | |
172 | +(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))") | |
b54cf83a | 173 | |
594a3565 | 174 | (define_insn_reservation "power4-vecstore" 12 |
6d6ab190 DE |
175 | (and (eq_attr "type" "vecstore") |
176 | (eq_attr "cpu" "power4")) | |
9259f3b0 DE |
177 | "(du1_power4,lsu1_power4,vec_power4)\ |
178 | |(du2_power4,lsu2_power4,vec_power4)\ | |
4e596a09 DE |
179 | |(du3_power4,lsu2_power4,vec_power4)\ |
180 | |(du4_power4,lsu1_power4,vec_power4)") | |
6d6ab190 | 181 | |
b52110d4 DE |
182 | (define_insn_reservation "power4-llsc" 11 |
183 | (and (eq_attr "type" "load_l,store_c,sync") | |
184 | (eq_attr "cpu" "power4")) | |
1244a8b7 | 185 | "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4") |
b52110d4 | 186 | |
b54cf83a DE |
187 | |
188 | ; Integer latency is 2 cycles | |
189 | (define_insn_reservation "power4-integer" 2 | |
44cd321e | 190 | (and (eq_attr "type" "integer,insert_dword,shift,trap,\ |
47f67e51 | 191 | var_shift_rotate,cntlz,exts,isel") |
b54cf83a DE |
192 | (eq_attr "cpu" "power4")) |
193 | "iq_power4") | |
194 | ||
943c15ed DE |
195 | (define_insn_reservation "power4-two" 2 |
196 | (and (eq_attr "type" "two") | |
197 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
198 | "((du1_power4+du2_power4)\ |
199 | |(du2_power4+du3_power4)\ | |
200 | |(du3_power4+du4_power4)\ | |
201 | |(du4_power4+du1_power4)),\ | |
202 | ((iu1_power4,nothing,iu2_power4)\ | |
203 | |(iu2_power4,nothing,iu2_power4)\ | |
204 | |(iu2_power4,nothing,iu1_power4)\ | |
205 | |(iu1_power4,nothing,iu1_power4))") | |
943c15ed DE |
206 | |
207 | (define_insn_reservation "power4-three" 2 | |
208 | (and (eq_attr "type" "three") | |
209 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
210 | "(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\ |
211 | |du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\ | |
212 | ((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\ | |
213 | |(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\ | |
214 | |(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\ | |
215 | |(iu1_power4,nothing,iu2_power4,nothing,iu2_power4))") | |
943c15ed | 216 | |
8e8238f1 DE |
217 | (define_insn_reservation "power4-insert" 4 |
218 | (and (eq_attr "type" "insert_word") | |
219 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
220 | "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ |
221 | ((iu1_power4,nothing,iu2_power4)\ | |
222 | |(iu2_power4,nothing,iu2_power4)\ | |
223 | |(iu2_power4,nothing,iu1_power4))") | |
8e8238f1 | 224 | |
b54cf83a | 225 | (define_insn_reservation "power4-cmp" 3 |
a62bfff2 | 226 | (and (eq_attr "type" "cmp,fast_compare") |
b54cf83a DE |
227 | (eq_attr "cpu" "power4")) |
228 | "iq_power4") | |
229 | ||
9259f3b0 | 230 | (define_insn_reservation "power4-compare" 2 |
44cd321e | 231 | (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare") |
b54cf83a | 232 | (eq_attr "cpu" "power4")) |
1244a8b7 VM |
233 | "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ |
234 | ((iu1_power4,iu2_power4)\ | |
235 | |(iu2_power4,iu2_power4)\ | |
236 | |(iu2_power4,iu1_power4))") | |
b54cf83a | 237 | |
2c4a9cff | 238 | (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") |
f8f0e566 | 239 | |
984e25ac | 240 | (define_insn_reservation "power4-lmul-cmp" 7 |
9259f3b0 | 241 | (and (eq_attr "type" "lmul_compare") |
b54cf83a | 242 | (eq_attr "cpu" "power4")) |
1244a8b7 VM |
243 | "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ |
244 | ((iu1_power4*6,iu2_power4)\ | |
245 | |(iu2_power4*6,iu2_power4)\ | |
246 | |(iu2_power4*6,iu1_power4))") | |
b54cf83a | 247 | |
2c4a9cff | 248 | (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") |
9259f3b0 | 249 | |
984e25ac | 250 | (define_insn_reservation "power4-imul-cmp" 5 |
9259f3b0 DE |
251 | (and (eq_attr "type" "imul_compare") |
252 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
253 | "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ |
254 | ((iu1_power4*4,iu2_power4)\ | |
255 | |(iu2_power4*4,iu2_power4)\ | |
256 | |(iu2_power4*4,iu1_power4))") | |
9259f3b0 | 257 | |
2c4a9cff | 258 | (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") |
9259f3b0 | 259 | |
984e25ac | 260 | (define_insn_reservation "power4-lmul" 7 |
9259f3b0 | 261 | (and (eq_attr "type" "lmul") |
b54cf83a | 262 | (eq_attr "cpu" "power4")) |
1244a8b7 VM |
263 | "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
264 | (iu1_power4*6|iu2_power4*6)") | |
b54cf83a | 265 | |
984e25ac | 266 | (define_insn_reservation "power4-imul" 5 |
9259f3b0 | 267 | (and (eq_attr "type" "imul") |
b54cf83a | 268 | (eq_attr "cpu" "power4")) |
1244a8b7 VM |
269 | "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
270 | (iu1_power4*4|iu2_power4*4)") | |
9259f3b0 | 271 | |
984e25ac | 272 | (define_insn_reservation "power4-imul3" 4 |
9259f3b0 DE |
273 | (and (eq_attr "type" "imul2,imul3") |
274 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
275 | "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
276 | (iu1_power4*3|iu2_power4*3)") | |
9259f3b0 | 277 | |
b54cf83a DE |
278 | |
279 | ; SPR move only executes in first IU. | |
280 | ; Integer division only executes in second IU. | |
281 | (define_insn_reservation "power4-idiv" 36 | |
282 | (and (eq_attr "type" "idiv") | |
283 | (eq_attr "cpu" "power4")) | |
02ca7595 | 284 | "du1_power4+du2_power4,iu2_power4*35") |
b54cf83a DE |
285 | |
286 | (define_insn_reservation "power4-ldiv" 68 | |
287 | (and (eq_attr "type" "ldiv") | |
288 | (eq_attr "cpu" "power4")) | |
02ca7595 | 289 | "du1_power4+du2_power4,iu2_power4*67") |
b54cf83a DE |
290 | |
291 | ||
292 | (define_insn_reservation "power4-mtjmpr" 3 | |
02ca7595 | 293 | (and (eq_attr "type" "mtjmpr,mfjmpr") |
b54cf83a DE |
294 | (eq_attr "cpu" "power4")) |
295 | "du1_power4,bpu_power4") | |
296 | ||
297 | ||
298 | ; Branches take dispatch Slot 4. The presence_sets prevent other insn from | |
299 | ; grabbing previous dispatch slots once this is assigned. | |
300 | (define_insn_reservation "power4-branch" 2 | |
301 | (and (eq_attr "type" "jmpreg,branch") | |
302 | (eq_attr "cpu" "power4")) | |
29ae9364 DE |
303 | "(du5_power4\ |
304 | |du4_power4+du5_power4\ | |
305 | |du3_power4+du4_power4+du5_power4\ | |
306 | |du2_power4+du3_power4+du4_power4+du5_power4\ | |
307 | |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4") | |
b54cf83a DE |
308 | |
309 | ||
310 | ; Condition Register logical ops are split if non-destructive (RT != RB) | |
311 | (define_insn_reservation "power4-crlogical" 2 | |
312 | (and (eq_attr "type" "cr_logical") | |
313 | (eq_attr "cpu" "power4")) | |
314 | "du1_power4,cru_power4") | |
315 | ||
316 | (define_insn_reservation "power4-delayedcr" 4 | |
317 | (and (eq_attr "type" "delayed_cr") | |
318 | (eq_attr "cpu" "power4")) | |
02ca7595 | 319 | "du1_power4+du2_power4,cru_power4,cru_power4") |
b54cf83a DE |
320 | |
321 | ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu | |
322 | (define_insn_reservation "power4-mfcr" 6 | |
323 | (and (eq_attr "type" "mfcr") | |
324 | (eq_attr "cpu" "power4")) | |
02ca7595 DE |
325 | "du1_power4+du2_power4+du3_power4+du4_power4,\ |
326 | du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\ | |
327 | cru_power4,cru_power4,cru_power4") | |
b54cf83a | 328 | |
2c4a9cff DE |
329 | ; mfcrf (1 field) |
330 | (define_insn_reservation "power4-mfcrf" 3 | |
331 | (and (eq_attr "type" "mfcrf") | |
332 | (eq_attr "cpu" "power4")) | |
333 | "du1_power4,cru_power4") | |
334 | ||
b54cf83a DE |
335 | ; mtcrf (1 field) |
336 | (define_insn_reservation "power4-mtcr" 4 | |
337 | (and (eq_attr "type" "mtcr") | |
338 | (eq_attr "cpu" "power4")) | |
339 | "du1_power4,iu1_power4") | |
340 | ||
341 | ; Basic FP latency is 6 cycles | |
984e25ac | 342 | (define_insn_reservation "power4-fp" 6 |
b54cf83a DE |
343 | (and (eq_attr "type" "fp,dmul") |
344 | (eq_attr "cpu" "power4")) | |
345 | "fpq_power4") | |
346 | ||
347 | (define_insn_reservation "power4-fpcompare" 5 | |
348 | (and (eq_attr "type" "fpcompare") | |
349 | (eq_attr "cpu" "power4")) | |
350 | "fpq_power4") | |
351 | ||
352 | (define_insn_reservation "power4-sdiv" 33 | |
353 | (and (eq_attr "type" "sdiv,ddiv") | |
354 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
355 | "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
356 | (fpu1_power4*28|fpu2_power4*28)") | |
b54cf83a DE |
357 | |
358 | (define_insn_reservation "power4-sqrt" 40 | |
359 | (and (eq_attr "type" "ssqrt,dsqrt") | |
360 | (eq_attr "cpu" "power4")) | |
1244a8b7 VM |
361 | "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
362 | (fpu1_power4*35|fpu2_power4*35)") | |
b54cf83a | 363 | |
b52110d4 DE |
364 | (define_insn_reservation "power4-isync" 2 |
365 | (and (eq_attr "type" "isync") | |
366 | (eq_attr "cpu" "power4")) | |
1244a8b7 | 367 | "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4") |
b52110d4 | 368 | |
b54cf83a DE |
369 | |
370 | ; VMX | |
d47719fd DE |
371 | (define_insn_reservation "power4-vecsimple" 2 |
372 | (and (eq_attr "type" "vecsimple") | |
373 | (eq_attr "cpu" "power4")) | |
374 | "vq_power4") | |
375 | ||
09ec461d | 376 | (define_insn_reservation "power4-veccomplex" 5 |
d47719fd | 377 | (and (eq_attr "type" "veccomplex") |
b54cf83a DE |
378 | (eq_attr "cpu" "power4")) |
379 | "vq_power4") | |
380 | ||
381 | ; vecfp compare | |
382 | (define_insn_reservation "power4-veccmp" 8 | |
383 | (and (eq_attr "type" "veccmp") | |
384 | (eq_attr "cpu" "power4")) | |
385 | "vq_power4") | |
386 | ||
387 | (define_insn_reservation "power4-vecfloat" 8 | |
388 | (and (eq_attr "type" "vecfloat") | |
389 | (eq_attr "cpu" "power4")) | |
390 | "vq_power4") | |
391 | ||
392 | (define_insn_reservation "power4-vecperm" 2 | |
393 | (and (eq_attr "type" "vecperm") | |
394 | (eq_attr "cpu" "power4")) | |
395 | "vpq_power4") | |
396 | ||
397 | (define_bypass 4 "power4-vecload" "power4-vecperm") | |
d47719fd | 398 | |
09ec461d DE |
399 | (define_bypass 3 "power4-vecsimple" "power4-vecperm") |
400 | (define_bypass 6 "power4-veccomplex" "power4-vecperm") | |
d47719fd DE |
401 | (define_bypass 3 "power4-vecperm" |
402 | "power4-vecsimple,power4-veccomplex,power4-vecfloat") | |
403 | (define_bypass 9 "power4-vecfloat" "power4-vecperm") | |
404 | ||
405 | (define_bypass 5 "power4-vecsimple,power4-veccomplex" | |
2c4a9cff | 406 | "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") |
d47719fd DE |
407 | |
408 | (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore") | |
409 | (define_bypass 7 "power4-veccomplex" "power4-vecstore") | |
410 | (define_bypass 10 "power4-vecfloat" "power4-vecstore") |