[thirdparty/gcc.git] / gcc / config / rs6000 / power4.md

;; Scheduling description for IBM Power4 and PowerPC 970 processors.
;;   Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; Sources: IBM Red Book and White Paper on POWER4

;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
;; Instructions that update more than one register get broken into two
;; (split) or more internal ops.  The chip can issue up to 5
;; internal ops per cycle.

(define_automaton "power4iu,power4fpu,power4vec,power4misc")

(define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
(define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
(define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
(define_cpu_unit "bpu_power4,cru_power4" "power4misc")
(define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
(define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
		 "power4misc")

(define_reservation "lsq_power4"
		    "(du1_power4,lsu1_power4)\
		    |(du2_power4,lsu2_power4)\
		    |(du3_power4,lsu2_power4)\
		    |(du4_power4,lsu1_power4)")

(define_reservation "lsuq_power4"
		    "(du1_power4+du2_power4,lsu1_power4+iu2_power4)\
		    |(du2_power4+du3_power4,lsu2_power4+iu2_power4)\
		    |(du3_power4+du4_power4,lsu2_power4+iu1_power4)")

(define_reservation "iq_power4"
		    "(du1_power4,iu1_power4)\
		    |(du2_power4,iu2_power4)\
		    |(du3_power4,iu2_power4)\
		    |(du4_power4,iu1_power4)")

(define_reservation "fpq_power4"
		    "(du1_power4,fpu1_power4)\
		    |(du2_power4,fpu2_power4)\
		    |(du3_power4,fpu2_power4)\
		    |(du4_power4,fpu1_power4)")

(define_reservation "vq_power4"
		    "(du1_power4,vec_power4)\
		    |(du2_power4,vec_power4)\
		    |(du3_power4,vec_power4)\
		    |(du4_power4,vec_power4)")

(define_reservation "vpq_power4"
		    "(du1_power4,vecperm_power4)\
		    |(du2_power4,vecperm_power4)\
		    |(du3_power4,vecperm_power4)\
		    |(du4_power4,vecperm_power4)")


; Dispatch slots are allocated in order conforming to program order.
(absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
(absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
(absence_set "du3_power4" "du4_power4,du5_power4")
(absence_set "du4_power4" "du5_power4")


; Load/store
(define_insn_reservation "power4-load" 4 ; 3
  (and (eq_attr "type" "load")
       (eq_attr "cpu" "power4"))
  "lsq_power4")

(define_insn_reservation "power4-load-ext" 5
  (and (eq_attr "type" "load_ext")
       (eq_attr "cpu" "power4"))
  "(du1_power4+du2_power4,lsu1_power4,nothing,nothing,iu2_power4)\
  |(du2_power4+du3_power4,lsu2_power4,nothing,nothing,iu2_power4)\
  |(du3_power4+du4_power4,lsu2_power4,nothing,nothing,iu1_power4)")

(define_insn_reservation "power4-load-ext-update" 5
  (and (eq_attr "type" "load_ext_u")
       (eq_attr "cpu" "power4"))
  "du1_power4+du2_power4+du3_power4+du4_power4,\
   lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")

(define_insn_reservation "power4-load-ext-update-indexed" 5
  (and (eq_attr "type" "load_ext_ux")
       (eq_attr "cpu" "power4"))
  "du1_power4+du2_power4+du3_power4+du4_power4,\
   iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")

(define_insn_reservation "power4-load-update-indexed" 3
  (and (eq_attr "type" "load_ux")
       (eq_attr "cpu" "power4"))
  "du1_power4+du2_power4+du3_power4+du4_power4,\
   iu1_power4,lsu2_power4+iu2_power4")

(define_insn_reservation "power4-load-update" 4 ; 3
  (and (eq_attr "type" "load_u")
       (eq_attr "cpu" "power4"))
  "lsuq_power4")

(define_insn_reservation "power4-fpload" 6 ; 5
  (and (eq_attr "type" "fpload")
       (eq_attr "cpu" "power4"))
  "lsq_power4")

(define_insn_reservation "power4-fpload-update" 6 ; 5
  (and (eq_attr "type" "fpload_u,fpload_ux")
       (eq_attr "cpu" "power4"))
  "lsuq_power4")

(define_insn_reservation "power4-vecload" 6 ; 5
  (and (eq_attr "type" "vecload")
       (eq_attr "cpu" "power4"))
  "lsq_power4")

(define_insn_reservation "power4-store" 12
  (and (eq_attr "type" "store")
       (eq_attr "cpu" "power4"))
  "(du1_power4,lsu1_power4,iu1_power4)\
  |(du2_power4,lsu2_power4,iu2_power4)\
  |(du3_power4,lsu2_power4,iu2_power4)\
  |(du4_power4,lsu1_power4,iu1_power4)")

(define_insn_reservation "power4-store-update" 12
  (and (eq_attr "type" "store_u")
       (eq_attr "cpu" "power4"))
  "(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\
  |(du2_power4+du3_power4,lsu2_power4+iu2_power4,iu2_power4)\
  |(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\
  |(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)")

(define_insn_reservation "power4-store-update-indexed" 12
  (and (eq_attr "type" "store_ux")
       (eq_attr "cpu" "power4"))
   "du1_power4+du2_power4+du3_power4+du4_power4,\
    iu1_power4,lsu2_power4+iu2_power4,iu2_power4")

(define_insn_reservation "power4-fpstore" 12
  (and (eq_attr "type" "fpstore")
       (eq_attr "cpu" "power4"))
  "(du1_power4,lsu1_power4,fpu1_power4)\
  |(du2_power4,lsu2_power4,fpu2_power4)\
  |(du3_power4,lsu2_power4,fpu2_power4)\
  |(du4_power4,lsu1_power4,fpu1_power4)")

(define_insn_reservation "power4-fpstore-update" 12
  (and (eq_attr "type" "fpstore_u,fpstore_ux")
       (eq_attr "cpu" "power4"))
  "(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\
  |(du2_power4+du3_power4,lsu2_power4+iu2_power4,fpu2_power4)\
  |(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)")

(define_insn_reservation "power4-vecstore" 12
  (and (eq_attr "type" "vecstore")
       (eq_attr "cpu" "power4"))
  "(du1_power4,lsu1_power4,vec_power4)\
  |(du2_power4,lsu2_power4,vec_power4)\
  |(du3_power4,lsu2_power4,vec_power4)\
  |(du4_power4,lsu1_power4,vec_power4)")

(define_insn_reservation "power4-llsc" 11
  (and (eq_attr "type" "load_l,store_c,sync")
       (eq_attr "cpu" "power4"))
  "du1_power4+du2_power4+du3_power4+du4_power4,\
  lsu1_power4")


; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
  (and (eq_attr "type" "integer,insert_dword,shift,trap,\
                        var_shift_rotate,cntlz,exts")
       (eq_attr "cpu" "power4"))
  "iq_power4")

(define_insn_reservation "power4-two" 2
  (and (eq_attr "type" "two")
       (eq_attr "cpu" "power4"))
  "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
  |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
  |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)\
  |(du4_power4+du1_power4,iu1_power4,nothing,iu1_power4)")

(define_insn_reservation "power4-three" 2
  (and (eq_attr "type" "three")
       (eq_attr "cpu" "power4"))
  "(du1_power4+du2_power4+du3_power4,\
    iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
  |(du2_power4+du3_power4+du4_power4,\
    iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
  |(du3_power4+du4_power4+du1_power4,\
    iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
  |(du4_power4+du1_power4+du2_power4,\
    iu1_power4,nothing,iu2_power4,nothing,iu2_power4)")

(define_insn_reservation "power4-insert" 4
  (and (eq_attr "type" "insert_word")
       (eq_attr "cpu" "power4"))
  "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
  |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
  |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)")

(define_insn_reservation "power4-cmp" 3
  (and (eq_attr "type" "cmp,fast_compare")
       (eq_attr "cpu" "power4"))
  "iq_power4")

(define_insn_reservation "power4-compare" 2
  (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
       (eq_attr "cpu" "power4"))
  "(du1_power4+du2_power4,iu1_power4,iu2_power4)\
  |(du2_power4+du3_power4,iu2_power4,iu2_power4)\
  |(du3_power4+du4_power4,iu2_power4,iu1_power4)")

(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")

(define_insn_reservation "power4-lmul-cmp" 7
  (and (eq_attr "type" "lmul_compare")
       (eq_attr "cpu" "power4"))
  "(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\
  |(du2_power4+du3_power4,iu2_power4*6,iu2_power4)\
  |(du3_power4+du4_power4,iu2_power4*6,iu1_power4)")

(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")

(define_insn_reservation "power4-imul-cmp" 5
  (and (eq_attr "type" "imul_compare")
       (eq_attr "cpu" "power4"))
  "(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\
  |(du2_power4+du3_power4,iu2_power4*4,iu2_power4)\
  |(du3_power4+du4_power4,iu2_power4*4,iu1_power4)")

(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")

(define_insn_reservation "power4-lmul" 7
  (and (eq_attr "type" "lmul")
       (eq_attr "cpu" "power4"))
  "(du1_power4,iu1_power4*6)\
  |(du2_power4,iu2_power4*6)\
  |(du3_power4,iu2_power4*6)\
  |(du4_power4,iu1_power4*6)")

(define_insn_reservation "power4-imul" 5
  (and (eq_attr "type" "imul")
       (eq_attr "cpu" "power4"))
  "(du1_power4,iu1_power4*4)\
  |(du2_power4,iu2_power4*4)\
  |(du3_power4,iu2_power4*4)\
  |(du4_power4,iu1_power4*4)")

(define_insn_reservation "power4-imul3" 4
  (and (eq_attr "type" "imul2,imul3")
       (eq_attr "cpu" "power4"))
  "(du1_power4,iu1_power4*3)\
  |(du2_power4,iu2_power4*3)\
  |(du3_power4,iu2_power4*3)\
  |(du4_power4,iu1_power4*3)")


; SPR move only executes in first IU.
; Integer division only executes in second IU.
(define_insn_reservation "power4-idiv" 36
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "power4"))
  "du1_power4+du2_power4,iu2_power4*35")

(define_insn_reservation "power4-ldiv" 68
  (and (eq_attr "type" "ldiv")
       (eq_attr "cpu" "power4"))
  "du1_power4+du2_power4,iu2_power4*67")


(define_insn_reservation "power4-mtjmpr" 3
  (and (eq_attr "type" "mtjmpr,mfjmpr")
       (eq_attr "cpu" "power4"))
  "du1_power4,bpu_power4")


; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
; grabbing previous dispatch slots once this is assigned.
(define_insn_reservation "power4-branch" 2
  (and (eq_attr "type" "jmpreg,branch")
       (eq_attr "cpu" "power4"))
  "(du5_power4\
   |du4_power4+du5_power4\
   |du3_power4+du4_power4+du5_power4\
   |du2_power4+du3_power4+du4_power4+du5_power4\
   |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")


; Condition Register logical ops are split if non-destructive (RT != RB)
(define_insn_reservation "power4-crlogical" 2
  (and (eq_attr "type" "cr_logical")
       (eq_attr "cpu" "power4"))
  "du1_power4,cru_power4")

(define_insn_reservation "power4-delayedcr" 4
  (and (eq_attr "type" "delayed_cr")
       (eq_attr "cpu" "power4"))
  "du1_power4+du2_power4,cru_power4,cru_power4")

; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
(define_insn_reservation "power4-mfcr" 6
  (and (eq_attr "type" "mfcr")
       (eq_attr "cpu" "power4"))
  "du1_power4+du2_power4+du3_power4+du4_power4,\
   du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
   cru_power4,cru_power4,cru_power4")

; mfcrf (1 field)
(define_insn_reservation "power4-mfcrf" 3
  (and (eq_attr "type" "mfcrf")
       (eq_attr "cpu" "power4"))
  "du1_power4,cru_power4")

; mtcrf (1 field)
(define_insn_reservation "power4-mtcr" 4
  (and (eq_attr "type" "mtcr")
       (eq_attr "cpu" "power4"))
  "du1_power4,iu1_power4")

; Basic FP latency is 6 cycles
(define_insn_reservation "power4-fp" 6
  (and (eq_attr "type" "fp,dmul")
       (eq_attr "cpu" "power4"))
  "fpq_power4")

(define_insn_reservation "power4-fpcompare" 5
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "power4"))
  "fpq_power4")

(define_insn_reservation "power4-sdiv" 33
  (and (eq_attr "type" "sdiv,ddiv")
       (eq_attr "cpu" "power4"))
  "(du1_power4,fpu1_power4*28)\
  |(du2_power4,fpu2_power4*28)\
  |(du3_power4,fpu2_power4*28)\
  |(du4_power4,fpu1_power4*28)")

(define_insn_reservation "power4-sqrt" 40
  (and (eq_attr "type" "ssqrt,dsqrt")
       (eq_attr "cpu" "power4"))
  "(du1_power4,fpu1_power4*35)\
  |(du2_power4,fpu2_power4*35)\
  |(du3_power4,fpu2_power4*35)\
  |(du4_power4,fpu2_power4*35)")

(define_insn_reservation "power4-isync" 2
  (and (eq_attr "type" "isync")
       (eq_attr "cpu" "power4"))
  "du1_power4+du2_power4+du3_power4+du4_power4,\
  lsu1_power4")


; VMX
(define_insn_reservation "power4-vecsimple" 2
  (and (eq_attr "type" "vecsimple")
       (eq_attr "cpu" "power4"))
  "vq_power4")

(define_insn_reservation "power4-veccomplex" 5
  (and (eq_attr "type" "veccomplex")
       (eq_attr "cpu" "power4"))
  "vq_power4")

; vecfp compare
(define_insn_reservation "power4-veccmp" 8
  (and (eq_attr "type" "veccmp")
       (eq_attr "cpu" "power4"))
  "vq_power4")

(define_insn_reservation "power4-vecfloat" 8
  (and (eq_attr "type" "vecfloat")
       (eq_attr "cpu" "power4"))
  "vq_power4")

(define_insn_reservation "power4-vecperm" 2
  (and (eq_attr "type" "vecperm")
       (eq_attr "cpu" "power4"))
  "vpq_power4")

(define_bypass 4 "power4-vecload" "power4-vecperm")

(define_bypass 3 "power4-vecsimple" "power4-vecperm")
(define_bypass 6 "power4-veccomplex" "power4-vecperm")
(define_bypass 3 "power4-vecperm"
		 "power4-vecsimple,power4-veccomplex,power4-vecfloat")
(define_bypass 9 "power4-vecfloat" "power4-vecperm")

(define_bypass 5 "power4-vecsimple,power4-veccomplex"
		 "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")

(define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
(define_bypass 7 "power4-veccomplex" "power4-vecstore")
(define_bypass 10 "power4-vecfloat" "power4-vecstore")
Commit	Line	Data
aac77ea5	1	;; Scheduling description for IBM Power4 and PowerPC 970 processors.
2f83c7d6	2	;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
aac77ea5	3	;;
5de601cf	4	;; This file is part of GCC.
aac77ea5	5	;;
5de601cf NC	6	;; GCC is free software; you can redistribute it and/or modify it
5de601cf NC	7	;; under the terms of the GNU General Public License as published
2f83c7d6	8	;; by the Free Software Foundation; either version 3, or (at your
5de601cf	9	;; option) any later version.
aac77ea5	10	;;
5de601cf NC	11	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	12	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	14	;; License for more details.
aac77ea5 DE	15	;;
aac77ea5 DE	16	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	17	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	18	;; <http://www.gnu.org/licenses/>.
b54cf83a DE	19
	20	;; Sources: IBM Red Book and White Paper on POWER4
	21
	22	;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
	23	;; Instructions that update more than one register get broken into two
	24	;; (split) or more internal ops. The chip can issue up to 5
	25	;; internal ops per cycle.
	26
02ca7595	27	(define_automaton "power4iu,power4fpu,power4vec,power4misc")
b54cf83a DE	28
b54cf83a DE	29	(define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
02ca7595	30	(define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
b54cf83a DE	31	(define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
	32	(define_cpu_unit "bpu_power4,cru_power4" "power4misc")
	33	(define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
	34	(define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
02ca7595	35	"power4misc")
b54cf83a	36
9259f3b0 DE	37	(define_reservation "lsq_power4"
	38	"(du1_power4,lsu1_power4)\
	39	\|(du2_power4,lsu2_power4)\
4e596a09 DE	40	\|(du3_power4,lsu2_power4)\
4e596a09 DE	41	\|(du4_power4,lsu1_power4)")
b54cf83a DE	42
b54cf83a DE	43	(define_reservation "lsuq_power4"
02ca7595 DE	44	"(du1_power4+du2_power4,lsu1_power4+iu2_power4)\
	45	\|(du2_power4+du3_power4,lsu2_power4+iu2_power4)\
	46	\|(du3_power4+du4_power4,lsu2_power4+iu1_power4)")
b54cf83a	47
9259f3b0 DE	48	(define_reservation "iq_power4"
	49	"(du1_power4,iu1_power4)\
	50	\|(du2_power4,iu2_power4)\
4e596a09 DE	51	\|(du3_power4,iu2_power4)\
4e596a09 DE	52	\|(du4_power4,iu1_power4)")
b54cf83a	53
9259f3b0 DE	54	(define_reservation "fpq_power4"
	55	"(du1_power4,fpu1_power4)\
	56	\|(du2_power4,fpu2_power4)\
4e596a09 DE	57	\|(du3_power4,fpu2_power4)\
4e596a09 DE	58	\|(du4_power4,fpu1_power4)")
b54cf83a DE	59
b54cf83a DE	60	(define_reservation "vq_power4"
9259f3b0 DE	61	"(du1_power4,vec_power4)\
9259f3b0 DE	62	\|(du2_power4,vec_power4)\
4e596a09 DE	63	\|(du3_power4,vec_power4)\
4e596a09 DE	64	\|(du4_power4,vec_power4)")
9259f3b0	65
b54cf83a	66	(define_reservation "vpq_power4"
9259f3b0 DE	67	"(du1_power4,vecperm_power4)\
9259f3b0 DE	68	\|(du2_power4,vecperm_power4)\
4e596a09 DE	69	\|(du3_power4,vecperm_power4)\
4e596a09 DE	70	\|(du4_power4,vecperm_power4)")
b54cf83a DE	71
	72
	73	; Dispatch slots are allocated in order conforming to program order.
	74	(absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
	75	(absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
	76	(absence_set "du3_power4" "du4_power4,du5_power4")
	77	(absence_set "du4_power4" "du5_power4")
	78
	79
	80	; Load/store
9259f3b0	81	(define_insn_reservation "power4-load" 4 ; 3
b54cf83a DE	82	(and (eq_attr "type" "load")
	83	(eq_attr "cpu" "power4"))
	84	"lsq_power4")
	85
	86	(define_insn_reservation "power4-load-ext" 5
	87	(and (eq_attr "type" "load_ext")
	88	(eq_attr "cpu" "power4"))
9259f3b0 DE	89	"(du1_power4+du2_power4,lsu1_power4,nothing,nothing,iu2_power4)\
	90	\|(du2_power4+du3_power4,lsu2_power4,nothing,nothing,iu2_power4)\
	91	\|(du3_power4+du4_power4,lsu2_power4,nothing,nothing,iu1_power4)")
b54cf83a DE	92
	93	(define_insn_reservation "power4-load-ext-update" 5
	94	(and (eq_attr "type" "load_ext_u")
	95	(eq_attr "cpu" "power4"))
02ca7595 DE	96	"du1_power4+du2_power4+du3_power4+du4_power4,\
02ca7595 DE	97	lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
b54cf83a DE	98
	99	(define_insn_reservation "power4-load-ext-update-indexed" 5
	100	(and (eq_attr "type" "load_ext_ux")
	101	(eq_attr "cpu" "power4"))
02ca7595	102	"du1_power4+du2_power4+du3_power4+du4_power4,\
9259f3b0	103	iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
b54cf83a	104
984e25ac	105	(define_insn_reservation "power4-load-update-indexed" 3
b54cf83a DE	106	(and (eq_attr "type" "load_ux")
b54cf83a DE	107	(eq_attr "cpu" "power4"))
02ca7595	108	"du1_power4+du2_power4+du3_power4+du4_power4,\
9259f3b0	109	iu1_power4,lsu2_power4+iu2_power4")
b54cf83a	110
9259f3b0	111	(define_insn_reservation "power4-load-update" 4 ; 3
b54cf83a DE	112	(and (eq_attr "type" "load_u")
	113	(eq_attr "cpu" "power4"))
	114	"lsuq_power4")
	115
9259f3b0	116	(define_insn_reservation "power4-fpload" 6 ; 5
b54cf83a DE	117	(and (eq_attr "type" "fpload")
	118	(eq_attr "cpu" "power4"))
	119	"lsq_power4")
	120
9259f3b0 DE	121	(define_insn_reservation "power4-fpload-update" 6 ; 5
9259f3b0 DE	122	(and (eq_attr "type" "fpload_u,fpload_ux")
b54cf83a DE	123	(eq_attr "cpu" "power4"))
	124	"lsuq_power4")
	125
9259f3b0	126	(define_insn_reservation "power4-vecload" 6 ; 5
b54cf83a DE	127	(and (eq_attr "type" "vecload")
	128	(eq_attr "cpu" "power4"))
	129	"lsq_power4")
	130
594a3565	131	(define_insn_reservation "power4-store" 12
6d6ab190	132	(and (eq_attr "type" "store")
b54cf83a	133	(eq_attr "cpu" "power4"))
9259f3b0 DE	134	"(du1_power4,lsu1_power4,iu1_power4)\
9259f3b0 DE	135	\|(du2_power4,lsu2_power4,iu2_power4)\
4e596a09 DE	136	\|(du3_power4,lsu2_power4,iu2_power4)\
4e596a09 DE	137	\|(du4_power4,lsu1_power4,iu1_power4)")
b54cf83a	138
594a3565	139	(define_insn_reservation "power4-store-update" 12
b54cf83a DE	140	(and (eq_attr "type" "store_u")
b54cf83a DE	141	(eq_attr "cpu" "power4"))
9259f3b0 DE	142	"(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\
	143	\|(du2_power4+du3_power4,lsu2_power4+iu2_power4,iu2_power4)\
	144	\|(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\
	145	\|(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)")
b54cf83a	146
594a3565	147	(define_insn_reservation "power4-store-update-indexed" 12
b54cf83a DE	148	(and (eq_attr "type" "store_ux")
b54cf83a DE	149	(eq_attr "cpu" "power4"))
9259f3b0 DE	150	"du1_power4+du2_power4+du3_power4+du4_power4,\
9259f3b0 DE	151	iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
b54cf83a	152
594a3565	153	(define_insn_reservation "power4-fpstore" 12
b54cf83a DE	154	(and (eq_attr "type" "fpstore")
b54cf83a DE	155	(eq_attr "cpu" "power4"))
9259f3b0 DE	156	"(du1_power4,lsu1_power4,fpu1_power4)\
9259f3b0 DE	157	\|(du2_power4,lsu2_power4,fpu2_power4)\
4e596a09 DE	158	\|(du3_power4,lsu2_power4,fpu2_power4)\
4e596a09 DE	159	\|(du4_power4,lsu1_power4,fpu1_power4)")
b54cf83a	160
594a3565	161	(define_insn_reservation "power4-fpstore-update" 12
9259f3b0	162	(and (eq_attr "type" "fpstore_u,fpstore_ux")
b54cf83a	163	(eq_attr "cpu" "power4"))
9259f3b0 DE	164	"(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\
	165	\|(du2_power4+du3_power4,lsu2_power4+iu2_power4,fpu2_power4)\
	166	\|(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)")
b54cf83a	167
594a3565	168	(define_insn_reservation "power4-vecstore" 12
6d6ab190 DE	169	(and (eq_attr "type" "vecstore")
6d6ab190 DE	170	(eq_attr "cpu" "power4"))
9259f3b0 DE	171	"(du1_power4,lsu1_power4,vec_power4)\
9259f3b0 DE	172	\|(du2_power4,lsu2_power4,vec_power4)\
4e596a09 DE	173	\|(du3_power4,lsu2_power4,vec_power4)\
4e596a09 DE	174	\|(du4_power4,lsu1_power4,vec_power4)")
6d6ab190	175
b52110d4 DE	176	(define_insn_reservation "power4-llsc" 11
	177	(and (eq_attr "type" "load_l,store_c,sync")
	178	(eq_attr "cpu" "power4"))
	179	"du1_power4+du2_power4+du3_power4+du4_power4,\
	180	lsu1_power4")
	181
b54cf83a DE	182
	183	; Integer latency is 2 cycles
	184	(define_insn_reservation "power4-integer" 2
44cd321e PS	185	(and (eq_attr "type" "integer,insert_dword,shift,trap,\
44cd321e PS	186	var_shift_rotate,cntlz,exts")
b54cf83a DE	187	(eq_attr "cpu" "power4"))
	188	"iq_power4")
	189
943c15ed DE	190	(define_insn_reservation "power4-two" 2
	191	(and (eq_attr "type" "two")
	192	(eq_attr "cpu" "power4"))
	193	"(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
	194	\|(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
	195	\|(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)\
	196	\|(du4_power4+du1_power4,iu1_power4,nothing,iu1_power4)")
	197
	198	(define_insn_reservation "power4-three" 2
	199	(and (eq_attr "type" "three")
	200	(eq_attr "cpu" "power4"))
	201	"(du1_power4+du2_power4+du3_power4,\
	202	iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
	203	\|(du2_power4+du3_power4+du4_power4,\
	204	iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
	205	\|(du3_power4+du4_power4+du1_power4,\
	206	iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
	207	\|(du4_power4+du1_power4+du2_power4,\
	208	iu1_power4,nothing,iu2_power4,nothing,iu2_power4)")
	209
8e8238f1 DE	210	(define_insn_reservation "power4-insert" 4
	211	(and (eq_attr "type" "insert_word")
	212	(eq_attr "cpu" "power4"))
	213	"(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
	214	\|(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
	215	\|(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)")
	216
b54cf83a	217	(define_insn_reservation "power4-cmp" 3
a62bfff2	218	(and (eq_attr "type" "cmp,fast_compare")
b54cf83a DE	219	(eq_attr "cpu" "power4"))
	220	"iq_power4")
	221
9259f3b0	222	(define_insn_reservation "power4-compare" 2
44cd321e	223	(and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
b54cf83a	224	(eq_attr "cpu" "power4"))
9259f3b0 DE	225	"(du1_power4+du2_power4,iu1_power4,iu2_power4)\
9259f3b0 DE	226	\|(du2_power4+du3_power4,iu2_power4,iu2_power4)\
4e596a09	227	\|(du3_power4+du4_power4,iu2_power4,iu1_power4)")
b54cf83a	228
2c4a9cff	229	(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
f8f0e566	230
984e25ac	231	(define_insn_reservation "power4-lmul-cmp" 7
9259f3b0	232	(and (eq_attr "type" "lmul_compare")
b54cf83a	233	(eq_attr "cpu" "power4"))
9259f3b0 DE	234	"(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\
	235	\|(du2_power4+du3_power4,iu2_power4*6,iu2_power4)\
	236	\|(du3_power4+du4_power4,iu2_power4*6,iu1_power4)")
b54cf83a	237
2c4a9cff	238	(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
9259f3b0	239
984e25ac	240	(define_insn_reservation "power4-imul-cmp" 5
9259f3b0 DE	241	(and (eq_attr "type" "imul_compare")
	242	(eq_attr "cpu" "power4"))
	243	"(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\
	244	\|(du2_power4+du3_power4,iu2_power4*4,iu2_power4)\
	245	\|(du3_power4+du4_power4,iu2_power4*4,iu1_power4)")
9259f3b0	246
2c4a9cff	247	(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
9259f3b0	248
984e25ac	249	(define_insn_reservation "power4-lmul" 7
9259f3b0	250	(and (eq_attr "type" "lmul")
b54cf83a	251	(eq_attr "cpu" "power4"))
9259f3b0 DE	252	"(du1_power4,iu1_power4*6)\
	253	\|(du2_power4,iu2_power4*6)\
	254	\|(du3_power4,iu2_power4*6)\
f0259218	255	\|(du4_power4,iu1_power4*6)")
b54cf83a	256
984e25ac	257	(define_insn_reservation "power4-imul" 5
9259f3b0	258	(and (eq_attr "type" "imul")
b54cf83a	259	(eq_attr "cpu" "power4"))
9259f3b0 DE	260	"(du1_power4,iu1_power4*4)\
	261	\|(du2_power4,iu2_power4*4)\
	262	\|(du3_power4,iu2_power4*4)\
	263	\|(du4_power4,iu1_power4*4)")
9259f3b0	264
984e25ac	265	(define_insn_reservation "power4-imul3" 4
9259f3b0 DE	266	(and (eq_attr "type" "imul2,imul3")
	267	(eq_attr "cpu" "power4"))
	268	"(du1_power4,iu1_power4*3)\
	269	\|(du2_power4,iu2_power4*3)\
	270	\|(du3_power4,iu2_power4*3)\
	271	\|(du4_power4,iu1_power4*3)")
9259f3b0	272
b54cf83a DE	273
	274	; SPR move only executes in first IU.
	275	; Integer division only executes in second IU.
	276	(define_insn_reservation "power4-idiv" 36
	277	(and (eq_attr "type" "idiv")
	278	(eq_attr "cpu" "power4"))
02ca7595	279	"du1_power4+du2_power4,iu2_power4*35")
b54cf83a DE	280
	281	(define_insn_reservation "power4-ldiv" 68
	282	(and (eq_attr "type" "ldiv")
	283	(eq_attr "cpu" "power4"))
02ca7595	284	"du1_power4+du2_power4,iu2_power4*67")
b54cf83a DE	285
	286
	287	(define_insn_reservation "power4-mtjmpr" 3
02ca7595	288	(and (eq_attr "type" "mtjmpr,mfjmpr")
b54cf83a DE	289	(eq_attr "cpu" "power4"))
	290	"du1_power4,bpu_power4")
	291
	292
	293	; Branches take dispatch Slot 4. The presence_sets prevent other insn from
	294	; grabbing previous dispatch slots once this is assigned.
	295	(define_insn_reservation "power4-branch" 2
	296	(and (eq_attr "type" "jmpreg,branch")
	297	(eq_attr "cpu" "power4"))
29ae9364 DE	298	"(du5_power4\
	299	\|du4_power4+du5_power4\
	300	\|du3_power4+du4_power4+du5_power4\
	301	\|du2_power4+du3_power4+du4_power4+du5_power4\
	302	\|du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
b54cf83a DE	303
	304
	305	; Condition Register logical ops are split if non-destructive (RT != RB)
	306	(define_insn_reservation "power4-crlogical" 2
	307	(and (eq_attr "type" "cr_logical")
	308	(eq_attr "cpu" "power4"))
	309	"du1_power4,cru_power4")
	310
	311	(define_insn_reservation "power4-delayedcr" 4
	312	(and (eq_attr "type" "delayed_cr")
	313	(eq_attr "cpu" "power4"))
02ca7595	314	"du1_power4+du2_power4,cru_power4,cru_power4")
b54cf83a DE	315
	316	; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
	317	(define_insn_reservation "power4-mfcr" 6
	318	(and (eq_attr "type" "mfcr")
	319	(eq_attr "cpu" "power4"))
02ca7595 DE	320	"du1_power4+du2_power4+du3_power4+du4_power4,\
	321	du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
	322	cru_power4,cru_power4,cru_power4")
b54cf83a	323
2c4a9cff DE	324	; mfcrf (1 field)
	325	(define_insn_reservation "power4-mfcrf" 3
	326	(and (eq_attr "type" "mfcrf")
	327	(eq_attr "cpu" "power4"))
	328	"du1_power4,cru_power4")
	329
b54cf83a DE	330	; mtcrf (1 field)
	331	(define_insn_reservation "power4-mtcr" 4
	332	(and (eq_attr "type" "mtcr")
	333	(eq_attr "cpu" "power4"))
	334	"du1_power4,iu1_power4")
	335
	336	; Basic FP latency is 6 cycles
984e25ac	337	(define_insn_reservation "power4-fp" 6
b54cf83a DE	338	(and (eq_attr "type" "fp,dmul")
	339	(eq_attr "cpu" "power4"))
	340	"fpq_power4")
	341
	342	(define_insn_reservation "power4-fpcompare" 5
	343	(and (eq_attr "type" "fpcompare")
	344	(eq_attr "cpu" "power4"))
	345	"fpq_power4")
	346
	347	(define_insn_reservation "power4-sdiv" 33
	348	(and (eq_attr "type" "sdiv,ddiv")
	349	(eq_attr "cpu" "power4"))
9259f3b0 DE	350	"(du1_power4,fpu1_power4*28)\
	351	\|(du2_power4,fpu2_power4*28)\
	352	\|(du3_power4,fpu2_power4*28)\
	353	\|(du4_power4,fpu1_power4*28)")
b54cf83a DE	354
	355	(define_insn_reservation "power4-sqrt" 40
	356	(and (eq_attr "type" "ssqrt,dsqrt")
	357	(eq_attr "cpu" "power4"))
9259f3b0 DE	358	"(du1_power4,fpu1_power4*35)\
	359	\|(du2_power4,fpu2_power4*35)\
	360	\|(du3_power4,fpu2_power4*35)\
	361	\|(du4_power4,fpu2_power4*35)")
b54cf83a	362
b52110d4 DE	363	(define_insn_reservation "power4-isync" 2
	364	(and (eq_attr "type" "isync")
	365	(eq_attr "cpu" "power4"))
	366	"du1_power4+du2_power4+du3_power4+du4_power4,\
	367	lsu1_power4")
	368
b54cf83a DE	369
b54cf83a DE	370	; VMX
d47719fd DE	371	(define_insn_reservation "power4-vecsimple" 2
	372	(and (eq_attr "type" "vecsimple")
	373	(eq_attr "cpu" "power4"))
	374	"vq_power4")
	375
09ec461d	376	(define_insn_reservation "power4-veccomplex" 5
d47719fd	377	(and (eq_attr "type" "veccomplex")
b54cf83a DE	378	(eq_attr "cpu" "power4"))
	379	"vq_power4")
	380
	381	; vecfp compare
	382	(define_insn_reservation "power4-veccmp" 8
	383	(and (eq_attr "type" "veccmp")
	384	(eq_attr "cpu" "power4"))
	385	"vq_power4")
	386
	387	(define_insn_reservation "power4-vecfloat" 8
	388	(and (eq_attr "type" "vecfloat")
	389	(eq_attr "cpu" "power4"))
	390	"vq_power4")
	391
	392	(define_insn_reservation "power4-vecperm" 2
	393	(and (eq_attr "type" "vecperm")
	394	(eq_attr "cpu" "power4"))
	395	"vpq_power4")
	396
	397	(define_bypass 4 "power4-vecload" "power4-vecperm")
d47719fd	398
09ec461d DE	399	(define_bypass 3 "power4-vecsimple" "power4-vecperm")
09ec461d DE	400	(define_bypass 6 "power4-veccomplex" "power4-vecperm")
d47719fd DE	401	(define_bypass 3 "power4-vecperm"
	402	"power4-vecsimple,power4-veccomplex,power4-vecfloat")
	403	(define_bypass 9 "power4-vecfloat" "power4-vecperm")
	404
	405	(define_bypass 5 "power4-vecsimple,power4-veccomplex"
2c4a9cff	406	"power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
d47719fd DE	407
	408	(define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
	409	(define_bypass 7 "power4-veccomplex" "power4-vecstore")
	410	(define_bypass 10 "power4-vecfloat" "power4-vecstore")