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1 | ;; Scheduling description for IBM POWER5 processor. |
2 | ;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. | |
3 | ;; | |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify it | |
7 | ;; under the terms of the GNU General Public License as published | |
8 | ;; by the Free Software Foundation; either version 2, or (at your | |
9 | ;; option) any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
12 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | ;; License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING. If not, write to the | |
18 | ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
19 | ;; MA 02111-1307, USA. | |
20 | ||
21 | ;; Sources: IBM Red Book and White Paper on POWER5 | |
22 | ||
23 | ;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). | |
24 | ;; Instructions that update more than one register get broken into two | |
25 | ;; (split) or more internal ops. The chip can issue up to 5 | |
26 | ;; internal ops per cycle. | |
27 | ||
28 | (define_automaton "power5iu,power5fpu,power5misc") | |
29 | ||
30 | (define_cpu_unit "iu1_power5,iu2_power5" "power5iu") | |
31 | (define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc") | |
32 | (define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu") | |
33 | (define_cpu_unit "bpu_power5,cru_power5" "power5misc") | |
34 | (define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5" | |
35 | "power5misc") | |
36 | ||
37 | (define_reservation "lsq_power5" | |
38 | "(du1_power5,lsu1_power5)\ | |
39 | |(du2_power5,lsu2_power5)\ | |
40 | |(du3_power5,nothing,lsu2_power5)\ | |
41 | |(du4_power5,nothing,lsu1_power5)") | |
42 | ||
43 | (define_reservation "iq_power5" | |
44 | "(du1_power5,iu1_power5)\ | |
45 | |(du2_power5,iu2_power5)\ | |
46 | |(du3_power5,nothing,iu2_power5)\ | |
47 | |(du4_power5,nothing,iu1_power5)") | |
48 | ||
49 | (define_reservation "fpq_power5" | |
50 | "(du1_power5,fpu1_power5)\ | |
51 | |(du2_power5,fpu2_power5)\ | |
52 | |(du3_power5,nothing,fpu2_power5)\ | |
53 | |(du4_power5,nothing,fpu1_power5)") | |
54 | ||
55 | ; Dispatch slots are allocated in order conforming to program order. | |
56 | (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5") | |
57 | (absence_set "du2_power5" "du3_power5,du4_power5,du5_power5") | |
58 | (absence_set "du3_power5" "du4_power5,du5_power5") | |
59 | (absence_set "du4_power5" "du5_power5") | |
60 | ||
61 | ||
62 | ; Load/store | |
63 | (define_insn_reservation "power5-load" 4 ; 3 | |
64 | (and (eq_attr "type" "load") | |
65 | (eq_attr "cpu" "power5")) | |
66 | "lsq_power5") | |
67 | ||
68 | (define_insn_reservation "power5-load-ext" 5 | |
69 | (and (eq_attr "type" "load_ext") | |
70 | (eq_attr "cpu" "power5")) | |
71 | "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5") | |
72 | ||
73 | (define_insn_reservation "power5-load-ext-update" 5 | |
74 | (and (eq_attr "type" "load_ext_u") | |
75 | (eq_attr "cpu" "power5")) | |
76 | "du1_power5+du2_power5+du3_power5+du4_power5,\ | |
77 | lsu1_power5+iu2_power5,nothing,nothing,iu2_power5") | |
78 | ||
79 | (define_insn_reservation "power5-load-ext-update-indexed" 5 | |
80 | (and (eq_attr "type" "load_ext_ux") | |
81 | (eq_attr "cpu" "power5")) | |
82 | "du1_power5+du2_power5+du3_power5+du4_power5,\ | |
83 | iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5") | |
84 | ||
85 | (define_insn_reservation "power5-load-update-indexed" 3 | |
86 | (and (eq_attr "type" "load_ux") | |
87 | (eq_attr "cpu" "power5")) | |
88 | "du1_power5+du2_power5+du3_power5+du4_power5,\ | |
89 | iu1_power5,lsu2_power5+iu2_power5") | |
90 | ||
91 | (define_insn_reservation "power5-load-update" 4 ; 3 | |
92 | (and (eq_attr "type" "load_u") | |
93 | (eq_attr "cpu" "power5")) | |
94 | "du1_power5+du2_power5,lsu1_power5+iu2_power5") | |
95 | ||
96 | (define_insn_reservation "power5-fpload" 6 ; 5 | |
97 | (and (eq_attr "type" "fpload") | |
98 | (eq_attr "cpu" "power5")) | |
99 | "lsq_power5") | |
100 | ||
101 | (define_insn_reservation "power5-fpload-update" 6 ; 5 | |
102 | (and (eq_attr "type" "fpload_u,fpload_ux") | |
103 | (eq_attr "cpu" "power5")) | |
104 | "du1_power5+du2_power5,lsu1_power5+iu2_power5") | |
105 | ||
106 | (define_insn_reservation "power5-store" 1 | |
107 | (and (eq_attr "type" "store") | |
108 | (eq_attr "cpu" "power5")) | |
109 | "(du1_power5,lsu1_power5,iu1_power5)\ | |
110 | |(du2_power5,lsu2_power5,iu2_power5)\ | |
111 | |(du3_power5,lsu2_power5,nothing,iu2_power5)\ | |
112 | |(du4_power5,lsu1_power5,nothing,iu1_power5)") | |
113 | ||
114 | (define_insn_reservation "power5-store-update" 1 | |
115 | (and (eq_attr "type" "store_u") | |
116 | (eq_attr "cpu" "power5")) | |
117 | "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") | |
118 | ||
119 | (define_insn_reservation "power5-store-update-indexed" 1 | |
120 | (and (eq_attr "type" "store_ux") | |
121 | (eq_attr "cpu" "power5")) | |
122 | "du1_power5+du2_power5+du3_power5+du4_power5,\ | |
123 | iu1_power5,lsu2_power5+iu2_power5,iu2_power5") | |
124 | ||
125 | (define_insn_reservation "power5-fpstore" 1 | |
126 | (and (eq_attr "type" "fpstore") | |
127 | (eq_attr "cpu" "power5")) | |
128 | "(du1_power5,lsu1_power5,fpu1_power5)\ | |
129 | |(du2_power5,lsu2_power5,fpu2_power5)\ | |
130 | |(du3_power5,lsu2_power5,nothing,fpu2_power5)\ | |
131 | |(du4_power5,lsu1_power5,nothing,fpu1_power5)") | |
132 | ||
133 | (define_insn_reservation "power5-fpstore-update" 1 | |
134 | (and (eq_attr "type" "fpstore_u,fpstore_ux") | |
135 | (eq_attr "cpu" "power5")) | |
136 | "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") | |
137 | ||
138 | ||
139 | ; Integer latency is 2 cycles | |
140 | (define_insn_reservation "power5-integer" 2 | |
141 | (and (eq_attr "type" "integer") | |
142 | (eq_attr "cpu" "power5")) | |
143 | "iq_power5") | |
144 | ||
145 | (define_insn_reservation "power5-insert" 4 | |
146 | (and (eq_attr "type" "insert_word") | |
147 | (eq_attr "cpu" "power5")) | |
148 | "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5") | |
149 | ||
150 | (define_insn_reservation "power5-cmp" 3 | |
151 | (and (eq_attr "type" "cmp,fast_compare") | |
152 | (eq_attr "cpu" "power5")) | |
153 | "iq_power5") | |
154 | ||
155 | (define_insn_reservation "power5-compare" 2 | |
156 | (and (eq_attr "type" "compare,delayed_compare") | |
157 | (eq_attr "cpu" "power5")) | |
158 | "du1_power5+du2_power5,iu1_power5,iu2_power5") | |
159 | ||
160 | (define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") | |
161 | ||
162 | (define_insn_reservation "power5-lmul-cmp" 7 | |
163 | (and (eq_attr "type" "lmul_compare") | |
164 | (eq_attr "cpu" "power5")) | |
165 | "du1_power5+du2_power5,iu1_power5*6,iu2_power5") | |
166 | ||
167 | (define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") | |
168 | ||
169 | (define_insn_reservation "power5-imul-cmp" 5 | |
170 | (and (eq_attr "type" "imul_compare") | |
171 | (eq_attr "cpu" "power5")) | |
172 | "du1_power5+du2_power5,iu1_power5*4,iu2_power5") | |
173 | ||
174 | (define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") | |
175 | ||
176 | (define_insn_reservation "power5-lmul" 7 | |
177 | (and (eq_attr "type" "lmul") | |
178 | (eq_attr "cpu" "power5")) | |
179 | "(du1_power5,iu1_power5*6)\ | |
180 | |(du2_power5,iu2_power5*6)\ | |
181 | |(du3_power5,iu2_power5*6)\ | |
182 | |(du4_power5,iu2_power5*6)") | |
183 | ; |(du3_power5,nothing,iu2_power5*6)\ | |
184 | ; |(du4_power5,nothing,iu2_power5*6)") | |
185 | ||
186 | (define_insn_reservation "power5-imul" 5 | |
187 | (and (eq_attr "type" "imul") | |
188 | (eq_attr "cpu" "power5")) | |
189 | "(du1_power5,iu1_power5*4)\ | |
190 | |(du2_power5,iu2_power5*4)\ | |
191 | |(du3_power5,iu2_power5*4)\ | |
192 | |(du4_power5,iu1_power5*4)") | |
193 | ; |(du3_power5,nothing,iu2_power5*4)\ | |
194 | ; |(du4_power5,nothing,iu1_power5*4)") | |
195 | ||
196 | (define_insn_reservation "power5-imul3" 4 | |
197 | (and (eq_attr "type" "imul2,imul3") | |
198 | (eq_attr "cpu" "power5")) | |
199 | "(du1_power5,iu1_power5*3)\ | |
200 | |(du2_power5,iu2_power5*3)\ | |
201 | |(du3_power5,iu2_power5*3)\ | |
202 | |(du4_power5,iu1_power5*3)") | |
203 | ; |(du3_power5,nothing,iu2_power5*3)\ | |
204 | ; |(du4_power5,nothing,iu1_power5*3)") | |
205 | ||
206 | ||
207 | ; SPR move only executes in first IU. | |
208 | ; Integer division only executes in second IU. | |
209 | (define_insn_reservation "power5-idiv" 36 | |
210 | (and (eq_attr "type" "idiv") | |
211 | (eq_attr "cpu" "power5")) | |
212 | "du1_power5+du2_power5,iu2_power5*35") | |
213 | ||
214 | (define_insn_reservation "power5-ldiv" 68 | |
215 | (and (eq_attr "type" "ldiv") | |
216 | (eq_attr "cpu" "power5")) | |
217 | "du1_power5+du2_power5,iu2_power5*67") | |
218 | ||
219 | ||
220 | (define_insn_reservation "power5-mtjmpr" 3 | |
221 | (and (eq_attr "type" "mtjmpr,mfjmpr") | |
222 | (eq_attr "cpu" "power5")) | |
223 | "du1_power5,bpu_power5") | |
224 | ||
225 | ||
226 | ; Branches take dispatch Slot 4. The presence_sets prevent other insn from | |
227 | ; grabbing previous dispatch slots once this is assigned. | |
228 | (define_insn_reservation "power5-branch" 2 | |
229 | (and (eq_attr "type" "jmpreg,branch") | |
230 | (eq_attr "cpu" "power5")) | |
231 | "(du5_power5\ | |
232 | |du4_power5+du5_power5\ | |
233 | |du3_power5+du4_power5+du5_power5\ | |
234 | |du2_power5+du3_power5+du4_power5+du5_power5\ | |
235 | |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5") | |
236 | ||
237 | ||
238 | ; Condition Register logical ops are split if non-destructive (RT != RB) | |
239 | (define_insn_reservation "power5-crlogical" 2 | |
240 | (and (eq_attr "type" "cr_logical") | |
241 | (eq_attr "cpu" "power5")) | |
242 | "du1_power5,cru_power5") | |
243 | ||
244 | (define_insn_reservation "power5-delayedcr" 4 | |
245 | (and (eq_attr "type" "delayed_cr") | |
246 | (eq_attr "cpu" "power5")) | |
247 | "du1_power5+du2_power5,cru_power5,cru_power5") | |
248 | ||
249 | ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu | |
250 | (define_insn_reservation "power5-mfcr" 6 | |
251 | (and (eq_attr "type" "mfcr") | |
252 | (eq_attr "cpu" "power5")) | |
253 | "du1_power5+du2_power5+du3_power5+du4_power5,\ | |
254 | du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\ | |
255 | cru_power5,cru_power5,cru_power5") | |
256 | ||
257 | ; mfcrf (1 field) | |
258 | (define_insn_reservation "power5-mfcrf" 3 | |
259 | (and (eq_attr "type" "mfcrf") | |
260 | (eq_attr "cpu" "power5")) | |
261 | "du1_power5,cru_power5") | |
262 | ||
263 | ; mtcrf (1 field) | |
264 | (define_insn_reservation "power5-mtcr" 4 | |
265 | (and (eq_attr "type" "mtcr") | |
266 | (eq_attr "cpu" "power5")) | |
267 | "du1_power5,iu1_power5") | |
268 | ||
269 | ; Basic FP latency is 6 cycles | |
270 | (define_insn_reservation "power5-fp" 6 | |
271 | (and (eq_attr "type" "fp,dmul") | |
272 | (eq_attr "cpu" "power5")) | |
273 | "fpq_power5") | |
274 | ||
275 | (define_insn_reservation "power5-fpcompare" 5 | |
276 | (and (eq_attr "type" "fpcompare") | |
277 | (eq_attr "cpu" "power5")) | |
278 | "fpq_power5") | |
279 | ||
280 | (define_insn_reservation "power5-sdiv" 33 | |
281 | (and (eq_attr "type" "sdiv,ddiv") | |
282 | (eq_attr "cpu" "power5")) | |
283 | "(du1_power5,fpu1_power5*28)\ | |
284 | |(du2_power5,fpu2_power5*28)\ | |
285 | |(du3_power5,fpu2_power5*28)\ | |
286 | |(du4_power5,fpu1_power5*28)") | |
287 | ; |(du3_power5,nothing,fpu2_power5*28)\ | |
288 | ; |(du4_power5,nothing,fpu1_power5*28)") | |
289 | ||
290 | (define_insn_reservation "power5-sqrt" 40 | |
291 | (and (eq_attr "type" "ssqrt,dsqrt") | |
292 | (eq_attr "cpu" "power5")) | |
293 | "(du1_power5,fpu1_power5*35)\ | |
294 | |(du2_power5,fpu2_power5*35)\ | |
295 | |(du3_power5,fpu2_power5*35)\ | |
296 | |(du4_power5,fpu2_power5*35)") | |
297 | ; |(du3_power5,nothing,fpu2_power5*35)\ | |
298 | ; |(du4_power5,nothing,fpu2_power5*35)") | |
299 |