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1 | ;; Scheduling description for IBM POWER6 processor. |
2 | ;; Copyright (C) 2006 Free Software Foundation, Inc. | |
3 | ;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com) | |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 2, or (at your | |
10 | ;; option) any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING. If not, write to the | |
19 | ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, | |
20 | ;; MA 02110-1301, USA. | |
21 | ||
22 | ;; Sources: | |
23 | ||
24 | ;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine | |
25 | ;; (2 engines per chip). The chip can issue up to 5 internal ops | |
26 | ;; per cycle. | |
27 | ||
28 | (define_automaton "power6iu,power6lsu,power6fpu,power6bu") | |
29 | ||
30 | (define_cpu_unit "iu1_power6,iu2_power6" "power6iu") | |
31 | (define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu") | |
32 | (define_cpu_unit "bpu_power6" "power6bu") | |
33 | (define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu") | |
34 | ||
35 | (define_reservation "LS2_power6" | |
36 | "lsu1_power6+lsu2_power6") | |
37 | ||
38 | (define_reservation "FPU_power6" | |
39 | "fpu1_power6|fpu2_power6") | |
40 | ||
41 | (define_reservation "BRU_power6" | |
42 | "bpu_power6") | |
43 | ||
44 | (define_reservation "LSU_power6" | |
45 | "lsu1_power6|lsu2_power6") | |
46 | ||
47 | (define_reservation "LSF_power6" | |
48 | "(lsu1_power6+fpu1_power6)\ | |
49 | |(lsu1_power6+fpu2_power6)\ | |
50 | |(lsu2_power6+fpu1_power6)\ | |
51 | |(lsu2_power6+fpu2_power6)") | |
52 | ||
53 | (define_reservation "LX2_power6" | |
54 | "(iu1_power6+iu2_power6+lsu1_power6)\ | |
55 | |(iu1_power6+iu2_power6+lsu2_power6)") | |
56 | ||
57 | (define_reservation "FX2_power6" | |
58 | "iu1_power6+iu2_power6") | |
59 | ||
60 | (define_reservation "X2F_power6" | |
61 | "(iu1_power6+iu2_power6+fpu1_power6)\ | |
62 | |(iu1_power6+iu2_power6+fpu2_power6)") | |
63 | ||
64 | (define_reservation "BX2_power6" | |
65 | "iu1_power6+iu2_power6+bpu_power6") | |
66 | ||
67 | (define_reservation "LSX_power6" | |
68 | "(iu1_power6+lsu1_power6)\ | |
69 | |(iu1_power6+lsu2_power6)\ | |
70 | |(iu2_power6+lsu1_power6)\ | |
71 | |(iu2_power6+lsu2_power6)") | |
72 | ||
73 | (define_reservation "FXU_power6" | |
74 | "iu1_power6|iu2_power6") | |
75 | ||
76 | (define_reservation "XLF_power6" | |
77 | "(iu1_power6+lsu1_power6+fpu1_power6)\ | |
78 | |(iu1_power6+lsu1_power6+fpu2_power6)\ | |
79 | |(iu1_power6+lsu2_power6+fpu1_power6)\ | |
80 | |(iu1_power6+lsu2_power6+fpu2_power6)\ | |
81 | |(iu2_power6+lsu1_power6+fpu1_power6)\ | |
82 | |(iu2_power6+lsu1_power6+fpu2_power6)\ | |
83 | |(iu2_power6+lsu2_power6+fpu1_power6)\ | |
84 | |(iu2_power6+lsu2_power6+fpu2_power6)") | |
85 | ||
86 | (define_reservation "BRX_power6" | |
87 | "(bpu_power6+iu1_power6)\ | |
88 | |(bpu_power6+iu2_power6)") | |
89 | ||
90 | ; Load/store | |
91 | ||
92 | ; The default for a value written by a fixed point load | |
93 | ; that is read/written by a subsequent fixed point op. | |
94 | (define_insn_reservation "power6-load" 2 ; fx | |
95 | (and (eq_attr "type" "load") | |
96 | (eq_attr "cpu" "power6")) | |
97 | "LSU_power6") | |
98 | ||
99 | ; define the bypass for the case where the value written | |
100 | ; by a fixed point load is used as the source value on | |
101 | ; a store. | |
102 | (define_bypass 1 "power6-load,\ | |
103 | power6-load-update,\ | |
104 | power6-load-update-indexed" | |
105 | "power6-store,\ | |
106 | power6-store-update,\ | |
107 | power6-store-update-indexed,\ | |
108 | power6-fpstore,\ | |
109 | power6-fpstore-update" | |
110 | "store_data_bypass_p") | |
111 | ||
112 | (define_insn_reservation "power6-load-ext" 4 ; fx | |
113 | (and (eq_attr "type" "load_ext") | |
114 | (eq_attr "cpu" "power6")) | |
115 | "LSU_power6") | |
116 | ||
117 | ; define the bypass for the case where the value written | |
118 | ; by a fixed point load ext is used as the source value on | |
119 | ; a store. | |
120 | (define_bypass 1 "power6-load-ext,\ | |
121 | power6-load-ext-update,\ | |
122 | power6-load-ext-update-indexed" | |
123 | "power6-store,\ | |
124 | power6-store-update,\ | |
125 | power6-store-update-indexed,\ | |
126 | power6-fpstore,\ | |
127 | power6-fpstore-update" | |
128 | "store_data_bypass_p") | |
129 | ||
130 | (define_insn_reservation "power6-load-update" 2 ; fx | |
131 | (and (eq_attr "type" "load_u") | |
132 | (eq_attr "cpu" "power6")) | |
133 | "LSX_power6") | |
134 | ||
135 | (define_insn_reservation "power6-load-update-indexed" 2 ; fx | |
136 | (and (eq_attr "type" "load_ux") | |
137 | (eq_attr "cpu" "power6")) | |
138 | "LSX_power6") | |
139 | ||
140 | (define_insn_reservation "power6-load-ext-update" 4 ; fx | |
141 | (and (eq_attr "type" "load_ext_u") | |
142 | (eq_attr "cpu" "power6")) | |
143 | "LSX_power6") | |
144 | ||
145 | (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx | |
146 | (and (eq_attr "type" "load_ext_ux") | |
147 | (eq_attr "cpu" "power6")) | |
148 | "LSX_power6") | |
149 | ||
150 | (define_insn_reservation "power6-fpload" 1 | |
151 | (and (eq_attr "type" "fpload") | |
152 | (eq_attr "cpu" "power6")) | |
153 | "LSU_power6") | |
154 | ||
155 | (define_insn_reservation "power6-fpload-update" 1 | |
156 | (and (eq_attr "type" "fpload_u,fpload_ux") | |
157 | (eq_attr "cpu" "power6")) | |
158 | "LSX_power6") | |
159 | ||
160 | (define_insn_reservation "power6-store" 14 | |
161 | (and (eq_attr "type" "store") | |
162 | (eq_attr "cpu" "power6")) | |
163 | "LSU_power6") | |
164 | ||
165 | (define_insn_reservation "power6-store-update" 14 | |
166 | (and (eq_attr "type" "store_u") | |
167 | (eq_attr "cpu" "power6")) | |
168 | "LSX_power6") | |
169 | ||
170 | (define_insn_reservation "power6-store-update-indexed" 14 | |
171 | (and (eq_attr "type" "store_ux") | |
172 | (eq_attr "cpu" "power6")) | |
173 | "LX2_power6") | |
174 | ||
175 | (define_insn_reservation "power6-fpstore" 14 | |
176 | (and (eq_attr "type" "fpstore") | |
177 | (eq_attr "cpu" "power6")) | |
178 | "LSF_power6") | |
179 | ||
180 | (define_insn_reservation "power6-fpstore-update" 14 | |
181 | (and (eq_attr "type" "fpstore_u,fpstore_ux") | |
182 | (eq_attr "cpu" "power6")) | |
183 | "XLF_power6") | |
184 | ||
185 | (define_insn_reservation "power6-larx" 3 | |
186 | (and (eq_attr "type" "load_l") | |
187 | (eq_attr "cpu" "power6")) | |
188 | "LS2_power6") | |
189 | ||
190 | (define_insn_reservation "power6-stcx" 10 ; best case | |
191 | (and (eq_attr "type" "store_c") | |
192 | (eq_attr "cpu" "power6")) | |
193 | "LSX_power6") | |
194 | ||
195 | (define_insn_reservation "power6-sync" 11 ; N/A | |
196 | (and (eq_attr "type" "sync") | |
197 | (eq_attr "cpu" "power6")) | |
198 | "LSU_power6") | |
199 | ||
200 | (define_insn_reservation "power6-integer" 1 | |
201 | (and (eq_attr "type" "integer") | |
202 | (eq_attr "cpu" "power6")) | |
203 | "FXU_power6") | |
204 | ||
205 | (define_insn_reservation "power6-exts" 1 | |
206 | (and (eq_attr "type" "exts") | |
207 | (eq_attr "cpu" "power6")) | |
208 | "FXU_power6") | |
209 | ||
210 | (define_insn_reservation "power6-shift" 1 | |
211 | (and (eq_attr "type" "shift") | |
212 | (eq_attr "cpu" "power6")) | |
213 | "FXU_power6") | |
214 | ||
215 | (define_insn_reservation "power6-insert" 1 | |
216 | (and (eq_attr "type" "insert_word") | |
217 | (eq_attr "cpu" "power6")) | |
218 | "FX2_power6") | |
219 | ||
220 | (define_insn_reservation "power6-insert-dword" 1 | |
221 | (and (eq_attr "type" "insert_dword") | |
222 | (eq_attr "cpu" "power6")) | |
223 | "FX2_power6") | |
224 | ||
225 | ; define the bypass for the case where the value written | |
226 | ; by a fixed point op is used as the source value on a | |
227 | ; store. | |
228 | (define_bypass 1 "power6-integer,\ | |
229 | power6-exts,\ | |
230 | power6-shift,\ | |
231 | power6-insert,\ | |
232 | power6-insert-dword" | |
233 | "power6-store,\ | |
234 | power6-store-update,\ | |
235 | power6-store-update-indexed,\ | |
236 | power6-fpstore,\ | |
237 | power6-fpstore-update" | |
238 | "store_data_bypass_p") | |
239 | ||
240 | (define_insn_reservation "power6-cntlz" 2 | |
241 | (and (eq_attr "type" "cntlz") | |
242 | (eq_attr "cpu" "power6")) | |
243 | "FXU_power6") | |
244 | ||
245 | (define_bypass 1 "power6-cntlz" | |
246 | "power6-store,\ | |
247 | power6-store-update,\ | |
248 | power6-store-update-indexed,\ | |
249 | power6-fpstore,\ | |
250 | power6-fpstore-update" | |
251 | "store_data_bypass_p") | |
252 | ||
253 | (define_insn_reservation "power6-var-rotate" 4 | |
254 | (and (eq_attr "type" "var_shift_rotate") | |
255 | (eq_attr "cpu" "power6")) | |
256 | "FXU_power6") | |
257 | ||
258 | (define_insn_reservation "power6-trap" 1 ; N/A | |
259 | (and (eq_attr "type" "trap") | |
260 | (eq_attr "cpu" "power6")) | |
261 | "BRX_power6") | |
262 | ||
263 | (define_insn_reservation "power6-two" 1 | |
264 | (and (eq_attr "type" "two") | |
265 | (eq_attr "cpu" "power6")) | |
266 | "(iu1_power6,iu1_power6)\ | |
267 | |(iu1_power6+iu2_power6,nothing)\ | |
268 | |(iu1_power6,iu2_power6)\ | |
269 | |(iu2_power6,iu1_power6)\ | |
270 | |(iu2_power6,iu2_power6)") | |
271 | ||
272 | (define_insn_reservation "power6-three" 1 | |
273 | (and (eq_attr "type" "three") | |
274 | (eq_attr "cpu" "power6")) | |
275 | "(iu1_power6,iu1_power6,iu1_power6)\ | |
276 | |(iu1_power6,iu1_power6,iu2_power6)\ | |
277 | |(iu1_power6,iu2_power6,iu1_power6)\ | |
278 | |(iu1_power6,iu2_power6,iu2_power6)\ | |
279 | |(iu2_power6,iu1_power6,iu1_power6)\ | |
280 | |(iu2_power6,iu1_power6,iu2_power6)\ | |
281 | |(iu2_power6,iu2_power6,iu1_power6)\ | |
282 | |(iu2_power6,iu2_power6,iu2_power6)\ | |
283 | |(iu1_power6+iu2_power6,iu1_power6)\ | |
284 | |(iu1_power6+iu2_power6,iu2_power6)\ | |
285 | |(iu1_power6,iu1_power6+iu2_power6)\ | |
286 | |(iu2_power6,iu1_power6+iu2_power6)") | |
287 | ||
288 | (define_insn_reservation "power6-cmp" 1 | |
289 | (and (eq_attr "type" "cmp") | |
290 | (eq_attr "cpu" "power6")) | |
291 | "FXU_power6") | |
292 | ||
293 | (define_insn_reservation "power6-compare" 1 | |
294 | (and (eq_attr "type" "compare") | |
295 | (eq_attr "cpu" "power6")) | |
296 | "FXU_power6") | |
297 | ||
298 | (define_insn_reservation "power6-fast-compare" 1 | |
299 | (and (eq_attr "type" "fast_compare") | |
300 | (eq_attr "cpu" "power6")) | |
301 | "FXU_power6") | |
302 | ||
303 | ; define the bypass for the case where the value written | |
304 | ; by a fixed point rec form op is used as the source value | |
305 | ; on a store. | |
306 | (define_bypass 1 "power6-compare,\ | |
307 | power6-fast-compare" | |
308 | "power6-store,\ | |
309 | power6-store-update,\ | |
310 | power6-store-update-indexed,\ | |
311 | power6-fpstore,\ | |
312 | power6-fpstore-update" | |
313 | "store_data_bypass_p") | |
314 | ||
315 | (define_insn_reservation "power6-delayed-compare" 2 ; N/A | |
316 | (and (eq_attr "type" "delayed_compare") | |
317 | (eq_attr "cpu" "power6")) | |
318 | "FXU_power6") | |
319 | ||
320 | (define_insn_reservation "power6-var-delayed-compare" 4 | |
321 | (and (eq_attr "type" "var_delayed_compare") | |
322 | (eq_attr "cpu" "power6")) | |
323 | "FXU_power6") | |
324 | ||
325 | (define_insn_reservation "power6-lmul-cmp" 16 | |
326 | (and (eq_attr "type" "lmul_compare") | |
327 | (eq_attr "cpu" "power6")) | |
328 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
329 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
330 | ||
331 | (define_insn_reservation "power6-imul-cmp" 16 | |
332 | (and (eq_attr "type" "imul_compare") | |
333 | (eq_attr "cpu" "power6")) | |
334 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
335 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
336 | ||
337 | (define_insn_reservation "power6-lmul" 16 | |
338 | (and (eq_attr "type" "lmul") | |
339 | (eq_attr "cpu" "power6")) | |
340 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
341 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
342 | ||
343 | (define_insn_reservation "power6-imul" 16 | |
344 | (and (eq_attr "type" "imul") | |
345 | (eq_attr "cpu" "power6")) | |
346 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
347 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
348 | ||
349 | (define_insn_reservation "power6-imul3" 16 | |
350 | (and (eq_attr "type" "imul2,imul3") | |
351 | (eq_attr "cpu" "power6")) | |
352 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
353 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
354 | ||
355 | (define_bypass 9 "power6-imul,\ | |
356 | power6-lmul,\ | |
357 | power6-imul-cmp,\ | |
358 | power6-lmul-cmp,\ | |
359 | power6-imul3" | |
360 | "power6-store,\ | |
361 | power6-store-update,\ | |
362 | power6-store-update-indexed,\ | |
363 | power6-fpstore,\ | |
364 | power6-fpstore-update" | |
365 | "store_data_bypass_p") | |
366 | ||
367 | (define_insn_reservation "power6-idiv" 44 | |
368 | (and (eq_attr "type" "idiv") | |
369 | (eq_attr "cpu" "power6")) | |
370 | "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\ | |
371 | |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)"); | |
372 | ||
373 | ; The latency for this bypass is yet to be defined | |
374 | ;(define_bypass ? "power6-idiv" | |
375 | ; "power6-store,\ | |
376 | ; power6-store-update,\ | |
377 | ; power6-store-update-indexed,\ | |
378 | ; power6-fpstore,\ | |
379 | ; power6-fpstore-update" | |
380 | ; "store_data_bypass_p") | |
381 | ||
382 | (define_insn_reservation "power6-ldiv" 56 | |
383 | (and (eq_attr "type" "ldiv") | |
384 | (eq_attr "cpu" "power6")) | |
385 | "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\ | |
386 | |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)"); | |
387 | ||
388 | ; The latency for this bypass is yet to be defined | |
389 | ;(define_bypass ? "power6-ldiv" | |
390 | ; "power6-store,\ | |
391 | ; power6-store-update,\ | |
392 | ; power6-store-update-indexed,\ | |
393 | ; power6-fpstore,\ | |
394 | ; power6-fpstore-update" | |
395 | ; "store_data_bypass_p") | |
396 | ||
397 | (define_insn_reservation "power6-mtjmpr" 2 | |
398 | (and (eq_attr "type" "mtjmpr,mfjmpr") | |
399 | (eq_attr "cpu" "power6")) | |
400 | "BX2_power6") | |
401 | ||
402 | (define_bypass 5 "power6-mtjmpr" "power6-branch") | |
403 | ||
404 | (define_insn_reservation "power6-branch" 2 | |
405 | (and (eq_attr "type" "jmpreg,branch") | |
406 | (eq_attr "cpu" "power6")) | |
407 | "BRU_power6") | |
408 | ||
409 | (define_bypass 5 "power6-branch" "power6-mtjmpr") | |
410 | ||
411 | (define_insn_reservation "power6-crlogical" 3 | |
412 | (and (eq_attr "type" "cr_logical") | |
413 | (eq_attr "cpu" "power6")) | |
414 | "BRU_power6") | |
415 | ||
416 | (define_bypass 3 "power6-crlogical" "power6-branch") | |
417 | ||
418 | (define_insn_reservation "power6-delayedcr" 3 | |
419 | (and (eq_attr "type" "delayed_cr") | |
420 | (eq_attr "cpu" "power6")) | |
421 | "BRU_power6") | |
422 | ||
423 | (define_insn_reservation "power6-mfcr" 6 ; N/A | |
424 | (and (eq_attr "type" "mfcr") | |
425 | (eq_attr "cpu" "power6")) | |
426 | "BX2_power6") | |
427 | ||
428 | ; mfcrf (1 field) | |
429 | (define_insn_reservation "power6-mfcrf" 3 ; N/A | |
430 | (and (eq_attr "type" "mfcrf") | |
431 | (eq_attr "cpu" "power6")) | |
432 | "BX2_power6") ; | |
433 | ||
434 | ; mtcrf (1 field) | |
435 | (define_insn_reservation "power6-mtcr" 4 ; N/A | |
436 | (and (eq_attr "type" "mtcr") | |
437 | (eq_attr "cpu" "power6")) | |
438 | "BX2_power6") | |
439 | ||
440 | (define_bypass 9 "power6-mtcr" "power6-branch") | |
441 | ||
442 | (define_insn_reservation "power6-fp" 6 | |
443 | (and (eq_attr "type" "fp,dmul") | |
444 | (eq_attr "cpu" "power6")) | |
445 | "FPU_power6") | |
446 | ||
447 | ; Any fp instruction that updates a CR has a latency | |
448 | ; of 6 to a dependent branch | |
449 | (define_bypass 6 "power6-fp" "power6-branch") | |
450 | ||
451 | (define_bypass 1 "power6-fp" | |
452 | "power6-fpstore,power6-fpstore-update" | |
453 | "store_data_bypass_p") | |
454 | ||
455 | (define_insn_reservation "power6-fpcompare" 8 | |
456 | (and (eq_attr "type" "fpcompare") | |
457 | (eq_attr "cpu" "power6")) | |
458 | "FPU_power6") | |
459 | ||
460 | (define_bypass 12 "power6-fpcompare" | |
461 | "power6-branch,power6-crlogical") | |
462 | ||
463 | (define_insn_reservation "power6-sdiv" 26 | |
464 | (and (eq_attr "type" "sdiv") | |
465 | (eq_attr "cpu" "power6")) | |
466 | "FPU_power6") | |
467 | ||
468 | (define_insn_reservation "power6-ddiv" 32 | |
469 | (and (eq_attr "type" "ddiv") | |
470 | (eq_attr "cpu" "power6")) | |
471 | "FPU_power6") | |
472 | ||
473 | (define_insn_reservation "power6-sqrt" 30 | |
474 | (and (eq_attr "type" "ssqrt") | |
475 | (eq_attr "cpu" "power6")) | |
476 | "FPU_power6") | |
477 | ||
478 | (define_insn_reservation "power6-dsqrt" 42 | |
479 | (and (eq_attr "type" "dsqrt") | |
480 | (eq_attr "cpu" "power6")) | |
481 | "FPU_power6") | |
482 | ||
483 | (define_insn_reservation "power6-isync" 2 ; N/A | |
484 | (and (eq_attr "type" "isync") | |
485 | (eq_attr "cpu" "power6")) | |
486 | "FXU_power6") | |
487 | ||
488 | (define_insn_reservation "power6-vecload" 1 | |
489 | (and (eq_attr "type" "vecload") | |
490 | (eq_attr "cpu" "power6")) | |
491 | "LSU_power6") | |
492 | ||
493 | (define_insn_reservation "power6-vecstore" 1 | |
494 | (and (eq_attr "type" "vecstore") | |
495 | (eq_attr "cpu" "power6")) | |
496 | "LSF_power6") | |
497 | ||
498 | (define_insn_reservation "power6-vecsimple" 3 | |
499 | (and (eq_attr "type" "vecsimple") | |
500 | (eq_attr "cpu" "power6")) | |
501 | "FPU_power6") | |
502 | ||
503 | (define_bypass 6 "power6-vecsimple" "power6-veccomplex,\ | |
504 | power6-vecperm") | |
505 | ||
506 | (define_bypass 5 "power6-vecsimple" "power6-vecfloat") | |
507 | ||
508 | (define_bypass 4 "power6-vecsimple" "power6-vecstore" ) | |
509 | ||
510 | (define_insn_reservation "power6-veccmp" 1 | |
511 | (and (eq_attr "type" "veccmp") | |
512 | (eq_attr "cpu" "power6")) | |
513 | "FPU_power6") | |
514 | ||
515 | (define_bypass 10 "power6-veccmp" "power6-branch") | |
516 | ||
517 | (define_insn_reservation "power6-vecfloat" 7 | |
518 | (and (eq_attr "type" "vecfloat") | |
519 | (eq_attr "cpu" "power6")) | |
520 | "FPU_power6") | |
521 | ||
522 | (define_bypass 10 "power6-vecfloat" "power6-vecsimple") | |
523 | ||
524 | (define_bypass 11 "power6-vecfloat" "power6-veccomplex,\ | |
525 | power6-vecperm") | |
526 | ||
527 | (define_bypass 9 "power6-vecfloat" "power6-vecstore" ) | |
528 | ||
529 | (define_insn_reservation "power6-veccomplex" 7 | |
530 | (and (eq_attr "type" "vecsimple") | |
531 | (eq_attr "cpu" "power6")) | |
532 | "FPU_power6") | |
533 | ||
534 | (define_bypass 10 "power6-veccomplex" "power6-vecsimple,\ | |
535 | power6-vecfloat" ) | |
536 | ||
537 | (define_bypass 9 "power6-veccomplex" "power6-vecperm" ) | |
538 | ||
539 | (define_bypass 8 "power6-veccomplex" "power6-vecstore" ) | |
540 | ||
541 | (define_insn_reservation "power6-vecperm" 4 | |
542 | (and (eq_attr "type" "vecperm") | |
543 | (eq_attr "cpu" "power6")) | |
544 | "FPU_power6") | |
545 | ||
546 | (define_bypass 7 "power6-vecperm" "power6-vecsimple,\ | |
547 | power6-vecfloat" ) | |
548 | ||
549 | (define_bypass 6 "power6-vecperm" "power6-veccomplex" ) | |
550 | ||
551 | (define_bypass 5 "power6-vecperm" "power6-vecstore" ) | |
552 | ||
553 | (define_insn_reservation "power6-mftgpr" 8 | |
554 | (and (eq_attr "type" "mftgpr") | |
555 | (eq_attr "cpu" "power6")) | |
556 | "X2F_power6") | |
557 | ||
558 | (define_insn_reservation "power6-mffgpr" 14 | |
559 | (and (eq_attr "type" "mffgpr") | |
560 | (eq_attr "cpu" "power6")) | |
561 | "LX2_power6") | |
562 | ||
563 | (define_bypass 4 "power6-mftgpr" "power6-imul,\ | |
564 | power6-lmul,\ | |
565 | power6-imul-cmp,\ | |
566 | power6-lmul-cmp,\ | |
567 | power6-imul3,\ | |
568 | power6-idiv,\ | |
569 | power6-ldiv" ) |