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44cd321e | 1 | ;; Scheduling description for IBM POWER6 processor. |
23a5b65a | 2 | ;; Copyright (C) 2006-2014 Free Software Foundation, Inc. |
44cd321e PS |
3 | ;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com) |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | ;; by the Free Software Foundation; either version 3, or (at your |
44cd321e PS |
10 | ;; option) any later version. |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
44cd321e PS |
20 | |
21 | ;; Sources: | |
22 | ||
23 | ;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine | |
24 | ;; (2 engines per chip). The chip can issue up to 5 internal ops | |
25 | ;; per cycle. | |
26 | ||
27 | (define_automaton "power6iu,power6lsu,power6fpu,power6bu") | |
28 | ||
29 | (define_cpu_unit "iu1_power6,iu2_power6" "power6iu") | |
30 | (define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu") | |
31 | (define_cpu_unit "bpu_power6" "power6bu") | |
32 | (define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu") | |
33 | ||
34 | (define_reservation "LS2_power6" | |
35 | "lsu1_power6+lsu2_power6") | |
36 | ||
37 | (define_reservation "FPU_power6" | |
38 | "fpu1_power6|fpu2_power6") | |
39 | ||
40 | (define_reservation "BRU_power6" | |
41 | "bpu_power6") | |
42 | ||
43 | (define_reservation "LSU_power6" | |
44 | "lsu1_power6|lsu2_power6") | |
45 | ||
46 | (define_reservation "LSF_power6" | |
47 | "(lsu1_power6+fpu1_power6)\ | |
48 | |(lsu1_power6+fpu2_power6)\ | |
49 | |(lsu2_power6+fpu1_power6)\ | |
50 | |(lsu2_power6+fpu2_power6)") | |
51 | ||
52 | (define_reservation "LX2_power6" | |
53 | "(iu1_power6+iu2_power6+lsu1_power6)\ | |
54 | |(iu1_power6+iu2_power6+lsu2_power6)") | |
55 | ||
56 | (define_reservation "FX2_power6" | |
57 | "iu1_power6+iu2_power6") | |
58 | ||
59 | (define_reservation "X2F_power6" | |
60 | "(iu1_power6+iu2_power6+fpu1_power6)\ | |
61 | |(iu1_power6+iu2_power6+fpu2_power6)") | |
62 | ||
63 | (define_reservation "BX2_power6" | |
64 | "iu1_power6+iu2_power6+bpu_power6") | |
65 | ||
66 | (define_reservation "LSX_power6" | |
67 | "(iu1_power6+lsu1_power6)\ | |
68 | |(iu1_power6+lsu2_power6)\ | |
69 | |(iu2_power6+lsu1_power6)\ | |
70 | |(iu2_power6+lsu2_power6)") | |
71 | ||
72 | (define_reservation "FXU_power6" | |
73 | "iu1_power6|iu2_power6") | |
74 | ||
75 | (define_reservation "XLF_power6" | |
76 | "(iu1_power6+lsu1_power6+fpu1_power6)\ | |
77 | |(iu1_power6+lsu1_power6+fpu2_power6)\ | |
78 | |(iu1_power6+lsu2_power6+fpu1_power6)\ | |
79 | |(iu1_power6+lsu2_power6+fpu2_power6)\ | |
80 | |(iu2_power6+lsu1_power6+fpu1_power6)\ | |
81 | |(iu2_power6+lsu1_power6+fpu2_power6)\ | |
82 | |(iu2_power6+lsu2_power6+fpu1_power6)\ | |
83 | |(iu2_power6+lsu2_power6+fpu2_power6)") | |
84 | ||
85 | (define_reservation "BRX_power6" | |
86 | "(bpu_power6+iu1_power6)\ | |
87 | |(bpu_power6+iu2_power6)") | |
88 | ||
89 | ; Load/store | |
90 | ||
91 | ; The default for a value written by a fixed point load | |
92 | ; that is read/written by a subsequent fixed point op. | |
93 | (define_insn_reservation "power6-load" 2 ; fx | |
94 | (and (eq_attr "type" "load") | |
d839f53b SB |
95 | (eq_attr "sign_extend" "no") |
96 | (eq_attr "update" "no") | |
44cd321e PS |
97 | (eq_attr "cpu" "power6")) |
98 | "LSU_power6") | |
99 | ||
100 | ; define the bypass for the case where the value written | |
101 | ; by a fixed point load is used as the source value on | |
102 | ; a store. | |
103 | (define_bypass 1 "power6-load,\ | |
104 | power6-load-update,\ | |
105 | power6-load-update-indexed" | |
106 | "power6-store,\ | |
107 | power6-store-update,\ | |
108 | power6-store-update-indexed,\ | |
109 | power6-fpstore,\ | |
110 | power6-fpstore-update" | |
111 | "store_data_bypass_p") | |
112 | ||
113 | (define_insn_reservation "power6-load-ext" 4 ; fx | |
d839f53b SB |
114 | (and (eq_attr "type" "load") |
115 | (eq_attr "sign_extend" "yes") | |
116 | (eq_attr "update" "no") | |
44cd321e PS |
117 | (eq_attr "cpu" "power6")) |
118 | "LSU_power6") | |
119 | ||
120 | ; define the bypass for the case where the value written | |
121 | ; by a fixed point load ext is used as the source value on | |
122 | ; a store. | |
123 | (define_bypass 1 "power6-load-ext,\ | |
124 | power6-load-ext-update,\ | |
125 | power6-load-ext-update-indexed" | |
126 | "power6-store,\ | |
127 | power6-store-update,\ | |
128 | power6-store-update-indexed,\ | |
129 | power6-fpstore,\ | |
130 | power6-fpstore-update" | |
131 | "store_data_bypass_p") | |
132 | ||
133 | (define_insn_reservation "power6-load-update" 2 ; fx | |
d839f53b SB |
134 | (and (eq_attr "type" "load") |
135 | (eq_attr "sign_extend" "no") | |
136 | (eq_attr "update" "yes") | |
137 | (eq_attr "indexed" "no") | |
44cd321e PS |
138 | (eq_attr "cpu" "power6")) |
139 | "LSX_power6") | |
140 | ||
141 | (define_insn_reservation "power6-load-update-indexed" 2 ; fx | |
d839f53b SB |
142 | (and (eq_attr "type" "load") |
143 | (eq_attr "sign_extend" "no") | |
144 | (eq_attr "update" "yes") | |
145 | (eq_attr "indexed" "yes") | |
44cd321e PS |
146 | (eq_attr "cpu" "power6")) |
147 | "LSX_power6") | |
148 | ||
149 | (define_insn_reservation "power6-load-ext-update" 4 ; fx | |
d839f53b SB |
150 | (and (eq_attr "type" "load") |
151 | (eq_attr "sign_extend" "yes") | |
152 | (eq_attr "update" "yes") | |
153 | (eq_attr "indexed" "no") | |
44cd321e PS |
154 | (eq_attr "cpu" "power6")) |
155 | "LSX_power6") | |
156 | ||
157 | (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx | |
d839f53b SB |
158 | (and (eq_attr "type" "load") |
159 | (eq_attr "sign_extend" "yes") | |
160 | (eq_attr "update" "yes") | |
161 | (eq_attr "indexed" "yes") | |
44cd321e PS |
162 | (eq_attr "cpu" "power6")) |
163 | "LSX_power6") | |
164 | ||
165 | (define_insn_reservation "power6-fpload" 1 | |
166 | (and (eq_attr "type" "fpload") | |
d839f53b | 167 | (eq_attr "update" "no") |
44cd321e PS |
168 | (eq_attr "cpu" "power6")) |
169 | "LSU_power6") | |
170 | ||
171 | (define_insn_reservation "power6-fpload-update" 1 | |
d839f53b SB |
172 | (and (eq_attr "type" "fpload") |
173 | (eq_attr "update" "yes") | |
44cd321e PS |
174 | (eq_attr "cpu" "power6")) |
175 | "LSX_power6") | |
176 | ||
177 | (define_insn_reservation "power6-store" 14 | |
178 | (and (eq_attr "type" "store") | |
d839f53b | 179 | (eq_attr "update" "no") |
44cd321e PS |
180 | (eq_attr "cpu" "power6")) |
181 | "LSU_power6") | |
182 | ||
183 | (define_insn_reservation "power6-store-update" 14 | |
d839f53b SB |
184 | (and (eq_attr "type" "store") |
185 | (eq_attr "update" "yes") | |
186 | (eq_attr "indexed" "no") | |
44cd321e PS |
187 | (eq_attr "cpu" "power6")) |
188 | "LSX_power6") | |
189 | ||
190 | (define_insn_reservation "power6-store-update-indexed" 14 | |
d839f53b SB |
191 | (and (eq_attr "type" "store") |
192 | (eq_attr "update" "yes") | |
193 | (eq_attr "indexed" "yes") | |
44cd321e PS |
194 | (eq_attr "cpu" "power6")) |
195 | "LX2_power6") | |
196 | ||
197 | (define_insn_reservation "power6-fpstore" 14 | |
198 | (and (eq_attr "type" "fpstore") | |
d839f53b | 199 | (eq_attr "update" "no") |
44cd321e PS |
200 | (eq_attr "cpu" "power6")) |
201 | "LSF_power6") | |
202 | ||
203 | (define_insn_reservation "power6-fpstore-update" 14 | |
d839f53b SB |
204 | (and (eq_attr "type" "fpstore") |
205 | (eq_attr "update" "yes") | |
44cd321e PS |
206 | (eq_attr "cpu" "power6")) |
207 | "XLF_power6") | |
208 | ||
209 | (define_insn_reservation "power6-larx" 3 | |
210 | (and (eq_attr "type" "load_l") | |
211 | (eq_attr "cpu" "power6")) | |
212 | "LS2_power6") | |
213 | ||
214 | (define_insn_reservation "power6-stcx" 10 ; best case | |
215 | (and (eq_attr "type" "store_c") | |
216 | (eq_attr "cpu" "power6")) | |
217 | "LSX_power6") | |
218 | ||
219 | (define_insn_reservation "power6-sync" 11 ; N/A | |
220 | (and (eq_attr "type" "sync") | |
221 | (eq_attr "cpu" "power6")) | |
222 | "LSU_power6") | |
223 | ||
224 | (define_insn_reservation "power6-integer" 1 | |
225 | (and (eq_attr "type" "integer") | |
226 | (eq_attr "cpu" "power6")) | |
227 | "FXU_power6") | |
228 | ||
47f67e51 PB |
229 | (define_insn_reservation "power6-isel" 1 |
230 | (and (eq_attr "type" "isel") | |
231 | (eq_attr "cpu" "power6")) | |
232 | "FXU_power6") | |
233 | ||
44cd321e PS |
234 | (define_insn_reservation "power6-exts" 1 |
235 | (and (eq_attr "type" "exts") | |
236 | (eq_attr "cpu" "power6")) | |
237 | "FXU_power6") | |
238 | ||
239 | (define_insn_reservation "power6-shift" 1 | |
240 | (and (eq_attr "type" "shift") | |
241 | (eq_attr "cpu" "power6")) | |
242 | "FXU_power6") | |
243 | ||
42533d77 EW |
244 | (define_insn_reservation "power6-popcnt" 1 |
245 | (and (eq_attr "type" "popcnt") | |
246 | (eq_attr "cpu" "power6")) | |
247 | "FXU_power6") | |
248 | ||
44cd321e PS |
249 | (define_insn_reservation "power6-insert" 1 |
250 | (and (eq_attr "type" "insert_word") | |
251 | (eq_attr "cpu" "power6")) | |
252 | "FX2_power6") | |
253 | ||
254 | (define_insn_reservation "power6-insert-dword" 1 | |
255 | (and (eq_attr "type" "insert_dword") | |
256 | (eq_attr "cpu" "power6")) | |
257 | "FX2_power6") | |
258 | ||
259 | ; define the bypass for the case where the value written | |
260 | ; by a fixed point op is used as the source value on a | |
261 | ; store. | |
262 | (define_bypass 1 "power6-integer,\ | |
263 | power6-exts,\ | |
264 | power6-shift,\ | |
265 | power6-insert,\ | |
266 | power6-insert-dword" | |
267 | "power6-store,\ | |
268 | power6-store-update,\ | |
269 | power6-store-update-indexed,\ | |
270 | power6-fpstore,\ | |
271 | power6-fpstore-update" | |
272 | "store_data_bypass_p") | |
273 | ||
274 | (define_insn_reservation "power6-cntlz" 2 | |
275 | (and (eq_attr "type" "cntlz") | |
276 | (eq_attr "cpu" "power6")) | |
277 | "FXU_power6") | |
278 | ||
279 | (define_bypass 1 "power6-cntlz" | |
280 | "power6-store,\ | |
281 | power6-store-update,\ | |
282 | power6-store-update-indexed,\ | |
283 | power6-fpstore,\ | |
284 | power6-fpstore-update" | |
285 | "store_data_bypass_p") | |
286 | ||
287 | (define_insn_reservation "power6-var-rotate" 4 | |
288 | (and (eq_attr "type" "var_shift_rotate") | |
289 | (eq_attr "cpu" "power6")) | |
290 | "FXU_power6") | |
291 | ||
292 | (define_insn_reservation "power6-trap" 1 ; N/A | |
293 | (and (eq_attr "type" "trap") | |
294 | (eq_attr "cpu" "power6")) | |
295 | "BRX_power6") | |
296 | ||
297 | (define_insn_reservation "power6-two" 1 | |
298 | (and (eq_attr "type" "two") | |
299 | (eq_attr "cpu" "power6")) | |
300 | "(iu1_power6,iu1_power6)\ | |
301 | |(iu1_power6+iu2_power6,nothing)\ | |
302 | |(iu1_power6,iu2_power6)\ | |
303 | |(iu2_power6,iu1_power6)\ | |
304 | |(iu2_power6,iu2_power6)") | |
305 | ||
306 | (define_insn_reservation "power6-three" 1 | |
307 | (and (eq_attr "type" "three") | |
308 | (eq_attr "cpu" "power6")) | |
309 | "(iu1_power6,iu1_power6,iu1_power6)\ | |
310 | |(iu1_power6,iu1_power6,iu2_power6)\ | |
311 | |(iu1_power6,iu2_power6,iu1_power6)\ | |
312 | |(iu1_power6,iu2_power6,iu2_power6)\ | |
313 | |(iu2_power6,iu1_power6,iu1_power6)\ | |
314 | |(iu2_power6,iu1_power6,iu2_power6)\ | |
315 | |(iu2_power6,iu2_power6,iu1_power6)\ | |
316 | |(iu2_power6,iu2_power6,iu2_power6)\ | |
317 | |(iu1_power6+iu2_power6,iu1_power6)\ | |
318 | |(iu1_power6+iu2_power6,iu2_power6)\ | |
319 | |(iu1_power6,iu1_power6+iu2_power6)\ | |
320 | |(iu2_power6,iu1_power6+iu2_power6)") | |
321 | ||
322 | (define_insn_reservation "power6-cmp" 1 | |
323 | (and (eq_attr "type" "cmp") | |
324 | (eq_attr "cpu" "power6")) | |
325 | "FXU_power6") | |
326 | ||
327 | (define_insn_reservation "power6-compare" 1 | |
328 | (and (eq_attr "type" "compare") | |
329 | (eq_attr "cpu" "power6")) | |
330 | "FXU_power6") | |
331 | ||
332 | (define_insn_reservation "power6-fast-compare" 1 | |
333 | (and (eq_attr "type" "fast_compare") | |
334 | (eq_attr "cpu" "power6")) | |
335 | "FXU_power6") | |
336 | ||
337 | ; define the bypass for the case where the value written | |
338 | ; by a fixed point rec form op is used as the source value | |
339 | ; on a store. | |
340 | (define_bypass 1 "power6-compare,\ | |
341 | power6-fast-compare" | |
342 | "power6-store,\ | |
343 | power6-store-update,\ | |
344 | power6-store-update-indexed,\ | |
345 | power6-fpstore,\ | |
346 | power6-fpstore-update" | |
347 | "store_data_bypass_p") | |
348 | ||
349 | (define_insn_reservation "power6-delayed-compare" 2 ; N/A | |
350 | (and (eq_attr "type" "delayed_compare") | |
351 | (eq_attr "cpu" "power6")) | |
352 | "FXU_power6") | |
353 | ||
354 | (define_insn_reservation "power6-var-delayed-compare" 4 | |
355 | (and (eq_attr "type" "var_delayed_compare") | |
356 | (eq_attr "cpu" "power6")) | |
357 | "FXU_power6") | |
358 | ||
359 | (define_insn_reservation "power6-lmul-cmp" 16 | |
e0528ed9 SB |
360 | (and (eq_attr "type" "mul") |
361 | (eq_attr "dot" "yes") | |
362 | (eq_attr "size" "64") | |
44cd321e PS |
363 | (eq_attr "cpu" "power6")) |
364 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
365 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
366 | ||
367 | (define_insn_reservation "power6-imul-cmp" 16 | |
e0528ed9 SB |
368 | (and (eq_attr "type" "mul") |
369 | (eq_attr "dot" "yes") | |
370 | (eq_attr "size" "32") | |
44cd321e PS |
371 | (eq_attr "cpu" "power6")) |
372 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
373 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
374 | ||
375 | (define_insn_reservation "power6-lmul" 16 | |
e0528ed9 SB |
376 | (and (eq_attr "type" "mul") |
377 | (eq_attr "dot" "no") | |
378 | (eq_attr "size" "64") | |
44cd321e PS |
379 | (eq_attr "cpu" "power6")) |
380 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
381 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
382 | ||
383 | (define_insn_reservation "power6-imul" 16 | |
e0528ed9 SB |
384 | (and (eq_attr "type" "mul") |
385 | (eq_attr "dot" "no") | |
386 | (eq_attr "size" "32") | |
44cd321e PS |
387 | (eq_attr "cpu" "power6")) |
388 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
389 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
390 | ||
391 | (define_insn_reservation "power6-imul3" 16 | |
e0528ed9 SB |
392 | (and (eq_attr "type" "mul") |
393 | (eq_attr "size" "8,16") | |
44cd321e PS |
394 | (eq_attr "cpu" "power6")) |
395 | "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ | |
396 | |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); | |
397 | ||
398 | (define_bypass 9 "power6-imul,\ | |
399 | power6-lmul,\ | |
400 | power6-imul-cmp,\ | |
401 | power6-lmul-cmp,\ | |
402 | power6-imul3" | |
403 | "power6-store,\ | |
404 | power6-store-update,\ | |
405 | power6-store-update-indexed,\ | |
406 | power6-fpstore,\ | |
407 | power6-fpstore-update" | |
408 | "store_data_bypass_p") | |
409 | ||
410 | (define_insn_reservation "power6-idiv" 44 | |
411 | (and (eq_attr "type" "idiv") | |
412 | (eq_attr "cpu" "power6")) | |
413 | "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\ | |
414 | |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)"); | |
415 | ||
416 | ; The latency for this bypass is yet to be defined | |
417 | ;(define_bypass ? "power6-idiv" | |
418 | ; "power6-store,\ | |
419 | ; power6-store-update,\ | |
420 | ; power6-store-update-indexed,\ | |
421 | ; power6-fpstore,\ | |
422 | ; power6-fpstore-update" | |
423 | ; "store_data_bypass_p") | |
424 | ||
425 | (define_insn_reservation "power6-ldiv" 56 | |
426 | (and (eq_attr "type" "ldiv") | |
427 | (eq_attr "cpu" "power6")) | |
428 | "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\ | |
429 | |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)"); | |
430 | ||
431 | ; The latency for this bypass is yet to be defined | |
432 | ;(define_bypass ? "power6-ldiv" | |
433 | ; "power6-store,\ | |
434 | ; power6-store-update,\ | |
435 | ; power6-store-update-indexed,\ | |
436 | ; power6-fpstore,\ | |
437 | ; power6-fpstore-update" | |
438 | ; "store_data_bypass_p") | |
439 | ||
440 | (define_insn_reservation "power6-mtjmpr" 2 | |
441 | (and (eq_attr "type" "mtjmpr,mfjmpr") | |
442 | (eq_attr "cpu" "power6")) | |
443 | "BX2_power6") | |
444 | ||
445 | (define_bypass 5 "power6-mtjmpr" "power6-branch") | |
446 | ||
447 | (define_insn_reservation "power6-branch" 2 | |
448 | (and (eq_attr "type" "jmpreg,branch") | |
449 | (eq_attr "cpu" "power6")) | |
450 | "BRU_power6") | |
451 | ||
452 | (define_bypass 5 "power6-branch" "power6-mtjmpr") | |
453 | ||
454 | (define_insn_reservation "power6-crlogical" 3 | |
455 | (and (eq_attr "type" "cr_logical") | |
456 | (eq_attr "cpu" "power6")) | |
457 | "BRU_power6") | |
458 | ||
459 | (define_bypass 3 "power6-crlogical" "power6-branch") | |
460 | ||
461 | (define_insn_reservation "power6-delayedcr" 3 | |
462 | (and (eq_attr "type" "delayed_cr") | |
463 | (eq_attr "cpu" "power6")) | |
464 | "BRU_power6") | |
465 | ||
466 | (define_insn_reservation "power6-mfcr" 6 ; N/A | |
467 | (and (eq_attr "type" "mfcr") | |
468 | (eq_attr "cpu" "power6")) | |
469 | "BX2_power6") | |
470 | ||
471 | ; mfcrf (1 field) | |
472 | (define_insn_reservation "power6-mfcrf" 3 ; N/A | |
473 | (and (eq_attr "type" "mfcrf") | |
474 | (eq_attr "cpu" "power6")) | |
475 | "BX2_power6") ; | |
476 | ||
477 | ; mtcrf (1 field) | |
478 | (define_insn_reservation "power6-mtcr" 4 ; N/A | |
479 | (and (eq_attr "type" "mtcr") | |
480 | (eq_attr "cpu" "power6")) | |
481 | "BX2_power6") | |
482 | ||
483 | (define_bypass 9 "power6-mtcr" "power6-branch") | |
484 | ||
485 | (define_insn_reservation "power6-fp" 6 | |
486 | (and (eq_attr "type" "fp,dmul") | |
487 | (eq_attr "cpu" "power6")) | |
488 | "FPU_power6") | |
489 | ||
490 | ; Any fp instruction that updates a CR has a latency | |
491 | ; of 6 to a dependent branch | |
492 | (define_bypass 6 "power6-fp" "power6-branch") | |
493 | ||
494 | (define_bypass 1 "power6-fp" | |
495 | "power6-fpstore,power6-fpstore-update" | |
496 | "store_data_bypass_p") | |
497 | ||
498 | (define_insn_reservation "power6-fpcompare" 8 | |
499 | (and (eq_attr "type" "fpcompare") | |
500 | (eq_attr "cpu" "power6")) | |
501 | "FPU_power6") | |
502 | ||
503 | (define_bypass 12 "power6-fpcompare" | |
504 | "power6-branch,power6-crlogical") | |
505 | ||
506 | (define_insn_reservation "power6-sdiv" 26 | |
507 | (and (eq_attr "type" "sdiv") | |
508 | (eq_attr "cpu" "power6")) | |
509 | "FPU_power6") | |
510 | ||
511 | (define_insn_reservation "power6-ddiv" 32 | |
512 | (and (eq_attr "type" "ddiv") | |
513 | (eq_attr "cpu" "power6")) | |
514 | "FPU_power6") | |
515 | ||
516 | (define_insn_reservation "power6-sqrt" 30 | |
517 | (and (eq_attr "type" "ssqrt") | |
518 | (eq_attr "cpu" "power6")) | |
519 | "FPU_power6") | |
520 | ||
521 | (define_insn_reservation "power6-dsqrt" 42 | |
522 | (and (eq_attr "type" "dsqrt") | |
523 | (eq_attr "cpu" "power6")) | |
524 | "FPU_power6") | |
525 | ||
526 | (define_insn_reservation "power6-isync" 2 ; N/A | |
527 | (and (eq_attr "type" "isync") | |
528 | (eq_attr "cpu" "power6")) | |
529 | "FXU_power6") | |
530 | ||
531 | (define_insn_reservation "power6-vecload" 1 | |
532 | (and (eq_attr "type" "vecload") | |
533 | (eq_attr "cpu" "power6")) | |
534 | "LSU_power6") | |
535 | ||
536 | (define_insn_reservation "power6-vecstore" 1 | |
537 | (and (eq_attr "type" "vecstore") | |
538 | (eq_attr "cpu" "power6")) | |
539 | "LSF_power6") | |
540 | ||
541 | (define_insn_reservation "power6-vecsimple" 3 | |
542 | (and (eq_attr "type" "vecsimple") | |
543 | (eq_attr "cpu" "power6")) | |
544 | "FPU_power6") | |
545 | ||
546 | (define_bypass 6 "power6-vecsimple" "power6-veccomplex,\ | |
547 | power6-vecperm") | |
548 | ||
549 | (define_bypass 5 "power6-vecsimple" "power6-vecfloat") | |
550 | ||
551 | (define_bypass 4 "power6-vecsimple" "power6-vecstore" ) | |
552 | ||
553 | (define_insn_reservation "power6-veccmp" 1 | |
554 | (and (eq_attr "type" "veccmp") | |
555 | (eq_attr "cpu" "power6")) | |
556 | "FPU_power6") | |
557 | ||
558 | (define_bypass 10 "power6-veccmp" "power6-branch") | |
559 | ||
560 | (define_insn_reservation "power6-vecfloat" 7 | |
561 | (and (eq_attr "type" "vecfloat") | |
562 | (eq_attr "cpu" "power6")) | |
563 | "FPU_power6") | |
564 | ||
565 | (define_bypass 10 "power6-vecfloat" "power6-vecsimple") | |
566 | ||
567 | (define_bypass 11 "power6-vecfloat" "power6-veccomplex,\ | |
568 | power6-vecperm") | |
569 | ||
570 | (define_bypass 9 "power6-vecfloat" "power6-vecstore" ) | |
571 | ||
572 | (define_insn_reservation "power6-veccomplex" 7 | |
573 | (and (eq_attr "type" "vecsimple") | |
574 | (eq_attr "cpu" "power6")) | |
575 | "FPU_power6") | |
576 | ||
577 | (define_bypass 10 "power6-veccomplex" "power6-vecsimple,\ | |
578 | power6-vecfloat" ) | |
579 | ||
580 | (define_bypass 9 "power6-veccomplex" "power6-vecperm" ) | |
581 | ||
582 | (define_bypass 8 "power6-veccomplex" "power6-vecstore" ) | |
583 | ||
584 | (define_insn_reservation "power6-vecperm" 4 | |
585 | (and (eq_attr "type" "vecperm") | |
586 | (eq_attr "cpu" "power6")) | |
587 | "FPU_power6") | |
588 | ||
589 | (define_bypass 7 "power6-vecperm" "power6-vecsimple,\ | |
590 | power6-vecfloat" ) | |
591 | ||
592 | (define_bypass 6 "power6-vecperm" "power6-veccomplex" ) | |
593 | ||
594 | (define_bypass 5 "power6-vecperm" "power6-vecstore" ) | |
595 | ||
596 | (define_insn_reservation "power6-mftgpr" 8 | |
597 | (and (eq_attr "type" "mftgpr") | |
598 | (eq_attr "cpu" "power6")) | |
599 | "X2F_power6") | |
600 | ||
601 | (define_insn_reservation "power6-mffgpr" 14 | |
602 | (and (eq_attr "type" "mffgpr") | |
603 | (eq_attr "cpu" "power6")) | |
604 | "LX2_power6") | |
605 | ||
606 | (define_bypass 4 "power6-mftgpr" "power6-imul,\ | |
607 | power6-lmul,\ | |
608 | power6-imul-cmp,\ | |
609 | power6-lmul-cmp,\ | |
610 | power6-imul3,\ | |
611 | power6-idiv,\ | |
612 | power6-ldiv" ) |