[thirdparty/gcc.git] / gcc / config / rs6000 / power7.md

;; Scheduling description for IBM POWER7 processor.
;; Copyright (C) 2009-2014 Free Software Foundation, Inc.
;;
;; Contributed by Pat Haugen (pthaugen@us.ibm.com).

;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

(define_automaton "power7iu,power7lsu,power7vsu,power7misc")

(define_cpu_unit "iu1_power7,iu2_power7" "power7iu")
(define_cpu_unit "lsu1_power7,lsu2_power7" "power7lsu")
(define_cpu_unit "vsu1_power7,vsu2_power7" "power7vsu")
(define_cpu_unit "bpu_power7,cru_power7" "power7misc")
(define_cpu_unit "du1_power7,du2_power7,du3_power7,du4_power7,du5_power7"
                 "power7misc")


(define_reservation "DU_power7"
		    "du1_power7|du2_power7|du3_power7|du4_power7")

(define_reservation "DU2F_power7"
		    "du1_power7+du2_power7")

(define_reservation "DU4_power7"
		    "du1_power7+du2_power7+du3_power7+du4_power7")

(define_reservation "FXU_power7"
                    "iu1_power7|iu2_power7")

(define_reservation "VSU_power7"
                    "vsu1_power7|vsu2_power7")

(define_reservation "LSU_power7"
                    "lsu1_power7|lsu2_power7")


; Dispatch slots are allocated in order conforming to program order.
(absence_set "du1_power7" "du2_power7,du3_power7,du4_power7,du5_power7")
(absence_set "du2_power7" "du3_power7,du4_power7,du5_power7")
(absence_set "du3_power7" "du4_power7,du5_power7")
(absence_set "du4_power7" "du5_power7")


; LS Unit
(define_insn_reservation "power7-load" 2
  (and (eq_attr "type" "load")
       (eq_attr "sign_extend" "no")
       (eq_attr "update" "no")
       (eq_attr "cpu" "power7"))
  "DU_power7,LSU_power7")

(define_insn_reservation "power7-load-ext" 3
  (and (eq_attr "type" "load")
       (eq_attr "sign_extend" "yes")
       (eq_attr "update" "no")
       (eq_attr "cpu" "power7"))
  "DU2F_power7,LSU_power7,FXU_power7")

(define_insn_reservation "power7-load-update" 2
  (and (eq_attr "type" "load")
       (eq_attr "sign_extend" "no")
       (eq_attr "update" "yes")
       (eq_attr "indexed" "no")
       (eq_attr "cpu" "power7"))
  "DU2F_power7,LSU_power7+FXU_power7")

(define_insn_reservation "power7-load-update-indexed" 3
  (and (eq_attr "type" "load")
       (eq_attr "sign_extend" "no")
       (eq_attr "update" "yes")
       (eq_attr "indexed" "yes")
       (eq_attr "cpu" "power7"))
  "DU4_power7,FXU_power7,LSU_power7+FXU_power7")

(define_insn_reservation "power7-load-ext-update" 4
  (and (eq_attr "type" "load")
       (eq_attr "sign_extend" "yes")
       (eq_attr "update" "yes")
       (eq_attr "indexed" "no")
       (eq_attr "cpu" "power7"))
  "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")

(define_insn_reservation "power7-load-ext-update-indexed" 4
  (and (eq_attr "type" "load")
       (eq_attr "sign_extend" "yes")
       (eq_attr "update" "yes")
       (eq_attr "indexed" "yes")
       (eq_attr "cpu" "power7"))
  "DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")

(define_insn_reservation "power7-fpload" 3
  (and (eq_attr "type" "fpload")
       (eq_attr "update" "no")
       (eq_attr "cpu" "power7"))
  "DU_power7,LSU_power7")

(define_insn_reservation "power7-fpload-update" 3
  (and (eq_attr "type" "fpload")
       (eq_attr "update" "yes")
       (eq_attr "cpu" "power7"))
  "DU2F_power7,LSU_power7+FXU_power7")

(define_insn_reservation "power7-store" 6 ; store-forwarding latency
  (and (eq_attr "type" "store")
       (eq_attr "update" "no")
       (eq_attr "cpu" "power7"))
  "DU_power7,LSU_power7+FXU_power7")

(define_insn_reservation "power7-store-update" 6
  (and (eq_attr "type" "store")
       (eq_attr "update" "yes")
       (eq_attr "indexed" "no")
       (eq_attr "cpu" "power7"))
  "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")

(define_insn_reservation "power7-store-update-indexed" 6
  (and (eq_attr "type" "store")
       (eq_attr "update" "yes")
       (eq_attr "indexed" "yes")
       (eq_attr "cpu" "power7"))
  "DU4_power7,LSU_power7+FXU_power7,FXU_power7")

(define_insn_reservation "power7-fpstore" 6
  (and (eq_attr "type" "fpstore")
       (eq_attr "update" "no")
       (eq_attr "cpu" "power7"))
  "DU_power7,LSU_power7+VSU_power7")

(define_insn_reservation "power7-fpstore-update" 6
  (and (eq_attr "type" "fpstore")
       (eq_attr "update" "yes")
       (eq_attr "cpu" "power7"))
  "DU_power7,LSU_power7+VSU_power7+FXU_power7")

(define_insn_reservation "power7-larx" 3
  (and (eq_attr "type" "load_l")
       (eq_attr "cpu" "power7"))
  "DU4_power7,LSU_power7")

(define_insn_reservation "power7-stcx" 10
  (and (eq_attr "type" "store_c")
       (eq_attr "cpu" "power7"))
  "DU4_power7,LSU_power7")

(define_insn_reservation "power7-vecload" 3
  (and (eq_attr "type" "vecload")
       (eq_attr "cpu" "power7"))
  "DU_power7,LSU_power7")

(define_insn_reservation "power7-vecstore" 6
  (and (eq_attr "type" "vecstore")
       (eq_attr "cpu" "power7"))
  "DU_power7,LSU_power7+vsu2_power7")

(define_insn_reservation "power7-sync" 11
  (and (eq_attr "type" "sync")
       (eq_attr "cpu" "power7"))
  "DU4_power7,LSU_power7")


; FX Unit
(define_insn_reservation "power7-integer" 1
  (and (ior (eq_attr "type" "integer,insert,trap,exts,isel,popcnt")
	    (and (eq_attr "type" "add,shift")
		 (eq_attr "dot" "no")))
       (eq_attr "cpu" "power7"))
  "DU_power7,FXU_power7")

(define_insn_reservation "power7-cntlz" 2
  (and (eq_attr "type" "cntlz")
       (eq_attr "cpu" "power7"))
  "DU_power7,FXU_power7")

(define_insn_reservation "power7-two" 2
  (and (eq_attr "type" "two")
       (eq_attr "cpu" "power7"))
  "DU_power7+DU_power7,FXU_power7,FXU_power7")

(define_insn_reservation "power7-three" 3
  (and (eq_attr "type" "three")
       (eq_attr "cpu" "power7"))
  "DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")

(define_insn_reservation "power7-cmp" 1
  (and (ior (eq_attr "type" "cmp,fast_compare")
	    (and (eq_attr "type" "add")
		 (eq_attr "dot" "yes")))
       (eq_attr "cpu" "power7"))
  "DU_power7,FXU_power7")

(define_insn_reservation "power7-compare" 2
  (and (ior (eq_attr "type" "compare")
	    (and (eq_attr "type" "shift")
		 (eq_attr "dot" "yes")))
       (eq_attr "cpu" "power7"))
  "DU2F_power7,FXU_power7,FXU_power7")

(define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")

(define_insn_reservation "power7-mul" 4
  (and (eq_attr "type" "mul")
       (eq_attr "dot" "no")
       (eq_attr "cpu" "power7"))
  "DU_power7,FXU_power7")

(define_insn_reservation "power7-mul-compare" 5
  (and (eq_attr "type" "mul")
       (eq_attr "dot" "yes")
       (eq_attr "cpu" "power7"))
  "DU2F_power7,FXU_power7,nothing*3,FXU_power7")

(define_insn_reservation "power7-idiv" 36
  (and (eq_attr "type" "div")
       (eq_attr "size" "32")
       (eq_attr "cpu" "power7"))
  "DU2F_power7,iu1_power7*36|iu2_power7*36")

(define_insn_reservation "power7-ldiv" 68
  (and (eq_attr "type" "div")
       (eq_attr "size" "64")
       (eq_attr "cpu" "power7"))
  "DU2F_power7,iu1_power7*68|iu2_power7*68")

(define_insn_reservation "power7-isync" 1 ;
  (and (eq_attr "type" "isync")
       (eq_attr "cpu" "power7"))
  "DU4_power7,FXU_power7")


; CR Unit
(define_insn_reservation "power7-mtjmpr" 4
  (and (eq_attr "type" "mtjmpr")
       (eq_attr "cpu" "power7"))
  "du1_power7,FXU_power7")

(define_insn_reservation "power7-mfjmpr" 5
  (and (eq_attr "type" "mfjmpr")
       (eq_attr "cpu" "power7"))
  "du1_power7,cru_power7+FXU_power7")

(define_insn_reservation "power7-crlogical" 3
  (and (eq_attr "type" "cr_logical")
       (eq_attr "cpu" "power7"))
  "du1_power7,cru_power7")

(define_insn_reservation "power7-delayedcr" 3
  (and (eq_attr "type" "delayed_cr")
       (eq_attr "cpu" "power7"))
  "du1_power7,cru_power7")

(define_insn_reservation "power7-mfcr" 6
  (and (eq_attr "type" "mfcr")
       (eq_attr "cpu" "power7"))
  "du1_power7,cru_power7")

(define_insn_reservation "power7-mfcrf" 3
  (and (eq_attr "type" "mfcrf")
       (eq_attr "cpu" "power7"))
  "du1_power7,cru_power7")

(define_insn_reservation "power7-mtcr" 3
  (and (eq_attr "type" "mtcr")
       (eq_attr "cpu" "power7"))
  "DU4_power7,cru_power7+FXU_power7")


; BR Unit
; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
; grabbing previous dispatch slots once this is assigned.
(define_insn_reservation "power7-branch" 3
  (and (eq_attr "type" "jmpreg,branch")
       (eq_attr "cpu" "power7"))
  "(du5_power7\
   |du4_power7+du5_power7\
   |du3_power7+du4_power7+du5_power7\
   |du2_power7+du3_power7+du4_power7+du5_power7\
   |du1_power7+du2_power7+du3_power7+du4_power7+du5_power7),bpu_power7")


; VS Unit (includes FP/VSX/VMX/DFP)
(define_insn_reservation "power7-fp" 6
  (and (eq_attr "type" "fp,dmul")
       (eq_attr "cpu" "power7"))
  "DU_power7,VSU_power7")

(define_bypass 8 "power7-fp" "power7-branch")

(define_insn_reservation "power7-fpcompare" 8
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "power7"))
  "DU_power7,VSU_power7")

(define_insn_reservation "power7-sdiv" 27
  (and (eq_attr "type" "sdiv")
       (eq_attr "cpu" "power7"))
  "DU_power7,VSU_power7")

(define_insn_reservation "power7-ddiv" 33
  (and (eq_attr "type" "ddiv")
       (eq_attr "cpu" "power7"))
  "DU_power7,VSU_power7")

(define_insn_reservation "power7-sqrt" 32
  (and (eq_attr "type" "ssqrt")
       (eq_attr "cpu" "power7"))
  "DU_power7,VSU_power7")

(define_insn_reservation "power7-dsqrt" 44
  (and (eq_attr "type" "dsqrt")
       (eq_attr "cpu" "power7"))
  "DU_power7,VSU_power7")

(define_insn_reservation "power7-vecsimple" 2
  (and (eq_attr "type" "vecsimple,veccmp")
       (eq_attr "cpu" "power7"))
  "DU_power7,vsu1_power7")

(define_insn_reservation "power7-vecfloat" 6
  (and (eq_attr "type" "vecfloat")
       (eq_attr "cpu" "power7"))
  "DU_power7,vsu1_power7")

(define_bypass 7 "power7-vecfloat" "power7-vecsimple,power7-veccomplex,\
				    power7-vecperm")

(define_insn_reservation "power7-veccomplex" 7
  (and (eq_attr "type" "veccomplex")
       (eq_attr "cpu" "power7"))
  "DU_power7,vsu1_power7")

(define_insn_reservation "power7-vecperm" 3
  (and (eq_attr "type" "vecperm")
       (eq_attr "cpu" "power7"))
  "DU_power7,vsu2_power7")

(define_insn_reservation "power7-vecdouble" 6
  (and (eq_attr "type" "vecdouble")
       (eq_attr "cpu" "power7"))
  "DU_power7,VSU_power7")

(define_bypass 7 "power7-vecdouble" "power7-vecsimple,power7-veccomplex,\
				    power7-vecperm")

(define_insn_reservation "power7-vecfdiv" 26
  (and (eq_attr "type" "vecfdiv")
       (eq_attr "cpu" "power7"))
  "DU_power7,VSU_power7")

(define_insn_reservation "power7-vecdiv" 32
  (and (eq_attr "type" "vecdiv")
       (eq_attr "cpu" "power7"))
  "DU_power7,VSU_power7")
Commit	Line	Data
29e6733c	1	;; Scheduling description for IBM POWER7 processor.
23a5b65a	2	;; Copyright (C) 2009-2014 Free Software Foundation, Inc.
29e6733c MM	3	;;
	4	;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
	5
	6	;; This file is part of GCC.
	7	;;
	8	;; GCC is free software; you can redistribute it and/or modify it
	9	;; under the terms of the GNU General Public License as published
	10	;; by the Free Software Foundation; either version 3, or (at your
	11	;; option) any later version.
	12	;;
	13	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	14	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	16	;; License for more details.
	17	;;
	18	;; You should have received a copy of the GNU General Public License
	19	;; along with GCC; see the file COPYING3. If not see
	20	;; <http://www.gnu.org/licenses/>.
	21
	22	(define_automaton "power7iu,power7lsu,power7vsu,power7misc")
	23
	24	(define_cpu_unit "iu1_power7,iu2_power7" "power7iu")
	25	(define_cpu_unit "lsu1_power7,lsu2_power7" "power7lsu")
	26	(define_cpu_unit "vsu1_power7,vsu2_power7" "power7vsu")
	27	(define_cpu_unit "bpu_power7,cru_power7" "power7misc")
	28	(define_cpu_unit "du1_power7,du2_power7,du3_power7,du4_power7,du5_power7"
	29	"power7misc")
	30
	31
	32	(define_reservation "DU_power7"
	33	"du1_power7\|du2_power7\|du3_power7\|du4_power7")
	34
	35	(define_reservation "DU2F_power7"
	36	"du1_power7+du2_power7")
	37
	38	(define_reservation "DU4_power7"
	39	"du1_power7+du2_power7+du3_power7+du4_power7")
	40
	41	(define_reservation "FXU_power7"
	42	"iu1_power7\|iu2_power7")
	43
	44	(define_reservation "VSU_power7"
	45	"vsu1_power7\|vsu2_power7")
	46
	47	(define_reservation "LSU_power7"
	48	"lsu1_power7\|lsu2_power7")
	49
	50
	51	; Dispatch slots are allocated in order conforming to program order.
	52	(absence_set "du1_power7" "du2_power7,du3_power7,du4_power7,du5_power7")
	53	(absence_set "du2_power7" "du3_power7,du4_power7,du5_power7")
	54	(absence_set "du3_power7" "du4_power7,du5_power7")
	55	(absence_set "du4_power7" "du5_power7")
	56
	57
	58	; LS Unit
	59	(define_insn_reservation "power7-load" 2
	60	(and (eq_attr "type" "load")
d839f53b SB	61	(eq_attr "sign_extend" "no")
d839f53b SB	62	(eq_attr "update" "no")
29e6733c MM	63	(eq_attr "cpu" "power7"))
	64	"DU_power7,LSU_power7")
	65
	66	(define_insn_reservation "power7-load-ext" 3
d839f53b SB	67	(and (eq_attr "type" "load")
	68	(eq_attr "sign_extend" "yes")
	69	(eq_attr "update" "no")
29e6733c MM	70	(eq_attr "cpu" "power7"))
	71	"DU2F_power7,LSU_power7,FXU_power7")
	72
	73	(define_insn_reservation "power7-load-update" 2
d839f53b SB	74	(and (eq_attr "type" "load")
	75	(eq_attr "sign_extend" "no")
	76	(eq_attr "update" "yes")
	77	(eq_attr "indexed" "no")
29e6733c MM	78	(eq_attr "cpu" "power7"))
	79	"DU2F_power7,LSU_power7+FXU_power7")
	80
	81	(define_insn_reservation "power7-load-update-indexed" 3
d839f53b SB	82	(and (eq_attr "type" "load")
	83	(eq_attr "sign_extend" "no")
	84	(eq_attr "update" "yes")
	85	(eq_attr "indexed" "yes")
29e6733c MM	86	(eq_attr "cpu" "power7"))
	87	"DU4_power7,FXU_power7,LSU_power7+FXU_power7")
	88
	89	(define_insn_reservation "power7-load-ext-update" 4
d839f53b SB	90	(and (eq_attr "type" "load")
	91	(eq_attr "sign_extend" "yes")
	92	(eq_attr "update" "yes")
	93	(eq_attr "indexed" "no")
29e6733c MM	94	(eq_attr "cpu" "power7"))
	95	"DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
	96
	97	(define_insn_reservation "power7-load-ext-update-indexed" 4
d839f53b SB	98	(and (eq_attr "type" "load")
	99	(eq_attr "sign_extend" "yes")
	100	(eq_attr "update" "yes")
	101	(eq_attr "indexed" "yes")
29e6733c MM	102	(eq_attr "cpu" "power7"))
	103	"DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")
	104
	105	(define_insn_reservation "power7-fpload" 3
	106	(and (eq_attr "type" "fpload")
d839f53b	107	(eq_attr "update" "no")
29e6733c MM	108	(eq_attr "cpu" "power7"))
	109	"DU_power7,LSU_power7")
	110
	111	(define_insn_reservation "power7-fpload-update" 3
d839f53b SB	112	(and (eq_attr "type" "fpload")
d839f53b SB	113	(eq_attr "update" "yes")
29e6733c MM	114	(eq_attr "cpu" "power7"))
	115	"DU2F_power7,LSU_power7+FXU_power7")
	116
	117	(define_insn_reservation "power7-store" 6 ; store-forwarding latency
	118	(and (eq_attr "type" "store")
d839f53b	119	(eq_attr "update" "no")
29e6733c MM	120	(eq_attr "cpu" "power7"))
	121	"DU_power7,LSU_power7+FXU_power7")
	122
	123	(define_insn_reservation "power7-store-update" 6
d839f53b SB	124	(and (eq_attr "type" "store")
	125	(eq_attr "update" "yes")
	126	(eq_attr "indexed" "no")
29e6733c MM	127	(eq_attr "cpu" "power7"))
	128	"DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
	129
	130	(define_insn_reservation "power7-store-update-indexed" 6
d839f53b SB	131	(and (eq_attr "type" "store")
	132	(eq_attr "update" "yes")
	133	(eq_attr "indexed" "yes")
29e6733c MM	134	(eq_attr "cpu" "power7"))
	135	"DU4_power7,LSU_power7+FXU_power7,FXU_power7")
	136
	137	(define_insn_reservation "power7-fpstore" 6
	138	(and (eq_attr "type" "fpstore")
d839f53b	139	(eq_attr "update" "no")
29e6733c MM	140	(eq_attr "cpu" "power7"))
	141	"DU_power7,LSU_power7+VSU_power7")
	142
	143	(define_insn_reservation "power7-fpstore-update" 6
d839f53b SB	144	(and (eq_attr "type" "fpstore")
d839f53b SB	145	(eq_attr "update" "yes")
29e6733c MM	146	(eq_attr "cpu" "power7"))
	147	"DU_power7,LSU_power7+VSU_power7+FXU_power7")
	148
	149	(define_insn_reservation "power7-larx" 3
	150	(and (eq_attr "type" "load_l")
	151	(eq_attr "cpu" "power7"))
	152	"DU4_power7,LSU_power7")
	153
	154	(define_insn_reservation "power7-stcx" 10
	155	(and (eq_attr "type" "store_c")
	156	(eq_attr "cpu" "power7"))
	157	"DU4_power7,LSU_power7")
	158
	159	(define_insn_reservation "power7-vecload" 3
	160	(and (eq_attr "type" "vecload")
	161	(eq_attr "cpu" "power7"))
	162	"DU_power7,LSU_power7")
	163
	164	(define_insn_reservation "power7-vecstore" 6
	165	(and (eq_attr "type" "vecstore")
	166	(eq_attr "cpu" "power7"))
4356b75d	167	"DU_power7,LSU_power7+vsu2_power7")
29e6733c MM	168
	169	(define_insn_reservation "power7-sync" 11
	170	(and (eq_attr "type" "sync")
	171	(eq_attr "cpu" "power7"))
	172	"DU4_power7,LSU_power7")
	173
	174
	175	; FX Unit
	176	(define_insn_reservation "power7-integer" 1
892e7fa6	177	(and (ior (eq_attr "type" "integer,insert,trap,exts,isel,popcnt")
0cbb4f58	178	(and (eq_attr "type" "add,shift")
892e7fa6	179	(eq_attr "dot" "no")))
29e6733c MM	180	(eq_attr "cpu" "power7"))
	181	"DU_power7,FXU_power7")
	182
	183	(define_insn_reservation "power7-cntlz" 2
	184	(and (eq_attr "type" "cntlz")
	185	(eq_attr "cpu" "power7"))
	186	"DU_power7,FXU_power7")
	187
	188	(define_insn_reservation "power7-two" 2
	189	(and (eq_attr "type" "two")
	190	(eq_attr "cpu" "power7"))
	191	"DU_power7+DU_power7,FXU_power7,FXU_power7")
	192
	193	(define_insn_reservation "power7-three" 3
	194	(and (eq_attr "type" "three")
	195	(eq_attr "cpu" "power7"))
	196	"DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
	197
	198	(define_insn_reservation "power7-cmp" 1
0cbb4f58 SB	199	(and (ior (eq_attr "type" "cmp,fast_compare")
	200	(and (eq_attr "type" "add")
	201	(eq_attr "dot" "yes")))
29e6733c MM	202	(eq_attr "cpu" "power7"))
	203	"DU_power7,FXU_power7")
	204
	205	(define_insn_reservation "power7-compare" 2
892e7fa6 SB	206	(and (ior (eq_attr "type" "compare")
	207	(and (eq_attr "type" "shift")
	208	(eq_attr "dot" "yes")))
29e6733c MM	209	(eq_attr "cpu" "power7"))
	210	"DU2F_power7,FXU_power7,FXU_power7")
	211
	212	(define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
	213
	214	(define_insn_reservation "power7-mul" 4
e0528ed9 SB	215	(and (eq_attr "type" "mul")
e0528ed9 SB	216	(eq_attr "dot" "no")
29e6733c MM	217	(eq_attr "cpu" "power7"))
	218	"DU_power7,FXU_power7")
	219
	220	(define_insn_reservation "power7-mul-compare" 5
e0528ed9 SB	221	(and (eq_attr "type" "mul")
e0528ed9 SB	222	(eq_attr "dot" "yes")
29e6733c MM	223	(eq_attr "cpu" "power7"))
	224	"DU2F_power7,FXU_power7,nothing*3,FXU_power7")
	225
	226	(define_insn_reservation "power7-idiv" 36
441e02a5 SB	227	(and (eq_attr "type" "div")
441e02a5 SB	228	(eq_attr "size" "32")
29e6733c MM	229	(eq_attr "cpu" "power7"))
	230	"DU2F_power7,iu1_power736\|iu2_power736")
	231
	232	(define_insn_reservation "power7-ldiv" 68
441e02a5 SB	233	(and (eq_attr "type" "div")
441e02a5 SB	234	(eq_attr "size" "64")
29e6733c MM	235	(eq_attr "cpu" "power7"))
	236	"DU2F_power7,iu1_power768\|iu2_power768")
	237
	238	(define_insn_reservation "power7-isync" 1 ;
	239	(and (eq_attr "type" "isync")
	240	(eq_attr "cpu" "power7"))
	241	"DU4_power7,FXU_power7")
	242
	243
	244	; CR Unit
	245	(define_insn_reservation "power7-mtjmpr" 4
	246	(and (eq_attr "type" "mtjmpr")
	247	(eq_attr "cpu" "power7"))
	248	"du1_power7,FXU_power7")
	249
	250	(define_insn_reservation "power7-mfjmpr" 5
	251	(and (eq_attr "type" "mfjmpr")
	252	(eq_attr "cpu" "power7"))
	253	"du1_power7,cru_power7+FXU_power7")
	254
	255	(define_insn_reservation "power7-crlogical" 3
	256	(and (eq_attr "type" "cr_logical")
	257	(eq_attr "cpu" "power7"))
	258	"du1_power7,cru_power7")
	259
	260	(define_insn_reservation "power7-delayedcr" 3
	261	(and (eq_attr "type" "delayed_cr")
	262	(eq_attr "cpu" "power7"))
	263	"du1_power7,cru_power7")
	264
	265	(define_insn_reservation "power7-mfcr" 6
	266	(and (eq_attr "type" "mfcr")
	267	(eq_attr "cpu" "power7"))
	268	"du1_power7,cru_power7")
	269
	270	(define_insn_reservation "power7-mfcrf" 3
	271	(and (eq_attr "type" "mfcrf")
	272	(eq_attr "cpu" "power7"))
	273	"du1_power7,cru_power7")
	274
	275	(define_insn_reservation "power7-mtcr" 3
	276	(and (eq_attr "type" "mtcr")
	277	(eq_attr "cpu" "power7"))
	278	"DU4_power7,cru_power7+FXU_power7")
	279
	280
	281	; BR Unit
	282	; Branches take dispatch Slot 4. The presence_sets prevent other insn from
	283	; grabbing previous dispatch slots once this is assigned.
	284	(define_insn_reservation "power7-branch" 3
	285	(and (eq_attr "type" "jmpreg,branch")
	286	(eq_attr "cpu" "power7"))
	287	"(du5_power7\
	288	\|du4_power7+du5_power7\
	289	\|du3_power7+du4_power7+du5_power7\
	290	\|du2_power7+du3_power7+du4_power7+du5_power7\
	291	\|du1_power7+du2_power7+du3_power7+du4_power7+du5_power7),bpu_power7")
	292
	293
	294	; VS Unit (includes FP/VSX/VMX/DFP)
	295	(define_insn_reservation "power7-fp" 6
	296	(and (eq_attr "type" "fp,dmul")
	297	(eq_attr "cpu" "power7"))
	298	"DU_power7,VSU_power7")
299
300	(define_bypass 8 "power7-fp" "power7-branch")
301
4356b75d	302	(define_insn_reservation "power7-fpcompare" 8
29e6733c MM	303	(and (eq_attr "type" "fpcompare")
	304	(eq_attr "cpu" "power7"))
	305	"DU_power7,VSU_power7")
	306
4356b75d	307	(define_insn_reservation "power7-sdiv" 27
29e6733c MM	308	(and (eq_attr "type" "sdiv")
	309	(eq_attr "cpu" "power7"))
	310	"DU_power7,VSU_power7")
	311
4356b75d	312	(define_insn_reservation "power7-ddiv" 33
29e6733c MM	313	(and (eq_attr "type" "ddiv")
	314	(eq_attr "cpu" "power7"))
	315	"DU_power7,VSU_power7")
	316
4356b75d	317	(define_insn_reservation "power7-sqrt" 32
29e6733c MM	318	(and (eq_attr "type" "ssqrt")
	319	(eq_attr "cpu" "power7"))
	320	"DU_power7,VSU_power7")
	321
4356b75d	322	(define_insn_reservation "power7-dsqrt" 44
29e6733c MM	323	(and (eq_attr "type" "dsqrt")
	324	(eq_attr "cpu" "power7"))
	325	"DU_power7,VSU_power7")
	326
	327	(define_insn_reservation "power7-vecsimple" 2
4356b75d	328	(and (eq_attr "type" "vecsimple,veccmp")
29e6733c	329	(eq_attr "cpu" "power7"))
4356b75d	330	"DU_power7,vsu1_power7")
29e6733c	331
4356b75d	332	(define_insn_reservation "power7-vecfloat" 6
29e6733c MM	333	(and (eq_attr "type" "vecfloat")
29e6733c MM	334	(eq_attr "cpu" "power7"))
4356b75d	335	"DU_power7,vsu1_power7")
29e6733c	336
4356b75d PH	337	(define_bypass 7 "power7-vecfloat" "power7-vecsimple,power7-veccomplex,\
4356b75d PH	338	power7-vecperm")
29e6733c MM	339
	340	(define_insn_reservation "power7-veccomplex" 7
	341	(and (eq_attr "type" "veccomplex")
	342	(eq_attr "cpu" "power7"))
4356b75d	343	"DU_power7,vsu1_power7")
29e6733c MM	344
	345	(define_insn_reservation "power7-vecperm" 3
	346	(and (eq_attr "type" "vecperm")
	347	(eq_attr "cpu" "power7"))
4356b75d PH	348	"DU_power7,vsu2_power7")
	349
	350	(define_insn_reservation "power7-vecdouble" 6
	351	(and (eq_attr "type" "vecdouble")
	352	(eq_attr "cpu" "power7"))
	353	"DU_power7,VSU_power7")
	354
	355	(define_bypass 7 "power7-vecdouble" "power7-vecsimple,power7-veccomplex,\
	356	power7-vecperm")
	357
	358	(define_insn_reservation "power7-vecfdiv" 26
	359	(and (eq_attr "type" "vecfdiv")
	360	(eq_attr "cpu" "power7"))
	361	"DU_power7,VSU_power7")
	362
	363	(define_insn_reservation "power7-vecdiv" 32
	364	(and (eq_attr "type" "vecdiv")
	365	(eq_attr "cpu" "power7"))
	366	"DU_power7,VSU_power7")
	367