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29e6733c | 1 | ;; Scheduling description for IBM POWER7 processor. |
85ec4feb | 2 | ;; Copyright (C) 2009-2018 Free Software Foundation, Inc. |
29e6733c MM |
3 | ;; |
4 | ;; Contributed by Pat Haugen (pthaugen@us.ibm.com). | |
5 | ||
6 | ;; This file is part of GCC. | |
7 | ;; | |
8 | ;; GCC is free software; you can redistribute it and/or modify it | |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 3, or (at your | |
11 | ;; option) any later version. | |
12 | ;; | |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
17 | ;; | |
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GCC; see the file COPYING3. If not see | |
20 | ;; <http://www.gnu.org/licenses/>. | |
21 | ||
22 | (define_automaton "power7iu,power7lsu,power7vsu,power7misc") | |
23 | ||
24 | (define_cpu_unit "iu1_power7,iu2_power7" "power7iu") | |
25 | (define_cpu_unit "lsu1_power7,lsu2_power7" "power7lsu") | |
26 | (define_cpu_unit "vsu1_power7,vsu2_power7" "power7vsu") | |
27 | (define_cpu_unit "bpu_power7,cru_power7" "power7misc") | |
28 | (define_cpu_unit "du1_power7,du2_power7,du3_power7,du4_power7,du5_power7" | |
29 | "power7misc") | |
30 | ||
31 | ||
32 | (define_reservation "DU_power7" | |
33 | "du1_power7|du2_power7|du3_power7|du4_power7") | |
34 | ||
35 | (define_reservation "DU2F_power7" | |
36 | "du1_power7+du2_power7") | |
37 | ||
38 | (define_reservation "DU4_power7" | |
39 | "du1_power7+du2_power7+du3_power7+du4_power7") | |
40 | ||
41 | (define_reservation "FXU_power7" | |
42 | "iu1_power7|iu2_power7") | |
43 | ||
44 | (define_reservation "VSU_power7" | |
45 | "vsu1_power7|vsu2_power7") | |
46 | ||
47 | (define_reservation "LSU_power7" | |
48 | "lsu1_power7|lsu2_power7") | |
49 | ||
50 | ||
51 | ; Dispatch slots are allocated in order conforming to program order. | |
52 | (absence_set "du1_power7" "du2_power7,du3_power7,du4_power7,du5_power7") | |
53 | (absence_set "du2_power7" "du3_power7,du4_power7,du5_power7") | |
54 | (absence_set "du3_power7" "du4_power7,du5_power7") | |
55 | (absence_set "du4_power7" "du5_power7") | |
56 | ||
57 | ||
58 | ; LS Unit | |
59 | (define_insn_reservation "power7-load" 2 | |
60 | (and (eq_attr "type" "load") | |
d839f53b SB |
61 | (eq_attr "sign_extend" "no") |
62 | (eq_attr "update" "no") | |
29e6733c MM |
63 | (eq_attr "cpu" "power7")) |
64 | "DU_power7,LSU_power7") | |
65 | ||
66 | (define_insn_reservation "power7-load-ext" 3 | |
d839f53b SB |
67 | (and (eq_attr "type" "load") |
68 | (eq_attr "sign_extend" "yes") | |
69 | (eq_attr "update" "no") | |
29e6733c MM |
70 | (eq_attr "cpu" "power7")) |
71 | "DU2F_power7,LSU_power7,FXU_power7") | |
72 | ||
73 | (define_insn_reservation "power7-load-update" 2 | |
d839f53b SB |
74 | (and (eq_attr "type" "load") |
75 | (eq_attr "sign_extend" "no") | |
76 | (eq_attr "update" "yes") | |
77 | (eq_attr "indexed" "no") | |
29e6733c MM |
78 | (eq_attr "cpu" "power7")) |
79 | "DU2F_power7,LSU_power7+FXU_power7") | |
80 | ||
81 | (define_insn_reservation "power7-load-update-indexed" 3 | |
d839f53b SB |
82 | (and (eq_attr "type" "load") |
83 | (eq_attr "sign_extend" "no") | |
84 | (eq_attr "update" "yes") | |
85 | (eq_attr "indexed" "yes") | |
29e6733c MM |
86 | (eq_attr "cpu" "power7")) |
87 | "DU4_power7,FXU_power7,LSU_power7+FXU_power7") | |
88 | ||
89 | (define_insn_reservation "power7-load-ext-update" 4 | |
d839f53b SB |
90 | (and (eq_attr "type" "load") |
91 | (eq_attr "sign_extend" "yes") | |
92 | (eq_attr "update" "yes") | |
93 | (eq_attr "indexed" "no") | |
29e6733c MM |
94 | (eq_attr "cpu" "power7")) |
95 | "DU2F_power7,LSU_power7+FXU_power7,FXU_power7") | |
96 | ||
97 | (define_insn_reservation "power7-load-ext-update-indexed" 4 | |
d839f53b SB |
98 | (and (eq_attr "type" "load") |
99 | (eq_attr "sign_extend" "yes") | |
100 | (eq_attr "update" "yes") | |
101 | (eq_attr "indexed" "yes") | |
29e6733c MM |
102 | (eq_attr "cpu" "power7")) |
103 | "DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7") | |
104 | ||
105 | (define_insn_reservation "power7-fpload" 3 | |
106 | (and (eq_attr "type" "fpload") | |
d839f53b | 107 | (eq_attr "update" "no") |
29e6733c MM |
108 | (eq_attr "cpu" "power7")) |
109 | "DU_power7,LSU_power7") | |
110 | ||
111 | (define_insn_reservation "power7-fpload-update" 3 | |
d839f53b SB |
112 | (and (eq_attr "type" "fpload") |
113 | (eq_attr "update" "yes") | |
29e6733c MM |
114 | (eq_attr "cpu" "power7")) |
115 | "DU2F_power7,LSU_power7+FXU_power7") | |
116 | ||
117 | (define_insn_reservation "power7-store" 6 ; store-forwarding latency | |
118 | (and (eq_attr "type" "store") | |
d839f53b | 119 | (eq_attr "update" "no") |
29e6733c MM |
120 | (eq_attr "cpu" "power7")) |
121 | "DU_power7,LSU_power7+FXU_power7") | |
122 | ||
123 | (define_insn_reservation "power7-store-update" 6 | |
d839f53b SB |
124 | (and (eq_attr "type" "store") |
125 | (eq_attr "update" "yes") | |
126 | (eq_attr "indexed" "no") | |
29e6733c MM |
127 | (eq_attr "cpu" "power7")) |
128 | "DU2F_power7,LSU_power7+FXU_power7,FXU_power7") | |
129 | ||
130 | (define_insn_reservation "power7-store-update-indexed" 6 | |
d839f53b SB |
131 | (and (eq_attr "type" "store") |
132 | (eq_attr "update" "yes") | |
133 | (eq_attr "indexed" "yes") | |
29e6733c MM |
134 | (eq_attr "cpu" "power7")) |
135 | "DU4_power7,LSU_power7+FXU_power7,FXU_power7") | |
136 | ||
137 | (define_insn_reservation "power7-fpstore" 6 | |
138 | (and (eq_attr "type" "fpstore") | |
d839f53b | 139 | (eq_attr "update" "no") |
29e6733c MM |
140 | (eq_attr "cpu" "power7")) |
141 | "DU_power7,LSU_power7+VSU_power7") | |
142 | ||
143 | (define_insn_reservation "power7-fpstore-update" 6 | |
d839f53b SB |
144 | (and (eq_attr "type" "fpstore") |
145 | (eq_attr "update" "yes") | |
29e6733c MM |
146 | (eq_attr "cpu" "power7")) |
147 | "DU_power7,LSU_power7+VSU_power7+FXU_power7") | |
148 | ||
149 | (define_insn_reservation "power7-larx" 3 | |
150 | (and (eq_attr "type" "load_l") | |
151 | (eq_attr "cpu" "power7")) | |
152 | "DU4_power7,LSU_power7") | |
153 | ||
154 | (define_insn_reservation "power7-stcx" 10 | |
155 | (and (eq_attr "type" "store_c") | |
156 | (eq_attr "cpu" "power7")) | |
157 | "DU4_power7,LSU_power7") | |
158 | ||
159 | (define_insn_reservation "power7-vecload" 3 | |
160 | (and (eq_attr "type" "vecload") | |
161 | (eq_attr "cpu" "power7")) | |
162 | "DU_power7,LSU_power7") | |
163 | ||
164 | (define_insn_reservation "power7-vecstore" 6 | |
165 | (and (eq_attr "type" "vecstore") | |
166 | (eq_attr "cpu" "power7")) | |
4356b75d | 167 | "DU_power7,LSU_power7+vsu2_power7") |
29e6733c MM |
168 | |
169 | (define_insn_reservation "power7-sync" 11 | |
170 | (and (eq_attr "type" "sync") | |
171 | (eq_attr "cpu" "power7")) | |
172 | "DU4_power7,LSU_power7") | |
173 | ||
174 | ||
175 | ; FX Unit | |
176 | (define_insn_reservation "power7-integer" 1 | |
79430730 SB |
177 | (and (ior (eq_attr "type" "integer,insert,trap,isel,popcnt") |
178 | (and (eq_attr "type" "add,logical,shift,exts") | |
892e7fa6 | 179 | (eq_attr "dot" "no"))) |
29e6733c MM |
180 | (eq_attr "cpu" "power7")) |
181 | "DU_power7,FXU_power7") | |
182 | ||
183 | (define_insn_reservation "power7-cntlz" 2 | |
184 | (and (eq_attr "type" "cntlz") | |
185 | (eq_attr "cpu" "power7")) | |
186 | "DU_power7,FXU_power7") | |
187 | ||
188 | (define_insn_reservation "power7-two" 2 | |
189 | (and (eq_attr "type" "two") | |
190 | (eq_attr "cpu" "power7")) | |
191 | "DU_power7+DU_power7,FXU_power7,FXU_power7") | |
192 | ||
193 | (define_insn_reservation "power7-three" 3 | |
194 | (and (eq_attr "type" "three") | |
195 | (eq_attr "cpu" "power7")) | |
196 | "DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7") | |
197 | ||
198 | (define_insn_reservation "power7-cmp" 1 | |
73c076c8 SB |
199 | (and (ior (eq_attr "type" "cmp") |
200 | (and (eq_attr "type" "add,logical") | |
0cbb4f58 | 201 | (eq_attr "dot" "yes"))) |
29e6733c MM |
202 | (eq_attr "cpu" "power7")) |
203 | "DU_power7,FXU_power7") | |
204 | ||
205 | (define_insn_reservation "power7-compare" 2 | |
f5ae5a23 SB |
206 | (and (eq_attr "type" "shift,exts") |
207 | (eq_attr "dot" "yes") | |
29e6733c MM |
208 | (eq_attr "cpu" "power7")) |
209 | "DU2F_power7,FXU_power7,FXU_power7") | |
210 | ||
211 | (define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr") | |
212 | ||
213 | (define_insn_reservation "power7-mul" 4 | |
e0528ed9 SB |
214 | (and (eq_attr "type" "mul") |
215 | (eq_attr "dot" "no") | |
29e6733c MM |
216 | (eq_attr "cpu" "power7")) |
217 | "DU_power7,FXU_power7") | |
218 | ||
219 | (define_insn_reservation "power7-mul-compare" 5 | |
e0528ed9 SB |
220 | (and (eq_attr "type" "mul") |
221 | (eq_attr "dot" "yes") | |
29e6733c MM |
222 | (eq_attr "cpu" "power7")) |
223 | "DU2F_power7,FXU_power7,nothing*3,FXU_power7") | |
224 | ||
225 | (define_insn_reservation "power7-idiv" 36 | |
441e02a5 SB |
226 | (and (eq_attr "type" "div") |
227 | (eq_attr "size" "32") | |
29e6733c MM |
228 | (eq_attr "cpu" "power7")) |
229 | "DU2F_power7,iu1_power7*36|iu2_power7*36") | |
230 | ||
231 | (define_insn_reservation "power7-ldiv" 68 | |
441e02a5 SB |
232 | (and (eq_attr "type" "div") |
233 | (eq_attr "size" "64") | |
29e6733c MM |
234 | (eq_attr "cpu" "power7")) |
235 | "DU2F_power7,iu1_power7*68|iu2_power7*68") | |
236 | ||
237 | (define_insn_reservation "power7-isync" 1 ; | |
238 | (and (eq_attr "type" "isync") | |
239 | (eq_attr "cpu" "power7")) | |
240 | "DU4_power7,FXU_power7") | |
241 | ||
242 | ||
243 | ; CR Unit | |
244 | (define_insn_reservation "power7-mtjmpr" 4 | |
245 | (and (eq_attr "type" "mtjmpr") | |
246 | (eq_attr "cpu" "power7")) | |
247 | "du1_power7,FXU_power7") | |
248 | ||
249 | (define_insn_reservation "power7-mfjmpr" 5 | |
250 | (and (eq_attr "type" "mfjmpr") | |
251 | (eq_attr "cpu" "power7")) | |
252 | "du1_power7,cru_power7+FXU_power7") | |
253 | ||
254 | (define_insn_reservation "power7-crlogical" 3 | |
255 | (and (eq_attr "type" "cr_logical") | |
256 | (eq_attr "cpu" "power7")) | |
257 | "du1_power7,cru_power7") | |
258 | ||
259 | (define_insn_reservation "power7-delayedcr" 3 | |
260 | (and (eq_attr "type" "delayed_cr") | |
261 | (eq_attr "cpu" "power7")) | |
262 | "du1_power7,cru_power7") | |
263 | ||
264 | (define_insn_reservation "power7-mfcr" 6 | |
265 | (and (eq_attr "type" "mfcr") | |
266 | (eq_attr "cpu" "power7")) | |
267 | "du1_power7,cru_power7") | |
268 | ||
269 | (define_insn_reservation "power7-mfcrf" 3 | |
270 | (and (eq_attr "type" "mfcrf") | |
271 | (eq_attr "cpu" "power7")) | |
272 | "du1_power7,cru_power7") | |
273 | ||
274 | (define_insn_reservation "power7-mtcr" 3 | |
275 | (and (eq_attr "type" "mtcr") | |
276 | (eq_attr "cpu" "power7")) | |
277 | "DU4_power7,cru_power7+FXU_power7") | |
278 | ||
279 | ||
280 | ; BR Unit | |
281 | ; Branches take dispatch Slot 4. The presence_sets prevent other insn from | |
282 | ; grabbing previous dispatch slots once this is assigned. | |
283 | (define_insn_reservation "power7-branch" 3 | |
284 | (and (eq_attr "type" "jmpreg,branch") | |
285 | (eq_attr "cpu" "power7")) | |
286 | "(du5_power7\ | |
287 | |du4_power7+du5_power7\ | |
288 | |du3_power7+du4_power7+du5_power7\ | |
289 | |du2_power7+du3_power7+du4_power7+du5_power7\ | |
290 | |du1_power7+du2_power7+du3_power7+du4_power7+du5_power7),bpu_power7") | |
291 | ||
292 | ||
293 | ; VS Unit (includes FP/VSX/VMX/DFP) | |
294 | (define_insn_reservation "power7-fp" 6 | |
eda328bf | 295 | (and (eq_attr "type" "fp,fpsimple,dmul,dfp") |
29e6733c MM |
296 | (eq_attr "cpu" "power7")) |
297 | "DU_power7,VSU_power7") | |
298 | ||
299 | (define_bypass 8 "power7-fp" "power7-branch") | |
300 | ||
4356b75d | 301 | (define_insn_reservation "power7-fpcompare" 8 |
29e6733c MM |
302 | (and (eq_attr "type" "fpcompare") |
303 | (eq_attr "cpu" "power7")) | |
304 | "DU_power7,VSU_power7") | |
305 | ||
4356b75d | 306 | (define_insn_reservation "power7-sdiv" 27 |
29e6733c MM |
307 | (and (eq_attr "type" "sdiv") |
308 | (eq_attr "cpu" "power7")) | |
309 | "DU_power7,VSU_power7") | |
310 | ||
4356b75d | 311 | (define_insn_reservation "power7-ddiv" 33 |
29e6733c MM |
312 | (and (eq_attr "type" "ddiv") |
313 | (eq_attr "cpu" "power7")) | |
314 | "DU_power7,VSU_power7") | |
315 | ||
4356b75d | 316 | (define_insn_reservation "power7-sqrt" 32 |
29e6733c MM |
317 | (and (eq_attr "type" "ssqrt") |
318 | (eq_attr "cpu" "power7")) | |
319 | "DU_power7,VSU_power7") | |
320 | ||
4356b75d | 321 | (define_insn_reservation "power7-dsqrt" 44 |
29e6733c MM |
322 | (and (eq_attr "type" "dsqrt") |
323 | (eq_attr "cpu" "power7")) | |
324 | "DU_power7,VSU_power7") | |
325 | ||
326 | (define_insn_reservation "power7-vecsimple" 2 | |
7c788ce2 | 327 | (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx") |
29e6733c | 328 | (eq_attr "cpu" "power7")) |
4356b75d | 329 | "DU_power7,vsu1_power7") |
29e6733c | 330 | |
4356b75d | 331 | (define_insn_reservation "power7-vecfloat" 6 |
29e6733c MM |
332 | (and (eq_attr "type" "vecfloat") |
333 | (eq_attr "cpu" "power7")) | |
4356b75d | 334 | "DU_power7,vsu1_power7") |
29e6733c | 335 | |
4356b75d PH |
336 | (define_bypass 7 "power7-vecfloat" "power7-vecsimple,power7-veccomplex,\ |
337 | power7-vecperm") | |
29e6733c MM |
338 | |
339 | (define_insn_reservation "power7-veccomplex" 7 | |
340 | (and (eq_attr "type" "veccomplex") | |
341 | (eq_attr "cpu" "power7")) | |
4356b75d | 342 | "DU_power7,vsu1_power7") |
29e6733c MM |
343 | |
344 | (define_insn_reservation "power7-vecperm" 3 | |
345 | (and (eq_attr "type" "vecperm") | |
346 | (eq_attr "cpu" "power7")) | |
4356b75d PH |
347 | "DU_power7,vsu2_power7") |
348 | ||
349 | (define_insn_reservation "power7-vecdouble" 6 | |
350 | (and (eq_attr "type" "vecdouble") | |
351 | (eq_attr "cpu" "power7")) | |
352 | "DU_power7,VSU_power7") | |
353 | ||
354 | (define_bypass 7 "power7-vecdouble" "power7-vecsimple,power7-veccomplex,\ | |
355 | power7-vecperm") | |
356 | ||
357 | (define_insn_reservation "power7-vecfdiv" 26 | |
358 | (and (eq_attr "type" "vecfdiv") | |
359 | (eq_attr "cpu" "power7")) | |
360 | "DU_power7,VSU_power7") | |
361 | ||
362 | (define_insn_reservation "power7-vecdiv" 32 | |
363 | (and (eq_attr "type" "vecdiv") | |
364 | (eq_attr "cpu" "power7")) | |
365 | "DU_power7,VSU_power7") | |
366 |