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48d72335 | 1 | ;; Predicate definitions for POWER and PowerPC. |
d652f226 JJ |
2 | ;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 |
3 | ;; Free Software Foundation, Inc. | |
48d72335 DE |
4 | ;; |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 9 | ;; the Free Software Foundation; either version 3, or (at your option) |
48d72335 DE |
10 | ;; any later version. |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
48d72335 DE |
20 | |
21 | ;; Return 1 for anything except PARALLEL. | |
22 | (define_predicate "any_operand" | |
23 | (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")) | |
24 | ||
25 | ;; Return 1 for any PARALLEL. | |
26 | (define_predicate "any_parallel_operand" | |
27 | (match_code "parallel")) | |
28 | ||
29 | ;; Return 1 if op is COUNT register. | |
30 | (define_predicate "count_register_operand" | |
31 | (and (match_code "reg") | |
1de43f85 | 32 | (match_test "REGNO (op) == CTR_REGNO |
48d72335 DE |
33 | || REGNO (op) > LAST_VIRTUAL_REGISTER"))) |
34 | ||
35 | ;; Return 1 if op is an Altivec register. | |
36 | (define_predicate "altivec_register_operand" | |
5b296c8a DE |
37 | (and (match_operand 0 "register_operand") |
38 | (match_test "GET_CODE (op) != REG | |
39 | || ALTIVEC_REGNO_P (REGNO (op)) | |
40 | || REGNO (op) > LAST_VIRTUAL_REGISTER"))) | |
48d72335 | 41 | |
a72c65c7 MM |
42 | ;; Return 1 if op is a VSX register. |
43 | (define_predicate "vsx_register_operand" | |
44 | (and (match_operand 0 "register_operand") | |
45 | (match_test "GET_CODE (op) != REG | |
46 | || VSX_REGNO_P (REGNO (op)) | |
47 | || REGNO (op) > LAST_VIRTUAL_REGISTER"))) | |
48 | ||
49 | ;; Return 1 if op is a vector register that operates on floating point vectors | |
50 | ;; (either altivec or VSX). | |
51 | (define_predicate "vfloat_operand" | |
52 | (and (match_operand 0 "register_operand") | |
53 | (match_test "GET_CODE (op) != REG | |
54 | || VFLOAT_REGNO_P (REGNO (op)) | |
55 | || REGNO (op) > LAST_VIRTUAL_REGISTER"))) | |
56 | ||
57 | ;; Return 1 if op is a vector register that operates on integer vectors | |
58 | ;; (only altivec, VSX doesn't support integer vectors) | |
59 | (define_predicate "vint_operand" | |
60 | (and (match_operand 0 "register_operand") | |
61 | (match_test "GET_CODE (op) != REG | |
62 | || VINT_REGNO_P (REGNO (op)) | |
63 | || REGNO (op) > LAST_VIRTUAL_REGISTER"))) | |
64 | ||
65 | ;; Return 1 if op is a vector register to do logical operations on (and, or, | |
66 | ;; xor, etc.) | |
67 | (define_predicate "vlogical_operand" | |
68 | (and (match_operand 0 "register_operand") | |
69 | (match_test "GET_CODE (op) != REG | |
70 | || VLOGICAL_REGNO_P (REGNO (op)) | |
71 | || REGNO (op) > LAST_VIRTUAL_REGISTER"))) | |
72 | ||
f6b5d695 SB |
73 | ;; Return 1 if op is the carry register. |
74 | (define_predicate "ca_operand" | |
48d72335 | 75 | (and (match_code "reg") |
f6b5d695 | 76 | (match_test "CA_REGNO_P (REGNO (op))"))) |
48d72335 | 77 | |
afca671b DP |
78 | ;; Return 1 if op is a signed 5-bit constant integer. |
79 | (define_predicate "s5bit_cint_operand" | |
80 | (and (match_code "const_int") | |
81 | (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) | |
82 | ||
83 | ;; Return 1 if op is a unsigned 5-bit constant integer. | |
84 | (define_predicate "u5bit_cint_operand" | |
85 | (and (match_code "const_int") | |
86 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) | |
87 | ||
48d72335 | 88 | ;; Return 1 if op is a signed 8-bit constant integer. |
c83eecad | 89 | ;; Integer multiplication complete more quickly |
48d72335 DE |
90 | (define_predicate "s8bit_cint_operand" |
91 | (and (match_code "const_int") | |
92 | (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) | |
93 | ||
94 | ;; Return 1 if op is a constant integer that can fit in a D field. | |
95 | (define_predicate "short_cint_operand" | |
96 | (and (match_code "const_int") | |
279bb624 | 97 | (match_test "satisfies_constraint_I (op)"))) |
48d72335 DE |
98 | |
99 | ;; Return 1 if op is a constant integer that can fit in an unsigned D field. | |
100 | (define_predicate "u_short_cint_operand" | |
101 | (and (match_code "const_int") | |
279bb624 | 102 | (match_test "satisfies_constraint_K (op)"))) |
48d72335 DE |
103 | |
104 | ;; Return 1 if op is a constant integer that cannot fit in a signed D field. | |
105 | (define_predicate "non_short_cint_operand" | |
106 | (and (match_code "const_int") | |
107 | (match_test "(unsigned HOST_WIDE_INT) | |
108 | (INTVAL (op) + 0x8000) >= 0x10000"))) | |
109 | ||
110 | ;; Return 1 if op is a positive constant integer that is an exact power of 2. | |
111 | (define_predicate "exact_log2_cint_operand" | |
112 | (and (match_code "const_int") | |
113 | (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) | |
114 | ||
8c1249f9 | 115 | ;; Return 1 if op is a register that is not special. |
48d72335 | 116 | (define_predicate "gpc_reg_operand" |
5b296c8a | 117 | (and (match_operand 0 "register_operand") |
8c1249f9 | 118 | (match_test "(GET_CODE (op) != REG |
14502dad | 119 | || (REGNO (op) >= ARG_POINTER_REGNUM |
f6b5d695 | 120 | && !CA_REGNO_P (REGNO (op))) |
14502dad JM |
121 | || REGNO (op) < MQ_REGNO) |
122 | && !((TARGET_E500_DOUBLE || TARGET_SPE) | |
123 | && invalid_e500_subreg (op, mode))"))) | |
48d72335 DE |
124 | |
125 | ;; Return 1 if op is a register that is a condition register field. | |
126 | (define_predicate "cc_reg_operand" | |
5b296c8a DE |
127 | (and (match_operand 0 "register_operand") |
128 | (match_test "GET_CODE (op) != REG | |
129 | || REGNO (op) > LAST_VIRTUAL_REGISTER | |
130 | || CR_REGNO_P (REGNO (op))"))) | |
48d72335 DE |
131 | |
132 | ;; Return 1 if op is a register that is a condition register field not cr0. | |
133 | (define_predicate "cc_reg_not_cr0_operand" | |
5b296c8a DE |
134 | (and (match_operand 0 "register_operand") |
135 | (match_test "GET_CODE (op) != REG | |
136 | || REGNO (op) > LAST_VIRTUAL_REGISTER | |
137 | || CR_REGNO_NOT_CR0_P (REGNO (op))"))) | |
48d72335 | 138 | |
c921bad8 AP |
139 | ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0. |
140 | (define_predicate "cc_reg_not_micro_cr0_operand" | |
141 | (and (match_operand 0 "register_operand") | |
142 | (match_test "GET_CODE (op) != REG | |
143 | || REGNO (op) > LAST_VIRTUAL_REGISTER | |
144 | || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op))) | |
145 | || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))"))) | |
146 | ||
48d72335 DE |
147 | ;; Return 1 if op is a constant integer valid for D field |
148 | ;; or non-special register register. | |
149 | (define_predicate "reg_or_short_operand" | |
150 | (if_then_else (match_code "const_int") | |
151 | (match_operand 0 "short_cint_operand") | |
152 | (match_operand 0 "gpc_reg_operand"))) | |
153 | ||
154 | ;; Return 1 if op is a constant integer valid whose negation is valid for | |
155 | ;; D field or non-special register register. | |
156 | ;; Do not allow a constant zero because all patterns that call this | |
157 | ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than | |
158 | ;; or equal to const, which does not work for zero. | |
159 | (define_predicate "reg_or_neg_short_operand" | |
160 | (if_then_else (match_code "const_int") | |
279bb624 | 161 | (match_test "satisfies_constraint_P (op) |
48d72335 DE |
162 | && INTVAL (op) != 0") |
163 | (match_operand 0 "gpc_reg_operand"))) | |
164 | ||
165 | ;; Return 1 if op is a constant integer valid for DS field | |
166 | ;; or non-special register. | |
167 | (define_predicate "reg_or_aligned_short_operand" | |
168 | (if_then_else (match_code "const_int") | |
169 | (and (match_operand 0 "short_cint_operand") | |
170 | (match_test "!(INTVAL (op) & 3)")) | |
171 | (match_operand 0 "gpc_reg_operand"))) | |
172 | ||
173 | ;; Return 1 if op is a constant integer whose high-order 16 bits are zero | |
174 | ;; or non-special register. | |
175 | (define_predicate "reg_or_u_short_operand" | |
176 | (if_then_else (match_code "const_int") | |
177 | (match_operand 0 "u_short_cint_operand") | |
178 | (match_operand 0 "gpc_reg_operand"))) | |
179 | ||
180 | ;; Return 1 if op is any constant integer | |
181 | ;; or non-special register. | |
182 | (define_predicate "reg_or_cint_operand" | |
183 | (ior (match_code "const_int") | |
184 | (match_operand 0 "gpc_reg_operand"))) | |
185 | ||
4ae234b0 | 186 | ;; Return 1 if op is a constant integer valid for addition |
48d72335 | 187 | ;; or non-special register. |
4ae234b0 | 188 | (define_predicate "reg_or_add_cint_operand" |
48d72335 | 189 | (if_then_else (match_code "const_int") |
4ae234b0 GK |
190 | (match_test "(HOST_BITS_PER_WIDE_INT == 32 |
191 | && (mode == SImode || INTVAL (op) < 0x7fff8000)) | |
94dcded2 | 192 | || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
48d72335 DE |
193 | < (unsigned HOST_WIDE_INT) 0x100000000ll)") |
194 | (match_operand 0 "gpc_reg_operand"))) | |
195 | ||
4ae234b0 | 196 | ;; Return 1 if op is a constant integer valid for subtraction |
48d72335 | 197 | ;; or non-special register. |
4ae234b0 | 198 | (define_predicate "reg_or_sub_cint_operand" |
48d72335 | 199 | (if_then_else (match_code "const_int") |
4ae234b0 GK |
200 | (match_test "(HOST_BITS_PER_WIDE_INT == 32 |
201 | && (mode == SImode || - INTVAL (op) < 0x7fff8000)) | |
202 | || ((unsigned HOST_WIDE_INT) (- INTVAL (op) | |
203 | + (mode == SImode | |
204 | ? 0x80000000 : 0x80008000)) | |
48d72335 DE |
205 | < (unsigned HOST_WIDE_INT) 0x100000000ll)") |
206 | (match_operand 0 "gpc_reg_operand"))) | |
207 | ||
208 | ;; Return 1 if op is any 32-bit unsigned constant integer | |
209 | ;; or non-special register. | |
210 | (define_predicate "reg_or_logical_cint_operand" | |
211 | (if_then_else (match_code "const_int") | |
212 | (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT | |
213 | && INTVAL (op) >= 0) | |
214 | || ((INTVAL (op) & GET_MODE_MASK (mode) | |
215 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") | |
216 | (if_then_else (match_code "const_double") | |
217 | (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT | |
218 | && mode == DImode | |
219 | && CONST_DOUBLE_HIGH (op) == 0") | |
220 | (match_operand 0 "gpc_reg_operand")))) | |
221 | ||
222 | ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register | |
223 | ;; with no more than one instruction per word. | |
224 | (define_predicate "easy_fp_constant" | |
225 | (match_code "const_double") | |
226 | { | |
992d08b1 NS |
227 | long k[4]; |
228 | REAL_VALUE_TYPE rv; | |
229 | ||
48d72335 | 230 | if (GET_MODE (op) != mode |
ebb109ad | 231 | || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode)) |
48d72335 DE |
232 | return 0; |
233 | ||
234 | /* Consider all constants with -msoft-float to be easy. */ | |
696e45ba ME |
235 | if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE |
236 | || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT))) | |
48d72335 DE |
237 | && mode != DImode) |
238 | return 1; | |
239 | ||
00b79d54 BE |
240 | if (DECIMAL_FLOAT_MODE_P (mode)) |
241 | return 0; | |
242 | ||
48d72335 DE |
243 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
244 | if (flag_pic && DEFAULT_ABI == ABI_V4) | |
245 | return 0; | |
246 | ||
247 | #ifdef TARGET_RELOCATABLE | |
248 | /* Similarly if we are using -mrelocatable, consider all constants | |
249 | to be hard. */ | |
250 | if (TARGET_RELOCATABLE) | |
251 | return 0; | |
252 | #endif | |
253 | ||
992d08b1 | 254 | switch (mode) |
48d72335 | 255 | { |
992d08b1 | 256 | case TFmode: |
624b157f JM |
257 | if (TARGET_E500_DOUBLE) |
258 | return 0; | |
259 | ||
48d72335 DE |
260 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
261 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
262 | ||
263 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
264 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
265 | && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
266 | && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
48d72335 | 267 | |
992d08b1 | 268 | case DFmode: |
a72c65c7 MM |
269 | /* The constant 0.f is easy under VSX. */ |
270 | if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode)) | |
271 | return 1; | |
272 | ||
b6dc5507 DE |
273 | /* Force constants to memory before reload to utilize |
274 | compress_float_constant. | |
275 | Avoid this when flag_unsafe_math_optimizations is enabled | |
276 | because RDIV division to reciprocal optimization is not able | |
277 | to regenerate the division. */ | |
278 | if (TARGET_E500_DOUBLE | |
279 | || (!reload_in_progress && !reload_completed | |
280 | && !flag_unsafe_math_optimizations)) | |
281 | return 0; | |
48d72335 DE |
282 | |
283 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
284 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
285 | ||
286 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
287 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
48d72335 | 288 | |
992d08b1 | 289 | case SFmode: |
8308679f DE |
290 | /* The constant 0.f is easy. */ |
291 | if (op == CONST0_RTX (SFmode)) | |
292 | return 1; | |
293 | ||
b6dc5507 DE |
294 | /* Force constants to memory before reload to utilize |
295 | compress_float_constant. | |
296 | Avoid this when flag_unsafe_math_optimizations is enabled | |
297 | because RDIV division to reciprocal optimization is not able | |
298 | to regenerate the division. */ | |
299 | if (!reload_in_progress && !reload_completed | |
300 | && !flag_unsafe_math_optimizations) | |
301 | return 0; | |
302 | ||
48d72335 | 303 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
992d08b1 | 304 | REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]); |
48d72335 | 305 | |
992d08b1 | 306 | return num_insns_constant_wide (k[0]) == 1; |
48d72335 | 307 | |
992d08b1 | 308 | case DImode: |
48d72335 DE |
309 | return ((TARGET_POWERPC64 |
310 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) | |
311 | || (num_insns_constant (op, DImode) <= 2)); | |
312 | ||
992d08b1 | 313 | case SImode: |
48d72335 | 314 | return 1; |
992d08b1 NS |
315 | |
316 | default: | |
317 | gcc_unreachable (); | |
318 | } | |
48d72335 DE |
319 | }) |
320 | ||
321 | ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a | |
322 | ;; vector register without using memory. | |
323 | (define_predicate "easy_vector_constant" | |
324 | (match_code "const_vector") | |
325 | { | |
f5027409 RE |
326 | /* As the paired vectors are actually FPRs it seems that there is |
327 | no easy way to load a CONST_VECTOR without using memory. */ | |
328 | if (TARGET_PAIRED_FLOAT) | |
329 | return false; | |
330 | ||
a72c65c7 MM |
331 | if ((VSX_VECTOR_MODE (mode) || mode == TImode) && zero_constant (op, mode)) |
332 | return true; | |
333 | ||
66180ff3 PB |
334 | if (ALTIVEC_VECTOR_MODE (mode)) |
335 | { | |
336 | if (zero_constant (op, mode)) | |
337 | return true; | |
66180ff3 PB |
338 | return easy_altivec_constant (op, mode); |
339 | } | |
48d72335 | 340 | |
66180ff3 | 341 | if (SPE_VECTOR_MODE (mode)) |
48d72335 | 342 | { |
66180ff3 PB |
343 | int cst, cst2; |
344 | if (zero_constant (op, mode)) | |
345 | return true; | |
346 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) | |
347 | return false; | |
348 | ||
349 | /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
350 | li r0, CONSTANT1 | |
351 | evmergelo r0, r0, r0 | |
352 | li r0, CONSTANT2 | |
353 | ||
354 | I don't know how efficient it would be to allow bigger constants, | |
355 | considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
356 | instructions is better than a 64-bit memory load, but I don't | |
357 | have the e500 timing specs. */ | |
358 | if (mode == V2SImode) | |
359 | { | |
360 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
361 | cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
362 | return cst >= -0x7fff && cst <= 0x7fff | |
363 | && cst2 >= -0x7fff && cst2 <= 0x7fff; | |
364 | } | |
48d72335 | 365 | } |
66180ff3 PB |
366 | |
367 | return false; | |
48d72335 DE |
368 | }) |
369 | ||
370 | ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. | |
371 | (define_predicate "easy_vector_constant_add_self" | |
372 | (and (match_code "const_vector") | |
373 | (and (match_test "TARGET_ALTIVEC") | |
66180ff3 PB |
374 | (match_test "easy_altivec_constant (op, mode)"))) |
375 | { | |
847535b6 JJ |
376 | HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); |
377 | val = ((val & 0xff) ^ 0x80) - 0x80; | |
66180ff3 PB |
378 | return EASY_VECTOR_15_ADD_SELF (val); |
379 | }) | |
48d72335 | 380 | |
29e6733c MM |
381 | ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB. |
382 | (define_predicate "easy_vector_constant_msb" | |
383 | (and (match_code "const_vector") | |
384 | (and (match_test "TARGET_ALTIVEC") | |
385 | (match_test "easy_altivec_constant (op, mode)"))) | |
386 | { | |
387 | HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); | |
388 | return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode)); | |
389 | }) | |
390 | ||
48d72335 DE |
391 | ;; Return 1 if operand is constant zero (scalars and vectors). |
392 | (define_predicate "zero_constant" | |
393 | (and (match_code "const_int,const_double,const_vector") | |
394 | (match_test "op == CONST0_RTX (mode)"))) | |
395 | ||
396 | ;; Return 1 if operand is 0.0. | |
397 | ;; or non-special register register field no cr0 | |
398 | (define_predicate "zero_fp_constant" | |
399 | (and (match_code "const_double") | |
ebb109ad | 400 | (match_test "SCALAR_FLOAT_MODE_P (mode) |
48d72335 DE |
401 | && op == CONST0_RTX (mode)"))) |
402 | ||
403 | ;; Return 1 if the operand is in volatile memory. Note that during the | |
404 | ;; RTL generation phase, memory_operand does not return TRUE for volatile | |
405 | ;; memory references. So this function allows us to recognize volatile | |
f3b569ca | 406 | ;; references where it's safe. |
48d72335 DE |
407 | (define_predicate "volatile_mem_operand" |
408 | (and (and (match_code "mem") | |
409 | (match_test "MEM_VOLATILE_P (op)")) | |
410 | (if_then_else (match_test "reload_completed") | |
411 | (match_operand 0 "memory_operand") | |
412 | (if_then_else (match_test "reload_in_progress") | |
413 | (match_test "strict_memory_address_p (mode, XEXP (op, 0))") | |
414 | (match_test "memory_address_p (mode, XEXP (op, 0))"))))) | |
415 | ||
416 | ;; Return 1 if the operand is an offsettable memory operand. | |
417 | (define_predicate "offsettable_mem_operand" | |
b0d6c7d8 | 418 | (and (match_operand 0 "memory_operand") |
406d1650 | 419 | (match_test "offsettable_nonstrict_memref_p (op)"))) |
48d72335 | 420 | |
b6d2248c GK |
421 | ;; Return 1 if the operand is a memory operand with an address divisible by 4 |
422 | (define_predicate "word_offset_memref_operand" | |
2665ab87 DE |
423 | (match_operand 0 "memory_operand") |
424 | { | |
425 | /* Address inside MEM. */ | |
426 | op = XEXP (op, 0); | |
427 | ||
428 | /* Extract address from auto-inc/dec. */ | |
429 | if (GET_CODE (op) == PRE_INC | |
430 | || GET_CODE (op) == PRE_DEC) | |
431 | op = XEXP (op, 0); | |
432 | else if (GET_CODE (op) == PRE_MODIFY) | |
433 | op = XEXP (op, 1); | |
434 | ||
435 | return (GET_CODE (op) != PLUS | |
436 | || ! REG_P (XEXP (op, 0)) | |
437 | || GET_CODE (XEXP (op, 1)) != CONST_INT | |
438 | || INTVAL (XEXP (op, 1)) % 4 == 0); | |
439 | }) | |
b6d2248c | 440 | |
bf00cc0f AM |
441 | ;; Return 1 if the operand is an indexed or indirect memory operand. |
442 | (define_predicate "indexed_or_indirect_operand" | |
443 | (match_code "mem") | |
444 | { | |
445 | op = XEXP (op, 0); | |
a72c65c7 | 446 | if (VECTOR_MEM_ALTIVEC_P (mode) |
bf00cc0f AM |
447 | && GET_CODE (op) == AND |
448 | && GET_CODE (XEXP (op, 1)) == CONST_INT | |
449 | && INTVAL (XEXP (op, 1)) == -16) | |
450 | op = XEXP (op, 0); | |
451 | ||
452 | return indexed_or_indirect_address (op, mode); | |
453 | }) | |
454 | ||
a72c65c7 MM |
455 | ;; Return 1 if the operand is an indexed or indirect memory operand with an |
456 | ;; AND -16 in it, used to recognize when we need to switch to Altivec loads | |
457 | ;; to realign loops instead of VSX (altivec silently ignores the bottom bits, | |
458 | ;; while VSX uses the full address and traps) | |
459 | (define_predicate "altivec_indexed_or_indirect_operand" | |
460 | (match_code "mem") | |
461 | { | |
462 | op = XEXP (op, 0); | |
463 | if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) | |
464 | && GET_CODE (op) == AND | |
465 | && GET_CODE (XEXP (op, 1)) == CONST_INT | |
466 | && INTVAL (XEXP (op, 1)) == -16) | |
467 | return indexed_or_indirect_address (XEXP (op, 0), mode); | |
468 | ||
469 | return 0; | |
470 | }) | |
471 | ||
11aac14f | 472 | ;; Return 1 if the operand is an indexed or indirect address. |
bf00cc0f AM |
473 | (define_special_predicate "indexed_or_indirect_address" |
474 | (and (match_test "REG_P (op) | |
11aac14f | 475 | || (GET_CODE (op) == PLUS |
bf00cc0f AM |
476 | /* Omit testing REG_P (XEXP (op, 0)). */ |
477 | && REG_P (XEXP (op, 1)))") | |
478 | (match_operand 0 "address_operand"))) | |
11aac14f | 479 | |
045a8eb3 GK |
480 | ;; Used for the destination of the fix_truncdfsi2 expander. |
481 | ;; If stfiwx will be used, the result goes to memory; otherwise, | |
482 | ;; we're going to emit a store and a load of a subreg, so the dest is a | |
483 | ;; register. | |
484 | (define_predicate "fix_trunc_dest_operand" | |
485 | (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT") | |
486 | (match_operand 0 "memory_operand") | |
487 | (match_operand 0 "gpc_reg_operand"))) | |
488 | ||
48d72335 DE |
489 | ;; Return 1 if the operand is either a non-special register or can be used |
490 | ;; as the operand of a `mode' add insn. | |
491 | (define_predicate "add_operand" | |
492 | (if_then_else (match_code "const_int") | |
279bb624 DE |
493 | (match_test "satisfies_constraint_I (op) |
494 | || satisfies_constraint_L (op)") | |
48d72335 DE |
495 | (match_operand 0 "gpc_reg_operand"))) |
496 | ||
497 | ;; Return 1 if OP is a constant but not a valid add_operand. | |
498 | (define_predicate "non_add_cint_operand" | |
499 | (and (match_code "const_int") | |
279bb624 DE |
500 | (match_test "!satisfies_constraint_I (op) |
501 | && !satisfies_constraint_L (op)"))) | |
48d72335 | 502 | |
410c459d PB |
503 | ;; Return 1 if the operand is a constant that can be used as the operand |
504 | ;; of an OR or XOR. | |
505 | (define_predicate "logical_const_operand" | |
506 | (match_code "const_int,const_double") | |
48d72335 DE |
507 | { |
508 | HOST_WIDE_INT opl, oph; | |
509 | ||
48d72335 DE |
510 | if (GET_CODE (op) == CONST_INT) |
511 | { | |
512 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
513 | ||
514 | if (HOST_BITS_PER_WIDE_INT <= 32 | |
515 | && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
516 | return 0; | |
517 | } | |
518 | else if (GET_CODE (op) == CONST_DOUBLE) | |
519 | { | |
992d08b1 | 520 | gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT); |
48d72335 DE |
521 | |
522 | opl = CONST_DOUBLE_LOW (op); | |
523 | oph = CONST_DOUBLE_HIGH (op); | |
524 | if (oph != 0) | |
525 | return 0; | |
526 | } | |
527 | else | |
528 | return 0; | |
529 | ||
530 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 | |
531 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
532 | }) | |
533 | ||
410c459d PB |
534 | ;; Return 1 if the operand is a non-special register or a constant that |
535 | ;; can be used as the operand of an OR or XOR. | |
536 | (define_predicate "logical_operand" | |
537 | (ior (match_operand 0 "gpc_reg_operand") | |
538 | (match_operand 0 "logical_const_operand"))) | |
539 | ||
48d72335 DE |
540 | ;; Return 1 if op is a constant that is not a logical operand, but could |
541 | ;; be split into one. | |
542 | (define_predicate "non_logical_cint_operand" | |
543 | (and (match_code "const_int,const_double") | |
544 | (and (not (match_operand 0 "logical_operand")) | |
545 | (match_operand 0 "reg_or_logical_cint_operand")))) | |
546 | ||
1990cd79 AM |
547 | ;; Return 1 if op is a constant that can be encoded in a 32-bit mask, |
548 | ;; suitable for use with rlwinm (no more than two 1->0 or 0->1 | |
549 | ;; transitions). Reject all ones and all zeros, since these should have | |
550 | ;; been optimized away and confuse the making of MB and ME. | |
48d72335 DE |
551 | (define_predicate "mask_operand" |
552 | (match_code "const_int") | |
553 | { | |
554 | HOST_WIDE_INT c, lsb; | |
555 | ||
556 | c = INTVAL (op); | |
557 | ||
1990cd79 AM |
558 | if (TARGET_POWERPC64) |
559 | { | |
560 | /* Fail if the mask is not 32-bit. */ | |
561 | if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0) | |
562 | return 0; | |
4ae234b0 | 563 | |
1990cd79 AM |
564 | /* Fail if the mask wraps around because the upper 32-bits of the |
565 | mask will all be 1s, contrary to GCC's internal view. */ | |
566 | if ((c & 0x80000001) == 0x80000001) | |
567 | return 0; | |
568 | } | |
48d72335 DE |
569 | |
570 | /* We don't change the number of transitions by inverting, | |
571 | so make sure we start with the LS bit zero. */ | |
572 | if (c & 1) | |
573 | c = ~c; | |
574 | ||
1990cd79 AM |
575 | /* Reject all zeros or all ones. */ |
576 | if (c == 0) | |
577 | return 0; | |
578 | ||
48d72335 DE |
579 | /* Find the first transition. */ |
580 | lsb = c & -c; | |
581 | ||
1990cd79 AM |
582 | /* Invert to look for a second transition. */ |
583 | c = ~c; | |
48d72335 | 584 | |
1990cd79 AM |
585 | /* Erase first transition. */ |
586 | c &= -lsb; | |
48d72335 | 587 | |
1990cd79 AM |
588 | /* Find the second transition (if any). */ |
589 | lsb = c & -c; | |
48d72335 DE |
590 | |
591 | /* Match if all the bits above are 1's (or c is zero). */ | |
592 | return c == -lsb; | |
593 | }) | |
594 | ||
595 | ;; Return 1 for the PowerPC64 rlwinm corner case. | |
596 | (define_predicate "mask_operand_wrap" | |
597 | (match_code "const_int") | |
598 | { | |
599 | HOST_WIDE_INT c, lsb; | |
600 | ||
601 | c = INTVAL (op); | |
602 | ||
603 | if ((c & 0x80000001) != 0x80000001) | |
604 | return 0; | |
605 | ||
606 | c = ~c; | |
607 | if (c == 0) | |
608 | return 0; | |
609 | ||
610 | lsb = c & -c; | |
611 | c = ~c; | |
612 | c &= -lsb; | |
613 | lsb = c & -c; | |
614 | return c == -lsb; | |
615 | }) | |
616 | ||
1990cd79 AM |
617 | ;; Return 1 if the operand is a constant that is a PowerPC64 mask |
618 | ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1 | |
619 | ;; transition). Reject all zeros, since zero should have been | |
620 | ;; optimized away and confuses the making of MB and ME. | |
621 | (define_predicate "mask64_operand" | |
622 | (match_code "const_int") | |
623 | { | |
624 | HOST_WIDE_INT c, lsb; | |
625 | ||
626 | c = INTVAL (op); | |
627 | ||
628 | /* Reject all zeros. */ | |
629 | if (c == 0) | |
630 | return 0; | |
631 | ||
632 | /* We don't change the number of transitions by inverting, | |
633 | so make sure we start with the LS bit zero. */ | |
634 | if (c & 1) | |
635 | c = ~c; | |
636 | ||
637 | /* Find the first transition. */ | |
638 | lsb = c & -c; | |
639 | ||
640 | /* Match if all the bits above are 1's (or c is zero). */ | |
641 | return c == -lsb; | |
642 | }) | |
643 | ||
644 | ;; Like mask64_operand, but allow up to three transitions. This | |
48d72335 DE |
645 | ;; predicate is used by insn patterns that generate two rldicl or |
646 | ;; rldicr machine insns. | |
647 | (define_predicate "mask64_2_operand" | |
648 | (match_code "const_int") | |
649 | { | |
1990cd79 AM |
650 | HOST_WIDE_INT c, lsb; |
651 | ||
652 | c = INTVAL (op); | |
653 | ||
654 | /* Disallow all zeros. */ | |
655 | if (c == 0) | |
656 | return 0; | |
657 | ||
658 | /* We don't change the number of transitions by inverting, | |
659 | so make sure we start with the LS bit zero. */ | |
660 | if (c & 1) | |
661 | c = ~c; | |
662 | ||
663 | /* Find the first transition. */ | |
664 | lsb = c & -c; | |
665 | ||
666 | /* Invert to look for a second transition. */ | |
667 | c = ~c; | |
668 | ||
669 | /* Erase first transition. */ | |
670 | c &= -lsb; | |
671 | ||
672 | /* Find the second transition. */ | |
673 | lsb = c & -c; | |
674 | ||
675 | /* Invert to look for a third transition. */ | |
676 | c = ~c; | |
677 | ||
678 | /* Erase second transition. */ | |
679 | c &= -lsb; | |
680 | ||
681 | /* Find the third transition (if any). */ | |
682 | lsb = c & -c; | |
683 | ||
684 | /* Match if all the bits above are 1's (or c is zero). */ | |
685 | return c == -lsb; | |
48d72335 DE |
686 | }) |
687 | ||
4ae234b0 | 688 | ;; Like and_operand, but also match constants that can be implemented |
48d72335 DE |
689 | ;; with two rldicl or rldicr insns. |
690 | (define_predicate "and64_2_operand" | |
1990cd79 | 691 | (ior (match_operand 0 "mask64_2_operand") |
334269b9 DE |
692 | (if_then_else (match_test "fixed_regs[CR0_REGNO]") |
693 | (match_operand 0 "gpc_reg_operand") | |
694 | (match_operand 0 "logical_operand")))) | |
48d72335 DE |
695 | |
696 | ;; Return 1 if the operand is either a non-special register or a | |
697 | ;; constant that can be used as the operand of a logical AND. | |
698 | (define_predicate "and_operand" | |
334269b9 | 699 | (ior (match_operand 0 "mask_operand") |
1990cd79 AM |
700 | (ior (and (match_test "TARGET_POWERPC64 && mode == DImode") |
701 | (match_operand 0 "mask64_operand")) | |
702 | (if_then_else (match_test "fixed_regs[CR0_REGNO]") | |
703 | (match_operand 0 "gpc_reg_operand") | |
704 | (match_operand 0 "logical_operand"))))) | |
48d72335 | 705 | |
e9441276 DE |
706 | ;; Return 1 if the operand is either a logical operand or a short cint operand. |
707 | (define_predicate "scc_eq_operand" | |
708 | (ior (match_operand 0 "logical_operand") | |
709 | (match_operand 0 "short_cint_operand"))) | |
710 | ||
48d72335 DE |
711 | ;; Return 1 if the operand is a general non-special register or memory operand. |
712 | (define_predicate "reg_or_mem_operand" | |
48d72335 | 713 | (ior (match_operand 0 "memory_operand") |
fc0d1c49 BE |
714 | (ior (and (match_code "mem") |
715 | (match_test "macho_lo_sum_memory_operand (op, mode)")) | |
716 | (ior (match_operand 0 "volatile_mem_operand") | |
717 | (match_operand 0 "gpc_reg_operand"))))) | |
48d72335 | 718 | |
97c54d9a DE |
719 | ;; Return 1 if the operand is either an easy FP constant or memory or reg. |
720 | (define_predicate "reg_or_none500mem_operand" | |
721 | (if_then_else (match_code "mem") | |
722 | (and (match_test "!TARGET_E500_DOUBLE") | |
723 | (ior (match_operand 0 "memory_operand") | |
724 | (ior (match_test "macho_lo_sum_memory_operand (op, mode)") | |
725 | (match_operand 0 "volatile_mem_operand")))) | |
726 | (match_operand 0 "gpc_reg_operand"))) | |
727 | ||
728 | ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand. | |
729 | (define_predicate "zero_reg_mem_operand" | |
730 | (ior (match_operand 0 "zero_fp_constant") | |
731 | (match_operand 0 "reg_or_mem_operand"))) | |
732 | ||
48d72335 | 733 | ;; Return 1 if the operand is a general register or memory operand without |
6fb5fa3c DB |
734 | ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC |
735 | ;; lwa instruction. | |
48d72335 DE |
736 | (define_predicate "lwa_operand" |
737 | (match_code "reg,subreg,mem") | |
738 | { | |
739 | rtx inner = op; | |
740 | ||
741 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
742 | inner = SUBREG_REG (inner); | |
743 | ||
744 | return gpc_reg_operand (inner, mode) | |
745 | || (memory_operand (inner, mode) | |
746 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
747 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC | |
6fb5fa3c DB |
748 | && (GET_CODE (XEXP (inner, 0)) != PRE_MODIFY |
749 | || legitimate_indexed_address_p (XEXP (XEXP (inner, 0), 1), 0)) | |
48d72335 DE |
750 | && (GET_CODE (XEXP (inner, 0)) != PLUS |
751 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT | |
752 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
753 | }) | |
754 | ||
755 | ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. | |
756 | (define_predicate "symbol_ref_operand" | |
757 | (and (match_code "symbol_ref") | |
758 | (match_test "(mode == VOIDmode || GET_MODE (op) == mode) | |
759 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))"))) | |
760 | ||
761 | ;; Return 1 if op is an operand that can be loaded via the GOT. | |
762 | ;; or non-special register register field no cr0 | |
763 | (define_predicate "got_operand" | |
764 | (match_code "symbol_ref,const,label_ref")) | |
765 | ||
766 | ;; Return 1 if op is a simple reference that can be loaded via the GOT, | |
aabcd309 | 767 | ;; excluding labels involving addition. |
48d72335 DE |
768 | (define_predicate "got_no_const_operand" |
769 | (match_code "symbol_ref,label_ref")) | |
770 | ||
771 | ;; Return 1 if op is a SYMBOL_REF for a TLS symbol. | |
772 | (define_predicate "rs6000_tls_symbol_ref" | |
773 | (and (match_code "symbol_ref") | |
774 | (match_test "RS6000_SYMBOL_REF_TLS_P (op)"))) | |
775 | ||
776 | ;; Return 1 if the operand, used inside a MEM, is a valid first argument | |
777 | ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. | |
778 | (define_predicate "call_operand" | |
779 | (if_then_else (match_code "reg") | |
1de43f85 DE |
780 | (match_test "REGNO (op) == LR_REGNO |
781 | || REGNO (op) == CTR_REGNO | |
48d72335 DE |
782 | || REGNO (op) >= FIRST_PSEUDO_REGISTER") |
783 | (match_code "symbol_ref"))) | |
784 | ||
785 | ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
786 | ;; this file. | |
787 | (define_predicate "current_file_function_operand" | |
788 | (and (match_code "symbol_ref") | |
789 | (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
8aa19d95 JJ |
790 | && ((SYMBOL_REF_LOCAL_P (op) |
791 | && (DEFAULT_ABI != ABI_AIX | |
792 | || !SYMBOL_REF_EXTERNAL_P (op))) | |
48d72335 DE |
793 | || (op == XEXP (DECL_RTL (current_function_decl), |
794 | 0)))"))) | |
795 | ||
796 | ;; Return 1 if this operand is a valid input for a move insn. | |
797 | (define_predicate "input_operand" | |
798 | (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem, | |
799 | const_double,const_vector,const_int,plus") | |
800 | { | |
801 | /* Memory is always valid. */ | |
802 | if (memory_operand (op, mode)) | |
803 | return 1; | |
804 | ||
805 | /* For floating-point, easy constants are valid. */ | |
ebb109ad | 806 | if (SCALAR_FLOAT_MODE_P (mode) |
48d72335 DE |
807 | && CONSTANT_P (op) |
808 | && easy_fp_constant (op, mode)) | |
809 | return 1; | |
810 | ||
811 | /* Allow any integer constant. */ | |
812 | if (GET_MODE_CLASS (mode) == MODE_INT | |
813 | && (GET_CODE (op) == CONST_INT | |
814 | || GET_CODE (op) == CONST_DOUBLE)) | |
815 | return 1; | |
816 | ||
817 | /* Allow easy vector constants. */ | |
818 | if (GET_CODE (op) == CONST_VECTOR | |
819 | && easy_vector_constant (op, mode)) | |
820 | return 1; | |
821 | ||
61c76239 JM |
822 | /* Do not allow invalid E500 subregs. */ |
823 | if ((TARGET_E500_DOUBLE || TARGET_SPE) | |
824 | && GET_CODE (op) == SUBREG | |
825 | && invalid_e500_subreg (op, mode)) | |
826 | return 0; | |
827 | ||
48d72335 DE |
828 | /* For floating-point or multi-word mode, the only remaining valid type |
829 | is a register. */ | |
ebb109ad | 830 | if (SCALAR_FLOAT_MODE_P (mode) |
48d72335 DE |
831 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) |
832 | return register_operand (op, mode); | |
833 | ||
834 | /* The only cases left are integral modes one word or smaller (we | |
835 | do not get called for MODE_CC values). These can be in any | |
836 | register. */ | |
837 | if (register_operand (op, mode)) | |
838 | return 1; | |
839 | ||
840 | /* A SYMBOL_REF referring to the TOC is valid. */ | |
070b27da | 841 | if (legitimate_constant_pool_address_p (op, false)) |
48d72335 DE |
842 | return 1; |
843 | ||
844 | /* A constant pool expression (relative to the TOC) is valid */ | |
845 | if (toc_relative_expr_p (op)) | |
846 | return 1; | |
847 | ||
848 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region | |
849 | to be valid. */ | |
850 | if (DEFAULT_ABI == ABI_V4 | |
851 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) | |
852 | && small_data_operand (op, Pmode)) | |
853 | return 1; | |
854 | ||
855 | return 0; | |
856 | }) | |
857 | ||
858 | ;; Return true if OP is an invalid SUBREG operation on the e500. | |
859 | (define_predicate "rs6000_nonimmediate_operand" | |
860 | (match_code "reg,subreg,mem") | |
861 | { | |
61c76239 | 862 | if ((TARGET_E500_DOUBLE || TARGET_SPE) |
48d72335 DE |
863 | && GET_CODE (op) == SUBREG |
864 | && invalid_e500_subreg (op, mode)) | |
865 | return 0; | |
866 | ||
867 | return nonimmediate_operand (op, mode); | |
868 | }) | |
869 | ||
870 | ;; Return true if operand is boolean operator. | |
871 | (define_predicate "boolean_operator" | |
872 | (match_code "and,ior,xor")) | |
873 | ||
874 | ;; Return true if operand is OR-form of boolean operator. | |
875 | (define_predicate "boolean_or_operator" | |
876 | (match_code "ior,xor")) | |
877 | ||
28d0e143 PB |
878 | ;; Return true if operand is an equality operator. |
879 | (define_special_predicate "equality_operator" | |
880 | (match_code "eq,ne")) | |
881 | ||
48d72335 DE |
882 | ;; Return true if operand is MIN or MAX operator. |
883 | (define_predicate "min_max_operator" | |
884 | (match_code "smin,smax,umin,umax")) | |
885 | ||
886 | ;; Return 1 if OP is a comparison operation that is valid for a branch | |
57a71826 DE |
887 | ;; instruction. We check the opcode against the mode of the CC value. |
888 | ;; validate_condition_mode is an assertion. | |
364849ee | 889 | (define_predicate "branch_comparison_operator" |
ede62875 DE |
890 | (and (match_operand 0 "comparison_operator") |
891 | (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC") | |
892 | (match_test "validate_condition_mode (GET_CODE (op), | |
893 | GET_MODE (XEXP (op, 0))), | |
894 | 1")))) | |
48d72335 | 895 | |
f90b7a5a PB |
896 | (define_predicate "rs6000_cbranch_operator" |
897 | (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS") | |
898 | (match_operand 0 "ordered_comparison_operator") | |
899 | (match_operand 0 "comparison_operator"))) | |
900 | ||
48d72335 DE |
901 | ;; Return 1 if OP is a comparison operation that is valid for an SCC insn -- |
902 | ;; it must be a positive comparison. | |
364849ee | 903 | (define_predicate "scc_comparison_operator" |
ede62875 DE |
904 | (and (match_operand 0 "branch_comparison_operator") |
905 | (match_code "eq,lt,gt,ltu,gtu,unordered"))) | |
48d72335 | 906 | |
d2333f6e NF |
907 | ;; Return 1 if OP is a comparison operation whose inverse would be valid for |
908 | ;; an SCC insn. | |
909 | (define_predicate "scc_rev_comparison_operator" | |
910 | (and (match_operand 0 "branch_comparison_operator") | |
911 | (match_code "ne,le,ge,leu,geu,ordered"))) | |
912 | ||
48d72335 DE |
913 | ;; Return 1 if OP is a comparison operation that is valid for a branch |
914 | ;; insn, which is true if the corresponding bit in the CC register is set. | |
364849ee | 915 | (define_predicate "branch_positive_comparison_operator" |
ede62875 DE |
916 | (and (match_operand 0 "branch_comparison_operator") |
917 | (match_code "eq,lt,gt,ltu,gtu,unordered"))) | |
48d72335 | 918 | |
48d72335 DE |
919 | ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL. |
920 | (define_predicate "load_multiple_operation" | |
921 | (match_code "parallel") | |
922 | { | |
923 | int count = XVECLEN (op, 0); | |
924 | unsigned int dest_regno; | |
925 | rtx src_addr; | |
926 | int i; | |
927 | ||
928 | /* Perform a quick check so we don't blow up below. */ | |
929 | if (count <= 1 | |
930 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
931 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
932 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
933 | return 0; | |
934 | ||
935 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
936 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
937 | ||
938 | for (i = 1; i < count; i++) | |
939 | { | |
940 | rtx elt = XVECEXP (op, 0, i); | |
941 | ||
942 | if (GET_CODE (elt) != SET | |
943 | || GET_CODE (SET_DEST (elt)) != REG | |
944 | || GET_MODE (SET_DEST (elt)) != SImode | |
945 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
946 | || GET_CODE (SET_SRC (elt)) != MEM | |
947 | || GET_MODE (SET_SRC (elt)) != SImode | |
948 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
949 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
950 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
951 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
952 | return 0; | |
953 | } | |
954 | ||
955 | return 1; | |
956 | }) | |
957 | ||
958 | ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL. | |
959 | ;; The second vector element is a CLOBBER. | |
960 | (define_predicate "store_multiple_operation" | |
961 | (match_code "parallel") | |
962 | { | |
963 | int count = XVECLEN (op, 0) - 1; | |
964 | unsigned int src_regno; | |
965 | rtx dest_addr; | |
966 | int i; | |
967 | ||
968 | /* Perform a quick check so we don't blow up below. */ | |
969 | if (count <= 1 | |
970 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
971 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
972 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
973 | return 0; | |
974 | ||
975 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
976 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
977 | ||
978 | for (i = 1; i < count; i++) | |
979 | { | |
980 | rtx elt = XVECEXP (op, 0, i + 1); | |
981 | ||
982 | if (GET_CODE (elt) != SET | |
983 | || GET_CODE (SET_SRC (elt)) != REG | |
984 | || GET_MODE (SET_SRC (elt)) != SImode | |
985 | || REGNO (SET_SRC (elt)) != src_regno + i | |
986 | || GET_CODE (SET_DEST (elt)) != MEM | |
987 | || GET_MODE (SET_DEST (elt)) != SImode | |
988 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
989 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
990 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
991 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
992 | return 0; | |
993 | } | |
994 | ||
995 | return 1; | |
996 | }) | |
997 | ||
998 | ;; Return 1 if OP is valid for a save_world call in prologue, known to be | |
999 | ;; a PARLLEL. | |
1000 | (define_predicate "save_world_operation" | |
1001 | (match_code "parallel") | |
1002 | { | |
1003 | int index; | |
1004 | int i; | |
1005 | rtx elt; | |
1006 | int count = XVECLEN (op, 0); | |
1007 | ||
f78c3290 | 1008 | if (count != 54) |
48d72335 DE |
1009 | return 0; |
1010 | ||
1011 | index = 0; | |
1012 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1013 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
1014 | return 0; | |
1015 | ||
1016 | for (i=1; i <= 18; i++) | |
1017 | { | |
1018 | elt = XVECEXP (op, 0, index++); | |
1019 | if (GET_CODE (elt) != SET | |
1020 | || GET_CODE (SET_DEST (elt)) != MEM | |
1021 | || ! memory_operand (SET_DEST (elt), DFmode) | |
1022 | || GET_CODE (SET_SRC (elt)) != REG | |
1023 | || GET_MODE (SET_SRC (elt)) != DFmode) | |
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | for (i=1; i <= 12; i++) | |
1028 | { | |
1029 | elt = XVECEXP (op, 0, index++); | |
1030 | if (GET_CODE (elt) != SET | |
1031 | || GET_CODE (SET_DEST (elt)) != MEM | |
1032 | || GET_CODE (SET_SRC (elt)) != REG | |
1033 | || GET_MODE (SET_SRC (elt)) != V4SImode) | |
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | for (i=1; i <= 19; i++) | |
1038 | { | |
1039 | elt = XVECEXP (op, 0, index++); | |
1040 | if (GET_CODE (elt) != SET | |
1041 | || GET_CODE (SET_DEST (elt)) != MEM | |
1042 | || ! memory_operand (SET_DEST (elt), Pmode) | |
1043 | || GET_CODE (SET_SRC (elt)) != REG | |
1044 | || GET_MODE (SET_SRC (elt)) != Pmode) | |
1045 | return 0; | |
1046 | } | |
1047 | ||
1048 | elt = XVECEXP (op, 0, index++); | |
1049 | if (GET_CODE (elt) != SET | |
1050 | || GET_CODE (SET_DEST (elt)) != MEM | |
1051 | || ! memory_operand (SET_DEST (elt), Pmode) | |
1052 | || GET_CODE (SET_SRC (elt)) != REG | |
1053 | || REGNO (SET_SRC (elt)) != CR2_REGNO | |
1054 | || GET_MODE (SET_SRC (elt)) != Pmode) | |
1055 | return 0; | |
1056 | ||
f78c3290 NF |
1057 | if (GET_CODE (XVECEXP (op, 0, index++)) != SET |
1058 | || GET_CODE (XVECEXP (op, 0, index++)) != SET) | |
48d72335 DE |
1059 | return 0; |
1060 | return 1; | |
1061 | }) | |
1062 | ||
1063 | ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be | |
1064 | ;; a PARLLEL. | |
1065 | (define_predicate "restore_world_operation" | |
1066 | (match_code "parallel") | |
1067 | { | |
1068 | int index; | |
1069 | int i; | |
1070 | rtx elt; | |
1071 | int count = XVECLEN (op, 0); | |
1072 | ||
1073 | if (count != 59) | |
1074 | return 0; | |
1075 | ||
1076 | index = 0; | |
1077 | if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN | |
1078 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
1079 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
1080 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) | |
1081 | return 0; | |
1082 | ||
1083 | elt = XVECEXP (op, 0, index++); | |
1084 | if (GET_CODE (elt) != SET | |
1085 | || GET_CODE (SET_SRC (elt)) != MEM | |
1086 | || ! memory_operand (SET_SRC (elt), Pmode) | |
1087 | || GET_CODE (SET_DEST (elt)) != REG | |
1088 | || REGNO (SET_DEST (elt)) != CR2_REGNO | |
1089 | || GET_MODE (SET_DEST (elt)) != Pmode) | |
1090 | return 0; | |
1091 | ||
1092 | for (i=1; i <= 19; i++) | |
1093 | { | |
1094 | elt = XVECEXP (op, 0, index++); | |
1095 | if (GET_CODE (elt) != SET | |
1096 | || GET_CODE (SET_SRC (elt)) != MEM | |
1097 | || ! memory_operand (SET_SRC (elt), Pmode) | |
1098 | || GET_CODE (SET_DEST (elt)) != REG | |
1099 | || GET_MODE (SET_DEST (elt)) != Pmode) | |
1100 | return 0; | |
1101 | } | |
1102 | ||
1103 | for (i=1; i <= 12; i++) | |
1104 | { | |
1105 | elt = XVECEXP (op, 0, index++); | |
1106 | if (GET_CODE (elt) != SET | |
1107 | || GET_CODE (SET_SRC (elt)) != MEM | |
1108 | || GET_CODE (SET_DEST (elt)) != REG | |
1109 | || GET_MODE (SET_DEST (elt)) != V4SImode) | |
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | for (i=1; i <= 18; i++) | |
1114 | { | |
1115 | elt = XVECEXP (op, 0, index++); | |
1116 | if (GET_CODE (elt) != SET | |
1117 | || GET_CODE (SET_SRC (elt)) != MEM | |
1118 | || ! memory_operand (SET_SRC (elt), DFmode) | |
1119 | || GET_CODE (SET_DEST (elt)) != REG | |
1120 | || GET_MODE (SET_DEST (elt)) != DFmode) | |
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1125 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1126 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1127 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1128 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
1129 | return 0; | |
1130 | return 1; | |
1131 | }) | |
1132 | ||
1133 | ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL. | |
1134 | (define_predicate "vrsave_operation" | |
1135 | (match_code "parallel") | |
1136 | { | |
1137 | int count = XVECLEN (op, 0); | |
1138 | unsigned int dest_regno, src_regno; | |
1139 | int i; | |
1140 | ||
1141 | if (count <= 1 | |
1142 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1143 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
72c164b3 DE |
1144 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE |
1145 | || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE) | |
48d72335 DE |
1146 | return 0; |
1147 | ||
1148 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
833126ad | 1149 | src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); |
48d72335 | 1150 | |
833126ad | 1151 | if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) |
48d72335 DE |
1152 | return 0; |
1153 | ||
1154 | for (i = 1; i < count; i++) | |
1155 | { | |
1156 | rtx elt = XVECEXP (op, 0, i); | |
1157 | ||
1158 | if (GET_CODE (elt) != CLOBBER | |
1159 | && GET_CODE (elt) != SET) | |
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | return 1; | |
1164 | }) | |
1165 | ||
1166 | ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL. | |
1167 | (define_predicate "mfcr_operation" | |
1168 | (match_code "parallel") | |
1169 | { | |
1170 | int count = XVECLEN (op, 0); | |
1171 | int i; | |
1172 | ||
1173 | /* Perform a quick check so we don't blow up below. */ | |
1174 | if (count < 1 | |
1175 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1176 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
1177 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
1178 | return 0; | |
1179 | ||
1180 | for (i = 0; i < count; i++) | |
1181 | { | |
1182 | rtx exp = XVECEXP (op, 0, i); | |
1183 | rtx unspec; | |
1184 | int maskval; | |
1185 | rtx src_reg; | |
1186 | ||
1187 | src_reg = XVECEXP (SET_SRC (exp), 0, 0); | |
1188 | ||
1189 | if (GET_CODE (src_reg) != REG | |
1190 | || GET_MODE (src_reg) != CCmode | |
1191 | || ! CR_REGNO_P (REGNO (src_reg))) | |
1192 | return 0; | |
1193 | ||
1194 | if (GET_CODE (exp) != SET | |
1195 | || GET_CODE (SET_DEST (exp)) != REG | |
1196 | || GET_MODE (SET_DEST (exp)) != SImode | |
1197 | || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) | |
1198 | return 0; | |
1199 | unspec = SET_SRC (exp); | |
1200 | maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); | |
1201 | ||
1202 | if (GET_CODE (unspec) != UNSPEC | |
1203 | || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR | |
1204 | || XVECLEN (unspec, 0) != 2 | |
1205 | || XVECEXP (unspec, 0, 0) != src_reg | |
1206 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
1207 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
1208 | return 0; | |
1209 | } | |
1210 | return 1; | |
1211 | }) | |
1212 | ||
1213 | ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL. | |
1214 | (define_predicate "mtcrf_operation" | |
1215 | (match_code "parallel") | |
1216 | { | |
1217 | int count = XVECLEN (op, 0); | |
1218 | int i; | |
1219 | rtx src_reg; | |
1220 | ||
1221 | /* Perform a quick check so we don't blow up below. */ | |
1222 | if (count < 1 | |
1223 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1224 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
1225 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
1226 | return 0; | |
1227 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); | |
1228 | ||
1229 | if (GET_CODE (src_reg) != REG | |
1230 | || GET_MODE (src_reg) != SImode | |
1231 | || ! INT_REGNO_P (REGNO (src_reg))) | |
1232 | return 0; | |
1233 | ||
1234 | for (i = 0; i < count; i++) | |
1235 | { | |
1236 | rtx exp = XVECEXP (op, 0, i); | |
1237 | rtx unspec; | |
1238 | int maskval; | |
1239 | ||
1240 | if (GET_CODE (exp) != SET | |
1241 | || GET_CODE (SET_DEST (exp)) != REG | |
1242 | || GET_MODE (SET_DEST (exp)) != CCmode | |
1243 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
1244 | return 0; | |
1245 | unspec = SET_SRC (exp); | |
1246 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
1247 | ||
1248 | if (GET_CODE (unspec) != UNSPEC | |
1249 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR | |
1250 | || XVECLEN (unspec, 0) != 2 | |
1251 | || XVECEXP (unspec, 0, 0) != src_reg | |
1252 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
1253 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
1254 | return 0; | |
1255 | } | |
1256 | return 1; | |
1257 | }) | |
1258 | ||
1259 | ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. | |
1260 | (define_predicate "lmw_operation" | |
1261 | (match_code "parallel") | |
1262 | { | |
1263 | int count = XVECLEN (op, 0); | |
1264 | unsigned int dest_regno; | |
1265 | rtx src_addr; | |
1266 | unsigned int base_regno; | |
1267 | HOST_WIDE_INT offset; | |
1268 | int i; | |
1269 | ||
1270 | /* Perform a quick check so we don't blow up below. */ | |
1271 | if (count <= 1 | |
1272 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1273 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
1274 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
1275 | return 0; | |
1276 | ||
1277 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
1278 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
1279 | ||
1280 | if (dest_regno > 31 | |
1281 | || count != 32 - (int) dest_regno) | |
1282 | return 0; | |
1283 | ||
1284 | if (legitimate_indirect_address_p (src_addr, 0)) | |
1285 | { | |
1286 | offset = 0; | |
1287 | base_regno = REGNO (src_addr); | |
1288 | if (base_regno == 0) | |
1289 | return 0; | |
1290 | } | |
1291 | else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0)) | |
1292 | { | |
1293 | offset = INTVAL (XEXP (src_addr, 1)); | |
1294 | base_regno = REGNO (XEXP (src_addr, 0)); | |
1295 | } | |
1296 | else | |
1297 | return 0; | |
1298 | ||
1299 | for (i = 0; i < count; i++) | |
1300 | { | |
1301 | rtx elt = XVECEXP (op, 0, i); | |
1302 | rtx newaddr; | |
1303 | rtx addr_reg; | |
1304 | HOST_WIDE_INT newoffset; | |
1305 | ||
1306 | if (GET_CODE (elt) != SET | |
1307 | || GET_CODE (SET_DEST (elt)) != REG | |
1308 | || GET_MODE (SET_DEST (elt)) != SImode | |
1309 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
1310 | || GET_CODE (SET_SRC (elt)) != MEM | |
1311 | || GET_MODE (SET_SRC (elt)) != SImode) | |
1312 | return 0; | |
1313 | newaddr = XEXP (SET_SRC (elt), 0); | |
1314 | if (legitimate_indirect_address_p (newaddr, 0)) | |
1315 | { | |
1316 | newoffset = 0; | |
1317 | addr_reg = newaddr; | |
1318 | } | |
1319 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) | |
1320 | { | |
1321 | addr_reg = XEXP (newaddr, 0); | |
1322 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
1323 | } | |
1324 | else | |
1325 | return 0; | |
1326 | if (REGNO (addr_reg) != base_regno | |
1327 | || newoffset != offset + 4 * i) | |
1328 | return 0; | |
1329 | } | |
1330 | ||
1331 | return 1; | |
1332 | }) | |
1333 | ||
1334 | ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL. | |
1335 | (define_predicate "stmw_operation" | |
1336 | (match_code "parallel") | |
1337 | { | |
1338 | int count = XVECLEN (op, 0); | |
1339 | unsigned int src_regno; | |
1340 | rtx dest_addr; | |
1341 | unsigned int base_regno; | |
1342 | HOST_WIDE_INT offset; | |
1343 | int i; | |
1344 | ||
1345 | /* Perform a quick check so we don't blow up below. */ | |
1346 | if (count <= 1 | |
1347 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1348 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
1349 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
1350 | return 0; | |
1351 | ||
1352 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
1353 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
1354 | ||
1355 | if (src_regno > 31 | |
1356 | || count != 32 - (int) src_regno) | |
1357 | return 0; | |
1358 | ||
1359 | if (legitimate_indirect_address_p (dest_addr, 0)) | |
1360 | { | |
1361 | offset = 0; | |
1362 | base_regno = REGNO (dest_addr); | |
1363 | if (base_regno == 0) | |
1364 | return 0; | |
1365 | } | |
1366 | else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0)) | |
1367 | { | |
1368 | offset = INTVAL (XEXP (dest_addr, 1)); | |
1369 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
1370 | } | |
1371 | else | |
1372 | return 0; | |
1373 | ||
1374 | for (i = 0; i < count; i++) | |
1375 | { | |
1376 | rtx elt = XVECEXP (op, 0, i); | |
1377 | rtx newaddr; | |
1378 | rtx addr_reg; | |
1379 | HOST_WIDE_INT newoffset; | |
1380 | ||
1381 | if (GET_CODE (elt) != SET | |
1382 | || GET_CODE (SET_SRC (elt)) != REG | |
1383 | || GET_MODE (SET_SRC (elt)) != SImode | |
1384 | || REGNO (SET_SRC (elt)) != src_regno + i | |
1385 | || GET_CODE (SET_DEST (elt)) != MEM | |
1386 | || GET_MODE (SET_DEST (elt)) != SImode) | |
1387 | return 0; | |
1388 | newaddr = XEXP (SET_DEST (elt), 0); | |
1389 | if (legitimate_indirect_address_p (newaddr, 0)) | |
1390 | { | |
1391 | newoffset = 0; | |
1392 | addr_reg = newaddr; | |
1393 | } | |
1394 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) | |
1395 | { | |
1396 | addr_reg = XEXP (newaddr, 0); | |
1397 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
1398 | } | |
1399 | else | |
1400 | return 0; | |
1401 | if (REGNO (addr_reg) != base_regno | |
1402 | || newoffset != offset + 4 * i) | |
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | return 1; | |
1407 | }) |