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48d72335 | 1 | ;; Predicate definitions for POWER and PowerPC. |
00b79d54 | 2 | ;; Copyright (C) 2005, 2006 Free Software Foundation, Inc. |
48d72335 DE |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 2, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING. If not, write to | |
39d14dda KC |
18 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
19 | ;; Boston, MA 02110-1301, USA. | |
48d72335 DE |
20 | |
21 | ;; Return 1 for anything except PARALLEL. | |
22 | (define_predicate "any_operand" | |
23 | (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")) | |
24 | ||
25 | ;; Return 1 for any PARALLEL. | |
26 | (define_predicate "any_parallel_operand" | |
27 | (match_code "parallel")) | |
28 | ||
29 | ;; Return 1 if op is COUNT register. | |
30 | (define_predicate "count_register_operand" | |
31 | (and (match_code "reg") | |
32 | (match_test "REGNO (op) == COUNT_REGISTER_REGNUM | |
33 | || REGNO (op) > LAST_VIRTUAL_REGISTER"))) | |
34 | ||
35 | ;; Return 1 if op is an Altivec register. | |
36 | (define_predicate "altivec_register_operand" | |
5b296c8a DE |
37 | (and (match_operand 0 "register_operand") |
38 | (match_test "GET_CODE (op) != REG | |
39 | || ALTIVEC_REGNO_P (REGNO (op)) | |
40 | || REGNO (op) > LAST_VIRTUAL_REGISTER"))) | |
48d72335 DE |
41 | |
42 | ;; Return 1 if op is XER register. | |
43 | (define_predicate "xer_operand" | |
44 | (and (match_code "reg") | |
45 | (match_test "XER_REGNO_P (REGNO (op))"))) | |
46 | ||
afca671b DP |
47 | ;; Return 1 if op is a signed 5-bit constant integer. |
48 | (define_predicate "s5bit_cint_operand" | |
49 | (and (match_code "const_int") | |
50 | (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) | |
51 | ||
52 | ;; Return 1 if op is a unsigned 5-bit constant integer. | |
53 | (define_predicate "u5bit_cint_operand" | |
54 | (and (match_code "const_int") | |
55 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) | |
56 | ||
48d72335 | 57 | ;; Return 1 if op is a signed 8-bit constant integer. |
c83eecad | 58 | ;; Integer multiplication complete more quickly |
48d72335 DE |
59 | (define_predicate "s8bit_cint_operand" |
60 | (and (match_code "const_int") | |
61 | (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) | |
62 | ||
63 | ;; Return 1 if op is a constant integer that can fit in a D field. | |
64 | (define_predicate "short_cint_operand" | |
65 | (and (match_code "const_int") | |
279bb624 | 66 | (match_test "satisfies_constraint_I (op)"))) |
48d72335 DE |
67 | |
68 | ;; Return 1 if op is a constant integer that can fit in an unsigned D field. | |
69 | (define_predicate "u_short_cint_operand" | |
70 | (and (match_code "const_int") | |
279bb624 | 71 | (match_test "satisfies_constraint_K (op)"))) |
48d72335 DE |
72 | |
73 | ;; Return 1 if op is a constant integer that cannot fit in a signed D field. | |
74 | (define_predicate "non_short_cint_operand" | |
75 | (and (match_code "const_int") | |
76 | (match_test "(unsigned HOST_WIDE_INT) | |
77 | (INTVAL (op) + 0x8000) >= 0x10000"))) | |
78 | ||
79 | ;; Return 1 if op is a positive constant integer that is an exact power of 2. | |
80 | (define_predicate "exact_log2_cint_operand" | |
81 | (and (match_code "const_int") | |
82 | (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) | |
83 | ||
84 | ;; Return 1 if op is a register that is not special. | |
85 | (define_predicate "gpc_reg_operand" | |
5b296c8a DE |
86 | (and (match_operand 0 "register_operand") |
87 | (match_test "GET_CODE (op) != REG | |
88 | || (REGNO (op) >= ARG_POINTER_REGNUM | |
89 | && !XER_REGNO_P (REGNO (op))) | |
90 | || REGNO (op) < MQ_REGNO"))) | |
48d72335 DE |
91 | |
92 | ;; Return 1 if op is a register that is a condition register field. | |
93 | (define_predicate "cc_reg_operand" | |
5b296c8a DE |
94 | (and (match_operand 0 "register_operand") |
95 | (match_test "GET_CODE (op) != REG | |
96 | || REGNO (op) > LAST_VIRTUAL_REGISTER | |
97 | || CR_REGNO_P (REGNO (op))"))) | |
48d72335 DE |
98 | |
99 | ;; Return 1 if op is a register that is a condition register field not cr0. | |
100 | (define_predicate "cc_reg_not_cr0_operand" | |
5b296c8a DE |
101 | (and (match_operand 0 "register_operand") |
102 | (match_test "GET_CODE (op) != REG | |
103 | || REGNO (op) > LAST_VIRTUAL_REGISTER | |
104 | || CR_REGNO_NOT_CR0_P (REGNO (op))"))) | |
48d72335 DE |
105 | |
106 | ;; Return 1 if op is a constant integer valid for D field | |
107 | ;; or non-special register register. | |
108 | (define_predicate "reg_or_short_operand" | |
109 | (if_then_else (match_code "const_int") | |
110 | (match_operand 0 "short_cint_operand") | |
111 | (match_operand 0 "gpc_reg_operand"))) | |
112 | ||
113 | ;; Return 1 if op is a constant integer valid whose negation is valid for | |
114 | ;; D field or non-special register register. | |
115 | ;; Do not allow a constant zero because all patterns that call this | |
116 | ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than | |
117 | ;; or equal to const, which does not work for zero. | |
118 | (define_predicate "reg_or_neg_short_operand" | |
119 | (if_then_else (match_code "const_int") | |
279bb624 | 120 | (match_test "satisfies_constraint_P (op) |
48d72335 DE |
121 | && INTVAL (op) != 0") |
122 | (match_operand 0 "gpc_reg_operand"))) | |
123 | ||
124 | ;; Return 1 if op is a constant integer valid for DS field | |
125 | ;; or non-special register. | |
126 | (define_predicate "reg_or_aligned_short_operand" | |
127 | (if_then_else (match_code "const_int") | |
128 | (and (match_operand 0 "short_cint_operand") | |
129 | (match_test "!(INTVAL (op) & 3)")) | |
130 | (match_operand 0 "gpc_reg_operand"))) | |
131 | ||
132 | ;; Return 1 if op is a constant integer whose high-order 16 bits are zero | |
133 | ;; or non-special register. | |
134 | (define_predicate "reg_or_u_short_operand" | |
135 | (if_then_else (match_code "const_int") | |
136 | (match_operand 0 "u_short_cint_operand") | |
137 | (match_operand 0 "gpc_reg_operand"))) | |
138 | ||
139 | ;; Return 1 if op is any constant integer | |
140 | ;; or non-special register. | |
141 | (define_predicate "reg_or_cint_operand" | |
142 | (ior (match_code "const_int") | |
143 | (match_operand 0 "gpc_reg_operand"))) | |
144 | ||
4ae234b0 | 145 | ;; Return 1 if op is a constant integer valid for addition |
48d72335 | 146 | ;; or non-special register. |
4ae234b0 | 147 | (define_predicate "reg_or_add_cint_operand" |
48d72335 | 148 | (if_then_else (match_code "const_int") |
4ae234b0 GK |
149 | (match_test "(HOST_BITS_PER_WIDE_INT == 32 |
150 | && (mode == SImode || INTVAL (op) < 0x7fff8000)) | |
94dcded2 | 151 | || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
48d72335 DE |
152 | < (unsigned HOST_WIDE_INT) 0x100000000ll)") |
153 | (match_operand 0 "gpc_reg_operand"))) | |
154 | ||
4ae234b0 | 155 | ;; Return 1 if op is a constant integer valid for subtraction |
48d72335 | 156 | ;; or non-special register. |
4ae234b0 | 157 | (define_predicate "reg_or_sub_cint_operand" |
48d72335 | 158 | (if_then_else (match_code "const_int") |
4ae234b0 GK |
159 | (match_test "(HOST_BITS_PER_WIDE_INT == 32 |
160 | && (mode == SImode || - INTVAL (op) < 0x7fff8000)) | |
161 | || ((unsigned HOST_WIDE_INT) (- INTVAL (op) | |
162 | + (mode == SImode | |
163 | ? 0x80000000 : 0x80008000)) | |
48d72335 DE |
164 | < (unsigned HOST_WIDE_INT) 0x100000000ll)") |
165 | (match_operand 0 "gpc_reg_operand"))) | |
166 | ||
167 | ;; Return 1 if op is any 32-bit unsigned constant integer | |
168 | ;; or non-special register. | |
169 | (define_predicate "reg_or_logical_cint_operand" | |
170 | (if_then_else (match_code "const_int") | |
171 | (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT | |
172 | && INTVAL (op) >= 0) | |
173 | || ((INTVAL (op) & GET_MODE_MASK (mode) | |
174 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") | |
175 | (if_then_else (match_code "const_double") | |
176 | (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT | |
177 | && mode == DImode | |
178 | && CONST_DOUBLE_HIGH (op) == 0") | |
179 | (match_operand 0 "gpc_reg_operand")))) | |
180 | ||
181 | ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register | |
182 | ;; with no more than one instruction per word. | |
183 | (define_predicate "easy_fp_constant" | |
184 | (match_code "const_double") | |
185 | { | |
992d08b1 NS |
186 | long k[4]; |
187 | REAL_VALUE_TYPE rv; | |
188 | ||
48d72335 | 189 | if (GET_MODE (op) != mode |
ebb109ad | 190 | || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode)) |
48d72335 DE |
191 | return 0; |
192 | ||
193 | /* Consider all constants with -msoft-float to be easy. */ | |
194 | if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) | |
195 | && mode != DImode) | |
196 | return 1; | |
197 | ||
00b79d54 BE |
198 | if (DECIMAL_FLOAT_MODE_P (mode)) |
199 | return 0; | |
200 | ||
48d72335 DE |
201 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
202 | if (flag_pic && DEFAULT_ABI == ABI_V4) | |
203 | return 0; | |
204 | ||
205 | #ifdef TARGET_RELOCATABLE | |
206 | /* Similarly if we are using -mrelocatable, consider all constants | |
207 | to be hard. */ | |
208 | if (TARGET_RELOCATABLE) | |
209 | return 0; | |
210 | #endif | |
211 | ||
992d08b1 | 212 | switch (mode) |
48d72335 | 213 | { |
992d08b1 | 214 | case TFmode: |
48d72335 DE |
215 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
216 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
217 | ||
218 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
219 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
220 | && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
221 | && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
48d72335 | 222 | |
992d08b1 | 223 | case DFmode: |
b6dc5507 DE |
224 | /* Force constants to memory before reload to utilize |
225 | compress_float_constant. | |
226 | Avoid this when flag_unsafe_math_optimizations is enabled | |
227 | because RDIV division to reciprocal optimization is not able | |
228 | to regenerate the division. */ | |
229 | if (TARGET_E500_DOUBLE | |
230 | || (!reload_in_progress && !reload_completed | |
231 | && !flag_unsafe_math_optimizations)) | |
232 | return 0; | |
48d72335 DE |
233 | |
234 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
235 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
236 | ||
237 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
238 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
48d72335 | 239 | |
992d08b1 | 240 | case SFmode: |
8308679f DE |
241 | /* The constant 0.f is easy. */ |
242 | if (op == CONST0_RTX (SFmode)) | |
243 | return 1; | |
244 | ||
b6dc5507 DE |
245 | /* Force constants to memory before reload to utilize |
246 | compress_float_constant. | |
247 | Avoid this when flag_unsafe_math_optimizations is enabled | |
248 | because RDIV division to reciprocal optimization is not able | |
249 | to regenerate the division. */ | |
250 | if (!reload_in_progress && !reload_completed | |
251 | && !flag_unsafe_math_optimizations) | |
252 | return 0; | |
253 | ||
48d72335 | 254 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
992d08b1 | 255 | REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]); |
48d72335 | 256 | |
992d08b1 | 257 | return num_insns_constant_wide (k[0]) == 1; |
48d72335 | 258 | |
992d08b1 | 259 | case DImode: |
48d72335 DE |
260 | return ((TARGET_POWERPC64 |
261 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) | |
262 | || (num_insns_constant (op, DImode) <= 2)); | |
263 | ||
992d08b1 | 264 | case SImode: |
48d72335 | 265 | return 1; |
992d08b1 NS |
266 | |
267 | default: | |
268 | gcc_unreachable (); | |
269 | } | |
48d72335 DE |
270 | }) |
271 | ||
272 | ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a | |
273 | ;; vector register without using memory. | |
274 | (define_predicate "easy_vector_constant" | |
275 | (match_code "const_vector") | |
276 | { | |
66180ff3 PB |
277 | if (ALTIVEC_VECTOR_MODE (mode)) |
278 | { | |
279 | if (zero_constant (op, mode)) | |
280 | return true; | |
281 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) | |
282 | return false; | |
48d72335 | 283 | |
66180ff3 PB |
284 | return easy_altivec_constant (op, mode); |
285 | } | |
48d72335 | 286 | |
66180ff3 | 287 | if (SPE_VECTOR_MODE (mode)) |
48d72335 | 288 | { |
66180ff3 PB |
289 | int cst, cst2; |
290 | if (zero_constant (op, mode)) | |
291 | return true; | |
292 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) | |
293 | return false; | |
294 | ||
295 | /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
296 | li r0, CONSTANT1 | |
297 | evmergelo r0, r0, r0 | |
298 | li r0, CONSTANT2 | |
299 | ||
300 | I don't know how efficient it would be to allow bigger constants, | |
301 | considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
302 | instructions is better than a 64-bit memory load, but I don't | |
303 | have the e500 timing specs. */ | |
304 | if (mode == V2SImode) | |
305 | { | |
306 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
307 | cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
308 | return cst >= -0x7fff && cst <= 0x7fff | |
309 | && cst2 >= -0x7fff && cst2 <= 0x7fff; | |
310 | } | |
48d72335 | 311 | } |
66180ff3 PB |
312 | |
313 | return false; | |
48d72335 DE |
314 | }) |
315 | ||
316 | ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. | |
317 | (define_predicate "easy_vector_constant_add_self" | |
318 | (and (match_code "const_vector") | |
319 | (and (match_test "TARGET_ALTIVEC") | |
66180ff3 PB |
320 | (match_test "easy_altivec_constant (op, mode)"))) |
321 | { | |
322 | rtx last = CONST_VECTOR_ELT (op, GET_MODE_NUNITS (mode) - 1); | |
8f7bb6d7 | 323 | HOST_WIDE_INT val = ((INTVAL (last) & 0xff) ^ 0x80) - 0x80; |
66180ff3 PB |
324 | return EASY_VECTOR_15_ADD_SELF (val); |
325 | }) | |
48d72335 DE |
326 | |
327 | ;; Return 1 if operand is constant zero (scalars and vectors). | |
328 | (define_predicate "zero_constant" | |
329 | (and (match_code "const_int,const_double,const_vector") | |
330 | (match_test "op == CONST0_RTX (mode)"))) | |
331 | ||
332 | ;; Return 1 if operand is 0.0. | |
333 | ;; or non-special register register field no cr0 | |
334 | (define_predicate "zero_fp_constant" | |
335 | (and (match_code "const_double") | |
ebb109ad | 336 | (match_test "SCALAR_FLOAT_MODE_P (mode) |
48d72335 DE |
337 | && op == CONST0_RTX (mode)"))) |
338 | ||
339 | ;; Return 1 if the operand is in volatile memory. Note that during the | |
340 | ;; RTL generation phase, memory_operand does not return TRUE for volatile | |
341 | ;; memory references. So this function allows us to recognize volatile | |
f3b569ca | 342 | ;; references where it's safe. |
48d72335 DE |
343 | (define_predicate "volatile_mem_operand" |
344 | (and (and (match_code "mem") | |
345 | (match_test "MEM_VOLATILE_P (op)")) | |
346 | (if_then_else (match_test "reload_completed") | |
347 | (match_operand 0 "memory_operand") | |
348 | (if_then_else (match_test "reload_in_progress") | |
349 | (match_test "strict_memory_address_p (mode, XEXP (op, 0))") | |
350 | (match_test "memory_address_p (mode, XEXP (op, 0))"))))) | |
351 | ||
352 | ;; Return 1 if the operand is an offsettable memory operand. | |
353 | (define_predicate "offsettable_mem_operand" | |
354 | (and (match_code "mem") | |
355 | (match_test "offsettable_address_p (reload_completed | |
356 | || reload_in_progress, | |
357 | mode, XEXP (op, 0))"))) | |
358 | ||
b6d2248c GK |
359 | ;; Return 1 if the operand is a memory operand with an address divisible by 4 |
360 | (define_predicate "word_offset_memref_operand" | |
361 | (and (match_operand 0 "memory_operand") | |
362 | (match_test "GET_CODE (XEXP (op, 0)) != PLUS | |
363 | || ! REG_P (XEXP (XEXP (op, 0), 0)) | |
364 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT | |
365 | || INTVAL (XEXP (XEXP (op, 0), 1)) % 4 == 0"))) | |
366 | ||
bf00cc0f AM |
367 | ;; Return 1 if the operand is an indexed or indirect memory operand. |
368 | (define_predicate "indexed_or_indirect_operand" | |
369 | (match_code "mem") | |
370 | { | |
371 | op = XEXP (op, 0); | |
372 | if (TARGET_ALTIVEC | |
373 | && ALTIVEC_VECTOR_MODE (mode) | |
374 | && GET_CODE (op) == AND | |
375 | && GET_CODE (XEXP (op, 1)) == CONST_INT | |
376 | && INTVAL (XEXP (op, 1)) == -16) | |
377 | op = XEXP (op, 0); | |
378 | ||
379 | return indexed_or_indirect_address (op, mode); | |
380 | }) | |
381 | ||
11aac14f | 382 | ;; Return 1 if the operand is an indexed or indirect address. |
bf00cc0f AM |
383 | (define_special_predicate "indexed_or_indirect_address" |
384 | (and (match_test "REG_P (op) | |
11aac14f | 385 | || (GET_CODE (op) == PLUS |
bf00cc0f AM |
386 | /* Omit testing REG_P (XEXP (op, 0)). */ |
387 | && REG_P (XEXP (op, 1)))") | |
388 | (match_operand 0 "address_operand"))) | |
11aac14f | 389 | |
045a8eb3 GK |
390 | ;; Used for the destination of the fix_truncdfsi2 expander. |
391 | ;; If stfiwx will be used, the result goes to memory; otherwise, | |
392 | ;; we're going to emit a store and a load of a subreg, so the dest is a | |
393 | ;; register. | |
394 | (define_predicate "fix_trunc_dest_operand" | |
395 | (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT") | |
396 | (match_operand 0 "memory_operand") | |
397 | (match_operand 0 "gpc_reg_operand"))) | |
398 | ||
48d72335 DE |
399 | ;; Return 1 if the operand is either a non-special register or can be used |
400 | ;; as the operand of a `mode' add insn. | |
401 | (define_predicate "add_operand" | |
402 | (if_then_else (match_code "const_int") | |
279bb624 DE |
403 | (match_test "satisfies_constraint_I (op) |
404 | || satisfies_constraint_L (op)") | |
48d72335 DE |
405 | (match_operand 0 "gpc_reg_operand"))) |
406 | ||
407 | ;; Return 1 if OP is a constant but not a valid add_operand. | |
408 | (define_predicate "non_add_cint_operand" | |
409 | (and (match_code "const_int") | |
279bb624 DE |
410 | (match_test "!satisfies_constraint_I (op) |
411 | && !satisfies_constraint_L (op)"))) | |
48d72335 | 412 | |
410c459d PB |
413 | ;; Return 1 if the operand is a constant that can be used as the operand |
414 | ;; of an OR or XOR. | |
415 | (define_predicate "logical_const_operand" | |
416 | (match_code "const_int,const_double") | |
48d72335 DE |
417 | { |
418 | HOST_WIDE_INT opl, oph; | |
419 | ||
48d72335 DE |
420 | if (GET_CODE (op) == CONST_INT) |
421 | { | |
422 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
423 | ||
424 | if (HOST_BITS_PER_WIDE_INT <= 32 | |
425 | && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
426 | return 0; | |
427 | } | |
428 | else if (GET_CODE (op) == CONST_DOUBLE) | |
429 | { | |
992d08b1 | 430 | gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT); |
48d72335 DE |
431 | |
432 | opl = CONST_DOUBLE_LOW (op); | |
433 | oph = CONST_DOUBLE_HIGH (op); | |
434 | if (oph != 0) | |
435 | return 0; | |
436 | } | |
437 | else | |
438 | return 0; | |
439 | ||
440 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 | |
441 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
442 | }) | |
443 | ||
410c459d PB |
444 | ;; Return 1 if the operand is a non-special register or a constant that |
445 | ;; can be used as the operand of an OR or XOR. | |
446 | (define_predicate "logical_operand" | |
447 | (ior (match_operand 0 "gpc_reg_operand") | |
448 | (match_operand 0 "logical_const_operand"))) | |
449 | ||
48d72335 DE |
450 | ;; Return 1 if op is a constant that is not a logical operand, but could |
451 | ;; be split into one. | |
452 | (define_predicate "non_logical_cint_operand" | |
453 | (and (match_code "const_int,const_double") | |
454 | (and (not (match_operand 0 "logical_operand")) | |
455 | (match_operand 0 "reg_or_logical_cint_operand")))) | |
456 | ||
1990cd79 AM |
457 | ;; Return 1 if op is a constant that can be encoded in a 32-bit mask, |
458 | ;; suitable for use with rlwinm (no more than two 1->0 or 0->1 | |
459 | ;; transitions). Reject all ones and all zeros, since these should have | |
460 | ;; been optimized away and confuse the making of MB and ME. | |
48d72335 DE |
461 | (define_predicate "mask_operand" |
462 | (match_code "const_int") | |
463 | { | |
464 | HOST_WIDE_INT c, lsb; | |
465 | ||
466 | c = INTVAL (op); | |
467 | ||
1990cd79 AM |
468 | if (TARGET_POWERPC64) |
469 | { | |
470 | /* Fail if the mask is not 32-bit. */ | |
471 | if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0) | |
472 | return 0; | |
4ae234b0 | 473 | |
1990cd79 AM |
474 | /* Fail if the mask wraps around because the upper 32-bits of the |
475 | mask will all be 1s, contrary to GCC's internal view. */ | |
476 | if ((c & 0x80000001) == 0x80000001) | |
477 | return 0; | |
478 | } | |
48d72335 DE |
479 | |
480 | /* We don't change the number of transitions by inverting, | |
481 | so make sure we start with the LS bit zero. */ | |
482 | if (c & 1) | |
483 | c = ~c; | |
484 | ||
1990cd79 AM |
485 | /* Reject all zeros or all ones. */ |
486 | if (c == 0) | |
487 | return 0; | |
488 | ||
48d72335 DE |
489 | /* Find the first transition. */ |
490 | lsb = c & -c; | |
491 | ||
1990cd79 AM |
492 | /* Invert to look for a second transition. */ |
493 | c = ~c; | |
48d72335 | 494 | |
1990cd79 AM |
495 | /* Erase first transition. */ |
496 | c &= -lsb; | |
48d72335 | 497 | |
1990cd79 AM |
498 | /* Find the second transition (if any). */ |
499 | lsb = c & -c; | |
48d72335 DE |
500 | |
501 | /* Match if all the bits above are 1's (or c is zero). */ | |
502 | return c == -lsb; | |
503 | }) | |
504 | ||
505 | ;; Return 1 for the PowerPC64 rlwinm corner case. | |
506 | (define_predicate "mask_operand_wrap" | |
507 | (match_code "const_int") | |
508 | { | |
509 | HOST_WIDE_INT c, lsb; | |
510 | ||
511 | c = INTVAL (op); | |
512 | ||
513 | if ((c & 0x80000001) != 0x80000001) | |
514 | return 0; | |
515 | ||
516 | c = ~c; | |
517 | if (c == 0) | |
518 | return 0; | |
519 | ||
520 | lsb = c & -c; | |
521 | c = ~c; | |
522 | c &= -lsb; | |
523 | lsb = c & -c; | |
524 | return c == -lsb; | |
525 | }) | |
526 | ||
1990cd79 AM |
527 | ;; Return 1 if the operand is a constant that is a PowerPC64 mask |
528 | ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1 | |
529 | ;; transition). Reject all zeros, since zero should have been | |
530 | ;; optimized away and confuses the making of MB and ME. | |
531 | (define_predicate "mask64_operand" | |
532 | (match_code "const_int") | |
533 | { | |
534 | HOST_WIDE_INT c, lsb; | |
535 | ||
536 | c = INTVAL (op); | |
537 | ||
538 | /* Reject all zeros. */ | |
539 | if (c == 0) | |
540 | return 0; | |
541 | ||
542 | /* We don't change the number of transitions by inverting, | |
543 | so make sure we start with the LS bit zero. */ | |
544 | if (c & 1) | |
545 | c = ~c; | |
546 | ||
547 | /* Find the first transition. */ | |
548 | lsb = c & -c; | |
549 | ||
550 | /* Match if all the bits above are 1's (or c is zero). */ | |
551 | return c == -lsb; | |
552 | }) | |
553 | ||
554 | ;; Like mask64_operand, but allow up to three transitions. This | |
48d72335 DE |
555 | ;; predicate is used by insn patterns that generate two rldicl or |
556 | ;; rldicr machine insns. | |
557 | (define_predicate "mask64_2_operand" | |
558 | (match_code "const_int") | |
559 | { | |
1990cd79 AM |
560 | HOST_WIDE_INT c, lsb; |
561 | ||
562 | c = INTVAL (op); | |
563 | ||
564 | /* Disallow all zeros. */ | |
565 | if (c == 0) | |
566 | return 0; | |
567 | ||
568 | /* We don't change the number of transitions by inverting, | |
569 | so make sure we start with the LS bit zero. */ | |
570 | if (c & 1) | |
571 | c = ~c; | |
572 | ||
573 | /* Find the first transition. */ | |
574 | lsb = c & -c; | |
575 | ||
576 | /* Invert to look for a second transition. */ | |
577 | c = ~c; | |
578 | ||
579 | /* Erase first transition. */ | |
580 | c &= -lsb; | |
581 | ||
582 | /* Find the second transition. */ | |
583 | lsb = c & -c; | |
584 | ||
585 | /* Invert to look for a third transition. */ | |
586 | c = ~c; | |
587 | ||
588 | /* Erase second transition. */ | |
589 | c &= -lsb; | |
590 | ||
591 | /* Find the third transition (if any). */ | |
592 | lsb = c & -c; | |
593 | ||
594 | /* Match if all the bits above are 1's (or c is zero). */ | |
595 | return c == -lsb; | |
48d72335 DE |
596 | }) |
597 | ||
4ae234b0 | 598 | ;; Like and_operand, but also match constants that can be implemented |
48d72335 DE |
599 | ;; with two rldicl or rldicr insns. |
600 | (define_predicate "and64_2_operand" | |
1990cd79 | 601 | (ior (match_operand 0 "mask64_2_operand") |
334269b9 DE |
602 | (if_then_else (match_test "fixed_regs[CR0_REGNO]") |
603 | (match_operand 0 "gpc_reg_operand") | |
604 | (match_operand 0 "logical_operand")))) | |
48d72335 DE |
605 | |
606 | ;; Return 1 if the operand is either a non-special register or a | |
607 | ;; constant that can be used as the operand of a logical AND. | |
608 | (define_predicate "and_operand" | |
334269b9 | 609 | (ior (match_operand 0 "mask_operand") |
1990cd79 AM |
610 | (ior (and (match_test "TARGET_POWERPC64 && mode == DImode") |
611 | (match_operand 0 "mask64_operand")) | |
612 | (if_then_else (match_test "fixed_regs[CR0_REGNO]") | |
613 | (match_operand 0 "gpc_reg_operand") | |
614 | (match_operand 0 "logical_operand"))))) | |
48d72335 | 615 | |
e9441276 DE |
616 | ;; Return 1 if the operand is either a logical operand or a short cint operand. |
617 | (define_predicate "scc_eq_operand" | |
618 | (ior (match_operand 0 "logical_operand") | |
619 | (match_operand 0 "short_cint_operand"))) | |
620 | ||
48d72335 DE |
621 | ;; Return 1 if the operand is a general non-special register or memory operand. |
622 | (define_predicate "reg_or_mem_operand" | |
48d72335 | 623 | (ior (match_operand 0 "memory_operand") |
fc0d1c49 BE |
624 | (ior (and (match_code "mem") |
625 | (match_test "macho_lo_sum_memory_operand (op, mode)")) | |
626 | (ior (match_operand 0 "volatile_mem_operand") | |
627 | (match_operand 0 "gpc_reg_operand"))))) | |
48d72335 | 628 | |
97c54d9a DE |
629 | ;; Return 1 if the operand is either an easy FP constant or memory or reg. |
630 | (define_predicate "reg_or_none500mem_operand" | |
631 | (if_then_else (match_code "mem") | |
632 | (and (match_test "!TARGET_E500_DOUBLE") | |
633 | (ior (match_operand 0 "memory_operand") | |
634 | (ior (match_test "macho_lo_sum_memory_operand (op, mode)") | |
635 | (match_operand 0 "volatile_mem_operand")))) | |
636 | (match_operand 0 "gpc_reg_operand"))) | |
637 | ||
638 | ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand. | |
639 | (define_predicate "zero_reg_mem_operand" | |
640 | (ior (match_operand 0 "zero_fp_constant") | |
641 | (match_operand 0 "reg_or_mem_operand"))) | |
642 | ||
48d72335 DE |
643 | ;; Return 1 if the operand is a general register or memory operand without |
644 | ;; pre_inc or pre_dec, which produces invalid form of PowerPC lwa | |
645 | ;; instruction. | |
646 | (define_predicate "lwa_operand" | |
647 | (match_code "reg,subreg,mem") | |
648 | { | |
649 | rtx inner = op; | |
650 | ||
651 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
652 | inner = SUBREG_REG (inner); | |
653 | ||
654 | return gpc_reg_operand (inner, mode) | |
655 | || (memory_operand (inner, mode) | |
656 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
657 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC | |
658 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
659 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT | |
660 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
661 | }) | |
662 | ||
663 | ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. | |
664 | (define_predicate "symbol_ref_operand" | |
665 | (and (match_code "symbol_ref") | |
666 | (match_test "(mode == VOIDmode || GET_MODE (op) == mode) | |
667 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))"))) | |
668 | ||
669 | ;; Return 1 if op is an operand that can be loaded via the GOT. | |
670 | ;; or non-special register register field no cr0 | |
671 | (define_predicate "got_operand" | |
672 | (match_code "symbol_ref,const,label_ref")) | |
673 | ||
674 | ;; Return 1 if op is a simple reference that can be loaded via the GOT, | |
aabcd309 | 675 | ;; excluding labels involving addition. |
48d72335 DE |
676 | (define_predicate "got_no_const_operand" |
677 | (match_code "symbol_ref,label_ref")) | |
678 | ||
679 | ;; Return 1 if op is a SYMBOL_REF for a TLS symbol. | |
680 | (define_predicate "rs6000_tls_symbol_ref" | |
681 | (and (match_code "symbol_ref") | |
682 | (match_test "RS6000_SYMBOL_REF_TLS_P (op)"))) | |
683 | ||
684 | ;; Return 1 if the operand, used inside a MEM, is a valid first argument | |
685 | ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. | |
686 | (define_predicate "call_operand" | |
687 | (if_then_else (match_code "reg") | |
688 | (match_test "REGNO (op) == LINK_REGISTER_REGNUM | |
689 | || REGNO (op) == COUNT_REGISTER_REGNUM | |
690 | || REGNO (op) >= FIRST_PSEUDO_REGISTER") | |
691 | (match_code "symbol_ref"))) | |
692 | ||
693 | ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
694 | ;; this file. | |
695 | (define_predicate "current_file_function_operand" | |
696 | (and (match_code "symbol_ref") | |
697 | (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
698 | && (SYMBOL_REF_LOCAL_P (op) | |
699 | || (op == XEXP (DECL_RTL (current_function_decl), | |
700 | 0)))"))) | |
701 | ||
702 | ;; Return 1 if this operand is a valid input for a move insn. | |
703 | (define_predicate "input_operand" | |
704 | (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem, | |
705 | const_double,const_vector,const_int,plus") | |
706 | { | |
707 | /* Memory is always valid. */ | |
708 | if (memory_operand (op, mode)) | |
709 | return 1; | |
710 | ||
711 | /* For floating-point, easy constants are valid. */ | |
ebb109ad | 712 | if (SCALAR_FLOAT_MODE_P (mode) |
48d72335 DE |
713 | && CONSTANT_P (op) |
714 | && easy_fp_constant (op, mode)) | |
715 | return 1; | |
716 | ||
717 | /* Allow any integer constant. */ | |
718 | if (GET_MODE_CLASS (mode) == MODE_INT | |
719 | && (GET_CODE (op) == CONST_INT | |
720 | || GET_CODE (op) == CONST_DOUBLE)) | |
721 | return 1; | |
722 | ||
723 | /* Allow easy vector constants. */ | |
724 | if (GET_CODE (op) == CONST_VECTOR | |
725 | && easy_vector_constant (op, mode)) | |
726 | return 1; | |
727 | ||
728 | /* For floating-point or multi-word mode, the only remaining valid type | |
729 | is a register. */ | |
ebb109ad | 730 | if (SCALAR_FLOAT_MODE_P (mode) |
48d72335 DE |
731 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) |
732 | return register_operand (op, mode); | |
733 | ||
734 | /* The only cases left are integral modes one word or smaller (we | |
735 | do not get called for MODE_CC values). These can be in any | |
736 | register. */ | |
737 | if (register_operand (op, mode)) | |
738 | return 1; | |
739 | ||
740 | /* A SYMBOL_REF referring to the TOC is valid. */ | |
741 | if (legitimate_constant_pool_address_p (op)) | |
742 | return 1; | |
743 | ||
744 | /* A constant pool expression (relative to the TOC) is valid */ | |
745 | if (toc_relative_expr_p (op)) | |
746 | return 1; | |
747 | ||
748 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region | |
749 | to be valid. */ | |
750 | if (DEFAULT_ABI == ABI_V4 | |
751 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) | |
752 | && small_data_operand (op, Pmode)) | |
753 | return 1; | |
754 | ||
755 | return 0; | |
756 | }) | |
757 | ||
758 | ;; Return true if OP is an invalid SUBREG operation on the e500. | |
759 | (define_predicate "rs6000_nonimmediate_operand" | |
760 | (match_code "reg,subreg,mem") | |
761 | { | |
762 | if (TARGET_E500_DOUBLE | |
763 | && GET_CODE (op) == SUBREG | |
764 | && invalid_e500_subreg (op, mode)) | |
765 | return 0; | |
766 | ||
767 | return nonimmediate_operand (op, mode); | |
768 | }) | |
769 | ||
770 | ;; Return true if operand is boolean operator. | |
771 | (define_predicate "boolean_operator" | |
772 | (match_code "and,ior,xor")) | |
773 | ||
774 | ;; Return true if operand is OR-form of boolean operator. | |
775 | (define_predicate "boolean_or_operator" | |
776 | (match_code "ior,xor")) | |
777 | ||
28d0e143 PB |
778 | ;; Return true if operand is an equality operator. |
779 | (define_special_predicate "equality_operator" | |
780 | (match_code "eq,ne")) | |
781 | ||
48d72335 DE |
782 | ;; Return true if operand is MIN or MAX operator. |
783 | (define_predicate "min_max_operator" | |
784 | (match_code "smin,smax,umin,umax")) | |
785 | ||
786 | ;; Return 1 if OP is a comparison operation that is valid for a branch | |
57a71826 DE |
787 | ;; instruction. We check the opcode against the mode of the CC value. |
788 | ;; validate_condition_mode is an assertion. | |
364849ee | 789 | (define_predicate "branch_comparison_operator" |
ede62875 DE |
790 | (and (match_operand 0 "comparison_operator") |
791 | (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC") | |
792 | (match_test "validate_condition_mode (GET_CODE (op), | |
793 | GET_MODE (XEXP (op, 0))), | |
794 | 1")))) | |
48d72335 DE |
795 | |
796 | ;; Return 1 if OP is a comparison operation that is valid for an SCC insn -- | |
797 | ;; it must be a positive comparison. | |
364849ee | 798 | (define_predicate "scc_comparison_operator" |
ede62875 DE |
799 | (and (match_operand 0 "branch_comparison_operator") |
800 | (match_code "eq,lt,gt,ltu,gtu,unordered"))) | |
48d72335 DE |
801 | |
802 | ;; Return 1 if OP is a comparison operation that is valid for a branch | |
803 | ;; insn, which is true if the corresponding bit in the CC register is set. | |
364849ee | 804 | (define_predicate "branch_positive_comparison_operator" |
ede62875 DE |
805 | (and (match_operand 0 "branch_comparison_operator") |
806 | (match_code "eq,lt,gt,ltu,gtu,unordered"))) | |
48d72335 DE |
807 | |
808 | ;; Return 1 is OP is a comparison operation that is valid for a trap insn. | |
809 | (define_predicate "trap_comparison_operator" | |
ede62875 DE |
810 | (and (match_operand 0 "comparison_operator") |
811 | (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu"))) | |
48d72335 DE |
812 | |
813 | ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL. | |
814 | (define_predicate "load_multiple_operation" | |
815 | (match_code "parallel") | |
816 | { | |
817 | int count = XVECLEN (op, 0); | |
818 | unsigned int dest_regno; | |
819 | rtx src_addr; | |
820 | int i; | |
821 | ||
822 | /* Perform a quick check so we don't blow up below. */ | |
823 | if (count <= 1 | |
824 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
825 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
826 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
827 | return 0; | |
828 | ||
829 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
830 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
831 | ||
832 | for (i = 1; i < count; i++) | |
833 | { | |
834 | rtx elt = XVECEXP (op, 0, i); | |
835 | ||
836 | if (GET_CODE (elt) != SET | |
837 | || GET_CODE (SET_DEST (elt)) != REG | |
838 | || GET_MODE (SET_DEST (elt)) != SImode | |
839 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
840 | || GET_CODE (SET_SRC (elt)) != MEM | |
841 | || GET_MODE (SET_SRC (elt)) != SImode | |
842 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
843 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
844 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
845 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
846 | return 0; | |
847 | } | |
848 | ||
849 | return 1; | |
850 | }) | |
851 | ||
852 | ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL. | |
853 | ;; The second vector element is a CLOBBER. | |
854 | (define_predicate "store_multiple_operation" | |
855 | (match_code "parallel") | |
856 | { | |
857 | int count = XVECLEN (op, 0) - 1; | |
858 | unsigned int src_regno; | |
859 | rtx dest_addr; | |
860 | int i; | |
861 | ||
862 | /* Perform a quick check so we don't blow up below. */ | |
863 | if (count <= 1 | |
864 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
865 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
866 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
867 | return 0; | |
868 | ||
869 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
870 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
871 | ||
872 | for (i = 1; i < count; i++) | |
873 | { | |
874 | rtx elt = XVECEXP (op, 0, i + 1); | |
875 | ||
876 | if (GET_CODE (elt) != SET | |
877 | || GET_CODE (SET_SRC (elt)) != REG | |
878 | || GET_MODE (SET_SRC (elt)) != SImode | |
879 | || REGNO (SET_SRC (elt)) != src_regno + i | |
880 | || GET_CODE (SET_DEST (elt)) != MEM | |
881 | || GET_MODE (SET_DEST (elt)) != SImode | |
882 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
883 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
884 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
885 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
886 | return 0; | |
887 | } | |
888 | ||
889 | return 1; | |
890 | }) | |
891 | ||
892 | ;; Return 1 if OP is valid for a save_world call in prologue, known to be | |
893 | ;; a PARLLEL. | |
894 | (define_predicate "save_world_operation" | |
895 | (match_code "parallel") | |
896 | { | |
897 | int index; | |
898 | int i; | |
899 | rtx elt; | |
900 | int count = XVECLEN (op, 0); | |
901 | ||
902 | if (count != 55) | |
903 | return 0; | |
904 | ||
905 | index = 0; | |
906 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
907 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
908 | return 0; | |
909 | ||
910 | for (i=1; i <= 18; i++) | |
911 | { | |
912 | elt = XVECEXP (op, 0, index++); | |
913 | if (GET_CODE (elt) != SET | |
914 | || GET_CODE (SET_DEST (elt)) != MEM | |
915 | || ! memory_operand (SET_DEST (elt), DFmode) | |
916 | || GET_CODE (SET_SRC (elt)) != REG | |
917 | || GET_MODE (SET_SRC (elt)) != DFmode) | |
918 | return 0; | |
919 | } | |
920 | ||
921 | for (i=1; i <= 12; i++) | |
922 | { | |
923 | elt = XVECEXP (op, 0, index++); | |
924 | if (GET_CODE (elt) != SET | |
925 | || GET_CODE (SET_DEST (elt)) != MEM | |
926 | || GET_CODE (SET_SRC (elt)) != REG | |
927 | || GET_MODE (SET_SRC (elt)) != V4SImode) | |
928 | return 0; | |
929 | } | |
930 | ||
931 | for (i=1; i <= 19; i++) | |
932 | { | |
933 | elt = XVECEXP (op, 0, index++); | |
934 | if (GET_CODE (elt) != SET | |
935 | || GET_CODE (SET_DEST (elt)) != MEM | |
936 | || ! memory_operand (SET_DEST (elt), Pmode) | |
937 | || GET_CODE (SET_SRC (elt)) != REG | |
938 | || GET_MODE (SET_SRC (elt)) != Pmode) | |
939 | return 0; | |
940 | } | |
941 | ||
942 | elt = XVECEXP (op, 0, index++); | |
943 | if (GET_CODE (elt) != SET | |
944 | || GET_CODE (SET_DEST (elt)) != MEM | |
945 | || ! memory_operand (SET_DEST (elt), Pmode) | |
946 | || GET_CODE (SET_SRC (elt)) != REG | |
947 | || REGNO (SET_SRC (elt)) != CR2_REGNO | |
948 | || GET_MODE (SET_SRC (elt)) != Pmode) | |
949 | return 0; | |
950 | ||
951 | if (GET_CODE (XVECEXP (op, 0, index++)) != USE | |
952 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
953 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) | |
954 | return 0; | |
955 | return 1; | |
956 | }) | |
957 | ||
958 | ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be | |
959 | ;; a PARLLEL. | |
960 | (define_predicate "restore_world_operation" | |
961 | (match_code "parallel") | |
962 | { | |
963 | int index; | |
964 | int i; | |
965 | rtx elt; | |
966 | int count = XVECLEN (op, 0); | |
967 | ||
968 | if (count != 59) | |
969 | return 0; | |
970 | ||
971 | index = 0; | |
972 | if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN | |
973 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
974 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
975 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) | |
976 | return 0; | |
977 | ||
978 | elt = XVECEXP (op, 0, index++); | |
979 | if (GET_CODE (elt) != SET | |
980 | || GET_CODE (SET_SRC (elt)) != MEM | |
981 | || ! memory_operand (SET_SRC (elt), Pmode) | |
982 | || GET_CODE (SET_DEST (elt)) != REG | |
983 | || REGNO (SET_DEST (elt)) != CR2_REGNO | |
984 | || GET_MODE (SET_DEST (elt)) != Pmode) | |
985 | return 0; | |
986 | ||
987 | for (i=1; i <= 19; i++) | |
988 | { | |
989 | elt = XVECEXP (op, 0, index++); | |
990 | if (GET_CODE (elt) != SET | |
991 | || GET_CODE (SET_SRC (elt)) != MEM | |
992 | || ! memory_operand (SET_SRC (elt), Pmode) | |
993 | || GET_CODE (SET_DEST (elt)) != REG | |
994 | || GET_MODE (SET_DEST (elt)) != Pmode) | |
995 | return 0; | |
996 | } | |
997 | ||
998 | for (i=1; i <= 12; i++) | |
999 | { | |
1000 | elt = XVECEXP (op, 0, index++); | |
1001 | if (GET_CODE (elt) != SET | |
1002 | || GET_CODE (SET_SRC (elt)) != MEM | |
1003 | || GET_CODE (SET_DEST (elt)) != REG | |
1004 | || GET_MODE (SET_DEST (elt)) != V4SImode) | |
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | for (i=1; i <= 18; i++) | |
1009 | { | |
1010 | elt = XVECEXP (op, 0, index++); | |
1011 | if (GET_CODE (elt) != SET | |
1012 | || GET_CODE (SET_SRC (elt)) != MEM | |
1013 | || ! memory_operand (SET_SRC (elt), DFmode) | |
1014 | || GET_CODE (SET_DEST (elt)) != REG | |
1015 | || GET_MODE (SET_DEST (elt)) != DFmode) | |
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1020 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1021 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1022 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1023 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
1024 | return 0; | |
1025 | return 1; | |
1026 | }) | |
1027 | ||
1028 | ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL. | |
1029 | (define_predicate "vrsave_operation" | |
1030 | (match_code "parallel") | |
1031 | { | |
1032 | int count = XVECLEN (op, 0); | |
1033 | unsigned int dest_regno, src_regno; | |
1034 | int i; | |
1035 | ||
1036 | if (count <= 1 | |
1037 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1038 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
72c164b3 DE |
1039 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE |
1040 | || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE) | |
48d72335 DE |
1041 | return 0; |
1042 | ||
1043 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
833126ad | 1044 | src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); |
48d72335 | 1045 | |
833126ad | 1046 | if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) |
48d72335 DE |
1047 | return 0; |
1048 | ||
1049 | for (i = 1; i < count; i++) | |
1050 | { | |
1051 | rtx elt = XVECEXP (op, 0, i); | |
1052 | ||
1053 | if (GET_CODE (elt) != CLOBBER | |
1054 | && GET_CODE (elt) != SET) | |
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | return 1; | |
1059 | }) | |
1060 | ||
1061 | ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL. | |
1062 | (define_predicate "mfcr_operation" | |
1063 | (match_code "parallel") | |
1064 | { | |
1065 | int count = XVECLEN (op, 0); | |
1066 | int i; | |
1067 | ||
1068 | /* Perform a quick check so we don't blow up below. */ | |
1069 | if (count < 1 | |
1070 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1071 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
1072 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
1073 | return 0; | |
1074 | ||
1075 | for (i = 0; i < count; i++) | |
1076 | { | |
1077 | rtx exp = XVECEXP (op, 0, i); | |
1078 | rtx unspec; | |
1079 | int maskval; | |
1080 | rtx src_reg; | |
1081 | ||
1082 | src_reg = XVECEXP (SET_SRC (exp), 0, 0); | |
1083 | ||
1084 | if (GET_CODE (src_reg) != REG | |
1085 | || GET_MODE (src_reg) != CCmode | |
1086 | || ! CR_REGNO_P (REGNO (src_reg))) | |
1087 | return 0; | |
1088 | ||
1089 | if (GET_CODE (exp) != SET | |
1090 | || GET_CODE (SET_DEST (exp)) != REG | |
1091 | || GET_MODE (SET_DEST (exp)) != SImode | |
1092 | || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) | |
1093 | return 0; | |
1094 | unspec = SET_SRC (exp); | |
1095 | maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); | |
1096 | ||
1097 | if (GET_CODE (unspec) != UNSPEC | |
1098 | || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR | |
1099 | || XVECLEN (unspec, 0) != 2 | |
1100 | || XVECEXP (unspec, 0, 0) != src_reg | |
1101 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
1102 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
1103 | return 0; | |
1104 | } | |
1105 | return 1; | |
1106 | }) | |
1107 | ||
1108 | ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL. | |
1109 | (define_predicate "mtcrf_operation" | |
1110 | (match_code "parallel") | |
1111 | { | |
1112 | int count = XVECLEN (op, 0); | |
1113 | int i; | |
1114 | rtx src_reg; | |
1115 | ||
1116 | /* Perform a quick check so we don't blow up below. */ | |
1117 | if (count < 1 | |
1118 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1119 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
1120 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
1121 | return 0; | |
1122 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); | |
1123 | ||
1124 | if (GET_CODE (src_reg) != REG | |
1125 | || GET_MODE (src_reg) != SImode | |
1126 | || ! INT_REGNO_P (REGNO (src_reg))) | |
1127 | return 0; | |
1128 | ||
1129 | for (i = 0; i < count; i++) | |
1130 | { | |
1131 | rtx exp = XVECEXP (op, 0, i); | |
1132 | rtx unspec; | |
1133 | int maskval; | |
1134 | ||
1135 | if (GET_CODE (exp) != SET | |
1136 | || GET_CODE (SET_DEST (exp)) != REG | |
1137 | || GET_MODE (SET_DEST (exp)) != CCmode | |
1138 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
1139 | return 0; | |
1140 | unspec = SET_SRC (exp); | |
1141 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
1142 | ||
1143 | if (GET_CODE (unspec) != UNSPEC | |
1144 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR | |
1145 | || XVECLEN (unspec, 0) != 2 | |
1146 | || XVECEXP (unspec, 0, 0) != src_reg | |
1147 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
1148 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
1149 | return 0; | |
1150 | } | |
1151 | return 1; | |
1152 | }) | |
1153 | ||
1154 | ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. | |
1155 | (define_predicate "lmw_operation" | |
1156 | (match_code "parallel") | |
1157 | { | |
1158 | int count = XVECLEN (op, 0); | |
1159 | unsigned int dest_regno; | |
1160 | rtx src_addr; | |
1161 | unsigned int base_regno; | |
1162 | HOST_WIDE_INT offset; | |
1163 | int i; | |
1164 | ||
1165 | /* Perform a quick check so we don't blow up below. */ | |
1166 | if (count <= 1 | |
1167 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1168 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
1169 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
1170 | return 0; | |
1171 | ||
1172 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
1173 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
1174 | ||
1175 | if (dest_regno > 31 | |
1176 | || count != 32 - (int) dest_regno) | |
1177 | return 0; | |
1178 | ||
1179 | if (legitimate_indirect_address_p (src_addr, 0)) | |
1180 | { | |
1181 | offset = 0; | |
1182 | base_regno = REGNO (src_addr); | |
1183 | if (base_regno == 0) | |
1184 | return 0; | |
1185 | } | |
1186 | else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0)) | |
1187 | { | |
1188 | offset = INTVAL (XEXP (src_addr, 1)); | |
1189 | base_regno = REGNO (XEXP (src_addr, 0)); | |
1190 | } | |
1191 | else | |
1192 | return 0; | |
1193 | ||
1194 | for (i = 0; i < count; i++) | |
1195 | { | |
1196 | rtx elt = XVECEXP (op, 0, i); | |
1197 | rtx newaddr; | |
1198 | rtx addr_reg; | |
1199 | HOST_WIDE_INT newoffset; | |
1200 | ||
1201 | if (GET_CODE (elt) != SET | |
1202 | || GET_CODE (SET_DEST (elt)) != REG | |
1203 | || GET_MODE (SET_DEST (elt)) != SImode | |
1204 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
1205 | || GET_CODE (SET_SRC (elt)) != MEM | |
1206 | || GET_MODE (SET_SRC (elt)) != SImode) | |
1207 | return 0; | |
1208 | newaddr = XEXP (SET_SRC (elt), 0); | |
1209 | if (legitimate_indirect_address_p (newaddr, 0)) | |
1210 | { | |
1211 | newoffset = 0; | |
1212 | addr_reg = newaddr; | |
1213 | } | |
1214 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) | |
1215 | { | |
1216 | addr_reg = XEXP (newaddr, 0); | |
1217 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
1218 | } | |
1219 | else | |
1220 | return 0; | |
1221 | if (REGNO (addr_reg) != base_regno | |
1222 | || newoffset != offset + 4 * i) | |
1223 | return 0; | |
1224 | } | |
1225 | ||
1226 | return 1; | |
1227 | }) | |
1228 | ||
1229 | ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL. | |
1230 | (define_predicate "stmw_operation" | |
1231 | (match_code "parallel") | |
1232 | { | |
1233 | int count = XVECLEN (op, 0); | |
1234 | unsigned int src_regno; | |
1235 | rtx dest_addr; | |
1236 | unsigned int base_regno; | |
1237 | HOST_WIDE_INT offset; | |
1238 | int i; | |
1239 | ||
1240 | /* Perform a quick check so we don't blow up below. */ | |
1241 | if (count <= 1 | |
1242 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1243 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
1244 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
1245 | return 0; | |
1246 | ||
1247 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
1248 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
1249 | ||
1250 | if (src_regno > 31 | |
1251 | || count != 32 - (int) src_regno) | |
1252 | return 0; | |
1253 | ||
1254 | if (legitimate_indirect_address_p (dest_addr, 0)) | |
1255 | { | |
1256 | offset = 0; | |
1257 | base_regno = REGNO (dest_addr); | |
1258 | if (base_regno == 0) | |
1259 | return 0; | |
1260 | } | |
1261 | else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0)) | |
1262 | { | |
1263 | offset = INTVAL (XEXP (dest_addr, 1)); | |
1264 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
1265 | } | |
1266 | else | |
1267 | return 0; | |
1268 | ||
1269 | for (i = 0; i < count; i++) | |
1270 | { | |
1271 | rtx elt = XVECEXP (op, 0, i); | |
1272 | rtx newaddr; | |
1273 | rtx addr_reg; | |
1274 | HOST_WIDE_INT newoffset; | |
1275 | ||
1276 | if (GET_CODE (elt) != SET | |
1277 | || GET_CODE (SET_SRC (elt)) != REG | |
1278 | || GET_MODE (SET_SRC (elt)) != SImode | |
1279 | || REGNO (SET_SRC (elt)) != src_regno + i | |
1280 | || GET_CODE (SET_DEST (elt)) != MEM | |
1281 | || GET_MODE (SET_DEST (elt)) != SImode) | |
1282 | return 0; | |
1283 | newaddr = XEXP (SET_DEST (elt), 0); | |
1284 | if (legitimate_indirect_address_p (newaddr, 0)) | |
1285 | { | |
1286 | newoffset = 0; | |
1287 | addr_reg = newaddr; | |
1288 | } | |
1289 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) | |
1290 | { | |
1291 | addr_reg = XEXP (newaddr, 0); | |
1292 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
1293 | } | |
1294 | else | |
1295 | return 0; | |
1296 | if (REGNO (addr_reg) != base_regno | |
1297 | || newoffset != offset + 4 * i) | |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | return 1; | |
1302 | }) |