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55920223 1/* Subroutines for the C front end on the PowerPC architecture.
fbd26352 2 Copyright (C) 2002-2019 Free Software Foundation, Inc.
edd2f2ae 3
4 Contributed by Zack Weinberg <zack@codesourcery.com>
65441f6f 5 and Paolo Bonzini <bonzini@gnu.org>
edd2f2ae 6
3a5a28e2 7 This file is part of GCC.
edd2f2ae 8
3a5a28e2 9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
038d1e19 11 by the Free Software Foundation; either version 3, or (at your
3a5a28e2 12 option) any later version.
edd2f2ae 13
3a5a28e2 14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
edd2f2ae 18
3a5a28e2 19 You should have received a copy of the GNU General Public License
038d1e19 20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
edd2f2ae 22
785790dc 23#define IN_TARGET_CODE 1
24
edd2f2ae 25#include "config.h"
26#include "system.h"
805e22b2 27#include "coretypes.h"
c1eb80de 28#include "target.h"
7bedc3a0 29#include "c-family/c-common.h"
ad7b10a2 30#include "memmodel.h"
edd2f2ae 31#include "tm_p.h"
c1eb80de 32#include "stringpool.h"
33#include "stor-layout.h"
34#include "c-family/c-pragma.h"
65441f6f 35#include "langhooks.h"
f14b1922 36#include "c/c-tree.h"
65441f6f 37
38
39
edd2f2ae 40/* Handle the machine specific pragma longcall. Its syntax is
41
42 # pragma longcall ( TOGGLE )
43
44 where TOGGLE is either 0 or 1.
45
46 rs6000_default_long_calls is set to the value of TOGGLE, changing
47 whether or not new function declarations receive a longcall
48 attribute by default. */
49
e8d0745d 50#define SYNTAX_ERROR(gmsgid) do { \
51 warning (OPT_Wpragmas, gmsgid); \
52 warning (OPT_Wpragmas, "ignoring malformed #pragma longcall"); \
53 return; \
edd2f2ae 54} while (0)
55
56void
ee515bba 57rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED)
edd2f2ae 58{
59 tree x, n;
60
61 /* If we get here, generic code has already scanned the directive
62 leader and the word "longcall". */
63
b5d533bb 64 if (pragma_lex (&x) != CPP_OPEN_PAREN)
edd2f2ae 65 SYNTAX_ERROR ("missing open paren");
b5d533bb 66 if (pragma_lex (&n) != CPP_NUMBER)
edd2f2ae 67 SYNTAX_ERROR ("missing number");
b5d533bb 68 if (pragma_lex (&x) != CPP_CLOSE_PAREN)
edd2f2ae 69 SYNTAX_ERROR ("missing close paren");
70
71 if (n != integer_zero_node && n != integer_one_node)
72 SYNTAX_ERROR ("number must be 0 or 1");
73
b5d533bb 74 if (pragma_lex (&x) != CPP_EOF)
e8d0745d 75 warning (OPT_Wpragmas, "junk at end of #pragma longcall");
edd2f2ae 76
77 rs6000_default_long_calls = (n == integer_one_node);
78}
b2d381e8 79
80/* Handle defining many CPP flags based on TARGET_xxx. As a general
81 policy, rather than trying to guess what flags a user might want a
82 #define for, it's better to define a flag for everything. */
83
84#define builtin_define(TXT) cpp_define (pfile, TXT)
85#define builtin_assert(TXT) cpp_assert (pfile, TXT)
86
89768577 87/* Keep the AltiVec keywords handy for fast comparisons. */
ce9abfc3 88static GTY(()) tree __vector_keyword;
89static GTY(()) tree vector_keyword;
90static GTY(()) tree __pixel_keyword;
91static GTY(()) tree pixel_keyword;
92static GTY(()) tree __bool_keyword;
93static GTY(()) tree bool_keyword;
fd36071f 94static GTY(()) tree _Bool_keyword;
ae61c502 95static GTY(()) tree __int128_type;
96static GTY(()) tree __uint128_type;
89768577 97
98/* Preserved across calls. */
99static tree expand_bool_pixel;
100
101static cpp_hashnode *
102altivec_categorize_keyword (const cpp_token *tok)
103{
104 if (tok->type == CPP_NAME)
105 {
9d6d8a52 106 cpp_hashnode *ident = tok->val.node.node;
89768577 107
02413110 108 if (ident == C_CPP_HASHNODE (vector_keyword))
89768577 109 return C_CPP_HASHNODE (__vector_keyword);
110
02413110 111 if (ident == C_CPP_HASHNODE (pixel_keyword))
89768577 112 return C_CPP_HASHNODE (__pixel_keyword);
113
02413110 114 if (ident == C_CPP_HASHNODE (bool_keyword))
89768577 115 return C_CPP_HASHNODE (__bool_keyword);
116
fd36071f 117 if (ident == C_CPP_HASHNODE (_Bool_keyword))
118 return C_CPP_HASHNODE (__bool_keyword);
119
89768577 120 return ident;
121 }
122
123 return 0;
124}
125
126static void
127init_vector_keywords (void)
128{
ae61c502 129 /* Keywords without two leading underscores are context-sensitive, and hence
130 implemented as conditional macros, controlled by the
131 rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit
132 support, record the __int128_t and __uint128_t types. */
89768577 133
134 __vector_keyword = get_identifier ("__vector");
135 C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
136
137 __pixel_keyword = get_identifier ("__pixel");
138 C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL;
139
140 __bool_keyword = get_identifier ("__bool");
141 C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL;
142
143 vector_keyword = get_identifier ("vector");
144 C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL;
145
146 pixel_keyword = get_identifier ("pixel");
147 C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL;
148
149 bool_keyword = get_identifier ("bool");
150 C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL;
fd36071f 151
152 _Bool_keyword = get_identifier ("_Bool");
153 C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
ae61c502 154
155 if (TARGET_VADDUQM)
156 {
157 __int128_type = get_identifier ("__int128_t");
158 __uint128_type = get_identifier ("__uint128_t");
159 }
89768577 160}
161
08a9c372 162/* Helper function to find out which RID_INT_N_* code is the one for
163 __int128, if any. Returns RID_MAX+1 if none apply, which is safe
164 (for our purposes, since we always expect to have __int128) to
165 compare against. */
166static int
167rid_int128(void)
168{
169 int i;
170
171 for (i = 0; i < NUM_INT_N_ENTS; i ++)
172 if (int_n_enabled_p[i]
173 && int_n_data[i].bitsize == 128)
174 return RID_INT_N_0 + i;
175
176 return RID_MAX + 1;
177}
178
89768577 179/* Called to decide whether a conditional macro should be expanded.
180 Since we have exactly one such macro (i.e, 'vector'), we do not
181 need to examine the 'tok' parameter. */
182
183static cpp_hashnode *
184rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
185{
9d6d8a52 186 cpp_hashnode *expand_this = tok->val.node.node;
89768577 187 cpp_hashnode *ident;
188
0375b229 189 /* If the current machine does not have altivec, don't look for the
190 keywords. */
191 if (!TARGET_ALTIVEC)
192 return NULL;
193
89768577 194 ident = altivec_categorize_keyword (tok);
195
02413110 196 if (ident != expand_this)
197 expand_this = NULL;
198
89768577 199 if (ident == C_CPP_HASHNODE (__vector_keyword))
200 {
02413110 201 int idx = 0;
202 do
203 tok = cpp_peek_token (pfile, idx++);
204 while (tok->type == CPP_PADDING);
89768577 205 ident = altivec_categorize_keyword (tok);
206
02413110 207 if (ident == C_CPP_HASHNODE (__pixel_keyword))
89768577 208 {
209 expand_this = C_CPP_HASHNODE (__vector_keyword);
210 expand_bool_pixel = __pixel_keyword;
211 }
212 else if (ident == C_CPP_HASHNODE (__bool_keyword))
213 {
214 expand_this = C_CPP_HASHNODE (__vector_keyword);
215 expand_bool_pixel = __bool_keyword;
216 }
0e6b798b 217 /* The boost libraries have code with Iterator::vector vector in it. If
218 we allow the normal handling, this module will be called recursively,
219 and the vector will be skipped.; */
220 else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword)))
89768577 221 {
222 enum rid rid_code = (enum rid)(ident->rid_code);
793b38da 223 bool is_macro = cpp_macro_p (ident);
224
afdde20c 225 /* If there is a function-like macro, check if it is going to be
226 invoked with or without arguments. Without following ( treat
227 it like non-macro, otherwise the following cpp_get_token eats
228 what should be preserved. */
793b38da 229 if (is_macro && cpp_fun_like_macro_p (ident))
afdde20c 230 {
231 int idx2 = idx;
232 do
233 tok = cpp_peek_token (pfile, idx2++);
234 while (tok->type == CPP_PADDING);
235 if (tok->type != CPP_OPEN_PAREN)
793b38da 236 is_macro = false;
afdde20c 237 }
793b38da 238
239 if (is_macro)
89768577 240 {
02413110 241 do
242 (void) cpp_get_token (pfile);
243 while (--idx > 0);
244 do
245 tok = cpp_peek_token (pfile, idx++);
246 while (tok->type == CPP_PADDING);
89768577 247 ident = altivec_categorize_keyword (tok);
69dfb43a 248 if (ident == C_CPP_HASHNODE (__pixel_keyword))
249 {
250 expand_this = C_CPP_HASHNODE (__vector_keyword);
251 expand_bool_pixel = __pixel_keyword;
252 rid_code = RID_MAX;
253 }
254 else if (ident == C_CPP_HASHNODE (__bool_keyword))
255 {
256 expand_this = C_CPP_HASHNODE (__vector_keyword);
257 expand_bool_pixel = __bool_keyword;
258 rid_code = RID_MAX;
259 }
260 else if (ident)
89768577 261 rid_code = (enum rid)(ident->rid_code);
262 }
263
264 if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
265 || rid_code == RID_SHORT || rid_code == RID_SIGNED
266 || rid_code == RID_INT || rid_code == RID_CHAR
32374e3c 267 || rid_code == RID_FLOAT
ae61c502 268 || (rid_code == RID_DOUBLE && TARGET_VSX)
08a9c372 269 || (rid_code == rid_int128 () && TARGET_VADDUQM))
89768577 270 {
271 expand_this = C_CPP_HASHNODE (__vector_keyword);
272 /* If the next keyword is bool or pixel, it
273 will need to be expanded as well. */
02413110 274 do
275 tok = cpp_peek_token (pfile, idx++);
276 while (tok->type == CPP_PADDING);
89768577 277 ident = altivec_categorize_keyword (tok);
278
02413110 279 if (ident == C_CPP_HASHNODE (__pixel_keyword))
89768577 280 expand_bool_pixel = __pixel_keyword;
281 else if (ident == C_CPP_HASHNODE (__bool_keyword))
282 expand_bool_pixel = __bool_keyword;
283 else
284 {
285 /* Try two tokens down, too. */
02413110 286 do
287 tok = cpp_peek_token (pfile, idx++);
288 while (tok->type == CPP_PADDING);
89768577 289 ident = altivec_categorize_keyword (tok);
02413110 290 if (ident == C_CPP_HASHNODE (__pixel_keyword))
89768577 291 expand_bool_pixel = __pixel_keyword;
292 else if (ident == C_CPP_HASHNODE (__bool_keyword))
293 expand_bool_pixel = __bool_keyword;
294 }
295 }
ae61c502 296
297 /* Support vector __int128_t, but we don't need to worry about bool
298 or pixel on this type. */
299 else if (TARGET_VADDUQM
300 && (ident == C_CPP_HASHNODE (__int128_type)
301 || ident == C_CPP_HASHNODE (__uint128_type)))
302 expand_this = C_CPP_HASHNODE (__vector_keyword);
89768577 303 }
304 }
305 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))
306 {
307 expand_this = C_CPP_HASHNODE (__pixel_keyword);
308 expand_bool_pixel = 0;
309 }
310 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword))
311 {
312 expand_this = C_CPP_HASHNODE (__bool_keyword);
313 expand_bool_pixel = 0;
314 }
315
316 return expand_this;
317}
318
0375b229 319
320/* Define or undefine a single macro. */
321
322static void
323rs6000_define_or_undefine_macro (bool define_p, const char *name)
324{
325 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
326 fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name);
327
328 if (define_p)
329 cpp_define (parse_in, name);
330 else
331 cpp_undef (parse_in, name);
332}
333
334/* Define or undefine macros based on the current target. If the user does
335 #pragma GCC target, we need to adjust the macros dynamically. Note, some of
336 the options needed for builtins have been moved to separate variables, so
337 have both the target flags and the builtin flags as arguments. */
338
339void
8ce9ff04 340rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
341 HOST_WIDE_INT bu_mask)
0375b229 342{
343 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
8ce9ff04 344 fprintf (stderr,
345 "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX
346 ", " HOST_WIDE_INT_PRINT_HEX ")\n",
0375b229 347 (define_p) ? "define" : "undef",
8ce9ff04 348 flags, bu_mask);
0375b229 349
11683e94 350 /* Each of the flags mentioned below controls whether certain
351 preprocessor macros will be automatically defined when
352 preprocessing source files for compilation by this compiler.
353 While most of these flags can be enabled or disabled
354 explicitly by specifying certain command-line options when
355 invoking the compiler, there are also many ways in which these
356 flags are enabled or disabled implicitly, based on compiler
357 defaults, configuration choices, and on the presence of certain
358 related command-line options. Many, but not all, of these
359 implicit behaviors can be found in file "rs6000.c", the
360 rs6000_option_override_internal() function.
361
362 In general, each of the flags may be automatically enabled in
363 any of the following conditions:
364
365 1. If no -mcpu target is specified on the command line and no
366 --with-cpu target is specified to the configure command line
367 and the TARGET_DEFAULT macro for this default cpu host
368 includes the flag, and the flag has not been explicitly disabled
369 by command-line options.
370
371 2. If the target specified with -mcpu=target on the command line, or
372 in the absence of a -mcpu=target command-line option, if the
373 target specified using --with-cpu=target on the configure
374 command line, is disqualified because the associated binary
375 tools (e.g. the assembler) lack support for the requested cpu,
376 and the TARGET_DEFAULT macro for this default cpu host
377 includes the flag, and the flag has not been explicitly disabled
378 by command-line options.
379
380 3. If either of the above two conditions apply except that the
381 TARGET_DEFAULT macro is defined to equal zero, and
382 TARGET_POWERPC64 and
383 a) BYTES_BIG_ENDIAN and the flag to be enabled is either
384 MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64"
385 target), or
386 b) !BYTES_BIG_ENDIAN and the flag to be enabled is either
387 MASK_POWERPC64 or it is one of the flags included in
388 ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target).
389
390 4. If a cpu has been requested with a -mcpu=target command-line option
391 and this cpu has not been disqualified due to shortcomings of the
392 binary tools, and the set of flags associated with the requested cpu
393 include the flag to be enabled. See rs6000-cpus.def for macro
394 definitions that represent various ABI standards
395 (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of
396 the specific flags that are associated with each of the cpu
397 choices that can be specified as the target of a -mcpu=target
398 compile option, or as the the target of a --with-cpu=target
399 configure option. Target flags that are specified in either
400 of these two ways are considered "implicit" since the flags
401 are not mentioned specifically by name.
402
403 Additional documentation describing behavior specific to
404 particular flags is provided below, immediately preceding the
405 use of each relevant flag.
406
407 5. If there is no -mcpu=target command-line option, and the cpu
408 requested by a --with-cpu=target command-line option has not
409 been disqualified due to shortcomings of the binary tools, and
410 the set of flags associated with the specified target include
411 the flag to be enabled. See the notes immediately above for a
412 summary of the flags associated with particular cpu
413 definitions. */
414
62b54165 415 /* rs6000_isa_flags based options. */
34c34d94 416 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
62b54165 417 if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
0375b229 418 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
62b54165 419 if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
0375b229 420 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
62b54165 421 if ((flags & OPTION_MASK_POWERPC64) != 0)
0375b229 422 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
62b54165 423 if ((flags & OPTION_MASK_MFCRF) != 0)
0375b229 424 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
62b54165 425 if ((flags & OPTION_MASK_POPCNTB) != 0)
0375b229 426 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
62b54165 427 if ((flags & OPTION_MASK_FPRND) != 0)
0375b229 428 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
62b54165 429 if ((flags & OPTION_MASK_CMPB) != 0)
0375b229 430 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
62b54165 431 if ((flags & OPTION_MASK_MFPGPR) != 0)
0375b229 432 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
62b54165 433 if ((flags & OPTION_MASK_POPCNTD) != 0)
0375b229 434 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
11683e94 435 /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
c6bfc2a3 436 turned on in the following condition:
efcf68d5 437 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
438 explicitly disabled.
c6bfc2a3 439 Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
440 have been turned on explicitly.
441 Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
11683e94 442 turned off in any of the following conditions:
443 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
444 disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
445 enabled.
446 2. TARGET_VSX is off. */
81f0e7d0 447 if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
448 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
a875ad2e 449 if ((flags & OPTION_MASK_MODULO) != 0)
450 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
62b54165 451 if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
0375b229 452 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
62b54165 453 if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
0375b229 454 rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
11683e94 455 /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on
456 in any of the following conditions:
fc3703b8 457 1. The operating system is Darwin and it is configured for 64
11683e94 458 bit. (See darwin_rs6000_override_options.)
fc3703b8 459 2. The operating system is Darwin and the operating system
11683e94 460 version is 10.5 or higher and the user has not explicitly
461 disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and
462 the compiler is not producing code for integration within the
463 kernel. (See darwin_rs6000_override_options.)
464 Note that the OPTION_MASK_ALTIVEC flag is automatically turned
465 off in any of the following conditions:
466 1. The operating system does not support saving of AltiVec
467 registers (OS_MISSING_ALTIVEC).
468 2. If an inner context (as introduced by
469 __attribute__((__target__())) or #pragma GCC target()
470 requests a target that normally enables the
471 OPTION_MASK_ALTIVEC flag but the outer-most "main target"
472 does not support the rs6000_altivec_abi, this flag is
473 turned off for the inner context unless OPTION_MASK_ALTIVEC
474 was explicitly enabled for the inner context. */
62b54165 475 if ((flags & OPTION_MASK_ALTIVEC) != 0)
0375b229 476 {
477 const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
478 rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
479 rs6000_define_or_undefine_macro (define_p, vec_str);
480
481 /* Define this when supporting context-sensitive keywords. */
482 if (!flag_iso)
483 rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
484 }
c6bfc2a3 485 /* Note that the OPTION_MASK_VSX flag is automatically turned on in
486 the following conditions:
487 1. TARGET_P8_VECTOR is explicitly turned on and the OPTION_MASK_VSX
488 was not explicitly turned off. Hereafter, the OPTION_MASK_VSX
489 flag is considered to have been explicitly turned on.
490 Note that the OPTION_MASK_VSX flag is automatically turned off in
11683e94 491 the following conditions:
492 1. The operating system does not support saving of AltiVec
493 registers (OS_MISSING_ALTIVEC).
6fd39ec4 494 2. If the option TARGET_HARD_FLOAT is turned off. Hereafter, the
df8015ff 495 OPTION_MASK_VSX flag is considered to have been turned off
496 explicitly.
6354e315 497 3. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
11683e94 498 compilation context, or if it is turned on by any means in an
499 inner compilation context. Hereafter, the OPTION_MASK_VSX
500 flag is considered to have been turned off explicitly.
6354e315 501 4. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the
11683e94 502 OPTION_MASK_VSX flag is considered to have been turned off
503 explicitly.
6354e315 504 5. If an inner context (as introduced by
11683e94 505 __attribute__((__target__())) or #pragma GCC target()
506 requests a target that normally enables the
507 OPTION_MASK_VSX flag but the outer-most "main target"
508 does not support the rs6000_altivec_abi, this flag is
509 turned off for the inner context unless OPTION_MASK_VSX
510 was explicitly enabled for the inner context. */
62b54165 511 if ((flags & OPTION_MASK_VSX) != 0)
0375b229 512 rs6000_define_or_undefine_macro (define_p, "__VSX__");
5088e479 513 if ((flags & OPTION_MASK_HTM) != 0)
3718614d 514 {
515 rs6000_define_or_undefine_macro (define_p, "__HTM__");
516 /* Tell the user that our HTM insn patterns act as memory barriers. */
517 rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
518 }
11683e94 519 /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
c6bfc2a3 520 on in the following conditions:
521 1. TARGET_P9_VECTOR is explicitly turned on and
522 OPTION_MASK_P8_VECTOR is not explicitly turned off.
523 Hereafter, the OPTION_MASK_P8_VECTOR flag is considered to
524 have been turned off explicitly.
525 Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
11683e94 526 off in the following conditions:
527 1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX
528 were turned off explicitly and OPTION_MASK_P8_VECTOR flag was
529 not turned on explicitly.
530 2. If TARGET_ALTIVEC is turned off. Hereafter, the
531 OPTION_MASK_P8_VECTOR flag is considered to have been turned off
532 explicitly.
c6bfc2a3 533 3. If TARGET_VSX is turned off and OPTION_MASK_P8_VECTOR was not
534 explicitly enabled. If TARGET_VSX is explicitly enabled, the
535 OPTION_MASK_P8_VECTOR flag is hereafter also considered to
536 have been turned off explicitly. */
81f0e7d0 537 if ((flags & OPTION_MASK_P8_VECTOR) != 0)
538 rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
11683e94 539 /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned
540 off in the following conditions:
c6bfc2a3 541 1. If TARGET_P8_VECTOR is turned off and OPTION_MASK_P9_VECTOR is
542 not turned on explicitly. Hereafter, if OPTION_MASK_P8_VECTOR
543 was turned on explicitly, the OPTION_MASK_P9_VECTOR flag is
544 also considered to have been turned off explicitly.
545 Note that the OPTION_MASK_P9_VECTOR is automatically turned on
546 in the following conditions:
efcf68d5 547 1. If TARGET_P9_MINMAX was turned on explicitly.
c6bfc2a3 548 Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to
549 have been turned on explicitly. */
7f6b8cff 550 if ((flags & OPTION_MASK_P9_VECTOR) != 0)
551 rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__");
11683e94 552 /* Note that the OPTION_MASK_QUAD_MEMORY flag is automatically
553 turned off in the following conditions:
554 1. If TARGET_POWERPC64 is turned off.
555 2. If WORDS_BIG_ENDIAN is false (non-atomic quad memory
556 load/store are disabled on little endian). */
1c09f133 557 if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
558 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
11683e94 559 /* Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is automatically
560 turned off in the following conditions:
561 1. If TARGET_POWERPC64 is turned off.
562 Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is
563 automatically turned on in the following conditions:
564 1. If TARGET_QUAD_MEMORY and this flag was not explicitly
565 disabled. */
1c09f133 566 if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
567 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
11683e94 568 /* Note that the OPTION_MASK_CRYPTO flag is automatically turned off
569 in the following conditions:
570 1. If any of TARGET_HARD_FLOAT or TARGET_ALTIVEC or TARGET_VSX
571 are turned off explicitly and OPTION_MASK_CRYPTO is not turned
572 on explicitly.
573 2. If TARGET_ALTIVEC is turned off. */
81f0e7d0 574 if ((flags & OPTION_MASK_CRYPTO) != 0)
575 rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
9959b729 576 if ((flags & OPTION_MASK_FLOAT128_KEYWORD) != 0)
577 {
578 rs6000_define_or_undefine_macro (define_p, "__FLOAT128__");
579 if (define_p)
580 rs6000_define_or_undefine_macro (true, "__float128=__ieee128");
581 else
582 rs6000_define_or_undefine_macro (false, "__float128");
583 }
584 /* OPTION_MASK_FLOAT128_HARDWARE can be turned on if -mcpu=power9 is used or
585 via the target attribute/pragma. */
586 if ((flags & OPTION_MASK_FLOAT128_HW) != 0)
587 rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__");
0375b229 588
589 /* options from the builtin masks. */
11683e94 590 /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
591 PROCESSOR_CELL) (e.g. -mcpu=cell). */
0375b229 592 if ((bu_mask & RS6000_BTM_CELL) != 0)
593 rs6000_define_or_undefine_macro (define_p, "__PPU__");
594}
595
b2d381e8 596void
ee515bba 597rs6000_cpu_cpp_builtins (cpp_reader *pfile)
b2d381e8 598{
0375b229 599 /* Define all of the common macros. */
62b54165 600 rs6000_target_modify_macros (true, rs6000_isa_flags,
0375b229 601 rs6000_builtin_mask_calculate ());
602
0375b229 603 if (TARGET_FRE)
604 builtin_define ("__RECIP__");
605 if (TARGET_FRES)
606 builtin_define ("__RECIPF__");
607 if (TARGET_FRSQRTE)
608 builtin_define ("__RSQRTE__");
609 if (TARGET_FRSQRTES)
610 builtin_define ("__RSQRTEF__");
7d29bba9 611 if (TARGET_FLOAT128_TYPE)
612 builtin_define ("__FLOAT128_TYPE__");
9f6dc184 613#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
614 builtin_define ("__BUILTIN_CPU_SUPPORTS__");
615#endif
7d29bba9 616
c378948c 617 if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
0375b229 618 {
53469839 619 /* Define the AltiVec syntactic elements. */
620 builtin_define ("__vector=__attribute__((altivec(vector__)))");
621 builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short");
622 builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned");
89768577 623
624 if (!flag_iso)
625 {
89768577 626 builtin_define ("vector=vector");
627 builtin_define ("pixel=pixel");
628 builtin_define ("bool=bool");
fd36071f 629 builtin_define ("_Bool=_Bool");
89768577 630 init_vector_keywords ();
631
632 /* Enable context-sensitive macros. */
633 cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
634 }
53469839 635 }
6fd39ec4 636 if (!TARGET_HARD_FLOAT)
3da0fdbc 637 builtin_define ("_SOFT_DOUBLE");
b7f6aee4 638 /* Used by lwarx/stwcx. errata work-around. */
639 if (rs6000_cpu == PROCESSOR_PPC405)
640 builtin_define ("__PPC405__");
ac951330 641 /* Used by libstdc++. */
642 if (TARGET_NO_LWSYNC)
643 builtin_define ("__NO_LWSYNC__");
32374e3c 644
0375b229 645 if (TARGET_EXTRA_BUILTINS)
646 {
32374e3c 647 /* For the VSX builtin functions identical to Altivec functions, just map
648 the altivec builtin into the vsx version (the altivec functions
649 generate VSX code if -mvsx). */
650 builtin_define ("__builtin_vsx_xxland=__builtin_vec_and");
651 builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc");
652 builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor");
653 builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or");
654 builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor");
655 builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel");
656 builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm");
657
658 /* Also map the a and m versions of the multiply/add instructions to the
659 builtin for people blindly going off the instruction manual. */
660 builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp");
661 builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp");
662 builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp");
663 builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp");
664 builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp");
665 builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp");
666 builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp");
667 builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp");
668 builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp");
669 builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp");
670 builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp");
671 builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp");
672 builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp");
673 builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp");
674 builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
675 builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
676 }
677
822daf91 678 /* Map the old _Float128 'q' builtins into the new 'f128' builtins. */
679 if (TARGET_FLOAT128_TYPE)
680 {
681 builtin_define ("__builtin_fabsq=__builtin_fabsf128");
682 builtin_define ("__builtin_copysignq=__builtin_copysignf128");
683 builtin_define ("__builtin_nanq=__builtin_nanf128");
684 builtin_define ("__builtin_nansq=__builtin_nansf128");
685 builtin_define ("__builtin_infq=__builtin_inff128");
686 builtin_define ("__builtin_huge_valq=__builtin_huge_valf128");
687 }
688
32374e3c 689 /* Tell users they can use __builtin_bswap{16,64}. */
690 builtin_define ("__HAVE_BSWAP__");
a429a994 691
692 /* May be overridden by target configuration. */
693 RS6000_CPU_CPP_ENDIAN_BUILTINS();
694
b2d381e8 695 if (TARGET_LONG_DOUBLE_128)
0cc77516 696 {
697 builtin_define ("__LONG_DOUBLE_128__");
698 builtin_define ("__LONGDOUBLE128");
3f2bdc95 699
700 if (TARGET_IEEEQUAD)
b95c28c7 701 {
702 /* Older versions of GLIBC used __attribute__((__KC__)) to create the
703 IEEE 128-bit floating point complex type for C++ (which does not
704 support _Float128 _Complex). If the default for long double is
705 IEEE 128-bit mode, the library would need to use
706 __attribute__((__TC__)) instead. Defining __KF__ and __KC__
707 is a stop-gap to build with the older libraries, until we
708 get an updated library. */
709 builtin_define ("__LONG_DOUBLE_IEEE128__");
710 builtin_define ("__KF__=__TF__");
711 builtin_define ("__KC__=__TC__");
712 }
3f2bdc95 713 else
714 builtin_define ("__LONG_DOUBLE_IBM128__");
0cc77516 715 }
b2d381e8 716
17681ddd 717 switch (TARGET_CMODEL)
718 {
719 /* Deliberately omit __CMODEL_SMALL__ since that was the default
720 before --mcmodel support was added. */
721 case CMODEL_MEDIUM:
722 builtin_define ("__CMODEL_MEDIUM__");
723 break;
724 case CMODEL_LARGE:
725 builtin_define ("__CMODEL_LARGE__");
726 break;
727 default:
728 break;
729 }
730
b2d381e8 731 switch (rs6000_current_abi)
732 {
733 case ABI_V4:
734 builtin_define ("_CALL_SYSV");
735 break;
b2d381e8 736 case ABI_AIX:
737 builtin_define ("_CALL_AIXDESC");
738 builtin_define ("_CALL_AIX");
238f342d 739 builtin_define ("_CALL_ELF=1");
740 break;
741 case ABI_ELFv2:
742 builtin_define ("_CALL_ELF=2");
b2d381e8 743 break;
744 case ABI_DARWIN:
745 builtin_define ("_CALL_DARWIN");
746 break;
b7f6aee4 747 default:
748 break;
b2d381e8 749 }
65441f6f 750
7b44b5b0 751 /* Vector element order. */
fc3703b8 752 if (BYTES_BIG_ENDIAN)
7b44b5b0 753 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__");
754 else
755 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
756
d2776534 757 /* Let the compiled code know if 'f' class registers will not be available. */
df8015ff 758 if (TARGET_SOFT_FLOAT)
d2776534 759 builtin_define ("__NO_FPRS__");
b91a266c 760
238f342d 761 /* Whether aggregates passed by value are aligned to a 16 byte boundary
762 if their alignment is 16 bytes or larger. */
763 if ((TARGET_MACHO && rs6000_darwin64_abi)
764 || DEFAULT_ABI == ABI_ELFv2
765 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
766 builtin_define ("__STRUCT_PARM_ALIGN__=16");
65441f6f 767}
768
769\f
770struct altivec_builtin_types
771{
772 enum rs6000_builtins code;
773 enum rs6000_builtins overloaded_code;
774 signed char ret_type;
775 signed char op1;
776 signed char op2;
777 signed char op3;
778};
779
780const struct altivec_builtin_types altivec_overloaded_builtins[] = {
32374e3c 781 /* Unary AltiVec/VSX builtins. */
65441f6f 782 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
783 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
784 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
785 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
786 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
787 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
ae52d0de 788 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
789 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
65441f6f 790 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
791 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
32374e3c 792 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
793 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
65441f6f 794 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
795 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
796 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
797 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
798 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
799 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
800 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
801 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
32374e3c 802 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
803 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
65441f6f 804 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
805 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
32374e3c 806 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
807 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
65441f6f 808 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
809 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
810 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
811 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
812 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
813 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
814 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
815 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
816 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
817 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
818 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
819 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
820 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
821 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
822 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
823 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
824 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
825 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
826 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
827 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
828 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
829 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
830 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
831 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
832 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
833 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
0eac26de 834 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
835 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
65441f6f 836 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
837 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
d5f3ed72 838 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
839 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
0eac26de 840 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
841 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
842 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
843 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
844 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
845 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
0375b229 846 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
0eac26de 847 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
65441f6f 848 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
849 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
0eac26de 850 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
851 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
65441f6f 852 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
853 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
32374e3c 854 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
855 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
65441f6f 856 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
857 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
858 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
546c4794 859 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
65441f6f 860 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
861 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
862 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
546c4794 863 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
ae52d0de 864 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
865 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
866 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
867 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
65441f6f 868 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
869 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
733b6816 870 { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF,
a7aebe61 871 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
65441f6f 872 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
873 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
874 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
546c4794 875 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
ae52d0de 876 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
877 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
878 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
879 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
65441f6f 880 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
881 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
882 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
883 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
884 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
885 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
886 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
546c4794 887 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
65441f6f 888 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
889 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
890 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
546c4794 891 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
65441f6f 892 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
893 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
894 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
895 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
896 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
546c4794 897 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
ae52d0de 898 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
899 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
900 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
901 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
733b6816 902 { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF,
a7aebe61 903 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
65441f6f 904 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
905 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
906 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
907 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
908 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
909 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
910 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
546c4794 911 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
65441f6f 912 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
913 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
914 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
546c4794 915 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
65441f6f 916
32374e3c 917 /* Binary AltiVec/VSX builtins. */
65441f6f 918 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
919 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
920 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
921 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
922 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
923 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
924 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
925 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
926 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
927 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
928 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
929 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
930 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
931 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
932 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
933 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
934 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
935 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
936 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
937 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
938 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
939 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
940 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
941 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
942 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
943 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
944 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
945 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
946 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
947 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
948 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
949 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
950 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
951 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
952 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
953 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
ae52d0de 954 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
955 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
956 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
957 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
958 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
959 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
960 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
961 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
962 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
963 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
964 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
965 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
65441f6f 966 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
967 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
32374e3c 968 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
969 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
ae61c502 970 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
971 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
972 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
973 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
974 RS6000_BTI_unsigned_V1TI, 0 },
65441f6f 975 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
976 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
977 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
978 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
979 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
980 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
981 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
982 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
983 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
984 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
985 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
986 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
987 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
988 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
989 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
990 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
991 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
992 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
993 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
994 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
995 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
996 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
997 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
998 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
999 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1000 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1001 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1002 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1003 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1004 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1005 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1006 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1007 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1008 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1009 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1010 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1011 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1012 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1013 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1014 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1015 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1016 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1017 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1018 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1019 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1020 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1021 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1022 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1023 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1024 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1025 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
a9c17725 1026 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1027 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1028 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1029 RS6000_BTI_unsigned_V4SI, 0 },
1030 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1031 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1032 RS6000_BTI_unsigned_V1TI, 0 },
1033 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1034 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
a9c17725 1035 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1036 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1037 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
1038 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1039 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
65441f6f 1040 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1041 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1042 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1043 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1044 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1045 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1046 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1047 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1048 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1049 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1050 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1051 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1052 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1053 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1054 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1055 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1056 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1057 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1058 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1059 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1060 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1061 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1062 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1063 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1064 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1065 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1066 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1067 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1068 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1069 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1070 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1071 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1072 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1073 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1074 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1075 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1076 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1077 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1078 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1079 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1080 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1081 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1082 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1083 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1084 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1085 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1086 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1087 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1088 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1089 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1090 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1091 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1092 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1093 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1094 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1095 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1096 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1097 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1098 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1099 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1100 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1101 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1102 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1103 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1104 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1105 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1106 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1107 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1108 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1109 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1110 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1111 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1112 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1113 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1114 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1115 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1116 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1117 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1118 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1119 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1120 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1121 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1122 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1123 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1124 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1125 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1126 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1127 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1128 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1129 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
702c5d85 1130 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1131 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1132 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
32374e3c 1133 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
702c5d85 1134 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
32374e3c 1135 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
271b79e4 1136 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1137 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1138 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1139 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1140 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1141 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1142 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1143 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1144 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1145 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1146 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1147 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
a7aebe61 1148 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1149 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
65441f6f 1150 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1151 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1152 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1153 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1154 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1155 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1156 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1157 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1158 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1159 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1160 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1161 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1162 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1163 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1164 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1165 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1166 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1167 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1168 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1169 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1170 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1171 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1172 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1173 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1174 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1175 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1176 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1177 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1178 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1179 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1180 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1181 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1182 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1183 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1184 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1185 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1186 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1187 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1188 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1189 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1190 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1191 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1192 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1193 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1194 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1195 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1196 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1197 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
702c5d85 1198 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1199 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1200 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
32374e3c 1201 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
702c5d85 1202 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
32374e3c 1203 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
271b79e4 1204 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1205 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1206 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1207 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1208 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1209 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
a9c17725 1210 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1211 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
271b79e4 1212 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1213 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1214 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1215 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1216 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1217 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
65441f6f 1218 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1219 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1220 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1221 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1222 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1223 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1224 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1225 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1226 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1227 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1228 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1229 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1230 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1231 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1232 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1233 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1234 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1235 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1236 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1237 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1238 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1239 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1240 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1241 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1242 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1243 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1244 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1245 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1246 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1247 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1248 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1249 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1250 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1251 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1252 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1253 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1254 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1255 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1256 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1257 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1258 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1259 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1260 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
1261 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1262 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
1263 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1264 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
1265 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1266 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
1267 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1268 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
1269 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1270 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
1271 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1272 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
1273 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1274 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
1275 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1276 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
1277 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1278 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
1279 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1280 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
1281 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1282 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
1283 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1284 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
1285 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1286 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1287 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1288 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1289 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
231d5e0b 1290 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1291 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1292 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1293 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
65441f6f 1294 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1295 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1296 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1297 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
231d5e0b 1298 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1299 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
65441f6f 1300 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1301 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1302 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1303 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
231d5e0b 1304 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1305 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
ae52d0de 1306 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1307 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1308 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1309 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
65441f6f 1310 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
1311 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
32374e3c 1312 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
1313 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
65441f6f 1314 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
546c4794 1315 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1316
65441f6f 1317 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1318 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1319 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1320 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
546c4794 1321
65441f6f 1322 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1323 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1324 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1325 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
546c4794 1326
65441f6f 1327 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1328 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1329 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1330 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
546c4794 1331
65441f6f 1332 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
1333 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
32374e3c 1334 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
1335 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
35267be7 1336 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
1337 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1338 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
1339 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1340 RS6000_BTI_unsigned_V16QI, 0},
1341 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
1342 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1343 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
1344 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1345 RS6000_BTI_unsigned_V8HI, 0},
1346 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
1347 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1348 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
1349 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1350 RS6000_BTI_unsigned_V4SI, 0},
1351 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
1352 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1353 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
1354 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1355 RS6000_BTI_unsigned_V2DI, 0},
65441f6f 1356 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
1357 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1358 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
1359 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1360 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
1361 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1362 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
1363 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1364 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
1365 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1366 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
1367 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
ae52d0de 1368 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
1369 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1370 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
1371 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
65441f6f 1372 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
1373 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
32374e3c 1374 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
1375 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
65441f6f 1376 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
546c4794 1377 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
65441f6f 1378 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
546c4794 1379 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
65441f6f 1380 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1381 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1382 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
546c4794 1383 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
65441f6f 1384 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1385 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1386 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
546c4794 1387 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
65441f6f 1388 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1389 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1390 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
1391 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
32374e3c 1392 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
1393 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
35267be7 1394 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
1395 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1396 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
1397 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1398 RS6000_BTI_unsigned_V16QI, 0},
1399 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
1400 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1401 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
1402 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1403 RS6000_BTI_unsigned_V8HI, 0},
1404 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
1405 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1406 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
1407 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1408 RS6000_BTI_unsigned_V4SI, 0},
1409 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
1410 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1411 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
1412 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1413 RS6000_BTI_unsigned_V2DI, 0},
65441f6f 1414 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
1415 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1416 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
1417 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1418 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
1419 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1420 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
1421 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1422 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
1423 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1424 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
1425 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
ae52d0de 1426 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
1427 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1428 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
1429 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
65441f6f 1430 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
1431 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
32374e3c 1432 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
1433 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1434 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
1435 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1436 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
1437 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
65441f6f 1438 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
1439 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1440 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
1441 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
c4de79b6 1442 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
1443 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
1444 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
1445 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
65441f6f 1446 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
1447 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1448 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
1449 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1450 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
1451 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
c4de79b6 1452 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
1453 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
65441f6f 1454 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
1455 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
c4de79b6 1456 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
1457 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
32374e3c 1458 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
1459 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1460 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
1461 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
d5f3ed72 1462 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
1463 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1464 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
1465 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
a9c17725 1466 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
1467 RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
1468 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1469 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1911475f 1470
1471 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
1472 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1473 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
1474 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1475 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
1476 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1477
1478 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
1479 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1480 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
1481 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1482 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
1483 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1484
1485 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI,
1486 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1487 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI,
1488 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1489 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF,
1490 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1491
1492 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI,
1493 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1494 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI,
1495 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1496 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF,
1497 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1498
67d38f28 1499 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1500 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1501 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1502 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
e7db8bd2 1503 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF,
5cc94c58 1504 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
e7db8bd2 1505 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI,
67d38f28 1506 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
e7db8bd2 1507 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI,
67d38f28 1508 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1509 RS6000_BTI_unsigned_V2DI, 0 },
1510 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1511 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1512 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1513 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1514 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI,
1515 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1516 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF,
1517 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1518 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1519 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1520 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1521 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1522
9e1f8220 1523 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1524 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
1525 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1526 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 },
1527 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1528 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
1529 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1530 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
1531
b2633cce 1532 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
a501acda 1533 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
b2633cce 1534 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
a501acda 1535 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
b2633cce 1536 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
a501acda 1537 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1538 ~RS6000_BTI_unsigned_V2DI, 0 },
b2633cce 1539 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
a501acda 1540 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
b2633cce 1541 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
65441f6f 1542 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
b2633cce 1543 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
65441f6f 1544 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
b2633cce 1545 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
65441f6f 1546 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
b2633cce 1547 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
65441f6f 1548 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
b2633cce 1549 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
65441f6f 1550 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
b2633cce 1551 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
65441f6f 1552 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
b2633cce 1553 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
65441f6f 1554 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
b2633cce 1555 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
65441f6f 1556 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
b2633cce 1557 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
65441f6f 1558 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
b2633cce 1559 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
65441f6f 1560 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
b2633cce 1561 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
65441f6f 1562 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
b2633cce 1563 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
65441f6f 1564 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
b2633cce 1565 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
65441f6f 1566 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
b2633cce 1567 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
65441f6f 1568 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
b2633cce 1569 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
65441f6f 1570 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
b2633cce 1571 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
65441f6f 1572 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
b2633cce 1573 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
65441f6f 1574 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
b2633cce 1575 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
65441f6f 1576 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
b2633cce 1577 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
65441f6f 1578 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
b2633cce 1579 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
65441f6f 1580 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1581 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1582 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1583 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1584 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1585 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1586 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1587 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1588 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1589 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1590 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1591 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1592 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1593 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1594 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1595 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1596 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1597 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1598 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1599 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1600 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1601 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1602 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1603 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1604 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1605 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1606 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1607 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1608 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1609 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1610 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1611 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1612 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1613 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1614 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1615 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1616 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
d297c68a 1617
1618 /* vector float vec_ldl (int, vector float *);
1619 vector float vec_ldl (int, float *); */
b2633cce 1620 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
65441f6f 1621 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
b2633cce 1622 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
65441f6f 1623 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
d297c68a 1624
1625 /* vector bool int vec_ldl (int, vector bool int *);
1626 vector bool int vec_ldl (int, bool int *);
1627 vector int vec_ldl (int, vector int *);
1628 vector int vec_ldl (int, int *);
1629 vector unsigned int vec_ldl (int, vector unsigned int *);
1630 vector unsigned int vec_ldl (int, unsigned int *); */
b2633cce 1631 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
65441f6f 1632 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
d297c68a 1633 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1634 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 },
b2633cce 1635 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
65441f6f 1636 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
b2633cce 1637 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
65441f6f 1638 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
b2633cce 1639 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
65441f6f 1640 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
b2633cce 1641 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
65441f6f 1642 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
d297c68a 1643
1644 /* vector bool short vec_ldl (int, vector bool short *);
1645 vector bool short vec_ldl (int, bool short *);
1646 vector pixel vec_ldl (int, vector pixel *);
1647 vector short vec_ldl (int, vector short *);
1648 vector short vec_ldl (int, short *);
1649 vector unsigned short vec_ldl (int, vector unsigned short *);
1650 vector unsigned short vec_ldl (int, unsigned short *); */
b2633cce 1651 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
65441f6f 1652 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
d297c68a 1653 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1654 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 },
b2633cce 1655 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
65441f6f 1656 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
b2633cce 1657 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
65441f6f 1658 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
b2633cce 1659 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
65441f6f 1660 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
b2633cce 1661 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
65441f6f 1662 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
b2633cce 1663 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
65441f6f 1664 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
d297c68a 1665
1666 /* vector bool char vec_ldl (int, vector bool char *);
1667 vector bool char vec_ldl (int, bool char *);
1668 vector char vec_ldl (int, vector char *);
1669 vector char vec_ldl (int, char *);
1670 vector unsigned char vec_ldl (int, vector unsigned char *);
1671 vector unsigned char vec_ldl (int, unsigned char *); */
b2633cce 1672 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
65441f6f 1673 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
d297c68a 1674 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1675 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 },
b2633cce 1676 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
65441f6f 1677 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
b2633cce 1678 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
65441f6f 1679 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
b2633cce 1680 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
a501acda 1681 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1682 ~RS6000_BTI_unsigned_V16QI, 0 },
b2633cce 1683 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
65441f6f 1684 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
d297c68a 1685
1686 /* vector double vec_ldl (int, vector double *);
1687 vector double vec_ldl (int, double *); */
b2633cce 1688 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
a501acda 1689 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
d297c68a 1690 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1691 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1692
1693 /* vector long long vec_ldl (int, vector long long *);
1694 vector long long vec_ldl (int, long long *);
1695 vector unsigned long long vec_ldl (int, vector unsigned long long *);
1696 vector unsigned long long vec_ldl (int, unsigned long long *);
1697 vector bool long long vec_ldl (int, vector bool long long *);
1698 vector bool long long vec_ldl (int, bool long long *); */
b2633cce 1699 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
a501acda 1700 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
d297c68a 1701 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1702 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
b2633cce 1703 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
a501acda 1704 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1705 ~RS6000_BTI_unsigned_V2DI, 0 },
d297c68a 1706 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1707 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1708 ~RS6000_BTI_unsigned_long_long, 0 },
b2633cce 1709 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
a501acda 1710 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
d297c68a 1711 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1712 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 },
1713
65441f6f 1714 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1715 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1716 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1717 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1718 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1719 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1720 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1721 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1722 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1723 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1724 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1725 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1726 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1727 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1728 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1729 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1730 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1731 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
a501acda 1732 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1733 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1734 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1735 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1736 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1737 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1738 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1739 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1740 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1741 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1742 ~RS6000_BTI_unsigned_long_long, 0 },
65441f6f 1743 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1744 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1745 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1746 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1747 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1748 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1749 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1750 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1751 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1752 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1753 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1754 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1755 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1756 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1757 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1758 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1759 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1760 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
a501acda 1761 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1762 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1763 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1764 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1765 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1766 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1767 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1768 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1769 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1770 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1771 ~RS6000_BTI_unsigned_long_long, 0 },
3fd96979 1772 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1773 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1774 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1775 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1776 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1777 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1778 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1779 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1780 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1781 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1782 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1783 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1784 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1785 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1786 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1787 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1788 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1789 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1790 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1791 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1792 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1793 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1794 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1795 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1796 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1797 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1798 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1799 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1800 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1801 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1802 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1803 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1804 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1805 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1806 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1807 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1808 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1809 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1810 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1811 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1812 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1813 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1814 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1815 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1816 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1817 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1818 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1819 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1820 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1821 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1822 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1823 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1824 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1825 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1826 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1827 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1828 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1829 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1830 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1831 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1832 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1833 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1834 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1835 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1836 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1837 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1838 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1839 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1840 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1841 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1842 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1843 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1844 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1845 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1846 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1847 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1848 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1849 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1850 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1851 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1852 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1853 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1854 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1855 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1856 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1857 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1858 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1859 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1860 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1861 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1862 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1863 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1864 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1865 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1866 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1867 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1868 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1869 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1870 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1871 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1872 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1873 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1874 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1875 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1876 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1877 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1878 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1879 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1880 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1881 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1882 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1883 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1884 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1885 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1886 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1887 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1888 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1889 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1890 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1891 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1892 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1893 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1894 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1895 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1896 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1897 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1898 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1899 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1900 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1901 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1902 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1903 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1904 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1905 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1906 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1907 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1908 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1909 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1910 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1911 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1912 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1913 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1914 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1915 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
65441f6f 1916 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1917 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1918 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1919 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1920 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1921 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1922 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1923 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1924 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1925 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1926 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1927 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1928 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1929 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1930 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1931 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1932 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1933 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1934 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1935 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1936 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1937 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1938 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1939 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1940 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1941 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1942 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1943 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1944 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1945 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1946 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1947 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1948 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1949 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1950 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1951 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
ae52d0de 1952 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1953 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1954 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1955 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1956 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1957 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1958 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1959 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1960 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1961 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1962 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1963 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
65441f6f 1964 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
1965 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
32374e3c 1966 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
1967 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
65441f6f 1968 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
1969 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1970 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1971 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1972 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1973 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1974 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1975 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1976 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1977 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1978 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1979 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1980 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1981 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1982 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1983 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1984 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1985 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1986 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1987 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1988 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1989 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1990 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1991 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1992 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1993 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1994 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1995 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1996 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1997 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1998 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1999 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2000 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2001 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2002 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
2003 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2004 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
2005 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2006 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
2007 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2008 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2009 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2010 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2011 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2012 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2013 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2014 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2015 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2016 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2017 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2018 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
2019 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2020 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
2021 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2022 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
2023 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2024 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2025 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2026 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2027 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2028 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2029 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2030 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2031 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2032 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2033 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2034 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2035 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2036 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2037 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2038 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2039 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
e3e1b729 2040 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
2041 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2042 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2043 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
271b79e4 2044 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2045 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2046 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2047 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2048 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2049 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2050 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2051 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2052 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2053 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
a9c17725 2054 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2055 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
65441f6f 2056 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2057 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2058 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2059 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2060 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2061 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2062 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2063 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2064 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2065 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2066 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2067 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2068 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2069 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2070 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2071 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2072 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2073 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2074 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2075 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2076 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2077 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2078 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2079 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2080 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2081 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2082 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2083 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2084 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2085 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2086 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2087 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2088 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2089 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2090 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2091 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2092 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2093 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2094 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2095 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2096 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2097 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2098 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2099 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
e3e1b729 2100 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
2101 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2102 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2103 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
271b79e4 2104 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2105 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2106 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2107 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2108 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2109 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2110 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2111 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2112 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2113 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
a9c17725 2114 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2115 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
65441f6f 2116 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2117 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2118 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2119 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2120 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2121 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2122 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2123 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2124 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2125 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2126 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2127 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2128 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2129 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2130 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2131 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2132 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2133 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2134 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2135 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2136 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2137 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2138 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2139 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2140 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2141 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2142 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2143 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2144 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2145 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2146 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2147 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2148 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2149 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2150 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2151 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2152 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2153 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2154 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2155 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2156 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2157 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2158 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2159 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2160 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2161 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2162 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2163 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2164 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2165 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2166 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2167 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2168 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2169 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2170 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2171 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2172 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2173 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
ae52d0de 2174 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2175 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2176 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2177 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2178 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2179 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2180 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2181 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2182 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2183 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2184 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2185 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
65441f6f 2186 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
2187 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
32374e3c 2188 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
2189 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
65441f6f 2190 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
2191 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2192 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2193 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2194 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2195 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2196 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2197 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2198 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2199 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2200 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2201 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2202 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2203 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2204 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2205 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2206 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2207 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2208 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2209 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2210 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2211 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2212 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2213 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2214 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2215 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2216 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2217 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2218 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2219 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2220 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2221 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2222 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2223 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2224 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2225 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2226 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2227 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2228 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2229 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2230 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2231 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2232 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2233 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2234 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2235 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2236 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2237 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2238 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2239 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2240 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
2241 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2242 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
2243 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2244 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
2245 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2246 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2247 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
8bb7c9b7 2248 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
da31e631 2249 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
8bb7c9b7 2250 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
da31e631 2251 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
33d39774 2252 RS6000_BTI_unsigned_V4SI, 0 },
65441f6f 2253 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
2254 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2255 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
2256 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2257 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
2258 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2259 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
2260 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
8bb7c9b7 2261 { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
934c5284 2262 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
8bb7c9b7 2263 { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
934c5284 2264 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
65441f6f 2265 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
2266 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2267 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
2268 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2269 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
2270 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
8bb7c9b7 2271 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW,
da31e631 2272 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
8bb7c9b7 2273 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
da31e631 2274 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
33d39774 2275 RS6000_BTI_unsigned_V4SI, 0 },
65441f6f 2276 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2277 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2278 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
2279 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2280 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
2281 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2282 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
2283 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2284 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
2285 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
8bb7c9b7 2286 { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW,
934c5284 2287 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
8bb7c9b7 2288 { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW,
934c5284 2289 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2290
85d4e063 2291 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
2292 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2293 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
2294 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2295 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
2296 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2297 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
2298 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2299 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
2300 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2301 { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
2302 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
32374e3c 2303 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
2304 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2305 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
2306 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
16f61488 2307
65441f6f 2308 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2309 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
702c5d85 2310 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2311 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
271b79e4 2312 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2313 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2314 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2315 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2316 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2317 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2318 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2319 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2320 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2321 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2322 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2323 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
a9c17725 2324 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2325 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
65441f6f 2326 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2327 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2328 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2329 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2330 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2331 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2332 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2333 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2334 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2335 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2336 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2337 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2338 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2339 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2340 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2341 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2342 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2343 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2344 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2345 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2346 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2347 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
2348 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2349 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
702c5d85 2350 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2351 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2352 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
32374e3c 2353 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
702c5d85 2354 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
32374e3c 2355 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
271b79e4 2356 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2357 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2358 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2359 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2360 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2361 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2362 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2363 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2364 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2365 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2366 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2367 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
a9c17725 2368 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2369 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
65441f6f 2370 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2371 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2372 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2373 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2374 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2375 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2376 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2377 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2378 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2379 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2380 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2381 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2382 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2383 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2384 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2385 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2386 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2387 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2388 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2389 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2390 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2391 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2392 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2393 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2394 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2395 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2396 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2397 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2398 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2399 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2400 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2401 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2402 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2403 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2404 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2405 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2406 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2407 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2408 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2409 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2410 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2411 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2412 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2413 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2414 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2415 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2416 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2417 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2418 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2419 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2420 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2421 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2422 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2423 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
ae52d0de 2424 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2425 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2426 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2427 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2428 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2429 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
37a0a76c 2430 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF,
e691d850 2431 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
b3f0e7fb 2432
747cac42 2433 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI,
2434 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2435 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI,
2436 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2437 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI,
2438 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2439 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI,
2440 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2441 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF,
2442 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2443 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF,
2444 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2445
b3f0e7fb 2446 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
2447 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2448
f9afdf24 2449 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2450 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2451 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2452 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2453 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2454 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2455 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2456 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2457 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2458 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2459 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2460 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2461 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2462 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2463 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2464 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2465 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2466 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2467 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2468 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2469 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2470 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2471 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2472 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2473 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2474 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2475 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2476 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2477 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2478 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2479 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2480 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2481 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2482 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2483 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2484 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2485
2486 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2487 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI,
2488 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2489 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2490 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI,
2491 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2492 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2493 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2494 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2495 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2496 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2497 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2498 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2499 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2500 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2501 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2502 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2503 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2504
65441f6f 2505 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2506 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2507 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2508 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2509 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2510 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2511 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2512 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2513 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2514 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2515 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2516 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2517 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2518 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2519 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2520 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2521 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2522 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2523 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2524 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2525 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2526 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
ae52d0de 2527 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2528 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2529 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2530 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
8a3ae1e6 2531 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2532 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2533 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2534 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
65441f6f 2535 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2536 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2537 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2538 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2539 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2540 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2541 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2542 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2543 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2544 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2545 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2546 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
ae52d0de 2547 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2548 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
755a9c21 2549 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS,
271b79e4 2550 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
65441f6f 2551 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2552 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2553 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2554 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
32374e3c 2555 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2556 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2557 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2558 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
65441f6f 2559 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2560 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2561 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2562 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2563 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2564 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2565 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2566 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2567 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2568 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2569 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2570 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
ae52d0de 2571 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2572 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2573 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2574 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
65441f6f 2575 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2576 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2577 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2578 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2579 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2580 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2581 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2582 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2583 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2584 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2585 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2586 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3bc3ba6f 2587 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2588 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2589 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2590 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2591 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2592 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2593 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2594 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2595 RS6000_BTI_unsigned_V4SI, 0 },
2596 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2597 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2598 RS6000_BTI_unsigned_V2DI, 0 },
65441f6f 2599 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2600 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2601 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2602 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2603 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2604 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2605 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2606 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2607 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2608 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2609 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2610 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
ae52d0de 2611 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2612 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2613 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2614 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
32374e3c 2615 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2616 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2617 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2618 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
65441f6f 2619 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2620 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2621 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2622 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2623 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2624 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2625 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2626 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2627 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2628 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2629 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2630 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2631 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2632 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2633 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2634 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2635 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2636 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2637 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2638 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2639 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2640 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2641 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2642 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2643 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2644 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2645 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2646 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2647 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2648 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2649 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2650 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2651 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2652 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2653 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2654 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2655 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2656 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2657 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2658 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2659 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2660 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2661 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2662 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2663 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2664 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2665 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2666 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2667 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2668 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2669 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2670 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2671 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2672 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2673 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2674 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2675 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2676 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2677 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2678 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2679 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2680 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2681 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2682 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2683 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2684 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2685 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2686 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2687 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2688 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2689 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2690 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
a7aebe61 2691
2692 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2693 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2694 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2695 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2696 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2697 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2698 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2699 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2700 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2701 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 },
2702
65441f6f 2703 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2704 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2705 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2706 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2707 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2708 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2709 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2710 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2711 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2712 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2713 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2714 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2715 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2716 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2717 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2718 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2719 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2720 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2721 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2722 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2723 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2724 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2725 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2726 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2727 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2728 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2729 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2730 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2731 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2732 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2733 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2734 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
c6bd4248 2735 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2736 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2737 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2738 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2739 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2740 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2741 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2742 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
65441f6f 2743 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2744 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2745 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2746 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2747 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2748 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2749 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2750 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2751 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2752 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2753 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2754 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2755 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2756 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2757 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2758 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2759 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2760 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2761 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2762 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2763 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2764 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
d5f3ed72 2765 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2766 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2767 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2768 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2769 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2770 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2771 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2772 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
65441f6f 2773 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2774 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2775 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2776 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2777 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2778 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2779 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2780 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2781 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2782 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2783 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2784 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2785 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2786 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2787 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2788 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2789 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2790 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2791 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2792 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2793 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2794 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2795 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2796 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2797 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2798 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2799 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2800 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2801 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2802 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2803 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2804 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2805 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2806 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
ae52d0de 2807 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2808 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2809 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2810 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
65441f6f 2811 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2812 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2813 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2814 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2815 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2816 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2817 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2818 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2819 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2820 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2821 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2822 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2823 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2824 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2825 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2826 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2827 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2828 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2829 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2830 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2831 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2832 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2833 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2834 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
ae52d0de 2835 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2836 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
954344f9 2837 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
ae52d0de 2838 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
65441f6f 2839 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2840 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2841 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2842 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2843 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2844 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2845 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2846 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2847 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2848 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2849 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2850 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2851 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2852 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2853 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2854 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2855 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2856 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2857 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2858 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2859 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2860 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2861 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2862 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2863 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2864 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2865 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2866 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2867 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2868 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2869 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2870 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2871 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2872 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2873 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2874 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2875 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2876 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2877 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2878 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2879 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2880 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2881 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2882 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2883 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2884 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2885 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2886 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2887 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2888 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2889 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2890 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2891 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2892 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2893 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2894 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2895 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2896 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2897 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2898 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2899 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2900 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2901 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2902 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2903 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2904 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2905 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2906 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2907 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2908 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2909 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2910 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
a7aebe61 2911 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2912 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2913 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2914 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
65441f6f 2915 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2916 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2917 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2918 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2919 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2920 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2921 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2922 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2923 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2924 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2925 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2926 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2927 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2928 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2929 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2930 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2931 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2932 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2933 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2934 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2935 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2936 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2937 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2938 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2939 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2940 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2941 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2942 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2943 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2944 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2945 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2946 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
a7aebe61 2947 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2948 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2949 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2950 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2951 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2952 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2953 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2954 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2955
65441f6f 2956 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2957 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2958 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2959 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2960 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2961 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2962 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2963 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2964 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2965 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2966 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2967 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2968 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2969 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2970 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2971 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2972 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2973 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2974 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2975 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2976 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2977 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2978 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2979 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2980 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2981 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2982 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2983 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2984 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2985 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2986 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2987 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2988 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2989 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2990 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2991 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
ae52d0de 2992 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2993 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2994 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2995 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2996 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2997 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2998 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2999 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3000 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3001 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3002 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3003 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
65441f6f 3004 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
3005 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
32374e3c 3006 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
3007 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
ae61c502 3008 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
3009 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
3010 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
3011 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
3012 RS6000_BTI_unsigned_V1TI, 0 },
65441f6f 3013 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
3014 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3015 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3016 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3017 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3018 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3019 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3020 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3021 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3022 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3023 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3024 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3025 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3026 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3027 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3028 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
3029 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3030 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3031 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3032 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3033 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3034 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3035 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3036 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
3037 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3038 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3039 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3040 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3041 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3042 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3043 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3044 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3045 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3046 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3047 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3048 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3049 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3050 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3051 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3052 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3053 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3054 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3055 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3056 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3057 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3058 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3059 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3060 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3061 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3062 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4a777525 3063
3064 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
3065 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
65441f6f 3066 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
3067 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4a777525 3068 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
3069 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
3070 RS6000_BTI_unsigned_V1TI, 0 },
3071 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
3072 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
3073
65441f6f 3074 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
3075 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3076 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
3077 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3078 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
3079 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3080 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
3081 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3082 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
3083 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3084 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
3085 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3086 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
3087 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3088 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
3089 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3090 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
3091 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3092 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
3093 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3094 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
3095 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3096 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
3097 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3098 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
3099 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3100 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
3101 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3102 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
3103 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3104 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
3105 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3106 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
3107 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3108 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
3109 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3110 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
3111 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3112 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
3113 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3114 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
3115 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3116 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3117 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3118 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3119 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
3120 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3121 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3122 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3123 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3124 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3125 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3126 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3127 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3128 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3129 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3130 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3131 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3132 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3133 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3134 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3135 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
3136 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3137 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3138 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3139 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3140 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3141 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3142 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3143 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3144 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3145 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3146 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3147 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3148 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3149 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3150 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3151 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3152 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3153 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3154 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3155 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3156 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3157 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3158 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
3159 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3160 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
3161 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3162 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
3163 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3164 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
3165 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3166 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
3167 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3168 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
3169 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3170 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
3171 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3172 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
3173 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3ef84acc 3174
3175 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
d94e6223 3176 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3ef84acc 3177 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
d94e6223 3178 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
515e04bd 3179 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3180 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3181 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3182 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
3183 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3184 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3ef84acc 3185 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
d94e6223 3186 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3ef84acc 3187 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
d94e6223 3188 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
515e04bd 3189 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3190 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
3ef84acc 3191 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
d94e6223 3192 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3193 ~RS6000_BTI_unsigned_V2DI, 0 },
3ef84acc 3194 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
d94e6223 3195 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3196 ~RS6000_BTI_unsigned_long_long, 0 },
515e04bd 3197 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3198 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
3199
3ef84acc 3200 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
d94e6223 3201 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3ef84acc 3202 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
d94e6223 3203 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3ef84acc 3204 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
d94e6223 3205 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3ef84acc 3206 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
d94e6223 3207 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3ef84acc 3208 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
d94e6223 3209 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3ef84acc 3210 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
d94e6223 3211 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3ef84acc 3212 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
d94e6223 3213 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3ef84acc 3214 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
d94e6223 3215 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3ef84acc 3216 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
d94e6223 3217 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3ef84acc 3218 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
d94e6223 3219 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3ef84acc 3220 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
d94e6223 3221 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3ef84acc 3222 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
d94e6223 3223 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3ef84acc 3224 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
d94e6223 3225 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3226 ~RS6000_BTI_unsigned_V16QI, 0 },
3ef84acc 3227 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
f7b0548e 3228 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3ef84acc 3229
3230 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3231 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3232 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3233 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
515e04bd 3234 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3235 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3236 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3237 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3ef84acc 3238 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3239 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3240 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
f7b0548e 3241 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3ef84acc 3242 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3243 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3244 ~RS6000_BTI_unsigned_V2DI, 0 },
3245 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3246 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3247 ~RS6000_BTI_unsigned_long_long, 0 },
3248 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
3249 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3250 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
f7b0548e 3251 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3ef84acc 3252 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3253 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3254 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3255 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3256 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3257 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3258 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3259 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3260 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3261 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3262 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3263 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3264 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3265 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3266 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3267 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3268 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3269 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3270 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3271 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3272 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3273 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3274 ~RS6000_BTI_unsigned_V16QI, 0 },
3275 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3276 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
65441f6f 3277 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3278 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3279 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3280 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
3281 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3282 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
702c5d85 3283 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3284 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3285 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
32374e3c 3286 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
702c5d85 3287 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
32374e3c 3288 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
271b79e4 3289 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3290 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3291 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3292 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3293 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3294 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3295 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3296 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3297 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3298 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3299 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3300 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
a9c17725 3301 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3302 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
65441f6f 3303 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3304 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
3305 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3306 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3307 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3308 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3309 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3310 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3311 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3312 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3313 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3314 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3315 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3316 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3317 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3318 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
3319 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3320 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3321 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3322 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3323 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3324 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3325 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3326 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3327 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3328 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3329 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3330 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3331 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3332 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3333 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3334 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
3335 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3336 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3337 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3338 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3339 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3340 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3341 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3342 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3343 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3344 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3345
32374e3c 3346 /* Ternary AltiVec/VSX builtins. */
65441f6f 3347 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3348 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3349 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3350 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3351 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3352 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3353 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3354 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3355 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3356 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3357 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3358 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3359 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3360 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3361 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3362 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3363 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3364 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3365 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3366 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3367 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3368 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3369 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3370 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3371 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3372 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3373 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3374 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3375 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3376 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3377 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3378 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3379 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3380 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3381 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3382 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3383 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3384 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3385 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3386 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3387 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3388 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3389 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3390 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3391 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3392 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3393 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3394 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3395 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3396 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3397 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3398 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3399 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3400 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3401 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3402 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3403 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3404 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3405 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3406 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3407 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3408 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3409 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3410 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3411 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3412 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3413 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3414 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3415 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3416 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3417 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3418 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3419 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3420 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3421 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3422 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3423 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3424 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3425 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3426 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3427 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3428 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3429 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3430 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3431 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3432 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3433 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3434 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3435 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3436 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3437 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3438 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3439 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3440 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3441 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3442 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3443 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3444 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3445 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3446 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3447 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3448 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3449 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3450 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3451 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3452 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3453 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3454 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3455 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3456 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3457 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3458 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3459 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3460 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3461 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3462 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3463 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3464 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3465 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3466 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3467 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3468 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3469 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3470 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3471 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3472 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3473 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3474 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3475 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3476 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3477 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3478 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3479 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3480 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3481 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3482 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3483 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3484 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3485 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3486 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3487 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3488 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3489 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3490 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3491 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3492 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3493 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3494 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3495 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3496 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3497 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3498 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3499 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3500 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3501 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3502 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3503 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3504 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3505 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3506 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3507 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3508 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
32374e3c 3509 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3510 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
f2e7ec4a 3511 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3512 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3513 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3514 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3515 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3516 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3517 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3518 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
65441f6f 3519 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3520 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3521 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3522 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3523 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3524 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3525 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3526 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3527 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3528 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3529 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3530 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
32374e3c 3531 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3532 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3533 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3534 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
65441f6f 3535 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3536 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3537 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3538 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3539 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3540 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3541 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3542 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3543 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3544 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3545 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3546 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3547 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3548 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3549 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3550 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3551 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3552 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3553 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3554 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3555 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3556 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3557 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3558 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
32374e3c 3559 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3560 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3561 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3562 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
65441f6f 3563 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3564 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
32374e3c 3565 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3566 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
702c5d85 3567 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3568 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3569 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3570 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
271b79e4 3571 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3572 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
a9c17725 3573 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3574 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3575 RS6000_BTI_unsigned_V16QI },
65441f6f 3576 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3577 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3578 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3579 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3580 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3581 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3582 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3583 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3584 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3585 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3586 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3587 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3588 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3589 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3590 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3591 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3592 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3593 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3594 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3595 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3596 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3597 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3598 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3599 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3600 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3601 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
6d164b20 3602
3603 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3604 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
3605 RS6000_BTI_bool_V16QI },
3606 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3607 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3608 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3609 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3610 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3611
702c5d85 3612 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3613 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3614 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3615 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3616 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3617 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3618 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3619 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3620 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3621 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3622 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3623 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3624 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3625 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
271b79e4 3626 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3627 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3628 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3629 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3630 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3631 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
a9c17725 3632 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3633 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3634 RS6000_BTI_bool_V2DI },
3635 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3636 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3637 RS6000_BTI_unsigned_V2DI },
65441f6f 3638 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3639 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3640 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3641 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
702c5d85 3642 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3643 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3644 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3645 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
65441f6f 3646 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3647 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3648 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3649 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3650 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3651 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3652 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3653 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3654 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3655 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3656 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3657 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3658 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3659 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3660 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3661 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3662 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3663 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3664 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3665 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3666 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3667 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3668 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3669 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3670 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3671 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3672 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3673 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3674 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3675 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3676 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3677 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3678 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3679 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3680 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3681 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3682 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
1b5cf007 3683 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
65441f6f 3684 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
1b5cf007 3685 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
65441f6f 3686 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
1b5cf007 3687 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI },
65441f6f 3688 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
1b5cf007 3689 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
65441f6f 3690 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
1b5cf007 3691 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
65441f6f 3692 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
1b5cf007 3693 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
65441f6f 3694 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
1b5cf007 3695 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI },
65441f6f 3696 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
1b5cf007 3697 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI },
65441f6f 3698 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
1b5cf007 3699 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
65441f6f 3700 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
1b5cf007 3701 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
65441f6f 3702 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
1b5cf007 3703 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI },
e691d850 3704 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
1b5cf007 3705 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
a7aebe61 3706 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
1b5cf007 3707 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI },
a7aebe61 3708 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
1b5cf007 3709 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
a7aebe61 3710 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
1b5cf007 3711 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
a7aebe61 3712
33d39774 3713 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3714 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
1b5cf007 3715 RS6000_BTI_INTSI },
33d39774 3716 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3717 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
1b5cf007 3718 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
33d39774 3719 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3720 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
1b5cf007 3721 RS6000_BTI_INTSI },
33d39774 3722 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3723 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
1b5cf007 3724 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
33d39774 3725 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3726 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
1b5cf007 3727 RS6000_BTI_INTSI },
33d39774 3728 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3729 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1b5cf007 3730 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
33d39774 3731 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3732 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
1b5cf007 3733 RS6000_BTI_INTSI },
33d39774 3734 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3735 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
1b5cf007 3736 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3737
b2633cce 3738 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
a501acda 3739 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
b2633cce 3740 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
a501acda 3741 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
b2633cce 3742 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
a501acda 3743 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3744 ~RS6000_BTI_unsigned_V2DI },
b2633cce 3745 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
a501acda 3746 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3747 ~RS6000_BTI_bool_V2DI },
b2633cce 3748 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
65441f6f 3749 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
b2633cce 3750 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
65441f6f 3751 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
b2633cce 3752 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
65441f6f 3753 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
b2633cce 3754 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
65441f6f 3755 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
b2633cce 3756 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
65441f6f 3757 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
b2633cce 3758 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
65441f6f 3759 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
b2633cce 3760 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
65441f6f 3761 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
b2633cce 3762 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
65441f6f 3763 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
b2633cce 3764 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
65441f6f 3765 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
b2633cce 3766 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
65441f6f 3767 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
b2633cce 3768 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
65441f6f 3769 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
b2633cce 3770 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
65441f6f 3771 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
b2633cce 3772 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
65441f6f 3773 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
b2633cce 3774 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
65441f6f 3775 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
b2633cce 3776 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
65441f6f 3777 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
b2633cce 3778 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
65441f6f 3779 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
b2633cce 3780 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
65441f6f 3781 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
b2633cce 3782 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
65441f6f 3783 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
b2633cce 3784 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
65441f6f 3785 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
b2633cce 3786 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
65441f6f 3787 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
b2633cce 3788 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
65441f6f 3789 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
b2633cce 3790 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
65441f6f 3791 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
b2633cce 3792 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
65441f6f 3793 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
b2633cce 3794 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
65441f6f 3795 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3796 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3797 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3798 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3799 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3800 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3801 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3802 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3803 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3804 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3805 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3806 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3807 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3808 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3809 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3810 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3811 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3812 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3813 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3814 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3815 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3816 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3817 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3818 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3819 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3820 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3821 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3822 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3823 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3824 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3825 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3826 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3827 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3828 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3829 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3830 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3831 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3832 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3833 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3834 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3835 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3836 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3837 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3838 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3839 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3840 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3841 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3842 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3843 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3844 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3845 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3846 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3847 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3848 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3849 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3850 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3851 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3852 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3853 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3854 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3855 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3856 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3857 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3858 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3859 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3860 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3861 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3862 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3863 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3864 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3865 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
b2633cce 3866 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
65441f6f 3867 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
b2633cce 3868 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
65441f6f 3869 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
b2633cce 3870 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
65441f6f 3871 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
b2633cce 3872 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
65441f6f 3873 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
b2633cce 3874 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
65441f6f 3875 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
b2633cce 3876 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
65441f6f 3877 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
b2633cce 3878 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
65441f6f 3879 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
b2633cce 3880 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
65441f6f 3881 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
b2633cce 3882 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
65441f6f 3883 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
b2633cce 3884 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
65441f6f 3885 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
b2633cce 3886 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
65441f6f 3887 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
b2633cce 3888 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
65441f6f 3889 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
b2633cce 3890 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
65441f6f 3891 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
b2633cce 3892 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
65441f6f 3893 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
b2633cce 3894 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
65441f6f 3895 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
b2633cce 3896 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
65441f6f 3897 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
b2633cce 3898 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
65441f6f 3899 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
b2633cce 3900 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
65441f6f 3901 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
b2633cce 3902 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
65441f6f 3903 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
b2633cce 3904 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
65441f6f 3905 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
b2633cce 3906 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
65441f6f 3907 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
b2633cce 3908 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
65441f6f 3909 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
b2633cce 3910 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
65441f6f 3911 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
b2633cce 3912 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
65441f6f 3913 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
b2633cce 3914 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
a501acda 3915 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
b2633cce 3916 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
a501acda 3917 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
b2633cce 3918 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
a501acda 3919 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
b2633cce 3920 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
a501acda 3921 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3922 ~RS6000_BTI_unsigned_V2DI },
b2633cce 3923 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
a501acda 3924 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3925 ~RS6000_BTI_bool_V2DI },
3fd96979 3926 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3927 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3928 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3929 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3930 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3931 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3932 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3933 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3934 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3935 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3936 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3937 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3938 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3939 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3940 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3941 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3942 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3943 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3944 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3945 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3946 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3947 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3948 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3949 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3950 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3951 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3952 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3953 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3954 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3955 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3956 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3957 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3958 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3959 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3960 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3961 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3962 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3963 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3964 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3965 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3966 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3967 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3968 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3969 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3970 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3971 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3972 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3973 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3974 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3975 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3976 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3977 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3978 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3979 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3980 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3981 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3982 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3983 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3984 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3985 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3986 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3987 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3988 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3989 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3990 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3991 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3992 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3993 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3994 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3995 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3996 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3997 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3998 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3999 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4000 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4001 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4002 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4003 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4004 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4005 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4006 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4007 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4008 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4009 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4010 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4011 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4012 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4013 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4014 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4015 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4016 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4017 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4018 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4019 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4020 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4021 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4022 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4023 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4024 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4025 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4026 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4027 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4028 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4029 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4030 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4031 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4032 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4033 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4034 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4035 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4036 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4037 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4038 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4039 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4040 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4041 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4042 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4043 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4044 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4045 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4046 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4047 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4048 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4049 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4050 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4051 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4052 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4053 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4054 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4055 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4056 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4057 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4058 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4059 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4060 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4061 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4062 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4063 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4064 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4065 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4066 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4067 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4068 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4069 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3ef84acc 4070 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
4071 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
0e5c4a3d 4072 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
4073 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3ef84acc 4074 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4075 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
0e5c4a3d 4076 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4077 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
4078 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void,
4079 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long },
3ef84acc 4080 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4081 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4082 ~RS6000_BTI_unsigned_V2DI },
4083 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4084 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4085 ~RS6000_BTI_bool_V2DI },
4086 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
4087 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4088 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
4089 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4090 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4091 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4092 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4093 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4094 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4095 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4096 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4097 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4098 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4099 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4100 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4101 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4102 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4103 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4104 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4105 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4106 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4107 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4108 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4109 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4110 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4111 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4112 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4113 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4114 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4115 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4116 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4117 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4118 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4119 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4120 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4121 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4122 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4123 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4124 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4125 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4126 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4127 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4128 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4129 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4130 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4131 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4132 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4133 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4134 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
d94e6223 4135 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3ef84acc 4136 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
d94e6223 4137 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
515e04bd 4138 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
4139 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI },
4140 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
4141 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI },
3ef84acc 4142 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
d94e6223 4143 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3ef84acc 4144 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
d94e6223 4145 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
4146 ~RS6000_BTI_long_long },
3ef84acc 4147 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
d94e6223 4148 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4149 ~RS6000_BTI_unsigned_V2DI },
3ef84acc 4150 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
d94e6223 4151 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4152 ~RS6000_BTI_unsigned_long_long },
3ef84acc 4153 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
d94e6223 4154 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3ef84acc 4155 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
d94e6223 4156 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3ef84acc 4157 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
d94e6223 4158 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3ef84acc 4159 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
d94e6223 4160 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3ef84acc 4161 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
d94e6223 4162 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4163 ~RS6000_BTI_unsigned_V4SI },
3ef84acc 4164 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
d94e6223 4165 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4166 ~RS6000_BTI_UINTSI },
3ef84acc 4167 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
d94e6223 4168 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3ef84acc 4169 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
d94e6223 4170 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3ef84acc 4171 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
d94e6223 4172 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4173 ~RS6000_BTI_unsigned_V8HI },
3ef84acc 4174 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
d94e6223 4175 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4176 ~RS6000_BTI_UINTHI },
3ef84acc 4177 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
d94e6223 4178 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3ef84acc 4179 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
d94e6223 4180 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3ef84acc 4181 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
d94e6223 4182 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4183 ~RS6000_BTI_unsigned_V16QI },
3ef84acc 4184 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
d94e6223 4185 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4186 ~RS6000_BTI_UINTQI },
32374e3c 4187 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
1b5cf007 4188 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
32374e3c 4189 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
4190 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
1b5cf007 4191 RS6000_BTI_INTSI },
32374e3c 4192 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
1b5cf007 4193 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
32374e3c 4194 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
4195 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
1b5cf007 4196 RS6000_BTI_INTSI },
32374e3c 4197 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
1b5cf007 4198 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
32374e3c 4199 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
4200 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1b5cf007 4201 RS6000_BTI_INTSI },
32374e3c 4202 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
1b5cf007 4203 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
32374e3c 4204 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
4205 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
1b5cf007 4206 RS6000_BTI_INTSI },
32374e3c 4207 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
1b5cf007 4208 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
32374e3c 4209 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
1b5cf007 4210 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
4211
32374e3c 4212 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
1b5cf007 4213 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
32374e3c 4214 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
1b5cf007 4215 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
32374e3c 4216 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
4217 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
1b5cf007 4218 RS6000_BTI_INTSI },
32374e3c 4219 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
1b5cf007 4220 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
32374e3c 4221 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
1b5cf007 4222 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
32374e3c 4223 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
4224 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1b5cf007 4225 RS6000_BTI_INTSI },
32374e3c 4226 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
1b5cf007 4227 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
32374e3c 4228 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
4229 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
1b5cf007 4230 RS6000_BTI_INTSI },
32374e3c 4231 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
1b5cf007 4232 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
32374e3c 4233 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
4234 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
1b5cf007 4235 RS6000_BTI_INTSI },
65441f6f 4236
a501acda 4237 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
4238 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3ab2fd6f 4239 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
4240 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
a501acda 4241 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4242 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
515e04bd 4243 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4244 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
4245 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4246 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
515e04bd 4247 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4248 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
a501acda 4249 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4250 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4251 ~RS6000_BTI_unsigned_V2DI, 0 },
515e04bd 4252 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4253 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
a501acda 4254 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4255 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
4256 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
4257 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
4258 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
4259 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
4260 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4261 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
4262 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4263 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
4264 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4265 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
4266 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4267 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
4268 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4269 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4270 ~RS6000_BTI_unsigned_V4SI, 0 },
4271 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4272 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
4273 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4274 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4275 ~RS6000_BTI_unsigned_long, 0 },
4276 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4277 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
4278 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4279 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
4280 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4281 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
4282 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4283 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
4284 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4285 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4286 ~RS6000_BTI_unsigned_V8HI, 0 },
4287 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4288 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
4289 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4290 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
4291 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4292 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
4293 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4294 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
4295 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4296 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4297 ~RS6000_BTI_unsigned_V16QI, 0 },
4298 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4299 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4300
4301 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4302 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3ab2fd6f 4303 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4304 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
515e04bd 4305 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4306 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI,
4307 ~RS6000_BTI_long_long },
4308 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4309 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI,
4310 ~RS6000_BTI_unsigned_long_long },
4311 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4312 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI },
4313 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4314 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI },
a501acda 4315 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4316 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4317 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4318 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4319 ~RS6000_BTI_unsigned_V2DI },
4320 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4321 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4322 ~RS6000_BTI_bool_V2DI },
4323 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4324 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4325 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4326 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4327 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4328 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4329 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4330 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4331 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4332 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4333 ~RS6000_BTI_unsigned_V4SI },
4334 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4335 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4336 ~RS6000_BTI_UINTSI },
4337 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4338 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4339 ~RS6000_BTI_bool_V4SI },
4340 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4341 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4342 ~RS6000_BTI_UINTSI },
4343 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4344 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4345 ~RS6000_BTI_INTSI },
4346 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4347 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4348 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4349 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4350 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4351 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4352 ~RS6000_BTI_unsigned_V8HI },
4353 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4354 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4355 ~RS6000_BTI_UINTHI },
4356 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4357 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4358 ~RS6000_BTI_bool_V8HI },
4359 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4360 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4361 ~RS6000_BTI_UINTHI },
4362 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4363 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4364 ~RS6000_BTI_INTHI },
4365 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4366 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4367 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4368 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4369 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4370 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4371 ~RS6000_BTI_unsigned_V16QI },
4372 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4373 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4374 ~RS6000_BTI_UINTQI },
4375 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4376 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4377 ~RS6000_BTI_bool_V16QI },
4378 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4379 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4380 ~RS6000_BTI_UINTQI },
4381 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4382 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4383 ~RS6000_BTI_INTQI },
4384 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4385 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
4386 ~RS6000_BTI_pixel_V8HI },
4387
65441f6f 4388 /* Predicates. */
0375b229 4389 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
65441f6f 4390 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
0375b229 4391 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
65441f6f 4392 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
0375b229 4393 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
65441f6f 4394 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
0375b229 4395 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
65441f6f 4396 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
0375b229 4397 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
65441f6f 4398 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
0375b229 4399 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
65441f6f 4400 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
0375b229 4401 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
65441f6f 4402 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
0375b229 4403 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
65441f6f 4404 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
0375b229 4405 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
65441f6f 4406 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
0375b229 4407 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
65441f6f 4408 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
0375b229 4409 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
65441f6f 4410 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
0375b229 4411 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
65441f6f 4412 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
0375b229 4413 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
65441f6f 4414 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
0375b229 4415 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
65441f6f 4416 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
0375b229 4417 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
65441f6f 4418 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
0375b229 4419 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
65441f6f 4420 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
0375b229 4421 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
65441f6f 4422 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
0375b229 4423 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
65441f6f 4424 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
271b79e4 4425 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4426 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4427 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4428 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4429 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4430 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4431 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4432 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4433 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4434 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4435 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4436 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
0375b229 4437 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
65441f6f 4438 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
0375b229 4439 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
32374e3c 4440 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
65441f6f 4441
4442
0375b229 4443 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
65441f6f 4444 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
0375b229 4445 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
65441f6f 4446 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
0375b229 4447 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
65441f6f 4448 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
0375b229 4449 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
65441f6f 4450 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
0375b229 4451 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
65441f6f 4452 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
0375b229 4453 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
65441f6f 4454 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
0375b229 4455 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
65441f6f 4456 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
0375b229 4457 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
65441f6f 4458 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
0375b229 4459 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
65441f6f 4460 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
0375b229 4461 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
65441f6f 4462 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
0375b229 4463 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
65441f6f 4464 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
0375b229 4465 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
65441f6f 4466 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
0375b229 4467 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
65441f6f 4468 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
0375b229 4469 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
65441f6f 4470 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
0375b229 4471 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
65441f6f 4472 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
0375b229 4473 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
65441f6f 4474 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
0375b229 4475 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
65441f6f 4476 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
0375b229 4477 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
65441f6f 4478 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
0375b229 4479 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
65441f6f 4480 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
0375b229 4481 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
65441f6f 4482 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
0375b229 4483 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
65441f6f 4484 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
0375b229 4485 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
65441f6f 4486 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
ae52d0de 4487 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4488 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4489 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4490 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4491 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4492 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4493 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4494 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4495 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4496 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4497 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4498 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4499 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4500 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
0375b229 4501 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
65441f6f 4502 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
0375b229 4503 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
32374e3c 4504 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
65441f6f 4505
4506
4507 /* cmpge is the same as cmpgt for all cases except floating point.
4508 There is further code to deal with this special case in
4509 altivec_build_resolved_builtin. */
0375b229 4510 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
65441f6f 4511 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
0375b229 4512 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
65441f6f 4513 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
0375b229 4514 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
65441f6f 4515 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
0375b229 4516 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
65441f6f 4517 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
0375b229 4518 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
65441f6f 4519 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
0375b229 4520 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
65441f6f 4521 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
0375b229 4522 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
65441f6f 4523 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
0375b229 4524 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
65441f6f 4525 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
0375b229 4526 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
65441f6f 4527 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
0375b229 4528 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
65441f6f 4529 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
0375b229 4530 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
65441f6f 4531 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
0375b229 4532 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
65441f6f 4533 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
0375b229 4534 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
65441f6f 4535 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
0375b229 4536 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
65441f6f 4537 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
0375b229 4538 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
65441f6f 4539 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
0375b229 4540 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
65441f6f 4541 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
0375b229 4542 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
65441f6f 4543 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
0375b229 4544 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
65441f6f 4545 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
ae52d0de 4546 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4547 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4548 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4549 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4550 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4551 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4552 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4553 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4554 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4555 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4556 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4557 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
0375b229 4558 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
65441f6f 4559 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
0375b229 4560 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
32374e3c 4561 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
65441f6f 4562
7028141d 4563 /* Power8 vector overloaded functions. */
4564 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4565 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4566 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4567 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4568 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4569 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
a9c17725 4570 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4571 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
7028141d 4572 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4573 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4574 RS6000_BTI_unsigned_V16QI, 0 },
4575 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4576 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4577 RS6000_BTI_bool_V16QI, 0 },
4578 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4579 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4580 RS6000_BTI_unsigned_V16QI, 0 },
4581 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4582 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4583 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4584 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4585 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4586 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
a9c17725 4587 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4588 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
7028141d 4589 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4590 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4591 RS6000_BTI_unsigned_V8HI, 0 },
4592 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4593 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4594 RS6000_BTI_bool_V8HI, 0 },
4595 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4596 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4597 RS6000_BTI_unsigned_V8HI, 0 },
4598 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4599 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4600 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4601 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4602 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4603 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
a9c17725 4604 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4605 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
7028141d 4606 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4607 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4608 RS6000_BTI_unsigned_V4SI, 0 },
4609 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4610 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4611 RS6000_BTI_bool_V4SI, 0 },
4612 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4613 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4614 RS6000_BTI_unsigned_V4SI, 0 },
4615 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4616 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4617 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4618 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4619 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4620 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
a9c17725 4621 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4622 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
7028141d 4623 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4624 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4625 RS6000_BTI_unsigned_V2DI, 0 },
4626 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4627 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4628 RS6000_BTI_bool_V2DI, 0 },
4629 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4630 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4631 RS6000_BTI_unsigned_V2DI, 0 },
4632 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4633 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4634 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4635 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4636
4637 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4638 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4639 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4640 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4641 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4642 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4643 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4644 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4645 RS6000_BTI_unsigned_V16QI, 0 },
4646 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4647 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4648 RS6000_BTI_bool_V16QI, 0 },
4649 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4650 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4651 RS6000_BTI_unsigned_V16QI, 0 },
a9c17725 4652 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4653 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
7028141d 4654 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4655 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4656 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4657 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4658 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4659 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4660 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4661 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4662 RS6000_BTI_unsigned_V8HI, 0 },
4663 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4664 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4665 RS6000_BTI_bool_V8HI, 0 },
4666 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4667 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4668 RS6000_BTI_unsigned_V8HI, 0 },
a9c17725 4669 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4670 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
7028141d 4671 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4672 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4673 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4674 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4675 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4676 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4677 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4678 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4679 RS6000_BTI_unsigned_V4SI, 0 },
4680 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4681 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4682 RS6000_BTI_bool_V4SI, 0 },
4683 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4684 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4685 RS6000_BTI_unsigned_V4SI, 0 },
a9c17725 4686 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4687 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
7028141d 4688 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4689 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4690 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4691 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4692 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4693 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4694 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4695 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4696 RS6000_BTI_unsigned_V2DI, 0 },
4697 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4698 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4699 RS6000_BTI_bool_V2DI, 0 },
4700 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4701 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4702 RS6000_BTI_unsigned_V2DI, 0 },
a9c17725 4703 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4704 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
7028141d 4705 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4706 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4707 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4708 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4709
4710 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4711 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4712 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4713 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4714 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4715 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4716 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4717 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4718 RS6000_BTI_unsigned_V16QI, 0 },
4719 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4720 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4721 RS6000_BTI_bool_V16QI, 0 },
4722 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4723 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4724 RS6000_BTI_unsigned_V16QI, 0 },
a9c17725 4725 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4726 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
7028141d 4727 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4728 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4729 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4730 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4731 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4732 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4733 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4734 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4735 RS6000_BTI_unsigned_V8HI, 0 },
4736 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4737 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4738 RS6000_BTI_bool_V8HI, 0 },
4739 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4740 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4741 RS6000_BTI_unsigned_V8HI, 0 },
a9c17725 4742 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4743 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
7028141d 4744 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4745 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4746 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4747 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4748 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4749 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4750 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4751 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4752 RS6000_BTI_unsigned_V4SI, 0 },
4753 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4754 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4755 RS6000_BTI_bool_V4SI, 0 },
4756 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4757 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4758 RS6000_BTI_unsigned_V4SI, 0 },
a9c17725 4759 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4760 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
7028141d 4761 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4762 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4763 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4764 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4765 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4766 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4767 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4768 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4769 RS6000_BTI_unsigned_V2DI, 0 },
4770 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4771 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4772 RS6000_BTI_bool_V2DI, 0 },
4773 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4774 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4775 RS6000_BTI_unsigned_V2DI, 0 },
a9c17725 4776 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4777 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
7028141d 4778 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4779 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4780 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4781 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4782
ae61c502 4783 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4784 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4785 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4786 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4787 RS6000_BTI_unsigned_V1TI, 0 },
4788
7028141d 4789 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4790 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4791 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4792 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4793 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4794 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4795 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4796 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4797 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4798 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4799 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4800 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4801
ae61c502 4802 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4803 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4804 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4805 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4806 RS6000_BTI_unsigned_V1TI, 0 },
4807
24cb4506 4808 { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4809 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4810 RS6000_BTI_unsigned_V16QI, 0 },
4811 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4812 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4813 RS6000_BTI_unsigned_V16QI, 0 },
4814 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4815 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4816 RS6000_BTI_unsigned_V16QI, 0 },
4817
33d39774 4818 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4819 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4820 RS6000_BTI_unsigned_V16QI, 0 },
a1546352 4821 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4822 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4823 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4824 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4825 RS6000_BTI_unsigned_V16QI, 0 },
a9c17725 4826 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4827 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4828 RS6000_BTI_unsigned_V16QI, 0 },
a1546352 4829
7028141d 4830 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4831 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4832 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4833 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4834 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4835 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4836 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4837 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4838 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4839 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4840 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4841 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4842 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4843 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4844 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4845 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4846
4847 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4848 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4849 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4850 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4851
4852 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4853 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4854 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4855 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4856
4857 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4858 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4859 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4860 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4861
4862 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4863 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4864 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4865 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4866
17c32c4a 4867 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4868 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4869 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4870 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4871
4872 { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4873 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4874 { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4875 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4876
4877 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4878 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4879 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4880 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4881
4882 { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4883 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4884 { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4885 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4886
4887 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4888 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4889 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4890 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4891
4892 { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4893 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4894 { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4895 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4896
4897 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4898 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4899 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4900 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4901
4902 { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4903 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4904 { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4905 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4906
af648be2 4907 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4908 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4909 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4910 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4911 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4912 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4913 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4914 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4915 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4916 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4917 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4918 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4919 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4920 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4921 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4922 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4923
4924 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4925 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4926 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4927 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4928
4929 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4930 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4931 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4932 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4933
4934 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4935 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4936 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4937 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4938
4939 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4940 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4941 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4942 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4943
412f195f 4944 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4945 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4946 RS6000_BTI_unsigned_V16QI, 0 },
4947 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4948 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4949 RS6000_BTI_unsigned_V8HI, 0 },
4950 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4951 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4952 RS6000_BTI_unsigned_V4SI, 0 },
4953
4954 { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4955 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4956 RS6000_BTI_unsigned_V16QI, 0 },
4957
4958 { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4959 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4960 RS6000_BTI_unsigned_V8HI, 0 },
4961
4962 { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
4963 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4964 RS6000_BTI_unsigned_V4SI, 0 },
4965
97468983 4966 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
b8588f71 4967 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
97468983 4968 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
b8588f71 4969 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
97468983 4970
4971 { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
b8588f71 4972 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
97468983 4973 { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
b8588f71 4974 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
97468983 4975
4976 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
b8588f71 4977 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
97468983 4978 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
b8588f71 4979 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
97468983 4980
4981 { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
b8588f71 4982 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
97468983 4983 { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
b8588f71 4984 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
97468983 4985
4986 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
b8588f71 4987 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
97468983 4988 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
b8588f71 4989 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
97468983 4990
4991 { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
b8588f71 4992 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
97468983 4993 { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
b8588f71 4994 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
97468983 4995
4996 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4997 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
b8588f71 4998 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4999 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
5000
97468983 5001 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
5002 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
b8588f71 5003 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
5004 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
97468983 5005
5006 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
5007 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
b8588f71 5008 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
5009 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
5010
97468983 5011 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
5012 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
b8588f71 5013 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
5014 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
97468983 5015
5016 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
b8588f71 5017 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
97468983 5018 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
b8588f71 5019 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4a71f283 5020 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP,
5021 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
97468983 5022
5023 { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
b8588f71 5024 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
97468983 5025 { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
b8588f71 5026 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4a71f283 5027 { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP,
5028 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
97468983 5029
5030 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
b8588f71 5031 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
97468983 5032 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
b8588f71 5033 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4a71f283 5034 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP,
5035 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
97468983 5036
5037 { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
b8588f71 5038 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
97468983 5039 { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
b8588f71 5040 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4a71f283 5041 { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP,
5042 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
97468983 5043
5044 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
5045 RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
4a71f283 5046 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP,
5047 RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 },
97468983 5048
5049 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
5050 RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
4a71f283 5051 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP,
5052 RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 },
97468983 5053
5054 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
5055 RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
b8588f71 5056 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
5057 RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
97468983 5058
4a71f283 5059 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP,
5060 RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 },
5061 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
5062 RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
5063
35f422fa 5064 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT,
97468983 5065 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
35f422fa 5066 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT,
5067 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
5068 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT,
97468983 5069 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
35f422fa 5070 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT,
5071 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
5072 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ,
97468983 5073 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
35f422fa 5074 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ,
5075 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
5076 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO,
97468983 5077 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
35f422fa 5078 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO,
5079 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
97468983 5080
5433fcc8 5081 { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
5082 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
5083 RS6000_BTI_unsigned_long_long, 0 },
5084
f9debd38 5085 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5086 RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
5087 RS6000_BTI_unsigned_long_long, 0 },
5088 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5089 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
5090 RS6000_BTI_unsigned_long_long, 0 },
5091
5092 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5093 RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
5094 RS6000_BTI_unsigned_long_long, 0 },
5095 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5096 RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
5097 RS6000_BTI_unsigned_long_long, 0 },
5098
5099 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5100 RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
5101 RS6000_BTI_unsigned_long_long, 0 },
5102 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5103 RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
5104 RS6000_BTI_unsigned_long_long, 0 },
5105
5106 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5107 RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
5108 RS6000_BTI_unsigned_long_long, 0 },
5109 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5110 RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
5111 RS6000_BTI_unsigned_long_long, 0 },
5112
5113 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5114 RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
5115 RS6000_BTI_unsigned_long_long, 0 },
5116 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5117 RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
5118 RS6000_BTI_unsigned_long_long, 0 },
5119
5120 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5121 RS6000_BTI_V2DF, ~RS6000_BTI_double,
5122 RS6000_BTI_unsigned_long_long, 0 },
5123 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5124 RS6000_BTI_V4SF, ~RS6000_BTI_float,
5125 RS6000_BTI_unsigned_long_long, 0 },
5126 /* At an appropriate future time, add support for the
5127 RS6000_BTI_Float16 (exact name to be determined) type here. */
5128
5433fcc8 5129 { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,
5130 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,
5131 ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},
5132
f9debd38 5133 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5134 RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
5135 RS6000_BTI_unsigned_long_long },
5136 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5137 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
5138 RS6000_BTI_unsigned_long_long },
5139
5140 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5141 RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
5142 RS6000_BTI_unsigned_long_long },
5143 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5144 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
5145 RS6000_BTI_unsigned_long_long },
5146
5147 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5148 RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
5149 RS6000_BTI_unsigned_long_long },
5150 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5151 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
5152 RS6000_BTI_unsigned_long_long },
5153
5154 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5155 RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
5156 RS6000_BTI_unsigned_long_long },
5157 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5158 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
5159 RS6000_BTI_unsigned_long_long },
5160
5161 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5162 RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
5163 RS6000_BTI_unsigned_long_long },
5164 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5165 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
5166 RS6000_BTI_unsigned_long_long },
5167
5168 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5169 RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
5170 RS6000_BTI_unsigned_long_long },
5171 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5172 RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
5173 RS6000_BTI_unsigned_long_long },
5174 /* At an appropriate future time, add support for the
5175 RS6000_BTI_Float16 (exact name to be determined) type here. */
5176
5177 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5178 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
5179 RS6000_BTI_bool_V16QI, 0 },
5180 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5181 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5182 RS6000_BTI_V16QI, 0 },
5183 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5184 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5185 RS6000_BTI_unsigned_V16QI, 0 },
5186
5187 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5188 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
5189 RS6000_BTI_bool_V8HI, 0 },
5190 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5191 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5192 RS6000_BTI_V8HI, 0 },
5193 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5194 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5195 RS6000_BTI_unsigned_V8HI, 0 },
5196
5197 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5198 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
5199 RS6000_BTI_bool_V4SI, 0 },
5200 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5201 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5202 RS6000_BTI_V4SI, 0 },
5203 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5204 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5205 RS6000_BTI_unsigned_V4SI, 0 },
f9debd38 5206
5207 /* The following 2 entries have been deprecated. */
5208 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
7f6b8cff 5209 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5210 RS6000_BTI_unsigned_V16QI, 0 },
f9debd38 5211 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
7f6b8cff 5212 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5213 RS6000_BTI_bool_V16QI, 0 },
f9debd38 5214 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
7f6b8cff 5215 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5216 RS6000_BTI_unsigned_V16QI, 0 },
f9debd38 5217
5218 /* The following 2 entries have been deprecated. */
5219 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
7f6b8cff 5220 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5221 RS6000_BTI_V16QI, 0 },
f9debd38 5222 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
7f6b8cff 5223 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5224 RS6000_BTI_bool_V16QI, 0 },
f9debd38 5225 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
7f6b8cff 5226 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
f9debd38 5227 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
7f6b8cff 5228 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5229 RS6000_BTI_bool_V16QI, 0 },
f9debd38 5230
5231 /* The following 2 entries have been deprecated. */
5232 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
7f6b8cff 5233 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5234 RS6000_BTI_unsigned_V8HI, 0 },
f9debd38 5235 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
7f6b8cff 5236 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5237 RS6000_BTI_bool_V8HI, 0 },
f9debd38 5238 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
7f6b8cff 5239 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5240 RS6000_BTI_unsigned_V8HI, 0 },
f9debd38 5241 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
7f6b8cff 5242 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
f9debd38 5243
5244 /* The following 2 entries have been deprecated. */
5245 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
7f6b8cff 5246 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5247 RS6000_BTI_V8HI, 0 },
f9debd38 5248 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
7f6b8cff 5249 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5250 RS6000_BTI_bool_V8HI, 0 },
f9debd38 5251 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
7f6b8cff 5252 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5253 RS6000_BTI_bool_V8HI, 0 },
f9debd38 5254 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
7f6b8cff 5255 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5256 RS6000_BTI_pixel_V8HI, 0 },
f9debd38 5257
5258 /* The following 2 entries have been deprecated. */
5259 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
7f6b8cff 5260 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5261 RS6000_BTI_unsigned_V4SI, 0 },
f9debd38 5262 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
7f6b8cff 5263 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5264 RS6000_BTI_bool_V4SI, 0 },
f9debd38 5265 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
7f6b8cff 5266 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5267 RS6000_BTI_unsigned_V4SI, 0 },
f9debd38 5268
5269 /* The following 2 entries have been deprecated. */
5270 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
7f6b8cff 5271 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5272 RS6000_BTI_V4SI, 0 },
f9debd38 5273 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
7f6b8cff 5274 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5275 RS6000_BTI_bool_V4SI, 0 },
f9debd38 5276 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
7f6b8cff 5277 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
f9debd38 5278 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
7f6b8cff 5279 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5280 RS6000_BTI_bool_V4SI, 0 },
f9debd38 5281
5282 /* The following 2 entries have been deprecated. */
5283 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
7f6b8cff 5284 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5285 RS6000_BTI_unsigned_V2DI, 0 },
f9debd38 5286 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
7f6b8cff 5287 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5288 RS6000_BTI_bool_V2DI, 0 },
f9debd38 5289 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
7f6b8cff 5290 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5291 RS6000_BTI_unsigned_V2DI, 0
5292 },
f9debd38 5293
5294 /* The following 2 entries have been deprecated. */
5295 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
7f6b8cff 5296 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5297 RS6000_BTI_V2DI, 0 },
f9debd38 5298 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
7f6b8cff 5299 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5300 RS6000_BTI_bool_V2DI, 0 },
f9debd38 5301 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
7f6b8cff 5302 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
f9debd38 5303 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
7f6b8cff 5304 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5305 RS6000_BTI_bool_V2DI, 0 },
f9debd38 5306
5307 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
7f6b8cff 5308 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
f9debd38 5309 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
7f6b8cff 5310 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5311
5312 /* The following 2 entries have been deprecated. */
5313 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5314 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5315 RS6000_BTI_unsigned_V16QI, 0 },
5316 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5317 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5318 RS6000_BTI_bool_V16QI, 0 },
5319 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5320 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5321 RS6000_BTI_unsigned_V16QI, 0 },
5322
5323 /* The following 2 entries have been deprecated. */
5324 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5325 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5326 RS6000_BTI_V16QI, 0 },
5327 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5328 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5329 RS6000_BTI_bool_V16QI, 0 },
5330 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5331 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5332 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5333 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5334 RS6000_BTI_bool_V16QI, 0 },
5335
5336 /* The following 2 entries have been deprecated. */
5337 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5338 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5339 RS6000_BTI_unsigned_V8HI, 0 },
5340 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5341 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5342 RS6000_BTI_bool_V8HI, 0 },
5343 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5344 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5345 RS6000_BTI_unsigned_V8HI, 0 },
5346 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5347 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5348
5349 /* The following 2 entries have been deprecated. */
5350 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5351 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5352 RS6000_BTI_V8HI, 0 },
5353 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5354 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5355 RS6000_BTI_bool_V8HI, 0 },
5356 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5357 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5358 RS6000_BTI_bool_V8HI, 0 },
5359 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5360 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5361 RS6000_BTI_pixel_V8HI, 0 },
5362
5363 /* The following 2 entries have been deprecated. */
5364 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5365 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5366 RS6000_BTI_unsigned_V4SI, 0 },
5367 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5368 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5369 RS6000_BTI_bool_V4SI, 0 },
5370 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5371 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5372 RS6000_BTI_unsigned_V4SI, 0 },
5373
5374 /* The following 2 entries have been deprecated. */
5375 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5376 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5377 RS6000_BTI_V4SI, 0 },
5378 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5379 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5380 RS6000_BTI_bool_V4SI, 0 },
5381 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5382 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5383 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5384 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5385 RS6000_BTI_bool_V4SI, 0 },
5386
5387 /* The following 2 entries have been deprecated. */
5388 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5389 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5390 RS6000_BTI_unsigned_V2DI, 0 },
5391 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5392 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5393 RS6000_BTI_bool_V2DI, 0 },
5394 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5395 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5396 RS6000_BTI_unsigned_V2DI, 0
5397 },
5398
5399 /* The following 2 entries have been deprecated. */
5400 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5401 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5402 RS6000_BTI_V2DI, 0 },
5403 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5404 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5405 RS6000_BTI_bool_V2DI, 0 },
5406 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5407 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5408 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5409 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5410 RS6000_BTI_bool_V2DI, 0 },
5411
5412 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
5413 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5414 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
5415 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
f9debd38 5416
5417 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5418 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5419 RS6000_BTI_unsigned_V16QI },
5420 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5421 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
5422
5423 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5424 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5425 RS6000_BTI_unsigned_V8HI },
5426 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5427 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
5428
5429 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5430 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5431 RS6000_BTI_unsigned_V4SI },
5432 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5433 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
5434
5435 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5436 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5437 RS6000_BTI_V16QI, 0 },
5438 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5439 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5440 RS6000_BTI_unsigned_V16QI, 0 },
5441
5442 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5443 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5444 RS6000_BTI_V8HI, 0 },
5445 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5446 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5447 RS6000_BTI_unsigned_V8HI, 0 },
5448
5449 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5450 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5451 RS6000_BTI_V4SI, 0 },
5452 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5453 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5454 RS6000_BTI_unsigned_V4SI, 0 },
5455
b6b5f0f8 5456 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
f9debd38 5457 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
b6b5f0f8 5458 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
f9debd38 5459 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5460
f9afdf24 5461 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
f9debd38 5462 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
f9afdf24 5463 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
f9debd38 5464 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
f9afdf24 5465 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI,
5466 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5467 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI,
5468 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 },
f9debd38 5469
8c76a28e 5470 { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
5471 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
ee33c236 5472
d782c3b8 5473 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5474 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5475 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5476 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5477
f9debd38 5478 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5479 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5480 RS6000_BTI_V16QI, 0 },
5481 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5482 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5483 RS6000_BTI_unsigned_V16QI, 0 },
5484
5485 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5486 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5487 RS6000_BTI_V8HI, 0 },
5488 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5489 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5490 RS6000_BTI_unsigned_V8HI, 0 },
5491
5492 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5493 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5494 RS6000_BTI_V4SI, 0 },
5495 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5496 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5497 RS6000_BTI_unsigned_V4SI, 0 },
5498 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5499 RS6000_BTI_float, RS6000_BTI_UINTSI,
5500 RS6000_BTI_V4SF, 0 },
5501
5502 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5503 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5504 RS6000_BTI_V16QI, 0 },
5505 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5506 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5507 RS6000_BTI_unsigned_V16QI, 0 },
5508
5509 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5510 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5511 RS6000_BTI_V8HI, 0 },
5512 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5513 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5514 RS6000_BTI_unsigned_V8HI, 0 },
5515
5516 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5517 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5518 RS6000_BTI_V4SI, 0 },
5519 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5520 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5521 RS6000_BTI_unsigned_V4SI, 0 },
5522 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5523 RS6000_BTI_float, RS6000_BTI_UINTSI,
5524 RS6000_BTI_V4SF, 0 },
5525
7028141d 5526 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5527 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5528 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5529 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5530
8c76a28e 5531 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5532 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI,
5533 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5534 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5535 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5536 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
ee33c236 5537
ae61c502 5538 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5539 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5540 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5541 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5542 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5543
5544 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5545 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5546 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5547 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5548 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5549
5550 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5551 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5552 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5553 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5554 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5555
5556 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5557 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5558 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5559 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5560 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5561
7028141d 5562 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5563 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5564 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5565 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5566 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5567 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5568
5569 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5570 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5571 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5572 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5573 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5574 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5575
5576 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5577 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5578 RS6000_BTI_unsigned_V2DI, 0 },
5579 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5580 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5581 RS6000_BTI_bool_V2DI, 0 },
5582 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5583 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5584 RS6000_BTI_unsigned_V2DI, 0 },
5585
5586 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5587 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5588 RS6000_BTI_unsigned_V2DI, 0 },
5589 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5590 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5591 RS6000_BTI_bool_V2DI, 0 },
5592 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5593 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5594 RS6000_BTI_unsigned_V2DI, 0 },
5595
5cc94c58 5596 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5597 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5598 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5599 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5600 RS6000_BTI_unsigned_V2DI, 0 },
5601 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5602 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5603 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF,
5604 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5605 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF,
5606 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
67d38f28 5607 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
7028141d 5608 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
67d38f28 5609 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
7028141d 5610 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5611 RS6000_BTI_unsigned_V4SI, 0 },
67d38f28 5612 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
271b79e4 5613 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
7028141d 5614
5cc94c58 5615 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
7028141d 5616 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5cc94c58 5617 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
7028141d 5618 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5619 RS6000_BTI_unsigned_V4SI, 0 },
5cc94c58 5620 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
271b79e4 5621 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5cc94c58 5622 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5623 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5624 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5cc94c58 5625 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5626 RS6000_BTI_unsigned_V2DI, 0 },
5627 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5628 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5629 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF,
5630 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5631 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF,
5632 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
7028141d 5633
f2e7ec4a 5634 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5635 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5636 RS6000_BTI_unsigned_V16QI, 0 },
5637 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5638 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5639 RS6000_BTI_unsigned_V8HI, 0 },
5640 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5641 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5642 RS6000_BTI_unsigned_V4SI, 0 },
5643 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5644 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5645 RS6000_BTI_unsigned_V2DI, 0 },
5646
7028141d 5647 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5648 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5649 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5650 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5651 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5652 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5653 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5654 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5655 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5656 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5657 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5658 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5659 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5660 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5661 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5662 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5663
5664 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5665 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5666 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5667 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5668
c6bd4248 5669 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5670 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5671 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5672 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5673
5674 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5675 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5676 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5677 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5678
5679 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5680 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5681 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5682 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5683
5684 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5685 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5686 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5687 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5688
7028141d 5689 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5690 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5691 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5692 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5693
5694 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5695 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5696 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5697 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5698
5699 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5700 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5701 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5702 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5703
af648be2 5704 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5705 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5706 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5707 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5708 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5709 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5710 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5711 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5712 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5713 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5714 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5715 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5716 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5717 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5718 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5719 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5720
5721 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5722 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5723 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5724 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5725
5726 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5727 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5728 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5729 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5730
5731 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5732 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5733 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5734 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5735 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5736 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5737 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5738 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5739
05a7d070 5740 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5741 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5742 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5743 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5744 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5745 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5746 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5747 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5748 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5749 RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
5750 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5751 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5752
9cd62877 5753 { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5754 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5755 { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5756 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5757 { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5758 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5759
7028141d 5760 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5761 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5762 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5763 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5764 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5765 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5766
5767 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5768 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5769
5770 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5771 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5772
5773 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5774 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5775
5776 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5777 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5778 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5779 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5780
5781 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5782 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5783 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5784 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5785
5786 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5787 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5788 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5789 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5790
5791 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5792 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
954344f9 5793 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
7028141d 5794 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5795
ae61c502 5796 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5797 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5798 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5799 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5800 RS6000_BTI_unsigned_V1TI, 0 },
5801
7028141d 5802 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5803 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5804 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5805 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5806 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5807 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5808 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5809 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5810 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5811 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5812 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5813 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5814
ae61c502 5815 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5816 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5817 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5818 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5819 RS6000_BTI_unsigned_V1TI, 0 },
5820
9534dff5 5821 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5822 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5823 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5824 RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5825
7028141d 5826 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5827 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5828 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5829 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5830
5831 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5832 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5833 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5834 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5835
5a5b02e1 5836 { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5837 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5838 RS6000_BTI_unsigned_V16QI, 0 },
5839 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5840 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5841 RS6000_BTI_unsigned_V16QI, 0 },
5842
14aaf770 5843 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
288e4639 5844 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
14aaf770 5845 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5846 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5847 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5848 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5849 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
288e4639 5850 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
14aaf770 5851 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
288e4639 5852 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
14aaf770 5853 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
f879a116 5854 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
14aaf770 5855 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
288e4639 5856 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
14aaf770 5857 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
288e4639 5858 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
14aaf770 5859 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
f879a116 5860 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
14aaf770 5861 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
288e4639 5862 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
14aaf770 5863 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
288e4639 5864 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
14aaf770 5865 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5866 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5867 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5868 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5869 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5870 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5871 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF,
5872 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5873 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF,
5874 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
288e4639 5875
a990b86c 5876 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5877 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5878 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5879 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5880 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5881 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5882 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5883 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5884 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5885 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5886 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5887 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5888 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5889 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5890 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5891 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5892 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
5893 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5894 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
5895 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5896 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5897 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5898 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5899 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5900 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5901 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5902 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5903 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5904
ee9f1372 5905 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF,
5906 RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 },
5907 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF,
5908 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5909 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5910 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5911 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5912 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
6de50102 5913 { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF,
ee9f1372 5914 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5915
5916 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5917 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5918 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5919 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5920 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5921 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5922 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5923 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
6de50102 5924 { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF,
ee9f1372 5925 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5926 RS6000_BTI_V2DF, 0 },
5927
81f0e7d0 5928 /* Crypto builtins. */
5929 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5930 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5931 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5932 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5933 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5934 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5935 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5936 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5937 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5938 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5939 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5940 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5941
5942 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5943 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5944 RS6000_BTI_unsigned_V16QI, 0 },
5945 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5946 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5947 RS6000_BTI_unsigned_V8HI, 0 },
5948 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5949 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5950 RS6000_BTI_unsigned_V4SI, 0 },
5951 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5952 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5953 RS6000_BTI_unsigned_V2DI, 0 },
5954
5955 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5956 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5957 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5958 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5959 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5960 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5961
bc620c5c 5962 { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
65441f6f 5963};
5964\f
5965
5966/* Convert a type stored into a struct altivec_builtin_types as ID,
5967 into a tree. The types are in rs6000_builtin_types: negative values
5968 create a pointer type for the type associated to ~ID. Note it is
5969 a logical NOT, rather than a negation, otherwise you cannot represent
5970 a pointer type for ID 0. */
5971
5972static inline tree
5973rs6000_builtin_type (int id)
5974{
5975 tree t;
5976 t = rs6000_builtin_types[id < 0 ? ~id : id];
5977 return id < 0 ? build_pointer_type (t) : t;
5978}
5979
a192d26f 5980/* Check whether the type of an argument, T, is compatible with a type ID
5981 stored into a struct altivec_builtin_types. Integer types are considered
5982 compatible; otherwise, the language hook lang_hooks.types_compatible_p makes
5983 the decision. Also allow long double and _Float128 to be compatible if
5984 -mabi=ieeelongdouble. */
65441f6f 5985
a192d26f 5986static inline bool
5987is_float128_p (tree t)
5988{
5989 return (t == float128_type_node
5990 || (TARGET_IEEEQUAD
5991 && TARGET_LONG_DOUBLE_128
5992 && t == long_double_type_node));
5993}
5994
65441f6f 5995static inline bool
5996rs6000_builtin_type_compatible (tree t, int id)
5997{
5998 tree builtin_type;
5999 builtin_type = rs6000_builtin_type (id);
f082efb4 6000 if (t == error_mark_node)
6001 return false;
65441f6f 6002 if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type))
6003 return true;
a192d26f 6004 else if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
6005 && is_float128_p (t) && is_float128_p (builtin_type))
6006 return true;
65441f6f 6007 else
6008 return lang_hooks.types_compatible_p (t, builtin_type);
6009}
6010
6011
745d490f 6012/* In addition to calling fold_convert for EXPR of type TYPE, also
6013 call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be
6014 hiding there (PR47197). */
6015
6016static tree
6017fully_fold_convert (tree type, tree expr)
6018{
6019 tree result = fold_convert (type, expr);
6020 bool maybe_const = true;
6021
6022 if (!c_dialect_cxx ())
6023 result = c_fully_fold (result, false, &maybe_const);
6024
6025 return result;
6026}
6027
65441f6f 6028/* Build a tree for a function call to an Altivec non-overloaded builtin.
6029 The overloaded builtin that matched the types and args is described
6030 by DESC. The N arguments are given in ARGS, respectively.
6031
6032 Actually the only thing it does is calling fold_convert on ARGS, with
6033 a small exception for vec_{all,any}_{ge,le} predicates. */
6034
6035static tree
6036altivec_build_resolved_builtin (tree *args, int n,
6037 const struct altivec_builtin_types *desc)
6038{
6039 tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code];
6040 tree ret_type = rs6000_builtin_type (desc->ret_type);
6041 tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl));
c2f47e15 6042 tree arg_type[3];
6043 tree call;
65441f6f 6044
6045 int i;
6046 for (i = 0; i < n; i++)
6047 arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes);
6048
6049 /* The AltiVec overloading implementation is overall gross, but this
6050 is particularly disgusting. The vec_{all,any}_{ge,le} builtins
6051 are completely different for floating-point vs. integer vector
6052 types, because the former has vcmpgefp, but the latter should use
6053 vcmpgtXX.
6054
6055 In practice, the second and third arguments are swapped, and the
6056 condition (LT vs. EQ, which is recognizable by bit 1 of the first
6057 argument) is reversed. Patch the arguments here before building
6058 the resolved CALL_EXPR. */
0375b229 6059 if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P
a89df520 6060 && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P
6061 && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P)
65441f6f 6062 {
6063 tree t;
6064 t = args[2], args[2] = args[1], args[1] = t;
6065 t = arg_type[2], arg_type[2] = arg_type[1], arg_type[1] = t;
6066
6067 args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0],
6068 build_int_cst (NULL_TREE, 2));
6069 }
6070
c2f47e15 6071 switch (n)
6072 {
6073 case 0:
6074 call = build_call_expr (impl_fndecl, 0);
6075 break;
6076 case 1:
6077 call = build_call_expr (impl_fndecl, 1,
745d490f 6078 fully_fold_convert (arg_type[0], args[0]));
c2f47e15 6079 break;
6080 case 2:
6081 call = build_call_expr (impl_fndecl, 2,
745d490f 6082 fully_fold_convert (arg_type[0], args[0]),
6083 fully_fold_convert (arg_type[1], args[1]));
c2f47e15 6084 break;
6085 case 3:
6086 call = build_call_expr (impl_fndecl, 3,
745d490f 6087 fully_fold_convert (arg_type[0], args[0]),
6088 fully_fold_convert (arg_type[1], args[1]),
6089 fully_fold_convert (arg_type[2], args[2]));
c2f47e15 6090 break;
6091 default:
6092 gcc_unreachable ();
6093 }
6094 return fold_convert (ret_type, call);
65441f6f 6095}
6096
6097/* Implementation of the resolve_overloaded_builtin target hook, to
6098 support Altivec's overloaded builtins. */
6099
02e6a8e1 6100tree
65edca84 6101altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
052a8489 6102 void *passed_arglist)
65441f6f 6103{
f1f41a6c 6104 vec<tree, va_gc> *arglist = static_cast<vec<tree, va_gc> *> (passed_arglist);
6105 unsigned int nargs = vec_safe_length (arglist);
0375b229 6106 enum rs6000_builtins fcode
6107 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
65441f6f 6108 tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl));
6109 tree types[3], args[3];
6110 const struct altivec_builtin_types *desc;
b9c74b4d 6111 unsigned int n;
65441f6f 6112
0375b229 6113 if (!rs6000_overloaded_builtin_p (fcode))
65441f6f 6114 return NULL_TREE;
6115
0375b229 6116 if (TARGET_DEBUG_BUILTIN)
6117 fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n",
6118 (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)));
6b529612 6119
6120 /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */
fc3703b8 6121 if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !BYTES_BIG_ENDIAN)
e2319838 6122 warning (OPT_Wdeprecated,
6123 "vec_lvsl is deprecated for little endian; use "
6124 "assignment for unaligned loads and stores");
fc3703b8 6125 else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !BYTES_BIG_ENDIAN)
e2319838 6126 warning (OPT_Wdeprecated,
6127 "vec_lvsr is deprecated for little endian; use "
6128 "assignment for unaligned loads and stores");
0375b229 6129
2d76c36a 6130 if (fcode == ALTIVEC_BUILTIN_VEC_MUL)
6131 {
6132 /* vec_mul needs to be special cased because there are no instructions
6133 for it for the {un}signed char, {un}signed short, and {un}signed int
6134 types. */
6135 if (nargs != 2)
6136 {
2d67bb48 6137 error ("builtin %qs only accepts 2 arguments", "vec_mul");
2d76c36a 6138 return error_mark_node;
6139 }
6140
6141 tree arg0 = (*arglist)[0];
6142 tree arg0_type = TREE_TYPE (arg0);
6143 tree arg1 = (*arglist)[1];
6144 tree arg1_type = TREE_TYPE (arg1);
6145
c51713e6 6146 /* Both arguments must be vectors and the types must be compatible. */
2d76c36a 6147 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6148 goto bad;
c51713e6 6149 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
6150 goto bad;
2d76c36a 6151
6152 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6153 {
916ace94 6154 case E_QImode:
6155 case E_HImode:
6156 case E_SImode:
6157 case E_DImode:
6158 case E_TImode:
2d76c36a 6159 {
6160 /* For scalar types just use a multiply expression. */
c51713e6 6161 return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0,
6162 fold_convert (TREE_TYPE (arg0), arg1));
2d76c36a 6163 }
916ace94 6164 case E_SFmode:
2d76c36a 6165 {
6166 /* For floats use the xvmulsp instruction directly. */
6167 tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP];
6168 return build_call_expr (call, 2, arg0, arg1);
6169 }
916ace94 6170 case E_DFmode:
2d76c36a 6171 {
6172 /* For doubles use the xvmuldp instruction directly. */
6173 tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP];
6174 return build_call_expr (call, 2, arg0, arg1);
6175 }
6176 /* Other types are errors. */
6177 default:
6178 goto bad;
6179 }
6180 }
77102dbe 6181
6182 if (fcode == ALTIVEC_BUILTIN_VEC_CMPNE)
6183 {
6184 /* vec_cmpne needs to be special cased because there are no instructions
6185 for it (prior to power 9). */
6186 if (nargs != 2)
6187 {
2d67bb48 6188 error ("builtin %qs only accepts 2 arguments", "vec_cmpne");
77102dbe 6189 return error_mark_node;
6190 }
6191
6192 tree arg0 = (*arglist)[0];
6193 tree arg0_type = TREE_TYPE (arg0);
6194 tree arg1 = (*arglist)[1];
6195 tree arg1_type = TREE_TYPE (arg1);
6196
55022684 6197 /* Both arguments must be vectors and the types must be compatible. */
6198 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6199 goto bad;
6200 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
6201 goto bad;
6202
f9debd38 6203 /* Power9 instructions provide the most efficient implementation of
7f6b8cff 6204 ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode
6205 or SFmode or DFmode. */
f9debd38 6206 if (!TARGET_P9_VECTOR
6207 || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
7f6b8cff 6208 || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode)
6209 || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode)
6210 || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode))
77102dbe 6211 {
f9debd38 6212 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6213 {
6214 /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
6215 vec_cmpeq (va, vb)). */
6216 /* Note: vec_nand also works but opt changes vec_nand's
6217 to vec_nor's anyway. */
916ace94 6218 case E_QImode:
6219 case E_HImode:
6220 case E_SImode:
6221 case E_DImode:
6222 case E_TImode:
6223 case E_SFmode:
6224 case E_DFmode:
f9debd38 6225 {
6226 /* call = vec_cmpeq (va, vb)
6227 result = vec_nor (call, call). */
6228 vec<tree, va_gc> *params = make_tree_vector ();
6229 vec_safe_push (params, arg0);
6230 vec_safe_push (params, arg1);
6231 tree call = altivec_resolve_overloaded_builtin
6232 (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ],
6233 params);
6234 /* Use save_expr to ensure that operands used more than once
6235 that may have side effects (like calls) are only evaluated
6236 once. */
6237 call = save_expr (call);
6238 params = make_tree_vector ();
6239 vec_safe_push (params, call);
6240 vec_safe_push (params, call);
6241 return altivec_resolve_overloaded_builtin
6242 (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params);
6243 }
6244 /* Other types are errors. */
6245 default:
6246 goto bad;
6247 }
77102dbe 6248 }
f9debd38 6249 /* else, fall through and process the Power9 alternative below */
77102dbe 6250 }
6251
4a777525 6252 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE
6253 || fcode == ALTIVEC_BUILTIN_VEC_SUBE)
e40e5340 6254 {
6255 /* vec_adde needs to be special cased because there is no instruction
6256 for the {un}signed int version. */
6257 if (nargs != 3)
6258 {
4a777525 6259 const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDE ?
6260 "vec_adde": "vec_sube";
2d67bb48 6261 error ("builtin %qs only accepts 3 arguments", name);
e40e5340 6262 return error_mark_node;
6263 }
6264
6265 tree arg0 = (*arglist)[0];
6266 tree arg0_type = TREE_TYPE (arg0);
6267 tree arg1 = (*arglist)[1];
6268 tree arg1_type = TREE_TYPE (arg1);
6269 tree arg2 = (*arglist)[2];
6270 tree arg2_type = TREE_TYPE (arg2);
6271
6272 /* All 3 arguments must be vectors of (signed or unsigned) (int or
c51713e6 6273 __int128) and the types must be compatible. */
e40e5340 6274 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
bb7145f6 6275 goto bad;
55022684 6276 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)
6277 || !lang_hooks.types_compatible_p (arg1_type, arg2_type))
c51713e6 6278 goto bad;
e40e5340 6279
6280 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6281 {
bb7145f6 6282 /* For {un}signed ints,
6283 vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb),
4a777525 6284 vec_and (carryv, 1)).
6285 vec_sube (va, vb, carryv) == vec_sub (vec_sub (va, vb),
6286 vec_and (carryv, 1)). */
916ace94 6287 case E_SImode:
e40e5340 6288 {
4a777525 6289 tree add_sub_builtin;
6290
bb7145f6 6291 vec<tree, va_gc> *params = make_tree_vector ();
e40e5340 6292 vec_safe_push (params, arg0);
6293 vec_safe_push (params, arg1);
4a777525 6294
6295 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
6296 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
6297 else
6298 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
6299
6300 tree call = altivec_resolve_overloaded_builtin (loc,
6301 add_sub_builtin,
bb7145f6 6302 params);
6303 tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
6304 tree ones_vector = build_vector_from_val (arg0_type, const1);
6305 tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
6306 arg2, ones_vector);
6307 params = make_tree_vector ();
e40e5340 6308 vec_safe_push (params, call);
6309 vec_safe_push (params, and_expr);
4a777525 6310 return altivec_resolve_overloaded_builtin (loc, add_sub_builtin,
bb7145f6 6311 params);
e40e5340 6312 }
6313 /* For {un}signed __int128s use the vaddeuqm instruction
6314 directly. */
916ace94 6315 case E_TImode:
bb7145f6 6316 {
4a777525 6317 tree bii;
6318
6319 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
6320 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM];
6321
6322 else
6323 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBEUQM];
6324
6325 return altivec_resolve_overloaded_builtin (loc, bii, arglist);
bb7145f6 6326 }
e40e5340 6327
6328 /* Types other than {un}signed int and {un}signed __int128
6329 are errors. */
6330 default:
6331 goto bad;
6332 }
6333 }
6334
4a777525 6335 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC
6336 || fcode == ALTIVEC_BUILTIN_VEC_SUBEC)
61736a1b 6337 {
4a777525 6338 /* vec_addec and vec_subec needs to be special cased because there is
6339 no instruction for the {un}signed int version. */
61736a1b 6340 if (nargs != 3)
6341 {
4a777525 6342 const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDEC ?
6343 "vec_addec": "vec_subec";
2d67bb48 6344 error ("builtin %qs only accepts 3 arguments", name);
61736a1b 6345 return error_mark_node;
6346 }
6347
6348 tree arg0 = (*arglist)[0];
6349 tree arg0_type = TREE_TYPE (arg0);
6350 tree arg1 = (*arglist)[1];
6351 tree arg1_type = TREE_TYPE (arg1);
6352 tree arg2 = (*arglist)[2];
6353 tree arg2_type = TREE_TYPE (arg2);
6354
6355 /* All 3 arguments must be vectors of (signed or unsigned) (int or
c51713e6 6356 __int128) and the types must be compatible. */
61736a1b 6357 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6358 goto bad;
55022684 6359 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)
6360 || !lang_hooks.types_compatible_p (arg1_type, arg2_type))
c51713e6 6361 goto bad;
61736a1b 6362
6363 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6364 {
6365 /* For {un}signed ints,
6366 vec_addec (va, vb, carryv) ==
6367 vec_or (vec_addc (va, vb),
6368 vec_addc (vec_add (va, vb),
6369 vec_and (carryv, 0x1))). */
916ace94 6370 case E_SImode:
61736a1b 6371 {
6372 /* Use save_expr to ensure that operands used more than once
6373 that may have side effects (like calls) are only evaluated
6374 once. */
4a777525 6375 tree as_builtin;
6376 tree as_c_builtin;
6377
61736a1b 6378 arg0 = save_expr (arg0);
6379 arg1 = save_expr (arg1);
6380 vec<tree, va_gc> *params = make_tree_vector ();
6381 vec_safe_push (params, arg0);
6382 vec_safe_push (params, arg1);
4a777525 6383
6384 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6385 as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADDC];
6386 else
6387 as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUBC];
6388
6389 tree call1 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
61736a1b 6390 params);
6391 params = make_tree_vector ();
6392 vec_safe_push (params, arg0);
6393 vec_safe_push (params, arg1);
4a777525 6394
6395
6396 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6397 as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
6398 else
6399 as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
6400
6401 tree call2 = altivec_resolve_overloaded_builtin (loc, as_builtin,
61736a1b 6402 params);
6403 tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
6404 tree ones_vector = build_vector_from_val (arg0_type, const1);
6405 tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
6406 arg2, ones_vector);
6407 params = make_tree_vector ();
6408 vec_safe_push (params, call2);
6409 vec_safe_push (params, and_expr);
4a777525 6410 call2 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
61736a1b 6411 params);
6412 params = make_tree_vector ();
6413 vec_safe_push (params, call1);
6414 vec_safe_push (params, call2);
6415 tree or_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_OR];
6416 return altivec_resolve_overloaded_builtin (loc, or_builtin,
6417 params);
6418 }
4a777525 6419 /* For {un}signed __int128s use the vaddecuq/vsubbecuq
6420 instructions. */
916ace94 6421 case E_TImode:
61736a1b 6422 {
4a777525 6423 tree bii;
6424
6425 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6426 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ];
6427
6428 else
6429 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBECUQ];
6430
6431 return altivec_resolve_overloaded_builtin (loc, bii, arglist);
61736a1b 6432 }
6433 /* Types other than {un}signed int and {un}signed __int128
6434 are errors. */
6435 default:
6436 goto bad;
6437 }
6438 }
6439
290e0184 6440 /* For now treat vec_splats and vec_promote as the same. */
6441 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS
6442 || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)
6443 {
6444 tree type, arg;
6445 int size;
6446 int i;
6447 bool unsigned_p;
f1f41a6c 6448 vec<constructor_elt, va_gc> *vec;
290e0184 6449 const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote";
6450
b9c74b4d 6451 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1)
290e0184 6452 {
2d67bb48 6453 error ("builtin %qs only accepts 1 argument", name);
290e0184 6454 return error_mark_node;
6455 }
b9c74b4d 6456 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2)
290e0184 6457 {
2d67bb48 6458 error ("builtin %qs only accepts 2 arguments", name);
290e0184 6459 return error_mark_node;
6460 }
6461 /* Ignore promote's element argument. */
6462 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE
f1f41a6c 6463 && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1])))
290e0184 6464 goto bad;
6465
f1f41a6c 6466 arg = (*arglist)[0];
290e0184 6467 type = TREE_TYPE (arg);
6468 if (!SCALAR_FLOAT_TYPE_P (type)
6469 && !INTEGRAL_TYPE_P (type))
6470 goto bad;
6471 unsigned_p = TYPE_UNSIGNED (type);
290e0184 6472 switch (TYPE_MODE (type))
6473 {
916ace94 6474 case E_TImode:
ae61c502 6475 type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
6476 size = 1;
6477 break;
916ace94 6478 case E_DImode:
32374e3c 6479 type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
6480 size = 2;
6481 break;
916ace94 6482 case E_SImode:
290e0184 6483 type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
6484 size = 4;
6485 break;
916ace94 6486 case E_HImode:
290e0184 6487 type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
6488 size = 8;
6489 break;
916ace94 6490 case E_QImode:
290e0184 6491 type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
6492 size = 16;
6493 break;
916ace94 6494 case E_SFmode: type = V4SF_type_node; size = 4; break;
6495 case E_DFmode: type = V2DF_type_node; size = 2; break;
290e0184 6496 default:
6497 goto bad;
6498 }
6499 arg = save_expr (fold_convert (TREE_TYPE (type), arg));
f1f41a6c 6500 vec_alloc (vec, size);
290e0184 6501 for(i = 0; i < size; i++)
6502 {
e82e4eb5 6503 constructor_elt elt = {NULL_TREE, arg};
f1f41a6c 6504 vec->quick_push (elt);
290e0184 6505 }
6506 return build_constructor (type, vec);
6507 }
6508
51cc20fd 6509 /* For now use pointer tricks to do the extraction, unless we are on VSX
32374e3c 6510 extracting a double from a constant offset. */
290e0184 6511 if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)
6512 {
6513 tree arg1;
6514 tree arg1_type;
6515 tree arg2;
6516 tree arg1_inner_type;
6517 tree decl, stmt;
6518 tree innerptrtype;
3754d046 6519 machine_mode mode;
290e0184 6520
6521 /* No second argument. */
b9c74b4d 6522 if (nargs != 2)
290e0184 6523 {
2d67bb48 6524 error ("builtin %qs only accepts 2 arguments", "vec_extract");
290e0184 6525 return error_mark_node;
6526 }
6527
f1f41a6c 6528 arg2 = (*arglist)[1];
6529 arg1 = (*arglist)[0];
290e0184 6530 arg1_type = TREE_TYPE (arg1);
6531
6532 if (TREE_CODE (arg1_type) != VECTOR_TYPE)
bb7145f6 6533 goto bad;
290e0184 6534 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
bb7145f6 6535 goto bad;
32374e3c 6536
a52bb7a0 6537 /* See if we can optimize vec_extracts with the current VSX instruction
6538 set. */
32374e3c 6539 mode = TYPE_MODE (arg1_type);
a52bb7a0 6540 if (VECTOR_MEM_VSX_P (mode))
6541
32374e3c 6542 {
6543 tree call = NULL_TREE;
a52bb7a0 6544 int nunits = GET_MODE_NUNITS (mode);
6545
4f9cda3d 6546 arg2 = fold_for_warn (arg2);
6547
a52bb7a0 6548 /* If the second argument is an integer constant, if the value is in
6549 the expected range, generate the built-in code if we can. We need
6550 64-bit and direct move to extract the small integer vectors. */
e3d0f65c 6551 if (TREE_CODE (arg2) == INTEGER_CST
6552 && wi::ltu_p (wi::to_wide (arg2), nunits))
a52bb7a0 6553 {
6554 switch (mode)
6555 {
6556 default:
6557 break;
6558
916ace94 6559 case E_V1TImode:
a52bb7a0 6560 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
6561 break;
32374e3c 6562
916ace94 6563 case E_V2DFmode:
a52bb7a0 6564 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6565 break;
6566
916ace94 6567 case E_V2DImode:
a52bb7a0 6568 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6569 break;
c79d3723 6570
916ace94 6571 case E_V4SFmode:
c79d3723 6572 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6573 break;
6574
916ace94 6575 case E_V4SImode:
c79d3723 6576 if (TARGET_DIRECT_MOVE_64BIT)
6577 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6578 break;
6579
916ace94 6580 case E_V8HImode:
c79d3723 6581 if (TARGET_DIRECT_MOVE_64BIT)
6582 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6583 break;
6584
916ace94 6585 case E_V16QImode:
c79d3723 6586 if (TARGET_DIRECT_MOVE_64BIT)
6587 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6588 break;
a52bb7a0 6589 }
6590 }
6591
6592 /* If the second argument is variable, we can optimize it if we are
6593 generating 64-bit code on a machine with direct move. */
6594 else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT)
6595 {
6596 switch (mode)
6597 {
6598 default:
6599 break;
6600
916ace94 6601 case E_V2DFmode:
a52bb7a0 6602 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6603 break;
6604
916ace94 6605 case E_V2DImode:
a52bb7a0 6606 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6607 break;
c79d3723 6608
916ace94 6609 case E_V4SFmode:
c79d3723 6610 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6611 break;
6612
916ace94 6613 case E_V4SImode:
c79d3723 6614 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6615 break;
6616
916ace94 6617 case E_V8HImode:
c79d3723 6618 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6619 break;
6620
916ace94 6621 case E_V16QImode:
c79d3723 6622 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6623 break;
a52bb7a0 6624 }
6625 }
32374e3c 6626
6627 if (call)
6628 return build_call_expr (call, 2, arg1, arg2);
6629 }
6630
290e0184 6631 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */
6632 arg1_inner_type = TREE_TYPE (arg1_type);
65edca84 6633 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
290e0184 6634 build_int_cst (TREE_TYPE (arg2),
6635 TYPE_VECTOR_SUBPARTS (arg1_type)
6636 - 1), 0);
65edca84 6637 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
290e0184 6638 DECL_EXTERNAL (decl) = 0;
6639 TREE_PUBLIC (decl) = 0;
6640 DECL_CONTEXT (decl) = current_function_decl;
6641 TREE_USED (decl) = 1;
6642 TREE_TYPE (decl) = arg1_type;
6643 TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
79f0505e 6644 if (c_dialect_cxx ())
6645 {
6646 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6647 NULL_TREE, NULL_TREE);
6648 SET_EXPR_LOCATION (stmt, loc);
6649 }
6650 else
6651 {
6652 DECL_INITIAL (decl) = arg1;
6653 stmt = build1 (DECL_EXPR, arg1_type, decl);
6654 TREE_ADDRESSABLE (decl) = 1;
6655 SET_EXPR_LOCATION (stmt, loc);
6656 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6657 }
290e0184 6658
6659 innerptrtype = build_pointer_type (arg1_inner_type);
6660
65edca84 6661 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
290e0184 6662 stmt = convert (innerptrtype, stmt);
65edca84 6663 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
98a3a0b0 6664 stmt = build_indirect_ref (loc, stmt, RO_NULL);
290e0184 6665
4482dd6d 6666 /* PR83660: We mark this as having side effects so that
6667 downstream in fold_build_cleanup_point_expr () it will get a
6668 CLEANUP_POINT_EXPR. If it does not we can run into an ICE
6669 later in gimplify_cleanup_point_expr (). Potentially this
6670 causes missed optimization because the actually is no side
6671 effect. */
6672 if (c_dialect_cxx ())
6673 TREE_SIDE_EFFECTS (stmt) = 1;
6674
290e0184 6675 return stmt;
6676 }
6677
51cc20fd 6678 /* For now use pointer tricks to do the insertion, unless we are on VSX
32374e3c 6679 inserting a double to a constant offset.. */
290e0184 6680 if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)
6681 {
6682 tree arg0;
6683 tree arg1;
6684 tree arg2;
6685 tree arg1_type;
6686 tree arg1_inner_type;
6687 tree decl, stmt;
6688 tree innerptrtype;
3754d046 6689 machine_mode mode;
32374e3c 6690
290e0184 6691 /* No second or third arguments. */
b9c74b4d 6692 if (nargs != 3)
290e0184 6693 {
2d67bb48 6694 error ("builtin %qs only accepts 3 arguments", "vec_insert");
290e0184 6695 return error_mark_node;
6696 }
6697
f1f41a6c 6698 arg0 = (*arglist)[0];
6699 arg1 = (*arglist)[1];
290e0184 6700 arg1_type = TREE_TYPE (arg1);
4f9cda3d 6701 arg2 = fold_for_warn ((*arglist)[2]);
290e0184 6702
6703 if (TREE_CODE (arg1_type) != VECTOR_TYPE)
bb7145f6 6704 goto bad;
290e0184 6705 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
bb7145f6 6706 goto bad;
32374e3c 6707
6708 /* If we can use the VSX xxpermdi instruction, use that for insert. */
6709 mode = TYPE_MODE (arg1_type);
6710 if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)
38f59234 6711 && TREE_CODE (arg2) == INTEGER_CST
e3d0f65c 6712 && wi::ltu_p (wi::to_wide (arg2), 2))
32374e3c 6713 {
6714 tree call = NULL_TREE;
6715
6716 if (mode == V2DFmode)
6717 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF];
6718 else if (mode == V2DImode)
6719 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI];
6720
6721 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6722 reversed. */
6723 if (call)
6724 return build_call_expr (call, 3, arg1, arg0, arg2);
6725 }
ae61c502 6726 else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)
6727 && TREE_CODE (arg2) == INTEGER_CST
e3d0f65c 6728 && wi::eq_p (wi::to_wide (arg2), 0))
ae61c502 6729 {
6730 tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];
6731
6732 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6733 reversed. */
6734 return build_call_expr (call, 3, arg1, arg0, arg2);
6735 }
32374e3c 6736
290e0184 6737 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */
6738 arg1_inner_type = TREE_TYPE (arg1_type);
65edca84 6739 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
290e0184 6740 build_int_cst (TREE_TYPE (arg2),
6741 TYPE_VECTOR_SUBPARTS (arg1_type)
6742 - 1), 0);
65edca84 6743 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
290e0184 6744 DECL_EXTERNAL (decl) = 0;
6745 TREE_PUBLIC (decl) = 0;
6746 DECL_CONTEXT (decl) = current_function_decl;
6747 TREE_USED (decl) = 1;
6748 TREE_TYPE (decl) = arg1_type;
6749 TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
79f0505e 6750 if (c_dialect_cxx ())
6751 {
6752 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6753 NULL_TREE, NULL_TREE);
6754 SET_EXPR_LOCATION (stmt, loc);
6755 }
6756 else
6757 {
6758 DECL_INITIAL (decl) = arg1;
6759 stmt = build1 (DECL_EXPR, arg1_type, decl);
6760 TREE_ADDRESSABLE (decl) = 1;
6761 SET_EXPR_LOCATION (stmt, loc);
6762 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6763 }
290e0184 6764
6765 innerptrtype = build_pointer_type (arg1_inner_type);
6766
65edca84 6767 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
290e0184 6768 stmt = convert (innerptrtype, stmt);
65edca84 6769 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
98a3a0b0 6770 stmt = build_indirect_ref (loc, stmt, RO_NULL);
290e0184 6771 stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt,
6772 convert (TREE_TYPE (stmt), arg0));
6773 stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl);
6774 return stmt;
6775 }
6776
65441f6f 6777 for (n = 0;
b9c74b4d 6778 !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs;
6779 fnargs = TREE_CHAIN (fnargs), n++)
65441f6f 6780 {
6781 tree decl_type = TREE_VALUE (fnargs);
f1f41a6c 6782 tree arg = (*arglist)[n];
65441f6f 6783 tree type;
6784
6785 if (arg == error_mark_node)
6786 return error_mark_node;
6787
6788 if (n >= 3)
6789 abort ();
6790
6791 arg = default_conversion (arg);
6792
6793 /* The C++ front-end converts float * to const void * using
6794 NOP_EXPR<const void *> (NOP_EXPR<void *> (x)). */
6795 type = TREE_TYPE (arg);
6796 if (POINTER_TYPE_P (type)
6797 && TREE_CODE (arg) == NOP_EXPR
6798 && lang_hooks.types_compatible_p (TREE_TYPE (arg),
6799 const_ptr_type_node)
6800 && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)),
6801 ptr_type_node))
6802 {
6803 arg = TREE_OPERAND (arg, 0);
6804 type = TREE_TYPE (arg);
6805 }
6806
6807 /* Remove the const from the pointers to simplify the overload
6808 matching further down. */
6809 if (POINTER_TYPE_P (decl_type)
6810 && POINTER_TYPE_P (type)
6811 && TYPE_QUALS (TREE_TYPE (type)) != 0)
6812 {
6813 if (TYPE_READONLY (TREE_TYPE (type))
6814 && !TYPE_READONLY (TREE_TYPE (decl_type)))
d0abd9e0 6815 warning (0, "passing arg %d of %qE discards qualifiers from "
65441f6f 6816 "pointer target type", n + 1, fndecl);
6817 type = build_pointer_type (build_qualified_type (TREE_TYPE (type),
6818 0));
6819 arg = fold_convert (type, arg);
6820 }
6821
6822 args[n] = arg;
6823 types[n] = type;
6824 }
6825
6826 /* If the number of arguments did not match the prototype, return NULL
6827 and the generic code will issue the appropriate error message. */
da84efc1 6828 if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs)
65441f6f 6829 return NULL;
6830
6831 if (n == 0)
6832 abort ();
6833
6834 if (fcode == ALTIVEC_BUILTIN_VEC_STEP)
6835 {
6836 if (TREE_CODE (types[0]) != VECTOR_TYPE)
6837 goto bad;
6838
6839 return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0]));
6840 }
6841
97468983 6842 {
6843 bool unsupported_builtin = false;
d8cd56b1 6844 enum rs6000_builtins overloaded_code;
6845 tree result = NULL;
97468983 6846 for (desc = altivec_overloaded_builtins;
6847 desc->code && desc->code != fcode; desc++)
6848 continue;
9534dff5 6849
6850 /* Need to special case __builtin_cmp because the overloaded forms
6851 of this function take (unsigned int, unsigned int) or (unsigned
6852 long long int, unsigned long long int). Since C conventions
6853 allow the respective argument types to be implicitly coerced into
6854 each other, the default handling does not provide adequate
6855 discrimination between the desired forms of the function. */
6856 if (fcode == P6_OV_BUILTIN_CMPB)
97468983 6857 {
582adad1 6858 machine_mode arg1_mode = TYPE_MODE (types[0]);
6859 machine_mode arg2_mode = TYPE_MODE (types[1]);
9534dff5 6860
6861 if (nargs != 2)
6862 {
2d67bb48 6863 error ("builtin %qs only accepts 2 arguments", "__builtin_cmpb");
9534dff5 6864 return error_mark_node;
6865 }
6866
6867 /* If any supplied arguments are wider than 32 bits, resolve to
6868 64-bit variant of built-in function. */
6869 if ((GET_MODE_PRECISION (arg1_mode) > 32)
6870 || (GET_MODE_PRECISION (arg2_mode) > 32))
6871 {
6872 /* Assure all argument and result types are compatible with
6873 the built-in function represented by P6_BUILTIN_CMPB. */
6874 overloaded_code = P6_BUILTIN_CMPB;
6875 }
6876 else
6877 {
6878 /* Assure all argument and result types are compatible with
6879 the built-in function represented by P6_BUILTIN_CMPB_32. */
6880 overloaded_code = P6_BUILTIN_CMPB_32;
6881 }
6882
55022684 6883 while (desc->code && desc->code == fcode
6884 && desc->overloaded_code != overloaded_code)
9534dff5 6885 desc++;
6886
6887 if (desc->code && (desc->code == fcode)
6888 && rs6000_builtin_type_compatible (types[0], desc->op1)
6889 && rs6000_builtin_type_compatible (types[1], desc->op2))
97468983 6890 {
6891 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
d8cd56b1 6892 {
6893 result = altivec_build_resolved_builtin (args, n, desc);
6894 /* overloaded_code is set above */
6895 if (!rs6000_builtin_is_supported_p (overloaded_code))
6896 unsupported_builtin = true;
6897 else
6898 return result;
6899 }
97468983 6900 else
6901 unsupported_builtin = true;
6902 }
6903 }
4a71f283 6904 else if (fcode == P9V_BUILTIN_VEC_VSIEDP)
6905 {
80a63790 6906 machine_mode arg1_mode = TYPE_MODE (types[0]);
4a71f283 6907
6908 if (nargs != 2)
6909 {
2d67bb48 6910 error ("builtin %qs only accepts 2 arguments",
6911 "scalar_insert_exp");
4a71f283 6912 return error_mark_node;
6913 }
6914
6915 /* If supplied first argument is wider than 64 bits, resolve to
6916 128-bit variant of built-in function. */
6917 if (GET_MODE_PRECISION (arg1_mode) > 64)
6918 {
6919 /* If first argument is of float variety, choose variant
6920 that expects __ieee128 argument. Otherwise, expect
6921 __int128 argument. */
6922 if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
6923 overloaded_code = P9V_BUILTIN_VSIEQPF;
6924 else
6925 overloaded_code = P9V_BUILTIN_VSIEQP;
6926 }
6927 else
6928 {
6929 /* If first argument is of float variety, choose variant
6930 that expects double argument. Otherwise, expect
6931 long long int argument. */
6932 if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
6933 overloaded_code = P9V_BUILTIN_VSIEDPF;
6934 else
6935 overloaded_code = P9V_BUILTIN_VSIEDP;
6936 }
55022684 6937 while (desc->code && desc->code == fcode
6938 && desc->overloaded_code != overloaded_code)
4a71f283 6939 desc++;
d8cd56b1 6940
4a71f283 6941 if (desc->code && (desc->code == fcode)
6942 && rs6000_builtin_type_compatible (types[0], desc->op1)
6943 && rs6000_builtin_type_compatible (types[1], desc->op2))
6944 {
6945 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
d8cd56b1 6946 {
6947 result = altivec_build_resolved_builtin (args, n, desc);
6948 /* overloaded_code is set above. */
6949 if (!rs6000_builtin_is_supported_p (overloaded_code))
6950 unsupported_builtin = true;
6951 else
6952 return result;
6953 }
4a71f283 6954 else
6955 unsupported_builtin = true;
6956 }
6957 }
9534dff5 6958 else
6959 {
6960 /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in
6961 the opX fields. */
6962 for (; desc->code == fcode; desc++)
6963 {
6964 if ((desc->op1 == RS6000_BTI_NOT_OPAQUE
6965 || rs6000_builtin_type_compatible (types[0], desc->op1))
6966 && (desc->op2 == RS6000_BTI_NOT_OPAQUE
6967 || rs6000_builtin_type_compatible (types[1], desc->op2))
6968 && (desc->op3 == RS6000_BTI_NOT_OPAQUE
6969 || rs6000_builtin_type_compatible (types[2], desc->op3)))
6970 {
6971 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
d8cd56b1 6972 {
6973 result = altivec_build_resolved_builtin (args, n, desc);
6974 if (!rs6000_builtin_is_supported_p (desc->overloaded_code))
6975 {
6976 /* Allow loop to continue in case a different
6977 definition is supported. */
6978 overloaded_code = desc->overloaded_code;
6979 unsupported_builtin = true;
6980 }
6981 else
6982 return result;
6983 }
9534dff5 6984 else
6985 unsupported_builtin = true;
6986 }
6987 }
6988 }
6989
97468983 6990 if (unsupported_builtin)
6991 {
6992 const char *name = rs6000_overloaded_builtin_name (fcode);
d8cd56b1 6993 if (result != NULL)
6994 {
6995 const char *internal_name
6996 = rs6000_overloaded_builtin_name (overloaded_code);
6997 /* An error message making reference to the name of the
6998 non-overloaded function has already been issued. Add
6999 clarification of the previous message. */
7000 rich_location richloc (line_table, input_location);
7001 inform (&richloc, "builtin %qs requires builtin %qs",
7002 name, internal_name);
7003 }
7004 else
7005 error ("builtin function %qs not supported in this compiler "
7006 "configuration", name);
7007 /* If an error-representing result tree was returned from
7008 altivec_build_resolved_builtin above, use it. */
7009 return (result != NULL) ? result : error_mark_node;
97468983 7010 }
7011 }
65441f6f 7012 bad:
55022684 7013 {
7014 const char *name = rs6000_overloaded_builtin_name (fcode);
2d67bb48 7015 error ("invalid parameter combination for AltiVec intrinsic %qs", name);
55022684 7016 return error_mark_node;
7017 }
b2d381e8 7018}
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