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[PATCH, PR target/94954] Fix wrong codegen for vec_pack_to_short_fp32() builtin
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000-call.c
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1acf0246
BS		 1/* Subroutines used to generate function calls and handle built-in
2 instructions on IBM RS/6000.
8d9254fc 3 Copyright (C) 1991-2020 Free Software Foundation, Inc.
1acf0246
BS		 4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21#define IN_TARGET_CODE 1
22
23#include "config.h"
24#include "system.h"
25#include "coretypes.h"
26#include "backend.h"
27#include "rtl.h"
28#include "tree.h"
29#include "memmodel.h"
30#include "gimple.h"
31#include "cfghooks.h"
32#include "cfgloop.h"
33#include "df.h"
34#include "tm_p.h"
35#include "stringpool.h"
36#include "expmed.h"
37#include "optabs.h"
38#include "regs.h"
39#include "ira.h"
40#include "recog.h"
41#include "cgraph.h"
42#include "diagnostic-core.h"
43#include "insn-attr.h"
44#include "flags.h"
45#include "alias.h"
46#include "fold-const.h"
47#include "attribs.h"
48#include "stor-layout.h"
49#include "calls.h"
50#include "print-tree.h"
51#include "varasm.h"
52#include "explow.h"
53#include "expr.h"
54#include "output.h"
55#include "common/common-target.h"
56#include "langhooks.h"
57#include "gimplify.h"
58#include "gimple-fold.h"
59#include "gimple-iterator.h"
60#include "gimple-ssa.h"
61#include "builtins.h"
62#include "tree-vector-builder.h"
63#if TARGET_XCOFF
64#include "xcoffout.h" /* get declarations of xcoff_*_section_name */
65#endif
66#include "ppc-auxv.h"
67#include "tree-ssa-propagate.h"
68#include "tree-vrp.h"
69#include "tree-ssanames.h"
70#include "targhooks.h"
691eeb65 71#include "opts.h"
1acf0246
BS		 72
73#include "rs6000-internal.h"
74
75#if TARGET_MACHO
76#include "gstab.h" /* for N_SLINE */
77#include "dbxout.h" /* dbxout_ */
78#endif
79
80#ifndef TARGET_PROFILE_KERNEL
81#define TARGET_PROFILE_KERNEL 0
82#endif
83
c3550462
BS		 84#ifdef HAVE_AS_GNU_ATTRIBUTE
85# ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
86# define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
87# endif
88#endif
89
48df9391
IS		 90#ifndef TARGET_NO_PROTOTYPE
91#define TARGET_NO_PROTOTYPE 0
92#endif
93
1acf0246
BS		 94struct builtin_description
95{
96 const HOST_WIDE_INT mask;
97 const enum insn_code icode;
98 const char *const name;
99 const enum rs6000_builtins code;
100};
101
102/* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
103static const struct
104{
105 const char *cpu;
106 unsigned int cpuid;
107} cpu_is_info[] = {
108 { "power9", PPC_PLATFORM_POWER9 },
109 { "power8", PPC_PLATFORM_POWER8 },
110 { "power7", PPC_PLATFORM_POWER7 },
111 { "power6x", PPC_PLATFORM_POWER6X },
112 { "power6", PPC_PLATFORM_POWER6 },
113 { "power5+", PPC_PLATFORM_POWER5_PLUS },
114 { "power5", PPC_PLATFORM_POWER5 },
115 { "ppc970", PPC_PLATFORM_PPC970 },
116 { "power4", PPC_PLATFORM_POWER4 },
117 { "ppca2", PPC_PLATFORM_PPCA2 },
118 { "ppc476", PPC_PLATFORM_PPC476 },
119 { "ppc464", PPC_PLATFORM_PPC464 },
120 { "ppc440", PPC_PLATFORM_PPC440 },
121 { "ppc405", PPC_PLATFORM_PPC405 },
122 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
123};
124
125/* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
126static const struct
127{
128 const char *hwcap;
129 int mask;
130 unsigned int id;
131} cpu_supports_info[] = {
132 /* AT_HWCAP masks. */
133 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
134 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
135 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
136 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
137 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
138 { "booke", PPC_FEATURE_BOOKE, 0 },
139 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
140 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
141 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
142 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
143 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
144 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
145 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
146 { "notb", PPC_FEATURE_NO_TB, 0 },
147 { "pa6t", PPC_FEATURE_PA6T, 0 },
148 { "power4", PPC_FEATURE_POWER4, 0 },
149 { "power5", PPC_FEATURE_POWER5, 0 },
150 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
151 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
152 { "ppc32", PPC_FEATURE_32, 0 },
153 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
154 { "ppc64", PPC_FEATURE_64, 0 },
155 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
156 { "smt", PPC_FEATURE_SMT, 0 },
157 { "spe", PPC_FEATURE_HAS_SPE, 0 },
158 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
159 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
160 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
161
162 /* AT_HWCAP2 masks. */
163 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
164 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
165 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
166 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
167 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
168 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
169 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
170 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
171 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
172 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
173 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
174 { "darn", PPC_FEATURE2_DARN, 1 },
7ba33e89
MM		 175 { "scv", PPC_FEATURE2_SCV, 1 },
176 { "arch_3_1", PPC_FEATURE2_ARCH_3_1, 1 },
177 { "mma", PPC_FEATURE2_MMA, 1 },
1acf0246
BS		 178};
179
180static void altivec_init_builtins (void);
181static tree builtin_function_type (machine_mode, machine_mode,
182 machine_mode, machine_mode,
183 enum rs6000_builtins, const char *name);
184static void rs6000_common_init_builtins (void);
185static void htm_init_builtins (void);
8ee2640b 186static void mma_init_builtins (void);
1acf0246
BS		 187
188
189/* Hash table to keep track of the argument types for builtin functions. */
190
191struct GTY((for_user)) builtin_hash_struct
192{
193 tree type;
194 machine_mode mode[4]; /* return value + 3 arguments. */
195 unsigned char uns_p[4]; /* and whether the types are unsigned. */
196};
197
198struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
199{
200 static hashval_t hash (builtin_hash_struct *);
201 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
202};
203
204static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
205
206/* Hash function for builtin functions with up to 3 arguments and a return
207 type. */
208hashval_t
209builtin_hasher::hash (builtin_hash_struct *bh)
210{
211 unsigned ret = 0;
212 int i;
213
214 for (i = 0; i < 4; i++)
215 {
216 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
217 ret = (ret * 2) + bh->uns_p[i];
218 }
219
220 return ret;
221}
222
223/* Compare builtin hash entries H1 and H2 for equivalence. */
224bool
225builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
226{
227 return ((p1->mode[0] == p2->mode[0])
228 && (p1->mode[1] == p2->mode[1])
229 && (p1->mode[2] == p2->mode[2])
230 && (p1->mode[3] == p2->mode[3])
231 && (p1->uns_p[0] == p2->uns_p[0])
232 && (p1->uns_p[1] == p2->uns_p[1])
233 && (p1->uns_p[2] == p2->uns_p[2])
234 && (p1->uns_p[3] == p2->uns_p[3]));
235}
236
237\f
238/* Table that classifies rs6000 builtin functions (pure, const, etc.). */
239#undef RS6000_BUILTIN_0
240#undef RS6000_BUILTIN_1
241#undef RS6000_BUILTIN_2
242#undef RS6000_BUILTIN_3
840ac85c 243#undef RS6000_BUILTIN_4
1acf0246
BS		 244#undef RS6000_BUILTIN_A
245#undef RS6000_BUILTIN_D
246#undef RS6000_BUILTIN_H
8ee2640b 247#undef RS6000_BUILTIN_M
1acf0246
BS		 248#undef RS6000_BUILTIN_P
249#undef RS6000_BUILTIN_X
250
251#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
252 { NAME, ICODE, MASK, ATTR },
253
254#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
255 { NAME, ICODE, MASK, ATTR },
256
257#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
258 { NAME, ICODE, MASK, ATTR },
259
260#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
261 { NAME, ICODE, MASK, ATTR },
262
840ac85c
KN		 263#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) \
264 { NAME, ICODE, MASK, ATTR },
265
1acf0246
BS		 266#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
267 { NAME, ICODE, MASK, ATTR },
268
269#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
270 { NAME, ICODE, MASK, ATTR },
271
272#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
273 { NAME, ICODE, MASK, ATTR },
274
8ee2640b
PB		 275#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \
276 { NAME, ICODE, MASK, ATTR },
277
1acf0246
BS		 278#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
279 { NAME, ICODE, MASK, ATTR },
280
281#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
282 { NAME, ICODE, MASK, ATTR },
283
284struct rs6000_builtin_info_type {
285 const char *name;
286 const enum insn_code icode;
287 const HOST_WIDE_INT mask;
288 const unsigned attr;
289};
290
25ffd3d3 291static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1acf0246
BS		 292{
293#include "rs6000-builtin.def"
294};
295
296#undef RS6000_BUILTIN_0
297#undef RS6000_BUILTIN_1
298#undef RS6000_BUILTIN_2
299#undef RS6000_BUILTIN_3
840ac85c 300#undef RS6000_BUILTIN_4
1acf0246
BS		 301#undef RS6000_BUILTIN_A
302#undef RS6000_BUILTIN_D
303#undef RS6000_BUILTIN_H
8ee2640b 304#undef RS6000_BUILTIN_M
1acf0246
BS		 305#undef RS6000_BUILTIN_P
306#undef RS6000_BUILTIN_X
307
25ffd3d3
PB		 308const struct altivec_builtin_types altivec_overloaded_builtins[] = {
309 /* Unary AltiVec/VSX builtins. */
310 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
311 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
312 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
313 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
314 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
315 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
316 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
317 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
318 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
319 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
320 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
321 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
322 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
323 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
324 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
325 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
326 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
327 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
328 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
329 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
330 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
331 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
332 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
333 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
334 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
335 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
336 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
337 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
338 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
339 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
340 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
341 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
342 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
343 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
344 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
345 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
346 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
347 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
348 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
349 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
350 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
351 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
352 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
353 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
354 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
355 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
356 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
357 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
358 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
359 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
360 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
361 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
362 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
363 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
364 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
365 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
366 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
367 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
368 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
369 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
370 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
371 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
372 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
373 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
374 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
375 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
376 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
377 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
378 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
379 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
380 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
381 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
382 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
383 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
384 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
385 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
386 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
387 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
388 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
389 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
390 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
391 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
392 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
393 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
394 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
395 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
396 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
397 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
398 { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF,
399 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
400 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
401 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
402 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
403 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
404 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
405 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
406 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
407 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
408 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
409 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
410 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
411 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
412 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
413 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
414 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
415 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
416 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
417 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
418 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
419 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
420 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
421 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
422 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
423 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
424 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
425 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
426 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
427 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
428 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
429 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
430 { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF,
431 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
432 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
433 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
434 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
435 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
436 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
437 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
438 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
439 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
440 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
441 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
442 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
443 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
444
445 /* Binary AltiVec/VSX builtins. */
446 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
447 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
448 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
449 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
450 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
451 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
452 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
453 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
454 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
455 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
456 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
457 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
458 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
459 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
460 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
461 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
462 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
463 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
464 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
465 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
466 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
467 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
468 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
469 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
470 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
471 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
472 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
473 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
474 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
475 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
476 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
477 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
478 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
479 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
480 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
481 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
482 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
483 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
484 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
485 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
486 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
487 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
488 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
489 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
490 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
491 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
492 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
493 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
494 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
495 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
496 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
497 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
498 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
499 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
500 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
501 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
502 RS6000_BTI_unsigned_V1TI, 0 },
503 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
504 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
505 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
506 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
507 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
508 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
509 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
510 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
511 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
512 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
513 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
514 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
515 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
516 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
517 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
518 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
519 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
520 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
521 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
522 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
523 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
524 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
525 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
526 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
527 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
528 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
529 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
530 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
531 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
532 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
533 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
534 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
535 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
536 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
537 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
538 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
539 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
540 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
541 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
542 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
543 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
544 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
545 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
546 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
547 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
548 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
549 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
550 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
551 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
552 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
553 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
554 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
555 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
556 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
557 RS6000_BTI_unsigned_V4SI, 0 },
558 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
559 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
560 RS6000_BTI_unsigned_V1TI, 0 },
561 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
562 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
563 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
564 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
565 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
566 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
567 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
568 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
569 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
570 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
571 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
572 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
573 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
574 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
575 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
576 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
577 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
578 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
579 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
580 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
581 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
582 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
583 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
584 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
585 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
586 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
587 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
588 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
589 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
590 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
591 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
592 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
593 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
594 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
595 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
596 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
597 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
598 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
599 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
600 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
601 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
602 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
603 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
604 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
605 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
606 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
607 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
608 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
609 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
610 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
611 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
612 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
613 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
614 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
615 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
616 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
617 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
618 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
619 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
620 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
621 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
622 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
623 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
624 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
625 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
626 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
627 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
628 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
629 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
630 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
631 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
632 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
633 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
634 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
635 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
636 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
637 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
638 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
639 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
640 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
641 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
642 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
643 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
644 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
645 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
646 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
647 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
648 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
649 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
650 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
651 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23
PB		 652
653 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
25ffd3d3 654 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 655 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
25ffd3d3 656 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 657 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
25ffd3d3 658 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 659 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
25ffd3d3 660 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 661 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
25ffd3d3 662 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 663 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
25ffd3d3 664 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 665 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
25ffd3d3 666 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 667 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
25ffd3d3 668 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 669 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
25ffd3d3 670 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 671 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 672 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 673 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 674 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 675 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 676 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 677 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 678 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 679 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 680 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 681 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
25ffd3d3 682 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 683 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
25ffd3d3 684 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 685 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
25ffd3d3 686 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 687 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 688 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 689 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 690 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 691 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 692 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 693 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 694 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 695 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
25ffd3d3 696 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 697 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
25ffd3d3 698 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 699 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
25ffd3d3 700 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 701 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 702 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 703 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 704 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 705 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 706 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 707 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
25ffd3d3 708 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 709 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 710 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 711 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
25ffd3d3 712 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 713 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
25ffd3d3 714 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 715 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 716 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 717 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 718 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 719 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 720 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23
PB		 721
722 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
25ffd3d3 723 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 724 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
25ffd3d3 725 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 726 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
25ffd3d3 727 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 728 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
25ffd3d3 729 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 730 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
25ffd3d3 731 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 732 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
25ffd3d3 733 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 734 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
25ffd3d3 735 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 736 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
25ffd3d3 737 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 738 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
25ffd3d3 739 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 740 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 741 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 742 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 743 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 744 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 745 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 746 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 747 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 748 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 749 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 750 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
25ffd3d3 751 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 752 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
25ffd3d3 753 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 754 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
25ffd3d3 755 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 756 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 757 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 758 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 759 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 760 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 761 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 762 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 763 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 764 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
25ffd3d3 765 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 766 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
25ffd3d3 767 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 768 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
25ffd3d3 769 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 770 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 771 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 772 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 773 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 774 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 775 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 776 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
25ffd3d3 777 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 778 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 779 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 780 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
25ffd3d3 781 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 782 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
25ffd3d3 783 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 784 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 785 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 786 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 787 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 788 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 789 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 790
25ffd3d3
PB		 791 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
792 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
793 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
794 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
795 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
796 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
797 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
798 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
799 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
800 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
801 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
802 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
803 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
804 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
805 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
806 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
807 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
808 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
809 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
810 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
811 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
812 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
813 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
814 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
815 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
816 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
817 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
818 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
819 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
820 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
821 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
822 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
823 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
824 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
825 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
826 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
827 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
828 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
829 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
830 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
831 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
832 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
833 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
834 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
835 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
836 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
837 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
838 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
839 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
840 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
841 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
842 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
843 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
844 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
845 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
846 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
847
848 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
849 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
850 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
851 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
852
853 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
854 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
855 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
856 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
857
858 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
859 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
860 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
861 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
862
863 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
864 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
865 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
866 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
867 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
868 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
869 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
870 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
871 RS6000_BTI_unsigned_V16QI, 0},
872 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
873 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
874 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
875 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
876 RS6000_BTI_unsigned_V8HI, 0},
877 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
878 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
879 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
880 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
881 RS6000_BTI_unsigned_V4SI, 0},
882 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
883 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
884 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
885 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
886 RS6000_BTI_unsigned_V2DI, 0},
887 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
888 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
889 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
890 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
891 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
892 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
893 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
894 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
895 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
896 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
897 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
898 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
899 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
900 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
901 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
902 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
903 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
904 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
905 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
906 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
907 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
908 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
909 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
910 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
911 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
912 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
913 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
914 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
915 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
916 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
917 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
918 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
919 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
920 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
921 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
922 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
923 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
924 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
925 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
926 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
927 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
928 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
929 RS6000_BTI_unsigned_V16QI, 0},
930 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
931 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
932 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
933 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
934 RS6000_BTI_unsigned_V8HI, 0},
935 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
936 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
937 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
938 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
939 RS6000_BTI_unsigned_V4SI, 0},
940 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
941 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
942 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
943 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
944 RS6000_BTI_unsigned_V2DI, 0},
945 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
946 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
947 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
948 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
949 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
950 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
951 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
952 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
953 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
954 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
955 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
956 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
957 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
958 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
959 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
960 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
961 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
962 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
963 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
964 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
965 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
966 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
967 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
968 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
969 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
970 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
971 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
972 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
973 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
974 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
975 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
976 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
977 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
978 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
979 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
980 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
981 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
982 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
983 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
984 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
985 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
986 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
987 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
988 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
989 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
990 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
991 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
992 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
993 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
994 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
995 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
996 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
997 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
998 RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
999 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1000 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1001
1002 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
1003 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1004 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
1005 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1006 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
1007 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1008
1009 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
1010 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1011 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
1012 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1013 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
1014 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1015
1016 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI,
1017 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1018 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI,
1019 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1020 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF,
1021 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1022
1023 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI,
1024 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1025 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI,
1026 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1027 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF,
1028 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1029
1030 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1031 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1032 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1033 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1034 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF,
1035 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1036 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI,
1037 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1038 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI,
1039 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1040 RS6000_BTI_unsigned_V2DI, 0 },
1041 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1042 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1043 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1044 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1045 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI,
1046 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1047 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF,
1048 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1049 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1050 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1051 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1052 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1053
1054 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1055 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
1056 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1057 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 },
1058 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1059 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
1060 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1061 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
1062
1063 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1064 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1065 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1066 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1067 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1068 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1069 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1070 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1071 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1072 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1073 ~RS6000_BTI_unsigned_V2DI, 0 },
1074 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1075 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1076 ~RS6000_BTI_unsigned_long_long, 0 },
1077 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1078 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1079 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1080 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1081 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1082 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1083 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1084 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1085 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1086 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1087 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1088 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1089 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1090 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1091 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1092 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1093 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1094 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1095 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1096 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1097 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1098 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1099 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1100 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1101 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1102 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1103 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1104 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1105 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1106 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1107 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1108 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1109 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1110 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1111 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1112 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1113 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1114 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1115 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1116 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1117 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1118 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1119 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1120 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1121 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1122 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1123 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1124 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1125 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1126 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1127 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1128 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1129 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1130 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1131 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1132 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1133 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1134 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1135 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1136 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1137 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1138 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1139 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1140 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1141 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1142 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1143 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1144 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1145 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1146 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1147 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1148 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1149 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1150 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1151 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1152 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1153 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1154 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1155
1156 /* vector float vec_ldl (int, vector float *);
1157 vector float vec_ldl (int, float *); */
1158 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1159 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1160 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1161 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1162
1163 /* vector bool int vec_ldl (int, vector bool int *);
1164 vector bool int vec_ldl (int, bool int *);
1165 vector int vec_ldl (int, vector int *);
1166 vector int vec_ldl (int, int *);
1167 vector unsigned int vec_ldl (int, vector unsigned int *);
1168 vector unsigned int vec_ldl (int, unsigned int *); */
1169 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1170 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1171 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1172 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 },
1173 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1174 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1175 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1176 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1177 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1178 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1179 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1180 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1181
1182 /* vector bool short vec_ldl (int, vector bool short *);
1183 vector bool short vec_ldl (int, bool short *);
1184 vector pixel vec_ldl (int, vector pixel *);
1185 vector short vec_ldl (int, vector short *);
1186 vector short vec_ldl (int, short *);
1187 vector unsigned short vec_ldl (int, vector unsigned short *);
1188 vector unsigned short vec_ldl (int, unsigned short *); */
1189 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1190 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1191 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1192 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 },
1193 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1194 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1195 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1196 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1197 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1198 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1199 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1200 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1201 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1202 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1203
1204 /* vector bool char vec_ldl (int, vector bool char *);
1205 vector bool char vec_ldl (int, bool char *);
1206 vector char vec_ldl (int, vector char *);
1207 vector char vec_ldl (int, char *);
1208 vector unsigned char vec_ldl (int, vector unsigned char *);
1209 vector unsigned char vec_ldl (int, unsigned char *); */
1210 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1211 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1212 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1213 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 },
1214 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1215 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1216 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1217 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1218 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1219 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1220 ~RS6000_BTI_unsigned_V16QI, 0 },
1221 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1222 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1223
1224 /* vector double vec_ldl (int, vector double *);
1225 vector double vec_ldl (int, double *); */
1226 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1227 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1228 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1229 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1230
1231 /* vector long long vec_ldl (int, vector long long *);
1232 vector long long vec_ldl (int, long long *);
1233 vector unsigned long long vec_ldl (int, vector unsigned long long *);
1234 vector unsigned long long vec_ldl (int, unsigned long long *);
1235 vector bool long long vec_ldl (int, vector bool long long *);
1236 vector bool long long vec_ldl (int, bool long long *); */
1237 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1238 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1239 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1240 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1241 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1242 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1243 ~RS6000_BTI_unsigned_V2DI, 0 },
1244 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1245 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1246 ~RS6000_BTI_unsigned_long_long, 0 },
1247 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1248 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1249 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1250 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 },
1251
1252 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1253 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1254 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1255 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1256 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1257 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1258 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1259 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1260 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1261 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1262 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1263 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1264 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1265 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1266 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1267 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1268 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1269 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1270 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1271 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1272 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1273 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1274 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1275 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1276 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1277 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1278 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1279 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1280 ~RS6000_BTI_unsigned_long_long, 0 },
1281 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1282 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1283 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1284 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1285 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1286 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1287 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1288 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1289 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1290 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1291 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1292 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1293 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1294 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1295 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1296 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1297 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1298 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1299 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1300 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1301 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1302 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1303 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1304 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1305 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1306 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1307 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1308 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1309 ~RS6000_BTI_unsigned_long_long, 0 },
1310 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1311 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1312 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1313 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1314 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1315 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1316 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1317 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1318 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1319 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1320 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1321 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1322 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1323 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1324 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1325 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1326 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1327 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1328 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1329 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1330 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1331 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1332 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1333 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1334 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1335 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1336 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1337 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1338 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1339 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1340 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1341 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1342 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1343 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1344 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1345 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1346 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1347 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1348 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1349 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1350 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1351 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1352 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1353 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1354 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1355 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1356 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1357 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1358 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1359 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1360 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1361 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1362 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1363 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1364 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1365 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1366 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1367 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1368 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1369 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1370 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1371 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1372 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1373 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1374 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1375 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1376 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1377 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1378 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1379 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1380 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1381 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1382 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1383 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1384 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1385 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1386 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1387 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1388 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1389 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1390 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1391 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1392 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1393 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1394 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1395 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1396 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1397 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1398 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1399 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1400 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1401 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1402 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1403 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1404 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1405 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1406 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1407 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1408 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1409 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1410 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1411 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1412 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1413 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1414 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1415 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1416 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1417 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1418 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1419 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1420 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1421 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1422 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1423 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1424 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1425 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1426 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1427 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1428 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1429 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1430 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1431 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1432 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1433 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1434 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1435 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1436 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1437 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1438 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1439 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1440 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1441 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1442 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1443 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1444 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1445 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1446 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1447 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1448 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1449 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1450 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1451 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1452 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1453 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1454 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1455 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1456 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1457 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1458 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1459 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1460 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1461 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1462 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1463 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1464 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1465 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1466 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1467 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1468 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1469 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1470 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1471 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1472 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1473 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1474 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1475 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1476 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1477 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1478 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1479 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1480 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1481 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1482 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1483 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1484 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1485 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1486 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1487 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1488 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1489 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1490 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1491 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1492 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1493 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1494 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1495 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1496 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1497 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1498 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1499 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1500 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1501 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1502 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
1503 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1504 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
1505 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1506 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
1507 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1508 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1509 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1510 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1511 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1512 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1513 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1514 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1515 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1516 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1517 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1518 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1519 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1520 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1521 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1522 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1523 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1524 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1525 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1526 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1527 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1528 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1529 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1530 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1531 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1532 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1533 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1534 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1535 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1536 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1537 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1538 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1539 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1540 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1541 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1542 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1543 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1544 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1545 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1546 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1547 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1548 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1549 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1550 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1551 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1552 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1553 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1554 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1555 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1556 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1557 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1558 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1559 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1560 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1561 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1562 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1563 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1564 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1565 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1566 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1567 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1568 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1569 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1570 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1571 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1572 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1573 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1574 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1575 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1576 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1577 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1578 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
1579 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1580 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1581 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1582 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1583 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1584 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1585 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1586 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1587 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1588 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1589 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1590 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1591 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1592 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1593 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1594 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1595 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1596 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1597 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1598 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1599 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1600 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1601 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1602 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1603 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1604 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1605 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1606 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1607 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1608 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1609 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1610 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1611 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1612 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1613 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1614 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1615 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1616 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1617 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1618 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1619 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1620 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1621 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1622 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1623 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1624 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1625 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1626 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1627 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1628 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1629 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1630 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1631 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1632 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1633 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1634 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1635 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1636 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1637 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1638 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
1639 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1640 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1641 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1642 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1643 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1644 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1645 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1646 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1647 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1648 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1649 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1650 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1651 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1652 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1653 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1654 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1655 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1656 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1657 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1658 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1659 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1660 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1661 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1662 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1663 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1664 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1665 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1666 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1667 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1668 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1669 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1670 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1671 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1672 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1673 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1674 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1675 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1676 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1677 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1678 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1679 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1680 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1681 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1682 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1683 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1684 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1685 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1686 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1687 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1688 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1689 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1690 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1691 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1692 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1693 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1694 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1695 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1696 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1697 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1698 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1699 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1700 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1701 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1702 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1703 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1704 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1705 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1706 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1707 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1708 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1709 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1710 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1711 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1712 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1713 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1714 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1715 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1716 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1717 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1718 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1719 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1720 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1721 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1722 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1723 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1724 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
1725 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1726 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
1727 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1728 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
1729 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1730 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1731 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1732 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1733 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1734 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1735 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1736 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1737 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1738 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1739 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1740 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1741 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1742 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1743 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1744 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1745 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1746 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1747 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1748 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1749 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1750 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1751 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1752 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1753 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1754 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1755 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1756 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1757 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1758 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1759 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1760 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1761 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1762 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1763 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1764 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1765 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1766 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1767 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1768 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1769 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1770 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1771 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1772 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1773 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1774 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1775 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1776 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1777 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1778 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
1779 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1780 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
1781 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1782 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
1783 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1784 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
1785 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1786 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
1787 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1788 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
1789 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
1790 RS6000_BTI_unsigned_V4SI, 0 },
1791 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
1792 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1793 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
1794 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1795 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
1796 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1797 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
1798 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1799 { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
1800 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1801 { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
1802 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1803 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
1804 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1805 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
1806 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1807 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
1808 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1809 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW,
1810 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1811 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
1812 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
1813 RS6000_BTI_unsigned_V4SI, 0 },
1814 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
1815 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1816 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
1817 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1818 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
1819 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1820 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
1821 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1822 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
1823 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1824 { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW,
1825 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1826 { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW,
1827 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1828
1829 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
1830 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
1831 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
1832 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
1833 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
1834 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
1835 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
1836 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
1837 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
1838 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
1839 { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
1840 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
1841 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
1842 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
1843 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
1844 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
1845
4559be23 1846 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SF,
25ffd3d3 1847 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 1848 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DF,
25ffd3d3 1849 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 1850 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
25ffd3d3 1851 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1852 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
25ffd3d3 1853 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1854 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
25ffd3d3 1855 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1856 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1857 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1858 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1859 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1860 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1861 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1862 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1863 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1864 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI,
25ffd3d3 1865 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 1866 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
25ffd3d3 1867 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 1868 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
25ffd3d3 1869 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 1870 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI,
25ffd3d3 1871 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 1872 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
25ffd3d3 1873 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 1874 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
25ffd3d3 1875 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 1876 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI,
25ffd3d3 1877 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 1878 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
25ffd3d3 1879 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 1880 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
25ffd3d3 1881 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23
PB		 1882
1883 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
25ffd3d3 1884 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 1885 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
25ffd3d3 1886 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 1887 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
25ffd3d3 1888 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 1889 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
25ffd3d3 1890 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 1891 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
25ffd3d3 1892 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 1893 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
25ffd3d3 1894 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 1895 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
25ffd3d3 1896 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1897 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
25ffd3d3 1898 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1899 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
25ffd3d3 1900 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1901 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 1902 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1903 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 1904 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1905 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 1906 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1907 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 1908 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1909 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 1910 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 1911 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
25ffd3d3 1912 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 1913 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
25ffd3d3 1914 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 1915 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
25ffd3d3 1916 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 1917 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 1918 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 1919 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 1920 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 1921 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 1922 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 1923 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 1924 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 1925 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
25ffd3d3 1926 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 1927 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
25ffd3d3 1928 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 1929 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
25ffd3d3 1930 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 1931 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 1932 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 1933 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 1934 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 1935 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 1936 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 1937 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
25ffd3d3 1938 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 1939 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 1940 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 1941 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
25ffd3d3 1942 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 1943 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
25ffd3d3 1944 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 1945 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 1946 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 1947 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 1948 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 1949 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 1950 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 1951
25ffd3d3
PB		 1952 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
1953 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1954 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
1955 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1956 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
1957 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1958 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
1959 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1960 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
1961 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1962 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
1963 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1964 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
1965 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1966 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
1967 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1968 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
1969 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1970 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF,
1971 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1972
1973 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI,
1974 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
1975 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI,
1976 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
1977 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI,
1978 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
1979 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI,
1980 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
1981 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF,
1982 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
1983 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF,
1984 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
1985
1986 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
1987 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
58b475a2
WS		 1988 { P9V_BUILTIN_VEC_CONVERT_4F32_8F16, P9V_BUILTIN_CONVERT_4F32_8F16,
1989 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
25ffd3d3
PB		 1990
1991 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
1992 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1993 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
1994 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1995 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
1996 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1997 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
1998 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1999 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2000 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2001 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2002 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2003 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2004 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2005 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2006 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2007 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2008 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2009 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2010 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2011 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2012 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2013 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2014 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2015 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2016 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2017 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2018 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2019 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2020 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2021 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2022 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2023 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2024 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2025 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2026 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2027
2028 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2029 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI,
2030 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2031 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2032 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI,
2033 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2034 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2035 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2036 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2037 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2038 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2039 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2040 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2041 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2042 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2043 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2044 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2045 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2046
2047 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2048 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2049 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2050 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2051 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2052 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2053 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2054 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2055 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2056 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2057 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2058 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2059 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2060 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2061 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2062 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2063 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2064 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2065 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2066 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2067 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2068 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2069 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2070 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2071 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2072 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2073 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2074 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2075 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2076 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2077 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2078 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2079 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2080 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2081 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2082 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2083 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2084 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2085 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2086 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2087 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2088 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2089 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2090 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2091 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS,
2092 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2093 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2094 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2095 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2096 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2097 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2098 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2099 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2100 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2101 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2102 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2103 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2104 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2105 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2106 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2107 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2108 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2109 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2110 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2111 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2112 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2113 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2114 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2115 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2116 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2117 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2118 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2119 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2120 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2121 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2122 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2123 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2124 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2125 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2126 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2127 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2128 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2129 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2130 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2131 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2132 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2133 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2134 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2135 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2136 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2137 RS6000_BTI_unsigned_V4SI, 0 },
2138 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2139 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2140 RS6000_BTI_unsigned_V2DI, 0 },
2141 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2142 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2143 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2144 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2145 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2146 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2147 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2148 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2149 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2150 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2151 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2152 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2153 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2154 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2155 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2156 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2157 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2158 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2159 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2160 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2161 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2162 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2163 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2164 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2165 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2166 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2167 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2168 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2169 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2170 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2171 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2172 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2173 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2174 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2175 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2176 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2177 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2178 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2179 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2180 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2181 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2182 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2183 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2184 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2185 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2186 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2187 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2188 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2189 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2190 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2191 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2192 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2193 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2194 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2195 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2196 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2197 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2198 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2199 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2200 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2201 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2202 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2203 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2204 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2205 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2206 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2207 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2208 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2209 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2210 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2211 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2212 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2213 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2214 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2215 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2216 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2217 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2218 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2219 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2220 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2221 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2222 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2223 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2224 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2225 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2226 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2227 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2228 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2229 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2230 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2231 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2232 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2233
2234 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2235 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2236 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2237 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2238 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2239 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2240 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2241 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2242 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2243 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 },
2244
2245 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2246 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2247 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2248 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2249 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2250 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2251 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2252 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2253 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2254 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2255 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2256 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2257 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2258 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2259 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2260 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2261 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2262 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2263 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2264 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2265 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2266 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2267 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2268 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2269 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2270 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2271 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2272 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2273 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2274 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2275 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2276 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2277 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2278 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2279 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2280 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2281 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2282 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2283 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2284 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2285 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2286 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2287 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2288 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2289 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2290 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2291 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2292 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2293 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2294 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2295 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2296 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2297 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2298 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2299 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2300 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2301 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2302 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2303 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2304 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2305 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2306 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2307 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2308 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2309 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2310 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2311 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2312 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2313 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2314 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2315 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2316 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2317 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2318 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2319 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2320 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2321 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2322 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2323 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2324 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2325 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2326 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2327 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2328 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2329 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2330 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2331 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2332 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2333 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2334 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2335 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2336 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2337 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2338 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2339 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2340 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2341 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2342 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2343 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2344 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2345 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2346 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2347 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2348 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2349 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2350 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2351 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2352 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2353 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2354 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2355 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2356 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2357 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2358 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2359 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2360 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2361 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2362 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2363 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2364 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2365 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2366 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2367 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2368 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2369 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2370 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2371 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2372 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2373 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2374 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2375 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2376 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2377 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2378 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2379 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2380 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2381 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2382 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2383 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2384 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2385 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2386 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2387 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2388 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2389 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2390 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2391 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2392 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2393 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2394 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2395 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2396 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2397 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2398 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2399 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2400 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2401 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2402 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2403 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2404 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2405 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2406 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2407 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2408 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2409 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2410 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2411 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2412 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2413 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2414 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2415 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2416 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2417 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2418 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2419 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2420 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2421 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2422 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2423 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2424 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2425 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2426 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2427 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2428 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2429 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2430 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2431 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2432 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2433 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2434 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2435 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2436 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2437 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2438 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2439 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2440 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2441 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2442 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2443 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2444 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2445 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2446 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2447 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2448 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2449 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2450 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2451 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2452 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2453 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2454 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2455 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2456 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2457 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2458 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2459 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2460 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2461 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2462 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2463 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2464 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2465 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2466 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2467 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2468 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2469 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2470 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2471 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2472 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2473 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2474 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2475 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2476 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2477 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2478 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2479 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2480 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2481 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2482 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2483 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2484 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2485 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2486 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2487 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2488 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2489 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2490 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2491 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2492 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2493 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2494 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2495 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2496 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2497
2498 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2499 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2500 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2501 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2502 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2503 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2504 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2505 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2506 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2507 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2508 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2509 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2510 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2511 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2512 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2513 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2514 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2515 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2516 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2517 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2518 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2519 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2520 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2521 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2522 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2523 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2524 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2525 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2526 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2527 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2528 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2529 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2530 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2531 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2532 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2533 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2534 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2535 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2536 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2537 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2538 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2539 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2540 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2541 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2542 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2543 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2544 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2545 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2546 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
2547 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2548 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
2549 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2550 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2551 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2552 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2553 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2554 RS6000_BTI_unsigned_V1TI, 0 },
2555 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
2556 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2557 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2558 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2559 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2560 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2561 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2562 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2563 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2564 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2565 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2566 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2567 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2568 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2569 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2570 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2571 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2572 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2573 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2574 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2575 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2576 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2577 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2578 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2579 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2580 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2581 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2582 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2583 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2584 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2585 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2586 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2587 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2588 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2589 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2590 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2591 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2592 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2593 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2594 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2595 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2596 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2597 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2598 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2599 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2600 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2601 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2602 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2603 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2604 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2605
2606 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2607 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2608 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2609 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2610 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2611 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2612 RS6000_BTI_unsigned_V1TI, 0 },
2613 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2614 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2615
2616 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2617 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2618 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2619 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2620 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2621 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2622 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2623 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2624 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2625 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2626 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2627 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2628 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2629 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2630 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2631 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2632 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2633 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2634 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2635 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2636 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2637 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2638 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2639 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2640 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2641 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2642 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2643 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2644 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2645 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2646 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2647 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2648 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2649 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2650 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2651 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2652 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2653 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2654 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2655 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2656 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2657 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2658 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2659 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2660 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2661 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2662 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2663 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2664 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2665 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2666 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2667 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2668 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2669 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2670 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2671 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2672 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2673 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2674 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2675 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2676 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2677 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2678 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2679 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2680 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2681 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2682 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2683 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2684 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2685 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2686 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2687 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2688 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2689 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2690 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2691 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2692 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2693 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2694 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2695 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2696 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2697 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2698 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2699 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2700 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
2701 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2702 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
2703 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2704 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
2705 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2706 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
2707 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2708 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
2709 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2710 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
2711 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2712 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
2713 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2714 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
2715 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2716
2717 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
2718 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
2719 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
2720 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
2721 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2722 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
2723 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2724 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
2725 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2726 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
2727 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2728 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
2729 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2730 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
2731 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2732 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
2733 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2734 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2735 ~RS6000_BTI_unsigned_V2DI, 0 },
2736 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2737 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2738 ~RS6000_BTI_unsigned_long_long, 0 },
2739 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2740 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
2741
2742 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
2743 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
2744 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
2745 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
2746 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2747 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
2748 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2749 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
2750 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2751 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
2752 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2753 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
2754 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2755 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
2756 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2757 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
2758 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2759 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
2760 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2761 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
2762 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2763 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
2764 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2765 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
2766 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2767 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
2768 ~RS6000_BTI_unsigned_V16QI, 0 },
2769 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2770 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
2771
2772 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
2773 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
2774 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
2775 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
2776 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
2777 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
2778 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
2779 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
2780 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2781 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
2782 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2783 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
2784 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2785 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2786 ~RS6000_BTI_unsigned_V2DI, 0 },
2787 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2788 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2789 ~RS6000_BTI_unsigned_long_long, 0 },
2790 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
2791 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
2792 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
2793 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
2794 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2795 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
2796 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2797 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
2798 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2799 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
2800 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2801 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
2802 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2803 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
2804 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2805 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
2806 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2807 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
2808 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2809 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
2810 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2811 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
2812 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2813 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
2814 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2815 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
2816 ~RS6000_BTI_unsigned_V16QI, 0 },
2817 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2818 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4559be23
PB		 2819
2820 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF,
25ffd3d3 2821 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 2822 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2823 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 2824 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF,
25ffd3d3 2825 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 2826 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF,
25ffd3d3 2827 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 2828 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2829 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 2830 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF,
25ffd3d3 2831 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 2832 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2833 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 2834 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2835 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2836 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2837 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 2838 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2839 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 2840 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2841 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2842 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2843 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 2844 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2845 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2846 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2847 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2848 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2849 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 2850 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2851 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2852 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2853 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 2854 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2855 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 2856 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2857 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2858 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2859 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 2860 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 2861 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2862 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
25ffd3d3 2863 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 2864 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
25ffd3d3 2865 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2866 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
25ffd3d3 2867 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 2868 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 2869 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 2870 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 2871 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2872 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 2873 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23
PB		 2874
2875 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
25ffd3d3 2876 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23
PB		 2877 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
2878 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2879 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
25ffd3d3 2880 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23
PB		 2881 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
2882 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2883 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
2884 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2885 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
2886 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2887 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
2888 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2889 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
25ffd3d3 2890 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 2891 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
25ffd3d3
PB		 2892 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2893
2894 /* Ternary AltiVec/VSX builtins. */
2895 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2896 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2897 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2898 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2899 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2900 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2901 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2902 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2903 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2904 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2905 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2906 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2907 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2908 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2909 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2910 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2911 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2912 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2913 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2914 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2915 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2916 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2917 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2918 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2919 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2920 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2921 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2922 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2923 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2924 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2925 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2926 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2927 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2928 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2929 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2930 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2931 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2932 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2933 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2934 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2935 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2936 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2937 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2938 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2939 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2940 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2941 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2942 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2943 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2944 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2945 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2946 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2947 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2948 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2949 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2950 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2951 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2952 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2953 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2954 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2955 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2956 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2957 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2958 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2959 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2960 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2961 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2962 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2963 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2964 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2965 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2966 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2967 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2968 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2969 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2970 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2971 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2972 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2973 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2974 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2975 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2976 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2977 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2978 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2979 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2980 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2981 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2982 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2983 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2984 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2985 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2986 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2987 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2988 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2989 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2990 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2991 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2992 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2993 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2994 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2995 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2996 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2997 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2998 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2999 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3000 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3001 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3002 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3003 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3004 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3005 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3006 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3007 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3008 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3009 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3010 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3011 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3012 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3013 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3014 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3015 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3016 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3017 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3018 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3019 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3020 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3021 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3022 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3023 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3024 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3025 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3026 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3027 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3028 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3029 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3030 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3031 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3032 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3033 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3034 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3035 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3036 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3037 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3038 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3039 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3040 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3041 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3042 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3043 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3044 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3045 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3046 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3047 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3048 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3049 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3050 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3051 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3052 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3053 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3054 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3055 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3056 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3057 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3058 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3059 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3060 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3061 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3062 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3063 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3064 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3065 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3066 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3067 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3068 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3069 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3070 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3071 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3072 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3073 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3074 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3075 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3076 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3077 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3078 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3079 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3080 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3081 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3082 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3083 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3084 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3085 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3086 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3087 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3088 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3089 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3090 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3091 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3092 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3093 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3094 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3095 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3096 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3097 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3098 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3099 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3100 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3101 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3102 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3103 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3104 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3105 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3106 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3107 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3108 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3109 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3110 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3111 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3112 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3113 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3114 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3115 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3116 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3117 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3118 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3119 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3120 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3121 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3122 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3123 RS6000_BTI_unsigned_V16QI },
3124 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3125 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3126 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3127 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3128 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3129 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3130 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3131 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3132 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3133 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3134 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3135 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3136 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3137 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3138 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3139 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3140 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3141 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3142 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3143 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3144 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3145 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3146 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3147 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3148 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3149 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3150
3151 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3152 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
3153 RS6000_BTI_bool_V16QI },
3154 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3155 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3156 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3157 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3158 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3159
3160 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3161 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3162 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3163 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3164 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3165 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3166 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3167 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3168 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3169 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3170 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3171 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3172 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3173 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3174 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3175 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3176 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3177 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3178 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3179 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3180 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3181 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3182 RS6000_BTI_bool_V2DI },
3183 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3184 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3185 RS6000_BTI_unsigned_V2DI },
3186 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3187 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3188 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3189 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3190 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3191 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3192 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3193 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3194 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3195 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3196 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3197 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3198 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3199 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3200 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3201 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3202 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3203 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3204 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3205 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3206 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3207 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3208 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3209 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3210 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3211 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3212 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3213 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3214 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3215 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3216 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3217 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3218 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3219 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3220 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3221 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3222 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3223 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3224 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3225 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3226 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3227 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3228 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3229 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3230 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3231 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3232 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3233 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3234 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3235 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI },
3236 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3237 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3238 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3239 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3240 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3241 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3242 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3243 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI },
3244 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3245 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI },
3246 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3247 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3248 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3249 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3250 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3251 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI },
3252 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3253 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3254 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3255 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI },
3256 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3257 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3258 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3259 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3260
3261 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3262 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3263 RS6000_BTI_INTSI },
3264 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3265 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3266 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3267 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3268 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3269 RS6000_BTI_INTSI },
3270 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3271 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3272 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3273 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3274 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3275 RS6000_BTI_INTSI },
3276 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3277 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3278 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3279 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3280 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3281 RS6000_BTI_INTSI },
3282 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3283 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3284 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3285
3286 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3287 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3288 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3289 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3290 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3291 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3292 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3293 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
3294 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3295 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3296 ~RS6000_BTI_unsigned_V2DI },
3297 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3298 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3299 ~RS6000_BTI_unsigned_long_long },
3300 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3301 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3302 ~RS6000_BTI_bool_V2DI },
3303 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3304 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3305 ~RS6000_BTI_long_long },
3306 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3307 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3308 ~RS6000_BTI_unsigned_long_long },
3309 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3310 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3311 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3312 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3313 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3314 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3315 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3316 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3317 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3318 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3319 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3320 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3321 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3322 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3323 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3324 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3325 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3326 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3327 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3328 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3329 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3330 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3331 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3332 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3333 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3334 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3335 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3336 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3337 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3338 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3339 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3340 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3341 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3342 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3343 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3344 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3345 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3346 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3347 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3348 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3349 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3350 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3351 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3352 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3353 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3354 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3355 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3356 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3357 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3358 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3359 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3360 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3361 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3362 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3363 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3364 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3365 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3366 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3367 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3368 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3369 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3370 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3371 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3372 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3373 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3374 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3375 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3376 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3377 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3378 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3379 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3380 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3381 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3382 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3383 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3384 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3385 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3386 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3387 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3388 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3389 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3390 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3391 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3392 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3393 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3394 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3395 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3396 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3397 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3398 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3399 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3400 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3401 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3402 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3403 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3404 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3405 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3406 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3407 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3408 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3409 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3410 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3411 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3412 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3413 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3414 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3415 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3416 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3417 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3418 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3419 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3420 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3421 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3422 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3423 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3424 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3425 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3426 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3427 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3428 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3429 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3430 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3431 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3432 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3433 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3434 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3435 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3436 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3437 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3438 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3439 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3440 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3441 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3442 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3443 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3444 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3445 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3446 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3447 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3448 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3449 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3450 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3451 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3452 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3453 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3454 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3455 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3456 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3457 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3458 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3459 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3460 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3461 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3462 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3463 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3464 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3465 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3466 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3467 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3468 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3469 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3470 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3471 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3472 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3473 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3474 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3475 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3476 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3477 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3478 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3479 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3480 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3481 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3482 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3483 ~RS6000_BTI_unsigned_V2DI },
3484 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3485 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3486 ~RS6000_BTI_bool_V2DI },
3487 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3488 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3489 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3490 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3491 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3492 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3493 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3494 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3495 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3496 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3497 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3498 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3499 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3500 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3501 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3502 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3503 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3504 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3505 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3506 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3507 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3508 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3509 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3510 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3511 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3512 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3513 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3514 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3515 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3516 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3517 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3518 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3519 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3520 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3521 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3522 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3523 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3524 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3525 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3526 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3527 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3528 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3529 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3530 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3531 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3532 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3533 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3534 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3535 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3536 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3537 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3538 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3539 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3540 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3541 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3542 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3543 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3544 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3545 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3546 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3547 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3548 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3549 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3550 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3551 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3552 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3553 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3554 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3555 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3556 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3557 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3558 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3559 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3560 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3561 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3562 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3563 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3564 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3565 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3566 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3567 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3568 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3569 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3570 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3571 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3572 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3573 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3574 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3575 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3576 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3577 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3578 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3579 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3580 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3581 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3582 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3583 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3584 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3585 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3586 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3587 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3588 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3589 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3590 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3591 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3592 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3593 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3594 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3595 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3596 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3597 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3598 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3599 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3600 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3601 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3602 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3603 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3604 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3605 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3606 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3607 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3608 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3609 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3610 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3611 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3612 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3613 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3614 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3615 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3616 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3617 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3618 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3619 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3620 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3621 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3622 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3623 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3624 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3625 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3626 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3627 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3628 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3629 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3630 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3631 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3632 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3633 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3634 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3635 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3636 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3637 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3638 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
3639 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void,
3640 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long },
3641 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3642 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3643 ~RS6000_BTI_unsigned_V2DI },
3644 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3645 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3646 ~RS6000_BTI_bool_V2DI },
3647 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
3648 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3649 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
3650 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3651 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3652 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3653 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3654 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3655 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3656 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3657 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3658 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3659 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3660 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3661 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3662 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3663 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3664 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3665 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3666 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3667 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3668 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3669 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3670 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3671 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3672 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3673 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3674 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3675 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3676 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3677 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3678 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3679 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3680 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3681 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3682 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3683 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3684 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3685 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3686 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3687 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3688 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3689 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3690 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3691 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3692 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3693 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3694 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3695 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
3696 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3697 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
3698 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3699 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
3700 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI },
3701 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
3702 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI },
3703 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3704 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3705 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3706 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
3707 ~RS6000_BTI_long_long },
3708 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3709 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3710 ~RS6000_BTI_unsigned_V2DI },
3711 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3712 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3713 ~RS6000_BTI_unsigned_long_long },
3714 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3715 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3716 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3717 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3718 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3719 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3720 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3721 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3722 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3723 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3724 ~RS6000_BTI_unsigned_V4SI },
3725 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3726 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3727 ~RS6000_BTI_UINTSI },
3728 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3729 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3730 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3731 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3732 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3733 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3734 ~RS6000_BTI_unsigned_V8HI },
3735 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3736 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3737 ~RS6000_BTI_UINTHI },
3738 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3739 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3740 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3741 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3742 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3743 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3744 ~RS6000_BTI_unsigned_V16QI },
3745 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3746 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3747 ~RS6000_BTI_UINTQI },
3748 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3749 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3750 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3751 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3752 RS6000_BTI_INTSI },
3753 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3754 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3755 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3756 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3757 RS6000_BTI_INTSI },
3758 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3759 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3760 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3761 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3762 RS6000_BTI_INTSI },
3763 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3764 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3765 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3766 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3767 RS6000_BTI_INTSI },
3768 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
3769 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3770 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
3771 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3772
3773 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
3774 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3775 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3776 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3777 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3778 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3779 RS6000_BTI_INTSI },
3780 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
3781 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3782 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3783 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3784 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3785 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3786 RS6000_BTI_INTSI },
3787 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3788 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3789 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3790 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3791 RS6000_BTI_INTSI },
3792 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3793 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3794 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3795 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3796 RS6000_BTI_INTSI },
3797
3798 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3799 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3800 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3801 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3802 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3803 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3804 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3805 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3806 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3807 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3808 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3809 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3810 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3811 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3812 ~RS6000_BTI_unsigned_V2DI, 0 },
3813 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3814 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
3815 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3816 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
3817 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3818 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3819 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3820 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3821 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3822 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
3823 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3824 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3825 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3826 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3827 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3828 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
3829 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3830 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3831 ~RS6000_BTI_unsigned_V4SI, 0 },
3832 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3833 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3834 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3835 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3836 ~RS6000_BTI_unsigned_long, 0 },
3837 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3838 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
3839 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3840 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
3841 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3842 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3843 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3844 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3845 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3846 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3847 ~RS6000_BTI_unsigned_V8HI, 0 },
3848 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3849 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3850 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3851 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
3852 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3853 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3854 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3855 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3856 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3857 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3858 ~RS6000_BTI_unsigned_V16QI, 0 },
3859 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3860 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3861
3862 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
3863 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3864 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
3865 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3866 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3867 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI,
3868 ~RS6000_BTI_long_long },
3869 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3870 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI,
3871 ~RS6000_BTI_unsigned_long_long },
3872 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
3873 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI },
3874 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
3875 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI },
3876 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3877 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3878 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3879 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3880 ~RS6000_BTI_unsigned_V2DI },
3881 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3882 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3883 ~RS6000_BTI_bool_V2DI },
3884 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3885 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3886 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3887 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3888 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3889 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3890 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3891 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3892 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3893 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3894 ~RS6000_BTI_unsigned_V4SI },
3895 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3896 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3897 ~RS6000_BTI_UINTSI },
3898 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3899 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3900 ~RS6000_BTI_bool_V4SI },
3901 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3902 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3903 ~RS6000_BTI_UINTSI },
3904 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3905 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3906 ~RS6000_BTI_INTSI },
3907 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3908 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3909 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3910 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3911 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3912 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3913 ~RS6000_BTI_unsigned_V8HI },
3914 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3915 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3916 ~RS6000_BTI_UINTHI },
3917 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3918 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3919 ~RS6000_BTI_bool_V8HI },
3920 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3921 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3922 ~RS6000_BTI_UINTHI },
3923 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3924 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3925 ~RS6000_BTI_INTHI },
3926 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3927 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3928 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3929 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3930 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3931 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3932 ~RS6000_BTI_unsigned_V16QI },
3933 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3934 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3935 ~RS6000_BTI_UINTQI },
3936 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3937 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3938 ~RS6000_BTI_bool_V16QI },
3939 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3940 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3941 ~RS6000_BTI_UINTQI },
3942 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3943 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3944 ~RS6000_BTI_INTQI },
3945 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3946 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
3947 ~RS6000_BTI_pixel_V8HI },
3948
3949 /* Predicates. */
3950 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
3951 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3952 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
3953 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3954 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
3955 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3956 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
3957 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
3958 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
3959 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3960 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
3961 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3962 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
3963 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3964 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
3965 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3966 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
3967 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3968 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
3969 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3970 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
3971 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
3972 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
3973 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3974 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
3975 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3976 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
3977 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3978 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
3979 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3980 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
3981 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
3982 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
3983 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3984 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
3985 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
3986 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
3987 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
3988 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
3989 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3990 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
3991 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3992 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
3993 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
3994 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
3995 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3996 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
3997 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3998 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
3999 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4000 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
4001 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4002
4003
4004 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4005 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4006 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4007 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4008 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4009 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4010 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4011 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4012 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4013 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4014 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4015 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4016 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4017 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4018 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4019 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4020 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4021 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4022 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4023 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4024 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4025 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4026 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4027 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4028 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4029 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4030 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4031 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4032 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4033 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4034 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4035 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4036 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4037 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4038 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4039 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4040 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4041 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4042 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4043 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4044 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4045 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4046 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4047 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4048 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4049 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4050 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4051 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4052 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4053 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4054 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4055 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4056 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4057 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4058 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4059 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4060 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4061 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4062 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4063 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4064 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4065 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4066
4067
4068 /* cmpge is the same as cmpgt for all cases except floating point.
4069 There is further code to deal with this special case in
4070 altivec_build_resolved_builtin. */
4071 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4072 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4073 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4074 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4075 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4076 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4077 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4078 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4079 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4080 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4081 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4082 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4083 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4084 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4085 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4086 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4087 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4088 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4089 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4090 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4091 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4092 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4093 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4094 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4095 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4096 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4097 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4098 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4099 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4100 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4101 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4102 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4103 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4104 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4105 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4106 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4107 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4108 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4109 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4110 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4111 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4112 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4113 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4114 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4115 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4116 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4117 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4118 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4119 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4120 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4121 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4122 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4123
4124 /* Power8 vector overloaded functions. */
4125 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4126 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4127 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4128 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4129 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4130 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 4131 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3 4132 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 4133 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3
PB		 4134 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4135 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4136 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3
PB		 4137 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4138 RS6000_BTI_bool_V16QI, 0 },
4559be23 4139 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3
PB		 4140 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4141 RS6000_BTI_unsigned_V16QI, 0 },
4142 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4143 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4144 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4145 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4146 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4147 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 4148 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3 4149 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 4150 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3
PB		 4151 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4152 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4153 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3
PB		 4154 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4155 RS6000_BTI_bool_V8HI, 0 },
4559be23 4156 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3
PB		 4157 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4158 RS6000_BTI_unsigned_V8HI, 0 },
4159 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4160 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4161 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4162 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4163 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4164 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 4165 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3 4166 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 4167 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3
PB		 4168 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4169 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4170 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3
PB		 4171 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4172 RS6000_BTI_bool_V4SI, 0 },
4559be23 4173 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3
PB		 4174 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4175 RS6000_BTI_unsigned_V4SI, 0 },
4176 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4177 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4178 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4179 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4180 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4181 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 4182 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3 4183 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 4184 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3
PB		 4185 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4186 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4187 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3
PB		 4188 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4189 RS6000_BTI_bool_V2DI, 0 },
4559be23 4190 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3
PB		 4191 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4192 RS6000_BTI_unsigned_V2DI, 0 },
4193 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4194 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4195 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4196 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4197
4198 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4199 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4200 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4201 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4202 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4203 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 4204 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4205 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4206 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4207 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4208 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4209 RS6000_BTI_bool_V16QI, 0 },
4559be23 4210 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4211 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4212 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4213 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4214 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4215 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4216 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4217 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4218 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4219 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4220 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 4221 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4222 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4223 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4224 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4225 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4226 RS6000_BTI_bool_V8HI, 0 },
4559be23 4227 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4228 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4229 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4230 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4231 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4232 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4233 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4234 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4235 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4236 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4237 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 4238 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4239 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4240 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4241 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4242 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4243 RS6000_BTI_bool_V4SI, 0 },
4559be23 4244 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4245 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4246 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4247 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4248 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4249 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4250 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4251 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4252 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4253 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4254 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 4255 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4256 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4257 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4258 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4259 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4260 RS6000_BTI_bool_V2DI, 0 },
4559be23 4261 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4262 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4263 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4264 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4265 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4266 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4267 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4268 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4269 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4270
4271 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4272 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4273 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4274 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4275 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4276 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 4277 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4278 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4279 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4280 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4281 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4282 RS6000_BTI_bool_V16QI, 0 },
4559be23 4283 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4284 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4285 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4286 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4287 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4288 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4289 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4290 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4291 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4292 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4293 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 4294 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4295 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4296 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4297 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4298 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4299 RS6000_BTI_bool_V8HI, 0 },
4559be23 4300 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4301 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4302 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4303 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4304 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4305 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4306 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4307 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4308 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4309 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4310 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 4311 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4312 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4313 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4314 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4315 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4316 RS6000_BTI_bool_V4SI, 0 },
4559be23 4317 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4318 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4319 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4320 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4321 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4322 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4323 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4324 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4325 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4326 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4327 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 4328 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4329 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4330 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4331 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4332 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4333 RS6000_BTI_bool_V2DI, 0 },
4559be23 4334 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4335 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4336 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4337 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4338 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4339 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4340 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4341 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4342 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4343
4344 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4345 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4346 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4347 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4348 RS6000_BTI_unsigned_V1TI, 0 },
4349
4350 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4351 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4352 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4353 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4354 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4355 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4356 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4357 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4358 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4359 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4360 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4361 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4362
4363 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4364 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4365 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4366 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4367 RS6000_BTI_unsigned_V1TI, 0 },
4368
4369 { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4370 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4371 RS6000_BTI_unsigned_V16QI, 0 },
4372 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4373 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4374 RS6000_BTI_unsigned_V16QI, 0 },
4375 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4376 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4377 RS6000_BTI_unsigned_V16QI, 0 },
4378
4379 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4380 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4381 RS6000_BTI_unsigned_V16QI, 0 },
4382 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4383 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4384 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4385 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4386 RS6000_BTI_unsigned_V16QI, 0 },
4387 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4388 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4389 RS6000_BTI_unsigned_V16QI, 0 },
4390
4391 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4392 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4393 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4394 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4395 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4396 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4397 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4398 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4399 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4400 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4401 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4402 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4403 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4404 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4405 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4406 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4407
4408 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4409 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4410 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4411 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4412
4413 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4414 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4415 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4416 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4417
4418 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4419 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4420 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4421 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4422
4423 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4424 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4425 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4426 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4427
4428 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4429 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4430 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4431 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4432
4433 { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4434 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4435 { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4436 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4437
4438 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4439 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4440 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4441 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4442
4443 { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4444 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4445 { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4446 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4447
4448 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4449 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4450 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4451 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4452
4453 { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4454 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4455 { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4456 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4457
4458 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4459 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4460 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4461 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4462
4463 { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4464 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4465 { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4466 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4467
4468 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4469 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4470 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4471 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4472 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4473 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4474 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4475 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4476 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4477 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4478 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4479 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4480 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4481 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4482 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4483 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4484
4485 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4486 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4487 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4488 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4489
4490 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4491 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4492 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4493 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4494
4495 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4496 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4497 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4498 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4499
4500 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4501 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4502 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4503 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4504
4505 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4506 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4507 RS6000_BTI_unsigned_V16QI, 0 },
4508 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4509 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4510 RS6000_BTI_unsigned_V8HI, 0 },
4511 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4512 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4513 RS6000_BTI_unsigned_V4SI, 0 },
4514
4515 { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4516 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4517 RS6000_BTI_unsigned_V16QI, 0 },
4518
4519 { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4520 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4521 RS6000_BTI_unsigned_V8HI, 0 },
4522
4523 { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
4524 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4525 RS6000_BTI_unsigned_V4SI, 0 },
4526
4527 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
4528 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4529 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
4530 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4531
4532 { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
4533 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4534 { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
4535 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4536
4537 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
4538 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4539 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
4540 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4541
4542 { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
4543 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4544 { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
4545 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4546
4547 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
4548 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4549 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
4550 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4551
4552 { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
4553 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4554 { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
4555 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4556
4557 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4558 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4560 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4561
4562 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4563 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4564 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4565 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4566
4567 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4568 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4569 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4570 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4571
4572 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4573 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4574 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4575 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4576
4577 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
4578 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4579 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
4580 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4581 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP,
4582 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4583
4584 { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
4585 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4586 { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
4587 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4588 { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP,
4589 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4590
4591 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
4592 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4593 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
4594 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4595 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP,
4596 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4597
4598 { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
4599 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4600 { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
4601 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4602 { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP,
4603 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4604
4605 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
4606 RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
4607 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP,
4608 RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 },
4609
4610 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
4611 RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
4612 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP,
4613 RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 },
4614
4615 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
4616 RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
4617 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
4618 RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
4619
4620 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP,
4621 RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 },
4622 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
4623 RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
4624
4625 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT,
4626 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4627 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT,
4628 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4629 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT,
4630 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4631 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT,
4632 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4633 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ,
4634 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4635 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ,
4636 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4637 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO,
4638 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4639 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO,
4640 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4641
4642 { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
4643 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4644 RS6000_BTI_unsigned_long_long, 0 },
4645
4646 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4647 RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4648 RS6000_BTI_unsigned_long_long, 0 },
4649 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4650 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4651 RS6000_BTI_unsigned_long_long, 0 },
4652
4653 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4654 RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4655 RS6000_BTI_unsigned_long_long, 0 },
4656 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4657 RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4658 RS6000_BTI_unsigned_long_long, 0 },
4659
4660 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4661 RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4662 RS6000_BTI_unsigned_long_long, 0 },
4663 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4664 RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4665 RS6000_BTI_unsigned_long_long, 0 },
4666
4667 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4668 RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4669 RS6000_BTI_unsigned_long_long, 0 },
4670 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4671 RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4672 RS6000_BTI_unsigned_long_long, 0 },
4673
4674 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4675 RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4676 RS6000_BTI_unsigned_long_long, 0 },
4677 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4678 RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4679 RS6000_BTI_unsigned_long_long, 0 },
4680
4681 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4682 RS6000_BTI_V2DF, ~RS6000_BTI_double,
4683 RS6000_BTI_unsigned_long_long, 0 },
4684 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4685 RS6000_BTI_V4SF, ~RS6000_BTI_float,
4686 RS6000_BTI_unsigned_long_long, 0 },
4687 /* At an appropriate future time, add support for the
4688 RS6000_BTI_Float16 (exact name to be determined) type here. */
4689
4690 { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,
4691 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,
4692 ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},
4693
4694 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4695 RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4696 RS6000_BTI_unsigned_long_long },
4697 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4698 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4699 RS6000_BTI_unsigned_long_long },
4700
4701 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4702 RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4703 RS6000_BTI_unsigned_long_long },
4704 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4705 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4706 RS6000_BTI_unsigned_long_long },
4707
4708 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4709 RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4710 RS6000_BTI_unsigned_long_long },
4711 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4712 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4713 RS6000_BTI_unsigned_long_long },
4714
4715 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4716 RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4717 RS6000_BTI_unsigned_long_long },
4718 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4719 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4720 RS6000_BTI_unsigned_long_long },
4721
4722 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4723 RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4724 RS6000_BTI_unsigned_long_long },
4725 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4726 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4727 RS6000_BTI_unsigned_long_long },
4728
4729 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4730 RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
4731 RS6000_BTI_unsigned_long_long },
4732 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4733 RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
4734 RS6000_BTI_unsigned_long_long },
4735 /* At an appropriate future time, add support for the
4736 RS6000_BTI_Float16 (exact name to be determined) type here. */
4737
4738 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4739 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
4740 RS6000_BTI_bool_V16QI, 0 },
4741 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4742 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4743 RS6000_BTI_V16QI, 0 },
4744 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4745 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
4746 RS6000_BTI_unsigned_V16QI, 0 },
4747
4748 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4749 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
4750 RS6000_BTI_bool_V8HI, 0 },
4751 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4752 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
4753 RS6000_BTI_V8HI, 0 },
4754 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4755 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
4756 RS6000_BTI_unsigned_V8HI, 0 },
4757
4758 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4759 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
4760 RS6000_BTI_bool_V4SI, 0 },
4761 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4762 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
4763 RS6000_BTI_V4SI, 0 },
4764 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4765 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
4766 RS6000_BTI_unsigned_V4SI, 0 },
4767
4768 /* The following 2 entries have been deprecated. */
4769 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4770 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4771 RS6000_BTI_unsigned_V16QI, 0 },
4772 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4773 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4774 RS6000_BTI_bool_V16QI, 0 },
4775 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4776 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4777 RS6000_BTI_unsigned_V16QI, 0 },
4778
4779 /* The following 2 entries have been deprecated. */
4780 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4781 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4782 RS6000_BTI_V16QI, 0 },
4783 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4784 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4785 RS6000_BTI_bool_V16QI, 0 },
4786 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4787 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4788 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4789 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4790 RS6000_BTI_bool_V16QI, 0 },
4791
4792 /* The following 2 entries have been deprecated. */
4793 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4794 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4795 RS6000_BTI_unsigned_V8HI, 0 },
4796 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4797 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4798 RS6000_BTI_bool_V8HI, 0 },
4799 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4800 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4801 RS6000_BTI_unsigned_V8HI, 0 },
4802 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4803 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4804
4805 /* The following 2 entries have been deprecated. */
4806 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4807 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4808 RS6000_BTI_V8HI, 0 },
4809 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4810 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4811 RS6000_BTI_bool_V8HI, 0 },
4812 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4813 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4814 RS6000_BTI_bool_V8HI, 0 },
4815 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4816 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4817 RS6000_BTI_pixel_V8HI, 0 },
4818
4819 /* The following 2 entries have been deprecated. */
4820 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4821 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4822 RS6000_BTI_unsigned_V4SI, 0 },
4823 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4824 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4825 RS6000_BTI_bool_V4SI, 0 },
4826 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4827 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4828 RS6000_BTI_unsigned_V4SI, 0 },
4829
4830 /* The following 2 entries have been deprecated. */
4831 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4832 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4833 RS6000_BTI_V4SI, 0 },
4834 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4835 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4836 RS6000_BTI_bool_V4SI, 0 },
4837 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4838 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4839 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4840 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4841 RS6000_BTI_bool_V4SI, 0 },
4842
4843 /* The following 2 entries have been deprecated. */
4844 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4845 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4846 RS6000_BTI_unsigned_V2DI, 0 },
4847 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4848 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4849 RS6000_BTI_bool_V2DI, 0 },
4850 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4851 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4852 RS6000_BTI_unsigned_V2DI, 0
4853 },
4854
4855 /* The following 2 entries have been deprecated. */
4856 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4857 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4858 RS6000_BTI_V2DI, 0 },
4859 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4860 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
4861 RS6000_BTI_bool_V2DI, 0 },
4862 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4863 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4864 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4865 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4866 RS6000_BTI_bool_V2DI, 0 },
4867
4868 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
4869 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4870 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
4871 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4872
4873 /* The following 2 entries have been deprecated. */
4874 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4875 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4876 RS6000_BTI_unsigned_V16QI, 0 },
4877 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4878 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4879 RS6000_BTI_bool_V16QI, 0 },
4880 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4881 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4882 RS6000_BTI_unsigned_V16QI, 0 },
4883
4884 /* The following 2 entries have been deprecated. */
4885 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4886 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4887 RS6000_BTI_V16QI, 0 },
4888 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4889 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4890 RS6000_BTI_bool_V16QI, 0 },
4891 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4892 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4893 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4894 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4895 RS6000_BTI_bool_V16QI, 0 },
4896
4897 /* The following 2 entries have been deprecated. */
4898 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4899 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4900 RS6000_BTI_unsigned_V8HI, 0 },
4901 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4902 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4903 RS6000_BTI_bool_V8HI, 0 },
4904 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4905 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4906 RS6000_BTI_unsigned_V8HI, 0 },
4907 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4908 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4909
4910 /* The following 2 entries have been deprecated. */
4911 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4912 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4913 RS6000_BTI_V8HI, 0 },
4914 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4915 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4916 RS6000_BTI_bool_V8HI, 0 },
4917 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4918 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4919 RS6000_BTI_bool_V8HI, 0 },
4920 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4921 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4922 RS6000_BTI_pixel_V8HI, 0 },
4923
4924 /* The following 2 entries have been deprecated. */
4925 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4926 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4927 RS6000_BTI_unsigned_V4SI, 0 },
4928 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4929 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4930 RS6000_BTI_bool_V4SI, 0 },
4931 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4932 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4933 RS6000_BTI_unsigned_V4SI, 0 },
4934
4935 /* The following 2 entries have been deprecated. */
4936 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4937 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4938 RS6000_BTI_V4SI, 0 },
4939 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4940 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4941 RS6000_BTI_bool_V4SI, 0 },
4942 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4943 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4944 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4945 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4946 RS6000_BTI_bool_V4SI, 0 },
4947
4948 /* The following 2 entries have been deprecated. */
4949 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4950 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4951 RS6000_BTI_unsigned_V2DI, 0 },
4952 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4953 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4954 RS6000_BTI_bool_V2DI, 0 },
4955 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4956 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4957 RS6000_BTI_unsigned_V2DI, 0
4958 },
4959
4960 /* The following 2 entries have been deprecated. */
4961 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4962 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4963 RS6000_BTI_V2DI, 0 },
4964 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4965 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
4966 RS6000_BTI_bool_V2DI, 0 },
4967 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4968 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4969 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4970 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4971 RS6000_BTI_bool_V2DI, 0 },
4972
4973 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
4974 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4975 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
4976 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4977
4978 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
4979 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4980 RS6000_BTI_unsigned_V16QI },
4981 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
4982 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4983
4984 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
4985 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4986 RS6000_BTI_unsigned_V8HI },
4987 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
4988 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4989
4990 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
4991 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4992 RS6000_BTI_unsigned_V4SI },
4993 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
4994 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4995
4996 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
4997 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4998 RS6000_BTI_V16QI, 0 },
4999 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5000 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5001 RS6000_BTI_unsigned_V16QI, 0 },
5002
5003 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5004 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5005 RS6000_BTI_V8HI, 0 },
5006 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5007 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5008 RS6000_BTI_unsigned_V8HI, 0 },
5009
5010 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5011 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5012 RS6000_BTI_V4SI, 0 },
5013 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5014 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5015 RS6000_BTI_unsigned_V4SI, 0 },
5016
5017 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5018 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5019 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5020 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5021
5022 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5023 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5024 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5025 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5026 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI,
5027 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5028 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI,
5029 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 },
5030
5031 { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
5032 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
5033
5034 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5035 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5036 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5037 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5038
5039 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5040 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5041 RS6000_BTI_V16QI, 0 },
5042 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5043 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5044 RS6000_BTI_unsigned_V16QI, 0 },
5045
5046 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5047 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5048 RS6000_BTI_V8HI, 0 },
5049 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5050 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5051 RS6000_BTI_unsigned_V8HI, 0 },
5052
5053 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5054 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5055 RS6000_BTI_V4SI, 0 },
5056 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5057 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5058 RS6000_BTI_unsigned_V4SI, 0 },
5059 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5060 RS6000_BTI_float, RS6000_BTI_UINTSI,
5061 RS6000_BTI_V4SF, 0 },
5062
5063 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5064 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5065 RS6000_BTI_V16QI, 0 },
5066 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5067 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5068 RS6000_BTI_unsigned_V16QI, 0 },
5069
5070 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5071 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5072 RS6000_BTI_V8HI, 0 },
5073 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5074 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5075 RS6000_BTI_unsigned_V8HI, 0 },
5076
5077 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5078 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5079 RS6000_BTI_V4SI, 0 },
5080 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5081 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5082 RS6000_BTI_unsigned_V4SI, 0 },
5083 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5084 RS6000_BTI_float, RS6000_BTI_UINTSI,
5085 RS6000_BTI_V4SF, 0 },
5086
5087 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5088 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5089 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5090 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5091
5092 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5093 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI,
5094 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5095 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5096 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5097 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5098
5099 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5100 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5101 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5102 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5103 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5104
5105 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5106 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5107 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5108 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5109 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5110
5111 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5112 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5113 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5114 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5115 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5116
5117 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5118 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5119 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5120 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5121 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5122
5123 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5124 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5125 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5126 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5127 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5128 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5129
5130 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5131 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5132 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5133 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5134 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5135 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5136
5137 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5138 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5139 RS6000_BTI_unsigned_V2DI, 0 },
5140 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5141 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5142 RS6000_BTI_bool_V2DI, 0 },
5143 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5144 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5145 RS6000_BTI_unsigned_V2DI, 0 },
5146
5147 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5148 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5149 RS6000_BTI_unsigned_V2DI, 0 },
5150 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5151 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5152 RS6000_BTI_bool_V2DI, 0 },
5153 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5154 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5155 RS6000_BTI_unsigned_V2DI, 0 },
5156
5157 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5158 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5159 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5160 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5161 RS6000_BTI_unsigned_V2DI, 0 },
5162 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5163 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5164 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF,
5165 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5166 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF,
5167 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5168 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5169 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5170 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5171 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5172 RS6000_BTI_unsigned_V4SI, 0 },
5173 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5174 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5175
5176 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5177 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5178 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5179 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5180 RS6000_BTI_unsigned_V4SI, 0 },
5181 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5182 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5183 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5184 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5185 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5186 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5187 RS6000_BTI_unsigned_V2DI, 0 },
5188 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5189 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5190 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF,
5191 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5192 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF,
5193 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5194
5195 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5196 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5197 RS6000_BTI_unsigned_V16QI, 0 },
5198 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5199 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5200 RS6000_BTI_unsigned_V8HI, 0 },
5201 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5202 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5203 RS6000_BTI_unsigned_V4SI, 0 },
5204 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5205 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5206 RS6000_BTI_unsigned_V2DI, 0 },
5207
5208 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5209 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5210 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5211 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5212 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5213 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5214 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5215 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5216 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5217 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5218 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5219 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5220 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5221 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5222 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5223 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5224
5225 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5226 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5227 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5228 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5229
5230 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5231 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5232 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5233 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5234
5235 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5236 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5237 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5238 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5239
5240 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5241 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5242 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5243 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5244
5245 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5246 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5247 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5248 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5249
5250 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5251 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5252 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5253 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5254
5255 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5256 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5257 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5258 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5259
5260 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5261 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5262 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5263 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5264
5265 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5266 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5267 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5268 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5269 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5270 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5271 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5272 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5273 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5274 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5275 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5276 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5277 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5278 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5279 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5280 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5281
5282 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5283 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5284 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5285 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5286
5287 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5288 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5289 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5290 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5291
5292 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5293 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5294 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5295 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5296 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5297 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5298 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5299 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5300
5301 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5302 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5303 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5304 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5305 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5306 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5307 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5308 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5309 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5310 RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
5311 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5312 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5313
5314 { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5315 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5316 { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5317 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5318 { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5319 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5320
5321 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5322 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5323 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5324 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5325 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5326 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5327
5328 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5329 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5330
5331 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5332 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5333
5334 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5335 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5336
5337 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5338 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5339 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5340 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5341
5342 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5343 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5344 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5345 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5346
5347 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5348 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5349 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5350 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5351
5352 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5353 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5354 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5355 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5356
5357 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5358 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5359 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5360 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5361 RS6000_BTI_unsigned_V1TI, 0 },
5362
5363 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5364 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5365 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5366 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5367 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5368 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5369 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5370 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5371 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5372 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5373 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5374 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5375
5376 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5377 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5378 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5379 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5380 RS6000_BTI_unsigned_V1TI, 0 },
5381
5382 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5383 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5384 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5385 RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5386
5387 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5388 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5389 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5390 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5391
5392 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5393 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5394 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5395 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5396
5397 { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5398 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5399 RS6000_BTI_unsigned_V16QI, 0 },
5400 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5401 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5402 RS6000_BTI_unsigned_V16QI, 0 },
5403
5404 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5405 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5406 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5407 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5408 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5409 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5410 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5411 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5412 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5413 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5414 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5415 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5416 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5417 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5418 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5419 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5420 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5421 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5422 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5423 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5424 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5425 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5426 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5427 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5428 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5429 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5430 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5431 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5432 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF,
5433 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5434 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF,
5435 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5436
5437 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5438 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5439 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5440 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5441 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5442 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5443 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5444 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5445 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5446 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5447 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5448 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5449 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5450 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5451 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5452 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5453 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
5454 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5455 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
5456 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5457 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5458 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5459 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5460 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5461 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5462 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5463 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5464 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5465
5466 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF,
5467 RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 },
5468 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF,
5469 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5470 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5471 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5472 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5473 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5474 { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF,
5475 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5476
5477 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5478 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5479 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5480 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5481 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5482 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5483 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5484 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5485 { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF,
5486 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5487 RS6000_BTI_V2DF, 0 },
5488
5489 /* Crypto builtins. */
5490 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5491 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5492 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5493 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5494 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5495 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5496 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5497 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5498 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5499 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5500 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5501 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5502
5503 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5504 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5505 RS6000_BTI_unsigned_V16QI, 0 },
5506 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5507 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5508 RS6000_BTI_unsigned_V8HI, 0 },
5509 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5510 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5511 RS6000_BTI_unsigned_V4SI, 0 },
5512 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5513 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5514 RS6000_BTI_unsigned_V2DI, 0 },
5515
5516 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5517 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5518 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5519 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5520 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5521 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5522
5d9d0c94
SB		 5523 /* Overloaded built-in functions for ISA3.1 (power10). */
5524 { P10_BUILTIN_VEC_CLRL, P10_BUILTIN_VCLRLB,
25bf7d32 5525 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
5d9d0c94 5526 { P10_BUILTIN_VEC_CLRL, P10_BUILTIN_VCLRLB,
25bf7d32
KN		 5527 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5528 RS6000_BTI_UINTSI, 0 },
5d9d0c94 5529 { P10_BUILTIN_VEC_CLRR, P10_BUILTIN_VCLRRB,
25bf7d32 5530 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
5d9d0c94 5531 { P10_BUILTIN_VEC_CLRR, P10_BUILTIN_VCLRRB,
25bf7d32
KN		 5532 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5533 RS6000_BTI_UINTSI, 0 },
5534
5d9d0c94 5535 { P10_BUILTIN_VEC_GNB, P10_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
7c00c559 5536 RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTQI, 0 },
5d9d0c94 5537 { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V2DI,
b8eaa754 5538 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
5d9d0c94 5539 { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V4SI,
b8eaa754 5540 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
5d9d0c94 5541 { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V8HI,
b8eaa754 5542 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
5d9d0c94 5543 { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V16QI,
b8eaa754
CL		 5544 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5545 RS6000_BTI_INTSI, 0 },
840ac85c
KN		 5546
5547 /* The overloaded XXEVAL definitions are handled specially because the
5548 fourth unsigned char operand is not encoded in this table. */
5d9d0c94 5549 { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
840ac85c
KN		 5550 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5551 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5d9d0c94 5552 { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
840ac85c
KN		 5553 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5554 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5d9d0c94 5555 { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
840ac85c
KN		 5556 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5557 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5d9d0c94 5558 { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
840ac85c
KN		 5559 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5560 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5d9d0c94 5561 { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
840ac85c
KN		 5562 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5563 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5564
5d9d0c94 5565 { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTBL,
c21d2b66
KN		 5566 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
5567 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
5d9d0c94 5568 { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTHL,
c21d2b66
KN		 5569 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
5570 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
5d9d0c94 5571 { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTWL,
c21d2b66
KN		 5572 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5573 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
5d9d0c94 5574 { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTDL,
c21d2b66
KN		 5575 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5576 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
5577
5d9d0c94 5578 { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTBR,
c21d2b66
KN		 5579 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
5580 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
5d9d0c94 5581 { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTHR,
c21d2b66
KN		 5582 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
5583 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
5d9d0c94 5584 { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTWR,
c21d2b66
KN		 5585 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5586 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
5d9d0c94 5587 { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTDR,
c21d2b66
KN		 5588 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5589 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
5590
5d9d0c94 5591 { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIBL,
89ce3290 5592 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5d9d0c94 5593 { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIBL,
89ce3290
KN		 5594 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5595
5d9d0c94 5596 { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIHL,
89ce3290 5597 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5d9d0c94 5598 { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIHL,
89ce3290
KN		 5599 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5600
5d9d0c94 5601 { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIBL_P,
89ce3290 5602 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5d9d0c94 5603 { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIBL_P,
89ce3290
KN		 5604 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5605
5d9d0c94 5606 { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIHL_P,
89ce3290 5607 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5d9d0c94 5608 { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIHL_P,
89ce3290
KN		 5609 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5610
5d9d0c94 5611 { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIBR,
89ce3290 5612 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5d9d0c94 5613 { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIBR,
89ce3290
KN		 5614 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5615
5d9d0c94 5616 { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIHR,
89ce3290 5617 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5d9d0c94 5618 { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIHR,
89ce3290
KN		 5619 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5620
5d9d0c94 5621 { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIBR_P,
89ce3290 5622 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5d9d0c94 5623 { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIBR_P,
89ce3290
KN		 5624 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5625
5d9d0c94 5626 { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P,
89ce3290 5627 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5d9d0c94 5628 { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P,
89ce3290
KN		 5629 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5630
25ffd3d3
PB		 5631 { RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
5632};
1acf0246
BS		 5633\f
5634/* Nonzero if we can use a floating-point register to pass this arg. */
5635#define USE_FP_FOR_ARG_P(CUM,MODE) \
5636 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
5637 && (CUM)->fregno <= FP_ARG_MAX_REG \
5638 && TARGET_HARD_FLOAT)
5639
5640/* Nonzero if we can use an AltiVec register to pass this arg. */
5641#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
5642 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
5643 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5644 && TARGET_ALTIVEC_ABI \
5645 && (NAMED))
5646
5647/* Walk down the type tree of TYPE counting consecutive base elements.
5648 If *MODEP is VOIDmode, then set it to the first valid floating point
5649 or vector type. If a non-floating point or vector type is found, or
5650 if a floating point or vector type that doesn't match a non-VOIDmode
5651 *MODEP is found, then return -1, otherwise return the count in the
5652 sub-tree. */
5653
5654static int
a39ed81b 5655rs6000_aggregate_candidate (const_tree type, machine_mode *modep,
575ac27f 5656 int *empty_base_seen)
1acf0246
BS		 5657{
5658 machine_mode mode;
5659 HOST_WIDE_INT size;
5660
5661 switch (TREE_CODE (type))
5662 {
5663 case REAL_TYPE:
5664 mode = TYPE_MODE (type);
5665 if (!SCALAR_FLOAT_MODE_P (mode))
5666 return -1;
5667
5668 if (*modep == VOIDmode)
5669 *modep = mode;
5670
5671 if (*modep == mode)
5672 return 1;
5673
5674 break;
5675
5676 case COMPLEX_TYPE:
5677 mode = TYPE_MODE (TREE_TYPE (type));
5678 if (!SCALAR_FLOAT_MODE_P (mode))
5679 return -1;
5680
5681 if (*modep == VOIDmode)
5682 *modep = mode;
5683
5684 if (*modep == mode)
5685 return 2;
5686
5687 break;
5688
5689 case VECTOR_TYPE:
5690 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
5691 return -1;
5692
5693 /* Use V4SImode as representative of all 128-bit vector types. */
5694 size = int_size_in_bytes (type);
5695 switch (size)
5696 {
5697 case 16:
5698 mode = V4SImode;
5699 break;
5700 default:
5701 return -1;
5702 }
5703
5704 if (*modep == VOIDmode)
5705 *modep = mode;
5706
5707 /* Vector modes are considered to be opaque: two vectors are
5708 equivalent for the purposes of being homogeneous aggregates
5709 if they are the same size. */
5710 if (*modep == mode)
5711 return 1;
5712
5713 break;
5714
5715 case ARRAY_TYPE:
5716 {
5717 int count;
5718 tree index = TYPE_DOMAIN (type);
5719
5720 /* Can't handle incomplete types nor sizes that are not
5721 fixed. */
5722 if (!COMPLETE_TYPE_P (type)
5723 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
5724 return -1;
5725
a39ed81b 5726 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep,
575ac27f 5727 empty_base_seen);
1acf0246
BS		 5728 if (count == -1
5729 || !index
5730 || !TYPE_MAX_VALUE (index)
5731 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
5732 || !TYPE_MIN_VALUE (index)
5733 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
5734 || count < 0)
5735 return -1;
5736
5737 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
5738 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
5739
5740 /* There must be no padding. */
5741 if (wi::to_wide (TYPE_SIZE (type))
5742 != count * GET_MODE_BITSIZE (*modep))
5743 return -1;
5744
5745 return count;
5746 }
5747
5748 case RECORD_TYPE:
5749 {
5750 int count = 0;
5751 int sub_count;
5752 tree field;
5753
5754 /* Can't handle incomplete types nor sizes that are not
5755 fixed. */
5756 if (!COMPLETE_TYPE_P (type)
5757 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
5758 return -1;
5759
5760 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5761 {
5762 if (TREE_CODE (field) != FIELD_DECL)
5763 continue;
5764
575ac27f 5765 if (DECL_FIELD_ABI_IGNORED (field))
a39ed81b 5766 {
575ac27f
JJ		 5767 if (lookup_attribute ("no_unique_address",
5768 DECL_ATTRIBUTES (field)))
5769 *empty_base_seen |= 2;
5770 else
5771 *empty_base_seen |= 1;
a39ed81b
JJ		 5772 continue;
5773 }
5774
5775 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep,
575ac27f 5776 empty_base_seen);
1acf0246
BS		 5777 if (sub_count < 0)
5778 return -1;
5779 count += sub_count;
5780 }
5781
5782 /* There must be no padding. */
5783 if (wi::to_wide (TYPE_SIZE (type))
5784 != count * GET_MODE_BITSIZE (*modep))
5785 return -1;
5786
5787 return count;
5788 }
5789
5790 case UNION_TYPE:
5791 case QUAL_UNION_TYPE:
5792 {
5793 /* These aren't very interesting except in a degenerate case. */
5794 int count = 0;
5795 int sub_count;
5796 tree field;
5797
5798 /* Can't handle incomplete types nor sizes that are not
5799 fixed. */
5800 if (!COMPLETE_TYPE_P (type)
5801 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
5802 return -1;
5803
5804 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5805 {
5806 if (TREE_CODE (field) != FIELD_DECL)
5807 continue;
5808
a39ed81b 5809 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep,
575ac27f 5810 empty_base_seen);
1acf0246
BS		 5811 if (sub_count < 0)
5812 return -1;
5813 count = count > sub_count ? count : sub_count;
5814 }
5815
5816 /* There must be no padding. */
5817 if (wi::to_wide (TYPE_SIZE (type))
5818 != count * GET_MODE_BITSIZE (*modep))
5819 return -1;
5820
5821 return count;
5822 }
5823
5824 default:
5825 break;
5826 }
5827
5828 return -1;
5829}
5830
5831/* If an argument, whose type is described by TYPE and MODE, is a homogeneous
5832 float or vector aggregate that shall be passed in FP/vector registers
5833 according to the ELFv2 ABI, return the homogeneous element mode in
5834 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
5835
5836 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
5837
5838bool
5839rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
5840 machine_mode *elt_mode,
5841 int *n_elts)
5842{
5843 /* Note that we do not accept complex types at the top level as
5844 homogeneous aggregates; these types are handled via the
5845 targetm.calls.split_complex_arg mechanism. Complex types
5846 can be elements of homogeneous aggregates, however. */
5847 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
5848 && AGGREGATE_TYPE_P (type))
5849 {
5850 machine_mode field_mode = VOIDmode;
575ac27f 5851 int empty_base_seen = 0;
a39ed81b 5852 int field_count = rs6000_aggregate_candidate (type, &field_mode,
575ac27f 5853 &empty_base_seen);
1acf0246
BS		 5854
5855 if (field_count > 0)
5856 {
5857 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
5858 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
5859
5860 /* The ELFv2 ABI allows homogeneous aggregates to occupy
5861 up to AGGR_ARG_NUM_REG registers. */
5862 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
5863 {
5864 if (elt_mode)
5865 *elt_mode = field_mode;
5866 if (n_elts)
5867 *n_elts = field_count;
575ac27f 5868 if (empty_base_seen && warn_psabi)
a39ed81b 5869 {
239cfd92
JJ		 5870 static unsigned last_reported_type_uid;
5871 unsigned uid = TYPE_UID (TYPE_MAIN_VARIANT (type));
5872 if (uid != last_reported_type_uid)
a39ed81b 5873 {
e33a1eae
JJ		 5874 const char *url
5875 = CHANGES_ROOT_URL "gcc-10/changes.html#empty_base";
575ac27f
JJ		 5876 if (empty_base_seen & 1)
5877 inform (input_location,
5878 "parameter passing for argument of type %qT "
5879 "when C++17 is enabled changed to match C++14 "
691eeb65 5880 "%{in GCC 10.1%}", type, url);
575ac27f
JJ		 5881 else
5882 inform (input_location,
5883 "parameter passing for argument of type %qT "
5884 "with %<[[no_unique_address]]%> members "
691eeb65 5885 "changed %{in GCC 10.1%}", type, url);
239cfd92 5886 last_reported_type_uid = uid;
a39ed81b
JJ		 5887 }
5888 }
1acf0246
BS		 5889 return true;
5890 }
5891 }
5892 }
5893
5894 if (elt_mode)
5895 *elt_mode = mode;
5896 if (n_elts)
5897 *n_elts = 1;
5898 return false;
5899}
5900
5901/* Return a nonzero value to say to return the function value in
5902 memory, just as large structures are always returned. TYPE will be
5903 the data type of the value, and FNTYPE will be the type of the
5904 function doing the returning, or @code{NULL} for libcalls.
5905
5906 The AIX ABI for the RS/6000 specifies that all structures are
5907 returned in memory. The Darwin ABI does the same.
5908
5909 For the Darwin 64 Bit ABI, a function result can be returned in
5910 registers or in memory, depending on the size of the return data
5911 type. If it is returned in registers, the value occupies the same
5912 registers as it would if it were the first and only function
5913 argument. Otherwise, the function places its result in memory at
5914 the location pointed to by GPR3.
5915
5916 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
5917 but a draft put them in memory, and GCC used to implement the draft
5918 instead of the final standard. Therefore, aix_struct_return
5919 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5920 compatibility can change DRAFT_V4_STRUCT_RET to override the
5921 default, and -m switches get the final word. See
5922 rs6000_option_override_internal for more details.
5923
5924 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5925 long double support is enabled. These values are returned in memory.
5926
5927 int_size_in_bytes returns -1 for variable size objects, which go in
5928 memory always. The cast to unsigned makes -1 > 8. */
5929
5930bool
5931rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5932{
5933 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
5934 if (TARGET_MACHO
5935 && rs6000_darwin64_abi
5936 && TREE_CODE (type) == RECORD_TYPE
5937 && int_size_in_bytes (type) > 0)
5938 {
5939 CUMULATIVE_ARGS valcum;
5940 rtx valret;
5941
5942 valcum.words = 0;
5943 valcum.fregno = FP_ARG_MIN_REG;
5944 valcum.vregno = ALTIVEC_ARG_MIN_REG;
5945 /* Do a trial code generation as if this were going to be passed
5946 as an argument; if any part goes in memory, we return NULL. */
5947 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
5948 if (valret)
5949 return false;
5950 /* Otherwise fall through to more conventional ABI rules. */
5951 }
5952
5953 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
5954 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
5955 NULL, NULL))
5956 return false;
5957
5958 /* The ELFv2 ABI returns aggregates up to 16B in registers */
5959 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
5960 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
5961 return false;
5962
5963 if (AGGREGATE_TYPE_P (type)
5964 && (aix_struct_return
5965 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
5966 return true;
5967
5968 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5969 modes only exist for GCC vector types if -maltivec. */
5970 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
5971 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5972 return false;
5973
5974 /* Return synthetic vectors in memory. */
5975 if (TREE_CODE (type) == VECTOR_TYPE
5976 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5977 {
5978 static bool warned_for_return_big_vectors = false;
5979 if (!warned_for_return_big_vectors)
5980 {
5981 warning (OPT_Wpsabi, "GCC vector returned by reference: "
5982 "non-standard ABI extension with no compatibility "
5983 "guarantee");
5984 warned_for_return_big_vectors = true;
5985 }
5986 return true;
5987 }
5988
5989 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
5990 && FLOAT128_IEEE_P (TYPE_MODE (type)))
5991 return true;
5992
5993 return false;
5994}
5995
5996/* Specify whether values returned in registers should be at the most
5997 significant end of a register. We want aggregates returned by
5998 value to match the way aggregates are passed to functions. */
5999
6000bool
6001rs6000_return_in_msb (const_tree valtype)
6002{
6003 return (DEFAULT_ABI == ABI_ELFv2
6004 && BYTES_BIG_ENDIAN
6005 && AGGREGATE_TYPE_P (valtype)
6006 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
6007 == PAD_UPWARD));
6008}
6009
6010#ifdef HAVE_AS_GNU_ATTRIBUTE
6011/* Return TRUE if a call to function FNDECL may be one that
6012 potentially affects the function calling ABI of the object file. */
6013
6014static bool
6015call_ABI_of_interest (tree fndecl)
6016{
6017 if (rs6000_gnu_attr && symtab->state == EXPANSION)
6018 {
6019 struct cgraph_node *c_node;
6020
6021 /* Libcalls are always interesting. */
6022 if (fndecl == NULL_TREE)
6023 return true;
6024
6025 /* Any call to an external function is interesting. */
6026 if (DECL_EXTERNAL (fndecl))
6027 return true;
6028
6029 /* Interesting functions that we are emitting in this object file. */
6030 c_node = cgraph_node::get (fndecl);
6031 c_node = c_node->ultimate_alias_target ();
6032 return !c_node->only_called_directly_p ();
6033 }
6034 return false;
6035}
6036#endif
6037
6038/* Initialize a variable CUM of type CUMULATIVE_ARGS
6039 for a call to a function whose data type is FNTYPE.
6040 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
6041
6042 For incoming args we set the number of arguments in the prototype large
6043 so we never return a PARALLEL. */
6044
6045void
6046init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
6047 rtx libname ATTRIBUTE_UNUSED, int incoming,
6048 int libcall, int n_named_args,
6049 tree fndecl,
6050 machine_mode return_mode ATTRIBUTE_UNUSED)
6051{
6052 static CUMULATIVE_ARGS zero_cumulative;
6053
6054 *cum = zero_cumulative;
6055 cum->words = 0;
6056 cum->fregno = FP_ARG_MIN_REG;
6057 cum->vregno = ALTIVEC_ARG_MIN_REG;
6058 cum->prototype = (fntype && prototype_p (fntype));
6059 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
6060 ? CALL_LIBCALL : CALL_NORMAL);
6061 cum->sysv_gregno = GP_ARG_MIN_REG;
6062 cum->stdarg = stdarg_p (fntype);
6063 cum->libcall = libcall;
6064
6065 cum->nargs_prototype = 0;
6066 if (incoming || cum->prototype)
6067 cum->nargs_prototype = n_named_args;
6068
6069 /* Check for a longcall attribute. */
6070 if ((!fntype && rs6000_default_long_calls)
6071 || (fntype
6072 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
6073 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
6074 cum->call_cookie |= CALL_LONG;
6075 else if (DEFAULT_ABI != ABI_DARWIN)
6076 {
6077 bool is_local = (fndecl
6078 && !DECL_EXTERNAL (fndecl)
6079 && !DECL_WEAK (fndecl)
6080 && (*targetm.binds_local_p) (fndecl));
6081 if (is_local)
6082 ;
6083 else if (flag_plt)
6084 {
6085 if (fntype
6086 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype)))
6087 cum->call_cookie |= CALL_LONG;
6088 }
6089 else
6090 {
6091 if (!(fntype
6092 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype))))
6093 cum->call_cookie |= CALL_LONG;
6094 }
6095 }
6096
6097 if (TARGET_DEBUG_ARG)
6098 {
6099 fprintf (stderr, "\ninit_cumulative_args:");
6100 if (fntype)
6101 {
6102 tree ret_type = TREE_TYPE (fntype);
6103 fprintf (stderr, " ret code = %s,",
6104 get_tree_code_name (TREE_CODE (ret_type)));
6105 }
6106
6107 if (cum->call_cookie & CALL_LONG)
6108 fprintf (stderr, " longcall,");
6109
6110 fprintf (stderr, " proto = %d, nargs = %d\n",
6111 cum->prototype, cum->nargs_prototype);
6112 }
6113
6114#ifdef HAVE_AS_GNU_ATTRIBUTE
6115 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
6116 {
6117 cum->escapes = call_ABI_of_interest (fndecl);
6118 if (cum->escapes)
6119 {
6120 tree return_type;
6121
6122 if (fntype)
6123 {
6124 return_type = TREE_TYPE (fntype);
6125 return_mode = TYPE_MODE (return_type);
6126 }
6127 else
6128 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
6129
6130 if (return_type != NULL)
6131 {
6132 if (TREE_CODE (return_type) == RECORD_TYPE
6133 && TYPE_TRANSPARENT_AGGR (return_type))
6134 {
6135 return_type = TREE_TYPE (first_field (return_type));
6136 return_mode = TYPE_MODE (return_type);
6137 }
6138 if (AGGREGATE_TYPE_P (return_type)
6139 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
6140 <= 8))
6141 rs6000_returns_struct = true;
6142 }
6143 if (SCALAR_FLOAT_MODE_P (return_mode))
6144 {
6145 rs6000_passes_float = true;
6146 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
6147 && (FLOAT128_IBM_P (return_mode)
6148 || FLOAT128_IEEE_P (return_mode)
6149 || (return_type != NULL
6150 && (TYPE_MAIN_VARIANT (return_type)
6151 == long_double_type_node))))
6152 rs6000_passes_long_double = true;
6153
6154 /* Note if we passed or return a IEEE 128-bit type. We changed
6155 the mangling for these types, and we may need to make an alias
6156 with the old mangling. */
6157 if (FLOAT128_IEEE_P (return_mode))
6158 rs6000_passes_ieee128 = true;
6159 }
6160 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
6161 rs6000_passes_vector = true;
6162 }
6163 }
6164#endif
6165
6166 if (fntype
6167 && !TARGET_ALTIVEC
6168 && TARGET_ALTIVEC_ABI
6169 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
6170 {
6171 error ("cannot return value in vector register because"
6172 " altivec instructions are disabled, use %qs"
6173 " to enable them", "-maltivec");
6174 }
6175}
6176\f
6177
6178/* On rs6000, function arguments are promoted, as are function return
6179 values. */
6180
6181machine_mode
6182rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
6183 machine_mode mode,
6184 int *punsignedp ATTRIBUTE_UNUSED,
6185 const_tree, int)
6186{
6187 PROMOTE_MODE (mode, *punsignedp, type);
6188
6189 return mode;
6190}
6191
6192/* Return true if TYPE must be passed on the stack and not in registers. */
6193
6194bool
0ffef200 6195rs6000_must_pass_in_stack (const function_arg_info &arg)
1acf0246
BS		 6196{
6197 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
0ffef200 6198 return must_pass_in_stack_var_size (arg);
1acf0246 6199 else
0ffef200 6200 return must_pass_in_stack_var_size_or_pad (arg);
1acf0246
BS		 6201}
6202
6203static inline bool
6204is_complex_IBM_long_double (machine_mode mode)
6205{
6206 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
6207}
6208
6209/* Whether ABI_V4 passes MODE args to a function in floating point
6210 registers. */
6211
6212static bool
6213abi_v4_pass_in_fpr (machine_mode mode, bool named)
6214{
6215 if (!TARGET_HARD_FLOAT)
6216 return false;
6217 if (mode == DFmode)
6218 return true;
6219 if (mode == SFmode && named)
6220 return true;
6221 /* ABI_V4 passes complex IBM long double in 8 gprs.
6222 Stupid, but we can't change the ABI now. */
6223 if (is_complex_IBM_long_double (mode))
6224 return false;
6225 if (FLOAT128_2REG_P (mode))
6226 return true;
6227 if (DECIMAL_FLOAT_MODE_P (mode))
6228 return true;
6229 return false;
6230}
6231
6232/* Implement TARGET_FUNCTION_ARG_PADDING.
6233
6234 For the AIX ABI structs are always stored left shifted in their
6235 argument slot. */
6236
6237pad_direction
6238rs6000_function_arg_padding (machine_mode mode, const_tree type)
6239{
6240#ifndef AGGREGATE_PADDING_FIXED
6241#define AGGREGATE_PADDING_FIXED 0
6242#endif
6243#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
6244#define AGGREGATES_PAD_UPWARD_ALWAYS 0
6245#endif
6246
6247 if (!AGGREGATE_PADDING_FIXED)
6248 {
6249 /* GCC used to pass structures of the same size as integer types as
6250 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
6251 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
6252 passed padded downward, except that -mstrict-align further
6253 muddied the water in that multi-component structures of 2 and 4
6254 bytes in size were passed padded upward.
6255
6256 The following arranges for best compatibility with previous
6257 versions of gcc, but removes the -mstrict-align dependency. */
6258 if (BYTES_BIG_ENDIAN)
6259 {
6260 HOST_WIDE_INT size = 0;
6261
6262 if (mode == BLKmode)
6263 {
6264 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
6265 size = int_size_in_bytes (type);
6266 }
6267 else
6268 size = GET_MODE_SIZE (mode);
6269
6270 if (size == 1 || size == 2 || size == 4)
6271 return PAD_DOWNWARD;
6272 }
6273 return PAD_UPWARD;
6274 }
6275
6276 if (AGGREGATES_PAD_UPWARD_ALWAYS)
6277 {
6278 if (type != 0 && AGGREGATE_TYPE_P (type))
6279 return PAD_UPWARD;
6280 }
6281
6282 /* Fall back to the default. */
6283 return default_function_arg_padding (mode, type);
6284}
6285
6286/* If defined, a C expression that gives the alignment boundary, in bits,
6287 of an argument with the specified mode and type. If it is not defined,
6288 PARM_BOUNDARY is used for all arguments.
6289
6290 V.4 wants long longs and doubles to be double word aligned. Just
6291 testing the mode size is a boneheaded way to do this as it means
6292 that other types such as complex int are also double word aligned.
6293 However, we're stuck with this because changing the ABI might break
6294 existing library interfaces.
6295
6296 Quadword align Altivec/VSX vectors.
6297 Quadword align large synthetic vector types. */
6298
6299unsigned int
6300rs6000_function_arg_boundary (machine_mode mode, const_tree type)
6301{
6302 machine_mode elt_mode;
6303 int n_elts;
6304
6305 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
6306
6307 if (DEFAULT_ABI == ABI_V4
6308 && (GET_MODE_SIZE (mode) == 8
6309 || (TARGET_HARD_FLOAT
6310 && !is_complex_IBM_long_double (mode)
6311 && FLOAT128_2REG_P (mode))))
6312 return 64;
6313 else if (FLOAT128_VECTOR_P (mode))
6314 return 128;
6315 else if (type && TREE_CODE (type) == VECTOR_TYPE
6316 && int_size_in_bytes (type) >= 8
6317 && int_size_in_bytes (type) < 16)
6318 return 64;
6319 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
6320 || (type && TREE_CODE (type) == VECTOR_TYPE
6321 && int_size_in_bytes (type) >= 16))
6322 return 128;
6323
6324 /* Aggregate types that need > 8 byte alignment are quadword-aligned
6325 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
6326 -mcompat-align-parm is used. */
6327 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
6328 || DEFAULT_ABI == ABI_ELFv2)
6329 && type && TYPE_ALIGN (type) > 64)
6330 {
6331 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
6332 or homogeneous float/vector aggregates here. We already handled
6333 vector aggregates above, but still need to check for float here. */
6334 bool aggregate_p = (AGGREGATE_TYPE_P (type)
6335 && !SCALAR_FLOAT_MODE_P (elt_mode));
6336
6337 /* We used to check for BLKmode instead of the above aggregate type
6338 check. Warn when this results in any difference to the ABI. */
6339 if (aggregate_p != (mode == BLKmode))
6340 {
6341 static bool warned;
6342 if (!warned && warn_psabi)
6343 {
6344 warned = true;
6345 inform (input_location,
6346 "the ABI of passing aggregates with %d-byte alignment"
6347 " has changed in GCC 5",
6348 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
6349 }
6350 }
6351
6352 if (aggregate_p)
6353 return 128;
6354 }
6355
6356 /* Similar for the Darwin64 ABI. Note that for historical reasons we
6357 implement the "aggregate type" check as a BLKmode check here; this
6358 means certain aggregate types are in fact not aligned. */
6359 if (TARGET_MACHO && rs6000_darwin64_abi
6360 && mode == BLKmode
6361 && type && TYPE_ALIGN (type) > 64)
6362 return 128;
6363
6364 return PARM_BOUNDARY;
6365}
6366
6367/* The offset in words to the start of the parameter save area. */
6368
6369static unsigned int
6370rs6000_parm_offset (void)
6371{
6372 return (DEFAULT_ABI == ABI_V4 ? 2
6373 : DEFAULT_ABI == ABI_ELFv2 ? 4
6374 : 6);
6375}
6376
6377/* For a function parm of MODE and TYPE, return the starting word in
6378 the parameter area. NWORDS of the parameter area are already used. */
6379
6380static unsigned int
6381rs6000_parm_start (machine_mode mode, const_tree type,
6382 unsigned int nwords)
6383{
6384 unsigned int align;
6385
6386 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
6387 return nwords + (-(rs6000_parm_offset () + nwords) & align);
6388}
6389
6390/* Compute the size (in words) of a function argument. */
6391
6392static unsigned long
6393rs6000_arg_size (machine_mode mode, const_tree type)
6394{
6395 unsigned long size;
6396
6397 if (mode != BLKmode)
6398 size = GET_MODE_SIZE (mode);
6399 else
6400 size = int_size_in_bytes (type);
6401
6402 if (TARGET_32BIT)
6403 return (size + 3) >> 2;
6404 else
6405 return (size + 7) >> 3;
6406}
6407\f
6408/* Use this to flush pending int fields. */
6409
6410static void
6411rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
6412 HOST_WIDE_INT bitpos, int final)
6413{
6414 unsigned int startbit, endbit;
6415 int intregs, intoffset;
6416
6417 /* Handle the situations where a float is taking up the first half
6418 of the GPR, and the other half is empty (typically due to
6419 alignment restrictions). We can detect this by a 8-byte-aligned
6420 int field, or by seeing that this is the final flush for this
6421 argument. Count the word and continue on. */
6422 if (cum->floats_in_gpr == 1
6423 && (cum->intoffset % 64 == 0
6424 || (cum->intoffset == -1 && final)))
6425 {
6426 cum->words++;
6427 cum->floats_in_gpr = 0;
6428 }
6429
6430 if (cum->intoffset == -1)
6431 return;
6432
6433 intoffset = cum->intoffset;
6434 cum->intoffset = -1;
6435 cum->floats_in_gpr = 0;
6436
6437 if (intoffset % BITS_PER_WORD != 0)
6438 {
6439 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
6440 if (!int_mode_for_size (bits, 0).exists ())
6441 {
6442 /* We couldn't find an appropriate mode, which happens,
6443 e.g., in packed structs when there are 3 bytes to load.
6444 Back intoffset back to the beginning of the word in this
6445 case. */
6446 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
6447 }
6448 }
6449
6450 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
6451 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
6452 intregs = (endbit - startbit) / BITS_PER_WORD;
6453 cum->words += intregs;
6454 /* words should be unsigned. */
6455 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
6456 {
6457 int pad = (endbit/BITS_PER_WORD) - cum->words;
6458 cum->words += pad;
6459 }
6460}
6461
6462/* The darwin64 ABI calls for us to recurse down through structs,
6463 looking for elements passed in registers. Unfortunately, we have
6464 to track int register count here also because of misalignments
6465 in powerpc alignment mode. */
6466
6467static void
6468rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
6469 const_tree type,
6470 HOST_WIDE_INT startbitpos)
6471{
6472 tree f;
6473
6474 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
6475 if (TREE_CODE (f) == FIELD_DECL)
6476 {
6477 HOST_WIDE_INT bitpos = startbitpos;
6478 tree ftype = TREE_TYPE (f);
6479 machine_mode mode;
6480 if (ftype == error_mark_node)
6481 continue;
6482 mode = TYPE_MODE (ftype);
6483
6484 if (DECL_SIZE (f) != 0
6485 && tree_fits_uhwi_p (bit_position (f)))
6486 bitpos += int_bit_position (f);
6487
6488 /* ??? FIXME: else assume zero offset. */
6489
6490 if (TREE_CODE (ftype) == RECORD_TYPE)
6491 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
6492 else if (USE_FP_FOR_ARG_P (cum, mode))
6493 {
6494 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
6495 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
6496 cum->fregno += n_fpregs;
6497 /* Single-precision floats present a special problem for
6498 us, because they are smaller than an 8-byte GPR, and so
6499 the structure-packing rules combined with the standard
6500 varargs behavior mean that we want to pack float/float
6501 and float/int combinations into a single register's
6502 space. This is complicated by the arg advance flushing,
6503 which works on arbitrarily large groups of int-type
6504 fields. */
6505 if (mode == SFmode)
6506 {
6507 if (cum->floats_in_gpr == 1)
6508 {
6509 /* Two floats in a word; count the word and reset
6510 the float count. */
6511 cum->words++;
6512 cum->floats_in_gpr = 0;
6513 }
6514 else if (bitpos % 64 == 0)
6515 {
6516 /* A float at the beginning of an 8-byte word;
6517 count it and put off adjusting cum->words until
6518 we see if a arg advance flush is going to do it
6519 for us. */
6520 cum->floats_in_gpr++;
6521 }
6522 else
6523 {
6524 /* The float is at the end of a word, preceded
6525 by integer fields, so the arg advance flush
6526 just above has already set cum->words and
6527 everything is taken care of. */
6528 }
6529 }
6530 else
6531 cum->words += n_fpregs;
6532 }
6533 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
6534 {
6535 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
6536 cum->vregno++;
6537 cum->words += 2;
6538 }
6539 else if (cum->intoffset == -1)
6540 cum->intoffset = bitpos;
6541 }
6542}
6543
6544/* Check for an item that needs to be considered specially under the darwin 64
6545 bit ABI. These are record types where the mode is BLK or the structure is
6546 8 bytes in size. */
6547int
6548rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
6549{
6550 return rs6000_darwin64_abi
6551 && ((mode == BLKmode
6552 && TREE_CODE (type) == RECORD_TYPE
6553 && int_size_in_bytes (type) > 0)
6554 || (type && TREE_CODE (type) == RECORD_TYPE
6555 && int_size_in_bytes (type) == 8)) ? 1 : 0;
6556}
6557
6558/* Update the data in CUM to advance over an argument
6559 of mode MODE and data type TYPE.
6560 (TYPE is null for libcalls where that information may not be available.)
6561
6562 Note that for args passed by reference, function_arg will be called
6563 with MODE and TYPE set to that of the pointer to the arg, not the arg
6564 itself. */
6565
6566static void
6567rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
6568 const_tree type, bool named, int depth)
6569{
6570 machine_mode elt_mode;
6571 int n_elts;
6572
6573 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
6574
6575 /* Only tick off an argument if we're not recursing. */
6576 if (depth == 0)
6577 cum->nargs_prototype--;
6578
6579#ifdef HAVE_AS_GNU_ATTRIBUTE
6580 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
6581 && cum->escapes)
6582 {
6583 if (SCALAR_FLOAT_MODE_P (mode))
6584 {
6585 rs6000_passes_float = true;
6586 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
6587 && (FLOAT128_IBM_P (mode)
6588 || FLOAT128_IEEE_P (mode)
6589 || (type != NULL
6590 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
6591 rs6000_passes_long_double = true;
6592
6593 /* Note if we passed or return a IEEE 128-bit type. We changed the
6594 mangling for these types, and we may need to make an alias with
6595 the old mangling. */
6596 if (FLOAT128_IEEE_P (mode))
6597 rs6000_passes_ieee128 = true;
6598 }
6599 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
6600 rs6000_passes_vector = true;
6601 }
6602#endif
6603
6604 if (TARGET_ALTIVEC_ABI
6605 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
6606 || (type && TREE_CODE (type) == VECTOR_TYPE
6607 && int_size_in_bytes (type) == 16)))
6608 {
6609 bool stack = false;
6610
6611 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
6612 {
6613 cum->vregno += n_elts;
6614
6615 if (!TARGET_ALTIVEC)
6616 error ("cannot pass argument in vector register because"
6617 " altivec instructions are disabled, use %qs"
6618 " to enable them", "-maltivec");
6619
6620 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
6621 even if it is going to be passed in a vector register.
6622 Darwin does the same for variable-argument functions. */
6623 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
6624 && TARGET_64BIT)
6625 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
6626 stack = true;
6627 }
6628 else
6629 stack = true;
6630
6631 if (stack)
6632 {
6633 int align;
6634
6635 /* Vector parameters must be 16-byte aligned. In 32-bit
6636 mode this means we need to take into account the offset
6637 to the parameter save area. In 64-bit mode, they just
6638 have to start on an even word, since the parameter save
6639 area is 16-byte aligned. */
6640 if (TARGET_32BIT)
6641 align = -(rs6000_parm_offset () + cum->words) & 3;
6642 else
6643 align = cum->words & 1;
6644 cum->words += align + rs6000_arg_size (mode, type);
6645
6646 if (TARGET_DEBUG_ARG)
6647 {
6648 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
6649 cum->words, align);
6650 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
6651 cum->nargs_prototype, cum->prototype,
6652 GET_MODE_NAME (mode));
6653 }
6654 }
6655 }
6656 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
6657 {
6658 int size = int_size_in_bytes (type);
6659 /* Variable sized types have size == -1 and are
6660 treated as if consisting entirely of ints.
6661 Pad to 16 byte boundary if needed. */
6662 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
6663 && (cum->words % 2) != 0)
6664 cum->words++;
6665 /* For varargs, we can just go up by the size of the struct. */
6666 if (!named)
6667 cum->words += (size + 7) / 8;
6668 else
6669 {
6670 /* It is tempting to say int register count just goes up by
6671 sizeof(type)/8, but this is wrong in a case such as
6672 { int; double; int; } [powerpc alignment]. We have to
6673 grovel through the fields for these too. */
6674 cum->intoffset = 0;
6675 cum->floats_in_gpr = 0;
6676 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
6677 rs6000_darwin64_record_arg_advance_flush (cum,
6678 size * BITS_PER_UNIT, 1);
6679 }
6680 if (TARGET_DEBUG_ARG)
6681 {
6682 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
6683 cum->words, TYPE_ALIGN (type), size);
6684 fprintf (stderr,
6685 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
6686 cum->nargs_prototype, cum->prototype,
6687 GET_MODE_NAME (mode));
6688 }
6689 }
6690 else if (DEFAULT_ABI == ABI_V4)
6691 {
6692 if (abi_v4_pass_in_fpr (mode, named))
6693 {
6694 /* _Decimal128 must use an even/odd register pair. This assumes
6695 that the register number is odd when fregno is odd. */
6696 if (mode == TDmode && (cum->fregno % 2) == 1)
6697 cum->fregno++;
6698
6699 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
6700 <= FP_ARG_V4_MAX_REG)
6701 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
6702 else
6703 {
6704 cum->fregno = FP_ARG_V4_MAX_REG + 1;
6705 if (mode == DFmode || FLOAT128_IBM_P (mode)
6706 || mode == DDmode || mode == TDmode)
6707 cum->words += cum->words & 1;
6708 cum->words += rs6000_arg_size (mode, type);
6709 }
6710 }
6711 else
6712 {
6713 int n_words = rs6000_arg_size (mode, type);
6714 int gregno = cum->sysv_gregno;
6715
6716 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
6717 As does any other 2 word item such as complex int due to a
6718 historical mistake. */
6719 if (n_words == 2)
6720 gregno += (1 - gregno) & 1;
6721
6722 /* Multi-reg args are not split between registers and stack. */
6723 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
6724 {
6725 /* Long long is aligned on the stack. So are other 2 word
6726 items such as complex int due to a historical mistake. */
6727 if (n_words == 2)
6728 cum->words += cum->words & 1;
6729 cum->words += n_words;
6730 }
6731
6732 /* Note: continuing to accumulate gregno past when we've started
6733 spilling to the stack indicates the fact that we've started
6734 spilling to the stack to expand_builtin_saveregs. */
6735 cum->sysv_gregno = gregno + n_words;
6736 }
6737
6738 if (TARGET_DEBUG_ARG)
6739 {
6740 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
6741 cum->words, cum->fregno);
6742 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
6743 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
6744 fprintf (stderr, "mode = %4s, named = %d\n",
6745 GET_MODE_NAME (mode), named);
6746 }
6747 }
6748 else
6749 {
6750 int n_words = rs6000_arg_size (mode, type);
6751 int start_words = cum->words;
6752 int align_words = rs6000_parm_start (mode, type, start_words);
6753
6754 cum->words = align_words + n_words;
6755
6756 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
6757 {
6758 /* _Decimal128 must be passed in an even/odd float register pair.
6759 This assumes that the register number is odd when fregno is
6760 odd. */
6761 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
6762 cum->fregno++;
6763 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
6764 }
6765
6766 if (TARGET_DEBUG_ARG)
6767 {
6768 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
6769 cum->words, cum->fregno);
6770 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
6771 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
6772 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
6773 named, align_words - start_words, depth);
6774 }
6775 }
6776}
6777
6778void
6930c98c
RS		 6779rs6000_function_arg_advance (cumulative_args_t cum,
6780 const function_arg_info &arg)
1acf0246 6781{
6930c98c
RS		 6782 rs6000_function_arg_advance_1 (get_cumulative_args (cum),
6783 arg.mode, arg.type, arg.named, 0);
1acf0246
BS		 6784}
6785
6786/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
6787 structure between cum->intoffset and bitpos to integer registers. */
6788
6789static void
6790rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
6791 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
6792{
6793 machine_mode mode;
6794 unsigned int regno;
6795 unsigned int startbit, endbit;
6796 int this_regno, intregs, intoffset;
6797 rtx reg;
6798
6799 if (cum->intoffset == -1)
6800 return;
6801
6802 intoffset = cum->intoffset;
6803 cum->intoffset = -1;
6804
6805 /* If this is the trailing part of a word, try to only load that
6806 much into the register. Otherwise load the whole register. Note
6807 that in the latter case we may pick up unwanted bits. It's not a
6808 problem at the moment but may wish to revisit. */
6809
6810 if (intoffset % BITS_PER_WORD != 0)
6811 {
6812 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
6813 if (!int_mode_for_size (bits, 0).exists (&mode))
6814 {
6815 /* We couldn't find an appropriate mode, which happens,
6816 e.g., in packed structs when there are 3 bytes to load.
6817 Back intoffset back to the beginning of the word in this
6818 case. */
6819 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
6820 mode = word_mode;
6821 }
6822 }
6823 else
6824 mode = word_mode;
6825
6826 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
6827 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
6828 intregs = (endbit - startbit) / BITS_PER_WORD;
6829 this_regno = cum->words + intoffset / BITS_PER_WORD;
6830
6831 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
6832 cum->use_stack = 1;
6833
6834 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
6835 if (intregs <= 0)
6836 return;
6837
6838 intoffset /= BITS_PER_UNIT;
6839 do
6840 {
6841 regno = GP_ARG_MIN_REG + this_regno;
6842 reg = gen_rtx_REG (mode, regno);
6843 rvec[(*k)++] =
6844 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
6845
6846 this_regno += 1;
6847 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
6848 mode = word_mode;
6849 intregs -= 1;
6850 }
6851 while (intregs > 0);
6852}
6853
6854/* Recursive workhorse for the following. */
6855
6856static void
6857rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
6858 HOST_WIDE_INT startbitpos, rtx rvec[],
6859 int *k)
6860{
6861 tree f;
6862
6863 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
6864 if (TREE_CODE (f) == FIELD_DECL)
6865 {
6866 HOST_WIDE_INT bitpos = startbitpos;
6867 tree ftype = TREE_TYPE (f);
6868 machine_mode mode;
6869 if (ftype == error_mark_node)
6870 continue;
6871 mode = TYPE_MODE (ftype);
6872
6873 if (DECL_SIZE (f) != 0
6874 && tree_fits_uhwi_p (bit_position (f)))
6875 bitpos += int_bit_position (f);
6876
6877 /* ??? FIXME: else assume zero offset. */
6878
6879 if (TREE_CODE (ftype) == RECORD_TYPE)
6880 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
6881 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
6882 {
6883 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
6884#if 0
6885 switch (mode)
6886 {
6887 case E_SCmode: mode = SFmode; break;
6888 case E_DCmode: mode = DFmode; break;
6889 case E_TCmode: mode = TFmode; break;
6890 default: break;
6891 }
6892#endif
6893 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
6894 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
6895 {
6896 gcc_assert (cum->fregno == FP_ARG_MAX_REG
6897 && (mode == TFmode || mode == TDmode));
6898 /* Long double or _Decimal128 split over regs and memory. */
6899 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
6900 cum->use_stack=1;
6901 }
6902 rvec[(*k)++]
6903 = gen_rtx_EXPR_LIST (VOIDmode,
6904 gen_rtx_REG (mode, cum->fregno++),
6905 GEN_INT (bitpos / BITS_PER_UNIT));
6906 if (FLOAT128_2REG_P (mode))
6907 cum->fregno++;
6908 }
6909 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
6910 {
6911 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
6912 rvec[(*k)++]
6913 = gen_rtx_EXPR_LIST (VOIDmode,
6914 gen_rtx_REG (mode, cum->vregno++),
6915 GEN_INT (bitpos / BITS_PER_UNIT));
6916 }
6917 else if (cum->intoffset == -1)
6918 cum->intoffset = bitpos;
6919 }
6920}
6921
6922/* For the darwin64 ABI, we want to construct a PARALLEL consisting of
6923 the register(s) to be used for each field and subfield of a struct
6924 being passed by value, along with the offset of where the
6925 register's value may be found in the block. FP fields go in FP
6926 register, vector fields go in vector registers, and everything
6927 else goes in int registers, packed as in memory.
6928
6929 This code is also used for function return values. RETVAL indicates
6930 whether this is the case.
6931
6932 Much of this is taken from the SPARC V9 port, which has a similar
6933 calling convention. */
6934
6935rtx
6936rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
6937 bool named, bool retval)
6938{
6939 rtx rvec[FIRST_PSEUDO_REGISTER];
6940 int k = 1, kbase = 1;
6941 HOST_WIDE_INT typesize = int_size_in_bytes (type);
6942 /* This is a copy; modifications are not visible to our caller. */
6943 CUMULATIVE_ARGS copy_cum = *orig_cum;
6944 CUMULATIVE_ARGS *cum = &copy_cum;
6945
6946 /* Pad to 16 byte boundary if needed. */
6947 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
6948 && (cum->words % 2) != 0)
6949 cum->words++;
6950
6951 cum->intoffset = 0;
6952 cum->use_stack = 0;
6953 cum->named = named;
6954
6955 /* Put entries into rvec[] for individual FP and vector fields, and
6956 for the chunks of memory that go in int regs. Note we start at
6957 element 1; 0 is reserved for an indication of using memory, and
6958 may or may not be filled in below. */
6959 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
6960 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
6961
6962 /* If any part of the struct went on the stack put all of it there.
6963 This hack is because the generic code for
6964 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
6965 parts of the struct are not at the beginning. */
6966 if (cum->use_stack)
6967 {
6968 if (retval)
6969 return NULL_RTX; /* doesn't go in registers at all */
6970 kbase = 0;
6971 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6972 }
6973 if (k > 1 || cum->use_stack)
6974 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
6975 else
6976 return NULL_RTX;
6977}
6978
6979/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
6980
6981static rtx
6982rs6000_mixed_function_arg (machine_mode mode, const_tree type,
6983 int align_words)
6984{
6985 int n_units;
6986 int i, k;
6987 rtx rvec[GP_ARG_NUM_REG + 1];
6988
6989 if (align_words >= GP_ARG_NUM_REG)
6990 return NULL_RTX;
6991
6992 n_units = rs6000_arg_size (mode, type);
6993
6994 /* Optimize the simple case where the arg fits in one gpr, except in
6995 the case of BLKmode due to assign_parms assuming that registers are
6996 BITS_PER_WORD wide. */
6997 if (n_units == 0
6998 || (n_units == 1 && mode != BLKmode))
6999 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7000
7001 k = 0;
7002 if (align_words + n_units > GP_ARG_NUM_REG)
7003 /* Not all of the arg fits in gprs. Say that it goes in memory too,
7004 using a magic NULL_RTX component.
7005 This is not strictly correct. Only some of the arg belongs in
7006 memory, not all of it. However, the normal scheme using
7007 function_arg_partial_nregs can result in unusual subregs, eg.
7008 (subreg:SI (reg:DF) 4), which are not handled well. The code to
7009 store the whole arg to memory is often more efficient than code
7010 to store pieces, and we know that space is available in the right
7011 place for the whole arg. */
7012 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7013
7014 i = 0;
7015 do
7016 {
7017 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
7018 rtx off = GEN_INT (i++ * 4);
7019 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7020 }
7021 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
7022
7023 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
7024}
7025
7026/* We have an argument of MODE and TYPE that goes into FPRs or VRs,
7027 but must also be copied into the parameter save area starting at
7028 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
7029 to the GPRs and/or memory. Return the number of elements used. */
7030
7031static int
7032rs6000_psave_function_arg (machine_mode mode, const_tree type,
7033 int align_words, rtx *rvec)
7034{
7035 int k = 0;
7036
7037 if (align_words < GP_ARG_NUM_REG)
7038 {
7039 int n_words = rs6000_arg_size (mode, type);
7040
7041 if (align_words + n_words > GP_ARG_NUM_REG
7042 || mode == BLKmode
7043 || (TARGET_32BIT && TARGET_POWERPC64))
7044 {
7045 /* If this is partially on the stack, then we only
7046 include the portion actually in registers here. */
7047 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
7048 int i = 0;
7049
7050 if (align_words + n_words > GP_ARG_NUM_REG)
7051 {
7052 /* Not all of the arg fits in gprs. Say that it goes in memory
7053 too, using a magic NULL_RTX component. Also see comment in
7054 rs6000_mixed_function_arg for why the normal
7055 function_arg_partial_nregs scheme doesn't work in this case. */
7056 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7057 }
7058
7059 do
7060 {
7061 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
7062 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
7063 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7064 }
7065 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
7066 }
7067 else
7068 {
7069 /* The whole arg fits in gprs. */
7070 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7071 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
7072 }
7073 }
7074 else
7075 {
7076 /* It's entirely in memory. */
7077 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7078 }
7079
7080 return k;
7081}
7082
7083/* RVEC is a vector of K components of an argument of mode MODE.
7084 Construct the final function_arg return value from it. */
7085
7086static rtx
7087rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
7088{
7089 gcc_assert (k >= 1);
7090
7091 /* Avoid returning a PARALLEL in the trivial cases. */
7092 if (k == 1)
7093 {
7094 if (XEXP (rvec[0], 0) == NULL_RTX)
7095 return NULL_RTX;
7096
7097 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
7098 return XEXP (rvec[0], 0);
7099 }
7100
7101 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
7102}
7103
7104/* Determine where to put an argument to a function.
7105 Value is zero to push the argument on the stack,
7106 or a hard register in which to store the argument.
7107
1acf0246
BS		 7108 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7109 the preceding args and about the function being called. It is
7110 not modified in this routine.
6783fdb7 7111 ARG is a description of the argument.
1acf0246
BS		 7112
7113 On RS/6000 the first eight words of non-FP are normally in registers
7114 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
7115 Under V.4, the first 8 FP args are in registers.
7116
7117 If this is floating-point and no prototype is specified, we use
7118 both an FP and integer register (or possibly FP reg and stack). Library
7119 functions (when CALL_LIBCALL is set) always have the proper types for args,
7120 so we can pass the FP value just in one register. emit_library_function
7121 doesn't support PARALLEL anyway.
7122
7123 Note that for args passed by reference, function_arg will be called
6783fdb7 7124 with ARG describing the pointer to the arg, not the arg itself. */
1acf0246
BS		 7125
7126rtx
6783fdb7 7127rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
1acf0246
BS		 7128{
7129 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6783fdb7
RS		 7130 tree type = arg.type;
7131 machine_mode mode = arg.mode;
7132 bool named = arg.named;
1acf0246
BS		 7133 enum rs6000_abi abi = DEFAULT_ABI;
7134 machine_mode elt_mode;
7135 int n_elts;
7136
7137 /* Return a marker to indicate whether CR1 needs to set or clear the
7138 bit that V.4 uses to say fp args were passed in registers.
7139 Assume that we don't need the marker for software floating point,
7140 or compiler generated library calls. */
6783fdb7 7141 if (arg.end_marker_p ())
1acf0246
BS		 7142 {
7143 if (abi == ABI_V4
7144 && (cum->call_cookie & CALL_LIBCALL) == 0
7145 && (cum->stdarg
7146 || (cum->nargs_prototype < 0
7147 && (cum->prototype || TARGET_NO_PROTOTYPE)))
7148 && TARGET_HARD_FLOAT)
7149 return GEN_INT (cum->call_cookie
7150 | ((cum->fregno == FP_ARG_MIN_REG)
7151 ? CALL_V4_SET_FP_ARGS
7152 : CALL_V4_CLEAR_FP_ARGS));
7153
7154 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
7155 }
7156
7157 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
7158
7159 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7160 {
7161 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
7162 if (rslt != NULL_RTX)
7163 return rslt;
7164 /* Else fall through to usual handling. */
7165 }
7166
7167 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
7168 {
7169 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
7170 rtx r, off;
7171 int i, k = 0;
7172
7173 /* Do we also need to pass this argument in the parameter save area?
7174 Library support functions for IEEE 128-bit are assumed to not need the
7175 value passed both in GPRs and in vector registers. */
7176 if (TARGET_64BIT && !cum->prototype
7177 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
7178 {
7179 int align_words = ROUND_UP (cum->words, 2);
7180 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
7181 }
7182
7183 /* Describe where this argument goes in the vector registers. */
7184 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
7185 {
7186 r = gen_rtx_REG (elt_mode, cum->vregno + i);
7187 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
7188 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7189 }
7190
7191 return rs6000_finish_function_arg (mode, rvec, k);
7192 }
7193 else if (TARGET_ALTIVEC_ABI
7194 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7195 || (type && TREE_CODE (type) == VECTOR_TYPE
7196 && int_size_in_bytes (type) == 16)))
7197 {
7198 if (named || abi == ABI_V4)
7199 return NULL_RTX;
7200 else
7201 {
7202 /* Vector parameters to varargs functions under AIX or Darwin
7203 get passed in memory and possibly also in GPRs. */
7204 int align, align_words, n_words;
7205 machine_mode part_mode;
7206
7207 /* Vector parameters must be 16-byte aligned. In 32-bit
7208 mode this means we need to take into account the offset
7209 to the parameter save area. In 64-bit mode, they just
7210 have to start on an even word, since the parameter save
7211 area is 16-byte aligned. */
7212 if (TARGET_32BIT)
7213 align = -(rs6000_parm_offset () + cum->words) & 3;
7214 else
7215 align = cum->words & 1;
7216 align_words = cum->words + align;
7217
7218 /* Out of registers? Memory, then. */
7219 if (align_words >= GP_ARG_NUM_REG)
7220 return NULL_RTX;
7221
7222 if (TARGET_32BIT && TARGET_POWERPC64)
7223 return rs6000_mixed_function_arg (mode, type, align_words);
7224
7225 /* The vector value goes in GPRs. Only the part of the
7226 value in GPRs is reported here. */
7227 part_mode = mode;
7228 n_words = rs6000_arg_size (mode, type);
7229 if (align_words + n_words > GP_ARG_NUM_REG)
7230 /* Fortunately, there are only two possibilities, the value
7231 is either wholly in GPRs or half in GPRs and half not. */
7232 part_mode = DImode;
7233
7234 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
7235 }
7236 }
7237
7238 else if (abi == ABI_V4)
7239 {
7240 if (abi_v4_pass_in_fpr (mode, named))
7241 {
7242 /* _Decimal128 must use an even/odd register pair. This assumes
7243 that the register number is odd when fregno is odd. */
7244 if (mode == TDmode && (cum->fregno % 2) == 1)
7245 cum->fregno++;
7246
7247 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
7248 <= FP_ARG_V4_MAX_REG)
7249 return gen_rtx_REG (mode, cum->fregno);
7250 else
7251 return NULL_RTX;
7252 }
7253 else
7254 {
7255 int n_words = rs6000_arg_size (mode, type);
7256 int gregno = cum->sysv_gregno;
7257
7258 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
7259 As does any other 2 word item such as complex int due to a
7260 historical mistake. */
7261 if (n_words == 2)
7262 gregno += (1 - gregno) & 1;
7263
7264 /* Multi-reg args are not split between registers and stack. */
7265 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7266 return NULL_RTX;
7267
7268 if (TARGET_32BIT && TARGET_POWERPC64)
7269 return rs6000_mixed_function_arg (mode, type,
7270 gregno - GP_ARG_MIN_REG);
7271 return gen_rtx_REG (mode, gregno);
7272 }
7273 }
7274 else
7275 {
7276 int align_words = rs6000_parm_start (mode, type, cum->words);
7277
7278 /* _Decimal128 must be passed in an even/odd float register pair.
7279 This assumes that the register number is odd when fregno is odd. */
7280 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
7281 cum->fregno++;
7282
7283 if (USE_FP_FOR_ARG_P (cum, elt_mode)
7284 && !(TARGET_AIX && !TARGET_ELF
7285 && type != NULL && AGGREGATE_TYPE_P (type)))
7286 {
7287 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
7288 rtx r, off;
7289 int i, k = 0;
7290 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
7291 int fpr_words;
7292
7293 /* Do we also need to pass this argument in the parameter
7294 save area? */
7295 if (type && (cum->nargs_prototype <= 0
7296 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7297 && TARGET_XL_COMPAT
7298 && align_words >= GP_ARG_NUM_REG)))
7299 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
7300
7301 /* Describe where this argument goes in the fprs. */
7302 for (i = 0; i < n_elts
7303 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
7304 {
7305 /* Check if the argument is split over registers and memory.
7306 This can only ever happen for long double or _Decimal128;
7307 complex types are handled via split_complex_arg. */
7308 machine_mode fmode = elt_mode;
7309 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
7310 {
7311 gcc_assert (FLOAT128_2REG_P (fmode));
7312 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
7313 }
7314
7315 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
7316 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
7317 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7318 }
7319
7320 /* If there were not enough FPRs to hold the argument, the rest
7321 usually goes into memory. However, if the current position
7322 is still within the register parameter area, a portion may
7323 actually have to go into GPRs.
7324
7325 Note that it may happen that the portion of the argument
7326 passed in the first "half" of the first GPR was already
7327 passed in the last FPR as well.
7328
7329 For unnamed arguments, we already set up GPRs to cover the
7330 whole argument in rs6000_psave_function_arg, so there is
7331 nothing further to do at this point. */
7332 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
7333 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
7334 && cum->nargs_prototype > 0)
7335 {
7336 static bool warned;
7337
7338 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
7339 int n_words = rs6000_arg_size (mode, type);
7340
7341 align_words += fpr_words;
7342 n_words -= fpr_words;
7343
7344 do
7345 {
7346 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
7347 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
7348 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7349 }
7350 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
7351
7352 if (!warned && warn_psabi)
7353 {
7354 warned = true;
7355 inform (input_location,
7356 "the ABI of passing homogeneous %<float%> aggregates"
7357 " has changed in GCC 5");
7358 }
7359 }
7360
7361 return rs6000_finish_function_arg (mode, rvec, k);
7362 }
7363 else if (align_words < GP_ARG_NUM_REG)
7364 {
7365 if (TARGET_32BIT && TARGET_POWERPC64)
7366 return rs6000_mixed_function_arg (mode, type, align_words);
7367
7368 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7369 }
7370 else
7371 return NULL_RTX;
7372 }
7373}
7374\f
7375/* For an arg passed partly in registers and partly in memory, this is
7376 the number of bytes passed in registers. For args passed entirely in
7377 registers or entirely in memory, zero. When an arg is described by a
7378 PARALLEL, perhaps using more than one register type, this function
7379 returns the number of bytes used by the first element of the PARALLEL. */
7380
7381int
a7c81bc1
RS		 7382rs6000_arg_partial_bytes (cumulative_args_t cum_v,
7383 const function_arg_info &arg)
1acf0246
BS		 7384{
7385 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7386 bool passed_in_gprs = true;
7387 int ret = 0;
7388 int align_words;
7389 machine_mode elt_mode;
7390 int n_elts;
7391
a7c81bc1
RS		 7392 rs6000_discover_homogeneous_aggregate (arg.mode, arg.type,
7393 &elt_mode, &n_elts);
1acf0246
BS		 7394
7395 if (DEFAULT_ABI == ABI_V4)
7396 return 0;
7397
a7c81bc1 7398 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, arg.named))
1acf0246
BS		 7399 {
7400 /* If we are passing this arg in the fixed parameter save area (gprs or
7401 memory) as well as VRs, we do not use the partial bytes mechanism;
7402 instead, rs6000_function_arg will return a PARALLEL including a memory
7403 element as necessary. Library support functions for IEEE 128-bit are
7404 assumed to not need the value passed both in GPRs and in vector
7405 registers. */
7406 if (TARGET_64BIT && !cum->prototype
7407 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
7408 return 0;
7409
7410 /* Otherwise, we pass in VRs only. Check for partial copies. */
7411 passed_in_gprs = false;
7412 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
7413 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
7414 }
7415
7416 /* In this complicated case we just disable the partial_nregs code. */
a7c81bc1 7417 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (arg.mode, arg.type))
1acf0246
BS		 7418 return 0;
7419
a7c81bc1 7420 align_words = rs6000_parm_start (arg.mode, arg.type, cum->words);
1acf0246
BS		 7421
7422 if (USE_FP_FOR_ARG_P (cum, elt_mode)
a7c81bc1 7423 && !(TARGET_AIX && !TARGET_ELF && arg.aggregate_type_p ()))
1acf0246
BS		 7424 {
7425 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
7426
7427 /* If we are passing this arg in the fixed parameter save area
7428 (gprs or memory) as well as FPRs, we do not use the partial
7429 bytes mechanism; instead, rs6000_function_arg will return a
7430 PARALLEL including a memory element as necessary. */
a7c81bc1 7431 if (arg.type
1acf0246
BS		 7432 && (cum->nargs_prototype <= 0
7433 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7434 && TARGET_XL_COMPAT
7435 && align_words >= GP_ARG_NUM_REG)))
7436 return 0;
7437
7438 /* Otherwise, we pass in FPRs only. Check for partial copies. */
7439 passed_in_gprs = false;
7440 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
7441 {
7442 /* Compute number of bytes / words passed in FPRs. If there
7443 is still space available in the register parameter area
7444 *after* that amount, a part of the argument will be passed
7445 in GPRs. In that case, the total amount passed in any
7446 registers is equal to the amount that would have been passed
7447 in GPRs if everything were passed there, so we fall back to
7448 the GPR code below to compute the appropriate value. */
7449 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
7450 * MIN (8, GET_MODE_SIZE (elt_mode)));
7451 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
7452
7453 if (align_words + fpr_words < GP_ARG_NUM_REG)
7454 passed_in_gprs = true;
7455 else
7456 ret = fpr;
7457 }
7458 }
7459
7460 if (passed_in_gprs
7461 && align_words < GP_ARG_NUM_REG
a7c81bc1 7462 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (arg.mode, arg.type))
1acf0246
BS		 7463 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
7464
7465 if (ret != 0 && TARGET_DEBUG_ARG)
7466 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
7467
7468 return ret;
7469}
7470\f
7471/* A C expression that indicates when an argument must be passed by
7472 reference. If nonzero for an argument, a copy of that argument is
7473 made in memory and a pointer to the argument is passed instead of
7474 the argument itself. The pointer is passed in whatever way is
7475 appropriate for passing a pointer to that type.
7476
7477 Under V.4, aggregates and long double are passed by reference.
7478
7479 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
7480 reference unless the AltiVec vector extension ABI is in force.
7481
7482 As an extension to all ABIs, variable sized types are passed by
7483 reference. */
7484
7485bool
52090e4d 7486rs6000_pass_by_reference (cumulative_args_t, const function_arg_info &arg)
1acf0246 7487{
52090e4d 7488 if (!arg.type)
1acf0246
BS		 7489 return 0;
7490
7491 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
52090e4d 7492 && FLOAT128_IEEE_P (TYPE_MODE (arg.type)))
1acf0246
BS		 7493 {
7494 if (TARGET_DEBUG_ARG)
7495 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
7496 return 1;
7497 }
7498
52090e4d 7499 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (arg.type))
1acf0246
BS		 7500 {
7501 if (TARGET_DEBUG_ARG)
7502 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
7503 return 1;
7504 }
7505
52090e4d 7506 if (int_size_in_bytes (arg.type) < 0)
1acf0246
BS		 7507 {
7508 if (TARGET_DEBUG_ARG)
7509 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
7510 return 1;
7511 }
7512
7513 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7514 modes only exist for GCC vector types if -maltivec. */
52090e4d 7515 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (arg.mode))
1acf0246
BS		 7516 {
7517 if (TARGET_DEBUG_ARG)
7518 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
7519 return 1;
7520 }
7521
7522 /* Pass synthetic vectors in memory. */
52090e4d
RS		 7523 if (TREE_CODE (arg.type) == VECTOR_TYPE
7524 && int_size_in_bytes (arg.type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
1acf0246
BS		 7525 {
7526 static bool warned_for_pass_big_vectors = false;
7527 if (TARGET_DEBUG_ARG)
7528 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
7529 if (!warned_for_pass_big_vectors)
7530 {
7531 warning (OPT_Wpsabi, "GCC vector passed by reference: "
7532 "non-standard ABI extension with no compatibility "
7533 "guarantee");
7534 warned_for_pass_big_vectors = true;
7535 }
7536 return 1;
7537 }
7538
7539 return 0;
7540}
7541
7542/* Process parameter of type TYPE after ARGS_SO_FAR parameters were
7543 already processes. Return true if the parameter must be passed
7544 (fully or partially) on the stack. */
7545
7546static bool
7547rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
7548{
1acf0246
BS		 7549 int unsignedp;
7550 rtx entry_parm;
7551
7552 /* Catch errors. */
7553 if (type == NULL || type == error_mark_node)
7554 return true;
7555
7556 /* Handle types with no storage requirement. */
7557 if (TYPE_MODE (type) == VOIDmode)
7558 return false;
7559
7560 /* Handle complex types. */
7561 if (TREE_CODE (type) == COMPLEX_TYPE)
7562 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
7563 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
7564
7565 /* Handle transparent aggregates. */
7566 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
7567 && TYPE_TRANSPARENT_AGGR (type))
7568 type = TREE_TYPE (first_field (type));
7569
7570 /* See if this arg was passed by invisible reference. */
b12cdd6e
RS		 7571 function_arg_info arg (type, /*named=*/true);
7572 apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg);
1acf0246
BS		 7573
7574 /* Find mode as it is passed by the ABI. */
7575 unsignedp = TYPE_UNSIGNED (type);
b12cdd6e 7576 arg.mode = promote_mode (arg.type, arg.mode, &unsignedp);
1acf0246
BS		 7577
7578 /* If we must pass in stack, we need a stack. */
0ffef200 7579 if (rs6000_must_pass_in_stack (arg))
1acf0246
BS		 7580 return true;
7581
7582 /* If there is no incoming register, we need a stack. */
6783fdb7 7583 entry_parm = rs6000_function_arg (args_so_far, arg);
1acf0246
BS		 7584 if (entry_parm == NULL)
7585 return true;
7586
7587 /* Likewise if we need to pass both in registers and on the stack. */
7588 if (GET_CODE (entry_parm) == PARALLEL
7589 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
7590 return true;
7591
7592 /* Also true if we're partially in registers and partially not. */
a7c81bc1 7593 if (rs6000_arg_partial_bytes (args_so_far, arg) != 0)
1acf0246
BS		 7594 return true;
7595
7596 /* Update info on where next arg arrives in registers. */
6930c98c 7597 rs6000_function_arg_advance (args_so_far, arg);
1acf0246
BS		 7598 return false;
7599}
7600
7601/* Return true if FUN has no prototype, has a variable argument
7602 list, or passes any parameter in memory. */
7603
7604static bool
7605rs6000_function_parms_need_stack (tree fun, bool incoming)
7606{
7607 tree fntype, result;
7608 CUMULATIVE_ARGS args_so_far_v;
7609 cumulative_args_t args_so_far;
7610
7611 if (!fun)
7612 /* Must be a libcall, all of which only use reg parms. */
7613 return false;
7614
7615 fntype = fun;
7616 if (!TYPE_P (fun))
7617 fntype = TREE_TYPE (fun);
7618
7619 /* Varargs functions need the parameter save area. */
7620 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
7621 return true;
7622
7623 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
7624 args_so_far = pack_cumulative_args (&args_so_far_v);
7625
7626 /* When incoming, we will have been passed the function decl.
7627 It is necessary to use the decl to handle K&R style functions,
7628 where TYPE_ARG_TYPES may not be available. */
7629 if (incoming)
7630 {
7631 gcc_assert (DECL_P (fun));
7632 result = DECL_RESULT (fun);
7633 }
7634 else
7635 result = TREE_TYPE (fntype);
7636
7637 if (result && aggregate_value_p (result, fntype))
7638 {
7639 if (!TYPE_P (result))
7640 result = TREE_TYPE (result);
7641 result = build_pointer_type (result);
7642 rs6000_parm_needs_stack (args_so_far, result);
7643 }
7644
7645 if (incoming)
7646 {
7647 tree parm;
7648
7649 for (parm = DECL_ARGUMENTS (fun);
7650 parm && parm != void_list_node;
7651 parm = TREE_CHAIN (parm))
7652 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
7653 return true;
7654 }
7655 else
7656 {
7657 function_args_iterator args_iter;
7658 tree arg_type;
7659
7660 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
7661 if (rs6000_parm_needs_stack (args_so_far, arg_type))
7662 return true;
7663 }
7664
7665 return false;
7666}
7667
7668/* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
7669 usually a constant depending on the ABI. However, in the ELFv2 ABI
7670 the register parameter area is optional when calling a function that
7671 has a prototype is scope, has no variable argument list, and passes
7672 all parameters in registers. */
7673
7674int
7675rs6000_reg_parm_stack_space (tree fun, bool incoming)
7676{
7677 int reg_parm_stack_space;
7678
7679 switch (DEFAULT_ABI)
7680 {
7681 default:
7682 reg_parm_stack_space = 0;
7683 break;
7684
7685 case ABI_AIX:
7686 case ABI_DARWIN:
7687 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
7688 break;
7689
7690 case ABI_ELFv2:
7691 /* ??? Recomputing this every time is a bit expensive. Is there
7692 a place to cache this information? */
7693 if (rs6000_function_parms_need_stack (fun, incoming))
7694 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
7695 else
7696 reg_parm_stack_space = 0;
7697 break;
7698 }
7699
7700 return reg_parm_stack_space;
7701}
7702
7703static void
7704rs6000_move_block_from_reg (int regno, rtx x, int nregs)
7705{
7706 int i;
7707 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
7708
7709 if (nregs == 0)
7710 return;
7711
7712 for (i = 0; i < nregs; i++)
7713 {
7714 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
7715 if (reload_completed)
7716 {
7717 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
7718 tem = NULL_RTX;
7719 else
7720 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
7721 i * GET_MODE_SIZE (reg_mode));
7722 }
7723 else
7724 tem = replace_equiv_address (tem, XEXP (tem, 0));
7725
7726 gcc_assert (tem);
7727
7728 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
7729 }
7730}
7731\f
7732/* Perform any needed actions needed for a function that is receiving a
7733 variable number of arguments.
7734
7735 CUM is as above.
7736
e7056ca4 7737 ARG is the last named argument.
1acf0246
BS		 7738
7739 PRETEND_SIZE is a variable that should be set to the amount of stack
7740 that must be pushed by the prolog to pretend that our caller pushed
7741 it.
7742
7743 Normally, this macro will push all remaining incoming registers on the
7744 stack and set PRETEND_SIZE to the length of the registers pushed. */
7745
7746void
e7056ca4
RS		 7747setup_incoming_varargs (cumulative_args_t cum,
7748 const function_arg_info &arg,
7749 int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
1acf0246
BS		 7750{
7751 CUMULATIVE_ARGS next_cum;
7752 int reg_size = TARGET_32BIT ? 4 : 8;
7753 rtx save_area = NULL_RTX, mem;
7754 int first_reg_offset;
7755 alias_set_type set;
7756
7757 /* Skip the last named argument. */
7758 next_cum = *get_cumulative_args (cum);
e7056ca4 7759 rs6000_function_arg_advance_1 (&next_cum, arg.mode, arg.type, arg.named, 0);
1acf0246
BS		 7760
7761 if (DEFAULT_ABI == ABI_V4)
7762 {
7763 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
7764
7765 if (! no_rtl)
7766 {
7767 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
7768 HOST_WIDE_INT offset = 0;
7769
7770 /* Try to optimize the size of the varargs save area.
7771 The ABI requires that ap.reg_save_area is doubleword
7772 aligned, but we don't need to allocate space for all
7773 the bytes, only those to which we actually will save
7774 anything. */
7775 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
7776 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
7777 if (TARGET_HARD_FLOAT
7778 && next_cum.fregno <= FP_ARG_V4_MAX_REG
7779 && cfun->va_list_fpr_size)
7780 {
7781 if (gpr_reg_num)
7782 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
7783 * UNITS_PER_FP_WORD;
7784 if (cfun->va_list_fpr_size
7785 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
7786 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
7787 else
7788 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
7789 * UNITS_PER_FP_WORD;
7790 }
7791 if (gpr_reg_num)
7792 {
7793 offset = -((first_reg_offset * reg_size) & ~7);
7794 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
7795 {
7796 gpr_reg_num = cfun->va_list_gpr_size;
7797 if (reg_size == 4 && (first_reg_offset & 1))
7798 gpr_reg_num++;
7799 }
7800 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
7801 }
7802 else if (fpr_size)
7803 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
7804 * UNITS_PER_FP_WORD
7805 - (int) (GP_ARG_NUM_REG * reg_size);
7806
7807 if (gpr_size + fpr_size)
7808 {
7809 rtx reg_save_area
7810 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
7811 gcc_assert (MEM_P (reg_save_area));
7812 reg_save_area = XEXP (reg_save_area, 0);
7813 if (GET_CODE (reg_save_area) == PLUS)
7814 {
7815 gcc_assert (XEXP (reg_save_area, 0)
7816 == virtual_stack_vars_rtx);
7817 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
7818 offset += INTVAL (XEXP (reg_save_area, 1));
7819 }
7820 else
7821 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
7822 }
7823
7824 cfun->machine->varargs_save_offset = offset;
7825 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
7826 }
7827 }
7828 else
7829 {
7830 first_reg_offset = next_cum.words;
7831 save_area = crtl->args.internal_arg_pointer;
7832
0ffef200 7833 if (targetm.calls.must_pass_in_stack (arg))
e7056ca4 7834 first_reg_offset += rs6000_arg_size (TYPE_MODE (arg.type), arg.type);
1acf0246
BS		 7835 }
7836
7837 set = get_varargs_alias_set ();
7838 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
7839 && cfun->va_list_gpr_size)
7840 {
7841 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
7842
7843 if (va_list_gpr_counter_field)
7844 /* V4 va_list_gpr_size counts number of registers needed. */
7845 n_gpr = cfun->va_list_gpr_size;
7846 else
7847 /* char * va_list instead counts number of bytes needed. */
7848 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
7849
7850 if (nregs > n_gpr)
7851 nregs = n_gpr;
7852
7853 mem = gen_rtx_MEM (BLKmode,
7854 plus_constant (Pmode, save_area,
7855 first_reg_offset * reg_size));
7856 MEM_NOTRAP_P (mem) = 1;
7857 set_mem_alias_set (mem, set);
7858 set_mem_align (mem, BITS_PER_WORD);
7859
7860 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
7861 nregs);
7862 }
7863
7864 /* Save FP registers if needed. */
7865 if (DEFAULT_ABI == ABI_V4
7866 && TARGET_HARD_FLOAT
7867 && ! no_rtl
7868 && next_cum.fregno <= FP_ARG_V4_MAX_REG
7869 && cfun->va_list_fpr_size)
7870 {
7871 int fregno = next_cum.fregno, nregs;
7872 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
7873 rtx lab = gen_label_rtx ();
7874 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
7875 * UNITS_PER_FP_WORD);
7876
7877 emit_jump_insn
7878 (gen_rtx_SET (pc_rtx,
7879 gen_rtx_IF_THEN_ELSE (VOIDmode,
7880 gen_rtx_NE (VOIDmode, cr1,
7881 const0_rtx),
7882 gen_rtx_LABEL_REF (VOIDmode, lab),
7883 pc_rtx)));
7884
7885 for (nregs = 0;
7886 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
7887 fregno++, off += UNITS_PER_FP_WORD, nregs++)
7888 {
7889 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
7890 plus_constant (Pmode, save_area, off));
7891 MEM_NOTRAP_P (mem) = 1;
7892 set_mem_alias_set (mem, set);
7893 set_mem_align (mem, GET_MODE_ALIGNMENT (
7894 TARGET_HARD_FLOAT ? DFmode : SFmode));
7895 emit_move_insn (mem, gen_rtx_REG (
7896 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
7897 }
7898
7899 emit_label (lab);
7900 }
7901}
7902
7903/* Create the va_list data type. */
7904
7905tree
7906rs6000_build_builtin_va_list (void)
7907{
7908 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
7909
7910 /* For AIX, prefer 'char *' because that's what the system
7911 header files like. */
7912 if (DEFAULT_ABI != ABI_V4)
7913 return build_pointer_type (char_type_node);
7914
7915 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7916 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
7917 get_identifier ("__va_list_tag"), record);
7918
7919 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
7920 unsigned_char_type_node);
7921 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
7922 unsigned_char_type_node);
7923 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
7924 every user file. */
7925 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
7926 get_identifier ("reserved"), short_unsigned_type_node);
7927 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
7928 get_identifier ("overflow_arg_area"),
7929 ptr_type_node);
7930 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
7931 get_identifier ("reg_save_area"),
7932 ptr_type_node);
7933
7934 va_list_gpr_counter_field = f_gpr;
7935 va_list_fpr_counter_field = f_fpr;
7936
7937 DECL_FIELD_CONTEXT (f_gpr) = record;
7938 DECL_FIELD_CONTEXT (f_fpr) = record;
7939 DECL_FIELD_CONTEXT (f_res) = record;
7940 DECL_FIELD_CONTEXT (f_ovf) = record;
7941 DECL_FIELD_CONTEXT (f_sav) = record;
7942
7943 TYPE_STUB_DECL (record) = type_decl;
7944 TYPE_NAME (record) = type_decl;
7945 TYPE_FIELDS (record) = f_gpr;
7946 DECL_CHAIN (f_gpr) = f_fpr;
7947 DECL_CHAIN (f_fpr) = f_res;
7948 DECL_CHAIN (f_res) = f_ovf;
7949 DECL_CHAIN (f_ovf) = f_sav;
7950
7951 layout_type (record);
7952
7953 /* The correct type is an array type of one element. */
7954 return build_array_type (record, build_index_type (size_zero_node));
7955}
7956
7957/* Implement va_start. */
7958
7959void
7960rs6000_va_start (tree valist, rtx nextarg)
7961{
7962 HOST_WIDE_INT words, n_gpr, n_fpr;
7963 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
7964 tree gpr, fpr, ovf, sav, t;
7965
7966 /* Only SVR4 needs something special. */
7967 if (DEFAULT_ABI != ABI_V4)
7968 {
7969 std_expand_builtin_va_start (valist, nextarg);
7970 return;
7971 }
7972
7973 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7974 f_fpr = DECL_CHAIN (f_gpr);
7975 f_res = DECL_CHAIN (f_fpr);
7976 f_ovf = DECL_CHAIN (f_res);
7977 f_sav = DECL_CHAIN (f_ovf);
7978
7979 valist = build_simple_mem_ref (valist);
7980 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7981 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
7982 f_fpr, NULL_TREE);
7983 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
7984 f_ovf, NULL_TREE);
7985 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
7986 f_sav, NULL_TREE);
7987
7988 /* Count number of gp and fp argument registers used. */
7989 words = crtl->args.info.words;
7990 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
7991 GP_ARG_NUM_REG);
7992 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
7993 FP_ARG_NUM_REG);
7994
7995 if (TARGET_DEBUG_ARG)
7996 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
7997 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
7998 words, n_gpr, n_fpr);
7999
8000 if (cfun->va_list_gpr_size)
8001 {
8002 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8003 build_int_cst (NULL_TREE, n_gpr));
8004 TREE_SIDE_EFFECTS (t) = 1;
8005 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8006 }
8007
8008 if (cfun->va_list_fpr_size)
8009 {
8010 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8011 build_int_cst (NULL_TREE, n_fpr));
8012 TREE_SIDE_EFFECTS (t) = 1;
8013 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8014
8015#ifdef HAVE_AS_GNU_ATTRIBUTE
8016 if (call_ABI_of_interest (cfun->decl))
8017 rs6000_passes_float = true;
8018#endif
8019 }
8020
8021 /* Find the overflow area. */
8022 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
8023 if (words != 0)
8024 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
8025 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8026 TREE_SIDE_EFFECTS (t) = 1;
8027 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8028
8029 /* If there were no va_arg invocations, don't set up the register
8030 save area. */
8031 if (!cfun->va_list_gpr_size
8032 && !cfun->va_list_fpr_size
8033 && n_gpr < GP_ARG_NUM_REG
8034 && n_fpr < FP_ARG_V4_MAX_REG)
8035 return;
8036
8037 /* Find the register save area. */
8038 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
8039 if (cfun->machine->varargs_save_offset)
8040 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
8041 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8042 TREE_SIDE_EFFECTS (t) = 1;
8043 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8044}
8045
8046/* Implement va_arg. */
8047
8048tree
8049rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8050 gimple_seq *post_p)
8051{
8052 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
8053 tree gpr, fpr, ovf, sav, reg, t, u;
8054 int size, rsize, n_reg, sav_ofs, sav_scale;
8055 tree lab_false, lab_over, addr;
8056 int align;
8057 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
8058 int regalign = 0;
8059 gimple *stmt;
8060
fde65a89 8061 if (pass_va_arg_by_reference (type))
1acf0246
BS		 8062 {
8063 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
8064 return build_va_arg_indirect_ref (t);
8065 }
8066
8067 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
8068 earlier version of gcc, with the property that it always applied alignment
8069 adjustments to the va-args (even for zero-sized types). The cheapest way
8070 to deal with this is to replicate the effect of the part of
8071 std_gimplify_va_arg_expr that carries out the align adjust, for the case
8072 of relevance.
8073 We don't need to check for pass-by-reference because of the test above.
8074 We can return a simplifed answer, since we know there's no offset to add. */
8075
8076 if (((TARGET_MACHO
8077 && rs6000_darwin64_abi)
8078 || DEFAULT_ABI == ABI_ELFv2
8079 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
8080 && integer_zerop (TYPE_SIZE (type)))
8081 {
8082 unsigned HOST_WIDE_INT align, boundary;
8083 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
8084 align = PARM_BOUNDARY / BITS_PER_UNIT;
8085 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
8086 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
8087 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
8088 boundary /= BITS_PER_UNIT;
8089 if (boundary > align)
8090 {
8091 tree t ;
8092 /* This updates arg ptr by the amount that would be necessary
8093 to align the zero-sized (but not zero-alignment) item. */
8094 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
8095 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
8096 gimplify_and_add (t, pre_p);
8097
8098 t = fold_convert (sizetype, valist_tmp);
8099 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
8100 fold_convert (TREE_TYPE (valist),
8101 fold_build2 (BIT_AND_EXPR, sizetype, t,
8102 size_int (-boundary))));
8103 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
8104 gimplify_and_add (t, pre_p);
8105 }
8106 /* Since it is zero-sized there's no increment for the item itself. */
8107 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
8108 return build_va_arg_indirect_ref (valist_tmp);
8109 }
8110
8111 if (DEFAULT_ABI != ABI_V4)
8112 {
8113 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
8114 {
8115 tree elem_type = TREE_TYPE (type);
8116 machine_mode elem_mode = TYPE_MODE (elem_type);
8117 int elem_size = GET_MODE_SIZE (elem_mode);
8118
8119 if (elem_size < UNITS_PER_WORD)
8120 {
8121 tree real_part, imag_part;
8122 gimple_seq post = NULL;
8123
8124 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
8125 &post);
8126 /* Copy the value into a temporary, lest the formal temporary
8127 be reused out from under us. */
8128 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
8129 gimple_seq_add_seq (pre_p, post);
8130
8131 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
8132 post_p);
8133
8134 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
8135 }
8136 }
8137
8138 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
8139 }
8140
8141 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8142 f_fpr = DECL_CHAIN (f_gpr);
8143 f_res = DECL_CHAIN (f_fpr);
8144 f_ovf = DECL_CHAIN (f_res);
8145 f_sav = DECL_CHAIN (f_ovf);
8146
8147 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8148 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
8149 f_fpr, NULL_TREE);
8150 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
8151 f_ovf, NULL_TREE);
8152 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
8153 f_sav, NULL_TREE);
8154
8155 size = int_size_in_bytes (type);
8156 rsize = (size + 3) / 4;
8157 int pad = 4 * rsize - size;
8158 align = 1;
8159
8160 machine_mode mode = TYPE_MODE (type);
8161 if (abi_v4_pass_in_fpr (mode, false))
8162 {
8163 /* FP args go in FP registers, if present. */
8164 reg = fpr;
8165 n_reg = (size + 7) / 8;
8166 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
8167 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
8168 if (mode != SFmode && mode != SDmode)
8169 align = 8;
8170 }
8171 else
8172 {
8173 /* Otherwise into GP registers. */
8174 reg = gpr;
8175 n_reg = rsize;
8176 sav_ofs = 0;
8177 sav_scale = 4;
8178 if (n_reg == 2)
8179 align = 8;
8180 }
8181
8182 /* Pull the value out of the saved registers.... */
8183
8184 lab_over = NULL;
8185 addr = create_tmp_var (ptr_type_node, "addr");
8186
8187 /* AltiVec vectors never go in registers when -mabi=altivec. */
8188 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8189 align = 16;
8190 else
8191 {
8192 lab_false = create_artificial_label (input_location);
8193 lab_over = create_artificial_label (input_location);
8194
8195 /* Long long is aligned in the registers. As are any other 2 gpr
8196 item such as complex int due to a historical mistake. */
8197 u = reg;
8198 if (n_reg == 2 && reg == gpr)
8199 {
8200 regalign = 1;
8201 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8202 build_int_cst (TREE_TYPE (reg), n_reg - 1));
8203 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
8204 unshare_expr (reg), u);
8205 }
8206 /* _Decimal128 is passed in even/odd fpr pairs; the stored
8207 reg number is 0 for f1, so we want to make it odd. */
8208 else if (reg == fpr && mode == TDmode)
8209 {
8210 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8211 build_int_cst (TREE_TYPE (reg), 1));
8212 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
8213 }
8214
8215 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
8216 t = build2 (GE_EXPR, boolean_type_node, u, t);
8217 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8218 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8219 gimplify_and_add (t, pre_p);
8220
8221 t = sav;
8222 if (sav_ofs)
8223 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
8224
8225 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8226 build_int_cst (TREE_TYPE (reg), n_reg));
8227 u = fold_convert (sizetype, u);
8228 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
8229 t = fold_build_pointer_plus (t, u);
8230
8231 /* _Decimal32 varargs are located in the second word of the 64-bit
8232 FP register for 32-bit binaries. */
8233 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
8234 t = fold_build_pointer_plus_hwi (t, size);
8235
8236 /* Args are passed right-aligned. */
8237 if (BYTES_BIG_ENDIAN)
8238 t = fold_build_pointer_plus_hwi (t, pad);
8239
8240 gimplify_assign (addr, t, pre_p);
8241
8242 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8243
8244 stmt = gimple_build_label (lab_false);
8245 gimple_seq_add_stmt (pre_p, stmt);
8246
8247 if ((n_reg == 2 && !regalign) || n_reg > 2)
8248 {
8249 /* Ensure that we don't find any more args in regs.
8250 Alignment has taken care of for special cases. */
8251 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
8252 }
8253 }
8254
8255 /* ... otherwise out of the overflow area. */
8256
8257 /* Care for on-stack alignment if needed. */
8258 t = ovf;
8259 if (align != 1)
8260 {
8261 t = fold_build_pointer_plus_hwi (t, align - 1);
8262 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
8263 build_int_cst (TREE_TYPE (t), -align));
8264 }
8265
8266 /* Args are passed right-aligned. */
8267 if (BYTES_BIG_ENDIAN)
8268 t = fold_build_pointer_plus_hwi (t, pad);
8269
8270 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8271
8272 gimplify_assign (unshare_expr (addr), t, pre_p);
8273
8274 t = fold_build_pointer_plus_hwi (t, size);
8275 gimplify_assign (unshare_expr (ovf), t, pre_p);
8276
8277 if (lab_over)
8278 {
8279 stmt = gimple_build_label (lab_over);
8280 gimple_seq_add_stmt (pre_p, stmt);
8281 }
8282
8283 if (STRICT_ALIGNMENT
8284 && (TYPE_ALIGN (type)
8285 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
8286 {
8287 /* The value (of type complex double, for example) may not be
8288 aligned in memory in the saved registers, so copy via a
8289 temporary. (This is the same code as used for SPARC.) */
8290 tree tmp = create_tmp_var (type, "va_arg_tmp");
8291 tree dest_addr = build_fold_addr_expr (tmp);
8292
8293 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
8294 3, dest_addr, addr, size_int (rsize * 4));
8295 TREE_ADDRESSABLE (tmp) = 1;
8296
8297 gimplify_and_add (copy, pre_p);
8298 addr = dest_addr;
8299 }
8300
8301 addr = fold_convert (ptrtype, addr);
8302 return build_va_arg_indirect_ref (addr);
8303}
8304
8305/* Builtins. */
8306
8307static void
8308def_builtin (const char *name, tree type, enum rs6000_builtins code)
8309{
8310 tree t;
8311 unsigned classify = rs6000_builtin_info[(int)code].attr;
8312 const char *attr_string = "";
8313
a92cc0da
PB		 8314 /* Don't define the builtin if it doesn't have a type. See PR92661. */
8315 if (type == NULL_TREE)
8316 return;
8317
1acf0246
BS		 8318 gcc_assert (name != NULL);
8319 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
8320
8321 if (rs6000_builtin_decls[(int)code])
8322 fatal_error (input_location,
8323 "internal error: builtin function %qs already processed",
8324 name);
8325
8326 rs6000_builtin_decls[(int)code] = t =
8327 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
8328
8329 /* Set any special attributes. */
8330 if ((classify & RS6000_BTC_CONST) != 0)
8331 {
8332 /* const function, function only depends on the inputs. */
8333 TREE_READONLY (t) = 1;
8334 TREE_NOTHROW (t) = 1;
8335 attr_string = ", const";
8336 }
8337 else if ((classify & RS6000_BTC_PURE) != 0)
8338 {
8339 /* pure function, function can read global memory, but does not set any
8340 external state. */
8341 DECL_PURE_P (t) = 1;
8342 TREE_NOTHROW (t) = 1;
8343 attr_string = ", pure";
8344 }
8345 else if ((classify & RS6000_BTC_FP) != 0)
8346 {
8347 /* Function is a math function. If rounding mode is on, then treat the
8348 function as not reading global memory, but it can have arbitrary side
8349 effects. If it is off, then assume the function is a const function.
8350 This mimics the ATTR_MATHFN_FPROUNDING attribute in
8351 builtin-attribute.def that is used for the math functions. */
8352 TREE_NOTHROW (t) = 1;
8353 if (flag_rounding_math)
8354 {
8355 DECL_PURE_P (t) = 1;
8356 DECL_IS_NOVOPS (t) = 1;
8357 attr_string = ", fp, pure";
8358 }
8359 else
8360 {
8361 TREE_READONLY (t) = 1;
8362 attr_string = ", fp, const";
8363 }
8364 }
8ee2640b
PB		 8365 else if ((classify & (RS6000_BTC_QUAD | RS6000_BTC_PAIR)) != 0)
8366 /* The function uses a register quad and/or pair. Nothing to do. */
8367 ;
1acf0246
BS		 8368 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
8369 gcc_unreachable ();
8370
8371 if (TARGET_DEBUG_BUILTIN)
8372 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
8373 (int)code, name, attr_string);
8374}
8375
8376/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
8377
8378#undef RS6000_BUILTIN_0
8379#undef RS6000_BUILTIN_1
8380#undef RS6000_BUILTIN_2
8381#undef RS6000_BUILTIN_3
840ac85c 8382#undef RS6000_BUILTIN_4
1acf0246
BS		 8383#undef RS6000_BUILTIN_A
8384#undef RS6000_BUILTIN_D
8385#undef RS6000_BUILTIN_H
8ee2640b 8386#undef RS6000_BUILTIN_M
1acf0246
BS		 8387#undef RS6000_BUILTIN_P
8388#undef RS6000_BUILTIN_X
8389
8390#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8391#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8392#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8393#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
8394 { MASK, ICODE, NAME, ENUM },
8395
840ac85c 8396#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8397#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8398#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8399#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8400#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8401#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8402#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8403
8404static const struct builtin_description bdesc_3arg[] =
8405{
8406#include "rs6000-builtin.def"
8407};
8408
840ac85c
KN		 8409/* Simple quaternary operations: VECd = foo (VECa, VECb, VECc, VECd). */
8410
8411#undef RS6000_BUILTIN_0
8412#undef RS6000_BUILTIN_1
8413#undef RS6000_BUILTIN_2
8414#undef RS6000_BUILTIN_3
8415#undef RS6000_BUILTIN_4
8416#undef RS6000_BUILTIN_A
8417#undef RS6000_BUILTIN_D
8418#undef RS6000_BUILTIN_H
8ee2640b 8419#undef RS6000_BUILTIN_M
840ac85c
KN		 8420#undef RS6000_BUILTIN_P
8421#undef RS6000_BUILTIN_X
8422
8423#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8424#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8425#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8426#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8427#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) \
8428 { MASK, ICODE, NAME, ENUM },
8429
8430#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8431#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8432#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8433#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c
KN		 8434#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8435#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8436
8437static const struct builtin_description bdesc_4arg[] =
8438{
8439#include "rs6000-builtin.def"
8440};
8441
1acf0246
BS		 8442/* DST operations: void foo (void *, const int, const char). */
8443
8444#undef RS6000_BUILTIN_0
8445#undef RS6000_BUILTIN_1
8446#undef RS6000_BUILTIN_2
8447#undef RS6000_BUILTIN_3
840ac85c 8448#undef RS6000_BUILTIN_4
1acf0246
BS		 8449#undef RS6000_BUILTIN_A
8450#undef RS6000_BUILTIN_D
8451#undef RS6000_BUILTIN_H
8ee2640b 8452#undef RS6000_BUILTIN_M
1acf0246
BS		 8453#undef RS6000_BUILTIN_P
8454#undef RS6000_BUILTIN_X
8455
8456#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8457#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8458#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8459#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8460#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8461#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8462#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
8463 { MASK, ICODE, NAME, ENUM },
8464
8465#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8466#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8467#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8468#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8469
8470static const struct builtin_description bdesc_dst[] =
8471{
8472#include "rs6000-builtin.def"
8473};
8474
8475/* Simple binary operations: VECc = foo (VECa, VECb). */
8476
8477#undef RS6000_BUILTIN_0
8478#undef RS6000_BUILTIN_1
8479#undef RS6000_BUILTIN_2
8480#undef RS6000_BUILTIN_3
840ac85c 8481#undef RS6000_BUILTIN_4
1acf0246
BS		 8482#undef RS6000_BUILTIN_A
8483#undef RS6000_BUILTIN_D
8484#undef RS6000_BUILTIN_H
8ee2640b 8485#undef RS6000_BUILTIN_M
1acf0246
BS		 8486#undef RS6000_BUILTIN_P
8487#undef RS6000_BUILTIN_X
8488
8489#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8490#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8491#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
8492 { MASK, ICODE, NAME, ENUM },
8493
8494#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8495#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8496#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8497#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8498#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8499#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8500#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8501#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8502
8503static const struct builtin_description bdesc_2arg[] =
8504{
8505#include "rs6000-builtin.def"
8506};
8507
8508#undef RS6000_BUILTIN_0
8509#undef RS6000_BUILTIN_1
8510#undef RS6000_BUILTIN_2
8511#undef RS6000_BUILTIN_3
840ac85c 8512#undef RS6000_BUILTIN_4
1acf0246
BS		 8513#undef RS6000_BUILTIN_A
8514#undef RS6000_BUILTIN_D
8515#undef RS6000_BUILTIN_H
8ee2640b 8516#undef RS6000_BUILTIN_M
1acf0246
BS		 8517#undef RS6000_BUILTIN_P
8518#undef RS6000_BUILTIN_X
8519
8520#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8521#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8522#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8523#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8524#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8525#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8526#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8527#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8528#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8529#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
8530 { MASK, ICODE, NAME, ENUM },
8531
8532#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8533
8534/* AltiVec predicates. */
8535
8536static const struct builtin_description bdesc_altivec_preds[] =
8537{
8538#include "rs6000-builtin.def"
8539};
8540
8541/* ABS* operations. */
8542
8543#undef RS6000_BUILTIN_0
8544#undef RS6000_BUILTIN_1
8545#undef RS6000_BUILTIN_2
8546#undef RS6000_BUILTIN_3
840ac85c 8547#undef RS6000_BUILTIN_4
1acf0246
BS		 8548#undef RS6000_BUILTIN_A
8549#undef RS6000_BUILTIN_D
8550#undef RS6000_BUILTIN_H
8ee2640b 8551#undef RS6000_BUILTIN_M
1acf0246
BS		 8552#undef RS6000_BUILTIN_P
8553#undef RS6000_BUILTIN_X
8554
8555#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8556#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8557#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8558#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8559#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8560#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
8561 { MASK, ICODE, NAME, ENUM },
8562
8563#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8564#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8565#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8566#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8567#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8568
8569static const struct builtin_description bdesc_abs[] =
8570{
8571#include "rs6000-builtin.def"
8572};
8573
8574/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
8575 foo (VECa). */
8576
8577#undef RS6000_BUILTIN_0
8578#undef RS6000_BUILTIN_1
8579#undef RS6000_BUILTIN_2
8580#undef RS6000_BUILTIN_3
840ac85c 8581#undef RS6000_BUILTIN_4
1acf0246
BS		 8582#undef RS6000_BUILTIN_A
8583#undef RS6000_BUILTIN_D
8584#undef RS6000_BUILTIN_H
8ee2640b 8585#undef RS6000_BUILTIN_M
1acf0246
BS		 8586#undef RS6000_BUILTIN_P
8587#undef RS6000_BUILTIN_X
8588
8589#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8590#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
8591 { MASK, ICODE, NAME, ENUM },
8592
8593#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8594#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8595#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8596#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8597#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8598#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8599#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8600#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8601#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8602
8603static const struct builtin_description bdesc_1arg[] =
8604{
8605#include "rs6000-builtin.def"
8606};
8607
8608/* Simple no-argument operations: result = __builtin_darn_32 () */
8609
8610#undef RS6000_BUILTIN_0
8611#undef RS6000_BUILTIN_1
8612#undef RS6000_BUILTIN_2
8613#undef RS6000_BUILTIN_3
840ac85c 8614#undef RS6000_BUILTIN_4
1acf0246
BS		 8615#undef RS6000_BUILTIN_A
8616#undef RS6000_BUILTIN_D
8617#undef RS6000_BUILTIN_H
8ee2640b 8618#undef RS6000_BUILTIN_M
1acf0246
BS		 8619#undef RS6000_BUILTIN_P
8620#undef RS6000_BUILTIN_X
8621
8622#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
8623 { MASK, ICODE, NAME, ENUM },
8624
8625#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8626#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8627#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8628#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8629#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8630#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8631#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8632#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8633#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8634#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8635
8636static const struct builtin_description bdesc_0arg[] =
8637{
8638#include "rs6000-builtin.def"
8639};
8640
8641/* HTM builtins. */
8642#undef RS6000_BUILTIN_0
8643#undef RS6000_BUILTIN_1
8644#undef RS6000_BUILTIN_2
8645#undef RS6000_BUILTIN_3
840ac85c 8646#undef RS6000_BUILTIN_4
1acf0246
BS		 8647#undef RS6000_BUILTIN_A
8648#undef RS6000_BUILTIN_D
8649#undef RS6000_BUILTIN_H
8ee2640b 8650#undef RS6000_BUILTIN_M
1acf0246
BS		 8651#undef RS6000_BUILTIN_P
8652#undef RS6000_BUILTIN_X
8653
8654#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8655#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8656#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8657#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8658#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8659#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8660#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8661#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
8662 { MASK, ICODE, NAME, ENUM },
8663
8ee2640b 8664#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8665#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8666#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8667
8668static const struct builtin_description bdesc_htm[] =
8669{
8670#include "rs6000-builtin.def"
8671};
8672
8ee2640b 8673/* MMA builtins. */
1acf0246
BS		 8674#undef RS6000_BUILTIN_0
8675#undef RS6000_BUILTIN_1
8676#undef RS6000_BUILTIN_2
8677#undef RS6000_BUILTIN_3
840ac85c 8678#undef RS6000_BUILTIN_4
1acf0246
BS		 8679#undef RS6000_BUILTIN_A
8680#undef RS6000_BUILTIN_D
8681#undef RS6000_BUILTIN_H
8ee2640b 8682#undef RS6000_BUILTIN_M
1acf0246 8683#undef RS6000_BUILTIN_P
8ee2640b
PB		 8684#undef RS6000_BUILTIN_X
8685
8686#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8687#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8688#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8689#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8690#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
8691#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8692#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8693#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8694#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \
8695 { MASK, ICODE, NAME, ENUM },
8696
8697#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8698#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8699
8700static const struct builtin_description bdesc_mma[] =
8701{
8702#include "rs6000-builtin.def"
8703};
8704
8705#undef RS6000_BUILTIN_0
8706#undef RS6000_BUILTIN_1
8707#undef RS6000_BUILTIN_2
8708#undef RS6000_BUILTIN_3
8709#undef RS6000_BUILTIN_4
8710#undef RS6000_BUILTIN_A
8711#undef RS6000_BUILTIN_D
8712#undef RS6000_BUILTIN_H
8713#undef RS6000_BUILTIN_M
8714#undef RS6000_BUILTIN_P
8715#undef RS6000_BUILTIN_X
1acf0246
BS		 8716
8717/* Return true if a builtin function is overloaded. */
8718bool
8719rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
8720{
8721 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
8722}
8723
8724const char *
8725rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
8726{
8727 return rs6000_builtin_info[(int)fncode].name;
8728}
8729
8730/* Expand an expression EXP that calls a builtin without arguments. */
8731static rtx
8732rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
8733{
8734 rtx pat;
8735 machine_mode tmode = insn_data[icode].operand[0].mode;
8736
8737 if (icode == CODE_FOR_nothing)
8738 /* Builtin not supported on this processor. */
8739 return 0;
8740
8741 if (icode == CODE_FOR_rs6000_mffsl
8742 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
8743 {
8744 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
8745 return const0_rtx;
8746 }
8747
8748 if (target == 0
8749 || GET_MODE (target) != tmode
8750 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8751 target = gen_reg_rtx (tmode);
8752
8753 pat = GEN_FCN (icode) (target);
8754 if (! pat)
8755 return 0;
8756 emit_insn (pat);
8757
8758 return target;
8759}
8760
8761
8762static rtx
8763rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
8764{
8765 rtx pat;
8766 tree arg0 = CALL_EXPR_ARG (exp, 0);
8767 tree arg1 = CALL_EXPR_ARG (exp, 1);
8768 rtx op0 = expand_normal (arg0);
8769 rtx op1 = expand_normal (arg1);
8770 machine_mode mode0 = insn_data[icode].operand[0].mode;
8771 machine_mode mode1 = insn_data[icode].operand[1].mode;
8772
8773 if (icode == CODE_FOR_nothing)
8774 /* Builtin not supported on this processor. */
8775 return 0;
8776
8777 /* If we got invalid arguments bail out before generating bad rtl. */
8778 if (arg0 == error_mark_node || arg1 == error_mark_node)
8779 return const0_rtx;
8780
8781 if (!CONST_INT_P (op0)
8782 || INTVAL (op0) > 255
8783 || INTVAL (op0) < 0)
8784 {
8785 error ("argument 1 must be an 8-bit field value");
8786 return const0_rtx;
8787 }
8788
8789 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8790 op0 = copy_to_mode_reg (mode0, op0);
8791
8792 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8793 op1 = copy_to_mode_reg (mode1, op1);
8794
8795 pat = GEN_FCN (icode) (op0, op1);
8796 if (!pat)
8797 return const0_rtx;
8798 emit_insn (pat);
8799
8800 return NULL_RTX;
8801}
8802
8803static rtx
8804rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
8805{
8806 rtx pat;
8807 tree arg0 = CALL_EXPR_ARG (exp, 0);
8808 rtx op0 = expand_normal (arg0);
8809
8810 if (icode == CODE_FOR_nothing)
8811 /* Builtin not supported on this processor. */
8812 return 0;
8813
8814 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
8815 {
8816 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
8817 "%<-msoft-float%>");
8818 return const0_rtx;
8819 }
8820
8821 /* If we got invalid arguments bail out before generating bad rtl. */
8822 if (arg0 == error_mark_node)
8823 return const0_rtx;
8824
8825 /* Only allow bit numbers 0 to 31. */
8826 if (!u5bit_cint_operand (op0, VOIDmode))
8827 {
8828 error ("Argument must be a constant between 0 and 31.");
8829 return const0_rtx;
8830 }
8831
8832 pat = GEN_FCN (icode) (op0);
8833 if (!pat)
8834 return const0_rtx;
8835 emit_insn (pat);
8836
8837 return NULL_RTX;
8838}
8839
8840static rtx
8841rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
8842{
8843 rtx pat;
8844 tree arg0 = CALL_EXPR_ARG (exp, 0);
8845 rtx op0 = expand_normal (arg0);
8846 machine_mode mode0 = insn_data[icode].operand[0].mode;
8847
8848 if (icode == CODE_FOR_nothing)
8849 /* Builtin not supported on this processor. */
8850 return 0;
8851
8852 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
8853 {
8854 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
8855 return const0_rtx;
8856 }
8857
8858 /* If we got invalid arguments bail out before generating bad rtl. */
8859 if (arg0 == error_mark_node)
8860 return const0_rtx;
8861
8862 /* If the argument is a constant, check the range. Argument can only be a
8863 2-bit value. Unfortunately, can't check the range of the value at
8864 compile time if the argument is a variable. The least significant two
8865 bits of the argument, regardless of type, are used to set the rounding
8866 mode. All other bits are ignored. */
8867 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
8868 {
8869 error ("Argument must be a value between 0 and 3.");
8870 return const0_rtx;
8871 }
8872
8873 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8874 op0 = copy_to_mode_reg (mode0, op0);
8875
8876 pat = GEN_FCN (icode) (op0);
8877 if (!pat)
8878 return const0_rtx;
8879 emit_insn (pat);
8880
8881 return NULL_RTX;
8882}
8883static rtx
8884rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
8885{
8886 rtx pat;
8887 tree arg0 = CALL_EXPR_ARG (exp, 0);
8888 rtx op0 = expand_normal (arg0);
8889 machine_mode mode0 = insn_data[icode].operand[0].mode;
8890
8891 if (TARGET_32BIT)
8892 /* Builtin not supported in 32-bit mode. */
8893 fatal_error (input_location,
8894 "%<__builtin_set_fpscr_drn%> is not supported "
8895 "in 32-bit mode");
8896
8897 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
8898 {
8899 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
8900 return const0_rtx;
8901 }
8902
8903 if (icode == CODE_FOR_nothing)
8904 /* Builtin not supported on this processor. */
8905 return 0;
8906
8907 /* If we got invalid arguments bail out before generating bad rtl. */
8908 if (arg0 == error_mark_node)
8909 return const0_rtx;
8910
8911 /* If the argument is a constant, check the range. Agrument can only be a
8912 3-bit value. Unfortunately, can't check the range of the value at
8913 compile time if the argument is a variable. The least significant two
8914 bits of the argument, regardless of type, are used to set the rounding
8915 mode. All other bits are ignored. */
8916 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode))
8917 {
8918 error ("Argument must be a value between 0 and 7.");
8919 return const0_rtx;
8920 }
8921
8922 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8923 op0 = copy_to_mode_reg (mode0, op0);
8924
8925 pat = GEN_FCN (icode) (op0);
8926 if (! pat)
8927 return const0_rtx;
8928 emit_insn (pat);
8929
8930 return NULL_RTX;
8931}
8932
8933static rtx
8934rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
8935{
8936 rtx pat;
8937 tree arg0 = CALL_EXPR_ARG (exp, 0);
8938 rtx op0 = expand_normal (arg0);
8939 machine_mode tmode = insn_data[icode].operand[0].mode;
8940 machine_mode mode0 = insn_data[icode].operand[1].mode;
8941
8942 if (icode == CODE_FOR_nothing)
8943 /* Builtin not supported on this processor. */
8944 return 0;
8945
8946 /* If we got invalid arguments bail out before generating bad rtl. */
8947 if (arg0 == error_mark_node)
8948 return const0_rtx;
8949
8950 if (icode == CODE_FOR_altivec_vspltisb
8951 || icode == CODE_FOR_altivec_vspltish
8952 || icode == CODE_FOR_altivec_vspltisw)
8953 {
8954 /* Only allow 5-bit *signed* literals. */
8955 if (!CONST_INT_P (op0)
8956 || INTVAL (op0) > 15
8957 || INTVAL (op0) < -16)
8958 {
8959 error ("argument 1 must be a 5-bit signed literal");
8960 return CONST0_RTX (tmode);
8961 }
8962 }
8963
8964 if (target == 0
8965 || GET_MODE (target) != tmode
8966 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8967 target = gen_reg_rtx (tmode);
8968
8969 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8970 op0 = copy_to_mode_reg (mode0, op0);
8971
8972 pat = GEN_FCN (icode) (target, op0);
8973 if (! pat)
8974 return 0;
8975 emit_insn (pat);
8976
8977 return target;
8978}
8979
8980static rtx
8981altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
8982{
8983 rtx pat, scratch1, scratch2;
8984 tree arg0 = CALL_EXPR_ARG (exp, 0);
8985 rtx op0 = expand_normal (arg0);
8986 machine_mode tmode = insn_data[icode].operand[0].mode;
8987 machine_mode mode0 = insn_data[icode].operand[1].mode;
8988
8989 /* If we have invalid arguments, bail out before generating bad rtl. */
8990 if (arg0 == error_mark_node)
8991 return const0_rtx;
8992
8993 if (target == 0
8994 || GET_MODE (target) != tmode
8995 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8996 target = gen_reg_rtx (tmode);
8997
8998 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8999 op0 = copy_to_mode_reg (mode0, op0);
9000
9001 scratch1 = gen_reg_rtx (mode0);
9002 scratch2 = gen_reg_rtx (mode0);
9003
9004 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9005 if (! pat)
9006 return 0;
9007 emit_insn (pat);
9008
9009 return target;
9010}
9011
9012static rtx
9013rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
9014{
9015 rtx pat;
9016 tree arg0 = CALL_EXPR_ARG (exp, 0);
9017 tree arg1 = CALL_EXPR_ARG (exp, 1);
9018 rtx op0 = expand_normal (arg0);
9019 rtx op1 = expand_normal (arg1);
9020 machine_mode tmode = insn_data[icode].operand[0].mode;
9021 machine_mode mode0 = insn_data[icode].operand[1].mode;
9022 machine_mode mode1 = insn_data[icode].operand[2].mode;
9023
9024 if (icode == CODE_FOR_nothing)
9025 /* Builtin not supported on this processor. */
9026 return 0;
9027
9028 /* If we got invalid arguments bail out before generating bad rtl. */
9029 if (arg0 == error_mark_node || arg1 == error_mark_node)
9030 return const0_rtx;
9031
9032 if (icode == CODE_FOR_unpackv1ti
9033 || icode == CODE_FOR_unpackkf
9034 || icode == CODE_FOR_unpacktf
9035 || icode == CODE_FOR_unpackif
9036 || icode == CODE_FOR_unpacktd)
9037 {
9038 /* Only allow 1-bit unsigned literals. */
9039 STRIP_NOPS (arg1);
9040 if (TREE_CODE (arg1) != INTEGER_CST
9041 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
9042 {
9043 error ("argument 2 must be a 1-bit unsigned literal");
9044 return CONST0_RTX (tmode);
9045 }
9046 }
9047 else if (icode == CODE_FOR_altivec_vspltw)
9048 {
9049 /* Only allow 2-bit unsigned literals. */
9050 STRIP_NOPS (arg1);
9051 if (TREE_CODE (arg1) != INTEGER_CST
9052 || TREE_INT_CST_LOW (arg1) & ~3)
9053 {
9054 error ("argument 2 must be a 2-bit unsigned literal");
9055 return CONST0_RTX (tmode);
9056 }
9057 }
7c00c559
KN		 9058 else if (icode == CODE_FOR_vgnb)
9059 {
9060 /* Only allow unsigned literals in range 2..7. */
9061 /* Note that arg1 is second operand. */
9062 STRIP_NOPS (arg1);
9063 if (TREE_CODE (arg1) != INTEGER_CST
9064 || (TREE_INT_CST_LOW (arg1) & ~7)
9065 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 2, 7))
9066 {
9067 error ("argument 2 must be unsigned literal between "
9068 "2 and 7 inclusive");
9069 return CONST0_RTX (tmode);
9070 }
9071 }
1acf0246
BS		 9072 else if (icode == CODE_FOR_altivec_vsplth)
9073 {
9074 /* Only allow 3-bit unsigned literals. */
9075 STRIP_NOPS (arg1);
9076 if (TREE_CODE (arg1) != INTEGER_CST
9077 || TREE_INT_CST_LOW (arg1) & ~7)
9078 {
9079 error ("argument 2 must be a 3-bit unsigned literal");
9080 return CONST0_RTX (tmode);
9081 }
9082 }
9083 else if (icode == CODE_FOR_altivec_vspltb)
9084 {
9085 /* Only allow 4-bit unsigned literals. */
9086 STRIP_NOPS (arg1);
9087 if (TREE_CODE (arg1) != INTEGER_CST
9088 || TREE_INT_CST_LOW (arg1) & ~15)
9089 {
9090 error ("argument 2 must be a 4-bit unsigned literal");
9091 return CONST0_RTX (tmode);
9092 }
9093 }
9094 else if (icode == CODE_FOR_altivec_vcfux
9095 || icode == CODE_FOR_altivec_vcfsx
9096 || icode == CODE_FOR_altivec_vctsxs
9097 || icode == CODE_FOR_altivec_vctuxs)
9098 {
9099 /* Only allow 5-bit unsigned literals. */
9100 STRIP_NOPS (arg1);
9101 if (TREE_CODE (arg1) != INTEGER_CST
9102 || TREE_INT_CST_LOW (arg1) & ~0x1f)
9103 {
9104 error ("argument 2 must be a 5-bit unsigned literal");
9105 return CONST0_RTX (tmode);
9106 }
9107 }
9108 else if (icode == CODE_FOR_dfptstsfi_eq_dd
9109 || icode == CODE_FOR_dfptstsfi_lt_dd
9110 || icode == CODE_FOR_dfptstsfi_gt_dd
9111 || icode == CODE_FOR_dfptstsfi_unordered_dd
9112 || icode == CODE_FOR_dfptstsfi_eq_td
9113 || icode == CODE_FOR_dfptstsfi_lt_td
9114 || icode == CODE_FOR_dfptstsfi_gt_td
9115 || icode == CODE_FOR_dfptstsfi_unordered_td)
9116 {
9117 /* Only allow 6-bit unsigned literals. */
9118 STRIP_NOPS (arg0);
9119 if (TREE_CODE (arg0) != INTEGER_CST
9120 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
9121 {
9122 error ("argument 1 must be a 6-bit unsigned literal");
9123 return CONST0_RTX (tmode);
9124 }
9125 }
9126 else if (icode == CODE_FOR_xststdcqp_kf
9127 || icode == CODE_FOR_xststdcqp_tf
9128 || icode == CODE_FOR_xststdcdp
9129 || icode == CODE_FOR_xststdcsp
9130 || icode == CODE_FOR_xvtstdcdp
9131 || icode == CODE_FOR_xvtstdcsp)
9132 {
9133 /* Only allow 7-bit unsigned literals. */
9134 STRIP_NOPS (arg1);
9135 if (TREE_CODE (arg1) != INTEGER_CST
9136 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
9137 {
9138 error ("argument 2 must be a 7-bit unsigned literal");
9139 return CONST0_RTX (tmode);
9140 }
9141 }
9142
9143 if (target == 0
9144 || GET_MODE (target) != tmode
9145 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9146 target = gen_reg_rtx (tmode);
9147
9148 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9149 op0 = copy_to_mode_reg (mode0, op0);
9150 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9151 op1 = copy_to_mode_reg (mode1, op1);
9152
9153 pat = GEN_FCN (icode) (target, op0, op1);
9154 if (! pat)
9155 return 0;
9156 emit_insn (pat);
9157
9158 return target;
9159}
9160
9161static rtx
9162altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9163{
9164 rtx pat, scratch;
9165 tree cr6_form = CALL_EXPR_ARG (exp, 0);
9166 tree arg0 = CALL_EXPR_ARG (exp, 1);
9167 tree arg1 = CALL_EXPR_ARG (exp, 2);
9168 rtx op0 = expand_normal (arg0);
9169 rtx op1 = expand_normal (arg1);
9170 machine_mode tmode = SImode;
9171 machine_mode mode0 = insn_data[icode].operand[1].mode;
9172 machine_mode mode1 = insn_data[icode].operand[2].mode;
9173 int cr6_form_int;
9174
9175 if (TREE_CODE (cr6_form) != INTEGER_CST)
9176 {
9177 error ("argument 1 of %qs must be a constant",
9178 "__builtin_altivec_predicate");
9179 return const0_rtx;
9180 }
9181 else
9182 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
9183
9184 gcc_assert (mode0 == mode1);
9185
9186 /* If we have invalid arguments, bail out before generating bad rtl. */
9187 if (arg0 == error_mark_node || arg1 == error_mark_node)
9188 return const0_rtx;
9189
9190 if (target == 0
9191 || GET_MODE (target) != tmode
9192 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9193 target = gen_reg_rtx (tmode);
9194
9195 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9196 op0 = copy_to_mode_reg (mode0, op0);
9197 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9198 op1 = copy_to_mode_reg (mode1, op1);
9199
9200 /* Note that for many of the relevant operations (e.g. cmpne or
9201 cmpeq) with float or double operands, it makes more sense for the
9202 mode of the allocated scratch register to select a vector of
9203 integer. But the choice to copy the mode of operand 0 was made
9204 long ago and there are no plans to change it. */
9205 scratch = gen_reg_rtx (mode0);
9206
9207 pat = GEN_FCN (icode) (scratch, op0, op1);
9208 if (! pat)
9209 return 0;
9210 emit_insn (pat);
9211
9212 /* The vec_any* and vec_all* predicates use the same opcodes for two
9213 different operations, but the bits in CR6 will be different
9214 depending on what information we want. So we have to play tricks
9215 with CR6 to get the right bits out.
9216
9217 If you think this is disgusting, look at the specs for the
9218 AltiVec predicates. */
9219
9220 switch (cr6_form_int)
9221 {
9222 case 0:
9223 emit_insn (gen_cr6_test_for_zero (target));
9224 break;
9225 case 1:
9226 emit_insn (gen_cr6_test_for_zero_reverse (target));
9227 break;
9228 case 2:
9229 emit_insn (gen_cr6_test_for_lt (target));
9230 break;
9231 case 3:
9232 emit_insn (gen_cr6_test_for_lt_reverse (target));
9233 break;
9234 default:
9235 error ("argument 1 of %qs is out of range",
9236 "__builtin_altivec_predicate");
9237 break;
9238 }
9239
9240 return target;
9241}
9242
9243rtx
9244swap_endian_selector_for_mode (machine_mode mode)
9245{
9246 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
9247 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
9248 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
9249 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
9250
9251 unsigned int *swaparray, i;
9252 rtx perm[16];
9253
9254 switch (mode)
9255 {
9256 case E_V1TImode:
9257 swaparray = swap1;
9258 break;
9259 case E_V2DFmode:
9260 case E_V2DImode:
9261 swaparray = swap2;
9262 break;
9263 case E_V4SFmode:
9264 case E_V4SImode:
9265 swaparray = swap4;
9266 break;
9267 case E_V8HImode:
9268 swaparray = swap8;
9269 break;
9270 default:
9271 gcc_unreachable ();
9272 }
9273
9274 for (i = 0; i < 16; ++i)
9275 perm[i] = GEN_INT (swaparray[i]);
9276
9277 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
9278 gen_rtvec_v (16, perm)));
9279}
9280
9281static rtx
9282altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
9283{
9284 rtx pat, addr;
9285 tree arg0 = CALL_EXPR_ARG (exp, 0);
9286 tree arg1 = CALL_EXPR_ARG (exp, 1);
9287 machine_mode tmode = insn_data[icode].operand[0].mode;
9288 machine_mode mode0 = Pmode;
9289 machine_mode mode1 = Pmode;
9290 rtx op0 = expand_normal (arg0);
9291 rtx op1 = expand_normal (arg1);
9292
9293 if (icode == CODE_FOR_nothing)
9294 /* Builtin not supported on this processor. */
9295 return 0;
9296
9297 /* If we got invalid arguments bail out before generating bad rtl. */
9298 if (arg0 == error_mark_node || arg1 == error_mark_node)
9299 return const0_rtx;
9300
9301 if (target == 0
9302 || GET_MODE (target) != tmode
9303 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9304 target = gen_reg_rtx (tmode);
9305
9306 op1 = copy_to_mode_reg (mode1, op1);
9307
9308 /* For LVX, express the RTL accurately by ANDing the address with -16.
9309 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
9310 so the raw address is fine. */
9311 if (icode == CODE_FOR_altivec_lvx_v1ti
9312 || icode == CODE_FOR_altivec_lvx_v2df
9313 || icode == CODE_FOR_altivec_lvx_v2di
9314 || icode == CODE_FOR_altivec_lvx_v4sf
9315 || icode == CODE_FOR_altivec_lvx_v4si
9316 || icode == CODE_FOR_altivec_lvx_v8hi
9317 || icode == CODE_FOR_altivec_lvx_v16qi)
9318 {
9319 rtx rawaddr;
9320 if (op0 == const0_rtx)
9321 rawaddr = op1;
9322 else
9323 {
9324 op0 = copy_to_mode_reg (mode0, op0);
9325 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
9326 }
9327 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
9328 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
9329
9330 emit_insn (gen_rtx_SET (target, addr));
9331 }
9332 else
9333 {
9334 if (op0 == const0_rtx)
9335 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
9336 else
9337 {
9338 op0 = copy_to_mode_reg (mode0, op0);
9339 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
9340 gen_rtx_PLUS (Pmode, op1, op0));
9341 }
9342
9343 pat = GEN_FCN (icode) (target, addr);
9344 if (! pat)
9345 return 0;
9346 emit_insn (pat);
9347 }
9348
9349 return target;
9350}
9351
9352static rtx
9353altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
9354{
9355 rtx pat;
9356 tree arg0 = CALL_EXPR_ARG (exp, 0);
9357 tree arg1 = CALL_EXPR_ARG (exp, 1);
9358 tree arg2 = CALL_EXPR_ARG (exp, 2);
9359 rtx op0 = expand_normal (arg0);
9360 rtx op1 = expand_normal (arg1);
9361 rtx op2 = expand_normal (arg2);
9362 machine_mode mode0 = insn_data[icode].operand[0].mode;
9363 machine_mode mode1 = insn_data[icode].operand[1].mode;
9364 machine_mode mode2 = insn_data[icode].operand[2].mode;
9365
9366 if (icode == CODE_FOR_nothing)
9367 /* Builtin not supported on this processor. */
9368 return NULL_RTX;
9369
9370 /* If we got invalid arguments bail out before generating bad rtl. */
9371 if (arg0 == error_mark_node
9372 || arg1 == error_mark_node
9373 || arg2 == error_mark_node)
9374 return NULL_RTX;
9375
9376 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9377 op0 = copy_to_mode_reg (mode0, op0);
9378 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9379 op1 = copy_to_mode_reg (mode1, op1);
9380 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
9381 op2 = copy_to_mode_reg (mode2, op2);
9382
9383 pat = GEN_FCN (icode) (op0, op1, op2);
9384 if (pat)
9385 emit_insn (pat);
9386
9387 return NULL_RTX;
9388}
9389
9390static rtx
9391altivec_expand_stv_builtin (enum insn_code icode, tree exp)
9392{
9393 tree arg0 = CALL_EXPR_ARG (exp, 0);
9394 tree arg1 = CALL_EXPR_ARG (exp, 1);
9395 tree arg2 = CALL_EXPR_ARG (exp, 2);
9396 rtx op0 = expand_normal (arg0);
9397 rtx op1 = expand_normal (arg1);
9398 rtx op2 = expand_normal (arg2);
9399 rtx pat, addr, rawaddr;
9400 machine_mode tmode = insn_data[icode].operand[0].mode;
9401 machine_mode smode = insn_data[icode].operand[1].mode;
9402 machine_mode mode1 = Pmode;
9403 machine_mode mode2 = Pmode;
9404
9405 /* Invalid arguments. Bail before doing anything stoopid! */
9406 if (arg0 == error_mark_node
9407 || arg1 == error_mark_node
9408 || arg2 == error_mark_node)
9409 return const0_rtx;
9410
9411 op2 = copy_to_mode_reg (mode2, op2);
9412
9413 /* For STVX, express the RTL accurately by ANDing the address with -16.
9414 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
9415 so the raw address is fine. */
9416 if (icode == CODE_FOR_altivec_stvx_v2df
9417 || icode == CODE_FOR_altivec_stvx_v2di
9418 || icode == CODE_FOR_altivec_stvx_v4sf
9419 || icode == CODE_FOR_altivec_stvx_v4si
9420 || icode == CODE_FOR_altivec_stvx_v8hi
9421 || icode == CODE_FOR_altivec_stvx_v16qi)
9422 {
9423 if (op1 == const0_rtx)
9424 rawaddr = op2;
9425 else
9426 {
9427 op1 = copy_to_mode_reg (mode1, op1);
9428 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
9429 }
9430
9431 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
9432 addr = gen_rtx_MEM (tmode, addr);
9433
9434 op0 = copy_to_mode_reg (tmode, op0);
9435
9436 emit_insn (gen_rtx_SET (addr, op0));
9437 }
9438 else
9439 {
9440 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
9441 op0 = copy_to_mode_reg (smode, op0);
9442
9443 if (op1 == const0_rtx)
9444 addr = gen_rtx_MEM (tmode, op2);
9445 else
9446 {
9447 op1 = copy_to_mode_reg (mode1, op1);
9448 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
9449 }
9450
9451 pat = GEN_FCN (icode) (addr, op0);
9452 if (pat)
9453 emit_insn (pat);
9454 }
9455
9456 return NULL_RTX;
9457}
9458
8ee2640b
PB		 9459/* Expand the MMA built-in in EXP.
9460 Store true in *EXPANDEDP if we found a built-in to expand. */
9461
9462static rtx
9463mma_expand_builtin (tree exp, rtx target, bool *expandedp)
9464{
9465 unsigned i;
9466 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9467 enum rs6000_builtins fcode
9468 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
9469 const struct builtin_description *d = bdesc_mma;
9470
9471 /* Expand the MMA built-in. */
9472 for (i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++)
9473 if (d->code == fcode)
9474 break;
9475
9476 if (i >= ARRAY_SIZE (bdesc_mma))
9477 {
9478 *expandedp = false;
9479 return NULL_RTX;
9480 }
9481
9482 *expandedp = true;
9483
9484 tree arg;
9485 call_expr_arg_iterator iter;
9486 enum insn_code icode = d->icode;
9487 const struct insn_operand_data *insn_op;
9488 rtx op[MAX_MMA_OPERANDS];
9489 unsigned nopnds = 0;
9490 unsigned attr = rs6000_builtin_info[fcode].attr;
9491 bool void_func = (attr & RS6000_BTC_VOID);
9492 machine_mode tmode = VOIDmode;
9493
9494 if (TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node)
9495 {
9496 tmode = insn_data[icode].operand[0].mode;
9497 if (!target
9498 || GET_MODE (target) != tmode
9499 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9500 target = gen_reg_rtx (tmode);
9501 op[nopnds++] = target;
9502 }
9503 else
9504 target = const0_rtx;
9505
9506 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9507 {
9508 if (arg == error_mark_node)
9509 return const0_rtx;
9510
9511 rtx opnd;
9512 insn_op = &insn_data[icode].operand[nopnds];
9513 if (TREE_CODE (arg) == ADDR_EXPR
9514 && MEM_P (DECL_RTL (TREE_OPERAND (arg, 0))))
9515 opnd = DECL_RTL (TREE_OPERAND (arg, 0));
9516 else
9517 opnd = expand_normal (arg);
9518
9519 if (!(*insn_op->predicate) (opnd, insn_op->mode))
9520 {
9521 if (!strcmp (insn_op->constraint, "n"))
9522 {
9523 if (!CONST_INT_P (opnd))
9524 error ("argument %d must be an unsigned literal", nopnds);
9525 else
9526 error ("argument %d is an unsigned literal that is "
9527 "out of range", nopnds);
9528 return const0_rtx;
9529 }
9530 opnd = copy_to_mode_reg (insn_op->mode, opnd);
9531 }
9532
9533 /* Some MMA instructions have INOUT accumulator operands, so force
9534 their target register to be the same as their input register. */
9535 if (!void_func
9536 && nopnds == 1
9537 && !strcmp (insn_op->constraint, "0")
9538 && insn_op->mode == tmode
9539 && REG_P (opnd)
9540 && (*insn_data[icode].operand[0].predicate) (opnd, tmode))
9541 target = op[0] = opnd;
9542
9543 op[nopnds++] = opnd;
9544 }
9545
9546 unsigned attr_args = attr & RS6000_BTC_OPND_MASK;
9547 if (attr & RS6000_BTC_QUAD)
9548 attr_args++;
9549
9550 gcc_assert (nopnds == attr_args);
9551
9552 rtx pat;
9553 switch (nopnds)
9554 {
9555 case 1:
9556 pat = GEN_FCN (icode) (op[0]);
9557 break;
9558 case 2:
9559 pat = GEN_FCN (icode) (op[0], op[1]);
9560 break;
9561 case 3:
9562 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
9563 break;
9564 case 4:
9565 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
9566 break;
9567 case 5:
9568 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
9569 break;
9570 case 6:
9571 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]);
9572 break;
9573 case 7:
9574 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5], op[6]);
9575 break;
9576 default:
9577 gcc_unreachable ();
9578 }
9579 if (!pat)
9580 return NULL_RTX;
9581 emit_insn (pat);
9582
9583 return target;
9584}
9585
1acf0246
BS		 9586/* Return the appropriate SPR number associated with the given builtin. */
9587static inline HOST_WIDE_INT
9588htm_spr_num (enum rs6000_builtins code)
9589{
9590 if (code == HTM_BUILTIN_GET_TFHAR
9591 || code == HTM_BUILTIN_SET_TFHAR)
9592 return TFHAR_SPR;
9593 else if (code == HTM_BUILTIN_GET_TFIAR
9594 || code == HTM_BUILTIN_SET_TFIAR)
9595 return TFIAR_SPR;
9596 else if (code == HTM_BUILTIN_GET_TEXASR
9597 || code == HTM_BUILTIN_SET_TEXASR)
9598 return TEXASR_SPR;
9599 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
9600 || code == HTM_BUILTIN_SET_TEXASRU);
9601 return TEXASRU_SPR;
9602}
9603
9604/* Return the correct ICODE value depending on whether we are
9605 setting or reading the HTM SPRs. */
9606static inline enum insn_code
9607rs6000_htm_spr_icode (bool nonvoid)
9608{
9609 if (nonvoid)
9610 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
9611 else
9612 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
9613}
9614
9615/* Expand the HTM builtin in EXP and store the result in TARGET.
9616 Store true in *EXPANDEDP if we found a builtin to expand. */
9617static rtx
9618htm_expand_builtin (tree exp, rtx target, bool * expandedp)
9619{
9620 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9621 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
4d732405
RS		 9622 enum rs6000_builtins fcode
9623 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 9624 const struct builtin_description *d;
9625 size_t i;
9626
9627 *expandedp = true;
9628
9629 if (!TARGET_POWERPC64
9630 && (fcode == HTM_BUILTIN_TABORTDC
9631 || fcode == HTM_BUILTIN_TABORTDCI))
9632 {
9633 size_t uns_fcode = (size_t)fcode;
9634 const char *name = rs6000_builtin_info[uns_fcode].name;
9635 error ("builtin %qs is only valid in 64-bit mode", name);
9636 return const0_rtx;
9637 }
9638
9639 /* Expand the HTM builtins. */
9640 d = bdesc_htm;
9641 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
9642 if (d->code == fcode)
9643 {
9644 rtx op[MAX_HTM_OPERANDS], pat;
9645 int nopnds = 0;
9646 tree arg;
9647 call_expr_arg_iterator iter;
9648 unsigned attr = rs6000_builtin_info[fcode].attr;
9649 enum insn_code icode = d->icode;
9650 const struct insn_operand_data *insn_op;
9651 bool uses_spr = (attr & RS6000_BTC_SPR);
9652 rtx cr = NULL_RTX;
9653
9654 if (uses_spr)
9655 icode = rs6000_htm_spr_icode (nonvoid);
9656 insn_op = &insn_data[icode].operand[0];
9657
9658 if (nonvoid)
9659 {
9660 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
9661 if (!target
9662 || GET_MODE (target) != tmode
9663 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
9664 target = gen_reg_rtx (tmode);
9665 if (uses_spr)
9666 op[nopnds++] = target;
9667 }
9668
9669 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9670 {
9671 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
9672 return const0_rtx;
9673
9674 insn_op = &insn_data[icode].operand[nopnds];
9675
9676 op[nopnds] = expand_normal (arg);
9677
9678 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
9679 {
9680 if (!strcmp (insn_op->constraint, "n"))
9681 {
9682 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
9683 if (!CONST_INT_P (op[nopnds]))
9684 error ("argument %d must be an unsigned literal", arg_num);
9685 else
9686 error ("argument %d is an unsigned literal that is "
9687 "out of range", arg_num);
9688 return const0_rtx;
9689 }
9690 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
9691 }
9692
9693 nopnds++;
9694 }
9695
9696 /* Handle the builtins for extended mnemonics. These accept
9697 no arguments, but map to builtins that take arguments. */
9698 switch (fcode)
9699 {
9700 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
9701 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
9702 op[nopnds++] = GEN_INT (1);
9703 if (flag_checking)
9704 attr |= RS6000_BTC_UNARY;
9705 break;
9706 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
9707 op[nopnds++] = GEN_INT (0);
9708 if (flag_checking)
9709 attr |= RS6000_BTC_UNARY;
9710 break;
9711 default:
9712 break;
9713 }
9714
9715 /* If this builtin accesses SPRs, then pass in the appropriate
9716 SPR number and SPR regno as the last two operands. */
9717 if (uses_spr)
9718 {
9719 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
9720 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
9721 }
9722 /* If this builtin accesses a CR, then pass in a scratch
9723 CR as the last operand. */
9724 else if (attr & RS6000_BTC_CR)
9725 { cr = gen_reg_rtx (CCmode);
9726 op[nopnds++] = cr;
9727 }
9728
9729 if (flag_checking)
9730 {
9731 int expected_nopnds = 0;
8ee2640b 9732 if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_UNARY)
1acf0246 9733 expected_nopnds = 1;
8ee2640b 9734 else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_BINARY)
1acf0246 9735 expected_nopnds = 2;
8ee2640b 9736 else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_TERNARY)
1acf0246 9737 expected_nopnds = 3;
840ac85c
KN		 9738 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_QUATERNARY)
9739 expected_nopnds = 4;
1acf0246
BS		 9740 if (!(attr & RS6000_BTC_VOID))
9741 expected_nopnds += 1;
9742 if (uses_spr)
9743 expected_nopnds += 1;
9744
9745 gcc_assert (nopnds == expected_nopnds
9746 && nopnds <= MAX_HTM_OPERANDS);
9747 }
9748
9749 switch (nopnds)
9750 {
9751 case 1:
9752 pat = GEN_FCN (icode) (op[0]);
9753 break;
9754 case 2:
9755 pat = GEN_FCN (icode) (op[0], op[1]);
9756 break;
9757 case 3:
9758 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
9759 break;
9760 case 4:
9761 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
9762 break;
9763 default:
9764 gcc_unreachable ();
9765 }
9766 if (!pat)
9767 return NULL_RTX;
9768 emit_insn (pat);
9769
9770 if (attr & RS6000_BTC_CR)
9771 {
9772 if (fcode == HTM_BUILTIN_TBEGIN)
9773 {
9774 /* Emit code to set TARGET to true or false depending on
9775 whether the tbegin. instruction successfully or failed
9776 to start a transaction. We do this by placing the 1's
9777 complement of CR's EQ bit into TARGET. */
9778 rtx scratch = gen_reg_rtx (SImode);
9779 emit_insn (gen_rtx_SET (scratch,
9780 gen_rtx_EQ (SImode, cr,
9781 const0_rtx)));
9782 emit_insn (gen_rtx_SET (target,
9783 gen_rtx_XOR (SImode, scratch,
9784 GEN_INT (1))));
9785 }
9786 else
9787 {
9788 /* Emit code to copy the 4-bit condition register field
9789 CR into the least significant end of register TARGET. */
9790 rtx scratch1 = gen_reg_rtx (SImode);
9791 rtx scratch2 = gen_reg_rtx (SImode);
9792 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
9793 emit_insn (gen_movcc (subreg, cr));
9794 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
9795 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
9796 }
9797 }
9798
9799 if (nonvoid)
9800 return target;
9801 return const0_rtx;
9802 }
9803
9804 *expandedp = false;
9805 return NULL_RTX;
9806}
9807
9808/* Expand the CPU builtin in FCODE and store the result in TARGET. */
9809
9810static rtx
9811cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
9812 rtx target)
9813{
9814 /* __builtin_cpu_init () is a nop, so expand to nothing. */
9815 if (fcode == RS6000_BUILTIN_CPU_INIT)
9816 return const0_rtx;
9817
9818 if (target == 0 || GET_MODE (target) != SImode)
9819 target = gen_reg_rtx (SImode);
9820
9821#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
9822 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
9823 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
9824 to a STRING_CST. */
9825 if (TREE_CODE (arg) == ARRAY_REF
9826 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
9827 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
9828 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
9829 arg = TREE_OPERAND (arg, 0);
9830
9831 if (TREE_CODE (arg) != STRING_CST)
9832 {
9833 error ("builtin %qs only accepts a string argument",
9834 rs6000_builtin_info[(size_t) fcode].name);
9835 return const0_rtx;
9836 }
9837
9838 if (fcode == RS6000_BUILTIN_CPU_IS)
9839 {
9840 const char *cpu = TREE_STRING_POINTER (arg);
9841 rtx cpuid = NULL_RTX;
9842 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
9843 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
9844 {
9845 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
9846 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
9847 break;
9848 }
9849 if (cpuid == NULL_RTX)
9850 {
9851 /* Invalid CPU argument. */
9852 error ("cpu %qs is an invalid argument to builtin %qs",
9853 cpu, rs6000_builtin_info[(size_t) fcode].name);
9854 return const0_rtx;
9855 }
9856
9857 rtx platform = gen_reg_rtx (SImode);
9858 rtx tcbmem = gen_const_mem (SImode,
9859 gen_rtx_PLUS (Pmode,
9860 gen_rtx_REG (Pmode, TLS_REGNUM),
9861 GEN_INT (TCB_PLATFORM_OFFSET)));
9862 emit_move_insn (platform, tcbmem);
9863 emit_insn (gen_eqsi3 (target, platform, cpuid));
9864 }
9865 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
9866 {
9867 const char *hwcap = TREE_STRING_POINTER (arg);
9868 rtx mask = NULL_RTX;
9869 int hwcap_offset;
9870 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
9871 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
9872 {
9873 mask = GEN_INT (cpu_supports_info[i].mask);
9874 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
9875 break;
9876 }
9877 if (mask == NULL_RTX)
9878 {
9879 /* Invalid HWCAP argument. */
9880 error ("%s %qs is an invalid argument to builtin %qs",
9881 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
9882 return const0_rtx;
9883 }
9884
9885 rtx tcb_hwcap = gen_reg_rtx (SImode);
9886 rtx tcbmem = gen_const_mem (SImode,
9887 gen_rtx_PLUS (Pmode,
9888 gen_rtx_REG (Pmode, TLS_REGNUM),
9889 GEN_INT (hwcap_offset)));
9890 emit_move_insn (tcb_hwcap, tcbmem);
9891 rtx scratch1 = gen_reg_rtx (SImode);
9892 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
9893 rtx scratch2 = gen_reg_rtx (SImode);
9894 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
9895 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
9896 }
9897 else
9898 gcc_unreachable ();
9899
9900 /* Record that we have expanded a CPU builtin, so that we can later
9901 emit a reference to the special symbol exported by LIBC to ensure we
9902 do not link against an old LIBC that doesn't support this feature. */
9903 cpu_builtin_p = true;
9904
9905#else
9906 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
9907 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
9908
9909 /* For old LIBCs, always return FALSE. */
9910 emit_move_insn (target, GEN_INT (0));
9911#endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
9912
9913 return target;
9914}
9915
840ac85c
KN		 9916static rtx
9917rs6000_expand_quaternop_builtin (enum insn_code icode, tree exp, rtx target)
9918{
9919 rtx pat;
9920 tree arg0 = CALL_EXPR_ARG (exp, 0);
9921 tree arg1 = CALL_EXPR_ARG (exp, 1);
9922 tree arg2 = CALL_EXPR_ARG (exp, 2);
9923 tree arg3 = CALL_EXPR_ARG (exp, 3);
9924 rtx op0 = expand_normal (arg0);
9925 rtx op1 = expand_normal (arg1);
9926 rtx op2 = expand_normal (arg2);
9927 rtx op3 = expand_normal (arg3);
9928 machine_mode tmode = insn_data[icode].operand[0].mode;
9929 machine_mode mode0 = insn_data[icode].operand[1].mode;
9930 machine_mode mode1 = insn_data[icode].operand[2].mode;
9931 machine_mode mode2 = insn_data[icode].operand[3].mode;
9932 machine_mode mode3 = insn_data[icode].operand[4].mode;
9933
9934 if (icode == CODE_FOR_nothing)
9935 /* Builtin not supported on this processor. */
9936 return 0;
9937
9938 /* If we got invalid arguments bail out before generating bad rtl. */
9939 if (arg0 == error_mark_node
9940 || arg1 == error_mark_node
9941 || arg2 == error_mark_node
9942 || arg3 == error_mark_node)
9943 return const0_rtx;
9944
9945 /* Check and prepare argument depending on the instruction code.
9946
9947 Note that a switch statement instead of the sequence of tests
9948 would be incorrect as many of the CODE_FOR values could be
9949 CODE_FOR_nothing and that would yield multiple alternatives
9950 with identical values. We'd never reach here at runtime in
9951 this case. */
9952 if (icode == CODE_FOR_xxeval)
9953 {
9954 /* Only allow 8-bit unsigned literals. */
9955 STRIP_NOPS (arg3);
9956 if (TREE_CODE (arg3) != INTEGER_CST
9957 || TREE_INT_CST_LOW (arg3) & ~0xff)
9958 {
9959 error ("argument 4 must be an 8-bit unsigned literal");
9960 return CONST0_RTX (tmode);
9961 }
9962 }
9963
9964 if (target == 0
9965 || GET_MODE (target) != tmode
9966 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9967 target = gen_reg_rtx (tmode);
9968
9969 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9970 op0 = copy_to_mode_reg (mode0, op0);
9971 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9972 op1 = copy_to_mode_reg (mode1, op1);
9973 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
9974 op2 = copy_to_mode_reg (mode2, op2);
9975 if (! (*insn_data[icode].operand[4].predicate) (op3, mode3))
9976 op3 = copy_to_mode_reg (mode3, op3);
9977
9978 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
9979 if (! pat)
9980 return 0;
9981 emit_insn (pat);
9982
9983 return target;
9984}
9985
1acf0246
BS		 9986static rtx
9987rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
9988{
9989 rtx pat;
9990 tree arg0 = CALL_EXPR_ARG (exp, 0);
9991 tree arg1 = CALL_EXPR_ARG (exp, 1);
9992 tree arg2 = CALL_EXPR_ARG (exp, 2);
9993 rtx op0 = expand_normal (arg0);
9994 rtx op1 = expand_normal (arg1);
9995 rtx op2 = expand_normal (arg2);
9996 machine_mode tmode = insn_data[icode].operand[0].mode;
9997 machine_mode mode0 = insn_data[icode].operand[1].mode;
9998 machine_mode mode1 = insn_data[icode].operand[2].mode;
9999 machine_mode mode2 = insn_data[icode].operand[3].mode;
10000
10001 if (icode == CODE_FOR_nothing)
10002 /* Builtin not supported on this processor. */
10003 return 0;
10004
10005 /* If we got invalid arguments bail out before generating bad rtl. */
10006 if (arg0 == error_mark_node
10007 || arg1 == error_mark_node
10008 || arg2 == error_mark_node)
10009 return const0_rtx;
10010
10011 /* Check and prepare argument depending on the instruction code.
10012
10013 Note that a switch statement instead of the sequence of tests
10014 would be incorrect as many of the CODE_FOR values could be
10015 CODE_FOR_nothing and that would yield multiple alternatives
10016 with identical values. We'd never reach here at runtime in
10017 this case. */
10018 if (icode == CODE_FOR_altivec_vsldoi_v4sf
10019 || icode == CODE_FOR_altivec_vsldoi_v2df
10020 || icode == CODE_FOR_altivec_vsldoi_v4si
10021 || icode == CODE_FOR_altivec_vsldoi_v8hi
10022 || icode == CODE_FOR_altivec_vsldoi_v16qi)
10023 {
10024 /* Only allow 4-bit unsigned literals. */
10025 STRIP_NOPS (arg2);
10026 if (TREE_CODE (arg2) != INTEGER_CST
10027 || TREE_INT_CST_LOW (arg2) & ~0xf)
10028 {
10029 error ("argument 3 must be a 4-bit unsigned literal");
10030 return CONST0_RTX (tmode);
10031 }
10032 }
10033 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10034 || icode == CODE_FOR_vsx_xxpermdi_v2di
10035 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
10036 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
10037 || icode == CODE_FOR_vsx_xxpermdi_v1ti
10038 || icode == CODE_FOR_vsx_xxpermdi_v4sf
10039 || icode == CODE_FOR_vsx_xxpermdi_v4si
10040 || icode == CODE_FOR_vsx_xxpermdi_v8hi
10041 || icode == CODE_FOR_vsx_xxpermdi_v16qi
10042 || icode == CODE_FOR_vsx_xxsldwi_v16qi
10043 || icode == CODE_FOR_vsx_xxsldwi_v8hi
10044 || icode == CODE_FOR_vsx_xxsldwi_v4si
10045 || icode == CODE_FOR_vsx_xxsldwi_v4sf
10046 || icode == CODE_FOR_vsx_xxsldwi_v2di
10047 || icode == CODE_FOR_vsx_xxsldwi_v2df)
10048 {
10049 /* Only allow 2-bit unsigned literals. */
10050 STRIP_NOPS (arg2);
10051 if (TREE_CODE (arg2) != INTEGER_CST
10052 || TREE_INT_CST_LOW (arg2) & ~0x3)
10053 {
10054 error ("argument 3 must be a 2-bit unsigned literal");
10055 return CONST0_RTX (tmode);
10056 }
10057 }
10058 else if (icode == CODE_FOR_vsx_set_v2df
10059 || icode == CODE_FOR_vsx_set_v2di
10060 || icode == CODE_FOR_bcdadd
10061 || icode == CODE_FOR_bcdadd_lt
10062 || icode == CODE_FOR_bcdadd_eq
10063 || icode == CODE_FOR_bcdadd_gt
10064 || icode == CODE_FOR_bcdsub
10065 || icode == CODE_FOR_bcdsub_lt
10066 || icode == CODE_FOR_bcdsub_eq
10067 || icode == CODE_FOR_bcdsub_gt)
10068 {
10069 /* Only allow 1-bit unsigned literals. */
10070 STRIP_NOPS (arg2);
10071 if (TREE_CODE (arg2) != INTEGER_CST
10072 || TREE_INT_CST_LOW (arg2) & ~0x1)
10073 {
10074 error ("argument 3 must be a 1-bit unsigned literal");
10075 return CONST0_RTX (tmode);
10076 }
10077 }
10078 else if (icode == CODE_FOR_dfp_ddedpd_dd
10079 || icode == CODE_FOR_dfp_ddedpd_td)
10080 {
10081 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
10082 STRIP_NOPS (arg0);
10083 if (TREE_CODE (arg0) != INTEGER_CST
10084 || TREE_INT_CST_LOW (arg2) & ~0x3)
10085 {
10086 error ("argument 1 must be 0 or 2");
10087 return CONST0_RTX (tmode);
10088 }
10089 }
10090 else if (icode == CODE_FOR_dfp_denbcd_dd
10091 || icode == CODE_FOR_dfp_denbcd_td)
10092 {
10093 /* Only allow 1-bit unsigned literals. */
10094 STRIP_NOPS (arg0);
10095 if (TREE_CODE (arg0) != INTEGER_CST
10096 || TREE_INT_CST_LOW (arg0) & ~0x1)
10097 {
10098 error ("argument 1 must be a 1-bit unsigned literal");
10099 return CONST0_RTX (tmode);
10100 }
10101 }
10102 else if (icode == CODE_FOR_dfp_dscli_dd
10103 || icode == CODE_FOR_dfp_dscli_td
10104 || icode == CODE_FOR_dfp_dscri_dd
10105 || icode == CODE_FOR_dfp_dscri_td)
10106 {
10107 /* Only allow 6-bit unsigned literals. */
10108 STRIP_NOPS (arg1);
10109 if (TREE_CODE (arg1) != INTEGER_CST
10110 || TREE_INT_CST_LOW (arg1) & ~0x3f)
10111 {
10112 error ("argument 2 must be a 6-bit unsigned literal");
10113 return CONST0_RTX (tmode);
10114 }
10115 }
10116 else if (icode == CODE_FOR_crypto_vshasigmaw
10117 || icode == CODE_FOR_crypto_vshasigmad)
10118 {
10119 /* Check whether the 2nd and 3rd arguments are integer constants and in
10120 range and prepare arguments. */
10121 STRIP_NOPS (arg1);
10122 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
10123 {
10124 error ("argument 2 must be 0 or 1");
10125 return CONST0_RTX (tmode);
10126 }
10127
10128 STRIP_NOPS (arg2);
10129 if (TREE_CODE (arg2) != INTEGER_CST
10130 || wi::geu_p (wi::to_wide (arg2), 16))
10131 {
10132 error ("argument 3 must be in the range [0, 15]");
10133 return CONST0_RTX (tmode);
10134 }
10135 }
10136
10137 if (target == 0
10138 || GET_MODE (target) != tmode
10139 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10140 target = gen_reg_rtx (tmode);
10141
10142 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10143 op0 = copy_to_mode_reg (mode0, op0);
10144 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10145 op1 = copy_to_mode_reg (mode1, op1);
10146 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10147 op2 = copy_to_mode_reg (mode2, op2);
10148
10149 pat = GEN_FCN (icode) (target, op0, op1, op2);
10150 if (! pat)
10151 return 0;
10152 emit_insn (pat);
10153
10154 return target;
10155}
10156
10157
10158/* Expand the dst builtins. */
10159static rtx
10160altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10161 bool *expandedp)
10162{
10163 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
4d732405
RS		 10164 enum rs6000_builtins fcode
10165 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 10166 tree arg0, arg1, arg2;
10167 machine_mode mode0, mode1;
10168 rtx pat, op0, op1, op2;
10169 const struct builtin_description *d;
10170 size_t i;
10171
10172 *expandedp = false;
10173
10174 /* Handle DST variants. */
10175 d = bdesc_dst;
10176 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10177 if (d->code == fcode)
10178 {
10179 arg0 = CALL_EXPR_ARG (exp, 0);
10180 arg1 = CALL_EXPR_ARG (exp, 1);
10181 arg2 = CALL_EXPR_ARG (exp, 2);
10182 op0 = expand_normal (arg0);
10183 op1 = expand_normal (arg1);
10184 op2 = expand_normal (arg2);
10185 mode0 = insn_data[d->icode].operand[0].mode;
10186 mode1 = insn_data[d->icode].operand[1].mode;
10187
10188 /* Invalid arguments, bail out before generating bad rtl. */
10189 if (arg0 == error_mark_node
10190 || arg1 == error_mark_node
10191 || arg2 == error_mark_node)
10192 return const0_rtx;
10193
10194 *expandedp = true;
10195 STRIP_NOPS (arg2);
10196 if (TREE_CODE (arg2) != INTEGER_CST
10197 || TREE_INT_CST_LOW (arg2) & ~0x3)
10198 {
10199 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10200 return const0_rtx;
10201 }
10202
10203 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10204 op0 = copy_to_mode_reg (Pmode, op0);
10205 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10206 op1 = copy_to_mode_reg (mode1, op1);
10207
10208 pat = GEN_FCN (d->icode) (op0, op1, op2);
10209 if (pat != 0)
10210 emit_insn (pat);
10211
10212 return NULL_RTX;
10213 }
10214
10215 return NULL_RTX;
10216}
10217
10218/* Expand vec_init builtin. */
10219static rtx
10220altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
10221{
10222 machine_mode tmode = TYPE_MODE (type);
10223 machine_mode inner_mode = GET_MODE_INNER (tmode);
10224 int i, n_elt = GET_MODE_NUNITS (tmode);
10225
10226 gcc_assert (VECTOR_MODE_P (tmode));
10227 gcc_assert (n_elt == call_expr_nargs (exp));
10228
10229 if (!target || !register_operand (target, tmode))
10230 target = gen_reg_rtx (tmode);
10231
10232 /* If we have a vector compromised of a single element, such as V1TImode, do
10233 the initialization directly. */
10234 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
10235 {
10236 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
10237 emit_move_insn (target, gen_lowpart (tmode, x));
10238 }
10239 else
10240 {
10241 rtvec v = rtvec_alloc (n_elt);
10242
10243 for (i = 0; i < n_elt; ++i)
10244 {
10245 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
10246 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
10247 }
10248
10249 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
10250 }
10251
10252 return target;
10253}
10254
10255/* Return the integer constant in ARG. Constrain it to be in the range
10256 of the subparts of VEC_TYPE; issue an error if not. */
10257
10258static int
10259get_element_number (tree vec_type, tree arg)
10260{
10261 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
10262
10263 if (!tree_fits_uhwi_p (arg)
10264 || (elt = tree_to_uhwi (arg), elt > max))
10265 {
10266 error ("selector must be an integer constant in the range [0, %wi]", max);
10267 return 0;
10268 }
10269
10270 return elt;
10271}
10272
10273/* Expand vec_set builtin. */
10274static rtx
10275altivec_expand_vec_set_builtin (tree exp)
10276{
10277 machine_mode tmode, mode1;
10278 tree arg0, arg1, arg2;
10279 int elt;
10280 rtx op0, op1;
10281
10282 arg0 = CALL_EXPR_ARG (exp, 0);
10283 arg1 = CALL_EXPR_ARG (exp, 1);
10284 arg2 = CALL_EXPR_ARG (exp, 2);
10285
10286 tmode = TYPE_MODE (TREE_TYPE (arg0));
10287 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10288 gcc_assert (VECTOR_MODE_P (tmode));
10289
10290 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
10291 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
10292 elt = get_element_number (TREE_TYPE (arg0), arg2);
10293
10294 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
10295 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
10296
10297 op0 = force_reg (tmode, op0);
10298 op1 = force_reg (mode1, op1);
10299
10300 rs6000_expand_vector_set (op0, op1, elt);
10301
10302 return op0;
10303}
10304
10305/* Expand vec_ext builtin. */
10306static rtx
10307altivec_expand_vec_ext_builtin (tree exp, rtx target)
10308{
10309 machine_mode tmode, mode0;
10310 tree arg0, arg1;
10311 rtx op0;
10312 rtx op1;
10313
10314 arg0 = CALL_EXPR_ARG (exp, 0);
10315 arg1 = CALL_EXPR_ARG (exp, 1);
10316
10317 op0 = expand_normal (arg0);
10318 op1 = expand_normal (arg1);
10319
10320 if (TREE_CODE (arg1) == INTEGER_CST)
10321 {
10322 unsigned HOST_WIDE_INT elt;
10323 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0));
10324 unsigned int truncated_selector;
10325 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
10326 returns low-order bits of INTEGER_CST for modulo indexing. */
10327 elt = TREE_INT_CST_LOW (arg1);
10328 truncated_selector = elt % size;
10329 op1 = GEN_INT (truncated_selector);
10330 }
10331
10332 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10333 mode0 = TYPE_MODE (TREE_TYPE (arg0));
10334 gcc_assert (VECTOR_MODE_P (mode0));
10335
10336 op0 = force_reg (mode0, op0);
10337
10338 if (optimize || !target || !register_operand (target, tmode))
10339 target = gen_reg_rtx (tmode);
10340
10341 rs6000_expand_vector_extract (target, op0, op1);
10342
10343 return target;
10344}
10345
10346/* Expand the builtin in EXP and store the result in TARGET. Store
10347 true in *EXPANDEDP if we found a builtin to expand. */
10348static rtx
10349altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
10350{
10351 const struct builtin_description *d;
10352 size_t i;
10353 enum insn_code icode;
10354 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10355 tree arg0, arg1, arg2;
10356 rtx op0, pat;
10357 machine_mode tmode, mode0;
10358 enum rs6000_builtins fcode
4d732405 10359 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 10360
10361 if (rs6000_overloaded_builtin_p (fcode))
10362 {
10363 *expandedp = true;
10364 error ("unresolved overload for Altivec builtin %qF", fndecl);
10365
10366 /* Given it is invalid, just generate a normal call. */
10367 return expand_call (exp, target, false);
10368 }
10369
10370 target = altivec_expand_dst_builtin (exp, target, expandedp);
10371 if (*expandedp)
10372 return target;
10373
10374 *expandedp = true;
10375
10376 switch (fcode)
10377 {
10378 case ALTIVEC_BUILTIN_STVX_V2DF:
10379 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
10380 case ALTIVEC_BUILTIN_STVX_V2DI:
10381 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
10382 case ALTIVEC_BUILTIN_STVX_V4SF:
10383 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
10384 case ALTIVEC_BUILTIN_STVX:
10385 case ALTIVEC_BUILTIN_STVX_V4SI:
10386 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10387 case ALTIVEC_BUILTIN_STVX_V8HI:
10388 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
10389 case ALTIVEC_BUILTIN_STVX_V16QI:
10390 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
10391 case ALTIVEC_BUILTIN_STVEBX:
10392 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10393 case ALTIVEC_BUILTIN_STVEHX:
10394 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
10395 case ALTIVEC_BUILTIN_STVEWX:
10396 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
10397 case ALTIVEC_BUILTIN_STVXL_V2DF:
10398 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
10399 case ALTIVEC_BUILTIN_STVXL_V2DI:
10400 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
10401 case ALTIVEC_BUILTIN_STVXL_V4SF:
10402 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
10403 case ALTIVEC_BUILTIN_STVXL:
10404 case ALTIVEC_BUILTIN_STVXL_V4SI:
10405 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
10406 case ALTIVEC_BUILTIN_STVXL_V8HI:
10407 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
10408 case ALTIVEC_BUILTIN_STVXL_V16QI:
10409 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
10410
10411 case ALTIVEC_BUILTIN_STVLX:
10412 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
10413 case ALTIVEC_BUILTIN_STVLXL:
10414 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
10415 case ALTIVEC_BUILTIN_STVRX:
10416 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
10417 case ALTIVEC_BUILTIN_STVRXL:
10418 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
10419
10420 case P9V_BUILTIN_STXVL:
10421 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
10422
10423 case P9V_BUILTIN_XST_LEN_R:
10424 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
10425
10426 case VSX_BUILTIN_STXVD2X_V1TI:
10427 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
10428 case VSX_BUILTIN_STXVD2X_V2DF:
10429 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
10430 case VSX_BUILTIN_STXVD2X_V2DI:
10431 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
10432 case VSX_BUILTIN_STXVW4X_V4SF:
10433 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
10434 case VSX_BUILTIN_STXVW4X_V4SI:
10435 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
10436 case VSX_BUILTIN_STXVW4X_V8HI:
10437 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10438 case VSX_BUILTIN_STXVW4X_V16QI:
10439 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10440
10441 /* For the following on big endian, it's ok to use any appropriate
10442 unaligned-supporting store, so use a generic expander. For
10443 little-endian, the exact element-reversing instruction must
10444 be used. */
10445 case VSX_BUILTIN_ST_ELEMREV_V1TI:
10446 {
10447 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
10448 : CODE_FOR_vsx_st_elemrev_v1ti);
10449 return altivec_expand_stv_builtin (code, exp);
10450 }
10451 case VSX_BUILTIN_ST_ELEMREV_V2DF:
10452 {
10453 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
10454 : CODE_FOR_vsx_st_elemrev_v2df);
10455 return altivec_expand_stv_builtin (code, exp);
10456 }
10457 case VSX_BUILTIN_ST_ELEMREV_V2DI:
10458 {
10459 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
10460 : CODE_FOR_vsx_st_elemrev_v2di);
10461 return altivec_expand_stv_builtin (code, exp);
10462 }
10463 case VSX_BUILTIN_ST_ELEMREV_V4SF:
10464 {
10465 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
10466 : CODE_FOR_vsx_st_elemrev_v4sf);
10467 return altivec_expand_stv_builtin (code, exp);
10468 }
10469 case VSX_BUILTIN_ST_ELEMREV_V4SI:
10470 {
10471 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
10472 : CODE_FOR_vsx_st_elemrev_v4si);
10473 return altivec_expand_stv_builtin (code, exp);
10474 }
10475 case VSX_BUILTIN_ST_ELEMREV_V8HI:
10476 {
10477 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
10478 : CODE_FOR_vsx_st_elemrev_v8hi);
10479 return altivec_expand_stv_builtin (code, exp);
10480 }
10481 case VSX_BUILTIN_ST_ELEMREV_V16QI:
10482 {
10483 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
10484 : CODE_FOR_vsx_st_elemrev_v16qi);
10485 return altivec_expand_stv_builtin (code, exp);
10486 }
10487
10488 case ALTIVEC_BUILTIN_MFVSCR:
10489 icode = CODE_FOR_altivec_mfvscr;
10490 tmode = insn_data[icode].operand[0].mode;
10491
10492 if (target == 0
10493 || GET_MODE (target) != tmode
10494 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10495 target = gen_reg_rtx (tmode);
10496
10497 pat = GEN_FCN (icode) (target);
10498 if (! pat)
10499 return 0;
10500 emit_insn (pat);
10501 return target;
10502
10503 case ALTIVEC_BUILTIN_MTVSCR:
10504 icode = CODE_FOR_altivec_mtvscr;
10505 arg0 = CALL_EXPR_ARG (exp, 0);
10506 op0 = expand_normal (arg0);
10507 mode0 = insn_data[icode].operand[0].mode;
10508
10509 /* If we got invalid arguments bail out before generating bad rtl. */
10510 if (arg0 == error_mark_node)
10511 return const0_rtx;
10512
10513 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10514 op0 = copy_to_mode_reg (mode0, op0);
10515
10516 pat = GEN_FCN (icode) (op0);
10517 if (pat)
10518 emit_insn (pat);
10519 return NULL_RTX;
10520
10521 case ALTIVEC_BUILTIN_DSSALL:
10522 emit_insn (gen_altivec_dssall ());
10523 return NULL_RTX;
10524
10525 case ALTIVEC_BUILTIN_DSS:
10526 icode = CODE_FOR_altivec_dss;
10527 arg0 = CALL_EXPR_ARG (exp, 0);
10528 STRIP_NOPS (arg0);
10529 op0 = expand_normal (arg0);
10530 mode0 = insn_data[icode].operand[0].mode;
10531
10532 /* If we got invalid arguments bail out before generating bad rtl. */
10533 if (arg0 == error_mark_node)
10534 return const0_rtx;
10535
10536 if (TREE_CODE (arg0) != INTEGER_CST
10537 || TREE_INT_CST_LOW (arg0) & ~0x3)
10538 {
10539 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
10540 return const0_rtx;
10541 }
10542
10543 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10544 op0 = copy_to_mode_reg (mode0, op0);
10545
10546 emit_insn (gen_altivec_dss (op0));
10547 return NULL_RTX;
10548
10549 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
10550 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
10551 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
10552 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
10553 case VSX_BUILTIN_VEC_INIT_V2DF:
10554 case VSX_BUILTIN_VEC_INIT_V2DI:
10555 case VSX_BUILTIN_VEC_INIT_V1TI:
10556 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
10557
10558 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
10559 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
10560 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
10561 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
10562 case VSX_BUILTIN_VEC_SET_V2DF:
10563 case VSX_BUILTIN_VEC_SET_V2DI:
10564 case VSX_BUILTIN_VEC_SET_V1TI:
10565 return altivec_expand_vec_set_builtin (exp);
10566
10567 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
10568 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
10569 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
10570 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
10571 case VSX_BUILTIN_VEC_EXT_V2DF:
10572 case VSX_BUILTIN_VEC_EXT_V2DI:
10573 case VSX_BUILTIN_VEC_EXT_V1TI:
10574 return altivec_expand_vec_ext_builtin (exp, target);
10575
10576 case P9V_BUILTIN_VEC_EXTRACT4B:
10577 arg1 = CALL_EXPR_ARG (exp, 1);
10578 STRIP_NOPS (arg1);
10579
10580 /* Generate a normal call if it is invalid. */
10581 if (arg1 == error_mark_node)
10582 return expand_call (exp, target, false);
10583
10584 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
10585 {
10586 error ("second argument to %qs must be [0, 12]", "vec_vextract4b");
10587 return expand_call (exp, target, false);
10588 }
10589 break;
10590
10591 case P9V_BUILTIN_VEC_INSERT4B:
10592 arg2 = CALL_EXPR_ARG (exp, 2);
10593 STRIP_NOPS (arg2);
10594
10595 /* Generate a normal call if it is invalid. */
10596 if (arg2 == error_mark_node)
10597 return expand_call (exp, target, false);
10598
10599 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
10600 {
10601 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b");
10602 return expand_call (exp, target, false);
10603 }
10604 break;
10605
5d9d0c94 10606 case P10_BUILTIN_VEC_XXGENPCVM:
b8eaa754
CL		 10607 arg1 = CALL_EXPR_ARG (exp, 1);
10608 STRIP_NOPS (arg1);
10609
10610 /* Generate a normal call if it is invalid. */
10611 if (arg1 == error_mark_node)
10612 return expand_call (exp, target, false);
10613
10614 if (TREE_CODE (arg1) != INTEGER_CST
10615 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 3))
10616 {
10617 size_t uns_fcode = (size_t) fcode;
10618 const char *name = rs6000_builtin_info[uns_fcode].name;
10619 error ("Second argument of %qs must be in the range [0, 3].", name);
10620 return expand_call (exp, target, false);
10621 }
10622 break;
10623
1acf0246
BS		 10624 default:
10625 break;
10626 /* Fall through. */
10627 }
10628
10629 /* Expand abs* operations. */
10630 d = bdesc_abs;
10631 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10632 if (d->code == fcode)
10633 return altivec_expand_abs_builtin (d->icode, exp, target);
10634
10635 /* Expand the AltiVec predicates. */
10636 d = bdesc_altivec_preds;
10637 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
10638 if (d->code == fcode)
10639 return altivec_expand_predicate_builtin (d->icode, exp, target);
10640
10641 /* LV* are funky. We initialized them differently. */
10642 switch (fcode)
10643 {
10644 case ALTIVEC_BUILTIN_LVSL:
10645 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
10646 exp, target, false);
10647 case ALTIVEC_BUILTIN_LVSR:
10648 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
10649 exp, target, false);
10650 case ALTIVEC_BUILTIN_LVEBX:
10651 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
10652 exp, target, false);
10653 case ALTIVEC_BUILTIN_LVEHX:
10654 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
10655 exp, target, false);
10656 case ALTIVEC_BUILTIN_LVEWX:
10657 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
10658 exp, target, false);
10659 case ALTIVEC_BUILTIN_LVXL_V2DF:
10660 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
10661 exp, target, false);
10662 case ALTIVEC_BUILTIN_LVXL_V2DI:
10663 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
10664 exp, target, false);
10665 case ALTIVEC_BUILTIN_LVXL_V4SF:
10666 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
10667 exp, target, false);
10668 case ALTIVEC_BUILTIN_LVXL:
10669 case ALTIVEC_BUILTIN_LVXL_V4SI:
10670 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
10671 exp, target, false);
10672 case ALTIVEC_BUILTIN_LVXL_V8HI:
10673 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
10674 exp, target, false);
10675 case ALTIVEC_BUILTIN_LVXL_V16QI:
10676 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
10677 exp, target, false);
10678 case ALTIVEC_BUILTIN_LVX_V1TI:
10679 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
10680 exp, target, false);
10681 case ALTIVEC_BUILTIN_LVX_V2DF:
10682 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
10683 exp, target, false);
10684 case ALTIVEC_BUILTIN_LVX_V2DI:
10685 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
10686 exp, target, false);
10687 case ALTIVEC_BUILTIN_LVX_V4SF:
10688 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
10689 exp, target, false);
10690 case ALTIVEC_BUILTIN_LVX:
10691 case ALTIVEC_BUILTIN_LVX_V4SI:
10692 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10693 exp, target, false);
10694 case ALTIVEC_BUILTIN_LVX_V8HI:
10695 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
10696 exp, target, false);
10697 case ALTIVEC_BUILTIN_LVX_V16QI:
10698 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
10699 exp, target, false);
10700 case ALTIVEC_BUILTIN_LVLX:
10701 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10702 exp, target, true);
10703 case ALTIVEC_BUILTIN_LVLXL:
10704 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
10705 exp, target, true);
10706 case ALTIVEC_BUILTIN_LVRX:
10707 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
10708 exp, target, true);
10709 case ALTIVEC_BUILTIN_LVRXL:
10710 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10711 exp, target, true);
10712 case VSX_BUILTIN_LXVD2X_V1TI:
10713 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
10714 exp, target, false);
10715 case VSX_BUILTIN_LXVD2X_V2DF:
10716 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10717 exp, target, false);
10718 case VSX_BUILTIN_LXVD2X_V2DI:
10719 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10720 exp, target, false);
10721 case VSX_BUILTIN_LXVW4X_V4SF:
10722 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10723 exp, target, false);
10724 case VSX_BUILTIN_LXVW4X_V4SI:
10725 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10726 exp, target, false);
10727 case VSX_BUILTIN_LXVW4X_V8HI:
10728 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10729 exp, target, false);
10730 case VSX_BUILTIN_LXVW4X_V16QI:
10731 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10732 exp, target, false);
10733 /* For the following on big endian, it's ok to use any appropriate
10734 unaligned-supporting load, so use a generic expander. For
10735 little-endian, the exact element-reversing instruction must
10736 be used. */
10737 case VSX_BUILTIN_LD_ELEMREV_V2DF:
10738 {
10739 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
10740 : CODE_FOR_vsx_ld_elemrev_v2df);
10741 return altivec_expand_lv_builtin (code, exp, target, false);
10742 }
10743 case VSX_BUILTIN_LD_ELEMREV_V1TI:
10744 {
10745 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
10746 : CODE_FOR_vsx_ld_elemrev_v1ti);
10747 return altivec_expand_lv_builtin (code, exp, target, false);
10748 }
10749 case VSX_BUILTIN_LD_ELEMREV_V2DI:
10750 {
10751 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
10752 : CODE_FOR_vsx_ld_elemrev_v2di);
10753 return altivec_expand_lv_builtin (code, exp, target, false);
10754 }
10755 case VSX_BUILTIN_LD_ELEMREV_V4SF:
10756 {
10757 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
10758 : CODE_FOR_vsx_ld_elemrev_v4sf);
10759 return altivec_expand_lv_builtin (code, exp, target, false);
10760 }
10761 case VSX_BUILTIN_LD_ELEMREV_V4SI:
10762 {
10763 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
10764 : CODE_FOR_vsx_ld_elemrev_v4si);
10765 return altivec_expand_lv_builtin (code, exp, target, false);
10766 }
10767 case VSX_BUILTIN_LD_ELEMREV_V8HI:
10768 {
10769 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
10770 : CODE_FOR_vsx_ld_elemrev_v8hi);
10771 return altivec_expand_lv_builtin (code, exp, target, false);
10772 }
10773 case VSX_BUILTIN_LD_ELEMREV_V16QI:
10774 {
10775 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
10776 : CODE_FOR_vsx_ld_elemrev_v16qi);
10777 return altivec_expand_lv_builtin (code, exp, target, false);
10778 }
10779 break;
10780 default:
10781 break;
10782 /* Fall through. */
10783 }
10784
10785 *expandedp = false;
10786 return NULL_RTX;
10787}
10788
10789/* Check whether a builtin function is supported in this target
10790 configuration. */
10791bool
10792rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
10793{
10794 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
10795 if ((fnmask & rs6000_builtin_mask) != fnmask)
10796 return false;
10797 else
10798 return true;
10799}
10800
10801/* Raise an error message for a builtin function that is called without the
10802 appropriate target options being set. */
10803
871a8fab 10804static void
1acf0246
BS		 10805rs6000_invalid_builtin (enum rs6000_builtins fncode)
10806{
10807 size_t uns_fncode = (size_t) fncode;
10808 const char *name = rs6000_builtin_info[uns_fncode].name;
10809 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
10810
10811 gcc_assert (name != NULL);
10812 if ((fnmask & RS6000_BTM_CELL) != 0)
10813 error ("%qs is only valid for the cell processor", name);
10814 else if ((fnmask & RS6000_BTM_VSX) != 0)
10815 error ("%qs requires the %qs option", name, "-mvsx");
10816 else if ((fnmask & RS6000_BTM_HTM) != 0)
10817 error ("%qs requires the %qs option", name, "-mhtm");
10818 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
10819 error ("%qs requires the %qs option", name, "-maltivec");
10820 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
10821 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
10822 error ("%qs requires the %qs and %qs options", name, "-mhard-dfp",
10823 "-mpower8-vector");
10824 else if ((fnmask & RS6000_BTM_DFP) != 0)
10825 error ("%qs requires the %qs option", name, "-mhard-dfp");
10826 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
10827 error ("%qs requires the %qs option", name, "-mpower8-vector");
10828 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
10829 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
10830 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9",
10831 "-m64");
10832 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
10833 error ("%qs requires the %qs option", name, "-mcpu=power9");
10834 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
10835 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
10836 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9",
10837 "-m64");
10838 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
10839 error ("%qs requires the %qs option", name, "-mcpu=power9");
5d9d0c94
SB		 10840 else if ((fnmask & RS6000_BTM_P10) != 0)
10841 error ("%qs requires the %qs option", name, "-mcpu=power10");
8ee2640b
PB		 10842 else if ((fnmask & RS6000_BTM_MMA) != 0)
10843 error ("%qs requires the %qs option", name, "-mmma");
1acf0246
BS		 10844 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
10845 {
10846 if (!TARGET_HARD_FLOAT)
10847 error ("%qs requires the %qs option", name, "-mhard-float");
10848 else
10849 error ("%qs requires the %qs option", name,
10850 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
10851 }
10852 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
10853 error ("%qs requires the %qs option", name, "-mhard-float");
10854 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
10855 error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name);
10856 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
10857 error ("%qs requires the %qs option", name, "%<-mfloat128%>");
10858 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
10859 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
10860 error ("%qs requires the %qs (or newer), and %qs or %qs options",
10861 name, "-mcpu=power7", "-m64", "-mpowerpc64");
10862 else
10863 error ("%qs is not supported with the current options", name);
10864}
10865
10866/* Target hook for early folding of built-ins, shamelessly stolen
10867 from ia64.c. */
10868
10869tree
10870rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
10871 int n_args ATTRIBUTE_UNUSED,
10872 tree *args ATTRIBUTE_UNUSED,
10873 bool ignore ATTRIBUTE_UNUSED)
10874{
10875#ifdef SUBTARGET_FOLD_BUILTIN
10876 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
10877#else
10878 return NULL_TREE;
10879#endif
10880}
10881
10882/* Helper function to sort out which built-ins may be valid without having
10883 a LHS. */
10884static bool
10885rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
10886{
8ee2640b
PB		 10887 /* Check for built-ins explicitly marked as a void function. */
10888 if (rs6000_builtin_info[fn_code].attr & RS6000_BTC_VOID)
10889 return true;
10890
1acf0246
BS		 10891 switch (fn_code)
10892 {
10893 case ALTIVEC_BUILTIN_STVX_V16QI:
10894 case ALTIVEC_BUILTIN_STVX_V8HI:
10895 case ALTIVEC_BUILTIN_STVX_V4SI:
10896 case ALTIVEC_BUILTIN_STVX_V4SF:
10897 case ALTIVEC_BUILTIN_STVX_V2DI:
10898 case ALTIVEC_BUILTIN_STVX_V2DF:
10899 case VSX_BUILTIN_STXVW4X_V16QI:
10900 case VSX_BUILTIN_STXVW4X_V8HI:
10901 case VSX_BUILTIN_STXVW4X_V4SF:
10902 case VSX_BUILTIN_STXVW4X_V4SI:
10903 case VSX_BUILTIN_STXVD2X_V2DF:
10904 case VSX_BUILTIN_STXVD2X_V2DI:
10905 return true;
10906 default:
10907 return false;
10908 }
10909}
10910
10911/* Helper function to handle the gimple folding of a vector compare
10912 operation. This sets up true/false vectors, and uses the
10913 VEC_COND_EXPR operation.
10914 CODE indicates which comparison is to be made. (EQ, GT, ...).
e68cc3a8
ML		 10915 TYPE indicates the type of the result.
10916 Code is inserted before GSI. */
1acf0246 10917static tree
e68cc3a8
ML		 10918fold_build_vec_cmp (tree_code code, tree type, tree arg0, tree arg1,
10919 gimple_stmt_iterator *gsi)
1acf0246 10920{
e8738f4e 10921 tree cmp_type = truth_type_for (type);
1acf0246
BS		 10922 tree zero_vec = build_zero_cst (type);
10923 tree minus_one_vec = build_minus_one_cst (type);
e68cc3a8
ML		 10924 tree temp = create_tmp_reg_or_ssa_name (cmp_type);
10925 gimple *g = gimple_build_assign (temp, code, arg0, arg1);
10926 gsi_insert_before (gsi, g, GSI_SAME_STMT);
10927 return fold_build3 (VEC_COND_EXPR, type, temp, minus_one_vec, zero_vec);
1acf0246
BS		 10928}
10929
10930/* Helper function to handle the in-between steps for the
10931 vector compare built-ins. */
10932static void
10933fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
10934{
10935 tree arg0 = gimple_call_arg (stmt, 0);
10936 tree arg1 = gimple_call_arg (stmt, 1);
10937 tree lhs = gimple_call_lhs (stmt);
e68cc3a8 10938 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1, gsi);
1acf0246
BS		 10939 gimple *g = gimple_build_assign (lhs, cmp);
10940 gimple_set_location (g, gimple_location (stmt));
10941 gsi_replace (gsi, g, true);
10942}
10943
10944/* Helper function to map V2DF and V4SF types to their
10945 integral equivalents (V2DI and V4SI). */
10946tree map_to_integral_tree_type (tree input_tree_type)
10947{
10948 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
10949 return input_tree_type;
10950 else
10951 {
10952 if (types_compatible_p (TREE_TYPE (input_tree_type),
10953 TREE_TYPE (V2DF_type_node)))
10954 return V2DI_type_node;
10955 else if (types_compatible_p (TREE_TYPE (input_tree_type),
10956 TREE_TYPE (V4SF_type_node)))
10957 return V4SI_type_node;
10958 else
10959 gcc_unreachable ();
10960 }
10961}
10962
10963/* Helper function to handle the vector merge[hl] built-ins. The
10964 implementation difference between h and l versions for this code are in
10965 the values used when building of the permute vector for high word versus
10966 low word merge. The variance is keyed off the use_high parameter. */
10967static void
10968fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
10969{
10970 tree arg0 = gimple_call_arg (stmt, 0);
10971 tree arg1 = gimple_call_arg (stmt, 1);
10972 tree lhs = gimple_call_lhs (stmt);
10973 tree lhs_type = TREE_TYPE (lhs);
10974 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
10975 int midpoint = n_elts / 2;
10976 int offset = 0;
10977
10978 if (use_high == 1)
10979 offset = midpoint;
10980
10981 /* The permute_type will match the lhs for integral types. For double and
10982 float types, the permute type needs to map to the V2 or V4 type that
10983 matches size. */
10984 tree permute_type;
10985 permute_type = map_to_integral_tree_type (lhs_type);
10986 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
10987
10988 for (int i = 0; i < midpoint; i++)
10989 {
10990 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
10991 offset + i));
10992 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
10993 offset + n_elts + i));
10994 }
10995
10996 tree permute = elts.build ();
10997
10998 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
10999 gimple_set_location (g, gimple_location (stmt));
11000 gsi_replace (gsi, g, true);
11001}
11002
11003/* Helper function to handle the vector merge[eo] built-ins. */
11004static void
11005fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
11006{
11007 tree arg0 = gimple_call_arg (stmt, 0);
11008 tree arg1 = gimple_call_arg (stmt, 1);
11009 tree lhs = gimple_call_lhs (stmt);
11010 tree lhs_type = TREE_TYPE (lhs);
11011 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
11012
11013 /* The permute_type will match the lhs for integral types. For double and
11014 float types, the permute type needs to map to the V2 or V4 type that
11015 matches size. */
11016 tree permute_type;
11017 permute_type = map_to_integral_tree_type (lhs_type);
11018
11019 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
11020
11021 /* Build the permute vector. */
11022 for (int i = 0; i < n_elts / 2; i++)
11023 {
11024 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11025 2*i + use_odd));
11026 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11027 2*i + use_odd + n_elts));
11028 }
11029
11030 tree permute = elts.build ();
11031
11032 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
11033 gimple_set_location (g, gimple_location (stmt));
11034 gsi_replace (gsi, g, true);
11035}
11036
8ee2640b
PB		 11037/* Expand the MMA built-ins early, so that we can convert the pass-by-reference
11038 __vector_quad arguments into pass-by-value arguments, leading to more
11039 efficient code generation. */
11040
11041bool
11042rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi)
11043{
11044 gimple *stmt = gsi_stmt (*gsi);
11045 tree fndecl = gimple_call_fndecl (stmt);
11046 enum rs6000_builtins fncode
11047 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
11048 unsigned attr = rs6000_builtin_info[fncode].attr;
11049
11050 if ((attr & RS6000_BTC_GIMPLE) == 0)
11051 return false;
11052
11053 unsigned nopnds = (attr & RS6000_BTC_OPND_MASK);
11054 gimple_seq new_seq = NULL;
11055 gimple *new_call;
11056 tree new_decl;
11057
11058 if (rs6000_builtin_info[fncode + 1].icode == CODE_FOR_nothing)
11059 {
11060 /* This is an MMA disassemble built-in function. */
11061 gcc_assert (fncode == MMA_BUILTIN_DISASSEMBLE_ACC
11062 || fncode == MMA_BUILTIN_DISASSEMBLE_PAIR);
11063
11064 push_gimplify_context (true);
11065 tree dst_ptr = gimple_call_arg (stmt, 0);
11066 tree src_ptr = gimple_call_arg (stmt, 1);
11067 tree src_type = TREE_TYPE (src_ptr);
11068 tree src = make_ssa_name (TREE_TYPE (src_type));
11069 gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq);
11070
11071 /* If we are not disassembling an accumulator or our destination is
11072 another accumulator, then just copy the entire thing as is. */
11073 if (fncode != MMA_BUILTIN_DISASSEMBLE_ACC
11074 || TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_quad_type_node)
11075 {
11076 tree dst = build_simple_mem_ref (build1 (VIEW_CONVERT_EXPR,
11077 src_type, dst_ptr));
11078 gimplify_assign (dst, src, &new_seq);
11079 pop_gimplify_context (NULL);
11080 gsi_replace_with_seq (gsi, new_seq, true);
11081 return true;
11082 }
11083
11084 /* We're disassembling an accumulator into a different type, so we need
11085 to emit a xxmfacc instruction now, since we cannot do it later. */
11086 new_decl = rs6000_builtin_decls[MMA_BUILTIN_XXMFACC_INTERNAL];
11087 new_call = gimple_build_call (new_decl, 1, src);
11088 src = make_ssa_name (vector_quad_type_node);
11089 gimple_call_set_lhs (new_call, src);
11090 gimple_seq_add_stmt (&new_seq, new_call);
11091
11092 /* Copy the accumulator vector by vector. */
11093 tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node,
11094 ptr_mode, true);
11095 tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr);
11096 tree array_type = build_array_type_nelts (unsigned_V16QI_type_node, 4);
11097 tree src_array = build1 (VIEW_CONVERT_EXPR, array_type, src);
11098 for (unsigned i = 0; i < 4; i++)
11099 {
11100 tree ref = build4 (ARRAY_REF, unsigned_V16QI_type_node, src_array,
11101 build_int_cst (size_type_node, i),
11102 NULL_TREE, NULL_TREE);
11103 tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base,
11104 build_int_cst (dst_type, i * 16));
11105 gimplify_assign (dst, ref, &new_seq);
11106 }
11107 pop_gimplify_context (NULL);
11108 gsi_replace_with_seq (gsi, new_seq, true);
11109 return true;
11110 }
11111
11112 /* Convert this built-in into an internal version that uses pass-by-value
11113 arguments. The internal built-in follows immediately after this one. */
11114 new_decl = rs6000_builtin_decls[fncode + 1];
11115 tree lhs, mem, op[MAX_MMA_OPERANDS];
11116 tree acc = gimple_call_arg (stmt, 0);
11117 if (TREE_CODE (acc) == PARM_DECL)
11118 mem = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (acc)), acc);
11119 else
11120 mem = build_simple_mem_ref (acc);
11121 push_gimplify_context (true);
11122
11123 if ((attr & RS6000_BTC_QUAD) != 0)
11124 {
11125 /* This built-in has a pass-by-reference accumulator input, so load it
11126 into a temporary accumulator for use as a pass-by-value input. */
11127 op[0] = make_ssa_name (vector_quad_type_node);
11128 for (unsigned i = 1; i < nopnds; i++)
11129 op[i] = gimple_call_arg (stmt, i);
11130 gimplify_assign (op[0], mem, &new_seq);
11131 }
11132 else
11133 {
11134 /* This built-in does not use its pass-by-reference accumulator argument
11135 as an input argument, so remove it from the input list. */
11136 nopnds--;
11137 for (unsigned i = 0; i < nopnds; i++)
11138 op[i] = gimple_call_arg (stmt, i + 1);
11139 }
11140
11141 switch (nopnds)
11142 {
11143 case 0:
11144 new_call = gimple_build_call (new_decl, 0);
11145 break;
11146 case 1:
11147 new_call = gimple_build_call (new_decl, 1, op[0]);
11148 break;
11149 case 2:
11150 new_call = gimple_build_call (new_decl, 2, op[0], op[1]);
11151 break;
11152 case 3:
11153 new_call = gimple_build_call (new_decl, 3, op[0], op[1], op[2]);
11154 break;
11155 case 4:
11156 new_call = gimple_build_call (new_decl, 4, op[0], op[1], op[2], op[3]);
11157 break;
11158 case 5:
11159 new_call = gimple_build_call (new_decl, 5, op[0], op[1], op[2], op[3],
11160 op[4]);
11161 break;
11162 case 6:
11163 new_call = gimple_build_call (new_decl, 6, op[0], op[1], op[2], op[3],
11164 op[4], op[5]);
11165 break;
11166 case 7:
11167 new_call = gimple_build_call (new_decl, 7, op[0], op[1], op[2], op[3],
11168 op[4], op[5], op[6]);
11169 break;
11170 default:
11171 gcc_unreachable ();
11172 }
11173
11174 if (fncode == MMA_BUILTIN_ASSEMBLE_PAIR)
11175 lhs = make_ssa_name (vector_pair_type_node);
11176 else
11177 lhs = make_ssa_name (vector_quad_type_node);
11178 gimple_call_set_lhs (new_call, lhs);
11179 gimple_seq_add_stmt (&new_seq, new_call);
11180 gimplify_assign (mem, lhs, &new_seq);
11181 pop_gimplify_context (NULL);
11182 gsi_replace_with_seq (gsi, new_seq, true);
11183
11184 return true;
11185}
11186
1acf0246
BS		 11187/* Fold a machine-dependent built-in in GIMPLE. (For folding into
11188 a constant, use rs6000_fold_builtin.) */
11189
11190bool
11191rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
11192{
11193 gimple *stmt = gsi_stmt (*gsi);
11194 tree fndecl = gimple_call_fndecl (stmt);
11195 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
11196 enum rs6000_builtins fn_code
4d732405 11197 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 11198 tree arg0, arg1, lhs, temp;
11199 enum tree_code bcode;
11200 gimple *g;
11201
11202 size_t uns_fncode = (size_t) fn_code;
11203 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
11204 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
11205 const char *fn_name2 = (icode != CODE_FOR_nothing)
11206 ? get_insn_name ((int) icode)
11207 : "nothing";
11208
11209 if (TARGET_DEBUG_BUILTIN)
11210 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
11211 fn_code, fn_name1, fn_name2);
11212
11213 if (!rs6000_fold_gimple)
11214 return false;
11215
11216 /* Prevent gimple folding for code that does not have a LHS, unless it is
11217 allowed per the rs6000_builtin_valid_without_lhs helper function. */
11218 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
11219 return false;
11220
11221 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
8ee2640b 11222 if (!rs6000_builtin_is_supported_p (fn_code))
1acf0246
BS		 11223 return false;
11224
8ee2640b
PB		 11225 if (rs6000_gimple_fold_mma_builtin (gsi))
11226 return true;
11227
1acf0246
BS		 11228 switch (fn_code)
11229 {
11230 /* Flavors of vec_add. We deliberately don't expand
11231 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
11232 TImode, resulting in much poorer code generation. */
11233 case ALTIVEC_BUILTIN_VADDUBM:
11234 case ALTIVEC_BUILTIN_VADDUHM:
11235 case ALTIVEC_BUILTIN_VADDUWM:
11236 case P8V_BUILTIN_VADDUDM:
11237 case ALTIVEC_BUILTIN_VADDFP:
11238 case VSX_BUILTIN_XVADDDP:
11239 bcode = PLUS_EXPR;
11240 do_binary:
11241 arg0 = gimple_call_arg (stmt, 0);
11242 arg1 = gimple_call_arg (stmt, 1);
11243 lhs = gimple_call_lhs (stmt);
11244 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs)))
11245 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs))))
11246 {
11247 /* Ensure the binary operation is performed in a type
11248 that wraps if it is integral type. */
11249 gimple_seq stmts = NULL;
11250 tree type = unsigned_type_for (TREE_TYPE (lhs));
11251 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11252 type, arg0);
11253 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11254 type, arg1);
11255 tree res = gimple_build (&stmts, gimple_location (stmt), bcode,
11256 type, uarg0, uarg1);
11257 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11258 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR,
11259 build1 (VIEW_CONVERT_EXPR,
11260 TREE_TYPE (lhs), res));
11261 gsi_replace (gsi, g, true);
11262 return true;
11263 }
11264 g = gimple_build_assign (lhs, bcode, arg0, arg1);
11265 gimple_set_location (g, gimple_location (stmt));
11266 gsi_replace (gsi, g, true);
11267 return true;
11268 /* Flavors of vec_sub. We deliberately don't expand
11269 P8V_BUILTIN_VSUBUQM. */
11270 case ALTIVEC_BUILTIN_VSUBUBM:
11271 case ALTIVEC_BUILTIN_VSUBUHM:
11272 case ALTIVEC_BUILTIN_VSUBUWM:
11273 case P8V_BUILTIN_VSUBUDM:
11274 case ALTIVEC_BUILTIN_VSUBFP:
11275 case VSX_BUILTIN_XVSUBDP:
11276 bcode = MINUS_EXPR;
11277 goto do_binary;
11278 case VSX_BUILTIN_XVMULSP:
11279 case VSX_BUILTIN_XVMULDP:
11280 arg0 = gimple_call_arg (stmt, 0);
11281 arg1 = gimple_call_arg (stmt, 1);
11282 lhs = gimple_call_lhs (stmt);
11283 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
11284 gimple_set_location (g, gimple_location (stmt));
11285 gsi_replace (gsi, g, true);
11286 return true;
11287 /* Even element flavors of vec_mul (signed). */
11288 case ALTIVEC_BUILTIN_VMULESB:
11289 case ALTIVEC_BUILTIN_VMULESH:
11290 case P8V_BUILTIN_VMULESW:
11291 /* Even element flavors of vec_mul (unsigned). */
11292 case ALTIVEC_BUILTIN_VMULEUB:
11293 case ALTIVEC_BUILTIN_VMULEUH:
11294 case P8V_BUILTIN_VMULEUW:
11295 arg0 = gimple_call_arg (stmt, 0);
11296 arg1 = gimple_call_arg (stmt, 1);
11297 lhs = gimple_call_lhs (stmt);
11298 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
11299 gimple_set_location (g, gimple_location (stmt));
11300 gsi_replace (gsi, g, true);
11301 return true;
11302 /* Odd element flavors of vec_mul (signed). */
11303 case ALTIVEC_BUILTIN_VMULOSB:
11304 case ALTIVEC_BUILTIN_VMULOSH:
11305 case P8V_BUILTIN_VMULOSW:
11306 /* Odd element flavors of vec_mul (unsigned). */
11307 case ALTIVEC_BUILTIN_VMULOUB:
11308 case ALTIVEC_BUILTIN_VMULOUH:
11309 case P8V_BUILTIN_VMULOUW:
11310 arg0 = gimple_call_arg (stmt, 0);
11311 arg1 = gimple_call_arg (stmt, 1);
11312 lhs = gimple_call_lhs (stmt);
11313 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
11314 gimple_set_location (g, gimple_location (stmt));
11315 gsi_replace (gsi, g, true);
11316 return true;
11317 /* Flavors of vec_div (Integer). */
11318 case VSX_BUILTIN_DIV_V2DI:
11319 case VSX_BUILTIN_UDIV_V2DI:
11320 arg0 = gimple_call_arg (stmt, 0);
11321 arg1 = gimple_call_arg (stmt, 1);
11322 lhs = gimple_call_lhs (stmt);
11323 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
11324 gimple_set_location (g, gimple_location (stmt));
11325 gsi_replace (gsi, g, true);
11326 return true;
11327 /* Flavors of vec_div (Float). */
11328 case VSX_BUILTIN_XVDIVSP:
11329 case VSX_BUILTIN_XVDIVDP:
11330 arg0 = gimple_call_arg (stmt, 0);
11331 arg1 = gimple_call_arg (stmt, 1);
11332 lhs = gimple_call_lhs (stmt);
11333 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
11334 gimple_set_location (g, gimple_location (stmt));
11335 gsi_replace (gsi, g, true);
11336 return true;
11337 /* Flavors of vec_and. */
4559be23
PB		 11338 case ALTIVEC_BUILTIN_VAND_V16QI_UNS:
11339 case ALTIVEC_BUILTIN_VAND_V16QI:
11340 case ALTIVEC_BUILTIN_VAND_V8HI_UNS:
11341 case ALTIVEC_BUILTIN_VAND_V8HI:
11342 case ALTIVEC_BUILTIN_VAND_V4SI_UNS:
11343 case ALTIVEC_BUILTIN_VAND_V4SI:
11344 case ALTIVEC_BUILTIN_VAND_V2DI_UNS:
11345 case ALTIVEC_BUILTIN_VAND_V2DI:
11346 case ALTIVEC_BUILTIN_VAND_V4SF:
11347 case ALTIVEC_BUILTIN_VAND_V2DF:
1acf0246
BS		 11348 arg0 = gimple_call_arg (stmt, 0);
11349 arg1 = gimple_call_arg (stmt, 1);
11350 lhs = gimple_call_lhs (stmt);
11351 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
11352 gimple_set_location (g, gimple_location (stmt));
11353 gsi_replace (gsi, g, true);
11354 return true;
11355 /* Flavors of vec_andc. */
4559be23
PB		 11356 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS:
11357 case ALTIVEC_BUILTIN_VANDC_V16QI:
11358 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS:
11359 case ALTIVEC_BUILTIN_VANDC_V8HI:
11360 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS:
11361 case ALTIVEC_BUILTIN_VANDC_V4SI:
11362 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS:
11363 case ALTIVEC_BUILTIN_VANDC_V2DI:
11364 case ALTIVEC_BUILTIN_VANDC_V4SF:
11365 case ALTIVEC_BUILTIN_VANDC_V2DF:
1acf0246
BS		 11366 arg0 = gimple_call_arg (stmt, 0);
11367 arg1 = gimple_call_arg (stmt, 1);
11368 lhs = gimple_call_lhs (stmt);
11369 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
11370 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
11371 gimple_set_location (g, gimple_location (stmt));
11372 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11373 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
11374 gimple_set_location (g, gimple_location (stmt));
11375 gsi_replace (gsi, g, true);
11376 return true;
11377 /* Flavors of vec_nand. */
11378 case P8V_BUILTIN_VEC_NAND:
4559be23 11379 case P8V_BUILTIN_NAND_V16QI_UNS:
1acf0246 11380 case P8V_BUILTIN_NAND_V16QI:
4559be23 11381 case P8V_BUILTIN_NAND_V8HI_UNS:
1acf0246 11382 case P8V_BUILTIN_NAND_V8HI:
4559be23 11383 case P8V_BUILTIN_NAND_V4SI_UNS:
1acf0246 11384 case P8V_BUILTIN_NAND_V4SI:
4559be23
PB		 11385 case P8V_BUILTIN_NAND_V2DI_UNS:
11386 case P8V_BUILTIN_NAND_V2DI:
1acf0246
BS		 11387 case P8V_BUILTIN_NAND_V4SF:
11388 case P8V_BUILTIN_NAND_V2DF:
1acf0246
BS		 11389 arg0 = gimple_call_arg (stmt, 0);
11390 arg1 = gimple_call_arg (stmt, 1);
11391 lhs = gimple_call_lhs (stmt);
11392 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
11393 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
11394 gimple_set_location (g, gimple_location (stmt));
11395 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11396 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
11397 gimple_set_location (g, gimple_location (stmt));
11398 gsi_replace (gsi, g, true);
11399 return true;
11400 /* Flavors of vec_or. */
4559be23
PB		 11401 case ALTIVEC_BUILTIN_VOR_V16QI_UNS:
11402 case ALTIVEC_BUILTIN_VOR_V16QI:
11403 case ALTIVEC_BUILTIN_VOR_V8HI_UNS:
11404 case ALTIVEC_BUILTIN_VOR_V8HI:
11405 case ALTIVEC_BUILTIN_VOR_V4SI_UNS:
11406 case ALTIVEC_BUILTIN_VOR_V4SI:
11407 case ALTIVEC_BUILTIN_VOR_V2DI_UNS:
11408 case ALTIVEC_BUILTIN_VOR_V2DI:
11409 case ALTIVEC_BUILTIN_VOR_V4SF:
11410 case ALTIVEC_BUILTIN_VOR_V2DF:
1acf0246
BS		 11411 arg0 = gimple_call_arg (stmt, 0);
11412 arg1 = gimple_call_arg (stmt, 1);
11413 lhs = gimple_call_lhs (stmt);
11414 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
11415 gimple_set_location (g, gimple_location (stmt));
11416 gsi_replace (gsi, g, true);
11417 return true;
11418 /* flavors of vec_orc. */
4559be23 11419 case P8V_BUILTIN_ORC_V16QI_UNS:
1acf0246 11420 case P8V_BUILTIN_ORC_V16QI:
4559be23 11421 case P8V_BUILTIN_ORC_V8HI_UNS:
1acf0246 11422 case P8V_BUILTIN_ORC_V8HI:
4559be23 11423 case P8V_BUILTIN_ORC_V4SI_UNS:
1acf0246 11424 case P8V_BUILTIN_ORC_V4SI:
4559be23
PB		 11425 case P8V_BUILTIN_ORC_V2DI_UNS:
11426 case P8V_BUILTIN_ORC_V2DI:
1acf0246
BS		 11427 case P8V_BUILTIN_ORC_V4SF:
11428 case P8V_BUILTIN_ORC_V2DF:
1acf0246
BS		 11429 arg0 = gimple_call_arg (stmt, 0);
11430 arg1 = gimple_call_arg (stmt, 1);
11431 lhs = gimple_call_lhs (stmt);
11432 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
11433 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
11434 gimple_set_location (g, gimple_location (stmt));
11435 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11436 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
11437 gimple_set_location (g, gimple_location (stmt));
11438 gsi_replace (gsi, g, true);
11439 return true;
11440 /* Flavors of vec_xor. */
4559be23
PB		 11441 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS:
11442 case ALTIVEC_BUILTIN_VXOR_V16QI:
11443 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS:
11444 case ALTIVEC_BUILTIN_VXOR_V8HI:
11445 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS:
11446 case ALTIVEC_BUILTIN_VXOR_V4SI:
11447 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS:
11448 case ALTIVEC_BUILTIN_VXOR_V2DI:
11449 case ALTIVEC_BUILTIN_VXOR_V4SF:
11450 case ALTIVEC_BUILTIN_VXOR_V2DF:
1acf0246
BS		 11451 arg0 = gimple_call_arg (stmt, 0);
11452 arg1 = gimple_call_arg (stmt, 1);
11453 lhs = gimple_call_lhs (stmt);
11454 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
11455 gimple_set_location (g, gimple_location (stmt));
11456 gsi_replace (gsi, g, true);
11457 return true;
11458 /* Flavors of vec_nor. */
4559be23
PB		 11459 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS:
11460 case ALTIVEC_BUILTIN_VNOR_V16QI:
11461 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS:
11462 case ALTIVEC_BUILTIN_VNOR_V8HI:
11463 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS:
11464 case ALTIVEC_BUILTIN_VNOR_V4SI:
11465 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS:
11466 case ALTIVEC_BUILTIN_VNOR_V2DI:
11467 case ALTIVEC_BUILTIN_VNOR_V4SF:
11468 case ALTIVEC_BUILTIN_VNOR_V2DF:
1acf0246
BS		 11469 arg0 = gimple_call_arg (stmt, 0);
11470 arg1 = gimple_call_arg (stmt, 1);
11471 lhs = gimple_call_lhs (stmt);
11472 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
11473 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
11474 gimple_set_location (g, gimple_location (stmt));
11475 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11476 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
11477 gimple_set_location (g, gimple_location (stmt));
11478 gsi_replace (gsi, g, true);
11479 return true;
11480 /* flavors of vec_abs. */
11481 case ALTIVEC_BUILTIN_ABS_V16QI:
11482 case ALTIVEC_BUILTIN_ABS_V8HI:
11483 case ALTIVEC_BUILTIN_ABS_V4SI:
11484 case ALTIVEC_BUILTIN_ABS_V4SF:
11485 case P8V_BUILTIN_ABS_V2DI:
11486 case VSX_BUILTIN_XVABSDP:
11487 arg0 = gimple_call_arg (stmt, 0);
11488 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
11489 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
11490 return false;
11491 lhs = gimple_call_lhs (stmt);
11492 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
11493 gimple_set_location (g, gimple_location (stmt));
11494 gsi_replace (gsi, g, true);
11495 return true;
11496 /* flavors of vec_min. */
11497 case VSX_BUILTIN_XVMINDP:
11498 case P8V_BUILTIN_VMINSD:
11499 case P8V_BUILTIN_VMINUD:
11500 case ALTIVEC_BUILTIN_VMINSB:
11501 case ALTIVEC_BUILTIN_VMINSH:
11502 case ALTIVEC_BUILTIN_VMINSW:
11503 case ALTIVEC_BUILTIN_VMINUB:
11504 case ALTIVEC_BUILTIN_VMINUH:
11505 case ALTIVEC_BUILTIN_VMINUW:
11506 case ALTIVEC_BUILTIN_VMINFP:
11507 arg0 = gimple_call_arg (stmt, 0);
11508 arg1 = gimple_call_arg (stmt, 1);
11509 lhs = gimple_call_lhs (stmt);
11510 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
11511 gimple_set_location (g, gimple_location (stmt));
11512 gsi_replace (gsi, g, true);
11513 return true;
11514 /* flavors of vec_max. */
11515 case VSX_BUILTIN_XVMAXDP:
11516 case P8V_BUILTIN_VMAXSD:
11517 case P8V_BUILTIN_VMAXUD:
11518 case ALTIVEC_BUILTIN_VMAXSB:
11519 case ALTIVEC_BUILTIN_VMAXSH:
11520 case ALTIVEC_BUILTIN_VMAXSW:
11521 case ALTIVEC_BUILTIN_VMAXUB:
11522 case ALTIVEC_BUILTIN_VMAXUH:
11523 case ALTIVEC_BUILTIN_VMAXUW:
11524 case ALTIVEC_BUILTIN_VMAXFP:
11525 arg0 = gimple_call_arg (stmt, 0);
11526 arg1 = gimple_call_arg (stmt, 1);
11527 lhs = gimple_call_lhs (stmt);
11528 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
11529 gimple_set_location (g, gimple_location (stmt));
11530 gsi_replace (gsi, g, true);
11531 return true;
11532 /* Flavors of vec_eqv. */
11533 case P8V_BUILTIN_EQV_V16QI:
11534 case P8V_BUILTIN_EQV_V8HI:
11535 case P8V_BUILTIN_EQV_V4SI:
11536 case P8V_BUILTIN_EQV_V4SF:
11537 case P8V_BUILTIN_EQV_V2DF:
11538 case P8V_BUILTIN_EQV_V2DI:
11539 arg0 = gimple_call_arg (stmt, 0);
11540 arg1 = gimple_call_arg (stmt, 1);
11541 lhs = gimple_call_lhs (stmt);
11542 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
11543 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
11544 gimple_set_location (g, gimple_location (stmt));
11545 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11546 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
11547 gimple_set_location (g, gimple_location (stmt));
11548 gsi_replace (gsi, g, true);
11549 return true;
11550 /* Flavors of vec_rotate_left. */
11551 case ALTIVEC_BUILTIN_VRLB:
11552 case ALTIVEC_BUILTIN_VRLH:
11553 case ALTIVEC_BUILTIN_VRLW:
11554 case P8V_BUILTIN_VRLD:
11555 arg0 = gimple_call_arg (stmt, 0);
11556 arg1 = gimple_call_arg (stmt, 1);
11557 lhs = gimple_call_lhs (stmt);
11558 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
11559 gimple_set_location (g, gimple_location (stmt));
11560 gsi_replace (gsi, g, true);
11561 return true;
11562 /* Flavors of vector shift right algebraic.
11563 vec_sra{b,h,w} -> vsra{b,h,w}. */
11564 case ALTIVEC_BUILTIN_VSRAB:
11565 case ALTIVEC_BUILTIN_VSRAH:
11566 case ALTIVEC_BUILTIN_VSRAW:
11567 case P8V_BUILTIN_VSRAD:
11568 {
11569 arg0 = gimple_call_arg (stmt, 0);
11570 arg1 = gimple_call_arg (stmt, 1);
11571 lhs = gimple_call_lhs (stmt);
11572 tree arg1_type = TREE_TYPE (arg1);
11573 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
11574 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
11575 location_t loc = gimple_location (stmt);
11576 /* Force arg1 into the range valid matching the arg0 type. */
11577 /* Build a vector consisting of the max valid bit-size values. */
11578 int n_elts = VECTOR_CST_NELTS (arg1);
11579 tree element_size = build_int_cst (unsigned_element_type,
11580 128 / n_elts);
11581 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
11582 for (int i = 0; i < n_elts; i++)
11583 elts.safe_push (element_size);
11584 tree modulo_tree = elts.build ();
11585 /* Modulo the provided shift value against that vector. */
11586 gimple_seq stmts = NULL;
11587 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11588 unsigned_arg1_type, arg1);
11589 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
11590 unsigned_arg1_type, unsigned_arg1,
11591 modulo_tree);
11592 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11593 /* And finally, do the shift. */
11594 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1);
11595 gimple_set_location (g, loc);
11596 gsi_replace (gsi, g, true);
11597 return true;
11598 }
11599 /* Flavors of vector shift left.
11600 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
11601 case ALTIVEC_BUILTIN_VSLB:
11602 case ALTIVEC_BUILTIN_VSLH:
11603 case ALTIVEC_BUILTIN_VSLW:
11604 case P8V_BUILTIN_VSLD:
11605 {
11606 location_t loc;
11607 gimple_seq stmts = NULL;
11608 arg0 = gimple_call_arg (stmt, 0);
11609 tree arg0_type = TREE_TYPE (arg0);
11610 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
11611 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
11612 return false;
11613 arg1 = gimple_call_arg (stmt, 1);
11614 tree arg1_type = TREE_TYPE (arg1);
11615 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
11616 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
11617 loc = gimple_location (stmt);
11618 lhs = gimple_call_lhs (stmt);
11619 /* Force arg1 into the range valid matching the arg0 type. */
11620 /* Build a vector consisting of the max valid bit-size values. */
11621 int n_elts = VECTOR_CST_NELTS (arg1);
11622 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
11623 * BITS_PER_UNIT;
11624 tree element_size = build_int_cst (unsigned_element_type,
11625 tree_size_in_bits / n_elts);
11626 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
11627 for (int i = 0; i < n_elts; i++)
11628 elts.safe_push (element_size);
11629 tree modulo_tree = elts.build ();
11630 /* Modulo the provided shift value against that vector. */
11631 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11632 unsigned_arg1_type, arg1);
11633 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
11634 unsigned_arg1_type, unsigned_arg1,
11635 modulo_tree);
11636 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11637 /* And finally, do the shift. */
11638 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
11639 gimple_set_location (g, gimple_location (stmt));
11640 gsi_replace (gsi, g, true);
11641 return true;
11642 }
11643 /* Flavors of vector shift right. */
11644 case ALTIVEC_BUILTIN_VSRB:
11645 case ALTIVEC_BUILTIN_VSRH:
11646 case ALTIVEC_BUILTIN_VSRW:
11647 case P8V_BUILTIN_VSRD:
11648 {
11649 arg0 = gimple_call_arg (stmt, 0);
11650 arg1 = gimple_call_arg (stmt, 1);
11651 lhs = gimple_call_lhs (stmt);
11652 tree arg1_type = TREE_TYPE (arg1);
11653 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
11654 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
11655 location_t loc = gimple_location (stmt);
11656 gimple_seq stmts = NULL;
11657 /* Convert arg0 to unsigned. */
11658 tree arg0_unsigned
11659 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11660 unsigned_type_for (TREE_TYPE (arg0)), arg0);
11661 /* Force arg1 into the range valid matching the arg0 type. */
11662 /* Build a vector consisting of the max valid bit-size values. */
11663 int n_elts = VECTOR_CST_NELTS (arg1);
11664 tree element_size = build_int_cst (unsigned_element_type,
11665 128 / n_elts);
11666 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
11667 for (int i = 0; i < n_elts; i++)
11668 elts.safe_push (element_size);
11669 tree modulo_tree = elts.build ();
11670 /* Modulo the provided shift value against that vector. */
11671 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11672 unsigned_arg1_type, arg1);
11673 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
11674 unsigned_arg1_type, unsigned_arg1,
11675 modulo_tree);
11676 /* Do the shift. */
11677 tree res
11678 = gimple_build (&stmts, RSHIFT_EXPR,
11679 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1);
11680 /* Convert result back to the lhs type. */
11681 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
11682 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11683 update_call_from_tree (gsi, res);
11684 return true;
11685 }
11686 /* Vector loads. */
11687 case ALTIVEC_BUILTIN_LVX_V16QI:
11688 case ALTIVEC_BUILTIN_LVX_V8HI:
11689 case ALTIVEC_BUILTIN_LVX_V4SI:
11690 case ALTIVEC_BUILTIN_LVX_V4SF:
11691 case ALTIVEC_BUILTIN_LVX_V2DI:
11692 case ALTIVEC_BUILTIN_LVX_V2DF:
11693 case ALTIVEC_BUILTIN_LVX_V1TI:
11694 {
11695 arg0 = gimple_call_arg (stmt, 0); // offset
11696 arg1 = gimple_call_arg (stmt, 1); // address
11697 lhs = gimple_call_lhs (stmt);
11698 location_t loc = gimple_location (stmt);
11699 /* Since arg1 may be cast to a different type, just use ptr_type_node
11700 here instead of trying to enforce TBAA on pointer types. */
11701 tree arg1_type = ptr_type_node;
11702 tree lhs_type = TREE_TYPE (lhs);
11703 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
11704 the tree using the value from arg0. The resulting type will match
11705 the type of arg1. */
11706 gimple_seq stmts = NULL;
11707 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
11708 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
11709 arg1_type, arg1, temp_offset);
11710 /* Mask off any lower bits from the address. */
11711 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
11712 arg1_type, temp_addr,
11713 build_int_cst (arg1_type, -16));
11714 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11715 if (!is_gimple_mem_ref_addr (aligned_addr))
11716 {
11717 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
11718 gimple *g = gimple_build_assign (t, aligned_addr);
11719 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11720 aligned_addr = t;
11721 }
11722 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
11723 take an offset, but since we've already incorporated the offset
11724 above, here we just pass in a zero. */
11725 gimple *g
11726 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
11727 build_int_cst (arg1_type, 0)));
11728 gimple_set_location (g, loc);
11729 gsi_replace (gsi, g, true);
11730 return true;
11731 }
11732 /* Vector stores. */
11733 case ALTIVEC_BUILTIN_STVX_V16QI:
11734 case ALTIVEC_BUILTIN_STVX_V8HI:
11735 case ALTIVEC_BUILTIN_STVX_V4SI:
11736 case ALTIVEC_BUILTIN_STVX_V4SF:
11737 case ALTIVEC_BUILTIN_STVX_V2DI:
11738 case ALTIVEC_BUILTIN_STVX_V2DF:
11739 {
11740 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
11741 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
11742 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
11743 location_t loc = gimple_location (stmt);
11744 tree arg0_type = TREE_TYPE (arg0);
11745 /* Use ptr_type_node (no TBAA) for the arg2_type.
11746 FIXME: (Richard) "A proper fix would be to transition this type as
11747 seen from the frontend to GIMPLE, for example in a similar way we
11748 do for MEM_REFs by piggy-backing that on an extra argument, a
11749 constant zero pointer of the alias pointer type to use (which would
11750 also serve as a type indicator of the store itself). I'd use a
11751 target specific internal function for this (not sure if we can have
11752 those target specific, but I guess if it's folded away then that's
11753 fine) and get away with the overload set." */
11754 tree arg2_type = ptr_type_node;
11755 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
11756 the tree using the value from arg0. The resulting type will match
11757 the type of arg2. */
11758 gimple_seq stmts = NULL;
11759 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
11760 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
11761 arg2_type, arg2, temp_offset);
11762 /* Mask off any lower bits from the address. */
11763 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
11764 arg2_type, temp_addr,
11765 build_int_cst (arg2_type, -16));
11766 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11767 if (!is_gimple_mem_ref_addr (aligned_addr))
11768 {
11769 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
11770 gimple *g = gimple_build_assign (t, aligned_addr);
11771 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11772 aligned_addr = t;
11773 }
11774 /* The desired gimple result should be similar to:
11775 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
11776 gimple *g
11777 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
11778 build_int_cst (arg2_type, 0)), arg0);
11779 gimple_set_location (g, loc);
11780 gsi_replace (gsi, g, true);
11781 return true;
11782 }
11783
11784 /* unaligned Vector loads. */
11785 case VSX_BUILTIN_LXVW4X_V16QI:
11786 case VSX_BUILTIN_LXVW4X_V8HI:
11787 case VSX_BUILTIN_LXVW4X_V4SF:
11788 case VSX_BUILTIN_LXVW4X_V4SI:
11789 case VSX_BUILTIN_LXVD2X_V2DF:
11790 case VSX_BUILTIN_LXVD2X_V2DI:
11791 {
11792 arg0 = gimple_call_arg (stmt, 0); // offset
11793 arg1 = gimple_call_arg (stmt, 1); // address
11794 lhs = gimple_call_lhs (stmt);
11795 location_t loc = gimple_location (stmt);
11796 /* Since arg1 may be cast to a different type, just use ptr_type_node
11797 here instead of trying to enforce TBAA on pointer types. */
11798 tree arg1_type = ptr_type_node;
11799 tree lhs_type = TREE_TYPE (lhs);
11800 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
11801 required alignment (power) is 4 bytes regardless of data type. */
11802 tree align_ltype = build_aligned_type (lhs_type, 4);
11803 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
11804 the tree using the value from arg0. The resulting type will match
11805 the type of arg1. */
11806 gimple_seq stmts = NULL;
11807 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
11808 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
11809 arg1_type, arg1, temp_offset);
11810 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11811 if (!is_gimple_mem_ref_addr (temp_addr))
11812 {
11813 tree t = make_ssa_name (TREE_TYPE (temp_addr));
11814 gimple *g = gimple_build_assign (t, temp_addr);
11815 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11816 temp_addr = t;
11817 }
11818 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
11819 take an offset, but since we've already incorporated the offset
11820 above, here we just pass in a zero. */
11821 gimple *g;
11822 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
11823 build_int_cst (arg1_type, 0)));
11824 gimple_set_location (g, loc);
11825 gsi_replace (gsi, g, true);
11826 return true;
11827 }
11828
11829 /* unaligned Vector stores. */
11830 case VSX_BUILTIN_STXVW4X_V16QI:
11831 case VSX_BUILTIN_STXVW4X_V8HI:
11832 case VSX_BUILTIN_STXVW4X_V4SF:
11833 case VSX_BUILTIN_STXVW4X_V4SI:
11834 case VSX_BUILTIN_STXVD2X_V2DF:
11835 case VSX_BUILTIN_STXVD2X_V2DI:
11836 {
11837 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
11838 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
11839 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
11840 location_t loc = gimple_location (stmt);
11841 tree arg0_type = TREE_TYPE (arg0);
11842 /* Use ptr_type_node (no TBAA) for the arg2_type. */
11843 tree arg2_type = ptr_type_node;
11844 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
11845 required alignment (power) is 4 bytes regardless of data type. */
11846 tree align_stype = build_aligned_type (arg0_type, 4);
11847 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
11848 the tree using the value from arg1. */
11849 gimple_seq stmts = NULL;
11850 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
11851 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
11852 arg2_type, arg2, temp_offset);
11853 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11854 if (!is_gimple_mem_ref_addr (temp_addr))
11855 {
11856 tree t = make_ssa_name (TREE_TYPE (temp_addr));
11857 gimple *g = gimple_build_assign (t, temp_addr);
11858 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11859 temp_addr = t;
11860 }
11861 gimple *g;
11862 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
11863 build_int_cst (arg2_type, 0)), arg0);
11864 gimple_set_location (g, loc);
11865 gsi_replace (gsi, g, true);
11866 return true;
11867 }
11868
11869 /* Vector Fused multiply-add (fma). */
11870 case ALTIVEC_BUILTIN_VMADDFP:
11871 case VSX_BUILTIN_XVMADDDP:
11872 case ALTIVEC_BUILTIN_VMLADDUHM:
11873 {
11874 arg0 = gimple_call_arg (stmt, 0);
11875 arg1 = gimple_call_arg (stmt, 1);
11876 tree arg2 = gimple_call_arg (stmt, 2);
11877 lhs = gimple_call_lhs (stmt);
11878 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
11879 gimple_call_set_lhs (g, lhs);
11880 gimple_call_set_nothrow (g, true);
11881 gimple_set_location (g, gimple_location (stmt));
11882 gsi_replace (gsi, g, true);
11883 return true;
11884 }
11885
11886 /* Vector compares; EQ, NE, GE, GT, LE. */
11887 case ALTIVEC_BUILTIN_VCMPEQUB:
11888 case ALTIVEC_BUILTIN_VCMPEQUH:
11889 case ALTIVEC_BUILTIN_VCMPEQUW:
11890 case P8V_BUILTIN_VCMPEQUD:
11891 fold_compare_helper (gsi, EQ_EXPR, stmt);
11892 return true;
11893
11894 case P9V_BUILTIN_CMPNEB:
11895 case P9V_BUILTIN_CMPNEH:
11896 case P9V_BUILTIN_CMPNEW:
11897 fold_compare_helper (gsi, NE_EXPR, stmt);
11898 return true;
11899
11900 case VSX_BUILTIN_CMPGE_16QI:
11901 case VSX_BUILTIN_CMPGE_U16QI:
11902 case VSX_BUILTIN_CMPGE_8HI:
11903 case VSX_BUILTIN_CMPGE_U8HI:
11904 case VSX_BUILTIN_CMPGE_4SI:
11905 case VSX_BUILTIN_CMPGE_U4SI:
11906 case VSX_BUILTIN_CMPGE_2DI:
11907 case VSX_BUILTIN_CMPGE_U2DI:
11908 fold_compare_helper (gsi, GE_EXPR, stmt);
11909 return true;
11910
11911 case ALTIVEC_BUILTIN_VCMPGTSB:
11912 case ALTIVEC_BUILTIN_VCMPGTUB:
11913 case ALTIVEC_BUILTIN_VCMPGTSH:
11914 case ALTIVEC_BUILTIN_VCMPGTUH:
11915 case ALTIVEC_BUILTIN_VCMPGTSW:
11916 case ALTIVEC_BUILTIN_VCMPGTUW:
11917 case P8V_BUILTIN_VCMPGTUD:
11918 case P8V_BUILTIN_VCMPGTSD:
11919 fold_compare_helper (gsi, GT_EXPR, stmt);
11920 return true;
11921
11922 case VSX_BUILTIN_CMPLE_16QI:
11923 case VSX_BUILTIN_CMPLE_U16QI:
11924 case VSX_BUILTIN_CMPLE_8HI:
11925 case VSX_BUILTIN_CMPLE_U8HI:
11926 case VSX_BUILTIN_CMPLE_4SI:
11927 case VSX_BUILTIN_CMPLE_U4SI:
11928 case VSX_BUILTIN_CMPLE_2DI:
11929 case VSX_BUILTIN_CMPLE_U2DI:
11930 fold_compare_helper (gsi, LE_EXPR, stmt);
11931 return true;
11932
11933 /* flavors of vec_splat_[us]{8,16,32}. */
11934 case ALTIVEC_BUILTIN_VSPLTISB:
11935 case ALTIVEC_BUILTIN_VSPLTISH:
11936 case ALTIVEC_BUILTIN_VSPLTISW:
11937 {
11938 arg0 = gimple_call_arg (stmt, 0);
11939 lhs = gimple_call_lhs (stmt);
11940
11941 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
11942 5-bit signed constant in range -16 to +15. */
11943 if (TREE_CODE (arg0) != INTEGER_CST
11944 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15))
11945 return false;
11946 gimple_seq stmts = NULL;
11947 location_t loc = gimple_location (stmt);
11948 tree splat_value = gimple_convert (&stmts, loc,
11949 TREE_TYPE (TREE_TYPE (lhs)), arg0);
11950 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11951 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
11952 g = gimple_build_assign (lhs, splat_tree);
11953 gimple_set_location (g, gimple_location (stmt));
11954 gsi_replace (gsi, g, true);
11955 return true;
11956 }
11957
11958 /* Flavors of vec_splat. */
11959 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
11960 case ALTIVEC_BUILTIN_VSPLTB:
11961 case ALTIVEC_BUILTIN_VSPLTH:
11962 case ALTIVEC_BUILTIN_VSPLTW:
11963 case VSX_BUILTIN_XXSPLTD_V2DI:
11964 case VSX_BUILTIN_XXSPLTD_V2DF:
11965 {
11966 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
11967 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
11968 /* Only fold the vec_splat_*() if arg1 is both a constant value and
11969 is a valid index into the arg0 vector. */
11970 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
11971 if (TREE_CODE (arg1) != INTEGER_CST
11972 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
11973 return false;
11974 lhs = gimple_call_lhs (stmt);
11975 tree lhs_type = TREE_TYPE (lhs);
11976 tree arg0_type = TREE_TYPE (arg0);
11977 tree splat;
11978 if (TREE_CODE (arg0) == VECTOR_CST)
11979 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
11980 else
11981 {
11982 /* Determine (in bits) the length and start location of the
11983 splat value for a call to the tree_vec_extract helper. */
11984 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
11985 * BITS_PER_UNIT / n_elts;
11986 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
11987 tree len = build_int_cst (bitsizetype, splat_elem_size);
11988 tree start = build_int_cst (bitsizetype, splat_start_bit);
11989 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
11990 len, start);
11991 }
11992 /* And finally, build the new vector. */
11993 tree splat_tree = build_vector_from_val (lhs_type, splat);
11994 g = gimple_build_assign (lhs, splat_tree);
11995 gimple_set_location (g, gimple_location (stmt));
11996 gsi_replace (gsi, g, true);
11997 return true;
11998 }
11999
12000 /* vec_mergel (integrals). */
12001 case ALTIVEC_BUILTIN_VMRGLH:
12002 case ALTIVEC_BUILTIN_VMRGLW:
12003 case VSX_BUILTIN_XXMRGLW_4SI:
12004 case ALTIVEC_BUILTIN_VMRGLB:
12005 case VSX_BUILTIN_VEC_MERGEL_V2DI:
12006 case VSX_BUILTIN_XXMRGLW_4SF:
12007 case VSX_BUILTIN_VEC_MERGEL_V2DF:
12008 fold_mergehl_helper (gsi, stmt, 1);
12009 return true;
12010 /* vec_mergeh (integrals). */
12011 case ALTIVEC_BUILTIN_VMRGHH:
12012 case ALTIVEC_BUILTIN_VMRGHW:
12013 case VSX_BUILTIN_XXMRGHW_4SI:
12014 case ALTIVEC_BUILTIN_VMRGHB:
12015 case VSX_BUILTIN_VEC_MERGEH_V2DI:
12016 case VSX_BUILTIN_XXMRGHW_4SF:
12017 case VSX_BUILTIN_VEC_MERGEH_V2DF:
12018 fold_mergehl_helper (gsi, stmt, 0);
12019 return true;
12020
12021 /* Flavors of vec_mergee. */
12022 case P8V_BUILTIN_VMRGEW_V4SI:
12023 case P8V_BUILTIN_VMRGEW_V2DI:
12024 case P8V_BUILTIN_VMRGEW_V4SF:
12025 case P8V_BUILTIN_VMRGEW_V2DF:
12026 fold_mergeeo_helper (gsi, stmt, 0);
12027 return true;
12028 /* Flavors of vec_mergeo. */
12029 case P8V_BUILTIN_VMRGOW_V4SI:
12030 case P8V_BUILTIN_VMRGOW_V2DI:
12031 case P8V_BUILTIN_VMRGOW_V4SF:
12032 case P8V_BUILTIN_VMRGOW_V2DF:
12033 fold_mergeeo_helper (gsi, stmt, 1);
12034 return true;
12035
12036 /* d = vec_pack (a, b) */
12037 case P8V_BUILTIN_VPKUDUM:
12038 case ALTIVEC_BUILTIN_VPKUHUM:
12039 case ALTIVEC_BUILTIN_VPKUWUM:
12040 {
12041 arg0 = gimple_call_arg (stmt, 0);
12042 arg1 = gimple_call_arg (stmt, 1);
12043 lhs = gimple_call_lhs (stmt);
12044 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
12045 gimple_set_location (g, gimple_location (stmt));
12046 gsi_replace (gsi, g, true);
12047 return true;
12048 }
12049
12050 /* d = vec_unpackh (a) */
12051 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
12052 in this code is sensitive to endian-ness, and needs to be inverted to
12053 handle both LE and BE targets. */
12054 case ALTIVEC_BUILTIN_VUPKHSB:
12055 case ALTIVEC_BUILTIN_VUPKHSH:
12056 case P8V_BUILTIN_VUPKHSW:
12057 {
12058 arg0 = gimple_call_arg (stmt, 0);
12059 lhs = gimple_call_lhs (stmt);
12060 if (BYTES_BIG_ENDIAN)
12061 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
12062 else
12063 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
12064 gimple_set_location (g, gimple_location (stmt));
12065 gsi_replace (gsi, g, true);
12066 return true;
12067 }
12068 /* d = vec_unpackl (a) */
12069 case ALTIVEC_BUILTIN_VUPKLSB:
12070 case ALTIVEC_BUILTIN_VUPKLSH:
12071 case P8V_BUILTIN_VUPKLSW:
12072 {
12073 arg0 = gimple_call_arg (stmt, 0);
12074 lhs = gimple_call_lhs (stmt);
12075 if (BYTES_BIG_ENDIAN)
12076 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
12077 else
12078 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
12079 gimple_set_location (g, gimple_location (stmt));
12080 gsi_replace (gsi, g, true);
12081 return true;
12082 }
12083 /* There is no gimple type corresponding with pixel, so just return. */
12084 case ALTIVEC_BUILTIN_VUPKHPX:
12085 case ALTIVEC_BUILTIN_VUPKLPX:
12086 return false;
12087
12088 /* vec_perm. */
12089 case ALTIVEC_BUILTIN_VPERM_16QI:
12090 case ALTIVEC_BUILTIN_VPERM_8HI:
12091 case ALTIVEC_BUILTIN_VPERM_4SI:
12092 case ALTIVEC_BUILTIN_VPERM_2DI:
12093 case ALTIVEC_BUILTIN_VPERM_4SF:
12094 case ALTIVEC_BUILTIN_VPERM_2DF:
12095 {
12096 arg0 = gimple_call_arg (stmt, 0);
12097 arg1 = gimple_call_arg (stmt, 1);
12098 tree permute = gimple_call_arg (stmt, 2);
12099 lhs = gimple_call_lhs (stmt);
12100 location_t loc = gimple_location (stmt);
12101 gimple_seq stmts = NULL;
12102 // convert arg0 and arg1 to match the type of the permute
12103 // for the VEC_PERM_EXPR operation.
12104 tree permute_type = (TREE_TYPE (permute));
b6d53324
RS		 12105 tree arg0_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
12106 permute_type, arg0);
12107 tree arg1_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
12108 permute_type, arg1);
1acf0246
BS		 12109 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
12110 permute_type, arg0_ptype, arg1_ptype,
12111 permute);
12112 // Convert the result back to the desired lhs type upon completion.
b6d53324
RS		 12113 tree temp = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
12114 TREE_TYPE (lhs), lhs_ptype);
1acf0246
BS		 12115 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12116 g = gimple_build_assign (lhs, temp);
12117 gimple_set_location (g, loc);
12118 gsi_replace (gsi, g, true);
12119 return true;
12120 }
12121
12122 default:
12123 if (TARGET_DEBUG_BUILTIN)
12124 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
12125 fn_code, fn_name1, fn_name2);
12126 break;
12127 }
12128
12129 return false;
12130}
12131
12132/* Expand an expression EXP that calls a built-in function,
12133 with result going to TARGET if that's convenient
12134 (and in mode MODE if that's convenient).
12135 SUBTARGET may be used as the target for computing one of EXP's operands.
12136 IGNORE is nonzero if the value is to be ignored. */
12137
12138rtx
12139rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
12140 machine_mode mode ATTRIBUTE_UNUSED,
12141 int ignore ATTRIBUTE_UNUSED)
12142{
12143 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
12144 enum rs6000_builtins fcode
4d732405 12145 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 12146 size_t uns_fcode = (size_t)fcode;
12147 const struct builtin_description *d;
12148 size_t i;
12149 rtx ret;
12150 bool success;
12151 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
12152 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
12153 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
12154
12155 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
12156 floating point type, depending on whether long double is the IBM extended
12157 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
12158 we only define one variant of the built-in function, and switch the code
12159 when defining it, rather than defining two built-ins and using the
12160 overload table in rs6000-c.c to switch between the two. If we don't have
12161 the proper assembler, don't do this switch because CODE_FOR_*kf* and
12162 CODE_FOR_*tf* will be CODE_FOR_nothing. */
12163 if (FLOAT128_IEEE_P (TFmode))
12164 switch (icode)
12165 {
12166 default:
12167 break;
12168
12169 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
12170 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
12171 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
12172 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
12173 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
12174 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
12175 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
12176 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
12177 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
12178 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
12179 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
12180 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
12181 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
12182 }
12183
12184 if (TARGET_DEBUG_BUILTIN)
12185 {
12186 const char *name1 = rs6000_builtin_info[uns_fcode].name;
12187 const char *name2 = (icode != CODE_FOR_nothing)
12188 ? get_insn_name ((int) icode)
12189 : "nothing";
12190 const char *name3;
12191
12192 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
12193 {
12194 default: name3 = "unknown"; break;
12195 case RS6000_BTC_SPECIAL: name3 = "special"; break;
12196 case RS6000_BTC_UNARY: name3 = "unary"; break;
12197 case RS6000_BTC_BINARY: name3 = "binary"; break;
12198 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
840ac85c 12199 case RS6000_BTC_QUATERNARY:name3 = "quaternary";break;
1acf0246
BS		 12200 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
12201 case RS6000_BTC_ABS: name3 = "abs"; break;
12202 case RS6000_BTC_DST: name3 = "dst"; break;
12203 }
12204
12205
12206 fprintf (stderr,
12207 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
12208 (name1) ? name1 : "---", fcode,
12209 (name2) ? name2 : "---", (int) icode,
12210 name3,
12211 func_valid_p ? "" : ", not valid");
12212 }
12213
12214 if (!func_valid_p)
12215 {
12216 rs6000_invalid_builtin (fcode);
12217
12218 /* Given it is invalid, just generate a normal call. */
12219 return expand_call (exp, target, ignore);
12220 }
12221
12222 switch (fcode)
12223 {
12224 case RS6000_BUILTIN_RECIP:
12225 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
12226
12227 case RS6000_BUILTIN_RECIPF:
12228 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
12229
12230 case RS6000_BUILTIN_RSQRTF:
12231 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
12232
12233 case RS6000_BUILTIN_RSQRT:
12234 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
12235
12236 case POWER7_BUILTIN_BPERMD:
12237 return rs6000_expand_binop_builtin (((TARGET_64BIT)
12238 ? CODE_FOR_bpermd_di
12239 : CODE_FOR_bpermd_si), exp, target);
12240
12241 case RS6000_BUILTIN_GET_TB:
12242 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
12243 target);
12244
12245 case RS6000_BUILTIN_MFTB:
12246 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
12247 ? CODE_FOR_rs6000_mftb_di
12248 : CODE_FOR_rs6000_mftb_si),
12249 target);
12250
12251 case RS6000_BUILTIN_MFFS:
12252 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
12253
12254 case RS6000_BUILTIN_MTFSB0:
12255 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
12256
12257 case RS6000_BUILTIN_MTFSB1:
12258 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
12259
12260 case RS6000_BUILTIN_SET_FPSCR_RN:
12261 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
12262 exp);
12263
12264 case RS6000_BUILTIN_SET_FPSCR_DRN:
12265 return
12266 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
12267 exp);
12268
12269 case RS6000_BUILTIN_MFFSL:
12270 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
12271
12272 case RS6000_BUILTIN_MTFSF:
12273 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
12274
12275 case RS6000_BUILTIN_CPU_INIT:
12276 case RS6000_BUILTIN_CPU_IS:
12277 case RS6000_BUILTIN_CPU_SUPPORTS:
12278 return cpu_expand_builtin (fcode, exp, target);
12279
12280 case MISC_BUILTIN_SPEC_BARRIER:
12281 {
12282 emit_insn (gen_speculation_barrier ());
12283 return NULL_RTX;
12284 }
12285
12286 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
12287 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
12288 {
12289 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
12290 : (int) CODE_FOR_altivec_lvsl_direct);
12291 machine_mode tmode = insn_data[icode2].operand[0].mode;
12292 machine_mode mode = insn_data[icode2].operand[1].mode;
12293 tree arg;
12294 rtx op, addr, pat;
12295
12296 gcc_assert (TARGET_ALTIVEC);
12297
12298 arg = CALL_EXPR_ARG (exp, 0);
12299 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
12300 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
12301 addr = memory_address (mode, op);
12302 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
12303 op = addr;
12304 else
12305 {
12306 /* For the load case need to negate the address. */
12307 op = gen_reg_rtx (GET_MODE (addr));
12308 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
12309 }
12310 op = gen_rtx_MEM (mode, op);
12311
12312 if (target == 0
12313 || GET_MODE (target) != tmode
12314 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
12315 target = gen_reg_rtx (tmode);
12316
12317 pat = GEN_FCN (icode2) (target, op);
12318 if (!pat)
12319 return 0;
12320 emit_insn (pat);
12321
12322 return target;
12323 }
12324
12325 case ALTIVEC_BUILTIN_VCFUX:
12326 case ALTIVEC_BUILTIN_VCFSX:
12327 case ALTIVEC_BUILTIN_VCTUXS:
12328 case ALTIVEC_BUILTIN_VCTSXS:
12329 /* FIXME: There's got to be a nicer way to handle this case than
12330 constructing a new CALL_EXPR. */
12331 if (call_expr_nargs (exp) == 1)
12332 {
12333 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
12334 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
12335 }
12336 break;
12337
12338 /* For the pack and unpack int128 routines, fix up the builtin so it
12339 uses the correct IBM128 type. */
12340 case MISC_BUILTIN_PACK_IF:
12341 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
12342 {
12343 icode = CODE_FOR_packtf;
12344 fcode = MISC_BUILTIN_PACK_TF;
12345 uns_fcode = (size_t)fcode;
12346 }
12347 break;
12348
12349 case MISC_BUILTIN_UNPACK_IF:
12350 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
12351 {
12352 icode = CODE_FOR_unpacktf;
12353 fcode = MISC_BUILTIN_UNPACK_TF;
12354 uns_fcode = (size_t)fcode;
12355 }
12356 break;
12357
12358 default:
12359 break;
12360 }
12361
8ee2640b
PB		 12362 if (TARGET_MMA)
12363 {
12364 ret = mma_expand_builtin (exp, target, &success);
12365
12366 if (success)
12367 return ret;
12368 }
1acf0246
BS		 12369 if (TARGET_ALTIVEC)
12370 {
12371 ret = altivec_expand_builtin (exp, target, &success);
12372
12373 if (success)
12374 return ret;
12375 }
12376 if (TARGET_HTM)
12377 {
12378 ret = htm_expand_builtin (exp, target, &success);
12379
12380 if (success)
12381 return ret;
12382 }
12383
8ee2640b 12384 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_OPND_MASK;
1acf0246
BS		 12385 /* RS6000_BTC_SPECIAL represents no-operand operators. */
12386 gcc_assert (attr == RS6000_BTC_UNARY
12387 || attr == RS6000_BTC_BINARY
12388 || attr == RS6000_BTC_TERNARY
840ac85c 12389 || attr == RS6000_BTC_QUATERNARY
1acf0246
BS		 12390 || attr == RS6000_BTC_SPECIAL);
12391
12392 /* Handle simple unary operations. */
12393 d = bdesc_1arg;
12394 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12395 if (d->code == fcode)
12396 return rs6000_expand_unop_builtin (icode, exp, target);
12397
12398 /* Handle simple binary operations. */
12399 d = bdesc_2arg;
12400 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12401 if (d->code == fcode)
12402 return rs6000_expand_binop_builtin (icode, exp, target);
12403
12404 /* Handle simple ternary operations. */
12405 d = bdesc_3arg;
12406 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
12407 if (d->code == fcode)
12408 return rs6000_expand_ternop_builtin (icode, exp, target);
12409
840ac85c
KN		 12410 /* Handle simple quaternary operations. */
12411 d = bdesc_4arg;
12412 for (i = 0; i < ARRAY_SIZE (bdesc_4arg); i++, d++)
12413 if (d->code == fcode)
12414 return rs6000_expand_quaternop_builtin (icode, exp, target);
12415
1acf0246
BS		 12416 /* Handle simple no-argument operations. */
12417 d = bdesc_0arg;
12418 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
12419 if (d->code == fcode)
12420 return rs6000_expand_zeroop_builtin (icode, target);
12421
12422 gcc_unreachable ();
12423}
12424
12425/* Create a builtin vector type with a name. Taking care not to give
12426 the canonical type a name. */
12427
12428static tree
12429rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
12430{
12431 tree result = build_vector_type (elt_type, num_elts);
12432
12433 /* Copy so we don't give the canonical type a name. */
12434 result = build_variant_type_copy (result);
12435
12436 add_builtin_type (name, result);
12437
12438 return result;
12439}
12440
12441void
12442rs6000_init_builtins (void)
12443{
12444 tree tdecl;
12445 tree ftype;
12446 machine_mode mode;
12447
12448 if (TARGET_DEBUG_BUILTIN)
12449 fprintf (stderr, "rs6000_init_builtins%s%s\n",
12450 (TARGET_ALTIVEC) ? ", altivec" : "",
12451 (TARGET_VSX) ? ", vsx" : "");
12452
12453 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
12454 : "__vector long long",
12455 intDI_type_node, 2);
12456 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
12457 V4SI_type_node = rs6000_vector_type ("__vector signed int",
12458 intSI_type_node, 4);
12459 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
12460 V8HI_type_node = rs6000_vector_type ("__vector signed short",
12461 intHI_type_node, 8);
12462 V16QI_type_node = rs6000_vector_type ("__vector signed char",
12463 intQI_type_node, 16);
12464
12465 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
12466 unsigned_intQI_type_node, 16);
12467 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
12468 unsigned_intHI_type_node, 8);
12469 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
12470 unsigned_intSI_type_node, 4);
12471 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
12472 ? "__vector unsigned long"
12473 : "__vector unsigned long long",
12474 unsigned_intDI_type_node, 2);
12475
12476 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
12477
12478 const_str_type_node
12479 = build_pointer_type (build_qualified_type (char_type_node,
12480 TYPE_QUAL_CONST));
12481
12482 /* We use V1TI mode as a special container to hold __int128_t items that
12483 must live in VSX registers. */
12484 if (intTI_type_node)
12485 {
12486 V1TI_type_node = rs6000_vector_type ("__vector __int128",
12487 intTI_type_node, 1);
12488 unsigned_V1TI_type_node
12489 = rs6000_vector_type ("__vector unsigned __int128",
12490 unsigned_intTI_type_node, 1);
12491 }
12492
12493 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
12494 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
12495 'vector unsigned short'. */
12496
12497 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
12498 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
12499 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
12500 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
12501 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
12502
12503 long_integer_type_internal_node = long_integer_type_node;
12504 long_unsigned_type_internal_node = long_unsigned_type_node;
12505 long_long_integer_type_internal_node = long_long_integer_type_node;
12506 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
12507 intQI_type_internal_node = intQI_type_node;
12508 uintQI_type_internal_node = unsigned_intQI_type_node;
12509 intHI_type_internal_node = intHI_type_node;
12510 uintHI_type_internal_node = unsigned_intHI_type_node;
12511 intSI_type_internal_node = intSI_type_node;
12512 uintSI_type_internal_node = unsigned_intSI_type_node;
12513 intDI_type_internal_node = intDI_type_node;
12514 uintDI_type_internal_node = unsigned_intDI_type_node;
12515 intTI_type_internal_node = intTI_type_node;
12516 uintTI_type_internal_node = unsigned_intTI_type_node;
12517 float_type_internal_node = float_type_node;
12518 double_type_internal_node = double_type_node;
12519 long_double_type_internal_node = long_double_type_node;
12520 dfloat64_type_internal_node = dfloat64_type_node;
12521 dfloat128_type_internal_node = dfloat128_type_node;
12522 void_type_internal_node = void_type_node;
12523
12524 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
12525 IFmode is the IBM extended 128-bit format that is a pair of doubles.
12526 TFmode will be either IEEE 128-bit floating point or the IBM double-double
12527 format that uses a pair of doubles, depending on the switches and
12528 defaults.
12529
12530 If we don't support for either 128-bit IBM double double or IEEE 128-bit
12531 floating point, we need make sure the type is non-zero or else self-test
12532 fails during bootstrap.
12533
12534 Always create __ibm128 as a separate type, even if the current long double
12535 format is IBM extended double.
12536
12537 For IEEE 128-bit floating point, always create the type __ieee128. If the
12538 user used -mfloat128, rs6000-c.c will create a define from __float128 to
12539 __ieee128. */
12540 if (TARGET_FLOAT128_TYPE)
12541 {
12542 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
12543 ibm128_float_type_node = long_double_type_node;
12544 else
12545 {
12546 ibm128_float_type_node = make_node (REAL_TYPE);
12547 TYPE_PRECISION (ibm128_float_type_node) = 128;
12548 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
12549 layout_type (ibm128_float_type_node);
12550 }
12551
12552 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
12553 "__ibm128");
12554
12555 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
12556 ieee128_float_type_node = long_double_type_node;
12557 else
12558 ieee128_float_type_node = float128_type_node;
12559
12560 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
12561 "__ieee128");
12562 }
12563
12564 else
12565 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
12566
8ee2640b 12567 /* Vector pair and vector quad support. */
f002c046
PB		 12568 if (TARGET_MMA)
12569 {
12570 tree oi_uns_type = make_unsigned_type (256);
12571 vector_pair_type_node = build_distinct_type_copy (oi_uns_type);
12572 SET_TYPE_MODE (vector_pair_type_node, POImode);
12573 layout_type (vector_pair_type_node);
12574 lang_hooks.types.register_builtin_type (vector_pair_type_node,
12575 "__vector_pair");
12576
12577 tree xi_uns_type = make_unsigned_type (512);
12578 vector_quad_type_node = build_distinct_type_copy (xi_uns_type);
12579 SET_TYPE_MODE (vector_quad_type_node, PXImode);
12580 layout_type (vector_quad_type_node);
12581 lang_hooks.types.register_builtin_type (vector_quad_type_node,
12582 "__vector_quad");
12583 }
12584
1acf0246
BS		 12585 /* Initialize the modes for builtin_function_type, mapping a machine mode to
12586 tree type node. */
12587 builtin_mode_to_type[QImode][0] = integer_type_node;
840ac85c 12588 builtin_mode_to_type[QImode][1] = unsigned_intSI_type_node;
1acf0246 12589 builtin_mode_to_type[HImode][0] = integer_type_node;
840ac85c 12590 builtin_mode_to_type[HImode][1] = unsigned_intSI_type_node;
1acf0246
BS		 12591 builtin_mode_to_type[SImode][0] = intSI_type_node;
12592 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
12593 builtin_mode_to_type[DImode][0] = intDI_type_node;
12594 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
12595 builtin_mode_to_type[TImode][0] = intTI_type_node;
12596 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
12597 builtin_mode_to_type[SFmode][0] = float_type_node;
12598 builtin_mode_to_type[DFmode][0] = double_type_node;
12599 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
12600 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
12601 builtin_mode_to_type[TFmode][0] = long_double_type_node;
12602 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
12603 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
12604 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
12605 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
12606 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
12607 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
12608 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
12609 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
12610 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
12611 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
12612 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
12613 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
12614 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
12615 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
f002c046
PB		 12616 builtin_mode_to_type[POImode][1] = vector_pair_type_node;
12617 builtin_mode_to_type[PXImode][1] = vector_quad_type_node;
1acf0246
BS		 12618
12619 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
12620 TYPE_NAME (bool_char_type_node) = tdecl;
12621
12622 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
12623 TYPE_NAME (bool_short_type_node) = tdecl;
12624
12625 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
12626 TYPE_NAME (bool_int_type_node) = tdecl;
12627
12628 tdecl = add_builtin_type ("__pixel", pixel_type_node);
12629 TYPE_NAME (pixel_type_node) = tdecl;
12630
12631 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
12632 bool_char_type_node, 16);
12633 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
12634 bool_short_type_node, 8);
12635 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
12636 bool_int_type_node, 4);
12637 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
12638 ? "__vector __bool long"
12639 : "__vector __bool long long",
12640 bool_long_long_type_node, 2);
12641 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
12642 pixel_type_node, 8);
12643
12644 /* Create Altivec and VSX builtins on machines with at least the
12645 general purpose extensions (970 and newer) to allow the use of
12646 the target attribute. */
12647 if (TARGET_EXTRA_BUILTINS)
12648 altivec_init_builtins ();
8ee2640b
PB		 12649 if (TARGET_MMA)
12650 mma_init_builtins ();
1acf0246
BS		 12651 if (TARGET_HTM)
12652 htm_init_builtins ();
12653
12654 if (TARGET_EXTRA_BUILTINS)
12655 rs6000_common_init_builtins ();
12656
12657 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
12658 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
12659 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
12660
12661 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
12662 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
12663 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
12664
12665 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
12666 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
12667 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
12668
12669 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
12670 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
12671 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
12672
12673 mode = (TARGET_64BIT) ? DImode : SImode;
12674 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
12675 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
12676 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
12677
12678 ftype = build_function_type_list (unsigned_intDI_type_node,
12679 NULL_TREE);
12680 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
12681
12682 if (TARGET_64BIT)
12683 ftype = build_function_type_list (unsigned_intDI_type_node,
12684 NULL_TREE);
12685 else
12686 ftype = build_function_type_list (unsigned_intSI_type_node,
12687 NULL_TREE);
12688 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
12689
12690 ftype = build_function_type_list (double_type_node, NULL_TREE);
12691 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
12692
12693 ftype = build_function_type_list (double_type_node, NULL_TREE);
12694 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
12695
12696 ftype = build_function_type_list (void_type_node,
12697 intSI_type_node,
12698 NULL_TREE);
12699 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
12700
12701 ftype = build_function_type_list (void_type_node,
12702 intSI_type_node,
12703 NULL_TREE);
12704 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
12705
12706 ftype = build_function_type_list (void_type_node,
12707 intDI_type_node,
12708 NULL_TREE);
12709 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
12710
12711 ftype = build_function_type_list (void_type_node,
12712 intDI_type_node,
12713 NULL_TREE);
12714 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
12715
12716 ftype = build_function_type_list (void_type_node,
12717 intSI_type_node, double_type_node,
12718 NULL_TREE);
12719 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
12720
12721 ftype = build_function_type_list (void_type_node, NULL_TREE);
12722 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
12723 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
12724 MISC_BUILTIN_SPEC_BARRIER);
12725
12726 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
12727 NULL_TREE);
12728 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
12729 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
12730
5e681acd
DE		 12731 if (TARGET_XCOFF)
12732 {
12733 /* AIX libm provides clog as __clog. */
12734 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
12735 set_user_assembler_name (tdecl, "__clog");
12736
12737 /* When long double is 64 bit, some long double builtins of libc
12738 functions (like __builtin_frexpl) must call the double version
12739 (frexp) not the long double version (frexpl) that expects a 128 bit
12740 argument. */
12741 if (! TARGET_LONG_DOUBLE_128)
12742 {
12743 if ((tdecl = builtin_decl_explicit (BUILT_IN_FMODL)) != NULL_TREE)
12744 set_user_assembler_name (tdecl, "fmod");
12745 if ((tdecl = builtin_decl_explicit (BUILT_IN_FREXPL)) != NULL_TREE)
12746 set_user_assembler_name (tdecl, "frexp");
12747 if ((tdecl = builtin_decl_explicit (BUILT_IN_LDEXPL)) != NULL_TREE)
12748 set_user_assembler_name (tdecl, "ldexp");
12749 if ((tdecl = builtin_decl_explicit (BUILT_IN_MODFL)) != NULL_TREE)
12750 set_user_assembler_name (tdecl, "modf");
12751 }
12752 }
1acf0246
BS		 12753
12754#ifdef SUBTARGET_INIT_BUILTINS
12755 SUBTARGET_INIT_BUILTINS;
12756#endif
12757}
12758
12759/* Returns the rs6000 builtin decl for CODE. */
12760
12761tree
12762rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
12763{
12764 HOST_WIDE_INT fnmask;
12765
12766 if (code >= RS6000_BUILTIN_COUNT)
12767 return error_mark_node;
12768
12769 fnmask = rs6000_builtin_info[code].mask;
12770 if ((fnmask & rs6000_builtin_mask) != fnmask)
12771 {
12772 rs6000_invalid_builtin ((enum rs6000_builtins)code);
12773 return error_mark_node;
12774 }
12775
12776 return rs6000_builtin_decls[code];
12777}
12778
12779static void
12780altivec_init_builtins (void)
12781{
12782 const struct builtin_description *d;
12783 size_t i;
12784 tree ftype;
12785 tree decl;
1acf0246
BS		 12786
12787 tree pvoid_type_node = build_pointer_type (void_type_node);
12788
12789 tree pcvoid_type_node
12790 = build_pointer_type (build_qualified_type (void_type_node,
12791 TYPE_QUAL_CONST));
12792
12793 tree int_ftype_opaque
12794 = build_function_type_list (integer_type_node,
12795 opaque_V4SI_type_node, NULL_TREE);
12796 tree opaque_ftype_opaque
12797 = build_function_type_list (integer_type_node, NULL_TREE);
12798 tree opaque_ftype_opaque_int
12799 = build_function_type_list (opaque_V4SI_type_node,
12800 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
12801 tree opaque_ftype_opaque_opaque_int
12802 = build_function_type_list (opaque_V4SI_type_node,
12803 opaque_V4SI_type_node, opaque_V4SI_type_node,
12804 integer_type_node, NULL_TREE);
12805 tree opaque_ftype_opaque_opaque_opaque
12806 = build_function_type_list (opaque_V4SI_type_node,
12807 opaque_V4SI_type_node, opaque_V4SI_type_node,
12808 opaque_V4SI_type_node, NULL_TREE);
12809 tree opaque_ftype_opaque_opaque
12810 = build_function_type_list (opaque_V4SI_type_node,
12811 opaque_V4SI_type_node, opaque_V4SI_type_node,
12812 NULL_TREE);
12813 tree int_ftype_int_opaque_opaque
12814 = build_function_type_list (integer_type_node,
12815 integer_type_node, opaque_V4SI_type_node,
12816 opaque_V4SI_type_node, NULL_TREE);
12817 tree int_ftype_int_v4si_v4si
12818 = build_function_type_list (integer_type_node,
12819 integer_type_node, V4SI_type_node,
12820 V4SI_type_node, NULL_TREE);
12821 tree int_ftype_int_v2di_v2di
12822 = build_function_type_list (integer_type_node,
12823 integer_type_node, V2DI_type_node,
12824 V2DI_type_node, NULL_TREE);
12825 tree void_ftype_v4si
12826 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
12827 tree v8hi_ftype_void
12828 = build_function_type_list (V8HI_type_node, NULL_TREE);
12829 tree void_ftype_void
12830 = build_function_type_list (void_type_node, NULL_TREE);
12831 tree void_ftype_int
12832 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
12833
12834 tree opaque_ftype_long_pcvoid
12835 = build_function_type_list (opaque_V4SI_type_node,
12836 long_integer_type_node, pcvoid_type_node,
12837 NULL_TREE);
12838 tree v16qi_ftype_long_pcvoid
12839 = build_function_type_list (V16QI_type_node,
12840 long_integer_type_node, pcvoid_type_node,
12841 NULL_TREE);
12842 tree v8hi_ftype_long_pcvoid
12843 = build_function_type_list (V8HI_type_node,
12844 long_integer_type_node, pcvoid_type_node,
12845 NULL_TREE);
12846 tree v4si_ftype_long_pcvoid
12847 = build_function_type_list (V4SI_type_node,
12848 long_integer_type_node, pcvoid_type_node,
12849 NULL_TREE);
12850 tree v4sf_ftype_long_pcvoid
12851 = build_function_type_list (V4SF_type_node,
12852 long_integer_type_node, pcvoid_type_node,
12853 NULL_TREE);
12854 tree v2df_ftype_long_pcvoid
12855 = build_function_type_list (V2DF_type_node,
12856 long_integer_type_node, pcvoid_type_node,
12857 NULL_TREE);
12858 tree v2di_ftype_long_pcvoid
12859 = build_function_type_list (V2DI_type_node,
12860 long_integer_type_node, pcvoid_type_node,
12861 NULL_TREE);
12862 tree v1ti_ftype_long_pcvoid
12863 = build_function_type_list (V1TI_type_node,
12864 long_integer_type_node, pcvoid_type_node,
12865 NULL_TREE);
12866
12867 tree void_ftype_opaque_long_pvoid
12868 = build_function_type_list (void_type_node,
12869 opaque_V4SI_type_node, long_integer_type_node,
12870 pvoid_type_node, NULL_TREE);
12871 tree void_ftype_v4si_long_pvoid
12872 = build_function_type_list (void_type_node,
12873 V4SI_type_node, long_integer_type_node,
12874 pvoid_type_node, NULL_TREE);
12875 tree void_ftype_v16qi_long_pvoid
12876 = build_function_type_list (void_type_node,
12877 V16QI_type_node, long_integer_type_node,
12878 pvoid_type_node, NULL_TREE);
12879
12880 tree void_ftype_v16qi_pvoid_long
12881 = build_function_type_list (void_type_node,
12882 V16QI_type_node, pvoid_type_node,
12883 long_integer_type_node, NULL_TREE);
12884
12885 tree void_ftype_v8hi_long_pvoid
12886 = build_function_type_list (void_type_node,
12887 V8HI_type_node, long_integer_type_node,
12888 pvoid_type_node, NULL_TREE);
12889 tree void_ftype_v4sf_long_pvoid
12890 = build_function_type_list (void_type_node,
12891 V4SF_type_node, long_integer_type_node,
12892 pvoid_type_node, NULL_TREE);
12893 tree void_ftype_v2df_long_pvoid
12894 = build_function_type_list (void_type_node,
12895 V2DF_type_node, long_integer_type_node,
12896 pvoid_type_node, NULL_TREE);
12897 tree void_ftype_v1ti_long_pvoid
12898 = build_function_type_list (void_type_node,
12899 V1TI_type_node, long_integer_type_node,
12900 pvoid_type_node, NULL_TREE);
12901 tree void_ftype_v2di_long_pvoid
12902 = build_function_type_list (void_type_node,
12903 V2DI_type_node, long_integer_type_node,
12904 pvoid_type_node, NULL_TREE);
12905 tree int_ftype_int_v8hi_v8hi
12906 = build_function_type_list (integer_type_node,
12907 integer_type_node, V8HI_type_node,
12908 V8HI_type_node, NULL_TREE);
12909 tree int_ftype_int_v16qi_v16qi
12910 = build_function_type_list (integer_type_node,
12911 integer_type_node, V16QI_type_node,
12912 V16QI_type_node, NULL_TREE);
12913 tree int_ftype_int_v4sf_v4sf
12914 = build_function_type_list (integer_type_node,
12915 integer_type_node, V4SF_type_node,
12916 V4SF_type_node, NULL_TREE);
12917 tree int_ftype_int_v2df_v2df
12918 = build_function_type_list (integer_type_node,
12919 integer_type_node, V2DF_type_node,
12920 V2DF_type_node, NULL_TREE);
12921 tree v2di_ftype_v2di
12922 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
12923 tree v4si_ftype_v4si
12924 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
12925 tree v8hi_ftype_v8hi
12926 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
12927 tree v16qi_ftype_v16qi
12928 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
12929 tree v4sf_ftype_v4sf
12930 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
12931 tree v2df_ftype_v2df
12932 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
12933 tree void_ftype_pcvoid_int_int
12934 = build_function_type_list (void_type_node,
12935 pcvoid_type_node, integer_type_node,
12936 integer_type_node, NULL_TREE);
12937
12938 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
12939 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
12940 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
12941 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
12942 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
12943 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
12944 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
12945 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
12946 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
12947 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
12948 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
12949 ALTIVEC_BUILTIN_LVXL_V2DF);
12950 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
12951 ALTIVEC_BUILTIN_LVXL_V2DI);
12952 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
12953 ALTIVEC_BUILTIN_LVXL_V4SF);
12954 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
12955 ALTIVEC_BUILTIN_LVXL_V4SI);
12956 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
12957 ALTIVEC_BUILTIN_LVXL_V8HI);
12958 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
12959 ALTIVEC_BUILTIN_LVXL_V16QI);
12960 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
12961 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
12962 ALTIVEC_BUILTIN_LVX_V1TI);
12963 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
12964 ALTIVEC_BUILTIN_LVX_V2DF);
12965 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
12966 ALTIVEC_BUILTIN_LVX_V2DI);
12967 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
12968 ALTIVEC_BUILTIN_LVX_V4SF);
12969 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
12970 ALTIVEC_BUILTIN_LVX_V4SI);
12971 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
12972 ALTIVEC_BUILTIN_LVX_V8HI);
12973 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
12974 ALTIVEC_BUILTIN_LVX_V16QI);
12975 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
12976 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
12977 ALTIVEC_BUILTIN_STVX_V2DF);
12978 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
12979 ALTIVEC_BUILTIN_STVX_V2DI);
12980 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
12981 ALTIVEC_BUILTIN_STVX_V4SF);
12982 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
12983 ALTIVEC_BUILTIN_STVX_V4SI);
12984 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
12985 ALTIVEC_BUILTIN_STVX_V8HI);
12986 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
12987 ALTIVEC_BUILTIN_STVX_V16QI);
12988 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
12989 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
12990 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
12991 ALTIVEC_BUILTIN_STVXL_V2DF);
12992 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
12993 ALTIVEC_BUILTIN_STVXL_V2DI);
12994 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
12995 ALTIVEC_BUILTIN_STVXL_V4SF);
12996 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
12997 ALTIVEC_BUILTIN_STVXL_V4SI);
12998 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
12999 ALTIVEC_BUILTIN_STVXL_V8HI);
13000 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
13001 ALTIVEC_BUILTIN_STVXL_V16QI);
13002 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
13003 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
13004 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
13005 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
13006 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
13007 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
13008 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
13009 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
13010 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
13011 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
13012 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
13013 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
13014 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
13015 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
13016 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
13017 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
13018
13019 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
13020 VSX_BUILTIN_LXVD2X_V2DF);
13021 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
13022 VSX_BUILTIN_LXVD2X_V2DI);
13023 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
13024 VSX_BUILTIN_LXVW4X_V4SF);
13025 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
13026 VSX_BUILTIN_LXVW4X_V4SI);
13027 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
13028 VSX_BUILTIN_LXVW4X_V8HI);
13029 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
13030 VSX_BUILTIN_LXVW4X_V16QI);
13031 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
13032 VSX_BUILTIN_STXVD2X_V2DF);
13033 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
13034 VSX_BUILTIN_STXVD2X_V2DI);
13035 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
13036 VSX_BUILTIN_STXVW4X_V4SF);
13037 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
13038 VSX_BUILTIN_STXVW4X_V4SI);
13039 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
13040 VSX_BUILTIN_STXVW4X_V8HI);
13041 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
13042 VSX_BUILTIN_STXVW4X_V16QI);
13043
13044 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
13045 VSX_BUILTIN_LD_ELEMREV_V2DF);
13046 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
13047 VSX_BUILTIN_LD_ELEMREV_V2DI);
13048 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
13049 VSX_BUILTIN_LD_ELEMREV_V4SF);
13050 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
13051 VSX_BUILTIN_LD_ELEMREV_V4SI);
13052 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
13053 VSX_BUILTIN_LD_ELEMREV_V8HI);
13054 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
13055 VSX_BUILTIN_LD_ELEMREV_V16QI);
13056 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
13057 VSX_BUILTIN_ST_ELEMREV_V2DF);
13058 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
13059 VSX_BUILTIN_ST_ELEMREV_V1TI);
13060 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
13061 VSX_BUILTIN_ST_ELEMREV_V2DI);
13062 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
13063 VSX_BUILTIN_ST_ELEMREV_V4SF);
13064 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
13065 VSX_BUILTIN_ST_ELEMREV_V4SI);
13066 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
13067 VSX_BUILTIN_ST_ELEMREV_V8HI);
13068 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
13069 VSX_BUILTIN_ST_ELEMREV_V16QI);
13070
13071 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
13072 VSX_BUILTIN_VEC_LD);
13073 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
13074 VSX_BUILTIN_VEC_ST);
13075 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
13076 VSX_BUILTIN_VEC_XL);
13077 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
13078 VSX_BUILTIN_VEC_XL_BE);
13079 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
13080 VSX_BUILTIN_VEC_XST);
13081 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
13082 VSX_BUILTIN_VEC_XST_BE);
13083
13084 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
13085 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
13086 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
13087
13088 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
13089 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
13090 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
13091 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
13092 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
13093 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
13094 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
13095 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
13096 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
13097 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
13098 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
13099 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
13100
13101 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
13102 ALTIVEC_BUILTIN_VEC_ADDE);
13103 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
13104 ALTIVEC_BUILTIN_VEC_ADDEC);
13105 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
13106 ALTIVEC_BUILTIN_VEC_CMPNE);
13107 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
13108 ALTIVEC_BUILTIN_VEC_MUL);
13109 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
13110 ALTIVEC_BUILTIN_VEC_SUBE);
13111 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
13112 ALTIVEC_BUILTIN_VEC_SUBEC);
13113
13114 /* Cell builtins. */
13115 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
13116 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
13117 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
13118 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
13119
13120 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
13121 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
13122 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
13123 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
13124
13125 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
13126 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
13127 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
13128 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
13129
13130 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
13131 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
13132 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
13133 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
13134
13135 if (TARGET_P9_VECTOR)
13136 {
13137 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
13138 P9V_BUILTIN_STXVL);
13139 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
13140 P9V_BUILTIN_XST_LEN_R);
13141 }
13142
13143 /* Add the DST variants. */
13144 d = bdesc_dst;
13145 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
13146 {
1acf0246
BS		 13147 /* It is expected that these dst built-in functions may have
13148 d->icode equal to CODE_FOR_nothing. */
1acf0246
BS		 13149 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
13150 }
13151
13152 /* Initialize the predicates. */
13153 d = bdesc_altivec_preds;
13154 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
13155 {
13156 machine_mode mode1;
13157 tree type;
1acf0246
BS		 13158
13159 if (rs6000_overloaded_builtin_p (d->code))
13160 mode1 = VOIDmode;
13161 else
13162 {
13163 /* Cannot define builtin if the instruction is disabled. */
13164 gcc_assert (d->icode != CODE_FOR_nothing);
13165 mode1 = insn_data[d->icode].operand[1].mode;
13166 }
13167
13168 switch (mode1)
13169 {
13170 case E_VOIDmode:
13171 type = int_ftype_int_opaque_opaque;
13172 break;
13173 case E_V2DImode:
13174 type = int_ftype_int_v2di_v2di;
13175 break;
13176 case E_V4SImode:
13177 type = int_ftype_int_v4si_v4si;
13178 break;
13179 case E_V8HImode:
13180 type = int_ftype_int_v8hi_v8hi;
13181 break;
13182 case E_V16QImode:
13183 type = int_ftype_int_v16qi_v16qi;
13184 break;
13185 case E_V4SFmode:
13186 type = int_ftype_int_v4sf_v4sf;
13187 break;
13188 case E_V2DFmode:
13189 type = int_ftype_int_v2df_v2df;
13190 break;
13191 default:
13192 gcc_unreachable ();
13193 }
13194
13195 def_builtin (d->name, type, d->code);
13196 }
13197
13198 /* Initialize the abs* operators. */
13199 d = bdesc_abs;
13200 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
13201 {
13202 machine_mode mode0;
13203 tree type;
1acf0246
BS		 13204
13205 /* Cannot define builtin if the instruction is disabled. */
13206 gcc_assert (d->icode != CODE_FOR_nothing);
13207 mode0 = insn_data[d->icode].operand[0].mode;
13208
13209 switch (mode0)
13210 {
13211 case E_V2DImode:
13212 type = v2di_ftype_v2di;
13213 break;
13214 case E_V4SImode:
13215 type = v4si_ftype_v4si;
13216 break;
13217 case E_V8HImode:
13218 type = v8hi_ftype_v8hi;
13219 break;
13220 case E_V16QImode:
13221 type = v16qi_ftype_v16qi;
13222 break;
13223 case E_V4SFmode:
13224 type = v4sf_ftype_v4sf;
13225 break;
13226 case E_V2DFmode:
13227 type = v2df_ftype_v2df;
13228 break;
13229 default:
13230 gcc_unreachable ();
13231 }
13232
13233 def_builtin (d->name, type, d->code);
13234 }
13235
13236 /* Initialize target builtin that implements
13237 targetm.vectorize.builtin_mask_for_load. */
13238
13239 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
13240 v16qi_ftype_long_pcvoid,
13241 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
13242 BUILT_IN_MD, NULL, NULL_TREE);
13243 TREE_READONLY (decl) = 1;
13244 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
13245 altivec_builtin_mask_for_load = decl;
13246
13247 /* Access to the vec_init patterns. */
13248 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
13249 integer_type_node, integer_type_node,
13250 integer_type_node, NULL_TREE);
13251 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
13252
13253 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
13254 short_integer_type_node,
13255 short_integer_type_node,
13256 short_integer_type_node,
13257 short_integer_type_node,
13258 short_integer_type_node,
13259 short_integer_type_node,
13260 short_integer_type_node, NULL_TREE);
13261 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
13262
13263 ftype = build_function_type_list (V16QI_type_node, char_type_node,
13264 char_type_node, char_type_node,
13265 char_type_node, char_type_node,
13266 char_type_node, char_type_node,
13267 char_type_node, char_type_node,
13268 char_type_node, char_type_node,
13269 char_type_node, char_type_node,
13270 char_type_node, char_type_node,
13271 char_type_node, NULL_TREE);
13272 def_builtin ("__builtin_vec_init_v16qi", ftype,
13273 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
13274
13275 ftype = build_function_type_list (V4SF_type_node, float_type_node,
13276 float_type_node, float_type_node,
13277 float_type_node, NULL_TREE);
13278 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
13279
13280 /* VSX builtins. */
13281 ftype = build_function_type_list (V2DF_type_node, double_type_node,
13282 double_type_node, NULL_TREE);
13283 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
13284
13285 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
13286 intDI_type_node, NULL_TREE);
13287 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
13288
13289 /* Access to the vec_set patterns. */
13290 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
13291 intSI_type_node,
13292 integer_type_node, NULL_TREE);
13293 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
13294
13295 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
13296 intHI_type_node,
13297 integer_type_node, NULL_TREE);
13298 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
13299
13300 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
13301 intQI_type_node,
13302 integer_type_node, NULL_TREE);
13303 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
13304
13305 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
13306 float_type_node,
13307 integer_type_node, NULL_TREE);
13308 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
13309
13310 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
13311 double_type_node,
13312 integer_type_node, NULL_TREE);
13313 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
13314
13315 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
13316 intDI_type_node,
13317 integer_type_node, NULL_TREE);
13318 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
13319
13320 /* Access to the vec_extract patterns. */
13321 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
13322 integer_type_node, NULL_TREE);
13323 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
13324
13325 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
13326 integer_type_node, NULL_TREE);
13327 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
13328
13329 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
13330 integer_type_node, NULL_TREE);
13331 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
13332
13333 ftype = build_function_type_list (float_type_node, V4SF_type_node,
13334 integer_type_node, NULL_TREE);
13335 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
13336
13337 ftype = build_function_type_list (double_type_node, V2DF_type_node,
13338 integer_type_node, NULL_TREE);
13339 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
13340
13341 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
13342 integer_type_node, NULL_TREE);
13343 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
13344
13345
13346 if (V1TI_type_node)
13347 {
13348 tree v1ti_ftype_long_pcvoid
13349 = build_function_type_list (V1TI_type_node,
13350 long_integer_type_node, pcvoid_type_node,
13351 NULL_TREE);
13352 tree void_ftype_v1ti_long_pvoid
13353 = build_function_type_list (void_type_node,
13354 V1TI_type_node, long_integer_type_node,
13355 pvoid_type_node, NULL_TREE);
13356 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
13357 VSX_BUILTIN_LD_ELEMREV_V1TI);
13358 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
13359 VSX_BUILTIN_LXVD2X_V1TI);
13360 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
13361 VSX_BUILTIN_STXVD2X_V1TI);
13362 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
13363 NULL_TREE, NULL_TREE);
13364 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
13365 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
13366 intTI_type_node,
13367 integer_type_node, NULL_TREE);
13368 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
13369 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
13370 integer_type_node, NULL_TREE);
13371 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
13372 }
13373
13374}
13375
8ee2640b
PB		 13376static void
13377mma_init_builtins (void)
13378{
13379 const struct builtin_description *d = bdesc_mma;
13380
13381 for (unsigned i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++)
13382 {
13383 tree op[MAX_MMA_OPERANDS], type;
13384 HOST_WIDE_INT mask = d->mask;
13385 unsigned icode = (unsigned) d->icode;
13386 unsigned attr = rs6000_builtin_info[d->code].attr;
13387 int attr_args = (attr & RS6000_BTC_OPND_MASK);
13388 bool gimple_func = (attr & RS6000_BTC_GIMPLE);
13389 unsigned nopnds = 0;
13390
13391 if ((mask & rs6000_builtin_mask) != mask)
13392 {
13393 if (TARGET_DEBUG_BUILTIN)
13394 fprintf (stderr, "mma_builtin, skip binary %s\n", d->name);
13395 continue;
13396 }
13397
13398 if (d->name == 0)
13399 {
13400 if (TARGET_DEBUG_BUILTIN)
13401 fprintf (stderr, "mma_builtin, bdesc_mma[%ld] no name\n",
13402 (long unsigned) i);
13403 continue;
13404 }
13405
13406 if (gimple_func)
13407 {
13408 gcc_assert (icode == CODE_FOR_nothing);
13409 op[nopnds++] = void_type_node;
13410 /* Some MMA built-ins that are expanded into gimple are converted
13411 into internal MMA built-ins that are expanded into rtl.
13412 The internal built-in follows immediately after this built-in. */
13413 icode = d[1].icode;
13414 }
13415 else
13416 {
13417 if ((attr & RS6000_BTC_QUAD) == 0)
13418 attr_args--;
13419
13420 /* Ensure we have the correct number and type of operands. */
13421 gcc_assert (attr_args == insn_data[icode].n_operands - 1);
13422 }
13423
13424 if (icode == CODE_FOR_nothing)
13425 {
13426 /* This is a disassemble MMA built-in function. */
13427 gcc_assert (attr_args == RS6000_BTC_BINARY
13428 && (d->code == MMA_BUILTIN_DISASSEMBLE_ACC
13429 || d->code == MMA_BUILTIN_DISASSEMBLE_PAIR));
13430 op[nopnds++] = build_pointer_type (void_type_node);
13431 if (attr & RS6000_BTC_QUAD)
13432 op[nopnds++] = build_pointer_type (vector_quad_type_node);
13433 else
13434 op[nopnds++] = build_pointer_type (vector_pair_type_node);
13435 }
13436 else
13437 {
13438 /* This is a normal MMA built-in function. */
13439 unsigned j = (attr & RS6000_BTC_QUAD) ? 1 : 0;
13440 for (; j < insn_data[icode].n_operands; j++)
13441 {
13442 machine_mode mode = insn_data[icode].operand[j].mode;
13443 if (gimple_func && mode == PXImode)
13444 op[nopnds++] = build_pointer_type (vector_quad_type_node);
13445 else if (gimple_func && mode == POImode
13446 && d->code == MMA_BUILTIN_ASSEMBLE_PAIR)
13447 op[nopnds++] = build_pointer_type (vector_pair_type_node);
13448 else
13449 /* MMA uses unsigned types. */
13450 op[nopnds++] = builtin_mode_to_type[mode][1];
13451 }
13452 }
13453
13454 switch (nopnds)
13455 {
13456 case 1:
13457 type = build_function_type_list (op[0], NULL_TREE);
13458 break;
13459 case 2:
13460 type = build_function_type_list (op[0], op[1], NULL_TREE);
13461 break;
13462 case 3:
13463 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
13464 break;
13465 case 4:
13466 type = build_function_type_list (op[0], op[1], op[2], op[3],
13467 NULL_TREE);
13468 break;
13469 case 5:
13470 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4],
13471 NULL_TREE);
13472 break;
13473 case 6:
13474 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4],
13475 op[5], NULL_TREE);
13476 break;
13477 case 7:
13478 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4],
13479 op[5], op[6], NULL_TREE);
13480 break;
13481 default:
13482 gcc_unreachable ();
13483 }
13484
13485 def_builtin (d->name, type, d->code);
13486 }
13487}
13488
1acf0246
BS		 13489static void
13490htm_init_builtins (void)
13491{
13492 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
13493 const struct builtin_description *d;
13494 size_t i;
13495
13496 d = bdesc_htm;
13497 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
13498 {
13499 tree op[MAX_HTM_OPERANDS], type;
13500 HOST_WIDE_INT mask = d->mask;
13501 unsigned attr = rs6000_builtin_info[d->code].attr;
13502 bool void_func = (attr & RS6000_BTC_VOID);
8ee2640b 13503 int attr_args = (attr & RS6000_BTC_OPND_MASK);
1acf0246
BS		 13504 int nopnds = 0;
13505 tree gpr_type_node;
13506 tree rettype;
13507 tree argtype;
13508
13509 /* It is expected that these htm built-in functions may have
13510 d->icode equal to CODE_FOR_nothing. */
13511
13512 if (TARGET_32BIT && TARGET_POWERPC64)
13513 gpr_type_node = long_long_unsigned_type_node;
13514 else
13515 gpr_type_node = long_unsigned_type_node;
13516
13517 if (attr & RS6000_BTC_SPR)
13518 {
13519 rettype = gpr_type_node;
13520 argtype = gpr_type_node;
13521 }
13522 else if (d->code == HTM_BUILTIN_TABORTDC
13523 || d->code == HTM_BUILTIN_TABORTDCI)
13524 {
13525 rettype = unsigned_type_node;
13526 argtype = gpr_type_node;
13527 }
13528 else
13529 {
13530 rettype = unsigned_type_node;
13531 argtype = unsigned_type_node;
13532 }
13533
13534 if ((mask & builtin_mask) != mask)
13535 {
13536 if (TARGET_DEBUG_BUILTIN)
13537 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
13538 continue;
13539 }
13540
13541 if (d->name == 0)
13542 {
13543 if (TARGET_DEBUG_BUILTIN)
13544 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
13545 (long unsigned) i);
13546 continue;
13547 }
13548
13549 op[nopnds++] = (void_func) ? void_type_node : rettype;
13550
13551 if (attr_args == RS6000_BTC_UNARY)
13552 op[nopnds++] = argtype;
13553 else if (attr_args == RS6000_BTC_BINARY)
13554 {
13555 op[nopnds++] = argtype;
13556 op[nopnds++] = argtype;
13557 }
13558 else if (attr_args == RS6000_BTC_TERNARY)
13559 {
13560 op[nopnds++] = argtype;
13561 op[nopnds++] = argtype;
13562 op[nopnds++] = argtype;
13563 }
13564
13565 switch (nopnds)
13566 {
13567 case 1:
13568 type = build_function_type_list (op[0], NULL_TREE);
13569 break;
13570 case 2:
13571 type = build_function_type_list (op[0], op[1], NULL_TREE);
13572 break;
13573 case 3:
13574 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
13575 break;
13576 case 4:
13577 type = build_function_type_list (op[0], op[1], op[2], op[3],
13578 NULL_TREE);
13579 break;
13580 default:
13581 gcc_unreachable ();
13582 }
13583
13584 def_builtin (d->name, type, d->code);
13585 }
13586}
13587
840ac85c
KN		 13588/* Map types for builtin functions with an explicit return type and
13589 exactly 4 arguments. Functions with fewer than 3 arguments use
13590 builtin_function_type. The number of quaternary built-in
13591 functions is very small. Handle each case specially. */
13592static tree
13593builtin_quaternary_function_type (machine_mode mode_ret,
13594 machine_mode mode_arg0,
13595 machine_mode mode_arg1,
13596 machine_mode mode_arg2,
13597 machine_mode mode_arg3,
13598 enum rs6000_builtins builtin)
13599{
13600 tree function_type = NULL;
13601
13602 static tree v2udi_type = builtin_mode_to_type[V2DImode][1];
13603 static tree uchar_type = builtin_mode_to_type[QImode][1];
13604
13605 static tree xxeval_type =
13606 build_function_type_list (v2udi_type, v2udi_type, v2udi_type,
13607 v2udi_type, uchar_type, NULL_TREE);
13608
13609 switch (builtin) {
13610
5d9d0c94 13611 case P10_BUILTIN_XXEVAL:
840ac85c
KN		 13612 gcc_assert ((mode_ret == V2DImode)
13613 && (mode_arg0 == V2DImode)
13614 && (mode_arg1 == V2DImode)
13615 && (mode_arg2 == V2DImode)
13616 && (mode_arg3 == QImode));
13617 function_type = xxeval_type;
13618 break;
13619
13620 default:
13621 /* A case for each quaternary built-in must be provided above. */
13622 gcc_unreachable ();
13623 }
13624
13625 return function_type;
13626}
13627
1acf0246
BS		 13628/* Map types for builtin functions with an explicit return type and up to 3
13629 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
13630 of the argument. */
13631static tree
13632builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
13633 machine_mode mode_arg1, machine_mode mode_arg2,
13634 enum rs6000_builtins builtin, const char *name)
13635{
13636 struct builtin_hash_struct h;
13637 struct builtin_hash_struct *h2;
13638 int num_args = 3;
13639 int i;
13640 tree ret_type = NULL_TREE;
13641 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
13642
13643 /* Create builtin_hash_table. */
13644 if (builtin_hash_table == NULL)
13645 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
13646
13647 h.type = NULL_TREE;
13648 h.mode[0] = mode_ret;
13649 h.mode[1] = mode_arg0;
13650 h.mode[2] = mode_arg1;
13651 h.mode[3] = mode_arg2;
13652 h.uns_p[0] = 0;
13653 h.uns_p[1] = 0;
13654 h.uns_p[2] = 0;
13655 h.uns_p[3] = 0;
13656
13657 /* If the builtin is a type that produces unsigned results or takes unsigned
13658 arguments, and it is returned as a decl for the vectorizer (such as
13659 widening multiplies, permute), make sure the arguments and return value
13660 are type correct. */
13661 switch (builtin)
13662 {
13663 /* unsigned 1 argument functions. */
13664 case CRYPTO_BUILTIN_VSBOX:
13665 case CRYPTO_BUILTIN_VSBOX_BE:
13666 case P8V_BUILTIN_VGBBD:
13667 case MISC_BUILTIN_CDTBCD:
13668 case MISC_BUILTIN_CBCDTD:
8ee2640b
PB		 13669 case VSX_BUILTIN_XVCVSPBF16:
13670 case VSX_BUILTIN_XVCVBF16SP:
1acf0246
BS		 13671 h.uns_p[0] = 1;
13672 h.uns_p[1] = 1;
13673 break;
13674
13675 /* unsigned 2 argument functions. */
13676 case ALTIVEC_BUILTIN_VMULEUB:
13677 case ALTIVEC_BUILTIN_VMULEUH:
13678 case P8V_BUILTIN_VMULEUW:
13679 case ALTIVEC_BUILTIN_VMULOUB:
13680 case ALTIVEC_BUILTIN_VMULOUH:
13681 case P8V_BUILTIN_VMULOUW:
13682 case CRYPTO_BUILTIN_VCIPHER:
13683 case CRYPTO_BUILTIN_VCIPHER_BE:
13684 case CRYPTO_BUILTIN_VCIPHERLAST:
13685 case CRYPTO_BUILTIN_VCIPHERLAST_BE:
13686 case CRYPTO_BUILTIN_VNCIPHER:
13687 case CRYPTO_BUILTIN_VNCIPHER_BE:
13688 case CRYPTO_BUILTIN_VNCIPHERLAST:
13689 case CRYPTO_BUILTIN_VNCIPHERLAST_BE:
13690 case CRYPTO_BUILTIN_VPMSUMB:
13691 case CRYPTO_BUILTIN_VPMSUMH:
13692 case CRYPTO_BUILTIN_VPMSUMW:
13693 case CRYPTO_BUILTIN_VPMSUMD:
13694 case CRYPTO_BUILTIN_VPMSUM:
13695 case MISC_BUILTIN_ADDG6S:
13696 case MISC_BUILTIN_DIVWEU:
13697 case MISC_BUILTIN_DIVDEU:
13698 case VSX_BUILTIN_UDIV_V2DI:
13699 case ALTIVEC_BUILTIN_VMAXUB:
13700 case ALTIVEC_BUILTIN_VMINUB:
13701 case ALTIVEC_BUILTIN_VMAXUH:
13702 case ALTIVEC_BUILTIN_VMINUH:
13703 case ALTIVEC_BUILTIN_VMAXUW:
13704 case ALTIVEC_BUILTIN_VMINUW:
13705 case P8V_BUILTIN_VMAXUD:
13706 case P8V_BUILTIN_VMINUD:
4559be23
PB		 13707 case ALTIVEC_BUILTIN_VAND_V16QI_UNS:
13708 case ALTIVEC_BUILTIN_VAND_V8HI_UNS:
13709 case ALTIVEC_BUILTIN_VAND_V4SI_UNS:
13710 case ALTIVEC_BUILTIN_VAND_V2DI_UNS:
13711 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS:
13712 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS:
13713 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS:
13714 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS:
13715 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS:
13716 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS:
13717 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS:
13718 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS:
13719 case ALTIVEC_BUILTIN_VOR_V16QI_UNS:
13720 case ALTIVEC_BUILTIN_VOR_V8HI_UNS:
13721 case ALTIVEC_BUILTIN_VOR_V4SI_UNS:
13722 case ALTIVEC_BUILTIN_VOR_V2DI_UNS:
13723 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS:
13724 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS:
13725 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS:
13726 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS:
13727 case P8V_BUILTIN_EQV_V16QI_UNS:
13728 case P8V_BUILTIN_EQV_V8HI_UNS:
13729 case P8V_BUILTIN_EQV_V4SI_UNS:
13730 case P8V_BUILTIN_EQV_V2DI_UNS:
13731 case P8V_BUILTIN_EQV_V1TI_UNS:
13732 case P8V_BUILTIN_NAND_V16QI_UNS:
13733 case P8V_BUILTIN_NAND_V8HI_UNS:
13734 case P8V_BUILTIN_NAND_V4SI_UNS:
13735 case P8V_BUILTIN_NAND_V2DI_UNS:
13736 case P8V_BUILTIN_NAND_V1TI_UNS:
13737 case P8V_BUILTIN_ORC_V16QI_UNS:
13738 case P8V_BUILTIN_ORC_V8HI_UNS:
13739 case P8V_BUILTIN_ORC_V4SI_UNS:
13740 case P8V_BUILTIN_ORC_V2DI_UNS:
13741 case P8V_BUILTIN_ORC_V1TI_UNS:
5d9d0c94
SB		 13742 case P10_BUILTIN_VCFUGED:
13743 case P10_BUILTIN_VCLZDM:
13744 case P10_BUILTIN_VCTZDM:
13745 case P10_BUILTIN_VGNB:
13746 case P10_BUILTIN_VPDEPD:
13747 case P10_BUILTIN_VPEXTD:
13748 case P10_BUILTIN_XXGENPCVM_V16QI:
13749 case P10_BUILTIN_XXGENPCVM_V8HI:
13750 case P10_BUILTIN_XXGENPCVM_V4SI:
13751 case P10_BUILTIN_XXGENPCVM_V2DI:
1acf0246
BS		 13752 h.uns_p[0] = 1;
13753 h.uns_p[1] = 1;
13754 h.uns_p[2] = 1;
13755 break;
13756
13757 /* unsigned 3 argument functions. */
13758 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
13759 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
13760 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
13761 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
13762 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
13763 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
13764 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
13765 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
13766 case VSX_BUILTIN_VPERM_16QI_UNS:
13767 case VSX_BUILTIN_VPERM_8HI_UNS:
13768 case VSX_BUILTIN_VPERM_4SI_UNS:
13769 case VSX_BUILTIN_VPERM_2DI_UNS:
13770 case VSX_BUILTIN_XXSEL_16QI_UNS:
13771 case VSX_BUILTIN_XXSEL_8HI_UNS:
13772 case VSX_BUILTIN_XXSEL_4SI_UNS:
13773 case VSX_BUILTIN_XXSEL_2DI_UNS:
13774 case CRYPTO_BUILTIN_VPERMXOR:
13775 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
13776 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
13777 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
13778 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
13779 case CRYPTO_BUILTIN_VSHASIGMAW:
13780 case CRYPTO_BUILTIN_VSHASIGMAD:
13781 case CRYPTO_BUILTIN_VSHASIGMA:
5d9d0c94
SB		 13782 case P10_BUILTIN_VEXTRACTBL:
13783 case P10_BUILTIN_VEXTRACTHL:
13784 case P10_BUILTIN_VEXTRACTWL:
13785 case P10_BUILTIN_VEXTRACTDL:
13786 case P10_BUILTIN_VEXTRACTBR:
13787 case P10_BUILTIN_VEXTRACTHR:
13788 case P10_BUILTIN_VEXTRACTWR:
13789 case P10_BUILTIN_VEXTRACTDR:
1acf0246
BS		 13790 h.uns_p[0] = 1;
13791 h.uns_p[1] = 1;
13792 h.uns_p[2] = 1;
13793 h.uns_p[3] = 1;
13794 break;
13795
13796 /* signed permute functions with unsigned char mask. */
13797 case ALTIVEC_BUILTIN_VPERM_16QI:
13798 case ALTIVEC_BUILTIN_VPERM_8HI:
13799 case ALTIVEC_BUILTIN_VPERM_4SI:
13800 case ALTIVEC_BUILTIN_VPERM_4SF:
13801 case ALTIVEC_BUILTIN_VPERM_2DI:
13802 case ALTIVEC_BUILTIN_VPERM_2DF:
13803 case VSX_BUILTIN_VPERM_16QI:
13804 case VSX_BUILTIN_VPERM_8HI:
13805 case VSX_BUILTIN_VPERM_4SI:
13806 case VSX_BUILTIN_VPERM_4SF:
13807 case VSX_BUILTIN_VPERM_2DI:
13808 case VSX_BUILTIN_VPERM_2DF:
13809 h.uns_p[3] = 1;
13810 break;
13811
13812 /* unsigned args, signed return. */
13813 case VSX_BUILTIN_XVCVUXDSP:
13814 case VSX_BUILTIN_XVCVUXDDP_UNS:
13815 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
13816 h.uns_p[1] = 1;
13817 break;
13818
13819 /* signed args, unsigned return. */
13820 case VSX_BUILTIN_XVCVDPUXDS_UNS:
13821 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
13822 case MISC_BUILTIN_UNPACK_TD:
13823 case MISC_BUILTIN_UNPACK_V1TI:
13824 h.uns_p[0] = 1;
13825 break;
13826
13827 /* unsigned arguments, bool return (compares). */
13828 case ALTIVEC_BUILTIN_VCMPEQUB:
13829 case ALTIVEC_BUILTIN_VCMPEQUH:
13830 case ALTIVEC_BUILTIN_VCMPEQUW:
13831 case P8V_BUILTIN_VCMPEQUD:
13832 case VSX_BUILTIN_CMPGE_U16QI:
13833 case VSX_BUILTIN_CMPGE_U8HI:
13834 case VSX_BUILTIN_CMPGE_U4SI:
13835 case VSX_BUILTIN_CMPGE_U2DI:
13836 case ALTIVEC_BUILTIN_VCMPGTUB:
13837 case ALTIVEC_BUILTIN_VCMPGTUH:
13838 case ALTIVEC_BUILTIN_VCMPGTUW:
13839 case P8V_BUILTIN_VCMPGTUD:
13840 h.uns_p[1] = 1;
13841 h.uns_p[2] = 1;
13842 break;
13843
13844 /* unsigned arguments for 128-bit pack instructions. */
13845 case MISC_BUILTIN_PACK_TD:
13846 case MISC_BUILTIN_PACK_V1TI:
13847 h.uns_p[1] = 1;
13848 h.uns_p[2] = 1;
13849 break;
13850
13851 /* unsigned second arguments (vector shift right). */
13852 case ALTIVEC_BUILTIN_VSRB:
13853 case ALTIVEC_BUILTIN_VSRH:
13854 case ALTIVEC_BUILTIN_VSRW:
13855 case P8V_BUILTIN_VSRD:
13856 h.uns_p[2] = 1;
13857 break;
13858
13859 default:
13860 break;
13861 }
13862
13863 /* Figure out how many args are present. */
13864 while (num_args > 0 && h.mode[num_args] == VOIDmode)
13865 num_args--;
13866
13867 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
13868 if (!ret_type && h.uns_p[0])
13869 ret_type = builtin_mode_to_type[h.mode[0]][0];
13870
a92cc0da
PB		 13871 /* If the required decimal float type has been disabled,
13872 then return NULL_TREE. */
13873 if (!ret_type && DECIMAL_FLOAT_MODE_P (h.mode[0]))
13874 return NULL_TREE;
13875
1acf0246
BS		 13876 if (!ret_type)
13877 fatal_error (input_location,
13878 "internal error: builtin function %qs had an unexpected "
13879 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
13880
13881 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
13882 arg_type[i] = NULL_TREE;
13883
13884 for (i = 0; i < num_args; i++)
13885 {
13886 int m = (int) h.mode[i+1];
13887 int uns_p = h.uns_p[i+1];
13888
13889 arg_type[i] = builtin_mode_to_type[m][uns_p];
13890 if (!arg_type[i] && uns_p)
13891 arg_type[i] = builtin_mode_to_type[m][0];
13892
a92cc0da
PB		 13893 /* If the required decimal float type has been disabled,
13894 then return NULL_TREE. */
13895 if (!arg_type[i] && DECIMAL_FLOAT_MODE_P (m))
13896 return NULL_TREE;
13897
1acf0246
BS		 13898 if (!arg_type[i])
13899 fatal_error (input_location,
13900 "internal error: builtin function %qs, argument %d "
13901 "had unexpected argument type %qs", name, i,
13902 GET_MODE_NAME (m));
13903 }
13904
13905 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
13906 if (*found == NULL)
13907 {
13908 h2 = ggc_alloc<builtin_hash_struct> ();
13909 *h2 = h;
13910 *found = h2;
13911
13912 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
13913 arg_type[2], NULL_TREE);
13914 }
13915
13916 return (*found)->type;
13917}
13918
13919static void
13920rs6000_common_init_builtins (void)
13921{
13922 const struct builtin_description *d;
13923 size_t i;
13924
13925 tree opaque_ftype_opaque = NULL_TREE;
13926 tree opaque_ftype_opaque_opaque = NULL_TREE;
13927 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
c21d2b66 13928 tree opaque_ftype_opaque_opaque_opaque_opaque = NULL_TREE;
1acf0246
BS		 13929 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
13930
13931 /* Create Altivec and VSX builtins on machines with at least the
13932 general purpose extensions (970 and newer) to allow the use of
13933 the target attribute. */
13934
13935 if (TARGET_EXTRA_BUILTINS)
13936 builtin_mask |= RS6000_BTM_COMMON;
13937
840ac85c
KN		 13938 /* Add the quaternary operators. */
13939 d = bdesc_4arg;
13940 for (i = 0; i < ARRAY_SIZE (bdesc_4arg); i++, d++)
13941 {
13942 tree type;
13943 HOST_WIDE_INT mask = d->mask;
13944
13945 if ((mask & builtin_mask) != mask)
13946 {
13947 if (TARGET_DEBUG_BUILTIN)
13948 fprintf (stderr, "rs6000_builtin, skip quaternary %s\n", d->name);
13949 continue;
13950 }
13951
13952 if (rs6000_overloaded_builtin_p (d->code))
13953 {
c21d2b66 13954 type = opaque_ftype_opaque_opaque_opaque_opaque;
840ac85c 13955 if (!type)
c21d2b66 13956 type = opaque_ftype_opaque_opaque_opaque_opaque
840ac85c
KN		 13957 = build_function_type_list (opaque_V4SI_type_node,
13958 opaque_V4SI_type_node,
13959 opaque_V4SI_type_node,
13960 opaque_V4SI_type_node,
13961 opaque_V4SI_type_node,
13962 NULL_TREE);
13963 }
13964 else
13965 {
13966 enum insn_code icode = d->icode;
13967 if (d->name == 0)
13968 {
13969 if (TARGET_DEBUG_BUILTIN)
13970 fprintf (stderr, "rs6000_builtin, bdesc_4arg[%ld] no name\n",
13971 (long) i);
13972 continue;
13973 }
13974
13975 if (icode == CODE_FOR_nothing)
13976 {
13977 if (TARGET_DEBUG_BUILTIN)
13978 fprintf (stderr,
13979 "rs6000_builtin, skip quaternary %s (no code)\n",
13980 d->name);
13981 continue;
13982 }
13983
13984 type =
13985 builtin_quaternary_function_type (insn_data[icode].operand[0].mode,
13986 insn_data[icode].operand[1].mode,
13987 insn_data[icode].operand[2].mode,
13988 insn_data[icode].operand[3].mode,
13989 insn_data[icode].operand[4].mode,
13990 d->code);
13991 }
13992 def_builtin (d->name, type, d->code);
13993 }
13994
1acf0246
BS		 13995 /* Add the ternary operators. */
13996 d = bdesc_3arg;
13997 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
13998 {
13999 tree type;
14000 HOST_WIDE_INT mask = d->mask;
14001
14002 if ((mask & builtin_mask) != mask)
14003 {
14004 if (TARGET_DEBUG_BUILTIN)
14005 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
14006 continue;
14007 }
14008
14009 if (rs6000_overloaded_builtin_p (d->code))
14010 {
14011 if (! (type = opaque_ftype_opaque_opaque_opaque))
14012 type = opaque_ftype_opaque_opaque_opaque
14013 = build_function_type_list (opaque_V4SI_type_node,
14014 opaque_V4SI_type_node,
14015 opaque_V4SI_type_node,
14016 opaque_V4SI_type_node,
14017 NULL_TREE);
14018 }
14019 else
14020 {
14021 enum insn_code icode = d->icode;
14022 if (d->name == 0)
14023 {
14024 if (TARGET_DEBUG_BUILTIN)
14025 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
14026 (long unsigned)i);
14027
14028 continue;
14029 }
14030
14031 if (icode == CODE_FOR_nothing)
14032 {
14033 if (TARGET_DEBUG_BUILTIN)
14034 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
14035 d->name);
14036
14037 continue;
14038 }
14039
14040 type = builtin_function_type (insn_data[icode].operand[0].mode,
14041 insn_data[icode].operand[1].mode,
14042 insn_data[icode].operand[2].mode,
14043 insn_data[icode].operand[3].mode,
14044 d->code, d->name);
14045 }
14046
14047 def_builtin (d->name, type, d->code);
14048 }
14049
14050 /* Add the binary operators. */
14051 d = bdesc_2arg;
14052 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
14053 {
14054 machine_mode mode0, mode1, mode2;
14055 tree type;
14056 HOST_WIDE_INT mask = d->mask;
14057
14058 if ((mask & builtin_mask) != mask)
14059 {
14060 if (TARGET_DEBUG_BUILTIN)
14061 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
14062 continue;
14063 }
14064
14065 if (rs6000_overloaded_builtin_p (d->code))
14066 {
25ffd3d3
PB		 14067 const struct altivec_builtin_types *desc;
14068
14069 /* Verify the builtin we are overloading has already been defined. */
14070 type = NULL_TREE;
14071 for (desc = altivec_overloaded_builtins;
14072 desc->code != RS6000_BUILTIN_NONE; desc++)
14073 if (desc->code == d->code
14074 && rs6000_builtin_decls[(int)desc->overloaded_code])
14075 {
14076 if (! (type = opaque_ftype_opaque_opaque))
14077 type = opaque_ftype_opaque_opaque
14078 = build_function_type_list (opaque_V4SI_type_node,
14079 opaque_V4SI_type_node,
14080 opaque_V4SI_type_node,
14081 NULL_TREE);
14082 break;
14083 }
1acf0246
BS		 14084 }
14085 else
14086 {
14087 enum insn_code icode = d->icode;
14088 if (d->name == 0)
14089 {
14090 if (TARGET_DEBUG_BUILTIN)
14091 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
14092 (long unsigned)i);
14093
14094 continue;
14095 }
14096
14097 if (icode == CODE_FOR_nothing)
14098 {
14099 if (TARGET_DEBUG_BUILTIN)
14100 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
14101 d->name);
14102
14103 continue;
14104 }
14105
14106 mode0 = insn_data[icode].operand[0].mode;
14107 mode1 = insn_data[icode].operand[1].mode;
14108 mode2 = insn_data[icode].operand[2].mode;
14109
14110 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
14111 d->code, d->name);
14112 }
14113
14114 def_builtin (d->name, type, d->code);
14115 }
14116
14117 /* Add the simple unary operators. */
14118 d = bdesc_1arg;
14119 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
14120 {
14121 machine_mode mode0, mode1;
14122 tree type;
14123 HOST_WIDE_INT mask = d->mask;
14124
14125 if ((mask & builtin_mask) != mask)
14126 {
14127 if (TARGET_DEBUG_BUILTIN)
14128 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
14129 continue;
14130 }
14131
14132 if (rs6000_overloaded_builtin_p (d->code))
14133 {
14134 if (! (type = opaque_ftype_opaque))
14135 type = opaque_ftype_opaque
14136 = build_function_type_list (opaque_V4SI_type_node,
14137 opaque_V4SI_type_node,
14138 NULL_TREE);
14139 }
14140 else
14141 {
14142 enum insn_code icode = d->icode;
14143 if (d->name == 0)
14144 {
14145 if (TARGET_DEBUG_BUILTIN)
14146 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
14147 (long unsigned)i);
14148
14149 continue;
14150 }
14151
14152 if (icode == CODE_FOR_nothing)
14153 {
14154 if (TARGET_DEBUG_BUILTIN)
14155 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
14156 d->name);
14157
14158 continue;
14159 }
14160
14161 mode0 = insn_data[icode].operand[0].mode;
14162 mode1 = insn_data[icode].operand[1].mode;
14163
14164 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
14165 d->code, d->name);
14166 }
14167
14168 def_builtin (d->name, type, d->code);
14169 }
14170
14171 /* Add the simple no-argument operators. */
14172 d = bdesc_0arg;
14173 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
14174 {
14175 machine_mode mode0;
14176 tree type;
14177 HOST_WIDE_INT mask = d->mask;
14178
14179 if ((mask & builtin_mask) != mask)
14180 {
14181 if (TARGET_DEBUG_BUILTIN)
14182 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
14183 continue;
14184 }
14185 if (rs6000_overloaded_builtin_p (d->code))
14186 {
14187 if (!opaque_ftype_opaque)
14188 opaque_ftype_opaque
14189 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
14190 type = opaque_ftype_opaque;
14191 }
14192 else
14193 {
14194 enum insn_code icode = d->icode;
14195 if (d->name == 0)
14196 {
14197 if (TARGET_DEBUG_BUILTIN)
14198 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
14199 (long unsigned) i);
14200 continue;
14201 }
14202 if (icode == CODE_FOR_nothing)
14203 {
14204 if (TARGET_DEBUG_BUILTIN)
14205 fprintf (stderr,
14206 "rs6000_builtin, skip no-argument %s (no code)\n",
14207 d->name);
14208 continue;
14209 }
14210 mode0 = insn_data[icode].operand[0].mode;
14211 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
14212 d->code, d->name);
14213 }
14214 def_builtin (d->name, type, d->code);
14215 }
14216}
14217
14218/* Return the internal arg pointer used for function incoming
14219 arguments. When -fsplit-stack, the arg pointer is r12 so we need
14220 to copy it to a pseudo in order for it to be preserved over calls
14221 and suchlike. We'd really like to use a pseudo here for the
14222 internal arg pointer but data-flow analysis is not prepared to
14223 accept pseudos as live at the beginning of a function. */
14224
14225rtx
14226rs6000_internal_arg_pointer (void)
14227{
14228 if (flag_split_stack
14229 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
14230 == NULL))
14231
14232 {
14233 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
14234 {
14235 rtx pat;
14236
14237 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
14238 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
14239
14240 /* Put the pseudo initialization right after the note at the
14241 beginning of the function. */
14242 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
14243 gen_rtx_REG (Pmode, 12));
14244 push_topmost_sequence ();
14245 emit_insn_after (pat, get_insns ());
14246 pop_topmost_sequence ();
14247 }
14248 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
14249 FIRST_PARM_OFFSET (current_function_decl));
14250 return copy_to_reg (ret);
14251 }
14252 return virtual_incoming_args_rtx;
14253}
14254
14255\f
14256/* A C compound statement that outputs the assembler code for a thunk
14257 function, used to implement C++ virtual function calls with
14258 multiple inheritance. The thunk acts as a wrapper around a virtual
14259 function, adjusting the implicit object parameter before handing
14260 control off to the real function.
14261
14262 First, emit code to add the integer DELTA to the location that
14263 contains the incoming first argument. Assume that this argument
14264 contains a pointer, and is the one used to pass the `this' pointer
14265 in C++. This is the incoming argument *before* the function
14266 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14267 values of all other incoming arguments.
14268
14269 After the addition, emit code to jump to FUNCTION, which is a
14270 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14271 not touch the return address. Hence returning from FUNCTION will
14272 return to whoever called the current `thunk'.
14273
14274 The effect must be as if FUNCTION had been called directly with the
14275 adjusted first argument. This macro is responsible for emitting
14276 all of the code for a thunk function; output_function_prologue()
14277 and output_function_epilogue() are not invoked.
14278
14279 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14280 been extracted from it.) It might possibly be useful on some
14281 targets, but probably not.
14282
14283 If you do not define this macro, the target-independent code in the
14284 C++ frontend will generate a less efficient heavyweight thunk that
14285 calls FUNCTION instead of jumping to it. The generic approach does
14286 not support varargs. */
14287
14288void
14289rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14290 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14291 tree function)
14292{
14293 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
14294 rtx this_rtx, funexp;
14295 rtx_insn *insn;
14296
14297 reload_completed = 1;
14298 epilogue_completed = 1;
14299
14300 /* Mark the end of the (empty) prologue. */
14301 emit_note (NOTE_INSN_PROLOGUE_END);
14302
14303 /* Find the "this" pointer. If the function returns a structure,
14304 the structure return pointer is in r3. */
14305 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14306 this_rtx = gen_rtx_REG (Pmode, 4);
14307 else
14308 this_rtx = gen_rtx_REG (Pmode, 3);
14309
14310 /* Apply the constant offset, if required. */
14311 if (delta)
14312 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
14313
14314 /* Apply the offset from the vtable, if required. */
14315 if (vcall_offset)
14316 {
14317 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14318 rtx tmp = gen_rtx_REG (Pmode, 12);
14319
14320 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
14321 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14322 {
14323 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
14324 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14325 }
14326 else
14327 {
14328 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14329
14330 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14331 }
14332 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
14333 }
14334
14335 /* Generate a tail call to the target function. */
14336 if (!TREE_USED (function))
14337 {
14338 assemble_external (function);
14339 TREE_USED (function) = 1;
14340 }
14341 funexp = XEXP (DECL_RTL (function), 0);
14342 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
14343
aef57966 14344 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, const0_rtx));
1acf0246
BS		 14345 SIBLING_CALL_P (insn) = 1;
14346 emit_barrier ();
14347
14348 /* Run just enough of rest_of_compilation to get the insns emitted.
14349 There's not really enough bulk here to make other passes such as
14350 instruction scheduling worth while. */
14351 insn = get_insns ();
14352 shorten_branches (insn);
14353 assemble_start_function (thunk_fndecl, fnname);
14354 final_start_function (insn, file, 1);
14355 final (insn, file, 1);
14356 final_end_function ();
14357 assemble_end_function (thunk_fndecl, fnname);
14358
14359 reload_completed = 0;
14360 epilogue_completed = 0;
14361}
14362
14363#include "gt-rs6000-call.h"
Mirror of https://gcc.gnu.org/git/gcc.git