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[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000-call.c
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1acf0246
BS		 1/* Subroutines used to generate function calls and handle built-in
2 instructions on IBM RS/6000.
8d9254fc 3 Copyright (C) 1991-2020 Free Software Foundation, Inc.
1acf0246
BS		 4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21#define IN_TARGET_CODE 1
22
23#include "config.h"
24#include "system.h"
25#include "coretypes.h"
26#include "backend.h"
27#include "rtl.h"
28#include "tree.h"
29#include "memmodel.h"
30#include "gimple.h"
31#include "cfghooks.h"
32#include "cfgloop.h"
33#include "df.h"
34#include "tm_p.h"
35#include "stringpool.h"
36#include "expmed.h"
37#include "optabs.h"
38#include "regs.h"
39#include "ira.h"
40#include "recog.h"
41#include "cgraph.h"
42#include "diagnostic-core.h"
43#include "insn-attr.h"
44#include "flags.h"
45#include "alias.h"
46#include "fold-const.h"
47#include "attribs.h"
48#include "stor-layout.h"
49#include "calls.h"
50#include "print-tree.h"
51#include "varasm.h"
52#include "explow.h"
53#include "expr.h"
54#include "output.h"
55#include "common/common-target.h"
56#include "langhooks.h"
57#include "gimplify.h"
58#include "gimple-fold.h"
59#include "gimple-iterator.h"
60#include "gimple-ssa.h"
61#include "builtins.h"
62#include "tree-vector-builder.h"
63#if TARGET_XCOFF
64#include "xcoffout.h" /* get declarations of xcoff_*_section_name */
65#endif
66#include "ppc-auxv.h"
67#include "tree-ssa-propagate.h"
68#include "tree-vrp.h"
69#include "tree-ssanames.h"
70#include "targhooks.h"
691eeb65 71#include "opts.h"
1acf0246
BS		 72
73#include "rs6000-internal.h"
74
75#if TARGET_MACHO
76#include "gstab.h" /* for N_SLINE */
77#include "dbxout.h" /* dbxout_ */
78#endif
79
80#ifndef TARGET_PROFILE_KERNEL
81#define TARGET_PROFILE_KERNEL 0
82#endif
83
c3550462
BS		 84#ifdef HAVE_AS_GNU_ATTRIBUTE
85# ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
86# define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
87# endif
88#endif
89
48df9391
IS		 90#ifndef TARGET_NO_PROTOTYPE
91#define TARGET_NO_PROTOTYPE 0
92#endif
93
1acf0246
BS		 94struct builtin_description
95{
96 const HOST_WIDE_INT mask;
97 const enum insn_code icode;
98 const char *const name;
99 const enum rs6000_builtins code;
100};
101
102/* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
103static const struct
104{
105 const char *cpu;
106 unsigned int cpuid;
107} cpu_is_info[] = {
108 { "power9", PPC_PLATFORM_POWER9 },
109 { "power8", PPC_PLATFORM_POWER8 },
110 { "power7", PPC_PLATFORM_POWER7 },
111 { "power6x", PPC_PLATFORM_POWER6X },
112 { "power6", PPC_PLATFORM_POWER6 },
113 { "power5+", PPC_PLATFORM_POWER5_PLUS },
114 { "power5", PPC_PLATFORM_POWER5 },
115 { "ppc970", PPC_PLATFORM_PPC970 },
116 { "power4", PPC_PLATFORM_POWER4 },
117 { "ppca2", PPC_PLATFORM_PPCA2 },
118 { "ppc476", PPC_PLATFORM_PPC476 },
119 { "ppc464", PPC_PLATFORM_PPC464 },
120 { "ppc440", PPC_PLATFORM_PPC440 },
121 { "ppc405", PPC_PLATFORM_PPC405 },
122 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
123};
124
125/* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
126static const struct
127{
128 const char *hwcap;
129 int mask;
130 unsigned int id;
131} cpu_supports_info[] = {
132 /* AT_HWCAP masks. */
133 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
134 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
135 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
136 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
137 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
138 { "booke", PPC_FEATURE_BOOKE, 0 },
139 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
140 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
141 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
142 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
143 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
144 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
145 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
146 { "notb", PPC_FEATURE_NO_TB, 0 },
147 { "pa6t", PPC_FEATURE_PA6T, 0 },
148 { "power4", PPC_FEATURE_POWER4, 0 },
149 { "power5", PPC_FEATURE_POWER5, 0 },
150 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
151 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
152 { "ppc32", PPC_FEATURE_32, 0 },
153 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
154 { "ppc64", PPC_FEATURE_64, 0 },
155 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
156 { "smt", PPC_FEATURE_SMT, 0 },
157 { "spe", PPC_FEATURE_HAS_SPE, 0 },
158 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
159 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
160 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
161
162 /* AT_HWCAP2 masks. */
163 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
164 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
165 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
166 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
167 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
168 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
169 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
170 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
171 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
172 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
173 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
174 { "darn", PPC_FEATURE2_DARN, 1 },
175 { "scv", PPC_FEATURE2_SCV, 1 }
176};
177
178static void altivec_init_builtins (void);
179static tree builtin_function_type (machine_mode, machine_mode,
180 machine_mode, machine_mode,
181 enum rs6000_builtins, const char *name);
182static void rs6000_common_init_builtins (void);
183static void htm_init_builtins (void);
184
185
186/* Hash table to keep track of the argument types for builtin functions. */
187
188struct GTY((for_user)) builtin_hash_struct
189{
190 tree type;
191 machine_mode mode[4]; /* return value + 3 arguments. */
192 unsigned char uns_p[4]; /* and whether the types are unsigned. */
193};
194
195struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
196{
197 static hashval_t hash (builtin_hash_struct *);
198 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
199};
200
201static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
202
203/* Hash function for builtin functions with up to 3 arguments and a return
204 type. */
205hashval_t
206builtin_hasher::hash (builtin_hash_struct *bh)
207{
208 unsigned ret = 0;
209 int i;
210
211 for (i = 0; i < 4; i++)
212 {
213 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
214 ret = (ret * 2) + bh->uns_p[i];
215 }
216
217 return ret;
218}
219
220/* Compare builtin hash entries H1 and H2 for equivalence. */
221bool
222builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
223{
224 return ((p1->mode[0] == p2->mode[0])
225 && (p1->mode[1] == p2->mode[1])
226 && (p1->mode[2] == p2->mode[2])
227 && (p1->mode[3] == p2->mode[3])
228 && (p1->uns_p[0] == p2->uns_p[0])
229 && (p1->uns_p[1] == p2->uns_p[1])
230 && (p1->uns_p[2] == p2->uns_p[2])
231 && (p1->uns_p[3] == p2->uns_p[3]));
232}
233
234\f
235/* Table that classifies rs6000 builtin functions (pure, const, etc.). */
236#undef RS6000_BUILTIN_0
237#undef RS6000_BUILTIN_1
238#undef RS6000_BUILTIN_2
239#undef RS6000_BUILTIN_3
240#undef RS6000_BUILTIN_A
241#undef RS6000_BUILTIN_D
242#undef RS6000_BUILTIN_H
243#undef RS6000_BUILTIN_P
244#undef RS6000_BUILTIN_X
245
246#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
247 { NAME, ICODE, MASK, ATTR },
248
249#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
250 { NAME, ICODE, MASK, ATTR },
251
252#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
253 { NAME, ICODE, MASK, ATTR },
254
255#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
256 { NAME, ICODE, MASK, ATTR },
257
258#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
259 { NAME, ICODE, MASK, ATTR },
260
261#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
262 { NAME, ICODE, MASK, ATTR },
263
264#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
265 { NAME, ICODE, MASK, ATTR },
266
267#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
268 { NAME, ICODE, MASK, ATTR },
269
270#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
271 { NAME, ICODE, MASK, ATTR },
272
273struct rs6000_builtin_info_type {
274 const char *name;
275 const enum insn_code icode;
276 const HOST_WIDE_INT mask;
277 const unsigned attr;
278};
279
25ffd3d3 280static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1acf0246
BS		 281{
282#include "rs6000-builtin.def"
283};
284
285#undef RS6000_BUILTIN_0
286#undef RS6000_BUILTIN_1
287#undef RS6000_BUILTIN_2
288#undef RS6000_BUILTIN_3
289#undef RS6000_BUILTIN_A
290#undef RS6000_BUILTIN_D
291#undef RS6000_BUILTIN_H
292#undef RS6000_BUILTIN_P
293#undef RS6000_BUILTIN_X
294
25ffd3d3
PB		 295const struct altivec_builtin_types altivec_overloaded_builtins[] = {
296 /* Unary AltiVec/VSX builtins. */
297 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
298 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
299 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
300 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
301 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
302 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
303 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
304 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
305 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
306 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
307 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
308 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
309 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
310 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
311 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
312 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
313 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
314 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
315 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
316 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
317 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
318 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
319 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
320 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
321 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
322 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
323 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
324 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
325 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
326 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
327 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
328 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
329 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
330 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
331 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
332 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
333 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
334 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
335 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
336 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
337 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
338 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
339 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
340 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
341 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
342 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
343 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
344 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
345 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
346 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
347 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
348 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
349 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
350 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
351 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
352 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
353 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
354 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
355 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
356 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
357 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
358 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
359 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
360 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
361 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
362 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
363 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
364 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
365 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
366 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
367 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
368 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
369 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
370 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
371 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
372 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
373 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
374 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
375 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
376 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
377 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
378 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
379 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
380 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
381 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
382 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
383 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
384 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
385 { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF,
386 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
387 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
388 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
389 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
390 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
391 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
392 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
393 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
394 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
395 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
396 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
397 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
398 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
399 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
400 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
401 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
402 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
403 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
404 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
405 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
406 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
407 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
408 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
409 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
410 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
411 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
412 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
413 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
414 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
415 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
416 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
417 { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF,
418 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
419 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
420 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
421 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
422 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
423 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
424 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
425 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
426 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
427 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
428 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
429 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
430 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
431
432 /* Binary AltiVec/VSX builtins. */
433 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
434 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
435 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
436 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
437 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
438 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
439 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
440 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
441 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
442 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
443 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
444 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
445 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
446 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
447 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
448 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
449 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
450 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
451 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
452 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
453 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
454 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
455 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
456 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
457 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
458 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
459 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
460 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
461 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
462 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
463 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
464 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
465 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
466 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
467 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
468 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
469 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
470 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
471 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
472 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
473 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
474 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
475 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
476 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
477 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
478 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
479 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
480 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
481 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
482 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
483 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
484 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
485 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
486 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
487 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
488 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
489 RS6000_BTI_unsigned_V1TI, 0 },
490 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
491 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
492 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
493 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
494 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
495 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
496 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
497 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
498 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
499 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
500 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
501 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
502 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
503 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
504 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
505 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
506 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
507 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
508 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
509 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
510 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
511 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
512 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
513 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
514 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
515 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
516 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
517 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
518 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
519 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
520 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
521 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
522 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
523 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
524 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
525 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
526 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
527 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
528 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
529 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
530 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
531 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
532 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
533 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
534 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
535 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
536 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
537 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
538 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
539 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
540 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
541 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
542 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
543 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
544 RS6000_BTI_unsigned_V4SI, 0 },
545 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
546 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
547 RS6000_BTI_unsigned_V1TI, 0 },
548 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
549 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
550 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
551 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
552 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
553 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
554 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
555 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
556 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
557 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
558 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
559 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
560 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
561 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
562 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
563 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
564 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
565 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
566 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
567 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
568 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
569 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
570 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
571 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
572 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
573 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
574 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
575 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
576 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
577 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
578 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
579 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
580 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
581 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
582 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
583 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
584 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
585 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
586 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
587 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
588 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
589 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
590 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
591 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
592 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
593 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
594 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
595 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
596 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
597 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
598 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
599 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
600 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
601 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
602 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
603 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
604 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
605 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
606 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
607 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
608 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
609 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
610 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
611 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
612 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
613 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
614 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
615 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
616 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
617 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
618 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
619 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
620 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
621 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
622 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
623 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
624 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
625 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
626 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
627 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
628 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
629 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
630 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
631 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
632 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
633 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
634 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
635 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
636 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
637 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
638 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23
PB		 639
640 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
25ffd3d3 641 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 642 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
25ffd3d3 643 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 644 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
25ffd3d3 645 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 646 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
25ffd3d3 647 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 648 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
25ffd3d3 649 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 650 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
25ffd3d3 651 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 652 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
25ffd3d3 653 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 654 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
25ffd3d3 655 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 656 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
25ffd3d3 657 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 658 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 659 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 660 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 661 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 662 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 663 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 664 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 665 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 666 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 667 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 668 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
25ffd3d3 669 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 670 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
25ffd3d3 671 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 672 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
25ffd3d3 673 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 674 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 675 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 676 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 677 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 678 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 679 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 680 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 681 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 682 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
25ffd3d3 683 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 684 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
25ffd3d3 685 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 686 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
25ffd3d3 687 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 688 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 689 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 690 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 691 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 692 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 693 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 694 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
25ffd3d3 695 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 696 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 697 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 698 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
25ffd3d3 699 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 700 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
25ffd3d3 701 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 702 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 703 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 704 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 705 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 706 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 707 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23
PB		 708
709 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
25ffd3d3 710 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 711 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
25ffd3d3 712 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 713 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
25ffd3d3 714 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 715 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
25ffd3d3 716 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 717 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
25ffd3d3 718 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 719 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
25ffd3d3 720 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 721 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
25ffd3d3 722 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 723 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
25ffd3d3 724 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 725 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
25ffd3d3 726 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 727 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 728 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 729 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 730 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 731 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 732 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 733 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 734 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 735 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 736 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 737 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
25ffd3d3 738 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 739 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
25ffd3d3 740 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 741 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
25ffd3d3 742 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 743 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 744 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 745 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 746 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 747 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 748 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 749 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 750 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 751 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
25ffd3d3 752 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 753 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
25ffd3d3 754 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 755 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
25ffd3d3 756 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 757 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 758 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 759 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 760 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 761 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 762 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 763 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
25ffd3d3 764 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 765 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 766 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 767 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
25ffd3d3 768 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 769 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
25ffd3d3 770 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 771 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 772 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 773 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 774 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 775 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 776 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 777
25ffd3d3
PB		 778 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
779 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
780 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
781 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
782 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
783 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
784 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
785 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
786 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
787 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
788 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
789 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
790 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
791 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
792 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
793 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
794 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
795 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
796 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
797 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
798 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
799 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
800 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
801 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
802 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
803 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
804 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
805 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
806 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
807 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
808 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
809 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
810 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
811 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
812 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
813 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
814 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
815 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
816 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
817 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
818 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
819 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
820 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
821 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
822 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
823 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
824 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
825 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
826 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
827 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
828 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
829 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
830 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
831 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
832 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
833 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
834
835 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
836 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
837 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
838 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
839
840 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
841 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
842 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
843 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
844
845 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
846 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
847 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
848 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
849
850 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
851 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
852 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
853 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
854 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
855 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
856 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
857 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
858 RS6000_BTI_unsigned_V16QI, 0},
859 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
860 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
861 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
862 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
863 RS6000_BTI_unsigned_V8HI, 0},
864 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
865 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
866 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
867 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
868 RS6000_BTI_unsigned_V4SI, 0},
869 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
870 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
871 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
872 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
873 RS6000_BTI_unsigned_V2DI, 0},
874 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
875 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
876 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
877 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
878 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
879 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
880 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
881 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
882 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
883 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
884 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
885 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
886 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
887 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
888 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
889 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
890 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
891 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
892 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
893 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
894 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
895 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
896 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
897 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
898 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
899 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
900 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
901 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
902 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
903 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
904 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
905 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
906 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
907 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
908 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
909 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
910 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
911 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
912 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
913 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
914 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
915 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
916 RS6000_BTI_unsigned_V16QI, 0},
917 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
918 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
919 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
920 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
921 RS6000_BTI_unsigned_V8HI, 0},
922 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
923 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
924 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
925 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
926 RS6000_BTI_unsigned_V4SI, 0},
927 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
928 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
929 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
930 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
931 RS6000_BTI_unsigned_V2DI, 0},
932 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
933 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
934 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
935 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
936 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
937 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
938 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
939 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
940 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
941 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
942 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
943 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
944 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
945 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
946 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
947 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
948 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
949 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
950 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
951 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
952 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
953 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
954 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
955 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
956 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
957 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
958 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
959 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
960 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
961 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
962 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
963 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
964 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
965 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
966 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
967 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
968 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
969 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
970 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
971 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
972 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
973 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
974 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
975 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
976 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
977 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
978 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
979 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
980 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
981 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
982 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
983 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
984 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
985 RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
986 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
987 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
988
989 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
990 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
991 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
992 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
993 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
994 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
995
996 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
997 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
998 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
999 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1000 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
1001 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1002
1003 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI,
1004 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1005 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI,
1006 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1007 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF,
1008 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1009
1010 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI,
1011 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1012 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI,
1013 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1014 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF,
1015 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1016
1017 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1018 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1019 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1020 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1021 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF,
1022 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1023 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI,
1024 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1025 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI,
1026 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1027 RS6000_BTI_unsigned_V2DI, 0 },
1028 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1029 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1030 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1031 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1032 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI,
1033 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1034 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF,
1035 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1036 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1037 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1038 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1039 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1040
1041 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1042 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
1043 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1044 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 },
1045 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1046 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
1047 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1048 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
1049
1050 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1051 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1052 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1053 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1054 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1055 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1056 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1057 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1058 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1059 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1060 ~RS6000_BTI_unsigned_V2DI, 0 },
1061 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1062 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1063 ~RS6000_BTI_unsigned_long_long, 0 },
1064 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1065 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1066 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1067 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1068 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1069 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1070 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1071 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1072 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1073 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1074 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1075 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1076 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1077 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1078 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1079 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1080 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1081 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1082 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1083 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1084 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1085 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1086 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1087 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1088 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1089 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1090 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1091 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1092 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1093 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1094 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1095 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1096 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1097 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1098 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1099 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1100 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1101 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1102 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1103 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1104 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1105 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1106 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1107 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1108 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1109 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1110 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1111 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1112 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1113 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1114 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1115 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1116 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1117 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1118 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1119 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1120 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1121 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1122 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1123 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1124 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1125 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1126 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1127 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1128 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1129 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1130 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1131 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1132 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1133 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1134 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1135 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1136 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1137 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1138 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1139 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1140 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1141 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1142
1143 /* vector float vec_ldl (int, vector float *);
1144 vector float vec_ldl (int, float *); */
1145 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1146 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1147 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1148 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1149
1150 /* vector bool int vec_ldl (int, vector bool int *);
1151 vector bool int vec_ldl (int, bool int *);
1152 vector int vec_ldl (int, vector int *);
1153 vector int vec_ldl (int, int *);
1154 vector unsigned int vec_ldl (int, vector unsigned int *);
1155 vector unsigned int vec_ldl (int, unsigned int *); */
1156 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1157 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1158 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1159 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 },
1160 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1161 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1162 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1163 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1164 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1165 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1166 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1167 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1168
1169 /* vector bool short vec_ldl (int, vector bool short *);
1170 vector bool short vec_ldl (int, bool short *);
1171 vector pixel vec_ldl (int, vector pixel *);
1172 vector short vec_ldl (int, vector short *);
1173 vector short vec_ldl (int, short *);
1174 vector unsigned short vec_ldl (int, vector unsigned short *);
1175 vector unsigned short vec_ldl (int, unsigned short *); */
1176 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1177 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1178 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1179 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 },
1180 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1181 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1182 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1183 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1184 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1185 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1186 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1187 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1188 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1189 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1190
1191 /* vector bool char vec_ldl (int, vector bool char *);
1192 vector bool char vec_ldl (int, bool char *);
1193 vector char vec_ldl (int, vector char *);
1194 vector char vec_ldl (int, char *);
1195 vector unsigned char vec_ldl (int, vector unsigned char *);
1196 vector unsigned char vec_ldl (int, unsigned char *); */
1197 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1198 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1199 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1200 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 },
1201 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1202 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1203 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1204 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1205 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1206 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1207 ~RS6000_BTI_unsigned_V16QI, 0 },
1208 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1209 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1210
1211 /* vector double vec_ldl (int, vector double *);
1212 vector double vec_ldl (int, double *); */
1213 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1214 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1215 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1216 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1217
1218 /* vector long long vec_ldl (int, vector long long *);
1219 vector long long vec_ldl (int, long long *);
1220 vector unsigned long long vec_ldl (int, vector unsigned long long *);
1221 vector unsigned long long vec_ldl (int, unsigned long long *);
1222 vector bool long long vec_ldl (int, vector bool long long *);
1223 vector bool long long vec_ldl (int, bool long long *); */
1224 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1225 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1226 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1227 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1228 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1229 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1230 ~RS6000_BTI_unsigned_V2DI, 0 },
1231 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1232 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1233 ~RS6000_BTI_unsigned_long_long, 0 },
1234 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1235 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1236 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1237 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 },
1238
1239 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1240 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1241 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1242 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1243 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1244 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1245 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1246 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1247 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1248 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1249 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1250 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1251 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1252 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1253 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1254 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1255 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1256 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1257 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1258 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1259 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1260 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1261 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1262 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1263 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1264 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1265 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1266 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1267 ~RS6000_BTI_unsigned_long_long, 0 },
1268 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1269 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1270 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1271 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1272 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1273 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1274 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1275 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1276 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1277 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1278 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1279 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1280 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1281 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1282 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1283 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1284 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1285 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1286 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1287 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1288 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1289 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1290 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1291 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1292 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1293 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1294 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1295 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1296 ~RS6000_BTI_unsigned_long_long, 0 },
1297 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1298 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1299 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1300 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1301 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1302 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1303 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1304 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1305 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1306 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1307 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1308 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1309 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1310 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1311 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1312 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1313 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1314 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1315 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1316 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1317 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1318 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1319 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1320 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1321 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1322 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1323 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1324 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1325 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1326 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1327 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1328 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1329 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1330 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1331 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1332 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1333 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1334 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1335 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1336 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1337 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1338 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1339 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1340 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1341 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1342 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1343 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1344 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1345 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1346 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1347 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1348 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1349 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1350 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1351 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1352 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1353 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1354 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1355 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1356 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1357 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1358 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1359 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1360 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1361 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1362 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1363 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1364 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1365 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1366 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1367 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1368 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1369 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1370 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1371 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1372 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1373 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1374 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1375 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1376 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1377 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1378 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1379 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1380 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1381 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1382 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1383 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1384 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1385 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1386 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1387 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1388 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1389 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1390 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1391 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1392 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1393 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1394 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1395 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1396 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1397 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1398 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1399 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1400 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1401 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1402 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1403 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1404 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1405 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1406 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1407 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1408 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1409 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1410 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1411 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1412 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1413 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1414 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1415 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1416 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1417 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1418 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1419 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1420 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1421 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1422 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1423 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1424 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1425 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1426 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1427 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1428 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1429 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1430 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1431 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1432 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1433 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1434 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1435 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1436 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1437 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1438 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1439 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1440 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1441 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1442 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1443 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1444 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1445 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1446 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1447 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1448 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1449 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1450 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1451 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1452 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1453 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1454 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1455 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1456 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1457 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1458 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1459 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1460 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1461 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1462 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1463 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1464 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1465 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1466 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1467 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1468 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1469 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1470 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1471 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1472 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1473 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1474 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1475 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1476 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1477 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1478 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1479 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1480 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1481 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1482 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1483 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1484 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1485 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1486 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1487 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1488 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1489 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
1490 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1491 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
1492 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1493 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
1494 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1495 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1496 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1497 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1498 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1499 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1500 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1501 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1502 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1503 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1504 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1505 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1506 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1507 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1508 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1509 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1510 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1511 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1512 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1513 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1514 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1515 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1516 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1517 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1518 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1519 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1520 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1521 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1522 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1523 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1524 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1525 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1526 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1527 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1528 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1529 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1530 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1531 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1532 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1533 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1534 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1535 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1536 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1537 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1538 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1539 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1540 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1541 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1542 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1543 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1544 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1545 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1546 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1547 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1548 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1549 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1550 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1551 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1552 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1553 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1554 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1555 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1556 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1557 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1558 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1559 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1560 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1561 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1562 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1563 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1564 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1565 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
1566 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1567 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1568 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1569 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1570 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1571 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1572 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1573 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1574 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1575 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1576 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1577 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1578 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1579 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1580 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1581 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1582 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1583 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1584 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1585 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1586 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1587 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1588 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1589 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1590 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1591 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1592 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1593 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1594 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1595 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1596 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1597 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1598 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1599 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1600 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1601 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1602 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1603 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1604 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1605 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1606 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1607 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1608 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1609 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1610 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1611 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1612 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1613 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1614 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1615 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1616 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1617 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1618 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1619 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1620 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1621 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1622 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1623 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1624 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1625 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
1626 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1627 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1628 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1629 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1630 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1631 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1632 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1633 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1634 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1635 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1636 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1637 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1638 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1639 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1640 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1641 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1642 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1643 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1644 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1645 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1646 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1647 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1648 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1649 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1650 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1651 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1652 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1653 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1654 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1655 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1656 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1657 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1658 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1659 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1660 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1661 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1662 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1663 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1664 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1665 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1666 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1667 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1668 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1669 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1670 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1671 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1672 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1673 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1674 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1675 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1676 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1677 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1678 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1679 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1680 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1681 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1682 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1683 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1684 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1685 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1686 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1687 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1688 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1689 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1690 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1691 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1692 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1693 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1694 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1695 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1696 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1697 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1698 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1699 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1700 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1701 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1702 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1703 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1704 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1705 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1706 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1707 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1708 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1709 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1710 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1711 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
1712 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1713 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
1714 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1715 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
1716 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1717 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1718 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1719 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1720 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1721 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1722 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1723 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1724 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1725 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1726 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1727 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1728 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1729 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1730 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1731 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1732 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1733 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1734 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1735 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1736 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1737 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1738 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1739 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1740 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1741 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1742 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1743 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1744 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1745 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1746 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1747 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1748 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1749 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1750 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1751 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1752 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1753 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1754 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1755 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1756 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1757 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1758 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1759 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1760 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1761 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1762 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1763 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1764 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1765 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
1766 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1767 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
1768 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1769 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
1770 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1771 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
1772 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1773 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
1774 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1775 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
1776 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
1777 RS6000_BTI_unsigned_V4SI, 0 },
1778 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
1779 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1780 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
1781 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1782 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
1783 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1784 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
1785 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1786 { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
1787 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1788 { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
1789 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1790 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
1791 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1792 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
1793 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1794 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
1795 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1796 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW,
1797 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1798 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
1799 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
1800 RS6000_BTI_unsigned_V4SI, 0 },
1801 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
1802 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1803 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
1804 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1805 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
1806 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1807 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
1808 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1809 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
1810 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1811 { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW,
1812 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1813 { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW,
1814 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1815
1816 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
1817 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
1818 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
1819 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
1820 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
1821 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
1822 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
1823 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
1824 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
1825 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
1826 { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
1827 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
1828 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
1829 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
1830 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
1831 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
1832
4559be23 1833 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SF,
25ffd3d3 1834 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 1835 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DF,
25ffd3d3 1836 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 1837 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
25ffd3d3 1838 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1839 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
25ffd3d3 1840 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1841 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
25ffd3d3 1842 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1843 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1844 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1845 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1846 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1847 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1848 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1849 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1850 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1851 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI,
25ffd3d3 1852 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 1853 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
25ffd3d3 1854 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 1855 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
25ffd3d3 1856 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 1857 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI,
25ffd3d3 1858 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 1859 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
25ffd3d3 1860 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 1861 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
25ffd3d3 1862 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 1863 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI,
25ffd3d3 1864 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 1865 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
25ffd3d3 1866 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 1867 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
25ffd3d3 1868 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23
PB		 1869
1870 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
25ffd3d3 1871 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 1872 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
25ffd3d3 1873 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 1874 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
25ffd3d3 1875 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 1876 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
25ffd3d3 1877 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 1878 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
25ffd3d3 1879 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 1880 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
25ffd3d3 1881 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 1882 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
25ffd3d3 1883 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1884 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
25ffd3d3 1885 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1886 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
25ffd3d3 1887 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1888 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 1889 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1890 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 1891 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1892 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 1893 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1894 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 1895 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1896 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 1897 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 1898 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
25ffd3d3 1899 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 1900 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
25ffd3d3 1901 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 1902 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
25ffd3d3 1903 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 1904 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 1905 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 1906 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 1907 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 1908 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 1909 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 1910 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 1911 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 1912 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
25ffd3d3 1913 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 1914 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
25ffd3d3 1915 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 1916 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
25ffd3d3 1917 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 1918 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 1919 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 1920 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 1921 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 1922 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 1923 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 1924 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
25ffd3d3 1925 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 1926 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 1927 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 1928 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
25ffd3d3 1929 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 1930 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
25ffd3d3 1931 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 1932 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 1933 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 1934 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 1935 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 1936 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 1937 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 1938
25ffd3d3
PB		 1939 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
1940 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1941 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
1942 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1943 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
1944 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1945 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
1946 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1947 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
1948 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1949 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
1950 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1951 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
1952 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1953 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
1954 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1955 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
1956 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1957 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF,
1958 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1959
1960 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI,
1961 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
1962 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI,
1963 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
1964 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI,
1965 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
1966 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI,
1967 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
1968 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF,
1969 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
1970 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF,
1971 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
1972
1973 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
1974 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1975
1976 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
1977 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1978 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
1979 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1980 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
1981 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1982 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
1983 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1984 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
1985 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1986 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
1987 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1988 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
1989 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1990 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
1991 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1992 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
1993 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1994 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
1995 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1996 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
1997 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1998 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
1999 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2000 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2001 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2002 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2003 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2004 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2005 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2006 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2007 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2008 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2009 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2010 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2011 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2012
2013 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2014 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI,
2015 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2016 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2017 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI,
2018 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2019 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2020 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2021 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2022 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2023 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2024 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2025 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2026 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2027 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2028 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2029 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2030 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2031
2032 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2033 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2034 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2035 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2036 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2037 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2038 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2039 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2040 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2041 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2042 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2043 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2044 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2045 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2046 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2047 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2048 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2049 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2050 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2051 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2052 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2053 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2054 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2055 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2056 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2057 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2058 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2059 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2060 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2061 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2062 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2063 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2064 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2065 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2066 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2067 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2068 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2069 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2070 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2071 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2072 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2073 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2074 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2075 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2076 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS,
2077 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2078 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2079 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2080 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2081 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2082 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2083 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2084 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2085 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2086 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2087 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2088 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2089 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2090 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2091 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2092 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2093 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2094 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2095 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2096 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2097 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2098 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2099 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2100 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2101 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2102 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2103 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2104 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2105 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2106 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2107 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2108 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2109 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2110 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2111 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2112 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2113 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2114 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2115 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2116 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2117 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2118 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2119 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2120 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2121 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2122 RS6000_BTI_unsigned_V4SI, 0 },
2123 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2124 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2125 RS6000_BTI_unsigned_V2DI, 0 },
2126 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2127 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2128 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2129 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2130 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2131 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2132 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2133 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2134 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2135 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2136 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2137 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2138 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2139 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2140 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2141 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2142 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2143 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2144 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2145 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2146 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2147 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2148 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2149 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2150 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2151 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2152 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2153 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2154 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2155 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2156 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2157 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2158 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2159 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2160 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2161 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2162 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2163 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2164 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2165 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2166 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2167 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2168 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2169 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2170 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2171 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2172 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2173 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2174 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2175 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2176 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2177 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2178 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2179 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2180 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2181 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2182 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2183 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2184 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2185 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2186 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2187 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2188 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2189 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2190 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2191 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2192 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2193 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2194 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2195 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2196 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2197 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2198 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2199 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2200 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2201 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2202 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2203 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2204 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2205 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2206 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2207 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2208 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2209 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2210 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2211 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2212 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2213 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2214 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2215 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2216 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2217 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2218
2219 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2220 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2221 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2222 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2223 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2224 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2225 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2226 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2227 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2228 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 },
2229
2230 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2231 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2232 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2233 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2234 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2235 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2236 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2237 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2238 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2239 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2240 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2241 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2242 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2243 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2244 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2245 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2246 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2247 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2248 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2249 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2250 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2251 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2252 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2253 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2254 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2255 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2256 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2257 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2258 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2259 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2260 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2261 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2262 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2263 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2264 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2265 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2266 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2267 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2268 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2269 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2270 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2271 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2272 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2273 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2274 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2275 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2276 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2277 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2278 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2279 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2280 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2281 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2282 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2283 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2284 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2285 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2286 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2287 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2288 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2289 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2290 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2291 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2292 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2293 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2294 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2295 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2296 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2297 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2298 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2299 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2300 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2301 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2302 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2303 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2304 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2305 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2306 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2307 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2308 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2309 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2310 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2311 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2312 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2313 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2314 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2315 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2316 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2317 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2318 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2319 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2320 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2321 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2322 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2323 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2324 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2325 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2326 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2327 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2328 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2329 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2330 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2331 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2332 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2333 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2334 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2335 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2336 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2337 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2338 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2339 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2340 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2341 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2342 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2343 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2344 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2345 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2346 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2347 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2348 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2349 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2350 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2351 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2352 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2353 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2354 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2355 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2356 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2357 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2358 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2359 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2360 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2361 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2362 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2363 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2364 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2365 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2366 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2367 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2368 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2369 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2370 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2371 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2372 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2373 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2374 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2375 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2376 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2377 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2378 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2379 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2380 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2381 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2382 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2383 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2384 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2385 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2386 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2387 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2388 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2389 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2390 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2391 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2392 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2393 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2394 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2395 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2396 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2397 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2398 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2399 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2400 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2401 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2402 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2403 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2404 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2405 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2406 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2407 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2408 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2409 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2410 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2411 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2412 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2413 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2414 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2415 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2416 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2417 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2418 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2419 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2420 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2421 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2422 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2423 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2424 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2425 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2426 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2427 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2428 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2429 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2430 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2431 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2432 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2433 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2434 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2435 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2436 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2437 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2438 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2439 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2440 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2441 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2442 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2443 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2444 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2445 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2446 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2447 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2448 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2449 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2450 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2451 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2452 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2453 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2454 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2455 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2456 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2457 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2458 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2459 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2460 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2461 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2462 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2463 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2464 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2465 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2466 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2467 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2468 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2469 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2470 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2471 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2472 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2473 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2474 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2475 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2476 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2477 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2478 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2479 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2480 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2481 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2482
2483 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2484 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2485 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2486 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2487 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2488 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2489 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2490 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2491 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2492 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2493 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2494 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2495 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2496 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2497 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2498 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2499 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2500 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2501 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2502 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2503 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2504 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2505 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2506 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2507 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2508 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2509 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2510 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2511 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2512 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2513 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2514 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2515 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2516 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2517 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2518 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2519 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2520 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2521 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2522 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2523 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2524 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2525 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2526 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2527 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2528 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2529 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2530 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2531 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
2532 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2533 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
2534 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2535 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2536 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2537 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2538 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2539 RS6000_BTI_unsigned_V1TI, 0 },
2540 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
2541 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2542 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2543 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2544 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2545 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2546 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2547 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2548 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2549 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2550 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2551 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2552 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2553 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2554 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2555 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2556 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2557 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2558 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2559 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2560 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2561 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2562 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2563 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2564 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2565 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2566 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2567 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2568 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2569 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2570 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2571 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2572 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2573 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2574 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2575 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2576 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2577 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2578 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2579 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2580 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2581 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2582 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2583 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2584 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2585 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2586 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2587 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2588 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2589 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2590
2591 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2592 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2593 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2594 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2595 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2596 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2597 RS6000_BTI_unsigned_V1TI, 0 },
2598 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2599 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2600
2601 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2602 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2603 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2604 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2605 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2606 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2607 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2608 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2609 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2610 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2611 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2612 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2613 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2614 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2615 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2616 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2617 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2618 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2619 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2620 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2621 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2622 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2623 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2624 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2625 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2626 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2627 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2628 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2629 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2630 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2631 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2632 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2633 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2634 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2635 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2636 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2637 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2638 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2639 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2640 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2641 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2642 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2643 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2644 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2645 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2646 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2647 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2648 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2649 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2650 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2651 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2652 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2653 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2654 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2655 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2656 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2657 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2658 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2659 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2660 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2661 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2662 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2663 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2664 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2665 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2666 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2667 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2668 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2669 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2670 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2671 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2672 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2673 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2674 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2675 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2676 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2677 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2678 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2679 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2680 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2681 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2682 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2683 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2684 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2685 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
2686 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2687 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
2688 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2689 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
2690 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2691 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
2692 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2693 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
2694 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2695 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
2696 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2697 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
2698 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2699 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
2700 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2701
2702 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
2703 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
2704 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
2705 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
2706 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2707 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
2708 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2709 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
2710 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2711 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
2712 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2713 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
2714 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2715 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
2716 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2717 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
2718 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2719 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2720 ~RS6000_BTI_unsigned_V2DI, 0 },
2721 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2722 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2723 ~RS6000_BTI_unsigned_long_long, 0 },
2724 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2725 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
2726
2727 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
2728 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
2729 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
2730 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
2731 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2732 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
2733 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2734 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
2735 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2736 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
2737 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2738 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
2739 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2740 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
2741 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2742 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
2743 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2744 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
2745 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2746 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
2747 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2748 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
2749 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2750 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
2751 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2752 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
2753 ~RS6000_BTI_unsigned_V16QI, 0 },
2754 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2755 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
2756
2757 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
2758 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
2759 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
2760 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
2761 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
2762 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
2763 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
2764 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
2765 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2766 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
2767 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2768 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
2769 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2770 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2771 ~RS6000_BTI_unsigned_V2DI, 0 },
2772 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2773 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2774 ~RS6000_BTI_unsigned_long_long, 0 },
2775 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
2776 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
2777 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
2778 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
2779 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2780 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
2781 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2782 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
2783 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2784 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
2785 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2786 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
2787 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2788 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
2789 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2790 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
2791 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2792 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
2793 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2794 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
2795 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2796 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
2797 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2798 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
2799 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2800 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
2801 ~RS6000_BTI_unsigned_V16QI, 0 },
2802 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2803 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4559be23
PB		 2804
2805 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF,
25ffd3d3 2806 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 2807 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2808 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 2809 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF,
25ffd3d3 2810 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 2811 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF,
25ffd3d3 2812 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 2813 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2814 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 2815 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF,
25ffd3d3 2816 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 2817 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2818 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 2819 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2820 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2821 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2822 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 2823 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2824 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 2825 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2826 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2827 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2828 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 2829 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2830 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2831 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2832 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2833 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2834 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 2835 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2836 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2837 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2838 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 2839 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2840 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 2841 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2842 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2843 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2844 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 2845 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 2846 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2847 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
25ffd3d3 2848 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 2849 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
25ffd3d3 2850 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2851 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
25ffd3d3 2852 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 2853 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 2854 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 2855 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 2856 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2857 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 2858 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23
PB		 2859
2860 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
25ffd3d3 2861 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23
PB		 2862 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
2863 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2864 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
25ffd3d3 2865 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23
PB		 2866 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
2867 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2868 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
2869 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2870 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
2871 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2872 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
2873 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2874 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
25ffd3d3 2875 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 2876 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
25ffd3d3
PB		 2877 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2878
2879 /* Ternary AltiVec/VSX builtins. */
2880 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2881 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2882 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2883 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2884 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2885 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2886 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2887 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2888 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2889 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2890 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2891 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2892 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2893 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2894 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2895 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2896 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2897 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2898 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2899 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2900 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2901 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2902 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2903 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2904 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2905 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2906 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2907 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2908 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2909 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2910 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2911 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2912 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2913 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2914 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2915 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2916 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2917 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2918 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
2919 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2920 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2921 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2922 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2923 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2924 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2925 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2926 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2927 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2928 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2929 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2930 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2931 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2932 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2933 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2934 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2935 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2936 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2937 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2938 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2939 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2940 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2941 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2942 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2943 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2944 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2945 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2946 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2947 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2948 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2949 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2950 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2951 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2952 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2953 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2954 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2955 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2956 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2957 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2958 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
2959 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2960 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2961 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2962 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2963 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2964 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2965 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2966 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2967 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2968 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2969 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2970 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2971 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2972 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2973 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2974 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2975 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2976 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2977 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2978 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2979 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2980 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2981 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2982 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2983 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2984 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2985 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2986 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2987 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2988 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2989 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2990 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2991 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2992 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2993 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2994 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2995 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2996 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2997 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
2998 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
2999 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3000 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3001 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3002 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3003 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3004 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3005 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3006 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3007 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3008 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3009 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3010 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3011 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3012 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3013 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3014 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3015 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3016 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3017 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3018 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3019 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3020 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3021 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3022 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3023 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3024 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3025 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3026 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3027 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3028 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3029 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3030 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3031 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3032 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3033 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3034 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3035 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3036 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3037 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3038 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3039 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3040 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3041 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3042 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3043 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3044 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3045 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3046 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3047 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3048 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3049 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3050 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3051 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3052 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3053 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3054 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3055 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3056 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3057 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3058 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3059 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3060 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3061 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3062 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3063 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3064 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3065 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3066 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3067 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3068 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3069 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3070 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3071 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3072 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3073 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3074 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3075 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3076 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3077 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3078 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3079 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3080 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3081 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3082 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3083 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3084 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3085 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3086 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3087 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3088 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3089 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3090 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3091 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3092 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3093 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3094 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3095 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3096 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3097 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3098 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3099 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3100 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3101 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3102 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3103 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3104 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3105 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3106 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3107 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3108 RS6000_BTI_unsigned_V16QI },
3109 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3110 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3111 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3112 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3113 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3114 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3115 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3116 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3117 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3118 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3119 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3120 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3121 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3122 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3123 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3124 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3125 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3126 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3127 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3128 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3129 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3130 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3131 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3132 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3133 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3134 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3135
3136 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3137 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
3138 RS6000_BTI_bool_V16QI },
3139 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3140 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3141 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3142 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3143 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3144
3145 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3146 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3147 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3148 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3149 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3150 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3151 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3152 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3153 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3154 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3155 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3156 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3157 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3158 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3159 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3160 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3161 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3162 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3163 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3164 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3165 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3166 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3167 RS6000_BTI_bool_V2DI },
3168 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3169 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3170 RS6000_BTI_unsigned_V2DI },
3171 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3172 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3173 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3174 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3175 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3176 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3177 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3178 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3179 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3180 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3181 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3182 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3183 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3184 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3185 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3186 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3187 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3188 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3189 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3190 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3191 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3192 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3193 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3194 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3195 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3196 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3197 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3198 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3199 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3200 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3201 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3202 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3203 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3204 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3205 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3206 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3207 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3208 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3209 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3210 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3211 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3212 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3213 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3214 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3215 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3216 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3217 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3218 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3219 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3220 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI },
3221 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3222 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3223 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3224 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3225 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3226 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3227 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3228 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI },
3229 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3230 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI },
3231 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3232 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3233 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3234 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3235 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3236 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI },
3237 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3238 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3239 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3240 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI },
3241 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3242 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3243 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3244 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3245
3246 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3247 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3248 RS6000_BTI_INTSI },
3249 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3250 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3251 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3252 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3253 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3254 RS6000_BTI_INTSI },
3255 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3256 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3257 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3258 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3259 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3260 RS6000_BTI_INTSI },
3261 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3262 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3263 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3264 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3265 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3266 RS6000_BTI_INTSI },
3267 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3268 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3269 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3270
3271 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3272 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3273 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3274 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3275 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3276 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3277 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3278 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
3279 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3280 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3281 ~RS6000_BTI_unsigned_V2DI },
3282 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3283 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3284 ~RS6000_BTI_unsigned_long_long },
3285 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3286 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3287 ~RS6000_BTI_bool_V2DI },
3288 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3289 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3290 ~RS6000_BTI_long_long },
3291 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3292 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3293 ~RS6000_BTI_unsigned_long_long },
3294 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3295 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3296 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3297 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3298 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3299 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3300 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3301 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3302 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3303 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3304 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3305 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3306 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3307 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3308 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3309 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3310 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3311 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3312 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3313 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3314 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3315 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3316 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3317 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3318 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3319 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3320 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3321 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3322 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3323 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3324 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3325 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3326 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3327 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3328 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3329 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3330 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3331 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3332 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3333 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3334 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3335 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3336 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3337 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3338 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3339 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3340 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3341 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3342 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3343 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3344 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3345 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3346 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3347 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3348 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3349 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3350 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3351 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3352 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3353 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3354 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3355 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3356 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3357 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3358 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3359 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3360 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3361 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3362 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3363 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3364 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3365 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3366 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3367 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3368 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3369 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3370 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3371 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3372 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3373 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3374 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3375 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3376 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3377 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3378 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3379 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3380 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3381 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3382 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3383 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3384 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3385 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3386 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3387 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3388 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3389 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3390 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3391 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3392 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3393 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3394 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3395 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3396 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3397 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3398 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3399 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3400 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3401 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3402 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3403 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3404 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3405 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3406 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3407 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3408 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3409 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3410 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3411 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3412 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3413 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3414 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3415 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3416 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3417 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3418 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3419 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3420 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3421 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3422 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3423 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3424 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3425 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3426 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3427 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3428 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3429 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3430 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3431 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3432 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3433 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3434 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3435 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3436 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3437 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3438 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3439 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3440 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3441 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3442 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3443 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3444 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3445 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3446 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3447 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3448 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3449 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3450 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3451 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3452 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3453 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3454 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3455 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3456 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3457 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3458 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3459 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3460 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3461 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3462 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3463 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3464 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3465 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3466 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3467 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3468 ~RS6000_BTI_unsigned_V2DI },
3469 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3470 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3471 ~RS6000_BTI_bool_V2DI },
3472 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3473 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3474 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3475 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3476 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3477 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3478 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3479 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3480 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3481 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3482 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3483 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3484 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3485 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3486 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3487 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3488 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3489 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3490 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3491 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3492 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3493 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3494 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3495 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3496 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3497 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3498 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3499 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3500 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3501 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3502 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3503 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3504 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3505 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3506 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3507 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3508 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3509 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3510 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3511 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3512 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3513 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3514 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3515 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3516 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3517 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3518 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3519 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3520 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3521 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3522 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3523 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3524 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3525 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3526 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3527 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3528 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3529 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3530 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3531 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3532 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3533 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3534 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3535 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3536 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3537 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3538 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3539 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3540 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3541 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3542 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3543 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3544 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3545 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3546 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3547 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3548 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3549 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3550 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3551 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3552 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3553 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3554 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3555 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3556 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3557 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3558 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3559 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3560 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3561 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3562 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3563 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3564 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3565 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3566 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3567 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3568 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3569 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3570 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3571 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3572 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3573 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3574 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3575 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3576 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3577 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3578 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3579 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3580 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3581 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3582 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3583 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3584 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3585 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3586 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3587 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3588 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3589 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3590 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3591 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3592 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3593 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3594 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3595 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3596 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3597 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3598 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3599 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3600 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3601 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3602 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3603 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3604 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3605 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3606 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3607 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3608 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3609 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3610 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3611 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3612 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3613 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3614 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3615 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3616 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3617 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3618 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3619 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3620 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3621 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3622 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3623 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
3624 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void,
3625 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long },
3626 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3627 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3628 ~RS6000_BTI_unsigned_V2DI },
3629 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3630 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3631 ~RS6000_BTI_bool_V2DI },
3632 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
3633 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3634 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
3635 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3636 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3637 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3638 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3639 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3640 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3641 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3642 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3643 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3644 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3645 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3646 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3647 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3648 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3649 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3650 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3651 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3652 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3653 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3654 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3655 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3656 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3657 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3658 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3659 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3660 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3661 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3662 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3663 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3664 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3665 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3666 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3667 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3668 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3669 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3670 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3671 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3672 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3673 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3674 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3675 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3676 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3677 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3678 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3679 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3680 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
3681 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3682 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
3683 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3684 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
3685 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI },
3686 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
3687 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI },
3688 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3689 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3690 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3691 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
3692 ~RS6000_BTI_long_long },
3693 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3694 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3695 ~RS6000_BTI_unsigned_V2DI },
3696 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3697 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3698 ~RS6000_BTI_unsigned_long_long },
3699 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3700 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3701 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3702 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3703 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3704 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3705 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3706 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3707 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3708 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3709 ~RS6000_BTI_unsigned_V4SI },
3710 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3711 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3712 ~RS6000_BTI_UINTSI },
3713 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3714 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3715 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3716 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3717 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3718 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3719 ~RS6000_BTI_unsigned_V8HI },
3720 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3721 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3722 ~RS6000_BTI_UINTHI },
3723 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3724 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3725 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3726 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3727 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3728 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3729 ~RS6000_BTI_unsigned_V16QI },
3730 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3731 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3732 ~RS6000_BTI_UINTQI },
3733 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3734 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3735 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3736 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3737 RS6000_BTI_INTSI },
3738 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3739 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3740 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3741 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3742 RS6000_BTI_INTSI },
3743 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3744 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3745 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3746 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3747 RS6000_BTI_INTSI },
3748 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3749 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3750 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3751 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3752 RS6000_BTI_INTSI },
3753 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
3754 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3755 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
3756 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3757
3758 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
3759 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3760 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3761 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3762 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3763 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3764 RS6000_BTI_INTSI },
3765 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
3766 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3767 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3768 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3769 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3770 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3771 RS6000_BTI_INTSI },
3772 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3773 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3774 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3775 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3776 RS6000_BTI_INTSI },
3777 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3778 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3779 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3780 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3781 RS6000_BTI_INTSI },
3782
3783 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3784 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3785 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3786 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3787 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3788 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3789 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3790 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3791 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3792 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3793 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3794 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3795 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3796 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3797 ~RS6000_BTI_unsigned_V2DI, 0 },
3798 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3799 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
3800 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3801 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
3802 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3803 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3804 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3805 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3806 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3807 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
3808 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3809 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3810 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3811 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3812 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3813 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
3814 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3815 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3816 ~RS6000_BTI_unsigned_V4SI, 0 },
3817 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3818 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3819 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3820 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3821 ~RS6000_BTI_unsigned_long, 0 },
3822 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3823 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
3824 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3825 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
3826 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3827 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3828 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3829 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3830 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3831 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3832 ~RS6000_BTI_unsigned_V8HI, 0 },
3833 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3834 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3835 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3836 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
3837 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3838 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3839 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3840 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3841 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3842 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3843 ~RS6000_BTI_unsigned_V16QI, 0 },
3844 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3845 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3846
3847 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
3848 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3849 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
3850 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3851 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3852 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI,
3853 ~RS6000_BTI_long_long },
3854 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3855 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI,
3856 ~RS6000_BTI_unsigned_long_long },
3857 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
3858 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI },
3859 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
3860 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI },
3861 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3862 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3863 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3864 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3865 ~RS6000_BTI_unsigned_V2DI },
3866 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3867 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3868 ~RS6000_BTI_bool_V2DI },
3869 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3870 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3871 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3872 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3873 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3874 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3875 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3876 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3877 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3878 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3879 ~RS6000_BTI_unsigned_V4SI },
3880 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3881 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3882 ~RS6000_BTI_UINTSI },
3883 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3884 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3885 ~RS6000_BTI_bool_V4SI },
3886 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3887 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3888 ~RS6000_BTI_UINTSI },
3889 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3890 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3891 ~RS6000_BTI_INTSI },
3892 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3893 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3894 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3895 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3896 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3897 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3898 ~RS6000_BTI_unsigned_V8HI },
3899 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3900 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3901 ~RS6000_BTI_UINTHI },
3902 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3903 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3904 ~RS6000_BTI_bool_V8HI },
3905 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3906 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3907 ~RS6000_BTI_UINTHI },
3908 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3909 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3910 ~RS6000_BTI_INTHI },
3911 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3912 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3913 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3914 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3915 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3916 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3917 ~RS6000_BTI_unsigned_V16QI },
3918 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3919 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3920 ~RS6000_BTI_UINTQI },
3921 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3922 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3923 ~RS6000_BTI_bool_V16QI },
3924 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3925 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3926 ~RS6000_BTI_UINTQI },
3927 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3928 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3929 ~RS6000_BTI_INTQI },
3930 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3931 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
3932 ~RS6000_BTI_pixel_V8HI },
3933
3934 /* Predicates. */
3935 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
3936 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3937 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
3938 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3939 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
3940 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3941 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
3942 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
3943 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
3944 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3945 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
3946 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3947 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
3948 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3949 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
3950 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3951 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
3952 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3953 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
3954 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3955 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
3956 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
3957 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
3958 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3959 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
3960 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3961 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
3962 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3963 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
3964 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3965 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
3966 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
3967 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
3968 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3969 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
3970 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
3971 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
3972 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
3973 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
3974 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3975 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
3976 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3977 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
3978 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
3979 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
3980 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3981 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
3982 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3983 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
3984 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3985 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
3986 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3987
3988
3989 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
3990 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3991 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
3992 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3993 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
3994 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3995 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
3996 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
3997 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
3998 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3999 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4000 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4001 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4002 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4003 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4004 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4005 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4006 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4007 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4008 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4009 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4010 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4011 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4012 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4013 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4014 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4015 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4016 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4017 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4018 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4019 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4020 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4021 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4022 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4023 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4024 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4025 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4026 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4027 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4028 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4029 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4030 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4031 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4032 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4033 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4034 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4035 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4036 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4037 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4038 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4039 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4040 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4041 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4042 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4043 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4044 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4045 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4046 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4047 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4048 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4049 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4050 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4051
4052
4053 /* cmpge is the same as cmpgt for all cases except floating point.
4054 There is further code to deal with this special case in
4055 altivec_build_resolved_builtin. */
4056 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4057 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4058 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4059 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4060 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4061 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4062 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4063 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4064 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4065 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4066 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4067 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4068 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4069 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4070 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4071 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4072 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4073 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4074 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4075 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4076 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4077 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4078 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4079 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4080 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4081 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4082 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4083 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4084 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4085 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4086 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4087 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4088 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4089 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4090 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4091 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4092 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4093 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4094 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4095 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4096 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4097 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4098 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4099 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4100 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4101 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4102 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4103 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4104 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4105 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4106 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4107 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4108
4109 /* Power8 vector overloaded functions. */
4110 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4111 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4112 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4113 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4114 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4115 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 4116 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3 4117 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 4118 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3
PB		 4119 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4120 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4121 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3
PB		 4122 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4123 RS6000_BTI_bool_V16QI, 0 },
4559be23 4124 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3
PB		 4125 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4126 RS6000_BTI_unsigned_V16QI, 0 },
4127 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4128 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4129 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4130 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4131 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4132 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 4133 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3 4134 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 4135 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3
PB		 4136 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4137 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4138 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3
PB		 4139 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4140 RS6000_BTI_bool_V8HI, 0 },
4559be23 4141 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3
PB		 4142 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4143 RS6000_BTI_unsigned_V8HI, 0 },
4144 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4145 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4146 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4147 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4148 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4149 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 4150 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3 4151 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 4152 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3
PB		 4153 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4154 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4155 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3
PB		 4156 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4157 RS6000_BTI_bool_V4SI, 0 },
4559be23 4158 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3
PB		 4159 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4160 RS6000_BTI_unsigned_V4SI, 0 },
4161 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4162 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4163 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4164 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4165 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4166 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 4167 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3 4168 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 4169 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3
PB		 4170 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4171 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4172 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3
PB		 4173 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4174 RS6000_BTI_bool_V2DI, 0 },
4559be23 4175 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3
PB		 4176 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4177 RS6000_BTI_unsigned_V2DI, 0 },
4178 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4179 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4180 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4181 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4182
4183 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4184 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4185 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4186 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4187 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4188 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 4189 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4190 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4191 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4192 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4193 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4194 RS6000_BTI_bool_V16QI, 0 },
4559be23 4195 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4196 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4197 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4198 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4199 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4200 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4201 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4202 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4203 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4204 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4205 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 4206 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4207 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4208 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4209 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4210 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4211 RS6000_BTI_bool_V8HI, 0 },
4559be23 4212 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4213 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4214 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4215 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4216 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4217 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4218 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4219 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4220 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4221 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4222 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 4223 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4224 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4225 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4226 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4227 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4228 RS6000_BTI_bool_V4SI, 0 },
4559be23 4229 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4230 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4231 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4232 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4233 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4234 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4235 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4236 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4237 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4238 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4239 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 4240 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4241 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4242 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4243 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4244 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4245 RS6000_BTI_bool_V2DI, 0 },
4559be23 4246 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4247 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4248 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4249 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4250 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4251 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4252 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4253 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4254 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4255
4256 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4257 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4258 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4259 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4260 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4261 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 4262 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4263 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4264 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4265 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4266 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4267 RS6000_BTI_bool_V16QI, 0 },
4559be23 4268 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4269 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4270 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4271 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4272 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4273 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4274 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4275 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4276 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4277 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4278 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 4279 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4280 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4281 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4282 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4283 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4284 RS6000_BTI_bool_V8HI, 0 },
4559be23 4285 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4286 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4287 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4288 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4289 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4290 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4291 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4292 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4293 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4294 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4295 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 4296 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4297 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4298 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4299 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4300 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4301 RS6000_BTI_bool_V4SI, 0 },
4559be23 4302 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4303 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4304 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4305 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4306 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4307 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4308 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4309 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4310 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4311 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4312 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 4313 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4314 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4315 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4316 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4317 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4318 RS6000_BTI_bool_V2DI, 0 },
4559be23 4319 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4320 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4321 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4322 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4323 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4324 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4325 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4326 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4327 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4328
4329 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4330 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4331 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4332 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4333 RS6000_BTI_unsigned_V1TI, 0 },
4334
4335 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4336 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4337 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4338 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4339 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4340 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4341 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4342 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4343 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4344 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4345 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4346 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4347
4348 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4349 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4350 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4351 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4352 RS6000_BTI_unsigned_V1TI, 0 },
4353
4354 { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4355 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4356 RS6000_BTI_unsigned_V16QI, 0 },
4357 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4358 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4359 RS6000_BTI_unsigned_V16QI, 0 },
4360 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4361 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4362 RS6000_BTI_unsigned_V16QI, 0 },
4363
4364 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4365 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4366 RS6000_BTI_unsigned_V16QI, 0 },
4367 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4368 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4369 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4370 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4371 RS6000_BTI_unsigned_V16QI, 0 },
4372 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4373 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4374 RS6000_BTI_unsigned_V16QI, 0 },
4375
4376 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4377 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4378 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4379 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4380 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4381 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4382 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4383 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4384 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4385 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4386 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4387 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4388 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4389 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4390 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4391 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4392
4393 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4394 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4395 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4396 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4397
4398 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4399 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4400 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4401 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4402
4403 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4404 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4405 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4406 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4407
4408 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4409 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4410 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4411 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4412
4413 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4414 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4415 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4416 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4417
4418 { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4419 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4420 { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4421 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4422
4423 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4424 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4425 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4426 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4427
4428 { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4429 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4430 { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4431 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4432
4433 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4434 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4435 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4436 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4437
4438 { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4439 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4440 { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4441 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4442
4443 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4444 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4445 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4446 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4447
4448 { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4449 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4450 { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4451 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4452
4453 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4454 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4455 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4456 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4457 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4458 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4459 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4460 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4461 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4462 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4463 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4464 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4465 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4466 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4467 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4468 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4469
4470 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4471 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4472 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4473 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4474
4475 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4476 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4477 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4478 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4479
4480 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4481 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4482 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4483 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4484
4485 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4486 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4487 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4488 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4489
4490 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4491 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4492 RS6000_BTI_unsigned_V16QI, 0 },
4493 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4494 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4495 RS6000_BTI_unsigned_V8HI, 0 },
4496 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4497 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4498 RS6000_BTI_unsigned_V4SI, 0 },
4499
4500 { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4501 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4502 RS6000_BTI_unsigned_V16QI, 0 },
4503
4504 { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4505 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4506 RS6000_BTI_unsigned_V8HI, 0 },
4507
4508 { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
4509 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4510 RS6000_BTI_unsigned_V4SI, 0 },
4511
4512 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
4513 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4514 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
4515 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4516
4517 { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
4518 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4519 { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
4520 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4521
4522 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
4523 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4524 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
4525 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4526
4527 { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
4528 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4529 { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
4530 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4531
4532 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
4533 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4534 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
4535 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4536
4537 { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
4538 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4539 { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
4540 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4541
4542 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4543 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4544 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4545 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4546
4547 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4548 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4549 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4550 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4551
4552 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4553 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4554 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4555 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4556
4557 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4558 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4560 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4561
4562 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
4563 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4564 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
4565 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4566 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP,
4567 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4568
4569 { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
4570 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4571 { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
4572 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4573 { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP,
4574 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4575
4576 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
4577 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4578 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
4579 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4580 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP,
4581 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4582
4583 { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
4584 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4585 { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
4586 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4587 { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP,
4588 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4589
4590 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
4591 RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
4592 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP,
4593 RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 },
4594
4595 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
4596 RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
4597 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP,
4598 RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 },
4599
4600 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
4601 RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
4602 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
4603 RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
4604
4605 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP,
4606 RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 },
4607 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
4608 RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
4609
4610 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT,
4611 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4612 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT,
4613 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4614 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT,
4615 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4616 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT,
4617 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4618 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ,
4619 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4620 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ,
4621 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4622 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO,
4623 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4624 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO,
4625 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4626
4627 { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
4628 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4629 RS6000_BTI_unsigned_long_long, 0 },
4630
4631 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4632 RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4633 RS6000_BTI_unsigned_long_long, 0 },
4634 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4635 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4636 RS6000_BTI_unsigned_long_long, 0 },
4637
4638 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4639 RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4640 RS6000_BTI_unsigned_long_long, 0 },
4641 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4642 RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4643 RS6000_BTI_unsigned_long_long, 0 },
4644
4645 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4646 RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4647 RS6000_BTI_unsigned_long_long, 0 },
4648 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4649 RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4650 RS6000_BTI_unsigned_long_long, 0 },
4651
4652 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4653 RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4654 RS6000_BTI_unsigned_long_long, 0 },
4655 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4656 RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4657 RS6000_BTI_unsigned_long_long, 0 },
4658
4659 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4660 RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4661 RS6000_BTI_unsigned_long_long, 0 },
4662 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4663 RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4664 RS6000_BTI_unsigned_long_long, 0 },
4665
4666 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4667 RS6000_BTI_V2DF, ~RS6000_BTI_double,
4668 RS6000_BTI_unsigned_long_long, 0 },
4669 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4670 RS6000_BTI_V4SF, ~RS6000_BTI_float,
4671 RS6000_BTI_unsigned_long_long, 0 },
4672 /* At an appropriate future time, add support for the
4673 RS6000_BTI_Float16 (exact name to be determined) type here. */
4674
4675 { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,
4676 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,
4677 ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},
4678
4679 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4680 RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4681 RS6000_BTI_unsigned_long_long },
4682 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4683 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4684 RS6000_BTI_unsigned_long_long },
4685
4686 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4687 RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4688 RS6000_BTI_unsigned_long_long },
4689 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4690 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4691 RS6000_BTI_unsigned_long_long },
4692
4693 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4694 RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4695 RS6000_BTI_unsigned_long_long },
4696 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4697 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4698 RS6000_BTI_unsigned_long_long },
4699
4700 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4701 RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4702 RS6000_BTI_unsigned_long_long },
4703 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4704 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4705 RS6000_BTI_unsigned_long_long },
4706
4707 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4708 RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4709 RS6000_BTI_unsigned_long_long },
4710 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4711 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4712 RS6000_BTI_unsigned_long_long },
4713
4714 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4715 RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
4716 RS6000_BTI_unsigned_long_long },
4717 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4718 RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
4719 RS6000_BTI_unsigned_long_long },
4720 /* At an appropriate future time, add support for the
4721 RS6000_BTI_Float16 (exact name to be determined) type here. */
4722
4723 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4724 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
4725 RS6000_BTI_bool_V16QI, 0 },
4726 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4727 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4728 RS6000_BTI_V16QI, 0 },
4729 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4730 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
4731 RS6000_BTI_unsigned_V16QI, 0 },
4732
4733 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4734 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
4735 RS6000_BTI_bool_V8HI, 0 },
4736 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4737 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
4738 RS6000_BTI_V8HI, 0 },
4739 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4740 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
4741 RS6000_BTI_unsigned_V8HI, 0 },
4742
4743 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4744 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
4745 RS6000_BTI_bool_V4SI, 0 },
4746 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4747 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
4748 RS6000_BTI_V4SI, 0 },
4749 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4750 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
4751 RS6000_BTI_unsigned_V4SI, 0 },
4752
4753 /* The following 2 entries have been deprecated. */
4754 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4755 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4756 RS6000_BTI_unsigned_V16QI, 0 },
4757 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4758 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4759 RS6000_BTI_bool_V16QI, 0 },
4760 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4761 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4762 RS6000_BTI_unsigned_V16QI, 0 },
4763
4764 /* The following 2 entries have been deprecated. */
4765 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4766 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4767 RS6000_BTI_V16QI, 0 },
4768 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4769 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4770 RS6000_BTI_bool_V16QI, 0 },
4771 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4772 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4773 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4774 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4775 RS6000_BTI_bool_V16QI, 0 },
4776
4777 /* The following 2 entries have been deprecated. */
4778 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4779 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4780 RS6000_BTI_unsigned_V8HI, 0 },
4781 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4782 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4783 RS6000_BTI_bool_V8HI, 0 },
4784 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4785 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4786 RS6000_BTI_unsigned_V8HI, 0 },
4787 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4788 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4789
4790 /* The following 2 entries have been deprecated. */
4791 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4792 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4793 RS6000_BTI_V8HI, 0 },
4794 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4795 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4796 RS6000_BTI_bool_V8HI, 0 },
4797 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4798 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4799 RS6000_BTI_bool_V8HI, 0 },
4800 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4801 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4802 RS6000_BTI_pixel_V8HI, 0 },
4803
4804 /* The following 2 entries have been deprecated. */
4805 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4806 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4807 RS6000_BTI_unsigned_V4SI, 0 },
4808 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4809 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4810 RS6000_BTI_bool_V4SI, 0 },
4811 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4812 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4813 RS6000_BTI_unsigned_V4SI, 0 },
4814
4815 /* The following 2 entries have been deprecated. */
4816 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4817 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4818 RS6000_BTI_V4SI, 0 },
4819 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4820 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4821 RS6000_BTI_bool_V4SI, 0 },
4822 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4823 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4824 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4825 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4826 RS6000_BTI_bool_V4SI, 0 },
4827
4828 /* The following 2 entries have been deprecated. */
4829 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4830 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4831 RS6000_BTI_unsigned_V2DI, 0 },
4832 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4833 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4834 RS6000_BTI_bool_V2DI, 0 },
4835 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4836 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4837 RS6000_BTI_unsigned_V2DI, 0
4838 },
4839
4840 /* The following 2 entries have been deprecated. */
4841 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4842 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4843 RS6000_BTI_V2DI, 0 },
4844 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4845 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
4846 RS6000_BTI_bool_V2DI, 0 },
4847 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4848 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4849 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4850 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4851 RS6000_BTI_bool_V2DI, 0 },
4852
4853 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
4854 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4855 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
4856 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4857
4858 /* The following 2 entries have been deprecated. */
4859 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4860 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4861 RS6000_BTI_unsigned_V16QI, 0 },
4862 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4863 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4864 RS6000_BTI_bool_V16QI, 0 },
4865 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4866 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4867 RS6000_BTI_unsigned_V16QI, 0 },
4868
4869 /* The following 2 entries have been deprecated. */
4870 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4871 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4872 RS6000_BTI_V16QI, 0 },
4873 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4874 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4875 RS6000_BTI_bool_V16QI, 0 },
4876 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4877 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4878 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4879 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4880 RS6000_BTI_bool_V16QI, 0 },
4881
4882 /* The following 2 entries have been deprecated. */
4883 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4884 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4885 RS6000_BTI_unsigned_V8HI, 0 },
4886 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4887 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4888 RS6000_BTI_bool_V8HI, 0 },
4889 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4890 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4891 RS6000_BTI_unsigned_V8HI, 0 },
4892 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4893 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4894
4895 /* The following 2 entries have been deprecated. */
4896 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4897 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4898 RS6000_BTI_V8HI, 0 },
4899 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4900 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4901 RS6000_BTI_bool_V8HI, 0 },
4902 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4903 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4904 RS6000_BTI_bool_V8HI, 0 },
4905 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4906 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4907 RS6000_BTI_pixel_V8HI, 0 },
4908
4909 /* The following 2 entries have been deprecated. */
4910 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4911 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4912 RS6000_BTI_unsigned_V4SI, 0 },
4913 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4914 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4915 RS6000_BTI_bool_V4SI, 0 },
4916 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4917 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4918 RS6000_BTI_unsigned_V4SI, 0 },
4919
4920 /* The following 2 entries have been deprecated. */
4921 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4922 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4923 RS6000_BTI_V4SI, 0 },
4924 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4925 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4926 RS6000_BTI_bool_V4SI, 0 },
4927 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4928 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4929 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4930 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4931 RS6000_BTI_bool_V4SI, 0 },
4932
4933 /* The following 2 entries have been deprecated. */
4934 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4935 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4936 RS6000_BTI_unsigned_V2DI, 0 },
4937 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4938 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4939 RS6000_BTI_bool_V2DI, 0 },
4940 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4941 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4942 RS6000_BTI_unsigned_V2DI, 0
4943 },
4944
4945 /* The following 2 entries have been deprecated. */
4946 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4947 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4948 RS6000_BTI_V2DI, 0 },
4949 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4950 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
4951 RS6000_BTI_bool_V2DI, 0 },
4952 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4953 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4954 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4955 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4956 RS6000_BTI_bool_V2DI, 0 },
4957
4958 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
4959 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4960 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
4961 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4962
4963 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
4964 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4965 RS6000_BTI_unsigned_V16QI },
4966 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
4967 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4968
4969 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
4970 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4971 RS6000_BTI_unsigned_V8HI },
4972 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
4973 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4974
4975 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
4976 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4977 RS6000_BTI_unsigned_V4SI },
4978 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
4979 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4980
4981 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
4982 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4983 RS6000_BTI_V16QI, 0 },
4984 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
4985 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
4986 RS6000_BTI_unsigned_V16QI, 0 },
4987
4988 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
4989 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
4990 RS6000_BTI_V8HI, 0 },
4991 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
4992 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
4993 RS6000_BTI_unsigned_V8HI, 0 },
4994
4995 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
4996 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
4997 RS6000_BTI_V4SI, 0 },
4998 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
4999 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5000 RS6000_BTI_unsigned_V4SI, 0 },
5001
5002 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5003 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5004 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5005 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5006
5007 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5008 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5009 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5010 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5011 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI,
5012 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5013 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI,
5014 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 },
5015
5016 { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
5017 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
5018
5019 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5020 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5021 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5022 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5023
5024 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5025 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5026 RS6000_BTI_V16QI, 0 },
5027 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5028 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5029 RS6000_BTI_unsigned_V16QI, 0 },
5030
5031 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5032 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5033 RS6000_BTI_V8HI, 0 },
5034 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5035 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5036 RS6000_BTI_unsigned_V8HI, 0 },
5037
5038 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5039 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5040 RS6000_BTI_V4SI, 0 },
5041 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5042 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5043 RS6000_BTI_unsigned_V4SI, 0 },
5044 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5045 RS6000_BTI_float, RS6000_BTI_UINTSI,
5046 RS6000_BTI_V4SF, 0 },
5047
5048 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5049 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5050 RS6000_BTI_V16QI, 0 },
5051 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5052 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5053 RS6000_BTI_unsigned_V16QI, 0 },
5054
5055 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5056 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5057 RS6000_BTI_V8HI, 0 },
5058 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5059 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5060 RS6000_BTI_unsigned_V8HI, 0 },
5061
5062 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5063 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5064 RS6000_BTI_V4SI, 0 },
5065 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5066 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5067 RS6000_BTI_unsigned_V4SI, 0 },
5068 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5069 RS6000_BTI_float, RS6000_BTI_UINTSI,
5070 RS6000_BTI_V4SF, 0 },
5071
5072 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5073 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5074 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5075 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5076
5077 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5078 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI,
5079 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5080 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5081 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5082 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5083
5084 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5085 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5086 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5087 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5088 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5089
5090 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5091 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5092 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5093 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5094 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5095
5096 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5097 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5098 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5099 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5100 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5101
5102 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5103 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5104 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5105 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5106 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5107
5108 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5109 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5110 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5111 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5112 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5113 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5114
5115 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5116 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5117 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5118 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5119 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5120 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5121
5122 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5123 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5124 RS6000_BTI_unsigned_V2DI, 0 },
5125 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5126 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5127 RS6000_BTI_bool_V2DI, 0 },
5128 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5129 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5130 RS6000_BTI_unsigned_V2DI, 0 },
5131
5132 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5133 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5134 RS6000_BTI_unsigned_V2DI, 0 },
5135 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5136 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5137 RS6000_BTI_bool_V2DI, 0 },
5138 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5139 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5140 RS6000_BTI_unsigned_V2DI, 0 },
5141
5142 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5143 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5144 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5145 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5146 RS6000_BTI_unsigned_V2DI, 0 },
5147 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5148 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5149 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF,
5150 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5151 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF,
5152 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5153 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5154 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5155 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5156 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5157 RS6000_BTI_unsigned_V4SI, 0 },
5158 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5159 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5160
5161 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5162 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5163 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5164 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5165 RS6000_BTI_unsigned_V4SI, 0 },
5166 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5167 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5168 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5169 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5170 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5171 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5172 RS6000_BTI_unsigned_V2DI, 0 },
5173 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5174 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5175 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF,
5176 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5177 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF,
5178 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5179
5180 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5181 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5182 RS6000_BTI_unsigned_V16QI, 0 },
5183 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5184 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5185 RS6000_BTI_unsigned_V8HI, 0 },
5186 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5187 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5188 RS6000_BTI_unsigned_V4SI, 0 },
5189 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5190 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5191 RS6000_BTI_unsigned_V2DI, 0 },
5192
5193 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5194 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5195 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5196 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5197 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5198 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5199 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5200 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5201 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5202 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5203 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5204 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5205 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5206 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5207 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5208 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5209
5210 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5211 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5212 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5213 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5214
5215 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5216 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5217 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5218 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5219
5220 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5221 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5222 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5223 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5224
5225 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5226 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5227 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5228 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5229
5230 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5231 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5232 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5233 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5234
5235 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5236 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5237 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5238 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5239
5240 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5241 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5242 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5243 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5244
5245 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5246 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5247 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5248 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5249
5250 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5251 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5252 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5253 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5254 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5255 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5256 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5257 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5258 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5259 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5260 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5261 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5262 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5263 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5264 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5265 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5266
5267 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5268 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5269 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5270 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5271
5272 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5273 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5274 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5275 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5276
5277 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5278 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5279 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5280 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5281 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5282 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5283 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5284 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5285
5286 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5287 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5288 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5289 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5290 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5291 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5292 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5293 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5294 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5295 RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
5296 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5297 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5298
5299 { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5300 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5301 { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5302 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5303 { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5304 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5305
5306 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5307 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5308 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5309 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5310 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5311 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5312
5313 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5314 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5315
5316 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5317 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5318
5319 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5320 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5321
5322 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5323 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5324 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5325 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5326
5327 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5328 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5329 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5330 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5331
5332 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5333 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5334 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5335 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5336
5337 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5338 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5339 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5340 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5341
5342 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5343 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5344 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5345 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5346 RS6000_BTI_unsigned_V1TI, 0 },
5347
5348 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5349 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5350 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5351 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5352 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5353 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5354 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5355 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5356 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5357 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5358 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5359 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5360
5361 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5362 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5363 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5364 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5365 RS6000_BTI_unsigned_V1TI, 0 },
5366
5367 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5368 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5369 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5370 RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5371
5372 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5373 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5374 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5375 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5376
5377 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5378 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5379 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5380 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5381
5382 { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5383 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5384 RS6000_BTI_unsigned_V16QI, 0 },
5385 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5386 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5387 RS6000_BTI_unsigned_V16QI, 0 },
5388
5389 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5390 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5391 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5392 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5393 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5394 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5395 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5396 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5397 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5398 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5399 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5400 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5401 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5402 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5403 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5404 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5405 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5406 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5407 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5408 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5409 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5410 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5411 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5412 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5413 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5414 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5415 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5416 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5417 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF,
5418 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5419 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF,
5420 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5421
5422 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5423 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5424 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5425 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5426 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5427 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5428 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5429 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5430 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5431 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5432 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5433 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5434 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5435 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5436 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5437 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5438 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
5439 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5440 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
5441 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5442 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5443 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5444 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5445 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5446 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5447 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5448 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5449 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5450
5451 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF,
5452 RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 },
5453 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF,
5454 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5455 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5456 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5457 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5458 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5459 { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF,
5460 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5461
5462 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5463 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5464 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5465 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5466 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5467 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5468 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5469 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5470 { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF,
5471 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5472 RS6000_BTI_V2DF, 0 },
5473
5474 /* Crypto builtins. */
5475 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5476 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5477 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5478 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5479 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5480 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5481 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5482 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5483 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5484 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5485 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5486 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5487
5488 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5489 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5490 RS6000_BTI_unsigned_V16QI, 0 },
5491 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5492 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5493 RS6000_BTI_unsigned_V8HI, 0 },
5494 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5495 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5496 RS6000_BTI_unsigned_V4SI, 0 },
5497 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5498 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5499 RS6000_BTI_unsigned_V2DI, 0 },
5500
5501 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5502 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5503 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5504 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5505 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5506 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5507
5508 { RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
5509};
1acf0246
BS		 5510\f
5511/* Nonzero if we can use a floating-point register to pass this arg. */
5512#define USE_FP_FOR_ARG_P(CUM,MODE) \
5513 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
5514 && (CUM)->fregno <= FP_ARG_MAX_REG \
5515 && TARGET_HARD_FLOAT)
5516
5517/* Nonzero if we can use an AltiVec register to pass this arg. */
5518#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
5519 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
5520 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5521 && TARGET_ALTIVEC_ABI \
5522 && (NAMED))
5523
5524/* Walk down the type tree of TYPE counting consecutive base elements.
5525 If *MODEP is VOIDmode, then set it to the first valid floating point
5526 or vector type. If a non-floating point or vector type is found, or
5527 if a floating point or vector type that doesn't match a non-VOIDmode
5528 *MODEP is found, then return -1, otherwise return the count in the
5529 sub-tree. */
5530
5531static int
a39ed81b 5532rs6000_aggregate_candidate (const_tree type, machine_mode *modep,
575ac27f 5533 int *empty_base_seen)
1acf0246
BS		 5534{
5535 machine_mode mode;
5536 HOST_WIDE_INT size;
5537
5538 switch (TREE_CODE (type))
5539 {
5540 case REAL_TYPE:
5541 mode = TYPE_MODE (type);
5542 if (!SCALAR_FLOAT_MODE_P (mode))
5543 return -1;
5544
5545 if (*modep == VOIDmode)
5546 *modep = mode;
5547
5548 if (*modep == mode)
5549 return 1;
5550
5551 break;
5552
5553 case COMPLEX_TYPE:
5554 mode = TYPE_MODE (TREE_TYPE (type));
5555 if (!SCALAR_FLOAT_MODE_P (mode))
5556 return -1;
5557
5558 if (*modep == VOIDmode)
5559 *modep = mode;
5560
5561 if (*modep == mode)
5562 return 2;
5563
5564 break;
5565
5566 case VECTOR_TYPE:
5567 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
5568 return -1;
5569
5570 /* Use V4SImode as representative of all 128-bit vector types. */
5571 size = int_size_in_bytes (type);
5572 switch (size)
5573 {
5574 case 16:
5575 mode = V4SImode;
5576 break;
5577 default:
5578 return -1;
5579 }
5580
5581 if (*modep == VOIDmode)
5582 *modep = mode;
5583
5584 /* Vector modes are considered to be opaque: two vectors are
5585 equivalent for the purposes of being homogeneous aggregates
5586 if they are the same size. */
5587 if (*modep == mode)
5588 return 1;
5589
5590 break;
5591
5592 case ARRAY_TYPE:
5593 {
5594 int count;
5595 tree index = TYPE_DOMAIN (type);
5596
5597 /* Can't handle incomplete types nor sizes that are not
5598 fixed. */
5599 if (!COMPLETE_TYPE_P (type)
5600 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
5601 return -1;
5602
a39ed81b 5603 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep,
575ac27f 5604 empty_base_seen);
1acf0246
BS		 5605 if (count == -1
5606 || !index
5607 || !TYPE_MAX_VALUE (index)
5608 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
5609 || !TYPE_MIN_VALUE (index)
5610 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
5611 || count < 0)
5612 return -1;
5613
5614 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
5615 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
5616
5617 /* There must be no padding. */
5618 if (wi::to_wide (TYPE_SIZE (type))
5619 != count * GET_MODE_BITSIZE (*modep))
5620 return -1;
5621
5622 return count;
5623 }
5624
5625 case RECORD_TYPE:
5626 {
5627 int count = 0;
5628 int sub_count;
5629 tree field;
5630
5631 /* Can't handle incomplete types nor sizes that are not
5632 fixed. */
5633 if (!COMPLETE_TYPE_P (type)
5634 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
5635 return -1;
5636
5637 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5638 {
5639 if (TREE_CODE (field) != FIELD_DECL)
5640 continue;
5641
575ac27f 5642 if (DECL_FIELD_ABI_IGNORED (field))
a39ed81b 5643 {
575ac27f
JJ		 5644 if (lookup_attribute ("no_unique_address",
5645 DECL_ATTRIBUTES (field)))
5646 *empty_base_seen |= 2;
5647 else
5648 *empty_base_seen |= 1;
a39ed81b
JJ		 5649 continue;
5650 }
5651
5652 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep,
575ac27f 5653 empty_base_seen);
1acf0246
BS		 5654 if (sub_count < 0)
5655 return -1;
5656 count += sub_count;
5657 }
5658
5659 /* There must be no padding. */
5660 if (wi::to_wide (TYPE_SIZE (type))
5661 != count * GET_MODE_BITSIZE (*modep))
5662 return -1;
5663
5664 return count;
5665 }
5666
5667 case UNION_TYPE:
5668 case QUAL_UNION_TYPE:
5669 {
5670 /* These aren't very interesting except in a degenerate case. */
5671 int count = 0;
5672 int sub_count;
5673 tree field;
5674
5675 /* Can't handle incomplete types nor sizes that are not
5676 fixed. */
5677 if (!COMPLETE_TYPE_P (type)
5678 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
5679 return -1;
5680
5681 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5682 {
5683 if (TREE_CODE (field) != FIELD_DECL)
5684 continue;
5685
a39ed81b 5686 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep,
575ac27f 5687 empty_base_seen);
1acf0246
BS		 5688 if (sub_count < 0)
5689 return -1;
5690 count = count > sub_count ? count : sub_count;
5691 }
5692
5693 /* There must be no padding. */
5694 if (wi::to_wide (TYPE_SIZE (type))
5695 != count * GET_MODE_BITSIZE (*modep))
5696 return -1;
5697
5698 return count;
5699 }
5700
5701 default:
5702 break;
5703 }
5704
5705 return -1;
5706}
5707
5708/* If an argument, whose type is described by TYPE and MODE, is a homogeneous
5709 float or vector aggregate that shall be passed in FP/vector registers
5710 according to the ELFv2 ABI, return the homogeneous element mode in
5711 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
5712
5713 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
5714
5715bool
5716rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
5717 machine_mode *elt_mode,
5718 int *n_elts)
5719{
5720 /* Note that we do not accept complex types at the top level as
5721 homogeneous aggregates; these types are handled via the
5722 targetm.calls.split_complex_arg mechanism. Complex types
5723 can be elements of homogeneous aggregates, however. */
5724 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
5725 && AGGREGATE_TYPE_P (type))
5726 {
5727 machine_mode field_mode = VOIDmode;
575ac27f 5728 int empty_base_seen = 0;
a39ed81b 5729 int field_count = rs6000_aggregate_candidate (type, &field_mode,
575ac27f 5730 &empty_base_seen);
1acf0246
BS		 5731
5732 if (field_count > 0)
5733 {
5734 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
5735 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
5736
5737 /* The ELFv2 ABI allows homogeneous aggregates to occupy
5738 up to AGGR_ARG_NUM_REG registers. */
5739 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
5740 {
5741 if (elt_mode)
5742 *elt_mode = field_mode;
5743 if (n_elts)
5744 *n_elts = field_count;
575ac27f 5745 if (empty_base_seen && warn_psabi)
a39ed81b 5746 {
239cfd92
JJ		 5747 static unsigned last_reported_type_uid;
5748 unsigned uid = TYPE_UID (TYPE_MAIN_VARIANT (type));
5749 if (uid != last_reported_type_uid)
a39ed81b 5750 {
691eeb65
JJ		 5751 char *url
5752 = get_changes_url ("gcc-10/changes.html#empty_base");
575ac27f
JJ		 5753 if (empty_base_seen & 1)
5754 inform (input_location,
5755 "parameter passing for argument of type %qT "
5756 "when C++17 is enabled changed to match C++14 "
691eeb65 5757 "%{in GCC 10.1%}", type, url);
575ac27f
JJ		 5758 else
5759 inform (input_location,
5760 "parameter passing for argument of type %qT "
5761 "with %<[[no_unique_address]]%> members "
691eeb65 5762 "changed %{in GCC 10.1%}", type, url);
239cfd92 5763 last_reported_type_uid = uid;
691eeb65 5764 free (url);
a39ed81b
JJ		 5765 }
5766 }
1acf0246
BS		 5767 return true;
5768 }
5769 }
5770 }
5771
5772 if (elt_mode)
5773 *elt_mode = mode;
5774 if (n_elts)
5775 *n_elts = 1;
5776 return false;
5777}
5778
5779/* Return a nonzero value to say to return the function value in
5780 memory, just as large structures are always returned. TYPE will be
5781 the data type of the value, and FNTYPE will be the type of the
5782 function doing the returning, or @code{NULL} for libcalls.
5783
5784 The AIX ABI for the RS/6000 specifies that all structures are
5785 returned in memory. The Darwin ABI does the same.
5786
5787 For the Darwin 64 Bit ABI, a function result can be returned in
5788 registers or in memory, depending on the size of the return data
5789 type. If it is returned in registers, the value occupies the same
5790 registers as it would if it were the first and only function
5791 argument. Otherwise, the function places its result in memory at
5792 the location pointed to by GPR3.
5793
5794 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
5795 but a draft put them in memory, and GCC used to implement the draft
5796 instead of the final standard. Therefore, aix_struct_return
5797 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5798 compatibility can change DRAFT_V4_STRUCT_RET to override the
5799 default, and -m switches get the final word. See
5800 rs6000_option_override_internal for more details.
5801
5802 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5803 long double support is enabled. These values are returned in memory.
5804
5805 int_size_in_bytes returns -1 for variable size objects, which go in
5806 memory always. The cast to unsigned makes -1 > 8. */
5807
5808bool
5809rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5810{
5811 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
5812 if (TARGET_MACHO
5813 && rs6000_darwin64_abi
5814 && TREE_CODE (type) == RECORD_TYPE
5815 && int_size_in_bytes (type) > 0)
5816 {
5817 CUMULATIVE_ARGS valcum;
5818 rtx valret;
5819
5820 valcum.words = 0;
5821 valcum.fregno = FP_ARG_MIN_REG;
5822 valcum.vregno = ALTIVEC_ARG_MIN_REG;
5823 /* Do a trial code generation as if this were going to be passed
5824 as an argument; if any part goes in memory, we return NULL. */
5825 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
5826 if (valret)
5827 return false;
5828 /* Otherwise fall through to more conventional ABI rules. */
5829 }
5830
5831 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
5832 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
5833 NULL, NULL))
5834 return false;
5835
5836 /* The ELFv2 ABI returns aggregates up to 16B in registers */
5837 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
5838 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
5839 return false;
5840
5841 if (AGGREGATE_TYPE_P (type)
5842 && (aix_struct_return
5843 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
5844 return true;
5845
5846 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5847 modes only exist for GCC vector types if -maltivec. */
5848 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
5849 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5850 return false;
5851
5852 /* Return synthetic vectors in memory. */
5853 if (TREE_CODE (type) == VECTOR_TYPE
5854 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5855 {
5856 static bool warned_for_return_big_vectors = false;
5857 if (!warned_for_return_big_vectors)
5858 {
5859 warning (OPT_Wpsabi, "GCC vector returned by reference: "
5860 "non-standard ABI extension with no compatibility "
5861 "guarantee");
5862 warned_for_return_big_vectors = true;
5863 }
5864 return true;
5865 }
5866
5867 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
5868 && FLOAT128_IEEE_P (TYPE_MODE (type)))
5869 return true;
5870
5871 return false;
5872}
5873
5874/* Specify whether values returned in registers should be at the most
5875 significant end of a register. We want aggregates returned by
5876 value to match the way aggregates are passed to functions. */
5877
5878bool
5879rs6000_return_in_msb (const_tree valtype)
5880{
5881 return (DEFAULT_ABI == ABI_ELFv2
5882 && BYTES_BIG_ENDIAN
5883 && AGGREGATE_TYPE_P (valtype)
5884 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
5885 == PAD_UPWARD));
5886}
5887
5888#ifdef HAVE_AS_GNU_ATTRIBUTE
5889/* Return TRUE if a call to function FNDECL may be one that
5890 potentially affects the function calling ABI of the object file. */
5891
5892static bool
5893call_ABI_of_interest (tree fndecl)
5894{
5895 if (rs6000_gnu_attr && symtab->state == EXPANSION)
5896 {
5897 struct cgraph_node *c_node;
5898
5899 /* Libcalls are always interesting. */
5900 if (fndecl == NULL_TREE)
5901 return true;
5902
5903 /* Any call to an external function is interesting. */
5904 if (DECL_EXTERNAL (fndecl))
5905 return true;
5906
5907 /* Interesting functions that we are emitting in this object file. */
5908 c_node = cgraph_node::get (fndecl);
5909 c_node = c_node->ultimate_alias_target ();
5910 return !c_node->only_called_directly_p ();
5911 }
5912 return false;
5913}
5914#endif
5915
5916/* Initialize a variable CUM of type CUMULATIVE_ARGS
5917 for a call to a function whose data type is FNTYPE.
5918 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
5919
5920 For incoming args we set the number of arguments in the prototype large
5921 so we never return a PARALLEL. */
5922
5923void
5924init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
5925 rtx libname ATTRIBUTE_UNUSED, int incoming,
5926 int libcall, int n_named_args,
5927 tree fndecl,
5928 machine_mode return_mode ATTRIBUTE_UNUSED)
5929{
5930 static CUMULATIVE_ARGS zero_cumulative;
5931
5932 *cum = zero_cumulative;
5933 cum->words = 0;
5934 cum->fregno = FP_ARG_MIN_REG;
5935 cum->vregno = ALTIVEC_ARG_MIN_REG;
5936 cum->prototype = (fntype && prototype_p (fntype));
5937 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
5938 ? CALL_LIBCALL : CALL_NORMAL);
5939 cum->sysv_gregno = GP_ARG_MIN_REG;
5940 cum->stdarg = stdarg_p (fntype);
5941 cum->libcall = libcall;
5942
5943 cum->nargs_prototype = 0;
5944 if (incoming || cum->prototype)
5945 cum->nargs_prototype = n_named_args;
5946
5947 /* Check for a longcall attribute. */
5948 if ((!fntype && rs6000_default_long_calls)
5949 || (fntype
5950 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
5951 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
5952 cum->call_cookie |= CALL_LONG;
5953 else if (DEFAULT_ABI != ABI_DARWIN)
5954 {
5955 bool is_local = (fndecl
5956 && !DECL_EXTERNAL (fndecl)
5957 && !DECL_WEAK (fndecl)
5958 && (*targetm.binds_local_p) (fndecl));
5959 if (is_local)
5960 ;
5961 else if (flag_plt)
5962 {
5963 if (fntype
5964 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype)))
5965 cum->call_cookie |= CALL_LONG;
5966 }
5967 else
5968 {
5969 if (!(fntype
5970 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype))))
5971 cum->call_cookie |= CALL_LONG;
5972 }
5973 }
5974
5975 if (TARGET_DEBUG_ARG)
5976 {
5977 fprintf (stderr, "\ninit_cumulative_args:");
5978 if (fntype)
5979 {
5980 tree ret_type = TREE_TYPE (fntype);
5981 fprintf (stderr, " ret code = %s,",
5982 get_tree_code_name (TREE_CODE (ret_type)));
5983 }
5984
5985 if (cum->call_cookie & CALL_LONG)
5986 fprintf (stderr, " longcall,");
5987
5988 fprintf (stderr, " proto = %d, nargs = %d\n",
5989 cum->prototype, cum->nargs_prototype);
5990 }
5991
5992#ifdef HAVE_AS_GNU_ATTRIBUTE
5993 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
5994 {
5995 cum->escapes = call_ABI_of_interest (fndecl);
5996 if (cum->escapes)
5997 {
5998 tree return_type;
5999
6000 if (fntype)
6001 {
6002 return_type = TREE_TYPE (fntype);
6003 return_mode = TYPE_MODE (return_type);
6004 }
6005 else
6006 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
6007
6008 if (return_type != NULL)
6009 {
6010 if (TREE_CODE (return_type) == RECORD_TYPE
6011 && TYPE_TRANSPARENT_AGGR (return_type))
6012 {
6013 return_type = TREE_TYPE (first_field (return_type));
6014 return_mode = TYPE_MODE (return_type);
6015 }
6016 if (AGGREGATE_TYPE_P (return_type)
6017 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
6018 <= 8))
6019 rs6000_returns_struct = true;
6020 }
6021 if (SCALAR_FLOAT_MODE_P (return_mode))
6022 {
6023 rs6000_passes_float = true;
6024 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
6025 && (FLOAT128_IBM_P (return_mode)
6026 || FLOAT128_IEEE_P (return_mode)
6027 || (return_type != NULL
6028 && (TYPE_MAIN_VARIANT (return_type)
6029 == long_double_type_node))))
6030 rs6000_passes_long_double = true;
6031
6032 /* Note if we passed or return a IEEE 128-bit type. We changed
6033 the mangling for these types, and we may need to make an alias
6034 with the old mangling. */
6035 if (FLOAT128_IEEE_P (return_mode))
6036 rs6000_passes_ieee128 = true;
6037 }
6038 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
6039 rs6000_passes_vector = true;
6040 }
6041 }
6042#endif
6043
6044 if (fntype
6045 && !TARGET_ALTIVEC
6046 && TARGET_ALTIVEC_ABI
6047 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
6048 {
6049 error ("cannot return value in vector register because"
6050 " altivec instructions are disabled, use %qs"
6051 " to enable them", "-maltivec");
6052 }
6053}
6054\f
6055
6056/* On rs6000, function arguments are promoted, as are function return
6057 values. */
6058
6059machine_mode
6060rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
6061 machine_mode mode,
6062 int *punsignedp ATTRIBUTE_UNUSED,
6063 const_tree, int)
6064{
6065 PROMOTE_MODE (mode, *punsignedp, type);
6066
6067 return mode;
6068}
6069
6070/* Return true if TYPE must be passed on the stack and not in registers. */
6071
6072bool
0ffef200 6073rs6000_must_pass_in_stack (const function_arg_info &arg)
1acf0246
BS		 6074{
6075 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
0ffef200 6076 return must_pass_in_stack_var_size (arg);
1acf0246 6077 else
0ffef200 6078 return must_pass_in_stack_var_size_or_pad (arg);
1acf0246
BS		 6079}
6080
6081static inline bool
6082is_complex_IBM_long_double (machine_mode mode)
6083{
6084 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
6085}
6086
6087/* Whether ABI_V4 passes MODE args to a function in floating point
6088 registers. */
6089
6090static bool
6091abi_v4_pass_in_fpr (machine_mode mode, bool named)
6092{
6093 if (!TARGET_HARD_FLOAT)
6094 return false;
6095 if (mode == DFmode)
6096 return true;
6097 if (mode == SFmode && named)
6098 return true;
6099 /* ABI_V4 passes complex IBM long double in 8 gprs.
6100 Stupid, but we can't change the ABI now. */
6101 if (is_complex_IBM_long_double (mode))
6102 return false;
6103 if (FLOAT128_2REG_P (mode))
6104 return true;
6105 if (DECIMAL_FLOAT_MODE_P (mode))
6106 return true;
6107 return false;
6108}
6109
6110/* Implement TARGET_FUNCTION_ARG_PADDING.
6111
6112 For the AIX ABI structs are always stored left shifted in their
6113 argument slot. */
6114
6115pad_direction
6116rs6000_function_arg_padding (machine_mode mode, const_tree type)
6117{
6118#ifndef AGGREGATE_PADDING_FIXED
6119#define AGGREGATE_PADDING_FIXED 0
6120#endif
6121#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
6122#define AGGREGATES_PAD_UPWARD_ALWAYS 0
6123#endif
6124
6125 if (!AGGREGATE_PADDING_FIXED)
6126 {
6127 /* GCC used to pass structures of the same size as integer types as
6128 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
6129 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
6130 passed padded downward, except that -mstrict-align further
6131 muddied the water in that multi-component structures of 2 and 4
6132 bytes in size were passed padded upward.
6133
6134 The following arranges for best compatibility with previous
6135 versions of gcc, but removes the -mstrict-align dependency. */
6136 if (BYTES_BIG_ENDIAN)
6137 {
6138 HOST_WIDE_INT size = 0;
6139
6140 if (mode == BLKmode)
6141 {
6142 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
6143 size = int_size_in_bytes (type);
6144 }
6145 else
6146 size = GET_MODE_SIZE (mode);
6147
6148 if (size == 1 || size == 2 || size == 4)
6149 return PAD_DOWNWARD;
6150 }
6151 return PAD_UPWARD;
6152 }
6153
6154 if (AGGREGATES_PAD_UPWARD_ALWAYS)
6155 {
6156 if (type != 0 && AGGREGATE_TYPE_P (type))
6157 return PAD_UPWARD;
6158 }
6159
6160 /* Fall back to the default. */
6161 return default_function_arg_padding (mode, type);
6162}
6163
6164/* If defined, a C expression that gives the alignment boundary, in bits,
6165 of an argument with the specified mode and type. If it is not defined,
6166 PARM_BOUNDARY is used for all arguments.
6167
6168 V.4 wants long longs and doubles to be double word aligned. Just
6169 testing the mode size is a boneheaded way to do this as it means
6170 that other types such as complex int are also double word aligned.
6171 However, we're stuck with this because changing the ABI might break
6172 existing library interfaces.
6173
6174 Quadword align Altivec/VSX vectors.
6175 Quadword align large synthetic vector types. */
6176
6177unsigned int
6178rs6000_function_arg_boundary (machine_mode mode, const_tree type)
6179{
6180 machine_mode elt_mode;
6181 int n_elts;
6182
6183 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
6184
6185 if (DEFAULT_ABI == ABI_V4
6186 && (GET_MODE_SIZE (mode) == 8
6187 || (TARGET_HARD_FLOAT
6188 && !is_complex_IBM_long_double (mode)
6189 && FLOAT128_2REG_P (mode))))
6190 return 64;
6191 else if (FLOAT128_VECTOR_P (mode))
6192 return 128;
6193 else if (type && TREE_CODE (type) == VECTOR_TYPE
6194 && int_size_in_bytes (type) >= 8
6195 && int_size_in_bytes (type) < 16)
6196 return 64;
6197 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
6198 || (type && TREE_CODE (type) == VECTOR_TYPE
6199 && int_size_in_bytes (type) >= 16))
6200 return 128;
6201
6202 /* Aggregate types that need > 8 byte alignment are quadword-aligned
6203 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
6204 -mcompat-align-parm is used. */
6205 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
6206 || DEFAULT_ABI == ABI_ELFv2)
6207 && type && TYPE_ALIGN (type) > 64)
6208 {
6209 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
6210 or homogeneous float/vector aggregates here. We already handled
6211 vector aggregates above, but still need to check for float here. */
6212 bool aggregate_p = (AGGREGATE_TYPE_P (type)
6213 && !SCALAR_FLOAT_MODE_P (elt_mode));
6214
6215 /* We used to check for BLKmode instead of the above aggregate type
6216 check. Warn when this results in any difference to the ABI. */
6217 if (aggregate_p != (mode == BLKmode))
6218 {
6219 static bool warned;
6220 if (!warned && warn_psabi)
6221 {
6222 warned = true;
6223 inform (input_location,
6224 "the ABI of passing aggregates with %d-byte alignment"
6225 " has changed in GCC 5",
6226 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
6227 }
6228 }
6229
6230 if (aggregate_p)
6231 return 128;
6232 }
6233
6234 /* Similar for the Darwin64 ABI. Note that for historical reasons we
6235 implement the "aggregate type" check as a BLKmode check here; this
6236 means certain aggregate types are in fact not aligned. */
6237 if (TARGET_MACHO && rs6000_darwin64_abi
6238 && mode == BLKmode
6239 && type && TYPE_ALIGN (type) > 64)
6240 return 128;
6241
6242 return PARM_BOUNDARY;
6243}
6244
6245/* The offset in words to the start of the parameter save area. */
6246
6247static unsigned int
6248rs6000_parm_offset (void)
6249{
6250 return (DEFAULT_ABI == ABI_V4 ? 2
6251 : DEFAULT_ABI == ABI_ELFv2 ? 4
6252 : 6);
6253}
6254
6255/* For a function parm of MODE and TYPE, return the starting word in
6256 the parameter area. NWORDS of the parameter area are already used. */
6257
6258static unsigned int
6259rs6000_parm_start (machine_mode mode, const_tree type,
6260 unsigned int nwords)
6261{
6262 unsigned int align;
6263
6264 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
6265 return nwords + (-(rs6000_parm_offset () + nwords) & align);
6266}
6267
6268/* Compute the size (in words) of a function argument. */
6269
6270static unsigned long
6271rs6000_arg_size (machine_mode mode, const_tree type)
6272{
6273 unsigned long size;
6274
6275 if (mode != BLKmode)
6276 size = GET_MODE_SIZE (mode);
6277 else
6278 size = int_size_in_bytes (type);
6279
6280 if (TARGET_32BIT)
6281 return (size + 3) >> 2;
6282 else
6283 return (size + 7) >> 3;
6284}
6285\f
6286/* Use this to flush pending int fields. */
6287
6288static void
6289rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
6290 HOST_WIDE_INT bitpos, int final)
6291{
6292 unsigned int startbit, endbit;
6293 int intregs, intoffset;
6294
6295 /* Handle the situations where a float is taking up the first half
6296 of the GPR, and the other half is empty (typically due to
6297 alignment restrictions). We can detect this by a 8-byte-aligned
6298 int field, or by seeing that this is the final flush for this
6299 argument. Count the word and continue on. */
6300 if (cum->floats_in_gpr == 1
6301 && (cum->intoffset % 64 == 0
6302 || (cum->intoffset == -1 && final)))
6303 {
6304 cum->words++;
6305 cum->floats_in_gpr = 0;
6306 }
6307
6308 if (cum->intoffset == -1)
6309 return;
6310
6311 intoffset = cum->intoffset;
6312 cum->intoffset = -1;
6313 cum->floats_in_gpr = 0;
6314
6315 if (intoffset % BITS_PER_WORD != 0)
6316 {
6317 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
6318 if (!int_mode_for_size (bits, 0).exists ())
6319 {
6320 /* We couldn't find an appropriate mode, which happens,
6321 e.g., in packed structs when there are 3 bytes to load.
6322 Back intoffset back to the beginning of the word in this
6323 case. */
6324 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
6325 }
6326 }
6327
6328 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
6329 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
6330 intregs = (endbit - startbit) / BITS_PER_WORD;
6331 cum->words += intregs;
6332 /* words should be unsigned. */
6333 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
6334 {
6335 int pad = (endbit/BITS_PER_WORD) - cum->words;
6336 cum->words += pad;
6337 }
6338}
6339
6340/* The darwin64 ABI calls for us to recurse down through structs,
6341 looking for elements passed in registers. Unfortunately, we have
6342 to track int register count here also because of misalignments
6343 in powerpc alignment mode. */
6344
6345static void
6346rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
6347 const_tree type,
6348 HOST_WIDE_INT startbitpos)
6349{
6350 tree f;
6351
6352 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
6353 if (TREE_CODE (f) == FIELD_DECL)
6354 {
6355 HOST_WIDE_INT bitpos = startbitpos;
6356 tree ftype = TREE_TYPE (f);
6357 machine_mode mode;
6358 if (ftype == error_mark_node)
6359 continue;
6360 mode = TYPE_MODE (ftype);
6361
6362 if (DECL_SIZE (f) != 0
6363 && tree_fits_uhwi_p (bit_position (f)))
6364 bitpos += int_bit_position (f);
6365
6366 /* ??? FIXME: else assume zero offset. */
6367
6368 if (TREE_CODE (ftype) == RECORD_TYPE)
6369 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
6370 else if (USE_FP_FOR_ARG_P (cum, mode))
6371 {
6372 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
6373 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
6374 cum->fregno += n_fpregs;
6375 /* Single-precision floats present a special problem for
6376 us, because they are smaller than an 8-byte GPR, and so
6377 the structure-packing rules combined with the standard
6378 varargs behavior mean that we want to pack float/float
6379 and float/int combinations into a single register's
6380 space. This is complicated by the arg advance flushing,
6381 which works on arbitrarily large groups of int-type
6382 fields. */
6383 if (mode == SFmode)
6384 {
6385 if (cum->floats_in_gpr == 1)
6386 {
6387 /* Two floats in a word; count the word and reset
6388 the float count. */
6389 cum->words++;
6390 cum->floats_in_gpr = 0;
6391 }
6392 else if (bitpos % 64 == 0)
6393 {
6394 /* A float at the beginning of an 8-byte word;
6395 count it and put off adjusting cum->words until
6396 we see if a arg advance flush is going to do it
6397 for us. */
6398 cum->floats_in_gpr++;
6399 }
6400 else
6401 {
6402 /* The float is at the end of a word, preceded
6403 by integer fields, so the arg advance flush
6404 just above has already set cum->words and
6405 everything is taken care of. */
6406 }
6407 }
6408 else
6409 cum->words += n_fpregs;
6410 }
6411 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
6412 {
6413 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
6414 cum->vregno++;
6415 cum->words += 2;
6416 }
6417 else if (cum->intoffset == -1)
6418 cum->intoffset = bitpos;
6419 }
6420}
6421
6422/* Check for an item that needs to be considered specially under the darwin 64
6423 bit ABI. These are record types where the mode is BLK or the structure is
6424 8 bytes in size. */
6425int
6426rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
6427{
6428 return rs6000_darwin64_abi
6429 && ((mode == BLKmode
6430 && TREE_CODE (type) == RECORD_TYPE
6431 && int_size_in_bytes (type) > 0)
6432 || (type && TREE_CODE (type) == RECORD_TYPE
6433 && int_size_in_bytes (type) == 8)) ? 1 : 0;
6434}
6435
6436/* Update the data in CUM to advance over an argument
6437 of mode MODE and data type TYPE.
6438 (TYPE is null for libcalls where that information may not be available.)
6439
6440 Note that for args passed by reference, function_arg will be called
6441 with MODE and TYPE set to that of the pointer to the arg, not the arg
6442 itself. */
6443
6444static void
6445rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
6446 const_tree type, bool named, int depth)
6447{
6448 machine_mode elt_mode;
6449 int n_elts;
6450
6451 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
6452
6453 /* Only tick off an argument if we're not recursing. */
6454 if (depth == 0)
6455 cum->nargs_prototype--;
6456
6457#ifdef HAVE_AS_GNU_ATTRIBUTE
6458 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
6459 && cum->escapes)
6460 {
6461 if (SCALAR_FLOAT_MODE_P (mode))
6462 {
6463 rs6000_passes_float = true;
6464 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
6465 && (FLOAT128_IBM_P (mode)
6466 || FLOAT128_IEEE_P (mode)
6467 || (type != NULL
6468 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
6469 rs6000_passes_long_double = true;
6470
6471 /* Note if we passed or return a IEEE 128-bit type. We changed the
6472 mangling for these types, and we may need to make an alias with
6473 the old mangling. */
6474 if (FLOAT128_IEEE_P (mode))
6475 rs6000_passes_ieee128 = true;
6476 }
6477 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
6478 rs6000_passes_vector = true;
6479 }
6480#endif
6481
6482 if (TARGET_ALTIVEC_ABI
6483 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
6484 || (type && TREE_CODE (type) == VECTOR_TYPE
6485 && int_size_in_bytes (type) == 16)))
6486 {
6487 bool stack = false;
6488
6489 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
6490 {
6491 cum->vregno += n_elts;
6492
6493 if (!TARGET_ALTIVEC)
6494 error ("cannot pass argument in vector register because"
6495 " altivec instructions are disabled, use %qs"
6496 " to enable them", "-maltivec");
6497
6498 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
6499 even if it is going to be passed in a vector register.
6500 Darwin does the same for variable-argument functions. */
6501 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
6502 && TARGET_64BIT)
6503 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
6504 stack = true;
6505 }
6506 else
6507 stack = true;
6508
6509 if (stack)
6510 {
6511 int align;
6512
6513 /* Vector parameters must be 16-byte aligned. In 32-bit
6514 mode this means we need to take into account the offset
6515 to the parameter save area. In 64-bit mode, they just
6516 have to start on an even word, since the parameter save
6517 area is 16-byte aligned. */
6518 if (TARGET_32BIT)
6519 align = -(rs6000_parm_offset () + cum->words) & 3;
6520 else
6521 align = cum->words & 1;
6522 cum->words += align + rs6000_arg_size (mode, type);
6523
6524 if (TARGET_DEBUG_ARG)
6525 {
6526 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
6527 cum->words, align);
6528 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
6529 cum->nargs_prototype, cum->prototype,
6530 GET_MODE_NAME (mode));
6531 }
6532 }
6533 }
6534 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
6535 {
6536 int size = int_size_in_bytes (type);
6537 /* Variable sized types have size == -1 and are
6538 treated as if consisting entirely of ints.
6539 Pad to 16 byte boundary if needed. */
6540 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
6541 && (cum->words % 2) != 0)
6542 cum->words++;
6543 /* For varargs, we can just go up by the size of the struct. */
6544 if (!named)
6545 cum->words += (size + 7) / 8;
6546 else
6547 {
6548 /* It is tempting to say int register count just goes up by
6549 sizeof(type)/8, but this is wrong in a case such as
6550 { int; double; int; } [powerpc alignment]. We have to
6551 grovel through the fields for these too. */
6552 cum->intoffset = 0;
6553 cum->floats_in_gpr = 0;
6554 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
6555 rs6000_darwin64_record_arg_advance_flush (cum,
6556 size * BITS_PER_UNIT, 1);
6557 }
6558 if (TARGET_DEBUG_ARG)
6559 {
6560 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
6561 cum->words, TYPE_ALIGN (type), size);
6562 fprintf (stderr,
6563 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
6564 cum->nargs_prototype, cum->prototype,
6565 GET_MODE_NAME (mode));
6566 }
6567 }
6568 else if (DEFAULT_ABI == ABI_V4)
6569 {
6570 if (abi_v4_pass_in_fpr (mode, named))
6571 {
6572 /* _Decimal128 must use an even/odd register pair. This assumes
6573 that the register number is odd when fregno is odd. */
6574 if (mode == TDmode && (cum->fregno % 2) == 1)
6575 cum->fregno++;
6576
6577 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
6578 <= FP_ARG_V4_MAX_REG)
6579 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
6580 else
6581 {
6582 cum->fregno = FP_ARG_V4_MAX_REG + 1;
6583 if (mode == DFmode || FLOAT128_IBM_P (mode)
6584 || mode == DDmode || mode == TDmode)
6585 cum->words += cum->words & 1;
6586 cum->words += rs6000_arg_size (mode, type);
6587 }
6588 }
6589 else
6590 {
6591 int n_words = rs6000_arg_size (mode, type);
6592 int gregno = cum->sysv_gregno;
6593
6594 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
6595 As does any other 2 word item such as complex int due to a
6596 historical mistake. */
6597 if (n_words == 2)
6598 gregno += (1 - gregno) & 1;
6599
6600 /* Multi-reg args are not split between registers and stack. */
6601 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
6602 {
6603 /* Long long is aligned on the stack. So are other 2 word
6604 items such as complex int due to a historical mistake. */
6605 if (n_words == 2)
6606 cum->words += cum->words & 1;
6607 cum->words += n_words;
6608 }
6609
6610 /* Note: continuing to accumulate gregno past when we've started
6611 spilling to the stack indicates the fact that we've started
6612 spilling to the stack to expand_builtin_saveregs. */
6613 cum->sysv_gregno = gregno + n_words;
6614 }
6615
6616 if (TARGET_DEBUG_ARG)
6617 {
6618 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
6619 cum->words, cum->fregno);
6620 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
6621 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
6622 fprintf (stderr, "mode = %4s, named = %d\n",
6623 GET_MODE_NAME (mode), named);
6624 }
6625 }
6626 else
6627 {
6628 int n_words = rs6000_arg_size (mode, type);
6629 int start_words = cum->words;
6630 int align_words = rs6000_parm_start (mode, type, start_words);
6631
6632 cum->words = align_words + n_words;
6633
6634 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
6635 {
6636 /* _Decimal128 must be passed in an even/odd float register pair.
6637 This assumes that the register number is odd when fregno is
6638 odd. */
6639 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
6640 cum->fregno++;
6641 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
6642 }
6643
6644 if (TARGET_DEBUG_ARG)
6645 {
6646 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
6647 cum->words, cum->fregno);
6648 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
6649 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
6650 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
6651 named, align_words - start_words, depth);
6652 }
6653 }
6654}
6655
6656void
6930c98c
RS		 6657rs6000_function_arg_advance (cumulative_args_t cum,
6658 const function_arg_info &arg)
1acf0246 6659{
6930c98c
RS		 6660 rs6000_function_arg_advance_1 (get_cumulative_args (cum),
6661 arg.mode, arg.type, arg.named, 0);
1acf0246
BS		 6662}
6663
6664/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
6665 structure between cum->intoffset and bitpos to integer registers. */
6666
6667static void
6668rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
6669 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
6670{
6671 machine_mode mode;
6672 unsigned int regno;
6673 unsigned int startbit, endbit;
6674 int this_regno, intregs, intoffset;
6675 rtx reg;
6676
6677 if (cum->intoffset == -1)
6678 return;
6679
6680 intoffset = cum->intoffset;
6681 cum->intoffset = -1;
6682
6683 /* If this is the trailing part of a word, try to only load that
6684 much into the register. Otherwise load the whole register. Note
6685 that in the latter case we may pick up unwanted bits. It's not a
6686 problem at the moment but may wish to revisit. */
6687
6688 if (intoffset % BITS_PER_WORD != 0)
6689 {
6690 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
6691 if (!int_mode_for_size (bits, 0).exists (&mode))
6692 {
6693 /* We couldn't find an appropriate mode, which happens,
6694 e.g., in packed structs when there are 3 bytes to load.
6695 Back intoffset back to the beginning of the word in this
6696 case. */
6697 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
6698 mode = word_mode;
6699 }
6700 }
6701 else
6702 mode = word_mode;
6703
6704 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
6705 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
6706 intregs = (endbit - startbit) / BITS_PER_WORD;
6707 this_regno = cum->words + intoffset / BITS_PER_WORD;
6708
6709 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
6710 cum->use_stack = 1;
6711
6712 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
6713 if (intregs <= 0)
6714 return;
6715
6716 intoffset /= BITS_PER_UNIT;
6717 do
6718 {
6719 regno = GP_ARG_MIN_REG + this_regno;
6720 reg = gen_rtx_REG (mode, regno);
6721 rvec[(*k)++] =
6722 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
6723
6724 this_regno += 1;
6725 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
6726 mode = word_mode;
6727 intregs -= 1;
6728 }
6729 while (intregs > 0);
6730}
6731
6732/* Recursive workhorse for the following. */
6733
6734static void
6735rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
6736 HOST_WIDE_INT startbitpos, rtx rvec[],
6737 int *k)
6738{
6739 tree f;
6740
6741 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
6742 if (TREE_CODE (f) == FIELD_DECL)
6743 {
6744 HOST_WIDE_INT bitpos = startbitpos;
6745 tree ftype = TREE_TYPE (f);
6746 machine_mode mode;
6747 if (ftype == error_mark_node)
6748 continue;
6749 mode = TYPE_MODE (ftype);
6750
6751 if (DECL_SIZE (f) != 0
6752 && tree_fits_uhwi_p (bit_position (f)))
6753 bitpos += int_bit_position (f);
6754
6755 /* ??? FIXME: else assume zero offset. */
6756
6757 if (TREE_CODE (ftype) == RECORD_TYPE)
6758 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
6759 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
6760 {
6761 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
6762#if 0
6763 switch (mode)
6764 {
6765 case E_SCmode: mode = SFmode; break;
6766 case E_DCmode: mode = DFmode; break;
6767 case E_TCmode: mode = TFmode; break;
6768 default: break;
6769 }
6770#endif
6771 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
6772 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
6773 {
6774 gcc_assert (cum->fregno == FP_ARG_MAX_REG
6775 && (mode == TFmode || mode == TDmode));
6776 /* Long double or _Decimal128 split over regs and memory. */
6777 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
6778 cum->use_stack=1;
6779 }
6780 rvec[(*k)++]
6781 = gen_rtx_EXPR_LIST (VOIDmode,
6782 gen_rtx_REG (mode, cum->fregno++),
6783 GEN_INT (bitpos / BITS_PER_UNIT));
6784 if (FLOAT128_2REG_P (mode))
6785 cum->fregno++;
6786 }
6787 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
6788 {
6789 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
6790 rvec[(*k)++]
6791 = gen_rtx_EXPR_LIST (VOIDmode,
6792 gen_rtx_REG (mode, cum->vregno++),
6793 GEN_INT (bitpos / BITS_PER_UNIT));
6794 }
6795 else if (cum->intoffset == -1)
6796 cum->intoffset = bitpos;
6797 }
6798}
6799
6800/* For the darwin64 ABI, we want to construct a PARALLEL consisting of
6801 the register(s) to be used for each field and subfield of a struct
6802 being passed by value, along with the offset of where the
6803 register's value may be found in the block. FP fields go in FP
6804 register, vector fields go in vector registers, and everything
6805 else goes in int registers, packed as in memory.
6806
6807 This code is also used for function return values. RETVAL indicates
6808 whether this is the case.
6809
6810 Much of this is taken from the SPARC V9 port, which has a similar
6811 calling convention. */
6812
6813rtx
6814rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
6815 bool named, bool retval)
6816{
6817 rtx rvec[FIRST_PSEUDO_REGISTER];
6818 int k = 1, kbase = 1;
6819 HOST_WIDE_INT typesize = int_size_in_bytes (type);
6820 /* This is a copy; modifications are not visible to our caller. */
6821 CUMULATIVE_ARGS copy_cum = *orig_cum;
6822 CUMULATIVE_ARGS *cum = &copy_cum;
6823
6824 /* Pad to 16 byte boundary if needed. */
6825 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
6826 && (cum->words % 2) != 0)
6827 cum->words++;
6828
6829 cum->intoffset = 0;
6830 cum->use_stack = 0;
6831 cum->named = named;
6832
6833 /* Put entries into rvec[] for individual FP and vector fields, and
6834 for the chunks of memory that go in int regs. Note we start at
6835 element 1; 0 is reserved for an indication of using memory, and
6836 may or may not be filled in below. */
6837 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
6838 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
6839
6840 /* If any part of the struct went on the stack put all of it there.
6841 This hack is because the generic code for
6842 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
6843 parts of the struct are not at the beginning. */
6844 if (cum->use_stack)
6845 {
6846 if (retval)
6847 return NULL_RTX; /* doesn't go in registers at all */
6848 kbase = 0;
6849 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6850 }
6851 if (k > 1 || cum->use_stack)
6852 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
6853 else
6854 return NULL_RTX;
6855}
6856
6857/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
6858
6859static rtx
6860rs6000_mixed_function_arg (machine_mode mode, const_tree type,
6861 int align_words)
6862{
6863 int n_units;
6864 int i, k;
6865 rtx rvec[GP_ARG_NUM_REG + 1];
6866
6867 if (align_words >= GP_ARG_NUM_REG)
6868 return NULL_RTX;
6869
6870 n_units = rs6000_arg_size (mode, type);
6871
6872 /* Optimize the simple case where the arg fits in one gpr, except in
6873 the case of BLKmode due to assign_parms assuming that registers are
6874 BITS_PER_WORD wide. */
6875 if (n_units == 0
6876 || (n_units == 1 && mode != BLKmode))
6877 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6878
6879 k = 0;
6880 if (align_words + n_units > GP_ARG_NUM_REG)
6881 /* Not all of the arg fits in gprs. Say that it goes in memory too,
6882 using a magic NULL_RTX component.
6883 This is not strictly correct. Only some of the arg belongs in
6884 memory, not all of it. However, the normal scheme using
6885 function_arg_partial_nregs can result in unusual subregs, eg.
6886 (subreg:SI (reg:DF) 4), which are not handled well. The code to
6887 store the whole arg to memory is often more efficient than code
6888 to store pieces, and we know that space is available in the right
6889 place for the whole arg. */
6890 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6891
6892 i = 0;
6893 do
6894 {
6895 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
6896 rtx off = GEN_INT (i++ * 4);
6897 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
6898 }
6899 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
6900
6901 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
6902}
6903
6904/* We have an argument of MODE and TYPE that goes into FPRs or VRs,
6905 but must also be copied into the parameter save area starting at
6906 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
6907 to the GPRs and/or memory. Return the number of elements used. */
6908
6909static int
6910rs6000_psave_function_arg (machine_mode mode, const_tree type,
6911 int align_words, rtx *rvec)
6912{
6913 int k = 0;
6914
6915 if (align_words < GP_ARG_NUM_REG)
6916 {
6917 int n_words = rs6000_arg_size (mode, type);
6918
6919 if (align_words + n_words > GP_ARG_NUM_REG
6920 || mode == BLKmode
6921 || (TARGET_32BIT && TARGET_POWERPC64))
6922 {
6923 /* If this is partially on the stack, then we only
6924 include the portion actually in registers here. */
6925 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
6926 int i = 0;
6927
6928 if (align_words + n_words > GP_ARG_NUM_REG)
6929 {
6930 /* Not all of the arg fits in gprs. Say that it goes in memory
6931 too, using a magic NULL_RTX component. Also see comment in
6932 rs6000_mixed_function_arg for why the normal
6933 function_arg_partial_nregs scheme doesn't work in this case. */
6934 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6935 }
6936
6937 do
6938 {
6939 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
6940 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
6941 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
6942 }
6943 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
6944 }
6945 else
6946 {
6947 /* The whole arg fits in gprs. */
6948 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6949 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
6950 }
6951 }
6952 else
6953 {
6954 /* It's entirely in memory. */
6955 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6956 }
6957
6958 return k;
6959}
6960
6961/* RVEC is a vector of K components of an argument of mode MODE.
6962 Construct the final function_arg return value from it. */
6963
6964static rtx
6965rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
6966{
6967 gcc_assert (k >= 1);
6968
6969 /* Avoid returning a PARALLEL in the trivial cases. */
6970 if (k == 1)
6971 {
6972 if (XEXP (rvec[0], 0) == NULL_RTX)
6973 return NULL_RTX;
6974
6975 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
6976 return XEXP (rvec[0], 0);
6977 }
6978
6979 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
6980}
6981
6982/* Determine where to put an argument to a function.
6983 Value is zero to push the argument on the stack,
6984 or a hard register in which to store the argument.
6985
1acf0246
BS		 6986 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6987 the preceding args and about the function being called. It is
6988 not modified in this routine.
6783fdb7 6989 ARG is a description of the argument.
1acf0246
BS		 6990
6991 On RS/6000 the first eight words of non-FP are normally in registers
6992 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
6993 Under V.4, the first 8 FP args are in registers.
6994
6995 If this is floating-point and no prototype is specified, we use
6996 both an FP and integer register (or possibly FP reg and stack). Library
6997 functions (when CALL_LIBCALL is set) always have the proper types for args,
6998 so we can pass the FP value just in one register. emit_library_function
6999 doesn't support PARALLEL anyway.
7000
7001 Note that for args passed by reference, function_arg will be called
6783fdb7 7002 with ARG describing the pointer to the arg, not the arg itself. */
1acf0246
BS		 7003
7004rtx
6783fdb7 7005rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
1acf0246
BS		 7006{
7007 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6783fdb7
RS		 7008 tree type = arg.type;
7009 machine_mode mode = arg.mode;
7010 bool named = arg.named;
1acf0246
BS		 7011 enum rs6000_abi abi = DEFAULT_ABI;
7012 machine_mode elt_mode;
7013 int n_elts;
7014
7015 /* Return a marker to indicate whether CR1 needs to set or clear the
7016 bit that V.4 uses to say fp args were passed in registers.
7017 Assume that we don't need the marker for software floating point,
7018 or compiler generated library calls. */
6783fdb7 7019 if (arg.end_marker_p ())
1acf0246
BS		 7020 {
7021 if (abi == ABI_V4
7022 && (cum->call_cookie & CALL_LIBCALL) == 0
7023 && (cum->stdarg
7024 || (cum->nargs_prototype < 0
7025 && (cum->prototype || TARGET_NO_PROTOTYPE)))
7026 && TARGET_HARD_FLOAT)
7027 return GEN_INT (cum->call_cookie
7028 | ((cum->fregno == FP_ARG_MIN_REG)
7029 ? CALL_V4_SET_FP_ARGS
7030 : CALL_V4_CLEAR_FP_ARGS));
7031
7032 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
7033 }
7034
7035 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
7036
7037 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7038 {
7039 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
7040 if (rslt != NULL_RTX)
7041 return rslt;
7042 /* Else fall through to usual handling. */
7043 }
7044
7045 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
7046 {
7047 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
7048 rtx r, off;
7049 int i, k = 0;
7050
7051 /* Do we also need to pass this argument in the parameter save area?
7052 Library support functions for IEEE 128-bit are assumed to not need the
7053 value passed both in GPRs and in vector registers. */
7054 if (TARGET_64BIT && !cum->prototype
7055 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
7056 {
7057 int align_words = ROUND_UP (cum->words, 2);
7058 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
7059 }
7060
7061 /* Describe where this argument goes in the vector registers. */
7062 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
7063 {
7064 r = gen_rtx_REG (elt_mode, cum->vregno + i);
7065 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
7066 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7067 }
7068
7069 return rs6000_finish_function_arg (mode, rvec, k);
7070 }
7071 else if (TARGET_ALTIVEC_ABI
7072 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7073 || (type && TREE_CODE (type) == VECTOR_TYPE
7074 && int_size_in_bytes (type) == 16)))
7075 {
7076 if (named || abi == ABI_V4)
7077 return NULL_RTX;
7078 else
7079 {
7080 /* Vector parameters to varargs functions under AIX or Darwin
7081 get passed in memory and possibly also in GPRs. */
7082 int align, align_words, n_words;
7083 machine_mode part_mode;
7084
7085 /* Vector parameters must be 16-byte aligned. In 32-bit
7086 mode this means we need to take into account the offset
7087 to the parameter save area. In 64-bit mode, they just
7088 have to start on an even word, since the parameter save
7089 area is 16-byte aligned. */
7090 if (TARGET_32BIT)
7091 align = -(rs6000_parm_offset () + cum->words) & 3;
7092 else
7093 align = cum->words & 1;
7094 align_words = cum->words + align;
7095
7096 /* Out of registers? Memory, then. */
7097 if (align_words >= GP_ARG_NUM_REG)
7098 return NULL_RTX;
7099
7100 if (TARGET_32BIT && TARGET_POWERPC64)
7101 return rs6000_mixed_function_arg (mode, type, align_words);
7102
7103 /* The vector value goes in GPRs. Only the part of the
7104 value in GPRs is reported here. */
7105 part_mode = mode;
7106 n_words = rs6000_arg_size (mode, type);
7107 if (align_words + n_words > GP_ARG_NUM_REG)
7108 /* Fortunately, there are only two possibilities, the value
7109 is either wholly in GPRs or half in GPRs and half not. */
7110 part_mode = DImode;
7111
7112 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
7113 }
7114 }
7115
7116 else if (abi == ABI_V4)
7117 {
7118 if (abi_v4_pass_in_fpr (mode, named))
7119 {
7120 /* _Decimal128 must use an even/odd register pair. This assumes
7121 that the register number is odd when fregno is odd. */
7122 if (mode == TDmode && (cum->fregno % 2) == 1)
7123 cum->fregno++;
7124
7125 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
7126 <= FP_ARG_V4_MAX_REG)
7127 return gen_rtx_REG (mode, cum->fregno);
7128 else
7129 return NULL_RTX;
7130 }
7131 else
7132 {
7133 int n_words = rs6000_arg_size (mode, type);
7134 int gregno = cum->sysv_gregno;
7135
7136 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
7137 As does any other 2 word item such as complex int due to a
7138 historical mistake. */
7139 if (n_words == 2)
7140 gregno += (1 - gregno) & 1;
7141
7142 /* Multi-reg args are not split between registers and stack. */
7143 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7144 return NULL_RTX;
7145
7146 if (TARGET_32BIT && TARGET_POWERPC64)
7147 return rs6000_mixed_function_arg (mode, type,
7148 gregno - GP_ARG_MIN_REG);
7149 return gen_rtx_REG (mode, gregno);
7150 }
7151 }
7152 else
7153 {
7154 int align_words = rs6000_parm_start (mode, type, cum->words);
7155
7156 /* _Decimal128 must be passed in an even/odd float register pair.
7157 This assumes that the register number is odd when fregno is odd. */
7158 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
7159 cum->fregno++;
7160
7161 if (USE_FP_FOR_ARG_P (cum, elt_mode)
7162 && !(TARGET_AIX && !TARGET_ELF
7163 && type != NULL && AGGREGATE_TYPE_P (type)))
7164 {
7165 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
7166 rtx r, off;
7167 int i, k = 0;
7168 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
7169 int fpr_words;
7170
7171 /* Do we also need to pass this argument in the parameter
7172 save area? */
7173 if (type && (cum->nargs_prototype <= 0
7174 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7175 && TARGET_XL_COMPAT
7176 && align_words >= GP_ARG_NUM_REG)))
7177 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
7178
7179 /* Describe where this argument goes in the fprs. */
7180 for (i = 0; i < n_elts
7181 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
7182 {
7183 /* Check if the argument is split over registers and memory.
7184 This can only ever happen for long double or _Decimal128;
7185 complex types are handled via split_complex_arg. */
7186 machine_mode fmode = elt_mode;
7187 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
7188 {
7189 gcc_assert (FLOAT128_2REG_P (fmode));
7190 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
7191 }
7192
7193 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
7194 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
7195 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7196 }
7197
7198 /* If there were not enough FPRs to hold the argument, the rest
7199 usually goes into memory. However, if the current position
7200 is still within the register parameter area, a portion may
7201 actually have to go into GPRs.
7202
7203 Note that it may happen that the portion of the argument
7204 passed in the first "half" of the first GPR was already
7205 passed in the last FPR as well.
7206
7207 For unnamed arguments, we already set up GPRs to cover the
7208 whole argument in rs6000_psave_function_arg, so there is
7209 nothing further to do at this point. */
7210 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
7211 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
7212 && cum->nargs_prototype > 0)
7213 {
7214 static bool warned;
7215
7216 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
7217 int n_words = rs6000_arg_size (mode, type);
7218
7219 align_words += fpr_words;
7220 n_words -= fpr_words;
7221
7222 do
7223 {
7224 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
7225 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
7226 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7227 }
7228 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
7229
7230 if (!warned && warn_psabi)
7231 {
7232 warned = true;
7233 inform (input_location,
7234 "the ABI of passing homogeneous %<float%> aggregates"
7235 " has changed in GCC 5");
7236 }
7237 }
7238
7239 return rs6000_finish_function_arg (mode, rvec, k);
7240 }
7241 else if (align_words < GP_ARG_NUM_REG)
7242 {
7243 if (TARGET_32BIT && TARGET_POWERPC64)
7244 return rs6000_mixed_function_arg (mode, type, align_words);
7245
7246 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7247 }
7248 else
7249 return NULL_RTX;
7250 }
7251}
7252\f
7253/* For an arg passed partly in registers and partly in memory, this is
7254 the number of bytes passed in registers. For args passed entirely in
7255 registers or entirely in memory, zero. When an arg is described by a
7256 PARALLEL, perhaps using more than one register type, this function
7257 returns the number of bytes used by the first element of the PARALLEL. */
7258
7259int
a7c81bc1
RS		 7260rs6000_arg_partial_bytes (cumulative_args_t cum_v,
7261 const function_arg_info &arg)
1acf0246
BS		 7262{
7263 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7264 bool passed_in_gprs = true;
7265 int ret = 0;
7266 int align_words;
7267 machine_mode elt_mode;
7268 int n_elts;
7269
a7c81bc1
RS		 7270 rs6000_discover_homogeneous_aggregate (arg.mode, arg.type,
7271 &elt_mode, &n_elts);
1acf0246
BS		 7272
7273 if (DEFAULT_ABI == ABI_V4)
7274 return 0;
7275
a7c81bc1 7276 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, arg.named))
1acf0246
BS		 7277 {
7278 /* If we are passing this arg in the fixed parameter save area (gprs or
7279 memory) as well as VRs, we do not use the partial bytes mechanism;
7280 instead, rs6000_function_arg will return a PARALLEL including a memory
7281 element as necessary. Library support functions for IEEE 128-bit are
7282 assumed to not need the value passed both in GPRs and in vector
7283 registers. */
7284 if (TARGET_64BIT && !cum->prototype
7285 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
7286 return 0;
7287
7288 /* Otherwise, we pass in VRs only. Check for partial copies. */
7289 passed_in_gprs = false;
7290 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
7291 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
7292 }
7293
7294 /* In this complicated case we just disable the partial_nregs code. */
a7c81bc1 7295 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (arg.mode, arg.type))
1acf0246
BS		 7296 return 0;
7297
a7c81bc1 7298 align_words = rs6000_parm_start (arg.mode, arg.type, cum->words);
1acf0246
BS		 7299
7300 if (USE_FP_FOR_ARG_P (cum, elt_mode)
a7c81bc1 7301 && !(TARGET_AIX && !TARGET_ELF && arg.aggregate_type_p ()))
1acf0246
BS		 7302 {
7303 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
7304
7305 /* If we are passing this arg in the fixed parameter save area
7306 (gprs or memory) as well as FPRs, we do not use the partial
7307 bytes mechanism; instead, rs6000_function_arg will return a
7308 PARALLEL including a memory element as necessary. */
a7c81bc1 7309 if (arg.type
1acf0246
BS		 7310 && (cum->nargs_prototype <= 0
7311 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7312 && TARGET_XL_COMPAT
7313 && align_words >= GP_ARG_NUM_REG)))
7314 return 0;
7315
7316 /* Otherwise, we pass in FPRs only. Check for partial copies. */
7317 passed_in_gprs = false;
7318 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
7319 {
7320 /* Compute number of bytes / words passed in FPRs. If there
7321 is still space available in the register parameter area
7322 *after* that amount, a part of the argument will be passed
7323 in GPRs. In that case, the total amount passed in any
7324 registers is equal to the amount that would have been passed
7325 in GPRs if everything were passed there, so we fall back to
7326 the GPR code below to compute the appropriate value. */
7327 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
7328 * MIN (8, GET_MODE_SIZE (elt_mode)));
7329 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
7330
7331 if (align_words + fpr_words < GP_ARG_NUM_REG)
7332 passed_in_gprs = true;
7333 else
7334 ret = fpr;
7335 }
7336 }
7337
7338 if (passed_in_gprs
7339 && align_words < GP_ARG_NUM_REG
a7c81bc1 7340 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (arg.mode, arg.type))
1acf0246
BS		 7341 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
7342
7343 if (ret != 0 && TARGET_DEBUG_ARG)
7344 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
7345
7346 return ret;
7347}
7348\f
7349/* A C expression that indicates when an argument must be passed by
7350 reference. If nonzero for an argument, a copy of that argument is
7351 made in memory and a pointer to the argument is passed instead of
7352 the argument itself. The pointer is passed in whatever way is
7353 appropriate for passing a pointer to that type.
7354
7355 Under V.4, aggregates and long double are passed by reference.
7356
7357 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
7358 reference unless the AltiVec vector extension ABI is in force.
7359
7360 As an extension to all ABIs, variable sized types are passed by
7361 reference. */
7362
7363bool
52090e4d 7364rs6000_pass_by_reference (cumulative_args_t, const function_arg_info &arg)
1acf0246 7365{
52090e4d 7366 if (!arg.type)
1acf0246
BS		 7367 return 0;
7368
7369 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
52090e4d 7370 && FLOAT128_IEEE_P (TYPE_MODE (arg.type)))
1acf0246
BS		 7371 {
7372 if (TARGET_DEBUG_ARG)
7373 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
7374 return 1;
7375 }
7376
52090e4d 7377 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (arg.type))
1acf0246
BS		 7378 {
7379 if (TARGET_DEBUG_ARG)
7380 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
7381 return 1;
7382 }
7383
52090e4d 7384 if (int_size_in_bytes (arg.type) < 0)
1acf0246
BS		 7385 {
7386 if (TARGET_DEBUG_ARG)
7387 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
7388 return 1;
7389 }
7390
7391 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7392 modes only exist for GCC vector types if -maltivec. */
52090e4d 7393 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (arg.mode))
1acf0246
BS		 7394 {
7395 if (TARGET_DEBUG_ARG)
7396 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
7397 return 1;
7398 }
7399
7400 /* Pass synthetic vectors in memory. */
52090e4d
RS		 7401 if (TREE_CODE (arg.type) == VECTOR_TYPE
7402 && int_size_in_bytes (arg.type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
1acf0246
BS		 7403 {
7404 static bool warned_for_pass_big_vectors = false;
7405 if (TARGET_DEBUG_ARG)
7406 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
7407 if (!warned_for_pass_big_vectors)
7408 {
7409 warning (OPT_Wpsabi, "GCC vector passed by reference: "
7410 "non-standard ABI extension with no compatibility "
7411 "guarantee");
7412 warned_for_pass_big_vectors = true;
7413 }
7414 return 1;
7415 }
7416
7417 return 0;
7418}
7419
7420/* Process parameter of type TYPE after ARGS_SO_FAR parameters were
7421 already processes. Return true if the parameter must be passed
7422 (fully or partially) on the stack. */
7423
7424static bool
7425rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
7426{
1acf0246
BS		 7427 int unsignedp;
7428 rtx entry_parm;
7429
7430 /* Catch errors. */
7431 if (type == NULL || type == error_mark_node)
7432 return true;
7433
7434 /* Handle types with no storage requirement. */
7435 if (TYPE_MODE (type) == VOIDmode)
7436 return false;
7437
7438 /* Handle complex types. */
7439 if (TREE_CODE (type) == COMPLEX_TYPE)
7440 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
7441 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
7442
7443 /* Handle transparent aggregates. */
7444 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
7445 && TYPE_TRANSPARENT_AGGR (type))
7446 type = TREE_TYPE (first_field (type));
7447
7448 /* See if this arg was passed by invisible reference. */
b12cdd6e
RS		 7449 function_arg_info arg (type, /*named=*/true);
7450 apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg);
1acf0246
BS		 7451
7452 /* Find mode as it is passed by the ABI. */
7453 unsignedp = TYPE_UNSIGNED (type);
b12cdd6e 7454 arg.mode = promote_mode (arg.type, arg.mode, &unsignedp);
1acf0246
BS		 7455
7456 /* If we must pass in stack, we need a stack. */
0ffef200 7457 if (rs6000_must_pass_in_stack (arg))
1acf0246
BS		 7458 return true;
7459
7460 /* If there is no incoming register, we need a stack. */
6783fdb7 7461 entry_parm = rs6000_function_arg (args_so_far, arg);
1acf0246
BS		 7462 if (entry_parm == NULL)
7463 return true;
7464
7465 /* Likewise if we need to pass both in registers and on the stack. */
7466 if (GET_CODE (entry_parm) == PARALLEL
7467 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
7468 return true;
7469
7470 /* Also true if we're partially in registers and partially not. */
a7c81bc1 7471 if (rs6000_arg_partial_bytes (args_so_far, arg) != 0)
1acf0246
BS		 7472 return true;
7473
7474 /* Update info on where next arg arrives in registers. */
6930c98c 7475 rs6000_function_arg_advance (args_so_far, arg);
1acf0246
BS		 7476 return false;
7477}
7478
7479/* Return true if FUN has no prototype, has a variable argument
7480 list, or passes any parameter in memory. */
7481
7482static bool
7483rs6000_function_parms_need_stack (tree fun, bool incoming)
7484{
7485 tree fntype, result;
7486 CUMULATIVE_ARGS args_so_far_v;
7487 cumulative_args_t args_so_far;
7488
7489 if (!fun)
7490 /* Must be a libcall, all of which only use reg parms. */
7491 return false;
7492
7493 fntype = fun;
7494 if (!TYPE_P (fun))
7495 fntype = TREE_TYPE (fun);
7496
7497 /* Varargs functions need the parameter save area. */
7498 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
7499 return true;
7500
7501 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
7502 args_so_far = pack_cumulative_args (&args_so_far_v);
7503
7504 /* When incoming, we will have been passed the function decl.
7505 It is necessary to use the decl to handle K&R style functions,
7506 where TYPE_ARG_TYPES may not be available. */
7507 if (incoming)
7508 {
7509 gcc_assert (DECL_P (fun));
7510 result = DECL_RESULT (fun);
7511 }
7512 else
7513 result = TREE_TYPE (fntype);
7514
7515 if (result && aggregate_value_p (result, fntype))
7516 {
7517 if (!TYPE_P (result))
7518 result = TREE_TYPE (result);
7519 result = build_pointer_type (result);
7520 rs6000_parm_needs_stack (args_so_far, result);
7521 }
7522
7523 if (incoming)
7524 {
7525 tree parm;
7526
7527 for (parm = DECL_ARGUMENTS (fun);
7528 parm && parm != void_list_node;
7529 parm = TREE_CHAIN (parm))
7530 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
7531 return true;
7532 }
7533 else
7534 {
7535 function_args_iterator args_iter;
7536 tree arg_type;
7537
7538 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
7539 if (rs6000_parm_needs_stack (args_so_far, arg_type))
7540 return true;
7541 }
7542
7543 return false;
7544}
7545
7546/* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
7547 usually a constant depending on the ABI. However, in the ELFv2 ABI
7548 the register parameter area is optional when calling a function that
7549 has a prototype is scope, has no variable argument list, and passes
7550 all parameters in registers. */
7551
7552int
7553rs6000_reg_parm_stack_space (tree fun, bool incoming)
7554{
7555 int reg_parm_stack_space;
7556
7557 switch (DEFAULT_ABI)
7558 {
7559 default:
7560 reg_parm_stack_space = 0;
7561 break;
7562
7563 case ABI_AIX:
7564 case ABI_DARWIN:
7565 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
7566 break;
7567
7568 case ABI_ELFv2:
7569 /* ??? Recomputing this every time is a bit expensive. Is there
7570 a place to cache this information? */
7571 if (rs6000_function_parms_need_stack (fun, incoming))
7572 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
7573 else
7574 reg_parm_stack_space = 0;
7575 break;
7576 }
7577
7578 return reg_parm_stack_space;
7579}
7580
7581static void
7582rs6000_move_block_from_reg (int regno, rtx x, int nregs)
7583{
7584 int i;
7585 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
7586
7587 if (nregs == 0)
7588 return;
7589
7590 for (i = 0; i < nregs; i++)
7591 {
7592 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
7593 if (reload_completed)
7594 {
7595 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
7596 tem = NULL_RTX;
7597 else
7598 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
7599 i * GET_MODE_SIZE (reg_mode));
7600 }
7601 else
7602 tem = replace_equiv_address (tem, XEXP (tem, 0));
7603
7604 gcc_assert (tem);
7605
7606 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
7607 }
7608}
7609\f
7610/* Perform any needed actions needed for a function that is receiving a
7611 variable number of arguments.
7612
7613 CUM is as above.
7614
e7056ca4 7615 ARG is the last named argument.
1acf0246
BS		 7616
7617 PRETEND_SIZE is a variable that should be set to the amount of stack
7618 that must be pushed by the prolog to pretend that our caller pushed
7619 it.
7620
7621 Normally, this macro will push all remaining incoming registers on the
7622 stack and set PRETEND_SIZE to the length of the registers pushed. */
7623
7624void
e7056ca4
RS		 7625setup_incoming_varargs (cumulative_args_t cum,
7626 const function_arg_info &arg,
7627 int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
1acf0246
BS		 7628{
7629 CUMULATIVE_ARGS next_cum;
7630 int reg_size = TARGET_32BIT ? 4 : 8;
7631 rtx save_area = NULL_RTX, mem;
7632 int first_reg_offset;
7633 alias_set_type set;
7634
7635 /* Skip the last named argument. */
7636 next_cum = *get_cumulative_args (cum);
e7056ca4 7637 rs6000_function_arg_advance_1 (&next_cum, arg.mode, arg.type, arg.named, 0);
1acf0246
BS		 7638
7639 if (DEFAULT_ABI == ABI_V4)
7640 {
7641 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
7642
7643 if (! no_rtl)
7644 {
7645 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
7646 HOST_WIDE_INT offset = 0;
7647
7648 /* Try to optimize the size of the varargs save area.
7649 The ABI requires that ap.reg_save_area is doubleword
7650 aligned, but we don't need to allocate space for all
7651 the bytes, only those to which we actually will save
7652 anything. */
7653 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
7654 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
7655 if (TARGET_HARD_FLOAT
7656 && next_cum.fregno <= FP_ARG_V4_MAX_REG
7657 && cfun->va_list_fpr_size)
7658 {
7659 if (gpr_reg_num)
7660 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
7661 * UNITS_PER_FP_WORD;
7662 if (cfun->va_list_fpr_size
7663 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
7664 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
7665 else
7666 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
7667 * UNITS_PER_FP_WORD;
7668 }
7669 if (gpr_reg_num)
7670 {
7671 offset = -((first_reg_offset * reg_size) & ~7);
7672 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
7673 {
7674 gpr_reg_num = cfun->va_list_gpr_size;
7675 if (reg_size == 4 && (first_reg_offset & 1))
7676 gpr_reg_num++;
7677 }
7678 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
7679 }
7680 else if (fpr_size)
7681 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
7682 * UNITS_PER_FP_WORD
7683 - (int) (GP_ARG_NUM_REG * reg_size);
7684
7685 if (gpr_size + fpr_size)
7686 {
7687 rtx reg_save_area
7688 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
7689 gcc_assert (MEM_P (reg_save_area));
7690 reg_save_area = XEXP (reg_save_area, 0);
7691 if (GET_CODE (reg_save_area) == PLUS)
7692 {
7693 gcc_assert (XEXP (reg_save_area, 0)
7694 == virtual_stack_vars_rtx);
7695 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
7696 offset += INTVAL (XEXP (reg_save_area, 1));
7697 }
7698 else
7699 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
7700 }
7701
7702 cfun->machine->varargs_save_offset = offset;
7703 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
7704 }
7705 }
7706 else
7707 {
7708 first_reg_offset = next_cum.words;
7709 save_area = crtl->args.internal_arg_pointer;
7710
0ffef200 7711 if (targetm.calls.must_pass_in_stack (arg))
e7056ca4 7712 first_reg_offset += rs6000_arg_size (TYPE_MODE (arg.type), arg.type);
1acf0246
BS		 7713 }
7714
7715 set = get_varargs_alias_set ();
7716 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
7717 && cfun->va_list_gpr_size)
7718 {
7719 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
7720
7721 if (va_list_gpr_counter_field)
7722 /* V4 va_list_gpr_size counts number of registers needed. */
7723 n_gpr = cfun->va_list_gpr_size;
7724 else
7725 /* char * va_list instead counts number of bytes needed. */
7726 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
7727
7728 if (nregs > n_gpr)
7729 nregs = n_gpr;
7730
7731 mem = gen_rtx_MEM (BLKmode,
7732 plus_constant (Pmode, save_area,
7733 first_reg_offset * reg_size));
7734 MEM_NOTRAP_P (mem) = 1;
7735 set_mem_alias_set (mem, set);
7736 set_mem_align (mem, BITS_PER_WORD);
7737
7738 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
7739 nregs);
7740 }
7741
7742 /* Save FP registers if needed. */
7743 if (DEFAULT_ABI == ABI_V4
7744 && TARGET_HARD_FLOAT
7745 && ! no_rtl
7746 && next_cum.fregno <= FP_ARG_V4_MAX_REG
7747 && cfun->va_list_fpr_size)
7748 {
7749 int fregno = next_cum.fregno, nregs;
7750 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
7751 rtx lab = gen_label_rtx ();
7752 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
7753 * UNITS_PER_FP_WORD);
7754
7755 emit_jump_insn
7756 (gen_rtx_SET (pc_rtx,
7757 gen_rtx_IF_THEN_ELSE (VOIDmode,
7758 gen_rtx_NE (VOIDmode, cr1,
7759 const0_rtx),
7760 gen_rtx_LABEL_REF (VOIDmode, lab),
7761 pc_rtx)));
7762
7763 for (nregs = 0;
7764 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
7765 fregno++, off += UNITS_PER_FP_WORD, nregs++)
7766 {
7767 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
7768 plus_constant (Pmode, save_area, off));
7769 MEM_NOTRAP_P (mem) = 1;
7770 set_mem_alias_set (mem, set);
7771 set_mem_align (mem, GET_MODE_ALIGNMENT (
7772 TARGET_HARD_FLOAT ? DFmode : SFmode));
7773 emit_move_insn (mem, gen_rtx_REG (
7774 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
7775 }
7776
7777 emit_label (lab);
7778 }
7779}
7780
7781/* Create the va_list data type. */
7782
7783tree
7784rs6000_build_builtin_va_list (void)
7785{
7786 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
7787
7788 /* For AIX, prefer 'char *' because that's what the system
7789 header files like. */
7790 if (DEFAULT_ABI != ABI_V4)
7791 return build_pointer_type (char_type_node);
7792
7793 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7794 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
7795 get_identifier ("__va_list_tag"), record);
7796
7797 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
7798 unsigned_char_type_node);
7799 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
7800 unsigned_char_type_node);
7801 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
7802 every user file. */
7803 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
7804 get_identifier ("reserved"), short_unsigned_type_node);
7805 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
7806 get_identifier ("overflow_arg_area"),
7807 ptr_type_node);
7808 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
7809 get_identifier ("reg_save_area"),
7810 ptr_type_node);
7811
7812 va_list_gpr_counter_field = f_gpr;
7813 va_list_fpr_counter_field = f_fpr;
7814
7815 DECL_FIELD_CONTEXT (f_gpr) = record;
7816 DECL_FIELD_CONTEXT (f_fpr) = record;
7817 DECL_FIELD_CONTEXT (f_res) = record;
7818 DECL_FIELD_CONTEXT (f_ovf) = record;
7819 DECL_FIELD_CONTEXT (f_sav) = record;
7820
7821 TYPE_STUB_DECL (record) = type_decl;
7822 TYPE_NAME (record) = type_decl;
7823 TYPE_FIELDS (record) = f_gpr;
7824 DECL_CHAIN (f_gpr) = f_fpr;
7825 DECL_CHAIN (f_fpr) = f_res;
7826 DECL_CHAIN (f_res) = f_ovf;
7827 DECL_CHAIN (f_ovf) = f_sav;
7828
7829 layout_type (record);
7830
7831 /* The correct type is an array type of one element. */
7832 return build_array_type (record, build_index_type (size_zero_node));
7833}
7834
7835/* Implement va_start. */
7836
7837void
7838rs6000_va_start (tree valist, rtx nextarg)
7839{
7840 HOST_WIDE_INT words, n_gpr, n_fpr;
7841 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
7842 tree gpr, fpr, ovf, sav, t;
7843
7844 /* Only SVR4 needs something special. */
7845 if (DEFAULT_ABI != ABI_V4)
7846 {
7847 std_expand_builtin_va_start (valist, nextarg);
7848 return;
7849 }
7850
7851 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7852 f_fpr = DECL_CHAIN (f_gpr);
7853 f_res = DECL_CHAIN (f_fpr);
7854 f_ovf = DECL_CHAIN (f_res);
7855 f_sav = DECL_CHAIN (f_ovf);
7856
7857 valist = build_simple_mem_ref (valist);
7858 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7859 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
7860 f_fpr, NULL_TREE);
7861 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
7862 f_ovf, NULL_TREE);
7863 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
7864 f_sav, NULL_TREE);
7865
7866 /* Count number of gp and fp argument registers used. */
7867 words = crtl->args.info.words;
7868 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
7869 GP_ARG_NUM_REG);
7870 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
7871 FP_ARG_NUM_REG);
7872
7873 if (TARGET_DEBUG_ARG)
7874 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
7875 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
7876 words, n_gpr, n_fpr);
7877
7878 if (cfun->va_list_gpr_size)
7879 {
7880 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7881 build_int_cst (NULL_TREE, n_gpr));
7882 TREE_SIDE_EFFECTS (t) = 1;
7883 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7884 }
7885
7886 if (cfun->va_list_fpr_size)
7887 {
7888 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7889 build_int_cst (NULL_TREE, n_fpr));
7890 TREE_SIDE_EFFECTS (t) = 1;
7891 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7892
7893#ifdef HAVE_AS_GNU_ATTRIBUTE
7894 if (call_ABI_of_interest (cfun->decl))
7895 rs6000_passes_float = true;
7896#endif
7897 }
7898
7899 /* Find the overflow area. */
7900 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
7901 if (words != 0)
7902 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
7903 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7904 TREE_SIDE_EFFECTS (t) = 1;
7905 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7906
7907 /* If there were no va_arg invocations, don't set up the register
7908 save area. */
7909 if (!cfun->va_list_gpr_size
7910 && !cfun->va_list_fpr_size
7911 && n_gpr < GP_ARG_NUM_REG
7912 && n_fpr < FP_ARG_V4_MAX_REG)
7913 return;
7914
7915 /* Find the register save area. */
7916 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
7917 if (cfun->machine->varargs_save_offset)
7918 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
7919 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7920 TREE_SIDE_EFFECTS (t) = 1;
7921 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7922}
7923
7924/* Implement va_arg. */
7925
7926tree
7927rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
7928 gimple_seq *post_p)
7929{
7930 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
7931 tree gpr, fpr, ovf, sav, reg, t, u;
7932 int size, rsize, n_reg, sav_ofs, sav_scale;
7933 tree lab_false, lab_over, addr;
7934 int align;
7935 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
7936 int regalign = 0;
7937 gimple *stmt;
7938
fde65a89 7939 if (pass_va_arg_by_reference (type))
1acf0246
BS		 7940 {
7941 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
7942 return build_va_arg_indirect_ref (t);
7943 }
7944
7945 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
7946 earlier version of gcc, with the property that it always applied alignment
7947 adjustments to the va-args (even for zero-sized types). The cheapest way
7948 to deal with this is to replicate the effect of the part of
7949 std_gimplify_va_arg_expr that carries out the align adjust, for the case
7950 of relevance.
7951 We don't need to check for pass-by-reference because of the test above.
7952 We can return a simplifed answer, since we know there's no offset to add. */
7953
7954 if (((TARGET_MACHO
7955 && rs6000_darwin64_abi)
7956 || DEFAULT_ABI == ABI_ELFv2
7957 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
7958 && integer_zerop (TYPE_SIZE (type)))
7959 {
7960 unsigned HOST_WIDE_INT align, boundary;
7961 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
7962 align = PARM_BOUNDARY / BITS_PER_UNIT;
7963 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
7964 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7965 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7966 boundary /= BITS_PER_UNIT;
7967 if (boundary > align)
7968 {
7969 tree t ;
7970 /* This updates arg ptr by the amount that would be necessary
7971 to align the zero-sized (but not zero-alignment) item. */
7972 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
7973 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
7974 gimplify_and_add (t, pre_p);
7975
7976 t = fold_convert (sizetype, valist_tmp);
7977 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
7978 fold_convert (TREE_TYPE (valist),
7979 fold_build2 (BIT_AND_EXPR, sizetype, t,
7980 size_int (-boundary))));
7981 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
7982 gimplify_and_add (t, pre_p);
7983 }
7984 /* Since it is zero-sized there's no increment for the item itself. */
7985 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
7986 return build_va_arg_indirect_ref (valist_tmp);
7987 }
7988
7989 if (DEFAULT_ABI != ABI_V4)
7990 {
7991 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
7992 {
7993 tree elem_type = TREE_TYPE (type);
7994 machine_mode elem_mode = TYPE_MODE (elem_type);
7995 int elem_size = GET_MODE_SIZE (elem_mode);
7996
7997 if (elem_size < UNITS_PER_WORD)
7998 {
7999 tree real_part, imag_part;
8000 gimple_seq post = NULL;
8001
8002 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
8003 &post);
8004 /* Copy the value into a temporary, lest the formal temporary
8005 be reused out from under us. */
8006 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
8007 gimple_seq_add_seq (pre_p, post);
8008
8009 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
8010 post_p);
8011
8012 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
8013 }
8014 }
8015
8016 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
8017 }
8018
8019 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8020 f_fpr = DECL_CHAIN (f_gpr);
8021 f_res = DECL_CHAIN (f_fpr);
8022 f_ovf = DECL_CHAIN (f_res);
8023 f_sav = DECL_CHAIN (f_ovf);
8024
8025 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8026 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
8027 f_fpr, NULL_TREE);
8028 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
8029 f_ovf, NULL_TREE);
8030 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
8031 f_sav, NULL_TREE);
8032
8033 size = int_size_in_bytes (type);
8034 rsize = (size + 3) / 4;
8035 int pad = 4 * rsize - size;
8036 align = 1;
8037
8038 machine_mode mode = TYPE_MODE (type);
8039 if (abi_v4_pass_in_fpr (mode, false))
8040 {
8041 /* FP args go in FP registers, if present. */
8042 reg = fpr;
8043 n_reg = (size + 7) / 8;
8044 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
8045 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
8046 if (mode != SFmode && mode != SDmode)
8047 align = 8;
8048 }
8049 else
8050 {
8051 /* Otherwise into GP registers. */
8052 reg = gpr;
8053 n_reg = rsize;
8054 sav_ofs = 0;
8055 sav_scale = 4;
8056 if (n_reg == 2)
8057 align = 8;
8058 }
8059
8060 /* Pull the value out of the saved registers.... */
8061
8062 lab_over = NULL;
8063 addr = create_tmp_var (ptr_type_node, "addr");
8064
8065 /* AltiVec vectors never go in registers when -mabi=altivec. */
8066 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8067 align = 16;
8068 else
8069 {
8070 lab_false = create_artificial_label (input_location);
8071 lab_over = create_artificial_label (input_location);
8072
8073 /* Long long is aligned in the registers. As are any other 2 gpr
8074 item such as complex int due to a historical mistake. */
8075 u = reg;
8076 if (n_reg == 2 && reg == gpr)
8077 {
8078 regalign = 1;
8079 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8080 build_int_cst (TREE_TYPE (reg), n_reg - 1));
8081 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
8082 unshare_expr (reg), u);
8083 }
8084 /* _Decimal128 is passed in even/odd fpr pairs; the stored
8085 reg number is 0 for f1, so we want to make it odd. */
8086 else if (reg == fpr && mode == TDmode)
8087 {
8088 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8089 build_int_cst (TREE_TYPE (reg), 1));
8090 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
8091 }
8092
8093 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
8094 t = build2 (GE_EXPR, boolean_type_node, u, t);
8095 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8096 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8097 gimplify_and_add (t, pre_p);
8098
8099 t = sav;
8100 if (sav_ofs)
8101 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
8102
8103 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8104 build_int_cst (TREE_TYPE (reg), n_reg));
8105 u = fold_convert (sizetype, u);
8106 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
8107 t = fold_build_pointer_plus (t, u);
8108
8109 /* _Decimal32 varargs are located in the second word of the 64-bit
8110 FP register for 32-bit binaries. */
8111 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
8112 t = fold_build_pointer_plus_hwi (t, size);
8113
8114 /* Args are passed right-aligned. */
8115 if (BYTES_BIG_ENDIAN)
8116 t = fold_build_pointer_plus_hwi (t, pad);
8117
8118 gimplify_assign (addr, t, pre_p);
8119
8120 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8121
8122 stmt = gimple_build_label (lab_false);
8123 gimple_seq_add_stmt (pre_p, stmt);
8124
8125 if ((n_reg == 2 && !regalign) || n_reg > 2)
8126 {
8127 /* Ensure that we don't find any more args in regs.
8128 Alignment has taken care of for special cases. */
8129 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
8130 }
8131 }
8132
8133 /* ... otherwise out of the overflow area. */
8134
8135 /* Care for on-stack alignment if needed. */
8136 t = ovf;
8137 if (align != 1)
8138 {
8139 t = fold_build_pointer_plus_hwi (t, align - 1);
8140 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
8141 build_int_cst (TREE_TYPE (t), -align));
8142 }
8143
8144 /* Args are passed right-aligned. */
8145 if (BYTES_BIG_ENDIAN)
8146 t = fold_build_pointer_plus_hwi (t, pad);
8147
8148 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8149
8150 gimplify_assign (unshare_expr (addr), t, pre_p);
8151
8152 t = fold_build_pointer_plus_hwi (t, size);
8153 gimplify_assign (unshare_expr (ovf), t, pre_p);
8154
8155 if (lab_over)
8156 {
8157 stmt = gimple_build_label (lab_over);
8158 gimple_seq_add_stmt (pre_p, stmt);
8159 }
8160
8161 if (STRICT_ALIGNMENT
8162 && (TYPE_ALIGN (type)
8163 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
8164 {
8165 /* The value (of type complex double, for example) may not be
8166 aligned in memory in the saved registers, so copy via a
8167 temporary. (This is the same code as used for SPARC.) */
8168 tree tmp = create_tmp_var (type, "va_arg_tmp");
8169 tree dest_addr = build_fold_addr_expr (tmp);
8170
8171 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
8172 3, dest_addr, addr, size_int (rsize * 4));
8173 TREE_ADDRESSABLE (tmp) = 1;
8174
8175 gimplify_and_add (copy, pre_p);
8176 addr = dest_addr;
8177 }
8178
8179 addr = fold_convert (ptrtype, addr);
8180 return build_va_arg_indirect_ref (addr);
8181}
8182
8183/* Builtins. */
8184
8185static void
8186def_builtin (const char *name, tree type, enum rs6000_builtins code)
8187{
8188 tree t;
8189 unsigned classify = rs6000_builtin_info[(int)code].attr;
8190 const char *attr_string = "";
8191
a92cc0da
PB		 8192 /* Don't define the builtin if it doesn't have a type. See PR92661. */
8193 if (type == NULL_TREE)
8194 return;
8195
1acf0246
BS		 8196 gcc_assert (name != NULL);
8197 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
8198
8199 if (rs6000_builtin_decls[(int)code])
8200 fatal_error (input_location,
8201 "internal error: builtin function %qs already processed",
8202 name);
8203
8204 rs6000_builtin_decls[(int)code] = t =
8205 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
8206
8207 /* Set any special attributes. */
8208 if ((classify & RS6000_BTC_CONST) != 0)
8209 {
8210 /* const function, function only depends on the inputs. */
8211 TREE_READONLY (t) = 1;
8212 TREE_NOTHROW (t) = 1;
8213 attr_string = ", const";
8214 }
8215 else if ((classify & RS6000_BTC_PURE) != 0)
8216 {
8217 /* pure function, function can read global memory, but does not set any
8218 external state. */
8219 DECL_PURE_P (t) = 1;
8220 TREE_NOTHROW (t) = 1;
8221 attr_string = ", pure";
8222 }
8223 else if ((classify & RS6000_BTC_FP) != 0)
8224 {
8225 /* Function is a math function. If rounding mode is on, then treat the
8226 function as not reading global memory, but it can have arbitrary side
8227 effects. If it is off, then assume the function is a const function.
8228 This mimics the ATTR_MATHFN_FPROUNDING attribute in
8229 builtin-attribute.def that is used for the math functions. */
8230 TREE_NOTHROW (t) = 1;
8231 if (flag_rounding_math)
8232 {
8233 DECL_PURE_P (t) = 1;
8234 DECL_IS_NOVOPS (t) = 1;
8235 attr_string = ", fp, pure";
8236 }
8237 else
8238 {
8239 TREE_READONLY (t) = 1;
8240 attr_string = ", fp, const";
8241 }
8242 }
8243 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
8244 gcc_unreachable ();
8245
8246 if (TARGET_DEBUG_BUILTIN)
8247 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
8248 (int)code, name, attr_string);
8249}
8250
8251/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
8252
8253#undef RS6000_BUILTIN_0
8254#undef RS6000_BUILTIN_1
8255#undef RS6000_BUILTIN_2
8256#undef RS6000_BUILTIN_3
8257#undef RS6000_BUILTIN_A
8258#undef RS6000_BUILTIN_D
8259#undef RS6000_BUILTIN_H
8260#undef RS6000_BUILTIN_P
8261#undef RS6000_BUILTIN_X
8262
8263#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8264#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8265#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8266#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
8267 { MASK, ICODE, NAME, ENUM },
8268
8269#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8270#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8271#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8272#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8273#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8274
8275static const struct builtin_description bdesc_3arg[] =
8276{
8277#include "rs6000-builtin.def"
8278};
8279
8280/* DST operations: void foo (void *, const int, const char). */
8281
8282#undef RS6000_BUILTIN_0
8283#undef RS6000_BUILTIN_1
8284#undef RS6000_BUILTIN_2
8285#undef RS6000_BUILTIN_3
8286#undef RS6000_BUILTIN_A
8287#undef RS6000_BUILTIN_D
8288#undef RS6000_BUILTIN_H
8289#undef RS6000_BUILTIN_P
8290#undef RS6000_BUILTIN_X
8291
8292#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8293#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8294#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8295#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8296#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8297#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
8298 { MASK, ICODE, NAME, ENUM },
8299
8300#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8301#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8302#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8303
8304static const struct builtin_description bdesc_dst[] =
8305{
8306#include "rs6000-builtin.def"
8307};
8308
8309/* Simple binary operations: VECc = foo (VECa, VECb). */
8310
8311#undef RS6000_BUILTIN_0
8312#undef RS6000_BUILTIN_1
8313#undef RS6000_BUILTIN_2
8314#undef RS6000_BUILTIN_3
8315#undef RS6000_BUILTIN_A
8316#undef RS6000_BUILTIN_D
8317#undef RS6000_BUILTIN_H
8318#undef RS6000_BUILTIN_P
8319#undef RS6000_BUILTIN_X
8320
8321#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8322#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8323#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
8324 { MASK, ICODE, NAME, ENUM },
8325
8326#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8327#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8328#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8329#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8330#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8331#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8332
8333static const struct builtin_description bdesc_2arg[] =
8334{
8335#include "rs6000-builtin.def"
8336};
8337
8338#undef RS6000_BUILTIN_0
8339#undef RS6000_BUILTIN_1
8340#undef RS6000_BUILTIN_2
8341#undef RS6000_BUILTIN_3
8342#undef RS6000_BUILTIN_A
8343#undef RS6000_BUILTIN_D
8344#undef RS6000_BUILTIN_H
8345#undef RS6000_BUILTIN_P
8346#undef RS6000_BUILTIN_X
8347
8348#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8349#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8350#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8351#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8352#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8353#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8354#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8355#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
8356 { MASK, ICODE, NAME, ENUM },
8357
8358#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8359
8360/* AltiVec predicates. */
8361
8362static const struct builtin_description bdesc_altivec_preds[] =
8363{
8364#include "rs6000-builtin.def"
8365};
8366
8367/* ABS* operations. */
8368
8369#undef RS6000_BUILTIN_0
8370#undef RS6000_BUILTIN_1
8371#undef RS6000_BUILTIN_2
8372#undef RS6000_BUILTIN_3
8373#undef RS6000_BUILTIN_A
8374#undef RS6000_BUILTIN_D
8375#undef RS6000_BUILTIN_H
8376#undef RS6000_BUILTIN_P
8377#undef RS6000_BUILTIN_X
8378
8379#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8380#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8381#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8382#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8383#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
8384 { MASK, ICODE, NAME, ENUM },
8385
8386#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8387#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8388#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8389#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8390
8391static const struct builtin_description bdesc_abs[] =
8392{
8393#include "rs6000-builtin.def"
8394};
8395
8396/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
8397 foo (VECa). */
8398
8399#undef RS6000_BUILTIN_0
8400#undef RS6000_BUILTIN_1
8401#undef RS6000_BUILTIN_2
8402#undef RS6000_BUILTIN_3
8403#undef RS6000_BUILTIN_A
8404#undef RS6000_BUILTIN_D
8405#undef RS6000_BUILTIN_H
8406#undef RS6000_BUILTIN_P
8407#undef RS6000_BUILTIN_X
8408
8409#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8410#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
8411 { MASK, ICODE, NAME, ENUM },
8412
8413#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8414#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8415#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8416#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8417#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8418#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8419#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8420
8421static const struct builtin_description bdesc_1arg[] =
8422{
8423#include "rs6000-builtin.def"
8424};
8425
8426/* Simple no-argument operations: result = __builtin_darn_32 () */
8427
8428#undef RS6000_BUILTIN_0
8429#undef RS6000_BUILTIN_1
8430#undef RS6000_BUILTIN_2
8431#undef RS6000_BUILTIN_3
8432#undef RS6000_BUILTIN_A
8433#undef RS6000_BUILTIN_D
8434#undef RS6000_BUILTIN_H
8435#undef RS6000_BUILTIN_P
8436#undef RS6000_BUILTIN_X
8437
8438#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
8439 { MASK, ICODE, NAME, ENUM },
8440
8441#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8442#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8443#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8444#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8445#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8446#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8447#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8448#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8449
8450static const struct builtin_description bdesc_0arg[] =
8451{
8452#include "rs6000-builtin.def"
8453};
8454
8455/* HTM builtins. */
8456#undef RS6000_BUILTIN_0
8457#undef RS6000_BUILTIN_1
8458#undef RS6000_BUILTIN_2
8459#undef RS6000_BUILTIN_3
8460#undef RS6000_BUILTIN_A
8461#undef RS6000_BUILTIN_D
8462#undef RS6000_BUILTIN_H
8463#undef RS6000_BUILTIN_P
8464#undef RS6000_BUILTIN_X
8465
8466#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8467#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8468#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8469#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8470#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8471#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8472#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
8473 { MASK, ICODE, NAME, ENUM },
8474
8475#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8476#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8477
8478static const struct builtin_description bdesc_htm[] =
8479{
8480#include "rs6000-builtin.def"
8481};
8482
8483#undef RS6000_BUILTIN_0
8484#undef RS6000_BUILTIN_1
8485#undef RS6000_BUILTIN_2
8486#undef RS6000_BUILTIN_3
8487#undef RS6000_BUILTIN_A
8488#undef RS6000_BUILTIN_D
8489#undef RS6000_BUILTIN_H
8490#undef RS6000_BUILTIN_P
8491
8492/* Return true if a builtin function is overloaded. */
8493bool
8494rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
8495{
8496 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
8497}
8498
8499const char *
8500rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
8501{
8502 return rs6000_builtin_info[(int)fncode].name;
8503}
8504
8505/* Expand an expression EXP that calls a builtin without arguments. */
8506static rtx
8507rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
8508{
8509 rtx pat;
8510 machine_mode tmode = insn_data[icode].operand[0].mode;
8511
8512 if (icode == CODE_FOR_nothing)
8513 /* Builtin not supported on this processor. */
8514 return 0;
8515
8516 if (icode == CODE_FOR_rs6000_mffsl
8517 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
8518 {
8519 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
8520 return const0_rtx;
8521 }
8522
8523 if (target == 0
8524 || GET_MODE (target) != tmode
8525 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8526 target = gen_reg_rtx (tmode);
8527
8528 pat = GEN_FCN (icode) (target);
8529 if (! pat)
8530 return 0;
8531 emit_insn (pat);
8532
8533 return target;
8534}
8535
8536
8537static rtx
8538rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
8539{
8540 rtx pat;
8541 tree arg0 = CALL_EXPR_ARG (exp, 0);
8542 tree arg1 = CALL_EXPR_ARG (exp, 1);
8543 rtx op0 = expand_normal (arg0);
8544 rtx op1 = expand_normal (arg1);
8545 machine_mode mode0 = insn_data[icode].operand[0].mode;
8546 machine_mode mode1 = insn_data[icode].operand[1].mode;
8547
8548 if (icode == CODE_FOR_nothing)
8549 /* Builtin not supported on this processor. */
8550 return 0;
8551
8552 /* If we got invalid arguments bail out before generating bad rtl. */
8553 if (arg0 == error_mark_node || arg1 == error_mark_node)
8554 return const0_rtx;
8555
8556 if (!CONST_INT_P (op0)
8557 || INTVAL (op0) > 255
8558 || INTVAL (op0) < 0)
8559 {
8560 error ("argument 1 must be an 8-bit field value");
8561 return const0_rtx;
8562 }
8563
8564 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8565 op0 = copy_to_mode_reg (mode0, op0);
8566
8567 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8568 op1 = copy_to_mode_reg (mode1, op1);
8569
8570 pat = GEN_FCN (icode) (op0, op1);
8571 if (!pat)
8572 return const0_rtx;
8573 emit_insn (pat);
8574
8575 return NULL_RTX;
8576}
8577
8578static rtx
8579rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
8580{
8581 rtx pat;
8582 tree arg0 = CALL_EXPR_ARG (exp, 0);
8583 rtx op0 = expand_normal (arg0);
8584
8585 if (icode == CODE_FOR_nothing)
8586 /* Builtin not supported on this processor. */
8587 return 0;
8588
8589 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
8590 {
8591 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
8592 "%<-msoft-float%>");
8593 return const0_rtx;
8594 }
8595
8596 /* If we got invalid arguments bail out before generating bad rtl. */
8597 if (arg0 == error_mark_node)
8598 return const0_rtx;
8599
8600 /* Only allow bit numbers 0 to 31. */
8601 if (!u5bit_cint_operand (op0, VOIDmode))
8602 {
8603 error ("Argument must be a constant between 0 and 31.");
8604 return const0_rtx;
8605 }
8606
8607 pat = GEN_FCN (icode) (op0);
8608 if (!pat)
8609 return const0_rtx;
8610 emit_insn (pat);
8611
8612 return NULL_RTX;
8613}
8614
8615static rtx
8616rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
8617{
8618 rtx pat;
8619 tree arg0 = CALL_EXPR_ARG (exp, 0);
8620 rtx op0 = expand_normal (arg0);
8621 machine_mode mode0 = insn_data[icode].operand[0].mode;
8622
8623 if (icode == CODE_FOR_nothing)
8624 /* Builtin not supported on this processor. */
8625 return 0;
8626
8627 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
8628 {
8629 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
8630 return const0_rtx;
8631 }
8632
8633 /* If we got invalid arguments bail out before generating bad rtl. */
8634 if (arg0 == error_mark_node)
8635 return const0_rtx;
8636
8637 /* If the argument is a constant, check the range. Argument can only be a
8638 2-bit value. Unfortunately, can't check the range of the value at
8639 compile time if the argument is a variable. The least significant two
8640 bits of the argument, regardless of type, are used to set the rounding
8641 mode. All other bits are ignored. */
8642 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
8643 {
8644 error ("Argument must be a value between 0 and 3.");
8645 return const0_rtx;
8646 }
8647
8648 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8649 op0 = copy_to_mode_reg (mode0, op0);
8650
8651 pat = GEN_FCN (icode) (op0);
8652 if (!pat)
8653 return const0_rtx;
8654 emit_insn (pat);
8655
8656 return NULL_RTX;
8657}
8658static rtx
8659rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
8660{
8661 rtx pat;
8662 tree arg0 = CALL_EXPR_ARG (exp, 0);
8663 rtx op0 = expand_normal (arg0);
8664 machine_mode mode0 = insn_data[icode].operand[0].mode;
8665
8666 if (TARGET_32BIT)
8667 /* Builtin not supported in 32-bit mode. */
8668 fatal_error (input_location,
8669 "%<__builtin_set_fpscr_drn%> is not supported "
8670 "in 32-bit mode");
8671
8672 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
8673 {
8674 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
8675 return const0_rtx;
8676 }
8677
8678 if (icode == CODE_FOR_nothing)
8679 /* Builtin not supported on this processor. */
8680 return 0;
8681
8682 /* If we got invalid arguments bail out before generating bad rtl. */
8683 if (arg0 == error_mark_node)
8684 return const0_rtx;
8685
8686 /* If the argument is a constant, check the range. Agrument can only be a
8687 3-bit value. Unfortunately, can't check the range of the value at
8688 compile time if the argument is a variable. The least significant two
8689 bits of the argument, regardless of type, are used to set the rounding
8690 mode. All other bits are ignored. */
8691 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode))
8692 {
8693 error ("Argument must be a value between 0 and 7.");
8694 return const0_rtx;
8695 }
8696
8697 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8698 op0 = copy_to_mode_reg (mode0, op0);
8699
8700 pat = GEN_FCN (icode) (op0);
8701 if (! pat)
8702 return const0_rtx;
8703 emit_insn (pat);
8704
8705 return NULL_RTX;
8706}
8707
8708static rtx
8709rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
8710{
8711 rtx pat;
8712 tree arg0 = CALL_EXPR_ARG (exp, 0);
8713 rtx op0 = expand_normal (arg0);
8714 machine_mode tmode = insn_data[icode].operand[0].mode;
8715 machine_mode mode0 = insn_data[icode].operand[1].mode;
8716
8717 if (icode == CODE_FOR_nothing)
8718 /* Builtin not supported on this processor. */
8719 return 0;
8720
8721 /* If we got invalid arguments bail out before generating bad rtl. */
8722 if (arg0 == error_mark_node)
8723 return const0_rtx;
8724
8725 if (icode == CODE_FOR_altivec_vspltisb
8726 || icode == CODE_FOR_altivec_vspltish
8727 || icode == CODE_FOR_altivec_vspltisw)
8728 {
8729 /* Only allow 5-bit *signed* literals. */
8730 if (!CONST_INT_P (op0)
8731 || INTVAL (op0) > 15
8732 || INTVAL (op0) < -16)
8733 {
8734 error ("argument 1 must be a 5-bit signed literal");
8735 return CONST0_RTX (tmode);
8736 }
8737 }
8738
8739 if (target == 0
8740 || GET_MODE (target) != tmode
8741 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8742 target = gen_reg_rtx (tmode);
8743
8744 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8745 op0 = copy_to_mode_reg (mode0, op0);
8746
8747 pat = GEN_FCN (icode) (target, op0);
8748 if (! pat)
8749 return 0;
8750 emit_insn (pat);
8751
8752 return target;
8753}
8754
8755static rtx
8756altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
8757{
8758 rtx pat, scratch1, scratch2;
8759 tree arg0 = CALL_EXPR_ARG (exp, 0);
8760 rtx op0 = expand_normal (arg0);
8761 machine_mode tmode = insn_data[icode].operand[0].mode;
8762 machine_mode mode0 = insn_data[icode].operand[1].mode;
8763
8764 /* If we have invalid arguments, bail out before generating bad rtl. */
8765 if (arg0 == error_mark_node)
8766 return const0_rtx;
8767
8768 if (target == 0
8769 || GET_MODE (target) != tmode
8770 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8771 target = gen_reg_rtx (tmode);
8772
8773 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8774 op0 = copy_to_mode_reg (mode0, op0);
8775
8776 scratch1 = gen_reg_rtx (mode0);
8777 scratch2 = gen_reg_rtx (mode0);
8778
8779 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
8780 if (! pat)
8781 return 0;
8782 emit_insn (pat);
8783
8784 return target;
8785}
8786
8787static rtx
8788rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
8789{
8790 rtx pat;
8791 tree arg0 = CALL_EXPR_ARG (exp, 0);
8792 tree arg1 = CALL_EXPR_ARG (exp, 1);
8793 rtx op0 = expand_normal (arg0);
8794 rtx op1 = expand_normal (arg1);
8795 machine_mode tmode = insn_data[icode].operand[0].mode;
8796 machine_mode mode0 = insn_data[icode].operand[1].mode;
8797 machine_mode mode1 = insn_data[icode].operand[2].mode;
8798
8799 if (icode == CODE_FOR_nothing)
8800 /* Builtin not supported on this processor. */
8801 return 0;
8802
8803 /* If we got invalid arguments bail out before generating bad rtl. */
8804 if (arg0 == error_mark_node || arg1 == error_mark_node)
8805 return const0_rtx;
8806
8807 if (icode == CODE_FOR_unpackv1ti
8808 || icode == CODE_FOR_unpackkf
8809 || icode == CODE_FOR_unpacktf
8810 || icode == CODE_FOR_unpackif
8811 || icode == CODE_FOR_unpacktd)
8812 {
8813 /* Only allow 1-bit unsigned literals. */
8814 STRIP_NOPS (arg1);
8815 if (TREE_CODE (arg1) != INTEGER_CST
8816 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
8817 {
8818 error ("argument 2 must be a 1-bit unsigned literal");
8819 return CONST0_RTX (tmode);
8820 }
8821 }
8822 else if (icode == CODE_FOR_altivec_vspltw)
8823 {
8824 /* Only allow 2-bit unsigned literals. */
8825 STRIP_NOPS (arg1);
8826 if (TREE_CODE (arg1) != INTEGER_CST
8827 || TREE_INT_CST_LOW (arg1) & ~3)
8828 {
8829 error ("argument 2 must be a 2-bit unsigned literal");
8830 return CONST0_RTX (tmode);
8831 }
8832 }
8833 else if (icode == CODE_FOR_altivec_vsplth)
8834 {
8835 /* Only allow 3-bit unsigned literals. */
8836 STRIP_NOPS (arg1);
8837 if (TREE_CODE (arg1) != INTEGER_CST
8838 || TREE_INT_CST_LOW (arg1) & ~7)
8839 {
8840 error ("argument 2 must be a 3-bit unsigned literal");
8841 return CONST0_RTX (tmode);
8842 }
8843 }
8844 else if (icode == CODE_FOR_altivec_vspltb)
8845 {
8846 /* Only allow 4-bit unsigned literals. */
8847 STRIP_NOPS (arg1);
8848 if (TREE_CODE (arg1) != INTEGER_CST
8849 || TREE_INT_CST_LOW (arg1) & ~15)
8850 {
8851 error ("argument 2 must be a 4-bit unsigned literal");
8852 return CONST0_RTX (tmode);
8853 }
8854 }
8855 else if (icode == CODE_FOR_altivec_vcfux
8856 || icode == CODE_FOR_altivec_vcfsx
8857 || icode == CODE_FOR_altivec_vctsxs
8858 || icode == CODE_FOR_altivec_vctuxs)
8859 {
8860 /* Only allow 5-bit unsigned literals. */
8861 STRIP_NOPS (arg1);
8862 if (TREE_CODE (arg1) != INTEGER_CST
8863 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8864 {
8865 error ("argument 2 must be a 5-bit unsigned literal");
8866 return CONST0_RTX (tmode);
8867 }
8868 }
8869 else if (icode == CODE_FOR_dfptstsfi_eq_dd
8870 || icode == CODE_FOR_dfptstsfi_lt_dd
8871 || icode == CODE_FOR_dfptstsfi_gt_dd
8872 || icode == CODE_FOR_dfptstsfi_unordered_dd
8873 || icode == CODE_FOR_dfptstsfi_eq_td
8874 || icode == CODE_FOR_dfptstsfi_lt_td
8875 || icode == CODE_FOR_dfptstsfi_gt_td
8876 || icode == CODE_FOR_dfptstsfi_unordered_td)
8877 {
8878 /* Only allow 6-bit unsigned literals. */
8879 STRIP_NOPS (arg0);
8880 if (TREE_CODE (arg0) != INTEGER_CST
8881 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
8882 {
8883 error ("argument 1 must be a 6-bit unsigned literal");
8884 return CONST0_RTX (tmode);
8885 }
8886 }
8887 else if (icode == CODE_FOR_xststdcqp_kf
8888 || icode == CODE_FOR_xststdcqp_tf
8889 || icode == CODE_FOR_xststdcdp
8890 || icode == CODE_FOR_xststdcsp
8891 || icode == CODE_FOR_xvtstdcdp
8892 || icode == CODE_FOR_xvtstdcsp)
8893 {
8894 /* Only allow 7-bit unsigned literals. */
8895 STRIP_NOPS (arg1);
8896 if (TREE_CODE (arg1) != INTEGER_CST
8897 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
8898 {
8899 error ("argument 2 must be a 7-bit unsigned literal");
8900 return CONST0_RTX (tmode);
8901 }
8902 }
8903
8904 if (target == 0
8905 || GET_MODE (target) != tmode
8906 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8907 target = gen_reg_rtx (tmode);
8908
8909 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8910 op0 = copy_to_mode_reg (mode0, op0);
8911 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8912 op1 = copy_to_mode_reg (mode1, op1);
8913
8914 pat = GEN_FCN (icode) (target, op0, op1);
8915 if (! pat)
8916 return 0;
8917 emit_insn (pat);
8918
8919 return target;
8920}
8921
8922static rtx
8923altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8924{
8925 rtx pat, scratch;
8926 tree cr6_form = CALL_EXPR_ARG (exp, 0);
8927 tree arg0 = CALL_EXPR_ARG (exp, 1);
8928 tree arg1 = CALL_EXPR_ARG (exp, 2);
8929 rtx op0 = expand_normal (arg0);
8930 rtx op1 = expand_normal (arg1);
8931 machine_mode tmode = SImode;
8932 machine_mode mode0 = insn_data[icode].operand[1].mode;
8933 machine_mode mode1 = insn_data[icode].operand[2].mode;
8934 int cr6_form_int;
8935
8936 if (TREE_CODE (cr6_form) != INTEGER_CST)
8937 {
8938 error ("argument 1 of %qs must be a constant",
8939 "__builtin_altivec_predicate");
8940 return const0_rtx;
8941 }
8942 else
8943 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
8944
8945 gcc_assert (mode0 == mode1);
8946
8947 /* If we have invalid arguments, bail out before generating bad rtl. */
8948 if (arg0 == error_mark_node || arg1 == error_mark_node)
8949 return const0_rtx;
8950
8951 if (target == 0
8952 || GET_MODE (target) != tmode
8953 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8954 target = gen_reg_rtx (tmode);
8955
8956 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8957 op0 = copy_to_mode_reg (mode0, op0);
8958 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8959 op1 = copy_to_mode_reg (mode1, op1);
8960
8961 /* Note that for many of the relevant operations (e.g. cmpne or
8962 cmpeq) with float or double operands, it makes more sense for the
8963 mode of the allocated scratch register to select a vector of
8964 integer. But the choice to copy the mode of operand 0 was made
8965 long ago and there are no plans to change it. */
8966 scratch = gen_reg_rtx (mode0);
8967
8968 pat = GEN_FCN (icode) (scratch, op0, op1);
8969 if (! pat)
8970 return 0;
8971 emit_insn (pat);
8972
8973 /* The vec_any* and vec_all* predicates use the same opcodes for two
8974 different operations, but the bits in CR6 will be different
8975 depending on what information we want. So we have to play tricks
8976 with CR6 to get the right bits out.
8977
8978 If you think this is disgusting, look at the specs for the
8979 AltiVec predicates. */
8980
8981 switch (cr6_form_int)
8982 {
8983 case 0:
8984 emit_insn (gen_cr6_test_for_zero (target));
8985 break;
8986 case 1:
8987 emit_insn (gen_cr6_test_for_zero_reverse (target));
8988 break;
8989 case 2:
8990 emit_insn (gen_cr6_test_for_lt (target));
8991 break;
8992 case 3:
8993 emit_insn (gen_cr6_test_for_lt_reverse (target));
8994 break;
8995 default:
8996 error ("argument 1 of %qs is out of range",
8997 "__builtin_altivec_predicate");
8998 break;
8999 }
9000
9001 return target;
9002}
9003
9004rtx
9005swap_endian_selector_for_mode (machine_mode mode)
9006{
9007 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
9008 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
9009 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
9010 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
9011
9012 unsigned int *swaparray, i;
9013 rtx perm[16];
9014
9015 switch (mode)
9016 {
9017 case E_V1TImode:
9018 swaparray = swap1;
9019 break;
9020 case E_V2DFmode:
9021 case E_V2DImode:
9022 swaparray = swap2;
9023 break;
9024 case E_V4SFmode:
9025 case E_V4SImode:
9026 swaparray = swap4;
9027 break;
9028 case E_V8HImode:
9029 swaparray = swap8;
9030 break;
9031 default:
9032 gcc_unreachable ();
9033 }
9034
9035 for (i = 0; i < 16; ++i)
9036 perm[i] = GEN_INT (swaparray[i]);
9037
9038 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
9039 gen_rtvec_v (16, perm)));
9040}
9041
9042static rtx
9043altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
9044{
9045 rtx pat, addr;
9046 tree arg0 = CALL_EXPR_ARG (exp, 0);
9047 tree arg1 = CALL_EXPR_ARG (exp, 1);
9048 machine_mode tmode = insn_data[icode].operand[0].mode;
9049 machine_mode mode0 = Pmode;
9050 machine_mode mode1 = Pmode;
9051 rtx op0 = expand_normal (arg0);
9052 rtx op1 = expand_normal (arg1);
9053
9054 if (icode == CODE_FOR_nothing)
9055 /* Builtin not supported on this processor. */
9056 return 0;
9057
9058 /* If we got invalid arguments bail out before generating bad rtl. */
9059 if (arg0 == error_mark_node || arg1 == error_mark_node)
9060 return const0_rtx;
9061
9062 if (target == 0
9063 || GET_MODE (target) != tmode
9064 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9065 target = gen_reg_rtx (tmode);
9066
9067 op1 = copy_to_mode_reg (mode1, op1);
9068
9069 /* For LVX, express the RTL accurately by ANDing the address with -16.
9070 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
9071 so the raw address is fine. */
9072 if (icode == CODE_FOR_altivec_lvx_v1ti
9073 || icode == CODE_FOR_altivec_lvx_v2df
9074 || icode == CODE_FOR_altivec_lvx_v2di
9075 || icode == CODE_FOR_altivec_lvx_v4sf
9076 || icode == CODE_FOR_altivec_lvx_v4si
9077 || icode == CODE_FOR_altivec_lvx_v8hi
9078 || icode == CODE_FOR_altivec_lvx_v16qi)
9079 {
9080 rtx rawaddr;
9081 if (op0 == const0_rtx)
9082 rawaddr = op1;
9083 else
9084 {
9085 op0 = copy_to_mode_reg (mode0, op0);
9086 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
9087 }
9088 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
9089 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
9090
9091 emit_insn (gen_rtx_SET (target, addr));
9092 }
9093 else
9094 {
9095 if (op0 == const0_rtx)
9096 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
9097 else
9098 {
9099 op0 = copy_to_mode_reg (mode0, op0);
9100 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
9101 gen_rtx_PLUS (Pmode, op1, op0));
9102 }
9103
9104 pat = GEN_FCN (icode) (target, addr);
9105 if (! pat)
9106 return 0;
9107 emit_insn (pat);
9108 }
9109
9110 return target;
9111}
9112
9113static rtx
9114altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
9115{
9116 rtx pat;
9117 tree arg0 = CALL_EXPR_ARG (exp, 0);
9118 tree arg1 = CALL_EXPR_ARG (exp, 1);
9119 tree arg2 = CALL_EXPR_ARG (exp, 2);
9120 rtx op0 = expand_normal (arg0);
9121 rtx op1 = expand_normal (arg1);
9122 rtx op2 = expand_normal (arg2);
9123 machine_mode mode0 = insn_data[icode].operand[0].mode;
9124 machine_mode mode1 = insn_data[icode].operand[1].mode;
9125 machine_mode mode2 = insn_data[icode].operand[2].mode;
9126
9127 if (icode == CODE_FOR_nothing)
9128 /* Builtin not supported on this processor. */
9129 return NULL_RTX;
9130
9131 /* If we got invalid arguments bail out before generating bad rtl. */
9132 if (arg0 == error_mark_node
9133 || arg1 == error_mark_node
9134 || arg2 == error_mark_node)
9135 return NULL_RTX;
9136
9137 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9138 op0 = copy_to_mode_reg (mode0, op0);
9139 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9140 op1 = copy_to_mode_reg (mode1, op1);
9141 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
9142 op2 = copy_to_mode_reg (mode2, op2);
9143
9144 pat = GEN_FCN (icode) (op0, op1, op2);
9145 if (pat)
9146 emit_insn (pat);
9147
9148 return NULL_RTX;
9149}
9150
9151static rtx
9152altivec_expand_stv_builtin (enum insn_code icode, tree exp)
9153{
9154 tree arg0 = CALL_EXPR_ARG (exp, 0);
9155 tree arg1 = CALL_EXPR_ARG (exp, 1);
9156 tree arg2 = CALL_EXPR_ARG (exp, 2);
9157 rtx op0 = expand_normal (arg0);
9158 rtx op1 = expand_normal (arg1);
9159 rtx op2 = expand_normal (arg2);
9160 rtx pat, addr, rawaddr;
9161 machine_mode tmode = insn_data[icode].operand[0].mode;
9162 machine_mode smode = insn_data[icode].operand[1].mode;
9163 machine_mode mode1 = Pmode;
9164 machine_mode mode2 = Pmode;
9165
9166 /* Invalid arguments. Bail before doing anything stoopid! */
9167 if (arg0 == error_mark_node
9168 || arg1 == error_mark_node
9169 || arg2 == error_mark_node)
9170 return const0_rtx;
9171
9172 op2 = copy_to_mode_reg (mode2, op2);
9173
9174 /* For STVX, express the RTL accurately by ANDing the address with -16.
9175 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
9176 so the raw address is fine. */
9177 if (icode == CODE_FOR_altivec_stvx_v2df
9178 || icode == CODE_FOR_altivec_stvx_v2di
9179 || icode == CODE_FOR_altivec_stvx_v4sf
9180 || icode == CODE_FOR_altivec_stvx_v4si
9181 || icode == CODE_FOR_altivec_stvx_v8hi
9182 || icode == CODE_FOR_altivec_stvx_v16qi)
9183 {
9184 if (op1 == const0_rtx)
9185 rawaddr = op2;
9186 else
9187 {
9188 op1 = copy_to_mode_reg (mode1, op1);
9189 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
9190 }
9191
9192 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
9193 addr = gen_rtx_MEM (tmode, addr);
9194
9195 op0 = copy_to_mode_reg (tmode, op0);
9196
9197 emit_insn (gen_rtx_SET (addr, op0));
9198 }
9199 else
9200 {
9201 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
9202 op0 = copy_to_mode_reg (smode, op0);
9203
9204 if (op1 == const0_rtx)
9205 addr = gen_rtx_MEM (tmode, op2);
9206 else
9207 {
9208 op1 = copy_to_mode_reg (mode1, op1);
9209 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
9210 }
9211
9212 pat = GEN_FCN (icode) (addr, op0);
9213 if (pat)
9214 emit_insn (pat);
9215 }
9216
9217 return NULL_RTX;
9218}
9219
9220/* Return the appropriate SPR number associated with the given builtin. */
9221static inline HOST_WIDE_INT
9222htm_spr_num (enum rs6000_builtins code)
9223{
9224 if (code == HTM_BUILTIN_GET_TFHAR
9225 || code == HTM_BUILTIN_SET_TFHAR)
9226 return TFHAR_SPR;
9227 else if (code == HTM_BUILTIN_GET_TFIAR
9228 || code == HTM_BUILTIN_SET_TFIAR)
9229 return TFIAR_SPR;
9230 else if (code == HTM_BUILTIN_GET_TEXASR
9231 || code == HTM_BUILTIN_SET_TEXASR)
9232 return TEXASR_SPR;
9233 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
9234 || code == HTM_BUILTIN_SET_TEXASRU);
9235 return TEXASRU_SPR;
9236}
9237
9238/* Return the correct ICODE value depending on whether we are
9239 setting or reading the HTM SPRs. */
9240static inline enum insn_code
9241rs6000_htm_spr_icode (bool nonvoid)
9242{
9243 if (nonvoid)
9244 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
9245 else
9246 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
9247}
9248
9249/* Expand the HTM builtin in EXP and store the result in TARGET.
9250 Store true in *EXPANDEDP if we found a builtin to expand. */
9251static rtx
9252htm_expand_builtin (tree exp, rtx target, bool * expandedp)
9253{
9254 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9255 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
4d732405
RS		 9256 enum rs6000_builtins fcode
9257 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 9258 const struct builtin_description *d;
9259 size_t i;
9260
9261 *expandedp = true;
9262
9263 if (!TARGET_POWERPC64
9264 && (fcode == HTM_BUILTIN_TABORTDC
9265 || fcode == HTM_BUILTIN_TABORTDCI))
9266 {
9267 size_t uns_fcode = (size_t)fcode;
9268 const char *name = rs6000_builtin_info[uns_fcode].name;
9269 error ("builtin %qs is only valid in 64-bit mode", name);
9270 return const0_rtx;
9271 }
9272
9273 /* Expand the HTM builtins. */
9274 d = bdesc_htm;
9275 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
9276 if (d->code == fcode)
9277 {
9278 rtx op[MAX_HTM_OPERANDS], pat;
9279 int nopnds = 0;
9280 tree arg;
9281 call_expr_arg_iterator iter;
9282 unsigned attr = rs6000_builtin_info[fcode].attr;
9283 enum insn_code icode = d->icode;
9284 const struct insn_operand_data *insn_op;
9285 bool uses_spr = (attr & RS6000_BTC_SPR);
9286 rtx cr = NULL_RTX;
9287
9288 if (uses_spr)
9289 icode = rs6000_htm_spr_icode (nonvoid);
9290 insn_op = &insn_data[icode].operand[0];
9291
9292 if (nonvoid)
9293 {
9294 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
9295 if (!target
9296 || GET_MODE (target) != tmode
9297 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
9298 target = gen_reg_rtx (tmode);
9299 if (uses_spr)
9300 op[nopnds++] = target;
9301 }
9302
9303 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9304 {
9305 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
9306 return const0_rtx;
9307
9308 insn_op = &insn_data[icode].operand[nopnds];
9309
9310 op[nopnds] = expand_normal (arg);
9311
9312 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
9313 {
9314 if (!strcmp (insn_op->constraint, "n"))
9315 {
9316 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
9317 if (!CONST_INT_P (op[nopnds]))
9318 error ("argument %d must be an unsigned literal", arg_num);
9319 else
9320 error ("argument %d is an unsigned literal that is "
9321 "out of range", arg_num);
9322 return const0_rtx;
9323 }
9324 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
9325 }
9326
9327 nopnds++;
9328 }
9329
9330 /* Handle the builtins for extended mnemonics. These accept
9331 no arguments, but map to builtins that take arguments. */
9332 switch (fcode)
9333 {
9334 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
9335 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
9336 op[nopnds++] = GEN_INT (1);
9337 if (flag_checking)
9338 attr |= RS6000_BTC_UNARY;
9339 break;
9340 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
9341 op[nopnds++] = GEN_INT (0);
9342 if (flag_checking)
9343 attr |= RS6000_BTC_UNARY;
9344 break;
9345 default:
9346 break;
9347 }
9348
9349 /* If this builtin accesses SPRs, then pass in the appropriate
9350 SPR number and SPR regno as the last two operands. */
9351 if (uses_spr)
9352 {
9353 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
9354 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
9355 }
9356 /* If this builtin accesses a CR, then pass in a scratch
9357 CR as the last operand. */
9358 else if (attr & RS6000_BTC_CR)
9359 { cr = gen_reg_rtx (CCmode);
9360 op[nopnds++] = cr;
9361 }
9362
9363 if (flag_checking)
9364 {
9365 int expected_nopnds = 0;
9366 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
9367 expected_nopnds = 1;
9368 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
9369 expected_nopnds = 2;
9370 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
9371 expected_nopnds = 3;
9372 if (!(attr & RS6000_BTC_VOID))
9373 expected_nopnds += 1;
9374 if (uses_spr)
9375 expected_nopnds += 1;
9376
9377 gcc_assert (nopnds == expected_nopnds
9378 && nopnds <= MAX_HTM_OPERANDS);
9379 }
9380
9381 switch (nopnds)
9382 {
9383 case 1:
9384 pat = GEN_FCN (icode) (op[0]);
9385 break;
9386 case 2:
9387 pat = GEN_FCN (icode) (op[0], op[1]);
9388 break;
9389 case 3:
9390 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
9391 break;
9392 case 4:
9393 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
9394 break;
9395 default:
9396 gcc_unreachable ();
9397 }
9398 if (!pat)
9399 return NULL_RTX;
9400 emit_insn (pat);
9401
9402 if (attr & RS6000_BTC_CR)
9403 {
9404 if (fcode == HTM_BUILTIN_TBEGIN)
9405 {
9406 /* Emit code to set TARGET to true or false depending on
9407 whether the tbegin. instruction successfully or failed
9408 to start a transaction. We do this by placing the 1's
9409 complement of CR's EQ bit into TARGET. */
9410 rtx scratch = gen_reg_rtx (SImode);
9411 emit_insn (gen_rtx_SET (scratch,
9412 gen_rtx_EQ (SImode, cr,
9413 const0_rtx)));
9414 emit_insn (gen_rtx_SET (target,
9415 gen_rtx_XOR (SImode, scratch,
9416 GEN_INT (1))));
9417 }
9418 else
9419 {
9420 /* Emit code to copy the 4-bit condition register field
9421 CR into the least significant end of register TARGET. */
9422 rtx scratch1 = gen_reg_rtx (SImode);
9423 rtx scratch2 = gen_reg_rtx (SImode);
9424 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
9425 emit_insn (gen_movcc (subreg, cr));
9426 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
9427 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
9428 }
9429 }
9430
9431 if (nonvoid)
9432 return target;
9433 return const0_rtx;
9434 }
9435
9436 *expandedp = false;
9437 return NULL_RTX;
9438}
9439
9440/* Expand the CPU builtin in FCODE and store the result in TARGET. */
9441
9442static rtx
9443cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
9444 rtx target)
9445{
9446 /* __builtin_cpu_init () is a nop, so expand to nothing. */
9447 if (fcode == RS6000_BUILTIN_CPU_INIT)
9448 return const0_rtx;
9449
9450 if (target == 0 || GET_MODE (target) != SImode)
9451 target = gen_reg_rtx (SImode);
9452
9453#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
9454 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
9455 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
9456 to a STRING_CST. */
9457 if (TREE_CODE (arg) == ARRAY_REF
9458 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
9459 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
9460 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
9461 arg = TREE_OPERAND (arg, 0);
9462
9463 if (TREE_CODE (arg) != STRING_CST)
9464 {
9465 error ("builtin %qs only accepts a string argument",
9466 rs6000_builtin_info[(size_t) fcode].name);
9467 return const0_rtx;
9468 }
9469
9470 if (fcode == RS6000_BUILTIN_CPU_IS)
9471 {
9472 const char *cpu = TREE_STRING_POINTER (arg);
9473 rtx cpuid = NULL_RTX;
9474 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
9475 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
9476 {
9477 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
9478 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
9479 break;
9480 }
9481 if (cpuid == NULL_RTX)
9482 {
9483 /* Invalid CPU argument. */
9484 error ("cpu %qs is an invalid argument to builtin %qs",
9485 cpu, rs6000_builtin_info[(size_t) fcode].name);
9486 return const0_rtx;
9487 }
9488
9489 rtx platform = gen_reg_rtx (SImode);
9490 rtx tcbmem = gen_const_mem (SImode,
9491 gen_rtx_PLUS (Pmode,
9492 gen_rtx_REG (Pmode, TLS_REGNUM),
9493 GEN_INT (TCB_PLATFORM_OFFSET)));
9494 emit_move_insn (platform, tcbmem);
9495 emit_insn (gen_eqsi3 (target, platform, cpuid));
9496 }
9497 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
9498 {
9499 const char *hwcap = TREE_STRING_POINTER (arg);
9500 rtx mask = NULL_RTX;
9501 int hwcap_offset;
9502 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
9503 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
9504 {
9505 mask = GEN_INT (cpu_supports_info[i].mask);
9506 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
9507 break;
9508 }
9509 if (mask == NULL_RTX)
9510 {
9511 /* Invalid HWCAP argument. */
9512 error ("%s %qs is an invalid argument to builtin %qs",
9513 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
9514 return const0_rtx;
9515 }
9516
9517 rtx tcb_hwcap = gen_reg_rtx (SImode);
9518 rtx tcbmem = gen_const_mem (SImode,
9519 gen_rtx_PLUS (Pmode,
9520 gen_rtx_REG (Pmode, TLS_REGNUM),
9521 GEN_INT (hwcap_offset)));
9522 emit_move_insn (tcb_hwcap, tcbmem);
9523 rtx scratch1 = gen_reg_rtx (SImode);
9524 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
9525 rtx scratch2 = gen_reg_rtx (SImode);
9526 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
9527 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
9528 }
9529 else
9530 gcc_unreachable ();
9531
9532 /* Record that we have expanded a CPU builtin, so that we can later
9533 emit a reference to the special symbol exported by LIBC to ensure we
9534 do not link against an old LIBC that doesn't support this feature. */
9535 cpu_builtin_p = true;
9536
9537#else
9538 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
9539 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
9540
9541 /* For old LIBCs, always return FALSE. */
9542 emit_move_insn (target, GEN_INT (0));
9543#endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
9544
9545 return target;
9546}
9547
9548static rtx
9549rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
9550{
9551 rtx pat;
9552 tree arg0 = CALL_EXPR_ARG (exp, 0);
9553 tree arg1 = CALL_EXPR_ARG (exp, 1);
9554 tree arg2 = CALL_EXPR_ARG (exp, 2);
9555 rtx op0 = expand_normal (arg0);
9556 rtx op1 = expand_normal (arg1);
9557 rtx op2 = expand_normal (arg2);
9558 machine_mode tmode = insn_data[icode].operand[0].mode;
9559 machine_mode mode0 = insn_data[icode].operand[1].mode;
9560 machine_mode mode1 = insn_data[icode].operand[2].mode;
9561 machine_mode mode2 = insn_data[icode].operand[3].mode;
9562
9563 if (icode == CODE_FOR_nothing)
9564 /* Builtin not supported on this processor. */
9565 return 0;
9566
9567 /* If we got invalid arguments bail out before generating bad rtl. */
9568 if (arg0 == error_mark_node
9569 || arg1 == error_mark_node
9570 || arg2 == error_mark_node)
9571 return const0_rtx;
9572
9573 /* Check and prepare argument depending on the instruction code.
9574
9575 Note that a switch statement instead of the sequence of tests
9576 would be incorrect as many of the CODE_FOR values could be
9577 CODE_FOR_nothing and that would yield multiple alternatives
9578 with identical values. We'd never reach here at runtime in
9579 this case. */
9580 if (icode == CODE_FOR_altivec_vsldoi_v4sf
9581 || icode == CODE_FOR_altivec_vsldoi_v2df
9582 || icode == CODE_FOR_altivec_vsldoi_v4si
9583 || icode == CODE_FOR_altivec_vsldoi_v8hi
9584 || icode == CODE_FOR_altivec_vsldoi_v16qi)
9585 {
9586 /* Only allow 4-bit unsigned literals. */
9587 STRIP_NOPS (arg2);
9588 if (TREE_CODE (arg2) != INTEGER_CST
9589 || TREE_INT_CST_LOW (arg2) & ~0xf)
9590 {
9591 error ("argument 3 must be a 4-bit unsigned literal");
9592 return CONST0_RTX (tmode);
9593 }
9594 }
9595 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
9596 || icode == CODE_FOR_vsx_xxpermdi_v2di
9597 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
9598 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
9599 || icode == CODE_FOR_vsx_xxpermdi_v1ti
9600 || icode == CODE_FOR_vsx_xxpermdi_v4sf
9601 || icode == CODE_FOR_vsx_xxpermdi_v4si
9602 || icode == CODE_FOR_vsx_xxpermdi_v8hi
9603 || icode == CODE_FOR_vsx_xxpermdi_v16qi
9604 || icode == CODE_FOR_vsx_xxsldwi_v16qi
9605 || icode == CODE_FOR_vsx_xxsldwi_v8hi
9606 || icode == CODE_FOR_vsx_xxsldwi_v4si
9607 || icode == CODE_FOR_vsx_xxsldwi_v4sf
9608 || icode == CODE_FOR_vsx_xxsldwi_v2di
9609 || icode == CODE_FOR_vsx_xxsldwi_v2df)
9610 {
9611 /* Only allow 2-bit unsigned literals. */
9612 STRIP_NOPS (arg2);
9613 if (TREE_CODE (arg2) != INTEGER_CST
9614 || TREE_INT_CST_LOW (arg2) & ~0x3)
9615 {
9616 error ("argument 3 must be a 2-bit unsigned literal");
9617 return CONST0_RTX (tmode);
9618 }
9619 }
9620 else if (icode == CODE_FOR_vsx_set_v2df
9621 || icode == CODE_FOR_vsx_set_v2di
9622 || icode == CODE_FOR_bcdadd
9623 || icode == CODE_FOR_bcdadd_lt
9624 || icode == CODE_FOR_bcdadd_eq
9625 || icode == CODE_FOR_bcdadd_gt
9626 || icode == CODE_FOR_bcdsub
9627 || icode == CODE_FOR_bcdsub_lt
9628 || icode == CODE_FOR_bcdsub_eq
9629 || icode == CODE_FOR_bcdsub_gt)
9630 {
9631 /* Only allow 1-bit unsigned literals. */
9632 STRIP_NOPS (arg2);
9633 if (TREE_CODE (arg2) != INTEGER_CST
9634 || TREE_INT_CST_LOW (arg2) & ~0x1)
9635 {
9636 error ("argument 3 must be a 1-bit unsigned literal");
9637 return CONST0_RTX (tmode);
9638 }
9639 }
9640 else if (icode == CODE_FOR_dfp_ddedpd_dd
9641 || icode == CODE_FOR_dfp_ddedpd_td)
9642 {
9643 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
9644 STRIP_NOPS (arg0);
9645 if (TREE_CODE (arg0) != INTEGER_CST
9646 || TREE_INT_CST_LOW (arg2) & ~0x3)
9647 {
9648 error ("argument 1 must be 0 or 2");
9649 return CONST0_RTX (tmode);
9650 }
9651 }
9652 else if (icode == CODE_FOR_dfp_denbcd_dd
9653 || icode == CODE_FOR_dfp_denbcd_td)
9654 {
9655 /* Only allow 1-bit unsigned literals. */
9656 STRIP_NOPS (arg0);
9657 if (TREE_CODE (arg0) != INTEGER_CST
9658 || TREE_INT_CST_LOW (arg0) & ~0x1)
9659 {
9660 error ("argument 1 must be a 1-bit unsigned literal");
9661 return CONST0_RTX (tmode);
9662 }
9663 }
9664 else if (icode == CODE_FOR_dfp_dscli_dd
9665 || icode == CODE_FOR_dfp_dscli_td
9666 || icode == CODE_FOR_dfp_dscri_dd
9667 || icode == CODE_FOR_dfp_dscri_td)
9668 {
9669 /* Only allow 6-bit unsigned literals. */
9670 STRIP_NOPS (arg1);
9671 if (TREE_CODE (arg1) != INTEGER_CST
9672 || TREE_INT_CST_LOW (arg1) & ~0x3f)
9673 {
9674 error ("argument 2 must be a 6-bit unsigned literal");
9675 return CONST0_RTX (tmode);
9676 }
9677 }
9678 else if (icode == CODE_FOR_crypto_vshasigmaw
9679 || icode == CODE_FOR_crypto_vshasigmad)
9680 {
9681 /* Check whether the 2nd and 3rd arguments are integer constants and in
9682 range and prepare arguments. */
9683 STRIP_NOPS (arg1);
9684 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
9685 {
9686 error ("argument 2 must be 0 or 1");
9687 return CONST0_RTX (tmode);
9688 }
9689
9690 STRIP_NOPS (arg2);
9691 if (TREE_CODE (arg2) != INTEGER_CST
9692 || wi::geu_p (wi::to_wide (arg2), 16))
9693 {
9694 error ("argument 3 must be in the range [0, 15]");
9695 return CONST0_RTX (tmode);
9696 }
9697 }
9698
9699 if (target == 0
9700 || GET_MODE (target) != tmode
9701 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9702 target = gen_reg_rtx (tmode);
9703
9704 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9705 op0 = copy_to_mode_reg (mode0, op0);
9706 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9707 op1 = copy_to_mode_reg (mode1, op1);
9708 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
9709 op2 = copy_to_mode_reg (mode2, op2);
9710
9711 pat = GEN_FCN (icode) (target, op0, op1, op2);
9712 if (! pat)
9713 return 0;
9714 emit_insn (pat);
9715
9716 return target;
9717}
9718
9719
9720/* Expand the dst builtins. */
9721static rtx
9722altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
9723 bool *expandedp)
9724{
9725 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
4d732405
RS		 9726 enum rs6000_builtins fcode
9727 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 9728 tree arg0, arg1, arg2;
9729 machine_mode mode0, mode1;
9730 rtx pat, op0, op1, op2;
9731 const struct builtin_description *d;
9732 size_t i;
9733
9734 *expandedp = false;
9735
9736 /* Handle DST variants. */
9737 d = bdesc_dst;
9738 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9739 if (d->code == fcode)
9740 {
9741 arg0 = CALL_EXPR_ARG (exp, 0);
9742 arg1 = CALL_EXPR_ARG (exp, 1);
9743 arg2 = CALL_EXPR_ARG (exp, 2);
9744 op0 = expand_normal (arg0);
9745 op1 = expand_normal (arg1);
9746 op2 = expand_normal (arg2);
9747 mode0 = insn_data[d->icode].operand[0].mode;
9748 mode1 = insn_data[d->icode].operand[1].mode;
9749
9750 /* Invalid arguments, bail out before generating bad rtl. */
9751 if (arg0 == error_mark_node
9752 || arg1 == error_mark_node
9753 || arg2 == error_mark_node)
9754 return const0_rtx;
9755
9756 *expandedp = true;
9757 STRIP_NOPS (arg2);
9758 if (TREE_CODE (arg2) != INTEGER_CST
9759 || TREE_INT_CST_LOW (arg2) & ~0x3)
9760 {
9761 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
9762 return const0_rtx;
9763 }
9764
9765 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
9766 op0 = copy_to_mode_reg (Pmode, op0);
9767 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
9768 op1 = copy_to_mode_reg (mode1, op1);
9769
9770 pat = GEN_FCN (d->icode) (op0, op1, op2);
9771 if (pat != 0)
9772 emit_insn (pat);
9773
9774 return NULL_RTX;
9775 }
9776
9777 return NULL_RTX;
9778}
9779
9780/* Expand vec_init builtin. */
9781static rtx
9782altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
9783{
9784 machine_mode tmode = TYPE_MODE (type);
9785 machine_mode inner_mode = GET_MODE_INNER (tmode);
9786 int i, n_elt = GET_MODE_NUNITS (tmode);
9787
9788 gcc_assert (VECTOR_MODE_P (tmode));
9789 gcc_assert (n_elt == call_expr_nargs (exp));
9790
9791 if (!target || !register_operand (target, tmode))
9792 target = gen_reg_rtx (tmode);
9793
9794 /* If we have a vector compromised of a single element, such as V1TImode, do
9795 the initialization directly. */
9796 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
9797 {
9798 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
9799 emit_move_insn (target, gen_lowpart (tmode, x));
9800 }
9801 else
9802 {
9803 rtvec v = rtvec_alloc (n_elt);
9804
9805 for (i = 0; i < n_elt; ++i)
9806 {
9807 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
9808 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
9809 }
9810
9811 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
9812 }
9813
9814 return target;
9815}
9816
9817/* Return the integer constant in ARG. Constrain it to be in the range
9818 of the subparts of VEC_TYPE; issue an error if not. */
9819
9820static int
9821get_element_number (tree vec_type, tree arg)
9822{
9823 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
9824
9825 if (!tree_fits_uhwi_p (arg)
9826 || (elt = tree_to_uhwi (arg), elt > max))
9827 {
9828 error ("selector must be an integer constant in the range [0, %wi]", max);
9829 return 0;
9830 }
9831
9832 return elt;
9833}
9834
9835/* Expand vec_set builtin. */
9836static rtx
9837altivec_expand_vec_set_builtin (tree exp)
9838{
9839 machine_mode tmode, mode1;
9840 tree arg0, arg1, arg2;
9841 int elt;
9842 rtx op0, op1;
9843
9844 arg0 = CALL_EXPR_ARG (exp, 0);
9845 arg1 = CALL_EXPR_ARG (exp, 1);
9846 arg2 = CALL_EXPR_ARG (exp, 2);
9847
9848 tmode = TYPE_MODE (TREE_TYPE (arg0));
9849 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
9850 gcc_assert (VECTOR_MODE_P (tmode));
9851
9852 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
9853 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
9854 elt = get_element_number (TREE_TYPE (arg0), arg2);
9855
9856 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
9857 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
9858
9859 op0 = force_reg (tmode, op0);
9860 op1 = force_reg (mode1, op1);
9861
9862 rs6000_expand_vector_set (op0, op1, elt);
9863
9864 return op0;
9865}
9866
9867/* Expand vec_ext builtin. */
9868static rtx
9869altivec_expand_vec_ext_builtin (tree exp, rtx target)
9870{
9871 machine_mode tmode, mode0;
9872 tree arg0, arg1;
9873 rtx op0;
9874 rtx op1;
9875
9876 arg0 = CALL_EXPR_ARG (exp, 0);
9877 arg1 = CALL_EXPR_ARG (exp, 1);
9878
9879 op0 = expand_normal (arg0);
9880 op1 = expand_normal (arg1);
9881
9882 if (TREE_CODE (arg1) == INTEGER_CST)
9883 {
9884 unsigned HOST_WIDE_INT elt;
9885 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0));
9886 unsigned int truncated_selector;
9887 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
9888 returns low-order bits of INTEGER_CST for modulo indexing. */
9889 elt = TREE_INT_CST_LOW (arg1);
9890 truncated_selector = elt % size;
9891 op1 = GEN_INT (truncated_selector);
9892 }
9893
9894 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
9895 mode0 = TYPE_MODE (TREE_TYPE (arg0));
9896 gcc_assert (VECTOR_MODE_P (mode0));
9897
9898 op0 = force_reg (mode0, op0);
9899
9900 if (optimize || !target || !register_operand (target, tmode))
9901 target = gen_reg_rtx (tmode);
9902
9903 rs6000_expand_vector_extract (target, op0, op1);
9904
9905 return target;
9906}
9907
9908/* Expand the builtin in EXP and store the result in TARGET. Store
9909 true in *EXPANDEDP if we found a builtin to expand. */
9910static rtx
9911altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
9912{
9913 const struct builtin_description *d;
9914 size_t i;
9915 enum insn_code icode;
9916 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9917 tree arg0, arg1, arg2;
9918 rtx op0, pat;
9919 machine_mode tmode, mode0;
9920 enum rs6000_builtins fcode
4d732405 9921 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 9922
9923 if (rs6000_overloaded_builtin_p (fcode))
9924 {
9925 *expandedp = true;
9926 error ("unresolved overload for Altivec builtin %qF", fndecl);
9927
9928 /* Given it is invalid, just generate a normal call. */
9929 return expand_call (exp, target, false);
9930 }
9931
9932 target = altivec_expand_dst_builtin (exp, target, expandedp);
9933 if (*expandedp)
9934 return target;
9935
9936 *expandedp = true;
9937
9938 switch (fcode)
9939 {
9940 case ALTIVEC_BUILTIN_STVX_V2DF:
9941 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
9942 case ALTIVEC_BUILTIN_STVX_V2DI:
9943 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
9944 case ALTIVEC_BUILTIN_STVX_V4SF:
9945 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
9946 case ALTIVEC_BUILTIN_STVX:
9947 case ALTIVEC_BUILTIN_STVX_V4SI:
9948 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
9949 case ALTIVEC_BUILTIN_STVX_V8HI:
9950 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
9951 case ALTIVEC_BUILTIN_STVX_V16QI:
9952 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
9953 case ALTIVEC_BUILTIN_STVEBX:
9954 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
9955 case ALTIVEC_BUILTIN_STVEHX:
9956 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
9957 case ALTIVEC_BUILTIN_STVEWX:
9958 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
9959 case ALTIVEC_BUILTIN_STVXL_V2DF:
9960 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
9961 case ALTIVEC_BUILTIN_STVXL_V2DI:
9962 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
9963 case ALTIVEC_BUILTIN_STVXL_V4SF:
9964 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
9965 case ALTIVEC_BUILTIN_STVXL:
9966 case ALTIVEC_BUILTIN_STVXL_V4SI:
9967 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
9968 case ALTIVEC_BUILTIN_STVXL_V8HI:
9969 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
9970 case ALTIVEC_BUILTIN_STVXL_V16QI:
9971 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
9972
9973 case ALTIVEC_BUILTIN_STVLX:
9974 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
9975 case ALTIVEC_BUILTIN_STVLXL:
9976 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
9977 case ALTIVEC_BUILTIN_STVRX:
9978 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
9979 case ALTIVEC_BUILTIN_STVRXL:
9980 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
9981
9982 case P9V_BUILTIN_STXVL:
9983 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
9984
9985 case P9V_BUILTIN_XST_LEN_R:
9986 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
9987
9988 case VSX_BUILTIN_STXVD2X_V1TI:
9989 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
9990 case VSX_BUILTIN_STXVD2X_V2DF:
9991 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
9992 case VSX_BUILTIN_STXVD2X_V2DI:
9993 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
9994 case VSX_BUILTIN_STXVW4X_V4SF:
9995 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
9996 case VSX_BUILTIN_STXVW4X_V4SI:
9997 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
9998 case VSX_BUILTIN_STXVW4X_V8HI:
9999 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10000 case VSX_BUILTIN_STXVW4X_V16QI:
10001 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10002
10003 /* For the following on big endian, it's ok to use any appropriate
10004 unaligned-supporting store, so use a generic expander. For
10005 little-endian, the exact element-reversing instruction must
10006 be used. */
10007 case VSX_BUILTIN_ST_ELEMREV_V1TI:
10008 {
10009 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
10010 : CODE_FOR_vsx_st_elemrev_v1ti);
10011 return altivec_expand_stv_builtin (code, exp);
10012 }
10013 case VSX_BUILTIN_ST_ELEMREV_V2DF:
10014 {
10015 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
10016 : CODE_FOR_vsx_st_elemrev_v2df);
10017 return altivec_expand_stv_builtin (code, exp);
10018 }
10019 case VSX_BUILTIN_ST_ELEMREV_V2DI:
10020 {
10021 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
10022 : CODE_FOR_vsx_st_elemrev_v2di);
10023 return altivec_expand_stv_builtin (code, exp);
10024 }
10025 case VSX_BUILTIN_ST_ELEMREV_V4SF:
10026 {
10027 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
10028 : CODE_FOR_vsx_st_elemrev_v4sf);
10029 return altivec_expand_stv_builtin (code, exp);
10030 }
10031 case VSX_BUILTIN_ST_ELEMREV_V4SI:
10032 {
10033 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
10034 : CODE_FOR_vsx_st_elemrev_v4si);
10035 return altivec_expand_stv_builtin (code, exp);
10036 }
10037 case VSX_BUILTIN_ST_ELEMREV_V8HI:
10038 {
10039 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
10040 : CODE_FOR_vsx_st_elemrev_v8hi);
10041 return altivec_expand_stv_builtin (code, exp);
10042 }
10043 case VSX_BUILTIN_ST_ELEMREV_V16QI:
10044 {
10045 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
10046 : CODE_FOR_vsx_st_elemrev_v16qi);
10047 return altivec_expand_stv_builtin (code, exp);
10048 }
10049
10050 case ALTIVEC_BUILTIN_MFVSCR:
10051 icode = CODE_FOR_altivec_mfvscr;
10052 tmode = insn_data[icode].operand[0].mode;
10053
10054 if (target == 0
10055 || GET_MODE (target) != tmode
10056 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10057 target = gen_reg_rtx (tmode);
10058
10059 pat = GEN_FCN (icode) (target);
10060 if (! pat)
10061 return 0;
10062 emit_insn (pat);
10063 return target;
10064
10065 case ALTIVEC_BUILTIN_MTVSCR:
10066 icode = CODE_FOR_altivec_mtvscr;
10067 arg0 = CALL_EXPR_ARG (exp, 0);
10068 op0 = expand_normal (arg0);
10069 mode0 = insn_data[icode].operand[0].mode;
10070
10071 /* If we got invalid arguments bail out before generating bad rtl. */
10072 if (arg0 == error_mark_node)
10073 return const0_rtx;
10074
10075 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10076 op0 = copy_to_mode_reg (mode0, op0);
10077
10078 pat = GEN_FCN (icode) (op0);
10079 if (pat)
10080 emit_insn (pat);
10081 return NULL_RTX;
10082
10083 case ALTIVEC_BUILTIN_DSSALL:
10084 emit_insn (gen_altivec_dssall ());
10085 return NULL_RTX;
10086
10087 case ALTIVEC_BUILTIN_DSS:
10088 icode = CODE_FOR_altivec_dss;
10089 arg0 = CALL_EXPR_ARG (exp, 0);
10090 STRIP_NOPS (arg0);
10091 op0 = expand_normal (arg0);
10092 mode0 = insn_data[icode].operand[0].mode;
10093
10094 /* If we got invalid arguments bail out before generating bad rtl. */
10095 if (arg0 == error_mark_node)
10096 return const0_rtx;
10097
10098 if (TREE_CODE (arg0) != INTEGER_CST
10099 || TREE_INT_CST_LOW (arg0) & ~0x3)
10100 {
10101 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
10102 return const0_rtx;
10103 }
10104
10105 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10106 op0 = copy_to_mode_reg (mode0, op0);
10107
10108 emit_insn (gen_altivec_dss (op0));
10109 return NULL_RTX;
10110
10111 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
10112 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
10113 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
10114 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
10115 case VSX_BUILTIN_VEC_INIT_V2DF:
10116 case VSX_BUILTIN_VEC_INIT_V2DI:
10117 case VSX_BUILTIN_VEC_INIT_V1TI:
10118 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
10119
10120 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
10121 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
10122 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
10123 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
10124 case VSX_BUILTIN_VEC_SET_V2DF:
10125 case VSX_BUILTIN_VEC_SET_V2DI:
10126 case VSX_BUILTIN_VEC_SET_V1TI:
10127 return altivec_expand_vec_set_builtin (exp);
10128
10129 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
10130 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
10131 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
10132 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
10133 case VSX_BUILTIN_VEC_EXT_V2DF:
10134 case VSX_BUILTIN_VEC_EXT_V2DI:
10135 case VSX_BUILTIN_VEC_EXT_V1TI:
10136 return altivec_expand_vec_ext_builtin (exp, target);
10137
10138 case P9V_BUILTIN_VEC_EXTRACT4B:
10139 arg1 = CALL_EXPR_ARG (exp, 1);
10140 STRIP_NOPS (arg1);
10141
10142 /* Generate a normal call if it is invalid. */
10143 if (arg1 == error_mark_node)
10144 return expand_call (exp, target, false);
10145
10146 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
10147 {
10148 error ("second argument to %qs must be [0, 12]", "vec_vextract4b");
10149 return expand_call (exp, target, false);
10150 }
10151 break;
10152
10153 case P9V_BUILTIN_VEC_INSERT4B:
10154 arg2 = CALL_EXPR_ARG (exp, 2);
10155 STRIP_NOPS (arg2);
10156
10157 /* Generate a normal call if it is invalid. */
10158 if (arg2 == error_mark_node)
10159 return expand_call (exp, target, false);
10160
10161 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
10162 {
10163 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b");
10164 return expand_call (exp, target, false);
10165 }
10166 break;
10167
10168 default:
10169 break;
10170 /* Fall through. */
10171 }
10172
10173 /* Expand abs* operations. */
10174 d = bdesc_abs;
10175 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10176 if (d->code == fcode)
10177 return altivec_expand_abs_builtin (d->icode, exp, target);
10178
10179 /* Expand the AltiVec predicates. */
10180 d = bdesc_altivec_preds;
10181 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
10182 if (d->code == fcode)
10183 return altivec_expand_predicate_builtin (d->icode, exp, target);
10184
10185 /* LV* are funky. We initialized them differently. */
10186 switch (fcode)
10187 {
10188 case ALTIVEC_BUILTIN_LVSL:
10189 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
10190 exp, target, false);
10191 case ALTIVEC_BUILTIN_LVSR:
10192 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
10193 exp, target, false);
10194 case ALTIVEC_BUILTIN_LVEBX:
10195 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
10196 exp, target, false);
10197 case ALTIVEC_BUILTIN_LVEHX:
10198 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
10199 exp, target, false);
10200 case ALTIVEC_BUILTIN_LVEWX:
10201 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
10202 exp, target, false);
10203 case ALTIVEC_BUILTIN_LVXL_V2DF:
10204 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
10205 exp, target, false);
10206 case ALTIVEC_BUILTIN_LVXL_V2DI:
10207 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
10208 exp, target, false);
10209 case ALTIVEC_BUILTIN_LVXL_V4SF:
10210 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
10211 exp, target, false);
10212 case ALTIVEC_BUILTIN_LVXL:
10213 case ALTIVEC_BUILTIN_LVXL_V4SI:
10214 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
10215 exp, target, false);
10216 case ALTIVEC_BUILTIN_LVXL_V8HI:
10217 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
10218 exp, target, false);
10219 case ALTIVEC_BUILTIN_LVXL_V16QI:
10220 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
10221 exp, target, false);
10222 case ALTIVEC_BUILTIN_LVX_V1TI:
10223 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
10224 exp, target, false);
10225 case ALTIVEC_BUILTIN_LVX_V2DF:
10226 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
10227 exp, target, false);
10228 case ALTIVEC_BUILTIN_LVX_V2DI:
10229 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
10230 exp, target, false);
10231 case ALTIVEC_BUILTIN_LVX_V4SF:
10232 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
10233 exp, target, false);
10234 case ALTIVEC_BUILTIN_LVX:
10235 case ALTIVEC_BUILTIN_LVX_V4SI:
10236 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10237 exp, target, false);
10238 case ALTIVEC_BUILTIN_LVX_V8HI:
10239 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
10240 exp, target, false);
10241 case ALTIVEC_BUILTIN_LVX_V16QI:
10242 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
10243 exp, target, false);
10244 case ALTIVEC_BUILTIN_LVLX:
10245 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10246 exp, target, true);
10247 case ALTIVEC_BUILTIN_LVLXL:
10248 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
10249 exp, target, true);
10250 case ALTIVEC_BUILTIN_LVRX:
10251 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
10252 exp, target, true);
10253 case ALTIVEC_BUILTIN_LVRXL:
10254 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10255 exp, target, true);
10256 case VSX_BUILTIN_LXVD2X_V1TI:
10257 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
10258 exp, target, false);
10259 case VSX_BUILTIN_LXVD2X_V2DF:
10260 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10261 exp, target, false);
10262 case VSX_BUILTIN_LXVD2X_V2DI:
10263 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10264 exp, target, false);
10265 case VSX_BUILTIN_LXVW4X_V4SF:
10266 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10267 exp, target, false);
10268 case VSX_BUILTIN_LXVW4X_V4SI:
10269 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10270 exp, target, false);
10271 case VSX_BUILTIN_LXVW4X_V8HI:
10272 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10273 exp, target, false);
10274 case VSX_BUILTIN_LXVW4X_V16QI:
10275 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10276 exp, target, false);
10277 /* For the following on big endian, it's ok to use any appropriate
10278 unaligned-supporting load, so use a generic expander. For
10279 little-endian, the exact element-reversing instruction must
10280 be used. */
10281 case VSX_BUILTIN_LD_ELEMREV_V2DF:
10282 {
10283 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
10284 : CODE_FOR_vsx_ld_elemrev_v2df);
10285 return altivec_expand_lv_builtin (code, exp, target, false);
10286 }
10287 case VSX_BUILTIN_LD_ELEMREV_V1TI:
10288 {
10289 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
10290 : CODE_FOR_vsx_ld_elemrev_v1ti);
10291 return altivec_expand_lv_builtin (code, exp, target, false);
10292 }
10293 case VSX_BUILTIN_LD_ELEMREV_V2DI:
10294 {
10295 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
10296 : CODE_FOR_vsx_ld_elemrev_v2di);
10297 return altivec_expand_lv_builtin (code, exp, target, false);
10298 }
10299 case VSX_BUILTIN_LD_ELEMREV_V4SF:
10300 {
10301 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
10302 : CODE_FOR_vsx_ld_elemrev_v4sf);
10303 return altivec_expand_lv_builtin (code, exp, target, false);
10304 }
10305 case VSX_BUILTIN_LD_ELEMREV_V4SI:
10306 {
10307 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
10308 : CODE_FOR_vsx_ld_elemrev_v4si);
10309 return altivec_expand_lv_builtin (code, exp, target, false);
10310 }
10311 case VSX_BUILTIN_LD_ELEMREV_V8HI:
10312 {
10313 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
10314 : CODE_FOR_vsx_ld_elemrev_v8hi);
10315 return altivec_expand_lv_builtin (code, exp, target, false);
10316 }
10317 case VSX_BUILTIN_LD_ELEMREV_V16QI:
10318 {
10319 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
10320 : CODE_FOR_vsx_ld_elemrev_v16qi);
10321 return altivec_expand_lv_builtin (code, exp, target, false);
10322 }
10323 break;
10324 default:
10325 break;
10326 /* Fall through. */
10327 }
10328
10329 *expandedp = false;
10330 return NULL_RTX;
10331}
10332
10333/* Check whether a builtin function is supported in this target
10334 configuration. */
10335bool
10336rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
10337{
10338 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
10339 if ((fnmask & rs6000_builtin_mask) != fnmask)
10340 return false;
10341 else
10342 return true;
10343}
10344
10345/* Raise an error message for a builtin function that is called without the
10346 appropriate target options being set. */
10347
871a8fab 10348static void
1acf0246
BS		 10349rs6000_invalid_builtin (enum rs6000_builtins fncode)
10350{
10351 size_t uns_fncode = (size_t) fncode;
10352 const char *name = rs6000_builtin_info[uns_fncode].name;
10353 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
10354
10355 gcc_assert (name != NULL);
10356 if ((fnmask & RS6000_BTM_CELL) != 0)
10357 error ("%qs is only valid for the cell processor", name);
10358 else if ((fnmask & RS6000_BTM_VSX) != 0)
10359 error ("%qs requires the %qs option", name, "-mvsx");
10360 else if ((fnmask & RS6000_BTM_HTM) != 0)
10361 error ("%qs requires the %qs option", name, "-mhtm");
10362 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
10363 error ("%qs requires the %qs option", name, "-maltivec");
10364 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
10365 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
10366 error ("%qs requires the %qs and %qs options", name, "-mhard-dfp",
10367 "-mpower8-vector");
10368 else if ((fnmask & RS6000_BTM_DFP) != 0)
10369 error ("%qs requires the %qs option", name, "-mhard-dfp");
10370 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
10371 error ("%qs requires the %qs option", name, "-mpower8-vector");
10372 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
10373 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
10374 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9",
10375 "-m64");
10376 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
10377 error ("%qs requires the %qs option", name, "-mcpu=power9");
10378 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
10379 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
10380 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9",
10381 "-m64");
10382 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
10383 error ("%qs requires the %qs option", name, "-mcpu=power9");
10384 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
10385 {
10386 if (!TARGET_HARD_FLOAT)
10387 error ("%qs requires the %qs option", name, "-mhard-float");
10388 else
10389 error ("%qs requires the %qs option", name,
10390 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
10391 }
10392 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
10393 error ("%qs requires the %qs option", name, "-mhard-float");
10394 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
10395 error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name);
10396 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
10397 error ("%qs requires the %qs option", name, "%<-mfloat128%>");
10398 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
10399 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
10400 error ("%qs requires the %qs (or newer), and %qs or %qs options",
10401 name, "-mcpu=power7", "-m64", "-mpowerpc64");
10402 else
10403 error ("%qs is not supported with the current options", name);
10404}
10405
10406/* Target hook for early folding of built-ins, shamelessly stolen
10407 from ia64.c. */
10408
10409tree
10410rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
10411 int n_args ATTRIBUTE_UNUSED,
10412 tree *args ATTRIBUTE_UNUSED,
10413 bool ignore ATTRIBUTE_UNUSED)
10414{
10415#ifdef SUBTARGET_FOLD_BUILTIN
10416 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
10417#else
10418 return NULL_TREE;
10419#endif
10420}
10421
10422/* Helper function to sort out which built-ins may be valid without having
10423 a LHS. */
10424static bool
10425rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
10426{
10427 switch (fn_code)
10428 {
10429 case ALTIVEC_BUILTIN_STVX_V16QI:
10430 case ALTIVEC_BUILTIN_STVX_V8HI:
10431 case ALTIVEC_BUILTIN_STVX_V4SI:
10432 case ALTIVEC_BUILTIN_STVX_V4SF:
10433 case ALTIVEC_BUILTIN_STVX_V2DI:
10434 case ALTIVEC_BUILTIN_STVX_V2DF:
10435 case VSX_BUILTIN_STXVW4X_V16QI:
10436 case VSX_BUILTIN_STXVW4X_V8HI:
10437 case VSX_BUILTIN_STXVW4X_V4SF:
10438 case VSX_BUILTIN_STXVW4X_V4SI:
10439 case VSX_BUILTIN_STXVD2X_V2DF:
10440 case VSX_BUILTIN_STXVD2X_V2DI:
10441 return true;
10442 default:
10443 return false;
10444 }
10445}
10446
10447/* Helper function to handle the gimple folding of a vector compare
10448 operation. This sets up true/false vectors, and uses the
10449 VEC_COND_EXPR operation.
10450 CODE indicates which comparison is to be made. (EQ, GT, ...).
10451 TYPE indicates the type of the result. */
10452static tree
10453fold_build_vec_cmp (tree_code code, tree type,
10454 tree arg0, tree arg1)
10455{
e8738f4e 10456 tree cmp_type = truth_type_for (type);
1acf0246
BS		 10457 tree zero_vec = build_zero_cst (type);
10458 tree minus_one_vec = build_minus_one_cst (type);
10459 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
10460 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
10461}
10462
10463/* Helper function to handle the in-between steps for the
10464 vector compare built-ins. */
10465static void
10466fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
10467{
10468 tree arg0 = gimple_call_arg (stmt, 0);
10469 tree arg1 = gimple_call_arg (stmt, 1);
10470 tree lhs = gimple_call_lhs (stmt);
10471 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
10472 gimple *g = gimple_build_assign (lhs, cmp);
10473 gimple_set_location (g, gimple_location (stmt));
10474 gsi_replace (gsi, g, true);
10475}
10476
10477/* Helper function to map V2DF and V4SF types to their
10478 integral equivalents (V2DI and V4SI). */
10479tree map_to_integral_tree_type (tree input_tree_type)
10480{
10481 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
10482 return input_tree_type;
10483 else
10484 {
10485 if (types_compatible_p (TREE_TYPE (input_tree_type),
10486 TREE_TYPE (V2DF_type_node)))
10487 return V2DI_type_node;
10488 else if (types_compatible_p (TREE_TYPE (input_tree_type),
10489 TREE_TYPE (V4SF_type_node)))
10490 return V4SI_type_node;
10491 else
10492 gcc_unreachable ();
10493 }
10494}
10495
10496/* Helper function to handle the vector merge[hl] built-ins. The
10497 implementation difference between h and l versions for this code are in
10498 the values used when building of the permute vector for high word versus
10499 low word merge. The variance is keyed off the use_high parameter. */
10500static void
10501fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
10502{
10503 tree arg0 = gimple_call_arg (stmt, 0);
10504 tree arg1 = gimple_call_arg (stmt, 1);
10505 tree lhs = gimple_call_lhs (stmt);
10506 tree lhs_type = TREE_TYPE (lhs);
10507 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
10508 int midpoint = n_elts / 2;
10509 int offset = 0;
10510
10511 if (use_high == 1)
10512 offset = midpoint;
10513
10514 /* The permute_type will match the lhs for integral types. For double and
10515 float types, the permute type needs to map to the V2 or V4 type that
10516 matches size. */
10517 tree permute_type;
10518 permute_type = map_to_integral_tree_type (lhs_type);
10519 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
10520
10521 for (int i = 0; i < midpoint; i++)
10522 {
10523 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
10524 offset + i));
10525 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
10526 offset + n_elts + i));
10527 }
10528
10529 tree permute = elts.build ();
10530
10531 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
10532 gimple_set_location (g, gimple_location (stmt));
10533 gsi_replace (gsi, g, true);
10534}
10535
10536/* Helper function to handle the vector merge[eo] built-ins. */
10537static void
10538fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
10539{
10540 tree arg0 = gimple_call_arg (stmt, 0);
10541 tree arg1 = gimple_call_arg (stmt, 1);
10542 tree lhs = gimple_call_lhs (stmt);
10543 tree lhs_type = TREE_TYPE (lhs);
10544 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
10545
10546 /* The permute_type will match the lhs for integral types. For double and
10547 float types, the permute type needs to map to the V2 or V4 type that
10548 matches size. */
10549 tree permute_type;
10550 permute_type = map_to_integral_tree_type (lhs_type);
10551
10552 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
10553
10554 /* Build the permute vector. */
10555 for (int i = 0; i < n_elts / 2; i++)
10556 {
10557 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
10558 2*i + use_odd));
10559 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
10560 2*i + use_odd + n_elts));
10561 }
10562
10563 tree permute = elts.build ();
10564
10565 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
10566 gimple_set_location (g, gimple_location (stmt));
10567 gsi_replace (gsi, g, true);
10568}
10569
10570/* Fold a machine-dependent built-in in GIMPLE. (For folding into
10571 a constant, use rs6000_fold_builtin.) */
10572
10573bool
10574rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
10575{
10576 gimple *stmt = gsi_stmt (*gsi);
10577 tree fndecl = gimple_call_fndecl (stmt);
10578 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
10579 enum rs6000_builtins fn_code
4d732405 10580 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 10581 tree arg0, arg1, lhs, temp;
10582 enum tree_code bcode;
10583 gimple *g;
10584
10585 size_t uns_fncode = (size_t) fn_code;
10586 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
10587 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
10588 const char *fn_name2 = (icode != CODE_FOR_nothing)
10589 ? get_insn_name ((int) icode)
10590 : "nothing";
10591
10592 if (TARGET_DEBUG_BUILTIN)
10593 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
10594 fn_code, fn_name1, fn_name2);
10595
10596 if (!rs6000_fold_gimple)
10597 return false;
10598
10599 /* Prevent gimple folding for code that does not have a LHS, unless it is
10600 allowed per the rs6000_builtin_valid_without_lhs helper function. */
10601 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
10602 return false;
10603
10604 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
10605 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
10606 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
10607 if (!func_valid_p)
10608 return false;
10609
10610 switch (fn_code)
10611 {
10612 /* Flavors of vec_add. We deliberately don't expand
10613 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
10614 TImode, resulting in much poorer code generation. */
10615 case ALTIVEC_BUILTIN_VADDUBM:
10616 case ALTIVEC_BUILTIN_VADDUHM:
10617 case ALTIVEC_BUILTIN_VADDUWM:
10618 case P8V_BUILTIN_VADDUDM:
10619 case ALTIVEC_BUILTIN_VADDFP:
10620 case VSX_BUILTIN_XVADDDP:
10621 bcode = PLUS_EXPR;
10622 do_binary:
10623 arg0 = gimple_call_arg (stmt, 0);
10624 arg1 = gimple_call_arg (stmt, 1);
10625 lhs = gimple_call_lhs (stmt);
10626 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs)))
10627 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs))))
10628 {
10629 /* Ensure the binary operation is performed in a type
10630 that wraps if it is integral type. */
10631 gimple_seq stmts = NULL;
10632 tree type = unsigned_type_for (TREE_TYPE (lhs));
10633 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
10634 type, arg0);
10635 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
10636 type, arg1);
10637 tree res = gimple_build (&stmts, gimple_location (stmt), bcode,
10638 type, uarg0, uarg1);
10639 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
10640 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR,
10641 build1 (VIEW_CONVERT_EXPR,
10642 TREE_TYPE (lhs), res));
10643 gsi_replace (gsi, g, true);
10644 return true;
10645 }
10646 g = gimple_build_assign (lhs, bcode, arg0, arg1);
10647 gimple_set_location (g, gimple_location (stmt));
10648 gsi_replace (gsi, g, true);
10649 return true;
10650 /* Flavors of vec_sub. We deliberately don't expand
10651 P8V_BUILTIN_VSUBUQM. */
10652 case ALTIVEC_BUILTIN_VSUBUBM:
10653 case ALTIVEC_BUILTIN_VSUBUHM:
10654 case ALTIVEC_BUILTIN_VSUBUWM:
10655 case P8V_BUILTIN_VSUBUDM:
10656 case ALTIVEC_BUILTIN_VSUBFP:
10657 case VSX_BUILTIN_XVSUBDP:
10658 bcode = MINUS_EXPR;
10659 goto do_binary;
10660 case VSX_BUILTIN_XVMULSP:
10661 case VSX_BUILTIN_XVMULDP:
10662 arg0 = gimple_call_arg (stmt, 0);
10663 arg1 = gimple_call_arg (stmt, 1);
10664 lhs = gimple_call_lhs (stmt);
10665 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
10666 gimple_set_location (g, gimple_location (stmt));
10667 gsi_replace (gsi, g, true);
10668 return true;
10669 /* Even element flavors of vec_mul (signed). */
10670 case ALTIVEC_BUILTIN_VMULESB:
10671 case ALTIVEC_BUILTIN_VMULESH:
10672 case P8V_BUILTIN_VMULESW:
10673 /* Even element flavors of vec_mul (unsigned). */
10674 case ALTIVEC_BUILTIN_VMULEUB:
10675 case ALTIVEC_BUILTIN_VMULEUH:
10676 case P8V_BUILTIN_VMULEUW:
10677 arg0 = gimple_call_arg (stmt, 0);
10678 arg1 = gimple_call_arg (stmt, 1);
10679 lhs = gimple_call_lhs (stmt);
10680 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
10681 gimple_set_location (g, gimple_location (stmt));
10682 gsi_replace (gsi, g, true);
10683 return true;
10684 /* Odd element flavors of vec_mul (signed). */
10685 case ALTIVEC_BUILTIN_VMULOSB:
10686 case ALTIVEC_BUILTIN_VMULOSH:
10687 case P8V_BUILTIN_VMULOSW:
10688 /* Odd element flavors of vec_mul (unsigned). */
10689 case ALTIVEC_BUILTIN_VMULOUB:
10690 case ALTIVEC_BUILTIN_VMULOUH:
10691 case P8V_BUILTIN_VMULOUW:
10692 arg0 = gimple_call_arg (stmt, 0);
10693 arg1 = gimple_call_arg (stmt, 1);
10694 lhs = gimple_call_lhs (stmt);
10695 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
10696 gimple_set_location (g, gimple_location (stmt));
10697 gsi_replace (gsi, g, true);
10698 return true;
10699 /* Flavors of vec_div (Integer). */
10700 case VSX_BUILTIN_DIV_V2DI:
10701 case VSX_BUILTIN_UDIV_V2DI:
10702 arg0 = gimple_call_arg (stmt, 0);
10703 arg1 = gimple_call_arg (stmt, 1);
10704 lhs = gimple_call_lhs (stmt);
10705 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
10706 gimple_set_location (g, gimple_location (stmt));
10707 gsi_replace (gsi, g, true);
10708 return true;
10709 /* Flavors of vec_div (Float). */
10710 case VSX_BUILTIN_XVDIVSP:
10711 case VSX_BUILTIN_XVDIVDP:
10712 arg0 = gimple_call_arg (stmt, 0);
10713 arg1 = gimple_call_arg (stmt, 1);
10714 lhs = gimple_call_lhs (stmt);
10715 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
10716 gimple_set_location (g, gimple_location (stmt));
10717 gsi_replace (gsi, g, true);
10718 return true;
10719 /* Flavors of vec_and. */
4559be23
PB		 10720 case ALTIVEC_BUILTIN_VAND_V16QI_UNS:
10721 case ALTIVEC_BUILTIN_VAND_V16QI:
10722 case ALTIVEC_BUILTIN_VAND_V8HI_UNS:
10723 case ALTIVEC_BUILTIN_VAND_V8HI:
10724 case ALTIVEC_BUILTIN_VAND_V4SI_UNS:
10725 case ALTIVEC_BUILTIN_VAND_V4SI:
10726 case ALTIVEC_BUILTIN_VAND_V2DI_UNS:
10727 case ALTIVEC_BUILTIN_VAND_V2DI:
10728 case ALTIVEC_BUILTIN_VAND_V4SF:
10729 case ALTIVEC_BUILTIN_VAND_V2DF:
1acf0246
BS		 10730 arg0 = gimple_call_arg (stmt, 0);
10731 arg1 = gimple_call_arg (stmt, 1);
10732 lhs = gimple_call_lhs (stmt);
10733 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
10734 gimple_set_location (g, gimple_location (stmt));
10735 gsi_replace (gsi, g, true);
10736 return true;
10737 /* Flavors of vec_andc. */
4559be23
PB		 10738 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS:
10739 case ALTIVEC_BUILTIN_VANDC_V16QI:
10740 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS:
10741 case ALTIVEC_BUILTIN_VANDC_V8HI:
10742 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS:
10743 case ALTIVEC_BUILTIN_VANDC_V4SI:
10744 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS:
10745 case ALTIVEC_BUILTIN_VANDC_V2DI:
10746 case ALTIVEC_BUILTIN_VANDC_V4SF:
10747 case ALTIVEC_BUILTIN_VANDC_V2DF:
1acf0246
BS		 10748 arg0 = gimple_call_arg (stmt, 0);
10749 arg1 = gimple_call_arg (stmt, 1);
10750 lhs = gimple_call_lhs (stmt);
10751 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
10752 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
10753 gimple_set_location (g, gimple_location (stmt));
10754 gsi_insert_before (gsi, g, GSI_SAME_STMT);
10755 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
10756 gimple_set_location (g, gimple_location (stmt));
10757 gsi_replace (gsi, g, true);
10758 return true;
10759 /* Flavors of vec_nand. */
10760 case P8V_BUILTIN_VEC_NAND:
4559be23 10761 case P8V_BUILTIN_NAND_V16QI_UNS:
1acf0246 10762 case P8V_BUILTIN_NAND_V16QI:
4559be23 10763 case P8V_BUILTIN_NAND_V8HI_UNS:
1acf0246 10764 case P8V_BUILTIN_NAND_V8HI:
4559be23 10765 case P8V_BUILTIN_NAND_V4SI_UNS:
1acf0246 10766 case P8V_BUILTIN_NAND_V4SI:
4559be23
PB		 10767 case P8V_BUILTIN_NAND_V2DI_UNS:
10768 case P8V_BUILTIN_NAND_V2DI:
1acf0246
BS		 10769 case P8V_BUILTIN_NAND_V4SF:
10770 case P8V_BUILTIN_NAND_V2DF:
1acf0246
BS		 10771 arg0 = gimple_call_arg (stmt, 0);
10772 arg1 = gimple_call_arg (stmt, 1);
10773 lhs = gimple_call_lhs (stmt);
10774 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
10775 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
10776 gimple_set_location (g, gimple_location (stmt));
10777 gsi_insert_before (gsi, g, GSI_SAME_STMT);
10778 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
10779 gimple_set_location (g, gimple_location (stmt));
10780 gsi_replace (gsi, g, true);
10781 return true;
10782 /* Flavors of vec_or. */
4559be23
PB		 10783 case ALTIVEC_BUILTIN_VOR_V16QI_UNS:
10784 case ALTIVEC_BUILTIN_VOR_V16QI:
10785 case ALTIVEC_BUILTIN_VOR_V8HI_UNS:
10786 case ALTIVEC_BUILTIN_VOR_V8HI:
10787 case ALTIVEC_BUILTIN_VOR_V4SI_UNS:
10788 case ALTIVEC_BUILTIN_VOR_V4SI:
10789 case ALTIVEC_BUILTIN_VOR_V2DI_UNS:
10790 case ALTIVEC_BUILTIN_VOR_V2DI:
10791 case ALTIVEC_BUILTIN_VOR_V4SF:
10792 case ALTIVEC_BUILTIN_VOR_V2DF:
1acf0246
BS		 10793 arg0 = gimple_call_arg (stmt, 0);
10794 arg1 = gimple_call_arg (stmt, 1);
10795 lhs = gimple_call_lhs (stmt);
10796 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
10797 gimple_set_location (g, gimple_location (stmt));
10798 gsi_replace (gsi, g, true);
10799 return true;
10800 /* flavors of vec_orc. */
4559be23 10801 case P8V_BUILTIN_ORC_V16QI_UNS:
1acf0246 10802 case P8V_BUILTIN_ORC_V16QI:
4559be23 10803 case P8V_BUILTIN_ORC_V8HI_UNS:
1acf0246 10804 case P8V_BUILTIN_ORC_V8HI:
4559be23 10805 case P8V_BUILTIN_ORC_V4SI_UNS:
1acf0246 10806 case P8V_BUILTIN_ORC_V4SI:
4559be23
PB		 10807 case P8V_BUILTIN_ORC_V2DI_UNS:
10808 case P8V_BUILTIN_ORC_V2DI:
1acf0246
BS		 10809 case P8V_BUILTIN_ORC_V4SF:
10810 case P8V_BUILTIN_ORC_V2DF:
1acf0246
BS		 10811 arg0 = gimple_call_arg (stmt, 0);
10812 arg1 = gimple_call_arg (stmt, 1);
10813 lhs = gimple_call_lhs (stmt);
10814 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
10815 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
10816 gimple_set_location (g, gimple_location (stmt));
10817 gsi_insert_before (gsi, g, GSI_SAME_STMT);
10818 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
10819 gimple_set_location (g, gimple_location (stmt));
10820 gsi_replace (gsi, g, true);
10821 return true;
10822 /* Flavors of vec_xor. */
4559be23
PB		 10823 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS:
10824 case ALTIVEC_BUILTIN_VXOR_V16QI:
10825 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS:
10826 case ALTIVEC_BUILTIN_VXOR_V8HI:
10827 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS:
10828 case ALTIVEC_BUILTIN_VXOR_V4SI:
10829 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS:
10830 case ALTIVEC_BUILTIN_VXOR_V2DI:
10831 case ALTIVEC_BUILTIN_VXOR_V4SF:
10832 case ALTIVEC_BUILTIN_VXOR_V2DF:
1acf0246
BS		 10833 arg0 = gimple_call_arg (stmt, 0);
10834 arg1 = gimple_call_arg (stmt, 1);
10835 lhs = gimple_call_lhs (stmt);
10836 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
10837 gimple_set_location (g, gimple_location (stmt));
10838 gsi_replace (gsi, g, true);
10839 return true;
10840 /* Flavors of vec_nor. */
4559be23
PB		 10841 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS:
10842 case ALTIVEC_BUILTIN_VNOR_V16QI:
10843 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS:
10844 case ALTIVEC_BUILTIN_VNOR_V8HI:
10845 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS:
10846 case ALTIVEC_BUILTIN_VNOR_V4SI:
10847 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS:
10848 case ALTIVEC_BUILTIN_VNOR_V2DI:
10849 case ALTIVEC_BUILTIN_VNOR_V4SF:
10850 case ALTIVEC_BUILTIN_VNOR_V2DF:
1acf0246
BS		 10851 arg0 = gimple_call_arg (stmt, 0);
10852 arg1 = gimple_call_arg (stmt, 1);
10853 lhs = gimple_call_lhs (stmt);
10854 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
10855 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
10856 gimple_set_location (g, gimple_location (stmt));
10857 gsi_insert_before (gsi, g, GSI_SAME_STMT);
10858 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
10859 gimple_set_location (g, gimple_location (stmt));
10860 gsi_replace (gsi, g, true);
10861 return true;
10862 /* flavors of vec_abs. */
10863 case ALTIVEC_BUILTIN_ABS_V16QI:
10864 case ALTIVEC_BUILTIN_ABS_V8HI:
10865 case ALTIVEC_BUILTIN_ABS_V4SI:
10866 case ALTIVEC_BUILTIN_ABS_V4SF:
10867 case P8V_BUILTIN_ABS_V2DI:
10868 case VSX_BUILTIN_XVABSDP:
10869 arg0 = gimple_call_arg (stmt, 0);
10870 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
10871 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
10872 return false;
10873 lhs = gimple_call_lhs (stmt);
10874 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
10875 gimple_set_location (g, gimple_location (stmt));
10876 gsi_replace (gsi, g, true);
10877 return true;
10878 /* flavors of vec_min. */
10879 case VSX_BUILTIN_XVMINDP:
10880 case P8V_BUILTIN_VMINSD:
10881 case P8V_BUILTIN_VMINUD:
10882 case ALTIVEC_BUILTIN_VMINSB:
10883 case ALTIVEC_BUILTIN_VMINSH:
10884 case ALTIVEC_BUILTIN_VMINSW:
10885 case ALTIVEC_BUILTIN_VMINUB:
10886 case ALTIVEC_BUILTIN_VMINUH:
10887 case ALTIVEC_BUILTIN_VMINUW:
10888 case ALTIVEC_BUILTIN_VMINFP:
10889 arg0 = gimple_call_arg (stmt, 0);
10890 arg1 = gimple_call_arg (stmt, 1);
10891 lhs = gimple_call_lhs (stmt);
10892 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
10893 gimple_set_location (g, gimple_location (stmt));
10894 gsi_replace (gsi, g, true);
10895 return true;
10896 /* flavors of vec_max. */
10897 case VSX_BUILTIN_XVMAXDP:
10898 case P8V_BUILTIN_VMAXSD:
10899 case P8V_BUILTIN_VMAXUD:
10900 case ALTIVEC_BUILTIN_VMAXSB:
10901 case ALTIVEC_BUILTIN_VMAXSH:
10902 case ALTIVEC_BUILTIN_VMAXSW:
10903 case ALTIVEC_BUILTIN_VMAXUB:
10904 case ALTIVEC_BUILTIN_VMAXUH:
10905 case ALTIVEC_BUILTIN_VMAXUW:
10906 case ALTIVEC_BUILTIN_VMAXFP:
10907 arg0 = gimple_call_arg (stmt, 0);
10908 arg1 = gimple_call_arg (stmt, 1);
10909 lhs = gimple_call_lhs (stmt);
10910 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
10911 gimple_set_location (g, gimple_location (stmt));
10912 gsi_replace (gsi, g, true);
10913 return true;
10914 /* Flavors of vec_eqv. */
10915 case P8V_BUILTIN_EQV_V16QI:
10916 case P8V_BUILTIN_EQV_V8HI:
10917 case P8V_BUILTIN_EQV_V4SI:
10918 case P8V_BUILTIN_EQV_V4SF:
10919 case P8V_BUILTIN_EQV_V2DF:
10920 case P8V_BUILTIN_EQV_V2DI:
10921 arg0 = gimple_call_arg (stmt, 0);
10922 arg1 = gimple_call_arg (stmt, 1);
10923 lhs = gimple_call_lhs (stmt);
10924 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
10925 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
10926 gimple_set_location (g, gimple_location (stmt));
10927 gsi_insert_before (gsi, g, GSI_SAME_STMT);
10928 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
10929 gimple_set_location (g, gimple_location (stmt));
10930 gsi_replace (gsi, g, true);
10931 return true;
10932 /* Flavors of vec_rotate_left. */
10933 case ALTIVEC_BUILTIN_VRLB:
10934 case ALTIVEC_BUILTIN_VRLH:
10935 case ALTIVEC_BUILTIN_VRLW:
10936 case P8V_BUILTIN_VRLD:
10937 arg0 = gimple_call_arg (stmt, 0);
10938 arg1 = gimple_call_arg (stmt, 1);
10939 lhs = gimple_call_lhs (stmt);
10940 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
10941 gimple_set_location (g, gimple_location (stmt));
10942 gsi_replace (gsi, g, true);
10943 return true;
10944 /* Flavors of vector shift right algebraic.
10945 vec_sra{b,h,w} -> vsra{b,h,w}. */
10946 case ALTIVEC_BUILTIN_VSRAB:
10947 case ALTIVEC_BUILTIN_VSRAH:
10948 case ALTIVEC_BUILTIN_VSRAW:
10949 case P8V_BUILTIN_VSRAD:
10950 {
10951 arg0 = gimple_call_arg (stmt, 0);
10952 arg1 = gimple_call_arg (stmt, 1);
10953 lhs = gimple_call_lhs (stmt);
10954 tree arg1_type = TREE_TYPE (arg1);
10955 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
10956 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
10957 location_t loc = gimple_location (stmt);
10958 /* Force arg1 into the range valid matching the arg0 type. */
10959 /* Build a vector consisting of the max valid bit-size values. */
10960 int n_elts = VECTOR_CST_NELTS (arg1);
10961 tree element_size = build_int_cst (unsigned_element_type,
10962 128 / n_elts);
10963 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
10964 for (int i = 0; i < n_elts; i++)
10965 elts.safe_push (element_size);
10966 tree modulo_tree = elts.build ();
10967 /* Modulo the provided shift value against that vector. */
10968 gimple_seq stmts = NULL;
10969 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
10970 unsigned_arg1_type, arg1);
10971 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
10972 unsigned_arg1_type, unsigned_arg1,
10973 modulo_tree);
10974 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
10975 /* And finally, do the shift. */
10976 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1);
10977 gimple_set_location (g, loc);
10978 gsi_replace (gsi, g, true);
10979 return true;
10980 }
10981 /* Flavors of vector shift left.
10982 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
10983 case ALTIVEC_BUILTIN_VSLB:
10984 case ALTIVEC_BUILTIN_VSLH:
10985 case ALTIVEC_BUILTIN_VSLW:
10986 case P8V_BUILTIN_VSLD:
10987 {
10988 location_t loc;
10989 gimple_seq stmts = NULL;
10990 arg0 = gimple_call_arg (stmt, 0);
10991 tree arg0_type = TREE_TYPE (arg0);
10992 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
10993 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
10994 return false;
10995 arg1 = gimple_call_arg (stmt, 1);
10996 tree arg1_type = TREE_TYPE (arg1);
10997 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
10998 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
10999 loc = gimple_location (stmt);
11000 lhs = gimple_call_lhs (stmt);
11001 /* Force arg1 into the range valid matching the arg0 type. */
11002 /* Build a vector consisting of the max valid bit-size values. */
11003 int n_elts = VECTOR_CST_NELTS (arg1);
11004 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
11005 * BITS_PER_UNIT;
11006 tree element_size = build_int_cst (unsigned_element_type,
11007 tree_size_in_bits / n_elts);
11008 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
11009 for (int i = 0; i < n_elts; i++)
11010 elts.safe_push (element_size);
11011 tree modulo_tree = elts.build ();
11012 /* Modulo the provided shift value against that vector. */
11013 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11014 unsigned_arg1_type, arg1);
11015 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
11016 unsigned_arg1_type, unsigned_arg1,
11017 modulo_tree);
11018 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11019 /* And finally, do the shift. */
11020 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
11021 gimple_set_location (g, gimple_location (stmt));
11022 gsi_replace (gsi, g, true);
11023 return true;
11024 }
11025 /* Flavors of vector shift right. */
11026 case ALTIVEC_BUILTIN_VSRB:
11027 case ALTIVEC_BUILTIN_VSRH:
11028 case ALTIVEC_BUILTIN_VSRW:
11029 case P8V_BUILTIN_VSRD:
11030 {
11031 arg0 = gimple_call_arg (stmt, 0);
11032 arg1 = gimple_call_arg (stmt, 1);
11033 lhs = gimple_call_lhs (stmt);
11034 tree arg1_type = TREE_TYPE (arg1);
11035 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
11036 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
11037 location_t loc = gimple_location (stmt);
11038 gimple_seq stmts = NULL;
11039 /* Convert arg0 to unsigned. */
11040 tree arg0_unsigned
11041 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11042 unsigned_type_for (TREE_TYPE (arg0)), arg0);
11043 /* Force arg1 into the range valid matching the arg0 type. */
11044 /* Build a vector consisting of the max valid bit-size values. */
11045 int n_elts = VECTOR_CST_NELTS (arg1);
11046 tree element_size = build_int_cst (unsigned_element_type,
11047 128 / n_elts);
11048 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
11049 for (int i = 0; i < n_elts; i++)
11050 elts.safe_push (element_size);
11051 tree modulo_tree = elts.build ();
11052 /* Modulo the provided shift value against that vector. */
11053 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11054 unsigned_arg1_type, arg1);
11055 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
11056 unsigned_arg1_type, unsigned_arg1,
11057 modulo_tree);
11058 /* Do the shift. */
11059 tree res
11060 = gimple_build (&stmts, RSHIFT_EXPR,
11061 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1);
11062 /* Convert result back to the lhs type. */
11063 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
11064 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11065 update_call_from_tree (gsi, res);
11066 return true;
11067 }
11068 /* Vector loads. */
11069 case ALTIVEC_BUILTIN_LVX_V16QI:
11070 case ALTIVEC_BUILTIN_LVX_V8HI:
11071 case ALTIVEC_BUILTIN_LVX_V4SI:
11072 case ALTIVEC_BUILTIN_LVX_V4SF:
11073 case ALTIVEC_BUILTIN_LVX_V2DI:
11074 case ALTIVEC_BUILTIN_LVX_V2DF:
11075 case ALTIVEC_BUILTIN_LVX_V1TI:
11076 {
11077 arg0 = gimple_call_arg (stmt, 0); // offset
11078 arg1 = gimple_call_arg (stmt, 1); // address
11079 lhs = gimple_call_lhs (stmt);
11080 location_t loc = gimple_location (stmt);
11081 /* Since arg1 may be cast to a different type, just use ptr_type_node
11082 here instead of trying to enforce TBAA on pointer types. */
11083 tree arg1_type = ptr_type_node;
11084 tree lhs_type = TREE_TYPE (lhs);
11085 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
11086 the tree using the value from arg0. The resulting type will match
11087 the type of arg1. */
11088 gimple_seq stmts = NULL;
11089 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
11090 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
11091 arg1_type, arg1, temp_offset);
11092 /* Mask off any lower bits from the address. */
11093 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
11094 arg1_type, temp_addr,
11095 build_int_cst (arg1_type, -16));
11096 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11097 if (!is_gimple_mem_ref_addr (aligned_addr))
11098 {
11099 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
11100 gimple *g = gimple_build_assign (t, aligned_addr);
11101 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11102 aligned_addr = t;
11103 }
11104 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
11105 take an offset, but since we've already incorporated the offset
11106 above, here we just pass in a zero. */
11107 gimple *g
11108 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
11109 build_int_cst (arg1_type, 0)));
11110 gimple_set_location (g, loc);
11111 gsi_replace (gsi, g, true);
11112 return true;
11113 }
11114 /* Vector stores. */
11115 case ALTIVEC_BUILTIN_STVX_V16QI:
11116 case ALTIVEC_BUILTIN_STVX_V8HI:
11117 case ALTIVEC_BUILTIN_STVX_V4SI:
11118 case ALTIVEC_BUILTIN_STVX_V4SF:
11119 case ALTIVEC_BUILTIN_STVX_V2DI:
11120 case ALTIVEC_BUILTIN_STVX_V2DF:
11121 {
11122 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
11123 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
11124 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
11125 location_t loc = gimple_location (stmt);
11126 tree arg0_type = TREE_TYPE (arg0);
11127 /* Use ptr_type_node (no TBAA) for the arg2_type.
11128 FIXME: (Richard) "A proper fix would be to transition this type as
11129 seen from the frontend to GIMPLE, for example in a similar way we
11130 do for MEM_REFs by piggy-backing that on an extra argument, a
11131 constant zero pointer of the alias pointer type to use (which would
11132 also serve as a type indicator of the store itself). I'd use a
11133 target specific internal function for this (not sure if we can have
11134 those target specific, but I guess if it's folded away then that's
11135 fine) and get away with the overload set." */
11136 tree arg2_type = ptr_type_node;
11137 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
11138 the tree using the value from arg0. The resulting type will match
11139 the type of arg2. */
11140 gimple_seq stmts = NULL;
11141 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
11142 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
11143 arg2_type, arg2, temp_offset);
11144 /* Mask off any lower bits from the address. */
11145 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
11146 arg2_type, temp_addr,
11147 build_int_cst (arg2_type, -16));
11148 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11149 if (!is_gimple_mem_ref_addr (aligned_addr))
11150 {
11151 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
11152 gimple *g = gimple_build_assign (t, aligned_addr);
11153 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11154 aligned_addr = t;
11155 }
11156 /* The desired gimple result should be similar to:
11157 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
11158 gimple *g
11159 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
11160 build_int_cst (arg2_type, 0)), arg0);
11161 gimple_set_location (g, loc);
11162 gsi_replace (gsi, g, true);
11163 return true;
11164 }
11165
11166 /* unaligned Vector loads. */
11167 case VSX_BUILTIN_LXVW4X_V16QI:
11168 case VSX_BUILTIN_LXVW4X_V8HI:
11169 case VSX_BUILTIN_LXVW4X_V4SF:
11170 case VSX_BUILTIN_LXVW4X_V4SI:
11171 case VSX_BUILTIN_LXVD2X_V2DF:
11172 case VSX_BUILTIN_LXVD2X_V2DI:
11173 {
11174 arg0 = gimple_call_arg (stmt, 0); // offset
11175 arg1 = gimple_call_arg (stmt, 1); // address
11176 lhs = gimple_call_lhs (stmt);
11177 location_t loc = gimple_location (stmt);
11178 /* Since arg1 may be cast to a different type, just use ptr_type_node
11179 here instead of trying to enforce TBAA on pointer types. */
11180 tree arg1_type = ptr_type_node;
11181 tree lhs_type = TREE_TYPE (lhs);
11182 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
11183 required alignment (power) is 4 bytes regardless of data type. */
11184 tree align_ltype = build_aligned_type (lhs_type, 4);
11185 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
11186 the tree using the value from arg0. The resulting type will match
11187 the type of arg1. */
11188 gimple_seq stmts = NULL;
11189 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
11190 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
11191 arg1_type, arg1, temp_offset);
11192 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11193 if (!is_gimple_mem_ref_addr (temp_addr))
11194 {
11195 tree t = make_ssa_name (TREE_TYPE (temp_addr));
11196 gimple *g = gimple_build_assign (t, temp_addr);
11197 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11198 temp_addr = t;
11199 }
11200 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
11201 take an offset, but since we've already incorporated the offset
11202 above, here we just pass in a zero. */
11203 gimple *g;
11204 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
11205 build_int_cst (arg1_type, 0)));
11206 gimple_set_location (g, loc);
11207 gsi_replace (gsi, g, true);
11208 return true;
11209 }
11210
11211 /* unaligned Vector stores. */
11212 case VSX_BUILTIN_STXVW4X_V16QI:
11213 case VSX_BUILTIN_STXVW4X_V8HI:
11214 case VSX_BUILTIN_STXVW4X_V4SF:
11215 case VSX_BUILTIN_STXVW4X_V4SI:
11216 case VSX_BUILTIN_STXVD2X_V2DF:
11217 case VSX_BUILTIN_STXVD2X_V2DI:
11218 {
11219 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
11220 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
11221 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
11222 location_t loc = gimple_location (stmt);
11223 tree arg0_type = TREE_TYPE (arg0);
11224 /* Use ptr_type_node (no TBAA) for the arg2_type. */
11225 tree arg2_type = ptr_type_node;
11226 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
11227 required alignment (power) is 4 bytes regardless of data type. */
11228 tree align_stype = build_aligned_type (arg0_type, 4);
11229 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
11230 the tree using the value from arg1. */
11231 gimple_seq stmts = NULL;
11232 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
11233 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
11234 arg2_type, arg2, temp_offset);
11235 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11236 if (!is_gimple_mem_ref_addr (temp_addr))
11237 {
11238 tree t = make_ssa_name (TREE_TYPE (temp_addr));
11239 gimple *g = gimple_build_assign (t, temp_addr);
11240 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11241 temp_addr = t;
11242 }
11243 gimple *g;
11244 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
11245 build_int_cst (arg2_type, 0)), arg0);
11246 gimple_set_location (g, loc);
11247 gsi_replace (gsi, g, true);
11248 return true;
11249 }
11250
11251 /* Vector Fused multiply-add (fma). */
11252 case ALTIVEC_BUILTIN_VMADDFP:
11253 case VSX_BUILTIN_XVMADDDP:
11254 case ALTIVEC_BUILTIN_VMLADDUHM:
11255 {
11256 arg0 = gimple_call_arg (stmt, 0);
11257 arg1 = gimple_call_arg (stmt, 1);
11258 tree arg2 = gimple_call_arg (stmt, 2);
11259 lhs = gimple_call_lhs (stmt);
11260 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
11261 gimple_call_set_lhs (g, lhs);
11262 gimple_call_set_nothrow (g, true);
11263 gimple_set_location (g, gimple_location (stmt));
11264 gsi_replace (gsi, g, true);
11265 return true;
11266 }
11267
11268 /* Vector compares; EQ, NE, GE, GT, LE. */
11269 case ALTIVEC_BUILTIN_VCMPEQUB:
11270 case ALTIVEC_BUILTIN_VCMPEQUH:
11271 case ALTIVEC_BUILTIN_VCMPEQUW:
11272 case P8V_BUILTIN_VCMPEQUD:
11273 fold_compare_helper (gsi, EQ_EXPR, stmt);
11274 return true;
11275
11276 case P9V_BUILTIN_CMPNEB:
11277 case P9V_BUILTIN_CMPNEH:
11278 case P9V_BUILTIN_CMPNEW:
11279 fold_compare_helper (gsi, NE_EXPR, stmt);
11280 return true;
11281
11282 case VSX_BUILTIN_CMPGE_16QI:
11283 case VSX_BUILTIN_CMPGE_U16QI:
11284 case VSX_BUILTIN_CMPGE_8HI:
11285 case VSX_BUILTIN_CMPGE_U8HI:
11286 case VSX_BUILTIN_CMPGE_4SI:
11287 case VSX_BUILTIN_CMPGE_U4SI:
11288 case VSX_BUILTIN_CMPGE_2DI:
11289 case VSX_BUILTIN_CMPGE_U2DI:
11290 fold_compare_helper (gsi, GE_EXPR, stmt);
11291 return true;
11292
11293 case ALTIVEC_BUILTIN_VCMPGTSB:
11294 case ALTIVEC_BUILTIN_VCMPGTUB:
11295 case ALTIVEC_BUILTIN_VCMPGTSH:
11296 case ALTIVEC_BUILTIN_VCMPGTUH:
11297 case ALTIVEC_BUILTIN_VCMPGTSW:
11298 case ALTIVEC_BUILTIN_VCMPGTUW:
11299 case P8V_BUILTIN_VCMPGTUD:
11300 case P8V_BUILTIN_VCMPGTSD:
11301 fold_compare_helper (gsi, GT_EXPR, stmt);
11302 return true;
11303
11304 case VSX_BUILTIN_CMPLE_16QI:
11305 case VSX_BUILTIN_CMPLE_U16QI:
11306 case VSX_BUILTIN_CMPLE_8HI:
11307 case VSX_BUILTIN_CMPLE_U8HI:
11308 case VSX_BUILTIN_CMPLE_4SI:
11309 case VSX_BUILTIN_CMPLE_U4SI:
11310 case VSX_BUILTIN_CMPLE_2DI:
11311 case VSX_BUILTIN_CMPLE_U2DI:
11312 fold_compare_helper (gsi, LE_EXPR, stmt);
11313 return true;
11314
11315 /* flavors of vec_splat_[us]{8,16,32}. */
11316 case ALTIVEC_BUILTIN_VSPLTISB:
11317 case ALTIVEC_BUILTIN_VSPLTISH:
11318 case ALTIVEC_BUILTIN_VSPLTISW:
11319 {
11320 arg0 = gimple_call_arg (stmt, 0);
11321 lhs = gimple_call_lhs (stmt);
11322
11323 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
11324 5-bit signed constant in range -16 to +15. */
11325 if (TREE_CODE (arg0) != INTEGER_CST
11326 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15))
11327 return false;
11328 gimple_seq stmts = NULL;
11329 location_t loc = gimple_location (stmt);
11330 tree splat_value = gimple_convert (&stmts, loc,
11331 TREE_TYPE (TREE_TYPE (lhs)), arg0);
11332 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11333 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
11334 g = gimple_build_assign (lhs, splat_tree);
11335 gimple_set_location (g, gimple_location (stmt));
11336 gsi_replace (gsi, g, true);
11337 return true;
11338 }
11339
11340 /* Flavors of vec_splat. */
11341 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
11342 case ALTIVEC_BUILTIN_VSPLTB:
11343 case ALTIVEC_BUILTIN_VSPLTH:
11344 case ALTIVEC_BUILTIN_VSPLTW:
11345 case VSX_BUILTIN_XXSPLTD_V2DI:
11346 case VSX_BUILTIN_XXSPLTD_V2DF:
11347 {
11348 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
11349 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
11350 /* Only fold the vec_splat_*() if arg1 is both a constant value and
11351 is a valid index into the arg0 vector. */
11352 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
11353 if (TREE_CODE (arg1) != INTEGER_CST
11354 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
11355 return false;
11356 lhs = gimple_call_lhs (stmt);
11357 tree lhs_type = TREE_TYPE (lhs);
11358 tree arg0_type = TREE_TYPE (arg0);
11359 tree splat;
11360 if (TREE_CODE (arg0) == VECTOR_CST)
11361 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
11362 else
11363 {
11364 /* Determine (in bits) the length and start location of the
11365 splat value for a call to the tree_vec_extract helper. */
11366 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
11367 * BITS_PER_UNIT / n_elts;
11368 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
11369 tree len = build_int_cst (bitsizetype, splat_elem_size);
11370 tree start = build_int_cst (bitsizetype, splat_start_bit);
11371 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
11372 len, start);
11373 }
11374 /* And finally, build the new vector. */
11375 tree splat_tree = build_vector_from_val (lhs_type, splat);
11376 g = gimple_build_assign (lhs, splat_tree);
11377 gimple_set_location (g, gimple_location (stmt));
11378 gsi_replace (gsi, g, true);
11379 return true;
11380 }
11381
11382 /* vec_mergel (integrals). */
11383 case ALTIVEC_BUILTIN_VMRGLH:
11384 case ALTIVEC_BUILTIN_VMRGLW:
11385 case VSX_BUILTIN_XXMRGLW_4SI:
11386 case ALTIVEC_BUILTIN_VMRGLB:
11387 case VSX_BUILTIN_VEC_MERGEL_V2DI:
11388 case VSX_BUILTIN_XXMRGLW_4SF:
11389 case VSX_BUILTIN_VEC_MERGEL_V2DF:
11390 fold_mergehl_helper (gsi, stmt, 1);
11391 return true;
11392 /* vec_mergeh (integrals). */
11393 case ALTIVEC_BUILTIN_VMRGHH:
11394 case ALTIVEC_BUILTIN_VMRGHW:
11395 case VSX_BUILTIN_XXMRGHW_4SI:
11396 case ALTIVEC_BUILTIN_VMRGHB:
11397 case VSX_BUILTIN_VEC_MERGEH_V2DI:
11398 case VSX_BUILTIN_XXMRGHW_4SF:
11399 case VSX_BUILTIN_VEC_MERGEH_V2DF:
11400 fold_mergehl_helper (gsi, stmt, 0);
11401 return true;
11402
11403 /* Flavors of vec_mergee. */
11404 case P8V_BUILTIN_VMRGEW_V4SI:
11405 case P8V_BUILTIN_VMRGEW_V2DI:
11406 case P8V_BUILTIN_VMRGEW_V4SF:
11407 case P8V_BUILTIN_VMRGEW_V2DF:
11408 fold_mergeeo_helper (gsi, stmt, 0);
11409 return true;
11410 /* Flavors of vec_mergeo. */
11411 case P8V_BUILTIN_VMRGOW_V4SI:
11412 case P8V_BUILTIN_VMRGOW_V2DI:
11413 case P8V_BUILTIN_VMRGOW_V4SF:
11414 case P8V_BUILTIN_VMRGOW_V2DF:
11415 fold_mergeeo_helper (gsi, stmt, 1);
11416 return true;
11417
11418 /* d = vec_pack (a, b) */
11419 case P8V_BUILTIN_VPKUDUM:
11420 case ALTIVEC_BUILTIN_VPKUHUM:
11421 case ALTIVEC_BUILTIN_VPKUWUM:
11422 {
11423 arg0 = gimple_call_arg (stmt, 0);
11424 arg1 = gimple_call_arg (stmt, 1);
11425 lhs = gimple_call_lhs (stmt);
11426 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
11427 gimple_set_location (g, gimple_location (stmt));
11428 gsi_replace (gsi, g, true);
11429 return true;
11430 }
11431
11432 /* d = vec_unpackh (a) */
11433 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
11434 in this code is sensitive to endian-ness, and needs to be inverted to
11435 handle both LE and BE targets. */
11436 case ALTIVEC_BUILTIN_VUPKHSB:
11437 case ALTIVEC_BUILTIN_VUPKHSH:
11438 case P8V_BUILTIN_VUPKHSW:
11439 {
11440 arg0 = gimple_call_arg (stmt, 0);
11441 lhs = gimple_call_lhs (stmt);
11442 if (BYTES_BIG_ENDIAN)
11443 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
11444 else
11445 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
11446 gimple_set_location (g, gimple_location (stmt));
11447 gsi_replace (gsi, g, true);
11448 return true;
11449 }
11450 /* d = vec_unpackl (a) */
11451 case ALTIVEC_BUILTIN_VUPKLSB:
11452 case ALTIVEC_BUILTIN_VUPKLSH:
11453 case P8V_BUILTIN_VUPKLSW:
11454 {
11455 arg0 = gimple_call_arg (stmt, 0);
11456 lhs = gimple_call_lhs (stmt);
11457 if (BYTES_BIG_ENDIAN)
11458 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
11459 else
11460 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
11461 gimple_set_location (g, gimple_location (stmt));
11462 gsi_replace (gsi, g, true);
11463 return true;
11464 }
11465 /* There is no gimple type corresponding with pixel, so just return. */
11466 case ALTIVEC_BUILTIN_VUPKHPX:
11467 case ALTIVEC_BUILTIN_VUPKLPX:
11468 return false;
11469
11470 /* vec_perm. */
11471 case ALTIVEC_BUILTIN_VPERM_16QI:
11472 case ALTIVEC_BUILTIN_VPERM_8HI:
11473 case ALTIVEC_BUILTIN_VPERM_4SI:
11474 case ALTIVEC_BUILTIN_VPERM_2DI:
11475 case ALTIVEC_BUILTIN_VPERM_4SF:
11476 case ALTIVEC_BUILTIN_VPERM_2DF:
11477 {
11478 arg0 = gimple_call_arg (stmt, 0);
11479 arg1 = gimple_call_arg (stmt, 1);
11480 tree permute = gimple_call_arg (stmt, 2);
11481 lhs = gimple_call_lhs (stmt);
11482 location_t loc = gimple_location (stmt);
11483 gimple_seq stmts = NULL;
11484 // convert arg0 and arg1 to match the type of the permute
11485 // for the VEC_PERM_EXPR operation.
11486 tree permute_type = (TREE_TYPE (permute));
b6d53324
RS		 11487 tree arg0_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
11488 permute_type, arg0);
11489 tree arg1_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
11490 permute_type, arg1);
1acf0246
BS		 11491 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
11492 permute_type, arg0_ptype, arg1_ptype,
11493 permute);
11494 // Convert the result back to the desired lhs type upon completion.
b6d53324
RS		 11495 tree temp = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
11496 TREE_TYPE (lhs), lhs_ptype);
1acf0246
BS		 11497 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11498 g = gimple_build_assign (lhs, temp);
11499 gimple_set_location (g, loc);
11500 gsi_replace (gsi, g, true);
11501 return true;
11502 }
11503
11504 default:
11505 if (TARGET_DEBUG_BUILTIN)
11506 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
11507 fn_code, fn_name1, fn_name2);
11508 break;
11509 }
11510
11511 return false;
11512}
11513
11514/* Expand an expression EXP that calls a built-in function,
11515 with result going to TARGET if that's convenient
11516 (and in mode MODE if that's convenient).
11517 SUBTARGET may be used as the target for computing one of EXP's operands.
11518 IGNORE is nonzero if the value is to be ignored. */
11519
11520rtx
11521rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11522 machine_mode mode ATTRIBUTE_UNUSED,
11523 int ignore ATTRIBUTE_UNUSED)
11524{
11525 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11526 enum rs6000_builtins fcode
4d732405 11527 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 11528 size_t uns_fcode = (size_t)fcode;
11529 const struct builtin_description *d;
11530 size_t i;
11531 rtx ret;
11532 bool success;
11533 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
11534 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
11535 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
11536
11537 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
11538 floating point type, depending on whether long double is the IBM extended
11539 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
11540 we only define one variant of the built-in function, and switch the code
11541 when defining it, rather than defining two built-ins and using the
11542 overload table in rs6000-c.c to switch between the two. If we don't have
11543 the proper assembler, don't do this switch because CODE_FOR_*kf* and
11544 CODE_FOR_*tf* will be CODE_FOR_nothing. */
11545 if (FLOAT128_IEEE_P (TFmode))
11546 switch (icode)
11547 {
11548 default:
11549 break;
11550
11551 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
11552 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
11553 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
11554 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
11555 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
11556 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
11557 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
11558 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
11559 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
11560 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
11561 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
11562 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
11563 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
11564 }
11565
11566 if (TARGET_DEBUG_BUILTIN)
11567 {
11568 const char *name1 = rs6000_builtin_info[uns_fcode].name;
11569 const char *name2 = (icode != CODE_FOR_nothing)
11570 ? get_insn_name ((int) icode)
11571 : "nothing";
11572 const char *name3;
11573
11574 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
11575 {
11576 default: name3 = "unknown"; break;
11577 case RS6000_BTC_SPECIAL: name3 = "special"; break;
11578 case RS6000_BTC_UNARY: name3 = "unary"; break;
11579 case RS6000_BTC_BINARY: name3 = "binary"; break;
11580 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
11581 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
11582 case RS6000_BTC_ABS: name3 = "abs"; break;
11583 case RS6000_BTC_DST: name3 = "dst"; break;
11584 }
11585
11586
11587 fprintf (stderr,
11588 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11589 (name1) ? name1 : "---", fcode,
11590 (name2) ? name2 : "---", (int) icode,
11591 name3,
11592 func_valid_p ? "" : ", not valid");
11593 }
11594
11595 if (!func_valid_p)
11596 {
11597 rs6000_invalid_builtin (fcode);
11598
11599 /* Given it is invalid, just generate a normal call. */
11600 return expand_call (exp, target, ignore);
11601 }
11602
11603 switch (fcode)
11604 {
11605 case RS6000_BUILTIN_RECIP:
11606 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
11607
11608 case RS6000_BUILTIN_RECIPF:
11609 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
11610
11611 case RS6000_BUILTIN_RSQRTF:
11612 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
11613
11614 case RS6000_BUILTIN_RSQRT:
11615 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
11616
11617 case POWER7_BUILTIN_BPERMD:
11618 return rs6000_expand_binop_builtin (((TARGET_64BIT)
11619 ? CODE_FOR_bpermd_di
11620 : CODE_FOR_bpermd_si), exp, target);
11621
11622 case RS6000_BUILTIN_GET_TB:
11623 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
11624 target);
11625
11626 case RS6000_BUILTIN_MFTB:
11627 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
11628 ? CODE_FOR_rs6000_mftb_di
11629 : CODE_FOR_rs6000_mftb_si),
11630 target);
11631
11632 case RS6000_BUILTIN_MFFS:
11633 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
11634
11635 case RS6000_BUILTIN_MTFSB0:
11636 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
11637
11638 case RS6000_BUILTIN_MTFSB1:
11639 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
11640
11641 case RS6000_BUILTIN_SET_FPSCR_RN:
11642 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
11643 exp);
11644
11645 case RS6000_BUILTIN_SET_FPSCR_DRN:
11646 return
11647 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
11648 exp);
11649
11650 case RS6000_BUILTIN_MFFSL:
11651 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
11652
11653 case RS6000_BUILTIN_MTFSF:
11654 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
11655
11656 case RS6000_BUILTIN_CPU_INIT:
11657 case RS6000_BUILTIN_CPU_IS:
11658 case RS6000_BUILTIN_CPU_SUPPORTS:
11659 return cpu_expand_builtin (fcode, exp, target);
11660
11661 case MISC_BUILTIN_SPEC_BARRIER:
11662 {
11663 emit_insn (gen_speculation_barrier ());
11664 return NULL_RTX;
11665 }
11666
11667 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
11668 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
11669 {
11670 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
11671 : (int) CODE_FOR_altivec_lvsl_direct);
11672 machine_mode tmode = insn_data[icode2].operand[0].mode;
11673 machine_mode mode = insn_data[icode2].operand[1].mode;
11674 tree arg;
11675 rtx op, addr, pat;
11676
11677 gcc_assert (TARGET_ALTIVEC);
11678
11679 arg = CALL_EXPR_ARG (exp, 0);
11680 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
11681 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
11682 addr = memory_address (mode, op);
11683 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
11684 op = addr;
11685 else
11686 {
11687 /* For the load case need to negate the address. */
11688 op = gen_reg_rtx (GET_MODE (addr));
11689 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
11690 }
11691 op = gen_rtx_MEM (mode, op);
11692
11693 if (target == 0
11694 || GET_MODE (target) != tmode
11695 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
11696 target = gen_reg_rtx (tmode);
11697
11698 pat = GEN_FCN (icode2) (target, op);
11699 if (!pat)
11700 return 0;
11701 emit_insn (pat);
11702
11703 return target;
11704 }
11705
11706 case ALTIVEC_BUILTIN_VCFUX:
11707 case ALTIVEC_BUILTIN_VCFSX:
11708 case ALTIVEC_BUILTIN_VCTUXS:
11709 case ALTIVEC_BUILTIN_VCTSXS:
11710 /* FIXME: There's got to be a nicer way to handle this case than
11711 constructing a new CALL_EXPR. */
11712 if (call_expr_nargs (exp) == 1)
11713 {
11714 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
11715 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
11716 }
11717 break;
11718
11719 /* For the pack and unpack int128 routines, fix up the builtin so it
11720 uses the correct IBM128 type. */
11721 case MISC_BUILTIN_PACK_IF:
11722 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
11723 {
11724 icode = CODE_FOR_packtf;
11725 fcode = MISC_BUILTIN_PACK_TF;
11726 uns_fcode = (size_t)fcode;
11727 }
11728 break;
11729
11730 case MISC_BUILTIN_UNPACK_IF:
11731 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
11732 {
11733 icode = CODE_FOR_unpacktf;
11734 fcode = MISC_BUILTIN_UNPACK_TF;
11735 uns_fcode = (size_t)fcode;
11736 }
11737 break;
11738
11739 default:
11740 break;
11741 }
11742
11743 if (TARGET_ALTIVEC)
11744 {
11745 ret = altivec_expand_builtin (exp, target, &success);
11746
11747 if (success)
11748 return ret;
11749 }
11750 if (TARGET_HTM)
11751 {
11752 ret = htm_expand_builtin (exp, target, &success);
11753
11754 if (success)
11755 return ret;
11756 }
11757
11758 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
11759 /* RS6000_BTC_SPECIAL represents no-operand operators. */
11760 gcc_assert (attr == RS6000_BTC_UNARY
11761 || attr == RS6000_BTC_BINARY
11762 || attr == RS6000_BTC_TERNARY
11763 || attr == RS6000_BTC_SPECIAL);
11764
11765 /* Handle simple unary operations. */
11766 d = bdesc_1arg;
11767 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11768 if (d->code == fcode)
11769 return rs6000_expand_unop_builtin (icode, exp, target);
11770
11771 /* Handle simple binary operations. */
11772 d = bdesc_2arg;
11773 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11774 if (d->code == fcode)
11775 return rs6000_expand_binop_builtin (icode, exp, target);
11776
11777 /* Handle simple ternary operations. */
11778 d = bdesc_3arg;
11779 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
11780 if (d->code == fcode)
11781 return rs6000_expand_ternop_builtin (icode, exp, target);
11782
11783 /* Handle simple no-argument operations. */
11784 d = bdesc_0arg;
11785 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
11786 if (d->code == fcode)
11787 return rs6000_expand_zeroop_builtin (icode, target);
11788
11789 gcc_unreachable ();
11790}
11791
11792/* Create a builtin vector type with a name. Taking care not to give
11793 the canonical type a name. */
11794
11795static tree
11796rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
11797{
11798 tree result = build_vector_type (elt_type, num_elts);
11799
11800 /* Copy so we don't give the canonical type a name. */
11801 result = build_variant_type_copy (result);
11802
11803 add_builtin_type (name, result);
11804
11805 return result;
11806}
11807
11808void
11809rs6000_init_builtins (void)
11810{
11811 tree tdecl;
11812 tree ftype;
11813 machine_mode mode;
11814
11815 if (TARGET_DEBUG_BUILTIN)
11816 fprintf (stderr, "rs6000_init_builtins%s%s\n",
11817 (TARGET_ALTIVEC) ? ", altivec" : "",
11818 (TARGET_VSX) ? ", vsx" : "");
11819
11820 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
11821 : "__vector long long",
11822 intDI_type_node, 2);
11823 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
11824 V4SI_type_node = rs6000_vector_type ("__vector signed int",
11825 intSI_type_node, 4);
11826 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
11827 V8HI_type_node = rs6000_vector_type ("__vector signed short",
11828 intHI_type_node, 8);
11829 V16QI_type_node = rs6000_vector_type ("__vector signed char",
11830 intQI_type_node, 16);
11831
11832 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
11833 unsigned_intQI_type_node, 16);
11834 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
11835 unsigned_intHI_type_node, 8);
11836 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
11837 unsigned_intSI_type_node, 4);
11838 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
11839 ? "__vector unsigned long"
11840 : "__vector unsigned long long",
11841 unsigned_intDI_type_node, 2);
11842
11843 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
11844
11845 const_str_type_node
11846 = build_pointer_type (build_qualified_type (char_type_node,
11847 TYPE_QUAL_CONST));
11848
11849 /* We use V1TI mode as a special container to hold __int128_t items that
11850 must live in VSX registers. */
11851 if (intTI_type_node)
11852 {
11853 V1TI_type_node = rs6000_vector_type ("__vector __int128",
11854 intTI_type_node, 1);
11855 unsigned_V1TI_type_node
11856 = rs6000_vector_type ("__vector unsigned __int128",
11857 unsigned_intTI_type_node, 1);
11858 }
11859
11860 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11861 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11862 'vector unsigned short'. */
11863
11864 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
11865 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11866 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
11867 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
11868 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11869
11870 long_integer_type_internal_node = long_integer_type_node;
11871 long_unsigned_type_internal_node = long_unsigned_type_node;
11872 long_long_integer_type_internal_node = long_long_integer_type_node;
11873 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
11874 intQI_type_internal_node = intQI_type_node;
11875 uintQI_type_internal_node = unsigned_intQI_type_node;
11876 intHI_type_internal_node = intHI_type_node;
11877 uintHI_type_internal_node = unsigned_intHI_type_node;
11878 intSI_type_internal_node = intSI_type_node;
11879 uintSI_type_internal_node = unsigned_intSI_type_node;
11880 intDI_type_internal_node = intDI_type_node;
11881 uintDI_type_internal_node = unsigned_intDI_type_node;
11882 intTI_type_internal_node = intTI_type_node;
11883 uintTI_type_internal_node = unsigned_intTI_type_node;
11884 float_type_internal_node = float_type_node;
11885 double_type_internal_node = double_type_node;
11886 long_double_type_internal_node = long_double_type_node;
11887 dfloat64_type_internal_node = dfloat64_type_node;
11888 dfloat128_type_internal_node = dfloat128_type_node;
11889 void_type_internal_node = void_type_node;
11890
11891 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
11892 IFmode is the IBM extended 128-bit format that is a pair of doubles.
11893 TFmode will be either IEEE 128-bit floating point or the IBM double-double
11894 format that uses a pair of doubles, depending on the switches and
11895 defaults.
11896
11897 If we don't support for either 128-bit IBM double double or IEEE 128-bit
11898 floating point, we need make sure the type is non-zero or else self-test
11899 fails during bootstrap.
11900
11901 Always create __ibm128 as a separate type, even if the current long double
11902 format is IBM extended double.
11903
11904 For IEEE 128-bit floating point, always create the type __ieee128. If the
11905 user used -mfloat128, rs6000-c.c will create a define from __float128 to
11906 __ieee128. */
11907 if (TARGET_FLOAT128_TYPE)
11908 {
11909 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
11910 ibm128_float_type_node = long_double_type_node;
11911 else
11912 {
11913 ibm128_float_type_node = make_node (REAL_TYPE);
11914 TYPE_PRECISION (ibm128_float_type_node) = 128;
11915 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
11916 layout_type (ibm128_float_type_node);
11917 }
11918
11919 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
11920 "__ibm128");
11921
11922 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
11923 ieee128_float_type_node = long_double_type_node;
11924 else
11925 ieee128_float_type_node = float128_type_node;
11926
11927 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
11928 "__ieee128");
11929 }
11930
11931 else
11932 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
11933
11934 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11935 tree type node. */
11936 builtin_mode_to_type[QImode][0] = integer_type_node;
11937 builtin_mode_to_type[HImode][0] = integer_type_node;
11938 builtin_mode_to_type[SImode][0] = intSI_type_node;
11939 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
11940 builtin_mode_to_type[DImode][0] = intDI_type_node;
11941 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
11942 builtin_mode_to_type[TImode][0] = intTI_type_node;
11943 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
11944 builtin_mode_to_type[SFmode][0] = float_type_node;
11945 builtin_mode_to_type[DFmode][0] = double_type_node;
11946 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
11947 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
11948 builtin_mode_to_type[TFmode][0] = long_double_type_node;
11949 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
11950 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
11951 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
11952 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
11953 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
11954 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
11955 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
11956 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
11957 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
11958 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
11959 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
11960 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
11961 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
11962 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
11963
11964 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
11965 TYPE_NAME (bool_char_type_node) = tdecl;
11966
11967 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
11968 TYPE_NAME (bool_short_type_node) = tdecl;
11969
11970 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
11971 TYPE_NAME (bool_int_type_node) = tdecl;
11972
11973 tdecl = add_builtin_type ("__pixel", pixel_type_node);
11974 TYPE_NAME (pixel_type_node) = tdecl;
11975
11976 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
11977 bool_char_type_node, 16);
11978 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
11979 bool_short_type_node, 8);
11980 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
11981 bool_int_type_node, 4);
11982 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
11983 ? "__vector __bool long"
11984 : "__vector __bool long long",
11985 bool_long_long_type_node, 2);
11986 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
11987 pixel_type_node, 8);
11988
11989 /* Create Altivec and VSX builtins on machines with at least the
11990 general purpose extensions (970 and newer) to allow the use of
11991 the target attribute. */
11992 if (TARGET_EXTRA_BUILTINS)
11993 altivec_init_builtins ();
11994 if (TARGET_HTM)
11995 htm_init_builtins ();
11996
11997 if (TARGET_EXTRA_BUILTINS)
11998 rs6000_common_init_builtins ();
11999
12000 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
12001 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
12002 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
12003
12004 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
12005 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
12006 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
12007
12008 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
12009 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
12010 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
12011
12012 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
12013 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
12014 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
12015
12016 mode = (TARGET_64BIT) ? DImode : SImode;
12017 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
12018 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
12019 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
12020
12021 ftype = build_function_type_list (unsigned_intDI_type_node,
12022 NULL_TREE);
12023 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
12024
12025 if (TARGET_64BIT)
12026 ftype = build_function_type_list (unsigned_intDI_type_node,
12027 NULL_TREE);
12028 else
12029 ftype = build_function_type_list (unsigned_intSI_type_node,
12030 NULL_TREE);
12031 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
12032
12033 ftype = build_function_type_list (double_type_node, NULL_TREE);
12034 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
12035
12036 ftype = build_function_type_list (double_type_node, NULL_TREE);
12037 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
12038
12039 ftype = build_function_type_list (void_type_node,
12040 intSI_type_node,
12041 NULL_TREE);
12042 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
12043
12044 ftype = build_function_type_list (void_type_node,
12045 intSI_type_node,
12046 NULL_TREE);
12047 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
12048
12049 ftype = build_function_type_list (void_type_node,
12050 intDI_type_node,
12051 NULL_TREE);
12052 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
12053
12054 ftype = build_function_type_list (void_type_node,
12055 intDI_type_node,
12056 NULL_TREE);
12057 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
12058
12059 ftype = build_function_type_list (void_type_node,
12060 intSI_type_node, double_type_node,
12061 NULL_TREE);
12062 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
12063
12064 ftype = build_function_type_list (void_type_node, NULL_TREE);
12065 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
12066 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
12067 MISC_BUILTIN_SPEC_BARRIER);
12068
12069 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
12070 NULL_TREE);
12071 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
12072 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
12073
12074 /* AIX libm provides clog as __clog. */
12075 if (TARGET_XCOFF &&
12076 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
12077 set_user_assembler_name (tdecl, "__clog");
12078
12079#ifdef SUBTARGET_INIT_BUILTINS
12080 SUBTARGET_INIT_BUILTINS;
12081#endif
12082}
12083
12084/* Returns the rs6000 builtin decl for CODE. */
12085
12086tree
12087rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
12088{
12089 HOST_WIDE_INT fnmask;
12090
12091 if (code >= RS6000_BUILTIN_COUNT)
12092 return error_mark_node;
12093
12094 fnmask = rs6000_builtin_info[code].mask;
12095 if ((fnmask & rs6000_builtin_mask) != fnmask)
12096 {
12097 rs6000_invalid_builtin ((enum rs6000_builtins)code);
12098 return error_mark_node;
12099 }
12100
12101 return rs6000_builtin_decls[code];
12102}
12103
12104static void
12105altivec_init_builtins (void)
12106{
12107 const struct builtin_description *d;
12108 size_t i;
12109 tree ftype;
12110 tree decl;
1acf0246
BS		 12111
12112 tree pvoid_type_node = build_pointer_type (void_type_node);
12113
12114 tree pcvoid_type_node
12115 = build_pointer_type (build_qualified_type (void_type_node,
12116 TYPE_QUAL_CONST));
12117
12118 tree int_ftype_opaque
12119 = build_function_type_list (integer_type_node,
12120 opaque_V4SI_type_node, NULL_TREE);
12121 tree opaque_ftype_opaque
12122 = build_function_type_list (integer_type_node, NULL_TREE);
12123 tree opaque_ftype_opaque_int
12124 = build_function_type_list (opaque_V4SI_type_node,
12125 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
12126 tree opaque_ftype_opaque_opaque_int
12127 = build_function_type_list (opaque_V4SI_type_node,
12128 opaque_V4SI_type_node, opaque_V4SI_type_node,
12129 integer_type_node, NULL_TREE);
12130 tree opaque_ftype_opaque_opaque_opaque
12131 = build_function_type_list (opaque_V4SI_type_node,
12132 opaque_V4SI_type_node, opaque_V4SI_type_node,
12133 opaque_V4SI_type_node, NULL_TREE);
12134 tree opaque_ftype_opaque_opaque
12135 = build_function_type_list (opaque_V4SI_type_node,
12136 opaque_V4SI_type_node, opaque_V4SI_type_node,
12137 NULL_TREE);
12138 tree int_ftype_int_opaque_opaque
12139 = build_function_type_list (integer_type_node,
12140 integer_type_node, opaque_V4SI_type_node,
12141 opaque_V4SI_type_node, NULL_TREE);
12142 tree int_ftype_int_v4si_v4si
12143 = build_function_type_list (integer_type_node,
12144 integer_type_node, V4SI_type_node,
12145 V4SI_type_node, NULL_TREE);
12146 tree int_ftype_int_v2di_v2di
12147 = build_function_type_list (integer_type_node,
12148 integer_type_node, V2DI_type_node,
12149 V2DI_type_node, NULL_TREE);
12150 tree void_ftype_v4si
12151 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
12152 tree v8hi_ftype_void
12153 = build_function_type_list (V8HI_type_node, NULL_TREE);
12154 tree void_ftype_void
12155 = build_function_type_list (void_type_node, NULL_TREE);
12156 tree void_ftype_int
12157 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
12158
12159 tree opaque_ftype_long_pcvoid
12160 = build_function_type_list (opaque_V4SI_type_node,
12161 long_integer_type_node, pcvoid_type_node,
12162 NULL_TREE);
12163 tree v16qi_ftype_long_pcvoid
12164 = build_function_type_list (V16QI_type_node,
12165 long_integer_type_node, pcvoid_type_node,
12166 NULL_TREE);
12167 tree v8hi_ftype_long_pcvoid
12168 = build_function_type_list (V8HI_type_node,
12169 long_integer_type_node, pcvoid_type_node,
12170 NULL_TREE);
12171 tree v4si_ftype_long_pcvoid
12172 = build_function_type_list (V4SI_type_node,
12173 long_integer_type_node, pcvoid_type_node,
12174 NULL_TREE);
12175 tree v4sf_ftype_long_pcvoid
12176 = build_function_type_list (V4SF_type_node,
12177 long_integer_type_node, pcvoid_type_node,
12178 NULL_TREE);
12179 tree v2df_ftype_long_pcvoid
12180 = build_function_type_list (V2DF_type_node,
12181 long_integer_type_node, pcvoid_type_node,
12182 NULL_TREE);
12183 tree v2di_ftype_long_pcvoid
12184 = build_function_type_list (V2DI_type_node,
12185 long_integer_type_node, pcvoid_type_node,
12186 NULL_TREE);
12187 tree v1ti_ftype_long_pcvoid
12188 = build_function_type_list (V1TI_type_node,
12189 long_integer_type_node, pcvoid_type_node,
12190 NULL_TREE);
12191
12192 tree void_ftype_opaque_long_pvoid
12193 = build_function_type_list (void_type_node,
12194 opaque_V4SI_type_node, long_integer_type_node,
12195 pvoid_type_node, NULL_TREE);
12196 tree void_ftype_v4si_long_pvoid
12197 = build_function_type_list (void_type_node,
12198 V4SI_type_node, long_integer_type_node,
12199 pvoid_type_node, NULL_TREE);
12200 tree void_ftype_v16qi_long_pvoid
12201 = build_function_type_list (void_type_node,
12202 V16QI_type_node, long_integer_type_node,
12203 pvoid_type_node, NULL_TREE);
12204
12205 tree void_ftype_v16qi_pvoid_long
12206 = build_function_type_list (void_type_node,
12207 V16QI_type_node, pvoid_type_node,
12208 long_integer_type_node, NULL_TREE);
12209
12210 tree void_ftype_v8hi_long_pvoid
12211 = build_function_type_list (void_type_node,
12212 V8HI_type_node, long_integer_type_node,
12213 pvoid_type_node, NULL_TREE);
12214 tree void_ftype_v4sf_long_pvoid
12215 = build_function_type_list (void_type_node,
12216 V4SF_type_node, long_integer_type_node,
12217 pvoid_type_node, NULL_TREE);
12218 tree void_ftype_v2df_long_pvoid
12219 = build_function_type_list (void_type_node,
12220 V2DF_type_node, long_integer_type_node,
12221 pvoid_type_node, NULL_TREE);
12222 tree void_ftype_v1ti_long_pvoid
12223 = build_function_type_list (void_type_node,
12224 V1TI_type_node, long_integer_type_node,
12225 pvoid_type_node, NULL_TREE);
12226 tree void_ftype_v2di_long_pvoid
12227 = build_function_type_list (void_type_node,
12228 V2DI_type_node, long_integer_type_node,
12229 pvoid_type_node, NULL_TREE);
12230 tree int_ftype_int_v8hi_v8hi
12231 = build_function_type_list (integer_type_node,
12232 integer_type_node, V8HI_type_node,
12233 V8HI_type_node, NULL_TREE);
12234 tree int_ftype_int_v16qi_v16qi
12235 = build_function_type_list (integer_type_node,
12236 integer_type_node, V16QI_type_node,
12237 V16QI_type_node, NULL_TREE);
12238 tree int_ftype_int_v4sf_v4sf
12239 = build_function_type_list (integer_type_node,
12240 integer_type_node, V4SF_type_node,
12241 V4SF_type_node, NULL_TREE);
12242 tree int_ftype_int_v2df_v2df
12243 = build_function_type_list (integer_type_node,
12244 integer_type_node, V2DF_type_node,
12245 V2DF_type_node, NULL_TREE);
12246 tree v2di_ftype_v2di
12247 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
12248 tree v4si_ftype_v4si
12249 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
12250 tree v8hi_ftype_v8hi
12251 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
12252 tree v16qi_ftype_v16qi
12253 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
12254 tree v4sf_ftype_v4sf
12255 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
12256 tree v2df_ftype_v2df
12257 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
12258 tree void_ftype_pcvoid_int_int
12259 = build_function_type_list (void_type_node,
12260 pcvoid_type_node, integer_type_node,
12261 integer_type_node, NULL_TREE);
12262
12263 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
12264 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
12265 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
12266 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
12267 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
12268 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
12269 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
12270 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
12271 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
12272 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
12273 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
12274 ALTIVEC_BUILTIN_LVXL_V2DF);
12275 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
12276 ALTIVEC_BUILTIN_LVXL_V2DI);
12277 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
12278 ALTIVEC_BUILTIN_LVXL_V4SF);
12279 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
12280 ALTIVEC_BUILTIN_LVXL_V4SI);
12281 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
12282 ALTIVEC_BUILTIN_LVXL_V8HI);
12283 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
12284 ALTIVEC_BUILTIN_LVXL_V16QI);
12285 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
12286 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
12287 ALTIVEC_BUILTIN_LVX_V1TI);
12288 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
12289 ALTIVEC_BUILTIN_LVX_V2DF);
12290 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
12291 ALTIVEC_BUILTIN_LVX_V2DI);
12292 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
12293 ALTIVEC_BUILTIN_LVX_V4SF);
12294 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
12295 ALTIVEC_BUILTIN_LVX_V4SI);
12296 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
12297 ALTIVEC_BUILTIN_LVX_V8HI);
12298 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
12299 ALTIVEC_BUILTIN_LVX_V16QI);
12300 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
12301 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
12302 ALTIVEC_BUILTIN_STVX_V2DF);
12303 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
12304 ALTIVEC_BUILTIN_STVX_V2DI);
12305 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
12306 ALTIVEC_BUILTIN_STVX_V4SF);
12307 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
12308 ALTIVEC_BUILTIN_STVX_V4SI);
12309 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
12310 ALTIVEC_BUILTIN_STVX_V8HI);
12311 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
12312 ALTIVEC_BUILTIN_STVX_V16QI);
12313 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
12314 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
12315 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
12316 ALTIVEC_BUILTIN_STVXL_V2DF);
12317 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
12318 ALTIVEC_BUILTIN_STVXL_V2DI);
12319 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
12320 ALTIVEC_BUILTIN_STVXL_V4SF);
12321 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
12322 ALTIVEC_BUILTIN_STVXL_V4SI);
12323 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
12324 ALTIVEC_BUILTIN_STVXL_V8HI);
12325 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
12326 ALTIVEC_BUILTIN_STVXL_V16QI);
12327 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
12328 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
12329 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
12330 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
12331 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
12332 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
12333 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
12334 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
12335 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
12336 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
12337 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
12338 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
12339 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
12340 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
12341 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
12342 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
12343
12344 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
12345 VSX_BUILTIN_LXVD2X_V2DF);
12346 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
12347 VSX_BUILTIN_LXVD2X_V2DI);
12348 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
12349 VSX_BUILTIN_LXVW4X_V4SF);
12350 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
12351 VSX_BUILTIN_LXVW4X_V4SI);
12352 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
12353 VSX_BUILTIN_LXVW4X_V8HI);
12354 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
12355 VSX_BUILTIN_LXVW4X_V16QI);
12356 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
12357 VSX_BUILTIN_STXVD2X_V2DF);
12358 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
12359 VSX_BUILTIN_STXVD2X_V2DI);
12360 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
12361 VSX_BUILTIN_STXVW4X_V4SF);
12362 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
12363 VSX_BUILTIN_STXVW4X_V4SI);
12364 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
12365 VSX_BUILTIN_STXVW4X_V8HI);
12366 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
12367 VSX_BUILTIN_STXVW4X_V16QI);
12368
12369 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
12370 VSX_BUILTIN_LD_ELEMREV_V2DF);
12371 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
12372 VSX_BUILTIN_LD_ELEMREV_V2DI);
12373 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
12374 VSX_BUILTIN_LD_ELEMREV_V4SF);
12375 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
12376 VSX_BUILTIN_LD_ELEMREV_V4SI);
12377 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
12378 VSX_BUILTIN_LD_ELEMREV_V8HI);
12379 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
12380 VSX_BUILTIN_LD_ELEMREV_V16QI);
12381 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
12382 VSX_BUILTIN_ST_ELEMREV_V2DF);
12383 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
12384 VSX_BUILTIN_ST_ELEMREV_V1TI);
12385 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
12386 VSX_BUILTIN_ST_ELEMREV_V2DI);
12387 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
12388 VSX_BUILTIN_ST_ELEMREV_V4SF);
12389 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
12390 VSX_BUILTIN_ST_ELEMREV_V4SI);
12391 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
12392 VSX_BUILTIN_ST_ELEMREV_V8HI);
12393 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
12394 VSX_BUILTIN_ST_ELEMREV_V16QI);
12395
12396 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
12397 VSX_BUILTIN_VEC_LD);
12398 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
12399 VSX_BUILTIN_VEC_ST);
12400 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
12401 VSX_BUILTIN_VEC_XL);
12402 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
12403 VSX_BUILTIN_VEC_XL_BE);
12404 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
12405 VSX_BUILTIN_VEC_XST);
12406 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
12407 VSX_BUILTIN_VEC_XST_BE);
12408
12409 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
12410 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
12411 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
12412
12413 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
12414 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
12415 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
12416 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
12417 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
12418 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
12419 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
12420 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
12421 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
12422 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
12423 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
12424 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
12425
12426 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
12427 ALTIVEC_BUILTIN_VEC_ADDE);
12428 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
12429 ALTIVEC_BUILTIN_VEC_ADDEC);
12430 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
12431 ALTIVEC_BUILTIN_VEC_CMPNE);
12432 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
12433 ALTIVEC_BUILTIN_VEC_MUL);
12434 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
12435 ALTIVEC_BUILTIN_VEC_SUBE);
12436 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
12437 ALTIVEC_BUILTIN_VEC_SUBEC);
12438
12439 /* Cell builtins. */
12440 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
12441 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
12442 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
12443 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
12444
12445 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
12446 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
12447 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
12448 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
12449
12450 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
12451 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
12452 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
12453 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
12454
12455 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
12456 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
12457 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
12458 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
12459
12460 if (TARGET_P9_VECTOR)
12461 {
12462 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
12463 P9V_BUILTIN_STXVL);
12464 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
12465 P9V_BUILTIN_XST_LEN_R);
12466 }
12467
12468 /* Add the DST variants. */
12469 d = bdesc_dst;
12470 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
12471 {
1acf0246
BS		 12472 /* It is expected that these dst built-in functions may have
12473 d->icode equal to CODE_FOR_nothing. */
1acf0246
BS		 12474 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
12475 }
12476
12477 /* Initialize the predicates. */
12478 d = bdesc_altivec_preds;
12479 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
12480 {
12481 machine_mode mode1;
12482 tree type;
1acf0246
BS		 12483
12484 if (rs6000_overloaded_builtin_p (d->code))
12485 mode1 = VOIDmode;
12486 else
12487 {
12488 /* Cannot define builtin if the instruction is disabled. */
12489 gcc_assert (d->icode != CODE_FOR_nothing);
12490 mode1 = insn_data[d->icode].operand[1].mode;
12491 }
12492
12493 switch (mode1)
12494 {
12495 case E_VOIDmode:
12496 type = int_ftype_int_opaque_opaque;
12497 break;
12498 case E_V2DImode:
12499 type = int_ftype_int_v2di_v2di;
12500 break;
12501 case E_V4SImode:
12502 type = int_ftype_int_v4si_v4si;
12503 break;
12504 case E_V8HImode:
12505 type = int_ftype_int_v8hi_v8hi;
12506 break;
12507 case E_V16QImode:
12508 type = int_ftype_int_v16qi_v16qi;
12509 break;
12510 case E_V4SFmode:
12511 type = int_ftype_int_v4sf_v4sf;
12512 break;
12513 case E_V2DFmode:
12514 type = int_ftype_int_v2df_v2df;
12515 break;
12516 default:
12517 gcc_unreachable ();
12518 }
12519
12520 def_builtin (d->name, type, d->code);
12521 }
12522
12523 /* Initialize the abs* operators. */
12524 d = bdesc_abs;
12525 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
12526 {
12527 machine_mode mode0;
12528 tree type;
1acf0246
BS		 12529
12530 /* Cannot define builtin if the instruction is disabled. */
12531 gcc_assert (d->icode != CODE_FOR_nothing);
12532 mode0 = insn_data[d->icode].operand[0].mode;
12533
12534 switch (mode0)
12535 {
12536 case E_V2DImode:
12537 type = v2di_ftype_v2di;
12538 break;
12539 case E_V4SImode:
12540 type = v4si_ftype_v4si;
12541 break;
12542 case E_V8HImode:
12543 type = v8hi_ftype_v8hi;
12544 break;
12545 case E_V16QImode:
12546 type = v16qi_ftype_v16qi;
12547 break;
12548 case E_V4SFmode:
12549 type = v4sf_ftype_v4sf;
12550 break;
12551 case E_V2DFmode:
12552 type = v2df_ftype_v2df;
12553 break;
12554 default:
12555 gcc_unreachable ();
12556 }
12557
12558 def_builtin (d->name, type, d->code);
12559 }
12560
12561 /* Initialize target builtin that implements
12562 targetm.vectorize.builtin_mask_for_load. */
12563
12564 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
12565 v16qi_ftype_long_pcvoid,
12566 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
12567 BUILT_IN_MD, NULL, NULL_TREE);
12568 TREE_READONLY (decl) = 1;
12569 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12570 altivec_builtin_mask_for_load = decl;
12571
12572 /* Access to the vec_init patterns. */
12573 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
12574 integer_type_node, integer_type_node,
12575 integer_type_node, NULL_TREE);
12576 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
12577
12578 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
12579 short_integer_type_node,
12580 short_integer_type_node,
12581 short_integer_type_node,
12582 short_integer_type_node,
12583 short_integer_type_node,
12584 short_integer_type_node,
12585 short_integer_type_node, NULL_TREE);
12586 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
12587
12588 ftype = build_function_type_list (V16QI_type_node, char_type_node,
12589 char_type_node, char_type_node,
12590 char_type_node, char_type_node,
12591 char_type_node, char_type_node,
12592 char_type_node, char_type_node,
12593 char_type_node, char_type_node,
12594 char_type_node, char_type_node,
12595 char_type_node, char_type_node,
12596 char_type_node, NULL_TREE);
12597 def_builtin ("__builtin_vec_init_v16qi", ftype,
12598 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
12599
12600 ftype = build_function_type_list (V4SF_type_node, float_type_node,
12601 float_type_node, float_type_node,
12602 float_type_node, NULL_TREE);
12603 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
12604
12605 /* VSX builtins. */
12606 ftype = build_function_type_list (V2DF_type_node, double_type_node,
12607 double_type_node, NULL_TREE);
12608 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
12609
12610 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
12611 intDI_type_node, NULL_TREE);
12612 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
12613
12614 /* Access to the vec_set patterns. */
12615 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
12616 intSI_type_node,
12617 integer_type_node, NULL_TREE);
12618 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
12619
12620 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
12621 intHI_type_node,
12622 integer_type_node, NULL_TREE);
12623 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
12624
12625 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
12626 intQI_type_node,
12627 integer_type_node, NULL_TREE);
12628 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
12629
12630 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
12631 float_type_node,
12632 integer_type_node, NULL_TREE);
12633 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
12634
12635 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
12636 double_type_node,
12637 integer_type_node, NULL_TREE);
12638 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
12639
12640 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
12641 intDI_type_node,
12642 integer_type_node, NULL_TREE);
12643 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
12644
12645 /* Access to the vec_extract patterns. */
12646 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
12647 integer_type_node, NULL_TREE);
12648 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
12649
12650 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
12651 integer_type_node, NULL_TREE);
12652 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
12653
12654 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
12655 integer_type_node, NULL_TREE);
12656 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
12657
12658 ftype = build_function_type_list (float_type_node, V4SF_type_node,
12659 integer_type_node, NULL_TREE);
12660 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
12661
12662 ftype = build_function_type_list (double_type_node, V2DF_type_node,
12663 integer_type_node, NULL_TREE);
12664 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
12665
12666 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
12667 integer_type_node, NULL_TREE);
12668 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
12669
12670
12671 if (V1TI_type_node)
12672 {
12673 tree v1ti_ftype_long_pcvoid
12674 = build_function_type_list (V1TI_type_node,
12675 long_integer_type_node, pcvoid_type_node,
12676 NULL_TREE);
12677 tree void_ftype_v1ti_long_pvoid
12678 = build_function_type_list (void_type_node,
12679 V1TI_type_node, long_integer_type_node,
12680 pvoid_type_node, NULL_TREE);
12681 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
12682 VSX_BUILTIN_LD_ELEMREV_V1TI);
12683 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
12684 VSX_BUILTIN_LXVD2X_V1TI);
12685 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
12686 VSX_BUILTIN_STXVD2X_V1TI);
12687 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
12688 NULL_TREE, NULL_TREE);
12689 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
12690 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
12691 intTI_type_node,
12692 integer_type_node, NULL_TREE);
12693 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
12694 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
12695 integer_type_node, NULL_TREE);
12696 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
12697 }
12698
12699}
12700
12701static void
12702htm_init_builtins (void)
12703{
12704 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
12705 const struct builtin_description *d;
12706 size_t i;
12707
12708 d = bdesc_htm;
12709 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
12710 {
12711 tree op[MAX_HTM_OPERANDS], type;
12712 HOST_WIDE_INT mask = d->mask;
12713 unsigned attr = rs6000_builtin_info[d->code].attr;
12714 bool void_func = (attr & RS6000_BTC_VOID);
12715 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
12716 int nopnds = 0;
12717 tree gpr_type_node;
12718 tree rettype;
12719 tree argtype;
12720
12721 /* It is expected that these htm built-in functions may have
12722 d->icode equal to CODE_FOR_nothing. */
12723
12724 if (TARGET_32BIT && TARGET_POWERPC64)
12725 gpr_type_node = long_long_unsigned_type_node;
12726 else
12727 gpr_type_node = long_unsigned_type_node;
12728
12729 if (attr & RS6000_BTC_SPR)
12730 {
12731 rettype = gpr_type_node;
12732 argtype = gpr_type_node;
12733 }
12734 else if (d->code == HTM_BUILTIN_TABORTDC
12735 || d->code == HTM_BUILTIN_TABORTDCI)
12736 {
12737 rettype = unsigned_type_node;
12738 argtype = gpr_type_node;
12739 }
12740 else
12741 {
12742 rettype = unsigned_type_node;
12743 argtype = unsigned_type_node;
12744 }
12745
12746 if ((mask & builtin_mask) != mask)
12747 {
12748 if (TARGET_DEBUG_BUILTIN)
12749 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
12750 continue;
12751 }
12752
12753 if (d->name == 0)
12754 {
12755 if (TARGET_DEBUG_BUILTIN)
12756 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
12757 (long unsigned) i);
12758 continue;
12759 }
12760
12761 op[nopnds++] = (void_func) ? void_type_node : rettype;
12762
12763 if (attr_args == RS6000_BTC_UNARY)
12764 op[nopnds++] = argtype;
12765 else if (attr_args == RS6000_BTC_BINARY)
12766 {
12767 op[nopnds++] = argtype;
12768 op[nopnds++] = argtype;
12769 }
12770 else if (attr_args == RS6000_BTC_TERNARY)
12771 {
12772 op[nopnds++] = argtype;
12773 op[nopnds++] = argtype;
12774 op[nopnds++] = argtype;
12775 }
12776
12777 switch (nopnds)
12778 {
12779 case 1:
12780 type = build_function_type_list (op[0], NULL_TREE);
12781 break;
12782 case 2:
12783 type = build_function_type_list (op[0], op[1], NULL_TREE);
12784 break;
12785 case 3:
12786 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
12787 break;
12788 case 4:
12789 type = build_function_type_list (op[0], op[1], op[2], op[3],
12790 NULL_TREE);
12791 break;
12792 default:
12793 gcc_unreachable ();
12794 }
12795
12796 def_builtin (d->name, type, d->code);
12797 }
12798}
12799
12800/* Map types for builtin functions with an explicit return type and up to 3
12801 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12802 of the argument. */
12803static tree
12804builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
12805 machine_mode mode_arg1, machine_mode mode_arg2,
12806 enum rs6000_builtins builtin, const char *name)
12807{
12808 struct builtin_hash_struct h;
12809 struct builtin_hash_struct *h2;
12810 int num_args = 3;
12811 int i;
12812 tree ret_type = NULL_TREE;
12813 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
12814
12815 /* Create builtin_hash_table. */
12816 if (builtin_hash_table == NULL)
12817 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
12818
12819 h.type = NULL_TREE;
12820 h.mode[0] = mode_ret;
12821 h.mode[1] = mode_arg0;
12822 h.mode[2] = mode_arg1;
12823 h.mode[3] = mode_arg2;
12824 h.uns_p[0] = 0;
12825 h.uns_p[1] = 0;
12826 h.uns_p[2] = 0;
12827 h.uns_p[3] = 0;
12828
12829 /* If the builtin is a type that produces unsigned results or takes unsigned
12830 arguments, and it is returned as a decl for the vectorizer (such as
12831 widening multiplies, permute), make sure the arguments and return value
12832 are type correct. */
12833 switch (builtin)
12834 {
12835 /* unsigned 1 argument functions. */
12836 case CRYPTO_BUILTIN_VSBOX:
12837 case CRYPTO_BUILTIN_VSBOX_BE:
12838 case P8V_BUILTIN_VGBBD:
12839 case MISC_BUILTIN_CDTBCD:
12840 case MISC_BUILTIN_CBCDTD:
12841 h.uns_p[0] = 1;
12842 h.uns_p[1] = 1;
12843 break;
12844
12845 /* unsigned 2 argument functions. */
12846 case ALTIVEC_BUILTIN_VMULEUB:
12847 case ALTIVEC_BUILTIN_VMULEUH:
12848 case P8V_BUILTIN_VMULEUW:
12849 case ALTIVEC_BUILTIN_VMULOUB:
12850 case ALTIVEC_BUILTIN_VMULOUH:
12851 case P8V_BUILTIN_VMULOUW:
12852 case CRYPTO_BUILTIN_VCIPHER:
12853 case CRYPTO_BUILTIN_VCIPHER_BE:
12854 case CRYPTO_BUILTIN_VCIPHERLAST:
12855 case CRYPTO_BUILTIN_VCIPHERLAST_BE:
12856 case CRYPTO_BUILTIN_VNCIPHER:
12857 case CRYPTO_BUILTIN_VNCIPHER_BE:
12858 case CRYPTO_BUILTIN_VNCIPHERLAST:
12859 case CRYPTO_BUILTIN_VNCIPHERLAST_BE:
12860 case CRYPTO_BUILTIN_VPMSUMB:
12861 case CRYPTO_BUILTIN_VPMSUMH:
12862 case CRYPTO_BUILTIN_VPMSUMW:
12863 case CRYPTO_BUILTIN_VPMSUMD:
12864 case CRYPTO_BUILTIN_VPMSUM:
12865 case MISC_BUILTIN_ADDG6S:
12866 case MISC_BUILTIN_DIVWEU:
12867 case MISC_BUILTIN_DIVDEU:
12868 case VSX_BUILTIN_UDIV_V2DI:
12869 case ALTIVEC_BUILTIN_VMAXUB:
12870 case ALTIVEC_BUILTIN_VMINUB:
12871 case ALTIVEC_BUILTIN_VMAXUH:
12872 case ALTIVEC_BUILTIN_VMINUH:
12873 case ALTIVEC_BUILTIN_VMAXUW:
12874 case ALTIVEC_BUILTIN_VMINUW:
12875 case P8V_BUILTIN_VMAXUD:
12876 case P8V_BUILTIN_VMINUD:
4559be23
PB		 12877 case ALTIVEC_BUILTIN_VAND_V16QI_UNS:
12878 case ALTIVEC_BUILTIN_VAND_V8HI_UNS:
12879 case ALTIVEC_BUILTIN_VAND_V4SI_UNS:
12880 case ALTIVEC_BUILTIN_VAND_V2DI_UNS:
12881 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS:
12882 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS:
12883 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS:
12884 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS:
12885 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS:
12886 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS:
12887 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS:
12888 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS:
12889 case ALTIVEC_BUILTIN_VOR_V16QI_UNS:
12890 case ALTIVEC_BUILTIN_VOR_V8HI_UNS:
12891 case ALTIVEC_BUILTIN_VOR_V4SI_UNS:
12892 case ALTIVEC_BUILTIN_VOR_V2DI_UNS:
12893 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS:
12894 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS:
12895 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS:
12896 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS:
12897 case P8V_BUILTIN_EQV_V16QI_UNS:
12898 case P8V_BUILTIN_EQV_V8HI_UNS:
12899 case P8V_BUILTIN_EQV_V4SI_UNS:
12900 case P8V_BUILTIN_EQV_V2DI_UNS:
12901 case P8V_BUILTIN_EQV_V1TI_UNS:
12902 case P8V_BUILTIN_NAND_V16QI_UNS:
12903 case P8V_BUILTIN_NAND_V8HI_UNS:
12904 case P8V_BUILTIN_NAND_V4SI_UNS:
12905 case P8V_BUILTIN_NAND_V2DI_UNS:
12906 case P8V_BUILTIN_NAND_V1TI_UNS:
12907 case P8V_BUILTIN_ORC_V16QI_UNS:
12908 case P8V_BUILTIN_ORC_V8HI_UNS:
12909 case P8V_BUILTIN_ORC_V4SI_UNS:
12910 case P8V_BUILTIN_ORC_V2DI_UNS:
12911 case P8V_BUILTIN_ORC_V1TI_UNS:
1acf0246
BS		 12912 h.uns_p[0] = 1;
12913 h.uns_p[1] = 1;
12914 h.uns_p[2] = 1;
12915 break;
12916
12917 /* unsigned 3 argument functions. */
12918 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
12919 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
12920 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
12921 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
12922 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
12923 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
12924 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
12925 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
12926 case VSX_BUILTIN_VPERM_16QI_UNS:
12927 case VSX_BUILTIN_VPERM_8HI_UNS:
12928 case VSX_BUILTIN_VPERM_4SI_UNS:
12929 case VSX_BUILTIN_VPERM_2DI_UNS:
12930 case VSX_BUILTIN_XXSEL_16QI_UNS:
12931 case VSX_BUILTIN_XXSEL_8HI_UNS:
12932 case VSX_BUILTIN_XXSEL_4SI_UNS:
12933 case VSX_BUILTIN_XXSEL_2DI_UNS:
12934 case CRYPTO_BUILTIN_VPERMXOR:
12935 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
12936 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
12937 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
12938 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
12939 case CRYPTO_BUILTIN_VSHASIGMAW:
12940 case CRYPTO_BUILTIN_VSHASIGMAD:
12941 case CRYPTO_BUILTIN_VSHASIGMA:
12942 h.uns_p[0] = 1;
12943 h.uns_p[1] = 1;
12944 h.uns_p[2] = 1;
12945 h.uns_p[3] = 1;
12946 break;
12947
12948 /* signed permute functions with unsigned char mask. */
12949 case ALTIVEC_BUILTIN_VPERM_16QI:
12950 case ALTIVEC_BUILTIN_VPERM_8HI:
12951 case ALTIVEC_BUILTIN_VPERM_4SI:
12952 case ALTIVEC_BUILTIN_VPERM_4SF:
12953 case ALTIVEC_BUILTIN_VPERM_2DI:
12954 case ALTIVEC_BUILTIN_VPERM_2DF:
12955 case VSX_BUILTIN_VPERM_16QI:
12956 case VSX_BUILTIN_VPERM_8HI:
12957 case VSX_BUILTIN_VPERM_4SI:
12958 case VSX_BUILTIN_VPERM_4SF:
12959 case VSX_BUILTIN_VPERM_2DI:
12960 case VSX_BUILTIN_VPERM_2DF:
12961 h.uns_p[3] = 1;
12962 break;
12963
12964 /* unsigned args, signed return. */
12965 case VSX_BUILTIN_XVCVUXDSP:
12966 case VSX_BUILTIN_XVCVUXDDP_UNS:
12967 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
12968 h.uns_p[1] = 1;
12969 break;
12970
12971 /* signed args, unsigned return. */
12972 case VSX_BUILTIN_XVCVDPUXDS_UNS:
12973 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
12974 case MISC_BUILTIN_UNPACK_TD:
12975 case MISC_BUILTIN_UNPACK_V1TI:
12976 h.uns_p[0] = 1;
12977 break;
12978
12979 /* unsigned arguments, bool return (compares). */
12980 case ALTIVEC_BUILTIN_VCMPEQUB:
12981 case ALTIVEC_BUILTIN_VCMPEQUH:
12982 case ALTIVEC_BUILTIN_VCMPEQUW:
12983 case P8V_BUILTIN_VCMPEQUD:
12984 case VSX_BUILTIN_CMPGE_U16QI:
12985 case VSX_BUILTIN_CMPGE_U8HI:
12986 case VSX_BUILTIN_CMPGE_U4SI:
12987 case VSX_BUILTIN_CMPGE_U2DI:
12988 case ALTIVEC_BUILTIN_VCMPGTUB:
12989 case ALTIVEC_BUILTIN_VCMPGTUH:
12990 case ALTIVEC_BUILTIN_VCMPGTUW:
12991 case P8V_BUILTIN_VCMPGTUD:
12992 h.uns_p[1] = 1;
12993 h.uns_p[2] = 1;
12994 break;
12995
12996 /* unsigned arguments for 128-bit pack instructions. */
12997 case MISC_BUILTIN_PACK_TD:
12998 case MISC_BUILTIN_PACK_V1TI:
12999 h.uns_p[1] = 1;
13000 h.uns_p[2] = 1;
13001 break;
13002
13003 /* unsigned second arguments (vector shift right). */
13004 case ALTIVEC_BUILTIN_VSRB:
13005 case ALTIVEC_BUILTIN_VSRH:
13006 case ALTIVEC_BUILTIN_VSRW:
13007 case P8V_BUILTIN_VSRD:
13008 h.uns_p[2] = 1;
13009 break;
13010
13011 default:
13012 break;
13013 }
13014
13015 /* Figure out how many args are present. */
13016 while (num_args > 0 && h.mode[num_args] == VOIDmode)
13017 num_args--;
13018
13019 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
13020 if (!ret_type && h.uns_p[0])
13021 ret_type = builtin_mode_to_type[h.mode[0]][0];
13022
a92cc0da
PB		 13023 /* If the required decimal float type has been disabled,
13024 then return NULL_TREE. */
13025 if (!ret_type && DECIMAL_FLOAT_MODE_P (h.mode[0]))
13026 return NULL_TREE;
13027
1acf0246
BS		 13028 if (!ret_type)
13029 fatal_error (input_location,
13030 "internal error: builtin function %qs had an unexpected "
13031 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
13032
13033 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
13034 arg_type[i] = NULL_TREE;
13035
13036 for (i = 0; i < num_args; i++)
13037 {
13038 int m = (int) h.mode[i+1];
13039 int uns_p = h.uns_p[i+1];
13040
13041 arg_type[i] = builtin_mode_to_type[m][uns_p];
13042 if (!arg_type[i] && uns_p)
13043 arg_type[i] = builtin_mode_to_type[m][0];
13044
a92cc0da
PB		 13045 /* If the required decimal float type has been disabled,
13046 then return NULL_TREE. */
13047 if (!arg_type[i] && DECIMAL_FLOAT_MODE_P (m))
13048 return NULL_TREE;
13049
1acf0246
BS		 13050 if (!arg_type[i])
13051 fatal_error (input_location,
13052 "internal error: builtin function %qs, argument %d "
13053 "had unexpected argument type %qs", name, i,
13054 GET_MODE_NAME (m));
13055 }
13056
13057 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
13058 if (*found == NULL)
13059 {
13060 h2 = ggc_alloc<builtin_hash_struct> ();
13061 *h2 = h;
13062 *found = h2;
13063
13064 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
13065 arg_type[2], NULL_TREE);
13066 }
13067
13068 return (*found)->type;
13069}
13070
13071static void
13072rs6000_common_init_builtins (void)
13073{
13074 const struct builtin_description *d;
13075 size_t i;
13076
13077 tree opaque_ftype_opaque = NULL_TREE;
13078 tree opaque_ftype_opaque_opaque = NULL_TREE;
13079 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
13080 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
13081
13082 /* Create Altivec and VSX builtins on machines with at least the
13083 general purpose extensions (970 and newer) to allow the use of
13084 the target attribute. */
13085
13086 if (TARGET_EXTRA_BUILTINS)
13087 builtin_mask |= RS6000_BTM_COMMON;
13088
13089 /* Add the ternary operators. */
13090 d = bdesc_3arg;
13091 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
13092 {
13093 tree type;
13094 HOST_WIDE_INT mask = d->mask;
13095
13096 if ((mask & builtin_mask) != mask)
13097 {
13098 if (TARGET_DEBUG_BUILTIN)
13099 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
13100 continue;
13101 }
13102
13103 if (rs6000_overloaded_builtin_p (d->code))
13104 {
13105 if (! (type = opaque_ftype_opaque_opaque_opaque))
13106 type = opaque_ftype_opaque_opaque_opaque
13107 = build_function_type_list (opaque_V4SI_type_node,
13108 opaque_V4SI_type_node,
13109 opaque_V4SI_type_node,
13110 opaque_V4SI_type_node,
13111 NULL_TREE);
13112 }
13113 else
13114 {
13115 enum insn_code icode = d->icode;
13116 if (d->name == 0)
13117 {
13118 if (TARGET_DEBUG_BUILTIN)
13119 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
13120 (long unsigned)i);
13121
13122 continue;
13123 }
13124
13125 if (icode == CODE_FOR_nothing)
13126 {
13127 if (TARGET_DEBUG_BUILTIN)
13128 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
13129 d->name);
13130
13131 continue;
13132 }
13133
13134 type = builtin_function_type (insn_data[icode].operand[0].mode,
13135 insn_data[icode].operand[1].mode,
13136 insn_data[icode].operand[2].mode,
13137 insn_data[icode].operand[3].mode,
13138 d->code, d->name);
13139 }
13140
13141 def_builtin (d->name, type, d->code);
13142 }
13143
13144 /* Add the binary operators. */
13145 d = bdesc_2arg;
13146 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13147 {
13148 machine_mode mode0, mode1, mode2;
13149 tree type;
13150 HOST_WIDE_INT mask = d->mask;
13151
13152 if ((mask & builtin_mask) != mask)
13153 {
13154 if (TARGET_DEBUG_BUILTIN)
13155 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
13156 continue;
13157 }
13158
13159 if (rs6000_overloaded_builtin_p (d->code))
13160 {
25ffd3d3
PB		 13161 const struct altivec_builtin_types *desc;
13162
13163 /* Verify the builtin we are overloading has already been defined. */
13164 type = NULL_TREE;
13165 for (desc = altivec_overloaded_builtins;
13166 desc->code != RS6000_BUILTIN_NONE; desc++)
13167 if (desc->code == d->code
13168 && rs6000_builtin_decls[(int)desc->overloaded_code])
13169 {
13170 if (! (type = opaque_ftype_opaque_opaque))
13171 type = opaque_ftype_opaque_opaque
13172 = build_function_type_list (opaque_V4SI_type_node,
13173 opaque_V4SI_type_node,
13174 opaque_V4SI_type_node,
13175 NULL_TREE);
13176 break;
13177 }
1acf0246
BS		 13178 }
13179 else
13180 {
13181 enum insn_code icode = d->icode;
13182 if (d->name == 0)
13183 {
13184 if (TARGET_DEBUG_BUILTIN)
13185 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
13186 (long unsigned)i);
13187
13188 continue;
13189 }
13190
13191 if (icode == CODE_FOR_nothing)
13192 {
13193 if (TARGET_DEBUG_BUILTIN)
13194 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
13195 d->name);
13196
13197 continue;
13198 }
13199
13200 mode0 = insn_data[icode].operand[0].mode;
13201 mode1 = insn_data[icode].operand[1].mode;
13202 mode2 = insn_data[icode].operand[2].mode;
13203
13204 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
13205 d->code, d->name);
13206 }
13207
13208 def_builtin (d->name, type, d->code);
13209 }
13210
13211 /* Add the simple unary operators. */
13212 d = bdesc_1arg;
13213 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
13214 {
13215 machine_mode mode0, mode1;
13216 tree type;
13217 HOST_WIDE_INT mask = d->mask;
13218
13219 if ((mask & builtin_mask) != mask)
13220 {
13221 if (TARGET_DEBUG_BUILTIN)
13222 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
13223 continue;
13224 }
13225
13226 if (rs6000_overloaded_builtin_p (d->code))
13227 {
13228 if (! (type = opaque_ftype_opaque))
13229 type = opaque_ftype_opaque
13230 = build_function_type_list (opaque_V4SI_type_node,
13231 opaque_V4SI_type_node,
13232 NULL_TREE);
13233 }
13234 else
13235 {
13236 enum insn_code icode = d->icode;
13237 if (d->name == 0)
13238 {
13239 if (TARGET_DEBUG_BUILTIN)
13240 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
13241 (long unsigned)i);
13242
13243 continue;
13244 }
13245
13246 if (icode == CODE_FOR_nothing)
13247 {
13248 if (TARGET_DEBUG_BUILTIN)
13249 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
13250 d->name);
13251
13252 continue;
13253 }
13254
13255 mode0 = insn_data[icode].operand[0].mode;
13256 mode1 = insn_data[icode].operand[1].mode;
13257
13258 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
13259 d->code, d->name);
13260 }
13261
13262 def_builtin (d->name, type, d->code);
13263 }
13264
13265 /* Add the simple no-argument operators. */
13266 d = bdesc_0arg;
13267 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
13268 {
13269 machine_mode mode0;
13270 tree type;
13271 HOST_WIDE_INT mask = d->mask;
13272
13273 if ((mask & builtin_mask) != mask)
13274 {
13275 if (TARGET_DEBUG_BUILTIN)
13276 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
13277 continue;
13278 }
13279 if (rs6000_overloaded_builtin_p (d->code))
13280 {
13281 if (!opaque_ftype_opaque)
13282 opaque_ftype_opaque
13283 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
13284 type = opaque_ftype_opaque;
13285 }
13286 else
13287 {
13288 enum insn_code icode = d->icode;
13289 if (d->name == 0)
13290 {
13291 if (TARGET_DEBUG_BUILTIN)
13292 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
13293 (long unsigned) i);
13294 continue;
13295 }
13296 if (icode == CODE_FOR_nothing)
13297 {
13298 if (TARGET_DEBUG_BUILTIN)
13299 fprintf (stderr,
13300 "rs6000_builtin, skip no-argument %s (no code)\n",
13301 d->name);
13302 continue;
13303 }
13304 mode0 = insn_data[icode].operand[0].mode;
13305 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
13306 d->code, d->name);
13307 }
13308 def_builtin (d->name, type, d->code);
13309 }
13310}
13311
13312/* Return the internal arg pointer used for function incoming
13313 arguments. When -fsplit-stack, the arg pointer is r12 so we need
13314 to copy it to a pseudo in order for it to be preserved over calls
13315 and suchlike. We'd really like to use a pseudo here for the
13316 internal arg pointer but data-flow analysis is not prepared to
13317 accept pseudos as live at the beginning of a function. */
13318
13319rtx
13320rs6000_internal_arg_pointer (void)
13321{
13322 if (flag_split_stack
13323 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
13324 == NULL))
13325
13326 {
13327 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
13328 {
13329 rtx pat;
13330
13331 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
13332 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
13333
13334 /* Put the pseudo initialization right after the note at the
13335 beginning of the function. */
13336 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
13337 gen_rtx_REG (Pmode, 12));
13338 push_topmost_sequence ();
13339 emit_insn_after (pat, get_insns ());
13340 pop_topmost_sequence ();
13341 }
13342 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
13343 FIRST_PARM_OFFSET (current_function_decl));
13344 return copy_to_reg (ret);
13345 }
13346 return virtual_incoming_args_rtx;
13347}
13348
13349\f
13350/* A C compound statement that outputs the assembler code for a thunk
13351 function, used to implement C++ virtual function calls with
13352 multiple inheritance. The thunk acts as a wrapper around a virtual
13353 function, adjusting the implicit object parameter before handing
13354 control off to the real function.
13355
13356 First, emit code to add the integer DELTA to the location that
13357 contains the incoming first argument. Assume that this argument
13358 contains a pointer, and is the one used to pass the `this' pointer
13359 in C++. This is the incoming argument *before* the function
13360 prologue, e.g. `%o0' on a sparc. The addition must preserve the
13361 values of all other incoming arguments.
13362
13363 After the addition, emit code to jump to FUNCTION, which is a
13364 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
13365 not touch the return address. Hence returning from FUNCTION will
13366 return to whoever called the current `thunk'.
13367
13368 The effect must be as if FUNCTION had been called directly with the
13369 adjusted first argument. This macro is responsible for emitting
13370 all of the code for a thunk function; output_function_prologue()
13371 and output_function_epilogue() are not invoked.
13372
13373 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
13374 been extracted from it.) It might possibly be useful on some
13375 targets, but probably not.
13376
13377 If you do not define this macro, the target-independent code in the
13378 C++ frontend will generate a less efficient heavyweight thunk that
13379 calls FUNCTION instead of jumping to it. The generic approach does
13380 not support varargs. */
13381
13382void
13383rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13384 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
13385 tree function)
13386{
13387 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
13388 rtx this_rtx, funexp;
13389 rtx_insn *insn;
13390
13391 reload_completed = 1;
13392 epilogue_completed = 1;
13393
13394 /* Mark the end of the (empty) prologue. */
13395 emit_note (NOTE_INSN_PROLOGUE_END);
13396
13397 /* Find the "this" pointer. If the function returns a structure,
13398 the structure return pointer is in r3. */
13399 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
13400 this_rtx = gen_rtx_REG (Pmode, 4);
13401 else
13402 this_rtx = gen_rtx_REG (Pmode, 3);
13403
13404 /* Apply the constant offset, if required. */
13405 if (delta)
13406 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
13407
13408 /* Apply the offset from the vtable, if required. */
13409 if (vcall_offset)
13410 {
13411 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
13412 rtx tmp = gen_rtx_REG (Pmode, 12);
13413
13414 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
13415 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
13416 {
13417 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
13418 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
13419 }
13420 else
13421 {
13422 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
13423
13424 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
13425 }
13426 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
13427 }
13428
13429 /* Generate a tail call to the target function. */
13430 if (!TREE_USED (function))
13431 {
13432 assemble_external (function);
13433 TREE_USED (function) = 1;
13434 }
13435 funexp = XEXP (DECL_RTL (function), 0);
13436 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
13437
aef57966 13438 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, const0_rtx));
1acf0246
BS		 13439 SIBLING_CALL_P (insn) = 1;
13440 emit_barrier ();
13441
13442 /* Run just enough of rest_of_compilation to get the insns emitted.
13443 There's not really enough bulk here to make other passes such as
13444 instruction scheduling worth while. */
13445 insn = get_insns ();
13446 shorten_branches (insn);
13447 assemble_start_function (thunk_fndecl, fnname);
13448 final_start_function (insn, file, 1);
13449 final (insn, file, 1);
13450 final_end_function ();
13451 assemble_end_function (thunk_fndecl, fnname);
13452
13453 reload_completed = 0;
13454 epilogue_completed = 0;
13455}
13456
13457#include "gt-rs6000-call.h"
Mirror of https://gcc.gnu.org/git/gcc.git