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1acf0246
BS		 1/* Subroutines used to generate function calls and handle built-in
2 instructions on IBM RS/6000.
99dee823 3 Copyright (C) 1991-2021 Free Software Foundation, Inc.
1acf0246
BS		 4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21#define IN_TARGET_CODE 1
22
23#include "config.h"
24#include "system.h"
25#include "coretypes.h"
26#include "backend.h"
27#include "rtl.h"
28#include "tree.h"
29#include "memmodel.h"
30#include "gimple.h"
31#include "cfghooks.h"
32#include "cfgloop.h"
33#include "df.h"
34#include "tm_p.h"
35#include "stringpool.h"
36#include "expmed.h"
37#include "optabs.h"
38#include "regs.h"
39#include "ira.h"
40#include "recog.h"
41#include "cgraph.h"
42#include "diagnostic-core.h"
43#include "insn-attr.h"
44#include "flags.h"
45#include "alias.h"
46#include "fold-const.h"
47#include "attribs.h"
48#include "stor-layout.h"
49#include "calls.h"
50#include "print-tree.h"
51#include "varasm.h"
52#include "explow.h"
53#include "expr.h"
54#include "output.h"
55#include "common/common-target.h"
56#include "langhooks.h"
57#include "gimplify.h"
58#include "gimple-fold.h"
59#include "gimple-iterator.h"
9885183c
DE		 60#include "ssa.h"
61#include "tree-ssa-propagate.h"
1acf0246
BS		 62#include "builtins.h"
63#include "tree-vector-builder.h"
64#if TARGET_XCOFF
65#include "xcoffout.h" /* get declarations of xcoff_*_section_name */
66#endif
67#include "ppc-auxv.h"
1acf0246 68#include "targhooks.h"
691eeb65 69#include "opts.h"
1acf0246
BS		 70
71#include "rs6000-internal.h"
72
73#if TARGET_MACHO
74#include "gstab.h" /* for N_SLINE */
75#include "dbxout.h" /* dbxout_ */
76#endif
77
78#ifndef TARGET_PROFILE_KERNEL
79#define TARGET_PROFILE_KERNEL 0
80#endif
81
c3550462
BS		 82#ifdef HAVE_AS_GNU_ATTRIBUTE
83# ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
84# define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
85# endif
86#endif
87
48df9391
IS		 88#ifndef TARGET_NO_PROTOTYPE
89#define TARGET_NO_PROTOTYPE 0
90#endif
91
1acf0246
BS		 92struct builtin_description
93{
94 const HOST_WIDE_INT mask;
95 const enum insn_code icode;
96 const char *const name;
97 const enum rs6000_builtins code;
98};
99
100/* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
101static const struct
102{
103 const char *cpu;
104 unsigned int cpuid;
105} cpu_is_info[] = {
67161d24 106 { "power10", PPC_PLATFORM_POWER10 },
1acf0246
BS		 107 { "power9", PPC_PLATFORM_POWER9 },
108 { "power8", PPC_PLATFORM_POWER8 },
109 { "power7", PPC_PLATFORM_POWER7 },
110 { "power6x", PPC_PLATFORM_POWER6X },
111 { "power6", PPC_PLATFORM_POWER6 },
112 { "power5+", PPC_PLATFORM_POWER5_PLUS },
113 { "power5", PPC_PLATFORM_POWER5 },
114 { "ppc970", PPC_PLATFORM_PPC970 },
115 { "power4", PPC_PLATFORM_POWER4 },
116 { "ppca2", PPC_PLATFORM_PPCA2 },
117 { "ppc476", PPC_PLATFORM_PPC476 },
118 { "ppc464", PPC_PLATFORM_PPC464 },
119 { "ppc440", PPC_PLATFORM_PPC440 },
120 { "ppc405", PPC_PLATFORM_PPC405 },
121 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
122};
123
124/* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
125static const struct
126{
127 const char *hwcap;
128 int mask;
129 unsigned int id;
130} cpu_supports_info[] = {
131 /* AT_HWCAP masks. */
132 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
133 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
134 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
135 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
136 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
137 { "booke", PPC_FEATURE_BOOKE, 0 },
138 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
139 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
140 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
141 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
142 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
143 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
144 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
145 { "notb", PPC_FEATURE_NO_TB, 0 },
146 { "pa6t", PPC_FEATURE_PA6T, 0 },
147 { "power4", PPC_FEATURE_POWER4, 0 },
148 { "power5", PPC_FEATURE_POWER5, 0 },
149 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
150 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
151 { "ppc32", PPC_FEATURE_32, 0 },
152 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
153 { "ppc64", PPC_FEATURE_64, 0 },
154 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
155 { "smt", PPC_FEATURE_SMT, 0 },
156 { "spe", PPC_FEATURE_HAS_SPE, 0 },
157 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
158 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
159 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
160
161 /* AT_HWCAP2 masks. */
162 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
163 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
164 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
165 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
166 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
167 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
168 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
169 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
170 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
171 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
172 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
173 { "darn", PPC_FEATURE2_DARN, 1 },
7ba33e89
MM		 174 { "scv", PPC_FEATURE2_SCV, 1 },
175 { "arch_3_1", PPC_FEATURE2_ARCH_3_1, 1 },
176 { "mma", PPC_FEATURE2_MMA, 1 },
1acf0246
BS		 177};
178
179static void altivec_init_builtins (void);
180static tree builtin_function_type (machine_mode, machine_mode,
181 machine_mode, machine_mode,
182 enum rs6000_builtins, const char *name);
183static void rs6000_common_init_builtins (void);
184static void htm_init_builtins (void);
8ee2640b 185static void mma_init_builtins (void);
1acf0246
BS		 186
187
188/* Hash table to keep track of the argument types for builtin functions. */
189
190struct GTY((for_user)) builtin_hash_struct
191{
192 tree type;
193 machine_mode mode[4]; /* return value + 3 arguments. */
194 unsigned char uns_p[4]; /* and whether the types are unsigned. */
195};
196
197struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
198{
199 static hashval_t hash (builtin_hash_struct *);
200 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
201};
202
203static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
204
205/* Hash function for builtin functions with up to 3 arguments and a return
206 type. */
207hashval_t
208builtin_hasher::hash (builtin_hash_struct *bh)
209{
210 unsigned ret = 0;
211 int i;
212
213 for (i = 0; i < 4; i++)
214 {
215 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
216 ret = (ret * 2) + bh->uns_p[i];
217 }
218
219 return ret;
220}
221
222/* Compare builtin hash entries H1 and H2 for equivalence. */
223bool
224builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
225{
226 return ((p1->mode[0] == p2->mode[0])
227 && (p1->mode[1] == p2->mode[1])
228 && (p1->mode[2] == p2->mode[2])
229 && (p1->mode[3] == p2->mode[3])
230 && (p1->uns_p[0] == p2->uns_p[0])
231 && (p1->uns_p[1] == p2->uns_p[1])
232 && (p1->uns_p[2] == p2->uns_p[2])
233 && (p1->uns_p[3] == p2->uns_p[3]));
234}
235
236\f
237/* Table that classifies rs6000 builtin functions (pure, const, etc.). */
238#undef RS6000_BUILTIN_0
239#undef RS6000_BUILTIN_1
240#undef RS6000_BUILTIN_2
241#undef RS6000_BUILTIN_3
840ac85c 242#undef RS6000_BUILTIN_4
1acf0246
BS		 243#undef RS6000_BUILTIN_A
244#undef RS6000_BUILTIN_D
245#undef RS6000_BUILTIN_H
8ee2640b 246#undef RS6000_BUILTIN_M
1acf0246
BS		 247#undef RS6000_BUILTIN_P
248#undef RS6000_BUILTIN_X
249
250#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
251 { NAME, ICODE, MASK, ATTR },
252
253#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
254 { NAME, ICODE, MASK, ATTR },
255
256#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
257 { NAME, ICODE, MASK, ATTR },
258
259#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
260 { NAME, ICODE, MASK, ATTR },
261
840ac85c
KN		 262#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) \
263 { NAME, ICODE, MASK, ATTR },
264
1acf0246
BS		 265#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
266 { NAME, ICODE, MASK, ATTR },
267
268#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
269 { NAME, ICODE, MASK, ATTR },
270
271#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
272 { NAME, ICODE, MASK, ATTR },
273
8ee2640b
PB		 274#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \
275 { NAME, ICODE, MASK, ATTR },
276
1acf0246
BS		 277#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
278 { NAME, ICODE, MASK, ATTR },
279
280#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
281 { NAME, ICODE, MASK, ATTR },
282
283struct rs6000_builtin_info_type {
284 const char *name;
285 const enum insn_code icode;
286 const HOST_WIDE_INT mask;
287 const unsigned attr;
288};
289
25ffd3d3 290static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1acf0246
BS		 291{
292#include "rs6000-builtin.def"
293};
294
295#undef RS6000_BUILTIN_0
296#undef RS6000_BUILTIN_1
297#undef RS6000_BUILTIN_2
298#undef RS6000_BUILTIN_3
840ac85c 299#undef RS6000_BUILTIN_4
1acf0246
BS		 300#undef RS6000_BUILTIN_A
301#undef RS6000_BUILTIN_D
302#undef RS6000_BUILTIN_H
8ee2640b 303#undef RS6000_BUILTIN_M
1acf0246
BS		 304#undef RS6000_BUILTIN_P
305#undef RS6000_BUILTIN_X
306
25ffd3d3
PB		 307const struct altivec_builtin_types altivec_overloaded_builtins[] = {
308 /* Unary AltiVec/VSX builtins. */
309 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
310 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
311 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
312 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
313 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
314 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
315 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
316 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
317 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
318 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
319 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
320 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
321 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
322 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
323 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
324 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
325 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
326 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
327 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
328 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
329 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
330 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
331 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
332 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
333 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
334 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
335 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
336 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
337 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
338 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
339 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
340 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
341 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
342 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
343 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
344 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
345 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
346 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
347 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
348 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
349 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
350 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
351 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
352 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
353 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
354 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
355 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
356 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
357 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
358 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
359 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
360 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
361 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
362 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
363 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
364 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
365 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
366 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
367 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
368 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
369 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
370 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
371 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
372 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
373 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
374 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
375 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
376 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
377 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
378 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
379 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
380 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
381 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
382 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
383 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
384 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
385 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
386 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
387 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
388 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
389 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
390 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
391 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
392 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
393 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
394 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
395 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
396 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
397 { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF,
398 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
399 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
400 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
401 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
402 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
403 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
404 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
405 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
406 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
407 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
408 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
409 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
410 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
411 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
412 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
413 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
414 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
415 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
416 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
417 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
418 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
419 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
420 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
421 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
422 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
423 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
424 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
425 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
426 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
427 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
428 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
429 { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF,
430 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
431 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
432 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
433 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
434 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
435 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
436 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
437 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
438 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
439 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
440 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
441 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
442 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
443
444 /* Binary AltiVec/VSX builtins. */
445 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
446 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
447 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
448 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
449 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
450 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
451 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
452 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
453 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
454 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
455 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
456 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
457 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
458 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
459 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
460 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
461 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
462 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
463 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
464 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
465 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
466 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
467 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
468 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
469 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
470 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
471 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
472 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
473 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
474 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
475 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
476 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
477 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
478 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
479 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
480 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
481 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
482 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
483 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
484 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
485 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
486 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
487 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
488 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
489 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
490 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
491 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
492 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
493 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
494 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
495 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
496 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
497 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
498 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
499 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
500 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
501 RS6000_BTI_unsigned_V1TI, 0 },
502 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
503 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
504 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
505 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
506 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
507 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
508 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
509 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
510 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
511 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
512 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
513 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
514 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
515 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
516 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
517 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
518 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
519 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
520 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
521 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
522 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
523 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
524 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
525 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
526 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
527 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
528 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
529 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
530 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
531 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
532 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
533 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
534 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
535 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
536 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
537 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
538 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
539 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
540 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
541 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
542 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
543 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
544 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
545 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
546 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
547 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
548 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
549 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
550 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
551 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
552 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
553 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
554 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
555 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
556 RS6000_BTI_unsigned_V4SI, 0 },
557 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
558 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
559 RS6000_BTI_unsigned_V1TI, 0 },
560 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
561 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
562 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
563 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
564 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
565 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
566 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
567 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
568 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
569 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
570 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
571 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
572 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
573 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
574 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
575 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
576 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
577 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
578 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
579 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
580 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
581 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
582 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
583 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
584 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
585 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
586 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
587 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
588 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
589 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
590 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
591 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
592 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
593 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
594 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
595 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
596 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
597 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
598 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
599 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
600 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
601 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
602 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
603 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
604 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
605 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
606 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
607 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
608 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
609 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
610 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
611 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
612 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
613 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
614 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
615 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
616 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
617 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
618 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
619 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
620 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
621 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
622 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
623 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
624 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
625 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
626 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
627 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
628 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
629 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
630 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
631 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
632 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
633 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
634 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
635 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
636 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
637 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
638 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
639 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
640 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
641 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
642 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
643 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
644 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
645 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
646 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
647 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
648 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
649 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
650 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23
PB		 651
652 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
25ffd3d3 653 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 654 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
25ffd3d3 655 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 656 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
25ffd3d3 657 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 658 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
25ffd3d3 659 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 660 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
25ffd3d3 661 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 662 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
25ffd3d3 663 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 664 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
25ffd3d3 665 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 666 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
25ffd3d3 667 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 668 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
25ffd3d3 669 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 670 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 671 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 672 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 673 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 674 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 675 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 676 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
25ffd3d3 677 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 678 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 679 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 680 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
25ffd3d3 681 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 682 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
25ffd3d3 683 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 684 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
25ffd3d3 685 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 686 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 687 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 688 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 689 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 690 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
25ffd3d3 691 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 692 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 693 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 694 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
25ffd3d3 695 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 696 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
25ffd3d3 697 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 698 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
25ffd3d3 699 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 700 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 701 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 702 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 703 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 704 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
25ffd3d3 705 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 706 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
25ffd3d3 707 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 708 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 709 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 710 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
25ffd3d3 711 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 712 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
25ffd3d3 713 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 714 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 715 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 716 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 717 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 718 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
25ffd3d3 719 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23
PB		 720
721 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
25ffd3d3 722 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 723 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
25ffd3d3 724 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 725 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
25ffd3d3 726 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 727 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
25ffd3d3 728 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 729 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
25ffd3d3 730 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 731 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
25ffd3d3 732 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 733 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
25ffd3d3 734 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 735 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
25ffd3d3 736 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 737 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
25ffd3d3 738 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 739 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 740 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 741 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 742 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 743 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 744 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 745 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
25ffd3d3 746 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 747 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 748 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 749 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
25ffd3d3 750 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 751 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
25ffd3d3 752 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 753 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
25ffd3d3 754 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 755 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 756 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 757 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 758 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 759 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
25ffd3d3 760 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 761 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 762 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 763 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
25ffd3d3 764 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 765 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
25ffd3d3 766 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 767 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
25ffd3d3 768 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 769 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 770 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 771 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 772 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 773 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
25ffd3d3 774 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 775 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
25ffd3d3 776 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 777 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 778 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 779 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
25ffd3d3 780 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 781 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
25ffd3d3 782 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 783 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 784 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 785 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 786 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 787 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
25ffd3d3 788 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 789
25ffd3d3
PB		 790 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
791 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
792 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
793 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
794 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
795 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
796 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
797 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
798 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
799 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
800 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
801 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
802 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
803 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
804 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
805 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
806 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
807 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
808 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
809 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
810 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
811 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
812 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
813 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
814 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
815 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
816 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
817 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
818 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
819 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
820 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
821 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
822 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
823 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
824 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
825 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
826 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
827 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
828 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
829 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
830 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
831 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
832 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
833 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
834 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
835 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
836 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
837 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
838 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
839 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
840 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
841 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
842 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
843 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
844 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
845 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
846
847 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
848 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
849 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
850 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
851
852 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
853 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
854 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
855 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
856
857 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
858 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
859 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
860 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
861
862 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
863 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
864 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
865 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
866 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
867 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
868 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
869 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
870 RS6000_BTI_unsigned_V16QI, 0},
871 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
872 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
873 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
874 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
875 RS6000_BTI_unsigned_V8HI, 0},
876 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
877 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
878 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
879 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
880 RS6000_BTI_unsigned_V4SI, 0},
881 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
882 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
883 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
884 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
885 RS6000_BTI_unsigned_V2DI, 0},
886 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
887 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
888 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
889 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
890 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
891 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
892 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
893 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
894 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
895 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
896 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
897 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
898 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
899 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
900 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
901 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
902 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
903 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
904 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
905 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
906 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
907 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
908 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
909 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
910 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
911 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
912 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
913 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
914 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
915 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
916 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
917 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
918 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
919 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
920 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
921 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
922 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
923 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
924 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
925 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
926 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
927 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
928 RS6000_BTI_unsigned_V16QI, 0},
929 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
930 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
931 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
932 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
933 RS6000_BTI_unsigned_V8HI, 0},
934 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
935 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
936 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
937 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
938 RS6000_BTI_unsigned_V4SI, 0},
939 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
940 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
941 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
942 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
943 RS6000_BTI_unsigned_V2DI, 0},
944 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
945 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
946 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
947 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
948 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
949 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
950 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
951 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
952 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
953 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
954 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
955 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
956 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
957 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
958 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
959 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
960 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
961 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
962 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
963 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
964 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
965 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
966 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
967 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
968 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
969 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
970 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
971 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
972 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
973 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
974 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
975 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
976 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
977 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
978 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
979 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
980 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
981 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
982 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
983 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
984 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
985 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
986 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
987 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
05161256
CL		 988
989 { P8V_BUILTIN_VEC_BCDADD, MISC_BUILTIN_BCDADD_V1TI,
990 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
991 { P8V_BUILTIN_VEC_BCDADD, MISC_BUILTIN_BCDADD_V16QI,
992 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
993 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
994 { P8V_BUILTIN_VEC_BCDADD_LT, MISC_BUILTIN_BCDADD_LT_V1TI,
995 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
996 { P8V_BUILTIN_VEC_BCDADD_LT, MISC_BUILTIN_BCDADD_LT_V16QI,
997 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
998 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
999 { P8V_BUILTIN_VEC_BCDADD_EQ, MISC_BUILTIN_BCDADD_EQ_V1TI,
1000 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1001 { P8V_BUILTIN_VEC_BCDADD_EQ, MISC_BUILTIN_BCDADD_EQ_V16QI,
1002 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1003 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1004 { P8V_BUILTIN_VEC_BCDADD_GT, MISC_BUILTIN_BCDADD_GT_V1TI,
1005 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1006 { P8V_BUILTIN_VEC_BCDADD_GT, MISC_BUILTIN_BCDADD_GT_V16QI,
1007 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1008 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1009 { P8V_BUILTIN_VEC_BCDADD_OV, MISC_BUILTIN_BCDADD_OV_V1TI,
1010 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1011 { P8V_BUILTIN_VEC_BCDADD_OV, MISC_BUILTIN_BCDADD_OV_V16QI,
1012 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1013 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1014 { P8V_BUILTIN_VEC_BCDINVALID, MISC_BUILTIN_BCDINVALID_V1TI,
1015 RS6000_BTI_INTSI, RS6000_BTI_V1TI, 0, 0 },
1016 { P8V_BUILTIN_VEC_BCDINVALID, MISC_BUILTIN_BCDINVALID_V16QI,
1017 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
1018
1019 { P9V_BUILTIN_VEC_BCDMUL10, P9V_BUILTIN_BCDMUL10_V16QI,
1020 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
1021 { P9V_BUILTIN_VEC_BCDDIV10, P9V_BUILTIN_BCDDIV10_V16QI,
1022 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
1023
1024 { P8V_BUILTIN_VEC_DENBCD, MISC_BUILTIN_DENBCD_V16QI,
1025 RS6000_BTI_dfloat128, RS6000_BTI_unsigned_V16QI, 0, 0 },
1026
1027 { P8V_BUILTIN_VEC_BCDSUB, MISC_BUILTIN_BCDSUB_V1TI,
1028 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1029 { P8V_BUILTIN_VEC_BCDSUB, MISC_BUILTIN_BCDSUB_V16QI,
1030 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
1031 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1032 { P8V_BUILTIN_VEC_BCDSUB_LT, MISC_BUILTIN_BCDSUB_LT_V1TI,
1033 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1034 { P8V_BUILTIN_VEC_BCDSUB_LT, MISC_BUILTIN_BCDSUB_LT_V16QI,
1035 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1036 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1037 { P8V_BUILTIN_VEC_BCDSUB_LE, MISC_BUILTIN_BCDSUB_LE_V1TI,
1038 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1039 { P8V_BUILTIN_VEC_BCDSUB_LE, MISC_BUILTIN_BCDSUB_LE_V16QI,
1040 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1041 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1042 { P8V_BUILTIN_VEC_BCDSUB_EQ, MISC_BUILTIN_BCDSUB_EQ_V1TI,
1043 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1044 { P8V_BUILTIN_VEC_BCDSUB_EQ, MISC_BUILTIN_BCDSUB_EQ_V16QI,
1045 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1046 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1047 { P8V_BUILTIN_VEC_BCDSUB_GT, MISC_BUILTIN_BCDSUB_GT_V1TI,
1048 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1049 { P8V_BUILTIN_VEC_BCDSUB_GT, MISC_BUILTIN_BCDSUB_GT_V16QI,
1050 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1051 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1052 { P8V_BUILTIN_VEC_BCDSUB_GE, MISC_BUILTIN_BCDSUB_GE_V1TI,
1053 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1054 { P8V_BUILTIN_VEC_BCDSUB_GE, MISC_BUILTIN_BCDSUB_GE_V16QI,
1055 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1056 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1057 { P8V_BUILTIN_VEC_BCDSUB_OV, MISC_BUILTIN_BCDSUB_OV_V1TI,
1058 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1059 { P8V_BUILTIN_VEC_BCDSUB_OV, MISC_BUILTIN_BCDSUB_OV_V16QI,
1060 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1061 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1062
1063
25ffd3d3
PB		 1064 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
1065 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1066 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
1067 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1068 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
1069 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1070 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
1071 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1072 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
1073 RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
1074 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1075 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1076
1077 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
1078 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1079 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
1080 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1081 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
1082 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1083
1084 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
1085 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1086 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
1087 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1088 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
1089 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1090
1091 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI,
1092 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1093 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI,
1094 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1095 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF,
1096 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1097
1098 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI,
1099 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1100 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI,
1101 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1102 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF,
1103 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1104
1105 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1106 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1107 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1108 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1109 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF,
1110 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1111 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI,
1112 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1113 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI,
1114 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1115 RS6000_BTI_unsigned_V2DI, 0 },
1116 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1117 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1118 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1119 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1120 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI,
1121 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1122 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF,
1123 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1124 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1125 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1126 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1127 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1128
1129 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1130 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
1131 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1132 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 },
1133 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1134 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
1135 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1136 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
1137
1138 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1139 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1140 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1141 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1142 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1143 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1144 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1145 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1146 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1147 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1148 ~RS6000_BTI_unsigned_V2DI, 0 },
1149 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1150 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1151 ~RS6000_BTI_unsigned_long_long, 0 },
1152 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1153 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1154 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1155 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1156 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1157 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1158 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1159 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1160 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1161 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1162 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1163 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1164 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1165 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1166 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1167 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1168 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1169 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1170 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1171 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1172 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1173 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1174 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1175 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1176 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1177 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1178 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1179 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1180 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1181 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1182 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1183 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1184 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1185 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1186 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1187 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1188 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1189 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1190 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1191 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1192 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1193 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1194 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1195 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1196 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1197 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1198 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1199 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1200 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1201 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1202 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1203 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1204 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1205 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1206 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1207 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1208 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1209 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1210 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1211 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1212 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1213 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1214 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1215 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1216 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1217 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1218 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1219 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1220 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1221 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1222 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1223 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1224 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1225 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1226 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1227 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1228 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1229 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1230
b69c0061
WS		 1231 /* vector signed__int128 vec_xl_sext (signed long long, signed char *);
1232 vector signed__int128 vec_xl_sext (signed long long, signed short *);
1233 vector signed__int128 vec_xl_sext (signed long long, signed int *);
1234 vector signed__int128 vec_xl_sext (signed long long, signed longlong *); */
1235 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRBX,
1236 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1237 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRHX,
1238 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1239 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRWX,
1240 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1241 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRDX,
1242 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1243 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRDX,
1244 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1245
1246 /* vector unsigned__int128 vec_xl_zext (signed long long, unsigned char *);
1247 vector unsigned__int128 vec_xl_zext (signed long long, unsigned short *);
1248 vector unsigned__int128 vec_xl_zext (signed long long, unsigned int *);
1249 vector unsigned__int128 vec_xl_zext (signed long long, unsigned longlong *); */
1250 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRBX,
1251 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1252 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRHX,
1253 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1254 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRWX,
1255 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1256 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRDX,
1257 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1258 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRDX,
1259 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
1260
1261 /* void vec_xst_trunc (vector signed __int128, signed long long, signed char *);
1262 void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *);
1263 void vec_xst_trunc (vector signed __int128, signed long long, signed char *);
1264 void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *);
1265 void vec_xst_trunc (vector signed __int128, signed long long, signed char *);
1266 void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *);
1267 void vec_xst_trunc (vector signed __int128, signed long long, signed char *);
1268 void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *); */
1269 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRBX, RS6000_BTI_void,
1270 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
1271 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRBX, RS6000_BTI_void,
1272 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
1273 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRHX, RS6000_BTI_void,
1274 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
1275 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRHX, RS6000_BTI_void,
1276 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
1277 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRWX, RS6000_BTI_void,
1278 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
1279 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRWX, RS6000_BTI_void,
1280 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
1281 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void,
1282 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
1283 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void,
1284 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long },
1285 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void,
1286 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI },
1287 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void,
1288 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI },
1289
25ffd3d3
PB		 1290 /* vector float vec_ldl (int, vector float *);
1291 vector float vec_ldl (int, float *); */
1292 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1293 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1294 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1295 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1296
1297 /* vector bool int vec_ldl (int, vector bool int *);
1298 vector bool int vec_ldl (int, bool int *);
1299 vector int vec_ldl (int, vector int *);
1300 vector int vec_ldl (int, int *);
1301 vector unsigned int vec_ldl (int, vector unsigned int *);
1302 vector unsigned int vec_ldl (int, unsigned int *); */
1303 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1304 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1305 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1306 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 },
1307 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1308 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1309 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1310 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1311 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1312 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1313 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1314 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1315
1316 /* vector bool short vec_ldl (int, vector bool short *);
1317 vector bool short vec_ldl (int, bool short *);
1318 vector pixel vec_ldl (int, vector pixel *);
1319 vector short vec_ldl (int, vector short *);
1320 vector short vec_ldl (int, short *);
1321 vector unsigned short vec_ldl (int, vector unsigned short *);
1322 vector unsigned short vec_ldl (int, unsigned short *); */
1323 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1324 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1325 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1326 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 },
1327 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1328 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1329 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1330 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1331 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1332 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1333 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1334 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1335 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1336 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1337
1338 /* vector bool char vec_ldl (int, vector bool char *);
1339 vector bool char vec_ldl (int, bool char *);
1340 vector char vec_ldl (int, vector char *);
1341 vector char vec_ldl (int, char *);
1342 vector unsigned char vec_ldl (int, vector unsigned char *);
1343 vector unsigned char vec_ldl (int, unsigned char *); */
1344 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1345 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1346 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1347 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 },
1348 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1349 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1350 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1351 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1352 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1353 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1354 ~RS6000_BTI_unsigned_V16QI, 0 },
1355 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1356 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1357
1358 /* vector double vec_ldl (int, vector double *);
1359 vector double vec_ldl (int, double *); */
1360 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1361 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1362 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1363 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1364
1365 /* vector long long vec_ldl (int, vector long long *);
1366 vector long long vec_ldl (int, long long *);
1367 vector unsigned long long vec_ldl (int, vector unsigned long long *);
1368 vector unsigned long long vec_ldl (int, unsigned long long *);
1369 vector bool long long vec_ldl (int, vector bool long long *);
1370 vector bool long long vec_ldl (int, bool long long *); */
1371 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1372 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1373 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1374 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1375 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1376 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1377 ~RS6000_BTI_unsigned_V2DI, 0 },
1378 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1379 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1380 ~RS6000_BTI_unsigned_long_long, 0 },
1381 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1382 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1383 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1384 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 },
1385
1386 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1387 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1388 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1389 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1390 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1391 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1392 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1393 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1394 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1395 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1396 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1397 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1398 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1399 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1400 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1401 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1402 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1403 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1404 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1405 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1406 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1407 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1408 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1409 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1410 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1411 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1412 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1413 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1414 ~RS6000_BTI_unsigned_long_long, 0 },
1415 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1416 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1417 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1418 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1419 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1420 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1421 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1422 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1423 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1424 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1425 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1426 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1427 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1428 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1429 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1430 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1431 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1432 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1433 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1434 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1435 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1436 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1437 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1438 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1439 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1440 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1441 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1442 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1443 ~RS6000_BTI_unsigned_long_long, 0 },
1444 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1445 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1446 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1447 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1448 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1449 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1450 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1451 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1452 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1453 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1454 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1455 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1456 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1457 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1458 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1459 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1460 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1461 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1462 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1463 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1464 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1465 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1466 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1467 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1468 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1469 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1470 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1471 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1472 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1473 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1474 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1475 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1476 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1477 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1478 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1479 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1480 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1481 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1482 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1483 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1484 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1485 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1486 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1487 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1488 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1489 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1490 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1491 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1492 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1493 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1494 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1495 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1496 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1497 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1498 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1499 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1500 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1501 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1502 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1503 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1504 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1505 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1506 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1507 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1508 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1509 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1510 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1511 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1512 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1513 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1514 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1515 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1516 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1517 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1518 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1519 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1520 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1521 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1522 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1523 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1524 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1525 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1526 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1527 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1528 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1529 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1530 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1531 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1532 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1533 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1534 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1535 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1536 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1537 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1538 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1539 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1540 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1541 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1542 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1543 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1544 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1545 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1546 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1547 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1548 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1549 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1550 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1551 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1552 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1553 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1554 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1555 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1556 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1557 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1558 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1559 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1560 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1561 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1562 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1563 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1564 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1565 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1566 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1567 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1568 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1569 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1570 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1571 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1572 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1573 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1574 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1575 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1576 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1577 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1578 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1579 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1580 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1581 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1582 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1583 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1584 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1585 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1586 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1587 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1588 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1589 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1590 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1591 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1592 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1593 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1594 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1595 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1596 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1597 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1598 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1599 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1600 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1601 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1602 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1603 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1604 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1605 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1606 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1607 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1608 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1609 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1610 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1611 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1612 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1613 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1614 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1615 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1616 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1617 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1618 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1619 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1620 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1621 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1622 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1623 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1624 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1625 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1626 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1627 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1628 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1629 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1630 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1631 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1632 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1633 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1634 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1635 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1636 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
1637 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1638 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
1639 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1640 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
1641 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1642 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1643 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1644 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1645 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1646 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1647 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1648 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1649 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1650 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1651 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1652 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1653 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1654 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1655 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1656 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1657 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1658 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1659 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1660 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1661 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1662 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1663 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1664 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1665 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1666 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1667 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1668 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1669 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1670 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1671 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1672 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1673 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1674 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1675 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1676 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1677 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1678 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1679 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1680 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1681 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1682 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1683 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1684 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1685 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1686 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1687 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1688 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1689 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1690 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1691 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1692 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1693 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1694 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1695 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1696 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1697 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1698 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1699 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1700 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1701 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1702 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1703 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1704 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1705 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1706 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1707 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1708 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1709 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1710 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1711 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1712 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
1713 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1714 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1715 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1716 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1717 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1718 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1719 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1720 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1721 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1722 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1723 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1724 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1725 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1726 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1727 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1728 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1729 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1730 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1731 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1732 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1733 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1734 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1735 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1736 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1737 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1738 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1739 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1740 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1741 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1742 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1743 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1744 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1745 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1746 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1747 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1748 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1749 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1750 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1751 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1752 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1753 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1754 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1755 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1756 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1757 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1758 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1759 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1760 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1761 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1762 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1763 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1764 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1765 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1766 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1767 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1768 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1769 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1770 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1771 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1772 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
1773 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1774 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1775 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1776 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1777 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1778 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1779 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1780 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1781 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1782 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1783 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1784 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1785 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1786 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1787 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1788 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1789 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1790 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1791 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1792 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1793 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1794 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1795 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1796 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1797 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1798 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1799 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1800 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1801 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1802 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1803 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1804 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1805 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1806 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1807 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1808 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1809 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1810 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1811 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1812 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1813 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1814 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1815 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1816 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1817 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1818 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1819 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1820 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1821 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1822 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1823 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1824 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1825 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1826 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1827 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1828 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1829 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1830 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1831 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1832 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1833 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1834 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1835 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1836 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1837 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1838 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1839 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1840 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1841 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1842 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1843 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1844 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1845 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1846 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1847 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1848 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1849 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1850 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1851 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1852 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1853 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1854 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1855 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1856 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1857 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1858 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
1859 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1860 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
1861 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1862 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
1863 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1864 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1865 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1866 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1867 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1868 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1869 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1870 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1871 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1872 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1873 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1874 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1875 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1876 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1877 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1878 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1879 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1880 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1881 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1882 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1883 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1884 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1885 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1886 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1887 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1888 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1889 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1890 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1891 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1892 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1893 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1894 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1895 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1896 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1897 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1898 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1899 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1900 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1901 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1902 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1903 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1904 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1905 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1906 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1907 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1908 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1909 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1910 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1911 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1912 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
1913 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1914 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
1915 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1916 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
1917 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1918 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
1919 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1920 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
1921 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1922 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
1923 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
1924 RS6000_BTI_unsigned_V4SI, 0 },
1925 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
1926 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1927 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
1928 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1929 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
1930 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1931 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
1932 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1933 { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
1934 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1935 { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
1936 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1937 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
1938 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1939 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
1940 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1941 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
1942 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1943 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW,
1944 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1945 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
1946 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
1947 RS6000_BTI_unsigned_V4SI, 0 },
1948 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
1949 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1950 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
1951 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1952 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
1953 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1954 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
1955 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1956 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
1957 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1958 { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW,
1959 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1960 { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW,
1961 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1962
1963 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
1964 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
1965 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
1966 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
1967 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
1968 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
1969 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
1970 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
1971 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
1972 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
1973 { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
1974 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
1975 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
1976 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
1977 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
1978 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
1979
4559be23 1980 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SF,
25ffd3d3 1981 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 1982 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DF,
25ffd3d3 1983 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 1984 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
25ffd3d3 1985 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1986 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
25ffd3d3 1987 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1988 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
25ffd3d3 1989 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 1990 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1991 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1992 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1993 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1994 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1995 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 1996 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
25ffd3d3 1997 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 1998 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI,
25ffd3d3 1999 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 2000 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
25ffd3d3 2001 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 2002 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
25ffd3d3 2003 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2004 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI,
25ffd3d3 2005 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 2006 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
25ffd3d3 2007 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 2008 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
25ffd3d3 2009 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2010 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI,
25ffd3d3 2011 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 2012 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
25ffd3d3 2013 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 2014 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
25ffd3d3 2015 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23
PB		 2016
2017 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
25ffd3d3 2018 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 2019 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
25ffd3d3 2020 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 2021 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
25ffd3d3 2022 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 2023 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
25ffd3d3 2024 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 2025 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
25ffd3d3 2026 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 2027 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
25ffd3d3 2028 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 2029 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
25ffd3d3 2030 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 2031 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
25ffd3d3 2032 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2033 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
25ffd3d3 2034 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 2035 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 2036 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 2037 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 2038 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2039 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 2040 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 2041 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
25ffd3d3 2042 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2043 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 2044 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2045 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
25ffd3d3 2046 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 2047 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
25ffd3d3 2048 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2049 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
25ffd3d3 2050 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 2051 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 2052 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 2053 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 2054 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2055 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
25ffd3d3 2056 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 2057 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 2058 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2059 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
25ffd3d3 2060 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 2061 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
25ffd3d3 2062 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2063 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
25ffd3d3 2064 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 2065 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 2066 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 2067 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 2068 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2069 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
25ffd3d3 2070 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 2071 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
25ffd3d3 2072 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 2073 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 2074 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 2075 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
25ffd3d3 2076 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 2077 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
25ffd3d3 2078 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 2079 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 2080 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 2081 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 2082 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 2083 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
25ffd3d3 2084 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
4559be23 2085
25ffd3d3
PB		 2086 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2087 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2088 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2089 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2090 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2091 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2092 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2093 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2094 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2095 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2096 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2097 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2098 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2099 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2100 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2101 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2102 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2103 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2104 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF,
2105 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2106
2107 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI,
2108 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2109 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI,
2110 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2111 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI,
2112 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2113 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI,
2114 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2115 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF,
2116 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2117 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF,
2118 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2119
2120 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
2121 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
58b475a2
WS		 2122 { P9V_BUILTIN_VEC_CONVERT_4F32_8F16, P9V_BUILTIN_CONVERT_4F32_8F16,
2123 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
25ffd3d3
PB		 2124
2125 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2126 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2127 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2128 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2129 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2130 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2131 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2132 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2133 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2134 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2135 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2136 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2137 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2138 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2139 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2140 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2141 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2142 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2143 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2144 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2145 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2146 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2147 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2148 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2149 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2150 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2151 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2152 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2153 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2154 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2155 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2156 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2157 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2158 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2159 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2160 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2161
2162 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2163 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI,
2164 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2165 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2166 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI,
2167 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2168 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2169 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2170 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2171 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2172 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2173 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2174 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2175 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2176 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2177 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2178 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2179 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2180
2181 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2182 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2183 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2184 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2185 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2186 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2187 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2188 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2189 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2190 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2191 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2192 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2193 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2194 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2195 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2196 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2197 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2198 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2199 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2200 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2201 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2202 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2203 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2204 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2205 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2206 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2207 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2208 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2209 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2210 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2211 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2212 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2213 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2214 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2215 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2216 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2217 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2218 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2219 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2220 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2221 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2222 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2223 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2224 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2225 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS,
2226 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2227 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2228 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2229 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2230 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2231 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2232 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2233 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2234 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2235 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2236 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2237 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2238 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2239 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2240 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2241 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2242 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2243 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2244 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2245 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2246 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2247 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2248 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2249 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2250 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2251 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2252 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2253 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2254 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2255 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2256 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2257 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2258 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2259 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2260 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2261 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2262 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2263 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2264 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2265 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2266 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2267 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2268 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2269 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2270 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2271 RS6000_BTI_unsigned_V4SI, 0 },
2272 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2273 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2274 RS6000_BTI_unsigned_V2DI, 0 },
2275 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2276 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2277 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2278 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2279 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2280 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2281 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2282 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2283 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2284 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2285 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2286 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2287 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2288 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2289 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2290 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2291 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2292 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2293 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2294 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2295 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2296 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2297 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2298 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2299 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2300 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2301 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2302 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2303 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2304 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2305 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2306 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2307 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2308 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2309 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2310 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2311 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2312 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2313 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2314 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2315 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2316 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2317 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2318 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2319 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2320 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2321 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2322 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2323 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2324 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2325 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2326 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2327 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2328 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2329 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2330 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2331 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2332 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2333 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2334 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2335 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2336 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2337 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2338 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2339 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2340 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2341 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2342 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2343 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2344 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2345 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2346 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2347 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2348 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2349 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2350 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2351 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2352 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2353 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2354 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2355 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2356 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2357 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2358 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2359 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2360 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2361 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2362 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2363 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2364 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2365 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2366 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2367
2368 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2369 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2370 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2371 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2372 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2373 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2374 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2375 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2376 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2377 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 },
2378
2379 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2380 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2381 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2382 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2383 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2384 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2385 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2386 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2387 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2388 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2389 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2390 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2391 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2392 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2393 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2394 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2395 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2396 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2397 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2398 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2399 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2400 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2401 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2402 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2403 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2404 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2405 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2406 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2407 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2408 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2409 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2410 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2411 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2412 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2413 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2414 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2415 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2416 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2417 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2418 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2419 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2420 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2421 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2422 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2423 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2424 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2425 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2426 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2427 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2428 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2429 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2430 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2431 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2432 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2433 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2434 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2435 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2436 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2437 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2438 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2439 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2440 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2441 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2442 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2443 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2444 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2445 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2446 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2447 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2448 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2449 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2450 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2451 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2452 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2453 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2454 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2455 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2456 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2457 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2458 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2459 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2460 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2461 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2462 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2463 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2464 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2465 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2466 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2467 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2468 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2469 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2470 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2471 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2472 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2473 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2474 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2475 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2476 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2477 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2478 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2479 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2480 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2481 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2482 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2483 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2484 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2485 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2486 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2487 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2488 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2489 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2490 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2491 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2492 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2493 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2494 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2495 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2496 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2497 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2498 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2499 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2500 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2501 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2502 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2503 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2504 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2505 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2506 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2507 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2508 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2509 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2510 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2511 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2512 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2513 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2514 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2515 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2516 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2517 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2518 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2519 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2520 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2521 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2522 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2523 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2524 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2525 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2526 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2527 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2528 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2529 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2530 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2531 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2532 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2533 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2534 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2535 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2536 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2537 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2538 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2539 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2540 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2541 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2542 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2543 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2544 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2545 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2546 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2547 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2548 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2549 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2550 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2551 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2552 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2553 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2554 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2555 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2556 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2557 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2558 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2559 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2560 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2561 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2562 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2563 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2564 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2565 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2566 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2567 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2568 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2569 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2570 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2571 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2572 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2573 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2574 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2575 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2576 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2577 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2578 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2579 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2580 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2581 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2582 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2583 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2584 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2585 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2586 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2587 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2588 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2589 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2590 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2591 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2592 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2593 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2594 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2595 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2596 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2597 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2598 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2599 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2600 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2601 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2602 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2603 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2604 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2605 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2606 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2607 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2608 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2609 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2610 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2611 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2612 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2613 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2614 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2615 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2616 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2617 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2618 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2619 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2620 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2621 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2622 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2623 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2624 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2625 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2626 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2627 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2628 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2629 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2630 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2631
2632 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2633 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2634 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2635 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2636 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2637 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2638 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2639 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2640 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2641 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2642 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2643 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2644 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2645 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2646 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2647 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2648 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2649 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2650 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2651 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2652 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2653 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2654 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2655 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2656 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2657 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2658 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2659 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2660 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2661 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2662 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2663 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2664 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2665 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2666 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2667 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2668 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2669 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2670 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2671 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2672 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2673 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2674 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2675 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2676 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2677 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2678 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2679 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2680 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
2681 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2682 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
2683 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2684 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2685 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2686 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2687 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2688 RS6000_BTI_unsigned_V1TI, 0 },
2689 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
2690 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2691 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2692 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2693 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2694 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2695 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2696 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2697 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2698 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2699 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2700 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2701 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2702 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2703 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2704 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2705 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2706 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2707 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2708 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2709 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2710 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2711 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2712 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2713 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2714 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2715 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2716 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2717 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2718 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2719 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2720 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2721 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2722 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2723 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2724 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2725 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2726 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2727 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2728 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2729 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2730 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2731 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2732 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2733 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2734 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2735 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2736 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2737 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2738 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2739
2740 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2741 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2742 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2743 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2744 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2745 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2746 RS6000_BTI_unsigned_V1TI, 0 },
2747 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2748 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2749
2750 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2751 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2752 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2753 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2754 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2755 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2756 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2757 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2758 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2759 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2760 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2761 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2762 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2763 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2764 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2765 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2766 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2767 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2768 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2769 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2770 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2771 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2772 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2773 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2774 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2775 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2776 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2777 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2778 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2779 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2780 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2781 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2782 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2783 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2784 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2785 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2786 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2787 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2788 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2789 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2790 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2791 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2792 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2793 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2794 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2795 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2796 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2797 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2798 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2799 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2800 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2801 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2802 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2803 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2804 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2805 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2806 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2807 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2808 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2809 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2810 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2811 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2812 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2813 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2814 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2815 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2816 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2817 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2818 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2819 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2820 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2821 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2822 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2823 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2824 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2825 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2826 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2827 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2828 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2829 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2830 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2831 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2832 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2833 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2834 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
2835 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2836 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
2837 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2838 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
2839 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2840 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
2841 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2842 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
2843 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2844 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
2845 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2846 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
2847 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2848 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
2849 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2850
2851 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
2852 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
2853 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
2854 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
2855 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2856 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
2857 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2858 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
2859 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2860 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
2861 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2862 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
2863 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2864 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
2865 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2866 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
2867 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2868 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2869 ~RS6000_BTI_unsigned_V2DI, 0 },
2870 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2871 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2872 ~RS6000_BTI_unsigned_long_long, 0 },
2873 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2874 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
2875
2876 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
2877 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
2878 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
2879 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
2880 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2881 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
2882 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2883 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
2884 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2885 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
2886 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
2887 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
2888 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2889 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
2890 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2891 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
2892 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2893 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
2894 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
2895 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
2896 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2897 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
2898 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2899 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
2900 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2901 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
2902 ~RS6000_BTI_unsigned_V16QI, 0 },
2903 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
2904 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
2905
2906 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
2907 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
2908 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
2909 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
2910 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
2911 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
2912 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
2913 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
2914 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2915 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
2916 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2917 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
2918 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2919 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2920 ~RS6000_BTI_unsigned_V2DI, 0 },
2921 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
2922 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2923 ~RS6000_BTI_unsigned_long_long, 0 },
2924 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
2925 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
2926 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
2927 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
2928 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2929 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
2930 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2931 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
2932 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2933 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
2934 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
2935 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
2936 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2937 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
2938 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2939 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
2940 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2941 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
2942 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
2943 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
2944 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2945 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
2946 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2947 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
2948 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2949 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
2950 ~RS6000_BTI_unsigned_V16QI, 0 },
2951 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
2952 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4559be23
PB		 2953
2954 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF,
25ffd3d3 2955 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4559be23 2956 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2957 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
4559be23 2958 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF,
25ffd3d3 2959 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
4559be23 2960 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF,
25ffd3d3 2961 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4559be23 2962 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2963 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
4559be23 2964 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF,
25ffd3d3 2965 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
4559be23 2966 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2967 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 2968 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2969 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2970 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
25ffd3d3 2971 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 2972 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2973 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 2974 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2975 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2976 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2977 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4559be23 2978 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
25ffd3d3 2979 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 2980 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2981 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2982 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2983 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 2984 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2985 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2986 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
25ffd3d3 2987 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 2988 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2989 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 2990 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2991 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 2992 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
25ffd3d3 2993 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4559be23 2994 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 2995 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 2996 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
25ffd3d3 2997 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 2998 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
25ffd3d3 2999 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 3000 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
25ffd3d3 3001 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 3002 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 3003 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23 3004 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 3005 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 3006 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
25ffd3d3 3007 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
4559be23
PB		 3008
3009 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
25ffd3d3 3010 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23
PB		 3011 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
3012 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3013 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
25ffd3d3 3014 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23
PB		 3015 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3016 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3017 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3018 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3019 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3020 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
3021 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3022 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3023 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
25ffd3d3 3024 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 3025 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
25ffd3d3
PB		 3026 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3027
3028 /* Ternary AltiVec/VSX builtins. */
3029 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3030 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3031 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3032 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3033 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3034 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3035 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3036 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3037 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3038 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3039 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3040 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3041 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3042 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3043 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3044 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3045 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3046 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3047 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3048 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3049 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3050 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3051 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3052 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3053 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3054 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3055 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3056 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3057 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3058 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3059 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3060 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3061 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3062 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3063 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3064 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3065 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3066 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3067 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3068 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3069 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3070 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3071 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3072 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3073 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3074 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3075 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3076 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3077 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3078 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3079 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3080 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3081 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3082 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3083 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3084 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3085 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3086 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3087 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3088 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3089 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3090 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3091 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3092 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3093 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3094 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3095 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3096 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3097 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3098 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3099 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3100 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3101 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3102 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3103 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3104 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3105 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3106 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3107 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3108 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3109 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3110 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3111 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3112 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3113 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3114 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3115 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3116 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3117 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3118 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3119 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3120 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3121 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3122 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3123 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3124 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3125 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3126 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3127 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3128 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3129 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3130 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3131 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3132 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3133 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3134 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3135 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3136 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3137 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3138 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3139 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3140 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3141 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3142 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3143 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3144 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3145 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3146 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3147 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3148 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3149 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3150 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3151 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3152 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3153 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3154 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3155 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3156 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3157 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3158 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3159 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3160 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3161 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3162 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3163 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3164 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3165 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3166 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3167 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3168 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3169 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3170 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3171 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3172 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3173 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3174 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3175 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3176 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3177 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3178 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3179 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3180 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3181 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3182 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3183 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3184 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3185 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3186 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3187 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3188 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3189 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3190 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3191 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3192 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3193 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3194 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3195 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3196 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3197 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3198 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3199 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3200 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3201 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3202 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3203 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3204 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3205 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3206 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3207 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3208 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3209 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3210 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3211 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3212 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3213 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3214 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3215 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3216 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3217 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3218 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3219 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3220 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3221 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3222 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3223 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3224 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
c1a57681
WS		 3225
3226 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM,
3227 RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V1TI },
3228 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM,
3229 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI },
3230
25ffd3d3
PB		 3231 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3232 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3233 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3234 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3235 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3236 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3237 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3238 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3239 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3240 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3241 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3242 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3243 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3244 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3245 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3246 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3247 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3248 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3249 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3250 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3251 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3252 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3253 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3254 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3255 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3256 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3257 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3258 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3259 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3260 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3261 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3262 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3263 RS6000_BTI_unsigned_V16QI },
3264 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3265 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3266 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3267 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3268 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3269 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3270 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3271 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3272 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3273 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3274 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3275 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3276 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3277 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3278 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3279 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3280 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3281 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3282 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3283 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3284 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3285 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3286 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3287 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3288 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3289 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3290
3291 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3292 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
3293 RS6000_BTI_bool_V16QI },
3294 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3295 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3296 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3297 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3298 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3299
3300 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3301 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3302 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3303 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3304 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3305 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3306 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3307 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3308 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3309 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3310 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3311 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3312 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3313 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3314 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3315 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3316 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3317 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3318 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3319 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3320 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3321 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3322 RS6000_BTI_bool_V2DI },
3323 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3324 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3325 RS6000_BTI_unsigned_V2DI },
3326 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3327 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3328 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3329 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3330 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3331 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3332 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3333 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3334 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3335 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3336 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3337 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3338 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3339 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3340 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3341 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3342 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3343 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3344 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3345 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3346 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3347 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3348 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3349 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3350 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3351 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3352 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3353 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3354 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3355 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3356 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3357 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3358 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3359 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3360 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3361 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3362 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3363 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3364 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3365 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3366 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3367 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3368 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3369 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3370 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3371 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3372 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3373 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3374 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3375 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI },
3376 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3377 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3378 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3379 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3380 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3381 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3382 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3383 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI },
3384 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3385 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI },
3386 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3387 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3388 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3389 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3390 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3391 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI },
3392 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3393 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3394 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3395 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI },
3396 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3397 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3398 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3399 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3400
3401 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3402 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3403 RS6000_BTI_INTSI },
3404 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3405 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3406 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3407 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3408 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3409 RS6000_BTI_INTSI },
3410 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3411 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3412 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3413 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3414 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3415 RS6000_BTI_INTSI },
3416 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3417 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3418 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3419 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3420 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3421 RS6000_BTI_INTSI },
3422 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3423 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3424 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3425
3426 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3427 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3428 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3429 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3430 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3431 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3432 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3433 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
3434 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3435 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3436 ~RS6000_BTI_unsigned_V2DI },
3437 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3438 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3439 ~RS6000_BTI_unsigned_long_long },
3440 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3441 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3442 ~RS6000_BTI_bool_V2DI },
3443 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3444 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3445 ~RS6000_BTI_long_long },
3446 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3447 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3448 ~RS6000_BTI_unsigned_long_long },
3449 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3450 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3451 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3452 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3453 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3454 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3455 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3456 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3457 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3458 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3459 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3460 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3461 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3462 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3463 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3464 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3465 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3466 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3467 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3468 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3469 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3470 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3471 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3472 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3473 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3474 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3475 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3476 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3477 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3478 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3479 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3480 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3481 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3482 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3483 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3484 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3485 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3486 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3487 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3488 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3489 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3490 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3491 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3492 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3493 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3494 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3495 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3496 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3497 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3498 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3499 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3500 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3501 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3502 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3503 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3504 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3505 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3506 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3507 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3508 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3509 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3510 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3511 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3512 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3513 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3514 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3515 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3516 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3517 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3518 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3519 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3520 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3521 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3522 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3523 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3524 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3525 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3526 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3527 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3528 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3529 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3530 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3531 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3532 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3533 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3534 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3535 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3536 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3537 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3538 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3539 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3540 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3541 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3542 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3543 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3544 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3545 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3546 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3547 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3548 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3549 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3550 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3551 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3552 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3553 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3554 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3555 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3556 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3557 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3558 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3559 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3560 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3561 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3562 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3563 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3564 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3565 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3566 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3567 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3568 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3569 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3570 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3571 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3572 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3573 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3574 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3575 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3576 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3577 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3578 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3579 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3580 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3581 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3582 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3583 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3584 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3585 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3586 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3587 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3588 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3589 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3590 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3591 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3592 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3593 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3594 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3595 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3596 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3597 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3598 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3599 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3600 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3601 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3602 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3603 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3604 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3605 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3606 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3607 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3608 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3609 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3610 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3611 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3612 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3613 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3614 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3615 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3616 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3617 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3618 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3619 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3620 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3621 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3622 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3623 ~RS6000_BTI_unsigned_V2DI },
3624 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3625 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3626 ~RS6000_BTI_bool_V2DI },
3627 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3628 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3629 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3630 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3631 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3632 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3633 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3634 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3635 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3636 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3637 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3638 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3639 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3640 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3641 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3642 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3643 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3644 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3645 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3646 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3647 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3648 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3649 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3650 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3651 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3652 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3653 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3654 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3655 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3656 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3657 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3658 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3659 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3660 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3661 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3662 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3663 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3664 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3665 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3666 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3667 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3668 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3669 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3670 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3671 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3672 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3673 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3674 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3675 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3676 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3677 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3678 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3679 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3680 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3681 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3682 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3683 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3684 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3685 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3686 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3687 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3688 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3689 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3690 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3691 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3692 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3693 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3694 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3695 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3696 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3697 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3698 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3699 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3700 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3701 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3702 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3703 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3704 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3705 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3706 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3707 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3708 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3709 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3710 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3711 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3712 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3713 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3714 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3715 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3716 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3717 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3718 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3719 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3720 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3721 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3722 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3723 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3724 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3725 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3726 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3727 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3728 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3729 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3730 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3731 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3732 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3733 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3734 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3735 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3736 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3737 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3738 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3739 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3740 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3741 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3742 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3743 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3744 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3745 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3746 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3747 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3748 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3749 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3750 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3751 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3752 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3753 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3754 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3755 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3756 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3757 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3758 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3759 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3760 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3761 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3762 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3763 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3764 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3765 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3766 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3767 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3768 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3769 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3770 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3771 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3772 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3773 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3774 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3775 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3776 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3777 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3778 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
3779 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void,
3780 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long },
3781 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3782 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3783 ~RS6000_BTI_unsigned_V2DI },
3784 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3785 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3786 ~RS6000_BTI_bool_V2DI },
3787 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
3788 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3789 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
3790 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3791 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3792 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3793 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3794 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3795 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3796 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3797 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3798 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3799 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3800 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3801 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3802 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3803 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3804 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3805 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3806 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3807 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3808 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3809 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3810 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3811 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3812 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3813 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3814 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3815 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3816 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3817 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3818 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3819 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3820 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3821 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3822 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3823 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3824 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3825 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3826 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3827 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3828 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3829 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3830 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3831 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3832 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3833 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3834 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3835 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
3836 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3837 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
3838 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3839 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
3840 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI },
3841 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
3842 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI },
3843 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3844 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3845 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3846 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
3847 ~RS6000_BTI_long_long },
3848 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3849 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3850 ~RS6000_BTI_unsigned_V2DI },
3851 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3852 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3853 ~RS6000_BTI_unsigned_long_long },
3854 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3855 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3856 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3857 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3858 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3859 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3860 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3861 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3862 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3863 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3864 ~RS6000_BTI_unsigned_V4SI },
3865 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3866 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3867 ~RS6000_BTI_UINTSI },
3868 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3869 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3870 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3871 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3872 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3873 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3874 ~RS6000_BTI_unsigned_V8HI },
3875 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3876 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3877 ~RS6000_BTI_UINTHI },
3878 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3879 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3880 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3881 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3882 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3883 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3884 ~RS6000_BTI_unsigned_V16QI },
3885 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3886 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3887 ~RS6000_BTI_UINTQI },
3888 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3889 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3890 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3891 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3892 RS6000_BTI_INTSI },
3893 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3894 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3895 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3896 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3897 RS6000_BTI_INTSI },
3898 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3899 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3900 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3901 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3902 RS6000_BTI_INTSI },
3903 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3904 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3905 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3906 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3907 RS6000_BTI_INTSI },
3908 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
3909 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3910 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
3911 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3912
3913 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
3914 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3915 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3916 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3917 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3918 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3919 RS6000_BTI_INTSI },
3920 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
3921 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3922 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3923 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3924 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3925 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3926 RS6000_BTI_INTSI },
3927 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3928 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3929 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3930 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3931 RS6000_BTI_INTSI },
3932 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3933 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3934 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3935 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3936 RS6000_BTI_INTSI },
3937
3938 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3939 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3940 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3941 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3942 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3943 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3944 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3945 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3946 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3947 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3948 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3949 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3950 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3951 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3952 ~RS6000_BTI_unsigned_V2DI, 0 },
3953 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3954 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
3955 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3956 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
3957 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3958 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3959 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3960 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3961 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3962 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
3963 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3964 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3965 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3966 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3967 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3968 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
3969 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3970 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3971 ~RS6000_BTI_unsigned_V4SI, 0 },
3972 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3973 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3974 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3975 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3976 ~RS6000_BTI_unsigned_long, 0 },
3977 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3978 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
3979 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3980 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
3981 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3982 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3983 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3984 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3985 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3986 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3987 ~RS6000_BTI_unsigned_V8HI, 0 },
3988 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3989 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3990 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3991 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
3992 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3993 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3994 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3995 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3996 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3997 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3998 ~RS6000_BTI_unsigned_V16QI, 0 },
3999 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4000 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4001
4002 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4003 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4004 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4005 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4006 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4007 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI,
4008 ~RS6000_BTI_long_long },
4009 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4010 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI,
4011 ~RS6000_BTI_unsigned_long_long },
4012 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4013 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI },
4014 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4015 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI },
4016 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4017 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4018 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4019 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4020 ~RS6000_BTI_unsigned_V2DI },
4021 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4022 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4023 ~RS6000_BTI_bool_V2DI },
4024 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4025 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4026 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4027 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4028 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4029 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4030 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4031 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4032 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4033 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4034 ~RS6000_BTI_unsigned_V4SI },
4035 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4036 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4037 ~RS6000_BTI_UINTSI },
4038 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4039 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4040 ~RS6000_BTI_bool_V4SI },
4041 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4042 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4043 ~RS6000_BTI_UINTSI },
4044 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4045 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4046 ~RS6000_BTI_INTSI },
4047 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4048 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4049 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4050 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4051 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4052 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4053 ~RS6000_BTI_unsigned_V8HI },
4054 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4055 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4056 ~RS6000_BTI_UINTHI },
4057 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4058 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4059 ~RS6000_BTI_bool_V8HI },
4060 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4061 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4062 ~RS6000_BTI_UINTHI },
4063 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4064 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4065 ~RS6000_BTI_INTHI },
4066 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4067 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4068 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4069 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4070 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4071 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4072 ~RS6000_BTI_unsigned_V16QI },
4073 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4074 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4075 ~RS6000_BTI_UINTQI },
4076 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4077 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4078 ~RS6000_BTI_bool_V16QI },
4079 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4080 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4081 ~RS6000_BTI_UINTQI },
4082 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4083 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4084 ~RS6000_BTI_INTQI },
4085 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4086 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
4087 ~RS6000_BTI_pixel_V8HI },
4088
4089 /* Predicates. */
4090 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4091 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4092 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4093 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4094 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4095 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4096 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4097 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4098 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4099 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4100 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4101 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4102 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4103 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4104 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4105 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4106 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4107 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4108 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4109 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4110 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4111 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4112 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4113 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4114 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4115 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4116 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4117 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4118 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4119 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4120 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4121 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4122 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4123 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4124 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4125 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4126 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4127 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4128 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4129 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4130 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4131 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4132 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4133 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4134 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4135 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4136 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4137 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4138 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
4139 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4140 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
4141 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4142
4143
4144 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4145 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4146 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4147 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4148 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4149 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4150 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4151 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4152 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4153 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4154 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4155 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4156 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4157 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4158 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4159 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4160 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4161 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4162 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4163 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4164 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4165 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4166 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4167 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4168 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4169 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4170 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4171 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4172 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4173 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4174 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4175 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4176 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4177 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4178 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4179 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4180 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4181 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4182 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4183 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4184 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4185 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4186 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4187 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4188 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4189 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4190 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4191 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4192 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4193 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4194 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4195 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4196 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4197 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4198 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4199 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4200 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4201 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4202 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4203 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4204 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4205 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4206
4207
4208 /* cmpge is the same as cmpgt for all cases except floating point.
4209 There is further code to deal with this special case in
4210 altivec_build_resolved_builtin. */
4211 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4212 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4213 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4214 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4215 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4216 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4217 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4218 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4219 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4220 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4221 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4222 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4223 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4224 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4225 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4226 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4227 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4228 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4229 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4230 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4231 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4232 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4233 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4234 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4235 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4236 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4237 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4238 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4239 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4240 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4241 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4242 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4243 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4244 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4245 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4246 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4247 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4248 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4249 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4250 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4251 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4252 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4253 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4254 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4255 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4256 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4257 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4258 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4259 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4260 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4261 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4262 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4263
4264 /* Power8 vector overloaded functions. */
4265 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4266 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4267 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4268 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4269 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4270 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 4271 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3 4272 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4559be23 4273 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3
PB		 4274 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4275 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4276 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3
PB		 4277 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4278 RS6000_BTI_bool_V16QI, 0 },
4559be23 4279 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
25ffd3d3
PB		 4280 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4281 RS6000_BTI_unsigned_V16QI, 0 },
4282 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4283 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4284 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4285 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4286 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4287 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 4288 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3 4289 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4559be23 4290 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3
PB		 4291 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4292 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4293 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3
PB		 4294 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4295 RS6000_BTI_bool_V8HI, 0 },
4559be23 4296 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
25ffd3d3
PB		 4297 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4298 RS6000_BTI_unsigned_V8HI, 0 },
4299 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4300 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4301 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4302 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4303 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4304 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 4305 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3 4306 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4559be23 4307 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3
PB		 4308 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4309 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4310 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3
PB		 4311 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4312 RS6000_BTI_bool_V4SI, 0 },
4559be23 4313 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
25ffd3d3
PB		 4314 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4315 RS6000_BTI_unsigned_V4SI, 0 },
4316 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4317 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4318 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4319 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4320 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4321 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 4322 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3 4323 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4559be23 4324 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3
PB		 4325 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4326 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4327 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3
PB		 4328 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4329 RS6000_BTI_bool_V2DI, 0 },
4559be23 4330 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
25ffd3d3
PB		 4331 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4332 RS6000_BTI_unsigned_V2DI, 0 },
4333 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4334 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4335 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4336 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4337
4338 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4339 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4340 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4341 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4342 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4343 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 4344 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4345 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4346 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4347 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4348 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4349 RS6000_BTI_bool_V16QI, 0 },
4559be23 4350 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4351 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4352 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4353 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
25ffd3d3
PB		 4354 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4355 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4356 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4357 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4358 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4359 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4360 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 4361 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4362 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4363 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4364 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4365 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4366 RS6000_BTI_bool_V8HI, 0 },
4559be23 4367 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4368 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4369 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4370 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
25ffd3d3
PB		 4371 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4372 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4373 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4374 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4375 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4376 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4377 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 4378 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4379 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4380 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4381 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4382 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4383 RS6000_BTI_bool_V4SI, 0 },
4559be23 4384 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4385 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4386 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4387 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
25ffd3d3
PB		 4388 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4389 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4390 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4391 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4392 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4393 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4394 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 4395 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4396 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4397 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4398 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4399 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4400 RS6000_BTI_bool_V2DI, 0 },
4559be23 4401 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4402 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4403 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4404 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
25ffd3d3
PB		 4405 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4406 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4407 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4408 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4409 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4410
4411 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4412 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4413 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4414 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4415 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4416 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4559be23 4417 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4418 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4419 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4420 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4421 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4422 RS6000_BTI_bool_V16QI, 0 },
4559be23 4423 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4424 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4425 RS6000_BTI_unsigned_V16QI, 0 },
4559be23 4426 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
25ffd3d3
PB		 4427 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4428 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4429 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4430 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4431 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4432 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4433 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4559be23 4434 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4435 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4436 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4437 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4438 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4439 RS6000_BTI_bool_V8HI, 0 },
4559be23 4440 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4441 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4442 RS6000_BTI_unsigned_V8HI, 0 },
4559be23 4443 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
25ffd3d3
PB		 4444 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4445 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4446 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4447 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4448 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4449 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4450 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4559be23 4451 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4452 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4453 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4454 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4455 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4456 RS6000_BTI_bool_V4SI, 0 },
4559be23 4457 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4458 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4459 RS6000_BTI_unsigned_V4SI, 0 },
4559be23 4460 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
25ffd3d3
PB		 4461 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4462 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4463 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4464 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4465 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4466 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4467 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4559be23 4468 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4469 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4470 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4471 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4472 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4473 RS6000_BTI_bool_V2DI, 0 },
4559be23 4474 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4475 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4476 RS6000_BTI_unsigned_V2DI, 0 },
4559be23 4477 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
25ffd3d3
PB		 4478 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4479 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4480 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4481 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4482 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4483
4484 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4485 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4486 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4487 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4488 RS6000_BTI_unsigned_V1TI, 0 },
4489
4490 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4491 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4492 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4493 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4494 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4495 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4496 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4497 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4498 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4499 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4500 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4501 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4502
4503 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4504 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4505 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4506 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4507 RS6000_BTI_unsigned_V1TI, 0 },
4508
4509 { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4510 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4511 RS6000_BTI_unsigned_V16QI, 0 },
4512 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4513 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4514 RS6000_BTI_unsigned_V16QI, 0 },
4515 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4516 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4517 RS6000_BTI_unsigned_V16QI, 0 },
4518
4519 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4520 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4521 RS6000_BTI_unsigned_V16QI, 0 },
4522 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4523 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4524 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4525 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4526 RS6000_BTI_unsigned_V16QI, 0 },
4527 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4528 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4529 RS6000_BTI_unsigned_V16QI, 0 },
4530
4531 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4532 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4533 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4534 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4535 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4536 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4537 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4538 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4539 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4540 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4541 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4542 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4543 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4544 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4545 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4546 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4547
4548 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4549 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4550 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4551 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4552
4553 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4554 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4555 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4556 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4557
4558 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4559 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4560 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4561 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4562
4563 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4564 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4565 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4566 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4567
4568 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4569 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4570 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4571 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4572
4573 { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4574 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4575 { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4576 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4577
4578 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4579 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4580 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4581 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4582
4583 { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4584 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4585 { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4586 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4587
4588 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4589 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4590 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4591 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4592
4593 { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4594 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4595 { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4596 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4597
4598 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4599 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4600 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4601 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4602
4603 { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4604 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4605 { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4606 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4607
4608 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4609 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4610 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4611 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4612 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4613 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4614 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4615 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4616 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4617 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4618 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4619 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4620 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4621 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4622 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4623 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4624
4625 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4626 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4627 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4628 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4629
4630 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4631 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4632 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4633 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4634
4635 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4636 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4637 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4638 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4639
4640 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4641 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4642 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4643 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4644
4645 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4646 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4647 RS6000_BTI_unsigned_V16QI, 0 },
4648 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4649 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4650 RS6000_BTI_unsigned_V8HI, 0 },
4651 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4652 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4653 RS6000_BTI_unsigned_V4SI, 0 },
4654
4655 { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4656 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4657 RS6000_BTI_unsigned_V16QI, 0 },
4658
4659 { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4660 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4661 RS6000_BTI_unsigned_V8HI, 0 },
4662
4663 { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
4664 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4665 RS6000_BTI_unsigned_V4SI, 0 },
4666
4667 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
4668 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4669 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
4670 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4671
4672 { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
4673 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4674 { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
4675 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4676
4677 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
4678 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4679 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
4680 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4681
4682 { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
4683 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4684 { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
4685 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4686
4687 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
4688 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4689 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
4690 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4691
4692 { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
4693 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4694 { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
4695 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4696
4697 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4698 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4699 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4700 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4701
4702 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4703 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4704 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4705 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4706
4707 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4708 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4709 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4710 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4711
4712 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4713 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4714 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4715 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4716
4717 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
4718 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4719 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
4720 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4721 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP,
4722 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4723
4724 { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
4725 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4726 { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
4727 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4728 { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP,
4729 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4730
4731 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
4732 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4733 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
4734 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4735 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP,
4736 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4737
4738 { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
4739 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4740 { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
4741 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4742 { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP,
4743 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4744
4745 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
4746 RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
4747 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP,
4748 RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 },
4749
4750 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
4751 RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
4752 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP,
4753 RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 },
4754
4755 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
4756 RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
4757 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
4758 RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
4759
4760 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP,
4761 RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 },
4762 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
4763 RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
4764
4765 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT,
4766 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4767 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT,
4768 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4769 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT,
4770 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4771 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT,
4772 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4773 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ,
4774 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4775 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ,
4776 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4777 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO,
4778 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4779 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO,
4780 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4781
4782 { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
4783 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4784 RS6000_BTI_unsigned_long_long, 0 },
4785
4786 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4787 RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4788 RS6000_BTI_unsigned_long_long, 0 },
4789 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4790 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4791 RS6000_BTI_unsigned_long_long, 0 },
4792
4793 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4794 RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4795 RS6000_BTI_unsigned_long_long, 0 },
4796 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4797 RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4798 RS6000_BTI_unsigned_long_long, 0 },
4799
4800 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4801 RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4802 RS6000_BTI_unsigned_long_long, 0 },
4803 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4804 RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4805 RS6000_BTI_unsigned_long_long, 0 },
4806
4807 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4808 RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4809 RS6000_BTI_unsigned_long_long, 0 },
4810 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4811 RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4812 RS6000_BTI_unsigned_long_long, 0 },
4813
4814 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4815 RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4816 RS6000_BTI_unsigned_long_long, 0 },
4817 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4818 RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4819 RS6000_BTI_unsigned_long_long, 0 },
4820
4821 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4822 RS6000_BTI_V2DF, ~RS6000_BTI_double,
4823 RS6000_BTI_unsigned_long_long, 0 },
4824 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4825 RS6000_BTI_V4SF, ~RS6000_BTI_float,
4826 RS6000_BTI_unsigned_long_long, 0 },
4827 /* At an appropriate future time, add support for the
4828 RS6000_BTI_Float16 (exact name to be determined) type here. */
4829
4830 { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,
4831 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,
4832 ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},
4833
4834 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4835 RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4836 RS6000_BTI_unsigned_long_long },
4837 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4838 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4839 RS6000_BTI_unsigned_long_long },
4840
4841 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4842 RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4843 RS6000_BTI_unsigned_long_long },
4844 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4845 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4846 RS6000_BTI_unsigned_long_long },
4847
4848 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4849 RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4850 RS6000_BTI_unsigned_long_long },
4851 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4852 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4853 RS6000_BTI_unsigned_long_long },
4854
4855 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4856 RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4857 RS6000_BTI_unsigned_long_long },
4858 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4859 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4860 RS6000_BTI_unsigned_long_long },
4861
4862 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4863 RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4864 RS6000_BTI_unsigned_long_long },
4865 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4866 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4867 RS6000_BTI_unsigned_long_long },
4868
4869 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4870 RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
4871 RS6000_BTI_unsigned_long_long },
4872 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4873 RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
4874 RS6000_BTI_unsigned_long_long },
4875 /* At an appropriate future time, add support for the
4876 RS6000_BTI_Float16 (exact name to be determined) type here. */
4877
4878 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4879 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
4880 RS6000_BTI_bool_V16QI, 0 },
4881 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4882 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4883 RS6000_BTI_V16QI, 0 },
4884 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4885 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
4886 RS6000_BTI_unsigned_V16QI, 0 },
4887
4888 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4889 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
4890 RS6000_BTI_bool_V8HI, 0 },
4891 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4892 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
4893 RS6000_BTI_V8HI, 0 },
4894 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4895 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
4896 RS6000_BTI_unsigned_V8HI, 0 },
4897
4898 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4899 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
4900 RS6000_BTI_bool_V4SI, 0 },
4901 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4902 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
4903 RS6000_BTI_V4SI, 0 },
4904 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4905 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
4906 RS6000_BTI_unsigned_V4SI, 0 },
4907
4908 /* The following 2 entries have been deprecated. */
4909 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4910 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4911 RS6000_BTI_unsigned_V16QI, 0 },
4912 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4913 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4914 RS6000_BTI_bool_V16QI, 0 },
4915 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4916 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4917 RS6000_BTI_unsigned_V16QI, 0 },
4918
4919 /* The following 2 entries have been deprecated. */
4920 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4921 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4922 RS6000_BTI_V16QI, 0 },
4923 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4924 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4925 RS6000_BTI_bool_V16QI, 0 },
4926 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4927 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4928 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4929 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4930 RS6000_BTI_bool_V16QI, 0 },
4931
4932 /* The following 2 entries have been deprecated. */
4933 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4934 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4935 RS6000_BTI_unsigned_V8HI, 0 },
4936 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4937 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4938 RS6000_BTI_bool_V8HI, 0 },
4939 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4940 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4941 RS6000_BTI_unsigned_V8HI, 0 },
4942 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4943 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4944
4945 /* The following 2 entries have been deprecated. */
4946 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4947 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4948 RS6000_BTI_V8HI, 0 },
4949 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4950 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4951 RS6000_BTI_bool_V8HI, 0 },
4952 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4953 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4954 RS6000_BTI_bool_V8HI, 0 },
4955 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4956 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4957 RS6000_BTI_pixel_V8HI, 0 },
4958
4959 /* The following 2 entries have been deprecated. */
4960 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4961 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4962 RS6000_BTI_unsigned_V4SI, 0 },
4963 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4964 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4965 RS6000_BTI_bool_V4SI, 0 },
4966 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4967 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4968 RS6000_BTI_unsigned_V4SI, 0 },
4969
4970 /* The following 2 entries have been deprecated. */
4971 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4972 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4973 RS6000_BTI_V4SI, 0 },
4974 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4975 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4976 RS6000_BTI_bool_V4SI, 0 },
4977 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4978 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4979 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4980 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4981 RS6000_BTI_bool_V4SI, 0 },
4982
4983 /* The following 2 entries have been deprecated. */
4984 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4985 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4986 RS6000_BTI_unsigned_V2DI, 0 },
4987 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4988 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4989 RS6000_BTI_bool_V2DI, 0 },
4990 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4991 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4992 RS6000_BTI_unsigned_V2DI, 0
4993 },
4994
4995 /* The following 2 entries have been deprecated. */
4996 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4997 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4998 RS6000_BTI_V2DI, 0 },
4999 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5000 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5001 RS6000_BTI_bool_V2DI, 0 },
5002 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5003 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5004 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5005 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5006 RS6000_BTI_bool_V2DI, 0 },
5007
5008 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
5009 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5010 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
5011 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5012
5013 /* The following 2 entries have been deprecated. */
5014 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5015 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5016 RS6000_BTI_unsigned_V16QI, 0 },
5017 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5018 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5019 RS6000_BTI_bool_V16QI, 0 },
5020 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5021 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5022 RS6000_BTI_unsigned_V16QI, 0 },
5023
5024 /* The following 2 entries have been deprecated. */
5025 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5026 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5027 RS6000_BTI_V16QI, 0 },
5028 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5029 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5030 RS6000_BTI_bool_V16QI, 0 },
5031 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5032 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5033 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5034 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5035 RS6000_BTI_bool_V16QI, 0 },
5036
5037 /* The following 2 entries have been deprecated. */
5038 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5039 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5040 RS6000_BTI_unsigned_V8HI, 0 },
5041 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5042 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5043 RS6000_BTI_bool_V8HI, 0 },
5044 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5045 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5046 RS6000_BTI_unsigned_V8HI, 0 },
5047 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5048 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5049
5050 /* The following 2 entries have been deprecated. */
5051 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5052 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5053 RS6000_BTI_V8HI, 0 },
5054 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5055 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5056 RS6000_BTI_bool_V8HI, 0 },
5057 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5058 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5059 RS6000_BTI_bool_V8HI, 0 },
5060 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5061 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5062 RS6000_BTI_pixel_V8HI, 0 },
5063
5064 /* The following 2 entries have been deprecated. */
5065 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5066 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5067 RS6000_BTI_unsigned_V4SI, 0 },
5068 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5069 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5070 RS6000_BTI_bool_V4SI, 0 },
5071 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5072 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5073 RS6000_BTI_unsigned_V4SI, 0 },
5074
5075 /* The following 2 entries have been deprecated. */
5076 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5077 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5078 RS6000_BTI_V4SI, 0 },
5079 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5080 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5081 RS6000_BTI_bool_V4SI, 0 },
5082 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5083 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5084 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5085 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5086 RS6000_BTI_bool_V4SI, 0 },
5087
5088 /* The following 2 entries have been deprecated. */
5089 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5090 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5091 RS6000_BTI_unsigned_V2DI, 0 },
5092 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5093 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5094 RS6000_BTI_bool_V2DI, 0 },
5095 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5096 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5097 RS6000_BTI_unsigned_V2DI, 0
5098 },
5099
5100 /* The following 2 entries have been deprecated. */
5101 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5102 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5103 RS6000_BTI_V2DI, 0 },
5104 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5105 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5106 RS6000_BTI_bool_V2DI, 0 },
5107 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5108 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5109 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5110 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5111 RS6000_BTI_bool_V2DI, 0 },
5112
5113 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
5114 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5115 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
5116 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5117
5118 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5119 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5120 RS6000_BTI_unsigned_V16QI },
5121 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5122 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
5123
5124 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5125 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5126 RS6000_BTI_unsigned_V8HI },
5127 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5128 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
5129
5130 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5131 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5132 RS6000_BTI_unsigned_V4SI },
5133 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5134 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
5135
5136 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5137 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5138 RS6000_BTI_V16QI, 0 },
5139 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5140 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5141 RS6000_BTI_unsigned_V16QI, 0 },
5142
5143 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5144 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5145 RS6000_BTI_V8HI, 0 },
5146 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5147 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5148 RS6000_BTI_unsigned_V8HI, 0 },
5149
5150 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5151 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5152 RS6000_BTI_V4SI, 0 },
5153 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5154 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5155 RS6000_BTI_unsigned_V4SI, 0 },
5156
5157 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5158 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5159 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5160 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5161
5162 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5163 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5164 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5165 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5166 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI,
5167 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5168 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI,
5169 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 },
5170
5171 { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
5172 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
5173
5174 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5175 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5176 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5177 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5178
5179 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5180 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5181 RS6000_BTI_V16QI, 0 },
5182 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5183 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5184 RS6000_BTI_unsigned_V16QI, 0 },
5185
5186 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5187 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5188 RS6000_BTI_V8HI, 0 },
5189 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5190 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5191 RS6000_BTI_unsigned_V8HI, 0 },
5192
5193 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5194 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5195 RS6000_BTI_V4SI, 0 },
5196 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5197 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5198 RS6000_BTI_unsigned_V4SI, 0 },
5199 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5200 RS6000_BTI_float, RS6000_BTI_UINTSI,
5201 RS6000_BTI_V4SF, 0 },
5202
5203 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5204 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5205 RS6000_BTI_V16QI, 0 },
5206 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5207 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5208 RS6000_BTI_unsigned_V16QI, 0 },
5209
5210 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5211 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5212 RS6000_BTI_V8HI, 0 },
5213 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5214 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5215 RS6000_BTI_unsigned_V8HI, 0 },
5216
5217 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5218 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5219 RS6000_BTI_V4SI, 0 },
5220 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5221 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5222 RS6000_BTI_unsigned_V4SI, 0 },
5223 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5224 RS6000_BTI_float, RS6000_BTI_UINTSI,
5225 RS6000_BTI_V4SF, 0 },
5226
5227 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5228 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5229 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5230 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5231
5232 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5233 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI,
5234 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5235 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5236 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5237 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5238
5239 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5240 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5241 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5242 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5243 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5244
5245 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5246 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5247 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5248 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5249 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5250
5251 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5252 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5253 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5254 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5255 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5256
5257 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5258 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5259 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5260 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5261 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5262
5263 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5264 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5265 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5266 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5267 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5268 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5269
5270 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5271 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5272 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5273 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5274 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5275 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5276
5277 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5278 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5279 RS6000_BTI_unsigned_V2DI, 0 },
5280 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5281 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5282 RS6000_BTI_bool_V2DI, 0 },
5283 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5284 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5285 RS6000_BTI_unsigned_V2DI, 0 },
5286
5287 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5288 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5289 RS6000_BTI_unsigned_V2DI, 0 },
5290 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5291 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5292 RS6000_BTI_bool_V2DI, 0 },
5293 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5294 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5295 RS6000_BTI_unsigned_V2DI, 0 },
5296
5297 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5298 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5299 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5300 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5301 RS6000_BTI_unsigned_V2DI, 0 },
5302 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5303 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5304 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF,
5305 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5306 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF,
5307 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5308 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5309 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5310 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5311 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5312 RS6000_BTI_unsigned_V4SI, 0 },
5313 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5314 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5315
5316 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5317 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5318 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5319 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5320 RS6000_BTI_unsigned_V4SI, 0 },
5321 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5322 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5323 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5324 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5325 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5326 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5327 RS6000_BTI_unsigned_V2DI, 0 },
5328 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5329 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5330 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF,
5331 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5332 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF,
5333 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5334
5335 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5336 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5337 RS6000_BTI_unsigned_V16QI, 0 },
5338 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5339 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5340 RS6000_BTI_unsigned_V8HI, 0 },
5341 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5342 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5343 RS6000_BTI_unsigned_V4SI, 0 },
5344 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5345 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5346 RS6000_BTI_unsigned_V2DI, 0 },
5347
5348 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5349 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5350 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5351 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5352 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5353 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5354 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5355 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5356 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5357 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5358 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5359 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5360 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5361 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5362 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5363 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5364
5365 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5366 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5367 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5368 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5369
5370 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5371 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5372 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5373 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5374
5375 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5376 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5377 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5378 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5379
5380 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5381 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5382 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5383 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5384
5385 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5386 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5387 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5388 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5389
5390 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5391 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5392 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5393 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5394
5395 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5396 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5397 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5398 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5399
5400 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5401 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5402 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5403 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5404
5405 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5406 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5407 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5408 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5409 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5410 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5411 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5412 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5413 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5414 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5415 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5416 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5417 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5418 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5419 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5420 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5421
5422 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5423 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5424 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5425 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5426
5427 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5428 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5429 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5430 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5431
5432 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5433 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5434 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5435 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5436 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5437 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5438 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5439 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5440
5441 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5442 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5443 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5444 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5445 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5446 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5447 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5448 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5449 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5450 RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
5451 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5452 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5453
5454 { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5455 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5456 { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5457 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5458 { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5459 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5460
5461 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5462 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5463 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5464 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5465 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5466 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5467
5468 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5469 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5470
5471 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5472 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5473
5474 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5475 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5476
5477 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5478 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5479 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5480 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5481
5482 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5483 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5484 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5485 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5486
5487 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5488 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5489 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5490 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5491
5492 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5493 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5494 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5495 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5496
5497 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5498 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5499 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5500 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5501 RS6000_BTI_unsigned_V1TI, 0 },
5502
5503 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5504 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5505 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5506 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5507 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5508 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5509 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5510 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5511 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5512 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5513 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5514 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5515
5516 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5517 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5518 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5519 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5520 RS6000_BTI_unsigned_V1TI, 0 },
5521
5522 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5523 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5524 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5525 RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5526
5527 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5528 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5529 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5530 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5531
5532 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5533 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5534 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5535 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5536
5537 { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5538 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5539 RS6000_BTI_unsigned_V16QI, 0 },
5540 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5541 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5542 RS6000_BTI_unsigned_V16QI, 0 },
5543
5544 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5545 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5546 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5547 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5548 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5549 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5550 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5551 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5552 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5553 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5554 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5555 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5556 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5557 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5558 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5559 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5560 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5561 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5562 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5563 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5564 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5565 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5566 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5567 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5568 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5569 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5570 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5571 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5572 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF,
5573 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5574 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF,
5575 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5576
5577 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5578 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5579 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5580 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5581 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5582 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5583 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5584 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5585 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5586 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5587 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5588 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5589 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5590 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5591 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5592 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5593 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
5594 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5595 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
5596 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5597 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5598 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5599 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5600 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5601 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5602 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5603 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5604 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5605
5606 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF,
5607 RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 },
5608 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF,
5609 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5610 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5611 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5612 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5613 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5614 { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF,
5615 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5616
5617 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5618 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5619 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5620 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5621 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5622 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5623 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5624 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5625 { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF,
5626 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5627 RS6000_BTI_V2DF, 0 },
5628
5629 /* Crypto builtins. */
5630 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5631 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5632 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5633 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5634 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5635 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5636 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5637 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5638 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5639 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5640 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5641 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5642
5643 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5644 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5645 RS6000_BTI_unsigned_V16QI, 0 },
5646 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5647 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5648 RS6000_BTI_unsigned_V8HI, 0 },
5649 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5650 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5651 RS6000_BTI_unsigned_V4SI, 0 },
5652 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5653 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5654 RS6000_BTI_unsigned_V2DI, 0 },
5655
5656 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5657 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5658 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5659 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5660 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5661 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5662
5d9d0c94 5663 /* Overloaded built-in functions for ISA3.1 (power10). */
07d456bb 5664 { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
25bf7d32 5665 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
07d456bb 5666 { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
25bf7d32
KN		 5667 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5668 RS6000_BTI_UINTSI, 0 },
07d456bb 5669 { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
25bf7d32 5670 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
07d456bb 5671 { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
25bf7d32
KN		 5672 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5673 RS6000_BTI_UINTSI, 0 },
5674
07d456bb 5675 { P10_BUILTIN_VEC_GNB, P10V_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
7c00c559 5676 RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTQI, 0 },
07d456bb 5677 { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V2DI,
b8eaa754 5678 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
07d456bb 5679 { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V4SI,
b8eaa754 5680 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
07d456bb 5681 { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V8HI,
b8eaa754 5682 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
07d456bb 5683 { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V16QI,
b8eaa754
CL		 5684 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5685 RS6000_BTI_INTSI, 0 },
840ac85c
KN		 5686
5687 /* The overloaded XXEVAL definitions are handled specially because the
5688 fourth unsigned char operand is not encoded in this table. */
07d456bb 5689 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
840ac85c
KN		 5690 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5691 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
07d456bb 5692 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
840ac85c
KN		 5693 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5694 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
07d456bb 5695 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
840ac85c
KN		 5696 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5697 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
07d456bb 5698 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
840ac85c
KN		 5699 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5700 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
07d456bb 5701 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
840ac85c
KN		 5702 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5703 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5704
5998f1bb
CL		 5705 /* The overloaded XXPERMX definitions are handled specially because the
5706 fourth unsigned char operand is not encoded in this table. */
07d456bb 5707 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5708 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
5709 RS6000_BTI_unsigned_V16QI },
07d456bb 5710 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5711 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5712 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
07d456bb 5713 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5714 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
5715 RS6000_BTI_unsigned_V16QI },
07d456bb 5716 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5717 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5718 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
07d456bb 5719 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5720 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
5721 RS6000_BTI_unsigned_V16QI },
07d456bb 5722 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5723 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5724 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
07d456bb 5725 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5726 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
5727 RS6000_BTI_unsigned_V16QI },
07d456bb 5728 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5729 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5730 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
07d456bb 5731 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5732 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
5733 RS6000_BTI_unsigned_V16QI },
07d456bb 5734 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5998f1bb
CL		 5735 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
5736 RS6000_BTI_unsigned_V16QI },
5737
07d456bb 5738 { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTBL,
c21d2b66
KN		 5739 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
5740 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
07d456bb 5741 { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTHL,
c21d2b66
KN		 5742 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
5743 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
07d456bb 5744 { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTWL,
c21d2b66
KN		 5745 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5746 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
07d456bb 5747 { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTDL,
c21d2b66
KN		 5748 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5749 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
5750
07d456bb 5751 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRBL,
530e9095
CL		 5752 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
5753 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
07d456bb 5754 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRHL,
530e9095
CL		 5755 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
5756 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
07d456bb 5757 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRWL,
530e9095
CL		 5758 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
5759 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
07d456bb 5760 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRDL,
530e9095
CL		 5761 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
5762 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
07d456bb 5763 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRBL,
530e9095
CL		 5764 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5765 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
07d456bb 5766 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRHL,
530e9095
CL		 5767 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5768 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
07d456bb 5769 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRWL,
530e9095
CL		 5770 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5771 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
5772
07d456bb 5773 { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTBR,
c21d2b66
KN		 5774 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
5775 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
07d456bb 5776 { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTHR,
c21d2b66
KN		 5777 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
5778 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
07d456bb 5779 { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTWR,
c21d2b66
KN		 5780 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5781 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
07d456bb 5782 { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTDR,
c21d2b66
KN		 5783 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5784 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
5785
07d456bb 5786 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRBR,
530e9095
CL		 5787 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
5788 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
07d456bb 5789 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRHR,
530e9095
CL		 5790 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
5791 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
07d456bb 5792 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRWR,
530e9095
CL		 5793 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
5794 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
07d456bb 5795 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRDR,
530e9095
CL		 5796 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
5797 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
07d456bb 5798 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRBR,
530e9095
CL		 5799 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5800 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
07d456bb 5801 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRHR,
530e9095
CL		 5802 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5803 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
07d456bb 5804 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRWR,
530e9095
CL		 5805 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5806 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
5807
07d456bb 5808 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV4SI,
3f029aea
CL		 5809 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5810 RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
07d456bb 5811 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SI,
3f029aea 5812 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
07d456bb 5813 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SF,
3f029aea 5814 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
07d456bb 5815 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV2DI,
3f029aea
CL		 5816 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5817 RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
07d456bb 5818 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DI,
3f029aea 5819 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
07d456bb 5820 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DF,
3f029aea
CL		 5821 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
5822
07d456bb 5823 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV4SI,
3f029aea
CL		 5824 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5825 RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
07d456bb 5826 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SI,
3f029aea 5827 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
07d456bb 5828 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SF,
3f029aea 5829 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
07d456bb 5830 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV2DI,
3f029aea
CL		 5831 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5832 RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
07d456bb 5833 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DI,
3f029aea 5834 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
07d456bb 5835 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DF,
3f029aea
CL		 5836 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
5837
07d456bb 5838 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
82f10dee
CL		 5839 RS6000_BTI_V16QI, RS6000_BTI_V16QI,
5840 RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
07d456bb 5841 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
82f10dee
CL		 5842 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5843 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
07d456bb 5844 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
82f10dee
CL		 5845 RS6000_BTI_V8HI, RS6000_BTI_V8HI,
5846 RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
07d456bb 5847 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
82f10dee
CL		 5848 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5849 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
07d456bb 5850 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
82f10dee
CL		 5851 RS6000_BTI_V4SI, RS6000_BTI_V4SI,
5852 RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
07d456bb 5853 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
82f10dee
CL		 5854 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5855 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
07d456bb 5856 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
82f10dee
CL		 5857 RS6000_BTI_V2DI, RS6000_BTI_V2DI,
5858 RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
07d456bb 5859 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
82f10dee
CL		 5860 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5861 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
5862
07d456bb 5863 { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SI,
7f3b1997 5864 RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0, 0 },
07d456bb 5865 { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SF,
7f3b1997
CL		 5866 RS6000_BTI_V4SF, RS6000_BTI_float, 0, 0 },
5867
07d456bb 5868 { P10_BUILTIN_VEC_XXSPLTID, P10V_BUILTIN_VXXSPLTID,
7f3b1997
CL		 5869 RS6000_BTI_V2DF, RS6000_BTI_float, 0, 0 },
5870
07d456bb 5871 { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
7f3b1997 5872 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_UINTQI, RS6000_BTI_INTSI },
07d456bb 5873 { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
7f3b1997
CL		 5874 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI,
5875 RS6000_BTI_UINTSI },
07d456bb 5876 { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SF,
7f3b1997
CL		 5877 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_UINTQI, RS6000_BTI_float },
5878
07d456bb 5879 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
5998f1bb
CL		 5880 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
5881 RS6000_BTI_unsigned_V16QI },
07d456bb 5882 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
5998f1bb
CL		 5883 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5884 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
07d456bb 5885 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
5998f1bb
CL		 5886 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
5887 RS6000_BTI_unsigned_V8HI },
07d456bb 5888 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
5998f1bb
CL		 5889 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5890 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
07d456bb 5891 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
5998f1bb
CL		 5892 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
5893 RS6000_BTI_unsigned_V4SI },
07d456bb 5894 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
5998f1bb
CL		 5895 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5896 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
07d456bb 5897 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
5998f1bb
CL		 5898 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
5899 RS6000_BTI_unsigned_V2DI },
07d456bb 5900 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
5998f1bb
CL		 5901 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5902 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
07d456bb 5903 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SF,
5998f1bb
CL		 5904 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
5905 RS6000_BTI_unsigned_V4SI },
07d456bb 5906 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DF,
5998f1bb
CL		 5907 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
5908 RS6000_BTI_unsigned_V2DI },
5909
07d456bb 5910 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
82f10dee
CL		 5911 RS6000_BTI_V16QI, RS6000_BTI_V16QI,
5912 RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
07d456bb 5913 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
82f10dee
CL		 5914 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5915 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
07d456bb 5916 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
82f10dee
CL		 5917 RS6000_BTI_V8HI, RS6000_BTI_V8HI,
5918 RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
07d456bb 5919 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
82f10dee
CL		 5920 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5921 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
07d456bb 5922 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
82f10dee
CL		 5923 RS6000_BTI_V4SI, RS6000_BTI_V4SI,
5924 RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
07d456bb 5925 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
82f10dee
CL		 5926 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5927 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
07d456bb 5928 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
82f10dee
CL		 5929 RS6000_BTI_V2DI, RS6000_BTI_V2DI,
5930 RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
07d456bb 5931 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
82f10dee
CL		 5932 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5933 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
5934
07d456bb 5935 { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
89ce3290 5936 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
07d456bb 5937 { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
89ce3290
KN		 5938 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5939
07d456bb 5940 { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
89ce3290 5941 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
07d456bb 5942 { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
89ce3290
KN		 5943 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5944
07d456bb 5945 { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
89ce3290 5946 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
07d456bb 5947 { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
89ce3290
KN		 5948 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5949
07d456bb 5950 { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
89ce3290 5951 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
07d456bb 5952 { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
89ce3290
KN		 5953 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5954
07d456bb 5955 { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
89ce3290 5956 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
07d456bb 5957 { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
89ce3290
KN		 5958 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5959
07d456bb 5960 { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
89ce3290 5961 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
07d456bb 5962 { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
89ce3290
KN		 5963 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5964
07d456bb 5965 { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
89ce3290 5966 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
07d456bb 5967 { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
89ce3290
KN		 5968 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5969
07d456bb 5970 { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
89ce3290 5971 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
07d456bb 5972 { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
89ce3290
KN		 5973 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5974
07d456bb 5975 { P10_BUILTIN_VEC_MTVSRBM, P10V_BUILTIN_MTVSRBM,
02ef74ba 5976 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, 0, 0 },
07d456bb 5977 { P10_BUILTIN_VEC_MTVSRHM, P10V_BUILTIN_MTVSRHM,
02ef74ba 5978 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTDI, 0, 0 },
07d456bb 5979 { P10_BUILTIN_VEC_MTVSRWM, P10V_BUILTIN_MTVSRWM,
02ef74ba 5980 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTDI, 0, 0 },
07d456bb 5981 { P10_BUILTIN_VEC_MTVSRDM, P10V_BUILTIN_MTVSRDM,
02ef74ba 5982 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, 0, 0 },
07d456bb 5983 { P10_BUILTIN_VEC_MTVSRQM, P10V_BUILTIN_MTVSRQM,
02ef74ba
CL		 5984 RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTDI, 0, 0 },
5985
07d456bb 5986 { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBB,
02ef74ba
CL		 5987 RS6000_BTI_unsigned_long_long,
5988 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 },
07d456bb 5989 { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBH,
02ef74ba
CL		 5990 RS6000_BTI_unsigned_long_long,
5991 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI, 0 },
07d456bb 5992 { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBW,
02ef74ba
CL		 5993 RS6000_BTI_unsigned_long_long,
5994 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI, 0 },
07d456bb 5995 { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBD,
02ef74ba
CL		 5996 RS6000_BTI_unsigned_long_long,
5997 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI, 0 },
5998
07d456bb 5999 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMB,
02ef74ba 6000 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
07d456bb 6001 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMH,
02ef74ba 6002 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
07d456bb 6003 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMW,
02ef74ba 6004 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
07d456bb 6005 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMD,
02ef74ba 6006 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
07d456bb 6007 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMQ,
02ef74ba
CL		 6008 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
6009
07d456bb 6010 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMB,
02ef74ba 6011 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
07d456bb 6012 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMH,
02ef74ba 6013 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
07d456bb 6014 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMW,
02ef74ba 6015 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 0, 0 },
07d456bb 6016 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMD,
02ef74ba 6017 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 0, 0 },
07d456bb 6018 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMQ,
02ef74ba
CL		 6019 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, 0, 0 },
6020
07d456bb 6021 { P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10V_BUILTIN_XVTLSBB_ZEROS,
cf5d0fc2 6022 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
07d456bb 6023 { P10_BUILTIN_VEC_XVTLSBB_ONES, P10V_BUILTIN_XVTLSBB_ONES,
cf5d0fc2
WS		 6024 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
6025
25ffd3d3
PB		 6026 { RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
6027};
1acf0246
BS		 6028\f
6029/* Nonzero if we can use a floating-point register to pass this arg. */
6030#define USE_FP_FOR_ARG_P(CUM,MODE) \
6031 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
6032 && (CUM)->fregno <= FP_ARG_MAX_REG \
6033 && TARGET_HARD_FLOAT)
6034
6035/* Nonzero if we can use an AltiVec register to pass this arg. */
6036#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
6037 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
6038 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
6039 && TARGET_ALTIVEC_ABI \
6040 && (NAMED))
6041
6042/* Walk down the type tree of TYPE counting consecutive base elements.
6043 If *MODEP is VOIDmode, then set it to the first valid floating point
6044 or vector type. If a non-floating point or vector type is found, or
6045 if a floating point or vector type that doesn't match a non-VOIDmode
6046 *MODEP is found, then return -1, otherwise return the count in the
6047 sub-tree. */
6048
6049static int
a39ed81b 6050rs6000_aggregate_candidate (const_tree type, machine_mode *modep,
575ac27f 6051 int *empty_base_seen)
1acf0246
BS		 6052{
6053 machine_mode mode;
6054 HOST_WIDE_INT size;
6055
6056 switch (TREE_CODE (type))
6057 {
6058 case REAL_TYPE:
6059 mode = TYPE_MODE (type);
6060 if (!SCALAR_FLOAT_MODE_P (mode))
6061 return -1;
6062
6063 if (*modep == VOIDmode)
6064 *modep = mode;
6065
6066 if (*modep == mode)
6067 return 1;
6068
6069 break;
6070
6071 case COMPLEX_TYPE:
6072 mode = TYPE_MODE (TREE_TYPE (type));
6073 if (!SCALAR_FLOAT_MODE_P (mode))
6074 return -1;
6075
6076 if (*modep == VOIDmode)
6077 *modep = mode;
6078
6079 if (*modep == mode)
6080 return 2;
6081
6082 break;
6083
6084 case VECTOR_TYPE:
6085 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
6086 return -1;
6087
6088 /* Use V4SImode as representative of all 128-bit vector types. */
6089 size = int_size_in_bytes (type);
6090 switch (size)
6091 {
6092 case 16:
6093 mode = V4SImode;
6094 break;
6095 default:
6096 return -1;
6097 }
6098
6099 if (*modep == VOIDmode)
6100 *modep = mode;
6101
6102 /* Vector modes are considered to be opaque: two vectors are
6103 equivalent for the purposes of being homogeneous aggregates
6104 if they are the same size. */
6105 if (*modep == mode)
6106 return 1;
6107
6108 break;
6109
6110 case ARRAY_TYPE:
6111 {
6112 int count;
6113 tree index = TYPE_DOMAIN (type);
6114
6115 /* Can't handle incomplete types nor sizes that are not
6116 fixed. */
6117 if (!COMPLETE_TYPE_P (type)
6118 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
6119 return -1;
6120
a39ed81b 6121 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep,
575ac27f 6122 empty_base_seen);
1acf0246
BS		 6123 if (count == -1
6124 || !index
6125 || !TYPE_MAX_VALUE (index)
6126 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
6127 || !TYPE_MIN_VALUE (index)
6128 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
6129 || count < 0)
6130 return -1;
6131
6132 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
6133 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
6134
6135 /* There must be no padding. */
6136 if (wi::to_wide (TYPE_SIZE (type))
6137 != count * GET_MODE_BITSIZE (*modep))
6138 return -1;
6139
6140 return count;
6141 }
6142
6143 case RECORD_TYPE:
6144 {
6145 int count = 0;
6146 int sub_count;
6147 tree field;
6148
6149 /* Can't handle incomplete types nor sizes that are not
6150 fixed. */
6151 if (!COMPLETE_TYPE_P (type)
6152 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
6153 return -1;
6154
6155 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6156 {
6157 if (TREE_CODE (field) != FIELD_DECL)
6158 continue;
6159
575ac27f 6160 if (DECL_FIELD_ABI_IGNORED (field))
a39ed81b 6161 {
575ac27f
JJ		 6162 if (lookup_attribute ("no_unique_address",
6163 DECL_ATTRIBUTES (field)))
6164 *empty_base_seen |= 2;
6165 else
6166 *empty_base_seen |= 1;
a39ed81b
JJ		 6167 continue;
6168 }
6169
6170 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep,
575ac27f 6171 empty_base_seen);
1acf0246
BS		 6172 if (sub_count < 0)
6173 return -1;
6174 count += sub_count;
6175 }
6176
6177 /* There must be no padding. */
6178 if (wi::to_wide (TYPE_SIZE (type))
6179 != count * GET_MODE_BITSIZE (*modep))
6180 return -1;
6181
6182 return count;
6183 }
6184
6185 case UNION_TYPE:
6186 case QUAL_UNION_TYPE:
6187 {
6188 /* These aren't very interesting except in a degenerate case. */
6189 int count = 0;
6190 int sub_count;
6191 tree field;
6192
6193 /* Can't handle incomplete types nor sizes that are not
6194 fixed. */
6195 if (!COMPLETE_TYPE_P (type)
6196 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
6197 return -1;
6198
6199 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6200 {
6201 if (TREE_CODE (field) != FIELD_DECL)
6202 continue;
6203
a39ed81b 6204 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep,
575ac27f 6205 empty_base_seen);
1acf0246
BS		 6206 if (sub_count < 0)
6207 return -1;
6208 count = count > sub_count ? count : sub_count;
6209 }
6210
6211 /* There must be no padding. */
6212 if (wi::to_wide (TYPE_SIZE (type))
6213 != count * GET_MODE_BITSIZE (*modep))
6214 return -1;
6215
6216 return count;
6217 }
6218
6219 default:
6220 break;
6221 }
6222
6223 return -1;
6224}
6225
6226/* If an argument, whose type is described by TYPE and MODE, is a homogeneous
6227 float or vector aggregate that shall be passed in FP/vector registers
6228 according to the ELFv2 ABI, return the homogeneous element mode in
6229 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
6230
6231 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
6232
6233bool
6234rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
6235 machine_mode *elt_mode,
6236 int *n_elts)
6237{
6238 /* Note that we do not accept complex types at the top level as
6239 homogeneous aggregates; these types are handled via the
6240 targetm.calls.split_complex_arg mechanism. Complex types
6241 can be elements of homogeneous aggregates, however. */
6242 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
6243 && AGGREGATE_TYPE_P (type))
6244 {
6245 machine_mode field_mode = VOIDmode;
575ac27f 6246 int empty_base_seen = 0;
a39ed81b 6247 int field_count = rs6000_aggregate_candidate (type, &field_mode,
575ac27f 6248 &empty_base_seen);
1acf0246
BS		 6249
6250 if (field_count > 0)
6251 {
6252 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
6253 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
6254
6255 /* The ELFv2 ABI allows homogeneous aggregates to occupy
6256 up to AGGR_ARG_NUM_REG registers. */
6257 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
6258 {
6259 if (elt_mode)
6260 *elt_mode = field_mode;
6261 if (n_elts)
6262 *n_elts = field_count;
575ac27f 6263 if (empty_base_seen && warn_psabi)
a39ed81b 6264 {
239cfd92
JJ		 6265 static unsigned last_reported_type_uid;
6266 unsigned uid = TYPE_UID (TYPE_MAIN_VARIANT (type));
6267 if (uid != last_reported_type_uid)
a39ed81b 6268 {
e33a1eae
JJ		 6269 const char *url
6270 = CHANGES_ROOT_URL "gcc-10/changes.html#empty_base";
575ac27f
JJ		 6271 if (empty_base_seen & 1)
6272 inform (input_location,
6273 "parameter passing for argument of type %qT "
6274 "when C++17 is enabled changed to match C++14 "
691eeb65 6275 "%{in GCC 10.1%}", type, url);
575ac27f
JJ		 6276 else
6277 inform (input_location,
6278 "parameter passing for argument of type %qT "
6279 "with %<[[no_unique_address]]%> members "
691eeb65 6280 "changed %{in GCC 10.1%}", type, url);
239cfd92 6281 last_reported_type_uid = uid;
a39ed81b
JJ		 6282 }
6283 }
1acf0246
BS		 6284 return true;
6285 }
6286 }
6287 }
6288
6289 if (elt_mode)
6290 *elt_mode = mode;
6291 if (n_elts)
6292 *n_elts = 1;
6293 return false;
6294}
6295
6296/* Return a nonzero value to say to return the function value in
6297 memory, just as large structures are always returned. TYPE will be
6298 the data type of the value, and FNTYPE will be the type of the
6299 function doing the returning, or @code{NULL} for libcalls.
6300
6301 The AIX ABI for the RS/6000 specifies that all structures are
6302 returned in memory. The Darwin ABI does the same.
6303
6304 For the Darwin 64 Bit ABI, a function result can be returned in
6305 registers or in memory, depending on the size of the return data
6306 type. If it is returned in registers, the value occupies the same
6307 registers as it would if it were the first and only function
6308 argument. Otherwise, the function places its result in memory at
6309 the location pointed to by GPR3.
6310
6311 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
6312 but a draft put them in memory, and GCC used to implement the draft
6313 instead of the final standard. Therefore, aix_struct_return
6314 controls this instead of DEFAULT_ABI; V.4 targets needing backward
6315 compatibility can change DRAFT_V4_STRUCT_RET to override the
6316 default, and -m switches get the final word. See
6317 rs6000_option_override_internal for more details.
6318
6319 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
6320 long double support is enabled. These values are returned in memory.
6321
6322 int_size_in_bytes returns -1 for variable size objects, which go in
6323 memory always. The cast to unsigned makes -1 > 8. */
6324
6325bool
6326rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6327{
f8f8909a
AS		 6328 /* We do not allow MMA types being used as return values. Only report
6329 the invalid return value usage the first time we encounter it. */
6330 if (cfun
6331 && !cfun->machine->mma_return_type_error
6332 && TREE_TYPE (cfun->decl) == fntype
6333 && (TYPE_MODE (type) == OOmode || TYPE_MODE (type) == XOmode))
6334 {
6335 /* Record we have now handled function CFUN, so the next time we
6336 are called, we do not re-report the same error. */
6337 cfun->machine->mma_return_type_error = true;
6338 if (TYPE_CANONICAL (type) != NULL_TREE)
6339 type = TYPE_CANONICAL (type);
6340 error ("invalid use of MMA type %qs as a function return value",
6341 IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))));
6342 }
6343
1acf0246
BS		 6344 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
6345 if (TARGET_MACHO
6346 && rs6000_darwin64_abi
6347 && TREE_CODE (type) == RECORD_TYPE
6348 && int_size_in_bytes (type) > 0)
6349 {
6350 CUMULATIVE_ARGS valcum;
6351 rtx valret;
6352
6353 valcum.words = 0;
6354 valcum.fregno = FP_ARG_MIN_REG;
6355 valcum.vregno = ALTIVEC_ARG_MIN_REG;
6356 /* Do a trial code generation as if this were going to be passed
6357 as an argument; if any part goes in memory, we return NULL. */
6358 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
6359 if (valret)
6360 return false;
6361 /* Otherwise fall through to more conventional ABI rules. */
6362 }
6363
6364 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
6365 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
6366 NULL, NULL))
6367 return false;
6368
6369 /* The ELFv2 ABI returns aggregates up to 16B in registers */
6370 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
6371 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
6372 return false;
6373
6374 if (AGGREGATE_TYPE_P (type)
6375 && (aix_struct_return
6376 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
6377 return true;
6378
6379 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6380 modes only exist for GCC vector types if -maltivec. */
6381 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
6382 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6383 return false;
6384
6385 /* Return synthetic vectors in memory. */
6386 if (TREE_CODE (type) == VECTOR_TYPE
6387 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6388 {
6389 static bool warned_for_return_big_vectors = false;
6390 if (!warned_for_return_big_vectors)
6391 {
6392 warning (OPT_Wpsabi, "GCC vector returned by reference: "
6393 "non-standard ABI extension with no compatibility "
6394 "guarantee");
6395 warned_for_return_big_vectors = true;
6396 }
6397 return true;
6398 }
6399
6400 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
6401 && FLOAT128_IEEE_P (TYPE_MODE (type)))
6402 return true;
6403
6404 return false;
6405}
6406
6407/* Specify whether values returned in registers should be at the most
6408 significant end of a register. We want aggregates returned by
6409 value to match the way aggregates are passed to functions. */
6410
6411bool
6412rs6000_return_in_msb (const_tree valtype)
6413{
6414 return (DEFAULT_ABI == ABI_ELFv2
6415 && BYTES_BIG_ENDIAN
6416 && AGGREGATE_TYPE_P (valtype)
6417 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
6418 == PAD_UPWARD));
6419}
6420
6421#ifdef HAVE_AS_GNU_ATTRIBUTE
6422/* Return TRUE if a call to function FNDECL may be one that
6423 potentially affects the function calling ABI of the object file. */
6424
6425static bool
6426call_ABI_of_interest (tree fndecl)
6427{
6428 if (rs6000_gnu_attr && symtab->state == EXPANSION)
6429 {
6430 struct cgraph_node *c_node;
6431
6432 /* Libcalls are always interesting. */
6433 if (fndecl == NULL_TREE)
6434 return true;
6435
6436 /* Any call to an external function is interesting. */
6437 if (DECL_EXTERNAL (fndecl))
6438 return true;
6439
6440 /* Interesting functions that we are emitting in this object file. */
6441 c_node = cgraph_node::get (fndecl);
6442 c_node = c_node->ultimate_alias_target ();
6443 return !c_node->only_called_directly_p ();
6444 }
6445 return false;
6446}
6447#endif
6448
6449/* Initialize a variable CUM of type CUMULATIVE_ARGS
6450 for a call to a function whose data type is FNTYPE.
6451 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
6452
6453 For incoming args we set the number of arguments in the prototype large
6454 so we never return a PARALLEL. */
6455
6456void
6457init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
6458 rtx libname ATTRIBUTE_UNUSED, int incoming,
6459 int libcall, int n_named_args,
6460 tree fndecl,
6461 machine_mode return_mode ATTRIBUTE_UNUSED)
6462{
6463 static CUMULATIVE_ARGS zero_cumulative;
6464
6465 *cum = zero_cumulative;
6466 cum->words = 0;
6467 cum->fregno = FP_ARG_MIN_REG;
6468 cum->vregno = ALTIVEC_ARG_MIN_REG;
6469 cum->prototype = (fntype && prototype_p (fntype));
6470 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
6471 ? CALL_LIBCALL : CALL_NORMAL);
6472 cum->sysv_gregno = GP_ARG_MIN_REG;
6473 cum->stdarg = stdarg_p (fntype);
6474 cum->libcall = libcall;
6475
6476 cum->nargs_prototype = 0;
6477 if (incoming || cum->prototype)
6478 cum->nargs_prototype = n_named_args;
6479
6480 /* Check for a longcall attribute. */
6481 if ((!fntype && rs6000_default_long_calls)
6482 || (fntype
6483 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
6484 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
6485 cum->call_cookie |= CALL_LONG;
6486 else if (DEFAULT_ABI != ABI_DARWIN)
6487 {
6488 bool is_local = (fndecl
6489 && !DECL_EXTERNAL (fndecl)
6490 && !DECL_WEAK (fndecl)
6491 && (*targetm.binds_local_p) (fndecl));
6492 if (is_local)
6493 ;
6494 else if (flag_plt)
6495 {
6496 if (fntype
6497 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype)))
6498 cum->call_cookie |= CALL_LONG;
6499 }
6500 else
6501 {
6502 if (!(fntype
6503 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype))))
6504 cum->call_cookie |= CALL_LONG;
6505 }
6506 }
6507
6508 if (TARGET_DEBUG_ARG)
6509 {
6510 fprintf (stderr, "\ninit_cumulative_args:");
6511 if (fntype)
6512 {
6513 tree ret_type = TREE_TYPE (fntype);
6514 fprintf (stderr, " ret code = %s,",
6515 get_tree_code_name (TREE_CODE (ret_type)));
6516 }
6517
6518 if (cum->call_cookie & CALL_LONG)
6519 fprintf (stderr, " longcall,");
6520
6521 fprintf (stderr, " proto = %d, nargs = %d\n",
6522 cum->prototype, cum->nargs_prototype);
6523 }
6524
6525#ifdef HAVE_AS_GNU_ATTRIBUTE
6526 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
6527 {
6528 cum->escapes = call_ABI_of_interest (fndecl);
6529 if (cum->escapes)
6530 {
6531 tree return_type;
6532
6533 if (fntype)
6534 {
6535 return_type = TREE_TYPE (fntype);
6536 return_mode = TYPE_MODE (return_type);
6537 }
6538 else
6539 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
6540
6541 if (return_type != NULL)
6542 {
6543 if (TREE_CODE (return_type) == RECORD_TYPE
6544 && TYPE_TRANSPARENT_AGGR (return_type))
6545 {
6546 return_type = TREE_TYPE (first_field (return_type));
6547 return_mode = TYPE_MODE (return_type);
6548 }
6549 if (AGGREGATE_TYPE_P (return_type)
6550 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
6551 <= 8))
6552 rs6000_returns_struct = true;
6553 }
6554 if (SCALAR_FLOAT_MODE_P (return_mode))
6555 {
6556 rs6000_passes_float = true;
6557 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
6558 && (FLOAT128_IBM_P (return_mode)
6559 || FLOAT128_IEEE_P (return_mode)
6560 || (return_type != NULL
6561 && (TYPE_MAIN_VARIANT (return_type)
6562 == long_double_type_node))))
6563 rs6000_passes_long_double = true;
6564
6565 /* Note if we passed or return a IEEE 128-bit type. We changed
6566 the mangling for these types, and we may need to make an alias
6567 with the old mangling. */
6568 if (FLOAT128_IEEE_P (return_mode))
6569 rs6000_passes_ieee128 = true;
6570 }
6571 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
6572 rs6000_passes_vector = true;
6573 }
6574 }
6575#endif
6576
6577 if (fntype
6578 && !TARGET_ALTIVEC
6579 && TARGET_ALTIVEC_ABI
6580 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
6581 {
6582 error ("cannot return value in vector register because"
6583 " altivec instructions are disabled, use %qs"
6584 " to enable them", "-maltivec");
6585 }
6586}
6587\f
6588
6589/* On rs6000, function arguments are promoted, as are function return
6590 values. */
6591
6592machine_mode
6593rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
6594 machine_mode mode,
6595 int *punsignedp ATTRIBUTE_UNUSED,
f8f8909a 6596 const_tree, int for_return ATTRIBUTE_UNUSED)
1acf0246
BS		 6597{
6598 PROMOTE_MODE (mode, *punsignedp, type);
6599
6600 return mode;
6601}
6602
6603/* Return true if TYPE must be passed on the stack and not in registers. */
6604
6605bool
0ffef200 6606rs6000_must_pass_in_stack (const function_arg_info &arg)
1acf0246
BS		 6607{
6608 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
0ffef200 6609 return must_pass_in_stack_var_size (arg);
1acf0246 6610 else
0ffef200 6611 return must_pass_in_stack_var_size_or_pad (arg);
1acf0246
BS		 6612}
6613
6614static inline bool
6615is_complex_IBM_long_double (machine_mode mode)
6616{
6617 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
6618}
6619
6620/* Whether ABI_V4 passes MODE args to a function in floating point
6621 registers. */
6622
6623static bool
6624abi_v4_pass_in_fpr (machine_mode mode, bool named)
6625{
6626 if (!TARGET_HARD_FLOAT)
6627 return false;
6628 if (mode == DFmode)
6629 return true;
6630 if (mode == SFmode && named)
6631 return true;
6632 /* ABI_V4 passes complex IBM long double in 8 gprs.
6633 Stupid, but we can't change the ABI now. */
6634 if (is_complex_IBM_long_double (mode))
6635 return false;
6636 if (FLOAT128_2REG_P (mode))
6637 return true;
6638 if (DECIMAL_FLOAT_MODE_P (mode))
6639 return true;
6640 return false;
6641}
6642
6643/* Implement TARGET_FUNCTION_ARG_PADDING.
6644
6645 For the AIX ABI structs are always stored left shifted in their
6646 argument slot. */
6647
6648pad_direction
6649rs6000_function_arg_padding (machine_mode mode, const_tree type)
6650{
6651#ifndef AGGREGATE_PADDING_FIXED
6652#define AGGREGATE_PADDING_FIXED 0
6653#endif
6654#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
6655#define AGGREGATES_PAD_UPWARD_ALWAYS 0
6656#endif
6657
6658 if (!AGGREGATE_PADDING_FIXED)
6659 {
6660 /* GCC used to pass structures of the same size as integer types as
6661 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
6662 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
6663 passed padded downward, except that -mstrict-align further
6664 muddied the water in that multi-component structures of 2 and 4
6665 bytes in size were passed padded upward.
6666
6667 The following arranges for best compatibility with previous
6668 versions of gcc, but removes the -mstrict-align dependency. */
6669 if (BYTES_BIG_ENDIAN)
6670 {
6671 HOST_WIDE_INT size = 0;
6672
6673 if (mode == BLKmode)
6674 {
6675 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
6676 size = int_size_in_bytes (type);
6677 }
6678 else
6679 size = GET_MODE_SIZE (mode);
6680
6681 if (size == 1 || size == 2 || size == 4)
6682 return PAD_DOWNWARD;
6683 }
6684 return PAD_UPWARD;
6685 }
6686
6687 if (AGGREGATES_PAD_UPWARD_ALWAYS)
6688 {
6689 if (type != 0 && AGGREGATE_TYPE_P (type))
6690 return PAD_UPWARD;
6691 }
6692
6693 /* Fall back to the default. */
6694 return default_function_arg_padding (mode, type);
6695}
6696
6697/* If defined, a C expression that gives the alignment boundary, in bits,
6698 of an argument with the specified mode and type. If it is not defined,
6699 PARM_BOUNDARY is used for all arguments.
6700
6701 V.4 wants long longs and doubles to be double word aligned. Just
6702 testing the mode size is a boneheaded way to do this as it means
6703 that other types such as complex int are also double word aligned.
6704 However, we're stuck with this because changing the ABI might break
6705 existing library interfaces.
6706
6707 Quadword align Altivec/VSX vectors.
6708 Quadword align large synthetic vector types. */
6709
6710unsigned int
6711rs6000_function_arg_boundary (machine_mode mode, const_tree type)
6712{
6713 machine_mode elt_mode;
6714 int n_elts;
6715
6716 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
6717
6718 if (DEFAULT_ABI == ABI_V4
6719 && (GET_MODE_SIZE (mode) == 8
6720 || (TARGET_HARD_FLOAT
6721 && !is_complex_IBM_long_double (mode)
6722 && FLOAT128_2REG_P (mode))))
6723 return 64;
6724 else if (FLOAT128_VECTOR_P (mode))
6725 return 128;
6726 else if (type && TREE_CODE (type) == VECTOR_TYPE
6727 && int_size_in_bytes (type) >= 8
6728 && int_size_in_bytes (type) < 16)
6729 return 64;
6730 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
6731 || (type && TREE_CODE (type) == VECTOR_TYPE
6732 && int_size_in_bytes (type) >= 16))
6733 return 128;
6734
6735 /* Aggregate types that need > 8 byte alignment are quadword-aligned
6736 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
6737 -mcompat-align-parm is used. */
6738 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
6739 || DEFAULT_ABI == ABI_ELFv2)
6740 && type && TYPE_ALIGN (type) > 64)
6741 {
6742 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
6743 or homogeneous float/vector aggregates here. We already handled
6744 vector aggregates above, but still need to check for float here. */
6745 bool aggregate_p = (AGGREGATE_TYPE_P (type)
6746 && !SCALAR_FLOAT_MODE_P (elt_mode));
6747
6748 /* We used to check for BLKmode instead of the above aggregate type
6749 check. Warn when this results in any difference to the ABI. */
6750 if (aggregate_p != (mode == BLKmode))
6751 {
6752 static bool warned;
6753 if (!warned && warn_psabi)
6754 {
6755 warned = true;
6756 inform (input_location,
6757 "the ABI of passing aggregates with %d-byte alignment"
6758 " has changed in GCC 5",
6759 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
6760 }
6761 }
6762
6763 if (aggregate_p)
6764 return 128;
6765 }
6766
6767 /* Similar for the Darwin64 ABI. Note that for historical reasons we
6768 implement the "aggregate type" check as a BLKmode check here; this
6769 means certain aggregate types are in fact not aligned. */
6770 if (TARGET_MACHO && rs6000_darwin64_abi
6771 && mode == BLKmode
6772 && type && TYPE_ALIGN (type) > 64)
6773 return 128;
6774
6775 return PARM_BOUNDARY;
6776}
6777
6778/* The offset in words to the start of the parameter save area. */
6779
6780static unsigned int
6781rs6000_parm_offset (void)
6782{
6783 return (DEFAULT_ABI == ABI_V4 ? 2
6784 : DEFAULT_ABI == ABI_ELFv2 ? 4
6785 : 6);
6786}
6787
6788/* For a function parm of MODE and TYPE, return the starting word in
6789 the parameter area. NWORDS of the parameter area are already used. */
6790
6791static unsigned int
6792rs6000_parm_start (machine_mode mode, const_tree type,
6793 unsigned int nwords)
6794{
6795 unsigned int align;
6796
6797 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
6798 return nwords + (-(rs6000_parm_offset () + nwords) & align);
6799}
6800
6801/* Compute the size (in words) of a function argument. */
6802
6803static unsigned long
6804rs6000_arg_size (machine_mode mode, const_tree type)
6805{
6806 unsigned long size;
6807
6808 if (mode != BLKmode)
6809 size = GET_MODE_SIZE (mode);
6810 else
6811 size = int_size_in_bytes (type);
6812
6813 if (TARGET_32BIT)
6814 return (size + 3) >> 2;
6815 else
6816 return (size + 7) >> 3;
6817}
6818\f
6819/* Use this to flush pending int fields. */
6820
6821static void
6822rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
6823 HOST_WIDE_INT bitpos, int final)
6824{
6825 unsigned int startbit, endbit;
6826 int intregs, intoffset;
6827
6828 /* Handle the situations where a float is taking up the first half
6829 of the GPR, and the other half is empty (typically due to
6830 alignment restrictions). We can detect this by a 8-byte-aligned
6831 int field, or by seeing that this is the final flush for this
6832 argument. Count the word and continue on. */
6833 if (cum->floats_in_gpr == 1
6834 && (cum->intoffset % 64 == 0
6835 || (cum->intoffset == -1 && final)))
6836 {
6837 cum->words++;
6838 cum->floats_in_gpr = 0;
6839 }
6840
6841 if (cum->intoffset == -1)
6842 return;
6843
6844 intoffset = cum->intoffset;
6845 cum->intoffset = -1;
6846 cum->floats_in_gpr = 0;
6847
6848 if (intoffset % BITS_PER_WORD != 0)
6849 {
6850 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
6851 if (!int_mode_for_size (bits, 0).exists ())
6852 {
6853 /* We couldn't find an appropriate mode, which happens,
6854 e.g., in packed structs when there are 3 bytes to load.
6855 Back intoffset back to the beginning of the word in this
6856 case. */
6857 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
6858 }
6859 }
6860
6861 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
6862 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
6863 intregs = (endbit - startbit) / BITS_PER_WORD;
6864 cum->words += intregs;
6865 /* words should be unsigned. */
6866 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
6867 {
6868 int pad = (endbit/BITS_PER_WORD) - cum->words;
6869 cum->words += pad;
6870 }
6871}
6872
6873/* The darwin64 ABI calls for us to recurse down through structs,
6874 looking for elements passed in registers. Unfortunately, we have
6875 to track int register count here also because of misalignments
6876 in powerpc alignment mode. */
6877
6878static void
6879rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
6880 const_tree type,
6881 HOST_WIDE_INT startbitpos)
6882{
6883 tree f;
6884
6885 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
6886 if (TREE_CODE (f) == FIELD_DECL)
6887 {
6888 HOST_WIDE_INT bitpos = startbitpos;
6889 tree ftype = TREE_TYPE (f);
6890 machine_mode mode;
6891 if (ftype == error_mark_node)
6892 continue;
6893 mode = TYPE_MODE (ftype);
6894
6895 if (DECL_SIZE (f) != 0
6896 && tree_fits_uhwi_p (bit_position (f)))
6897 bitpos += int_bit_position (f);
6898
6899 /* ??? FIXME: else assume zero offset. */
6900
6901 if (TREE_CODE (ftype) == RECORD_TYPE)
6902 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
6903 else if (USE_FP_FOR_ARG_P (cum, mode))
6904 {
6905 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
6906 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
6907 cum->fregno += n_fpregs;
6908 /* Single-precision floats present a special problem for
6909 us, because they are smaller than an 8-byte GPR, and so
6910 the structure-packing rules combined with the standard
6911 varargs behavior mean that we want to pack float/float
6912 and float/int combinations into a single register's
6913 space. This is complicated by the arg advance flushing,
6914 which works on arbitrarily large groups of int-type
6915 fields. */
6916 if (mode == SFmode)
6917 {
6918 if (cum->floats_in_gpr == 1)
6919 {
6920 /* Two floats in a word; count the word and reset
6921 the float count. */
6922 cum->words++;
6923 cum->floats_in_gpr = 0;
6924 }
6925 else if (bitpos % 64 == 0)
6926 {
6927 /* A float at the beginning of an 8-byte word;
6928 count it and put off adjusting cum->words until
6929 we see if a arg advance flush is going to do it
6930 for us. */
6931 cum->floats_in_gpr++;
6932 }
6933 else
6934 {
6935 /* The float is at the end of a word, preceded
6936 by integer fields, so the arg advance flush
6937 just above has already set cum->words and
6938 everything is taken care of. */
6939 }
6940 }
6941 else
6942 cum->words += n_fpregs;
6943 }
6944 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
6945 {
6946 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
6947 cum->vregno++;
6948 cum->words += 2;
6949 }
6950 else if (cum->intoffset == -1)
6951 cum->intoffset = bitpos;
6952 }
6953}
6954
6955/* Check for an item that needs to be considered specially under the darwin 64
6956 bit ABI. These are record types where the mode is BLK or the structure is
6957 8 bytes in size. */
6958int
6959rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
6960{
6961 return rs6000_darwin64_abi
6962 && ((mode == BLKmode
6963 && TREE_CODE (type) == RECORD_TYPE
6964 && int_size_in_bytes (type) > 0)
6965 || (type && TREE_CODE (type) == RECORD_TYPE
6966 && int_size_in_bytes (type) == 8)) ? 1 : 0;
6967}
6968
6969/* Update the data in CUM to advance over an argument
6970 of mode MODE and data type TYPE.
6971 (TYPE is null for libcalls where that information may not be available.)
6972
6973 Note that for args passed by reference, function_arg will be called
6974 with MODE and TYPE set to that of the pointer to the arg, not the arg
6975 itself. */
6976
6977static void
6978rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
6979 const_tree type, bool named, int depth)
6980{
6981 machine_mode elt_mode;
6982 int n_elts;
6983
6984 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
6985
6986 /* Only tick off an argument if we're not recursing. */
6987 if (depth == 0)
6988 cum->nargs_prototype--;
6989
6990#ifdef HAVE_AS_GNU_ATTRIBUTE
6991 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
6992 && cum->escapes)
6993 {
6994 if (SCALAR_FLOAT_MODE_P (mode))
6995 {
6996 rs6000_passes_float = true;
6997 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
6998 && (FLOAT128_IBM_P (mode)
6999 || FLOAT128_IEEE_P (mode)
7000 || (type != NULL
7001 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
7002 rs6000_passes_long_double = true;
7003
7004 /* Note if we passed or return a IEEE 128-bit type. We changed the
7005 mangling for these types, and we may need to make an alias with
7006 the old mangling. */
7007 if (FLOAT128_IEEE_P (mode))
7008 rs6000_passes_ieee128 = true;
7009 }
7010 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
7011 rs6000_passes_vector = true;
7012 }
7013#endif
7014
7015 if (TARGET_ALTIVEC_ABI
7016 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
7017 || (type && TREE_CODE (type) == VECTOR_TYPE
7018 && int_size_in_bytes (type) == 16)))
7019 {
7020 bool stack = false;
7021
7022 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
7023 {
7024 cum->vregno += n_elts;
7025
7026 if (!TARGET_ALTIVEC)
7027 error ("cannot pass argument in vector register because"
7028 " altivec instructions are disabled, use %qs"
7029 " to enable them", "-maltivec");
7030
7031 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7032 even if it is going to be passed in a vector register.
7033 Darwin does the same for variable-argument functions. */
7034 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7035 && TARGET_64BIT)
7036 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
7037 stack = true;
7038 }
7039 else
7040 stack = true;
7041
7042 if (stack)
7043 {
7044 int align;
7045
7046 /* Vector parameters must be 16-byte aligned. In 32-bit
7047 mode this means we need to take into account the offset
7048 to the parameter save area. In 64-bit mode, they just
7049 have to start on an even word, since the parameter save
7050 area is 16-byte aligned. */
7051 if (TARGET_32BIT)
7052 align = -(rs6000_parm_offset () + cum->words) & 3;
7053 else
7054 align = cum->words & 1;
7055 cum->words += align + rs6000_arg_size (mode, type);
7056
7057 if (TARGET_DEBUG_ARG)
7058 {
7059 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
7060 cum->words, align);
7061 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
7062 cum->nargs_prototype, cum->prototype,
7063 GET_MODE_NAME (mode));
7064 }
7065 }
7066 }
7067 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7068 {
7069 int size = int_size_in_bytes (type);
7070 /* Variable sized types have size == -1 and are
7071 treated as if consisting entirely of ints.
7072 Pad to 16 byte boundary if needed. */
7073 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
7074 && (cum->words % 2) != 0)
7075 cum->words++;
7076 /* For varargs, we can just go up by the size of the struct. */
7077 if (!named)
7078 cum->words += (size + 7) / 8;
7079 else
7080 {
7081 /* It is tempting to say int register count just goes up by
7082 sizeof(type)/8, but this is wrong in a case such as
7083 { int; double; int; } [powerpc alignment]. We have to
7084 grovel through the fields for these too. */
7085 cum->intoffset = 0;
7086 cum->floats_in_gpr = 0;
7087 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
7088 rs6000_darwin64_record_arg_advance_flush (cum,
7089 size * BITS_PER_UNIT, 1);
7090 }
7091 if (TARGET_DEBUG_ARG)
7092 {
7093 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
7094 cum->words, TYPE_ALIGN (type), size);
7095 fprintf (stderr,
7096 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
7097 cum->nargs_prototype, cum->prototype,
7098 GET_MODE_NAME (mode));
7099 }
7100 }
7101 else if (DEFAULT_ABI == ABI_V4)
7102 {
7103 if (abi_v4_pass_in_fpr (mode, named))
7104 {
7105 /* _Decimal128 must use an even/odd register pair. This assumes
7106 that the register number is odd when fregno is odd. */
7107 if (mode == TDmode && (cum->fregno % 2) == 1)
7108 cum->fregno++;
7109
7110 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
7111 <= FP_ARG_V4_MAX_REG)
7112 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
7113 else
7114 {
7115 cum->fregno = FP_ARG_V4_MAX_REG + 1;
7116 if (mode == DFmode || FLOAT128_IBM_P (mode)
7117 || mode == DDmode || mode == TDmode)
7118 cum->words += cum->words & 1;
7119 cum->words += rs6000_arg_size (mode, type);
7120 }
7121 }
7122 else
7123 {
7124 int n_words = rs6000_arg_size (mode, type);
7125 int gregno = cum->sysv_gregno;
7126
7127 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
7128 As does any other 2 word item such as complex int due to a
7129 historical mistake. */
7130 if (n_words == 2)
7131 gregno += (1 - gregno) & 1;
7132
7133 /* Multi-reg args are not split between registers and stack. */
7134 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7135 {
7136 /* Long long is aligned on the stack. So are other 2 word
7137 items such as complex int due to a historical mistake. */
7138 if (n_words == 2)
7139 cum->words += cum->words & 1;
7140 cum->words += n_words;
7141 }
7142
7143 /* Note: continuing to accumulate gregno past when we've started
7144 spilling to the stack indicates the fact that we've started
7145 spilling to the stack to expand_builtin_saveregs. */
7146 cum->sysv_gregno = gregno + n_words;
7147 }
7148
7149 if (TARGET_DEBUG_ARG)
7150 {
7151 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7152 cum->words, cum->fregno);
7153 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
7154 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
7155 fprintf (stderr, "mode = %4s, named = %d\n",
7156 GET_MODE_NAME (mode), named);
7157 }
7158 }
7159 else
7160 {
7161 int n_words = rs6000_arg_size (mode, type);
7162 int start_words = cum->words;
7163 int align_words = rs6000_parm_start (mode, type, start_words);
7164
7165 cum->words = align_words + n_words;
7166
7167 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
7168 {
7169 /* _Decimal128 must be passed in an even/odd float register pair.
7170 This assumes that the register number is odd when fregno is
7171 odd. */
7172 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
7173 cum->fregno++;
7174 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
7175 }
7176
7177 if (TARGET_DEBUG_ARG)
7178 {
7179 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7180 cum->words, cum->fregno);
7181 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
7182 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
7183 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
7184 named, align_words - start_words, depth);
7185 }
7186 }
7187}
7188
7189void
6930c98c
RS		 7190rs6000_function_arg_advance (cumulative_args_t cum,
7191 const function_arg_info &arg)
1acf0246 7192{
6930c98c
RS		 7193 rs6000_function_arg_advance_1 (get_cumulative_args (cum),
7194 arg.mode, arg.type, arg.named, 0);
1acf0246
BS		 7195}
7196
7197/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
7198 structure between cum->intoffset and bitpos to integer registers. */
7199
7200static void
7201rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
7202 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
7203{
7204 machine_mode mode;
7205 unsigned int regno;
7206 unsigned int startbit, endbit;
7207 int this_regno, intregs, intoffset;
7208 rtx reg;
7209
7210 if (cum->intoffset == -1)
7211 return;
7212
7213 intoffset = cum->intoffset;
7214 cum->intoffset = -1;
7215
7216 /* If this is the trailing part of a word, try to only load that
7217 much into the register. Otherwise load the whole register. Note
7218 that in the latter case we may pick up unwanted bits. It's not a
7219 problem at the moment but may wish to revisit. */
7220
7221 if (intoffset % BITS_PER_WORD != 0)
7222 {
7223 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
7224 if (!int_mode_for_size (bits, 0).exists (&mode))
7225 {
7226 /* We couldn't find an appropriate mode, which happens,
7227 e.g., in packed structs when there are 3 bytes to load.
7228 Back intoffset back to the beginning of the word in this
7229 case. */
7230 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
7231 mode = word_mode;
7232 }
7233 }
7234 else
7235 mode = word_mode;
7236
7237 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
7238 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
7239 intregs = (endbit - startbit) / BITS_PER_WORD;
7240 this_regno = cum->words + intoffset / BITS_PER_WORD;
7241
7242 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
7243 cum->use_stack = 1;
7244
7245 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
7246 if (intregs <= 0)
7247 return;
7248
7249 intoffset /= BITS_PER_UNIT;
7250 do
7251 {
7252 regno = GP_ARG_MIN_REG + this_regno;
7253 reg = gen_rtx_REG (mode, regno);
7254 rvec[(*k)++] =
7255 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
7256
7257 this_regno += 1;
7258 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
7259 mode = word_mode;
7260 intregs -= 1;
7261 }
7262 while (intregs > 0);
7263}
7264
7265/* Recursive workhorse for the following. */
7266
7267static void
7268rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
7269 HOST_WIDE_INT startbitpos, rtx rvec[],
7270 int *k)
7271{
7272 tree f;
7273
7274 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7275 if (TREE_CODE (f) == FIELD_DECL)
7276 {
7277 HOST_WIDE_INT bitpos = startbitpos;
7278 tree ftype = TREE_TYPE (f);
7279 machine_mode mode;
7280 if (ftype == error_mark_node)
7281 continue;
7282 mode = TYPE_MODE (ftype);
7283
7284 if (DECL_SIZE (f) != 0
7285 && tree_fits_uhwi_p (bit_position (f)))
7286 bitpos += int_bit_position (f);
7287
7288 /* ??? FIXME: else assume zero offset. */
7289
7290 if (TREE_CODE (ftype) == RECORD_TYPE)
7291 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
7292 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
7293 {
7294 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
7295#if 0
7296 switch (mode)
7297 {
7298 case E_SCmode: mode = SFmode; break;
7299 case E_DCmode: mode = DFmode; break;
7300 case E_TCmode: mode = TFmode; break;
7301 default: break;
7302 }
7303#endif
7304 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
7305 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
7306 {
7307 gcc_assert (cum->fregno == FP_ARG_MAX_REG
7308 && (mode == TFmode || mode == TDmode));
7309 /* Long double or _Decimal128 split over regs and memory. */
7310 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
7311 cum->use_stack=1;
7312 }
7313 rvec[(*k)++]
7314 = gen_rtx_EXPR_LIST (VOIDmode,
7315 gen_rtx_REG (mode, cum->fregno++),
7316 GEN_INT (bitpos / BITS_PER_UNIT));
7317 if (FLOAT128_2REG_P (mode))
7318 cum->fregno++;
7319 }
7320 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
7321 {
7322 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
7323 rvec[(*k)++]
7324 = gen_rtx_EXPR_LIST (VOIDmode,
7325 gen_rtx_REG (mode, cum->vregno++),
7326 GEN_INT (bitpos / BITS_PER_UNIT));
7327 }
7328 else if (cum->intoffset == -1)
7329 cum->intoffset = bitpos;
7330 }
7331}
7332
7333/* For the darwin64 ABI, we want to construct a PARALLEL consisting of
7334 the register(s) to be used for each field and subfield of a struct
7335 being passed by value, along with the offset of where the
7336 register's value may be found in the block. FP fields go in FP
7337 register, vector fields go in vector registers, and everything
7338 else goes in int registers, packed as in memory.
7339
7340 This code is also used for function return values. RETVAL indicates
7341 whether this is the case.
7342
7343 Much of this is taken from the SPARC V9 port, which has a similar
7344 calling convention. */
7345
7346rtx
7347rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
7348 bool named, bool retval)
7349{
7350 rtx rvec[FIRST_PSEUDO_REGISTER];
7351 int k = 1, kbase = 1;
7352 HOST_WIDE_INT typesize = int_size_in_bytes (type);
7353 /* This is a copy; modifications are not visible to our caller. */
7354 CUMULATIVE_ARGS copy_cum = *orig_cum;
7355 CUMULATIVE_ARGS *cum = &copy_cum;
7356
7357 /* Pad to 16 byte boundary if needed. */
7358 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
7359 && (cum->words % 2) != 0)
7360 cum->words++;
7361
7362 cum->intoffset = 0;
7363 cum->use_stack = 0;
7364 cum->named = named;
7365
7366 /* Put entries into rvec[] for individual FP and vector fields, and
7367 for the chunks of memory that go in int regs. Note we start at
7368 element 1; 0 is reserved for an indication of using memory, and
7369 may or may not be filled in below. */
7370 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
7371 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
7372
7373 /* If any part of the struct went on the stack put all of it there.
7374 This hack is because the generic code for
7375 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
7376 parts of the struct are not at the beginning. */
7377 if (cum->use_stack)
7378 {
7379 if (retval)
7380 return NULL_RTX; /* doesn't go in registers at all */
7381 kbase = 0;
7382 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7383 }
7384 if (k > 1 || cum->use_stack)
7385 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
7386 else
7387 return NULL_RTX;
7388}
7389
7390/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
7391
7392static rtx
7393rs6000_mixed_function_arg (machine_mode mode, const_tree type,
7394 int align_words)
7395{
7396 int n_units;
7397 int i, k;
7398 rtx rvec[GP_ARG_NUM_REG + 1];
7399
7400 if (align_words >= GP_ARG_NUM_REG)
7401 return NULL_RTX;
7402
7403 n_units = rs6000_arg_size (mode, type);
7404
7405 /* Optimize the simple case where the arg fits in one gpr, except in
7406 the case of BLKmode due to assign_parms assuming that registers are
7407 BITS_PER_WORD wide. */
7408 if (n_units == 0
7409 || (n_units == 1 && mode != BLKmode))
7410 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7411
7412 k = 0;
7413 if (align_words + n_units > GP_ARG_NUM_REG)
7414 /* Not all of the arg fits in gprs. Say that it goes in memory too,
7415 using a magic NULL_RTX component.
7416 This is not strictly correct. Only some of the arg belongs in
7417 memory, not all of it. However, the normal scheme using
7418 function_arg_partial_nregs can result in unusual subregs, eg.
7419 (subreg:SI (reg:DF) 4), which are not handled well. The code to
7420 store the whole arg to memory is often more efficient than code
7421 to store pieces, and we know that space is available in the right
7422 place for the whole arg. */
7423 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7424
7425 i = 0;
7426 do
7427 {
7428 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
7429 rtx off = GEN_INT (i++ * 4);
7430 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7431 }
7432 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
7433
7434 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
7435}
7436
7437/* We have an argument of MODE and TYPE that goes into FPRs or VRs,
7438 but must also be copied into the parameter save area starting at
7439 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
7440 to the GPRs and/or memory. Return the number of elements used. */
7441
7442static int
7443rs6000_psave_function_arg (machine_mode mode, const_tree type,
7444 int align_words, rtx *rvec)
7445{
7446 int k = 0;
7447
7448 if (align_words < GP_ARG_NUM_REG)
7449 {
7450 int n_words = rs6000_arg_size (mode, type);
7451
7452 if (align_words + n_words > GP_ARG_NUM_REG
7453 || mode == BLKmode
7454 || (TARGET_32BIT && TARGET_POWERPC64))
7455 {
7456 /* If this is partially on the stack, then we only
7457 include the portion actually in registers here. */
7458 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
7459 int i = 0;
7460
7461 if (align_words + n_words > GP_ARG_NUM_REG)
7462 {
7463 /* Not all of the arg fits in gprs. Say that it goes in memory
7464 too, using a magic NULL_RTX component. Also see comment in
7465 rs6000_mixed_function_arg for why the normal
7466 function_arg_partial_nregs scheme doesn't work in this case. */
7467 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7468 }
7469
7470 do
7471 {
7472 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
7473 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
7474 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7475 }
7476 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
7477 }
7478 else
7479 {
7480 /* The whole arg fits in gprs. */
7481 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7482 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
7483 }
7484 }
7485 else
7486 {
7487 /* It's entirely in memory. */
7488 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7489 }
7490
7491 return k;
7492}
7493
7494/* RVEC is a vector of K components of an argument of mode MODE.
7495 Construct the final function_arg return value from it. */
7496
7497static rtx
7498rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
7499{
7500 gcc_assert (k >= 1);
7501
7502 /* Avoid returning a PARALLEL in the trivial cases. */
7503 if (k == 1)
7504 {
7505 if (XEXP (rvec[0], 0) == NULL_RTX)
7506 return NULL_RTX;
7507
7508 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
7509 return XEXP (rvec[0], 0);
7510 }
7511
7512 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
7513}
7514
7515/* Determine where to put an argument to a function.
7516 Value is zero to push the argument on the stack,
7517 or a hard register in which to store the argument.
7518
1acf0246
BS		 7519 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7520 the preceding args and about the function being called. It is
7521 not modified in this routine.
6783fdb7 7522 ARG is a description of the argument.
1acf0246
BS		 7523
7524 On RS/6000 the first eight words of non-FP are normally in registers
7525 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
7526 Under V.4, the first 8 FP args are in registers.
7527
7528 If this is floating-point and no prototype is specified, we use
7529 both an FP and integer register (or possibly FP reg and stack). Library
7530 functions (when CALL_LIBCALL is set) always have the proper types for args,
7531 so we can pass the FP value just in one register. emit_library_function
7532 doesn't support PARALLEL anyway.
7533
7534 Note that for args passed by reference, function_arg will be called
6783fdb7 7535 with ARG describing the pointer to the arg, not the arg itself. */
1acf0246
BS		 7536
7537rtx
6783fdb7 7538rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
1acf0246
BS		 7539{
7540 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6783fdb7
RS		 7541 tree type = arg.type;
7542 machine_mode mode = arg.mode;
7543 bool named = arg.named;
1acf0246
BS		 7544 enum rs6000_abi abi = DEFAULT_ABI;
7545 machine_mode elt_mode;
7546 int n_elts;
7547
0ad7e730 7548 /* We do not allow MMA types being used as function arguments. */
f8f8909a 7549 if (mode == OOmode || mode == XOmode)
0ad7e730
PB		 7550 {
7551 if (TYPE_CANONICAL (type) != NULL_TREE)
7552 type = TYPE_CANONICAL (type);
7553 error ("invalid use of MMA operand of type %qs as a function parameter",
7554 IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))));
7555 return NULL_RTX;
7556 }
7557
1acf0246
BS		 7558 /* Return a marker to indicate whether CR1 needs to set or clear the
7559 bit that V.4 uses to say fp args were passed in registers.
7560 Assume that we don't need the marker for software floating point,
7561 or compiler generated library calls. */
6783fdb7 7562 if (arg.end_marker_p ())
1acf0246
BS		 7563 {
7564 if (abi == ABI_V4
7565 && (cum->call_cookie & CALL_LIBCALL) == 0
7566 && (cum->stdarg
7567 || (cum->nargs_prototype < 0
7568 && (cum->prototype || TARGET_NO_PROTOTYPE)))
7569 && TARGET_HARD_FLOAT)
7570 return GEN_INT (cum->call_cookie
7571 | ((cum->fregno == FP_ARG_MIN_REG)
7572 ? CALL_V4_SET_FP_ARGS
7573 : CALL_V4_CLEAR_FP_ARGS));
7574
7575 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
7576 }
7577
7578 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
7579
7580 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7581 {
7582 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
7583 if (rslt != NULL_RTX)
7584 return rslt;
7585 /* Else fall through to usual handling. */
7586 }
7587
7588 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
7589 {
7590 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
7591 rtx r, off;
7592 int i, k = 0;
7593
7594 /* Do we also need to pass this argument in the parameter save area?
7595 Library support functions for IEEE 128-bit are assumed to not need the
7596 value passed both in GPRs and in vector registers. */
7597 if (TARGET_64BIT && !cum->prototype
7598 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
7599 {
7600 int align_words = ROUND_UP (cum->words, 2);
7601 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
7602 }
7603
7604 /* Describe where this argument goes in the vector registers. */
7605 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
7606 {
7607 r = gen_rtx_REG (elt_mode, cum->vregno + i);
7608 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
7609 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7610 }
7611
7612 return rs6000_finish_function_arg (mode, rvec, k);
7613 }
7614 else if (TARGET_ALTIVEC_ABI
7615 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7616 || (type && TREE_CODE (type) == VECTOR_TYPE
7617 && int_size_in_bytes (type) == 16)))
7618 {
7619 if (named || abi == ABI_V4)
7620 return NULL_RTX;
7621 else
7622 {
7623 /* Vector parameters to varargs functions under AIX or Darwin
7624 get passed in memory and possibly also in GPRs. */
7625 int align, align_words, n_words;
7626 machine_mode part_mode;
7627
7628 /* Vector parameters must be 16-byte aligned. In 32-bit
7629 mode this means we need to take into account the offset
7630 to the parameter save area. In 64-bit mode, they just
7631 have to start on an even word, since the parameter save
7632 area is 16-byte aligned. */
7633 if (TARGET_32BIT)
7634 align = -(rs6000_parm_offset () + cum->words) & 3;
7635 else
7636 align = cum->words & 1;
7637 align_words = cum->words + align;
7638
7639 /* Out of registers? Memory, then. */
7640 if (align_words >= GP_ARG_NUM_REG)
7641 return NULL_RTX;
7642
7643 if (TARGET_32BIT && TARGET_POWERPC64)
7644 return rs6000_mixed_function_arg (mode, type, align_words);
7645
7646 /* The vector value goes in GPRs. Only the part of the
7647 value in GPRs is reported here. */
7648 part_mode = mode;
7649 n_words = rs6000_arg_size (mode, type);
7650 if (align_words + n_words > GP_ARG_NUM_REG)
7651 /* Fortunately, there are only two possibilities, the value
7652 is either wholly in GPRs or half in GPRs and half not. */
7653 part_mode = DImode;
7654
7655 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
7656 }
7657 }
7658
7659 else if (abi == ABI_V4)
7660 {
7661 if (abi_v4_pass_in_fpr (mode, named))
7662 {
7663 /* _Decimal128 must use an even/odd register pair. This assumes
7664 that the register number is odd when fregno is odd. */
7665 if (mode == TDmode && (cum->fregno % 2) == 1)
7666 cum->fregno++;
7667
7668 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
7669 <= FP_ARG_V4_MAX_REG)
7670 return gen_rtx_REG (mode, cum->fregno);
7671 else
7672 return NULL_RTX;
7673 }
7674 else
7675 {
7676 int n_words = rs6000_arg_size (mode, type);
7677 int gregno = cum->sysv_gregno;
7678
7679 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
7680 As does any other 2 word item such as complex int due to a
7681 historical mistake. */
7682 if (n_words == 2)
7683 gregno += (1 - gregno) & 1;
7684
7685 /* Multi-reg args are not split between registers and stack. */
7686 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7687 return NULL_RTX;
7688
7689 if (TARGET_32BIT && TARGET_POWERPC64)
7690 return rs6000_mixed_function_arg (mode, type,
7691 gregno - GP_ARG_MIN_REG);
7692 return gen_rtx_REG (mode, gregno);
7693 }
7694 }
7695 else
7696 {
7697 int align_words = rs6000_parm_start (mode, type, cum->words);
7698
7699 /* _Decimal128 must be passed in an even/odd float register pair.
7700 This assumes that the register number is odd when fregno is odd. */
7701 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
7702 cum->fregno++;
7703
7704 if (USE_FP_FOR_ARG_P (cum, elt_mode)
7705 && !(TARGET_AIX && !TARGET_ELF
7706 && type != NULL && AGGREGATE_TYPE_P (type)))
7707 {
7708 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
7709 rtx r, off;
7710 int i, k = 0;
7711 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
7712 int fpr_words;
7713
7714 /* Do we also need to pass this argument in the parameter
7715 save area? */
7716 if (type && (cum->nargs_prototype <= 0
7717 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7718 && TARGET_XL_COMPAT
7719 && align_words >= GP_ARG_NUM_REG)))
7720 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
7721
7722 /* Describe where this argument goes in the fprs. */
7723 for (i = 0; i < n_elts
7724 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
7725 {
7726 /* Check if the argument is split over registers and memory.
7727 This can only ever happen for long double or _Decimal128;
7728 complex types are handled via split_complex_arg. */
7729 machine_mode fmode = elt_mode;
7730 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
7731 {
7732 gcc_assert (FLOAT128_2REG_P (fmode));
7733 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
7734 }
7735
7736 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
7737 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
7738 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7739 }
7740
7741 /* If there were not enough FPRs to hold the argument, the rest
7742 usually goes into memory. However, if the current position
7743 is still within the register parameter area, a portion may
7744 actually have to go into GPRs.
7745
7746 Note that it may happen that the portion of the argument
7747 passed in the first "half" of the first GPR was already
7748 passed in the last FPR as well.
7749
7750 For unnamed arguments, we already set up GPRs to cover the
7751 whole argument in rs6000_psave_function_arg, so there is
7752 nothing further to do at this point. */
7753 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
7754 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
7755 && cum->nargs_prototype > 0)
7756 {
7757 static bool warned;
7758
7759 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
7760 int n_words = rs6000_arg_size (mode, type);
7761
7762 align_words += fpr_words;
7763 n_words -= fpr_words;
7764
7765 do
7766 {
7767 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
7768 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
7769 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7770 }
7771 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
7772
7773 if (!warned && warn_psabi)
7774 {
7775 warned = true;
7776 inform (input_location,
7777 "the ABI of passing homogeneous %<float%> aggregates"
7778 " has changed in GCC 5");
7779 }
7780 }
7781
7782 return rs6000_finish_function_arg (mode, rvec, k);
7783 }
7784 else if (align_words < GP_ARG_NUM_REG)
7785 {
7786 if (TARGET_32BIT && TARGET_POWERPC64)
7787 return rs6000_mixed_function_arg (mode, type, align_words);
7788
7789 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7790 }
7791 else
7792 return NULL_RTX;
7793 }
7794}
7795\f
7796/* For an arg passed partly in registers and partly in memory, this is
7797 the number of bytes passed in registers. For args passed entirely in
7798 registers or entirely in memory, zero. When an arg is described by a
7799 PARALLEL, perhaps using more than one register type, this function
7800 returns the number of bytes used by the first element of the PARALLEL. */
7801
7802int
a7c81bc1
RS		 7803rs6000_arg_partial_bytes (cumulative_args_t cum_v,
7804 const function_arg_info &arg)
1acf0246
BS		 7805{
7806 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7807 bool passed_in_gprs = true;
7808 int ret = 0;
7809 int align_words;
7810 machine_mode elt_mode;
7811 int n_elts;
7812
a7c81bc1
RS		 7813 rs6000_discover_homogeneous_aggregate (arg.mode, arg.type,
7814 &elt_mode, &n_elts);
1acf0246
BS		 7815
7816 if (DEFAULT_ABI == ABI_V4)
7817 return 0;
7818
a7c81bc1 7819 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, arg.named))
1acf0246
BS		 7820 {
7821 /* If we are passing this arg in the fixed parameter save area (gprs or
7822 memory) as well as VRs, we do not use the partial bytes mechanism;
7823 instead, rs6000_function_arg will return a PARALLEL including a memory
7824 element as necessary. Library support functions for IEEE 128-bit are
7825 assumed to not need the value passed both in GPRs and in vector
7826 registers. */
7827 if (TARGET_64BIT && !cum->prototype
7828 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
7829 return 0;
7830
7831 /* Otherwise, we pass in VRs only. Check for partial copies. */
7832 passed_in_gprs = false;
7833 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
7834 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
7835 }
7836
7837 /* In this complicated case we just disable the partial_nregs code. */
a7c81bc1 7838 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (arg.mode, arg.type))
1acf0246
BS		 7839 return 0;
7840
a7c81bc1 7841 align_words = rs6000_parm_start (arg.mode, arg.type, cum->words);
1acf0246
BS		 7842
7843 if (USE_FP_FOR_ARG_P (cum, elt_mode)
a7c81bc1 7844 && !(TARGET_AIX && !TARGET_ELF && arg.aggregate_type_p ()))
1acf0246
BS		 7845 {
7846 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
7847
7848 /* If we are passing this arg in the fixed parameter save area
7849 (gprs or memory) as well as FPRs, we do not use the partial
7850 bytes mechanism; instead, rs6000_function_arg will return a
7851 PARALLEL including a memory element as necessary. */
a7c81bc1 7852 if (arg.type
1acf0246
BS		 7853 && (cum->nargs_prototype <= 0
7854 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7855 && TARGET_XL_COMPAT
7856 && align_words >= GP_ARG_NUM_REG)))
7857 return 0;
7858
7859 /* Otherwise, we pass in FPRs only. Check for partial copies. */
7860 passed_in_gprs = false;
7861 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
7862 {
7863 /* Compute number of bytes / words passed in FPRs. If there
7864 is still space available in the register parameter area
7865 *after* that amount, a part of the argument will be passed
7866 in GPRs. In that case, the total amount passed in any
7867 registers is equal to the amount that would have been passed
7868 in GPRs if everything were passed there, so we fall back to
7869 the GPR code below to compute the appropriate value. */
7870 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
7871 * MIN (8, GET_MODE_SIZE (elt_mode)));
7872 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
7873
7874 if (align_words + fpr_words < GP_ARG_NUM_REG)
7875 passed_in_gprs = true;
7876 else
7877 ret = fpr;
7878 }
7879 }
7880
7881 if (passed_in_gprs
7882 && align_words < GP_ARG_NUM_REG
a7c81bc1 7883 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (arg.mode, arg.type))
1acf0246
BS		 7884 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
7885
7886 if (ret != 0 && TARGET_DEBUG_ARG)
7887 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
7888
7889 return ret;
7890}
7891\f
7892/* A C expression that indicates when an argument must be passed by
7893 reference. If nonzero for an argument, a copy of that argument is
7894 made in memory and a pointer to the argument is passed instead of
7895 the argument itself. The pointer is passed in whatever way is
7896 appropriate for passing a pointer to that type.
7897
7898 Under V.4, aggregates and long double are passed by reference.
7899
7900 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
7901 reference unless the AltiVec vector extension ABI is in force.
7902
7903 As an extension to all ABIs, variable sized types are passed by
7904 reference. */
7905
7906bool
52090e4d 7907rs6000_pass_by_reference (cumulative_args_t, const function_arg_info &arg)
1acf0246 7908{
52090e4d 7909 if (!arg.type)
1acf0246
BS		 7910 return 0;
7911
7912 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
52090e4d 7913 && FLOAT128_IEEE_P (TYPE_MODE (arg.type)))
1acf0246
BS		 7914 {
7915 if (TARGET_DEBUG_ARG)
7916 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
7917 return 1;
7918 }
7919
52090e4d 7920 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (arg.type))
1acf0246
BS		 7921 {
7922 if (TARGET_DEBUG_ARG)
7923 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
7924 return 1;
7925 }
7926
52090e4d 7927 if (int_size_in_bytes (arg.type) < 0)
1acf0246
BS		 7928 {
7929 if (TARGET_DEBUG_ARG)
7930 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
7931 return 1;
7932 }
7933
7934 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7935 modes only exist for GCC vector types if -maltivec. */
52090e4d 7936 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (arg.mode))
1acf0246
BS		 7937 {
7938 if (TARGET_DEBUG_ARG)
7939 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
7940 return 1;
7941 }
7942
7943 /* Pass synthetic vectors in memory. */
52090e4d
RS		 7944 if (TREE_CODE (arg.type) == VECTOR_TYPE
7945 && int_size_in_bytes (arg.type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
1acf0246
BS		 7946 {
7947 static bool warned_for_pass_big_vectors = false;
7948 if (TARGET_DEBUG_ARG)
7949 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
7950 if (!warned_for_pass_big_vectors)
7951 {
7952 warning (OPT_Wpsabi, "GCC vector passed by reference: "
7953 "non-standard ABI extension with no compatibility "
7954 "guarantee");
7955 warned_for_pass_big_vectors = true;
7956 }
7957 return 1;
7958 }
7959
7960 return 0;
7961}
7962
7963/* Process parameter of type TYPE after ARGS_SO_FAR parameters were
7964 already processes. Return true if the parameter must be passed
7965 (fully or partially) on the stack. */
7966
7967static bool
7968rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
7969{
1acf0246
BS		 7970 int unsignedp;
7971 rtx entry_parm;
7972
7973 /* Catch errors. */
7974 if (type == NULL || type == error_mark_node)
7975 return true;
7976
7977 /* Handle types with no storage requirement. */
7978 if (TYPE_MODE (type) == VOIDmode)
7979 return false;
7980
7981 /* Handle complex types. */
7982 if (TREE_CODE (type) == COMPLEX_TYPE)
7983 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
7984 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
7985
7986 /* Handle transparent aggregates. */
7987 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
7988 && TYPE_TRANSPARENT_AGGR (type))
7989 type = TREE_TYPE (first_field (type));
7990
7991 /* See if this arg was passed by invisible reference. */
b12cdd6e
RS		 7992 function_arg_info arg (type, /*named=*/true);
7993 apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg);
1acf0246
BS		 7994
7995 /* Find mode as it is passed by the ABI. */
7996 unsignedp = TYPE_UNSIGNED (type);
b12cdd6e 7997 arg.mode = promote_mode (arg.type, arg.mode, &unsignedp);
1acf0246
BS		 7998
7999 /* If we must pass in stack, we need a stack. */
0ffef200 8000 if (rs6000_must_pass_in_stack (arg))
1acf0246
BS		 8001 return true;
8002
8003 /* If there is no incoming register, we need a stack. */
6783fdb7 8004 entry_parm = rs6000_function_arg (args_so_far, arg);
1acf0246
BS		 8005 if (entry_parm == NULL)
8006 return true;
8007
8008 /* Likewise if we need to pass both in registers and on the stack. */
8009 if (GET_CODE (entry_parm) == PARALLEL
8010 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
8011 return true;
8012
8013 /* Also true if we're partially in registers and partially not. */
a7c81bc1 8014 if (rs6000_arg_partial_bytes (args_so_far, arg) != 0)
1acf0246
BS		 8015 return true;
8016
8017 /* Update info on where next arg arrives in registers. */
6930c98c 8018 rs6000_function_arg_advance (args_so_far, arg);
1acf0246
BS		 8019 return false;
8020}
8021
8022/* Return true if FUN has no prototype, has a variable argument
8023 list, or passes any parameter in memory. */
8024
8025static bool
8026rs6000_function_parms_need_stack (tree fun, bool incoming)
8027{
8028 tree fntype, result;
8029 CUMULATIVE_ARGS args_so_far_v;
8030 cumulative_args_t args_so_far;
8031
8032 if (!fun)
8033 /* Must be a libcall, all of which only use reg parms. */
8034 return false;
8035
8036 fntype = fun;
8037 if (!TYPE_P (fun))
8038 fntype = TREE_TYPE (fun);
8039
8040 /* Varargs functions need the parameter save area. */
8041 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
8042 return true;
8043
8044 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
8045 args_so_far = pack_cumulative_args (&args_so_far_v);
8046
8047 /* When incoming, we will have been passed the function decl.
8048 It is necessary to use the decl to handle K&R style functions,
8049 where TYPE_ARG_TYPES may not be available. */
8050 if (incoming)
8051 {
8052 gcc_assert (DECL_P (fun));
8053 result = DECL_RESULT (fun);
8054 }
8055 else
8056 result = TREE_TYPE (fntype);
8057
8058 if (result && aggregate_value_p (result, fntype))
8059 {
8060 if (!TYPE_P (result))
8061 result = TREE_TYPE (result);
8062 result = build_pointer_type (result);
8063 rs6000_parm_needs_stack (args_so_far, result);
8064 }
8065
8066 if (incoming)
8067 {
8068 tree parm;
8069
8070 for (parm = DECL_ARGUMENTS (fun);
8071 parm && parm != void_list_node;
8072 parm = TREE_CHAIN (parm))
8073 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
8074 return true;
8075 }
8076 else
8077 {
8078 function_args_iterator args_iter;
8079 tree arg_type;
8080
8081 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
8082 if (rs6000_parm_needs_stack (args_so_far, arg_type))
8083 return true;
8084 }
8085
8086 return false;
8087}
8088
8089/* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
8090 usually a constant depending on the ABI. However, in the ELFv2 ABI
8091 the register parameter area is optional when calling a function that
8092 has a prototype is scope, has no variable argument list, and passes
8093 all parameters in registers. */
8094
8095int
8096rs6000_reg_parm_stack_space (tree fun, bool incoming)
8097{
8098 int reg_parm_stack_space;
8099
8100 switch (DEFAULT_ABI)
8101 {
8102 default:
8103 reg_parm_stack_space = 0;
8104 break;
8105
8106 case ABI_AIX:
8107 case ABI_DARWIN:
8108 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
8109 break;
8110
8111 case ABI_ELFv2:
8112 /* ??? Recomputing this every time is a bit expensive. Is there
8113 a place to cache this information? */
8114 if (rs6000_function_parms_need_stack (fun, incoming))
8115 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
8116 else
8117 reg_parm_stack_space = 0;
8118 break;
8119 }
8120
8121 return reg_parm_stack_space;
8122}
8123
8124static void
8125rs6000_move_block_from_reg (int regno, rtx x, int nregs)
8126{
8127 int i;
8128 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
8129
8130 if (nregs == 0)
8131 return;
8132
8133 for (i = 0; i < nregs; i++)
8134 {
8135 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
8136 if (reload_completed)
8137 {
8138 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
8139 tem = NULL_RTX;
8140 else
8141 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
8142 i * GET_MODE_SIZE (reg_mode));
8143 }
8144 else
8145 tem = replace_equiv_address (tem, XEXP (tem, 0));
8146
8147 gcc_assert (tem);
8148
8149 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
8150 }
8151}
8152\f
8153/* Perform any needed actions needed for a function that is receiving a
8154 variable number of arguments.
8155
8156 CUM is as above.
8157
e7056ca4 8158 ARG is the last named argument.
1acf0246
BS		 8159
8160 PRETEND_SIZE is a variable that should be set to the amount of stack
8161 that must be pushed by the prolog to pretend that our caller pushed
8162 it.
8163
8164 Normally, this macro will push all remaining incoming registers on the
8165 stack and set PRETEND_SIZE to the length of the registers pushed. */
8166
8167void
e7056ca4
RS		 8168setup_incoming_varargs (cumulative_args_t cum,
8169 const function_arg_info &arg,
8170 int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
1acf0246
BS		 8171{
8172 CUMULATIVE_ARGS next_cum;
8173 int reg_size = TARGET_32BIT ? 4 : 8;
8174 rtx save_area = NULL_RTX, mem;
8175 int first_reg_offset;
8176 alias_set_type set;
8177
8178 /* Skip the last named argument. */
8179 next_cum = *get_cumulative_args (cum);
e7056ca4 8180 rs6000_function_arg_advance_1 (&next_cum, arg.mode, arg.type, arg.named, 0);
1acf0246
BS		 8181
8182 if (DEFAULT_ABI == ABI_V4)
8183 {
8184 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
8185
8186 if (! no_rtl)
8187 {
8188 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
8189 HOST_WIDE_INT offset = 0;
8190
8191 /* Try to optimize the size of the varargs save area.
8192 The ABI requires that ap.reg_save_area is doubleword
8193 aligned, but we don't need to allocate space for all
8194 the bytes, only those to which we actually will save
8195 anything. */
8196 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
8197 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
8198 if (TARGET_HARD_FLOAT
8199 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8200 && cfun->va_list_fpr_size)
8201 {
8202 if (gpr_reg_num)
8203 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
8204 * UNITS_PER_FP_WORD;
8205 if (cfun->va_list_fpr_size
8206 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8207 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
8208 else
8209 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8210 * UNITS_PER_FP_WORD;
8211 }
8212 if (gpr_reg_num)
8213 {
8214 offset = -((first_reg_offset * reg_size) & ~7);
8215 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
8216 {
8217 gpr_reg_num = cfun->va_list_gpr_size;
8218 if (reg_size == 4 && (first_reg_offset & 1))
8219 gpr_reg_num++;
8220 }
8221 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
8222 }
8223 else if (fpr_size)
8224 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
8225 * UNITS_PER_FP_WORD
8226 - (int) (GP_ARG_NUM_REG * reg_size);
8227
8228 if (gpr_size + fpr_size)
8229 {
8230 rtx reg_save_area
8231 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
8232 gcc_assert (MEM_P (reg_save_area));
8233 reg_save_area = XEXP (reg_save_area, 0);
8234 if (GET_CODE (reg_save_area) == PLUS)
8235 {
8236 gcc_assert (XEXP (reg_save_area, 0)
8237 == virtual_stack_vars_rtx);
8238 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
8239 offset += INTVAL (XEXP (reg_save_area, 1));
8240 }
8241 else
8242 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
8243 }
8244
8245 cfun->machine->varargs_save_offset = offset;
8246 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
8247 }
8248 }
8249 else
8250 {
8251 first_reg_offset = next_cum.words;
8252 save_area = crtl->args.internal_arg_pointer;
8253
0ffef200 8254 if (targetm.calls.must_pass_in_stack (arg))
e7056ca4 8255 first_reg_offset += rs6000_arg_size (TYPE_MODE (arg.type), arg.type);
1acf0246
BS		 8256 }
8257
8258 set = get_varargs_alias_set ();
8259 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
8260 && cfun->va_list_gpr_size)
8261 {
8262 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
8263
8264 if (va_list_gpr_counter_field)
8265 /* V4 va_list_gpr_size counts number of registers needed. */
8266 n_gpr = cfun->va_list_gpr_size;
8267 else
8268 /* char * va_list instead counts number of bytes needed. */
8269 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
8270
8271 if (nregs > n_gpr)
8272 nregs = n_gpr;
8273
8274 mem = gen_rtx_MEM (BLKmode,
8275 plus_constant (Pmode, save_area,
8276 first_reg_offset * reg_size));
8277 MEM_NOTRAP_P (mem) = 1;
8278 set_mem_alias_set (mem, set);
8279 set_mem_align (mem, BITS_PER_WORD);
8280
8281 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
8282 nregs);
8283 }
8284
8285 /* Save FP registers if needed. */
8286 if (DEFAULT_ABI == ABI_V4
8287 && TARGET_HARD_FLOAT
8288 && ! no_rtl
8289 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8290 && cfun->va_list_fpr_size)
8291 {
8292 int fregno = next_cum.fregno, nregs;
8293 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
8294 rtx lab = gen_label_rtx ();
8295 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
8296 * UNITS_PER_FP_WORD);
8297
8298 emit_jump_insn
8299 (gen_rtx_SET (pc_rtx,
8300 gen_rtx_IF_THEN_ELSE (VOIDmode,
8301 gen_rtx_NE (VOIDmode, cr1,
8302 const0_rtx),
8303 gen_rtx_LABEL_REF (VOIDmode, lab),
8304 pc_rtx)));
8305
8306 for (nregs = 0;
8307 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
8308 fregno++, off += UNITS_PER_FP_WORD, nregs++)
8309 {
8310 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
8311 plus_constant (Pmode, save_area, off));
8312 MEM_NOTRAP_P (mem) = 1;
8313 set_mem_alias_set (mem, set);
8314 set_mem_align (mem, GET_MODE_ALIGNMENT (
8315 TARGET_HARD_FLOAT ? DFmode : SFmode));
8316 emit_move_insn (mem, gen_rtx_REG (
8317 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
8318 }
8319
8320 emit_label (lab);
8321 }
8322}
8323
8324/* Create the va_list data type. */
8325
8326tree
8327rs6000_build_builtin_va_list (void)
8328{
8329 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
8330
8331 /* For AIX, prefer 'char *' because that's what the system
8332 header files like. */
8333 if (DEFAULT_ABI != ABI_V4)
8334 return build_pointer_type (char_type_node);
8335
8336 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
8337 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
8338 get_identifier ("__va_list_tag"), record);
8339
8340 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
8341 unsigned_char_type_node);
8342 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
8343 unsigned_char_type_node);
8344 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
8345 every user file. */
8346 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8347 get_identifier ("reserved"), short_unsigned_type_node);
8348 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8349 get_identifier ("overflow_arg_area"),
8350 ptr_type_node);
8351 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8352 get_identifier ("reg_save_area"),
8353 ptr_type_node);
8354
8355 va_list_gpr_counter_field = f_gpr;
8356 va_list_fpr_counter_field = f_fpr;
8357
8358 DECL_FIELD_CONTEXT (f_gpr) = record;
8359 DECL_FIELD_CONTEXT (f_fpr) = record;
8360 DECL_FIELD_CONTEXT (f_res) = record;
8361 DECL_FIELD_CONTEXT (f_ovf) = record;
8362 DECL_FIELD_CONTEXT (f_sav) = record;
8363
8364 TYPE_STUB_DECL (record) = type_decl;
8365 TYPE_NAME (record) = type_decl;
8366 TYPE_FIELDS (record) = f_gpr;
8367 DECL_CHAIN (f_gpr) = f_fpr;
8368 DECL_CHAIN (f_fpr) = f_res;
8369 DECL_CHAIN (f_res) = f_ovf;
8370 DECL_CHAIN (f_ovf) = f_sav;
8371
8372 layout_type (record);
8373
8374 /* The correct type is an array type of one element. */
8375 return build_array_type (record, build_index_type (size_zero_node));
8376}
8377
8378/* Implement va_start. */
8379
8380void
8381rs6000_va_start (tree valist, rtx nextarg)
8382{
8383 HOST_WIDE_INT words, n_gpr, n_fpr;
8384 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
8385 tree gpr, fpr, ovf, sav, t;
8386
8387 /* Only SVR4 needs something special. */
8388 if (DEFAULT_ABI != ABI_V4)
8389 {
8390 std_expand_builtin_va_start (valist, nextarg);
8391 return;
8392 }
8393
8394 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8395 f_fpr = DECL_CHAIN (f_gpr);
8396 f_res = DECL_CHAIN (f_fpr);
8397 f_ovf = DECL_CHAIN (f_res);
8398 f_sav = DECL_CHAIN (f_ovf);
8399
8400 valist = build_simple_mem_ref (valist);
8401 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8402 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
8403 f_fpr, NULL_TREE);
8404 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
8405 f_ovf, NULL_TREE);
8406 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
8407 f_sav, NULL_TREE);
8408
8409 /* Count number of gp and fp argument registers used. */
8410 words = crtl->args.info.words;
8411 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
8412 GP_ARG_NUM_REG);
8413 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
8414 FP_ARG_NUM_REG);
8415
8416 if (TARGET_DEBUG_ARG)
8417 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
8418 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
8419 words, n_gpr, n_fpr);
8420
8421 if (cfun->va_list_gpr_size)
8422 {
8423 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8424 build_int_cst (NULL_TREE, n_gpr));
8425 TREE_SIDE_EFFECTS (t) = 1;
8426 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8427 }
8428
8429 if (cfun->va_list_fpr_size)
8430 {
8431 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8432 build_int_cst (NULL_TREE, n_fpr));
8433 TREE_SIDE_EFFECTS (t) = 1;
8434 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8435
8436#ifdef HAVE_AS_GNU_ATTRIBUTE
8437 if (call_ABI_of_interest (cfun->decl))
8438 rs6000_passes_float = true;
8439#endif
8440 }
8441
8442 /* Find the overflow area. */
8443 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
8444 if (words != 0)
8445 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
8446 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8447 TREE_SIDE_EFFECTS (t) = 1;
8448 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8449
8450 /* If there were no va_arg invocations, don't set up the register
8451 save area. */
8452 if (!cfun->va_list_gpr_size
8453 && !cfun->va_list_fpr_size
8454 && n_gpr < GP_ARG_NUM_REG
8455 && n_fpr < FP_ARG_V4_MAX_REG)
8456 return;
8457
8458 /* Find the register save area. */
8459 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
8460 if (cfun->machine->varargs_save_offset)
8461 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
8462 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8463 TREE_SIDE_EFFECTS (t) = 1;
8464 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8465}
8466
8467/* Implement va_arg. */
8468
8469tree
8470rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8471 gimple_seq *post_p)
8472{
8473 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
8474 tree gpr, fpr, ovf, sav, reg, t, u;
8475 int size, rsize, n_reg, sav_ofs, sav_scale;
8476 tree lab_false, lab_over, addr;
8477 int align;
8478 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
8479 int regalign = 0;
8480 gimple *stmt;
8481
fde65a89 8482 if (pass_va_arg_by_reference (type))
1acf0246
BS		 8483 {
8484 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
8485 return build_va_arg_indirect_ref (t);
8486 }
8487
8488 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
8489 earlier version of gcc, with the property that it always applied alignment
8490 adjustments to the va-args (even for zero-sized types). The cheapest way
8491 to deal with this is to replicate the effect of the part of
8492 std_gimplify_va_arg_expr that carries out the align adjust, for the case
8493 of relevance.
8494 We don't need to check for pass-by-reference because of the test above.
8495 We can return a simplifed answer, since we know there's no offset to add. */
8496
8497 if (((TARGET_MACHO
8498 && rs6000_darwin64_abi)
8499 || DEFAULT_ABI == ABI_ELFv2
8500 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
8501 && integer_zerop (TYPE_SIZE (type)))
8502 {
8503 unsigned HOST_WIDE_INT align, boundary;
8504 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
8505 align = PARM_BOUNDARY / BITS_PER_UNIT;
8506 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
8507 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
8508 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
8509 boundary /= BITS_PER_UNIT;
8510 if (boundary > align)
8511 {
8512 tree t ;
8513 /* This updates arg ptr by the amount that would be necessary
8514 to align the zero-sized (but not zero-alignment) item. */
8515 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
8516 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
8517 gimplify_and_add (t, pre_p);
8518
8519 t = fold_convert (sizetype, valist_tmp);
8520 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
8521 fold_convert (TREE_TYPE (valist),
8522 fold_build2 (BIT_AND_EXPR, sizetype, t,
8523 size_int (-boundary))));
8524 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
8525 gimplify_and_add (t, pre_p);
8526 }
8527 /* Since it is zero-sized there's no increment for the item itself. */
8528 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
8529 return build_va_arg_indirect_ref (valist_tmp);
8530 }
8531
8532 if (DEFAULT_ABI != ABI_V4)
8533 {
8534 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
8535 {
8536 tree elem_type = TREE_TYPE (type);
8537 machine_mode elem_mode = TYPE_MODE (elem_type);
8538 int elem_size = GET_MODE_SIZE (elem_mode);
8539
8540 if (elem_size < UNITS_PER_WORD)
8541 {
8542 tree real_part, imag_part;
8543 gimple_seq post = NULL;
8544
8545 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
8546 &post);
8547 /* Copy the value into a temporary, lest the formal temporary
8548 be reused out from under us. */
8549 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
8550 gimple_seq_add_seq (pre_p, post);
8551
8552 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
8553 post_p);
8554
8555 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
8556 }
8557 }
8558
8559 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
8560 }
8561
8562 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8563 f_fpr = DECL_CHAIN (f_gpr);
8564 f_res = DECL_CHAIN (f_fpr);
8565 f_ovf = DECL_CHAIN (f_res);
8566 f_sav = DECL_CHAIN (f_ovf);
8567
8568 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8569 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
8570 f_fpr, NULL_TREE);
8571 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
8572 f_ovf, NULL_TREE);
8573 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
8574 f_sav, NULL_TREE);
8575
8576 size = int_size_in_bytes (type);
8577 rsize = (size + 3) / 4;
8578 int pad = 4 * rsize - size;
8579 align = 1;
8580
8581 machine_mode mode = TYPE_MODE (type);
8582 if (abi_v4_pass_in_fpr (mode, false))
8583 {
8584 /* FP args go in FP registers, if present. */
8585 reg = fpr;
8586 n_reg = (size + 7) / 8;
8587 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
8588 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
8589 if (mode != SFmode && mode != SDmode)
8590 align = 8;
8591 }
8592 else
8593 {
8594 /* Otherwise into GP registers. */
8595 reg = gpr;
8596 n_reg = rsize;
8597 sav_ofs = 0;
8598 sav_scale = 4;
8599 if (n_reg == 2)
8600 align = 8;
8601 }
8602
8603 /* Pull the value out of the saved registers.... */
8604
8605 lab_over = NULL;
8606 addr = create_tmp_var (ptr_type_node, "addr");
8607
8608 /* AltiVec vectors never go in registers when -mabi=altivec. */
8609 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8610 align = 16;
8611 else
8612 {
8613 lab_false = create_artificial_label (input_location);
8614 lab_over = create_artificial_label (input_location);
8615
8616 /* Long long is aligned in the registers. As are any other 2 gpr
8617 item such as complex int due to a historical mistake. */
8618 u = reg;
8619 if (n_reg == 2 && reg == gpr)
8620 {
8621 regalign = 1;
8622 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8623 build_int_cst (TREE_TYPE (reg), n_reg - 1));
8624 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
8625 unshare_expr (reg), u);
8626 }
8627 /* _Decimal128 is passed in even/odd fpr pairs; the stored
8628 reg number is 0 for f1, so we want to make it odd. */
8629 else if (reg == fpr && mode == TDmode)
8630 {
8631 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8632 build_int_cst (TREE_TYPE (reg), 1));
8633 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
8634 }
8635
8636 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
8637 t = build2 (GE_EXPR, boolean_type_node, u, t);
8638 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8639 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8640 gimplify_and_add (t, pre_p);
8641
8642 t = sav;
8643 if (sav_ofs)
8644 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
8645
8646 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8647 build_int_cst (TREE_TYPE (reg), n_reg));
8648 u = fold_convert (sizetype, u);
8649 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
8650 t = fold_build_pointer_plus (t, u);
8651
8652 /* _Decimal32 varargs are located in the second word of the 64-bit
8653 FP register for 32-bit binaries. */
8654 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
8655 t = fold_build_pointer_plus_hwi (t, size);
8656
8657 /* Args are passed right-aligned. */
8658 if (BYTES_BIG_ENDIAN)
8659 t = fold_build_pointer_plus_hwi (t, pad);
8660
8661 gimplify_assign (addr, t, pre_p);
8662
8663 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8664
8665 stmt = gimple_build_label (lab_false);
8666 gimple_seq_add_stmt (pre_p, stmt);
8667
8668 if ((n_reg == 2 && !regalign) || n_reg > 2)
8669 {
8670 /* Ensure that we don't find any more args in regs.
8671 Alignment has taken care of for special cases. */
8672 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
8673 }
8674 }
8675
8676 /* ... otherwise out of the overflow area. */
8677
8678 /* Care for on-stack alignment if needed. */
8679 t = ovf;
8680 if (align != 1)
8681 {
8682 t = fold_build_pointer_plus_hwi (t, align - 1);
8683 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
8684 build_int_cst (TREE_TYPE (t), -align));
8685 }
8686
8687 /* Args are passed right-aligned. */
8688 if (BYTES_BIG_ENDIAN)
8689 t = fold_build_pointer_plus_hwi (t, pad);
8690
8691 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8692
8693 gimplify_assign (unshare_expr (addr), t, pre_p);
8694
8695 t = fold_build_pointer_plus_hwi (t, size);
8696 gimplify_assign (unshare_expr (ovf), t, pre_p);
8697
8698 if (lab_over)
8699 {
8700 stmt = gimple_build_label (lab_over);
8701 gimple_seq_add_stmt (pre_p, stmt);
8702 }
8703
8704 if (STRICT_ALIGNMENT
8705 && (TYPE_ALIGN (type)
8706 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
8707 {
8708 /* The value (of type complex double, for example) may not be
8709 aligned in memory in the saved registers, so copy via a
8710 temporary. (This is the same code as used for SPARC.) */
8711 tree tmp = create_tmp_var (type, "va_arg_tmp");
8712 tree dest_addr = build_fold_addr_expr (tmp);
8713
8714 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
8715 3, dest_addr, addr, size_int (rsize * 4));
8716 TREE_ADDRESSABLE (tmp) = 1;
8717
8718 gimplify_and_add (copy, pre_p);
8719 addr = dest_addr;
8720 }
8721
8722 addr = fold_convert (ptrtype, addr);
8723 return build_va_arg_indirect_ref (addr);
8724}
8725
8726/* Builtins. */
8727
8728static void
8729def_builtin (const char *name, tree type, enum rs6000_builtins code)
8730{
8731 tree t;
8732 unsigned classify = rs6000_builtin_info[(int)code].attr;
8733 const char *attr_string = "";
8734
a92cc0da
PB		 8735 /* Don't define the builtin if it doesn't have a type. See PR92661. */
8736 if (type == NULL_TREE)
8737 return;
8738
1acf0246
BS		 8739 gcc_assert (name != NULL);
8740 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
8741
8742 if (rs6000_builtin_decls[(int)code])
8743 fatal_error (input_location,
8744 "internal error: builtin function %qs already processed",
8745 name);
8746
8747 rs6000_builtin_decls[(int)code] = t =
8748 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
8749
8750 /* Set any special attributes. */
8751 if ((classify & RS6000_BTC_CONST) != 0)
8752 {
8753 /* const function, function only depends on the inputs. */
8754 TREE_READONLY (t) = 1;
8755 TREE_NOTHROW (t) = 1;
8756 attr_string = ", const";
8757 }
8758 else if ((classify & RS6000_BTC_PURE) != 0)
8759 {
8760 /* pure function, function can read global memory, but does not set any
8761 external state. */
8762 DECL_PURE_P (t) = 1;
8763 TREE_NOTHROW (t) = 1;
8764 attr_string = ", pure";
8765 }
8766 else if ((classify & RS6000_BTC_FP) != 0)
8767 {
8768 /* Function is a math function. If rounding mode is on, then treat the
8769 function as not reading global memory, but it can have arbitrary side
8770 effects. If it is off, then assume the function is a const function.
8771 This mimics the ATTR_MATHFN_FPROUNDING attribute in
8772 builtin-attribute.def that is used for the math functions. */
8773 TREE_NOTHROW (t) = 1;
8774 if (flag_rounding_math)
8775 {
8776 DECL_PURE_P (t) = 1;
8777 DECL_IS_NOVOPS (t) = 1;
8778 attr_string = ", fp, pure";
8779 }
8780 else
8781 {
8782 TREE_READONLY (t) = 1;
8783 attr_string = ", fp, const";
8784 }
8785 }
8ee2640b
PB		 8786 else if ((classify & (RS6000_BTC_QUAD | RS6000_BTC_PAIR)) != 0)
8787 /* The function uses a register quad and/or pair. Nothing to do. */
8788 ;
1acf0246
BS		 8789 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
8790 gcc_unreachable ();
8791
8792 if (TARGET_DEBUG_BUILTIN)
8793 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
8794 (int)code, name, attr_string);
8795}
8796
8797/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
8798
8799#undef RS6000_BUILTIN_0
8800#undef RS6000_BUILTIN_1
8801#undef RS6000_BUILTIN_2
8802#undef RS6000_BUILTIN_3
840ac85c 8803#undef RS6000_BUILTIN_4
1acf0246
BS		 8804#undef RS6000_BUILTIN_A
8805#undef RS6000_BUILTIN_D
8806#undef RS6000_BUILTIN_H
8ee2640b 8807#undef RS6000_BUILTIN_M
1acf0246
BS		 8808#undef RS6000_BUILTIN_P
8809#undef RS6000_BUILTIN_X
8810
8811#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8812#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8813#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8814#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
8815 { MASK, ICODE, NAME, ENUM },
8816
840ac85c 8817#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8818#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8819#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8820#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8821#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8822#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8823#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8824
8825static const struct builtin_description bdesc_3arg[] =
8826{
8827#include "rs6000-builtin.def"
8828};
8829
840ac85c
KN		 8830/* Simple quaternary operations: VECd = foo (VECa, VECb, VECc, VECd). */
8831
8832#undef RS6000_BUILTIN_0
8833#undef RS6000_BUILTIN_1
8834#undef RS6000_BUILTIN_2
8835#undef RS6000_BUILTIN_3
8836#undef RS6000_BUILTIN_4
8837#undef RS6000_BUILTIN_A
8838#undef RS6000_BUILTIN_D
8839#undef RS6000_BUILTIN_H
8ee2640b 8840#undef RS6000_BUILTIN_M
840ac85c
KN		 8841#undef RS6000_BUILTIN_P
8842#undef RS6000_BUILTIN_X
8843
8844#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8845#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8846#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8847#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
8848#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) \
8849 { MASK, ICODE, NAME, ENUM },
8850
8851#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8852#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8853#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8854#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c
KN		 8855#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8856#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8857
8858static const struct builtin_description bdesc_4arg[] =
8859{
8860#include "rs6000-builtin.def"
8861};
8862
1acf0246
BS		 8863/* DST operations: void foo (void *, const int, const char). */
8864
8865#undef RS6000_BUILTIN_0
8866#undef RS6000_BUILTIN_1
8867#undef RS6000_BUILTIN_2
8868#undef RS6000_BUILTIN_3
840ac85c 8869#undef RS6000_BUILTIN_4
1acf0246
BS		 8870#undef RS6000_BUILTIN_A
8871#undef RS6000_BUILTIN_D
8872#undef RS6000_BUILTIN_H
8ee2640b 8873#undef RS6000_BUILTIN_M
1acf0246
BS		 8874#undef RS6000_BUILTIN_P
8875#undef RS6000_BUILTIN_X
8876
8877#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8878#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8879#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8880#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8881#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8882#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8883#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
8884 { MASK, ICODE, NAME, ENUM },
8885
8886#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8887#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8888#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8889#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8890
8891static const struct builtin_description bdesc_dst[] =
8892{
8893#include "rs6000-builtin.def"
8894};
8895
8896/* Simple binary operations: VECc = foo (VECa, VECb). */
8897
8898#undef RS6000_BUILTIN_0
8899#undef RS6000_BUILTIN_1
8900#undef RS6000_BUILTIN_2
8901#undef RS6000_BUILTIN_3
840ac85c 8902#undef RS6000_BUILTIN_4
1acf0246
BS		 8903#undef RS6000_BUILTIN_A
8904#undef RS6000_BUILTIN_D
8905#undef RS6000_BUILTIN_H
8ee2640b 8906#undef RS6000_BUILTIN_M
1acf0246
BS		 8907#undef RS6000_BUILTIN_P
8908#undef RS6000_BUILTIN_X
8909
8910#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8911#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8912#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
8913 { MASK, ICODE, NAME, ENUM },
8914
8915#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8916#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8917#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8918#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8919#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8920#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8921#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8922#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8923
8924static const struct builtin_description bdesc_2arg[] =
8925{
8926#include "rs6000-builtin.def"
8927};
8928
8929#undef RS6000_BUILTIN_0
8930#undef RS6000_BUILTIN_1
8931#undef RS6000_BUILTIN_2
8932#undef RS6000_BUILTIN_3
840ac85c 8933#undef RS6000_BUILTIN_4
1acf0246
BS		 8934#undef RS6000_BUILTIN_A
8935#undef RS6000_BUILTIN_D
8936#undef RS6000_BUILTIN_H
8ee2640b 8937#undef RS6000_BUILTIN_M
1acf0246
BS		 8938#undef RS6000_BUILTIN_P
8939#undef RS6000_BUILTIN_X
8940
8941#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8942#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8943#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8944#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8945#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8946#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
8947#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8948#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8949#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8950#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
8951 { MASK, ICODE, NAME, ENUM },
8952
8953#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8954
8955/* AltiVec predicates. */
8956
8957static const struct builtin_description bdesc_altivec_preds[] =
8958{
8959#include "rs6000-builtin.def"
8960};
8961
8962/* ABS* operations. */
8963
8964#undef RS6000_BUILTIN_0
8965#undef RS6000_BUILTIN_1
8966#undef RS6000_BUILTIN_2
8967#undef RS6000_BUILTIN_3
840ac85c 8968#undef RS6000_BUILTIN_4
1acf0246
BS		 8969#undef RS6000_BUILTIN_A
8970#undef RS6000_BUILTIN_D
8971#undef RS6000_BUILTIN_H
8ee2640b 8972#undef RS6000_BUILTIN_M
1acf0246
BS		 8973#undef RS6000_BUILTIN_P
8974#undef RS6000_BUILTIN_X
8975
8976#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8977#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8978#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8979#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 8980#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8981#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
8982 { MASK, ICODE, NAME, ENUM },
8983
8984#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
8985#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 8986#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 8987#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
8988#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
8989
8990static const struct builtin_description bdesc_abs[] =
8991{
8992#include "rs6000-builtin.def"
8993};
8994
8995/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
8996 foo (VECa). */
8997
8998#undef RS6000_BUILTIN_0
8999#undef RS6000_BUILTIN_1
9000#undef RS6000_BUILTIN_2
9001#undef RS6000_BUILTIN_3
840ac85c 9002#undef RS6000_BUILTIN_4
1acf0246
BS		 9003#undef RS6000_BUILTIN_A
9004#undef RS6000_BUILTIN_D
9005#undef RS6000_BUILTIN_H
8ee2640b 9006#undef RS6000_BUILTIN_M
1acf0246
BS		 9007#undef RS6000_BUILTIN_P
9008#undef RS6000_BUILTIN_X
9009
9010#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9011#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9012 { MASK, ICODE, NAME, ENUM },
9013
9014#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9015#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 9016#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 9017#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9018#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9019#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 9020#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 9021#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9022#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9023
9024static const struct builtin_description bdesc_1arg[] =
9025{
9026#include "rs6000-builtin.def"
9027};
9028
9029/* Simple no-argument operations: result = __builtin_darn_32 () */
9030
9031#undef RS6000_BUILTIN_0
9032#undef RS6000_BUILTIN_1
9033#undef RS6000_BUILTIN_2
9034#undef RS6000_BUILTIN_3
840ac85c 9035#undef RS6000_BUILTIN_4
1acf0246
BS		 9036#undef RS6000_BUILTIN_A
9037#undef RS6000_BUILTIN_D
9038#undef RS6000_BUILTIN_H
8ee2640b 9039#undef RS6000_BUILTIN_M
1acf0246
BS		 9040#undef RS6000_BUILTIN_P
9041#undef RS6000_BUILTIN_X
9042
9043#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
9044 { MASK, ICODE, NAME, ENUM },
9045
9046#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9047#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9048#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 9049#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 9050#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9051#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9052#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
8ee2640b 9053#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 9054#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9055#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9056
9057static const struct builtin_description bdesc_0arg[] =
9058{
9059#include "rs6000-builtin.def"
9060};
9061
9062/* HTM builtins. */
9063#undef RS6000_BUILTIN_0
9064#undef RS6000_BUILTIN_1
9065#undef RS6000_BUILTIN_2
9066#undef RS6000_BUILTIN_3
840ac85c 9067#undef RS6000_BUILTIN_4
1acf0246
BS		 9068#undef RS6000_BUILTIN_A
9069#undef RS6000_BUILTIN_D
9070#undef RS6000_BUILTIN_H
8ee2640b 9071#undef RS6000_BUILTIN_M
1acf0246
BS		 9072#undef RS6000_BUILTIN_P
9073#undef RS6000_BUILTIN_X
9074
9075#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9076#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9077#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9078#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
840ac85c 9079#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 9080#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9081#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9082#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
9083 { MASK, ICODE, NAME, ENUM },
9084
8ee2640b 9085#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
1acf0246
BS		 9086#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9087#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9088
9089static const struct builtin_description bdesc_htm[] =
9090{
9091#include "rs6000-builtin.def"
9092};
9093
8ee2640b 9094/* MMA builtins. */
1acf0246
BS		 9095#undef RS6000_BUILTIN_0
9096#undef RS6000_BUILTIN_1
9097#undef RS6000_BUILTIN_2
9098#undef RS6000_BUILTIN_3
840ac85c 9099#undef RS6000_BUILTIN_4
1acf0246
BS		 9100#undef RS6000_BUILTIN_A
9101#undef RS6000_BUILTIN_D
9102#undef RS6000_BUILTIN_H
8ee2640b 9103#undef RS6000_BUILTIN_M
1acf0246 9104#undef RS6000_BUILTIN_P
8ee2640b
PB		 9105#undef RS6000_BUILTIN_X
9106
9107#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9108#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9109#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9110#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9111#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9112#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9113#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9114#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9115#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \
9116 { MASK, ICODE, NAME, ENUM },
9117
9118#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9119#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9120
9121static const struct builtin_description bdesc_mma[] =
9122{
9123#include "rs6000-builtin.def"
9124};
9125
9126#undef RS6000_BUILTIN_0
9127#undef RS6000_BUILTIN_1
9128#undef RS6000_BUILTIN_2
9129#undef RS6000_BUILTIN_3
9130#undef RS6000_BUILTIN_4
9131#undef RS6000_BUILTIN_A
9132#undef RS6000_BUILTIN_D
9133#undef RS6000_BUILTIN_H
9134#undef RS6000_BUILTIN_M
9135#undef RS6000_BUILTIN_P
9136#undef RS6000_BUILTIN_X
1acf0246
BS		 9137
9138/* Return true if a builtin function is overloaded. */
9139bool
9140rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
9141{
9142 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
9143}
9144
9145const char *
9146rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
9147{
9148 return rs6000_builtin_info[(int)fncode].name;
9149}
9150
9151/* Expand an expression EXP that calls a builtin without arguments. */
9152static rtx
9153rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
9154{
9155 rtx pat;
9156 machine_mode tmode = insn_data[icode].operand[0].mode;
9157
9158 if (icode == CODE_FOR_nothing)
9159 /* Builtin not supported on this processor. */
9160 return 0;
9161
9162 if (icode == CODE_FOR_rs6000_mffsl
9163 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
9164 {
9165 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
9166 return const0_rtx;
9167 }
9168
9169 if (target == 0
9170 || GET_MODE (target) != tmode
9171 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9172 target = gen_reg_rtx (tmode);
9173
9174 pat = GEN_FCN (icode) (target);
9175 if (! pat)
9176 return 0;
9177 emit_insn (pat);
9178
9179 return target;
9180}
9181
9182
9183static rtx
9184rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
9185{
9186 rtx pat;
9187 tree arg0 = CALL_EXPR_ARG (exp, 0);
9188 tree arg1 = CALL_EXPR_ARG (exp, 1);
9189 rtx op0 = expand_normal (arg0);
9190 rtx op1 = expand_normal (arg1);
9191 machine_mode mode0 = insn_data[icode].operand[0].mode;
9192 machine_mode mode1 = insn_data[icode].operand[1].mode;
9193
9194 if (icode == CODE_FOR_nothing)
9195 /* Builtin not supported on this processor. */
9196 return 0;
9197
9198 /* If we got invalid arguments bail out before generating bad rtl. */
9199 if (arg0 == error_mark_node || arg1 == error_mark_node)
9200 return const0_rtx;
9201
9202 if (!CONST_INT_P (op0)
9203 || INTVAL (op0) > 255
9204 || INTVAL (op0) < 0)
9205 {
9206 error ("argument 1 must be an 8-bit field value");
9207 return const0_rtx;
9208 }
9209
9210 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
9211 op0 = copy_to_mode_reg (mode0, op0);
9212
9213 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
9214 op1 = copy_to_mode_reg (mode1, op1);
9215
9216 pat = GEN_FCN (icode) (op0, op1);
9217 if (!pat)
9218 return const0_rtx;
9219 emit_insn (pat);
9220
9221 return NULL_RTX;
9222}
9223
9224static rtx
9225rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
9226{
9227 rtx pat;
9228 tree arg0 = CALL_EXPR_ARG (exp, 0);
9229 rtx op0 = expand_normal (arg0);
9230
9231 if (icode == CODE_FOR_nothing)
9232 /* Builtin not supported on this processor. */
9233 return 0;
9234
9235 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
9236 {
9237 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
9238 "%<-msoft-float%>");
9239 return const0_rtx;
9240 }
9241
9242 /* If we got invalid arguments bail out before generating bad rtl. */
9243 if (arg0 == error_mark_node)
9244 return const0_rtx;
9245
9246 /* Only allow bit numbers 0 to 31. */
9247 if (!u5bit_cint_operand (op0, VOIDmode))
9248 {
9249 error ("Argument must be a constant between 0 and 31.");
9250 return const0_rtx;
9251 }
9252
9253 pat = GEN_FCN (icode) (op0);
9254 if (!pat)
9255 return const0_rtx;
9256 emit_insn (pat);
9257
9258 return NULL_RTX;
9259}
9260
9261static rtx
9262rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
9263{
9264 rtx pat;
9265 tree arg0 = CALL_EXPR_ARG (exp, 0);
9266 rtx op0 = expand_normal (arg0);
9267 machine_mode mode0 = insn_data[icode].operand[0].mode;
9268
9269 if (icode == CODE_FOR_nothing)
9270 /* Builtin not supported on this processor. */
9271 return 0;
9272
9273 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
9274 {
9275 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
9276 return const0_rtx;
9277 }
9278
9279 /* If we got invalid arguments bail out before generating bad rtl. */
9280 if (arg0 == error_mark_node)
9281 return const0_rtx;
9282
9283 /* If the argument is a constant, check the range. Argument can only be a
9284 2-bit value. Unfortunately, can't check the range of the value at
9285 compile time if the argument is a variable. The least significant two
9286 bits of the argument, regardless of type, are used to set the rounding
9287 mode. All other bits are ignored. */
9288 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
9289 {
9290 error ("Argument must be a value between 0 and 3.");
9291 return const0_rtx;
9292 }
9293
9294 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
9295 op0 = copy_to_mode_reg (mode0, op0);
9296
9297 pat = GEN_FCN (icode) (op0);
9298 if (!pat)
9299 return const0_rtx;
9300 emit_insn (pat);
9301
9302 return NULL_RTX;
9303}
9304static rtx
9305rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
9306{
9307 rtx pat;
9308 tree arg0 = CALL_EXPR_ARG (exp, 0);
9309 rtx op0 = expand_normal (arg0);
9310 machine_mode mode0 = insn_data[icode].operand[0].mode;
9311
9312 if (TARGET_32BIT)
9313 /* Builtin not supported in 32-bit mode. */
9314 fatal_error (input_location,
9315 "%<__builtin_set_fpscr_drn%> is not supported "
9316 "in 32-bit mode");
9317
9318 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
9319 {
9320 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
9321 return const0_rtx;
9322 }
9323
9324 if (icode == CODE_FOR_nothing)
9325 /* Builtin not supported on this processor. */
9326 return 0;
9327
9328 /* If we got invalid arguments bail out before generating bad rtl. */
9329 if (arg0 == error_mark_node)
9330 return const0_rtx;
9331
9332 /* If the argument is a constant, check the range. Agrument can only be a
9333 3-bit value. Unfortunately, can't check the range of the value at
9334 compile time if the argument is a variable. The least significant two
9335 bits of the argument, regardless of type, are used to set the rounding
9336 mode. All other bits are ignored. */
9337 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode))
9338 {
9339 error ("Argument must be a value between 0 and 7.");
9340 return const0_rtx;
9341 }
9342
9343 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
9344 op0 = copy_to_mode_reg (mode0, op0);
9345
9346 pat = GEN_FCN (icode) (op0);
9347 if (! pat)
9348 return const0_rtx;
9349 emit_insn (pat);
9350
9351 return NULL_RTX;
9352}
9353
9354static rtx
9355rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
9356{
9357 rtx pat;
9358 tree arg0 = CALL_EXPR_ARG (exp, 0);
9359 rtx op0 = expand_normal (arg0);
9360 machine_mode tmode = insn_data[icode].operand[0].mode;
9361 machine_mode mode0 = insn_data[icode].operand[1].mode;
9362
9363 if (icode == CODE_FOR_nothing)
9364 /* Builtin not supported on this processor. */
9365 return 0;
9366
9367 /* If we got invalid arguments bail out before generating bad rtl. */
9368 if (arg0 == error_mark_node)
9369 return const0_rtx;
9370
9371 if (icode == CODE_FOR_altivec_vspltisb
9372 || icode == CODE_FOR_altivec_vspltish
9373 || icode == CODE_FOR_altivec_vspltisw)
9374 {
9375 /* Only allow 5-bit *signed* literals. */
9376 if (!CONST_INT_P (op0)
9377 || INTVAL (op0) > 15
9378 || INTVAL (op0) < -16)
9379 {
9380 error ("argument 1 must be a 5-bit signed literal");
9381 return CONST0_RTX (tmode);
9382 }
9383 }
9384
9385 if (target == 0
9386 || GET_MODE (target) != tmode
9387 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9388 target = gen_reg_rtx (tmode);
9389
9390 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9391 op0 = copy_to_mode_reg (mode0, op0);
9392
9393 pat = GEN_FCN (icode) (target, op0);
9394 if (! pat)
9395 return 0;
9396 emit_insn (pat);
9397
9398 return target;
9399}
9400
9401static rtx
9402altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
9403{
9404 rtx pat, scratch1, scratch2;
9405 tree arg0 = CALL_EXPR_ARG (exp, 0);
9406 rtx op0 = expand_normal (arg0);
9407 machine_mode tmode = insn_data[icode].operand[0].mode;
9408 machine_mode mode0 = insn_data[icode].operand[1].mode;
9409
9410 /* If we have invalid arguments, bail out before generating bad rtl. */
9411 if (arg0 == error_mark_node)
9412 return const0_rtx;
9413
9414 if (target == 0
9415 || GET_MODE (target) != tmode
9416 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9417 target = gen_reg_rtx (tmode);
9418
9419 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9420 op0 = copy_to_mode_reg (mode0, op0);
9421
9422 scratch1 = gen_reg_rtx (mode0);
9423 scratch2 = gen_reg_rtx (mode0);
9424
9425 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9426 if (! pat)
9427 return 0;
9428 emit_insn (pat);
9429
9430 return target;
9431}
9432
9433static rtx
9434rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
9435{
9436 rtx pat;
9437 tree arg0 = CALL_EXPR_ARG (exp, 0);
9438 tree arg1 = CALL_EXPR_ARG (exp, 1);
9439 rtx op0 = expand_normal (arg0);
9440 rtx op1 = expand_normal (arg1);
9441 machine_mode tmode = insn_data[icode].operand[0].mode;
9442 machine_mode mode0 = insn_data[icode].operand[1].mode;
9443 machine_mode mode1 = insn_data[icode].operand[2].mode;
9444
9445 if (icode == CODE_FOR_nothing)
9446 /* Builtin not supported on this processor. */
9447 return 0;
9448
9449 /* If we got invalid arguments bail out before generating bad rtl. */
9450 if (arg0 == error_mark_node || arg1 == error_mark_node)
9451 return const0_rtx;
9452
9453 if (icode == CODE_FOR_unpackv1ti
9454 || icode == CODE_FOR_unpackkf
9455 || icode == CODE_FOR_unpacktf
9456 || icode == CODE_FOR_unpackif
02ef74ba
CL		 9457 || icode == CODE_FOR_unpacktd
9458 || icode == CODE_FOR_vec_cntmb_v16qi
9459 || icode == CODE_FOR_vec_cntmb_v8hi
9460 || icode == CODE_FOR_vec_cntmb_v4si
9461 || icode == CODE_FOR_vec_cntmb_v2di)
1acf0246
BS		 9462 {
9463 /* Only allow 1-bit unsigned literals. */
9464 STRIP_NOPS (arg1);
9465 if (TREE_CODE (arg1) != INTEGER_CST
9466 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
9467 {
9468 error ("argument 2 must be a 1-bit unsigned literal");
9469 return CONST0_RTX (tmode);
9470 }
9471 }
9472 else if (icode == CODE_FOR_altivec_vspltw)
9473 {
9474 /* Only allow 2-bit unsigned literals. */
9475 STRIP_NOPS (arg1);
9476 if (TREE_CODE (arg1) != INTEGER_CST
9477 || TREE_INT_CST_LOW (arg1) & ~3)
9478 {
9479 error ("argument 2 must be a 2-bit unsigned literal");
9480 return CONST0_RTX (tmode);
9481 }
9482 }
7c00c559
KN		 9483 else if (icode == CODE_FOR_vgnb)
9484 {
9485 /* Only allow unsigned literals in range 2..7. */
9486 /* Note that arg1 is second operand. */
9487 STRIP_NOPS (arg1);
9488 if (TREE_CODE (arg1) != INTEGER_CST
9489 || (TREE_INT_CST_LOW (arg1) & ~7)
9490 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 2, 7))
9491 {
9492 error ("argument 2 must be unsigned literal between "
9493 "2 and 7 inclusive");
9494 return CONST0_RTX (tmode);
9495 }
9496 }
1acf0246
BS		 9497 else if (icode == CODE_FOR_altivec_vsplth)
9498 {
9499 /* Only allow 3-bit unsigned literals. */
9500 STRIP_NOPS (arg1);
9501 if (TREE_CODE (arg1) != INTEGER_CST
9502 || TREE_INT_CST_LOW (arg1) & ~7)
9503 {
9504 error ("argument 2 must be a 3-bit unsigned literal");
9505 return CONST0_RTX (tmode);
9506 }
9507 }
9508 else if (icode == CODE_FOR_altivec_vspltb)
9509 {
9510 /* Only allow 4-bit unsigned literals. */
9511 STRIP_NOPS (arg1);
9512 if (TREE_CODE (arg1) != INTEGER_CST
9513 || TREE_INT_CST_LOW (arg1) & ~15)
9514 {
9515 error ("argument 2 must be a 4-bit unsigned literal");
9516 return CONST0_RTX (tmode);
9517 }
9518 }
9519 else if (icode == CODE_FOR_altivec_vcfux
9520 || icode == CODE_FOR_altivec_vcfsx
9521 || icode == CODE_FOR_altivec_vctsxs
9522 || icode == CODE_FOR_altivec_vctuxs)
9523 {
9524 /* Only allow 5-bit unsigned literals. */
9525 STRIP_NOPS (arg1);
9526 if (TREE_CODE (arg1) != INTEGER_CST
9527 || TREE_INT_CST_LOW (arg1) & ~0x1f)
9528 {
9529 error ("argument 2 must be a 5-bit unsigned literal");
9530 return CONST0_RTX (tmode);
9531 }
9532 }
9533 else if (icode == CODE_FOR_dfptstsfi_eq_dd
9534 || icode == CODE_FOR_dfptstsfi_lt_dd
9535 || icode == CODE_FOR_dfptstsfi_gt_dd
9536 || icode == CODE_FOR_dfptstsfi_unordered_dd
9537 || icode == CODE_FOR_dfptstsfi_eq_td
9538 || icode == CODE_FOR_dfptstsfi_lt_td
9539 || icode == CODE_FOR_dfptstsfi_gt_td
9540 || icode == CODE_FOR_dfptstsfi_unordered_td)
9541 {
9542 /* Only allow 6-bit unsigned literals. */
9543 STRIP_NOPS (arg0);
9544 if (TREE_CODE (arg0) != INTEGER_CST
9545 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
9546 {
9547 error ("argument 1 must be a 6-bit unsigned literal");
9548 return CONST0_RTX (tmode);
9549 }
9550 }
9551 else if (icode == CODE_FOR_xststdcqp_kf
9552 || icode == CODE_FOR_xststdcqp_tf
9553 || icode == CODE_FOR_xststdcdp
9554 || icode == CODE_FOR_xststdcsp
9555 || icode == CODE_FOR_xvtstdcdp
9556 || icode == CODE_FOR_xvtstdcsp)
9557 {
9558 /* Only allow 7-bit unsigned literals. */
9559 STRIP_NOPS (arg1);
9560 if (TREE_CODE (arg1) != INTEGER_CST
9561 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
9562 {
9563 error ("argument 2 must be a 7-bit unsigned literal");
9564 return CONST0_RTX (tmode);
9565 }
9566 }
9567
9568 if (target == 0
9569 || GET_MODE (target) != tmode
9570 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9571 target = gen_reg_rtx (tmode);
9572
9573 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9574 op0 = copy_to_mode_reg (mode0, op0);
9575 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9576 op1 = copy_to_mode_reg (mode1, op1);
9577
9578 pat = GEN_FCN (icode) (target, op0, op1);
9579 if (! pat)
9580 return 0;
9581 emit_insn (pat);
9582
9583 return target;
9584}
9585
9586static rtx
9587altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9588{
9589 rtx pat, scratch;
9590 tree cr6_form = CALL_EXPR_ARG (exp, 0);
9591 tree arg0 = CALL_EXPR_ARG (exp, 1);
9592 tree arg1 = CALL_EXPR_ARG (exp, 2);
9593 rtx op0 = expand_normal (arg0);
9594 rtx op1 = expand_normal (arg1);
9595 machine_mode tmode = SImode;
9596 machine_mode mode0 = insn_data[icode].operand[1].mode;
9597 machine_mode mode1 = insn_data[icode].operand[2].mode;
9598 int cr6_form_int;
9599
9600 if (TREE_CODE (cr6_form) != INTEGER_CST)
9601 {
9602 error ("argument 1 of %qs must be a constant",
9603 "__builtin_altivec_predicate");
9604 return const0_rtx;
9605 }
9606 else
9607 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
9608
9609 gcc_assert (mode0 == mode1);
9610
9611 /* If we have invalid arguments, bail out before generating bad rtl. */
9612 if (arg0 == error_mark_node || arg1 == error_mark_node)
9613 return const0_rtx;
9614
9615 if (target == 0
9616 || GET_MODE (target) != tmode
9617 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9618 target = gen_reg_rtx (tmode);
9619
9620 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9621 op0 = copy_to_mode_reg (mode0, op0);
9622 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9623 op1 = copy_to_mode_reg (mode1, op1);
9624
9625 /* Note that for many of the relevant operations (e.g. cmpne or
9626 cmpeq) with float or double operands, it makes more sense for the
9627 mode of the allocated scratch register to select a vector of
9628 integer. But the choice to copy the mode of operand 0 was made
9629 long ago and there are no plans to change it. */
9630 scratch = gen_reg_rtx (mode0);
9631
9632 pat = GEN_FCN (icode) (scratch, op0, op1);
9633 if (! pat)
9634 return 0;
9635 emit_insn (pat);
9636
9637 /* The vec_any* and vec_all* predicates use the same opcodes for two
9638 different operations, but the bits in CR6 will be different
9639 depending on what information we want. So we have to play tricks
9640 with CR6 to get the right bits out.
9641
9642 If you think this is disgusting, look at the specs for the
9643 AltiVec predicates. */
9644
9645 switch (cr6_form_int)
9646 {
9647 case 0:
9648 emit_insn (gen_cr6_test_for_zero (target));
9649 break;
9650 case 1:
9651 emit_insn (gen_cr6_test_for_zero_reverse (target));
9652 break;
9653 case 2:
9654 emit_insn (gen_cr6_test_for_lt (target));
9655 break;
9656 case 3:
9657 emit_insn (gen_cr6_test_for_lt_reverse (target));
9658 break;
9659 default:
9660 error ("argument 1 of %qs is out of range",
9661 "__builtin_altivec_predicate");
9662 break;
9663 }
9664
9665 return target;
9666}
9667
9668rtx
9669swap_endian_selector_for_mode (machine_mode mode)
9670{
9671 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
9672 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
9673 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
9674 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
9675
9676 unsigned int *swaparray, i;
9677 rtx perm[16];
9678
9679 switch (mode)
9680 {
9681 case E_V1TImode:
9682 swaparray = swap1;
9683 break;
9684 case E_V2DFmode:
9685 case E_V2DImode:
9686 swaparray = swap2;
9687 break;
9688 case E_V4SFmode:
9689 case E_V4SImode:
9690 swaparray = swap4;
9691 break;
9692 case E_V8HImode:
9693 swaparray = swap8;
9694 break;
9695 default:
9696 gcc_unreachable ();
9697 }
9698
9699 for (i = 0; i < 16; ++i)
9700 perm[i] = GEN_INT (swaparray[i]);
9701
9702 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
9703 gen_rtvec_v (16, perm)));
9704}
9705
b69c0061
WS		 9706/* For the load and sign extend rightmost elements; load and zero extend
9707 rightmost element builtins. */
9708static rtx
9709altivec_expand_lxvr_builtin (enum insn_code icode, tree exp, rtx target, bool blk, bool sign_extend)
9710{
9711 rtx pat, addr;
9712 tree arg0 = CALL_EXPR_ARG (exp, 0);
9713 tree arg1 = CALL_EXPR_ARG (exp, 1);
9714 machine_mode tmode = insn_data[icode].operand[0].mode;
9715 machine_mode smode = insn_data[icode].operand[1].mode;
9716 machine_mode mode0 = Pmode;
9717 machine_mode mode1 = Pmode;
9718 rtx op0 = expand_normal (arg0);
9719 rtx op1 = expand_normal (arg1);
9720
9721 if (icode == CODE_FOR_nothing)
9722 /* Builtin not supported on this processor. */
9723 return 0;
9724
9725 /* If we got invalid arguments bail out before generating bad rtl. */
9726 if (arg0 == error_mark_node || arg1 == error_mark_node)
9727 return const0_rtx;
9728
9729 if (target == 0
9730 || GET_MODE (target) != tmode
9731 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9732 target = gen_reg_rtx (tmode);
9733
9734 op1 = copy_to_mode_reg (mode1, op1);
9735
9736 if (op0 == const0_rtx)
9737 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
9738 else
9739 {
9740 op0 = copy_to_mode_reg (mode0, op0);
9741 addr = gen_rtx_MEM (blk ? BLKmode : smode,
9742 gen_rtx_PLUS (Pmode, op1, op0));
9743 }
9744
9745 if (sign_extend)
9746 {
9747 rtx discratch = gen_reg_rtx (DImode);
9748 rtx tiscratch = gen_reg_rtx (TImode);
9749
9750 /* Emit the lxvr*x insn. */
9751 pat = GEN_FCN (icode) (tiscratch, addr);
9752 if (!pat)
9753 return 0;
9754 emit_insn (pat);
9755
9756 /* Emit a sign extension from QI,HI,WI to double (DI). */
9757 rtx scratch = gen_lowpart (smode, tiscratch);
9758 if (icode == CODE_FOR_vsx_lxvrbx)
9759 emit_insn (gen_extendqidi2 (discratch, scratch));
9760 else if (icode == CODE_FOR_vsx_lxvrhx)
9761 emit_insn (gen_extendhidi2 (discratch, scratch));
9762 else if (icode == CODE_FOR_vsx_lxvrwx)
9763 emit_insn (gen_extendsidi2 (discratch, scratch));
9764 /* Assign discratch directly if scratch is already DI. */
9765 if (icode == CODE_FOR_vsx_lxvrdx)
9766 discratch = scratch;
9767
9768 /* Emit the sign extension from DI (double) to TI (quad). */
9769 emit_insn (gen_extendditi2 (target, discratch));
9770
9771 return target;
9772 }
9773 else
9774 {
9775 /* Zero extend. */
9776 pat = GEN_FCN (icode) (target, addr);
9777 if (!pat)
9778 return 0;
9779 emit_insn (pat);
9780 return target;
9781 }
9782 return 0;
9783}
9784
1acf0246
BS		 9785static rtx
9786altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
9787{
9788 rtx pat, addr;
9789 tree arg0 = CALL_EXPR_ARG (exp, 0);
9790 tree arg1 = CALL_EXPR_ARG (exp, 1);
9791 machine_mode tmode = insn_data[icode].operand[0].mode;
9792 machine_mode mode0 = Pmode;
9793 machine_mode mode1 = Pmode;
9794 rtx op0 = expand_normal (arg0);
9795 rtx op1 = expand_normal (arg1);
9796
9797 if (icode == CODE_FOR_nothing)
9798 /* Builtin not supported on this processor. */
9799 return 0;
9800
9801 /* If we got invalid arguments bail out before generating bad rtl. */
9802 if (arg0 == error_mark_node || arg1 == error_mark_node)
9803 return const0_rtx;
9804
9805 if (target == 0
9806 || GET_MODE (target) != tmode
9807 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9808 target = gen_reg_rtx (tmode);
9809
9810 op1 = copy_to_mode_reg (mode1, op1);
9811
9812 /* For LVX, express the RTL accurately by ANDing the address with -16.
9813 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
9814 so the raw address is fine. */
9815 if (icode == CODE_FOR_altivec_lvx_v1ti
9816 || icode == CODE_FOR_altivec_lvx_v2df
9817 || icode == CODE_FOR_altivec_lvx_v2di
9818 || icode == CODE_FOR_altivec_lvx_v4sf
9819 || icode == CODE_FOR_altivec_lvx_v4si
9820 || icode == CODE_FOR_altivec_lvx_v8hi
9821 || icode == CODE_FOR_altivec_lvx_v16qi)
9822 {
9823 rtx rawaddr;
9824 if (op0 == const0_rtx)
9825 rawaddr = op1;
9826 else
9827 {
9828 op0 = copy_to_mode_reg (mode0, op0);
9829 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
9830 }
9831 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
9832 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
9833
9834 emit_insn (gen_rtx_SET (target, addr));
9835 }
9836 else
9837 {
9838 if (op0 == const0_rtx)
9839 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
9840 else
9841 {
9842 op0 = copy_to_mode_reg (mode0, op0);
9843 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
9844 gen_rtx_PLUS (Pmode, op1, op0));
9845 }
9846
9847 pat = GEN_FCN (icode) (target, addr);
9848 if (! pat)
9849 return 0;
9850 emit_insn (pat);
9851 }
9852
9853 return target;
9854}
9855
9856static rtx
9857altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
9858{
9859 rtx pat;
9860 tree arg0 = CALL_EXPR_ARG (exp, 0);
9861 tree arg1 = CALL_EXPR_ARG (exp, 1);
9862 tree arg2 = CALL_EXPR_ARG (exp, 2);
9863 rtx op0 = expand_normal (arg0);
9864 rtx op1 = expand_normal (arg1);
9865 rtx op2 = expand_normal (arg2);
9866 machine_mode mode0 = insn_data[icode].operand[0].mode;
9867 machine_mode mode1 = insn_data[icode].operand[1].mode;
9868 machine_mode mode2 = insn_data[icode].operand[2].mode;
9869
9870 if (icode == CODE_FOR_nothing)
9871 /* Builtin not supported on this processor. */
9872 return NULL_RTX;
9873
9874 /* If we got invalid arguments bail out before generating bad rtl. */
9875 if (arg0 == error_mark_node
9876 || arg1 == error_mark_node
9877 || arg2 == error_mark_node)
9878 return NULL_RTX;
9879
9880 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9881 op0 = copy_to_mode_reg (mode0, op0);
9882 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9883 op1 = copy_to_mode_reg (mode1, op1);
9884 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
9885 op2 = copy_to_mode_reg (mode2, op2);
9886
9887 pat = GEN_FCN (icode) (op0, op1, op2);
9888 if (pat)
9889 emit_insn (pat);
9890
9891 return NULL_RTX;
9892}
9893
9894static rtx
9895altivec_expand_stv_builtin (enum insn_code icode, tree exp)
9896{
9897 tree arg0 = CALL_EXPR_ARG (exp, 0);
9898 tree arg1 = CALL_EXPR_ARG (exp, 1);
9899 tree arg2 = CALL_EXPR_ARG (exp, 2);
9900 rtx op0 = expand_normal (arg0);
9901 rtx op1 = expand_normal (arg1);
9902 rtx op2 = expand_normal (arg2);
b69c0061 9903 rtx pat, addr, rawaddr, truncrtx;
1acf0246
BS		 9904 machine_mode tmode = insn_data[icode].operand[0].mode;
9905 machine_mode smode = insn_data[icode].operand[1].mode;
9906 machine_mode mode1 = Pmode;
9907 machine_mode mode2 = Pmode;
9908
9909 /* Invalid arguments. Bail before doing anything stoopid! */
9910 if (arg0 == error_mark_node
9911 || arg1 == error_mark_node
9912 || arg2 == error_mark_node)
9913 return const0_rtx;
9914
9915 op2 = copy_to_mode_reg (mode2, op2);
9916
9917 /* For STVX, express the RTL accurately by ANDing the address with -16.
9918 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
9919 so the raw address is fine. */
9920 if (icode == CODE_FOR_altivec_stvx_v2df
9921 || icode == CODE_FOR_altivec_stvx_v2di
9922 || icode == CODE_FOR_altivec_stvx_v4sf
9923 || icode == CODE_FOR_altivec_stvx_v4si
9924 || icode == CODE_FOR_altivec_stvx_v8hi
9925 || icode == CODE_FOR_altivec_stvx_v16qi)
9926 {
9927 if (op1 == const0_rtx)
9928 rawaddr = op2;
9929 else
9930 {
9931 op1 = copy_to_mode_reg (mode1, op1);
9932 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
9933 }
9934
9935 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
9936 addr = gen_rtx_MEM (tmode, addr);
9937
9938 op0 = copy_to_mode_reg (tmode, op0);
9939
9940 emit_insn (gen_rtx_SET (addr, op0));
9941 }
b69c0061
WS		 9942 else if (icode == CODE_FOR_vsx_stxvrbx
9943 || icode == CODE_FOR_vsx_stxvrhx
9944 || icode == CODE_FOR_vsx_stxvrwx
9945 || icode == CODE_FOR_vsx_stxvrdx)
9946 {
9947 truncrtx = gen_rtx_TRUNCATE (tmode, op0);
9948 op0 = copy_to_mode_reg (E_TImode, truncrtx);
9949
9950 if (op1 == const0_rtx)
9951 addr = gen_rtx_MEM (Pmode, op2);
9952 else
9953 {
9954 op1 = copy_to_mode_reg (mode1, op1);
9955 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
9956 }
9957 pat = GEN_FCN (icode) (addr, op0);
9958 if (pat)
9959 emit_insn (pat);
9960 }
1acf0246
BS		 9961 else
9962 {
9963 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
9964 op0 = copy_to_mode_reg (smode, op0);
9965
9966 if (op1 == const0_rtx)
9967 addr = gen_rtx_MEM (tmode, op2);
9968 else
9969 {
9970 op1 = copy_to_mode_reg (mode1, op1);
9971 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
9972 }
9973
9974 pat = GEN_FCN (icode) (addr, op0);
9975 if (pat)
9976 emit_insn (pat);
9977 }
9978
9979 return NULL_RTX;
9980}
9981
8ee2640b
PB		 9982/* Expand the MMA built-in in EXP.
9983 Store true in *EXPANDEDP if we found a built-in to expand. */
9984
9985static rtx
9986mma_expand_builtin (tree exp, rtx target, bool *expandedp)
9987{
9988 unsigned i;
9989 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9990 enum rs6000_builtins fcode
9991 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
9992 const struct builtin_description *d = bdesc_mma;
9993
9994 /* Expand the MMA built-in. */
9995 for (i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++)
9996 if (d->code == fcode)
9997 break;
9998
9999 if (i >= ARRAY_SIZE (bdesc_mma))
10000 {
10001 *expandedp = false;
10002 return NULL_RTX;
10003 }
10004
10005 *expandedp = true;
10006
10007 tree arg;
10008 call_expr_arg_iterator iter;
10009 enum insn_code icode = d->icode;
10010 const struct insn_operand_data *insn_op;
10011 rtx op[MAX_MMA_OPERANDS];
10012 unsigned nopnds = 0;
10013 unsigned attr = rs6000_builtin_info[fcode].attr;
10014 bool void_func = (attr & RS6000_BTC_VOID);
10015 machine_mode tmode = VOIDmode;
10016
10017 if (TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node)
10018 {
10019 tmode = insn_data[icode].operand[0].mode;
10020 if (!target
10021 || GET_MODE (target) != tmode
10022 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
10023 target = gen_reg_rtx (tmode);
10024 op[nopnds++] = target;
10025 }
10026 else
10027 target = const0_rtx;
10028
10029 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10030 {
10031 if (arg == error_mark_node)
10032 return const0_rtx;
10033
10034 rtx opnd;
10035 insn_op = &insn_data[icode].operand[nopnds];
10036 if (TREE_CODE (arg) == ADDR_EXPR
10037 && MEM_P (DECL_RTL (TREE_OPERAND (arg, 0))))
10038 opnd = DECL_RTL (TREE_OPERAND (arg, 0));
10039 else
10040 opnd = expand_normal (arg);
10041
10042 if (!(*insn_op->predicate) (opnd, insn_op->mode))
10043 {
10044 if (!strcmp (insn_op->constraint, "n"))
10045 {
10046 if (!CONST_INT_P (opnd))
10047 error ("argument %d must be an unsigned literal", nopnds);
10048 else
10049 error ("argument %d is an unsigned literal that is "
10050 "out of range", nopnds);
10051 return const0_rtx;
10052 }
10053 opnd = copy_to_mode_reg (insn_op->mode, opnd);
10054 }
10055
10056 /* Some MMA instructions have INOUT accumulator operands, so force
10057 their target register to be the same as their input register. */
10058 if (!void_func
10059 && nopnds == 1
10060 && !strcmp (insn_op->constraint, "0")
10061 && insn_op->mode == tmode
10062 && REG_P (opnd)
10063 && (*insn_data[icode].operand[0].predicate) (opnd, tmode))
10064 target = op[0] = opnd;
10065
10066 op[nopnds++] = opnd;
10067 }
10068
10069 unsigned attr_args = attr & RS6000_BTC_OPND_MASK;
f8f8909a
AS		 10070 if (attr & RS6000_BTC_QUAD
10071 || fcode == MMA_BUILTIN_DISASSEMBLE_PAIR_INTERNAL)
8ee2640b
PB		 10072 attr_args++;
10073
10074 gcc_assert (nopnds == attr_args);
10075
10076 rtx pat;
10077 switch (nopnds)
10078 {
10079 case 1:
10080 pat = GEN_FCN (icode) (op[0]);
10081 break;
10082 case 2:
10083 pat = GEN_FCN (icode) (op[0], op[1]);
10084 break;
10085 case 3:
10086 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
10087 break;
10088 case 4:
10089 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
10090 break;
10091 case 5:
10092 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
10093 break;
10094 case 6:
10095 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]);
10096 break;
10097 case 7:
10098 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5], op[6]);
10099 break;
10100 default:
10101 gcc_unreachable ();
10102 }
10103 if (!pat)
10104 return NULL_RTX;
10105 emit_insn (pat);
10106
10107 return target;
10108}
10109
1acf0246
BS		 10110/* Return the appropriate SPR number associated with the given builtin. */
10111static inline HOST_WIDE_INT
10112htm_spr_num (enum rs6000_builtins code)
10113{
10114 if (code == HTM_BUILTIN_GET_TFHAR
10115 || code == HTM_BUILTIN_SET_TFHAR)
10116 return TFHAR_SPR;
10117 else if (code == HTM_BUILTIN_GET_TFIAR
10118 || code == HTM_BUILTIN_SET_TFIAR)
10119 return TFIAR_SPR;
10120 else if (code == HTM_BUILTIN_GET_TEXASR
10121 || code == HTM_BUILTIN_SET_TEXASR)
10122 return TEXASR_SPR;
10123 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
10124 || code == HTM_BUILTIN_SET_TEXASRU);
10125 return TEXASRU_SPR;
10126}
10127
10128/* Return the correct ICODE value depending on whether we are
10129 setting or reading the HTM SPRs. */
10130static inline enum insn_code
10131rs6000_htm_spr_icode (bool nonvoid)
10132{
10133 if (nonvoid)
10134 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
10135 else
10136 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
10137}
10138
10139/* Expand the HTM builtin in EXP and store the result in TARGET.
10140 Store true in *EXPANDEDP if we found a builtin to expand. */
10141static rtx
10142htm_expand_builtin (tree exp, rtx target, bool * expandedp)
10143{
10144 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10145 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
4d732405
RS		 10146 enum rs6000_builtins fcode
10147 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 10148 const struct builtin_description *d;
10149 size_t i;
10150
10151 *expandedp = true;
10152
10153 if (!TARGET_POWERPC64
10154 && (fcode == HTM_BUILTIN_TABORTDC
10155 || fcode == HTM_BUILTIN_TABORTDCI))
10156 {
10157 size_t uns_fcode = (size_t)fcode;
10158 const char *name = rs6000_builtin_info[uns_fcode].name;
10159 error ("builtin %qs is only valid in 64-bit mode", name);
10160 return const0_rtx;
10161 }
10162
10163 /* Expand the HTM builtins. */
10164 d = bdesc_htm;
10165 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
10166 if (d->code == fcode)
10167 {
10168 rtx op[MAX_HTM_OPERANDS], pat;
10169 int nopnds = 0;
10170 tree arg;
10171 call_expr_arg_iterator iter;
10172 unsigned attr = rs6000_builtin_info[fcode].attr;
10173 enum insn_code icode = d->icode;
10174 const struct insn_operand_data *insn_op;
10175 bool uses_spr = (attr & RS6000_BTC_SPR);
10176 rtx cr = NULL_RTX;
10177
10178 if (uses_spr)
10179 icode = rs6000_htm_spr_icode (nonvoid);
10180 insn_op = &insn_data[icode].operand[0];
10181
10182 if (nonvoid)
10183 {
10184 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
10185 if (!target
10186 || GET_MODE (target) != tmode
10187 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
10188 target = gen_reg_rtx (tmode);
10189 if (uses_spr)
10190 op[nopnds++] = target;
10191 }
10192
10193 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10194 {
10195 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
10196 return const0_rtx;
10197
10198 insn_op = &insn_data[icode].operand[nopnds];
10199
10200 op[nopnds] = expand_normal (arg);
10201
10202 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
10203 {
10204 if (!strcmp (insn_op->constraint, "n"))
10205 {
10206 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
10207 if (!CONST_INT_P (op[nopnds]))
10208 error ("argument %d must be an unsigned literal", arg_num);
10209 else
10210 error ("argument %d is an unsigned literal that is "
10211 "out of range", arg_num);
10212 return const0_rtx;
10213 }
10214 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
10215 }
10216
10217 nopnds++;
10218 }
10219
10220 /* Handle the builtins for extended mnemonics. These accept
10221 no arguments, but map to builtins that take arguments. */
10222 switch (fcode)
10223 {
10224 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
10225 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
10226 op[nopnds++] = GEN_INT (1);
10227 if (flag_checking)
10228 attr |= RS6000_BTC_UNARY;
10229 break;
10230 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
10231 op[nopnds++] = GEN_INT (0);
10232 if (flag_checking)
10233 attr |= RS6000_BTC_UNARY;
10234 break;
10235 default:
10236 break;
10237 }
10238
10239 /* If this builtin accesses SPRs, then pass in the appropriate
10240 SPR number and SPR regno as the last two operands. */
10241 if (uses_spr)
10242 {
10243 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
10244 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
10245 }
10246 /* If this builtin accesses a CR, then pass in a scratch
10247 CR as the last operand. */
10248 else if (attr & RS6000_BTC_CR)
10249 { cr = gen_reg_rtx (CCmode);
10250 op[nopnds++] = cr;
10251 }
10252
10253 if (flag_checking)
10254 {
10255 int expected_nopnds = 0;
8ee2640b 10256 if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_UNARY)
1acf0246 10257 expected_nopnds = 1;
8ee2640b 10258 else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_BINARY)
1acf0246 10259 expected_nopnds = 2;
8ee2640b 10260 else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_TERNARY)
1acf0246 10261 expected_nopnds = 3;
840ac85c
KN		 10262 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_QUATERNARY)
10263 expected_nopnds = 4;
1acf0246
BS		 10264 if (!(attr & RS6000_BTC_VOID))
10265 expected_nopnds += 1;
10266 if (uses_spr)
10267 expected_nopnds += 1;
10268
10269 gcc_assert (nopnds == expected_nopnds
10270 && nopnds <= MAX_HTM_OPERANDS);
10271 }
10272
10273 switch (nopnds)
10274 {
10275 case 1:
10276 pat = GEN_FCN (icode) (op[0]);
10277 break;
10278 case 2:
10279 pat = GEN_FCN (icode) (op[0], op[1]);
10280 break;
10281 case 3:
10282 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
10283 break;
10284 case 4:
10285 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
10286 break;
10287 default:
10288 gcc_unreachable ();
10289 }
10290 if (!pat)
10291 return NULL_RTX;
10292 emit_insn (pat);
10293
10294 if (attr & RS6000_BTC_CR)
10295 {
10296 if (fcode == HTM_BUILTIN_TBEGIN)
10297 {
10298 /* Emit code to set TARGET to true or false depending on
10299 whether the tbegin. instruction successfully or failed
10300 to start a transaction. We do this by placing the 1's
10301 complement of CR's EQ bit into TARGET. */
10302 rtx scratch = gen_reg_rtx (SImode);
10303 emit_insn (gen_rtx_SET (scratch,
10304 gen_rtx_EQ (SImode, cr,
10305 const0_rtx)));
10306 emit_insn (gen_rtx_SET (target,
10307 gen_rtx_XOR (SImode, scratch,
10308 GEN_INT (1))));
10309 }
10310 else
10311 {
10312 /* Emit code to copy the 4-bit condition register field
10313 CR into the least significant end of register TARGET. */
10314 rtx scratch1 = gen_reg_rtx (SImode);
10315 rtx scratch2 = gen_reg_rtx (SImode);
10316 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
10317 emit_insn (gen_movcc (subreg, cr));
10318 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
10319 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
10320 }
10321 }
10322
10323 if (nonvoid)
10324 return target;
10325 return const0_rtx;
10326 }
10327
10328 *expandedp = false;
10329 return NULL_RTX;
10330}
10331
10332/* Expand the CPU builtin in FCODE and store the result in TARGET. */
10333
10334static rtx
10335cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
10336 rtx target)
10337{
10338 /* __builtin_cpu_init () is a nop, so expand to nothing. */
10339 if (fcode == RS6000_BUILTIN_CPU_INIT)
10340 return const0_rtx;
10341
10342 if (target == 0 || GET_MODE (target) != SImode)
10343 target = gen_reg_rtx (SImode);
10344
10345#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
10346 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
10347 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
10348 to a STRING_CST. */
10349 if (TREE_CODE (arg) == ARRAY_REF
10350 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
10351 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
10352 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
10353 arg = TREE_OPERAND (arg, 0);
10354
10355 if (TREE_CODE (arg) != STRING_CST)
10356 {
10357 error ("builtin %qs only accepts a string argument",
10358 rs6000_builtin_info[(size_t) fcode].name);
10359 return const0_rtx;
10360 }
10361
10362 if (fcode == RS6000_BUILTIN_CPU_IS)
10363 {
10364 const char *cpu = TREE_STRING_POINTER (arg);
10365 rtx cpuid = NULL_RTX;
10366 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
10367 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
10368 {
10369 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
10370 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
10371 break;
10372 }
10373 if (cpuid == NULL_RTX)
10374 {
10375 /* Invalid CPU argument. */
10376 error ("cpu %qs is an invalid argument to builtin %qs",
10377 cpu, rs6000_builtin_info[(size_t) fcode].name);
10378 return const0_rtx;
10379 }
10380
10381 rtx platform = gen_reg_rtx (SImode);
10382 rtx tcbmem = gen_const_mem (SImode,
10383 gen_rtx_PLUS (Pmode,
10384 gen_rtx_REG (Pmode, TLS_REGNUM),
10385 GEN_INT (TCB_PLATFORM_OFFSET)));
10386 emit_move_insn (platform, tcbmem);
10387 emit_insn (gen_eqsi3 (target, platform, cpuid));
10388 }
10389 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
10390 {
10391 const char *hwcap = TREE_STRING_POINTER (arg);
10392 rtx mask = NULL_RTX;
10393 int hwcap_offset;
10394 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
10395 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
10396 {
10397 mask = GEN_INT (cpu_supports_info[i].mask);
10398 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
10399 break;
10400 }
10401 if (mask == NULL_RTX)
10402 {
10403 /* Invalid HWCAP argument. */
10404 error ("%s %qs is an invalid argument to builtin %qs",
10405 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
10406 return const0_rtx;
10407 }
10408
10409 rtx tcb_hwcap = gen_reg_rtx (SImode);
10410 rtx tcbmem = gen_const_mem (SImode,
10411 gen_rtx_PLUS (Pmode,
10412 gen_rtx_REG (Pmode, TLS_REGNUM),
10413 GEN_INT (hwcap_offset)));
10414 emit_move_insn (tcb_hwcap, tcbmem);
10415 rtx scratch1 = gen_reg_rtx (SImode);
10416 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
10417 rtx scratch2 = gen_reg_rtx (SImode);
10418 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
10419 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
10420 }
10421 else
10422 gcc_unreachable ();
10423
10424 /* Record that we have expanded a CPU builtin, so that we can later
10425 emit a reference to the special symbol exported by LIBC to ensure we
10426 do not link against an old LIBC that doesn't support this feature. */
10427 cpu_builtin_p = true;
10428
10429#else
10430 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
10431 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
10432
10433 /* For old LIBCs, always return FALSE. */
10434 emit_move_insn (target, GEN_INT (0));
10435#endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
10436
10437 return target;
10438}
10439
840ac85c
KN		 10440static rtx
10441rs6000_expand_quaternop_builtin (enum insn_code icode, tree exp, rtx target)
10442{
10443 rtx pat;
10444 tree arg0 = CALL_EXPR_ARG (exp, 0);
10445 tree arg1 = CALL_EXPR_ARG (exp, 1);
10446 tree arg2 = CALL_EXPR_ARG (exp, 2);
10447 tree arg3 = CALL_EXPR_ARG (exp, 3);
10448 rtx op0 = expand_normal (arg0);
10449 rtx op1 = expand_normal (arg1);
10450 rtx op2 = expand_normal (arg2);
10451 rtx op3 = expand_normal (arg3);
10452 machine_mode tmode = insn_data[icode].operand[0].mode;
10453 machine_mode mode0 = insn_data[icode].operand[1].mode;
10454 machine_mode mode1 = insn_data[icode].operand[2].mode;
10455 machine_mode mode2 = insn_data[icode].operand[3].mode;
10456 machine_mode mode3 = insn_data[icode].operand[4].mode;
10457
10458 if (icode == CODE_FOR_nothing)
10459 /* Builtin not supported on this processor. */
10460 return 0;
10461
10462 /* If we got invalid arguments bail out before generating bad rtl. */
10463 if (arg0 == error_mark_node
10464 || arg1 == error_mark_node
10465 || arg2 == error_mark_node
10466 || arg3 == error_mark_node)
10467 return const0_rtx;
10468
10469 /* Check and prepare argument depending on the instruction code.
10470
10471 Note that a switch statement instead of the sequence of tests
10472 would be incorrect as many of the CODE_FOR values could be
10473 CODE_FOR_nothing and that would yield multiple alternatives
10474 with identical values. We'd never reach here at runtime in
10475 this case. */
10476 if (icode == CODE_FOR_xxeval)
10477 {
10478 /* Only allow 8-bit unsigned literals. */
10479 STRIP_NOPS (arg3);
10480 if (TREE_CODE (arg3) != INTEGER_CST
10481 || TREE_INT_CST_LOW (arg3) & ~0xff)
10482 {
10483 error ("argument 4 must be an 8-bit unsigned literal");
10484 return CONST0_RTX (tmode);
10485 }
10486 }
5998f1bb
CL		 10487
10488 else if (icode == CODE_FOR_xxpermx)
10489 {
10490 /* Only allow 3-bit unsigned literals. */
10491 STRIP_NOPS (arg3);
10492 if (TREE_CODE (arg3) != INTEGER_CST
10493 || TREE_INT_CST_LOW (arg3) & ~0x7)
10494 {
10495 error ("argument 4 must be a 3-bit unsigned literal");
10496 return CONST0_RTX (tmode);
10497 }
10498 }
10499
3f029aea
CL		 10500 else if (icode == CODE_FOR_vreplace_elt_v4si
10501 || icode == CODE_FOR_vreplace_elt_v4sf)
10502 {
10503 /* Check whether the 3rd argument is an integer constant in the range
10504 0 to 3 inclusive. */
10505 STRIP_NOPS (arg2);
10506 if (TREE_CODE (arg2) != INTEGER_CST
10507 || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 3))
10508 {
10509 error ("argument 3 must be in the range 0 to 3");
10510 return CONST0_RTX (tmode);
10511 }
10512 }
10513
10514 else if (icode == CODE_FOR_vreplace_un_v4si
10515 || icode == CODE_FOR_vreplace_un_v4sf)
10516 {
10517 /* Check whether the 3rd argument is an integer constant in the range
10518 0 to 12 inclusive. */
10519 STRIP_NOPS (arg2);
10520 if (TREE_CODE (arg2) != INTEGER_CST
10521 || !IN_RANGE(TREE_INT_CST_LOW (arg2), 0, 12))
10522 {
10523 error ("argument 3 must be in the range 0 to 12");
10524 return CONST0_RTX (tmode);
10525 }
10526 }
840ac85c 10527
82f10dee
CL		 10528 else if (icode == CODE_FOR_vsldb_v16qi
10529 || icode == CODE_FOR_vsldb_v8hi
10530 || icode == CODE_FOR_vsldb_v4si
10531 || icode == CODE_FOR_vsldb_v2di
10532 || icode == CODE_FOR_vsrdb_v16qi
10533 || icode == CODE_FOR_vsrdb_v8hi
10534 || icode == CODE_FOR_vsrdb_v4si
10535 || icode == CODE_FOR_vsrdb_v2di)
10536 {
10537 /* Check whether the 3rd argument is an integer constant in the range
10538 0 to 7 inclusive. */
10539 STRIP_NOPS (arg2);
10540 if (TREE_CODE (arg2) != INTEGER_CST
10541 || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 7))
10542 {
10543 error ("argument 3 must be a constant in the range 0 to 7");
10544 return CONST0_RTX (tmode);
10545 }
10546 }
10547
840ac85c
KN		 10548 if (target == 0
10549 || GET_MODE (target) != tmode
10550 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10551 target = gen_reg_rtx (tmode);
10552
10553 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10554 op0 = copy_to_mode_reg (mode0, op0);
10555 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10556 op1 = copy_to_mode_reg (mode1, op1);
10557 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10558 op2 = copy_to_mode_reg (mode2, op2);
10559 if (! (*insn_data[icode].operand[4].predicate) (op3, mode3))
10560 op3 = copy_to_mode_reg (mode3, op3);
10561
10562 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
10563 if (! pat)
10564 return 0;
10565 emit_insn (pat);
10566
10567 return target;
10568}
10569
1acf0246
BS		 10570static rtx
10571rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
10572{
10573 rtx pat;
10574 tree arg0 = CALL_EXPR_ARG (exp, 0);
10575 tree arg1 = CALL_EXPR_ARG (exp, 1);
10576 tree arg2 = CALL_EXPR_ARG (exp, 2);
10577 rtx op0 = expand_normal (arg0);
10578 rtx op1 = expand_normal (arg1);
10579 rtx op2 = expand_normal (arg2);
10580 machine_mode tmode = insn_data[icode].operand[0].mode;
10581 machine_mode mode0 = insn_data[icode].operand[1].mode;
10582 machine_mode mode1 = insn_data[icode].operand[2].mode;
10583 machine_mode mode2 = insn_data[icode].operand[3].mode;
10584
10585 if (icode == CODE_FOR_nothing)
10586 /* Builtin not supported on this processor. */
10587 return 0;
10588
10589 /* If we got invalid arguments bail out before generating bad rtl. */
10590 if (arg0 == error_mark_node
10591 || arg1 == error_mark_node
10592 || arg2 == error_mark_node)
10593 return const0_rtx;
10594
10595 /* Check and prepare argument depending on the instruction code.
10596
10597 Note that a switch statement instead of the sequence of tests
10598 would be incorrect as many of the CODE_FOR values could be
10599 CODE_FOR_nothing and that would yield multiple alternatives
10600 with identical values. We'd never reach here at runtime in
10601 this case. */
10602 if (icode == CODE_FOR_altivec_vsldoi_v4sf
10603 || icode == CODE_FOR_altivec_vsldoi_v2df
10604 || icode == CODE_FOR_altivec_vsldoi_v4si
10605 || icode == CODE_FOR_altivec_vsldoi_v8hi
10606 || icode == CODE_FOR_altivec_vsldoi_v16qi)
10607 {
10608 /* Only allow 4-bit unsigned literals. */
10609 STRIP_NOPS (arg2);
10610 if (TREE_CODE (arg2) != INTEGER_CST
10611 || TREE_INT_CST_LOW (arg2) & ~0xf)
10612 {
10613 error ("argument 3 must be a 4-bit unsigned literal");
10614 return CONST0_RTX (tmode);
10615 }
10616 }
10617 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10618 || icode == CODE_FOR_vsx_xxpermdi_v2di
10619 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
10620 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
10621 || icode == CODE_FOR_vsx_xxpermdi_v1ti
10622 || icode == CODE_FOR_vsx_xxpermdi_v4sf
10623 || icode == CODE_FOR_vsx_xxpermdi_v4si
10624 || icode == CODE_FOR_vsx_xxpermdi_v8hi
10625 || icode == CODE_FOR_vsx_xxpermdi_v16qi
10626 || icode == CODE_FOR_vsx_xxsldwi_v16qi
10627 || icode == CODE_FOR_vsx_xxsldwi_v8hi
10628 || icode == CODE_FOR_vsx_xxsldwi_v4si
10629 || icode == CODE_FOR_vsx_xxsldwi_v4sf
10630 || icode == CODE_FOR_vsx_xxsldwi_v2di
10631 || icode == CODE_FOR_vsx_xxsldwi_v2df)
10632 {
10633 /* Only allow 2-bit unsigned literals. */
10634 STRIP_NOPS (arg2);
10635 if (TREE_CODE (arg2) != INTEGER_CST
10636 || TREE_INT_CST_LOW (arg2) & ~0x3)
10637 {
10638 error ("argument 3 must be a 2-bit unsigned literal");
10639 return CONST0_RTX (tmode);
10640 }
10641 }
10642 else if (icode == CODE_FOR_vsx_set_v2df
10643 || icode == CODE_FOR_vsx_set_v2di
05161256
CL		 10644 || icode == CODE_FOR_bcdadd_v16qi
10645 || icode == CODE_FOR_bcdadd_v1ti
10646 || icode == CODE_FOR_bcdadd_lt_v16qi
10647 || icode == CODE_FOR_bcdadd_lt_v1ti
10648 || icode == CODE_FOR_bcdadd_eq_v16qi
10649 || icode == CODE_FOR_bcdadd_eq_v1ti
10650 || icode == CODE_FOR_bcdadd_gt_v16qi
10651 || icode == CODE_FOR_bcdadd_gt_v1ti
10652 || icode == CODE_FOR_bcdsub_v16qi
10653 || icode == CODE_FOR_bcdsub_v1ti
10654 || icode == CODE_FOR_bcdsub_lt_v16qi
10655 || icode == CODE_FOR_bcdsub_lt_v1ti
10656 || icode == CODE_FOR_bcdsub_eq_v16qi
10657 || icode == CODE_FOR_bcdsub_eq_v1ti
10658 || icode == CODE_FOR_bcdsub_gt_v16qi
10659 || icode == CODE_FOR_bcdsub_gt_v1ti)
1acf0246
BS		 10660 {
10661 /* Only allow 1-bit unsigned literals. */
10662 STRIP_NOPS (arg2);
10663 if (TREE_CODE (arg2) != INTEGER_CST
10664 || TREE_INT_CST_LOW (arg2) & ~0x1)
10665 {
10666 error ("argument 3 must be a 1-bit unsigned literal");
10667 return CONST0_RTX (tmode);
10668 }
10669 }
10670 else if (icode == CODE_FOR_dfp_ddedpd_dd
10671 || icode == CODE_FOR_dfp_ddedpd_td)
10672 {
10673 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
10674 STRIP_NOPS (arg0);
10675 if (TREE_CODE (arg0) != INTEGER_CST
10676 || TREE_INT_CST_LOW (arg2) & ~0x3)
10677 {
10678 error ("argument 1 must be 0 or 2");
10679 return CONST0_RTX (tmode);
10680 }
10681 }
10682 else if (icode == CODE_FOR_dfp_denbcd_dd
05161256
CL		 10683 || icode == CODE_FOR_dfp_denbcd_td
10684 || icode == CODE_FOR_dfp_denbcd_v16qi)
1acf0246
BS		 10685 {
10686 /* Only allow 1-bit unsigned literals. */
10687 STRIP_NOPS (arg0);
10688 if (TREE_CODE (arg0) != INTEGER_CST
10689 || TREE_INT_CST_LOW (arg0) & ~0x1)
10690 {
10691 error ("argument 1 must be a 1-bit unsigned literal");
10692 return CONST0_RTX (tmode);
10693 }
10694 }
10695 else if (icode == CODE_FOR_dfp_dscli_dd
10696 || icode == CODE_FOR_dfp_dscli_td
10697 || icode == CODE_FOR_dfp_dscri_dd
10698 || icode == CODE_FOR_dfp_dscri_td)
10699 {
10700 /* Only allow 6-bit unsigned literals. */
10701 STRIP_NOPS (arg1);
10702 if (TREE_CODE (arg1) != INTEGER_CST
10703 || TREE_INT_CST_LOW (arg1) & ~0x3f)
10704 {
10705 error ("argument 2 must be a 6-bit unsigned literal");
10706 return CONST0_RTX (tmode);
10707 }
10708 }
10709 else if (icode == CODE_FOR_crypto_vshasigmaw
10710 || icode == CODE_FOR_crypto_vshasigmad)
10711 {
10712 /* Check whether the 2nd and 3rd arguments are integer constants and in
10713 range and prepare arguments. */
10714 STRIP_NOPS (arg1);
10715 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
10716 {
10717 error ("argument 2 must be 0 or 1");
10718 return CONST0_RTX (tmode);
10719 }
10720
10721 STRIP_NOPS (arg2);
10722 if (TREE_CODE (arg2) != INTEGER_CST
10723 || wi::geu_p (wi::to_wide (arg2), 16))
10724 {
10725 error ("argument 3 must be in the range [0, 15]");
10726 return CONST0_RTX (tmode);
10727 }
10728 }
10729
10730 if (target == 0
10731 || GET_MODE (target) != tmode
10732 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10733 target = gen_reg_rtx (tmode);
10734
10735 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10736 op0 = copy_to_mode_reg (mode0, op0);
10737 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10738 op1 = copy_to_mode_reg (mode1, op1);
10739 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10740 op2 = copy_to_mode_reg (mode2, op2);
10741
10742 pat = GEN_FCN (icode) (target, op0, op1, op2);
10743 if (! pat)
10744 return 0;
10745 emit_insn (pat);
10746
10747 return target;
10748}
10749
10750
10751/* Expand the dst builtins. */
10752static rtx
10753altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10754 bool *expandedp)
10755{
10756 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
4d732405
RS		 10757 enum rs6000_builtins fcode
10758 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 10759 tree arg0, arg1, arg2;
10760 machine_mode mode0, mode1;
10761 rtx pat, op0, op1, op2;
10762 const struct builtin_description *d;
10763 size_t i;
10764
10765 *expandedp = false;
10766
10767 /* Handle DST variants. */
10768 d = bdesc_dst;
10769 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10770 if (d->code == fcode)
10771 {
10772 arg0 = CALL_EXPR_ARG (exp, 0);
10773 arg1 = CALL_EXPR_ARG (exp, 1);
10774 arg2 = CALL_EXPR_ARG (exp, 2);
10775 op0 = expand_normal (arg0);
10776 op1 = expand_normal (arg1);
10777 op2 = expand_normal (arg2);
10778 mode0 = insn_data[d->icode].operand[0].mode;
10779 mode1 = insn_data[d->icode].operand[1].mode;
10780
10781 /* Invalid arguments, bail out before generating bad rtl. */
10782 if (arg0 == error_mark_node
10783 || arg1 == error_mark_node
10784 || arg2 == error_mark_node)
10785 return const0_rtx;
10786
10787 *expandedp = true;
10788 STRIP_NOPS (arg2);
10789 if (TREE_CODE (arg2) != INTEGER_CST
10790 || TREE_INT_CST_LOW (arg2) & ~0x3)
10791 {
10792 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10793 return const0_rtx;
10794 }
10795
10796 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10797 op0 = copy_to_mode_reg (Pmode, op0);
10798 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10799 op1 = copy_to_mode_reg (mode1, op1);
10800
10801 pat = GEN_FCN (d->icode) (op0, op1, op2);
10802 if (pat != 0)
10803 emit_insn (pat);
10804
10805 return NULL_RTX;
10806 }
10807
10808 return NULL_RTX;
10809}
10810
10811/* Expand vec_init builtin. */
10812static rtx
10813altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
10814{
10815 machine_mode tmode = TYPE_MODE (type);
10816 machine_mode inner_mode = GET_MODE_INNER (tmode);
10817 int i, n_elt = GET_MODE_NUNITS (tmode);
10818
10819 gcc_assert (VECTOR_MODE_P (tmode));
10820 gcc_assert (n_elt == call_expr_nargs (exp));
10821
10822 if (!target || !register_operand (target, tmode))
10823 target = gen_reg_rtx (tmode);
10824
10825 /* If we have a vector compromised of a single element, such as V1TImode, do
10826 the initialization directly. */
10827 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
10828 {
10829 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
10830 emit_move_insn (target, gen_lowpart (tmode, x));
10831 }
10832 else
10833 {
10834 rtvec v = rtvec_alloc (n_elt);
10835
10836 for (i = 0; i < n_elt; ++i)
10837 {
10838 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
10839 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
10840 }
10841
10842 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
10843 }
10844
10845 return target;
10846}
10847
10848/* Return the integer constant in ARG. Constrain it to be in the range
10849 of the subparts of VEC_TYPE; issue an error if not. */
10850
10851static int
10852get_element_number (tree vec_type, tree arg)
10853{
10854 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
10855
10856 if (!tree_fits_uhwi_p (arg)
10857 || (elt = tree_to_uhwi (arg), elt > max))
10858 {
10859 error ("selector must be an integer constant in the range [0, %wi]", max);
10860 return 0;
10861 }
10862
10863 return elt;
10864}
10865
10866/* Expand vec_set builtin. */
10867static rtx
10868altivec_expand_vec_set_builtin (tree exp)
10869{
10870 machine_mode tmode, mode1;
10871 tree arg0, arg1, arg2;
10872 int elt;
10873 rtx op0, op1;
10874
10875 arg0 = CALL_EXPR_ARG (exp, 0);
10876 arg1 = CALL_EXPR_ARG (exp, 1);
10877 arg2 = CALL_EXPR_ARG (exp, 2);
10878
10879 tmode = TYPE_MODE (TREE_TYPE (arg0));
10880 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10881 gcc_assert (VECTOR_MODE_P (tmode));
10882
10883 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
10884 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
10885 elt = get_element_number (TREE_TYPE (arg0), arg2);
10886
10887 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
10888 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
10889
10890 op0 = force_reg (tmode, op0);
10891 op1 = force_reg (mode1, op1);
10892
5e9f814d 10893 rs6000_expand_vector_set (op0, op1, GEN_INT (elt));
1acf0246
BS		 10894
10895 return op0;
10896}
10897
10898/* Expand vec_ext builtin. */
10899static rtx
10900altivec_expand_vec_ext_builtin (tree exp, rtx target)
10901{
10902 machine_mode tmode, mode0;
10903 tree arg0, arg1;
10904 rtx op0;
10905 rtx op1;
10906
10907 arg0 = CALL_EXPR_ARG (exp, 0);
10908 arg1 = CALL_EXPR_ARG (exp, 1);
10909
10910 op0 = expand_normal (arg0);
10911 op1 = expand_normal (arg1);
10912
10913 if (TREE_CODE (arg1) == INTEGER_CST)
10914 {
10915 unsigned HOST_WIDE_INT elt;
10916 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0));
10917 unsigned int truncated_selector;
10918 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
10919 returns low-order bits of INTEGER_CST for modulo indexing. */
10920 elt = TREE_INT_CST_LOW (arg1);
10921 truncated_selector = elt % size;
10922 op1 = GEN_INT (truncated_selector);
10923 }
10924
10925 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10926 mode0 = TYPE_MODE (TREE_TYPE (arg0));
10927 gcc_assert (VECTOR_MODE_P (mode0));
10928
10929 op0 = force_reg (mode0, op0);
10930
10931 if (optimize || !target || !register_operand (target, tmode))
10932 target = gen_reg_rtx (tmode);
10933
10934 rs6000_expand_vector_extract (target, op0, op1);
10935
10936 return target;
10937}
10938
10939/* Expand the builtin in EXP and store the result in TARGET. Store
10940 true in *EXPANDEDP if we found a builtin to expand. */
10941static rtx
10942altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
10943{
10944 const struct builtin_description *d;
10945 size_t i;
10946 enum insn_code icode;
10947 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10948 tree arg0, arg1, arg2;
10949 rtx op0, pat;
10950 machine_mode tmode, mode0;
10951 enum rs6000_builtins fcode
4d732405 10952 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 10953
10954 if (rs6000_overloaded_builtin_p (fcode))
10955 {
10956 *expandedp = true;
10957 error ("unresolved overload for Altivec builtin %qF", fndecl);
10958
10959 /* Given it is invalid, just generate a normal call. */
10960 return expand_call (exp, target, false);
10961 }
10962
10963 target = altivec_expand_dst_builtin (exp, target, expandedp);
10964 if (*expandedp)
10965 return target;
10966
10967 *expandedp = true;
10968
10969 switch (fcode)
10970 {
10971 case ALTIVEC_BUILTIN_STVX_V2DF:
10972 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
10973 case ALTIVEC_BUILTIN_STVX_V2DI:
10974 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
10975 case ALTIVEC_BUILTIN_STVX_V4SF:
10976 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
10977 case ALTIVEC_BUILTIN_STVX:
10978 case ALTIVEC_BUILTIN_STVX_V4SI:
10979 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10980 case ALTIVEC_BUILTIN_STVX_V8HI:
10981 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
10982 case ALTIVEC_BUILTIN_STVX_V16QI:
10983 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
10984 case ALTIVEC_BUILTIN_STVEBX:
10985 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10986 case ALTIVEC_BUILTIN_STVEHX:
10987 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
10988 case ALTIVEC_BUILTIN_STVEWX:
10989 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
b69c0061
WS		 10990
10991 case P10_BUILTIN_TR_STXVRBX:
10992 return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrbx, exp);
10993 case P10_BUILTIN_TR_STXVRHX:
10994 return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrhx, exp);
10995 case P10_BUILTIN_TR_STXVRWX:
10996 return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrwx, exp);
10997 case P10_BUILTIN_TR_STXVRDX:
10998 return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrdx, exp);
10999
1acf0246
BS		 11000 case ALTIVEC_BUILTIN_STVXL_V2DF:
11001 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
11002 case ALTIVEC_BUILTIN_STVXL_V2DI:
11003 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
11004 case ALTIVEC_BUILTIN_STVXL_V4SF:
11005 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
11006 case ALTIVEC_BUILTIN_STVXL:
11007 case ALTIVEC_BUILTIN_STVXL_V4SI:
11008 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
11009 case ALTIVEC_BUILTIN_STVXL_V8HI:
11010 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
11011 case ALTIVEC_BUILTIN_STVXL_V16QI:
11012 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
11013
11014 case ALTIVEC_BUILTIN_STVLX:
11015 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
11016 case ALTIVEC_BUILTIN_STVLXL:
11017 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
11018 case ALTIVEC_BUILTIN_STVRX:
11019 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
11020 case ALTIVEC_BUILTIN_STVRXL:
11021 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
11022
11023 case P9V_BUILTIN_STXVL:
11024 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
11025
11026 case P9V_BUILTIN_XST_LEN_R:
11027 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
11028
11029 case VSX_BUILTIN_STXVD2X_V1TI:
11030 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
11031 case VSX_BUILTIN_STXVD2X_V2DF:
11032 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
11033 case VSX_BUILTIN_STXVD2X_V2DI:
11034 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
11035 case VSX_BUILTIN_STXVW4X_V4SF:
11036 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
11037 case VSX_BUILTIN_STXVW4X_V4SI:
11038 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
11039 case VSX_BUILTIN_STXVW4X_V8HI:
11040 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
11041 case VSX_BUILTIN_STXVW4X_V16QI:
11042 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
11043
11044 /* For the following on big endian, it's ok to use any appropriate
11045 unaligned-supporting store, so use a generic expander. For
11046 little-endian, the exact element-reversing instruction must
11047 be used. */
11048 case VSX_BUILTIN_ST_ELEMREV_V1TI:
11049 {
11050 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
11051 : CODE_FOR_vsx_st_elemrev_v1ti);
11052 return altivec_expand_stv_builtin (code, exp);
11053 }
11054 case VSX_BUILTIN_ST_ELEMREV_V2DF:
11055 {
11056 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
11057 : CODE_FOR_vsx_st_elemrev_v2df);
11058 return altivec_expand_stv_builtin (code, exp);
11059 }
11060 case VSX_BUILTIN_ST_ELEMREV_V2DI:
11061 {
11062 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
11063 : CODE_FOR_vsx_st_elemrev_v2di);
11064 return altivec_expand_stv_builtin (code, exp);
11065 }
11066 case VSX_BUILTIN_ST_ELEMREV_V4SF:
11067 {
11068 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
11069 : CODE_FOR_vsx_st_elemrev_v4sf);
11070 return altivec_expand_stv_builtin (code, exp);
11071 }
11072 case VSX_BUILTIN_ST_ELEMREV_V4SI:
11073 {
11074 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
11075 : CODE_FOR_vsx_st_elemrev_v4si);
11076 return altivec_expand_stv_builtin (code, exp);
11077 }
11078 case VSX_BUILTIN_ST_ELEMREV_V8HI:
11079 {
11080 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
11081 : CODE_FOR_vsx_st_elemrev_v8hi);
11082 return altivec_expand_stv_builtin (code, exp);
11083 }
11084 case VSX_BUILTIN_ST_ELEMREV_V16QI:
11085 {
11086 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
11087 : CODE_FOR_vsx_st_elemrev_v16qi);
11088 return altivec_expand_stv_builtin (code, exp);
11089 }
11090
11091 case ALTIVEC_BUILTIN_MFVSCR:
11092 icode = CODE_FOR_altivec_mfvscr;
11093 tmode = insn_data[icode].operand[0].mode;
11094
11095 if (target == 0
11096 || GET_MODE (target) != tmode
11097 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11098 target = gen_reg_rtx (tmode);
11099
11100 pat = GEN_FCN (icode) (target);
11101 if (! pat)
11102 return 0;
11103 emit_insn (pat);
11104 return target;
11105
11106 case ALTIVEC_BUILTIN_MTVSCR:
11107 icode = CODE_FOR_altivec_mtvscr;
11108 arg0 = CALL_EXPR_ARG (exp, 0);
11109 op0 = expand_normal (arg0);
11110 mode0 = insn_data[icode].operand[0].mode;
11111
11112 /* If we got invalid arguments bail out before generating bad rtl. */
11113 if (arg0 == error_mark_node)
11114 return const0_rtx;
11115
11116 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
11117 op0 = copy_to_mode_reg (mode0, op0);
11118
11119 pat = GEN_FCN (icode) (op0);
11120 if (pat)
11121 emit_insn (pat);
11122 return NULL_RTX;
11123
11124 case ALTIVEC_BUILTIN_DSSALL:
11125 emit_insn (gen_altivec_dssall ());
11126 return NULL_RTX;
11127
11128 case ALTIVEC_BUILTIN_DSS:
11129 icode = CODE_FOR_altivec_dss;
11130 arg0 = CALL_EXPR_ARG (exp, 0);
11131 STRIP_NOPS (arg0);
11132 op0 = expand_normal (arg0);
11133 mode0 = insn_data[icode].operand[0].mode;
11134
11135 /* If we got invalid arguments bail out before generating bad rtl. */
11136 if (arg0 == error_mark_node)
11137 return const0_rtx;
11138
11139 if (TREE_CODE (arg0) != INTEGER_CST
11140 || TREE_INT_CST_LOW (arg0) & ~0x3)
11141 {
11142 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
11143 return const0_rtx;
11144 }
11145
11146 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
11147 op0 = copy_to_mode_reg (mode0, op0);
11148
11149 emit_insn (gen_altivec_dss (op0));
11150 return NULL_RTX;
11151
11152 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
11153 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
11154 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
11155 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
11156 case VSX_BUILTIN_VEC_INIT_V2DF:
11157 case VSX_BUILTIN_VEC_INIT_V2DI:
11158 case VSX_BUILTIN_VEC_INIT_V1TI:
11159 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
11160
11161 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
11162 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
11163 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
11164 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
11165 case VSX_BUILTIN_VEC_SET_V2DF:
11166 case VSX_BUILTIN_VEC_SET_V2DI:
11167 case VSX_BUILTIN_VEC_SET_V1TI:
11168 return altivec_expand_vec_set_builtin (exp);
11169
11170 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
11171 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
11172 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
11173 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
11174 case VSX_BUILTIN_VEC_EXT_V2DF:
11175 case VSX_BUILTIN_VEC_EXT_V2DI:
11176 case VSX_BUILTIN_VEC_EXT_V1TI:
11177 return altivec_expand_vec_ext_builtin (exp, target);
11178
11179 case P9V_BUILTIN_VEC_EXTRACT4B:
11180 arg1 = CALL_EXPR_ARG (exp, 1);
11181 STRIP_NOPS (arg1);
11182
11183 /* Generate a normal call if it is invalid. */
11184 if (arg1 == error_mark_node)
11185 return expand_call (exp, target, false);
11186
11187 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
11188 {
11189 error ("second argument to %qs must be [0, 12]", "vec_vextract4b");
11190 return expand_call (exp, target, false);
11191 }
11192 break;
11193
11194 case P9V_BUILTIN_VEC_INSERT4B:
11195 arg2 = CALL_EXPR_ARG (exp, 2);
11196 STRIP_NOPS (arg2);
11197
11198 /* Generate a normal call if it is invalid. */
11199 if (arg2 == error_mark_node)
11200 return expand_call (exp, target, false);
11201
11202 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
11203 {
11204 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b");
11205 return expand_call (exp, target, false);
11206 }
11207 break;
11208
5d9d0c94 11209 case P10_BUILTIN_VEC_XXGENPCVM:
b8eaa754
CL		 11210 arg1 = CALL_EXPR_ARG (exp, 1);
11211 STRIP_NOPS (arg1);
11212
11213 /* Generate a normal call if it is invalid. */
11214 if (arg1 == error_mark_node)
11215 return expand_call (exp, target, false);
11216
11217 if (TREE_CODE (arg1) != INTEGER_CST
11218 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 3))
11219 {
11220 size_t uns_fcode = (size_t) fcode;
11221 const char *name = rs6000_builtin_info[uns_fcode].name;
11222 error ("Second argument of %qs must be in the range [0, 3].", name);
11223 return expand_call (exp, target, false);
11224 }
11225 break;
11226
1acf0246
BS		 11227 default:
11228 break;
11229 /* Fall through. */
11230 }
11231
11232 /* Expand abs* operations. */
11233 d = bdesc_abs;
11234 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
11235 if (d->code == fcode)
11236 return altivec_expand_abs_builtin (d->icode, exp, target);
11237
11238 /* Expand the AltiVec predicates. */
11239 d = bdesc_altivec_preds;
11240 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
11241 if (d->code == fcode)
11242 return altivec_expand_predicate_builtin (d->icode, exp, target);
11243
11244 /* LV* are funky. We initialized them differently. */
11245 switch (fcode)
11246 {
11247 case ALTIVEC_BUILTIN_LVSL:
11248 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
11249 exp, target, false);
11250 case ALTIVEC_BUILTIN_LVSR:
11251 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
11252 exp, target, false);
11253 case ALTIVEC_BUILTIN_LVEBX:
11254 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
11255 exp, target, false);
11256 case ALTIVEC_BUILTIN_LVEHX:
11257 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
11258 exp, target, false);
11259 case ALTIVEC_BUILTIN_LVEWX:
11260 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
11261 exp, target, false);
b69c0061
WS		 11262 case P10_BUILTIN_SE_LXVRBX:
11263 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrbx,
11264 exp, target, false, true);
11265 case P10_BUILTIN_SE_LXVRHX:
11266 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrhx,
11267 exp, target, false, true);
11268 case P10_BUILTIN_SE_LXVRWX:
11269 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrwx,
11270 exp, target, false, true);
11271 case P10_BUILTIN_SE_LXVRDX:
11272 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrdx,
11273 exp, target, false, true);
11274 case P10_BUILTIN_ZE_LXVRBX:
11275 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrbx,
11276 exp, target, false, false);
11277 case P10_BUILTIN_ZE_LXVRHX:
11278 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrhx,
11279 exp, target, false, false);
11280 case P10_BUILTIN_ZE_LXVRWX:
11281 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrwx,
11282 exp, target, false, false);
11283 case P10_BUILTIN_ZE_LXVRDX:
11284 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrdx,
11285 exp, target, false, false);
1acf0246
BS		 11286 case ALTIVEC_BUILTIN_LVXL_V2DF:
11287 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
11288 exp, target, false);
11289 case ALTIVEC_BUILTIN_LVXL_V2DI:
11290 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
11291 exp, target, false);
11292 case ALTIVEC_BUILTIN_LVXL_V4SF:
11293 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
11294 exp, target, false);
11295 case ALTIVEC_BUILTIN_LVXL:
11296 case ALTIVEC_BUILTIN_LVXL_V4SI:
11297 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
11298 exp, target, false);
11299 case ALTIVEC_BUILTIN_LVXL_V8HI:
11300 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
11301 exp, target, false);
11302 case ALTIVEC_BUILTIN_LVXL_V16QI:
11303 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
11304 exp, target, false);
11305 case ALTIVEC_BUILTIN_LVX_V1TI:
11306 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
11307 exp, target, false);
11308 case ALTIVEC_BUILTIN_LVX_V2DF:
11309 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
11310 exp, target, false);
11311 case ALTIVEC_BUILTIN_LVX_V2DI:
11312 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
11313 exp, target, false);
11314 case ALTIVEC_BUILTIN_LVX_V4SF:
11315 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
11316 exp, target, false);
11317 case ALTIVEC_BUILTIN_LVX:
11318 case ALTIVEC_BUILTIN_LVX_V4SI:
11319 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
11320 exp, target, false);
11321 case ALTIVEC_BUILTIN_LVX_V8HI:
11322 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
11323 exp, target, false);
11324 case ALTIVEC_BUILTIN_LVX_V16QI:
11325 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
11326 exp, target, false);
11327 case ALTIVEC_BUILTIN_LVLX:
11328 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
11329 exp, target, true);
11330 case ALTIVEC_BUILTIN_LVLXL:
11331 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
11332 exp, target, true);
11333 case ALTIVEC_BUILTIN_LVRX:
11334 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
11335 exp, target, true);
11336 case ALTIVEC_BUILTIN_LVRXL:
11337 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
11338 exp, target, true);
11339 case VSX_BUILTIN_LXVD2X_V1TI:
11340 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
11341 exp, target, false);
11342 case VSX_BUILTIN_LXVD2X_V2DF:
11343 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
11344 exp, target, false);
11345 case VSX_BUILTIN_LXVD2X_V2DI:
11346 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
11347 exp, target, false);
11348 case VSX_BUILTIN_LXVW4X_V4SF:
11349 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
11350 exp, target, false);
11351 case VSX_BUILTIN_LXVW4X_V4SI:
11352 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
11353 exp, target, false);
11354 case VSX_BUILTIN_LXVW4X_V8HI:
11355 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
11356 exp, target, false);
11357 case VSX_BUILTIN_LXVW4X_V16QI:
11358 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
11359 exp, target, false);
11360 /* For the following on big endian, it's ok to use any appropriate
11361 unaligned-supporting load, so use a generic expander. For
11362 little-endian, the exact element-reversing instruction must
11363 be used. */
11364 case VSX_BUILTIN_LD_ELEMREV_V2DF:
11365 {
11366 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
11367 : CODE_FOR_vsx_ld_elemrev_v2df);
11368 return altivec_expand_lv_builtin (code, exp, target, false);
11369 }
11370 case VSX_BUILTIN_LD_ELEMREV_V1TI:
11371 {
11372 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
11373 : CODE_FOR_vsx_ld_elemrev_v1ti);
11374 return altivec_expand_lv_builtin (code, exp, target, false);
11375 }
11376 case VSX_BUILTIN_LD_ELEMREV_V2DI:
11377 {
11378 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
11379 : CODE_FOR_vsx_ld_elemrev_v2di);
11380 return altivec_expand_lv_builtin (code, exp, target, false);
11381 }
11382 case VSX_BUILTIN_LD_ELEMREV_V4SF:
11383 {
11384 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
11385 : CODE_FOR_vsx_ld_elemrev_v4sf);
11386 return altivec_expand_lv_builtin (code, exp, target, false);
11387 }
11388 case VSX_BUILTIN_LD_ELEMREV_V4SI:
11389 {
11390 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
11391 : CODE_FOR_vsx_ld_elemrev_v4si);
11392 return altivec_expand_lv_builtin (code, exp, target, false);
11393 }
11394 case VSX_BUILTIN_LD_ELEMREV_V8HI:
11395 {
11396 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
11397 : CODE_FOR_vsx_ld_elemrev_v8hi);
11398 return altivec_expand_lv_builtin (code, exp, target, false);
11399 }
11400 case VSX_BUILTIN_LD_ELEMREV_V16QI:
11401 {
11402 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
11403 : CODE_FOR_vsx_ld_elemrev_v16qi);
11404 return altivec_expand_lv_builtin (code, exp, target, false);
11405 }
11406 break;
11407 default:
11408 break;
11409 /* Fall through. */
11410 }
11411
11412 *expandedp = false;
11413 return NULL_RTX;
11414}
11415
11416/* Check whether a builtin function is supported in this target
11417 configuration. */
11418bool
11419rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
11420{
11421 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
11422 if ((fnmask & rs6000_builtin_mask) != fnmask)
11423 return false;
11424 else
11425 return true;
11426}
11427
11428/* Raise an error message for a builtin function that is called without the
11429 appropriate target options being set. */
11430
871a8fab 11431static void
1acf0246
BS		 11432rs6000_invalid_builtin (enum rs6000_builtins fncode)
11433{
11434 size_t uns_fncode = (size_t) fncode;
11435 const char *name = rs6000_builtin_info[uns_fncode].name;
11436 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
11437
11438 gcc_assert (name != NULL);
11439 if ((fnmask & RS6000_BTM_CELL) != 0)
11440 error ("%qs is only valid for the cell processor", name);
11441 else if ((fnmask & RS6000_BTM_VSX) != 0)
11442 error ("%qs requires the %qs option", name, "-mvsx");
11443 else if ((fnmask & RS6000_BTM_HTM) != 0)
11444 error ("%qs requires the %qs option", name, "-mhtm");
11445 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
11446 error ("%qs requires the %qs option", name, "-maltivec");
11447 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
11448 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
11449 error ("%qs requires the %qs and %qs options", name, "-mhard-dfp",
11450 "-mpower8-vector");
11451 else if ((fnmask & RS6000_BTM_DFP) != 0)
11452 error ("%qs requires the %qs option", name, "-mhard-dfp");
11453 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
11454 error ("%qs requires the %qs option", name, "-mpower8-vector");
11455 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
11456 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
11457 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9",
11458 "-m64");
11459 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
11460 error ("%qs requires the %qs option", name, "-mcpu=power9");
11461 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
11462 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
11463 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9",
11464 "-m64");
11465 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
11466 error ("%qs requires the %qs option", name, "-mcpu=power9");
5d9d0c94
SB		 11467 else if ((fnmask & RS6000_BTM_P10) != 0)
11468 error ("%qs requires the %qs option", name, "-mcpu=power10");
8ee2640b
PB		 11469 else if ((fnmask & RS6000_BTM_MMA) != 0)
11470 error ("%qs requires the %qs option", name, "-mmma");
1acf0246
BS		 11471 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
11472 {
11473 if (!TARGET_HARD_FLOAT)
11474 error ("%qs requires the %qs option", name, "-mhard-float");
11475 else
11476 error ("%qs requires the %qs option", name,
11477 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
11478 }
11479 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
11480 error ("%qs requires the %qs option", name, "-mhard-float");
11481 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
11482 error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name);
11483 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
11484 error ("%qs requires the %qs option", name, "%<-mfloat128%>");
11485 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
11486 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
11487 error ("%qs requires the %qs (or newer), and %qs or %qs options",
11488 name, "-mcpu=power7", "-m64", "-mpowerpc64");
11489 else
11490 error ("%qs is not supported with the current options", name);
11491}
11492
11493/* Target hook for early folding of built-ins, shamelessly stolen
11494 from ia64.c. */
11495
11496tree
11497rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
11498 int n_args ATTRIBUTE_UNUSED,
11499 tree *args ATTRIBUTE_UNUSED,
11500 bool ignore ATTRIBUTE_UNUSED)
11501{
11502#ifdef SUBTARGET_FOLD_BUILTIN
11503 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
11504#else
11505 return NULL_TREE;
11506#endif
11507}
11508
11509/* Helper function to sort out which built-ins may be valid without having
11510 a LHS. */
11511static bool
11512rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
11513{
8ee2640b
PB		 11514 /* Check for built-ins explicitly marked as a void function. */
11515 if (rs6000_builtin_info[fn_code].attr & RS6000_BTC_VOID)
11516 return true;
11517
1acf0246
BS		 11518 switch (fn_code)
11519 {
11520 case ALTIVEC_BUILTIN_STVX_V16QI:
11521 case ALTIVEC_BUILTIN_STVX_V8HI:
11522 case ALTIVEC_BUILTIN_STVX_V4SI:
11523 case ALTIVEC_BUILTIN_STVX_V4SF:
11524 case ALTIVEC_BUILTIN_STVX_V2DI:
11525 case ALTIVEC_BUILTIN_STVX_V2DF:
11526 case VSX_BUILTIN_STXVW4X_V16QI:
11527 case VSX_BUILTIN_STXVW4X_V8HI:
11528 case VSX_BUILTIN_STXVW4X_V4SF:
11529 case VSX_BUILTIN_STXVW4X_V4SI:
11530 case VSX_BUILTIN_STXVD2X_V2DF:
11531 case VSX_BUILTIN_STXVD2X_V2DI:
11532 return true;
11533 default:
11534 return false;
11535 }
11536}
11537
11538/* Helper function to handle the gimple folding of a vector compare
11539 operation. This sets up true/false vectors, and uses the
11540 VEC_COND_EXPR operation.
11541 CODE indicates which comparison is to be made. (EQ, GT, ...).
e68cc3a8
ML		 11542 TYPE indicates the type of the result.
11543 Code is inserted before GSI. */
1acf0246 11544static tree
e68cc3a8
ML		 11545fold_build_vec_cmp (tree_code code, tree type, tree arg0, tree arg1,
11546 gimple_stmt_iterator *gsi)
1acf0246 11547{
e8738f4e 11548 tree cmp_type = truth_type_for (type);
1acf0246
BS		 11549 tree zero_vec = build_zero_cst (type);
11550 tree minus_one_vec = build_minus_one_cst (type);
e68cc3a8
ML		 11551 tree temp = create_tmp_reg_or_ssa_name (cmp_type);
11552 gimple *g = gimple_build_assign (temp, code, arg0, arg1);
11553 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11554 return fold_build3 (VEC_COND_EXPR, type, temp, minus_one_vec, zero_vec);
1acf0246
BS		 11555}
11556
11557/* Helper function to handle the in-between steps for the
11558 vector compare built-ins. */
11559static void
11560fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
11561{
11562 tree arg0 = gimple_call_arg (stmt, 0);
11563 tree arg1 = gimple_call_arg (stmt, 1);
11564 tree lhs = gimple_call_lhs (stmt);
e68cc3a8 11565 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1, gsi);
1acf0246
BS		 11566 gimple *g = gimple_build_assign (lhs, cmp);
11567 gimple_set_location (g, gimple_location (stmt));
11568 gsi_replace (gsi, g, true);
11569}
11570
11571/* Helper function to map V2DF and V4SF types to their
11572 integral equivalents (V2DI and V4SI). */
11573tree map_to_integral_tree_type (tree input_tree_type)
11574{
11575 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
11576 return input_tree_type;
11577 else
11578 {
11579 if (types_compatible_p (TREE_TYPE (input_tree_type),
11580 TREE_TYPE (V2DF_type_node)))
11581 return V2DI_type_node;
11582 else if (types_compatible_p (TREE_TYPE (input_tree_type),
11583 TREE_TYPE (V4SF_type_node)))
11584 return V4SI_type_node;
11585 else
11586 gcc_unreachable ();
11587 }
11588}
11589
11590/* Helper function to handle the vector merge[hl] built-ins. The
11591 implementation difference between h and l versions for this code are in
11592 the values used when building of the permute vector for high word versus
11593 low word merge. The variance is keyed off the use_high parameter. */
11594static void
11595fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
11596{
11597 tree arg0 = gimple_call_arg (stmt, 0);
11598 tree arg1 = gimple_call_arg (stmt, 1);
11599 tree lhs = gimple_call_lhs (stmt);
11600 tree lhs_type = TREE_TYPE (lhs);
11601 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
11602 int midpoint = n_elts / 2;
11603 int offset = 0;
11604
11605 if (use_high == 1)
11606 offset = midpoint;
11607
11608 /* The permute_type will match the lhs for integral types. For double and
11609 float types, the permute type needs to map to the V2 or V4 type that
11610 matches size. */
11611 tree permute_type;
11612 permute_type = map_to_integral_tree_type (lhs_type);
11613 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
11614
11615 for (int i = 0; i < midpoint; i++)
11616 {
11617 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11618 offset + i));
11619 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11620 offset + n_elts + i));
11621 }
11622
11623 tree permute = elts.build ();
11624
11625 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
11626 gimple_set_location (g, gimple_location (stmt));
11627 gsi_replace (gsi, g, true);
11628}
11629
11630/* Helper function to handle the vector merge[eo] built-ins. */
11631static void
11632fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
11633{
11634 tree arg0 = gimple_call_arg (stmt, 0);
11635 tree arg1 = gimple_call_arg (stmt, 1);
11636 tree lhs = gimple_call_lhs (stmt);
11637 tree lhs_type = TREE_TYPE (lhs);
11638 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
11639
11640 /* The permute_type will match the lhs for integral types. For double and
11641 float types, the permute type needs to map to the V2 or V4 type that
11642 matches size. */
11643 tree permute_type;
11644 permute_type = map_to_integral_tree_type (lhs_type);
11645
11646 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
11647
11648 /* Build the permute vector. */
11649 for (int i = 0; i < n_elts / 2; i++)
11650 {
11651 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11652 2*i + use_odd));
11653 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11654 2*i + use_odd + n_elts));
11655 }
11656
11657 tree permute = elts.build ();
11658
11659 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
11660 gimple_set_location (g, gimple_location (stmt));
11661 gsi_replace (gsi, g, true);
11662}
11663
8ee2640b
PB		 11664/* Expand the MMA built-ins early, so that we can convert the pass-by-reference
11665 __vector_quad arguments into pass-by-value arguments, leading to more
11666 efficient code generation. */
11667
11668bool
11669rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi)
11670{
11671 gimple *stmt = gsi_stmt (*gsi);
11672 tree fndecl = gimple_call_fndecl (stmt);
11673 enum rs6000_builtins fncode
11674 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
11675 unsigned attr = rs6000_builtin_info[fncode].attr;
11676
11677 if ((attr & RS6000_BTC_GIMPLE) == 0)
11678 return false;
11679
11680 unsigned nopnds = (attr & RS6000_BTC_OPND_MASK);
11681 gimple_seq new_seq = NULL;
11682 gimple *new_call;
11683 tree new_decl;
11684
f8f8909a
AS		 11685 if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC
11686 || fncode == MMA_BUILTIN_DISASSEMBLE_PAIR)
8ee2640b
PB		 11687 {
11688 /* This is an MMA disassemble built-in function. */
8ee2640b 11689 push_gimplify_context (true);
f8f8909a 11690 unsigned nvec = (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) ? 4 : 2;
8ee2640b
PB		 11691 tree dst_ptr = gimple_call_arg (stmt, 0);
11692 tree src_ptr = gimple_call_arg (stmt, 1);
11693 tree src_type = TREE_TYPE (src_ptr);
11694 tree src = make_ssa_name (TREE_TYPE (src_type));
11695 gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq);
11696
f8f8909a
AS		 11697 /* If we are not disassembling an accumulator/pair or our destination is
11698 another accumulator/pair, then just copy the entire thing as is. */
11699 if ((fncode == MMA_BUILTIN_DISASSEMBLE_ACC
11700 && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_quad_type_node)
11701 || (fncode == MMA_BUILTIN_DISASSEMBLE_PAIR
11702 && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_pair_type_node))
8ee2640b
PB		 11703 {
11704 tree dst = build_simple_mem_ref (build1 (VIEW_CONVERT_EXPR,
11705 src_type, dst_ptr));
11706 gimplify_assign (dst, src, &new_seq);
11707 pop_gimplify_context (NULL);
11708 gsi_replace_with_seq (gsi, new_seq, true);
11709 return true;
11710 }
11711
f8f8909a 11712 /* If we're disassembling an accumulator into a different type, we need
8ee2640b 11713 to emit a xxmfacc instruction now, since we cannot do it later. */
f8f8909a
AS		 11714 if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC)
11715 {
11716 new_decl = rs6000_builtin_decls[MMA_BUILTIN_XXMFACC_INTERNAL];
11717 new_call = gimple_build_call (new_decl, 1, src);
11718 src = make_ssa_name (vector_quad_type_node);
11719 gimple_call_set_lhs (new_call, src);
11720 gimple_seq_add_stmt (&new_seq, new_call);
11721 }
8ee2640b 11722
f8f8909a
AS		 11723 /* Copy the accumulator/pair vector by vector. */
11724 new_decl = rs6000_builtin_decls[fncode + 1];
8ee2640b
PB		 11725 tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node,
11726 ptr_mode, true);
11727 tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr);
f8f8909a 11728 for (unsigned i = 0; i < nvec; i++)
8ee2640b 11729 {
f8f8909a 11730 unsigned index = WORDS_BIG_ENDIAN ? i : nvec - 1 - i;
8ee2640b 11731 tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base,
ae575662 11732 build_int_cst (dst_type, index * 16));
f8f8909a
AS		 11733 tree dstssa = make_ssa_name (unsigned_V16QI_type_node);
11734 new_call = gimple_build_call (new_decl, 2, src,
11735 build_int_cstu (uint16_type_node, i));
11736 gimple_call_set_lhs (new_call, dstssa);
11737 gimple_seq_add_stmt (&new_seq, new_call);
11738 gimplify_assign (dst, dstssa, &new_seq);
8ee2640b
PB		 11739 }
11740 pop_gimplify_context (NULL);
11741 gsi_replace_with_seq (gsi, new_seq, true);
11742 return true;
11743 }
11744
11745 /* Convert this built-in into an internal version that uses pass-by-value
11746 arguments. The internal built-in follows immediately after this one. */
11747 new_decl = rs6000_builtin_decls[fncode + 1];
8bc0f24d 11748 tree lhs, op[MAX_MMA_OPERANDS];
8ee2640b 11749 tree acc = gimple_call_arg (stmt, 0);
8ee2640b
PB		 11750 push_gimplify_context (true);
11751
11752 if ((attr & RS6000_BTC_QUAD) != 0)
11753 {
11754 /* This built-in has a pass-by-reference accumulator input, so load it
11755 into a temporary accumulator for use as a pass-by-value input. */
11756 op[0] = make_ssa_name (vector_quad_type_node);
11757 for (unsigned i = 1; i < nopnds; i++)
11758 op[i] = gimple_call_arg (stmt, i);
8bc0f24d 11759 gimplify_assign (op[0], build_simple_mem_ref (acc), &new_seq);
8ee2640b
PB		 11760 }
11761 else
11762 {
11763 /* This built-in does not use its pass-by-reference accumulator argument
11764 as an input argument, so remove it from the input list. */
11765 nopnds--;
11766 for (unsigned i = 0; i < nopnds; i++)
11767 op[i] = gimple_call_arg (stmt, i + 1);
11768 }
11769
11770 switch (nopnds)
11771 {
11772 case 0:
11773 new_call = gimple_build_call (new_decl, 0);
11774 break;
11775 case 1:
11776 new_call = gimple_build_call (new_decl, 1, op[0]);
11777 break;
11778 case 2:
11779 new_call = gimple_build_call (new_decl, 2, op[0], op[1]);
11780 break;
11781 case 3:
11782 new_call = gimple_build_call (new_decl, 3, op[0], op[1], op[2]);
11783 break;
11784 case 4:
11785 new_call = gimple_build_call (new_decl, 4, op[0], op[1], op[2], op[3]);
11786 break;
11787 case 5:
11788 new_call = gimple_build_call (new_decl, 5, op[0], op[1], op[2], op[3],
11789 op[4]);
11790 break;
11791 case 6:
11792 new_call = gimple_build_call (new_decl, 6, op[0], op[1], op[2], op[3],
11793 op[4], op[5]);
11794 break;
11795 case 7:
11796 new_call = gimple_build_call (new_decl, 7, op[0], op[1], op[2], op[3],
11797 op[4], op[5], op[6]);
11798 break;
11799 default:
11800 gcc_unreachable ();
11801 }
11802
11803 if (fncode == MMA_BUILTIN_ASSEMBLE_PAIR)
11804 lhs = make_ssa_name (vector_pair_type_node);
11805 else
11806 lhs = make_ssa_name (vector_quad_type_node);
11807 gimple_call_set_lhs (new_call, lhs);
11808 gimple_seq_add_stmt (&new_seq, new_call);
8bc0f24d 11809 gimplify_assign (build_simple_mem_ref (acc), lhs, &new_seq);
8ee2640b
PB		 11810 pop_gimplify_context (NULL);
11811 gsi_replace_with_seq (gsi, new_seq, true);
11812
11813 return true;
11814}
11815
1acf0246
BS		 11816/* Fold a machine-dependent built-in in GIMPLE. (For folding into
11817 a constant, use rs6000_fold_builtin.) */
11818
11819bool
11820rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
11821{
11822 gimple *stmt = gsi_stmt (*gsi);
11823 tree fndecl = gimple_call_fndecl (stmt);
11824 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
11825 enum rs6000_builtins fn_code
4d732405 11826 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 11827 tree arg0, arg1, lhs, temp;
11828 enum tree_code bcode;
11829 gimple *g;
11830
11831 size_t uns_fncode = (size_t) fn_code;
11832 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
11833 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
11834 const char *fn_name2 = (icode != CODE_FOR_nothing)
11835 ? get_insn_name ((int) icode)
11836 : "nothing";
11837
11838 if (TARGET_DEBUG_BUILTIN)
11839 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
11840 fn_code, fn_name1, fn_name2);
11841
11842 if (!rs6000_fold_gimple)
11843 return false;
11844
11845 /* Prevent gimple folding for code that does not have a LHS, unless it is
11846 allowed per the rs6000_builtin_valid_without_lhs helper function. */
11847 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
11848 return false;
11849
11850 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
8ee2640b 11851 if (!rs6000_builtin_is_supported_p (fn_code))
1acf0246
BS		 11852 return false;
11853
8ee2640b
PB		 11854 if (rs6000_gimple_fold_mma_builtin (gsi))
11855 return true;
11856
1acf0246
BS		 11857 switch (fn_code)
11858 {
11859 /* Flavors of vec_add. We deliberately don't expand
11860 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
11861 TImode, resulting in much poorer code generation. */
11862 case ALTIVEC_BUILTIN_VADDUBM:
11863 case ALTIVEC_BUILTIN_VADDUHM:
11864 case ALTIVEC_BUILTIN_VADDUWM:
11865 case P8V_BUILTIN_VADDUDM:
11866 case ALTIVEC_BUILTIN_VADDFP:
11867 case VSX_BUILTIN_XVADDDP:
11868 bcode = PLUS_EXPR;
11869 do_binary:
11870 arg0 = gimple_call_arg (stmt, 0);
11871 arg1 = gimple_call_arg (stmt, 1);
11872 lhs = gimple_call_lhs (stmt);
11873 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs)))
11874 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs))))
11875 {
11876 /* Ensure the binary operation is performed in a type
11877 that wraps if it is integral type. */
11878 gimple_seq stmts = NULL;
11879 tree type = unsigned_type_for (TREE_TYPE (lhs));
11880 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11881 type, arg0);
11882 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
11883 type, arg1);
11884 tree res = gimple_build (&stmts, gimple_location (stmt), bcode,
11885 type, uarg0, uarg1);
11886 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
11887 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR,
11888 build1 (VIEW_CONVERT_EXPR,
11889 TREE_TYPE (lhs), res));
11890 gsi_replace (gsi, g, true);
11891 return true;
11892 }
11893 g = gimple_build_assign (lhs, bcode, arg0, arg1);
11894 gimple_set_location (g, gimple_location (stmt));
11895 gsi_replace (gsi, g, true);
11896 return true;
11897 /* Flavors of vec_sub. We deliberately don't expand
11898 P8V_BUILTIN_VSUBUQM. */
11899 case ALTIVEC_BUILTIN_VSUBUBM:
11900 case ALTIVEC_BUILTIN_VSUBUHM:
11901 case ALTIVEC_BUILTIN_VSUBUWM:
11902 case P8V_BUILTIN_VSUBUDM:
11903 case ALTIVEC_BUILTIN_VSUBFP:
11904 case VSX_BUILTIN_XVSUBDP:
11905 bcode = MINUS_EXPR;
11906 goto do_binary;
11907 case VSX_BUILTIN_XVMULSP:
11908 case VSX_BUILTIN_XVMULDP:
11909 arg0 = gimple_call_arg (stmt, 0);
11910 arg1 = gimple_call_arg (stmt, 1);
11911 lhs = gimple_call_lhs (stmt);
11912 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
11913 gimple_set_location (g, gimple_location (stmt));
11914 gsi_replace (gsi, g, true);
11915 return true;
11916 /* Even element flavors of vec_mul (signed). */
11917 case ALTIVEC_BUILTIN_VMULESB:
11918 case ALTIVEC_BUILTIN_VMULESH:
11919 case P8V_BUILTIN_VMULESW:
11920 /* Even element flavors of vec_mul (unsigned). */
11921 case ALTIVEC_BUILTIN_VMULEUB:
11922 case ALTIVEC_BUILTIN_VMULEUH:
11923 case P8V_BUILTIN_VMULEUW:
11924 arg0 = gimple_call_arg (stmt, 0);
11925 arg1 = gimple_call_arg (stmt, 1);
11926 lhs = gimple_call_lhs (stmt);
11927 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
11928 gimple_set_location (g, gimple_location (stmt));
11929 gsi_replace (gsi, g, true);
11930 return true;
11931 /* Odd element flavors of vec_mul (signed). */
11932 case ALTIVEC_BUILTIN_VMULOSB:
11933 case ALTIVEC_BUILTIN_VMULOSH:
11934 case P8V_BUILTIN_VMULOSW:
11935 /* Odd element flavors of vec_mul (unsigned). */
11936 case ALTIVEC_BUILTIN_VMULOUB:
11937 case ALTIVEC_BUILTIN_VMULOUH:
11938 case P8V_BUILTIN_VMULOUW:
11939 arg0 = gimple_call_arg (stmt, 0);
11940 arg1 = gimple_call_arg (stmt, 1);
11941 lhs = gimple_call_lhs (stmt);
11942 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
11943 gimple_set_location (g, gimple_location (stmt));
11944 gsi_replace (gsi, g, true);
11945 return true;
11946 /* Flavors of vec_div (Integer). */
11947 case VSX_BUILTIN_DIV_V2DI:
11948 case VSX_BUILTIN_UDIV_V2DI:
11949 arg0 = gimple_call_arg (stmt, 0);
11950 arg1 = gimple_call_arg (stmt, 1);
11951 lhs = gimple_call_lhs (stmt);
11952 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
11953 gimple_set_location (g, gimple_location (stmt));
11954 gsi_replace (gsi, g, true);
11955 return true;
11956 /* Flavors of vec_div (Float). */
11957 case VSX_BUILTIN_XVDIVSP:
11958 case VSX_BUILTIN_XVDIVDP:
11959 arg0 = gimple_call_arg (stmt, 0);
11960 arg1 = gimple_call_arg (stmt, 1);
11961 lhs = gimple_call_lhs (stmt);
11962 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
11963 gimple_set_location (g, gimple_location (stmt));
11964 gsi_replace (gsi, g, true);
11965 return true;
11966 /* Flavors of vec_and. */
4559be23
PB		 11967 case ALTIVEC_BUILTIN_VAND_V16QI_UNS:
11968 case ALTIVEC_BUILTIN_VAND_V16QI:
11969 case ALTIVEC_BUILTIN_VAND_V8HI_UNS:
11970 case ALTIVEC_BUILTIN_VAND_V8HI:
11971 case ALTIVEC_BUILTIN_VAND_V4SI_UNS:
11972 case ALTIVEC_BUILTIN_VAND_V4SI:
11973 case ALTIVEC_BUILTIN_VAND_V2DI_UNS:
11974 case ALTIVEC_BUILTIN_VAND_V2DI:
11975 case ALTIVEC_BUILTIN_VAND_V4SF:
11976 case ALTIVEC_BUILTIN_VAND_V2DF:
1acf0246
BS		 11977 arg0 = gimple_call_arg (stmt, 0);
11978 arg1 = gimple_call_arg (stmt, 1);
11979 lhs = gimple_call_lhs (stmt);
11980 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
11981 gimple_set_location (g, gimple_location (stmt));
11982 gsi_replace (gsi, g, true);
11983 return true;
11984 /* Flavors of vec_andc. */
4559be23
PB		 11985 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS:
11986 case ALTIVEC_BUILTIN_VANDC_V16QI:
11987 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS:
11988 case ALTIVEC_BUILTIN_VANDC_V8HI:
11989 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS:
11990 case ALTIVEC_BUILTIN_VANDC_V4SI:
11991 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS:
11992 case ALTIVEC_BUILTIN_VANDC_V2DI:
11993 case ALTIVEC_BUILTIN_VANDC_V4SF:
11994 case ALTIVEC_BUILTIN_VANDC_V2DF:
1acf0246
BS		 11995 arg0 = gimple_call_arg (stmt, 0);
11996 arg1 = gimple_call_arg (stmt, 1);
11997 lhs = gimple_call_lhs (stmt);
11998 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
11999 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
12000 gimple_set_location (g, gimple_location (stmt));
12001 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12002 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
12003 gimple_set_location (g, gimple_location (stmt));
12004 gsi_replace (gsi, g, true);
12005 return true;
12006 /* Flavors of vec_nand. */
12007 case P8V_BUILTIN_VEC_NAND:
4559be23 12008 case P8V_BUILTIN_NAND_V16QI_UNS:
1acf0246 12009 case P8V_BUILTIN_NAND_V16QI:
4559be23 12010 case P8V_BUILTIN_NAND_V8HI_UNS:
1acf0246 12011 case P8V_BUILTIN_NAND_V8HI:
4559be23 12012 case P8V_BUILTIN_NAND_V4SI_UNS:
1acf0246 12013 case P8V_BUILTIN_NAND_V4SI:
4559be23
PB		 12014 case P8V_BUILTIN_NAND_V2DI_UNS:
12015 case P8V_BUILTIN_NAND_V2DI:
1acf0246
BS		 12016 case P8V_BUILTIN_NAND_V4SF:
12017 case P8V_BUILTIN_NAND_V2DF:
1acf0246
BS		 12018 arg0 = gimple_call_arg (stmt, 0);
12019 arg1 = gimple_call_arg (stmt, 1);
12020 lhs = gimple_call_lhs (stmt);
12021 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
12022 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
12023 gimple_set_location (g, gimple_location (stmt));
12024 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12025 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
12026 gimple_set_location (g, gimple_location (stmt));
12027 gsi_replace (gsi, g, true);
12028 return true;
12029 /* Flavors of vec_or. */
4559be23
PB		 12030 case ALTIVEC_BUILTIN_VOR_V16QI_UNS:
12031 case ALTIVEC_BUILTIN_VOR_V16QI:
12032 case ALTIVEC_BUILTIN_VOR_V8HI_UNS:
12033 case ALTIVEC_BUILTIN_VOR_V8HI:
12034 case ALTIVEC_BUILTIN_VOR_V4SI_UNS:
12035 case ALTIVEC_BUILTIN_VOR_V4SI:
12036 case ALTIVEC_BUILTIN_VOR_V2DI_UNS:
12037 case ALTIVEC_BUILTIN_VOR_V2DI:
12038 case ALTIVEC_BUILTIN_VOR_V4SF:
12039 case ALTIVEC_BUILTIN_VOR_V2DF:
1acf0246
BS		 12040 arg0 = gimple_call_arg (stmt, 0);
12041 arg1 = gimple_call_arg (stmt, 1);
12042 lhs = gimple_call_lhs (stmt);
12043 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
12044 gimple_set_location (g, gimple_location (stmt));
12045 gsi_replace (gsi, g, true);
12046 return true;
12047 /* flavors of vec_orc. */
4559be23 12048 case P8V_BUILTIN_ORC_V16QI_UNS:
1acf0246 12049 case P8V_BUILTIN_ORC_V16QI:
4559be23 12050 case P8V_BUILTIN_ORC_V8HI_UNS:
1acf0246 12051 case P8V_BUILTIN_ORC_V8HI:
4559be23 12052 case P8V_BUILTIN_ORC_V4SI_UNS:
1acf0246 12053 case P8V_BUILTIN_ORC_V4SI:
4559be23
PB		 12054 case P8V_BUILTIN_ORC_V2DI_UNS:
12055 case P8V_BUILTIN_ORC_V2DI:
1acf0246
BS		 12056 case P8V_BUILTIN_ORC_V4SF:
12057 case P8V_BUILTIN_ORC_V2DF:
1acf0246
BS		 12058 arg0 = gimple_call_arg (stmt, 0);
12059 arg1 = gimple_call_arg (stmt, 1);
12060 lhs = gimple_call_lhs (stmt);
12061 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
12062 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
12063 gimple_set_location (g, gimple_location (stmt));
12064 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12065 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
12066 gimple_set_location (g, gimple_location (stmt));
12067 gsi_replace (gsi, g, true);
12068 return true;
12069 /* Flavors of vec_xor. */
4559be23
PB		 12070 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS:
12071 case ALTIVEC_BUILTIN_VXOR_V16QI:
12072 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS:
12073 case ALTIVEC_BUILTIN_VXOR_V8HI:
12074 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS:
12075 case ALTIVEC_BUILTIN_VXOR_V4SI:
12076 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS:
12077 case ALTIVEC_BUILTIN_VXOR_V2DI:
12078 case ALTIVEC_BUILTIN_VXOR_V4SF:
12079 case ALTIVEC_BUILTIN_VXOR_V2DF:
1acf0246
BS		 12080 arg0 = gimple_call_arg (stmt, 0);
12081 arg1 = gimple_call_arg (stmt, 1);
12082 lhs = gimple_call_lhs (stmt);
12083 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
12084 gimple_set_location (g, gimple_location (stmt));
12085 gsi_replace (gsi, g, true);
12086 return true;
12087 /* Flavors of vec_nor. */
4559be23
PB		 12088 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS:
12089 case ALTIVEC_BUILTIN_VNOR_V16QI:
12090 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS:
12091 case ALTIVEC_BUILTIN_VNOR_V8HI:
12092 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS:
12093 case ALTIVEC_BUILTIN_VNOR_V4SI:
12094 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS:
12095 case ALTIVEC_BUILTIN_VNOR_V2DI:
12096 case ALTIVEC_BUILTIN_VNOR_V4SF:
12097 case ALTIVEC_BUILTIN_VNOR_V2DF:
1acf0246
BS		 12098 arg0 = gimple_call_arg (stmt, 0);
12099 arg1 = gimple_call_arg (stmt, 1);
12100 lhs = gimple_call_lhs (stmt);
12101 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
12102 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
12103 gimple_set_location (g, gimple_location (stmt));
12104 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12105 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
12106 gimple_set_location (g, gimple_location (stmt));
12107 gsi_replace (gsi, g, true);
12108 return true;
12109 /* flavors of vec_abs. */
12110 case ALTIVEC_BUILTIN_ABS_V16QI:
12111 case ALTIVEC_BUILTIN_ABS_V8HI:
12112 case ALTIVEC_BUILTIN_ABS_V4SI:
12113 case ALTIVEC_BUILTIN_ABS_V4SF:
12114 case P8V_BUILTIN_ABS_V2DI:
12115 case VSX_BUILTIN_XVABSDP:
12116 arg0 = gimple_call_arg (stmt, 0);
12117 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
12118 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
12119 return false;
12120 lhs = gimple_call_lhs (stmt);
12121 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
12122 gimple_set_location (g, gimple_location (stmt));
12123 gsi_replace (gsi, g, true);
12124 return true;
12125 /* flavors of vec_min. */
12126 case VSX_BUILTIN_XVMINDP:
12127 case P8V_BUILTIN_VMINSD:
12128 case P8V_BUILTIN_VMINUD:
12129 case ALTIVEC_BUILTIN_VMINSB:
12130 case ALTIVEC_BUILTIN_VMINSH:
12131 case ALTIVEC_BUILTIN_VMINSW:
12132 case ALTIVEC_BUILTIN_VMINUB:
12133 case ALTIVEC_BUILTIN_VMINUH:
12134 case ALTIVEC_BUILTIN_VMINUW:
12135 case ALTIVEC_BUILTIN_VMINFP:
12136 arg0 = gimple_call_arg (stmt, 0);
12137 arg1 = gimple_call_arg (stmt, 1);
12138 lhs = gimple_call_lhs (stmt);
12139 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
12140 gimple_set_location (g, gimple_location (stmt));
12141 gsi_replace (gsi, g, true);
12142 return true;
12143 /* flavors of vec_max. */
12144 case VSX_BUILTIN_XVMAXDP:
12145 case P8V_BUILTIN_VMAXSD:
12146 case P8V_BUILTIN_VMAXUD:
12147 case ALTIVEC_BUILTIN_VMAXSB:
12148 case ALTIVEC_BUILTIN_VMAXSH:
12149 case ALTIVEC_BUILTIN_VMAXSW:
12150 case ALTIVEC_BUILTIN_VMAXUB:
12151 case ALTIVEC_BUILTIN_VMAXUH:
12152 case ALTIVEC_BUILTIN_VMAXUW:
12153 case ALTIVEC_BUILTIN_VMAXFP:
12154 arg0 = gimple_call_arg (stmt, 0);
12155 arg1 = gimple_call_arg (stmt, 1);
12156 lhs = gimple_call_lhs (stmt);
12157 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
12158 gimple_set_location (g, gimple_location (stmt));
12159 gsi_replace (gsi, g, true);
12160 return true;
12161 /* Flavors of vec_eqv. */
12162 case P8V_BUILTIN_EQV_V16QI:
12163 case P8V_BUILTIN_EQV_V8HI:
12164 case P8V_BUILTIN_EQV_V4SI:
12165 case P8V_BUILTIN_EQV_V4SF:
12166 case P8V_BUILTIN_EQV_V2DF:
12167 case P8V_BUILTIN_EQV_V2DI:
12168 arg0 = gimple_call_arg (stmt, 0);
12169 arg1 = gimple_call_arg (stmt, 1);
12170 lhs = gimple_call_lhs (stmt);
12171 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
12172 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
12173 gimple_set_location (g, gimple_location (stmt));
12174 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12175 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
12176 gimple_set_location (g, gimple_location (stmt));
12177 gsi_replace (gsi, g, true);
12178 return true;
12179 /* Flavors of vec_rotate_left. */
12180 case ALTIVEC_BUILTIN_VRLB:
12181 case ALTIVEC_BUILTIN_VRLH:
12182 case ALTIVEC_BUILTIN_VRLW:
12183 case P8V_BUILTIN_VRLD:
12184 arg0 = gimple_call_arg (stmt, 0);
12185 arg1 = gimple_call_arg (stmt, 1);
12186 lhs = gimple_call_lhs (stmt);
12187 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
12188 gimple_set_location (g, gimple_location (stmt));
12189 gsi_replace (gsi, g, true);
12190 return true;
12191 /* Flavors of vector shift right algebraic.
12192 vec_sra{b,h,w} -> vsra{b,h,w}. */
12193 case ALTIVEC_BUILTIN_VSRAB:
12194 case ALTIVEC_BUILTIN_VSRAH:
12195 case ALTIVEC_BUILTIN_VSRAW:
12196 case P8V_BUILTIN_VSRAD:
12197 {
12198 arg0 = gimple_call_arg (stmt, 0);
12199 arg1 = gimple_call_arg (stmt, 1);
12200 lhs = gimple_call_lhs (stmt);
12201 tree arg1_type = TREE_TYPE (arg1);
12202 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
12203 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
12204 location_t loc = gimple_location (stmt);
12205 /* Force arg1 into the range valid matching the arg0 type. */
12206 /* Build a vector consisting of the max valid bit-size values. */
12207 int n_elts = VECTOR_CST_NELTS (arg1);
12208 tree element_size = build_int_cst (unsigned_element_type,
12209 128 / n_elts);
12210 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
12211 for (int i = 0; i < n_elts; i++)
12212 elts.safe_push (element_size);
12213 tree modulo_tree = elts.build ();
12214 /* Modulo the provided shift value against that vector. */
12215 gimple_seq stmts = NULL;
12216 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12217 unsigned_arg1_type, arg1);
12218 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
12219 unsigned_arg1_type, unsigned_arg1,
12220 modulo_tree);
12221 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12222 /* And finally, do the shift. */
12223 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1);
12224 gimple_set_location (g, loc);
12225 gsi_replace (gsi, g, true);
12226 return true;
12227 }
12228 /* Flavors of vector shift left.
12229 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
12230 case ALTIVEC_BUILTIN_VSLB:
12231 case ALTIVEC_BUILTIN_VSLH:
12232 case ALTIVEC_BUILTIN_VSLW:
12233 case P8V_BUILTIN_VSLD:
12234 {
12235 location_t loc;
12236 gimple_seq stmts = NULL;
12237 arg0 = gimple_call_arg (stmt, 0);
12238 tree arg0_type = TREE_TYPE (arg0);
12239 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
12240 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
12241 return false;
12242 arg1 = gimple_call_arg (stmt, 1);
12243 tree arg1_type = TREE_TYPE (arg1);
12244 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
12245 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
12246 loc = gimple_location (stmt);
12247 lhs = gimple_call_lhs (stmt);
12248 /* Force arg1 into the range valid matching the arg0 type. */
12249 /* Build a vector consisting of the max valid bit-size values. */
12250 int n_elts = VECTOR_CST_NELTS (arg1);
12251 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
12252 * BITS_PER_UNIT;
12253 tree element_size = build_int_cst (unsigned_element_type,
12254 tree_size_in_bits / n_elts);
12255 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
12256 for (int i = 0; i < n_elts; i++)
12257 elts.safe_push (element_size);
12258 tree modulo_tree = elts.build ();
12259 /* Modulo the provided shift value against that vector. */
12260 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12261 unsigned_arg1_type, arg1);
12262 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
12263 unsigned_arg1_type, unsigned_arg1,
12264 modulo_tree);
12265 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12266 /* And finally, do the shift. */
12267 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
12268 gimple_set_location (g, gimple_location (stmt));
12269 gsi_replace (gsi, g, true);
12270 return true;
12271 }
12272 /* Flavors of vector shift right. */
12273 case ALTIVEC_BUILTIN_VSRB:
12274 case ALTIVEC_BUILTIN_VSRH:
12275 case ALTIVEC_BUILTIN_VSRW:
12276 case P8V_BUILTIN_VSRD:
12277 {
12278 arg0 = gimple_call_arg (stmt, 0);
12279 arg1 = gimple_call_arg (stmt, 1);
12280 lhs = gimple_call_lhs (stmt);
12281 tree arg1_type = TREE_TYPE (arg1);
12282 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
12283 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
12284 location_t loc = gimple_location (stmt);
12285 gimple_seq stmts = NULL;
12286 /* Convert arg0 to unsigned. */
12287 tree arg0_unsigned
12288 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12289 unsigned_type_for (TREE_TYPE (arg0)), arg0);
12290 /* Force arg1 into the range valid matching the arg0 type. */
12291 /* Build a vector consisting of the max valid bit-size values. */
12292 int n_elts = VECTOR_CST_NELTS (arg1);
12293 tree element_size = build_int_cst (unsigned_element_type,
12294 128 / n_elts);
12295 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
12296 for (int i = 0; i < n_elts; i++)
12297 elts.safe_push (element_size);
12298 tree modulo_tree = elts.build ();
12299 /* Modulo the provided shift value against that vector. */
12300 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12301 unsigned_arg1_type, arg1);
12302 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
12303 unsigned_arg1_type, unsigned_arg1,
12304 modulo_tree);
12305 /* Do the shift. */
12306 tree res
12307 = gimple_build (&stmts, RSHIFT_EXPR,
12308 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1);
12309 /* Convert result back to the lhs type. */
12310 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
12311 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12312 update_call_from_tree (gsi, res);
12313 return true;
12314 }
12315 /* Vector loads. */
12316 case ALTIVEC_BUILTIN_LVX_V16QI:
12317 case ALTIVEC_BUILTIN_LVX_V8HI:
12318 case ALTIVEC_BUILTIN_LVX_V4SI:
12319 case ALTIVEC_BUILTIN_LVX_V4SF:
12320 case ALTIVEC_BUILTIN_LVX_V2DI:
12321 case ALTIVEC_BUILTIN_LVX_V2DF:
12322 case ALTIVEC_BUILTIN_LVX_V1TI:
12323 {
12324 arg0 = gimple_call_arg (stmt, 0); // offset
12325 arg1 = gimple_call_arg (stmt, 1); // address
12326 lhs = gimple_call_lhs (stmt);
12327 location_t loc = gimple_location (stmt);
12328 /* Since arg1 may be cast to a different type, just use ptr_type_node
12329 here instead of trying to enforce TBAA on pointer types. */
12330 tree arg1_type = ptr_type_node;
12331 tree lhs_type = TREE_TYPE (lhs);
12332 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
12333 the tree using the value from arg0. The resulting type will match
12334 the type of arg1. */
12335 gimple_seq stmts = NULL;
12336 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
12337 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
12338 arg1_type, arg1, temp_offset);
12339 /* Mask off any lower bits from the address. */
12340 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
12341 arg1_type, temp_addr,
12342 build_int_cst (arg1_type, -16));
12343 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12344 if (!is_gimple_mem_ref_addr (aligned_addr))
12345 {
12346 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
12347 gimple *g = gimple_build_assign (t, aligned_addr);
12348 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12349 aligned_addr = t;
12350 }
12351 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
12352 take an offset, but since we've already incorporated the offset
12353 above, here we just pass in a zero. */
12354 gimple *g
12355 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
12356 build_int_cst (arg1_type, 0)));
12357 gimple_set_location (g, loc);
12358 gsi_replace (gsi, g, true);
12359 return true;
12360 }
12361 /* Vector stores. */
12362 case ALTIVEC_BUILTIN_STVX_V16QI:
12363 case ALTIVEC_BUILTIN_STVX_V8HI:
12364 case ALTIVEC_BUILTIN_STVX_V4SI:
12365 case ALTIVEC_BUILTIN_STVX_V4SF:
12366 case ALTIVEC_BUILTIN_STVX_V2DI:
12367 case ALTIVEC_BUILTIN_STVX_V2DF:
12368 {
12369 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
12370 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
12371 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
12372 location_t loc = gimple_location (stmt);
12373 tree arg0_type = TREE_TYPE (arg0);
12374 /* Use ptr_type_node (no TBAA) for the arg2_type.
12375 FIXME: (Richard) "A proper fix would be to transition this type as
12376 seen from the frontend to GIMPLE, for example in a similar way we
12377 do for MEM_REFs by piggy-backing that on an extra argument, a
12378 constant zero pointer of the alias pointer type to use (which would
12379 also serve as a type indicator of the store itself). I'd use a
12380 target specific internal function for this (not sure if we can have
12381 those target specific, but I guess if it's folded away then that's
12382 fine) and get away with the overload set." */
12383 tree arg2_type = ptr_type_node;
12384 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
12385 the tree using the value from arg0. The resulting type will match
12386 the type of arg2. */
12387 gimple_seq stmts = NULL;
12388 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
12389 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
12390 arg2_type, arg2, temp_offset);
12391 /* Mask off any lower bits from the address. */
12392 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
12393 arg2_type, temp_addr,
12394 build_int_cst (arg2_type, -16));
12395 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12396 if (!is_gimple_mem_ref_addr (aligned_addr))
12397 {
12398 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
12399 gimple *g = gimple_build_assign (t, aligned_addr);
12400 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12401 aligned_addr = t;
12402 }
12403 /* The desired gimple result should be similar to:
12404 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
12405 gimple *g
12406 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
12407 build_int_cst (arg2_type, 0)), arg0);
12408 gimple_set_location (g, loc);
12409 gsi_replace (gsi, g, true);
12410 return true;
12411 }
12412
12413 /* unaligned Vector loads. */
12414 case VSX_BUILTIN_LXVW4X_V16QI:
12415 case VSX_BUILTIN_LXVW4X_V8HI:
12416 case VSX_BUILTIN_LXVW4X_V4SF:
12417 case VSX_BUILTIN_LXVW4X_V4SI:
12418 case VSX_BUILTIN_LXVD2X_V2DF:
12419 case VSX_BUILTIN_LXVD2X_V2DI:
12420 {
12421 arg0 = gimple_call_arg (stmt, 0); // offset
12422 arg1 = gimple_call_arg (stmt, 1); // address
12423 lhs = gimple_call_lhs (stmt);
12424 location_t loc = gimple_location (stmt);
12425 /* Since arg1 may be cast to a different type, just use ptr_type_node
12426 here instead of trying to enforce TBAA on pointer types. */
12427 tree arg1_type = ptr_type_node;
12428 tree lhs_type = TREE_TYPE (lhs);
12429 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
12430 required alignment (power) is 4 bytes regardless of data type. */
12431 tree align_ltype = build_aligned_type (lhs_type, 4);
12432 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
12433 the tree using the value from arg0. The resulting type will match
12434 the type of arg1. */
12435 gimple_seq stmts = NULL;
12436 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
12437 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
12438 arg1_type, arg1, temp_offset);
12439 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12440 if (!is_gimple_mem_ref_addr (temp_addr))
12441 {
12442 tree t = make_ssa_name (TREE_TYPE (temp_addr));
12443 gimple *g = gimple_build_assign (t, temp_addr);
12444 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12445 temp_addr = t;
12446 }
12447 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
12448 take an offset, but since we've already incorporated the offset
12449 above, here we just pass in a zero. */
12450 gimple *g;
12451 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
12452 build_int_cst (arg1_type, 0)));
12453 gimple_set_location (g, loc);
12454 gsi_replace (gsi, g, true);
12455 return true;
12456 }
12457
12458 /* unaligned Vector stores. */
12459 case VSX_BUILTIN_STXVW4X_V16QI:
12460 case VSX_BUILTIN_STXVW4X_V8HI:
12461 case VSX_BUILTIN_STXVW4X_V4SF:
12462 case VSX_BUILTIN_STXVW4X_V4SI:
12463 case VSX_BUILTIN_STXVD2X_V2DF:
12464 case VSX_BUILTIN_STXVD2X_V2DI:
12465 {
12466 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
12467 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
12468 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
12469 location_t loc = gimple_location (stmt);
12470 tree arg0_type = TREE_TYPE (arg0);
12471 /* Use ptr_type_node (no TBAA) for the arg2_type. */
12472 tree arg2_type = ptr_type_node;
12473 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
12474 required alignment (power) is 4 bytes regardless of data type. */
12475 tree align_stype = build_aligned_type (arg0_type, 4);
12476 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
12477 the tree using the value from arg1. */
12478 gimple_seq stmts = NULL;
12479 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
12480 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
12481 arg2_type, arg2, temp_offset);
12482 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12483 if (!is_gimple_mem_ref_addr (temp_addr))
12484 {
12485 tree t = make_ssa_name (TREE_TYPE (temp_addr));
12486 gimple *g = gimple_build_assign (t, temp_addr);
12487 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12488 temp_addr = t;
12489 }
12490 gimple *g;
12491 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
12492 build_int_cst (arg2_type, 0)), arg0);
12493 gimple_set_location (g, loc);
12494 gsi_replace (gsi, g, true);
12495 return true;
12496 }
12497
12498 /* Vector Fused multiply-add (fma). */
12499 case ALTIVEC_BUILTIN_VMADDFP:
12500 case VSX_BUILTIN_XVMADDDP:
12501 case ALTIVEC_BUILTIN_VMLADDUHM:
12502 {
12503 arg0 = gimple_call_arg (stmt, 0);
12504 arg1 = gimple_call_arg (stmt, 1);
12505 tree arg2 = gimple_call_arg (stmt, 2);
12506 lhs = gimple_call_lhs (stmt);
12507 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
12508 gimple_call_set_lhs (g, lhs);
12509 gimple_call_set_nothrow (g, true);
12510 gimple_set_location (g, gimple_location (stmt));
12511 gsi_replace (gsi, g, true);
12512 return true;
12513 }
12514
12515 /* Vector compares; EQ, NE, GE, GT, LE. */
12516 case ALTIVEC_BUILTIN_VCMPEQUB:
12517 case ALTIVEC_BUILTIN_VCMPEQUH:
12518 case ALTIVEC_BUILTIN_VCMPEQUW:
12519 case P8V_BUILTIN_VCMPEQUD:
12520 fold_compare_helper (gsi, EQ_EXPR, stmt);
12521 return true;
12522
12523 case P9V_BUILTIN_CMPNEB:
12524 case P9V_BUILTIN_CMPNEH:
12525 case P9V_BUILTIN_CMPNEW:
12526 fold_compare_helper (gsi, NE_EXPR, stmt);
12527 return true;
12528
12529 case VSX_BUILTIN_CMPGE_16QI:
12530 case VSX_BUILTIN_CMPGE_U16QI:
12531 case VSX_BUILTIN_CMPGE_8HI:
12532 case VSX_BUILTIN_CMPGE_U8HI:
12533 case VSX_BUILTIN_CMPGE_4SI:
12534 case VSX_BUILTIN_CMPGE_U4SI:
12535 case VSX_BUILTIN_CMPGE_2DI:
12536 case VSX_BUILTIN_CMPGE_U2DI:
12537 fold_compare_helper (gsi, GE_EXPR, stmt);
12538 return true;
12539
12540 case ALTIVEC_BUILTIN_VCMPGTSB:
12541 case ALTIVEC_BUILTIN_VCMPGTUB:
12542 case ALTIVEC_BUILTIN_VCMPGTSH:
12543 case ALTIVEC_BUILTIN_VCMPGTUH:
12544 case ALTIVEC_BUILTIN_VCMPGTSW:
12545 case ALTIVEC_BUILTIN_VCMPGTUW:
12546 case P8V_BUILTIN_VCMPGTUD:
12547 case P8V_BUILTIN_VCMPGTSD:
12548 fold_compare_helper (gsi, GT_EXPR, stmt);
12549 return true;
12550
12551 case VSX_BUILTIN_CMPLE_16QI:
12552 case VSX_BUILTIN_CMPLE_U16QI:
12553 case VSX_BUILTIN_CMPLE_8HI:
12554 case VSX_BUILTIN_CMPLE_U8HI:
12555 case VSX_BUILTIN_CMPLE_4SI:
12556 case VSX_BUILTIN_CMPLE_U4SI:
12557 case VSX_BUILTIN_CMPLE_2DI:
12558 case VSX_BUILTIN_CMPLE_U2DI:
12559 fold_compare_helper (gsi, LE_EXPR, stmt);
12560 return true;
12561
12562 /* flavors of vec_splat_[us]{8,16,32}. */
12563 case ALTIVEC_BUILTIN_VSPLTISB:
12564 case ALTIVEC_BUILTIN_VSPLTISH:
12565 case ALTIVEC_BUILTIN_VSPLTISW:
12566 {
12567 arg0 = gimple_call_arg (stmt, 0);
12568 lhs = gimple_call_lhs (stmt);
12569
12570 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
12571 5-bit signed constant in range -16 to +15. */
12572 if (TREE_CODE (arg0) != INTEGER_CST
12573 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15))
12574 return false;
12575 gimple_seq stmts = NULL;
12576 location_t loc = gimple_location (stmt);
12577 tree splat_value = gimple_convert (&stmts, loc,
12578 TREE_TYPE (TREE_TYPE (lhs)), arg0);
12579 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12580 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
12581 g = gimple_build_assign (lhs, splat_tree);
12582 gimple_set_location (g, gimple_location (stmt));
12583 gsi_replace (gsi, g, true);
12584 return true;
12585 }
12586
12587 /* Flavors of vec_splat. */
12588 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
12589 case ALTIVEC_BUILTIN_VSPLTB:
12590 case ALTIVEC_BUILTIN_VSPLTH:
12591 case ALTIVEC_BUILTIN_VSPLTW:
12592 case VSX_BUILTIN_XXSPLTD_V2DI:
12593 case VSX_BUILTIN_XXSPLTD_V2DF:
12594 {
12595 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
12596 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
12597 /* Only fold the vec_splat_*() if arg1 is both a constant value and
12598 is a valid index into the arg0 vector. */
12599 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
12600 if (TREE_CODE (arg1) != INTEGER_CST
12601 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
12602 return false;
12603 lhs = gimple_call_lhs (stmt);
12604 tree lhs_type = TREE_TYPE (lhs);
12605 tree arg0_type = TREE_TYPE (arg0);
12606 tree splat;
12607 if (TREE_CODE (arg0) == VECTOR_CST)
12608 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
12609 else
12610 {
12611 /* Determine (in bits) the length and start location of the
12612 splat value for a call to the tree_vec_extract helper. */
12613 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
12614 * BITS_PER_UNIT / n_elts;
12615 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
12616 tree len = build_int_cst (bitsizetype, splat_elem_size);
12617 tree start = build_int_cst (bitsizetype, splat_start_bit);
12618 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
12619 len, start);
12620 }
12621 /* And finally, build the new vector. */
12622 tree splat_tree = build_vector_from_val (lhs_type, splat);
12623 g = gimple_build_assign (lhs, splat_tree);
12624 gimple_set_location (g, gimple_location (stmt));
12625 gsi_replace (gsi, g, true);
12626 return true;
12627 }
12628
12629 /* vec_mergel (integrals). */
12630 case ALTIVEC_BUILTIN_VMRGLH:
12631 case ALTIVEC_BUILTIN_VMRGLW:
12632 case VSX_BUILTIN_XXMRGLW_4SI:
12633 case ALTIVEC_BUILTIN_VMRGLB:
12634 case VSX_BUILTIN_VEC_MERGEL_V2DI:
12635 case VSX_BUILTIN_XXMRGLW_4SF:
12636 case VSX_BUILTIN_VEC_MERGEL_V2DF:
12637 fold_mergehl_helper (gsi, stmt, 1);
12638 return true;
12639 /* vec_mergeh (integrals). */
12640 case ALTIVEC_BUILTIN_VMRGHH:
12641 case ALTIVEC_BUILTIN_VMRGHW:
12642 case VSX_BUILTIN_XXMRGHW_4SI:
12643 case ALTIVEC_BUILTIN_VMRGHB:
12644 case VSX_BUILTIN_VEC_MERGEH_V2DI:
12645 case VSX_BUILTIN_XXMRGHW_4SF:
12646 case VSX_BUILTIN_VEC_MERGEH_V2DF:
12647 fold_mergehl_helper (gsi, stmt, 0);
12648 return true;
12649
12650 /* Flavors of vec_mergee. */
12651 case P8V_BUILTIN_VMRGEW_V4SI:
12652 case P8V_BUILTIN_VMRGEW_V2DI:
12653 case P8V_BUILTIN_VMRGEW_V4SF:
12654 case P8V_BUILTIN_VMRGEW_V2DF:
12655 fold_mergeeo_helper (gsi, stmt, 0);
12656 return true;
12657 /* Flavors of vec_mergeo. */
12658 case P8V_BUILTIN_VMRGOW_V4SI:
12659 case P8V_BUILTIN_VMRGOW_V2DI:
12660 case P8V_BUILTIN_VMRGOW_V4SF:
12661 case P8V_BUILTIN_VMRGOW_V2DF:
12662 fold_mergeeo_helper (gsi, stmt, 1);
12663 return true;
12664
12665 /* d = vec_pack (a, b) */
12666 case P8V_BUILTIN_VPKUDUM:
12667 case ALTIVEC_BUILTIN_VPKUHUM:
12668 case ALTIVEC_BUILTIN_VPKUWUM:
12669 {
12670 arg0 = gimple_call_arg (stmt, 0);
12671 arg1 = gimple_call_arg (stmt, 1);
12672 lhs = gimple_call_lhs (stmt);
12673 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
12674 gimple_set_location (g, gimple_location (stmt));
12675 gsi_replace (gsi, g, true);
12676 return true;
12677 }
12678
12679 /* d = vec_unpackh (a) */
12680 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
12681 in this code is sensitive to endian-ness, and needs to be inverted to
12682 handle both LE and BE targets. */
12683 case ALTIVEC_BUILTIN_VUPKHSB:
12684 case ALTIVEC_BUILTIN_VUPKHSH:
12685 case P8V_BUILTIN_VUPKHSW:
12686 {
12687 arg0 = gimple_call_arg (stmt, 0);
12688 lhs = gimple_call_lhs (stmt);
12689 if (BYTES_BIG_ENDIAN)
12690 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
12691 else
12692 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
12693 gimple_set_location (g, gimple_location (stmt));
12694 gsi_replace (gsi, g, true);
12695 return true;
12696 }
12697 /* d = vec_unpackl (a) */
12698 case ALTIVEC_BUILTIN_VUPKLSB:
12699 case ALTIVEC_BUILTIN_VUPKLSH:
12700 case P8V_BUILTIN_VUPKLSW:
12701 {
12702 arg0 = gimple_call_arg (stmt, 0);
12703 lhs = gimple_call_lhs (stmt);
12704 if (BYTES_BIG_ENDIAN)
12705 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
12706 else
12707 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
12708 gimple_set_location (g, gimple_location (stmt));
12709 gsi_replace (gsi, g, true);
12710 return true;
12711 }
12712 /* There is no gimple type corresponding with pixel, so just return. */
12713 case ALTIVEC_BUILTIN_VUPKHPX:
12714 case ALTIVEC_BUILTIN_VUPKLPX:
12715 return false;
12716
12717 /* vec_perm. */
12718 case ALTIVEC_BUILTIN_VPERM_16QI:
12719 case ALTIVEC_BUILTIN_VPERM_8HI:
12720 case ALTIVEC_BUILTIN_VPERM_4SI:
12721 case ALTIVEC_BUILTIN_VPERM_2DI:
12722 case ALTIVEC_BUILTIN_VPERM_4SF:
12723 case ALTIVEC_BUILTIN_VPERM_2DF:
12724 {
12725 arg0 = gimple_call_arg (stmt, 0);
12726 arg1 = gimple_call_arg (stmt, 1);
12727 tree permute = gimple_call_arg (stmt, 2);
12728 lhs = gimple_call_lhs (stmt);
12729 location_t loc = gimple_location (stmt);
12730 gimple_seq stmts = NULL;
12731 // convert arg0 and arg1 to match the type of the permute
12732 // for the VEC_PERM_EXPR operation.
12733 tree permute_type = (TREE_TYPE (permute));
b6d53324
RS		 12734 tree arg0_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
12735 permute_type, arg0);
12736 tree arg1_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
12737 permute_type, arg1);
1acf0246
BS		 12738 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
12739 permute_type, arg0_ptype, arg1_ptype,
12740 permute);
12741 // Convert the result back to the desired lhs type upon completion.
b6d53324
RS		 12742 tree temp = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
12743 TREE_TYPE (lhs), lhs_ptype);
1acf0246
BS		 12744 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12745 g = gimple_build_assign (lhs, temp);
12746 gimple_set_location (g, loc);
12747 gsi_replace (gsi, g, true);
12748 return true;
12749 }
12750
12751 default:
12752 if (TARGET_DEBUG_BUILTIN)
12753 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
12754 fn_code, fn_name1, fn_name2);
12755 break;
12756 }
12757
12758 return false;
12759}
12760
12761/* Expand an expression EXP that calls a built-in function,
12762 with result going to TARGET if that's convenient
12763 (and in mode MODE if that's convenient).
12764 SUBTARGET may be used as the target for computing one of EXP's operands.
12765 IGNORE is nonzero if the value is to be ignored. */
12766
12767rtx
12768rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
12769 machine_mode mode ATTRIBUTE_UNUSED,
12770 int ignore ATTRIBUTE_UNUSED)
12771{
12772 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
12773 enum rs6000_builtins fcode
4d732405 12774 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
1acf0246
BS		 12775 size_t uns_fcode = (size_t)fcode;
12776 const struct builtin_description *d;
12777 size_t i;
12778 rtx ret;
12779 bool success;
12780 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
12781 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
12782 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
12783
12784 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
12785 floating point type, depending on whether long double is the IBM extended
12786 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
12787 we only define one variant of the built-in function, and switch the code
12788 when defining it, rather than defining two built-ins and using the
12789 overload table in rs6000-c.c to switch between the two. If we don't have
12790 the proper assembler, don't do this switch because CODE_FOR_*kf* and
12791 CODE_FOR_*tf* will be CODE_FOR_nothing. */
12792 if (FLOAT128_IEEE_P (TFmode))
12793 switch (icode)
12794 {
12795 default:
12796 break;
12797
12798 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
12799 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
12800 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
12801 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
12802 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
12803 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
12804 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
12805 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
12806 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
12807 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
12808 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
12809 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
12810 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
9bdb34ce
MM		 12811
12812 case CODE_FOR_xscmpexpqp_eq_kf:
12813 icode = CODE_FOR_xscmpexpqp_eq_tf;
12814 break;
12815
12816 case CODE_FOR_xscmpexpqp_lt_kf:
12817 icode = CODE_FOR_xscmpexpqp_lt_tf;
12818 break;
12819
12820 case CODE_FOR_xscmpexpqp_gt_kf:
12821 icode = CODE_FOR_xscmpexpqp_gt_tf;
12822 break;
12823
12824 case CODE_FOR_xscmpexpqp_unordered_kf:
12825 icode = CODE_FOR_xscmpexpqp_unordered_tf;
12826 break;
1acf0246
BS		 12827 }
12828
12829 if (TARGET_DEBUG_BUILTIN)
12830 {
12831 const char *name1 = rs6000_builtin_info[uns_fcode].name;
12832 const char *name2 = (icode != CODE_FOR_nothing)
12833 ? get_insn_name ((int) icode)
12834 : "nothing";
12835 const char *name3;
12836
12837 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
12838 {
12839 default: name3 = "unknown"; break;
12840 case RS6000_BTC_SPECIAL: name3 = "special"; break;
12841 case RS6000_BTC_UNARY: name3 = "unary"; break;
12842 case RS6000_BTC_BINARY: name3 = "binary"; break;
12843 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
840ac85c 12844 case RS6000_BTC_QUATERNARY:name3 = "quaternary";break;
1acf0246
BS		 12845 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
12846 case RS6000_BTC_ABS: name3 = "abs"; break;
12847 case RS6000_BTC_DST: name3 = "dst"; break;
12848 }
12849
12850
12851 fprintf (stderr,
12852 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
12853 (name1) ? name1 : "---", fcode,
12854 (name2) ? name2 : "---", (int) icode,
12855 name3,
12856 func_valid_p ? "" : ", not valid");
12857 }
12858
12859 if (!func_valid_p)
12860 {
12861 rs6000_invalid_builtin (fcode);
12862
12863 /* Given it is invalid, just generate a normal call. */
12864 return expand_call (exp, target, ignore);
12865 }
12866
12867 switch (fcode)
12868 {
12869 case RS6000_BUILTIN_RECIP:
12870 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
12871
12872 case RS6000_BUILTIN_RECIPF:
12873 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
12874
12875 case RS6000_BUILTIN_RSQRTF:
12876 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
12877
12878 case RS6000_BUILTIN_RSQRT:
12879 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
12880
12881 case POWER7_BUILTIN_BPERMD:
12882 return rs6000_expand_binop_builtin (((TARGET_64BIT)
12883 ? CODE_FOR_bpermd_di
12884 : CODE_FOR_bpermd_si), exp, target);
12885
12886 case RS6000_BUILTIN_GET_TB:
12887 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
12888 target);
12889
12890 case RS6000_BUILTIN_MFTB:
12891 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
12892 ? CODE_FOR_rs6000_mftb_di
12893 : CODE_FOR_rs6000_mftb_si),
12894 target);
12895
12896 case RS6000_BUILTIN_MFFS:
12897 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
12898
12899 case RS6000_BUILTIN_MTFSB0:
12900 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
12901
12902 case RS6000_BUILTIN_MTFSB1:
12903 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
12904
12905 case RS6000_BUILTIN_SET_FPSCR_RN:
12906 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
12907 exp);
12908
12909 case RS6000_BUILTIN_SET_FPSCR_DRN:
12910 return
12911 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
12912 exp);
12913
12914 case RS6000_BUILTIN_MFFSL:
12915 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
12916
12917 case RS6000_BUILTIN_MTFSF:
12918 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
12919
12920 case RS6000_BUILTIN_CPU_INIT:
12921 case RS6000_BUILTIN_CPU_IS:
12922 case RS6000_BUILTIN_CPU_SUPPORTS:
12923 return cpu_expand_builtin (fcode, exp, target);
12924
12925 case MISC_BUILTIN_SPEC_BARRIER:
12926 {
12927 emit_insn (gen_speculation_barrier ());
12928 return NULL_RTX;
12929 }
12930
12931 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
1acf0246
BS		 12932 {
12933 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
12934 : (int) CODE_FOR_altivec_lvsl_direct);
12935 machine_mode tmode = insn_data[icode2].operand[0].mode;
12936 machine_mode mode = insn_data[icode2].operand[1].mode;
12937 tree arg;
12938 rtx op, addr, pat;
12939
12940 gcc_assert (TARGET_ALTIVEC);
12941
12942 arg = CALL_EXPR_ARG (exp, 0);
12943 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
12944 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
12945 addr = memory_address (mode, op);
cd023352
BS		 12946 /* We need to negate the address. */
12947 op = gen_reg_rtx (GET_MODE (addr));
12948 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
1acf0246
BS		 12949 op = gen_rtx_MEM (mode, op);
12950
12951 if (target == 0
12952 || GET_MODE (target) != tmode
12953 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
12954 target = gen_reg_rtx (tmode);
12955
12956 pat = GEN_FCN (icode2) (target, op);
12957 if (!pat)
12958 return 0;
12959 emit_insn (pat);
12960
12961 return target;
12962 }
12963
12964 case ALTIVEC_BUILTIN_VCFUX:
12965 case ALTIVEC_BUILTIN_VCFSX:
12966 case ALTIVEC_BUILTIN_VCTUXS:
12967 case ALTIVEC_BUILTIN_VCTSXS:
12968 /* FIXME: There's got to be a nicer way to handle this case than
12969 constructing a new CALL_EXPR. */
12970 if (call_expr_nargs (exp) == 1)
12971 {
12972 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
12973 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
12974 }
12975 break;
12976
12977 /* For the pack and unpack int128 routines, fix up the builtin so it
12978 uses the correct IBM128 type. */
12979 case MISC_BUILTIN_PACK_IF:
12980 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
12981 {
12982 icode = CODE_FOR_packtf;
12983 fcode = MISC_BUILTIN_PACK_TF;
12984 uns_fcode = (size_t)fcode;
12985 }
12986 break;
12987
12988 case MISC_BUILTIN_UNPACK_IF:
12989 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
12990 {
12991 icode = CODE_FOR_unpacktf;
12992 fcode = MISC_BUILTIN_UNPACK_TF;
12993 uns_fcode = (size_t)fcode;
12994 }
12995 break;
12996
12997 default:
12998 break;
12999 }
13000
8ee2640b
PB		 13001 if (TARGET_MMA)
13002 {
13003 ret = mma_expand_builtin (exp, target, &success);
13004
13005 if (success)
13006 return ret;
13007 }
1acf0246
BS		 13008 if (TARGET_ALTIVEC)
13009 {
13010 ret = altivec_expand_builtin (exp, target, &success);
13011
13012 if (success)
13013 return ret;
13014 }
13015 if (TARGET_HTM)
13016 {
13017 ret = htm_expand_builtin (exp, target, &success);
13018
13019 if (success)
13020 return ret;
13021 }
13022
8ee2640b 13023 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_OPND_MASK;
1acf0246
BS		 13024 /* RS6000_BTC_SPECIAL represents no-operand operators. */
13025 gcc_assert (attr == RS6000_BTC_UNARY
13026 || attr == RS6000_BTC_BINARY
13027 || attr == RS6000_BTC_TERNARY
840ac85c 13028 || attr == RS6000_BTC_QUATERNARY
1acf0246
BS		 13029 || attr == RS6000_BTC_SPECIAL);
13030
13031 /* Handle simple unary operations. */
13032 d = bdesc_1arg;
13033 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
13034 if (d->code == fcode)
13035 return rs6000_expand_unop_builtin (icode, exp, target);
13036
13037 /* Handle simple binary operations. */
13038 d = bdesc_2arg;
13039 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13040 if (d->code == fcode)
13041 return rs6000_expand_binop_builtin (icode, exp, target);
13042
13043 /* Handle simple ternary operations. */
13044 d = bdesc_3arg;
13045 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
13046 if (d->code == fcode)
13047 return rs6000_expand_ternop_builtin (icode, exp, target);
13048
840ac85c
KN		 13049 /* Handle simple quaternary operations. */
13050 d = bdesc_4arg;
13051 for (i = 0; i < ARRAY_SIZE (bdesc_4arg); i++, d++)
13052 if (d->code == fcode)
13053 return rs6000_expand_quaternop_builtin (icode, exp, target);
13054
1acf0246
BS		 13055 /* Handle simple no-argument operations. */
13056 d = bdesc_0arg;
13057 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
13058 if (d->code == fcode)
13059 return rs6000_expand_zeroop_builtin (icode, target);
13060
13061 gcc_unreachable ();
13062}
13063
13064/* Create a builtin vector type with a name. Taking care not to give
13065 the canonical type a name. */
13066
13067static tree
13068rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
13069{
13070 tree result = build_vector_type (elt_type, num_elts);
13071
13072 /* Copy so we don't give the canonical type a name. */
13073 result = build_variant_type_copy (result);
13074
13075 add_builtin_type (name, result);
13076
13077 return result;
13078}
13079
13080void
13081rs6000_init_builtins (void)
13082{
13083 tree tdecl;
13084 tree ftype;
13085 machine_mode mode;
13086
13087 if (TARGET_DEBUG_BUILTIN)
13088 fprintf (stderr, "rs6000_init_builtins%s%s\n",
13089 (TARGET_ALTIVEC) ? ", altivec" : "",
13090 (TARGET_VSX) ? ", vsx" : "");
13091
13092 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
13093 : "__vector long long",
d8f3474f 13094 long_long_integer_type_node, 2);
1acf0246
BS		 13095 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
13096 V4SI_type_node = rs6000_vector_type ("__vector signed int",
13097 intSI_type_node, 4);
13098 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
13099 V8HI_type_node = rs6000_vector_type ("__vector signed short",
13100 intHI_type_node, 8);
13101 V16QI_type_node = rs6000_vector_type ("__vector signed char",
13102 intQI_type_node, 16);
13103
13104 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
13105 unsigned_intQI_type_node, 16);
13106 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
13107 unsigned_intHI_type_node, 8);
13108 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
13109 unsigned_intSI_type_node, 4);
13110 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
13111 ? "__vector unsigned long"
13112 : "__vector unsigned long long",
d8f3474f 13113 long_long_unsigned_type_node, 2);
1acf0246
BS		 13114
13115 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
13116
13117 const_str_type_node
13118 = build_pointer_type (build_qualified_type (char_type_node,
13119 TYPE_QUAL_CONST));
13120
13121 /* We use V1TI mode as a special container to hold __int128_t items that
13122 must live in VSX registers. */
13123 if (intTI_type_node)
13124 {
13125 V1TI_type_node = rs6000_vector_type ("__vector __int128",
13126 intTI_type_node, 1);
13127 unsigned_V1TI_type_node
13128 = rs6000_vector_type ("__vector unsigned __int128",
13129 unsigned_intTI_type_node, 1);
13130 }
13131
13132 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
13133 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
13134 'vector unsigned short'. */
13135
13136 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
13137 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
13138 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
13139 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
13140 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
13141
13142 long_integer_type_internal_node = long_integer_type_node;
13143 long_unsigned_type_internal_node = long_unsigned_type_node;
13144 long_long_integer_type_internal_node = long_long_integer_type_node;
13145 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
13146 intQI_type_internal_node = intQI_type_node;
13147 uintQI_type_internal_node = unsigned_intQI_type_node;
13148 intHI_type_internal_node = intHI_type_node;
13149 uintHI_type_internal_node = unsigned_intHI_type_node;
13150 intSI_type_internal_node = intSI_type_node;
13151 uintSI_type_internal_node = unsigned_intSI_type_node;
13152 intDI_type_internal_node = intDI_type_node;
13153 uintDI_type_internal_node = unsigned_intDI_type_node;
13154 intTI_type_internal_node = intTI_type_node;
13155 uintTI_type_internal_node = unsigned_intTI_type_node;
13156 float_type_internal_node = float_type_node;
13157 double_type_internal_node = double_type_node;
13158 long_double_type_internal_node = long_double_type_node;
13159 dfloat64_type_internal_node = dfloat64_type_node;
13160 dfloat128_type_internal_node = dfloat128_type_node;
13161 void_type_internal_node = void_type_node;
13162
13163 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
13164 IFmode is the IBM extended 128-bit format that is a pair of doubles.
13165 TFmode will be either IEEE 128-bit floating point or the IBM double-double
13166 format that uses a pair of doubles, depending on the switches and
13167 defaults.
13168
13169 If we don't support for either 128-bit IBM double double or IEEE 128-bit
13170 floating point, we need make sure the type is non-zero or else self-test
13171 fails during bootstrap.
13172
13173 Always create __ibm128 as a separate type, even if the current long double
13174 format is IBM extended double.
13175
13176 For IEEE 128-bit floating point, always create the type __ieee128. If the
13177 user used -mfloat128, rs6000-c.c will create a define from __float128 to
13178 __ieee128. */
13179 if (TARGET_FLOAT128_TYPE)
13180 {
13181 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
13182 ibm128_float_type_node = long_double_type_node;
13183 else
13184 {
13185 ibm128_float_type_node = make_node (REAL_TYPE);
13186 TYPE_PRECISION (ibm128_float_type_node) = 128;
13187 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
13188 layout_type (ibm128_float_type_node);
13189 }
13190
13191 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
13192 "__ibm128");
13193
13194 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
13195 ieee128_float_type_node = long_double_type_node;
13196 else
13197 ieee128_float_type_node = float128_type_node;
13198
13199 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
13200 "__ieee128");
13201 }
13202
13203 else
13204 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
13205
8ee2640b 13206 /* Vector pair and vector quad support. */
fd263be4 13207 if (TARGET_EXTRA_BUILTINS)
f002c046 13208 {
f8f8909a
AS		 13209 vector_pair_type_node = make_node (OPAQUE_TYPE);
13210 SET_TYPE_MODE (vector_pair_type_node, OOmode);
13211 TYPE_SIZE (vector_pair_type_node) = bitsize_int (GET_MODE_BITSIZE (OOmode));
13212 TYPE_PRECISION (vector_pair_type_node) = GET_MODE_BITSIZE (OOmode);
13213 TYPE_SIZE_UNIT (vector_pair_type_node) = size_int (GET_MODE_SIZE (OOmode));
a37b5bcf 13214 SET_TYPE_ALIGN (vector_pair_type_node, 256);
f8f8909a 13215 TYPE_USER_ALIGN (vector_pair_type_node) = 0;
f002c046
PB		 13216 lang_hooks.types.register_builtin_type (vector_pair_type_node,
13217 "__vector_pair");
13218
f8f8909a
AS		 13219 vector_quad_type_node = make_node (OPAQUE_TYPE);
13220 SET_TYPE_MODE (vector_quad_type_node, XOmode);
13221 TYPE_SIZE (vector_quad_type_node) = bitsize_int (GET_MODE_BITSIZE (XOmode));
13222 TYPE_PRECISION (vector_quad_type_node) = GET_MODE_BITSIZE (XOmode);
13223 TYPE_SIZE_UNIT (vector_quad_type_node) = size_int (GET_MODE_SIZE (XOmode));
a37b5bcf 13224 SET_TYPE_ALIGN (vector_quad_type_node, 512);
f8f8909a 13225 TYPE_USER_ALIGN (vector_quad_type_node) = 0;
f002c046
PB		 13226 lang_hooks.types.register_builtin_type (vector_quad_type_node,
13227 "__vector_quad");
13228 }
13229
1acf0246
BS		 13230 /* Initialize the modes for builtin_function_type, mapping a machine mode to
13231 tree type node. */
13232 builtin_mode_to_type[QImode][0] = integer_type_node;
840ac85c 13233 builtin_mode_to_type[QImode][1] = unsigned_intSI_type_node;
1acf0246 13234 builtin_mode_to_type[HImode][0] = integer_type_node;
840ac85c 13235 builtin_mode_to_type[HImode][1] = unsigned_intSI_type_node;
1acf0246
BS		 13236 builtin_mode_to_type[SImode][0] = intSI_type_node;
13237 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
13238 builtin_mode_to_type[DImode][0] = intDI_type_node;
13239 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
13240 builtin_mode_to_type[TImode][0] = intTI_type_node;
13241 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
13242 builtin_mode_to_type[SFmode][0] = float_type_node;
13243 builtin_mode_to_type[DFmode][0] = double_type_node;
13244 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
13245 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
13246 builtin_mode_to_type[TFmode][0] = long_double_type_node;
13247 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
13248 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
13249 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
13250 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
13251 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
13252 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
13253 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
13254 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
13255 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
13256 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
13257 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
13258 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
13259 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
13260 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
f8f8909a
AS		 13261 builtin_mode_to_type[OOmode][1] = vector_pair_type_node;
13262 builtin_mode_to_type[XOmode][1] = vector_quad_type_node;
1acf0246
BS		 13263
13264 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
13265 TYPE_NAME (bool_char_type_node) = tdecl;
13266
13267 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
13268 TYPE_NAME (bool_short_type_node) = tdecl;
13269
13270 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
13271 TYPE_NAME (bool_int_type_node) = tdecl;
13272
13273 tdecl = add_builtin_type ("__pixel", pixel_type_node);
13274 TYPE_NAME (pixel_type_node) = tdecl;
13275
13276 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
13277 bool_char_type_node, 16);
13278 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
13279 bool_short_type_node, 8);
13280 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
13281 bool_int_type_node, 4);
13282 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
13283 ? "__vector __bool long"
13284 : "__vector __bool long long",
13285 bool_long_long_type_node, 2);
13286 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
13287 pixel_type_node, 8);
13288
fd263be4 13289 /* Create Altivec, VSX and MMA builtins on machines with at least the
1acf0246
BS		 13290 general purpose extensions (970 and newer) to allow the use of
13291 the target attribute. */
13292 if (TARGET_EXTRA_BUILTINS)
fd263be4
PB		 13293 {
13294 altivec_init_builtins ();
13295 mma_init_builtins ();
13296 }
1acf0246
BS		 13297 if (TARGET_HTM)
13298 htm_init_builtins ();
13299
13300 if (TARGET_EXTRA_BUILTINS)
13301 rs6000_common_init_builtins ();
13302
13303 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
13304 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
13305 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
13306
13307 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
13308 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
13309 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
13310
13311 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
13312 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
13313 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
13314
13315 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
13316 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
13317 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
13318
13319 mode = (TARGET_64BIT) ? DImode : SImode;
13320 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
13321 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
13322 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
13323
13324 ftype = build_function_type_list (unsigned_intDI_type_node,
13325 NULL_TREE);
13326 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
13327
13328 if (TARGET_64BIT)
13329 ftype = build_function_type_list (unsigned_intDI_type_node,
13330 NULL_TREE);
13331 else
13332 ftype = build_function_type_list (unsigned_intSI_type_node,
13333 NULL_TREE);
13334 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
13335
13336 ftype = build_function_type_list (double_type_node, NULL_TREE);
13337 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
13338
13339 ftype = build_function_type_list (double_type_node, NULL_TREE);
13340 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
13341
13342 ftype = build_function_type_list (void_type_node,
13343 intSI_type_node,
13344 NULL_TREE);
13345 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
13346
13347 ftype = build_function_type_list (void_type_node,
13348 intSI_type_node,
13349 NULL_TREE);
13350 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
13351
13352 ftype = build_function_type_list (void_type_node,
13353 intDI_type_node,
13354 NULL_TREE);
13355 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
13356
13357 ftype = build_function_type_list (void_type_node,
13358 intDI_type_node,
13359 NULL_TREE);
13360 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
13361
13362 ftype = build_function_type_list (void_type_node,
13363 intSI_type_node, double_type_node,
13364 NULL_TREE);
13365 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
13366
13367 ftype = build_function_type_list (void_type_node, NULL_TREE);
13368 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
13369 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
13370 MISC_BUILTIN_SPEC_BARRIER);
13371
13372 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
13373 NULL_TREE);
13374 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
13375 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
13376
5e681acd
DE		 13377 if (TARGET_XCOFF)
13378 {
13379 /* AIX libm provides clog as __clog. */
13380 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
13381 set_user_assembler_name (tdecl, "__clog");
13382
13383 /* When long double is 64 bit, some long double builtins of libc
13384 functions (like __builtin_frexpl) must call the double version
13385 (frexp) not the long double version (frexpl) that expects a 128 bit
13386 argument. */
13387 if (! TARGET_LONG_DOUBLE_128)
13388 {
13389 if ((tdecl = builtin_decl_explicit (BUILT_IN_FMODL)) != NULL_TREE)
13390 set_user_assembler_name (tdecl, "fmod");
13391 if ((tdecl = builtin_decl_explicit (BUILT_IN_FREXPL)) != NULL_TREE)
13392 set_user_assembler_name (tdecl, "frexp");
13393 if ((tdecl = builtin_decl_explicit (BUILT_IN_LDEXPL)) != NULL_TREE)
13394 set_user_assembler_name (tdecl, "ldexp");
13395 if ((tdecl = builtin_decl_explicit (BUILT_IN_MODFL)) != NULL_TREE)
13396 set_user_assembler_name (tdecl, "modf");
13397 }
13398 }
1acf0246
BS		 13399
13400#ifdef SUBTARGET_INIT_BUILTINS
13401 SUBTARGET_INIT_BUILTINS;
13402#endif
13403}
13404
13405/* Returns the rs6000 builtin decl for CODE. */
13406
13407tree
13408rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
13409{
13410 HOST_WIDE_INT fnmask;
13411
13412 if (code >= RS6000_BUILTIN_COUNT)
13413 return error_mark_node;
13414
13415 fnmask = rs6000_builtin_info[code].mask;
13416 if ((fnmask & rs6000_builtin_mask) != fnmask)
13417 {
13418 rs6000_invalid_builtin ((enum rs6000_builtins)code);
13419 return error_mark_node;
13420 }
13421
13422 return rs6000_builtin_decls[code];
13423}
13424
13425static void
13426altivec_init_builtins (void)
13427{
13428 const struct builtin_description *d;
13429 size_t i;
13430 tree ftype;
13431 tree decl;
1acf0246
BS		 13432
13433 tree pvoid_type_node = build_pointer_type (void_type_node);
13434
13435 tree pcvoid_type_node
13436 = build_pointer_type (build_qualified_type (void_type_node,
13437 TYPE_QUAL_CONST));
13438
13439 tree int_ftype_opaque
13440 = build_function_type_list (integer_type_node,
13441 opaque_V4SI_type_node, NULL_TREE);
13442 tree opaque_ftype_opaque
13443 = build_function_type_list (integer_type_node, NULL_TREE);
13444 tree opaque_ftype_opaque_int
13445 = build_function_type_list (opaque_V4SI_type_node,
13446 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
13447 tree opaque_ftype_opaque_opaque_int
13448 = build_function_type_list (opaque_V4SI_type_node,
13449 opaque_V4SI_type_node, opaque_V4SI_type_node,
13450 integer_type_node, NULL_TREE);
13451 tree opaque_ftype_opaque_opaque_opaque
13452 = build_function_type_list (opaque_V4SI_type_node,
13453 opaque_V4SI_type_node, opaque_V4SI_type_node,
13454 opaque_V4SI_type_node, NULL_TREE);
13455 tree opaque_ftype_opaque_opaque
13456 = build_function_type_list (opaque_V4SI_type_node,
13457 opaque_V4SI_type_node, opaque_V4SI_type_node,
13458 NULL_TREE);
13459 tree int_ftype_int_opaque_opaque
13460 = build_function_type_list (integer_type_node,
13461 integer_type_node, opaque_V4SI_type_node,
13462 opaque_V4SI_type_node, NULL_TREE);
13463 tree int_ftype_int_v4si_v4si
13464 = build_function_type_list (integer_type_node,
13465 integer_type_node, V4SI_type_node,
13466 V4SI_type_node, NULL_TREE);
13467 tree int_ftype_int_v2di_v2di
13468 = build_function_type_list (integer_type_node,
13469 integer_type_node, V2DI_type_node,
13470 V2DI_type_node, NULL_TREE);
13471 tree void_ftype_v4si
13472 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
13473 tree v8hi_ftype_void
13474 = build_function_type_list (V8HI_type_node, NULL_TREE);
13475 tree void_ftype_void
13476 = build_function_type_list (void_type_node, NULL_TREE);
13477 tree void_ftype_int
13478 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
13479
13480 tree opaque_ftype_long_pcvoid
13481 = build_function_type_list (opaque_V4SI_type_node,
13482 long_integer_type_node, pcvoid_type_node,
13483 NULL_TREE);
c6b7ba5d
BS		 13484 tree v16qi_ftype_pcvoid
13485 = build_function_type_list (V16QI_type_node,
13486 pcvoid_type_node,
13487 NULL_TREE);
1acf0246
BS		 13488 tree v16qi_ftype_long_pcvoid
13489 = build_function_type_list (V16QI_type_node,
13490 long_integer_type_node, pcvoid_type_node,
13491 NULL_TREE);
13492 tree v8hi_ftype_long_pcvoid
13493 = build_function_type_list (V8HI_type_node,
13494 long_integer_type_node, pcvoid_type_node,
13495 NULL_TREE);
13496 tree v4si_ftype_long_pcvoid
13497 = build_function_type_list (V4SI_type_node,
13498 long_integer_type_node, pcvoid_type_node,
13499 NULL_TREE);
13500 tree v4sf_ftype_long_pcvoid
13501 = build_function_type_list (V4SF_type_node,
13502 long_integer_type_node, pcvoid_type_node,
13503 NULL_TREE);
13504 tree v2df_ftype_long_pcvoid
13505 = build_function_type_list (V2DF_type_node,
13506 long_integer_type_node, pcvoid_type_node,
13507 NULL_TREE);
13508 tree v2di_ftype_long_pcvoid
13509 = build_function_type_list (V2DI_type_node,
13510 long_integer_type_node, pcvoid_type_node,
13511 NULL_TREE);
13512 tree v1ti_ftype_long_pcvoid
13513 = build_function_type_list (V1TI_type_node,
13514 long_integer_type_node, pcvoid_type_node,
13515 NULL_TREE);
13516
13517 tree void_ftype_opaque_long_pvoid
13518 = build_function_type_list (void_type_node,
13519 opaque_V4SI_type_node, long_integer_type_node,
13520 pvoid_type_node, NULL_TREE);
13521 tree void_ftype_v4si_long_pvoid
13522 = build_function_type_list (void_type_node,
13523 V4SI_type_node, long_integer_type_node,
13524 pvoid_type_node, NULL_TREE);
13525 tree void_ftype_v16qi_long_pvoid
13526 = build_function_type_list (void_type_node,
13527 V16QI_type_node, long_integer_type_node,
13528 pvoid_type_node, NULL_TREE);
13529
13530 tree void_ftype_v16qi_pvoid_long
13531 = build_function_type_list (void_type_node,
13532 V16QI_type_node, pvoid_type_node,
13533 long_integer_type_node, NULL_TREE);
13534
13535 tree void_ftype_v8hi_long_pvoid
13536 = build_function_type_list (void_type_node,
13537 V8HI_type_node, long_integer_type_node,
13538 pvoid_type_node, NULL_TREE);
13539 tree void_ftype_v4sf_long_pvoid
13540 = build_function_type_list (void_type_node,
13541 V4SF_type_node, long_integer_type_node,
13542 pvoid_type_node, NULL_TREE);
13543 tree void_ftype_v2df_long_pvoid
13544 = build_function_type_list (void_type_node,
13545 V2DF_type_node, long_integer_type_node,
13546 pvoid_type_node, NULL_TREE);
13547 tree void_ftype_v1ti_long_pvoid
13548 = build_function_type_list (void_type_node,
13549 V1TI_type_node, long_integer_type_node,
13550 pvoid_type_node, NULL_TREE);
13551 tree void_ftype_v2di_long_pvoid
13552 = build_function_type_list (void_type_node,
13553 V2DI_type_node, long_integer_type_node,
13554 pvoid_type_node, NULL_TREE);
13555 tree int_ftype_int_v8hi_v8hi
13556 = build_function_type_list (integer_type_node,
13557 integer_type_node, V8HI_type_node,
13558 V8HI_type_node, NULL_TREE);
13559 tree int_ftype_int_v16qi_v16qi
13560 = build_function_type_list (integer_type_node,
13561 integer_type_node, V16QI_type_node,
13562 V16QI_type_node, NULL_TREE);
13563 tree int_ftype_int_v4sf_v4sf
13564 = build_function_type_list (integer_type_node,
13565 integer_type_node, V4SF_type_node,
13566 V4SF_type_node, NULL_TREE);
13567 tree int_ftype_int_v2df_v2df
13568 = build_function_type_list (integer_type_node,
13569 integer_type_node, V2DF_type_node,
13570 V2DF_type_node, NULL_TREE);
13571 tree v2di_ftype_v2di
13572 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
13573 tree v4si_ftype_v4si
13574 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
13575 tree v8hi_ftype_v8hi
13576 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
13577 tree v16qi_ftype_v16qi
13578 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
13579 tree v4sf_ftype_v4sf
13580 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
13581 tree v2df_ftype_v2df
13582 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
13583 tree void_ftype_pcvoid_int_int
13584 = build_function_type_list (void_type_node,
13585 pcvoid_type_node, integer_type_node,
13586 integer_type_node, NULL_TREE);
13587
13588 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
13589 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
13590 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
13591 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
13592 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
13593 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
13594 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
13595 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
13596 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
b69c0061
WS		 13597 def_builtin ("__builtin_altivec_se_lxvrbx", v16qi_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRBX);
13598 def_builtin ("__builtin_altivec_se_lxvrhx", v8hi_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRHX);
13599 def_builtin ("__builtin_altivec_se_lxvrwx", v4si_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRWX);
13600 def_builtin ("__builtin_altivec_se_lxvrdx", v2di_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRDX);
13601 def_builtin ("__builtin_altivec_ze_lxvrbx", v16qi_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRBX);
13602 def_builtin ("__builtin_altivec_ze_lxvrhx", v8hi_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRHX);
13603 def_builtin ("__builtin_altivec_ze_lxvrwx", v4si_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRWX);
13604 def_builtin ("__builtin_altivec_ze_lxvrdx", v2di_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRDX);
13605 def_builtin ("__builtin_altivec_tr_stxvrbx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRBX);
13606 def_builtin ("__builtin_altivec_tr_stxvrhx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRHX);
13607 def_builtin ("__builtin_altivec_tr_stxvrwx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRWX);
13608 def_builtin ("__builtin_altivec_tr_stxvrdx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRDX);
1acf0246
BS		 13609 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
13610 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
13611 ALTIVEC_BUILTIN_LVXL_V2DF);
13612 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
13613 ALTIVEC_BUILTIN_LVXL_V2DI);
13614 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
13615 ALTIVEC_BUILTIN_LVXL_V4SF);
13616 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
13617 ALTIVEC_BUILTIN_LVXL_V4SI);
13618 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
13619 ALTIVEC_BUILTIN_LVXL_V8HI);
13620 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
13621 ALTIVEC_BUILTIN_LVXL_V16QI);
13622 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
13623 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
13624 ALTIVEC_BUILTIN_LVX_V1TI);
13625 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
13626 ALTIVEC_BUILTIN_LVX_V2DF);
13627 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
13628 ALTIVEC_BUILTIN_LVX_V2DI);
13629 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
13630 ALTIVEC_BUILTIN_LVX_V4SF);
13631 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
13632 ALTIVEC_BUILTIN_LVX_V4SI);
13633 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
13634 ALTIVEC_BUILTIN_LVX_V8HI);
13635 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
13636 ALTIVEC_BUILTIN_LVX_V16QI);
13637 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
13638 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
13639 ALTIVEC_BUILTIN_STVX_V2DF);
13640 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
13641 ALTIVEC_BUILTIN_STVX_V2DI);
13642 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
13643 ALTIVEC_BUILTIN_STVX_V4SF);
13644 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
13645 ALTIVEC_BUILTIN_STVX_V4SI);
13646 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
13647 ALTIVEC_BUILTIN_STVX_V8HI);
13648 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
13649 ALTIVEC_BUILTIN_STVX_V16QI);
13650 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
13651 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
13652 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
13653 ALTIVEC_BUILTIN_STVXL_V2DF);
13654 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
13655 ALTIVEC_BUILTIN_STVXL_V2DI);
13656 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
13657 ALTIVEC_BUILTIN_STVXL_V4SF);
13658 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
13659 ALTIVEC_BUILTIN_STVXL_V4SI);
13660 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
13661 ALTIVEC_BUILTIN_STVXL_V8HI);
13662 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
13663 ALTIVEC_BUILTIN_STVXL_V16QI);
13664 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
13665 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
13666 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
13667 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
13668 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
13669 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
13670 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
13671 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
13672 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
13673 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
b69c0061
WS		 13674 def_builtin ("__builtin_vec_se_lxvrx", v1ti_ftype_long_pcvoid, P10_BUILTIN_VEC_SE_LXVRX);
13675 def_builtin ("__builtin_vec_ze_lxvrx", v1ti_ftype_long_pcvoid, P10_BUILTIN_VEC_ZE_LXVRX);
13676 def_builtin ("__builtin_vec_tr_stxvrx", void_ftype_opaque_long_pvoid, P10_BUILTIN_VEC_TR_STXVRX);
1acf0246
BS		 13677 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
13678 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
13679 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
13680 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
13681 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
13682 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
13683
13684 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
13685 VSX_BUILTIN_LXVD2X_V2DF);
13686 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
13687 VSX_BUILTIN_LXVD2X_V2DI);
13688 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
13689 VSX_BUILTIN_LXVW4X_V4SF);
13690 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
13691 VSX_BUILTIN_LXVW4X_V4SI);
13692 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
13693 VSX_BUILTIN_LXVW4X_V8HI);
13694 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
13695 VSX_BUILTIN_LXVW4X_V16QI);
13696 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
13697 VSX_BUILTIN_STXVD2X_V2DF);
13698 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
13699 VSX_BUILTIN_STXVD2X_V2DI);
13700 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
13701 VSX_BUILTIN_STXVW4X_V4SF);
13702 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
13703 VSX_BUILTIN_STXVW4X_V4SI);
13704 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
13705 VSX_BUILTIN_STXVW4X_V8HI);
13706 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
13707 VSX_BUILTIN_STXVW4X_V16QI);
13708
13709 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
13710 VSX_BUILTIN_LD_ELEMREV_V2DF);
13711 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
13712 VSX_BUILTIN_LD_ELEMREV_V2DI);
13713 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
13714 VSX_BUILTIN_LD_ELEMREV_V4SF);
13715 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
13716 VSX_BUILTIN_LD_ELEMREV_V4SI);
13717 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
13718 VSX_BUILTIN_LD_ELEMREV_V8HI);
13719 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
13720 VSX_BUILTIN_LD_ELEMREV_V16QI);
13721 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
13722 VSX_BUILTIN_ST_ELEMREV_V2DF);
13723 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
13724 VSX_BUILTIN_ST_ELEMREV_V1TI);
13725 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
13726 VSX_BUILTIN_ST_ELEMREV_V2DI);
13727 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
13728 VSX_BUILTIN_ST_ELEMREV_V4SF);
13729 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
13730 VSX_BUILTIN_ST_ELEMREV_V4SI);
13731 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
13732 VSX_BUILTIN_ST_ELEMREV_V8HI);
13733 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
13734 VSX_BUILTIN_ST_ELEMREV_V16QI);
13735
13736 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
13737 VSX_BUILTIN_VEC_LD);
13738 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
13739 VSX_BUILTIN_VEC_ST);
13740 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
13741 VSX_BUILTIN_VEC_XL);
13742 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
13743 VSX_BUILTIN_VEC_XL_BE);
13744 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
13745 VSX_BUILTIN_VEC_XST);
13746 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
13747 VSX_BUILTIN_VEC_XST_BE);
13748
13749 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
13750 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
13751 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
13752
13753 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
13754 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
13755 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
13756 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
13757 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
13758 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
13759 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
13760 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
13761 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
13762 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
13763 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
13764 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
13765
13766 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
13767 ALTIVEC_BUILTIN_VEC_ADDE);
13768 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
13769 ALTIVEC_BUILTIN_VEC_ADDEC);
13770 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
13771 ALTIVEC_BUILTIN_VEC_CMPNE);
13772 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
13773 ALTIVEC_BUILTIN_VEC_MUL);
13774 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
13775 ALTIVEC_BUILTIN_VEC_SUBE);
13776 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
13777 ALTIVEC_BUILTIN_VEC_SUBEC);
13778
13779 /* Cell builtins. */
13780 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
13781 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
13782 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
13783 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
13784
13785 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
13786 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
13787 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
13788 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
13789
13790 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
13791 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
13792 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
13793 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
13794
13795 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
13796 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
13797 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
13798 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
13799
13800 if (TARGET_P9_VECTOR)
13801 {
13802 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
13803 P9V_BUILTIN_STXVL);
3f3f28de 13804 def_builtin ("__builtin_altivec_xst_len_r", void_ftype_v16qi_pvoid_long,
1acf0246
BS		 13805 P9V_BUILTIN_XST_LEN_R);
13806 }
13807
13808 /* Add the DST variants. */
13809 d = bdesc_dst;
13810 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
13811 {
1acf0246
BS		 13812 /* It is expected that these dst built-in functions may have
13813 d->icode equal to CODE_FOR_nothing. */
1acf0246
BS		 13814 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
13815 }
13816
13817 /* Initialize the predicates. */
13818 d = bdesc_altivec_preds;
13819 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
13820 {
13821 machine_mode mode1;
13822 tree type;
1acf0246
BS		 13823
13824 if (rs6000_overloaded_builtin_p (d->code))
13825 mode1 = VOIDmode;
13826 else
13827 {
13828 /* Cannot define builtin if the instruction is disabled. */
13829 gcc_assert (d->icode != CODE_FOR_nothing);
13830 mode1 = insn_data[d->icode].operand[1].mode;
13831 }
13832
13833 switch (mode1)
13834 {
13835 case E_VOIDmode:
13836 type = int_ftype_int_opaque_opaque;
13837 break;
13838 case E_V2DImode:
13839 type = int_ftype_int_v2di_v2di;
13840 break;
13841 case E_V4SImode:
13842 type = int_ftype_int_v4si_v4si;
13843 break;
13844 case E_V8HImode:
13845 type = int_ftype_int_v8hi_v8hi;
13846 break;
13847 case E_V16QImode:
13848 type = int_ftype_int_v16qi_v16qi;
13849 break;
13850 case E_V4SFmode:
13851 type = int_ftype_int_v4sf_v4sf;
13852 break;
13853 case E_V2DFmode:
13854 type = int_ftype_int_v2df_v2df;
13855 break;
13856 default:
13857 gcc_unreachable ();
13858 }
13859
13860 def_builtin (d->name, type, d->code);
13861 }
13862
13863 /* Initialize the abs* operators. */
13864 d = bdesc_abs;
13865 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
13866 {
13867 machine_mode mode0;
13868 tree type;
1acf0246
BS		 13869
13870 /* Cannot define builtin if the instruction is disabled. */
13871 gcc_assert (d->icode != CODE_FOR_nothing);
13872 mode0 = insn_data[d->icode].operand[0].mode;
13873
13874 switch (mode0)
13875 {
13876 case E_V2DImode:
13877 type = v2di_ftype_v2di;
13878 break;
13879 case E_V4SImode:
13880 type = v4si_ftype_v4si;
13881 break;
13882 case E_V8HImode:
13883 type = v8hi_ftype_v8hi;
13884 break;
13885 case E_V16QImode:
13886 type = v16qi_ftype_v16qi;
13887 break;
13888 case E_V4SFmode:
13889 type = v4sf_ftype_v4sf;
13890 break;
13891 case E_V2DFmode:
13892 type = v2df_ftype_v2df;
13893 break;
13894 default:
13895 gcc_unreachable ();
13896 }
13897
13898 def_builtin (d->name, type, d->code);
13899 }
13900
13901 /* Initialize target builtin that implements
13902 targetm.vectorize.builtin_mask_for_load. */
13903
13904 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
c6b7ba5d 13905 v16qi_ftype_pcvoid,
1acf0246
BS		 13906 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
13907 BUILT_IN_MD, NULL, NULL_TREE);
13908 TREE_READONLY (decl) = 1;
13909 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
13910 altivec_builtin_mask_for_load = decl;
13911
13912 /* Access to the vec_init patterns. */
13913 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
13914 integer_type_node, integer_type_node,
13915 integer_type_node, NULL_TREE);
13916 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
13917
13918 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
13919 short_integer_type_node,
13920 short_integer_type_node,
13921 short_integer_type_node,
13922 short_integer_type_node,
13923 short_integer_type_node,
13924 short_integer_type_node,
13925 short_integer_type_node, NULL_TREE);
13926 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
13927
13928 ftype = build_function_type_list (V16QI_type_node, char_type_node,
13929 char_type_node, char_type_node,
13930 char_type_node, char_type_node,
13931 char_type_node, char_type_node,
13932 char_type_node, char_type_node,
13933 char_type_node, char_type_node,
13934 char_type_node, char_type_node,
13935 char_type_node, char_type_node,
13936 char_type_node, NULL_TREE);
13937 def_builtin ("__builtin_vec_init_v16qi", ftype,
13938 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
13939
13940 ftype = build_function_type_list (V4SF_type_node, float_type_node,
13941 float_type_node, float_type_node,
13942 float_type_node, NULL_TREE);
13943 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
13944
13945 /* VSX builtins. */
13946 ftype = build_function_type_list (V2DF_type_node, double_type_node,
13947 double_type_node, NULL_TREE);
13948 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
13949
13950 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
13951 intDI_type_node, NULL_TREE);
13952 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
13953
13954 /* Access to the vec_set patterns. */
13955 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
13956 intSI_type_node,
13957 integer_type_node, NULL_TREE);
13958 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
13959
13960 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
13961 intHI_type_node,
13962 integer_type_node, NULL_TREE);
13963 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
13964
13965 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
13966 intQI_type_node,
13967 integer_type_node, NULL_TREE);
13968 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
13969
13970 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
13971 float_type_node,
13972 integer_type_node, NULL_TREE);
13973 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
13974
13975 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
13976 double_type_node,
13977 integer_type_node, NULL_TREE);
13978 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
13979
13980 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
13981 intDI_type_node,
13982 integer_type_node, NULL_TREE);
13983 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
13984
13985 /* Access to the vec_extract patterns. */
13986 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
13987 integer_type_node, NULL_TREE);
13988 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
13989
13990 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
13991 integer_type_node, NULL_TREE);
13992 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
13993
13994 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
13995 integer_type_node, NULL_TREE);
13996 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
13997
13998 ftype = build_function_type_list (float_type_node, V4SF_type_node,
13999 integer_type_node, NULL_TREE);
14000 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
14001
14002 ftype = build_function_type_list (double_type_node, V2DF_type_node,
14003 integer_type_node, NULL_TREE);
14004 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
14005
14006 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
14007 integer_type_node, NULL_TREE);
14008 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
14009
14010
14011 if (V1TI_type_node)
14012 {
14013 tree v1ti_ftype_long_pcvoid
14014 = build_function_type_list (V1TI_type_node,
14015 long_integer_type_node, pcvoid_type_node,
14016 NULL_TREE);
14017 tree void_ftype_v1ti_long_pvoid
14018 = build_function_type_list (void_type_node,
14019 V1TI_type_node, long_integer_type_node,
14020 pvoid_type_node, NULL_TREE);
14021 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
14022 VSX_BUILTIN_LD_ELEMREV_V1TI);
14023 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
14024 VSX_BUILTIN_LXVD2X_V1TI);
14025 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
14026 VSX_BUILTIN_STXVD2X_V1TI);
14027 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
14028 NULL_TREE, NULL_TREE);
14029 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
14030 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
14031 intTI_type_node,
14032 integer_type_node, NULL_TREE);
14033 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
14034 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
14035 integer_type_node, NULL_TREE);
14036 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
14037 }
14038
14039}
14040
8ee2640b
PB		 14041static void
14042mma_init_builtins (void)
14043{
14044 const struct builtin_description *d = bdesc_mma;
14045
14046 for (unsigned i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++)
14047 {
14048 tree op[MAX_MMA_OPERANDS], type;
8ee2640b
PB		 14049 unsigned icode = (unsigned) d->icode;
14050 unsigned attr = rs6000_builtin_info[d->code].attr;
14051 int attr_args = (attr & RS6000_BTC_OPND_MASK);
14052 bool gimple_func = (attr & RS6000_BTC_GIMPLE);
14053 unsigned nopnds = 0;
14054
8ee2640b
PB		 14055 if (d->name == 0)
14056 {
14057 if (TARGET_DEBUG_BUILTIN)
14058 fprintf (stderr, "mma_builtin, bdesc_mma[%ld] no name\n",
14059 (long unsigned) i);
14060 continue;
14061 }
14062
14063 if (gimple_func)
14064 {
14065 gcc_assert (icode == CODE_FOR_nothing);
14066 op[nopnds++] = void_type_node;
14067 /* Some MMA built-ins that are expanded into gimple are converted
14068 into internal MMA built-ins that are expanded into rtl.
14069 The internal built-in follows immediately after this built-in. */
14070 icode = d[1].icode;
14071 }
14072 else
14073 {
f8f8909a
AS		 14074 if (!(d->code == MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL
14075 || d->code == MMA_BUILTIN_DISASSEMBLE_PAIR_INTERNAL)
14076 && (attr & RS6000_BTC_QUAD) == 0)
8ee2640b
PB		 14077 attr_args--;
14078
14079 /* Ensure we have the correct number and type of operands. */
14080 gcc_assert (attr_args == insn_data[icode].n_operands - 1);
14081 }
14082
f8f8909a
AS		 14083 /* This is a disassemble pair/acc function. */
14084 if (d->code == MMA_BUILTIN_DISASSEMBLE_ACC
14085 || d->code == MMA_BUILTIN_DISASSEMBLE_PAIR)
8ee2640b 14086 {
8ee2640b 14087 op[nopnds++] = build_pointer_type (void_type_node);
f8f8909a 14088 if (d->code == MMA_BUILTIN_DISASSEMBLE_ACC)
8ee2640b
PB		 14089 op[nopnds++] = build_pointer_type (vector_quad_type_node);
14090 else
14091 op[nopnds++] = build_pointer_type (vector_pair_type_node);
14092 }
14093 else
14094 {
14095 /* This is a normal MMA built-in function. */
f8f8909a
AS		 14096 unsigned j = 0;
14097 if (attr & RS6000_BTC_QUAD
14098 && d->code != MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL
14099 && d->code != MMA_BUILTIN_DISASSEMBLE_PAIR_INTERNAL)
14100 j = 1;
8005a3e4 14101 for (; j < (unsigned) insn_data[icode].n_operands; j++)
8ee2640b
PB		 14102 {
14103 machine_mode mode = insn_data[icode].operand[j].mode;
f8f8909a 14104 if (gimple_func && mode == XOmode)
8ee2640b 14105 op[nopnds++] = build_pointer_type (vector_quad_type_node);
f8f8909a 14106 else if (gimple_func && mode == OOmode
8ee2640b
PB		 14107 && d->code == MMA_BUILTIN_ASSEMBLE_PAIR)
14108 op[nopnds++] = build_pointer_type (vector_pair_type_node);
14109 else
14110 /* MMA uses unsigned types. */
14111 op[nopnds++] = builtin_mode_to_type[mode][1];
14112 }
14113 }
14114
14115 switch (nopnds)
14116 {
14117 case 1:
14118 type = build_function_type_list (op[0], NULL_TREE);
14119 break;
14120 case 2:
14121 type = build_function_type_list (op[0], op[1], NULL_TREE);
14122 break;
14123 case 3:
14124 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
14125 break;
14126 case 4:
14127 type = build_function_type_list (op[0], op[1], op[2], op[3],
14128 NULL_TREE);
14129 break;
14130 case 5:
14131 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4],
14132 NULL_TREE);
14133 break;
14134 case 6:
14135 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4],
14136 op[5], NULL_TREE);
14137 break;
14138 case 7:
14139 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4],
14140 op[5], op[6], NULL_TREE);
14141 break;
14142 default:
14143 gcc_unreachable ();
14144 }
14145
14146 def_builtin (d->name, type, d->code);
14147 }
14148}
14149
1acf0246
BS		 14150static void
14151htm_init_builtins (void)
14152{
14153 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
14154 const struct builtin_description *d;
14155 size_t i;
14156
14157 d = bdesc_htm;
14158 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14159 {
14160 tree op[MAX_HTM_OPERANDS], type;
14161 HOST_WIDE_INT mask = d->mask;
14162 unsigned attr = rs6000_builtin_info[d->code].attr;
14163 bool void_func = (attr & RS6000_BTC_VOID);
8ee2640b 14164 int attr_args = (attr & RS6000_BTC_OPND_MASK);
1acf0246
BS		 14165 int nopnds = 0;
14166 tree gpr_type_node;
14167 tree rettype;
14168 tree argtype;
14169
14170 /* It is expected that these htm built-in functions may have
14171 d->icode equal to CODE_FOR_nothing. */
14172
14173 if (TARGET_32BIT && TARGET_POWERPC64)
14174 gpr_type_node = long_long_unsigned_type_node;
14175 else
14176 gpr_type_node = long_unsigned_type_node;
14177
14178 if (attr & RS6000_BTC_SPR)
14179 {
14180 rettype = gpr_type_node;
14181 argtype = gpr_type_node;
14182 }
14183 else if (d->code == HTM_BUILTIN_TABORTDC
14184 || d->code == HTM_BUILTIN_TABORTDCI)
14185 {
14186 rettype = unsigned_type_node;
14187 argtype = gpr_type_node;
14188 }
14189 else
14190 {
14191 rettype = unsigned_type_node;
14192 argtype = unsigned_type_node;
14193 }
14194
14195 if ((mask & builtin_mask) != mask)
14196 {
14197 if (TARGET_DEBUG_BUILTIN)
14198 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
14199 continue;
14200 }
14201
14202 if (d->name == 0)
14203 {
14204 if (TARGET_DEBUG_BUILTIN)
14205 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
14206 (long unsigned) i);
14207 continue;
14208 }
14209
14210 op[nopnds++] = (void_func) ? void_type_node : rettype;
14211
14212 if (attr_args == RS6000_BTC_UNARY)
14213 op[nopnds++] = argtype;
14214 else if (attr_args == RS6000_BTC_BINARY)
14215 {
14216 op[nopnds++] = argtype;
14217 op[nopnds++] = argtype;
14218 }
14219 else if (attr_args == RS6000_BTC_TERNARY)
14220 {
14221 op[nopnds++] = argtype;
14222 op[nopnds++] = argtype;
14223 op[nopnds++] = argtype;
14224 }
14225
14226 switch (nopnds)
14227 {
14228 case 1:
14229 type = build_function_type_list (op[0], NULL_TREE);
14230 break;
14231 case 2:
14232 type = build_function_type_list (op[0], op[1], NULL_TREE);
14233 break;
14234 case 3:
14235 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
14236 break;
14237 case 4:
14238 type = build_function_type_list (op[0], op[1], op[2], op[3],
14239 NULL_TREE);
14240 break;
14241 default:
14242 gcc_unreachable ();
14243 }
14244
14245 def_builtin (d->name, type, d->code);
14246 }
14247}
14248
840ac85c
KN		 14249/* Map types for builtin functions with an explicit return type and
14250 exactly 4 arguments. Functions with fewer than 3 arguments use
14251 builtin_function_type. The number of quaternary built-in
14252 functions is very small. Handle each case specially. */
14253static tree
14254builtin_quaternary_function_type (machine_mode mode_ret,
14255 machine_mode mode_arg0,
14256 machine_mode mode_arg1,
14257 machine_mode mode_arg2,
14258 machine_mode mode_arg3,
14259 enum rs6000_builtins builtin)
14260{
14261 tree function_type = NULL;
14262
14263 static tree v2udi_type = builtin_mode_to_type[V2DImode][1];
5998f1bb 14264 static tree v16uqi_type = builtin_mode_to_type[V16QImode][1];
840ac85c
KN		 14265 static tree uchar_type = builtin_mode_to_type[QImode][1];
14266
14267 static tree xxeval_type =
14268 build_function_type_list (v2udi_type, v2udi_type, v2udi_type,
14269 v2udi_type, uchar_type, NULL_TREE);
14270
5998f1bb
CL		 14271 static tree xxpermx_type =
14272 build_function_type_list (v2udi_type, v2udi_type, v2udi_type,
14273 v16uqi_type, uchar_type, NULL_TREE);
14274
840ac85c
KN		 14275 switch (builtin) {
14276
07d456bb 14277 case P10V_BUILTIN_XXEVAL:
840ac85c
KN		 14278 gcc_assert ((mode_ret == V2DImode)
14279 && (mode_arg0 == V2DImode)
14280 && (mode_arg1 == V2DImode)
14281 && (mode_arg2 == V2DImode)
14282 && (mode_arg3 == QImode));
14283 function_type = xxeval_type;
14284 break;
14285
07d456bb 14286 case P10V_BUILTIN_VXXPERMX:
5998f1bb
CL		 14287 gcc_assert ((mode_ret == V2DImode)
14288 && (mode_arg0 == V2DImode)
14289 && (mode_arg1 == V2DImode)
14290 && (mode_arg2 == V16QImode)
14291 && (mode_arg3 == QImode));
14292 function_type = xxpermx_type;
14293 break;
14294
840ac85c
KN		 14295 default:
14296 /* A case for each quaternary built-in must be provided above. */
14297 gcc_unreachable ();
14298 }
14299
14300 return function_type;
14301}
14302
1acf0246
BS		 14303/* Map types for builtin functions with an explicit return type and up to 3
14304 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
14305 of the argument. */
14306static tree
14307builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
14308 machine_mode mode_arg1, machine_mode mode_arg2,
14309 enum rs6000_builtins builtin, const char *name)
14310{
14311 struct builtin_hash_struct h;
14312 struct builtin_hash_struct *h2;
14313 int num_args = 3;
14314 int i;
14315 tree ret_type = NULL_TREE;
14316 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
14317
14318 /* Create builtin_hash_table. */
14319 if (builtin_hash_table == NULL)
14320 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
14321
14322 h.type = NULL_TREE;
14323 h.mode[0] = mode_ret;
14324 h.mode[1] = mode_arg0;
14325 h.mode[2] = mode_arg1;
14326 h.mode[3] = mode_arg2;
14327 h.uns_p[0] = 0;
14328 h.uns_p[1] = 0;
14329 h.uns_p[2] = 0;
14330 h.uns_p[3] = 0;
14331
14332 /* If the builtin is a type that produces unsigned results or takes unsigned
14333 arguments, and it is returned as a decl for the vectorizer (such as
14334 widening multiplies, permute), make sure the arguments and return value
14335 are type correct. */
14336 switch (builtin)
14337 {
14338 /* unsigned 1 argument functions. */
14339 case CRYPTO_BUILTIN_VSBOX:
14340 case CRYPTO_BUILTIN_VSBOX_BE:
14341 case P8V_BUILTIN_VGBBD:
14342 case MISC_BUILTIN_CDTBCD:
14343 case MISC_BUILTIN_CBCDTD:
07d456bb
CL		 14344 case P10V_BUILTIN_XVCVSPBF16:
14345 case P10V_BUILTIN_XVCVBF16SPN:
14346 case P10V_BUILTIN_MTVSRBM:
14347 case P10V_BUILTIN_MTVSRHM:
14348 case P10V_BUILTIN_MTVSRWM:
14349 case P10V_BUILTIN_MTVSRDM:
14350 case P10V_BUILTIN_MTVSRQM:
14351 case P10V_BUILTIN_VCNTMBB:
14352 case P10V_BUILTIN_VCNTMBH:
14353 case P10V_BUILTIN_VCNTMBW:
14354 case P10V_BUILTIN_VCNTMBD:
14355 case P10V_BUILTIN_VEXPANDMB:
14356 case P10V_BUILTIN_VEXPANDMH:
14357 case P10V_BUILTIN_VEXPANDMW:
14358 case P10V_BUILTIN_VEXPANDMD:
14359 case P10V_BUILTIN_VEXPANDMQ:
1acf0246
BS		 14360 h.uns_p[0] = 1;
14361 h.uns_p[1] = 1;
14362 break;
14363
14364 /* unsigned 2 argument functions. */
14365 case ALTIVEC_BUILTIN_VMULEUB:
14366 case ALTIVEC_BUILTIN_VMULEUH:
14367 case P8V_BUILTIN_VMULEUW:
14368 case ALTIVEC_BUILTIN_VMULOUB:
14369 case ALTIVEC_BUILTIN_VMULOUH:
14370 case P8V_BUILTIN_VMULOUW:
14371 case CRYPTO_BUILTIN_VCIPHER:
14372 case CRYPTO_BUILTIN_VCIPHER_BE:
14373 case CRYPTO_BUILTIN_VCIPHERLAST:
14374 case CRYPTO_BUILTIN_VCIPHERLAST_BE:
14375 case CRYPTO_BUILTIN_VNCIPHER:
14376 case CRYPTO_BUILTIN_VNCIPHER_BE:
14377 case CRYPTO_BUILTIN_VNCIPHERLAST:
14378 case CRYPTO_BUILTIN_VNCIPHERLAST_BE:
14379 case CRYPTO_BUILTIN_VPMSUMB:
14380 case CRYPTO_BUILTIN_VPMSUMH:
14381 case CRYPTO_BUILTIN_VPMSUMW:
14382 case CRYPTO_BUILTIN_VPMSUMD:
14383 case CRYPTO_BUILTIN_VPMSUM:
14384 case MISC_BUILTIN_ADDG6S:
14385 case MISC_BUILTIN_DIVWEU:
14386 case MISC_BUILTIN_DIVDEU:
14387 case VSX_BUILTIN_UDIV_V2DI:
14388 case ALTIVEC_BUILTIN_VMAXUB:
14389 case ALTIVEC_BUILTIN_VMINUB:
14390 case ALTIVEC_BUILTIN_VMAXUH:
14391 case ALTIVEC_BUILTIN_VMINUH:
14392 case ALTIVEC_BUILTIN_VMAXUW:
14393 case ALTIVEC_BUILTIN_VMINUW:
14394 case P8V_BUILTIN_VMAXUD:
14395 case P8V_BUILTIN_VMINUD:
4559be23
PB		 14396 case ALTIVEC_BUILTIN_VAND_V16QI_UNS:
14397 case ALTIVEC_BUILTIN_VAND_V8HI_UNS:
14398 case ALTIVEC_BUILTIN_VAND_V4SI_UNS:
14399 case ALTIVEC_BUILTIN_VAND_V2DI_UNS:
14400 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS:
14401 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS:
14402 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS:
14403 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS:
14404 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS:
14405 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS:
14406 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS:
14407 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS:
14408 case ALTIVEC_BUILTIN_VOR_V16QI_UNS:
14409 case ALTIVEC_BUILTIN_VOR_V8HI_UNS:
14410 case ALTIVEC_BUILTIN_VOR_V4SI_UNS:
14411 case ALTIVEC_BUILTIN_VOR_V2DI_UNS:
14412 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS:
14413 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS:
14414 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS:
14415 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS:
14416 case P8V_BUILTIN_EQV_V16QI_UNS:
14417 case P8V_BUILTIN_EQV_V8HI_UNS:
14418 case P8V_BUILTIN_EQV_V4SI_UNS:
14419 case P8V_BUILTIN_EQV_V2DI_UNS:
14420 case P8V_BUILTIN_EQV_V1TI_UNS:
14421 case P8V_BUILTIN_NAND_V16QI_UNS:
14422 case P8V_BUILTIN_NAND_V8HI_UNS:
14423 case P8V_BUILTIN_NAND_V4SI_UNS:
14424 case P8V_BUILTIN_NAND_V2DI_UNS:
14425 case P8V_BUILTIN_NAND_V1TI_UNS:
14426 case P8V_BUILTIN_ORC_V16QI_UNS:
14427 case P8V_BUILTIN_ORC_V8HI_UNS:
14428 case P8V_BUILTIN_ORC_V4SI_UNS:
14429 case P8V_BUILTIN_ORC_V2DI_UNS:
14430 case P8V_BUILTIN_ORC_V1TI_UNS:
07d456bb
CL		 14431 case P10V_BUILTIN_VCFUGED:
14432 case P10V_BUILTIN_VCLZDM:
14433 case P10V_BUILTIN_VCTZDM:
14434 case P10V_BUILTIN_VGNB:
14435 case P10V_BUILTIN_VPDEPD:
14436 case P10V_BUILTIN_VPEXTD:
14437 case P10V_BUILTIN_XXGENPCVM_V16QI:
14438 case P10V_BUILTIN_XXGENPCVM_V8HI:
14439 case P10V_BUILTIN_XXGENPCVM_V4SI:
14440 case P10V_BUILTIN_XXGENPCVM_V2DI:
1acf0246
BS		 14441 h.uns_p[0] = 1;
14442 h.uns_p[1] = 1;
14443 h.uns_p[2] = 1;
14444 break;
14445
14446 /* unsigned 3 argument functions. */
14447 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
14448 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
14449 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
14450 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
14451 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
14452 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
14453 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
14454 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
14455 case VSX_BUILTIN_VPERM_16QI_UNS:
14456 case VSX_BUILTIN_VPERM_8HI_UNS:
14457 case VSX_BUILTIN_VPERM_4SI_UNS:
14458 case VSX_BUILTIN_VPERM_2DI_UNS:
14459 case VSX_BUILTIN_XXSEL_16QI_UNS:
14460 case VSX_BUILTIN_XXSEL_8HI_UNS:
14461 case VSX_BUILTIN_XXSEL_4SI_UNS:
14462 case VSX_BUILTIN_XXSEL_2DI_UNS:
14463 case CRYPTO_BUILTIN_VPERMXOR:
14464 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
14465 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
14466 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
14467 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
14468 case CRYPTO_BUILTIN_VSHASIGMAW:
14469 case CRYPTO_BUILTIN_VSHASIGMAD:
14470 case CRYPTO_BUILTIN_VSHASIGMA:
07d456bb
CL		 14471 case P10V_BUILTIN_VEXTRACTBL:
14472 case P10V_BUILTIN_VEXTRACTHL:
14473 case P10V_BUILTIN_VEXTRACTWL:
14474 case P10V_BUILTIN_VEXTRACTDL:
14475 case P10V_BUILTIN_VEXTRACTBR:
14476 case P10V_BUILTIN_VEXTRACTHR:
14477 case P10V_BUILTIN_VEXTRACTWR:
14478 case P10V_BUILTIN_VEXTRACTDR:
14479 case P10V_BUILTIN_VINSERTGPRBL:
14480 case P10V_BUILTIN_VINSERTGPRHL:
14481 case P10V_BUILTIN_VINSERTGPRWL:
14482 case P10V_BUILTIN_VINSERTGPRDL:
14483 case P10V_BUILTIN_VINSERTVPRBL:
14484 case P10V_BUILTIN_VINSERTVPRHL:
14485 case P10V_BUILTIN_VINSERTVPRWL:
14486 case P10V_BUILTIN_VREPLACE_ELT_UV4SI:
14487 case P10V_BUILTIN_VREPLACE_ELT_UV2DI:
14488 case P10V_BUILTIN_VREPLACE_UN_UV4SI:
14489 case P10V_BUILTIN_VREPLACE_UN_UV2DI:
14490 case P10V_BUILTIN_VXXBLEND_V16QI:
14491 case P10V_BUILTIN_VXXBLEND_V8HI:
14492 case P10V_BUILTIN_VXXBLEND_V4SI:
14493 case P10V_BUILTIN_VXXBLEND_V2DI:
1acf0246
BS		 14494 h.uns_p[0] = 1;
14495 h.uns_p[1] = 1;
14496 h.uns_p[2] = 1;
14497 h.uns_p[3] = 1;
14498 break;
14499
14500 /* signed permute functions with unsigned char mask. */
14501 case ALTIVEC_BUILTIN_VPERM_16QI:
14502 case ALTIVEC_BUILTIN_VPERM_8HI:
14503 case ALTIVEC_BUILTIN_VPERM_4SI:
14504 case ALTIVEC_BUILTIN_VPERM_4SF:
14505 case ALTIVEC_BUILTIN_VPERM_2DI:
14506 case ALTIVEC_BUILTIN_VPERM_2DF:
14507 case VSX_BUILTIN_VPERM_16QI:
14508 case VSX_BUILTIN_VPERM_8HI:
14509 case VSX_BUILTIN_VPERM_4SI:
14510 case VSX_BUILTIN_VPERM_4SF:
14511 case VSX_BUILTIN_VPERM_2DI:
14512 case VSX_BUILTIN_VPERM_2DF:
14513 h.uns_p[3] = 1;
14514 break;
14515
14516 /* unsigned args, signed return. */
14517 case VSX_BUILTIN_XVCVUXDSP:
14518 case VSX_BUILTIN_XVCVUXDDP_UNS:
14519 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
14520 h.uns_p[1] = 1;
14521 break;
14522
14523 /* signed args, unsigned return. */
14524 case VSX_BUILTIN_XVCVDPUXDS_UNS:
14525 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
14526 case MISC_BUILTIN_UNPACK_TD:
14527 case MISC_BUILTIN_UNPACK_V1TI:
14528 h.uns_p[0] = 1;
14529 break;
14530
14531 /* unsigned arguments, bool return (compares). */
14532 case ALTIVEC_BUILTIN_VCMPEQUB:
14533 case ALTIVEC_BUILTIN_VCMPEQUH:
14534 case ALTIVEC_BUILTIN_VCMPEQUW:
14535 case P8V_BUILTIN_VCMPEQUD:
14536 case VSX_BUILTIN_CMPGE_U16QI:
14537 case VSX_BUILTIN_CMPGE_U8HI:
14538 case VSX_BUILTIN_CMPGE_U4SI:
14539 case VSX_BUILTIN_CMPGE_U2DI:
14540 case ALTIVEC_BUILTIN_VCMPGTUB:
14541 case ALTIVEC_BUILTIN_VCMPGTUH:
14542 case ALTIVEC_BUILTIN_VCMPGTUW:
14543 case P8V_BUILTIN_VCMPGTUD:
14544 h.uns_p[1] = 1;
14545 h.uns_p[2] = 1;
14546 break;
14547
14548 /* unsigned arguments for 128-bit pack instructions. */
14549 case MISC_BUILTIN_PACK_TD:
14550 case MISC_BUILTIN_PACK_V1TI:
14551 h.uns_p[1] = 1;
14552 h.uns_p[2] = 1;
14553 break;
14554
14555 /* unsigned second arguments (vector shift right). */
14556 case ALTIVEC_BUILTIN_VSRB:
14557 case ALTIVEC_BUILTIN_VSRH:
14558 case ALTIVEC_BUILTIN_VSRW:
14559 case P8V_BUILTIN_VSRD:
7f3b1997 14560 /* Vector splat immediate insert */
07d456bb
CL		 14561 case P10V_BUILTIN_VXXSPLTI32DX_V4SI:
14562 case P10V_BUILTIN_VXXSPLTI32DX_V4SF:
1acf0246
BS		 14563 h.uns_p[2] = 1;
14564 break;
14565
14566 default:
14567 break;
14568 }
14569
14570 /* Figure out how many args are present. */
14571 while (num_args > 0 && h.mode[num_args] == VOIDmode)
14572 num_args--;
14573
14574 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
14575 if (!ret_type && h.uns_p[0])
14576 ret_type = builtin_mode_to_type[h.mode[0]][0];
14577
a92cc0da
PB		 14578 /* If the required decimal float type has been disabled,
14579 then return NULL_TREE. */
14580 if (!ret_type && DECIMAL_FLOAT_MODE_P (h.mode[0]))
14581 return NULL_TREE;
14582
1acf0246
BS		 14583 if (!ret_type)
14584 fatal_error (input_location,
14585 "internal error: builtin function %qs had an unexpected "
14586 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
14587
14588 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
14589 arg_type[i] = NULL_TREE;
14590
14591 for (i = 0; i < num_args; i++)
14592 {
14593 int m = (int) h.mode[i+1];
14594 int uns_p = h.uns_p[i+1];
14595
14596 arg_type[i] = builtin_mode_to_type[m][uns_p];
14597 if (!arg_type[i] && uns_p)
14598 arg_type[i] = builtin_mode_to_type[m][0];
14599
a92cc0da
PB		 14600 /* If the required decimal float type has been disabled,
14601 then return NULL_TREE. */
14602 if (!arg_type[i] && DECIMAL_FLOAT_MODE_P (m))
14603 return NULL_TREE;
14604
1acf0246
BS		 14605 if (!arg_type[i])
14606 fatal_error (input_location,
14607 "internal error: builtin function %qs, argument %d "
14608 "had unexpected argument type %qs", name, i,
14609 GET_MODE_NAME (m));
14610 }
14611
14612 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
14613 if (*found == NULL)
14614 {
14615 h2 = ggc_alloc<builtin_hash_struct> ();
14616 *h2 = h;
14617 *found = h2;
14618
14619 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
14620 arg_type[2], NULL_TREE);
14621 }
14622
14623 return (*found)->type;
14624}
14625
14626static void
14627rs6000_common_init_builtins (void)
14628{
14629 const struct builtin_description *d;
14630 size_t i;
14631
14632 tree opaque_ftype_opaque = NULL_TREE;
14633 tree opaque_ftype_opaque_opaque = NULL_TREE;
14634 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
c21d2b66 14635 tree opaque_ftype_opaque_opaque_opaque_opaque = NULL_TREE;
1acf0246
BS		 14636 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
14637
14638 /* Create Altivec and VSX builtins on machines with at least the
14639 general purpose extensions (970 and newer) to allow the use of
14640 the target attribute. */
14641
14642 if (TARGET_EXTRA_BUILTINS)
14643 builtin_mask |= RS6000_BTM_COMMON;
14644
840ac85c
KN		 14645 /* Add the quaternary operators. */
14646 d = bdesc_4arg;
14647 for (i = 0; i < ARRAY_SIZE (bdesc_4arg); i++, d++)
14648 {
14649 tree type;
14650 HOST_WIDE_INT mask = d->mask;
14651
14652 if ((mask & builtin_mask) != mask)
14653 {
14654 if (TARGET_DEBUG_BUILTIN)
14655 fprintf (stderr, "rs6000_builtin, skip quaternary %s\n", d->name);
14656 continue;
14657 }
14658
14659 if (rs6000_overloaded_builtin_p (d->code))
14660 {
c21d2b66 14661 type = opaque_ftype_opaque_opaque_opaque_opaque;
840ac85c 14662 if (!type)
c21d2b66 14663 type = opaque_ftype_opaque_opaque_opaque_opaque
840ac85c
KN		 14664 = build_function_type_list (opaque_V4SI_type_node,
14665 opaque_V4SI_type_node,
14666 opaque_V4SI_type_node,
14667 opaque_V4SI_type_node,
14668 opaque_V4SI_type_node,
14669 NULL_TREE);
14670 }
14671 else
14672 {
14673 enum insn_code icode = d->icode;
14674 if (d->name == 0)
14675 {
14676 if (TARGET_DEBUG_BUILTIN)
14677 fprintf (stderr, "rs6000_builtin, bdesc_4arg[%ld] no name\n",
14678 (long) i);
14679 continue;
14680 }
14681
14682 if (icode == CODE_FOR_nothing)
14683 {
14684 if (TARGET_DEBUG_BUILTIN)
14685 fprintf (stderr,
14686 "rs6000_builtin, skip quaternary %s (no code)\n",
14687 d->name);
14688 continue;
14689 }
14690
14691 type =
14692 builtin_quaternary_function_type (insn_data[icode].operand[0].mode,
14693 insn_data[icode].operand[1].mode,
14694 insn_data[icode].operand[2].mode,
14695 insn_data[icode].operand[3].mode,
14696 insn_data[icode].operand[4].mode,
14697 d->code);
14698 }
14699 def_builtin (d->name, type, d->code);
14700 }
14701
1acf0246
BS		 14702 /* Add the ternary operators. */
14703 d = bdesc_3arg;
14704 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
14705 {
14706 tree type;
14707 HOST_WIDE_INT mask = d->mask;
14708
14709 if ((mask & builtin_mask) != mask)
14710 {
14711 if (TARGET_DEBUG_BUILTIN)
14712 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
14713 continue;
14714 }
14715
14716 if (rs6000_overloaded_builtin_p (d->code))
14717 {
14718 if (! (type = opaque_ftype_opaque_opaque_opaque))
14719 type = opaque_ftype_opaque_opaque_opaque
14720 = build_function_type_list (opaque_V4SI_type_node,
14721 opaque_V4SI_type_node,
14722 opaque_V4SI_type_node,
14723 opaque_V4SI_type_node,
14724 NULL_TREE);
14725 }
14726 else
14727 {
14728 enum insn_code icode = d->icode;
14729 if (d->name == 0)
14730 {
14731 if (TARGET_DEBUG_BUILTIN)
14732 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
14733 (long unsigned)i);
14734
14735 continue;
14736 }
14737
f8f8909a 14738 if (icode == CODE_FOR_nothing)
1acf0246
BS		 14739 {
14740 if (TARGET_DEBUG_BUILTIN)
14741 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
14742 d->name);
14743
14744 continue;
14745 }
14746
14747 type = builtin_function_type (insn_data[icode].operand[0].mode,
14748 insn_data[icode].operand[1].mode,
14749 insn_data[icode].operand[2].mode,
14750 insn_data[icode].operand[3].mode,
14751 d->code, d->name);
14752 }
14753
14754 def_builtin (d->name, type, d->code);
14755 }
14756
14757 /* Add the binary operators. */
14758 d = bdesc_2arg;
14759 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
14760 {
14761 machine_mode mode0, mode1, mode2;
14762 tree type;
14763 HOST_WIDE_INT mask = d->mask;
14764
14765 if ((mask & builtin_mask) != mask)
14766 {
14767 if (TARGET_DEBUG_BUILTIN)
14768 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
14769 continue;
14770 }
14771
14772 if (rs6000_overloaded_builtin_p (d->code))
14773 {
25ffd3d3
PB		 14774 const struct altivec_builtin_types *desc;
14775
14776 /* Verify the builtin we are overloading has already been defined. */
14777 type = NULL_TREE;
14778 for (desc = altivec_overloaded_builtins;
14779 desc->code != RS6000_BUILTIN_NONE; desc++)
14780 if (desc->code == d->code
14781 && rs6000_builtin_decls[(int)desc->overloaded_code])
14782 {
14783 if (! (type = opaque_ftype_opaque_opaque))
14784 type = opaque_ftype_opaque_opaque
14785 = build_function_type_list (opaque_V4SI_type_node,
14786 opaque_V4SI_type_node,
14787 opaque_V4SI_type_node,
14788 NULL_TREE);
14789 break;
14790 }
1acf0246
BS		 14791 }
14792 else
14793 {
14794 enum insn_code icode = d->icode;
14795 if (d->name == 0)
14796 {
14797 if (TARGET_DEBUG_BUILTIN)
14798 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
14799 (long unsigned)i);
14800
14801 continue;
14802 }
14803
f8f8909a 14804 if (icode == CODE_FOR_nothing)
1acf0246
BS		 14805 {
14806 if (TARGET_DEBUG_BUILTIN)
14807 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
14808 d->name);
14809
14810 continue;
14811 }
14812
f8f8909a
AS		 14813 mode0 = insn_data[icode].operand[0].mode;
14814 mode1 = insn_data[icode].operand[1].mode;
14815 mode2 = insn_data[icode].operand[2].mode;
1acf0246
BS		 14816
14817 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
14818 d->code, d->name);
14819 }
14820
14821 def_builtin (d->name, type, d->code);
14822 }
14823
14824 /* Add the simple unary operators. */
14825 d = bdesc_1arg;
14826 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
14827 {
14828 machine_mode mode0, mode1;
14829 tree type;
14830 HOST_WIDE_INT mask = d->mask;
14831
14832 if ((mask & builtin_mask) != mask)
14833 {
14834 if (TARGET_DEBUG_BUILTIN)
14835 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
14836 continue;
14837 }
14838
14839 if (rs6000_overloaded_builtin_p (d->code))
14840 {
14841 if (! (type = opaque_ftype_opaque))
14842 type = opaque_ftype_opaque
14843 = build_function_type_list (opaque_V4SI_type_node,
14844 opaque_V4SI_type_node,
14845 NULL_TREE);
14846 }
14847 else
f8f8909a 14848 {
1acf0246
BS		 14849 enum insn_code icode = d->icode;
14850 if (d->name == 0)
14851 {
14852 if (TARGET_DEBUG_BUILTIN)
14853 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
14854 (long unsigned)i);
14855
14856 continue;
14857 }
14858
f8f8909a 14859 if (icode == CODE_FOR_nothing)
1acf0246
BS		 14860 {
14861 if (TARGET_DEBUG_BUILTIN)
14862 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
14863 d->name);
14864
14865 continue;
14866 }
14867
f8f8909a
AS		 14868 mode0 = insn_data[icode].operand[0].mode;
14869 mode1 = insn_data[icode].operand[1].mode;
1acf0246
BS		 14870
14871 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
14872 d->code, d->name);
14873 }
14874
14875 def_builtin (d->name, type, d->code);
14876 }
14877
14878 /* Add the simple no-argument operators. */
14879 d = bdesc_0arg;
14880 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
14881 {
14882 machine_mode mode0;
14883 tree type;
14884 HOST_WIDE_INT mask = d->mask;
14885
14886 if ((mask & builtin_mask) != mask)
14887 {
14888 if (TARGET_DEBUG_BUILTIN)
14889 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
14890 continue;
14891 }
14892 if (rs6000_overloaded_builtin_p (d->code))
14893 {
14894 if (!opaque_ftype_opaque)
14895 opaque_ftype_opaque
14896 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
14897 type = opaque_ftype_opaque;
14898 }
14899 else
14900 {
14901 enum insn_code icode = d->icode;
14902 if (d->name == 0)
14903 {
14904 if (TARGET_DEBUG_BUILTIN)
14905 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
14906 (long unsigned) i);
14907 continue;
14908 }
14909 if (icode == CODE_FOR_nothing)
14910 {
14911 if (TARGET_DEBUG_BUILTIN)
14912 fprintf (stderr,
14913 "rs6000_builtin, skip no-argument %s (no code)\n",
14914 d->name);
14915 continue;
14916 }
14917 mode0 = insn_data[icode].operand[0].mode;
14918 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
14919 d->code, d->name);
14920 }
14921 def_builtin (d->name, type, d->code);
14922 }
14923}
14924
14925/* Return the internal arg pointer used for function incoming
14926 arguments. When -fsplit-stack, the arg pointer is r12 so we need
14927 to copy it to a pseudo in order for it to be preserved over calls
14928 and suchlike. We'd really like to use a pseudo here for the
14929 internal arg pointer but data-flow analysis is not prepared to
14930 accept pseudos as live at the beginning of a function. */
14931
14932rtx
14933rs6000_internal_arg_pointer (void)
14934{
14935 if (flag_split_stack
14936 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
14937 == NULL))
14938
14939 {
14940 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
14941 {
14942 rtx pat;
14943
14944 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
14945 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
14946
14947 /* Put the pseudo initialization right after the note at the
14948 beginning of the function. */
14949 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
14950 gen_rtx_REG (Pmode, 12));
14951 push_topmost_sequence ();
14952 emit_insn_after (pat, get_insns ());
14953 pop_topmost_sequence ();
14954 }
14955 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
14956 FIRST_PARM_OFFSET (current_function_decl));
14957 return copy_to_reg (ret);
14958 }
14959 return virtual_incoming_args_rtx;
14960}
14961
14962\f
14963/* A C compound statement that outputs the assembler code for a thunk
14964 function, used to implement C++ virtual function calls with
14965 multiple inheritance. The thunk acts as a wrapper around a virtual
14966 function, adjusting the implicit object parameter before handing
14967 control off to the real function.
14968
14969 First, emit code to add the integer DELTA to the location that
14970 contains the incoming first argument. Assume that this argument
14971 contains a pointer, and is the one used to pass the `this' pointer
14972 in C++. This is the incoming argument *before* the function
14973 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14974 values of all other incoming arguments.
14975
14976 After the addition, emit code to jump to FUNCTION, which is a
14977 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14978 not touch the return address. Hence returning from FUNCTION will
14979 return to whoever called the current `thunk'.
14980
14981 The effect must be as if FUNCTION had been called directly with the
14982 adjusted first argument. This macro is responsible for emitting
14983 all of the code for a thunk function; output_function_prologue()
14984 and output_function_epilogue() are not invoked.
14985
14986 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14987 been extracted from it.) It might possibly be useful on some
14988 targets, but probably not.
14989
14990 If you do not define this macro, the target-independent code in the
14991 C++ frontend will generate a less efficient heavyweight thunk that
14992 calls FUNCTION instead of jumping to it. The generic approach does
14993 not support varargs. */
14994
14995void
14996rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14997 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14998 tree function)
14999{
15000 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
15001 rtx this_rtx, funexp;
15002 rtx_insn *insn;
15003
15004 reload_completed = 1;
15005 epilogue_completed = 1;
15006
15007 /* Mark the end of the (empty) prologue. */
15008 emit_note (NOTE_INSN_PROLOGUE_END);
15009
15010 /* Find the "this" pointer. If the function returns a structure,
15011 the structure return pointer is in r3. */
15012 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15013 this_rtx = gen_rtx_REG (Pmode, 4);
15014 else
15015 this_rtx = gen_rtx_REG (Pmode, 3);
15016
15017 /* Apply the constant offset, if required. */
15018 if (delta)
15019 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
15020
15021 /* Apply the offset from the vtable, if required. */
15022 if (vcall_offset)
15023 {
15024 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15025 rtx tmp = gen_rtx_REG (Pmode, 12);
15026
15027 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
15028 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15029 {
15030 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
15031 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15032 }
15033 else
15034 {
15035 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15036
15037 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15038 }
15039 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
15040 }
15041
15042 /* Generate a tail call to the target function. */
15043 if (!TREE_USED (function))
15044 {
15045 assemble_external (function);
15046 TREE_USED (function) = 1;
15047 }
15048 funexp = XEXP (DECL_RTL (function), 0);
15049 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15050
aef57966 15051 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, const0_rtx));
1acf0246
BS		 15052 SIBLING_CALL_P (insn) = 1;
15053 emit_barrier ();
15054
15055 /* Run just enough of rest_of_compilation to get the insns emitted.
15056 There's not really enough bulk here to make other passes such as
15057 instruction scheduling worth while. */
15058 insn = get_insns ();
15059 shorten_branches (insn);
15060 assemble_start_function (thunk_fndecl, fnname);
15061 final_start_function (insn, file, 1);
15062 final (insn, file, 1);
15063 final_end_function ();
15064 assemble_end_function (thunk_fndecl, fnname);
15065
15066 reload_completed = 0;
15067 epilogue_completed = 0;
15068}
15069
15070#include "gt-rs6000-call.h"
Mirror of https://gcc.gnu.org/git/gcc.git