[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000-cpus.def

/* IBM RS/6000 CPU names..
   Copyright (C) 1991-2013 Free Software Foundation, Inc.
   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

/* ISA masks.  */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS		OPTION_MASK_MFCRF
#define ISA_2_2_MASKS		(ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
#define ISA_2_4_MASKS		(ISA_2_2_MASKS | OPTION_MASK_FPRND)

  /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
     ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
     fre, fsqrt, etc. were no longer documented as optional.  Group masks by
     server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED	(ISA_2_2_MASKS				\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT)

#define ISA_2_5_MASKS_SERVER	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)

  /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
     altivec is a win so enable it.  */
#define ISA_2_6_MASKS_EMBEDDED	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER	(ISA_2_5_MASKS_SERVER			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_VSX			\
				 | OPTION_MASK_VSX_TIMODE)

#define POWERPC_7400_MASK	(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)

/* Deal with ports that do not have -mstrict-align.  */
#ifdef OPTION_MASK_STRICT_ALIGN
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
#else
#define OPTION_MASK_STRICT_ALIGN 0
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
#ifndef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#endif

/* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
#define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_DFP			\
				 | OPTION_MASK_DLMZB			\
				 | OPTION_MASK_FPRND			\
				 | OPTION_MASK_ISEL			\
				 | OPTION_MASK_MFCRF			\
				 | OPTION_MASK_MFPGPR			\
				 | OPTION_MASK_MULHW			\
				 | OPTION_MASK_NO_UPDATE		\
				 | OPTION_MASK_POPCNTB			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_POWERPC64		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT		\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_SOFT_FLOAT		\
				 | OPTION_MASK_STRICT_ALIGN_OPTIONAL	\
				 | OPTION_MASK_VSX			\
				 | OPTION_MASK_VSX_TIMODE)

#endif

/* This table occasionally claims that a processor does not support a
   particular feature even though it does, but the feature is slower than the
   alternative.  Thus, it shouldn't be relied on as a complete description of
   the processor's support.

   Please keep this list in order, and don't forget to update the documentation
   in invoke.texi when adding a new processor or flag.

   Before including this file, define a macro:

   RS6000_CPU (NAME, CPU, FLAGS)

   where the arguments are the fields of struct rs6000_ptt.  */

RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476,
	    MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
	    | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476,
	    MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2,
	    MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
	    | MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
	    | MASK_MFCRF | MASK_ISEL)
RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("970", PROCESSOR_POWER4,
	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL,
	    POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4,
	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7,   /* Don't add MASK_ISEL by default */
	    POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
	    | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
	    | MASK_VSX | MASK_RECIP_PRECISION | MASK_VSX_TIMODE)
RS6000_CPU ("power8", PROCESSOR_POWER7,   /* Don't add MASK_ISEL by default */
	    POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
	    | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
	    | MASK_VSX | MASK_RECIP_PRECISION | MASK_VSX_TIMODE)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
Commit	Line	Data
f10d3ac9	1	/* IBM RS/6000 CPU names..
d1e082c2	2	Copyright (C) 1991-2013 Free Software Foundation, Inc.
f10d3ac9 JM	3	Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
	4
	5	This file is part of GCC.
	6
	7	GCC is free software; you can redistribute it and/or modify it
	8	under the terms of the GNU General Public License as published
	9	by the Free Software Foundation; either version 3, or (at your
	10	option) any later version.
	11
	12	GCC is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GCC; see the file COPYING3. If not see
	19	<http://www.gnu.org/licenses/>. */
	20
4d967549 MM	21	/* ISA masks. */
	22	#ifndef ISA_2_1_MASKS
	23	#define ISA_2_1_MASKS OPTION_MASK_MFCRF
	24	#define ISA_2_2_MASKS (ISA_2_1_MASKS \| OPTION_MASK_POPCNTB)
	25	#define ISA_2_4_MASKS (ISA_2_2_MASKS \| OPTION_MASK_FPRND)
	26
	27	/* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
	28	ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
	29	fre, fsqrt, etc. were no longer documented as optional. Group masks by
	30	server and embedded. */
	31	#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \
	32	\| OPTION_MASK_CMPB \
	33	\| OPTION_MASK_RECIP_PRECISION \
	34	\| OPTION_MASK_PPC_GFXOPT \
	35	\| OPTION_MASK_PPC_GPOPT)
	36
	37	#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_DFP)
	38
	39	/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
	40	altivec is a win so enable it. */
	41	#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_POPCNTD)
	42	#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
	43	\| OPTION_MASK_POPCNTD \
	44	\| OPTION_MASK_ALTIVEC \
c6d5ff83 MM	45	\| OPTION_MASK_VSX \
c6d5ff83 MM	46	\| OPTION_MASK_VSX_TIMODE)
4d967549 MM	47
	48	#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_ALTIVEC)
	49
ad1a0853 MM	50	/* Deal with ports that do not have -mstrict-align. */
	51	#ifdef OPTION_MASK_STRICT_ALIGN
	52	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
	53	#else
	54	#define OPTION_MASK_STRICT_ALIGN 0
	55	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
	56	#ifndef MASK_STRICT_ALIGN
	57	#define MASK_STRICT_ALIGN 0
	58	#endif
	59	#endif
	60
4d967549 MM	61	/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
	62	#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
	63	\| OPTION_MASK_CMPB \
	64	\| OPTION_MASK_DFP \
	65	\| OPTION_MASK_DLMZB \
	66	\| OPTION_MASK_FPRND \
	67	\| OPTION_MASK_ISEL \
	68	\| OPTION_MASK_MFCRF \
	69	\| OPTION_MASK_MFPGPR \
	70	\| OPTION_MASK_MULHW \
	71	\| OPTION_MASK_NO_UPDATE \
	72	\| OPTION_MASK_POPCNTB \
	73	\| OPTION_MASK_POPCNTD \
	74	\| OPTION_MASK_POWERPC64 \
	75	\| OPTION_MASK_PPC_GFXOPT \
	76	\| OPTION_MASK_PPC_GPOPT \
	77	\| OPTION_MASK_RECIP_PRECISION \
	78	\| OPTION_MASK_SOFT_FLOAT \
ad1a0853	79	\| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
c6d5ff83 MM	80	\| OPTION_MASK_VSX \
c6d5ff83 MM	81	\| OPTION_MASK_VSX_TIMODE)
4d967549 MM	82
	83	#endif
	84
f10d3ac9 JM	85	/* This table occasionally claims that a processor does not support a
	86	particular feature even though it does, but the feature is slower than the
	87	alternative. Thus, it shouldn't be relied on as a complete description of
	88	the processor's support.
	89
	90	Please keep this list in order, and don't forget to update the documentation
	91	in invoke.texi when adding a new processor or flag.
	92
	93	Before including this file, define a macro:
	94
	95	RS6000_CPU (NAME, CPU, FLAGS)
	96
	97	where the arguments are the fields of struct rs6000_ptt. */
	98
6b39bc38 SB	99	RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
	100	RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT \| MASK_STRICT_ALIGN)
	101	RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	102	RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW \| MASK_DLMZB)
	103	RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	104	RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW \| MASK_DLMZB)
	105	RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	106	RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW \| MASK_DLMZB)
f10d3ac9	107	RS6000_CPU ("476", PROCESSOR_PPC476,
6b39bc38	108	MASK_SOFT_FLOAT \| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB
f10d3ac9	109	\| MASK_FPRND \| MASK_CMPB \| MASK_MULHW \| MASK_DLMZB)
6b39bc38 SB	110	RS6000_CPU ("476fp", PROCESSOR_PPC476,
	111	MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
	112	\| MASK_CMPB \| MASK_MULHW \| MASK_DLMZB)
	113	RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
	114	RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE \| MASK_STRING)
	115	RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	116	RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	117	RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	118	RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
	119	RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
	120	RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	121	RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	122	RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
f10d3ac9 JM	123	RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
f10d3ac9 JM	124	RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
6b39bc38 SB	125	RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
	126	RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	127	RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	128	RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	129	RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN \| MASK_ISEL)
	130	RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN \| MASK_ISEL)
f10d3ac9	131	RS6000_CPU ("a2", PROCESSOR_PPCA2,
6b39bc38 SB	132	MASK_PPC_GFXOPT \| MASK_POWERPC64 \| MASK_POPCNTB \| MASK_CMPB
	133	\| MASK_NO_UPDATE)
	134	RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
	135	RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
	136	RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT \| MASK_ISEL)
f10d3ac9	137	RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
6b39bc38 SB	138	MASK_POWERPC64 \| MASK_PPC_GFXOPT \| MASK_ISEL)
	139	RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
	140	MASK_POWERPC64 \| MASK_PPC_GFXOPT \| MASK_ISEL)
683ed19e EW	141	RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK \| MASK_POWERPC64
683ed19e EW	142	\| MASK_MFCRF \| MASK_ISEL)
6b39bc38	143	RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
f10d3ac9 JM	144	RS6000_CPU ("970", PROCESSOR_POWER4,
	145	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
	146	RS6000_CPU ("cell", PROCESSOR_CELL,
	147	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
6b39bc38 SB	148	RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
6b39bc38 SB	149	RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
f10d3ac9 JM	150	RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
	151	RS6000_CPU ("G5", PROCESSOR_POWER4,
	152	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
6b39bc38 SB	153	RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW \| MASK_DLMZB)
	154	RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	155	RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9	156	\| MASK_PPC_GFXOPT \| MASK_MFCRF)
6b39bc38	157	RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9	158	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB)
6b39bc38	159	RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9	160	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND)
6b39bc38	161	RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9 JM	162	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
f10d3ac9 JM	163	\| MASK_CMPB \| MASK_DFP \| MASK_RECIP_PRECISION)
6b39bc38	164	RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9 JM	165	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
	166	\| MASK_CMPB \| MASK_DFP \| MASK_MFPGPR \| MASK_RECIP_PRECISION)
	167	RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
	168	POWERPC_7400_MASK \| MASK_POWERPC64 \| MASK_PPC_GPOPT \| MASK_MFCRF
	169	\| MASK_POPCNTB \| MASK_FPRND \| MASK_CMPB \| MASK_DFP \| MASK_POPCNTD
c6d5ff83	170	\| MASK_VSX \| MASK_RECIP_PRECISION \| MASK_VSX_TIMODE)
428bffcb PB	171	RS6000_CPU ("power8", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
	172	POWERPC_7400_MASK \| MASK_POWERPC64 \| MASK_PPC_GPOPT \| MASK_MFCRF
	173	\| MASK_POPCNTB \| MASK_FPRND \| MASK_CMPB \| MASK_DFP \| MASK_POPCNTD
c6d5ff83	174	\| MASK_VSX \| MASK_RECIP_PRECISION \| MASK_VSX_TIMODE)
6b39bc38 SB	175	RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
	176	RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	177	RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT \| MASK_POWERPC64)