[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000-cpus.def

/* IBM RS/6000 CPU names..
   Copyright (C) 1991-2016 Free Software Foundation, Inc.
   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

/* ISA masks.  */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS		OPTION_MASK_MFCRF
#define ISA_2_2_MASKS		(ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
#define ISA_2_4_MASKS		(ISA_2_2_MASKS | OPTION_MASK_FPRND)

  /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
     ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
     fre, fsqrt, etc. were no longer documented as optional.  Group masks by
     server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED	(ISA_2_4_MASKS				\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT)

#define ISA_2_5_MASKS_SERVER	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)

  /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
     altivec is a win so enable it.  */
  /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
     PR 58587 is fixed.  */
#define ISA_2_6_MASKS_EMBEDDED	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER	(ISA_2_5_MASKS_SERVER			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_FLOAT128			\
				 | OPTION_MASK_VSX			\
				 | OPTION_MASK_UPPER_REGS_DF)

/* For now, don't provide an embedded version of ISA 2.07.  */
#define ISA_2_7_MASKS_SERVER	(ISA_2_6_MASKS_SERVER			\
				 | OPTION_MASK_P8_FUSION		\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_CRYPTO			\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_HTM			\
				 | OPTION_MASK_QUAD_MEMORY		\
  				 | OPTION_MASK_QUAD_MEMORY_ATOMIC	\
				 | OPTION_MASK_UPPER_REGS_SF)

/* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
   P9_DFORM or P9_MINMAX until they are fully debugged.  */
#define ISA_3_0_MASKS_SERVER	(ISA_2_7_MASKS_SERVER			\
				 | OPTION_MASK_FLOAT128_HW		\
				 | OPTION_MASK_ISEL			\
				 | OPTION_MASK_MODULO			\
				 | OPTION_MASK_P9_FUSION		\
				 | OPTION_MASK_P9_VECTOR)

#define POWERPC_7400_MASK	(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)

/* Deal with ports that do not have -mstrict-align.  */
#ifdef OPTION_MASK_STRICT_ALIGN
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
#else
#define OPTION_MASK_STRICT_ALIGN 0
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
#ifndef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#endif

/* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
#define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_CRYPTO			\
				 | OPTION_MASK_DFP			\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_DLMZB			\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_FLOAT128			\
				 | OPTION_MASK_FPRND			\
				 | OPTION_MASK_HTM			\
				 | OPTION_MASK_ISEL			\
				 | OPTION_MASK_MFCRF			\
				 | OPTION_MASK_MFPGPR			\
				 | OPTION_MASK_MODULO			\
				 | OPTION_MASK_MULHW			\
				 | OPTION_MASK_NO_UPDATE		\
				 | OPTION_MASK_P8_FUSION		\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_P9_DFORM			\
				 | OPTION_MASK_P9_FUSION		\
				 | OPTION_MASK_P9_MINMAX		\
				 | OPTION_MASK_P9_VECTOR		\
				 | OPTION_MASK_POPCNTB			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_POWERPC64		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT		\
				 | OPTION_MASK_QUAD_MEMORY		\
				 | OPTION_MASK_QUAD_MEMORY_ATOMIC	\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_SOFT_FLOAT		\
				 | OPTION_MASK_STRICT_ALIGN_OPTIONAL	\
				 | OPTION_MASK_TOC_FUSION		\
				 | OPTION_MASK_UPPER_REGS_DF		\
				 | OPTION_MASK_UPPER_REGS_SF		\
				 | OPTION_MASK_VSX			\
				 | OPTION_MASK_VSX_TIMODE)

#endif

/* This table occasionally claims that a processor does not support a
   particular feature even though it does, but the feature is slower than the
   alternative.  Thus, it shouldn't be relied on as a complete description of
   the processor's support.

   Please keep this list in order, and don't forget to update the documentation
   in invoke.texi when adding a new processor or flag.

   Before including this file, define a macro:

   RS6000_CPU (NAME, CPU, FLAGS)

   where the arguments are the fields of struct rs6000_ptt.  */

RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476,
	    MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
	    | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476,
	    MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2,
	    MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
	    | MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
	    | MASK_MFCRF | MASK_ISEL)
RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("970", PROCESSOR_POWER4,
	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL,
	    POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4,
	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7,   /* Don't add MASK_ISEL by default */
	    POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
	    | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
	    | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
Commit	Line	Data
d41a5879	1	/* IBM RS/6000 CPU names..
f1717362	2	Copyright (C) 1991-2016 Free Software Foundation, Inc.
d41a5879	3	Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
	4
	5	This file is part of GCC.
	6
	7	GCC is free software; you can redistribute it and/or modify it
	8	under the terms of the GNU General Public License as published
	9	by the Free Software Foundation; either version 3, or (at your
	10	option) any later version.
	11
	12	GCC is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GCC; see the file COPYING3. If not see
	19	<http://www.gnu.org/licenses/>. */
	20
62b54165	21	/* ISA masks. */
	22	#ifndef ISA_2_1_MASKS
	23	#define ISA_2_1_MASKS OPTION_MASK_MFCRF
	24	#define ISA_2_2_MASKS (ISA_2_1_MASKS \| OPTION_MASK_POPCNTB)
	25	#define ISA_2_4_MASKS (ISA_2_2_MASKS \| OPTION_MASK_FPRND)
	26
	27	/* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
	28	ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
	29	fre, fsqrt, etc. were no longer documented as optional. Group masks by
	30	server and embedded. */
81f0e7d0	31	#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
62b54165	32	\| OPTION_MASK_CMPB \
	33	\| OPTION_MASK_RECIP_PRECISION \
	34	\| OPTION_MASK_PPC_GFXOPT \
	35	\| OPTION_MASK_PPC_GPOPT)
	36
	37	#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_DFP)
	38
	39	/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
	40	altivec is a win so enable it. */
b6f7290d	41	/* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
b6f7290d	42	PR 58587 is fixed. */
62b54165	43	#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_POPCNTD)
	44	#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
	45	\| OPTION_MASK_POPCNTD \
	46	\| OPTION_MASK_ALTIVEC \
3f2bdc95	47	\| OPTION_MASK_FLOAT128 \
c9f03f9b	48	\| OPTION_MASK_VSX \
b6f7290d	49	\| OPTION_MASK_UPPER_REGS_DF)
62b54165	50
81f0e7d0	51	/* For now, don't provide an embedded version of ISA 2.07. */
	52	#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
	53	\| OPTION_MASK_P8_FUSION \
	54	\| OPTION_MASK_P8_VECTOR \
	55	\| OPTION_MASK_CRYPTO \
	56	\| OPTION_MASK_DIRECT_MOVE \
9fb5a144	57	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
5088e479	58	\| OPTION_MASK_HTM \
1c09f133	59	\| OPTION_MASK_QUAD_MEMORY \
c9f03f9b	60	\| OPTION_MASK_QUAD_MEMORY_ATOMIC \
c9f03f9b	61	\| OPTION_MASK_UPPER_REGS_SF)
81f0e7d0	62
a875ad2e	63	/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
	64	P9_DFORM or P9_MINMAX until they are fully debugged. */
	65	#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
	66	\| OPTION_MASK_FLOAT128_HW \
	67	\| OPTION_MASK_ISEL \
	68	\| OPTION_MASK_MODULO \
	69	\| OPTION_MASK_P9_FUSION \
	70	\| OPTION_MASK_P9_VECTOR)
	71
62b54165	72	#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_ALTIVEC)
62b54165	73
4df09c64	74	/* Deal with ports that do not have -mstrict-align. */
	75	#ifdef OPTION_MASK_STRICT_ALIGN
	76	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
	77	#else
	78	#define OPTION_MASK_STRICT_ALIGN 0
	79	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
	80	#ifndef MASK_STRICT_ALIGN
	81	#define MASK_STRICT_ALIGN 0
	82	#endif
	83	#endif
	84
62b54165	85	/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
	86	#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
	87	\| OPTION_MASK_CMPB \
81f0e7d0	88	\| OPTION_MASK_CRYPTO \
62b54165	89	\| OPTION_MASK_DFP \
81f0e7d0	90	\| OPTION_MASK_DIRECT_MOVE \
62b54165	91	\| OPTION_MASK_DLMZB \
9fb5a144	92	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
3f2bdc95	93	\| OPTION_MASK_FLOAT128 \
62b54165	94	\| OPTION_MASK_FPRND \
5088e479	95	\| OPTION_MASK_HTM \
62b54165	96	\| OPTION_MASK_ISEL \
	97	\| OPTION_MASK_MFCRF \
	98	\| OPTION_MASK_MFPGPR \
a875ad2e	99	\| OPTION_MASK_MODULO \
62b54165	100	\| OPTION_MASK_MULHW \
62b54165	101	\| OPTION_MASK_NO_UPDATE \
81f0e7d0	102	\| OPTION_MASK_P8_FUSION \
81f0e7d0	103	\| OPTION_MASK_P8_VECTOR \
a875ad2e	104	\| OPTION_MASK_P9_DFORM \
	105	\| OPTION_MASK_P9_FUSION \
	106	\| OPTION_MASK_P9_MINMAX \
	107	\| OPTION_MASK_P9_VECTOR \
62b54165	108	\| OPTION_MASK_POPCNTB \
	109	\| OPTION_MASK_POPCNTD \
	110	\| OPTION_MASK_POWERPC64 \
	111	\| OPTION_MASK_PPC_GFXOPT \
	112	\| OPTION_MASK_PPC_GPOPT \
81f0e7d0	113	\| OPTION_MASK_QUAD_MEMORY \
83c54f52	114	\| OPTION_MASK_QUAD_MEMORY_ATOMIC \
62b54165	115	\| OPTION_MASK_RECIP_PRECISION \
62b54165	116	\| OPTION_MASK_SOFT_FLOAT \
4df09c64	117	\| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
a875ad2e	118	\| OPTION_MASK_TOC_FUSION \
c9f03f9b	119	\| OPTION_MASK_UPPER_REGS_DF \
c9f03f9b	120	\| OPTION_MASK_UPPER_REGS_SF \
33a2d887	121	\| OPTION_MASK_VSX \
33a2d887	122	\| OPTION_MASK_VSX_TIMODE)
62b54165	123
	124	#endif
	125
d41a5879	126	/* This table occasionally claims that a processor does not support a
	127	particular feature even though it does, but the feature is slower than the
	128	alternative. Thus, it shouldn't be relied on as a complete description of
	129	the processor's support.
	130
	131	Please keep this list in order, and don't forget to update the documentation
	132	in invoke.texi when adding a new processor or flag.
	133
	134	Before including this file, define a macro:
	135
	136	RS6000_CPU (NAME, CPU, FLAGS)
	137
	138	where the arguments are the fields of struct rs6000_ptt. */
	139
4ff70f1c	140	RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
	141	RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT \| MASK_STRICT_ALIGN)
	142	RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	143	RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW \| MASK_DLMZB)
	144	RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	145	RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW \| MASK_DLMZB)
	146	RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	147	RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW \| MASK_DLMZB)
d41a5879	148	RS6000_CPU ("476", PROCESSOR_PPC476,
4ff70f1c	149	MASK_SOFT_FLOAT \| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB
d41a5879	150	\| MASK_FPRND \| MASK_CMPB \| MASK_MULHW \| MASK_DLMZB)
4ff70f1c	151	RS6000_CPU ("476fp", PROCESSOR_PPC476,
	152	MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
	153	\| MASK_CMPB \| MASK_MULHW \| MASK_DLMZB)
	154	RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
	155	RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE \| MASK_STRING)
	156	RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	157	RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	158	RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	159	RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
	160	RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
	161	RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	162	RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	163	RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
d41a5879	164	RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
d41a5879	165	RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
4ff70f1c	166	RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
	167	RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	168	RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	169	RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	170	RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN \| MASK_ISEL)
	171	RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN \| MASK_ISEL)
d41a5879	172	RS6000_CPU ("a2", PROCESSOR_PPCA2,
4ff70f1c	173	MASK_PPC_GFXOPT \| MASK_POWERPC64 \| MASK_POPCNTB \| MASK_CMPB
	174	\| MASK_NO_UPDATE)
	175	RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
	176	RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
	177	RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT \| MASK_ISEL)
d41a5879	178	RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
4ff70f1c	179	MASK_POWERPC64 \| MASK_PPC_GFXOPT \| MASK_ISEL)
	180	RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
	181	MASK_POWERPC64 \| MASK_PPC_GFXOPT \| MASK_ISEL)
b770074c	182	RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK \| MASK_POWERPC64
b770074c	183	\| MASK_MFCRF \| MASK_ISEL)
4ff70f1c	184	RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
d41a5879	185	RS6000_CPU ("970", PROCESSOR_POWER4,
	186	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
	187	RS6000_CPU ("cell", PROCESSOR_CELL,
	188	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
4ff70f1c	189	RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
4ff70f1c	190	RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
d41a5879	191	RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
	192	RS6000_CPU ("G5", PROCESSOR_POWER4,
	193	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
4ff70f1c	194	RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW \| MASK_DLMZB)
	195	RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	196	RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	197	\| MASK_PPC_GFXOPT \| MASK_MFCRF)
4ff70f1c	198	RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	199	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB)
4ff70f1c	200	RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	201	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND)
4ff70f1c	202	RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	203	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
d41a5879	204	\| MASK_CMPB \| MASK_DFP \| MASK_RECIP_PRECISION)
4ff70f1c	205	RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	206	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
	207	\| MASK_CMPB \| MASK_DFP \| MASK_MFPGPR \| MASK_RECIP_PRECISION)
	208	RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
	209	POWERPC_7400_MASK \| MASK_POWERPC64 \| MASK_PPC_GPOPT \| MASK_MFCRF
	210	\| MASK_POPCNTB \| MASK_FPRND \| MASK_CMPB \| MASK_DFP \| MASK_POPCNTD
b6f7290d	211	\| MASK_VSX \| MASK_RECIP_PRECISION \| OPTION_MASK_UPPER_REGS_DF)
ce67dec2	212	RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 \| ISA_2_7_MASKS_SERVER)
a875ad2e	213	RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 \| ISA_3_0_MASKS_SERVER)
4ff70f1c	214	RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
4ff70f1c	215	RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT \| MASK_POWERPC64)
49a1b909	216	RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 \| ISA_2_7_MASKS_SERVER)
4ff70f1c	217	RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT \| MASK_POWERPC64)