[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000-cpus.def

/* IBM RS/6000 CPU names..
   Copyright (C) 1991-2019 Free Software Foundation, Inc.
   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

/* ISA masks.  */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS		OPTION_MASK_MFCRF
#define ISA_2_2_MASKS		(ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
#define ISA_2_4_MASKS		(ISA_2_2_MASKS | OPTION_MASK_FPRND)

  /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
     ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
     fre, fsqrt, etc. were no longer documented as optional.  Group masks by
     server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED	(ISA_2_4_MASKS				\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT)

#define ISA_2_5_MASKS_SERVER	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)

  /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
     altivec is a win so enable it.  */
#define ISA_2_6_MASKS_EMBEDDED	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER	(ISA_2_5_MASKS_SERVER			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_VSX)

/* For now, don't provide an embedded version of ISA 2.07.  Do not set power8
   fusion here, instead set it in rs6000.c if we are tuning for a power8
   system.  */
#define ISA_2_7_MASKS_SERVER	(ISA_2_6_MASKS_SERVER			\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_CRYPTO			\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_HTM			\
				 | OPTION_MASK_QUAD_MEMORY		\
				 | OPTION_MASK_QUAD_MEMORY_ATOMIC)

/* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
   FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
#define ISA_3_0_MASKS_SERVER	(ISA_2_7_MASKS_SERVER			\
				 | OPTION_MASK_ISEL			\
				 | OPTION_MASK_MODULO			\
				 | OPTION_MASK_P9_MINMAX		\
				 | OPTION_MASK_P9_MISC			\
				 | OPTION_MASK_P9_VECTOR)

/* Support for the IEEE 128-bit floating point hardware requires a lot of the
   VSX instructions that are part of ISA 3.0.  */
#define ISA_3_0_MASKS_IEEE	(OPTION_MASK_VSX			\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_P9_VECTOR		\
				 | OPTION_MASK_DIRECT_MOVE)

/* Flags that need to be turned off if -mno-power9-vector.  */
#define OTHER_P9_VECTOR_MASKS	(OPTION_MASK_FLOAT128_HW		\
				 | OPTION_MASK_P9_MINMAX)

/* Flags that need to be turned off if -mno-power8-vector.  */
#define OTHER_P8_VECTOR_MASKS	(OTHER_P9_VECTOR_MASKS			\
				 | OPTION_MASK_P9_VECTOR		\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_CRYPTO)

/* Flags that need to be turned off if -mno-vsx.  */
#define OTHER_VSX_VECTOR_MASKS	(OTHER_P8_VECTOR_MASKS			\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_FLOAT128_KEYWORD		\
				 | OPTION_MASK_P8_VECTOR)

#define POWERPC_7400_MASK	(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)

/* Deal with ports that do not have -mstrict-align.  */
#ifdef OPTION_MASK_STRICT_ALIGN
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
#else
#define OPTION_MASK_STRICT_ALIGN 0
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
#ifndef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#endif

/* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
#define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_CRYPTO			\
				 | OPTION_MASK_DFP			\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_DLMZB			\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_FLOAT128_HW		\
				 | OPTION_MASK_FLOAT128_KEYWORD		\
				 | OPTION_MASK_FPRND			\
				 | OPTION_MASK_HTM			\
				 | OPTION_MASK_ISEL			\
				 | OPTION_MASK_MFCRF			\
				 | OPTION_MASK_MFPGPR			\
				 | OPTION_MASK_MODULO			\
				 | OPTION_MASK_MULHW			\
				 | OPTION_MASK_NO_UPDATE		\
				 | OPTION_MASK_P8_FUSION		\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_P9_MINMAX		\
				 | OPTION_MASK_P9_MISC			\
				 | OPTION_MASK_P9_VECTOR		\
				 | OPTION_MASK_POPCNTB			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_POWERPC64		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT		\
				 | OPTION_MASK_QUAD_MEMORY		\
				 | OPTION_MASK_QUAD_MEMORY_ATOMIC	\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_SOFT_FLOAT		\
				 | OPTION_MASK_STRICT_ALIGN_OPTIONAL	\
				 | OPTION_MASK_VSX)

#endif

/* This table occasionally claims that a processor does not support a
   particular feature even though it does, but the feature is slower than the
   alternative.  Thus, it shouldn't be relied on as a complete description of
   the processor's support.

   Please keep this list in order, and don't forget to update the documentation
   in invoke.texi when adding a new processor or flag.

   Before including this file, define a macro:

   RS6000_CPU (NAME, CPU, FLAGS)

   where the arguments are the fields of struct rs6000_ptt.  */

RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476,
	    MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
	    | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476,
	    MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE)
RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2,
	    MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
	    | MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
	    | MASK_MFCRF | MASK_ISEL)
RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("970", PROCESSOR_POWER4,
	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL,
	    POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4,
	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
Commit	Line	Data
d41a5879	1	/* IBM RS/6000 CPU names..
fbd26352	2	Copyright (C) 1991-2019 Free Software Foundation, Inc.
d41a5879	3	Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
	4
	5	This file is part of GCC.
	6
	7	GCC is free software; you can redistribute it and/or modify it
	8	under the terms of the GNU General Public License as published
	9	by the Free Software Foundation; either version 3, or (at your
	10	option) any later version.
	11
	12	GCC is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GCC; see the file COPYING3. If not see
	19	<http://www.gnu.org/licenses/>. */
	20
62b54165	21	/* ISA masks. */
	22	#ifndef ISA_2_1_MASKS
	23	#define ISA_2_1_MASKS OPTION_MASK_MFCRF
	24	#define ISA_2_2_MASKS (ISA_2_1_MASKS \| OPTION_MASK_POPCNTB)
	25	#define ISA_2_4_MASKS (ISA_2_2_MASKS \| OPTION_MASK_FPRND)
	26
	27	/* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
	28	ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
	29	fre, fsqrt, etc. were no longer documented as optional. Group masks by
	30	server and embedded. */
81f0e7d0	31	#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
62b54165	32	\| OPTION_MASK_CMPB \
	33	\| OPTION_MASK_RECIP_PRECISION \
	34	\| OPTION_MASK_PPC_GFXOPT \
	35	\| OPTION_MASK_PPC_GPOPT)
	36
	37	#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_DFP)
	38
	39	/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
	40	altivec is a win so enable it. */
	41	#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_POPCNTD)
	42	#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
	43	\| OPTION_MASK_POPCNTD \
	44	\| OPTION_MASK_ALTIVEC \
0a3cd125	45	\| OPTION_MASK_VSX)
62b54165	46
453b5ac5	47	/* For now, don't provide an embedded version of ISA 2.07. Do not set power8
	48	fusion here, instead set it in rs6000.c if we are tuning for a power8
	49	system. */
81f0e7d0	50	#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
81f0e7d0	51	\| OPTION_MASK_P8_VECTOR \
	52	\| OPTION_MASK_CRYPTO \
	53	\| OPTION_MASK_DIRECT_MOVE \
9fb5a144	54	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
5088e479	55	\| OPTION_MASK_HTM \
1c09f133	56	\| OPTION_MASK_QUAD_MEMORY \
a12937bc	57	\| OPTION_MASK_QUAD_MEMORY_ATOMIC)
81f0e7d0	58
a875ad2e	59	/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
98e771d6	60	FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
a875ad2e	61	#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
a875ad2e	62	\| OPTION_MASK_ISEL \
a875ad2e	63	\| OPTION_MASK_MODULO \
a8022fa7	64	\| OPTION_MASK_P9_MINMAX \
17c32c4a	65	\| OPTION_MASK_P9_MISC \
a875ad2e	66	\| OPTION_MASK_P9_VECTOR)
a875ad2e	67
98e771d6	68	/* Support for the IEEE 128-bit floating point hardware requires a lot of the
	69	VSX instructions that are part of ISA 3.0. */
	70	#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
	71	\| OPTION_MASK_P8_VECTOR \
	72	\| OPTION_MASK_P9_VECTOR \
a12937bc	73	\| OPTION_MASK_DIRECT_MOVE)
98e771d6	74
127080a4	75	/* Flags that need to be turned off if -mno-power9-vector. */
127080a4	76	#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
127080a4	77	\| OPTION_MASK_P9_MINMAX)
	78
	79	/* Flags that need to be turned off if -mno-power8-vector. */
	80	#define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \
	81	\| OPTION_MASK_P9_VECTOR \
	82	\| OPTION_MASK_DIRECT_MOVE \
0a3cd125	83	\| OPTION_MASK_CRYPTO)
127080a4	84
	85	/* Flags that need to be turned off if -mno-vsx. */
	86	#define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \
	87	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
	88	\| OPTION_MASK_FLOAT128_KEYWORD \
1da51dfb	89	\| OPTION_MASK_P8_VECTOR)
127080a4	90
62b54165	91	#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_ALTIVEC)
62b54165	92
4df09c64	93	/* Deal with ports that do not have -mstrict-align. */
	94	#ifdef OPTION_MASK_STRICT_ALIGN
	95	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
	96	#else
	97	#define OPTION_MASK_STRICT_ALIGN 0
	98	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
	99	#ifndef MASK_STRICT_ALIGN
	100	#define MASK_STRICT_ALIGN 0
	101	#endif
	102	#endif
	103
62b54165	104	/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
	105	#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
	106	\| OPTION_MASK_CMPB \
81f0e7d0	107	\| OPTION_MASK_CRYPTO \
62b54165	108	\| OPTION_MASK_DFP \
81f0e7d0	109	\| OPTION_MASK_DIRECT_MOVE \
62b54165	110	\| OPTION_MASK_DLMZB \
9fb5a144	111	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
7d29bba9	112	\| OPTION_MASK_FLOAT128_HW \
7d29bba9	113	\| OPTION_MASK_FLOAT128_KEYWORD \
62b54165	114	\| OPTION_MASK_FPRND \
5088e479	115	\| OPTION_MASK_HTM \
62b54165	116	\| OPTION_MASK_ISEL \
	117	\| OPTION_MASK_MFCRF \
	118	\| OPTION_MASK_MFPGPR \
a875ad2e	119	\| OPTION_MASK_MODULO \
62b54165	120	\| OPTION_MASK_MULHW \
62b54165	121	\| OPTION_MASK_NO_UPDATE \
81f0e7d0	122	\| OPTION_MASK_P8_FUSION \
81f0e7d0	123	\| OPTION_MASK_P8_VECTOR \
a875ad2e	124	\| OPTION_MASK_P9_MINMAX \
17c32c4a	125	\| OPTION_MASK_P9_MISC \
a875ad2e	126	\| OPTION_MASK_P9_VECTOR \
62b54165	127	\| OPTION_MASK_POPCNTB \
	128	\| OPTION_MASK_POPCNTD \
	129	\| OPTION_MASK_POWERPC64 \
	130	\| OPTION_MASK_PPC_GFXOPT \
	131	\| OPTION_MASK_PPC_GPOPT \
81f0e7d0	132	\| OPTION_MASK_QUAD_MEMORY \
83c54f52	133	\| OPTION_MASK_QUAD_MEMORY_ATOMIC \
62b54165	134	\| OPTION_MASK_RECIP_PRECISION \
62b54165	135	\| OPTION_MASK_SOFT_FLOAT \
4df09c64	136	\| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
1da51dfb	137	\| OPTION_MASK_VSX)
62b54165	138
	139	#endif
	140
d41a5879	141	/* This table occasionally claims that a processor does not support a
	142	particular feature even though it does, but the feature is slower than the
	143	alternative. Thus, it shouldn't be relied on as a complete description of
	144	the processor's support.
	145
	146	Please keep this list in order, and don't forget to update the documentation
	147	in invoke.texi when adding a new processor or flag.
	148
	149	Before including this file, define a macro:
	150
	151	RS6000_CPU (NAME, CPU, FLAGS)
	152
	153	where the arguments are the fields of struct rs6000_ptt. */
	154
4ff70f1c	155	RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
	156	RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT \| MASK_STRICT_ALIGN)
	157	RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	158	RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW \| MASK_DLMZB)
	159	RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	160	RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW \| MASK_DLMZB)
	161	RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	162	RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW \| MASK_DLMZB)
d41a5879	163	RS6000_CPU ("476", PROCESSOR_PPC476,
4ff70f1c	164	MASK_SOFT_FLOAT \| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB
d41a5879	165	\| MASK_FPRND \| MASK_CMPB \| MASK_MULHW \| MASK_DLMZB)
4ff70f1c	166	RS6000_CPU ("476fp", PROCESSOR_PPC476,
	167	MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
	168	\| MASK_CMPB \| MASK_MULHW \| MASK_DLMZB)
	169	RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
9599990a	170	RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE)
4ff70f1c	171	RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	172	RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	173	RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	174	RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
	175	RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
	176	RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	177	RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	178	RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
d41a5879	179	RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
d41a5879	180	RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
4ff70f1c	181	RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
	182	RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	183	RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	184	RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	185	RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN \| MASK_ISEL)
	186	RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN \| MASK_ISEL)
d41a5879	187	RS6000_CPU ("a2", PROCESSOR_PPCA2,
4ff70f1c	188	MASK_PPC_GFXOPT \| MASK_POWERPC64 \| MASK_POPCNTB \| MASK_CMPB
	189	\| MASK_NO_UPDATE)
	190	RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
	191	RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
	192	RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT \| MASK_ISEL)
d41a5879	193	RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
4ff70f1c	194	MASK_POWERPC64 \| MASK_PPC_GFXOPT \| MASK_ISEL)
	195	RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
	196	MASK_POWERPC64 \| MASK_PPC_GFXOPT \| MASK_ISEL)
b770074c	197	RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK \| MASK_POWERPC64
b770074c	198	\| MASK_MFCRF \| MASK_ISEL)
4ff70f1c	199	RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
d41a5879	200	RS6000_CPU ("970", PROCESSOR_POWER4,
	201	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
	202	RS6000_CPU ("cell", PROCESSOR_CELL,
	203	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
4ff70f1c	204	RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
4ff70f1c	205	RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
d41a5879	206	RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
	207	RS6000_CPU ("G5", PROCESSOR_POWER4,
	208	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
4ff70f1c	209	RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW \| MASK_DLMZB)
	210	RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	211	RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	212	\| MASK_PPC_GFXOPT \| MASK_MFCRF)
4ff70f1c	213	RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	214	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB)
4ff70f1c	215	RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	216	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND)
4ff70f1c	217	RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	218	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
d41a5879	219	\| MASK_CMPB \| MASK_DFP \| MASK_RECIP_PRECISION)
4ff70f1c	220	RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 \| MASK_PPC_GPOPT
d41a5879	221	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
d41a5879	222	\| MASK_CMPB \| MASK_DFP \| MASK_MFPGPR \| MASK_RECIP_PRECISION)
0a3cd125	223	RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 \| ISA_2_6_MASKS_SERVER)
ce67dec2	224	RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 \| ISA_2_7_MASKS_SERVER)
a875ad2e	225	RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 \| ISA_3_0_MASKS_SERVER)
4ff70f1c	226	RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
4ff70f1c	227	RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT \| MASK_POWERPC64)
49a1b909	228	RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 \| ISA_2_7_MASKS_SERVER)
4ff70f1c	229	RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT \| MASK_POWERPC64)