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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
f676971a | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
5b86a469 | 3 | 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
39d14dda KC |
20 | Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
cd3ce9b4 | 55 | #include "tree-gimple.h" |
4d3e6fae | 56 | #include "intl.h" |
59d6560b | 57 | #include "params.h" |
1bc7c5b6 ZW |
58 | #if TARGET_XCOFF |
59 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
60 | #endif | |
93a27b7b ZW |
61 | #if TARGET_MACHO |
62 | #include "gstab.h" /* for N_SLINE */ | |
63 | #endif | |
9b30bae2 | 64 | |
7509c759 MM |
65 | #ifndef TARGET_NO_PROTOTYPE |
66 | #define TARGET_NO_PROTOTYPE 0 | |
67 | #endif | |
68 | ||
9878760c RK |
69 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
70 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
71 | ||
d1d0c603 JJ |
72 | /* Structure used to define the rs6000 stack */ |
73 | typedef struct rs6000_stack { | |
74 | int first_gp_reg_save; /* first callee saved GP register used */ | |
75 | int first_fp_reg_save; /* first callee saved FP register used */ | |
76 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
77 | int lr_save_p; /* true if the link reg needs to be saved */ | |
78 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
79 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
d1d0c603 JJ |
80 | int push_p; /* true if we need to allocate stack space */ |
81 | int calls_p; /* true if the function makes any calls */ | |
c4ad648e | 82 | int world_save_p; /* true if we're saving *everything*: |
d62294f5 | 83 | r13-r31, cr, f14-f31, vrsave, v20-v31 */ |
d1d0c603 JJ |
84 | enum rs6000_abi abi; /* which ABI to use */ |
85 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
86 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
87 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
88 | int lr_save_offset; /* offset to save LR from initial SP */ | |
89 | int cr_save_offset; /* offset to save CR from initial SP */ | |
90 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
91 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
d1d0c603 JJ |
92 | int varargs_save_offset; /* offset to save the varargs registers */ |
93 | int ehrd_offset; /* offset to EH return data */ | |
94 | int reg_size; /* register size (4 or 8) */ | |
d1d0c603 JJ |
95 | HOST_WIDE_INT vars_size; /* variable save area size */ |
96 | int parm_size; /* outgoing parameter size */ | |
97 | int save_size; /* save area size */ | |
98 | int fixed_size; /* fixed size of stack frame */ | |
99 | int gp_size; /* size of saved GP registers */ | |
100 | int fp_size; /* size of saved FP registers */ | |
101 | int altivec_size; /* size of saved AltiVec registers */ | |
102 | int cr_size; /* size to hold CR if not in save_size */ | |
d1d0c603 JJ |
103 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ |
104 | int altivec_padding_size; /* size of altivec alignment padding if | |
105 | not in save_size */ | |
106 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
107 | int spe_padding_size; | |
d1d0c603 JJ |
108 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ |
109 | int spe_64bit_regs_used; | |
110 | } rs6000_stack_t; | |
111 | ||
5b667039 JJ |
112 | /* A C structure for machine-specific, per-function data. |
113 | This is added to the cfun structure. */ | |
114 | typedef struct machine_function GTY(()) | |
115 | { | |
116 | /* Flags if __builtin_return_address (n) with n >= 1 was used. */ | |
117 | int ra_needs_full_frame; | |
118 | /* Some local-dynamic symbol. */ | |
119 | const char *some_ld_name; | |
120 | /* Whether the instruction chain has been scanned already. */ | |
121 | int insn_chain_scanned_p; | |
122 | /* Flags if __builtin_return_address (0) was used. */ | |
123 | int ra_need_lr; | |
124 | /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4 | |
125 | varargs save area. */ | |
126 | HOST_WIDE_INT varargs_save_offset; | |
127 | } machine_function; | |
128 | ||
5248c961 RK |
129 | /* Target cpu type */ |
130 | ||
131 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
132 | struct rs6000_cpu_select rs6000_select[3] = |
133 | { | |
815cdc52 MM |
134 | /* switch name, tune arch */ |
135 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
136 | { (const char *)0, "-mcpu=", 1, 1 }, | |
137 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 138 | }; |
5248c961 | 139 | |
ec507f2d DE |
140 | /* Always emit branch hint bits. */ |
141 | static GTY(()) bool rs6000_always_hint; | |
142 | ||
143 | /* Schedule instructions for group formation. */ | |
144 | static GTY(()) bool rs6000_sched_groups; | |
145 | ||
569fa502 DN |
146 | /* Support for -msched-costly-dep option. */ |
147 | const char *rs6000_sched_costly_dep_str; | |
148 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
149 | ||
cbe26ab8 DN |
150 | /* Support for -minsert-sched-nops option. */ |
151 | const char *rs6000_sched_insert_nops_str; | |
152 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
153 | ||
7ccf35ed | 154 | /* Support targetm.vectorize.builtin_mask_for_load. */ |
13c62176 | 155 | static GTY(()) tree altivec_builtin_mask_for_load; |
7ccf35ed | 156 | |
6fa3f289 | 157 | /* Size of long double */ |
6fa3f289 ZW |
158 | int rs6000_long_double_type_size; |
159 | ||
160 | /* Whether -mabi=altivec has appeared */ | |
161 | int rs6000_altivec_abi; | |
162 | ||
a3170dc6 AH |
163 | /* Nonzero if we want SPE ABI extensions. */ |
164 | int rs6000_spe_abi; | |
165 | ||
5da702b1 AH |
166 | /* Nonzero if floating point operations are done in the GPRs. */ |
167 | int rs6000_float_gprs = 0; | |
168 | ||
594a51fe SS |
169 | /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */ |
170 | int rs6000_darwin64_abi; | |
171 | ||
a0ab749a | 172 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 173 | static GTY(()) int common_mode_defined; |
c81bebd7 | 174 | |
9878760c RK |
175 | /* Save information from a "cmpxx" operation until the branch or scc is |
176 | emitted. */ | |
9878760c RK |
177 | rtx rs6000_compare_op0, rs6000_compare_op1; |
178 | int rs6000_compare_fp_p; | |
874a0744 | 179 | |
874a0744 MM |
180 | /* Label number of label created for -mrelocatable, to call to so we can |
181 | get the address of the GOT section */ | |
182 | int rs6000_pic_labelno; | |
c81bebd7 | 183 | |
b91da81f | 184 | #ifdef USING_ELFOS_H |
c81bebd7 | 185 | /* Which abi to adhere to */ |
9739c90c | 186 | const char *rs6000_abi_name; |
d9407988 MM |
187 | |
188 | /* Semantics of the small data area */ | |
189 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
190 | ||
191 | /* Which small data model to use */ | |
815cdc52 | 192 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
193 | |
194 | /* Counter for labels which are to be placed in .fixup. */ | |
195 | int fixuplabelno = 0; | |
874a0744 | 196 | #endif |
4697a36c | 197 | |
c4501e62 JJ |
198 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
199 | int rs6000_tls_size = 32; | |
200 | const char *rs6000_tls_size_string; | |
201 | ||
b6c9286a MM |
202 | /* ABI enumeration available for subtarget to use. */ |
203 | enum rs6000_abi rs6000_current_abi; | |
204 | ||
85b776df AM |
205 | /* Whether to use variant of AIX ABI for PowerPC64 Linux. */ |
206 | int dot_symbols; | |
207 | ||
38c1f2d7 | 208 | /* Debug flags */ |
815cdc52 | 209 | const char *rs6000_debug_name; |
38c1f2d7 MM |
210 | int rs6000_debug_stack; /* debug stack applications */ |
211 | int rs6000_debug_arg; /* debug argument handling */ | |
212 | ||
aabcd309 | 213 | /* Value is TRUE if register/mode pair is acceptable. */ |
0d1fbc8c AH |
214 | bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
215 | ||
58646b77 PB |
216 | /* Built in types. */ |
217 | ||
218 | tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
219 | tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
8bb418a3 | 220 | |
57ac7be9 AM |
221 | const char *rs6000_traceback_name; |
222 | static enum { | |
223 | traceback_default = 0, | |
224 | traceback_none, | |
225 | traceback_part, | |
226 | traceback_full | |
227 | } rs6000_traceback; | |
228 | ||
38c1f2d7 MM |
229 | /* Flag to say the TOC is initialized */ |
230 | int toc_initialized; | |
9ebbca7d | 231 | char toc_label_name[10]; |
38c1f2d7 | 232 | |
d6b5193b RS |
233 | static GTY(()) section *read_only_data_section; |
234 | static GTY(()) section *private_data_section; | |
235 | static GTY(()) section *read_only_private_data_section; | |
236 | static GTY(()) section *sdata2_section; | |
237 | static GTY(()) section *toc_section; | |
238 | ||
a3c9585f KH |
239 | /* Control alignment for fields within structures. */ |
240 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
241 | int rs6000_alignment_flags; |
242 | ||
78f5898b AH |
243 | /* True for any options that were explicitly set. */ |
244 | struct { | |
df01da37 | 245 | bool aix_struct_ret; /* True if -maix-struct-ret was used. */ |
78f5898b AH |
246 | bool alignment; /* True if -malign- was used. */ |
247 | bool abi; /* True if -mabi= was used. */ | |
248 | bool spe; /* True if -mspe= was used. */ | |
249 | bool float_gprs; /* True if -mfloat-gprs= was used. */ | |
250 | bool isel; /* True if -misel was used. */ | |
251 | bool long_double; /* True if -mlong-double- was used. */ | |
252 | } rs6000_explicit_options; | |
253 | ||
a3170dc6 AH |
254 | struct builtin_description |
255 | { | |
256 | /* mask is not const because we're going to alter it below. This | |
257 | nonsense will go away when we rewrite the -march infrastructure | |
258 | to give us more target flag bits. */ | |
259 | unsigned int mask; | |
260 | const enum insn_code icode; | |
261 | const char *const name; | |
262 | const enum rs6000_builtins code; | |
263 | }; | |
8b897cfa RS |
264 | \f |
265 | /* Target cpu costs. */ | |
266 | ||
267 | struct processor_costs { | |
c4ad648e | 268 | const int mulsi; /* cost of SImode multiplication. */ |
8b897cfa RS |
269 | const int mulsi_const; /* cost of SImode multiplication by constant. */ |
270 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
c4ad648e AM |
271 | const int muldi; /* cost of DImode multiplication. */ |
272 | const int divsi; /* cost of SImode division. */ | |
273 | const int divdi; /* cost of DImode division. */ | |
274 | const int fp; /* cost of simple SFmode and DFmode insns. */ | |
275 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
276 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
277 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
8b897cfa RS |
278 | }; |
279 | ||
280 | const struct processor_costs *rs6000_cost; | |
281 | ||
282 | /* Processor costs (relative to an add) */ | |
283 | ||
284 | /* Instruction size costs on 32bit processors. */ | |
285 | static const | |
286 | struct processor_costs size32_cost = { | |
06a67bdd RS |
287 | COSTS_N_INSNS (1), /* mulsi */ |
288 | COSTS_N_INSNS (1), /* mulsi_const */ | |
289 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
290 | COSTS_N_INSNS (1), /* muldi */ | |
291 | COSTS_N_INSNS (1), /* divsi */ | |
292 | COSTS_N_INSNS (1), /* divdi */ | |
293 | COSTS_N_INSNS (1), /* fp */ | |
294 | COSTS_N_INSNS (1), /* dmul */ | |
295 | COSTS_N_INSNS (1), /* sdiv */ | |
296 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
297 | }; |
298 | ||
299 | /* Instruction size costs on 64bit processors. */ | |
300 | static const | |
301 | struct processor_costs size64_cost = { | |
06a67bdd RS |
302 | COSTS_N_INSNS (1), /* mulsi */ |
303 | COSTS_N_INSNS (1), /* mulsi_const */ | |
304 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
305 | COSTS_N_INSNS (1), /* muldi */ | |
306 | COSTS_N_INSNS (1), /* divsi */ | |
307 | COSTS_N_INSNS (1), /* divdi */ | |
308 | COSTS_N_INSNS (1), /* fp */ | |
309 | COSTS_N_INSNS (1), /* dmul */ | |
310 | COSTS_N_INSNS (1), /* sdiv */ | |
311 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
312 | }; |
313 | ||
314 | /* Instruction costs on RIOS1 processors. */ | |
315 | static const | |
316 | struct processor_costs rios1_cost = { | |
06a67bdd RS |
317 | COSTS_N_INSNS (5), /* mulsi */ |
318 | COSTS_N_INSNS (4), /* mulsi_const */ | |
319 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
320 | COSTS_N_INSNS (5), /* muldi */ | |
321 | COSTS_N_INSNS (19), /* divsi */ | |
322 | COSTS_N_INSNS (19), /* divdi */ | |
323 | COSTS_N_INSNS (2), /* fp */ | |
324 | COSTS_N_INSNS (2), /* dmul */ | |
325 | COSTS_N_INSNS (19), /* sdiv */ | |
326 | COSTS_N_INSNS (19), /* ddiv */ | |
8b897cfa RS |
327 | }; |
328 | ||
329 | /* Instruction costs on RIOS2 processors. */ | |
330 | static const | |
331 | struct processor_costs rios2_cost = { | |
06a67bdd RS |
332 | COSTS_N_INSNS (2), /* mulsi */ |
333 | COSTS_N_INSNS (2), /* mulsi_const */ | |
334 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
335 | COSTS_N_INSNS (2), /* muldi */ | |
336 | COSTS_N_INSNS (13), /* divsi */ | |
337 | COSTS_N_INSNS (13), /* divdi */ | |
338 | COSTS_N_INSNS (2), /* fp */ | |
339 | COSTS_N_INSNS (2), /* dmul */ | |
340 | COSTS_N_INSNS (17), /* sdiv */ | |
341 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
342 | }; |
343 | ||
344 | /* Instruction costs on RS64A processors. */ | |
345 | static const | |
346 | struct processor_costs rs64a_cost = { | |
06a67bdd RS |
347 | COSTS_N_INSNS (20), /* mulsi */ |
348 | COSTS_N_INSNS (12), /* mulsi_const */ | |
349 | COSTS_N_INSNS (8), /* mulsi_const9 */ | |
350 | COSTS_N_INSNS (34), /* muldi */ | |
351 | COSTS_N_INSNS (65), /* divsi */ | |
352 | COSTS_N_INSNS (67), /* divdi */ | |
353 | COSTS_N_INSNS (4), /* fp */ | |
354 | COSTS_N_INSNS (4), /* dmul */ | |
355 | COSTS_N_INSNS (31), /* sdiv */ | |
356 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
357 | }; |
358 | ||
359 | /* Instruction costs on MPCCORE processors. */ | |
360 | static const | |
361 | struct processor_costs mpccore_cost = { | |
06a67bdd RS |
362 | COSTS_N_INSNS (2), /* mulsi */ |
363 | COSTS_N_INSNS (2), /* mulsi_const */ | |
364 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
365 | COSTS_N_INSNS (2), /* muldi */ | |
366 | COSTS_N_INSNS (6), /* divsi */ | |
367 | COSTS_N_INSNS (6), /* divdi */ | |
368 | COSTS_N_INSNS (4), /* fp */ | |
369 | COSTS_N_INSNS (5), /* dmul */ | |
370 | COSTS_N_INSNS (10), /* sdiv */ | |
371 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
372 | }; |
373 | ||
374 | /* Instruction costs on PPC403 processors. */ | |
375 | static const | |
376 | struct processor_costs ppc403_cost = { | |
06a67bdd RS |
377 | COSTS_N_INSNS (4), /* mulsi */ |
378 | COSTS_N_INSNS (4), /* mulsi_const */ | |
379 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
380 | COSTS_N_INSNS (4), /* muldi */ | |
381 | COSTS_N_INSNS (33), /* divsi */ | |
382 | COSTS_N_INSNS (33), /* divdi */ | |
383 | COSTS_N_INSNS (11), /* fp */ | |
384 | COSTS_N_INSNS (11), /* dmul */ | |
385 | COSTS_N_INSNS (11), /* sdiv */ | |
386 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
387 | }; |
388 | ||
389 | /* Instruction costs on PPC405 processors. */ | |
390 | static const | |
391 | struct processor_costs ppc405_cost = { | |
06a67bdd RS |
392 | COSTS_N_INSNS (5), /* mulsi */ |
393 | COSTS_N_INSNS (4), /* mulsi_const */ | |
394 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
395 | COSTS_N_INSNS (5), /* muldi */ | |
396 | COSTS_N_INSNS (35), /* divsi */ | |
397 | COSTS_N_INSNS (35), /* divdi */ | |
398 | COSTS_N_INSNS (11), /* fp */ | |
399 | COSTS_N_INSNS (11), /* dmul */ | |
400 | COSTS_N_INSNS (11), /* sdiv */ | |
401 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
402 | }; |
403 | ||
404 | /* Instruction costs on PPC440 processors. */ | |
405 | static const | |
406 | struct processor_costs ppc440_cost = { | |
06a67bdd RS |
407 | COSTS_N_INSNS (3), /* mulsi */ |
408 | COSTS_N_INSNS (2), /* mulsi_const */ | |
409 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
410 | COSTS_N_INSNS (3), /* muldi */ | |
411 | COSTS_N_INSNS (34), /* divsi */ | |
412 | COSTS_N_INSNS (34), /* divdi */ | |
413 | COSTS_N_INSNS (5), /* fp */ | |
414 | COSTS_N_INSNS (5), /* dmul */ | |
415 | COSTS_N_INSNS (19), /* sdiv */ | |
416 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
417 | }; |
418 | ||
419 | /* Instruction costs on PPC601 processors. */ | |
420 | static const | |
421 | struct processor_costs ppc601_cost = { | |
06a67bdd RS |
422 | COSTS_N_INSNS (5), /* mulsi */ |
423 | COSTS_N_INSNS (5), /* mulsi_const */ | |
424 | COSTS_N_INSNS (5), /* mulsi_const9 */ | |
425 | COSTS_N_INSNS (5), /* muldi */ | |
426 | COSTS_N_INSNS (36), /* divsi */ | |
427 | COSTS_N_INSNS (36), /* divdi */ | |
428 | COSTS_N_INSNS (4), /* fp */ | |
429 | COSTS_N_INSNS (5), /* dmul */ | |
430 | COSTS_N_INSNS (17), /* sdiv */ | |
431 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
432 | }; |
433 | ||
434 | /* Instruction costs on PPC603 processors. */ | |
435 | static const | |
436 | struct processor_costs ppc603_cost = { | |
06a67bdd RS |
437 | COSTS_N_INSNS (5), /* mulsi */ |
438 | COSTS_N_INSNS (3), /* mulsi_const */ | |
439 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
440 | COSTS_N_INSNS (5), /* muldi */ | |
441 | COSTS_N_INSNS (37), /* divsi */ | |
442 | COSTS_N_INSNS (37), /* divdi */ | |
443 | COSTS_N_INSNS (3), /* fp */ | |
444 | COSTS_N_INSNS (4), /* dmul */ | |
445 | COSTS_N_INSNS (18), /* sdiv */ | |
446 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
447 | }; |
448 | ||
449 | /* Instruction costs on PPC604 processors. */ | |
450 | static const | |
451 | struct processor_costs ppc604_cost = { | |
06a67bdd RS |
452 | COSTS_N_INSNS (4), /* mulsi */ |
453 | COSTS_N_INSNS (4), /* mulsi_const */ | |
454 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
455 | COSTS_N_INSNS (4), /* muldi */ | |
456 | COSTS_N_INSNS (20), /* divsi */ | |
457 | COSTS_N_INSNS (20), /* divdi */ | |
458 | COSTS_N_INSNS (3), /* fp */ | |
459 | COSTS_N_INSNS (3), /* dmul */ | |
460 | COSTS_N_INSNS (18), /* sdiv */ | |
461 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
462 | }; |
463 | ||
464 | /* Instruction costs on PPC604e processors. */ | |
465 | static const | |
466 | struct processor_costs ppc604e_cost = { | |
06a67bdd RS |
467 | COSTS_N_INSNS (2), /* mulsi */ |
468 | COSTS_N_INSNS (2), /* mulsi_const */ | |
469 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
470 | COSTS_N_INSNS (2), /* muldi */ | |
471 | COSTS_N_INSNS (20), /* divsi */ | |
472 | COSTS_N_INSNS (20), /* divdi */ | |
473 | COSTS_N_INSNS (3), /* fp */ | |
474 | COSTS_N_INSNS (3), /* dmul */ | |
475 | COSTS_N_INSNS (18), /* sdiv */ | |
476 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
477 | }; |
478 | ||
f0517163 | 479 | /* Instruction costs on PPC620 processors. */ |
8b897cfa RS |
480 | static const |
481 | struct processor_costs ppc620_cost = { | |
06a67bdd RS |
482 | COSTS_N_INSNS (5), /* mulsi */ |
483 | COSTS_N_INSNS (4), /* mulsi_const */ | |
484 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
485 | COSTS_N_INSNS (7), /* muldi */ | |
486 | COSTS_N_INSNS (21), /* divsi */ | |
487 | COSTS_N_INSNS (37), /* divdi */ | |
488 | COSTS_N_INSNS (3), /* fp */ | |
489 | COSTS_N_INSNS (3), /* dmul */ | |
490 | COSTS_N_INSNS (18), /* sdiv */ | |
491 | COSTS_N_INSNS (32), /* ddiv */ | |
f0517163 RS |
492 | }; |
493 | ||
494 | /* Instruction costs on PPC630 processors. */ | |
495 | static const | |
496 | struct processor_costs ppc630_cost = { | |
06a67bdd RS |
497 | COSTS_N_INSNS (5), /* mulsi */ |
498 | COSTS_N_INSNS (4), /* mulsi_const */ | |
499 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
500 | COSTS_N_INSNS (7), /* muldi */ | |
501 | COSTS_N_INSNS (21), /* divsi */ | |
502 | COSTS_N_INSNS (37), /* divdi */ | |
503 | COSTS_N_INSNS (3), /* fp */ | |
504 | COSTS_N_INSNS (3), /* dmul */ | |
505 | COSTS_N_INSNS (17), /* sdiv */ | |
506 | COSTS_N_INSNS (21), /* ddiv */ | |
8b897cfa RS |
507 | }; |
508 | ||
509 | /* Instruction costs on PPC750 and PPC7400 processors. */ | |
510 | static const | |
511 | struct processor_costs ppc750_cost = { | |
06a67bdd RS |
512 | COSTS_N_INSNS (5), /* mulsi */ |
513 | COSTS_N_INSNS (3), /* mulsi_const */ | |
514 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
515 | COSTS_N_INSNS (5), /* muldi */ | |
516 | COSTS_N_INSNS (17), /* divsi */ | |
517 | COSTS_N_INSNS (17), /* divdi */ | |
518 | COSTS_N_INSNS (3), /* fp */ | |
519 | COSTS_N_INSNS (3), /* dmul */ | |
520 | COSTS_N_INSNS (17), /* sdiv */ | |
521 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
522 | }; |
523 | ||
524 | /* Instruction costs on PPC7450 processors. */ | |
525 | static const | |
526 | struct processor_costs ppc7450_cost = { | |
06a67bdd RS |
527 | COSTS_N_INSNS (4), /* mulsi */ |
528 | COSTS_N_INSNS (3), /* mulsi_const */ | |
529 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
530 | COSTS_N_INSNS (4), /* muldi */ | |
531 | COSTS_N_INSNS (23), /* divsi */ | |
532 | COSTS_N_INSNS (23), /* divdi */ | |
533 | COSTS_N_INSNS (5), /* fp */ | |
534 | COSTS_N_INSNS (5), /* dmul */ | |
535 | COSTS_N_INSNS (21), /* sdiv */ | |
536 | COSTS_N_INSNS (35), /* ddiv */ | |
8b897cfa | 537 | }; |
a3170dc6 | 538 | |
8b897cfa RS |
539 | /* Instruction costs on PPC8540 processors. */ |
540 | static const | |
541 | struct processor_costs ppc8540_cost = { | |
06a67bdd RS |
542 | COSTS_N_INSNS (4), /* mulsi */ |
543 | COSTS_N_INSNS (4), /* mulsi_const */ | |
544 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
545 | COSTS_N_INSNS (4), /* muldi */ | |
546 | COSTS_N_INSNS (19), /* divsi */ | |
547 | COSTS_N_INSNS (19), /* divdi */ | |
548 | COSTS_N_INSNS (4), /* fp */ | |
549 | COSTS_N_INSNS (4), /* dmul */ | |
550 | COSTS_N_INSNS (29), /* sdiv */ | |
551 | COSTS_N_INSNS (29), /* ddiv */ | |
8b897cfa RS |
552 | }; |
553 | ||
554 | /* Instruction costs on POWER4 and POWER5 processors. */ | |
555 | static const | |
556 | struct processor_costs power4_cost = { | |
06a67bdd RS |
557 | COSTS_N_INSNS (3), /* mulsi */ |
558 | COSTS_N_INSNS (2), /* mulsi_const */ | |
559 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
560 | COSTS_N_INSNS (4), /* muldi */ | |
561 | COSTS_N_INSNS (18), /* divsi */ | |
562 | COSTS_N_INSNS (34), /* divdi */ | |
563 | COSTS_N_INSNS (3), /* fp */ | |
564 | COSTS_N_INSNS (3), /* dmul */ | |
565 | COSTS_N_INSNS (17), /* sdiv */ | |
566 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
567 | }; |
568 | ||
569 | \f | |
a2369ed3 | 570 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
2ffa9a0c | 571 | static const char *rs6000_invalid_within_doloop (rtx); |
a2369ed3 DJ |
572 | static rtx rs6000_generate_compare (enum rtx_code); |
573 | static void rs6000_maybe_dead (rtx); | |
574 | static void rs6000_emit_stack_tie (void); | |
575 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
576 | static rtx spe_synthesize_frame_save (rtx); | |
577 | static bool spe_func_has_64bit_regs_p (void); | |
b20a9cca | 578 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 579 | int, HOST_WIDE_INT); |
a2369ed3 DJ |
580 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
581 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); | |
582 | static unsigned rs6000_hash_constant (rtx); | |
583 | static unsigned toc_hash_function (const void *); | |
584 | static int toc_hash_eq (const void *, const void *); | |
585 | static int constant_pool_expr_1 (rtx, int *, int *); | |
586 | static bool constant_pool_expr_p (rtx); | |
a2369ed3 | 587 | static bool legitimate_indexed_address_p (rtx, int); |
a2369ed3 DJ |
588 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
589 | static struct machine_function * rs6000_init_machine_status (void); | |
590 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
6d0a8091 | 591 | static bool no_global_regs_above (int); |
5add3202 | 592 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 593 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 594 | #endif |
a2369ed3 DJ |
595 | static int rs6000_ra_ever_killed (void); |
596 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
8bb418a3 | 597 | static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); |
76d2b81d | 598 | static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); |
f18eca82 | 599 | static const char *rs6000_mangle_fundamental_type (tree); |
b86fe7b4 | 600 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 DJ |
601 | static void rs6000_set_default_type_attributes (tree); |
602 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); | |
603 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
604 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
605 | tree); | |
a2369ed3 | 606 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
c6e8c921 | 607 | static bool rs6000_return_in_memory (tree, tree); |
a2369ed3 | 608 | static void rs6000_file_start (void); |
7c262518 | 609 | #if TARGET_ELF |
a2369ed3 DJ |
610 | static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); |
611 | static void rs6000_elf_asm_out_constructor (rtx, int); | |
612 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
1334b570 | 613 | static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED; |
d6b5193b RS |
614 | static void rs6000_elf_asm_init_sections (void); |
615 | static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); | |
a2369ed3 | 616 | static void rs6000_elf_unique_section (tree, int); |
d6b5193b RS |
617 | static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx, |
618 | unsigned HOST_WIDE_INT); | |
a56d7372 | 619 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 620 | ATTRIBUTE_UNUSED; |
7c262518 | 621 | #endif |
cbaaba19 | 622 | #if TARGET_XCOFF |
a2369ed3 | 623 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
d6b5193b | 624 | static void rs6000_xcoff_asm_init_sections (void); |
8210e4c4 | 625 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree); |
d6b5193b | 626 | static section *rs6000_xcoff_select_section (tree, int, |
b20a9cca | 627 | unsigned HOST_WIDE_INT); |
d6b5193b RS |
628 | static void rs6000_xcoff_unique_section (tree, int); |
629 | static section *rs6000_xcoff_select_rtx_section | |
630 | (enum machine_mode, rtx, unsigned HOST_WIDE_INT); | |
a2369ed3 DJ |
631 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
632 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
633 | static void rs6000_xcoff_file_start (void); | |
634 | static void rs6000_xcoff_file_end (void); | |
f1384257 | 635 | #endif |
a2369ed3 DJ |
636 | static int rs6000_variable_issue (FILE *, int, rtx, int); |
637 | static bool rs6000_rtx_costs (rtx, int, int, int *); | |
638 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); | |
cbe26ab8 | 639 | static bool is_microcoded_insn (rtx); |
79ae11c4 | 640 | static int is_dispatch_slot_restricted (rtx); |
cbe26ab8 DN |
641 | static bool is_cracked_insn (rtx); |
642 | static bool is_branch_slot_insn (rtx); | |
a2369ed3 DJ |
643 | static int rs6000_adjust_priority (rtx, int); |
644 | static int rs6000_issue_rate (void); | |
569fa502 | 645 | static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); |
cbe26ab8 DN |
646 | static rtx get_next_active_insn (rtx, rtx); |
647 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
648 | static bool is_costly_group (rtx *, rtx); | |
649 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
650 | static int redefine_groups (FILE *, int, rtx, rtx); | |
651 | static int pad_groups (FILE *, int, rtx, rtx); | |
652 | static void rs6000_sched_finish (FILE *, int); | |
a2369ed3 | 653 | static int rs6000_use_sched_lookahead (void); |
7ccf35ed | 654 | static tree rs6000_builtin_mask_for_load (void); |
a2369ed3 | 655 | |
58646b77 | 656 | static void def_builtin (int, const char *, tree, int); |
a2369ed3 DJ |
657 | static void rs6000_init_builtins (void); |
658 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
659 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
660 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
661 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
662 | static void altivec_init_builtins (void); | |
663 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 664 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 665 | |
b20a9cca AM |
666 | static void enable_mask_for_builtins (struct builtin_description *, int, |
667 | enum rs6000_builtins, | |
668 | enum rs6000_builtins); | |
7c62e993 | 669 | static tree build_opaque_vector_type (tree, int); |
a2369ed3 DJ |
670 | static void spe_init_builtins (void); |
671 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
61bea3b0 | 672 | static rtx spe_expand_stv_builtin (enum insn_code, tree); |
a2369ed3 DJ |
673 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); |
674 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
675 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
676 | static rs6000_stack_t *rs6000_stack_info (void); |
677 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
678 | |
679 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
680 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
681 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
682 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
683 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
f676971a | 684 | static rtx altivec_expand_predicate_builtin (enum insn_code, |
c4ad648e | 685 | const char *, tree, rtx); |
b4a62fa0 | 686 | static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); |
a2369ed3 | 687 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
7a4eca66 DE |
688 | static rtx altivec_expand_vec_init_builtin (tree, tree, rtx); |
689 | static rtx altivec_expand_vec_set_builtin (tree); | |
690 | static rtx altivec_expand_vec_ext_builtin (tree, rtx); | |
691 | static int get_element_number (tree, tree); | |
78f5898b | 692 | static bool rs6000_handle_option (size_t, const char *, int); |
a2369ed3 | 693 | static void rs6000_parse_tls_size_option (void); |
5da702b1 | 694 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
a2369ed3 DJ |
695 | static int first_altivec_reg_to_save (void); |
696 | static unsigned int compute_vrsave_mask (void); | |
9390387d | 697 | static void compute_save_world_info (rs6000_stack_t *info_ptr); |
a2369ed3 DJ |
698 | static void is_altivec_return_reg (rtx, void *); |
699 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
700 | int easy_vector_constant (rtx, enum machine_mode); | |
58646b77 | 701 | static bool rs6000_is_opaque_type (tree); |
a2369ed3 DJ |
702 | static rtx rs6000_dwarf_register_span (rtx); |
703 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); | |
fdbe66f2 | 704 | static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
a2369ed3 DJ |
705 | static rtx rs6000_tls_get_addr (void); |
706 | static rtx rs6000_got_sym (void); | |
9390387d | 707 | static int rs6000_tls_symbol_ref_1 (rtx *, void *); |
a2369ed3 DJ |
708 | static const char *rs6000_get_some_local_dynamic_name (void); |
709 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 710 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 711 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 712 | enum machine_mode, tree); |
0b5383eb DJ |
713 | static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *, |
714 | HOST_WIDE_INT); | |
715 | static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *, | |
716 | tree, HOST_WIDE_INT); | |
717 | static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *, | |
718 | HOST_WIDE_INT, | |
719 | rtx[], int *); | |
720 | static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *, | |
721 | tree, HOST_WIDE_INT, | |
722 | rtx[], int *); | |
723 | static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool); | |
ec6376ab | 724 | static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); |
b1917422 | 725 | static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); |
c6e8c921 GK |
726 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
727 | enum machine_mode, tree, | |
728 | int *, int); | |
8cd5a4e0 RH |
729 | static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
730 | tree, bool); | |
78a52f11 RH |
731 | static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
732 | tree, bool); | |
4d3e6fae | 733 | static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree); |
efdba735 SH |
734 | #if TARGET_MACHO |
735 | static void macho_branch_islands (void); | |
736 | static void add_compiler_branch_island (tree, tree, int); | |
737 | static int no_previous_def (tree function_name); | |
738 | static tree get_prev_label (tree function_name); | |
c4e18b1c | 739 | static void rs6000_darwin_file_start (void); |
efdba735 SH |
740 | #endif |
741 | ||
c35d187f | 742 | static tree rs6000_build_builtin_va_list (void); |
23a60a04 | 743 | static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); |
fe984136 | 744 | static bool rs6000_must_pass_in_stack (enum machine_mode, tree); |
f676971a | 745 | static bool rs6000_vector_mode_supported_p (enum machine_mode); |
94ff898d | 746 | static int get_vec_cmp_insn (enum rtx_code, enum machine_mode, |
21213b4c | 747 | enum machine_mode); |
94ff898d | 748 | static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx, |
21213b4c DP |
749 | enum machine_mode); |
750 | static int get_vsel_insn (enum machine_mode); | |
751 | static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx); | |
3aebbe5f | 752 | static tree rs6000_stack_protect_fail (void); |
21213b4c DP |
753 | |
754 | const int INSN_NOT_AVAILABLE = -1; | |
93f90be6 FJ |
755 | static enum machine_mode rs6000_eh_return_filter_mode (void); |
756 | ||
17211ab5 GK |
757 | /* Hash table stuff for keeping track of TOC entries. */ |
758 | ||
759 | struct toc_hash_struct GTY(()) | |
760 | { | |
761 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
762 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
763 | rtx key; | |
764 | enum machine_mode key_mode; | |
765 | int labelno; | |
766 | }; | |
767 | ||
768 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
769 | \f |
770 | /* Default register names. */ | |
771 | char rs6000_reg_names[][8] = | |
772 | { | |
802a0058 MM |
773 | "0", "1", "2", "3", "4", "5", "6", "7", |
774 | "8", "9", "10", "11", "12", "13", "14", "15", | |
775 | "16", "17", "18", "19", "20", "21", "22", "23", | |
776 | "24", "25", "26", "27", "28", "29", "30", "31", | |
777 | "0", "1", "2", "3", "4", "5", "6", "7", | |
778 | "8", "9", "10", "11", "12", "13", "14", "15", | |
779 | "16", "17", "18", "19", "20", "21", "22", "23", | |
780 | "24", "25", "26", "27", "28", "29", "30", "31", | |
781 | "mq", "lr", "ctr","ap", | |
782 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
783 | "xer", |
784 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
785 | "0", "1", "2", "3", "4", "5", "6", "7", |
786 | "8", "9", "10", "11", "12", "13", "14", "15", | |
787 | "16", "17", "18", "19", "20", "21", "22", "23", | |
788 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
789 | "vrsave", "vscr", |
790 | /* SPE registers. */ | |
7d5175e1 JJ |
791 | "spe_acc", "spefscr", |
792 | /* Soft frame pointer. */ | |
793 | "sfp" | |
c81bebd7 MM |
794 | }; |
795 | ||
796 | #ifdef TARGET_REGNAMES | |
8b60264b | 797 | static const char alt_reg_names[][8] = |
c81bebd7 | 798 | { |
802a0058 MM |
799 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
800 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
801 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
802 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
803 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
804 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
805 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
806 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
807 | "mq", "lr", "ctr", "ap", | |
808 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 809 | "xer", |
59a4c851 | 810 | /* AltiVec registers. */ |
0ac081f6 | 811 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
812 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
813 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
814 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
815 | "vrsave", "vscr", | |
816 | /* SPE registers. */ | |
7d5175e1 JJ |
817 | "spe_acc", "spefscr", |
818 | /* Soft frame pointer. */ | |
819 | "sfp" | |
c81bebd7 MM |
820 | }; |
821 | #endif | |
9878760c | 822 | \f |
daf11973 MM |
823 | #ifndef MASK_STRICT_ALIGN |
824 | #define MASK_STRICT_ALIGN 0 | |
825 | #endif | |
ffcfcb5f AM |
826 | #ifndef TARGET_PROFILE_KERNEL |
827 | #define TARGET_PROFILE_KERNEL 0 | |
828 | #endif | |
3961e8fe RH |
829 | |
830 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
831 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
672a6f42 NB |
832 | \f |
833 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
834 | #undef TARGET_ATTRIBUTE_TABLE |
835 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
836 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
837 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 838 | |
301d03af RS |
839 | #undef TARGET_ASM_ALIGNED_DI_OP |
840 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
841 | ||
842 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
843 | for non-ELF systems. */ | |
844 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 845 | #if TARGET_XCOFF |
ae6c1efd | 846 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
847 | 64-bit targets. */ |
848 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
849 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
850 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
851 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
852 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
853 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
854 | #else | |
855 | /* For Darwin. */ | |
856 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
857 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
858 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
859 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
49bd1d27 SS |
860 | #undef TARGET_ASM_UNALIGNED_DI_OP |
861 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t" | |
862 | #undef TARGET_ASM_ALIGNED_DI_OP | |
863 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
301d03af RS |
864 | #endif |
865 | #endif | |
866 | ||
867 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
868 | in 64-bit code. */ | |
869 | #undef TARGET_ASM_INTEGER | |
870 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
871 | ||
93638d7a AM |
872 | #ifdef HAVE_GAS_HIDDEN |
873 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
874 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
875 | #endif | |
876 | ||
c4501e62 JJ |
877 | #undef TARGET_HAVE_TLS |
878 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
879 | ||
880 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
a7e0b075 | 881 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p |
c4501e62 | 882 | |
08c148a8 NB |
883 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
884 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
885 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
886 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
887 | ||
b54cf83a DE |
888 | #undef TARGET_SCHED_VARIABLE_ISSUE |
889 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
890 | ||
c237e94a ZW |
891 | #undef TARGET_SCHED_ISSUE_RATE |
892 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
893 | #undef TARGET_SCHED_ADJUST_COST | |
894 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
895 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
896 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
f676971a | 897 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
569fa502 | 898 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence |
cbe26ab8 DN |
899 | #undef TARGET_SCHED_FINISH |
900 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
c237e94a | 901 | |
be12c2b0 VM |
902 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
903 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
904 | ||
7ccf35ed DN |
905 | #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD |
906 | #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load | |
907 | ||
0ac081f6 AH |
908 | #undef TARGET_INIT_BUILTINS |
909 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
910 | ||
911 | #undef TARGET_EXPAND_BUILTIN | |
912 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
913 | ||
f18eca82 ZL |
914 | #undef TARGET_MANGLE_FUNDAMENTAL_TYPE |
915 | #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type | |
916 | ||
c15c90bb ZW |
917 | #undef TARGET_INIT_LIBFUNCS |
918 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
919 | ||
f1384257 | 920 | #if TARGET_MACHO |
0e5dbd9b | 921 | #undef TARGET_BINDS_LOCAL_P |
31920d83 | 922 | #define TARGET_BINDS_LOCAL_P darwin_binds_local_p |
f1384257 | 923 | #endif |
0e5dbd9b | 924 | |
3961e8fe RH |
925 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
926 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
927 | ||
3961e8fe | 928 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 929 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 930 | |
4977bab6 ZW |
931 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
932 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
933 | ||
2e3f0db6 DJ |
934 | #undef TARGET_INVALID_WITHIN_DOLOOP |
935 | #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop | |
9419649c | 936 | |
3c50106f RH |
937 | #undef TARGET_RTX_COSTS |
938 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
939 | #undef TARGET_ADDRESS_COST |
940 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 941 | |
c8e4f0e9 | 942 | #undef TARGET_VECTOR_OPAQUE_P |
58646b77 | 943 | #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type |
62e1dfcf | 944 | |
96714395 AH |
945 | #undef TARGET_DWARF_REGISTER_SPAN |
946 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
947 | ||
c6e8c921 GK |
948 | /* On rs6000, function arguments are promoted, as are function return |
949 | values. */ | |
950 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
951 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
952 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
953 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
954 | ||
c6e8c921 GK |
955 | #undef TARGET_RETURN_IN_MEMORY |
956 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
957 | ||
958 | #undef TARGET_SETUP_INCOMING_VARARGS | |
959 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
960 | ||
961 | /* Always strict argument naming on rs6000. */ | |
962 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
963 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
964 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
965 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
42ba5130 RH |
966 | #undef TARGET_SPLIT_COMPLEX_ARG |
967 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true | |
fe984136 RH |
968 | #undef TARGET_MUST_PASS_IN_STACK |
969 | #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack | |
8cd5a4e0 RH |
970 | #undef TARGET_PASS_BY_REFERENCE |
971 | #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference | |
78a52f11 RH |
972 | #undef TARGET_ARG_PARTIAL_BYTES |
973 | #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes | |
c6e8c921 | 974 | |
c35d187f RH |
975 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
976 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
977 | ||
cd3ce9b4 JM |
978 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
979 | #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg | |
980 | ||
93f90be6 FJ |
981 | #undef TARGET_EH_RETURN_FILTER_MODE |
982 | #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode | |
983 | ||
f676971a EC |
984 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
985 | #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p | |
986 | ||
4d3e6fae FJ |
987 | #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN |
988 | #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn | |
989 | ||
78f5898b AH |
990 | #undef TARGET_HANDLE_OPTION |
991 | #define TARGET_HANDLE_OPTION rs6000_handle_option | |
992 | ||
993 | #undef TARGET_DEFAULT_TARGET_FLAGS | |
994 | #define TARGET_DEFAULT_TARGET_FLAGS \ | |
995 | (TARGET_DEFAULT | MASK_SCHED_PROLOG) | |
996 | ||
3aebbe5f JJ |
997 | #undef TARGET_STACK_PROTECT_FAIL |
998 | #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail | |
999 | ||
445cf5eb JM |
1000 | /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors |
1001 | The PowerPC architecture requires only weak consistency among | |
1002 | processors--that is, memory accesses between processors need not be | |
1003 | sequentially consistent and memory accesses among processors can occur | |
1004 | in any order. The ability to order memory accesses weakly provides | |
1005 | opportunities for more efficient use of the system bus. Unless a | |
1006 | dependency exists, the 604e allows read operations to precede store | |
1007 | operations. */ | |
1008 | #undef TARGET_RELAXED_ORDERING | |
1009 | #define TARGET_RELAXED_ORDERING true | |
1010 | ||
fdbe66f2 EB |
1011 | #ifdef HAVE_AS_TLS |
1012 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
1013 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel | |
1014 | #endif | |
1015 | ||
f6897b10 | 1016 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 1017 | \f |
0d1fbc8c AH |
1018 | |
1019 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
1020 | MODE. */ | |
1021 | static int | |
1022 | rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
1023 | { | |
1024 | /* The GPRs can hold any mode, but values bigger than one register | |
1025 | cannot go past R31. */ | |
1026 | if (INT_REGNO_P (regno)) | |
1027 | return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); | |
1028 | ||
1029 | /* The float registers can only hold floating modes and DImode. */ | |
1030 | if (FP_REGNO_P (regno)) | |
1031 | return | |
ebb109ad | 1032 | (SCALAR_FLOAT_MODE_P (mode) |
0d1fbc8c AH |
1033 | && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) |
1034 | || (GET_MODE_CLASS (mode) == MODE_INT | |
1035 | && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD); | |
1036 | ||
1037 | /* The CR register can only hold CC modes. */ | |
1038 | if (CR_REGNO_P (regno)) | |
1039 | return GET_MODE_CLASS (mode) == MODE_CC; | |
1040 | ||
1041 | if (XER_REGNO_P (regno)) | |
1042 | return mode == PSImode; | |
1043 | ||
1044 | /* AltiVec only in AldyVec registers. */ | |
1045 | if (ALTIVEC_REGNO_P (regno)) | |
1046 | return ALTIVEC_VECTOR_MODE (mode); | |
1047 | ||
1048 | /* ...but GPRs can hold SIMD data on the SPE in one register. */ | |
1049 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
1050 | return 1; | |
1051 | ||
1052 | /* We cannot put TImode anywhere except general register and it must be | |
1053 | able to fit within the register set. */ | |
1054 | ||
1055 | return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; | |
1056 | } | |
1057 | ||
1058 | /* Initialize rs6000_hard_regno_mode_ok_p table. */ | |
1059 | static void | |
1060 | rs6000_init_hard_regno_mode_ok (void) | |
1061 | { | |
1062 | int r, m; | |
1063 | ||
1064 | for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) | |
1065 | for (m = 0; m < NUM_MACHINE_MODES; ++m) | |
1066 | if (rs6000_hard_regno_mode_ok (r, m)) | |
1067 | rs6000_hard_regno_mode_ok_p[m][r] = true; | |
1068 | } | |
1069 | ||
c1e55850 GK |
1070 | /* If not otherwise specified by a target, make 'long double' equivalent to |
1071 | 'double'. */ | |
1072 | ||
1073 | #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE | |
1074 | #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 | |
1075 | #endif | |
1076 | ||
5248c961 RK |
1077 | /* Override command line options. Mostly we process the processor |
1078 | type and sometimes adjust other TARGET_ options. */ | |
1079 | ||
1080 | void | |
d779d0dc | 1081 | rs6000_override_options (const char *default_cpu) |
5248c961 | 1082 | { |
c4d38ccb | 1083 | size_t i, j; |
8e3f41e7 | 1084 | struct rs6000_cpu_select *ptr; |
66188a7e | 1085 | int set_masks; |
5248c961 | 1086 | |
66188a7e | 1087 | /* Simplifications for entries below. */ |
85638c0d | 1088 | |
66188a7e GK |
1089 | enum { |
1090 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
1091 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
1092 | }; | |
85638c0d | 1093 | |
66188a7e GK |
1094 | /* This table occasionally claims that a processor does not support |
1095 | a particular feature even though it does, but the feature is slower | |
1096 | than the alternative. Thus, it shouldn't be relied on as a | |
f676971a | 1097 | complete description of the processor's support. |
66188a7e GK |
1098 | |
1099 | Please keep this list in order, and don't forget to update the | |
1100 | documentation in invoke.texi when adding a new processor or | |
1101 | flag. */ | |
5248c961 RK |
1102 | static struct ptt |
1103 | { | |
8b60264b KG |
1104 | const char *const name; /* Canonical processor name. */ |
1105 | const enum processor_type processor; /* Processor type enum value. */ | |
1106 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 1107 | } const processor_target_table[] |
66188a7e | 1108 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 1109 | {"403", PROCESSOR_PPC403, |
66188a7e | 1110 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
131aeb82 JM |
1111 | {"405", PROCESSOR_PPC405, |
1112 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW}, | |
1113 | {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_MULHW}, | |
1114 | {"440", PROCESSOR_PPC440, | |
1115 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW}, | |
1116 | {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_MULHW}, | |
66188a7e | 1117 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, |
5248c961 | 1118 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
1119 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
1120 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1121 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1122 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1123 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1124 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
1125 | {"620", PROCESSOR_PPC620, |
1126 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1127 | {"630", PROCESSOR_PPC630, | |
1128 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
1129 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
1130 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
1131 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
1132 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1133 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1134 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1135 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1136 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
4d4cbc0e AH |
1137 | /* 8548 has a dummy entry for now. */ |
1138 | {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
66188a7e | 1139 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
7177e720 | 1140 | {"970", PROCESSOR_POWER4, |
66188a7e GK |
1141 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1142 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, | |
1143 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1144 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1145 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 1146 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
1147 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1148 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1149 | {"power2", PROCESSOR_POWER, | |
1150 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
1151 | {"power3", PROCESSOR_PPC630, |
1152 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1153 | {"power4", PROCESSOR_POWER4, | |
fc091c8e | 1154 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
ec507f2d | 1155 | {"power5", PROCESSOR_POWER5, |
432218ba DE |
1156 | POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT |
1157 | | MASK_MFCRF | MASK_POPCNTB}, | |
9719f3b7 DE |
1158 | {"power5+", PROCESSOR_POWER5, |
1159 | POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT | |
1160 | | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND}, | |
66188a7e GK |
1161 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
1162 | {"powerpc64", PROCESSOR_POWERPC64, | |
98c41d98 | 1163 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, |
66188a7e GK |
1164 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, |
1165 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1166 | {"rios2", PROCESSOR_RIOS2, | |
1167 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
1168 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1169 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
98c41d98 DE |
1170 | {"rs64", PROCESSOR_RS64A, |
1171 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64} | |
66188a7e | 1172 | }; |
5248c961 | 1173 | |
ca7558fc | 1174 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 1175 | |
66188a7e GK |
1176 | /* Some OSs don't support saving the high part of 64-bit registers on |
1177 | context switch. Other OSs don't support saving Altivec registers. | |
1178 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
1179 | settings; if the user wants either, the user must explicitly specify | |
1180 | them and we won't interfere with the user's specification. */ | |
1181 | ||
1182 | enum { | |
1183 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
f676971a | 1184 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT |
66188a7e | 1185 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC |
131aeb82 | 1186 | | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW) |
66188a7e | 1187 | }; |
0d1fbc8c AH |
1188 | |
1189 | rs6000_init_hard_regno_mode_ok (); | |
1190 | ||
c4ad648e | 1191 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; |
66188a7e GK |
1192 | #ifdef OS_MISSING_POWERPC64 |
1193 | if (OS_MISSING_POWERPC64) | |
1194 | set_masks &= ~MASK_POWERPC64; | |
1195 | #endif | |
1196 | #ifdef OS_MISSING_ALTIVEC | |
1197 | if (OS_MISSING_ALTIVEC) | |
1198 | set_masks &= ~MASK_ALTIVEC; | |
1199 | #endif | |
1200 | ||
768875a8 AM |
1201 | /* Don't override by the processor default if given explicitly. */ |
1202 | set_masks &= ~target_flags_explicit; | |
957211c3 | 1203 | |
a4f6c312 | 1204 | /* Identify the processor type. */ |
8e3f41e7 | 1205 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 1206 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 1207 | |
b6a1cbae | 1208 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 1209 | { |
8e3f41e7 MM |
1210 | ptr = &rs6000_select[i]; |
1211 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 1212 | { |
8e3f41e7 MM |
1213 | for (j = 0; j < ptt_size; j++) |
1214 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
1215 | { | |
1216 | if (ptr->set_tune_p) | |
1217 | rs6000_cpu = processor_target_table[j].processor; | |
1218 | ||
1219 | if (ptr->set_arch_p) | |
1220 | { | |
66188a7e GK |
1221 | target_flags &= ~set_masks; |
1222 | target_flags |= (processor_target_table[j].target_enable | |
1223 | & set_masks); | |
8e3f41e7 MM |
1224 | } |
1225 | break; | |
1226 | } | |
1227 | ||
4406229e | 1228 | if (j == ptt_size) |
8e3f41e7 | 1229 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
1230 | } |
1231 | } | |
8a61d227 | 1232 | |
993f19a8 | 1233 | if (TARGET_E500) |
a3170dc6 AH |
1234 | rs6000_isel = 1; |
1235 | ||
dff9f1b6 DE |
1236 | /* If we are optimizing big endian systems for space, use the load/store |
1237 | multiple and string instructions. */ | |
ef792183 | 1238 | if (BYTES_BIG_ENDIAN && optimize_size) |
957211c3 | 1239 | target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); |
938937d8 | 1240 | |
a4f6c312 SS |
1241 | /* Don't allow -mmultiple or -mstring on little endian systems |
1242 | unless the cpu is a 750, because the hardware doesn't support the | |
1243 | instructions used in little endian mode, and causes an alignment | |
1244 | trap. The 750 does not cause an alignment trap (except when the | |
1245 | target is unaligned). */ | |
bef84347 | 1246 | |
b21fb038 | 1247 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
1248 | { |
1249 | if (TARGET_MULTIPLE) | |
1250 | { | |
1251 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 1252 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
d4ee4d25 | 1253 | warning (0, "-mmultiple is not supported on little endian systems"); |
7e69e155 MM |
1254 | } |
1255 | ||
1256 | if (TARGET_STRING) | |
1257 | { | |
1258 | target_flags &= ~MASK_STRING; | |
b21fb038 | 1259 | if ((target_flags_explicit & MASK_STRING) != 0) |
d4ee4d25 | 1260 | warning (0, "-mstring is not supported on little endian systems"); |
7e69e155 MM |
1261 | } |
1262 | } | |
3933e0e1 | 1263 | |
38c1f2d7 MM |
1264 | /* Set debug flags */ |
1265 | if (rs6000_debug_name) | |
1266 | { | |
bfc79d3b | 1267 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 1268 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 1269 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 1270 | rs6000_debug_stack = 1; |
bfc79d3b | 1271 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
1272 | rs6000_debug_arg = 1; |
1273 | else | |
c725bd79 | 1274 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
1275 | } |
1276 | ||
57ac7be9 AM |
1277 | if (rs6000_traceback_name) |
1278 | { | |
1279 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
1280 | rs6000_traceback = traceback_full; | |
1281 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
1282 | rs6000_traceback = traceback_part; | |
1283 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
1284 | rs6000_traceback = traceback_none; | |
1285 | else | |
9e637a26 | 1286 | error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>", |
57ac7be9 AM |
1287 | rs6000_traceback_name); |
1288 | } | |
1289 | ||
78f5898b AH |
1290 | if (!rs6000_explicit_options.long_double) |
1291 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; | |
6fa3f289 | 1292 | |
6d0ef01e HP |
1293 | /* Set Altivec ABI as default for powerpc64 linux. */ |
1294 | if (TARGET_ELF && TARGET_64BIT) | |
1295 | { | |
1296 | rs6000_altivec_abi = 1; | |
78f5898b | 1297 | TARGET_ALTIVEC_VRSAVE = 1; |
6d0ef01e HP |
1298 | } |
1299 | ||
594a51fe SS |
1300 | /* Set the Darwin64 ABI as default for 64-bit Darwin. */ |
1301 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
1302 | { | |
1303 | rs6000_darwin64_abi = 1; | |
9c7956fd | 1304 | #if TARGET_MACHO |
6ac49599 | 1305 | darwin_one_byte_bool = 1; |
9c7956fd | 1306 | #endif |
d9168963 SS |
1307 | /* Default to natural alignment, for better performance. */ |
1308 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
594a51fe SS |
1309 | } |
1310 | ||
c4501e62 JJ |
1311 | /* Handle -mtls-size option. */ |
1312 | rs6000_parse_tls_size_option (); | |
1313 | ||
a7ae18e2 AH |
1314 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1315 | SUBTARGET_OVERRIDE_OPTIONS; | |
1316 | #endif | |
1317 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
1318 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
1319 | #endif | |
4d4cbc0e AH |
1320 | #ifdef SUB3TARGET_OVERRIDE_OPTIONS |
1321 | SUB3TARGET_OVERRIDE_OPTIONS; | |
1322 | #endif | |
a7ae18e2 | 1323 | |
5da702b1 AH |
1324 | if (TARGET_E500) |
1325 | { | |
e4463bf1 AH |
1326 | if (TARGET_ALTIVEC) |
1327 | error ("AltiVec and E500 instructions cannot coexist"); | |
1328 | ||
5da702b1 AH |
1329 | /* The e500 does not have string instructions, and we set |
1330 | MASK_STRING above when optimizing for size. */ | |
1331 | if ((target_flags & MASK_STRING) != 0) | |
1332 | target_flags = target_flags & ~MASK_STRING; | |
1333 | } | |
1334 | else if (rs6000_select[1].string != NULL) | |
1335 | { | |
1336 | /* For the powerpc-eabispe configuration, we set all these by | |
1337 | default, so let's unset them if we manually set another | |
1338 | CPU that is not the E500. */ | |
78f5898b | 1339 | if (!rs6000_explicit_options.abi) |
5da702b1 | 1340 | rs6000_spe_abi = 0; |
78f5898b | 1341 | if (!rs6000_explicit_options.spe) |
5da702b1 | 1342 | rs6000_spe = 0; |
78f5898b | 1343 | if (!rs6000_explicit_options.float_gprs) |
5da702b1 | 1344 | rs6000_float_gprs = 0; |
78f5898b | 1345 | if (!rs6000_explicit_options.isel) |
5da702b1 | 1346 | rs6000_isel = 0; |
78f5898b | 1347 | if (!rs6000_explicit_options.long_double) |
c1e55850 | 1348 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
5da702b1 | 1349 | } |
b5044283 | 1350 | |
ec507f2d DE |
1351 | rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 |
1352 | && rs6000_cpu != PROCESSOR_POWER5); | |
1353 | rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 | |
1354 | || rs6000_cpu == PROCESSOR_POWER5); | |
1355 | ||
ec507f2d DE |
1356 | rs6000_sched_restricted_insns_priority |
1357 | = (rs6000_sched_groups ? 1 : 0); | |
79ae11c4 | 1358 | |
569fa502 | 1359 | /* Handle -msched-costly-dep option. */ |
ec507f2d DE |
1360 | rs6000_sched_costly_dep |
1361 | = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); | |
432218ba | 1362 | |
569fa502 DN |
1363 | if (rs6000_sched_costly_dep_str) |
1364 | { | |
f676971a | 1365 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) |
c4ad648e | 1366 | rs6000_sched_costly_dep = no_dep_costly; |
569fa502 | 1367 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) |
c4ad648e | 1368 | rs6000_sched_costly_dep = all_deps_costly; |
569fa502 | 1369 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) |
c4ad648e | 1370 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; |
569fa502 | 1371 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) |
c4ad648e | 1372 | rs6000_sched_costly_dep = store_to_load_dep_costly; |
f676971a | 1373 | else |
c4ad648e | 1374 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); |
cbe26ab8 DN |
1375 | } |
1376 | ||
1377 | /* Handle -minsert-sched-nops option. */ | |
ec507f2d DE |
1378 | rs6000_sched_insert_nops |
1379 | = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); | |
432218ba | 1380 | |
cbe26ab8 DN |
1381 | if (rs6000_sched_insert_nops_str) |
1382 | { | |
1383 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
c4ad648e | 1384 | rs6000_sched_insert_nops = sched_finish_none; |
cbe26ab8 | 1385 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) |
c4ad648e | 1386 | rs6000_sched_insert_nops = sched_finish_pad_groups; |
cbe26ab8 | 1387 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) |
c4ad648e | 1388 | rs6000_sched_insert_nops = sched_finish_regroup_exact; |
cbe26ab8 | 1389 | else |
c4ad648e | 1390 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); |
569fa502 DN |
1391 | } |
1392 | ||
c81bebd7 | 1393 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
1394 | /* If the user desires alternate register names, copy in the |
1395 | alternate names now. */ | |
c81bebd7 | 1396 | if (TARGET_REGNAMES) |
4e135bdd | 1397 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
1398 | #endif |
1399 | ||
df01da37 | 1400 | /* Set aix_struct_return last, after the ABI is determined. |
6fa3f289 ZW |
1401 | If -maix-struct-return or -msvr4-struct-return was explicitly |
1402 | used, don't override with the ABI default. */ | |
df01da37 DE |
1403 | if (!rs6000_explicit_options.aix_struct_ret) |
1404 | aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET); | |
6fa3f289 | 1405 | |
fcce224d DE |
1406 | if (TARGET_LONG_DOUBLE_128 |
1407 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
70a01792 | 1408 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 1409 | |
f676971a | 1410 | if (TARGET_TOC) |
9ebbca7d | 1411 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); |
71f123ca | 1412 | |
301d03af RS |
1413 | /* We can only guarantee the availability of DI pseudo-ops when |
1414 | assembling for 64-bit targets. */ | |
ae6c1efd | 1415 | if (!TARGET_64BIT) |
301d03af RS |
1416 | { |
1417 | targetm.asm_out.aligned_op.di = NULL; | |
1418 | targetm.asm_out.unaligned_op.di = NULL; | |
1419 | } | |
1420 | ||
1494c534 DE |
1421 | /* Set branch target alignment, if not optimizing for size. */ |
1422 | if (!optimize_size) | |
1423 | { | |
1424 | if (rs6000_sched_groups) | |
1425 | { | |
1426 | if (align_functions <= 0) | |
1427 | align_functions = 16; | |
1428 | if (align_jumps <= 0) | |
1429 | align_jumps = 16; | |
1430 | if (align_loops <= 0) | |
1431 | align_loops = 16; | |
1432 | } | |
1433 | if (align_jumps_max_skip <= 0) | |
1434 | align_jumps_max_skip = 15; | |
1435 | if (align_loops_max_skip <= 0) | |
1436 | align_loops_max_skip = 15; | |
1437 | } | |
2792d578 | 1438 | |
71f123ca FS |
1439 | /* Arrange to save and restore machine status around nested functions. */ |
1440 | init_machine_status = rs6000_init_machine_status; | |
42ba5130 RH |
1441 | |
1442 | /* We should always be splitting complex arguments, but we can't break | |
1443 | Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ | |
18f63bfa | 1444 | if (DEFAULT_ABI != ABI_AIX) |
42ba5130 | 1445 | targetm.calls.split_complex_arg = NULL; |
8b897cfa RS |
1446 | |
1447 | /* Initialize rs6000_cost with the appropriate target costs. */ | |
1448 | if (optimize_size) | |
1449 | rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; | |
1450 | else | |
1451 | switch (rs6000_cpu) | |
1452 | { | |
1453 | case PROCESSOR_RIOS1: | |
1454 | rs6000_cost = &rios1_cost; | |
1455 | break; | |
1456 | ||
1457 | case PROCESSOR_RIOS2: | |
1458 | rs6000_cost = &rios2_cost; | |
1459 | break; | |
1460 | ||
1461 | case PROCESSOR_RS64A: | |
1462 | rs6000_cost = &rs64a_cost; | |
1463 | break; | |
1464 | ||
1465 | case PROCESSOR_MPCCORE: | |
1466 | rs6000_cost = &mpccore_cost; | |
1467 | break; | |
1468 | ||
1469 | case PROCESSOR_PPC403: | |
1470 | rs6000_cost = &ppc403_cost; | |
1471 | break; | |
1472 | ||
1473 | case PROCESSOR_PPC405: | |
1474 | rs6000_cost = &ppc405_cost; | |
1475 | break; | |
1476 | ||
1477 | case PROCESSOR_PPC440: | |
1478 | rs6000_cost = &ppc440_cost; | |
1479 | break; | |
1480 | ||
1481 | case PROCESSOR_PPC601: | |
1482 | rs6000_cost = &ppc601_cost; | |
1483 | break; | |
1484 | ||
1485 | case PROCESSOR_PPC603: | |
1486 | rs6000_cost = &ppc603_cost; | |
1487 | break; | |
1488 | ||
1489 | case PROCESSOR_PPC604: | |
1490 | rs6000_cost = &ppc604_cost; | |
1491 | break; | |
1492 | ||
1493 | case PROCESSOR_PPC604e: | |
1494 | rs6000_cost = &ppc604e_cost; | |
1495 | break; | |
1496 | ||
1497 | case PROCESSOR_PPC620: | |
8b897cfa RS |
1498 | rs6000_cost = &ppc620_cost; |
1499 | break; | |
1500 | ||
f0517163 RS |
1501 | case PROCESSOR_PPC630: |
1502 | rs6000_cost = &ppc630_cost; | |
1503 | break; | |
1504 | ||
8b897cfa RS |
1505 | case PROCESSOR_PPC750: |
1506 | case PROCESSOR_PPC7400: | |
1507 | rs6000_cost = &ppc750_cost; | |
1508 | break; | |
1509 | ||
1510 | case PROCESSOR_PPC7450: | |
1511 | rs6000_cost = &ppc7450_cost; | |
1512 | break; | |
1513 | ||
1514 | case PROCESSOR_PPC8540: | |
1515 | rs6000_cost = &ppc8540_cost; | |
1516 | break; | |
1517 | ||
1518 | case PROCESSOR_POWER4: | |
1519 | case PROCESSOR_POWER5: | |
1520 | rs6000_cost = &power4_cost; | |
1521 | break; | |
1522 | ||
1523 | default: | |
37409796 | 1524 | gcc_unreachable (); |
8b897cfa | 1525 | } |
5248c961 | 1526 | } |
5accd822 | 1527 | |
7ccf35ed DN |
1528 | /* Implement targetm.vectorize.builtin_mask_for_load. */ |
1529 | static tree | |
1530 | rs6000_builtin_mask_for_load (void) | |
1531 | { | |
1532 | if (TARGET_ALTIVEC) | |
1533 | return altivec_builtin_mask_for_load; | |
1534 | else | |
1535 | return 0; | |
1536 | } | |
1537 | ||
5da702b1 AH |
1538 | /* Handle generic options of the form -mfoo=yes/no. |
1539 | NAME is the option name. | |
1540 | VALUE is the option value. | |
1541 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
1542 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 1543 | static void |
5da702b1 | 1544 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 1545 | { |
5da702b1 | 1546 | if (value == 0) |
993f19a8 | 1547 | return; |
5da702b1 AH |
1548 | else if (!strcmp (value, "yes")) |
1549 | *flag = 1; | |
1550 | else if (!strcmp (value, "no")) | |
1551 | *flag = 0; | |
08b57fb3 | 1552 | else |
5da702b1 | 1553 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
1554 | } |
1555 | ||
c4501e62 JJ |
1556 | /* Validate and record the size specified with the -mtls-size option. */ |
1557 | ||
1558 | static void | |
863d938c | 1559 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
1560 | { |
1561 | if (rs6000_tls_size_string == 0) | |
1562 | return; | |
1563 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
1564 | rs6000_tls_size = 16; | |
1565 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
1566 | rs6000_tls_size = 32; | |
1567 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
1568 | rs6000_tls_size = 64; | |
1569 | else | |
9e637a26 | 1570 | error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string); |
c4501e62 JJ |
1571 | } |
1572 | ||
5accd822 | 1573 | void |
a2369ed3 | 1574 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 1575 | { |
2e3f0db6 DJ |
1576 | if (DEFAULT_ABI == ABI_DARWIN) |
1577 | /* The Darwin libraries never set errno, so we might as well | |
1578 | avoid calling them when that's the only reason we would. */ | |
1579 | flag_errno_math = 0; | |
59d6560b DE |
1580 | |
1581 | /* Double growth factor to counter reduced min jump length. */ | |
1582 | set_param_value ("max-grow-copy-bb-insns", 16); | |
5accd822 | 1583 | } |
78f5898b AH |
1584 | |
1585 | /* Implement TARGET_HANDLE_OPTION. */ | |
1586 | ||
1587 | static bool | |
1588 | rs6000_handle_option (size_t code, const char *arg, int value) | |
1589 | { | |
1590 | switch (code) | |
1591 | { | |
1592 | case OPT_mno_power: | |
1593 | target_flags &= ~(MASK_POWER | MASK_POWER2 | |
1594 | | MASK_MULTIPLE | MASK_STRING); | |
c2dba4ab AH |
1595 | target_flags_explicit |= (MASK_POWER | MASK_POWER2 |
1596 | | MASK_MULTIPLE | MASK_STRING); | |
78f5898b AH |
1597 | break; |
1598 | case OPT_mno_powerpc: | |
1599 | target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT | |
1600 | | MASK_PPC_GFXOPT | MASK_POWERPC64); | |
c2dba4ab AH |
1601 | target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT |
1602 | | MASK_PPC_GFXOPT | MASK_POWERPC64); | |
78f5898b AH |
1603 | break; |
1604 | case OPT_mfull_toc: | |
1605 | target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC | |
1606 | | MASK_NO_SUM_IN_TOC); | |
c2dba4ab AH |
1607 | target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC |
1608 | | MASK_NO_SUM_IN_TOC); | |
78f5898b AH |
1609 | #ifdef TARGET_USES_SYSV4_OPT |
1610 | /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be | |
1611 | just the same as -mminimal-toc. */ | |
1612 | target_flags |= MASK_MINIMAL_TOC; | |
c2dba4ab | 1613 | target_flags_explicit |= MASK_MINIMAL_TOC; |
78f5898b AH |
1614 | #endif |
1615 | break; | |
1616 | ||
1617 | #ifdef TARGET_USES_SYSV4_OPT | |
1618 | case OPT_mtoc: | |
1619 | /* Make -mtoc behave like -mminimal-toc. */ | |
1620 | target_flags |= MASK_MINIMAL_TOC; | |
c2dba4ab | 1621 | target_flags_explicit |= MASK_MINIMAL_TOC; |
78f5898b AH |
1622 | break; |
1623 | #endif | |
1624 | ||
1625 | #ifdef TARGET_USES_AIX64_OPT | |
1626 | case OPT_maix64: | |
1627 | #else | |
1628 | case OPT_m64: | |
1629 | #endif | |
2c9c9afd AM |
1630 | target_flags |= MASK_POWERPC64 | MASK_POWERPC; |
1631 | target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT; | |
1632 | target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC; | |
78f5898b AH |
1633 | break; |
1634 | ||
1635 | #ifdef TARGET_USES_AIX64_OPT | |
1636 | case OPT_maix32: | |
1637 | #else | |
1638 | case OPT_m32: | |
1639 | #endif | |
1640 | target_flags &= ~MASK_POWERPC64; | |
c2dba4ab | 1641 | target_flags_explicit |= MASK_POWERPC64; |
78f5898b AH |
1642 | break; |
1643 | ||
1644 | case OPT_minsert_sched_nops_: | |
1645 | rs6000_sched_insert_nops_str = arg; | |
1646 | break; | |
1647 | ||
1648 | case OPT_mminimal_toc: | |
1649 | if (value == 1) | |
1650 | { | |
c2dba4ab AH |
1651 | target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC); |
1652 | target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC); | |
78f5898b AH |
1653 | } |
1654 | break; | |
1655 | ||
1656 | case OPT_mpower: | |
1657 | if (value == 1) | |
c2dba4ab AH |
1658 | { |
1659 | target_flags |= (MASK_MULTIPLE | MASK_STRING); | |
1660 | target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING); | |
1661 | } | |
78f5898b AH |
1662 | break; |
1663 | ||
1664 | case OPT_mpower2: | |
1665 | if (value == 1) | |
c2dba4ab AH |
1666 | { |
1667 | target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING); | |
1668 | target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING); | |
1669 | } | |
78f5898b AH |
1670 | break; |
1671 | ||
1672 | case OPT_mpowerpc_gpopt: | |
1673 | case OPT_mpowerpc_gfxopt: | |
1674 | if (value == 1) | |
c2dba4ab AH |
1675 | { |
1676 | target_flags |= MASK_POWERPC; | |
1677 | target_flags_explicit |= MASK_POWERPC; | |
1678 | } | |
78f5898b AH |
1679 | break; |
1680 | ||
df01da37 DE |
1681 | case OPT_maix_struct_return: |
1682 | case OPT_msvr4_struct_return: | |
1683 | rs6000_explicit_options.aix_struct_ret = true; | |
1684 | break; | |
1685 | ||
78f5898b AH |
1686 | case OPT_mvrsave_: |
1687 | rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE)); | |
1688 | break; | |
78f5898b AH |
1689 | |
1690 | case OPT_misel_: | |
1691 | rs6000_explicit_options.isel = true; | |
1692 | rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel)); | |
1693 | break; | |
1694 | ||
1695 | case OPT_mspe_: | |
1696 | rs6000_explicit_options.spe = true; | |
1697 | rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe)); | |
1698 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
1699 | if (!rs6000_spe) | |
1700 | rs6000_long_double_type_size = 64; | |
1701 | break; | |
1702 | ||
1703 | case OPT_mdebug_: | |
1704 | rs6000_debug_name = arg; | |
1705 | break; | |
1706 | ||
1707 | #ifdef TARGET_USES_SYSV4_OPT | |
1708 | case OPT_mcall_: | |
1709 | rs6000_abi_name = arg; | |
1710 | break; | |
1711 | ||
1712 | case OPT_msdata_: | |
1713 | rs6000_sdata_name = arg; | |
1714 | break; | |
1715 | ||
1716 | case OPT_mtls_size_: | |
1717 | rs6000_tls_size_string = arg; | |
1718 | break; | |
1719 | ||
1720 | case OPT_mrelocatable: | |
1721 | if (value == 1) | |
c2dba4ab AH |
1722 | { |
1723 | target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC; | |
1724 | target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC; | |
1725 | } | |
78f5898b AH |
1726 | break; |
1727 | ||
1728 | case OPT_mrelocatable_lib: | |
1729 | if (value == 1) | |
c2dba4ab AH |
1730 | { |
1731 | target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC | |
1732 | | MASK_NO_FP_IN_TOC; | |
1733 | target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC | |
1734 | | MASK_NO_FP_IN_TOC; | |
1735 | } | |
78f5898b | 1736 | else |
c2dba4ab AH |
1737 | { |
1738 | target_flags &= ~MASK_RELOCATABLE; | |
1739 | target_flags_explicit |= MASK_RELOCATABLE; | |
1740 | } | |
78f5898b AH |
1741 | break; |
1742 | #endif | |
1743 | ||
1744 | case OPT_mabi_: | |
1745 | rs6000_explicit_options.abi = true; | |
1746 | if (!strcmp (arg, "altivec")) | |
1747 | { | |
1748 | rs6000_altivec_abi = 1; | |
1749 | rs6000_spe_abi = 0; | |
1750 | } | |
1751 | else if (! strcmp (arg, "no-altivec")) | |
1752 | rs6000_altivec_abi = 0; | |
1753 | else if (! strcmp (arg, "spe")) | |
1754 | { | |
1755 | rs6000_spe_abi = 1; | |
1756 | rs6000_altivec_abi = 0; | |
1757 | if (!TARGET_SPE_ABI) | |
1758 | error ("not configured for ABI: '%s'", arg); | |
1759 | } | |
1760 | else if (! strcmp (arg, "no-spe")) | |
1761 | rs6000_spe_abi = 0; | |
1762 | ||
1763 | /* These are here for testing during development only, do not | |
1764 | document in the manual please. */ | |
1765 | else if (! strcmp (arg, "d64")) | |
1766 | { | |
1767 | rs6000_darwin64_abi = 1; | |
1768 | warning (0, "Using darwin64 ABI"); | |
1769 | } | |
1770 | else if (! strcmp (arg, "d32")) | |
1771 | { | |
1772 | rs6000_darwin64_abi = 0; | |
1773 | warning (0, "Using old darwin ABI"); | |
1774 | } | |
1775 | ||
1776 | else | |
1777 | { | |
1778 | error ("unknown ABI specified: '%s'", arg); | |
1779 | return false; | |
1780 | } | |
1781 | break; | |
1782 | ||
1783 | case OPT_mcpu_: | |
1784 | rs6000_select[1].string = arg; | |
1785 | break; | |
1786 | ||
1787 | case OPT_mtune_: | |
1788 | rs6000_select[2].string = arg; | |
1789 | break; | |
1790 | ||
1791 | case OPT_mtraceback_: | |
1792 | rs6000_traceback_name = arg; | |
1793 | break; | |
1794 | ||
1795 | case OPT_mfloat_gprs_: | |
1796 | rs6000_explicit_options.float_gprs = true; | |
1797 | if (! strcmp (arg, "yes") || ! strcmp (arg, "single")) | |
1798 | rs6000_float_gprs = 1; | |
1799 | else if (! strcmp (arg, "double")) | |
1800 | rs6000_float_gprs = 2; | |
1801 | else if (! strcmp (arg, "no")) | |
1802 | rs6000_float_gprs = 0; | |
1803 | else | |
1804 | { | |
1805 | error ("invalid option for -mfloat-gprs: '%s'", arg); | |
1806 | return false; | |
1807 | } | |
1808 | break; | |
1809 | ||
1810 | case OPT_mlong_double_: | |
1811 | rs6000_explicit_options.long_double = true; | |
1812 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; | |
1813 | if (value != 64 && value != 128) | |
1814 | { | |
1815 | error ("Unknown switch -mlong-double-%s", arg); | |
1816 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; | |
1817 | return false; | |
1818 | } | |
1819 | else | |
1820 | rs6000_long_double_type_size = value; | |
1821 | break; | |
1822 | ||
1823 | case OPT_msched_costly_dep_: | |
1824 | rs6000_sched_costly_dep_str = arg; | |
1825 | break; | |
1826 | ||
1827 | case OPT_malign_: | |
1828 | rs6000_explicit_options.alignment = true; | |
1829 | if (! strcmp (arg, "power")) | |
1830 | { | |
1831 | /* On 64-bit Darwin, power alignment is ABI-incompatible with | |
1832 | some C library functions, so warn about it. The flag may be | |
1833 | useful for performance studies from time to time though, so | |
1834 | don't disable it entirely. */ | |
1835 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
1836 | warning (0, "-malign-power is not supported for 64-bit Darwin;" | |
1837 | " it is incompatible with the installed C and C++ libraries"); | |
1838 | rs6000_alignment_flags = MASK_ALIGN_POWER; | |
1839 | } | |
1840 | else if (! strcmp (arg, "natural")) | |
1841 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
1842 | else | |
1843 | { | |
1844 | error ("unknown -malign-XXXXX option specified: '%s'", arg); | |
1845 | return false; | |
1846 | } | |
1847 | break; | |
1848 | } | |
1849 | return true; | |
1850 | } | |
3cfa4909 MM |
1851 | \f |
1852 | /* Do anything needed at the start of the asm file. */ | |
1853 | ||
1bc7c5b6 | 1854 | static void |
863d938c | 1855 | rs6000_file_start (void) |
3cfa4909 | 1856 | { |
c4d38ccb | 1857 | size_t i; |
3cfa4909 | 1858 | char buffer[80]; |
d330fd93 | 1859 | const char *start = buffer; |
3cfa4909 | 1860 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
1861 | const char *default_cpu = TARGET_CPU_DEFAULT; |
1862 | FILE *file = asm_out_file; | |
1863 | ||
1864 | default_file_start (); | |
1865 | ||
1866 | #ifdef TARGET_BI_ARCH | |
1867 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
1868 | default_cpu = 0; | |
1869 | #endif | |
3cfa4909 MM |
1870 | |
1871 | if (flag_verbose_asm) | |
1872 | { | |
1873 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
1874 | rs6000_select[0].string = default_cpu; | |
1875 | ||
b6a1cbae | 1876 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
1877 | { |
1878 | ptr = &rs6000_select[i]; | |
1879 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
1880 | { | |
1881 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
1882 | start = ""; | |
1883 | } | |
1884 | } | |
1885 | ||
9c6b4ed9 | 1886 | if (PPC405_ERRATUM77) |
b0bfee6e | 1887 | { |
9c6b4ed9 | 1888 | fprintf (file, "%s PPC405CR_ERRATUM77", start); |
b0bfee6e DE |
1889 | start = ""; |
1890 | } | |
b0bfee6e | 1891 | |
b91da81f | 1892 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
1893 | switch (rs6000_sdata) |
1894 | { | |
1895 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
1896 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
1897 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
1898 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
1899 | } | |
1900 | ||
1901 | if (rs6000_sdata && g_switch_value) | |
1902 | { | |
307b599c MK |
1903 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
1904 | g_switch_value); | |
3cfa4909 MM |
1905 | start = ""; |
1906 | } | |
1907 | #endif | |
1908 | ||
1909 | if (*start == '\0') | |
949ea356 | 1910 | putc ('\n', file); |
3cfa4909 | 1911 | } |
b723e82f JJ |
1912 | |
1913 | if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2)) | |
1914 | { | |
d6b5193b RS |
1915 | switch_to_section (toc_section); |
1916 | switch_to_section (text_section); | |
b723e82f | 1917 | } |
3cfa4909 | 1918 | } |
c4e18b1c | 1919 | |
5248c961 | 1920 | \f |
a0ab749a | 1921 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1922 | |
1923 | int | |
863d938c | 1924 | direct_return (void) |
9878760c | 1925 | { |
4697a36c MM |
1926 | if (reload_completed) |
1927 | { | |
1928 | rs6000_stack_t *info = rs6000_stack_info (); | |
1929 | ||
1930 | if (info->first_gp_reg_save == 32 | |
1931 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1932 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1933 | && ! info->lr_save_p |
1934 | && ! info->cr_save_p | |
00b960c7 | 1935 | && info->vrsave_mask == 0 |
c81fc13e | 1936 | && ! info->push_p) |
4697a36c MM |
1937 | return 1; |
1938 | } | |
1939 | ||
1940 | return 0; | |
9878760c RK |
1941 | } |
1942 | ||
4e74d8ec MM |
1943 | /* Return the number of instructions it takes to form a constant in an |
1944 | integer register. */ | |
1945 | ||
48d72335 | 1946 | int |
a2369ed3 | 1947 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
1948 | { |
1949 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1950 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1951 | return 1; |
1952 | ||
4e74d8ec | 1953 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1954 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1955 | return 1; |
1956 | ||
5f59ecb7 | 1957 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1958 | else if (TARGET_POWERPC64) |
4e74d8ec | 1959 | { |
a65c591c DE |
1960 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1961 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 1962 | |
a65c591c | 1963 | if (high == 0 || high == -1) |
4e74d8ec MM |
1964 | return 2; |
1965 | ||
a65c591c | 1966 | high >>= 1; |
4e74d8ec | 1967 | |
a65c591c | 1968 | if (low == 0) |
4e74d8ec | 1969 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
1970 | else |
1971 | return (num_insns_constant_wide (high) | |
e396202a | 1972 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1973 | } |
1974 | #endif | |
1975 | ||
1976 | else | |
1977 | return 2; | |
1978 | } | |
1979 | ||
1980 | int | |
a2369ed3 | 1981 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 1982 | { |
37409796 | 1983 | HOST_WIDE_INT low, high; |
bb8df8a6 | 1984 | |
37409796 | 1985 | switch (GET_CODE (op)) |
0d30d435 | 1986 | { |
37409796 | 1987 | case CONST_INT: |
0d30d435 | 1988 | #if HOST_BITS_PER_WIDE_INT == 64 |
4e2c1c44 | 1989 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1990cd79 | 1990 | && mask64_operand (op, mode)) |
c4ad648e | 1991 | return 2; |
0d30d435 DE |
1992 | else |
1993 | #endif | |
1994 | return num_insns_constant_wide (INTVAL (op)); | |
4e74d8ec | 1995 | |
37409796 NS |
1996 | case CONST_DOUBLE: |
1997 | if (mode == SFmode) | |
1998 | { | |
1999 | long l; | |
2000 | REAL_VALUE_TYPE rv; | |
bb8df8a6 | 2001 | |
37409796 NS |
2002 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
2003 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
2004 | return num_insns_constant_wide ((HOST_WIDE_INT) l); | |
2005 | } | |
a260abc9 | 2006 | |
37409796 NS |
2007 | if (mode == VOIDmode || mode == DImode) |
2008 | { | |
2009 | high = CONST_DOUBLE_HIGH (op); | |
2010 | low = CONST_DOUBLE_LOW (op); | |
2011 | } | |
2012 | else | |
2013 | { | |
2014 | long l[2]; | |
2015 | REAL_VALUE_TYPE rv; | |
bb8df8a6 | 2016 | |
37409796 NS |
2017 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
2018 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
2019 | high = l[WORDS_BIG_ENDIAN == 0]; | |
2020 | low = l[WORDS_BIG_ENDIAN != 0]; | |
2021 | } | |
47ad8c61 | 2022 | |
37409796 NS |
2023 | if (TARGET_32BIT) |
2024 | return (num_insns_constant_wide (low) | |
2025 | + num_insns_constant_wide (high)); | |
2026 | else | |
2027 | { | |
2028 | if ((high == 0 && low >= 0) | |
2029 | || (high == -1 && low < 0)) | |
2030 | return num_insns_constant_wide (low); | |
bb8df8a6 | 2031 | |
1990cd79 | 2032 | else if (mask64_operand (op, mode)) |
37409796 | 2033 | return 2; |
bb8df8a6 | 2034 | |
37409796 NS |
2035 | else if (low == 0) |
2036 | return num_insns_constant_wide (high) + 1; | |
bb8df8a6 | 2037 | |
37409796 NS |
2038 | else |
2039 | return (num_insns_constant_wide (high) | |
2040 | + num_insns_constant_wide (low) + 1); | |
2041 | } | |
bb8df8a6 | 2042 | |
37409796 NS |
2043 | default: |
2044 | gcc_unreachable (); | |
4e74d8ec | 2045 | } |
4e74d8ec MM |
2046 | } |
2047 | ||
452a7d36 | 2048 | |
66180ff3 PB |
2049 | /* Return true if OP can be synthesized with a particular vspltisb, vspltish |
2050 | or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used | |
2051 | depends on STEP and COPIES, one of which will be 1. If COPIES > 1, | |
2052 | all items are set to the same value and contain COPIES replicas of the | |
2053 | vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's | |
2054 | operand and the others are set to the value of the operand's msb. */ | |
2055 | ||
2056 | static bool | |
2057 | vspltis_constant (rtx op, unsigned step, unsigned copies) | |
452a7d36 | 2058 | { |
66180ff3 PB |
2059 | enum machine_mode mode = GET_MODE (op); |
2060 | enum machine_mode inner = GET_MODE_INNER (mode); | |
2061 | ||
2062 | unsigned i; | |
2063 | unsigned nunits = GET_MODE_NUNITS (mode); | |
2064 | unsigned bitsize = GET_MODE_BITSIZE (inner); | |
2065 | unsigned mask = GET_MODE_MASK (inner); | |
2066 | ||
2067 | rtx last = CONST_VECTOR_ELT (op, nunits - 1); | |
2068 | HOST_WIDE_INT val = INTVAL (last); | |
2069 | HOST_WIDE_INT splat_val = val; | |
2070 | HOST_WIDE_INT msb_val = val > 0 ? 0 : -1; | |
2071 | ||
2072 | /* Construct the value to be splatted, if possible. If not, return 0. */ | |
2073 | for (i = 2; i <= copies; i *= 2) | |
452a7d36 | 2074 | { |
66180ff3 PB |
2075 | HOST_WIDE_INT small_val; |
2076 | bitsize /= 2; | |
2077 | small_val = splat_val >> bitsize; | |
2078 | mask >>= bitsize; | |
2079 | if (splat_val != ((small_val << bitsize) | (small_val & mask))) | |
2080 | return false; | |
2081 | splat_val = small_val; | |
2082 | } | |
c4ad648e | 2083 | |
66180ff3 PB |
2084 | /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */ |
2085 | if (EASY_VECTOR_15 (splat_val)) | |
2086 | ; | |
2087 | ||
2088 | /* Also check if we can splat, and then add the result to itself. Do so if | |
2089 | the value is positive, of if the splat instruction is using OP's mode; | |
2090 | for splat_val < 0, the splat and the add should use the same mode. */ | |
2091 | else if (EASY_VECTOR_15_ADD_SELF (splat_val) | |
2092 | && (splat_val >= 0 || (step == 1 && copies == 1))) | |
2093 | ; | |
2094 | ||
2095 | else | |
2096 | return false; | |
2097 | ||
2098 | /* Check if VAL is present in every STEP-th element, and the | |
2099 | other elements are filled with its most significant bit. */ | |
2100 | for (i = 0; i < nunits - 1; ++i) | |
2101 | { | |
2102 | HOST_WIDE_INT desired_val; | |
2103 | if (((i + 1) & (step - 1)) == 0) | |
2104 | desired_val = val; | |
2105 | else | |
2106 | desired_val = msb_val; | |
2107 | ||
2108 | if (desired_val != INTVAL (CONST_VECTOR_ELT (op, i))) | |
2109 | return false; | |
452a7d36 | 2110 | } |
66180ff3 PB |
2111 | |
2112 | return true; | |
452a7d36 HP |
2113 | } |
2114 | ||
69ef87e2 | 2115 | |
66180ff3 PB |
2116 | /* Return true if OP is of the given MODE and can be synthesized |
2117 | with a vspltisb, vspltish or vspltisw. */ | |
2118 | ||
2119 | bool | |
2120 | easy_altivec_constant (rtx op, enum machine_mode mode) | |
d744e06e | 2121 | { |
66180ff3 | 2122 | unsigned step, copies; |
d744e06e | 2123 | |
66180ff3 PB |
2124 | if (mode == VOIDmode) |
2125 | mode = GET_MODE (op); | |
2126 | else if (mode != GET_MODE (op)) | |
2127 | return false; | |
d744e06e | 2128 | |
66180ff3 PB |
2129 | /* Start with a vspltisw. */ |
2130 | step = GET_MODE_NUNITS (mode) / 4; | |
2131 | copies = 1; | |
2132 | ||
2133 | if (vspltis_constant (op, step, copies)) | |
2134 | return true; | |
2135 | ||
2136 | /* Then try with a vspltish. */ | |
2137 | if (step == 1) | |
2138 | copies <<= 1; | |
2139 | else | |
2140 | step >>= 1; | |
2141 | ||
2142 | if (vspltis_constant (op, step, copies)) | |
2143 | return true; | |
2144 | ||
2145 | /* And finally a vspltisb. */ | |
2146 | if (step == 1) | |
2147 | copies <<= 1; | |
2148 | else | |
2149 | step >>= 1; | |
2150 | ||
2151 | if (vspltis_constant (op, step, copies)) | |
2152 | return true; | |
2153 | ||
2154 | return false; | |
d744e06e AH |
2155 | } |
2156 | ||
66180ff3 PB |
2157 | /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose |
2158 | result is OP. Abort if it is not possible. */ | |
d744e06e | 2159 | |
f676971a | 2160 | rtx |
66180ff3 | 2161 | gen_easy_altivec_constant (rtx op) |
452a7d36 | 2162 | { |
66180ff3 PB |
2163 | enum machine_mode mode = GET_MODE (op); |
2164 | int nunits = GET_MODE_NUNITS (mode); | |
2165 | rtx last = CONST_VECTOR_ELT (op, nunits - 1); | |
2166 | unsigned step = nunits / 4; | |
2167 | unsigned copies = 1; | |
2168 | ||
2169 | /* Start with a vspltisw. */ | |
2170 | if (vspltis_constant (op, step, copies)) | |
2171 | return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last)); | |
2172 | ||
2173 | /* Then try with a vspltish. */ | |
2174 | if (step == 1) | |
2175 | copies <<= 1; | |
2176 | else | |
2177 | step >>= 1; | |
2178 | ||
2179 | if (vspltis_constant (op, step, copies)) | |
2180 | return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last)); | |
2181 | ||
2182 | /* And finally a vspltisb. */ | |
2183 | if (step == 1) | |
2184 | copies <<= 1; | |
2185 | else | |
2186 | step >>= 1; | |
2187 | ||
2188 | if (vspltis_constant (op, step, copies)) | |
2189 | return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last)); | |
2190 | ||
2191 | gcc_unreachable (); | |
d744e06e AH |
2192 | } |
2193 | ||
2194 | const char * | |
a2369ed3 | 2195 | output_vec_const_move (rtx *operands) |
d744e06e AH |
2196 | { |
2197 | int cst, cst2; | |
2198 | enum machine_mode mode; | |
2199 | rtx dest, vec; | |
2200 | ||
2201 | dest = operands[0]; | |
2202 | vec = operands[1]; | |
d744e06e | 2203 | mode = GET_MODE (dest); |
69ef87e2 | 2204 | |
d744e06e AH |
2205 | if (TARGET_ALTIVEC) |
2206 | { | |
66180ff3 | 2207 | rtx splat_vec; |
d744e06e AH |
2208 | if (zero_constant (vec, mode)) |
2209 | return "vxor %0,%0,%0"; | |
37409796 | 2210 | |
66180ff3 PB |
2211 | splat_vec = gen_easy_altivec_constant (vec); |
2212 | gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE); | |
2213 | operands[1] = XEXP (splat_vec, 0); | |
2214 | if (!EASY_VECTOR_15 (INTVAL (operands[1]))) | |
2215 | return "#"; | |
bb8df8a6 | 2216 | |
66180ff3 | 2217 | switch (GET_MODE (splat_vec)) |
98ef3137 | 2218 | { |
37409796 | 2219 | case V4SImode: |
66180ff3 | 2220 | return "vspltisw %0,%1"; |
c4ad648e | 2221 | |
37409796 | 2222 | case V8HImode: |
66180ff3 | 2223 | return "vspltish %0,%1"; |
c4ad648e | 2224 | |
37409796 | 2225 | case V16QImode: |
66180ff3 | 2226 | return "vspltisb %0,%1"; |
bb8df8a6 | 2227 | |
37409796 NS |
2228 | default: |
2229 | gcc_unreachable (); | |
98ef3137 | 2230 | } |
69ef87e2 AH |
2231 | } |
2232 | ||
37409796 | 2233 | gcc_assert (TARGET_SPE); |
bb8df8a6 | 2234 | |
37409796 NS |
2235 | /* Vector constant 0 is handled as a splitter of V2SI, and in the |
2236 | pattern of V1DI, V4HI, and V2SF. | |
2237 | ||
2238 | FIXME: We should probably return # and add post reload | |
2239 | splitters for these, but this way is so easy ;-). */ | |
e20dcbef PB |
2240 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
2241 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
2242 | operands[1] = CONST_VECTOR_ELT (vec, 0); | |
2243 | operands[2] = CONST_VECTOR_ELT (vec, 1); | |
37409796 NS |
2244 | if (cst == cst2) |
2245 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
2246 | else | |
2247 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
69ef87e2 AH |
2248 | } |
2249 | ||
7a4eca66 DE |
2250 | /* Initialize vector TARGET to VALS. */ |
2251 | ||
2252 | void | |
2253 | rs6000_expand_vector_init (rtx target, rtx vals) | |
2254 | { | |
2255 | enum machine_mode mode = GET_MODE (target); | |
2256 | enum machine_mode inner_mode = GET_MODE_INNER (mode); | |
2257 | int n_elts = GET_MODE_NUNITS (mode); | |
2258 | int n_var = 0, one_var = -1; | |
2259 | bool all_same = true, all_const_zero = true; | |
2260 | rtx x, mem; | |
2261 | int i; | |
2262 | ||
2263 | for (i = 0; i < n_elts; ++i) | |
2264 | { | |
2265 | x = XVECEXP (vals, 0, i); | |
2266 | if (!CONSTANT_P (x)) | |
2267 | ++n_var, one_var = i; | |
2268 | else if (x != CONST0_RTX (inner_mode)) | |
2269 | all_const_zero = false; | |
2270 | ||
2271 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
2272 | all_same = false; | |
2273 | } | |
2274 | ||
2275 | if (n_var == 0) | |
2276 | { | |
2277 | if (mode != V4SFmode && all_const_zero) | |
2278 | { | |
2279 | /* Zero register. */ | |
2280 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2281 | gen_rtx_XOR (mode, target, target))); | |
2282 | return; | |
2283 | } | |
66180ff3 | 2284 | else if (mode != V4SFmode && easy_vector_constant (vals, mode)) |
7a4eca66 DE |
2285 | { |
2286 | /* Splat immediate. */ | |
66180ff3 | 2287 | emit_insn (gen_rtx_SET (VOIDmode, target, vals)); |
7a4eca66 DE |
2288 | return; |
2289 | } | |
2290 | else if (all_same) | |
2291 | ; /* Splat vector element. */ | |
2292 | else | |
2293 | { | |
2294 | /* Load from constant pool. */ | |
2295 | emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0))); | |
2296 | return; | |
2297 | } | |
2298 | } | |
2299 | ||
2300 | /* Store value to stack temp. Load vector element. Splat. */ | |
2301 | if (all_same) | |
2302 | { | |
2303 | mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0); | |
2304 | emit_move_insn (adjust_address_nv (mem, inner_mode, 0), | |
2305 | XVECEXP (vals, 0, 0)); | |
2306 | x = gen_rtx_UNSPEC (VOIDmode, | |
2307 | gen_rtvec (1, const0_rtx), UNSPEC_LVE); | |
2308 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
2309 | gen_rtvec (2, | |
2310 | gen_rtx_SET (VOIDmode, | |
2311 | target, mem), | |
2312 | x))); | |
2313 | x = gen_rtx_VEC_SELECT (inner_mode, target, | |
2314 | gen_rtx_PARALLEL (VOIDmode, | |
2315 | gen_rtvec (1, const0_rtx))); | |
2316 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2317 | gen_rtx_VEC_DUPLICATE (mode, x))); | |
2318 | return; | |
2319 | } | |
2320 | ||
2321 | /* One field is non-constant. Load constant then overwrite | |
2322 | varying field. */ | |
2323 | if (n_var == 1) | |
2324 | { | |
2325 | rtx copy = copy_rtx (vals); | |
2326 | ||
57b51d4d | 2327 | /* Load constant part of vector, substitute neighboring value for |
7a4eca66 DE |
2328 | varying element. */ |
2329 | XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts); | |
2330 | rs6000_expand_vector_init (target, copy); | |
2331 | ||
2332 | /* Insert variable. */ | |
2333 | rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var); | |
2334 | return; | |
2335 | } | |
2336 | ||
2337 | /* Construct the vector in memory one field at a time | |
2338 | and load the whole vector. */ | |
2339 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); | |
2340 | for (i = 0; i < n_elts; i++) | |
2341 | emit_move_insn (adjust_address_nv (mem, inner_mode, | |
2342 | i * GET_MODE_SIZE (inner_mode)), | |
2343 | XVECEXP (vals, 0, i)); | |
2344 | emit_move_insn (target, mem); | |
2345 | } | |
2346 | ||
2347 | /* Set field ELT of TARGET to VAL. */ | |
2348 | ||
2349 | void | |
2350 | rs6000_expand_vector_set (rtx target, rtx val, int elt) | |
2351 | { | |
2352 | enum machine_mode mode = GET_MODE (target); | |
2353 | enum machine_mode inner_mode = GET_MODE_INNER (mode); | |
2354 | rtx reg = gen_reg_rtx (mode); | |
2355 | rtx mask, mem, x; | |
2356 | int width = GET_MODE_SIZE (inner_mode); | |
2357 | int i; | |
2358 | ||
2359 | /* Load single variable value. */ | |
2360 | mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0); | |
2361 | emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val); | |
2362 | x = gen_rtx_UNSPEC (VOIDmode, | |
2363 | gen_rtvec (1, const0_rtx), UNSPEC_LVE); | |
2364 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
2365 | gen_rtvec (2, | |
2366 | gen_rtx_SET (VOIDmode, | |
2367 | reg, mem), | |
2368 | x))); | |
2369 | ||
2370 | /* Linear sequence. */ | |
2371 | mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16)); | |
2372 | for (i = 0; i < 16; ++i) | |
2373 | XVECEXP (mask, 0, i) = GEN_INT (i); | |
2374 | ||
2375 | /* Set permute mask to insert element into target. */ | |
2376 | for (i = 0; i < width; ++i) | |
2377 | XVECEXP (mask, 0, elt*width + i) | |
2378 | = GEN_INT (i + 0x10); | |
2379 | x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0)); | |
2380 | x = gen_rtx_UNSPEC (mode, | |
2381 | gen_rtvec (3, target, reg, | |
2382 | force_reg (V16QImode, x)), | |
2383 | UNSPEC_VPERM); | |
2384 | emit_insn (gen_rtx_SET (VOIDmode, target, x)); | |
2385 | } | |
2386 | ||
2387 | /* Extract field ELT from VEC into TARGET. */ | |
2388 | ||
2389 | void | |
2390 | rs6000_expand_vector_extract (rtx target, rtx vec, int elt) | |
2391 | { | |
2392 | enum machine_mode mode = GET_MODE (vec); | |
2393 | enum machine_mode inner_mode = GET_MODE_INNER (mode); | |
2394 | rtx mem, x; | |
2395 | ||
2396 | /* Allocate mode-sized buffer. */ | |
2397 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); | |
2398 | ||
2399 | /* Add offset to field within buffer matching vector element. */ | |
2400 | mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode)); | |
2401 | ||
2402 | /* Store single field into mode-sized buffer. */ | |
2403 | x = gen_rtx_UNSPEC (VOIDmode, | |
2404 | gen_rtvec (1, const0_rtx), UNSPEC_STVE); | |
2405 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
2406 | gen_rtvec (2, | |
2407 | gen_rtx_SET (VOIDmode, | |
2408 | mem, vec), | |
2409 | x))); | |
2410 | emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0)); | |
2411 | } | |
2412 | ||
0ba1b2ff AM |
2413 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to |
2414 | implement ANDing by the mask IN. */ | |
2415 | void | |
a2369ed3 | 2416 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
2417 | { |
2418 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2419 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2420 | int shift; | |
2421 | ||
37409796 | 2422 | gcc_assert (GET_CODE (in) == CONST_INT); |
0ba1b2ff AM |
2423 | |
2424 | c = INTVAL (in); | |
2425 | if (c & 1) | |
2426 | { | |
2427 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2428 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2429 | is at the MS end and can be cleared with an rldicl mask. We then | |
2430 | rotate back and clear off the MS ^^ group of zeros with a | |
2431 | second rldicl. */ | |
2432 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2433 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2434 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2435 | c = ~c; /* c == 0x00fff000000fffff */ | |
2436 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2437 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2438 | c = ~c; /* c == 0xff000fffffffffff */ | |
2439 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2440 | shift = 0; | |
2441 | while ((lsb >>= 1) != 0) | |
2442 | shift++; /* shift == 44 on exit from loop */ | |
2443 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2444 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2445 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2446 | } |
2447 | else | |
0ba1b2ff AM |
2448 | { |
2449 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2450 | is to rotate the word so that the ^^^ middle group of zeros | |
2451 | is at the LS end and can be cleared with an rldicr mask. We then | |
2452 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2453 | a second rldicr. */ | |
2454 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2455 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2456 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2457 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2458 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2459 | c = ~c; /* c == 0xff000fffffffffff */ | |
2460 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2461 | shift = 0; | |
2462 | while ((lsb >>= 1) != 0) | |
2463 | shift++; /* shift == 44 on exit from loop */ | |
2464 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2465 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2466 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2467 | } | |
2468 | ||
2469 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2470 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2471 | out[0] = GEN_INT (64 - shift); | |
2472 | out[1] = GEN_INT (m1); | |
2473 | out[2] = GEN_INT (shift); | |
2474 | out[3] = GEN_INT (m2); | |
2475 | #else | |
045572c7 GK |
2476 | (void)in; |
2477 | (void)out; | |
37409796 | 2478 | gcc_unreachable (); |
0ba1b2ff | 2479 | #endif |
a260abc9 DE |
2480 | } |
2481 | ||
54b695e7 | 2482 | /* Return TRUE if OP is an invalid SUBREG operation on the e500. */ |
48d72335 DE |
2483 | |
2484 | bool | |
54b695e7 AH |
2485 | invalid_e500_subreg (rtx op, enum machine_mode mode) |
2486 | { | |
2487 | /* Reject (subreg:SI (reg:DF)). */ | |
2488 | if (GET_CODE (op) == SUBREG | |
2489 | && mode == SImode | |
2490 | && REG_P (SUBREG_REG (op)) | |
2491 | && GET_MODE (SUBREG_REG (op)) == DFmode) | |
2492 | return true; | |
2493 | ||
2494 | /* Reject (subreg:DF (reg:DI)). */ | |
2495 | if (GET_CODE (op) == SUBREG | |
2496 | && mode == DFmode | |
2497 | && REG_P (SUBREG_REG (op)) | |
2498 | && GET_MODE (SUBREG_REG (op)) == DImode) | |
2499 | return true; | |
2500 | ||
2501 | return false; | |
2502 | } | |
2503 | ||
95727fb8 AP |
2504 | /* Darwin, AIX increases natural record alignment to doubleword if the first |
2505 | field is an FP double while the FP fields remain word aligned. */ | |
2506 | ||
19d66194 | 2507 | unsigned int |
95727fb8 AP |
2508 | rs6000_special_round_type_align (tree type, int computed, int specified) |
2509 | { | |
2510 | tree field = TYPE_FIELDS (type); | |
95727fb8 | 2511 | |
bb8df8a6 | 2512 | /* Skip all non field decls */ |
85962ac8 | 2513 | while (field != NULL && TREE_CODE (field) != FIELD_DECL) |
95727fb8 AP |
2514 | field = TREE_CHAIN (field); |
2515 | ||
392cc400 AM |
2516 | if (field == NULL || field == type |
2517 | || TYPE_MODE (TREE_CODE (TREE_TYPE (field)) == ARRAY_TYPE | |
2518 | ? get_inner_array_type (field) | |
2519 | : TREE_TYPE (field)) != DFmode) | |
95727fb8 AP |
2520 | return MAX (computed, specified); |
2521 | ||
2522 | return MAX (MAX (computed, specified), 64); | |
2523 | } | |
2524 | ||
a4f6c312 | 2525 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
2526 | |
2527 | int | |
f676971a | 2528 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
a2369ed3 | 2529 | enum machine_mode mode ATTRIBUTE_UNUSED) |
7509c759 | 2530 | { |
38c1f2d7 | 2531 | #if TARGET_ELF |
5f59ecb7 | 2532 | rtx sym_ref; |
7509c759 | 2533 | |
d9407988 | 2534 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 2535 | return 0; |
a54d04b7 | 2536 | |
f607bc57 | 2537 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
2538 | return 0; |
2539 | ||
88228c4b MM |
2540 | if (GET_CODE (op) == SYMBOL_REF) |
2541 | sym_ref = op; | |
2542 | ||
2543 | else if (GET_CODE (op) != CONST | |
2544 | || GET_CODE (XEXP (op, 0)) != PLUS | |
2545 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
2546 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
2547 | return 0; |
2548 | ||
88228c4b | 2549 | else |
dbf55e53 MM |
2550 | { |
2551 | rtx sum = XEXP (op, 0); | |
2552 | HOST_WIDE_INT summand; | |
2553 | ||
2554 | /* We have to be careful here, because it is the referenced address | |
c4ad648e | 2555 | that must be 32k from _SDA_BASE_, not just the symbol. */ |
dbf55e53 | 2556 | summand = INTVAL (XEXP (sum, 1)); |
307b599c | 2557 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
9390387d | 2558 | return 0; |
dbf55e53 MM |
2559 | |
2560 | sym_ref = XEXP (sum, 0); | |
2561 | } | |
88228c4b | 2562 | |
20bfcd69 | 2563 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
2564 | #else |
2565 | return 0; | |
2566 | #endif | |
7509c759 | 2567 | } |
46c07df8 | 2568 | |
3a1f863f | 2569 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 2570 | |
3a1f863f DE |
2571 | bool |
2572 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 2573 | { |
3a1f863f DE |
2574 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
2575 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
2576 | } |
2577 | ||
9ebbca7d | 2578 | \f |
4d588c14 RH |
2579 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
2580 | ||
f676971a EC |
2581 | static int |
2582 | constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) | |
9ebbca7d | 2583 | { |
9390387d | 2584 | switch (GET_CODE (op)) |
9ebbca7d GK |
2585 | { |
2586 | case SYMBOL_REF: | |
c4501e62 JJ |
2587 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
2588 | return 0; | |
2589 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
2590 | { |
2591 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
2592 | { | |
2593 | *have_sym = 1; | |
2594 | return 1; | |
2595 | } | |
2596 | else | |
2597 | return 0; | |
2598 | } | |
2599 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
2600 | { | |
2601 | *have_toc = 1; | |
2602 | return 1; | |
2603 | } | |
2604 | else | |
2605 | return 0; | |
9ebbca7d GK |
2606 | case PLUS: |
2607 | case MINUS: | |
c1f11548 DE |
2608 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
2609 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 2610 | case CONST: |
a4f6c312 | 2611 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 2612 | case CONST_INT: |
a4f6c312 | 2613 | return 1; |
9ebbca7d | 2614 | default: |
a4f6c312 | 2615 | return 0; |
9ebbca7d GK |
2616 | } |
2617 | } | |
2618 | ||
4d588c14 | 2619 | static bool |
a2369ed3 | 2620 | constant_pool_expr_p (rtx op) |
9ebbca7d GK |
2621 | { |
2622 | int have_sym = 0; | |
2623 | int have_toc = 0; | |
2624 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
2625 | } | |
2626 | ||
48d72335 | 2627 | bool |
a2369ed3 | 2628 | toc_relative_expr_p (rtx op) |
9ebbca7d | 2629 | { |
4d588c14 RH |
2630 | int have_sym = 0; |
2631 | int have_toc = 0; | |
2632 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
2633 | } | |
2634 | ||
4d588c14 | 2635 | bool |
a2369ed3 | 2636 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
2637 | { |
2638 | return (TARGET_TOC | |
2639 | && GET_CODE (x) == PLUS | |
2640 | && GET_CODE (XEXP (x, 0)) == REG | |
2641 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
2642 | && constant_pool_expr_p (XEXP (x, 1))); | |
2643 | } | |
2644 | ||
0c380712 AM |
2645 | bool |
2646 | rs6000_legitimate_small_data_p (enum machine_mode mode, rtx x) | |
4d588c14 RH |
2647 | { |
2648 | return (DEFAULT_ABI == ABI_V4 | |
2649 | && !flag_pic && !TARGET_TOC | |
2650 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
2651 | && small_data_operand (x, mode)); | |
2652 | } | |
2653 | ||
60cdabab DE |
2654 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
2655 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
2656 | ||
76d2b81d DJ |
2657 | bool |
2658 | rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) | |
4d588c14 RH |
2659 | { |
2660 | unsigned HOST_WIDE_INT offset, extra; | |
2661 | ||
2662 | if (GET_CODE (x) != PLUS) | |
2663 | return false; | |
2664 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2665 | return false; | |
2666 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2667 | return false; | |
60cdabab DE |
2668 | if (legitimate_constant_pool_address_p (x)) |
2669 | return true; | |
4d588c14 RH |
2670 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
2671 | return false; | |
2672 | ||
2673 | offset = INTVAL (XEXP (x, 1)); | |
2674 | extra = 0; | |
2675 | switch (mode) | |
2676 | { | |
2677 | case V16QImode: | |
2678 | case V8HImode: | |
2679 | case V4SFmode: | |
2680 | case V4SImode: | |
7a4eca66 DE |
2681 | /* AltiVec vector modes. Only reg+reg addressing is valid and |
2682 | constant offset zero should not occur due to canonicalization. | |
2683 | Allow any offset when not strict before reload. */ | |
2684 | return !strict; | |
4d588c14 RH |
2685 | |
2686 | case V4HImode: | |
2687 | case V2SImode: | |
2688 | case V1DImode: | |
2689 | case V2SFmode: | |
2690 | /* SPE vector modes. */ | |
2691 | return SPE_CONST_OFFSET_OK (offset); | |
2692 | ||
2693 | case DFmode: | |
4d4cbc0e AH |
2694 | if (TARGET_E500_DOUBLE) |
2695 | return SPE_CONST_OFFSET_OK (offset); | |
2696 | ||
4d588c14 | 2697 | case DImode: |
54b695e7 AH |
2698 | /* On e500v2, we may have: |
2699 | ||
2700 | (subreg:DF (mem:DI (plus (reg) (const_int))) 0). | |
2701 | ||
2702 | Which gets addressed with evldd instructions. */ | |
2703 | if (TARGET_E500_DOUBLE) | |
2704 | return SPE_CONST_OFFSET_OK (offset); | |
2705 | ||
3364872d | 2706 | if (mode == DFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2707 | extra = 4; |
2708 | else if (offset & 3) | |
2709 | return false; | |
2710 | break; | |
2711 | ||
2712 | case TFmode: | |
2713 | case TImode: | |
3364872d | 2714 | if (mode == TFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2715 | extra = 12; |
2716 | else if (offset & 3) | |
2717 | return false; | |
2718 | else | |
2719 | extra = 8; | |
2720 | break; | |
2721 | ||
2722 | default: | |
2723 | break; | |
2724 | } | |
2725 | ||
b1917422 AM |
2726 | offset += 0x8000; |
2727 | return (offset < 0x10000) && (offset + extra < 0x10000); | |
4d588c14 RH |
2728 | } |
2729 | ||
2730 | static bool | |
a2369ed3 | 2731 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
2732 | { |
2733 | rtx op0, op1; | |
2734 | ||
2735 | if (GET_CODE (x) != PLUS) | |
2736 | return false; | |
850e8d3d | 2737 | |
4d588c14 RH |
2738 | op0 = XEXP (x, 0); |
2739 | op1 = XEXP (x, 1); | |
2740 | ||
bf00cc0f | 2741 | /* Recognize the rtl generated by reload which we know will later be |
9024f4b8 AM |
2742 | replaced with proper base and index regs. */ |
2743 | if (!strict | |
2744 | && reload_in_progress | |
2745 | && (REG_P (op0) || GET_CODE (op0) == PLUS) | |
2746 | && REG_P (op1)) | |
2747 | return true; | |
2748 | ||
2749 | return (REG_P (op0) && REG_P (op1) | |
2750 | && ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
2751 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
2752 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
2753 | && INT_REG_OK_FOR_INDEX_P (op0, strict)))); | |
9ebbca7d GK |
2754 | } |
2755 | ||
48d72335 | 2756 | inline bool |
a2369ed3 | 2757 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
2758 | { |
2759 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
2760 | } | |
2761 | ||
48d72335 | 2762 | bool |
4c81e946 FJ |
2763 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) |
2764 | { | |
c4ad648e | 2765 | if (!TARGET_MACHO || !flag_pic |
9390387d | 2766 | || mode != SImode || GET_CODE (x) != MEM) |
c4ad648e AM |
2767 | return false; |
2768 | x = XEXP (x, 0); | |
4c81e946 FJ |
2769 | |
2770 | if (GET_CODE (x) != LO_SUM) | |
2771 | return false; | |
2772 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2773 | return false; | |
2774 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
2775 | return false; | |
2776 | x = XEXP (x, 1); | |
2777 | ||
2778 | return CONSTANT_P (x); | |
2779 | } | |
2780 | ||
4d588c14 | 2781 | static bool |
a2369ed3 | 2782 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
2783 | { |
2784 | if (GET_CODE (x) != LO_SUM) | |
2785 | return false; | |
2786 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2787 | return false; | |
2788 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2789 | return false; | |
54b695e7 AH |
2790 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
2791 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) | |
f82f556d | 2792 | return false; |
4d588c14 RH |
2793 | x = XEXP (x, 1); |
2794 | ||
8622e235 | 2795 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 2796 | { |
a29077da | 2797 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
2798 | return false; |
2799 | if (TARGET_TOC) | |
2800 | return false; | |
2801 | if (GET_MODE_NUNITS (mode) != 1) | |
2802 | return false; | |
5e5f01b9 | 2803 | if (GET_MODE_BITSIZE (mode) > 64 |
3c028f65 AM |
2804 | || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64 |
2805 | && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))) | |
4d588c14 RH |
2806 | return false; |
2807 | ||
2808 | return CONSTANT_P (x); | |
2809 | } | |
2810 | ||
2811 | return false; | |
2812 | } | |
2813 | ||
2814 | ||
9ebbca7d GK |
2815 | /* Try machine-dependent ways of modifying an illegitimate address |
2816 | to be legitimate. If we find one, return the new, valid address. | |
2817 | This is used from only one place: `memory_address' in explow.c. | |
2818 | ||
a4f6c312 SS |
2819 | OLDX is the address as it was before break_out_memory_refs was |
2820 | called. In some cases it is useful to look at this to decide what | |
2821 | needs to be done. | |
9ebbca7d | 2822 | |
a4f6c312 | 2823 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 2824 | |
a4f6c312 SS |
2825 | It is always safe for this function to do nothing. It exists to |
2826 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
2827 | |
2828 | On RS/6000, first check for the sum of a register with a constant | |
2829 | integer that is out of range. If so, generate code to add the | |
2830 | constant with the low-order 16 bits masked to the register and force | |
2831 | this result into another register (this can be done with `cau'). | |
2832 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
2833 | possibility of bit 16 being a one. | |
2834 | ||
2835 | Then check for the sum of a register and something not constant, try to | |
2836 | load the other things into a register and return the sum. */ | |
4d588c14 | 2837 | |
9ebbca7d | 2838 | rtx |
a2369ed3 DJ |
2839 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
2840 | enum machine_mode mode) | |
0ac081f6 | 2841 | { |
c4501e62 JJ |
2842 | if (GET_CODE (x) == SYMBOL_REF) |
2843 | { | |
2844 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
2845 | if (model != 0) | |
2846 | return rs6000_legitimize_tls_address (x, model); | |
2847 | } | |
2848 | ||
f676971a | 2849 | if (GET_CODE (x) == PLUS |
9ebbca7d GK |
2850 | && GET_CODE (XEXP (x, 0)) == REG |
2851 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2852 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
f676971a | 2853 | { |
9ebbca7d GK |
2854 | HOST_WIDE_INT high_int, low_int; |
2855 | rtx sum; | |
a65c591c DE |
2856 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
2857 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
2858 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
2859 | GEN_INT (high_int)), 0); | |
2860 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
2861 | } | |
f676971a | 2862 | else if (GET_CODE (x) == PLUS |
9ebbca7d GK |
2863 | && GET_CODE (XEXP (x, 0)) == REG |
2864 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 2865 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
2866 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
2867 | || TARGET_POWERPC64 | |
54b695e7 AH |
2868 | || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE) |
2869 | && mode != TFmode)) | |
9ebbca7d GK |
2870 | && (TARGET_POWERPC64 || mode != DImode) |
2871 | && mode != TImode) | |
2872 | { | |
2873 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
2874 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
2875 | } | |
0ac081f6 AH |
2876 | else if (ALTIVEC_VECTOR_MODE (mode)) |
2877 | { | |
2878 | rtx reg; | |
2879 | ||
2880 | /* Make sure both operands are registers. */ | |
2881 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 2882 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
2883 | force_reg (Pmode, XEXP (x, 1))); |
2884 | ||
2885 | reg = force_reg (Pmode, x); | |
2886 | return reg; | |
2887 | } | |
4d4cbc0e | 2888 | else if (SPE_VECTOR_MODE (mode) |
54b695e7 AH |
2889 | || (TARGET_E500_DOUBLE && (mode == DFmode |
2890 | || mode == DImode))) | |
a3170dc6 | 2891 | { |
54b695e7 AH |
2892 | if (mode == DImode) |
2893 | return NULL_RTX; | |
a3170dc6 AH |
2894 | /* We accept [reg + reg] and [reg + OFFSET]. */ |
2895 | ||
2896 | if (GET_CODE (x) == PLUS) | |
c4ad648e AM |
2897 | { |
2898 | rtx op1 = XEXP (x, 0); | |
2899 | rtx op2 = XEXP (x, 1); | |
a3170dc6 | 2900 | |
c4ad648e | 2901 | op1 = force_reg (Pmode, op1); |
a3170dc6 | 2902 | |
c4ad648e AM |
2903 | if (GET_CODE (op2) != REG |
2904 | && (GET_CODE (op2) != CONST_INT | |
2905 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
2906 | op2 = force_reg (Pmode, op2); | |
a3170dc6 | 2907 | |
c4ad648e AM |
2908 | return gen_rtx_PLUS (Pmode, op1, op2); |
2909 | } | |
a3170dc6 AH |
2910 | |
2911 | return force_reg (Pmode, x); | |
2912 | } | |
f1384257 AM |
2913 | else if (TARGET_ELF |
2914 | && TARGET_32BIT | |
2915 | && TARGET_NO_TOC | |
2916 | && ! flag_pic | |
9ebbca7d | 2917 | && GET_CODE (x) != CONST_INT |
f676971a | 2918 | && GET_CODE (x) != CONST_DOUBLE |
9ebbca7d | 2919 | && CONSTANT_P (x) |
6ac7bf2c GK |
2920 | && GET_MODE_NUNITS (mode) == 1 |
2921 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 2922 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
2923 | { |
2924 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2925 | emit_insn (gen_elf_high (reg, x)); |
2926 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 2927 | } |
ee890fe2 SS |
2928 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
2929 | && ! flag_pic | |
ab82a49f AP |
2930 | #if TARGET_MACHO |
2931 | && ! MACHO_DYNAMIC_NO_PIC_P | |
2932 | #endif | |
ee890fe2 | 2933 | && GET_CODE (x) != CONST_INT |
f676971a | 2934 | && GET_CODE (x) != CONST_DOUBLE |
ee890fe2 | 2935 | && CONSTANT_P (x) |
f82f556d | 2936 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
f676971a | 2937 | && mode != DImode |
ee890fe2 SS |
2938 | && mode != TImode) |
2939 | { | |
2940 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2941 | emit_insn (gen_macho_high (reg, x)); |
2942 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 2943 | } |
f676971a | 2944 | else if (TARGET_TOC |
4d588c14 | 2945 | && constant_pool_expr_p (x) |
a9098fd0 | 2946 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
2947 | { |
2948 | return create_TOC_reference (x); | |
2949 | } | |
2950 | else | |
2951 | return NULL_RTX; | |
2952 | } | |
258bfae2 | 2953 | |
fdbe66f2 | 2954 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
c973d557 JJ |
2955 | We need to emit DTP-relative relocations. */ |
2956 | ||
fdbe66f2 | 2957 | static void |
c973d557 JJ |
2958 | rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) |
2959 | { | |
2960 | switch (size) | |
2961 | { | |
2962 | case 4: | |
2963 | fputs ("\t.long\t", file); | |
2964 | break; | |
2965 | case 8: | |
2966 | fputs (DOUBLE_INT_ASM_OP, file); | |
2967 | break; | |
2968 | default: | |
37409796 | 2969 | gcc_unreachable (); |
c973d557 JJ |
2970 | } |
2971 | output_addr_const (file, x); | |
2972 | fputs ("@dtprel+0x8000", file); | |
2973 | } | |
2974 | ||
c4501e62 JJ |
2975 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
2976 | ||
2977 | static GTY(()) rtx rs6000_tls_symbol; | |
2978 | static rtx | |
863d938c | 2979 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
2980 | { |
2981 | if (!rs6000_tls_symbol) | |
2982 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
2983 | ||
2984 | return rs6000_tls_symbol; | |
2985 | } | |
2986 | ||
2987 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
2988 | ||
2989 | static GTY(()) rtx rs6000_got_symbol; | |
2990 | static rtx | |
863d938c | 2991 | rs6000_got_sym (void) |
c4501e62 JJ |
2992 | { |
2993 | if (!rs6000_got_symbol) | |
2994 | { | |
2995 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2996 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
2997 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
f676971a | 2998 | } |
c4501e62 JJ |
2999 | |
3000 | return rs6000_got_symbol; | |
3001 | } | |
3002 | ||
3003 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3004 | this (thread-local) address. */ | |
3005 | ||
3006 | static rtx | |
a2369ed3 | 3007 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
3008 | { |
3009 | rtx dest, insn; | |
3010 | ||
3011 | dest = gen_reg_rtx (Pmode); | |
3012 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
3013 | { | |
3014 | rtx tlsreg; | |
3015 | ||
3016 | if (TARGET_64BIT) | |
3017 | { | |
3018 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3019 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
3020 | } | |
3021 | else | |
3022 | { | |
3023 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3024 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
3025 | } | |
3026 | emit_insn (insn); | |
3027 | } | |
3028 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
3029 | { | |
3030 | rtx tlsreg, tmp; | |
3031 | ||
3032 | tmp = gen_reg_rtx (Pmode); | |
3033 | if (TARGET_64BIT) | |
3034 | { | |
3035 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3036 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
3037 | } | |
3038 | else | |
3039 | { | |
3040 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3041 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
3042 | } | |
3043 | emit_insn (insn); | |
3044 | if (TARGET_64BIT) | |
3045 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
3046 | else | |
3047 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
3048 | emit_insn (insn); | |
3049 | } | |
3050 | else | |
3051 | { | |
3052 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
3053 | ||
4fed8f8f AM |
3054 | /* We currently use relocations like @got@tlsgd for tls, which |
3055 | means the linker will handle allocation of tls entries, placing | |
3056 | them in the .got section. So use a pointer to the .got section, | |
3057 | not one to secondary TOC sections used by 64-bit -mminimal-toc, | |
3058 | or to secondary GOT sections used by 32-bit -fPIC. */ | |
c4501e62 | 3059 | if (TARGET_64BIT) |
972f427b | 3060 | got = gen_rtx_REG (Pmode, 2); |
c4501e62 JJ |
3061 | else |
3062 | { | |
3063 | if (flag_pic == 1) | |
3064 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
3065 | else | |
3066 | { | |
3067 | rtx gsym = rs6000_got_sym (); | |
3068 | got = gen_reg_rtx (Pmode); | |
3069 | if (flag_pic == 0) | |
3070 | rs6000_emit_move (got, gsym, Pmode); | |
3071 | else | |
3072 | { | |
ccbca5e4 | 3073 | rtx tempLR, tmp3, mem; |
c4501e62 JJ |
3074 | rtx first, last; |
3075 | ||
c4501e62 JJ |
3076 | tempLR = gen_reg_rtx (Pmode); |
3077 | tmp1 = gen_reg_rtx (Pmode); | |
3078 | tmp2 = gen_reg_rtx (Pmode); | |
3079 | tmp3 = gen_reg_rtx (Pmode); | |
542a8afa | 3080 | mem = gen_const_mem (Pmode, tmp1); |
c4501e62 | 3081 | |
ccbca5e4 | 3082 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym)); |
c4501e62 JJ |
3083 | emit_move_insn (tmp1, tempLR); |
3084 | emit_move_insn (tmp2, mem); | |
3085 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
3086 | last = emit_move_insn (got, tmp3); | |
3087 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
3088 | REG_NOTES (last)); | |
3089 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
3090 | REG_NOTES (first)); | |
3091 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
3092 | REG_NOTES (last)); | |
3093 | } | |
3094 | } | |
3095 | } | |
3096 | ||
3097 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
3098 | { | |
3099 | r3 = gen_rtx_REG (Pmode, 3); | |
3100 | if (TARGET_64BIT) | |
3101 | insn = gen_tls_gd_64 (r3, got, addr); | |
3102 | else | |
3103 | insn = gen_tls_gd_32 (r3, got, addr); | |
3104 | start_sequence (); | |
3105 | emit_insn (insn); | |
3106 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3107 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3108 | insn = emit_call_insn (insn); | |
3109 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3110 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3111 | insn = get_insns (); | |
3112 | end_sequence (); | |
3113 | emit_libcall_block (insn, dest, r3, addr); | |
3114 | } | |
3115 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
3116 | { | |
3117 | r3 = gen_rtx_REG (Pmode, 3); | |
3118 | if (TARGET_64BIT) | |
3119 | insn = gen_tls_ld_64 (r3, got); | |
3120 | else | |
3121 | insn = gen_tls_ld_32 (r3, got); | |
3122 | start_sequence (); | |
3123 | emit_insn (insn); | |
3124 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3125 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3126 | insn = emit_call_insn (insn); | |
3127 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3128 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3129 | insn = get_insns (); | |
3130 | end_sequence (); | |
3131 | tmp1 = gen_reg_rtx (Pmode); | |
3132 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
3133 | UNSPEC_TLSLD); | |
3134 | emit_libcall_block (insn, tmp1, r3, eqv); | |
3135 | if (rs6000_tls_size == 16) | |
3136 | { | |
3137 | if (TARGET_64BIT) | |
3138 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
3139 | else | |
3140 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
3141 | } | |
3142 | else if (rs6000_tls_size == 32) | |
3143 | { | |
3144 | tmp2 = gen_reg_rtx (Pmode); | |
3145 | if (TARGET_64BIT) | |
3146 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
3147 | else | |
3148 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
3149 | emit_insn (insn); | |
3150 | if (TARGET_64BIT) | |
3151 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
3152 | else | |
3153 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
3154 | } | |
3155 | else | |
3156 | { | |
3157 | tmp2 = gen_reg_rtx (Pmode); | |
3158 | if (TARGET_64BIT) | |
3159 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
3160 | else | |
3161 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
3162 | emit_insn (insn); | |
3163 | insn = gen_rtx_SET (Pmode, dest, | |
3164 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
3165 | } | |
3166 | emit_insn (insn); | |
3167 | } | |
3168 | else | |
3169 | { | |
3170 | /* IE, or 64 bit offset LE. */ | |
3171 | tmp2 = gen_reg_rtx (Pmode); | |
3172 | if (TARGET_64BIT) | |
3173 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
3174 | else | |
3175 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
3176 | emit_insn (insn); | |
3177 | if (TARGET_64BIT) | |
3178 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
3179 | else | |
3180 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
3181 | emit_insn (insn); | |
3182 | } | |
3183 | } | |
3184 | ||
3185 | return dest; | |
3186 | } | |
3187 | ||
c4501e62 JJ |
3188 | /* Return 1 if X contains a thread-local symbol. */ |
3189 | ||
3190 | bool | |
a2369ed3 | 3191 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 3192 | { |
cd413cab AP |
3193 | if (! TARGET_HAVE_TLS) |
3194 | return false; | |
3195 | ||
c4501e62 JJ |
3196 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
3197 | } | |
3198 | ||
3199 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
3200 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
3201 | ||
9390387d | 3202 | static int |
a2369ed3 | 3203 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
3204 | { |
3205 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
3206 | } | |
3207 | ||
24ea750e DJ |
3208 | /* The convention appears to be to define this wherever it is used. |
3209 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
3210 | is now used here. */ | |
3211 | #ifndef REG_MODE_OK_FOR_BASE_P | |
3212 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
3213 | #endif | |
3214 | ||
3215 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
3216 | replace the input X, or the original X if no replacement is called for. | |
3217 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
3218 | 0 if it should not. | |
3219 | ||
3220 | For RS/6000, we wish to handle large displacements off a base | |
3221 | register by splitting the addend across an addiu/addis and the mem insn. | |
3222 | This cuts number of extra insns needed from 3 to 1. | |
3223 | ||
3224 | On Darwin, we use this to generate code for floating point constants. | |
3225 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
3226 | The Darwin code is inside #if TARGET_MACHO because only then is | |
3227 | machopic_function_base_name() defined. */ | |
3228 | rtx | |
f676971a | 3229 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
c4ad648e AM |
3230 | int opnum, int type, |
3231 | int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e | 3232 | { |
f676971a | 3233 | /* We must recognize output that we have already generated ourselves. */ |
24ea750e DJ |
3234 | if (GET_CODE (x) == PLUS |
3235 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3236 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
3237 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3238 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3239 | { | |
3240 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3241 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3242 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3243 | *win = 1; |
3244 | return x; | |
3245 | } | |
3deb2758 | 3246 | |
24ea750e DJ |
3247 | #if TARGET_MACHO |
3248 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
3249 | && GET_CODE (x) == LO_SUM | |
3250 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3251 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
3252 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
3253 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
3254 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
3255 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
3256 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
3257 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
3258 | { | |
3259 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 3260 | floating point constant. */ |
24ea750e | 3261 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
c4ad648e AM |
3262 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3263 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3264 | *win = 1; |
3265 | return x; | |
3266 | } | |
3267 | #endif | |
4937d02d DE |
3268 | |
3269 | /* Force ld/std non-word aligned offset into base register by wrapping | |
3270 | in offset 0. */ | |
3271 | if (GET_CODE (x) == PLUS | |
3272 | && GET_CODE (XEXP (x, 0)) == REG | |
3273 | && REGNO (XEXP (x, 0)) < 32 | |
3274 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
3275 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3276 | && (INTVAL (XEXP (x, 1)) & 3) != 0 | |
78796ad5 | 3277 | && !ALTIVEC_VECTOR_MODE (mode) |
4937d02d DE |
3278 | && GET_MODE_SIZE (mode) >= UNITS_PER_WORD |
3279 | && TARGET_POWERPC64) | |
3280 | { | |
3281 | x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0)); | |
3282 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3283 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
3284 | opnum, (enum reload_type) type); | |
3285 | *win = 1; | |
3286 | return x; | |
3287 | } | |
3288 | ||
24ea750e DJ |
3289 | if (GET_CODE (x) == PLUS |
3290 | && GET_CODE (XEXP (x, 0)) == REG | |
3291 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
3292 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 3293 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 3294 | && !SPE_VECTOR_MODE (mode) |
54b695e7 AH |
3295 | && !(TARGET_E500_DOUBLE && (mode == DFmode |
3296 | || mode == DImode)) | |
78c875e8 | 3297 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
3298 | { |
3299 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
3300 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
3301 | HOST_WIDE_INT high | |
c4ad648e | 3302 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; |
24ea750e DJ |
3303 | |
3304 | /* Check for 32-bit overflow. */ | |
3305 | if (high + low != val) | |
c4ad648e | 3306 | { |
24ea750e DJ |
3307 | *win = 0; |
3308 | return x; | |
3309 | } | |
3310 | ||
3311 | /* Reload the high part into a base reg; leave the low part | |
c4ad648e | 3312 | in the mem directly. */ |
24ea750e DJ |
3313 | |
3314 | x = gen_rtx_PLUS (GET_MODE (x), | |
c4ad648e AM |
3315 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), |
3316 | GEN_INT (high)), | |
3317 | GEN_INT (low)); | |
24ea750e DJ |
3318 | |
3319 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3320 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3321 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3322 | *win = 1; |
3323 | return x; | |
3324 | } | |
4937d02d | 3325 | |
24ea750e | 3326 | if (GET_CODE (x) == SYMBOL_REF |
69ef87e2 | 3327 | && !ALTIVEC_VECTOR_MODE (mode) |
8308679f DE |
3328 | #if TARGET_MACHO |
3329 | && DEFAULT_ABI == ABI_DARWIN | |
a29077da | 3330 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
8308679f DE |
3331 | #else |
3332 | && DEFAULT_ABI == ABI_V4 | |
3333 | && !flag_pic | |
3334 | #endif | |
0d8c1c97 AM |
3335 | /* Don't do this for TFmode, since the result isn't offsettable. |
3336 | The same goes for DImode without 64-bit gprs. */ | |
3337 | && mode != TFmode | |
3338 | && (mode != DImode || TARGET_POWERPC64)) | |
24ea750e | 3339 | { |
8308679f | 3340 | #if TARGET_MACHO |
a29077da GK |
3341 | if (flag_pic) |
3342 | { | |
3343 | rtx offset = gen_rtx_CONST (Pmode, | |
3344 | gen_rtx_MINUS (Pmode, x, | |
11abc112 | 3345 | machopic_function_base_sym ())); |
a29077da GK |
3346 | x = gen_rtx_LO_SUM (GET_MODE (x), |
3347 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
3348 | gen_rtx_HIGH (Pmode, offset)), offset); | |
3349 | } | |
3350 | else | |
8308679f | 3351 | #endif |
a29077da | 3352 | x = gen_rtx_LO_SUM (GET_MODE (x), |
c4ad648e | 3353 | gen_rtx_HIGH (Pmode, x), x); |
a29077da | 3354 | |
24ea750e | 3355 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
3356 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3357 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3358 | *win = 1; |
3359 | return x; | |
3360 | } | |
4937d02d | 3361 | |
dec1f3aa DE |
3362 | /* Reload an offset address wrapped by an AND that represents the |
3363 | masking of the lower bits. Strip the outer AND and let reload | |
3364 | convert the offset address into an indirect address. */ | |
3365 | if (TARGET_ALTIVEC | |
3366 | && ALTIVEC_VECTOR_MODE (mode) | |
3367 | && GET_CODE (x) == AND | |
3368 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3369 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
3370 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3371 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3372 | && INTVAL (XEXP (x, 1)) == -16) | |
3373 | { | |
3374 | x = XEXP (x, 0); | |
3375 | *win = 1; | |
3376 | return x; | |
3377 | } | |
3378 | ||
24ea750e | 3379 | if (TARGET_TOC |
4d588c14 | 3380 | && constant_pool_expr_p (x) |
c1f11548 | 3381 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3382 | { |
3383 | (x) = create_TOC_reference (x); | |
3384 | *win = 1; | |
3385 | return x; | |
3386 | } | |
3387 | *win = 0; | |
3388 | return x; | |
f676971a | 3389 | } |
24ea750e | 3390 | |
258bfae2 FS |
3391 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3392 | that is a valid memory address for an instruction. | |
3393 | The MODE argument is the machine mode for the MEM expression | |
3394 | that wants to use this address. | |
3395 | ||
3396 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3397 | refers to a constant pool entry of an address (or the sum of it | |
3398 | plus a constant), a short (16-bit signed) constant plus a register, | |
3399 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3400 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3401 | we must ensure that both words are addressable or PowerPC64 with offset |
3402 | word aligned. | |
3403 | ||
3404 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
76d2b81d | 3405 | 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because |
258bfae2 FS |
3406 | adjacent memory cells are accessed by adding word-sized offsets |
3407 | during assembly output. */ | |
3408 | int | |
a2369ed3 | 3409 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 3410 | { |
850e8d3d DN |
3411 | /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ |
3412 | if (TARGET_ALTIVEC | |
3413 | && ALTIVEC_VECTOR_MODE (mode) | |
3414 | && GET_CODE (x) == AND | |
3415 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3416 | && INTVAL (XEXP (x, 1)) == -16) | |
3417 | x = XEXP (x, 0); | |
3418 | ||
c4501e62 JJ |
3419 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3420 | return 0; | |
4d588c14 | 3421 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3422 | return 1; |
3423 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3424 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3425 | && !SPE_VECTOR_MODE (mode) |
54b695e7 AH |
3426 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
3427 | && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) | |
258bfae2 | 3428 | && TARGET_UPDATE |
4d588c14 | 3429 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3430 | return 1; |
0c380712 | 3431 | if (rs6000_legitimate_small_data_p (mode, x)) |
258bfae2 | 3432 | return 1; |
4d588c14 | 3433 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3434 | return 1; |
3435 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3436 | if (! reg_ok_strict | |
3437 | && GET_CODE (x) == PLUS | |
3438 | && GET_CODE (XEXP (x, 0)) == REG | |
708d2456 | 3439 | && (XEXP (x, 0) == virtual_stack_vars_rtx |
c4ad648e | 3440 | || XEXP (x, 0) == arg_pointer_rtx) |
258bfae2 FS |
3441 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
3442 | return 1; | |
76d2b81d | 3443 | if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3444 | return 1; |
3445 | if (mode != TImode | |
76d2b81d | 3446 | && mode != TFmode |
a3170dc6 AH |
3447 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3448 | || TARGET_POWERPC64 | |
4d4cbc0e | 3449 | || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode)) |
258bfae2 | 3450 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3451 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3452 | return 1; |
4d588c14 | 3453 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3454 | return 1; |
3455 | return 0; | |
3456 | } | |
4d588c14 RH |
3457 | |
3458 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3459 | has an effect that depends on the machine mode it is used for. | |
3460 | ||
3461 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3462 | modes don't allow them) or is a pre-increment or decrement. | |
3463 | ||
3464 | ??? Except that due to conceptual problems in offsettable_address_p | |
3465 | we can't really report the problems of integral offsets. So leave | |
f676971a | 3466 | this assuming that the adjustable offset must be valid for the |
4d588c14 RH |
3467 | sub-words of a TFmode operand, which is what we had before. */ |
3468 | ||
3469 | bool | |
a2369ed3 | 3470 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
3471 | { |
3472 | switch (GET_CODE (addr)) | |
3473 | { | |
3474 | case PLUS: | |
3475 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3476 | { | |
3477 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3478 | return val + 12 + 0x8000 >= 0x10000; | |
3479 | } | |
3480 | break; | |
3481 | ||
3482 | case LO_SUM: | |
3483 | return true; | |
3484 | ||
3485 | case PRE_INC: | |
3486 | case PRE_DEC: | |
3487 | return TARGET_UPDATE; | |
3488 | ||
3489 | default: | |
3490 | break; | |
3491 | } | |
3492 | ||
3493 | return false; | |
3494 | } | |
d8ecbcdb AH |
3495 | |
3496 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
3497 | to hold something of mode MODE. | |
3498 | This is ordinarily the length in words of a value of mode MODE | |
3499 | but can be less for certain modes in special long registers. | |
3500 | ||
3501 | For the SPE, GPRs are 64 bits but only 32 bits are visible in | |
3502 | scalar instructions. The upper 32 bits are only available to the | |
3503 | SIMD instructions. | |
3504 | ||
3505 | POWER and PowerPC GPRs hold 32 bits worth; | |
3506 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
3507 | ||
3508 | int | |
3509 | rs6000_hard_regno_nregs (int regno, enum machine_mode mode) | |
3510 | { | |
3511 | if (FP_REGNO_P (regno)) | |
3512 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; | |
3513 | ||
4d4cbc0e AH |
3514 | if (TARGET_E500_DOUBLE && mode == DFmode) |
3515 | return 1; | |
3516 | ||
d8ecbcdb AH |
3517 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
3518 | return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; | |
3519 | ||
3520 | if (ALTIVEC_REGNO_P (regno)) | |
3521 | return | |
3522 | (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; | |
3523 | ||
3524 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3525 | } | |
2aa4498c AH |
3526 | |
3527 | /* Change register usage conditional on target flags. */ | |
3528 | void | |
3529 | rs6000_conditional_register_usage (void) | |
3530 | { | |
3531 | int i; | |
3532 | ||
3533 | /* Set MQ register fixed (already call_used) if not POWER | |
3534 | architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not | |
3535 | be allocated. */ | |
3536 | if (! TARGET_POWER) | |
3537 | fixed_regs[64] = 1; | |
3538 | ||
7c9ac5c0 | 3539 | /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */ |
2aa4498c AH |
3540 | if (TARGET_64BIT) |
3541 | fixed_regs[13] = call_used_regs[13] | |
3542 | = call_really_used_regs[13] = 1; | |
3543 | ||
3544 | /* Conditionally disable FPRs. */ | |
3545 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
3546 | for (i = 32; i < 64; i++) | |
3547 | fixed_regs[i] = call_used_regs[i] | |
c4ad648e | 3548 | = call_really_used_regs[i] = 1; |
2aa4498c | 3549 | |
7c9ac5c0 PH |
3550 | /* The TOC register is not killed across calls in a way that is |
3551 | visible to the compiler. */ | |
3552 | if (DEFAULT_ABI == ABI_AIX) | |
3553 | call_really_used_regs[2] = 0; | |
3554 | ||
2aa4498c AH |
3555 | if (DEFAULT_ABI == ABI_V4 |
3556 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3557 | && flag_pic == 2) | |
3558 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3559 | ||
3560 | if (DEFAULT_ABI == ABI_V4 | |
3561 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3562 | && flag_pic == 1) | |
3563 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3564 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3565 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3566 | ||
3567 | if (DEFAULT_ABI == ABI_DARWIN | |
3568 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
6d0a8091 | 3569 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] |
2aa4498c AH |
3570 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] |
3571 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3572 | ||
b4db40bf JJ |
3573 | if (TARGET_TOC && TARGET_MINIMAL_TOC) |
3574 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3575 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3576 | ||
2aa4498c AH |
3577 | if (TARGET_ALTIVEC) |
3578 | global_regs[VSCR_REGNO] = 1; | |
3579 | ||
3580 | if (TARGET_SPE) | |
3581 | { | |
3582 | global_regs[SPEFSCR_REGNO] = 1; | |
3583 | fixed_regs[FIXED_SCRATCH] | |
c4ad648e | 3584 | = call_used_regs[FIXED_SCRATCH] |
2aa4498c AH |
3585 | = call_really_used_regs[FIXED_SCRATCH] = 1; |
3586 | } | |
3587 | ||
3588 | if (! TARGET_ALTIVEC) | |
3589 | { | |
3590 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
3591 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
3592 | call_really_used_regs[VRSAVE_REGNO] = 1; | |
3593 | } | |
3594 | ||
3595 | if (TARGET_ALTIVEC_ABI) | |
3596 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) | |
3597 | call_used_regs[i] = call_really_used_regs[i] = 1; | |
3598 | } | |
fb4d4348 | 3599 | \f |
a4f6c312 SS |
3600 | /* Try to output insns to set TARGET equal to the constant C if it can |
3601 | be done in less than N insns. Do all computations in MODE. | |
3602 | Returns the place where the output has been placed if it can be | |
3603 | done and the insns have been emitted. If it would take more than N | |
3604 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
3605 | |
3606 | rtx | |
f676971a | 3607 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
a2369ed3 | 3608 | rtx source, int n ATTRIBUTE_UNUSED) |
2bfcf297 | 3609 | { |
af8cb5c5 | 3610 | rtx result, insn, set; |
2bfcf297 DB |
3611 | HOST_WIDE_INT c0, c1; |
3612 | ||
37409796 | 3613 | switch (mode) |
2bfcf297 | 3614 | { |
37409796 NS |
3615 | case QImode: |
3616 | case HImode: | |
2bfcf297 | 3617 | if (dest == NULL) |
c4ad648e | 3618 | dest = gen_reg_rtx (mode); |
2bfcf297 DB |
3619 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); |
3620 | return dest; | |
bb8df8a6 | 3621 | |
37409796 | 3622 | case SImode: |
af8cb5c5 | 3623 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
bb8df8a6 | 3624 | |
af8cb5c5 DE |
3625 | emit_insn (gen_rtx_SET (VOIDmode, result, |
3626 | GEN_INT (INTVAL (source) | |
3627 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
3628 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3629 | gen_rtx_IOR (SImode, result, | |
3630 | GEN_INT (INTVAL (source) & 0xffff)))); | |
3631 | result = dest; | |
37409796 NS |
3632 | break; |
3633 | ||
3634 | case DImode: | |
3635 | switch (GET_CODE (source)) | |
af8cb5c5 | 3636 | { |
37409796 | 3637 | case CONST_INT: |
af8cb5c5 DE |
3638 | c0 = INTVAL (source); |
3639 | c1 = -(c0 < 0); | |
37409796 | 3640 | break; |
bb8df8a6 | 3641 | |
37409796 | 3642 | case CONST_DOUBLE: |
2bfcf297 | 3643 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
3644 | c0 = CONST_DOUBLE_LOW (source); |
3645 | c1 = -(c0 < 0); | |
2bfcf297 | 3646 | #else |
af8cb5c5 DE |
3647 | c0 = CONST_DOUBLE_LOW (source); |
3648 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 3649 | #endif |
37409796 NS |
3650 | break; |
3651 | ||
3652 | default: | |
3653 | gcc_unreachable (); | |
af8cb5c5 | 3654 | } |
af8cb5c5 DE |
3655 | |
3656 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
37409796 NS |
3657 | break; |
3658 | ||
3659 | default: | |
3660 | gcc_unreachable (); | |
2bfcf297 | 3661 | } |
2bfcf297 | 3662 | |
af8cb5c5 DE |
3663 | insn = get_last_insn (); |
3664 | set = single_set (insn); | |
3665 | if (! CONSTANT_P (SET_SRC (set))) | |
3666 | set_unique_reg_note (insn, REG_EQUAL, source); | |
3667 | ||
3668 | return result; | |
2bfcf297 DB |
3669 | } |
3670 | ||
3671 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
3672 | fall back to a straight forward decomposition. We do this to avoid | |
3673 | exponential run times encountered when looking for longer sequences | |
3674 | with rs6000_emit_set_const. */ | |
3675 | static rtx | |
a2369ed3 | 3676 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
3677 | { |
3678 | if (!TARGET_POWERPC64) | |
3679 | { | |
3680 | rtx operand1, operand2; | |
3681 | ||
3682 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
3683 | DImode); | |
3684 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
3685 | DImode); | |
3686 | emit_move_insn (operand1, GEN_INT (c1)); | |
3687 | emit_move_insn (operand2, GEN_INT (c2)); | |
3688 | } | |
3689 | else | |
3690 | { | |
bc06712d | 3691 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 3692 | |
bc06712d | 3693 | ud1 = c1 & 0xffff; |
f921c9c9 | 3694 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 3695 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 3696 | c2 = c1 >> 32; |
2bfcf297 | 3697 | #endif |
bc06712d | 3698 | ud3 = c2 & 0xffff; |
f921c9c9 | 3699 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 3700 | |
f676971a | 3701 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
bc06712d | 3702 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) |
2bfcf297 | 3703 | { |
bc06712d | 3704 | if (ud1 & 0x8000) |
b78d48dd | 3705 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
3706 | else |
3707 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 3708 | } |
2bfcf297 | 3709 | |
f676971a | 3710 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
bc06712d | 3711 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) |
252b88f7 | 3712 | { |
bc06712d | 3713 | if (ud2 & 0x8000) |
f676971a | 3714 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) |
bc06712d | 3715 | - 0x80000000)); |
252b88f7 | 3716 | else |
bc06712d TR |
3717 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
3718 | if (ud1 != 0) | |
3719 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 3720 | } |
f676971a | 3721 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
bc06712d TR |
3722 | || (ud4 == 0 && ! (ud3 & 0x8000))) |
3723 | { | |
3724 | if (ud3 & 0x8000) | |
f676971a | 3725 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) |
bc06712d TR |
3726 | - 0x80000000)); |
3727 | else | |
3728 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
3729 | ||
3730 | if (ud2 != 0) | |
3731 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
3732 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
3733 | if (ud1 != 0) | |
3734 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3735 | } | |
f676971a | 3736 | else |
bc06712d TR |
3737 | { |
3738 | if (ud4 & 0x8000) | |
f676971a | 3739 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) |
bc06712d TR |
3740 | - 0x80000000)); |
3741 | else | |
3742 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
3743 | ||
3744 | if (ud3 != 0) | |
3745 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 3746 | |
bc06712d TR |
3747 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
3748 | if (ud2 != 0) | |
f676971a EC |
3749 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, |
3750 | GEN_INT (ud2 << 16))); | |
bc06712d TR |
3751 | if (ud1 != 0) |
3752 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3753 | } | |
3754 | } | |
2bfcf297 DB |
3755 | return dest; |
3756 | } | |
3757 | ||
76d2b81d DJ |
3758 | /* Helper for the following. Get rid of [r+r] memory refs |
3759 | in cases where it won't work (TImode, TFmode). */ | |
3760 | ||
3761 | static void | |
3762 | rs6000_eliminate_indexed_memrefs (rtx operands[2]) | |
3763 | { | |
3764 | if (GET_CODE (operands[0]) == MEM | |
3765 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
55aa0757 | 3766 | && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0)) |
76d2b81d DJ |
3767 | && ! reload_in_progress) |
3768 | operands[0] | |
3769 | = replace_equiv_address (operands[0], | |
3770 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
3771 | ||
3772 | if (GET_CODE (operands[1]) == MEM | |
3773 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
55aa0757 | 3774 | && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0)) |
76d2b81d DJ |
3775 | && ! reload_in_progress) |
3776 | operands[1] | |
3777 | = replace_equiv_address (operands[1], | |
3778 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
3779 | } | |
3780 | ||
fb4d4348 GK |
3781 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
3782 | void | |
a2369ed3 | 3783 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
3784 | { |
3785 | rtx operands[2]; | |
3786 | operands[0] = dest; | |
3787 | operands[1] = source; | |
f676971a | 3788 | |
fb4d4348 GK |
3789 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ |
3790 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3791 | && ! FLOAT_MODE_P (mode) | |
3792 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
3793 | { | |
3794 | /* FIXME. This should never happen. */ | |
3795 | /* Since it seems that it does, do the safe thing and convert | |
3796 | to a CONST_INT. */ | |
2496c7bd | 3797 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 | 3798 | } |
37409796 NS |
3799 | gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE |
3800 | || FLOAT_MODE_P (mode) | |
3801 | || ((CONST_DOUBLE_HIGH (operands[1]) != 0 | |
3802 | || CONST_DOUBLE_LOW (operands[1]) < 0) | |
3803 | && (CONST_DOUBLE_HIGH (operands[1]) != -1 | |
3804 | || CONST_DOUBLE_LOW (operands[1]) >= 0))); | |
bb8df8a6 | 3805 | |
c9e8cb32 DD |
3806 | /* Check if GCC is setting up a block move that will end up using FP |
3807 | registers as temporaries. We must make sure this is acceptable. */ | |
3808 | if (GET_CODE (operands[0]) == MEM | |
3809 | && GET_CODE (operands[1]) == MEM | |
3810 | && mode == DImode | |
41543739 GK |
3811 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
3812 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
3813 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
3814 | ? 32 : MEM_ALIGN (operands[0]))) | |
3815 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
f676971a | 3816 | ? 32 |
41543739 GK |
3817 | : MEM_ALIGN (operands[1])))) |
3818 | && ! MEM_VOLATILE_P (operands [0]) | |
3819 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 3820 | { |
41543739 GK |
3821 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
3822 | adjust_address (operands[1], SImode, 0)); | |
3823 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
3824 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
3825 | return; |
3826 | } | |
630d42a0 | 3827 | |
55aa0757 | 3828 | if (!no_new_pseudos && GET_CODE (operands[0]) == MEM |
c9dbf840 | 3829 | && !gpc_reg_operand (operands[1], mode)) |
f6219a5e | 3830 | operands[1] = force_reg (mode, operands[1]); |
a9098fd0 | 3831 | |
a3170dc6 AH |
3832 | if (mode == SFmode && ! TARGET_POWERPC |
3833 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 3834 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 3835 | { |
ffc14f31 GK |
3836 | int regnum; |
3837 | ||
3838 | if (reload_in_progress || reload_completed) | |
3839 | regnum = true_regnum (operands[1]); | |
3840 | else if (GET_CODE (operands[1]) == REG) | |
3841 | regnum = REGNO (operands[1]); | |
3842 | else | |
3843 | regnum = -1; | |
f676971a | 3844 | |
fb4d4348 GK |
3845 | /* If operands[1] is a register, on POWER it may have |
3846 | double-precision data in it, so truncate it to single | |
3847 | precision. */ | |
3848 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
3849 | { | |
3850 | rtx newreg; | |
3851 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
3852 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
3853 | operands[1] = newreg; | |
3854 | } | |
3855 | } | |
3856 | ||
c4501e62 JJ |
3857 | /* Recognize the case where operand[1] is a reference to thread-local |
3858 | data and load its address to a register. */ | |
84f52ebd | 3859 | if (rs6000_tls_referenced_p (operands[1])) |
c4501e62 | 3860 | { |
84f52ebd RH |
3861 | enum tls_model model; |
3862 | rtx tmp = operands[1]; | |
3863 | rtx addend = NULL; | |
3864 | ||
3865 | if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) | |
3866 | { | |
3867 | addend = XEXP (XEXP (tmp, 0), 1); | |
3868 | tmp = XEXP (XEXP (tmp, 0), 0); | |
3869 | } | |
3870 | ||
3871 | gcc_assert (GET_CODE (tmp) == SYMBOL_REF); | |
3872 | model = SYMBOL_REF_TLS_MODEL (tmp); | |
3873 | gcc_assert (model != 0); | |
3874 | ||
3875 | tmp = rs6000_legitimize_tls_address (tmp, model); | |
3876 | if (addend) | |
3877 | { | |
3878 | tmp = gen_rtx_PLUS (mode, tmp, addend); | |
3879 | tmp = force_operand (tmp, operands[0]); | |
3880 | } | |
3881 | operands[1] = tmp; | |
c4501e62 JJ |
3882 | } |
3883 | ||
8f4e6caf RH |
3884 | /* Handle the case where reload calls us with an invalid address. */ |
3885 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 3886 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
3887 | || ! nonimmediate_operand (operands[0], mode))) |
3888 | goto emit_set; | |
3889 | ||
a9baceb1 GK |
3890 | /* 128-bit constant floating-point values on Darwin should really be |
3891 | loaded as two parts. */ | |
3892 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
3893 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
3894 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) | |
3895 | { | |
3896 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
3897 | know how to get a DFmode SUBREG of a TFmode. */ | |
3898 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), | |
3899 | simplify_gen_subreg (DImode, operands[1], mode, 0), | |
3900 | DImode); | |
3901 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, | |
3902 | GET_MODE_SIZE (DImode)), | |
3903 | simplify_gen_subreg (DImode, operands[1], mode, | |
3904 | GET_MODE_SIZE (DImode)), | |
3905 | DImode); | |
3906 | return; | |
3907 | } | |
3908 | ||
fb4d4348 GK |
3909 | /* FIXME: In the long term, this switch statement should go away |
3910 | and be replaced by a sequence of tests based on things like | |
3911 | mode == Pmode. */ | |
3912 | switch (mode) | |
3913 | { | |
3914 | case HImode: | |
3915 | case QImode: | |
3916 | if (CONSTANT_P (operands[1]) | |
3917 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 3918 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3919 | break; |
3920 | ||
06f4e019 | 3921 | case TFmode: |
76d2b81d DJ |
3922 | rs6000_eliminate_indexed_memrefs (operands); |
3923 | /* fall through */ | |
3924 | ||
fb4d4348 GK |
3925 | case DFmode: |
3926 | case SFmode: | |
f676971a | 3927 | if (CONSTANT_P (operands[1]) |
fb4d4348 | 3928 | && ! easy_fp_constant (operands[1], mode)) |
a9098fd0 | 3929 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 3930 | break; |
f676971a | 3931 | |
0ac081f6 AH |
3932 | case V16QImode: |
3933 | case V8HImode: | |
3934 | case V4SFmode: | |
3935 | case V4SImode: | |
a3170dc6 AH |
3936 | case V4HImode: |
3937 | case V2SFmode: | |
3938 | case V2SImode: | |
00a892b8 | 3939 | case V1DImode: |
69ef87e2 | 3940 | if (CONSTANT_P (operands[1]) |
d744e06e | 3941 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
3942 | operands[1] = force_const_mem (mode, operands[1]); |
3943 | break; | |
f676971a | 3944 | |
fb4d4348 | 3945 | case SImode: |
a9098fd0 | 3946 | case DImode: |
fb4d4348 GK |
3947 | /* Use default pattern for address of ELF small data */ |
3948 | if (TARGET_ELF | |
a9098fd0 | 3949 | && mode == Pmode |
f607bc57 | 3950 | && DEFAULT_ABI == ABI_V4 |
f676971a | 3951 | && (GET_CODE (operands[1]) == SYMBOL_REF |
a9098fd0 GK |
3952 | || GET_CODE (operands[1]) == CONST) |
3953 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
3954 | { |
3955 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
3956 | return; | |
3957 | } | |
3958 | ||
f607bc57 | 3959 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
3960 | && mode == Pmode && mode == SImode |
3961 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
3962 | { |
3963 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
3964 | return; | |
3965 | } | |
3966 | ||
ee890fe2 | 3967 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
3968 | && TARGET_NO_TOC |
3969 | && ! flag_pic | |
a9098fd0 | 3970 | && mode == Pmode |
fb4d4348 GK |
3971 | && CONSTANT_P (operands[1]) |
3972 | && GET_CODE (operands[1]) != HIGH | |
3973 | && GET_CODE (operands[1]) != CONST_INT) | |
3974 | { | |
a9098fd0 | 3975 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
3976 | |
3977 | /* If this is a function address on -mcall-aixdesc, | |
3978 | convert it to the address of the descriptor. */ | |
3979 | if (DEFAULT_ABI == ABI_AIX | |
3980 | && GET_CODE (operands[1]) == SYMBOL_REF | |
3981 | && XSTR (operands[1], 0)[0] == '.') | |
3982 | { | |
3983 | const char *name = XSTR (operands[1], 0); | |
3984 | rtx new_ref; | |
3985 | while (*name == '.') | |
3986 | name++; | |
3987 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
3988 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
3989 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 3990 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 3991 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 3992 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
3993 | operands[1] = new_ref; |
3994 | } | |
7509c759 | 3995 | |
ee890fe2 SS |
3996 | if (DEFAULT_ABI == ABI_DARWIN) |
3997 | { | |
ab82a49f AP |
3998 | #if TARGET_MACHO |
3999 | if (MACHO_DYNAMIC_NO_PIC_P) | |
4000 | { | |
4001 | /* Take care of any required data indirection. */ | |
4002 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
4003 | operands[1], mode, operands[0]); | |
4004 | if (operands[0] != operands[1]) | |
4005 | emit_insn (gen_rtx_SET (VOIDmode, | |
c4ad648e | 4006 | operands[0], operands[1])); |
ab82a49f AP |
4007 | return; |
4008 | } | |
4009 | #endif | |
b8a55285 AP |
4010 | emit_insn (gen_macho_high (target, operands[1])); |
4011 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
ee890fe2 SS |
4012 | return; |
4013 | } | |
4014 | ||
fb4d4348 GK |
4015 | emit_insn (gen_elf_high (target, operands[1])); |
4016 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
4017 | return; | |
4018 | } | |
4019 | ||
a9098fd0 GK |
4020 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
4021 | and we have put it in the TOC, we just need to make a TOC-relative | |
4022 | reference to it. */ | |
4023 | if (TARGET_TOC | |
4024 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 4025 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
4026 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
4027 | get_pool_mode (operands[1]))) | |
fb4d4348 | 4028 | { |
a9098fd0 | 4029 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 4030 | } |
a9098fd0 GK |
4031 | else if (mode == Pmode |
4032 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
4033 | && ((GET_CODE (operands[1]) != CONST_INT |
4034 | && ! easy_fp_constant (operands[1], mode)) | |
4035 | || (GET_CODE (operands[1]) == CONST_INT | |
4036 | && num_insns_constant (operands[1], mode) > 2) | |
4037 | || (GET_CODE (operands[0]) == REG | |
4038 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 4039 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
4040 | && ! legitimate_constant_pool_address_p (operands[1]) |
4041 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
4042 | { |
4043 | /* Emit a USE operation so that the constant isn't deleted if | |
4044 | expensive optimizations are turned on because nobody | |
4045 | references it. This should only be done for operands that | |
4046 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
4047 | This should not be done for operands that contain LABEL_REFs. | |
4048 | For now, we just handle the obvious case. */ | |
4049 | if (GET_CODE (operands[1]) != LABEL_REF) | |
4050 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
4051 | ||
c859cda6 | 4052 | #if TARGET_MACHO |
ee890fe2 | 4053 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 4054 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 4055 | { |
ee890fe2 SS |
4056 | operands[1] = |
4057 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
4058 | operands[0]); |
4059 | if (operands[0] != operands[1]) | |
4060 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
4061 | return; |
4062 | } | |
c859cda6 | 4063 | #endif |
ee890fe2 | 4064 | |
fb4d4348 GK |
4065 | /* If we are to limit the number of things we put in the TOC and |
4066 | this is a symbol plus a constant we can add in one insn, | |
4067 | just put the symbol in the TOC and add the constant. Don't do | |
4068 | this if reload is in progress. */ | |
4069 | if (GET_CODE (operands[1]) == CONST | |
4070 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
4071 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 4072 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
4073 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
4074 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
4075 | && ! side_effects_p (operands[0])) | |
4076 | { | |
a4f6c312 SS |
4077 | rtx sym = |
4078 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
4079 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
4080 | ||
a9098fd0 GK |
4081 | sym = force_reg (mode, sym); |
4082 | if (mode == SImode) | |
4083 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
4084 | else | |
4085 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
4086 | return; |
4087 | } | |
4088 | ||
a9098fd0 | 4089 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 4090 | |
f676971a | 4091 | if (TARGET_TOC |
4d588c14 | 4092 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
4093 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
4094 | get_pool_constant (XEXP (operands[1], 0)), | |
4095 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 4096 | { |
ba4828e0 | 4097 | operands[1] |
542a8afa | 4098 | = gen_const_mem (mode, |
c4ad648e | 4099 | create_TOC_reference (XEXP (operands[1], 0))); |
ba4828e0 | 4100 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); |
a9098fd0 | 4101 | } |
fb4d4348 GK |
4102 | } |
4103 | break; | |
a9098fd0 | 4104 | |
fb4d4348 | 4105 | case TImode: |
76d2b81d DJ |
4106 | rs6000_eliminate_indexed_memrefs (operands); |
4107 | ||
27dc0551 DE |
4108 | if (TARGET_POWER) |
4109 | { | |
4110 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
4111 | gen_rtvec (2, | |
4112 | gen_rtx_SET (VOIDmode, | |
4113 | operands[0], operands[1]), | |
4114 | gen_rtx_CLOBBER (VOIDmode, | |
4115 | gen_rtx_SCRATCH (SImode))))); | |
4116 | return; | |
4117 | } | |
fb4d4348 GK |
4118 | break; |
4119 | ||
4120 | default: | |
37409796 | 4121 | gcc_unreachable (); |
fb4d4348 GK |
4122 | } |
4123 | ||
a9098fd0 GK |
4124 | /* Above, we may have called force_const_mem which may have returned |
4125 | an invalid address. If we can, fix this up; otherwise, reload will | |
4126 | have to deal with it. */ | |
8f4e6caf RH |
4127 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
4128 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 4129 | |
8f4e6caf | 4130 | emit_set: |
fb4d4348 GK |
4131 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
4132 | } | |
4697a36c | 4133 | \f |
2858f73a GK |
4134 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
4135 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
ebb109ad | 4136 | (SCALAR_FLOAT_MODE_P (MODE) \ |
2858f73a GK |
4137 | && (CUM)->fregno <= FP_ARG_MAX_REG \ |
4138 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
4139 | ||
4140 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
4141 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
4142 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
4143 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
4144 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 4145 | && (NAMED)) |
2858f73a | 4146 | |
c6e8c921 GK |
4147 | /* Return a nonzero value to say to return the function value in |
4148 | memory, just as large structures are always returned. TYPE will be | |
4149 | the data type of the value, and FNTYPE will be the type of the | |
4150 | function doing the returning, or @code{NULL} for libcalls. | |
4151 | ||
4152 | The AIX ABI for the RS/6000 specifies that all structures are | |
4153 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
4154 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
4155 | draft put them in memory, and GCC used to implement the draft | |
df01da37 | 4156 | instead of the final standard. Therefore, aix_struct_return |
c6e8c921 GK |
4157 | controls this instead of DEFAULT_ABI; V.4 targets needing backward |
4158 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
4159 | default, and -m switches get the final word. See | |
4160 | rs6000_override_options for more details. | |
4161 | ||
4162 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
4163 | long double support is enabled. These values are returned in memory. | |
4164 | ||
4165 | int_size_in_bytes returns -1 for variable size objects, which go in | |
4166 | memory always. The cast to unsigned makes -1 > 8. */ | |
4167 | ||
4168 | static bool | |
4169 | rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
4170 | { | |
594a51fe SS |
4171 | /* In the darwin64 abi, try to use registers for larger structs |
4172 | if possible. */ | |
0b5383eb | 4173 | if (rs6000_darwin64_abi |
594a51fe | 4174 | && TREE_CODE (type) == RECORD_TYPE |
0b5383eb DJ |
4175 | && int_size_in_bytes (type) > 0) |
4176 | { | |
4177 | CUMULATIVE_ARGS valcum; | |
4178 | rtx valret; | |
4179 | ||
4180 | valcum.words = 0; | |
4181 | valcum.fregno = FP_ARG_MIN_REG; | |
4182 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
4183 | /* Do a trial code generation as if this were going to be passed | |
4184 | as an argument; if any part goes in memory, we return NULL. */ | |
4185 | valret = rs6000_darwin64_record_arg (&valcum, type, 1, true); | |
4186 | if (valret) | |
4187 | return false; | |
4188 | /* Otherwise fall through to more conventional ABI rules. */ | |
4189 | } | |
594a51fe | 4190 | |
c6e8c921 | 4191 | if (AGGREGATE_TYPE_P (type) |
df01da37 | 4192 | && (aix_struct_return |
c6e8c921 GK |
4193 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) |
4194 | return true; | |
b693336b | 4195 | |
bada2eb8 DE |
4196 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector |
4197 | modes only exist for GCC vector types if -maltivec. */ | |
4198 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI | |
4199 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
4200 | return false; | |
4201 | ||
b693336b PB |
4202 | /* Return synthetic vectors in memory. */ |
4203 | if (TREE_CODE (type) == VECTOR_TYPE | |
ad630bef | 4204 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
4205 | { |
4206 | static bool warned_for_return_big_vectors = false; | |
4207 | if (!warned_for_return_big_vectors) | |
4208 | { | |
d4ee4d25 | 4209 | warning (0, "GCC vector returned by reference: " |
b693336b PB |
4210 | "non-standard ABI extension with no compatibility guarantee"); |
4211 | warned_for_return_big_vectors = true; | |
4212 | } | |
4213 | return true; | |
4214 | } | |
4215 | ||
c6e8c921 GK |
4216 | if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode) |
4217 | return true; | |
ad630bef | 4218 | |
c6e8c921 GK |
4219 | return false; |
4220 | } | |
4221 | ||
4697a36c MM |
4222 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
4223 | for a call to a function whose data type is FNTYPE. | |
4224 | For a library call, FNTYPE is 0. | |
4225 | ||
4226 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 4227 | so we never return a PARALLEL. */ |
4697a36c MM |
4228 | |
4229 | void | |
f676971a | 4230 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
4231 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
4232 | int libcall, int n_named_args) | |
4697a36c MM |
4233 | { |
4234 | static CUMULATIVE_ARGS zero_cumulative; | |
4235 | ||
4236 | *cum = zero_cumulative; | |
4237 | cum->words = 0; | |
4238 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 4239 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 4240 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
4241 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
4242 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 4243 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
4244 | cum->stdarg = fntype |
4245 | && (TYPE_ARG_TYPES (fntype) != 0 | |
4246 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
4247 | != void_type_node)); | |
4697a36c | 4248 | |
0f6937fe AM |
4249 | cum->nargs_prototype = 0; |
4250 | if (incoming || cum->prototype) | |
4251 | cum->nargs_prototype = n_named_args; | |
4697a36c | 4252 | |
a5c76ee6 | 4253 | /* Check for a longcall attribute. */ |
3eb4e360 AM |
4254 | if ((!fntype && rs6000_default_long_calls) |
4255 | || (fntype | |
4256 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
4257 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))) | |
4258 | cum->call_cookie |= CALL_LONG; | |
6a4cee5f | 4259 | |
4697a36c MM |
4260 | if (TARGET_DEBUG_ARG) |
4261 | { | |
4262 | fprintf (stderr, "\ninit_cumulative_args:"); | |
4263 | if (fntype) | |
4264 | { | |
4265 | tree ret_type = TREE_TYPE (fntype); | |
4266 | fprintf (stderr, " ret code = %s,", | |
4267 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
4268 | } | |
4269 | ||
6a4cee5f MM |
4270 | if (cum->call_cookie & CALL_LONG) |
4271 | fprintf (stderr, " longcall,"); | |
4272 | ||
4697a36c MM |
4273 | fprintf (stderr, " proto = %d, nargs = %d\n", |
4274 | cum->prototype, cum->nargs_prototype); | |
4275 | } | |
f676971a | 4276 | |
c4ad648e AM |
4277 | if (fntype |
4278 | && !TARGET_ALTIVEC | |
4279 | && TARGET_ALTIVEC_ABI | |
4280 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) | |
4281 | { | |
c85ce869 | 4282 | error ("cannot return value in vector register because" |
c4ad648e | 4283 | " altivec instructions are disabled, use -maltivec" |
c85ce869 | 4284 | " to enable them"); |
c4ad648e | 4285 | } |
4697a36c MM |
4286 | } |
4287 | \f | |
fe984136 RH |
4288 | /* Return true if TYPE must be passed on the stack and not in registers. */ |
4289 | ||
4290 | static bool | |
4291 | rs6000_must_pass_in_stack (enum machine_mode mode, tree type) | |
4292 | { | |
4293 | if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT) | |
4294 | return must_pass_in_stack_var_size (mode, type); | |
4295 | else | |
4296 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
4297 | } | |
4298 | ||
c229cba9 DE |
4299 | /* If defined, a C expression which determines whether, and in which |
4300 | direction, to pad out an argument with extra space. The value | |
4301 | should be of type `enum direction': either `upward' to pad above | |
4302 | the argument, `downward' to pad below, or `none' to inhibit | |
4303 | padding. | |
4304 | ||
4305 | For the AIX ABI structs are always stored left shifted in their | |
4306 | argument slot. */ | |
4307 | ||
9ebbca7d | 4308 | enum direction |
a2369ed3 | 4309 | function_arg_padding (enum machine_mode mode, tree type) |
c229cba9 | 4310 | { |
6e985040 AM |
4311 | #ifndef AGGREGATE_PADDING_FIXED |
4312 | #define AGGREGATE_PADDING_FIXED 0 | |
4313 | #endif | |
4314 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
4315 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
4316 | #endif | |
4317 | ||
4318 | if (!AGGREGATE_PADDING_FIXED) | |
4319 | { | |
4320 | /* GCC used to pass structures of the same size as integer types as | |
4321 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
19525b57 | 4322 | i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were |
6e985040 AM |
4323 | passed padded downward, except that -mstrict-align further |
4324 | muddied the water in that multi-component structures of 2 and 4 | |
4325 | bytes in size were passed padded upward. | |
4326 | ||
4327 | The following arranges for best compatibility with previous | |
4328 | versions of gcc, but removes the -mstrict-align dependency. */ | |
4329 | if (BYTES_BIG_ENDIAN) | |
4330 | { | |
4331 | HOST_WIDE_INT size = 0; | |
4332 | ||
4333 | if (mode == BLKmode) | |
4334 | { | |
4335 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
4336 | size = int_size_in_bytes (type); | |
4337 | } | |
4338 | else | |
4339 | size = GET_MODE_SIZE (mode); | |
4340 | ||
4341 | if (size == 1 || size == 2 || size == 4) | |
4342 | return downward; | |
4343 | } | |
4344 | return upward; | |
4345 | } | |
4346 | ||
4347 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
4348 | { | |
4349 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
4350 | return upward; | |
4351 | } | |
c229cba9 | 4352 | |
d3704c46 KH |
4353 | /* Fall back to the default. */ |
4354 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
4355 | } |
4356 | ||
b6c9286a | 4357 | /* If defined, a C expression that gives the alignment boundary, in bits, |
f676971a | 4358 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a | 4359 | PARM_BOUNDARY is used for all arguments. |
f676971a | 4360 | |
b693336b PB |
4361 | V.4 wants long longs to be double word aligned. |
4362 | Doubleword align SPE vectors. | |
4363 | Quadword align Altivec vectors. | |
4364 | Quadword align large synthetic vector types. */ | |
b6c9286a MM |
4365 | |
4366 | int | |
b693336b | 4367 | function_arg_boundary (enum machine_mode mode, tree type) |
b6c9286a | 4368 | { |
4ed78545 AM |
4369 | if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8) |
4370 | return 64; | |
ad630bef DE |
4371 | else if (SPE_VECTOR_MODE (mode) |
4372 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4373 | && int_size_in_bytes (type) >= 8 | |
4374 | && int_size_in_bytes (type) < 16)) | |
e1f83b4d | 4375 | return 64; |
ad630bef DE |
4376 | else if (ALTIVEC_VECTOR_MODE (mode) |
4377 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4378 | && int_size_in_bytes (type) >= 16)) | |
0ac081f6 | 4379 | return 128; |
0b5383eb DJ |
4380 | else if (rs6000_darwin64_abi && mode == BLKmode |
4381 | && type && TYPE_ALIGN (type) > 64) | |
4382 | return 128; | |
9ebbca7d | 4383 | else |
b6c9286a | 4384 | return PARM_BOUNDARY; |
b6c9286a | 4385 | } |
c53bdcf5 | 4386 | |
294bd182 AM |
4387 | /* For a function parm of MODE and TYPE, return the starting word in |
4388 | the parameter area. NWORDS of the parameter area are already used. */ | |
4389 | ||
4390 | static unsigned int | |
4391 | rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords) | |
4392 | { | |
4393 | unsigned int align; | |
4394 | unsigned int parm_offset; | |
4395 | ||
4396 | align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; | |
4397 | parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6; | |
4398 | return nwords + (-(parm_offset + nwords) & align); | |
4399 | } | |
4400 | ||
c53bdcf5 AM |
4401 | /* Compute the size (in words) of a function argument. */ |
4402 | ||
4403 | static unsigned long | |
4404 | rs6000_arg_size (enum machine_mode mode, tree type) | |
4405 | { | |
4406 | unsigned long size; | |
4407 | ||
4408 | if (mode != BLKmode) | |
4409 | size = GET_MODE_SIZE (mode); | |
4410 | else | |
4411 | size = int_size_in_bytes (type); | |
4412 | ||
4413 | if (TARGET_32BIT) | |
4414 | return (size + 3) >> 2; | |
4415 | else | |
4416 | return (size + 7) >> 3; | |
4417 | } | |
b6c9286a | 4418 | \f |
0b5383eb | 4419 | /* Use this to flush pending int fields. */ |
594a51fe SS |
4420 | |
4421 | static void | |
0b5383eb DJ |
4422 | rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum, |
4423 | HOST_WIDE_INT bitpos) | |
594a51fe | 4424 | { |
0b5383eb DJ |
4425 | unsigned int startbit, endbit; |
4426 | int intregs, intoffset; | |
4427 | enum machine_mode mode; | |
594a51fe | 4428 | |
0b5383eb DJ |
4429 | if (cum->intoffset == -1) |
4430 | return; | |
594a51fe | 4431 | |
0b5383eb DJ |
4432 | intoffset = cum->intoffset; |
4433 | cum->intoffset = -1; | |
4434 | ||
4435 | if (intoffset % BITS_PER_WORD != 0) | |
4436 | { | |
4437 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, | |
4438 | MODE_INT, 0); | |
4439 | if (mode == BLKmode) | |
594a51fe | 4440 | { |
0b5383eb DJ |
4441 | /* We couldn't find an appropriate mode, which happens, |
4442 | e.g., in packed structs when there are 3 bytes to load. | |
4443 | Back intoffset back to the beginning of the word in this | |
4444 | case. */ | |
4445 | intoffset = intoffset & -BITS_PER_WORD; | |
594a51fe | 4446 | } |
594a51fe | 4447 | } |
0b5383eb DJ |
4448 | |
4449 | startbit = intoffset & -BITS_PER_WORD; | |
4450 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4451 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
4452 | cum->words += intregs; | |
4453 | } | |
4454 | ||
4455 | /* The darwin64 ABI calls for us to recurse down through structs, | |
4456 | looking for elements passed in registers. Unfortunately, we have | |
4457 | to track int register count here also because of misalignments | |
4458 | in powerpc alignment mode. */ | |
4459 | ||
4460 | static void | |
4461 | rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum, | |
4462 | tree type, | |
4463 | HOST_WIDE_INT startbitpos) | |
4464 | { | |
4465 | tree f; | |
4466 | ||
4467 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
4468 | if (TREE_CODE (f) == FIELD_DECL) | |
4469 | { | |
4470 | HOST_WIDE_INT bitpos = startbitpos; | |
4471 | tree ftype = TREE_TYPE (f); | |
4472 | enum machine_mode mode = TYPE_MODE (ftype); | |
4473 | ||
4474 | if (DECL_SIZE (f) != 0 | |
4475 | && host_integerp (bit_position (f), 1)) | |
4476 | bitpos += int_bit_position (f); | |
4477 | ||
4478 | /* ??? FIXME: else assume zero offset. */ | |
4479 | ||
4480 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
4481 | rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos); | |
4482 | else if (USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
4483 | { | |
4484 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
4485 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; | |
4486 | cum->words += (GET_MODE_SIZE (mode) + 7) >> 3; | |
4487 | } | |
4488 | else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1)) | |
4489 | { | |
4490 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
4491 | cum->vregno++; | |
4492 | cum->words += 2; | |
4493 | } | |
4494 | else if (cum->intoffset == -1) | |
4495 | cum->intoffset = bitpos; | |
4496 | } | |
594a51fe SS |
4497 | } |
4498 | ||
4697a36c MM |
4499 | /* Update the data in CUM to advance over an argument |
4500 | of mode MODE and data type TYPE. | |
b2d04ecf AM |
4501 | (TYPE is null for libcalls where that information may not be available.) |
4502 | ||
4503 | Note that for args passed by reference, function_arg will be called | |
4504 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4505 | itself. */ | |
4697a36c MM |
4506 | |
4507 | void | |
f676971a | 4508 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
594a51fe | 4509 | tree type, int named, int depth) |
4697a36c | 4510 | { |
0b5383eb DJ |
4511 | int size; |
4512 | ||
594a51fe SS |
4513 | /* Only tick off an argument if we're not recursing. */ |
4514 | if (depth == 0) | |
4515 | cum->nargs_prototype--; | |
4697a36c | 4516 | |
ad630bef DE |
4517 | if (TARGET_ALTIVEC_ABI |
4518 | && (ALTIVEC_VECTOR_MODE (mode) | |
4519 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4520 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 4521 | { |
4ed78545 AM |
4522 | bool stack = false; |
4523 | ||
2858f73a | 4524 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c4ad648e | 4525 | { |
6d0ef01e HP |
4526 | cum->vregno++; |
4527 | if (!TARGET_ALTIVEC) | |
c85ce869 | 4528 | error ("cannot pass argument in vector register because" |
6d0ef01e | 4529 | " altivec instructions are disabled, use -maltivec" |
c85ce869 | 4530 | " to enable them"); |
4ed78545 AM |
4531 | |
4532 | /* PowerPC64 Linux and AIX allocate GPRs for a vector argument | |
f676971a | 4533 | even if it is going to be passed in a vector register. |
4ed78545 AM |
4534 | Darwin does the same for variable-argument functions. */ |
4535 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4536 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
4537 | stack = true; | |
6d0ef01e | 4538 | } |
4ed78545 AM |
4539 | else |
4540 | stack = true; | |
4541 | ||
4542 | if (stack) | |
c4ad648e | 4543 | { |
a594a19c | 4544 | int align; |
f676971a | 4545 | |
2858f73a GK |
4546 | /* Vector parameters must be 16-byte aligned. This places |
4547 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
4548 | the parameter save area starts at offset 24 from the | |
4549 | stack. In 64-bit mode, they just have to start on an | |
4550 | even word, since the parameter save area is 16-byte | |
4551 | aligned. Space for GPRs is reserved even if the argument | |
4552 | will be passed in memory. */ | |
4553 | if (TARGET_32BIT) | |
4ed78545 | 4554 | align = (2 - cum->words) & 3; |
2858f73a GK |
4555 | else |
4556 | align = cum->words & 1; | |
c53bdcf5 | 4557 | cum->words += align + rs6000_arg_size (mode, type); |
f676971a | 4558 | |
a594a19c GK |
4559 | if (TARGET_DEBUG_ARG) |
4560 | { | |
f676971a | 4561 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", |
a594a19c GK |
4562 | cum->words, align); |
4563 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
f676971a | 4564 | cum->nargs_prototype, cum->prototype, |
2858f73a | 4565 | GET_MODE_NAME (mode)); |
a594a19c GK |
4566 | } |
4567 | } | |
0ac081f6 | 4568 | } |
a4b0320c | 4569 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
4570 | && !cum->stdarg |
4571 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 4572 | cum->sysv_gregno++; |
594a51fe SS |
4573 | |
4574 | else if (rs6000_darwin64_abi | |
4575 | && mode == BLKmode | |
0b5383eb DJ |
4576 | && TREE_CODE (type) == RECORD_TYPE |
4577 | && (size = int_size_in_bytes (type)) > 0) | |
4578 | { | |
4579 | /* Variable sized types have size == -1 and are | |
4580 | treated as if consisting entirely of ints. | |
4581 | Pad to 16 byte boundary if needed. */ | |
4582 | if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
4583 | && (cum->words % 2) != 0) | |
4584 | cum->words++; | |
4585 | /* For varargs, we can just go up by the size of the struct. */ | |
4586 | if (!named) | |
4587 | cum->words += (size + 7) / 8; | |
4588 | else | |
4589 | { | |
4590 | /* It is tempting to say int register count just goes up by | |
4591 | sizeof(type)/8, but this is wrong in a case such as | |
4592 | { int; double; int; } [powerpc alignment]. We have to | |
4593 | grovel through the fields for these too. */ | |
4594 | cum->intoffset = 0; | |
4595 | rs6000_darwin64_record_arg_advance_recurse (cum, type, 0); | |
bb8df8a6 | 4596 | rs6000_darwin64_record_arg_advance_flush (cum, |
0b5383eb DJ |
4597 | size * BITS_PER_UNIT); |
4598 | } | |
4599 | } | |
f607bc57 | 4600 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4601 | { |
a3170dc6 | 4602 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 4603 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 4604 | { |
4cc833b7 RH |
4605 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
4606 | cum->fregno++; | |
4607 | else | |
4608 | { | |
4609 | if (mode == DFmode) | |
c4ad648e | 4610 | cum->words += cum->words & 1; |
c53bdcf5 | 4611 | cum->words += rs6000_arg_size (mode, type); |
4cc833b7 | 4612 | } |
4697a36c | 4613 | } |
4cc833b7 RH |
4614 | else |
4615 | { | |
b2d04ecf | 4616 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4617 | int gregno = cum->sysv_gregno; |
4618 | ||
4ed78545 AM |
4619 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4620 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4621 | as complex int due to a historical mistake. */ | |
4622 | if (n_words == 2) | |
4623 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4624 | |
4ed78545 | 4625 | /* Multi-reg args are not split between registers and stack. */ |
4cc833b7 RH |
4626 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
4627 | { | |
4ed78545 AM |
4628 | /* Long long and SPE vectors are aligned on the stack. |
4629 | So are other 2 word items such as complex int due to | |
4630 | a historical mistake. */ | |
4cc833b7 RH |
4631 | if (n_words == 2) |
4632 | cum->words += cum->words & 1; | |
4633 | cum->words += n_words; | |
4634 | } | |
4697a36c | 4635 | |
4cc833b7 RH |
4636 | /* Note: continuing to accumulate gregno past when we've started |
4637 | spilling to the stack indicates the fact that we've started | |
4638 | spilling to the stack to expand_builtin_saveregs. */ | |
4639 | cum->sysv_gregno = gregno + n_words; | |
4640 | } | |
4697a36c | 4641 | |
4cc833b7 RH |
4642 | if (TARGET_DEBUG_ARG) |
4643 | { | |
4644 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4645 | cum->words, cum->fregno); | |
4646 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
4647 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
4648 | fprintf (stderr, "mode = %4s, named = %d\n", | |
4649 | GET_MODE_NAME (mode), named); | |
4650 | } | |
4697a36c MM |
4651 | } |
4652 | else | |
4cc833b7 | 4653 | { |
b2d04ecf | 4654 | int n_words = rs6000_arg_size (mode, type); |
294bd182 AM |
4655 | int start_words = cum->words; |
4656 | int align_words = rs6000_parm_start (mode, type, start_words); | |
a4f6c312 | 4657 | |
294bd182 | 4658 | cum->words = align_words + n_words; |
4697a36c | 4659 | |
ebb109ad | 4660 | if (SCALAR_FLOAT_MODE_P (mode) |
a3170dc6 | 4661 | && TARGET_HARD_FLOAT && TARGET_FPRS) |
c53bdcf5 | 4662 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; |
4cc833b7 RH |
4663 | |
4664 | if (TARGET_DEBUG_ARG) | |
4665 | { | |
4666 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4667 | cum->words, cum->fregno); | |
4668 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
4669 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
594a51fe | 4670 | fprintf (stderr, "named = %d, align = %d, depth = %d\n", |
294bd182 | 4671 | named, align_words - start_words, depth); |
4cc833b7 RH |
4672 | } |
4673 | } | |
4697a36c | 4674 | } |
a6c9bed4 | 4675 | |
f82f556d AH |
4676 | static rtx |
4677 | spe_build_register_parallel (enum machine_mode mode, int gregno) | |
4678 | { | |
54b695e7 | 4679 | rtx r1, r3; |
f82f556d | 4680 | |
37409796 | 4681 | switch (mode) |
f82f556d | 4682 | { |
37409796 | 4683 | case DFmode: |
54b695e7 AH |
4684 | r1 = gen_rtx_REG (DImode, gregno); |
4685 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
4686 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1)); | |
37409796 NS |
4687 | |
4688 | case DCmode: | |
54b695e7 AH |
4689 | r1 = gen_rtx_REG (DImode, gregno); |
4690 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
4691 | r3 = gen_rtx_REG (DImode, gregno + 2); | |
4692 | r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8)); | |
4693 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3)); | |
37409796 NS |
4694 | |
4695 | default: | |
4696 | gcc_unreachable (); | |
f82f556d | 4697 | } |
f82f556d | 4698 | } |
b78d48dd | 4699 | |
f82f556d | 4700 | /* Determine where to put a SIMD argument on the SPE. */ |
a6c9bed4 | 4701 | static rtx |
f676971a | 4702 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 4703 | tree type) |
a6c9bed4 | 4704 | { |
f82f556d AH |
4705 | int gregno = cum->sysv_gregno; |
4706 | ||
4707 | /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but | |
600e1f95 | 4708 | are passed and returned in a pair of GPRs for ABI compatibility. */ |
18f63bfa | 4709 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode)) |
f82f556d | 4710 | { |
b5870bee AH |
4711 | int n_words = rs6000_arg_size (mode, type); |
4712 | ||
f82f556d | 4713 | /* Doubles go in an odd/even register pair (r5/r6, etc). */ |
b5870bee AH |
4714 | if (mode == DFmode) |
4715 | gregno += (1 - gregno) & 1; | |
f82f556d | 4716 | |
b5870bee AH |
4717 | /* Multi-reg args are not split between registers and stack. */ |
4718 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
f82f556d AH |
4719 | return NULL_RTX; |
4720 | ||
4721 | return spe_build_register_parallel (mode, gregno); | |
4722 | } | |
a6c9bed4 AH |
4723 | if (cum->stdarg) |
4724 | { | |
c53bdcf5 | 4725 | int n_words = rs6000_arg_size (mode, type); |
a6c9bed4 AH |
4726 | |
4727 | /* SPE vectors are put in odd registers. */ | |
4728 | if (n_words == 2 && (gregno & 1) == 0) | |
4729 | gregno += 1; | |
4730 | ||
4731 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
4732 | { | |
4733 | rtx r1, r2; | |
4734 | enum machine_mode m = SImode; | |
4735 | ||
4736 | r1 = gen_rtx_REG (m, gregno); | |
4737 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
4738 | r2 = gen_rtx_REG (m, gregno + 1); | |
4739 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
4740 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
4741 | } | |
4742 | else | |
b78d48dd | 4743 | return NULL_RTX; |
a6c9bed4 AH |
4744 | } |
4745 | else | |
4746 | { | |
f82f556d AH |
4747 | if (gregno <= GP_ARG_MAX_REG) |
4748 | return gen_rtx_REG (mode, gregno); | |
a6c9bed4 | 4749 | else |
b78d48dd | 4750 | return NULL_RTX; |
a6c9bed4 AH |
4751 | } |
4752 | } | |
4753 | ||
0b5383eb DJ |
4754 | /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the |
4755 | structure between cum->intoffset and bitpos to integer registers. */ | |
594a51fe | 4756 | |
0b5383eb | 4757 | static void |
bb8df8a6 | 4758 | rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum, |
0b5383eb | 4759 | HOST_WIDE_INT bitpos, rtx rvec[], int *k) |
594a51fe | 4760 | { |
0b5383eb DJ |
4761 | enum machine_mode mode; |
4762 | unsigned int regno; | |
4763 | unsigned int startbit, endbit; | |
4764 | int this_regno, intregs, intoffset; | |
4765 | rtx reg; | |
594a51fe | 4766 | |
0b5383eb DJ |
4767 | if (cum->intoffset == -1) |
4768 | return; | |
4769 | ||
4770 | intoffset = cum->intoffset; | |
4771 | cum->intoffset = -1; | |
4772 | ||
4773 | /* If this is the trailing part of a word, try to only load that | |
4774 | much into the register. Otherwise load the whole register. Note | |
4775 | that in the latter case we may pick up unwanted bits. It's not a | |
4776 | problem at the moment but may wish to revisit. */ | |
4777 | ||
4778 | if (intoffset % BITS_PER_WORD != 0) | |
594a51fe | 4779 | { |
0b5383eb DJ |
4780 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
4781 | MODE_INT, 0); | |
4782 | if (mode == BLKmode) | |
4783 | { | |
4784 | /* We couldn't find an appropriate mode, which happens, | |
4785 | e.g., in packed structs when there are 3 bytes to load. | |
4786 | Back intoffset back to the beginning of the word in this | |
4787 | case. */ | |
4788 | intoffset = intoffset & -BITS_PER_WORD; | |
4789 | mode = word_mode; | |
4790 | } | |
4791 | } | |
4792 | else | |
4793 | mode = word_mode; | |
4794 | ||
4795 | startbit = intoffset & -BITS_PER_WORD; | |
4796 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4797 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
4798 | this_regno = cum->words + intoffset / BITS_PER_WORD; | |
4799 | ||
4800 | if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno) | |
4801 | cum->use_stack = 1; | |
bb8df8a6 | 4802 | |
0b5383eb DJ |
4803 | intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno); |
4804 | if (intregs <= 0) | |
4805 | return; | |
4806 | ||
4807 | intoffset /= BITS_PER_UNIT; | |
4808 | do | |
4809 | { | |
4810 | regno = GP_ARG_MIN_REG + this_regno; | |
4811 | reg = gen_rtx_REG (mode, regno); | |
4812 | rvec[(*k)++] = | |
4813 | gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); | |
4814 | ||
4815 | this_regno += 1; | |
4816 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
4817 | mode = word_mode; | |
4818 | intregs -= 1; | |
4819 | } | |
4820 | while (intregs > 0); | |
4821 | } | |
4822 | ||
4823 | /* Recursive workhorse for the following. */ | |
4824 | ||
4825 | static void | |
bb8df8a6 | 4826 | rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type, |
0b5383eb DJ |
4827 | HOST_WIDE_INT startbitpos, rtx rvec[], |
4828 | int *k) | |
4829 | { | |
4830 | tree f; | |
4831 | ||
4832 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
4833 | if (TREE_CODE (f) == FIELD_DECL) | |
4834 | { | |
4835 | HOST_WIDE_INT bitpos = startbitpos; | |
4836 | tree ftype = TREE_TYPE (f); | |
4837 | enum machine_mode mode = TYPE_MODE (ftype); | |
4838 | ||
4839 | if (DECL_SIZE (f) != 0 | |
4840 | && host_integerp (bit_position (f), 1)) | |
4841 | bitpos += int_bit_position (f); | |
4842 | ||
4843 | /* ??? FIXME: else assume zero offset. */ | |
4844 | ||
4845 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
4846 | rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k); | |
4847 | else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
594a51fe | 4848 | { |
0b5383eb DJ |
4849 | #if 0 |
4850 | switch (mode) | |
594a51fe | 4851 | { |
0b5383eb DJ |
4852 | case SCmode: mode = SFmode; break; |
4853 | case DCmode: mode = DFmode; break; | |
4854 | case TCmode: mode = TFmode; break; | |
4855 | default: break; | |
594a51fe | 4856 | } |
0b5383eb DJ |
4857 | #endif |
4858 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
4859 | rvec[(*k)++] | |
bb8df8a6 | 4860 | = gen_rtx_EXPR_LIST (VOIDmode, |
0b5383eb DJ |
4861 | gen_rtx_REG (mode, cum->fregno++), |
4862 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4863 | if (mode == TFmode) | |
4864 | cum->fregno++; | |
594a51fe | 4865 | } |
0b5383eb DJ |
4866 | else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1)) |
4867 | { | |
4868 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
4869 | rvec[(*k)++] | |
bb8df8a6 EC |
4870 | = gen_rtx_EXPR_LIST (VOIDmode, |
4871 | gen_rtx_REG (mode, cum->vregno++), | |
0b5383eb DJ |
4872 | GEN_INT (bitpos / BITS_PER_UNIT)); |
4873 | } | |
4874 | else if (cum->intoffset == -1) | |
4875 | cum->intoffset = bitpos; | |
4876 | } | |
4877 | } | |
594a51fe | 4878 | |
0b5383eb DJ |
4879 | /* For the darwin64 ABI, we want to construct a PARALLEL consisting of |
4880 | the register(s) to be used for each field and subfield of a struct | |
4881 | being passed by value, along with the offset of where the | |
4882 | register's value may be found in the block. FP fields go in FP | |
4883 | register, vector fields go in vector registers, and everything | |
bb8df8a6 | 4884 | else goes in int registers, packed as in memory. |
8ff40a74 | 4885 | |
0b5383eb DJ |
4886 | This code is also used for function return values. RETVAL indicates |
4887 | whether this is the case. | |
8ff40a74 | 4888 | |
a4d05547 | 4889 | Much of this is taken from the SPARC V9 port, which has a similar |
0b5383eb | 4890 | calling convention. */ |
594a51fe | 4891 | |
0b5383eb DJ |
4892 | static rtx |
4893 | rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type, | |
4894 | int named, bool retval) | |
4895 | { | |
4896 | rtx rvec[FIRST_PSEUDO_REGISTER]; | |
4897 | int k = 1, kbase = 1; | |
4898 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
4899 | /* This is a copy; modifications are not visible to our caller. */ | |
4900 | CUMULATIVE_ARGS copy_cum = *orig_cum; | |
4901 | CUMULATIVE_ARGS *cum = ©_cum; | |
4902 | ||
4903 | /* Pad to 16 byte boundary if needed. */ | |
4904 | if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
4905 | && (cum->words % 2) != 0) | |
4906 | cum->words++; | |
4907 | ||
4908 | cum->intoffset = 0; | |
4909 | cum->use_stack = 0; | |
4910 | cum->named = named; | |
4911 | ||
4912 | /* Put entries into rvec[] for individual FP and vector fields, and | |
4913 | for the chunks of memory that go in int regs. Note we start at | |
4914 | element 1; 0 is reserved for an indication of using memory, and | |
4915 | may or may not be filled in below. */ | |
4916 | rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k); | |
4917 | rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k); | |
4918 | ||
4919 | /* If any part of the struct went on the stack put all of it there. | |
4920 | This hack is because the generic code for | |
4921 | FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register | |
4922 | parts of the struct are not at the beginning. */ | |
4923 | if (cum->use_stack) | |
4924 | { | |
4925 | if (retval) | |
4926 | return NULL_RTX; /* doesn't go in registers at all */ | |
4927 | kbase = 0; | |
4928 | rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4929 | } | |
4930 | if (k > 1 || cum->use_stack) | |
4931 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase])); | |
594a51fe SS |
4932 | else |
4933 | return NULL_RTX; | |
4934 | } | |
4935 | ||
b78d48dd FJ |
4936 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
4937 | ||
4938 | static rtx | |
ec6376ab | 4939 | rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) |
b78d48dd | 4940 | { |
ec6376ab AM |
4941 | int n_units; |
4942 | int i, k; | |
4943 | rtx rvec[GP_ARG_NUM_REG + 1]; | |
4944 | ||
4945 | if (align_words >= GP_ARG_NUM_REG) | |
4946 | return NULL_RTX; | |
4947 | ||
4948 | n_units = rs6000_arg_size (mode, type); | |
4949 | ||
4950 | /* Optimize the simple case where the arg fits in one gpr, except in | |
4951 | the case of BLKmode due to assign_parms assuming that registers are | |
4952 | BITS_PER_WORD wide. */ | |
4953 | if (n_units == 0 | |
4954 | || (n_units == 1 && mode != BLKmode)) | |
4955 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4956 | ||
4957 | k = 0; | |
4958 | if (align_words + n_units > GP_ARG_NUM_REG) | |
4959 | /* Not all of the arg fits in gprs. Say that it goes in memory too, | |
4960 | using a magic NULL_RTX component. | |
4961 | FIXME: This is not strictly correct. Only some of the arg | |
4962 | belongs in memory, not all of it. However, there isn't any way | |
4963 | to do this currently, apart from building rtx descriptions for | |
4964 | the pieces of memory we want stored. Due to bugs in the generic | |
4965 | code we can't use the normal function_arg_partial_nregs scheme | |
4966 | with the PARALLEL arg description we emit here. | |
4967 | In any case, the code to store the whole arg to memory is often | |
4968 | more efficient than code to store pieces, and we know that space | |
4969 | is available in the right place for the whole arg. */ | |
78a52f11 RH |
4970 | /* FIXME: This should be fixed since the conversion to |
4971 | TARGET_ARG_PARTIAL_BYTES. */ | |
ec6376ab AM |
4972 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); |
4973 | ||
4974 | i = 0; | |
4975 | do | |
36a454e1 | 4976 | { |
ec6376ab AM |
4977 | rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); |
4978 | rtx off = GEN_INT (i++ * 4); | |
4979 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
36a454e1 | 4980 | } |
ec6376ab AM |
4981 | while (++align_words < GP_ARG_NUM_REG && --n_units != 0); |
4982 | ||
4983 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
b78d48dd FJ |
4984 | } |
4985 | ||
4697a36c MM |
4986 | /* Determine where to put an argument to a function. |
4987 | Value is zero to push the argument on the stack, | |
4988 | or a hard register in which to store the argument. | |
4989 | ||
4990 | MODE is the argument's machine mode. | |
4991 | TYPE is the data type of the argument (as a tree). | |
4992 | This is null for libcalls where that information may | |
4993 | not be available. | |
4994 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
0b5383eb DJ |
4995 | the preceding args and about the function being called. It is |
4996 | not modified in this routine. | |
4697a36c MM |
4997 | NAMED is nonzero if this argument is a named parameter |
4998 | (otherwise it is an extra parameter matching an ellipsis). | |
4999 | ||
5000 | On RS/6000 the first eight words of non-FP are normally in registers | |
5001 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
5002 | Under V.4, the first 8 FP args are in registers. | |
5003 | ||
5004 | If this is floating-point and no prototype is specified, we use | |
5005 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 5006 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 5007 | so we can pass the FP value just in one register. emit_library_function |
b2d04ecf AM |
5008 | doesn't support PARALLEL anyway. |
5009 | ||
5010 | Note that for args passed by reference, function_arg will be called | |
5011 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
5012 | itself. */ | |
4697a36c | 5013 | |
9390387d | 5014 | rtx |
f676971a | 5015 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 5016 | tree type, int named) |
4697a36c | 5017 | { |
4cc833b7 | 5018 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 5019 | |
a4f6c312 SS |
5020 | /* Return a marker to indicate whether CR1 needs to set or clear the |
5021 | bit that V.4 uses to say fp args were passed in registers. | |
5022 | Assume that we don't need the marker for software floating point, | |
5023 | or compiler generated library calls. */ | |
4697a36c MM |
5024 | if (mode == VOIDmode) |
5025 | { | |
f607bc57 | 5026 | if (abi == ABI_V4 |
b9599e46 | 5027 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
c1fa753e AM |
5028 | && (cum->stdarg |
5029 | || (cum->nargs_prototype < 0 | |
5030 | && (cum->prototype || TARGET_NO_PROTOTYPE)))) | |
7509c759 | 5031 | { |
a3170dc6 AH |
5032 | /* For the SPE, we need to crxor CR6 always. */ |
5033 | if (TARGET_SPE_ABI) | |
5034 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
5035 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
5036 | return GEN_INT (cum->call_cookie | |
5037 | | ((cum->fregno == FP_ARG_MIN_REG) | |
5038 | ? CALL_V4_SET_FP_ARGS | |
5039 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 5040 | } |
4697a36c | 5041 | |
7509c759 | 5042 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
5043 | } |
5044 | ||
0b5383eb DJ |
5045 | if (rs6000_darwin64_abi && mode == BLKmode |
5046 | && TREE_CODE (type) == RECORD_TYPE) | |
8ff40a74 | 5047 | { |
0b5383eb | 5048 | rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false); |
8ff40a74 SS |
5049 | if (rslt != NULL_RTX) |
5050 | return rslt; | |
5051 | /* Else fall through to usual handling. */ | |
5052 | } | |
5053 | ||
2858f73a | 5054 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
5055 | if (TARGET_64BIT && ! cum->prototype) |
5056 | { | |
c4ad648e AM |
5057 | /* Vector parameters get passed in vector register |
5058 | and also in GPRs or memory, in absence of prototype. */ | |
5059 | int align_words; | |
5060 | rtx slot; | |
5061 | align_words = (cum->words + 1) & ~1; | |
5062 | ||
5063 | if (align_words >= GP_ARG_NUM_REG) | |
5064 | { | |
5065 | slot = NULL_RTX; | |
5066 | } | |
5067 | else | |
5068 | { | |
5069 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5070 | } | |
5071 | return gen_rtx_PARALLEL (mode, | |
5072 | gen_rtvec (2, | |
5073 | gen_rtx_EXPR_LIST (VOIDmode, | |
5074 | slot, const0_rtx), | |
5075 | gen_rtx_EXPR_LIST (VOIDmode, | |
5076 | gen_rtx_REG (mode, cum->vregno), | |
5077 | const0_rtx))); | |
c72d6c26 HP |
5078 | } |
5079 | else | |
5080 | return gen_rtx_REG (mode, cum->vregno); | |
ad630bef DE |
5081 | else if (TARGET_ALTIVEC_ABI |
5082 | && (ALTIVEC_VECTOR_MODE (mode) | |
5083 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
5084 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 5085 | { |
2858f73a | 5086 | if (named || abi == ABI_V4) |
a594a19c | 5087 | return NULL_RTX; |
0ac081f6 | 5088 | else |
a594a19c GK |
5089 | { |
5090 | /* Vector parameters to varargs functions under AIX or Darwin | |
5091 | get passed in memory and possibly also in GPRs. */ | |
ec6376ab AM |
5092 | int align, align_words, n_words; |
5093 | enum machine_mode part_mode; | |
a594a19c GK |
5094 | |
5095 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
5096 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
5097 | save area starts at offset 24 from the stack. In 64-bit mode, | |
5098 | they just have to start on an even word, since the parameter | |
5099 | save area is 16-byte aligned. */ | |
5100 | if (TARGET_32BIT) | |
4ed78545 | 5101 | align = (2 - cum->words) & 3; |
2858f73a GK |
5102 | else |
5103 | align = cum->words & 1; | |
a594a19c GK |
5104 | align_words = cum->words + align; |
5105 | ||
5106 | /* Out of registers? Memory, then. */ | |
5107 | if (align_words >= GP_ARG_NUM_REG) | |
5108 | return NULL_RTX; | |
ec6376ab AM |
5109 | |
5110 | if (TARGET_32BIT && TARGET_POWERPC64) | |
5111 | return rs6000_mixed_function_arg (mode, type, align_words); | |
5112 | ||
2858f73a GK |
5113 | /* The vector value goes in GPRs. Only the part of the |
5114 | value in GPRs is reported here. */ | |
ec6376ab AM |
5115 | part_mode = mode; |
5116 | n_words = rs6000_arg_size (mode, type); | |
5117 | if (align_words + n_words > GP_ARG_NUM_REG) | |
839a4992 | 5118 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
5119 | is either wholly in GPRs or half in GPRs and half not. */ |
5120 | part_mode = DImode; | |
ec6376ab AM |
5121 | |
5122 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 5123 | } |
0ac081f6 | 5124 | } |
f82f556d AH |
5125 | else if (TARGET_SPE_ABI && TARGET_SPE |
5126 | && (SPE_VECTOR_MODE (mode) | |
18f63bfa AH |
5127 | || (TARGET_E500_DOUBLE && (mode == DFmode |
5128 | || mode == DCmode)))) | |
a6c9bed4 | 5129 | return rs6000_spe_function_arg (cum, mode, type); |
594a51fe | 5130 | |
f607bc57 | 5131 | else if (abi == ABI_V4) |
4697a36c | 5132 | { |
a3170dc6 | 5133 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
5134 | && (mode == SFmode || mode == DFmode)) |
5135 | { | |
5136 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
5137 | return gen_rtx_REG (mode, cum->fregno); | |
5138 | else | |
b78d48dd | 5139 | return NULL_RTX; |
4cc833b7 RH |
5140 | } |
5141 | else | |
5142 | { | |
b2d04ecf | 5143 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
5144 | int gregno = cum->sysv_gregno; |
5145 | ||
4ed78545 AM |
5146 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
5147 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
5148 | as complex int due to a historical mistake. */ | |
5149 | if (n_words == 2) | |
5150 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 5151 | |
4ed78545 | 5152 | /* Multi-reg args are not split between registers and stack. */ |
ec6376ab | 5153 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
b78d48dd | 5154 | return NULL_RTX; |
ec6376ab AM |
5155 | |
5156 | if (TARGET_32BIT && TARGET_POWERPC64) | |
5157 | return rs6000_mixed_function_arg (mode, type, | |
5158 | gregno - GP_ARG_MIN_REG); | |
5159 | return gen_rtx_REG (mode, gregno); | |
4cc833b7 | 5160 | } |
4697a36c | 5161 | } |
4cc833b7 RH |
5162 | else |
5163 | { | |
294bd182 | 5164 | int align_words = rs6000_parm_start (mode, type, cum->words); |
b78d48dd | 5165 | |
2858f73a | 5166 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 | 5167 | { |
ec6376ab AM |
5168 | rtx rvec[GP_ARG_NUM_REG + 1]; |
5169 | rtx r; | |
5170 | int k; | |
c53bdcf5 AM |
5171 | bool needs_psave; |
5172 | enum machine_mode fmode = mode; | |
c53bdcf5 AM |
5173 | unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; |
5174 | ||
5175 | if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) | |
5176 | { | |
c53bdcf5 AM |
5177 | /* Currently, we only ever need one reg here because complex |
5178 | doubles are split. */ | |
37409796 | 5179 | gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode); |
ec6376ab AM |
5180 | |
5181 | /* Long double split over regs and memory. */ | |
5182 | fmode = DFmode; | |
c53bdcf5 | 5183 | } |
c53bdcf5 AM |
5184 | |
5185 | /* Do we also need to pass this arg in the parameter save | |
5186 | area? */ | |
5187 | needs_psave = (type | |
5188 | && (cum->nargs_prototype <= 0 | |
5189 | || (DEFAULT_ABI == ABI_AIX | |
de17c25f | 5190 | && TARGET_XL_COMPAT |
c53bdcf5 AM |
5191 | && align_words >= GP_ARG_NUM_REG))); |
5192 | ||
5193 | if (!needs_psave && mode == fmode) | |
ec6376ab | 5194 | return gen_rtx_REG (fmode, cum->fregno); |
c53bdcf5 | 5195 | |
ec6376ab | 5196 | k = 0; |
c53bdcf5 AM |
5197 | if (needs_psave) |
5198 | { | |
ec6376ab | 5199 | /* Describe the part that goes in gprs or the stack. |
c53bdcf5 | 5200 | This piece must come first, before the fprs. */ |
c53bdcf5 AM |
5201 | if (align_words < GP_ARG_NUM_REG) |
5202 | { | |
5203 | unsigned long n_words = rs6000_arg_size (mode, type); | |
ec6376ab AM |
5204 | |
5205 | if (align_words + n_words > GP_ARG_NUM_REG | |
5206 | || (TARGET_32BIT && TARGET_POWERPC64)) | |
5207 | { | |
5208 | /* If this is partially on the stack, then we only | |
5209 | include the portion actually in registers here. */ | |
5210 | enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; | |
5211 | rtx off; | |
2e6c9641 | 5212 | int i=0; |
c4ad648e AM |
5213 | if (align_words + n_words > GP_ARG_NUM_REG |
5214 | && (TARGET_32BIT && TARGET_POWERPC64)) | |
5215 | /* Not all of the arg fits in gprs. Say that it | |
5216 | goes in memory too, using a magic NULL_RTX | |
5217 | component. Also see comment in | |
5218 | rs6000_mixed_function_arg for why the normal | |
5219 | function_arg_partial_nregs scheme doesn't work | |
5220 | in this case. */ | |
5221 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, | |
5222 | const0_rtx); | |
ec6376ab AM |
5223 | do |
5224 | { | |
5225 | r = gen_rtx_REG (rmode, | |
5226 | GP_ARG_MIN_REG + align_words); | |
2e6c9641 | 5227 | off = GEN_INT (i++ * GET_MODE_SIZE (rmode)); |
ec6376ab AM |
5228 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); |
5229 | } | |
5230 | while (++align_words < GP_ARG_NUM_REG && --n_words != 0); | |
5231 | } | |
5232 | else | |
5233 | { | |
5234 | /* The whole arg fits in gprs. */ | |
5235 | r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5236 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5237 | } | |
c53bdcf5 | 5238 | } |
ec6376ab AM |
5239 | else |
5240 | /* It's entirely in memory. */ | |
5241 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
c53bdcf5 AM |
5242 | } |
5243 | ||
ec6376ab AM |
5244 | /* Describe where this piece goes in the fprs. */ |
5245 | r = gen_rtx_REG (fmode, cum->fregno); | |
5246 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5247 | ||
5248 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
4cc833b7 RH |
5249 | } |
5250 | else if (align_words < GP_ARG_NUM_REG) | |
b2d04ecf | 5251 | { |
ec6376ab AM |
5252 | if (TARGET_32BIT && TARGET_POWERPC64) |
5253 | return rs6000_mixed_function_arg (mode, type, align_words); | |
b2d04ecf | 5254 | |
4eeca74f AM |
5255 | if (mode == BLKmode) |
5256 | mode = Pmode; | |
5257 | ||
b2d04ecf AM |
5258 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); |
5259 | } | |
4cc833b7 RH |
5260 | else |
5261 | return NULL_RTX; | |
4697a36c | 5262 | } |
4697a36c MM |
5263 | } |
5264 | \f | |
ec6376ab | 5265 | /* For an arg passed partly in registers and partly in memory, this is |
fb63c729 AM |
5266 | the number of bytes passed in registers. For args passed entirely in |
5267 | registers or entirely in memory, zero. When an arg is described by a | |
5268 | PARALLEL, perhaps using more than one register type, this function | |
5269 | returns the number of bytes used by the first element of the PARALLEL. */ | |
4697a36c | 5270 | |
78a52f11 RH |
5271 | static int |
5272 | rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
5273 | tree type, bool named) | |
4697a36c | 5274 | { |
c53bdcf5 | 5275 | int ret = 0; |
ec6376ab | 5276 | int align_words; |
c53bdcf5 | 5277 | |
f607bc57 | 5278 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 5279 | return 0; |
4697a36c | 5280 | |
c53bdcf5 AM |
5281 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) |
5282 | && cum->nargs_prototype >= 0) | |
5283 | return 0; | |
5284 | ||
0b5383eb DJ |
5285 | /* In this complicated case we just disable the partial_nregs code. */ |
5286 | if (rs6000_darwin64_abi && mode == BLKmode | |
5287 | && TREE_CODE (type) == RECORD_TYPE | |
5288 | && int_size_in_bytes (type) > 0) | |
5289 | return 0; | |
5290 | ||
294bd182 | 5291 | align_words = rs6000_parm_start (mode, type, cum->words); |
ec6376ab AM |
5292 | |
5293 | if (USE_FP_FOR_ARG_P (cum, mode, type) | |
fb63c729 AM |
5294 | /* If we are passing this arg in the fixed parameter save area |
5295 | (gprs or memory) as well as fprs, then this function should | |
5296 | return the number of bytes passed in the parameter save area | |
bb8df8a6 | 5297 | rather than bytes passed in fprs. */ |
ec6376ab AM |
5298 | && !(type |
5299 | && (cum->nargs_prototype <= 0 | |
5300 | || (DEFAULT_ABI == ABI_AIX | |
de17c25f | 5301 | && TARGET_XL_COMPAT |
ec6376ab | 5302 | && align_words >= GP_ARG_NUM_REG)))) |
4697a36c | 5303 | { |
c53bdcf5 | 5304 | if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1) |
ac7e839c | 5305 | ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8; |
c53bdcf5 | 5306 | else if (cum->nargs_prototype >= 0) |
4697a36c MM |
5307 | return 0; |
5308 | } | |
5309 | ||
ec6376ab AM |
5310 | if (align_words < GP_ARG_NUM_REG |
5311 | && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) | |
ac7e839c | 5312 | ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8); |
78a52f11 | 5313 | |
c53bdcf5 | 5314 | if (ret != 0 && TARGET_DEBUG_ARG) |
78a52f11 | 5315 | fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret); |
4697a36c | 5316 | |
c53bdcf5 | 5317 | return ret; |
4697a36c MM |
5318 | } |
5319 | \f | |
5320 | /* A C expression that indicates when an argument must be passed by | |
5321 | reference. If nonzero for an argument, a copy of that argument is | |
5322 | made in memory and a pointer to the argument is passed instead of | |
5323 | the argument itself. The pointer is passed in whatever way is | |
5324 | appropriate for passing a pointer to that type. | |
5325 | ||
b2d04ecf AM |
5326 | Under V.4, aggregates and long double are passed by reference. |
5327 | ||
5328 | As an extension to all 32-bit ABIs, AltiVec vectors are passed by | |
5329 | reference unless the AltiVec vector extension ABI is in force. | |
c8c99a68 DE |
5330 | |
5331 | As an extension to all ABIs, variable sized types are passed by | |
5332 | reference. */ | |
4697a36c | 5333 | |
8cd5a4e0 | 5334 | static bool |
f676971a | 5335 | rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
bada2eb8 DE |
5336 | enum machine_mode mode, tree type, |
5337 | bool named ATTRIBUTE_UNUSED) | |
4697a36c | 5338 | { |
bada2eb8 | 5339 | if (DEFAULT_ABI == ABI_V4 && mode == TFmode) |
4697a36c MM |
5340 | { |
5341 | if (TARGET_DEBUG_ARG) | |
bada2eb8 DE |
5342 | fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n"); |
5343 | return 1; | |
5344 | } | |
5345 | ||
5346 | if (!type) | |
5347 | return 0; | |
4697a36c | 5348 | |
bada2eb8 DE |
5349 | if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type)) |
5350 | { | |
5351 | if (TARGET_DEBUG_ARG) | |
5352 | fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n"); | |
5353 | return 1; | |
5354 | } | |
5355 | ||
5356 | if (int_size_in_bytes (type) < 0) | |
5357 | { | |
5358 | if (TARGET_DEBUG_ARG) | |
5359 | fprintf (stderr, "function_arg_pass_by_reference: variable size\n"); | |
5360 | return 1; | |
5361 | } | |
5362 | ||
5363 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector | |
5364 | modes only exist for GCC vector types if -maltivec. */ | |
5365 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
5366 | { | |
5367 | if (TARGET_DEBUG_ARG) | |
5368 | fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n"); | |
4697a36c MM |
5369 | return 1; |
5370 | } | |
b693336b PB |
5371 | |
5372 | /* Pass synthetic vectors in memory. */ | |
bada2eb8 | 5373 | if (TREE_CODE (type) == VECTOR_TYPE |
ad630bef | 5374 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
5375 | { |
5376 | static bool warned_for_pass_big_vectors = false; | |
5377 | if (TARGET_DEBUG_ARG) | |
5378 | fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n"); | |
5379 | if (!warned_for_pass_big_vectors) | |
5380 | { | |
d4ee4d25 | 5381 | warning (0, "GCC vector passed by reference: " |
b693336b PB |
5382 | "non-standard ABI extension with no compatibility guarantee"); |
5383 | warned_for_pass_big_vectors = true; | |
5384 | } | |
5385 | return 1; | |
5386 | } | |
5387 | ||
b2d04ecf | 5388 | return 0; |
4697a36c | 5389 | } |
5985c7a6 FJ |
5390 | |
5391 | static void | |
2d9db8eb | 5392 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
5393 | { |
5394 | int i; | |
5395 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
5396 | ||
5397 | if (nregs == 0) | |
5398 | return; | |
5399 | ||
c4ad648e | 5400 | for (i = 0; i < nregs; i++) |
5985c7a6 | 5401 | { |
9390387d | 5402 | rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode)); |
5985c7a6 | 5403 | if (reload_completed) |
c4ad648e AM |
5404 | { |
5405 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
5406 | tem = NULL_RTX; | |
5407 | else | |
5408 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
9390387d | 5409 | i * GET_MODE_SIZE (reg_mode)); |
c4ad648e | 5410 | } |
5985c7a6 FJ |
5411 | else |
5412 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
5413 | ||
37409796 | 5414 | gcc_assert (tem); |
5985c7a6 FJ |
5415 | |
5416 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
5417 | } | |
5418 | } | |
4697a36c MM |
5419 | \f |
5420 | /* Perform any needed actions needed for a function that is receiving a | |
f676971a | 5421 | variable number of arguments. |
4697a36c MM |
5422 | |
5423 | CUM is as above. | |
5424 | ||
5425 | MODE and TYPE are the mode and type of the current parameter. | |
5426 | ||
5427 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
5428 | that must be pushed by the prolog to pretend that our caller pushed | |
5429 | it. | |
5430 | ||
5431 | Normally, this macro will push all remaining incoming registers on the | |
5432 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
5433 | ||
c6e8c921 | 5434 | static void |
f676971a | 5435 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
c4ad648e AM |
5436 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5437 | int no_rtl) | |
4697a36c | 5438 | { |
4cc833b7 RH |
5439 | CUMULATIVE_ARGS next_cum; |
5440 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 5441 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 5442 | int first_reg_offset, set; |
4697a36c | 5443 | |
f31bf321 | 5444 | /* Skip the last named argument. */ |
d34c5b80 | 5445 | next_cum = *cum; |
594a51fe | 5446 | function_arg_advance (&next_cum, mode, type, 1, 0); |
4cc833b7 | 5447 | |
f607bc57 | 5448 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 5449 | { |
5b667039 JJ |
5450 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; |
5451 | ||
60e2d0ca | 5452 | if (! no_rtl) |
5b667039 JJ |
5453 | { |
5454 | int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0; | |
5455 | HOST_WIDE_INT offset = 0; | |
5456 | ||
5457 | /* Try to optimize the size of the varargs save area. | |
5458 | The ABI requires that ap.reg_save_area is doubleword | |
5459 | aligned, but we don't need to allocate space for all | |
5460 | the bytes, only those to which we actually will save | |
5461 | anything. */ | |
5462 | if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG) | |
5463 | gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset; | |
5464 | if (TARGET_HARD_FLOAT && TARGET_FPRS | |
5465 | && next_cum.fregno <= FP_ARG_V4_MAX_REG | |
5466 | && cfun->va_list_fpr_size) | |
5467 | { | |
5468 | if (gpr_reg_num) | |
5469 | fpr_size = (next_cum.fregno - FP_ARG_MIN_REG) | |
5470 | * UNITS_PER_FP_WORD; | |
5471 | if (cfun->va_list_fpr_size | |
5472 | < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno) | |
5473 | fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD; | |
5474 | else | |
5475 | fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno) | |
5476 | * UNITS_PER_FP_WORD; | |
5477 | } | |
5478 | if (gpr_reg_num) | |
5479 | { | |
5480 | offset = -((first_reg_offset * reg_size) & ~7); | |
5481 | if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size) | |
5482 | { | |
5483 | gpr_reg_num = cfun->va_list_gpr_size; | |
5484 | if (reg_size == 4 && (first_reg_offset & 1)) | |
5485 | gpr_reg_num++; | |
5486 | } | |
5487 | gpr_size = (gpr_reg_num * reg_size + 7) & ~7; | |
5488 | } | |
5489 | else if (fpr_size) | |
5490 | offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG) | |
5491 | * UNITS_PER_FP_WORD | |
5492 | - (int) (GP_ARG_NUM_REG * reg_size); | |
4cc833b7 | 5493 | |
5b667039 JJ |
5494 | if (gpr_size + fpr_size) |
5495 | { | |
5496 | rtx reg_save_area | |
5497 | = assign_stack_local (BLKmode, gpr_size + fpr_size, 64); | |
5498 | gcc_assert (GET_CODE (reg_save_area) == MEM); | |
5499 | reg_save_area = XEXP (reg_save_area, 0); | |
5500 | if (GET_CODE (reg_save_area) == PLUS) | |
5501 | { | |
5502 | gcc_assert (XEXP (reg_save_area, 0) | |
5503 | == virtual_stack_vars_rtx); | |
5504 | gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT); | |
5505 | offset += INTVAL (XEXP (reg_save_area, 1)); | |
5506 | } | |
5507 | else | |
5508 | gcc_assert (reg_save_area == virtual_stack_vars_rtx); | |
5509 | } | |
5510 | ||
5511 | cfun->machine->varargs_save_offset = offset; | |
5512 | save_area = plus_constant (virtual_stack_vars_rtx, offset); | |
5513 | } | |
4697a36c | 5514 | } |
60e2d0ca | 5515 | else |
4697a36c | 5516 | { |
d34c5b80 | 5517 | first_reg_offset = next_cum.words; |
4cc833b7 | 5518 | save_area = virtual_incoming_args_rtx; |
4697a36c | 5519 | |
fe984136 | 5520 | if (targetm.calls.must_pass_in_stack (mode, type)) |
c53bdcf5 | 5521 | first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); |
4cc833b7 | 5522 | } |
4697a36c | 5523 | |
dfafc897 | 5524 | set = get_varargs_alias_set (); |
9d30f3c1 JJ |
5525 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG |
5526 | && cfun->va_list_gpr_size) | |
4cc833b7 | 5527 | { |
9d30f3c1 JJ |
5528 | int nregs = GP_ARG_NUM_REG - first_reg_offset; |
5529 | ||
5530 | if (va_list_gpr_counter_field) | |
5531 | { | |
5532 | /* V4 va_list_gpr_size counts number of registers needed. */ | |
5533 | if (nregs > cfun->va_list_gpr_size) | |
5534 | nregs = cfun->va_list_gpr_size; | |
5535 | } | |
5536 | else | |
5537 | { | |
5538 | /* char * va_list instead counts number of bytes needed. */ | |
5539 | if (nregs > cfun->va_list_gpr_size / reg_size) | |
5540 | nregs = cfun->va_list_gpr_size / reg_size; | |
5541 | } | |
5542 | ||
dfafc897 | 5543 | mem = gen_rtx_MEM (BLKmode, |
c4ad648e | 5544 | plus_constant (save_area, |
13e2e16e DE |
5545 | first_reg_offset * reg_size)); |
5546 | MEM_NOTRAP_P (mem) = 1; | |
ba4828e0 | 5547 | set_mem_alias_set (mem, set); |
8ac61af7 | 5548 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 5549 | |
f676971a | 5550 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
9d30f3c1 | 5551 | nregs); |
4697a36c MM |
5552 | } |
5553 | ||
4697a36c | 5554 | /* Save FP registers if needed. */ |
f607bc57 | 5555 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
5556 | && TARGET_HARD_FLOAT && TARGET_FPRS |
5557 | && ! no_rtl | |
9d30f3c1 JJ |
5558 | && next_cum.fregno <= FP_ARG_V4_MAX_REG |
5559 | && cfun->va_list_fpr_size) | |
4697a36c | 5560 | { |
9d30f3c1 | 5561 | int fregno = next_cum.fregno, nregs; |
9ebbca7d | 5562 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 | 5563 | rtx lab = gen_label_rtx (); |
5b667039 JJ |
5564 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) |
5565 | * UNITS_PER_FP_WORD); | |
4697a36c | 5566 | |
c4ad648e AM |
5567 | emit_jump_insn |
5568 | (gen_rtx_SET (VOIDmode, | |
5569 | pc_rtx, | |
5570 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4cc833b7 | 5571 | gen_rtx_NE (VOIDmode, cr1, |
c4ad648e | 5572 | const0_rtx), |
39403d82 | 5573 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
5574 | pc_rtx))); |
5575 | ||
9d30f3c1 JJ |
5576 | for (nregs = 0; |
5577 | fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size; | |
5b667039 | 5578 | fregno++, off += UNITS_PER_FP_WORD, nregs++) |
4cc833b7 | 5579 | { |
5496b36f | 5580 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
13e2e16e | 5581 | MEM_NOTRAP_P (mem) = 1; |
c4ad648e | 5582 | set_mem_alias_set (mem, set); |
94ff898d | 5583 | set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode)); |
dfafc897 | 5584 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4697a36c | 5585 | } |
4cc833b7 RH |
5586 | |
5587 | emit_label (lab); | |
4697a36c | 5588 | } |
4697a36c | 5589 | } |
4697a36c | 5590 | |
dfafc897 | 5591 | /* Create the va_list data type. */ |
2c4974b7 | 5592 | |
c35d187f RH |
5593 | static tree |
5594 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 5595 | { |
64c2816f | 5596 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 5597 | |
9ebbca7d GK |
5598 | /* For AIX, prefer 'char *' because that's what the system |
5599 | header files like. */ | |
f607bc57 | 5600 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 5601 | return build_pointer_type (char_type_node); |
dfafc897 | 5602 | |
f1e639b1 | 5603 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 5604 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 5605 | |
f676971a | 5606 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
9ebbca7d | 5607 | unsigned_char_type_node); |
f676971a | 5608 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), |
9ebbca7d | 5609 | unsigned_char_type_node); |
64c2816f DT |
5610 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
5611 | every user file. */ | |
5612 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
5613 | short_unsigned_type_node); | |
dfafc897 FS |
5614 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
5615 | ptr_type_node); | |
5616 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
5617 | ptr_type_node); | |
5618 | ||
9d30f3c1 JJ |
5619 | va_list_gpr_counter_field = f_gpr; |
5620 | va_list_fpr_counter_field = f_fpr; | |
5621 | ||
dfafc897 FS |
5622 | DECL_FIELD_CONTEXT (f_gpr) = record; |
5623 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 5624 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
5625 | DECL_FIELD_CONTEXT (f_ovf) = record; |
5626 | DECL_FIELD_CONTEXT (f_sav) = record; | |
5627 | ||
bab45a51 FS |
5628 | TREE_CHAIN (record) = type_decl; |
5629 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
5630 | TYPE_FIELDS (record) = f_gpr; |
5631 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
5632 | TREE_CHAIN (f_fpr) = f_res; |
5633 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
5634 | TREE_CHAIN (f_ovf) = f_sav; |
5635 | ||
5636 | layout_type (record); | |
5637 | ||
5638 | /* The correct type is an array type of one element. */ | |
5639 | return build_array_type (record, build_index_type (size_zero_node)); | |
5640 | } | |
5641 | ||
5642 | /* Implement va_start. */ | |
5643 | ||
5644 | void | |
a2369ed3 | 5645 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 5646 | { |
dfafc897 | 5647 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 5648 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 5649 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 5650 | |
dfafc897 | 5651 | /* Only SVR4 needs something special. */ |
f607bc57 | 5652 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 5653 | { |
e5faf155 | 5654 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
5655 | return; |
5656 | } | |
5657 | ||
973a648b | 5658 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 5659 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
5660 | f_res = TREE_CHAIN (f_fpr); |
5661 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
5662 | f_sav = TREE_CHAIN (f_ovf); |
5663 | ||
872a65b5 | 5664 | valist = build_va_arg_indirect_ref (valist); |
47a25a46 RG |
5665 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5666 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5667 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5668 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
dfafc897 FS |
5669 | |
5670 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 5671 | words = current_function_args_info.words; |
987732e0 DE |
5672 | n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG, |
5673 | GP_ARG_NUM_REG); | |
5674 | n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG, | |
5675 | FP_ARG_NUM_REG); | |
dfafc897 FS |
5676 | |
5677 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
5678 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
5679 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
5680 | words, n_gpr, n_fpr); | |
dfafc897 | 5681 | |
9d30f3c1 JJ |
5682 | if (cfun->va_list_gpr_size) |
5683 | { | |
47a25a46 RG |
5684 | t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, |
5685 | build_int_cst (NULL_TREE, n_gpr)); | |
9d30f3c1 JJ |
5686 | TREE_SIDE_EFFECTS (t) = 1; |
5687 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5688 | } | |
58c8adc1 | 5689 | |
9d30f3c1 JJ |
5690 | if (cfun->va_list_fpr_size) |
5691 | { | |
47a25a46 RG |
5692 | t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, |
5693 | build_int_cst (NULL_TREE, n_fpr)); | |
9d30f3c1 JJ |
5694 | TREE_SIDE_EFFECTS (t) = 1; |
5695 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5696 | } | |
dfafc897 FS |
5697 | |
5698 | /* Find the overflow area. */ | |
5699 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
5700 | if (words != 0) | |
47a25a46 RG |
5701 | t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t, |
5702 | build_int_cst (NULL_TREE, words * UNITS_PER_WORD)); | |
5703 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
dfafc897 FS |
5704 | TREE_SIDE_EFFECTS (t) = 1; |
5705 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5706 | ||
9d30f3c1 JJ |
5707 | /* If there were no va_arg invocations, don't set up the register |
5708 | save area. */ | |
5709 | if (!cfun->va_list_gpr_size | |
5710 | && !cfun->va_list_fpr_size | |
5711 | && n_gpr < GP_ARG_NUM_REG | |
5712 | && n_fpr < FP_ARG_V4_MAX_REG) | |
5713 | return; | |
5714 | ||
dfafc897 FS |
5715 | /* Find the register save area. */ |
5716 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
5b667039 | 5717 | if (cfun->machine->varargs_save_offset) |
47a25a46 RG |
5718 | t = build2 (PLUS_EXPR, TREE_TYPE (sav), t, |
5719 | build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset)); | |
5720 | t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
dfafc897 FS |
5721 | TREE_SIDE_EFFECTS (t) = 1; |
5722 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5723 | } | |
5724 | ||
5725 | /* Implement va_arg. */ | |
5726 | ||
23a60a04 JM |
5727 | tree |
5728 | rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) | |
cd3ce9b4 | 5729 | { |
cd3ce9b4 JM |
5730 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
5731 | tree gpr, fpr, ovf, sav, reg, t, u; | |
08b0dc1b | 5732 | int size, rsize, n_reg, sav_ofs, sav_scale; |
cd3ce9b4 JM |
5733 | tree lab_false, lab_over, addr; |
5734 | int align; | |
5735 | tree ptrtype = build_pointer_type (type); | |
5736 | ||
08b0dc1b RH |
5737 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
5738 | { | |
5739 | t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); | |
872a65b5 | 5740 | return build_va_arg_indirect_ref (t); |
08b0dc1b RH |
5741 | } |
5742 | ||
cd3ce9b4 JM |
5743 | if (DEFAULT_ABI != ABI_V4) |
5744 | { | |
08b0dc1b | 5745 | if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) |
cd3ce9b4 JM |
5746 | { |
5747 | tree elem_type = TREE_TYPE (type); | |
5748 | enum machine_mode elem_mode = TYPE_MODE (elem_type); | |
5749 | int elem_size = GET_MODE_SIZE (elem_mode); | |
5750 | ||
5751 | if (elem_size < UNITS_PER_WORD) | |
5752 | { | |
23a60a04 | 5753 | tree real_part, imag_part; |
cd3ce9b4 JM |
5754 | tree post = NULL_TREE; |
5755 | ||
23a60a04 JM |
5756 | real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5757 | &post); | |
5758 | /* Copy the value into a temporary, lest the formal temporary | |
5759 | be reused out from under us. */ | |
5760 | real_part = get_initialized_tmp_var (real_part, pre_p, &post); | |
cd3ce9b4 JM |
5761 | append_to_statement_list (post, pre_p); |
5762 | ||
23a60a04 JM |
5763 | imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5764 | post_p); | |
cd3ce9b4 | 5765 | |
47a25a46 | 5766 | return build2 (COMPLEX_EXPR, type, real_part, imag_part); |
cd3ce9b4 JM |
5767 | } |
5768 | } | |
5769 | ||
23a60a04 | 5770 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 JM |
5771 | } |
5772 | ||
5773 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
5774 | f_fpr = TREE_CHAIN (f_gpr); | |
5775 | f_res = TREE_CHAIN (f_fpr); | |
5776 | f_ovf = TREE_CHAIN (f_res); | |
5777 | f_sav = TREE_CHAIN (f_ovf); | |
5778 | ||
872a65b5 | 5779 | valist = build_va_arg_indirect_ref (valist); |
47a25a46 RG |
5780 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5781 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5782 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5783 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
cd3ce9b4 JM |
5784 | |
5785 | size = int_size_in_bytes (type); | |
5786 | rsize = (size + 3) / 4; | |
5787 | align = 1; | |
5788 | ||
08b0dc1b RH |
5789 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
5790 | && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode)) | |
cd3ce9b4 JM |
5791 | { |
5792 | /* FP args go in FP registers, if present. */ | |
cd3ce9b4 JM |
5793 | reg = fpr; |
5794 | n_reg = 1; | |
5795 | sav_ofs = 8*4; | |
5796 | sav_scale = 8; | |
5797 | if (TYPE_MODE (type) == DFmode) | |
5798 | align = 8; | |
5799 | } | |
5800 | else | |
5801 | { | |
5802 | /* Otherwise into GP registers. */ | |
cd3ce9b4 JM |
5803 | reg = gpr; |
5804 | n_reg = rsize; | |
5805 | sav_ofs = 0; | |
5806 | sav_scale = 4; | |
5807 | if (n_reg == 2) | |
5808 | align = 8; | |
5809 | } | |
5810 | ||
5811 | /* Pull the value out of the saved registers.... */ | |
5812 | ||
5813 | lab_over = NULL; | |
5814 | addr = create_tmp_var (ptr_type_node, "addr"); | |
5815 | DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); | |
5816 | ||
5817 | /* AltiVec vectors never go in registers when -mabi=altivec. */ | |
5818 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
5819 | align = 16; | |
5820 | else | |
5821 | { | |
5822 | lab_false = create_artificial_label (); | |
5823 | lab_over = create_artificial_label (); | |
5824 | ||
5825 | /* Long long and SPE vectors are aligned in the registers. | |
5826 | As are any other 2 gpr item such as complex int due to a | |
5827 | historical mistake. */ | |
5828 | u = reg; | |
5829 | if (n_reg == 2) | |
5830 | { | |
5831 | u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
95674810 | 5832 | size_int (n_reg - 1)); |
cd3ce9b4 JM |
5833 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u); |
5834 | } | |
5835 | ||
95674810 | 5836 | t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); |
cd3ce9b4 JM |
5837 | t = build2 (GE_EXPR, boolean_type_node, u, t); |
5838 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
5839 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
5840 | gimplify_and_add (t, pre_p); | |
5841 | ||
5842 | t = sav; | |
5843 | if (sav_ofs) | |
95674810 | 5844 | t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs)); |
cd3ce9b4 | 5845 | |
95674810 | 5846 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg)); |
cd3ce9b4 | 5847 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
95674810 | 5848 | u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale)); |
cd3ce9b4 JM |
5849 | t = build2 (PLUS_EXPR, ptr_type_node, t, u); |
5850 | ||
5851 | t = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5852 | gimplify_and_add (t, pre_p); | |
5853 | ||
5854 | t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
5855 | gimplify_and_add (t, pre_p); | |
5856 | ||
5857 | t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
5858 | append_to_statement_list (t, pre_p); | |
5859 | ||
5860 | if (n_reg > 2) | |
5861 | { | |
5862 | /* Ensure that we don't find any more args in regs. | |
5863 | Alignment has taken care of the n_reg == 2 case. */ | |
47a25a46 | 5864 | t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8)); |
cd3ce9b4 JM |
5865 | gimplify_and_add (t, pre_p); |
5866 | } | |
5867 | } | |
5868 | ||
5869 | /* ... otherwise out of the overflow area. */ | |
5870 | ||
5871 | /* Care for on-stack alignment if needed. */ | |
5872 | t = ovf; | |
5873 | if (align != 1) | |
5874 | { | |
95674810 | 5875 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1)); |
4a90aeeb | 5876 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
7d60be94 | 5877 | build_int_cst (NULL_TREE, -align)); |
cd3ce9b4 JM |
5878 | } |
5879 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
5880 | ||
5881 | u = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5882 | gimplify_and_add (u, pre_p); | |
5883 | ||
95674810 | 5884 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); |
cd3ce9b4 JM |
5885 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5886 | gimplify_and_add (t, pre_p); | |
5887 | ||
5888 | if (lab_over) | |
5889 | { | |
5890 | t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
5891 | append_to_statement_list (t, pre_p); | |
5892 | } | |
5893 | ||
08b0dc1b | 5894 | addr = fold_convert (ptrtype, addr); |
872a65b5 | 5895 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
5896 | } |
5897 | ||
0ac081f6 AH |
5898 | /* Builtins. */ |
5899 | ||
58646b77 PB |
5900 | static void |
5901 | def_builtin (int mask, const char *name, tree type, int code) | |
5902 | { | |
5903 | if (mask & target_flags) | |
5904 | { | |
5905 | if (rs6000_builtin_decls[code]) | |
5906 | abort (); | |
5907 | ||
5908 | rs6000_builtin_decls[code] = | |
5909 | lang_hooks.builtin_function (name, type, code, BUILT_IN_MD, | |
5910 | NULL, NULL_TREE); | |
5911 | } | |
5912 | } | |
0ac081f6 | 5913 | |
24408032 AH |
5914 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
5915 | ||
2212663f | 5916 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
5917 | { |
5918 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
5919 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
5920 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
5921 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
5922 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
5923 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
5924 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
5925 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
5926 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
5927 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
f676971a | 5928 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, |
aba5fb01 NS |
5929 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, |
5930 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
5931 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
5932 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
5933 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
5934 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
5935 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
5936 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
5937 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
5938 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
5939 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
5940 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
58646b77 PB |
5941 | |
5942 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD }, | |
5943 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS }, | |
5944 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD }, | |
5945 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS }, | |
5946 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM }, | |
5947 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM }, | |
5948 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM }, | |
5949 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM }, | |
5950 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM }, | |
5951 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS }, | |
5952 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS }, | |
5953 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS }, | |
5954 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB }, | |
5955 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM }, | |
5956 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL }, | |
24408032 | 5957 | }; |
2212663f | 5958 | |
95385cbb AH |
5959 | /* DST operations: void foo (void *, const int, const char). */ |
5960 | ||
5961 | static const struct builtin_description bdesc_dst[] = | |
5962 | { | |
5963 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
5964 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
5965 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
58646b77 PB |
5966 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }, |
5967 | ||
5968 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST }, | |
5969 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT }, | |
5970 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST }, | |
5971 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT } | |
95385cbb AH |
5972 | }; |
5973 | ||
2212663f | 5974 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 5975 | |
a3170dc6 | 5976 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 5977 | { |
f18c054f DB |
5978 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
5979 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
5980 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
5981 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
5982 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
5983 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
5984 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
5985 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
5986 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
5987 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
5988 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 5989 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
aba5fb01 | 5990 | { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
0ac081f6 AH |
5991 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, |
5992 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
5993 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
5994 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
5995 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
5996 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
5997 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
5998 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
5999 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
6000 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
6001 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
6002 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
6003 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
6004 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
6005 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
6006 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
6007 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
6008 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
6009 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
6010 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
6011 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
6012 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
6013 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
6014 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
6015 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
6016 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
6017 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
6018 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
6019 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
6020 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
6021 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
6022 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
6023 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
6024 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
6025 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
6026 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
6027 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
6028 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
6029 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
6030 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
6031 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
6032 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
6033 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
6034 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
6035 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
6036 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
6037 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
6038 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
6039 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
6040 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
6041 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
f96bc213 | 6042 | { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, |
f18c054f | 6043 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
6044 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
6045 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
6046 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
0ac081f6 | 6047 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, |
0ac081f6 AH |
6048 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, |
6049 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
6050 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
6051 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
6052 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
6053 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
6054 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
6055 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
6056 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
6057 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
6058 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
6059 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
6060 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
6061 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
6062 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
6063 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
3e0de9d1 DP |
6064 | { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
6065 | { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, | |
6066 | { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
6067 | { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, | |
6068 | { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
6069 | { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
0ac081f6 AH |
6070 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, |
6071 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
6072 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
6073 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
6074 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
6075 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
6076 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
6077 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
6078 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
6079 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
6080 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
6081 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
6082 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
6083 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
6084 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
6085 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
6086 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
6087 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 6088 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 | 6089 | |
58646b77 PB |
6090 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD }, |
6091 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP }, | |
6092 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM }, | |
6093 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM }, | |
6094 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM }, | |
6095 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC }, | |
6096 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS }, | |
6097 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS }, | |
6098 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS }, | |
6099 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS }, | |
6100 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS }, | |
6101 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS }, | |
6102 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS }, | |
6103 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND }, | |
6104 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC }, | |
6105 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG }, | |
6106 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW }, | |
6107 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW }, | |
6108 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH }, | |
6109 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH }, | |
6110 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB }, | |
6111 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB }, | |
6112 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB }, | |
6113 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ }, | |
6114 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP }, | |
6115 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW }, | |
6116 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH }, | |
6117 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB }, | |
6118 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE }, | |
6119 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT }, | |
6120 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP }, | |
6121 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW }, | |
6122 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW }, | |
6123 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH }, | |
6124 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH }, | |
6125 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB }, | |
6126 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB }, | |
6127 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE }, | |
6128 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT }, | |
6129 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX }, | |
6130 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP }, | |
6131 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW }, | |
6132 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW }, | |
6133 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH }, | |
6134 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH }, | |
6135 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB }, | |
6136 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB }, | |
6137 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH }, | |
6138 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW }, | |
6139 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH }, | |
6140 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB }, | |
6141 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL }, | |
6142 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW }, | |
6143 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH }, | |
6144 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB }, | |
6145 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN }, | |
6146 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP }, | |
6147 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW }, | |
6148 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW }, | |
6149 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH }, | |
6150 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH }, | |
6151 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB }, | |
6152 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB }, | |
6153 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE }, | |
6154 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB }, | |
6155 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB }, | |
6156 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH }, | |
6157 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH }, | |
6158 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO }, | |
6159 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH }, | |
6160 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH }, | |
6161 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB }, | |
6162 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB }, | |
6163 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR }, | |
6164 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR }, | |
6165 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK }, | |
6166 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM }, | |
6167 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM }, | |
6168 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX }, | |
6169 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS }, | |
6170 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS }, | |
6171 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS }, | |
6172 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS }, | |
6173 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS }, | |
6174 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU }, | |
6175 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS }, | |
6176 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS }, | |
6177 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL }, | |
6178 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW }, | |
6179 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH }, | |
6180 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB }, | |
6181 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL }, | |
6182 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW }, | |
6183 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH }, | |
6184 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB }, | |
6185 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL }, | |
6186 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO }, | |
6187 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR }, | |
6188 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW }, | |
6189 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH }, | |
6190 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB }, | |
6191 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA }, | |
6192 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW }, | |
6193 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH }, | |
6194 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB }, | |
6195 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL }, | |
6196 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO }, | |
6197 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB }, | |
6198 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP }, | |
6199 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM }, | |
6200 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM }, | |
6201 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM }, | |
6202 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC }, | |
6203 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS }, | |
6204 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS }, | |
6205 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS }, | |
6206 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS }, | |
6207 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS }, | |
6208 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS }, | |
6209 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS }, | |
6210 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S }, | |
6211 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS }, | |
6212 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS }, | |
6213 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS }, | |
6214 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S }, | |
6215 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS }, | |
6216 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR }, | |
6217 | ||
a3170dc6 AH |
6218 | /* Place holder, leave as first spe builtin. */ |
6219 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
6220 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
6221 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
6222 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
6223 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
6224 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
6225 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
6226 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
6227 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
6228 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
6229 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
6230 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
6231 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
6232 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
6233 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
6234 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
6235 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
6236 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
6237 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
6238 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
6239 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
6240 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
6241 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
6242 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
6243 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
6244 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
6245 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
6246 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
6247 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
6248 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
6249 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
6250 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
6251 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
6252 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
6253 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
6254 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
6255 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
6256 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
6257 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
6258 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
6259 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
6260 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
6261 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
6262 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
6263 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
6264 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
6265 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
6266 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
6267 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
6268 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
6269 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
6270 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
6271 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
6272 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
6273 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
6274 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
6275 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
6276 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
6277 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
6278 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
6279 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
6280 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
6281 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
6282 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
6283 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
6284 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
6285 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
6286 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
6287 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
6288 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
6289 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
6290 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
6291 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
6292 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
6293 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
6294 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
6295 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
6296 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
6297 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
6298 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
6299 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
6300 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
6301 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
6302 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
6303 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
6304 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
6305 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
6306 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
6307 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
6308 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
6309 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
6310 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
6311 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
6312 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
6313 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
6314 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
6315 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
6316 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
6317 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
6318 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
6319 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
6320 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
6321 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
6322 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
6323 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
6324 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
6325 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
6326 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
6327 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
6328 | ||
6329 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
6330 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
6331 | ||
6332 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
6333 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
6334 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
6335 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
6336 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
6337 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
6338 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
6339 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
6340 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
6341 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
6342 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
6343 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
6344 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
6345 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
6346 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
6347 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
6348 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
6349 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
6350 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
6351 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
6352 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
6353 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
6354 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
6355 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
6356 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
6357 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
6358 | ||
6359 | /* Place-holder. Leave as last binary SPE builtin. */ | |
58646b77 | 6360 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR } |
ae4b4a02 AH |
6361 | }; |
6362 | ||
6363 | /* AltiVec predicates. */ | |
6364 | ||
6365 | struct builtin_description_predicates | |
6366 | { | |
6367 | const unsigned int mask; | |
6368 | const enum insn_code icode; | |
6369 | const char *opcode; | |
6370 | const char *const name; | |
6371 | const enum rs6000_builtins code; | |
6372 | }; | |
6373 | ||
6374 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
6375 | { | |
6376 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
6377 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
6378 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
6379 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
6380 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
6381 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
6382 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
6383 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
6384 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
6385 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
6386 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
6387 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
58646b77 PB |
6388 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }, |
6389 | ||
6390 | { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P }, | |
6391 | { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P }, | |
6392 | { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P } | |
0ac081f6 | 6393 | }; |
24408032 | 6394 | |
a3170dc6 AH |
6395 | /* SPE predicates. */ |
6396 | static struct builtin_description bdesc_spe_predicates[] = | |
6397 | { | |
6398 | /* Place-holder. Leave as first. */ | |
6399 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
6400 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
6401 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
6402 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
6403 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
6404 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
6405 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
6406 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
6407 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
6408 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
6409 | /* Place-holder. Leave as last. */ | |
6410 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
6411 | }; | |
6412 | ||
6413 | /* SPE evsel predicates. */ | |
6414 | static struct builtin_description bdesc_spe_evsel[] = | |
6415 | { | |
6416 | /* Place-holder. Leave as first. */ | |
6417 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
6418 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
6419 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
6420 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
6421 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
6422 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
6423 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
6424 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
6425 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
6426 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
6427 | /* Place-holder. Leave as last. */ | |
6428 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
6429 | }; | |
6430 | ||
b6d08ca1 | 6431 | /* ABS* operations. */ |
100c4561 AH |
6432 | |
6433 | static const struct builtin_description bdesc_abs[] = | |
6434 | { | |
6435 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
6436 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
6437 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
6438 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
6439 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
6440 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
6441 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
6442 | }; | |
6443 | ||
617e0e1d DB |
6444 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
6445 | foo (VECa). */ | |
24408032 | 6446 | |
a3170dc6 | 6447 | static struct builtin_description bdesc_1arg[] = |
2212663f | 6448 | { |
617e0e1d DB |
6449 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
6450 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
6451 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
6452 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
6453 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
6454 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
6455 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
6456 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
6457 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
6458 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
6459 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
6460 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
6461 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
6462 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
6463 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
6464 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
6465 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 | 6466 | |
58646b77 PB |
6467 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS }, |
6468 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS }, | |
6469 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL }, | |
6470 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE }, | |
6471 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR }, | |
6472 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE }, | |
6473 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR }, | |
6474 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE }, | |
6475 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND }, | |
6476 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE }, | |
6477 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC }, | |
6478 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH }, | |
6479 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH }, | |
6480 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX }, | |
6481 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB }, | |
6482 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL }, | |
6483 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX }, | |
6484 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH }, | |
6485 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB }, | |
6486 | ||
a3170dc6 AH |
6487 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and |
6488 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
6489 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
6490 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
6491 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
6492 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
6493 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
6494 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
6495 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
6496 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
6497 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
6498 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
6499 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
6500 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
6501 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
6502 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
6503 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
6504 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
6505 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
6506 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
6507 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
6508 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
6509 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
6510 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
6511 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
6a599451 | 6512 | { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, |
a3170dc6 AH |
6513 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, |
6514 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
6515 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
6516 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
6517 | |
6518 | /* Place-holder. Leave as last unary SPE builtin. */ | |
58646b77 | 6519 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW } |
2212663f DB |
6520 | }; |
6521 | ||
6522 | static rtx | |
a2369ed3 | 6523 | rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6524 | { |
6525 | rtx pat; | |
6526 | tree arg0 = TREE_VALUE (arglist); | |
6527 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6528 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6529 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6530 | ||
0559cc77 DE |
6531 | if (icode == CODE_FOR_nothing) |
6532 | /* Builtin not supported on this processor. */ | |
6533 | return 0; | |
6534 | ||
20e26713 AH |
6535 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6536 | if (arg0 == error_mark_node) | |
9a171fcd | 6537 | return const0_rtx; |
20e26713 | 6538 | |
0559cc77 DE |
6539 | if (icode == CODE_FOR_altivec_vspltisb |
6540 | || icode == CODE_FOR_altivec_vspltish | |
6541 | || icode == CODE_FOR_altivec_vspltisw | |
6542 | || icode == CODE_FOR_spe_evsplatfi | |
6543 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
6544 | { |
6545 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 | 6546 | if (GET_CODE (op0) != CONST_INT |
afca671b DP |
6547 | || INTVAL (op0) > 15 |
6548 | || INTVAL (op0) < -16) | |
b44140e7 AH |
6549 | { |
6550 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 6551 | return const0_rtx; |
b44140e7 | 6552 | } |
b44140e7 AH |
6553 | } |
6554 | ||
c62f2db5 | 6555 | if (target == 0 |
2212663f DB |
6556 | || GET_MODE (target) != tmode |
6557 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6558 | target = gen_reg_rtx (tmode); | |
6559 | ||
6560 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6561 | op0 = copy_to_mode_reg (mode0, op0); | |
6562 | ||
6563 | pat = GEN_FCN (icode) (target, op0); | |
6564 | if (! pat) | |
6565 | return 0; | |
6566 | emit_insn (pat); | |
0ac081f6 | 6567 | |
2212663f DB |
6568 | return target; |
6569 | } | |
ae4b4a02 | 6570 | |
100c4561 | 6571 | static rtx |
a2369ed3 | 6572 | altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) |
100c4561 AH |
6573 | { |
6574 | rtx pat, scratch1, scratch2; | |
6575 | tree arg0 = TREE_VALUE (arglist); | |
6576 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6577 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6578 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6579 | ||
6580 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6581 | if (arg0 == error_mark_node) | |
9a171fcd | 6582 | return const0_rtx; |
100c4561 AH |
6583 | |
6584 | if (target == 0 | |
6585 | || GET_MODE (target) != tmode | |
6586 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6587 | target = gen_reg_rtx (tmode); | |
6588 | ||
6589 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6590 | op0 = copy_to_mode_reg (mode0, op0); | |
6591 | ||
6592 | scratch1 = gen_reg_rtx (mode0); | |
6593 | scratch2 = gen_reg_rtx (mode0); | |
6594 | ||
6595 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
6596 | if (! pat) | |
6597 | return 0; | |
6598 | emit_insn (pat); | |
6599 | ||
6600 | return target; | |
6601 | } | |
6602 | ||
0ac081f6 | 6603 | static rtx |
a2369ed3 | 6604 | rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
0ac081f6 AH |
6605 | { |
6606 | rtx pat; | |
6607 | tree arg0 = TREE_VALUE (arglist); | |
6608 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6609 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6610 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6611 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6612 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6613 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6614 | ||
0559cc77 DE |
6615 | if (icode == CODE_FOR_nothing) |
6616 | /* Builtin not supported on this processor. */ | |
6617 | return 0; | |
6618 | ||
20e26713 AH |
6619 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6620 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6621 | return const0_rtx; |
20e26713 | 6622 | |
0559cc77 DE |
6623 | if (icode == CODE_FOR_altivec_vcfux |
6624 | || icode == CODE_FOR_altivec_vcfsx | |
6625 | || icode == CODE_FOR_altivec_vctsxs | |
6626 | || icode == CODE_FOR_altivec_vctuxs | |
6627 | || icode == CODE_FOR_altivec_vspltb | |
6628 | || icode == CODE_FOR_altivec_vsplth | |
6629 | || icode == CODE_FOR_altivec_vspltw | |
6630 | || icode == CODE_FOR_spe_evaddiw | |
6631 | || icode == CODE_FOR_spe_evldd | |
6632 | || icode == CODE_FOR_spe_evldh | |
6633 | || icode == CODE_FOR_spe_evldw | |
6634 | || icode == CODE_FOR_spe_evlhhesplat | |
6635 | || icode == CODE_FOR_spe_evlhhossplat | |
6636 | || icode == CODE_FOR_spe_evlhhousplat | |
6637 | || icode == CODE_FOR_spe_evlwhe | |
6638 | || icode == CODE_FOR_spe_evlwhos | |
6639 | || icode == CODE_FOR_spe_evlwhou | |
6640 | || icode == CODE_FOR_spe_evlwhsplat | |
6641 | || icode == CODE_FOR_spe_evlwwsplat | |
6642 | || icode == CODE_FOR_spe_evrlwi | |
6643 | || icode == CODE_FOR_spe_evslwi | |
6644 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 6645 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 6646 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
6647 | { |
6648 | /* Only allow 5-bit unsigned literals. */ | |
8bb418a3 | 6649 | STRIP_NOPS (arg1); |
b44140e7 AH |
6650 | if (TREE_CODE (arg1) != INTEGER_CST |
6651 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6652 | { | |
6653 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 6654 | return const0_rtx; |
b44140e7 | 6655 | } |
b44140e7 AH |
6656 | } |
6657 | ||
c62f2db5 | 6658 | if (target == 0 |
0ac081f6 AH |
6659 | || GET_MODE (target) != tmode |
6660 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6661 | target = gen_reg_rtx (tmode); | |
6662 | ||
6663 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6664 | op0 = copy_to_mode_reg (mode0, op0); | |
6665 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6666 | op1 = copy_to_mode_reg (mode1, op1); | |
6667 | ||
6668 | pat = GEN_FCN (icode) (target, op0, op1); | |
6669 | if (! pat) | |
6670 | return 0; | |
6671 | emit_insn (pat); | |
6672 | ||
6673 | return target; | |
6674 | } | |
6525c0e7 | 6675 | |
ae4b4a02 | 6676 | static rtx |
f676971a | 6677 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
a2369ed3 | 6678 | tree arglist, rtx target) |
ae4b4a02 AH |
6679 | { |
6680 | rtx pat, scratch; | |
6681 | tree cr6_form = TREE_VALUE (arglist); | |
6682 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6683 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6684 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6685 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6686 | enum machine_mode tmode = SImode; | |
6687 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6688 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6689 | int cr6_form_int; | |
6690 | ||
6691 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
6692 | { | |
6693 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 6694 | return const0_rtx; |
ae4b4a02 AH |
6695 | } |
6696 | else | |
6697 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
6698 | ||
37409796 | 6699 | gcc_assert (mode0 == mode1); |
ae4b4a02 AH |
6700 | |
6701 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6702 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6703 | return const0_rtx; |
ae4b4a02 AH |
6704 | |
6705 | if (target == 0 | |
6706 | || GET_MODE (target) != tmode | |
6707 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6708 | target = gen_reg_rtx (tmode); | |
6709 | ||
6710 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6711 | op0 = copy_to_mode_reg (mode0, op0); | |
6712 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6713 | op1 = copy_to_mode_reg (mode1, op1); | |
6714 | ||
6715 | scratch = gen_reg_rtx (mode0); | |
6716 | ||
6717 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 6718 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
6719 | if (! pat) |
6720 | return 0; | |
6721 | emit_insn (pat); | |
6722 | ||
6723 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
6724 | different operations, but the bits in CR6 will be different | |
6725 | depending on what information we want. So we have to play tricks | |
6726 | with CR6 to get the right bits out. | |
6727 | ||
6728 | If you think this is disgusting, look at the specs for the | |
6729 | AltiVec predicates. */ | |
6730 | ||
c4ad648e AM |
6731 | switch (cr6_form_int) |
6732 | { | |
6733 | case 0: | |
6734 | emit_insn (gen_cr6_test_for_zero (target)); | |
6735 | break; | |
6736 | case 1: | |
6737 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
6738 | break; | |
6739 | case 2: | |
6740 | emit_insn (gen_cr6_test_for_lt (target)); | |
6741 | break; | |
6742 | case 3: | |
6743 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
6744 | break; | |
6745 | default: | |
6746 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
6747 | break; | |
6748 | } | |
ae4b4a02 AH |
6749 | |
6750 | return target; | |
6751 | } | |
6752 | ||
b4a62fa0 | 6753 | static rtx |
38f391a5 | 6754 | altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) |
b4a62fa0 SB |
6755 | { |
6756 | rtx pat, addr; | |
6757 | tree arg0 = TREE_VALUE (arglist); | |
6758 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6759 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6760 | enum machine_mode mode0 = Pmode; | |
6761 | enum machine_mode mode1 = Pmode; | |
6762 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6763 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6764 | ||
6765 | if (icode == CODE_FOR_nothing) | |
6766 | /* Builtin not supported on this processor. */ | |
6767 | return 0; | |
6768 | ||
6769 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6770 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6771 | return const0_rtx; | |
6772 | ||
6773 | if (target == 0 | |
6774 | || GET_MODE (target) != tmode | |
6775 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6776 | target = gen_reg_rtx (tmode); | |
6777 | ||
f676971a | 6778 | op1 = copy_to_mode_reg (mode1, op1); |
b4a62fa0 SB |
6779 | |
6780 | if (op0 == const0_rtx) | |
6781 | { | |
6782 | addr = gen_rtx_MEM (tmode, op1); | |
6783 | } | |
6784 | else | |
6785 | { | |
6786 | op0 = copy_to_mode_reg (mode0, op0); | |
6787 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
6788 | } | |
6789 | ||
6790 | pat = GEN_FCN (icode) (target, addr); | |
6791 | ||
6792 | if (! pat) | |
6793 | return 0; | |
6794 | emit_insn (pat); | |
6795 | ||
6796 | return target; | |
6797 | } | |
6798 | ||
61bea3b0 AH |
6799 | static rtx |
6800 | spe_expand_stv_builtin (enum insn_code icode, tree arglist) | |
6801 | { | |
6802 | tree arg0 = TREE_VALUE (arglist); | |
6803 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6804 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6805 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6806 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6807 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6808 | rtx pat; | |
6809 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
6810 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
6811 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
6812 | ||
6813 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6814 | if (arg0 == error_mark_node | |
6815 | || arg1 == error_mark_node | |
6816 | || arg2 == error_mark_node) | |
6817 | return const0_rtx; | |
6818 | ||
6819 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
6820 | op0 = copy_to_mode_reg (mode2, op0); | |
6821 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
6822 | op1 = copy_to_mode_reg (mode0, op1); | |
6823 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6824 | op2 = copy_to_mode_reg (mode1, op2); | |
6825 | ||
6826 | pat = GEN_FCN (icode) (op1, op2, op0); | |
6827 | if (pat) | |
6828 | emit_insn (pat); | |
6829 | return NULL_RTX; | |
6830 | } | |
6831 | ||
6525c0e7 | 6832 | static rtx |
a2369ed3 | 6833 | altivec_expand_stv_builtin (enum insn_code icode, tree arglist) |
6525c0e7 AH |
6834 | { |
6835 | tree arg0 = TREE_VALUE (arglist); | |
6836 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6837 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6838 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6839 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6840 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
b4a62fa0 SB |
6841 | rtx pat, addr; |
6842 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6843 | enum machine_mode mode1 = Pmode; | |
6844 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
6845 | |
6846 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6847 | if (arg0 == error_mark_node | |
6848 | || arg1 == error_mark_node | |
6849 | || arg2 == error_mark_node) | |
9a171fcd | 6850 | return const0_rtx; |
6525c0e7 | 6851 | |
b4a62fa0 SB |
6852 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
6853 | op0 = copy_to_mode_reg (tmode, op0); | |
6854 | ||
f676971a | 6855 | op2 = copy_to_mode_reg (mode2, op2); |
b4a62fa0 SB |
6856 | |
6857 | if (op1 == const0_rtx) | |
6858 | { | |
6859 | addr = gen_rtx_MEM (tmode, op2); | |
6860 | } | |
6861 | else | |
6862 | { | |
6863 | op1 = copy_to_mode_reg (mode1, op1); | |
6864 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
6865 | } | |
6525c0e7 | 6866 | |
b4a62fa0 | 6867 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
6868 | if (pat) |
6869 | emit_insn (pat); | |
6870 | return NULL_RTX; | |
6871 | } | |
6872 | ||
2212663f | 6873 | static rtx |
a2369ed3 | 6874 | rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6875 | { |
6876 | rtx pat; | |
6877 | tree arg0 = TREE_VALUE (arglist); | |
6878 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6879 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6880 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6881 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6882 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6883 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6884 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6885 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6886 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 6887 | |
774b5662 DE |
6888 | if (icode == CODE_FOR_nothing) |
6889 | /* Builtin not supported on this processor. */ | |
6890 | return 0; | |
6891 | ||
20e26713 AH |
6892 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6893 | if (arg0 == error_mark_node | |
6894 | || arg1 == error_mark_node | |
6895 | || arg2 == error_mark_node) | |
9a171fcd | 6896 | return const0_rtx; |
20e26713 | 6897 | |
aba5fb01 NS |
6898 | if (icode == CODE_FOR_altivec_vsldoi_v4sf |
6899 | || icode == CODE_FOR_altivec_vsldoi_v4si | |
6900 | || icode == CODE_FOR_altivec_vsldoi_v8hi | |
6901 | || icode == CODE_FOR_altivec_vsldoi_v16qi) | |
b44140e7 AH |
6902 | { |
6903 | /* Only allow 4-bit unsigned literals. */ | |
8bb418a3 | 6904 | STRIP_NOPS (arg2); |
b44140e7 AH |
6905 | if (TREE_CODE (arg2) != INTEGER_CST |
6906 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
6907 | { | |
6908 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 6909 | return const0_rtx; |
b44140e7 | 6910 | } |
b44140e7 AH |
6911 | } |
6912 | ||
c62f2db5 | 6913 | if (target == 0 |
2212663f DB |
6914 | || GET_MODE (target) != tmode |
6915 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6916 | target = gen_reg_rtx (tmode); | |
6917 | ||
6918 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6919 | op0 = copy_to_mode_reg (mode0, op0); | |
6920 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6921 | op1 = copy_to_mode_reg (mode1, op1); | |
6922 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
6923 | op2 = copy_to_mode_reg (mode2, op2); | |
6924 | ||
6925 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
6926 | if (! pat) | |
6927 | return 0; | |
6928 | emit_insn (pat); | |
6929 | ||
6930 | return target; | |
6931 | } | |
92898235 | 6932 | |
3a9b8c7e | 6933 | /* Expand the lvx builtins. */ |
0ac081f6 | 6934 | static rtx |
a2369ed3 | 6935 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 6936 | { |
0ac081f6 AH |
6937 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6938 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 6939 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
6940 | tree arg0; |
6941 | enum machine_mode tmode, mode0; | |
7c3abc73 | 6942 | rtx pat, op0; |
3a9b8c7e | 6943 | enum insn_code icode; |
92898235 | 6944 | |
0ac081f6 AH |
6945 | switch (fcode) |
6946 | { | |
f18c054f | 6947 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
81466555 | 6948 | icode = CODE_FOR_altivec_lvx_v16qi; |
3a9b8c7e | 6949 | break; |
f18c054f | 6950 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
81466555 | 6951 | icode = CODE_FOR_altivec_lvx_v8hi; |
3a9b8c7e AH |
6952 | break; |
6953 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
81466555 | 6954 | icode = CODE_FOR_altivec_lvx_v4si; |
3a9b8c7e AH |
6955 | break; |
6956 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
81466555 | 6957 | icode = CODE_FOR_altivec_lvx_v4sf; |
3a9b8c7e AH |
6958 | break; |
6959 | default: | |
6960 | *expandedp = false; | |
6961 | return NULL_RTX; | |
6962 | } | |
0ac081f6 | 6963 | |
3a9b8c7e | 6964 | *expandedp = true; |
f18c054f | 6965 | |
3a9b8c7e AH |
6966 | arg0 = TREE_VALUE (arglist); |
6967 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6968 | tmode = insn_data[icode].operand[0].mode; | |
6969 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 6970 | |
3a9b8c7e AH |
6971 | if (target == 0 |
6972 | || GET_MODE (target) != tmode | |
6973 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6974 | target = gen_reg_rtx (tmode); | |
24408032 | 6975 | |
3a9b8c7e AH |
6976 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
6977 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 6978 | |
3a9b8c7e AH |
6979 | pat = GEN_FCN (icode) (target, op0); |
6980 | if (! pat) | |
6981 | return 0; | |
6982 | emit_insn (pat); | |
6983 | return target; | |
6984 | } | |
f18c054f | 6985 | |
3a9b8c7e AH |
6986 | /* Expand the stvx builtins. */ |
6987 | static rtx | |
f676971a | 6988 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 6989 | bool *expandedp) |
3a9b8c7e AH |
6990 | { |
6991 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6992 | tree arglist = TREE_OPERAND (exp, 1); | |
6993 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6994 | tree arg0, arg1; | |
6995 | enum machine_mode mode0, mode1; | |
7c3abc73 | 6996 | rtx pat, op0, op1; |
3a9b8c7e | 6997 | enum insn_code icode; |
f18c054f | 6998 | |
3a9b8c7e AH |
6999 | switch (fcode) |
7000 | { | |
7001 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
81466555 | 7002 | icode = CODE_FOR_altivec_stvx_v16qi; |
3a9b8c7e AH |
7003 | break; |
7004 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
81466555 | 7005 | icode = CODE_FOR_altivec_stvx_v8hi; |
3a9b8c7e AH |
7006 | break; |
7007 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
81466555 | 7008 | icode = CODE_FOR_altivec_stvx_v4si; |
3a9b8c7e AH |
7009 | break; |
7010 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
81466555 | 7011 | icode = CODE_FOR_altivec_stvx_v4sf; |
3a9b8c7e AH |
7012 | break; |
7013 | default: | |
7014 | *expandedp = false; | |
7015 | return NULL_RTX; | |
7016 | } | |
24408032 | 7017 | |
3a9b8c7e AH |
7018 | arg0 = TREE_VALUE (arglist); |
7019 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7020 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7021 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7022 | mode0 = insn_data[icode].operand[0].mode; | |
7023 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 7024 | |
3a9b8c7e AH |
7025 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
7026 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
7027 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
7028 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 7029 | |
3a9b8c7e AH |
7030 | pat = GEN_FCN (icode) (op0, op1); |
7031 | if (pat) | |
7032 | emit_insn (pat); | |
f18c054f | 7033 | |
3a9b8c7e AH |
7034 | *expandedp = true; |
7035 | return NULL_RTX; | |
7036 | } | |
f18c054f | 7037 | |
3a9b8c7e AH |
7038 | /* Expand the dst builtins. */ |
7039 | static rtx | |
f676971a | 7040 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 7041 | bool *expandedp) |
3a9b8c7e AH |
7042 | { |
7043 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
7044 | tree arglist = TREE_OPERAND (exp, 1); | |
7045 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7046 | tree arg0, arg1, arg2; | |
7047 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 7048 | rtx pat, op0, op1, op2; |
3a9b8c7e | 7049 | struct builtin_description *d; |
a3170dc6 | 7050 | size_t i; |
f18c054f | 7051 | |
3a9b8c7e | 7052 | *expandedp = false; |
f18c054f | 7053 | |
3a9b8c7e AH |
7054 | /* Handle DST variants. */ |
7055 | d = (struct builtin_description *) bdesc_dst; | |
7056 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
7057 | if (d->code == fcode) | |
7058 | { | |
7059 | arg0 = TREE_VALUE (arglist); | |
7060 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7061 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7062 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7063 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7064 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
7065 | mode0 = insn_data[d->icode].operand[0].mode; | |
7066 | mode1 = insn_data[d->icode].operand[1].mode; | |
7067 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 7068 | |
3a9b8c7e AH |
7069 | /* Invalid arguments, bail out before generating bad rtl. */ |
7070 | if (arg0 == error_mark_node | |
7071 | || arg1 == error_mark_node | |
7072 | || arg2 == error_mark_node) | |
7073 | return const0_rtx; | |
f18c054f | 7074 | |
86e7df90 | 7075 | *expandedp = true; |
8bb418a3 | 7076 | STRIP_NOPS (arg2); |
3a9b8c7e AH |
7077 | if (TREE_CODE (arg2) != INTEGER_CST |
7078 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
7079 | { | |
9e637a26 | 7080 | error ("argument to %qs must be a 2-bit unsigned literal", d->name); |
3a9b8c7e AH |
7081 | return const0_rtx; |
7082 | } | |
f18c054f | 7083 | |
3a9b8c7e | 7084 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
666158b9 | 7085 | op0 = copy_to_mode_reg (Pmode, op0); |
3a9b8c7e AH |
7086 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
7087 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 7088 | |
3a9b8c7e AH |
7089 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
7090 | if (pat != 0) | |
7091 | emit_insn (pat); | |
f18c054f | 7092 | |
3a9b8c7e AH |
7093 | return NULL_RTX; |
7094 | } | |
f18c054f | 7095 | |
3a9b8c7e AH |
7096 | return NULL_RTX; |
7097 | } | |
24408032 | 7098 | |
7a4eca66 DE |
7099 | /* Expand vec_init builtin. */ |
7100 | static rtx | |
7101 | altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target) | |
7102 | { | |
7103 | enum machine_mode tmode = TYPE_MODE (type); | |
7104 | enum machine_mode inner_mode = GET_MODE_INNER (tmode); | |
7105 | int i, n_elt = GET_MODE_NUNITS (tmode); | |
7106 | rtvec v = rtvec_alloc (n_elt); | |
7107 | ||
7108 | gcc_assert (VECTOR_MODE_P (tmode)); | |
7109 | ||
7110 | for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist)) | |
7111 | { | |
7112 | rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0); | |
7113 | RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x); | |
7114 | } | |
7115 | ||
7116 | gcc_assert (arglist == NULL); | |
7117 | ||
7118 | if (!target || !register_operand (target, tmode)) | |
7119 | target = gen_reg_rtx (tmode); | |
7120 | ||
7121 | rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v)); | |
7122 | return target; | |
7123 | } | |
7124 | ||
7125 | /* Return the integer constant in ARG. Constrain it to be in the range | |
7126 | of the subparts of VEC_TYPE; issue an error if not. */ | |
7127 | ||
7128 | static int | |
7129 | get_element_number (tree vec_type, tree arg) | |
7130 | { | |
7131 | unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1; | |
7132 | ||
7133 | if (!host_integerp (arg, 1) | |
7134 | || (elt = tree_low_cst (arg, 1), elt > max)) | |
7135 | { | |
7136 | error ("selector must be an integer constant in the range 0..%wi", max); | |
7137 | return 0; | |
7138 | } | |
7139 | ||
7140 | return elt; | |
7141 | } | |
7142 | ||
7143 | /* Expand vec_set builtin. */ | |
7144 | static rtx | |
7145 | altivec_expand_vec_set_builtin (tree arglist) | |
7146 | { | |
7147 | enum machine_mode tmode, mode1; | |
7148 | tree arg0, arg1, arg2; | |
7149 | int elt; | |
7150 | rtx op0, op1; | |
7151 | ||
7152 | arg0 = TREE_VALUE (arglist); | |
7153 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7154 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7155 | ||
7156 | tmode = TYPE_MODE (TREE_TYPE (arg0)); | |
7157 | mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); | |
7158 | gcc_assert (VECTOR_MODE_P (tmode)); | |
7159 | ||
7160 | op0 = expand_expr (arg0, NULL_RTX, tmode, 0); | |
7161 | op1 = expand_expr (arg1, NULL_RTX, mode1, 0); | |
7162 | elt = get_element_number (TREE_TYPE (arg0), arg2); | |
7163 | ||
7164 | if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode) | |
7165 | op1 = convert_modes (mode1, GET_MODE (op1), op1, true); | |
7166 | ||
7167 | op0 = force_reg (tmode, op0); | |
7168 | op1 = force_reg (mode1, op1); | |
7169 | ||
7170 | rs6000_expand_vector_set (op0, op1, elt); | |
7171 | ||
7172 | return op0; | |
7173 | } | |
7174 | ||
7175 | /* Expand vec_ext builtin. */ | |
7176 | static rtx | |
7177 | altivec_expand_vec_ext_builtin (tree arglist, rtx target) | |
7178 | { | |
7179 | enum machine_mode tmode, mode0; | |
7180 | tree arg0, arg1; | |
7181 | int elt; | |
7182 | rtx op0; | |
7183 | ||
7184 | arg0 = TREE_VALUE (arglist); | |
7185 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7186 | ||
7187 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7188 | elt = get_element_number (TREE_TYPE (arg0), arg1); | |
7189 | ||
7190 | tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); | |
7191 | mode0 = TYPE_MODE (TREE_TYPE (arg0)); | |
7192 | gcc_assert (VECTOR_MODE_P (mode0)); | |
7193 | ||
7194 | op0 = force_reg (mode0, op0); | |
7195 | ||
7196 | if (optimize || !target || !register_operand (target, tmode)) | |
7197 | target = gen_reg_rtx (tmode); | |
7198 | ||
7199 | rs6000_expand_vector_extract (target, op0, elt); | |
7200 | ||
7201 | return target; | |
7202 | } | |
7203 | ||
3a9b8c7e AH |
7204 | /* Expand the builtin in EXP and store the result in TARGET. Store |
7205 | true in *EXPANDEDP if we found a builtin to expand. */ | |
7206 | static rtx | |
a2369ed3 | 7207 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e AH |
7208 | { |
7209 | struct builtin_description *d; | |
7210 | struct builtin_description_predicates *dp; | |
7211 | size_t i; | |
7212 | enum insn_code icode; | |
7213 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
7214 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
7215 | tree arg0; |
7216 | rtx op0, pat; | |
7217 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 7218 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 7219 | |
58646b77 PB |
7220 | if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
7221 | && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST) | |
7222 | { | |
7223 | *expandedp = true; | |
ea40ba9c | 7224 | error ("unresolved overload for Altivec builtin %qF", fndecl); |
58646b77 PB |
7225 | return const0_rtx; |
7226 | } | |
7227 | ||
3a9b8c7e AH |
7228 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
7229 | if (*expandedp) | |
7230 | return target; | |
0ac081f6 | 7231 | |
3a9b8c7e AH |
7232 | target = altivec_expand_st_builtin (exp, target, expandedp); |
7233 | if (*expandedp) | |
7234 | return target; | |
7235 | ||
7236 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
7237 | if (*expandedp) | |
7238 | return target; | |
7239 | ||
7240 | *expandedp = true; | |
95385cbb | 7241 | |
3a9b8c7e AH |
7242 | switch (fcode) |
7243 | { | |
6525c0e7 AH |
7244 | case ALTIVEC_BUILTIN_STVX: |
7245 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
7246 | case ALTIVEC_BUILTIN_STVEBX: | |
7247 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
7248 | case ALTIVEC_BUILTIN_STVEHX: | |
7249 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
7250 | case ALTIVEC_BUILTIN_STVEWX: | |
7251 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
7252 | case ALTIVEC_BUILTIN_STVXL: | |
7253 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 7254 | |
95385cbb AH |
7255 | case ALTIVEC_BUILTIN_MFVSCR: |
7256 | icode = CODE_FOR_altivec_mfvscr; | |
7257 | tmode = insn_data[icode].operand[0].mode; | |
7258 | ||
7259 | if (target == 0 | |
7260 | || GET_MODE (target) != tmode | |
7261 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7262 | target = gen_reg_rtx (tmode); | |
f676971a | 7263 | |
95385cbb | 7264 | pat = GEN_FCN (icode) (target); |
0ac081f6 AH |
7265 | if (! pat) |
7266 | return 0; | |
7267 | emit_insn (pat); | |
95385cbb AH |
7268 | return target; |
7269 | ||
7270 | case ALTIVEC_BUILTIN_MTVSCR: | |
7271 | icode = CODE_FOR_altivec_mtvscr; | |
7272 | arg0 = TREE_VALUE (arglist); | |
7273 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7274 | mode0 = insn_data[icode].operand[0].mode; | |
7275 | ||
7276 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
7277 | if (arg0 == error_mark_node) | |
9a171fcd | 7278 | return const0_rtx; |
95385cbb AH |
7279 | |
7280 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
7281 | op0 = copy_to_mode_reg (mode0, op0); | |
7282 | ||
7283 | pat = GEN_FCN (icode) (op0); | |
7284 | if (pat) | |
7285 | emit_insn (pat); | |
7286 | return NULL_RTX; | |
3a9b8c7e | 7287 | |
95385cbb AH |
7288 | case ALTIVEC_BUILTIN_DSSALL: |
7289 | emit_insn (gen_altivec_dssall ()); | |
7290 | return NULL_RTX; | |
7291 | ||
7292 | case ALTIVEC_BUILTIN_DSS: | |
7293 | icode = CODE_FOR_altivec_dss; | |
7294 | arg0 = TREE_VALUE (arglist); | |
8bb418a3 | 7295 | STRIP_NOPS (arg0); |
95385cbb AH |
7296 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
7297 | mode0 = insn_data[icode].operand[0].mode; | |
7298 | ||
7299 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
7300 | if (arg0 == error_mark_node) | |
9a171fcd | 7301 | return const0_rtx; |
95385cbb | 7302 | |
b44140e7 AH |
7303 | if (TREE_CODE (arg0) != INTEGER_CST |
7304 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
7305 | { | |
7306 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 7307 | return const0_rtx; |
b44140e7 AH |
7308 | } |
7309 | ||
95385cbb AH |
7310 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
7311 | op0 = copy_to_mode_reg (mode0, op0); | |
7312 | ||
7313 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 | 7314 | return NULL_RTX; |
7a4eca66 DE |
7315 | |
7316 | case ALTIVEC_BUILTIN_VEC_INIT_V4SI: | |
7317 | case ALTIVEC_BUILTIN_VEC_INIT_V8HI: | |
7318 | case ALTIVEC_BUILTIN_VEC_INIT_V16QI: | |
7319 | case ALTIVEC_BUILTIN_VEC_INIT_V4SF: | |
7320 | return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target); | |
7321 | ||
7322 | case ALTIVEC_BUILTIN_VEC_SET_V4SI: | |
7323 | case ALTIVEC_BUILTIN_VEC_SET_V8HI: | |
7324 | case ALTIVEC_BUILTIN_VEC_SET_V16QI: | |
7325 | case ALTIVEC_BUILTIN_VEC_SET_V4SF: | |
7326 | return altivec_expand_vec_set_builtin (arglist); | |
7327 | ||
7328 | case ALTIVEC_BUILTIN_VEC_EXT_V4SI: | |
7329 | case ALTIVEC_BUILTIN_VEC_EXT_V8HI: | |
7330 | case ALTIVEC_BUILTIN_VEC_EXT_V16QI: | |
7331 | case ALTIVEC_BUILTIN_VEC_EXT_V4SF: | |
7332 | return altivec_expand_vec_ext_builtin (arglist, target); | |
7333 | ||
7334 | default: | |
7335 | break; | |
7336 | /* Fall through. */ | |
0ac081f6 | 7337 | } |
24408032 | 7338 | |
100c4561 AH |
7339 | /* Expand abs* operations. */ |
7340 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 7341 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
7342 | if (d->code == fcode) |
7343 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
7344 | ||
ae4b4a02 AH |
7345 | /* Expand the AltiVec predicates. */ |
7346 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 7347 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 | 7348 | if (dp->code == fcode) |
c4ad648e AM |
7349 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, |
7350 | arglist, target); | |
ae4b4a02 | 7351 | |
6525c0e7 AH |
7352 | /* LV* are funky. We initialized them differently. */ |
7353 | switch (fcode) | |
7354 | { | |
7355 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 7356 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
c4ad648e | 7357 | arglist, target); |
6525c0e7 | 7358 | case ALTIVEC_BUILTIN_LVSR: |
b4a62fa0 | 7359 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
c4ad648e | 7360 | arglist, target); |
6525c0e7 | 7361 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 7362 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
c4ad648e | 7363 | arglist, target); |
6525c0e7 | 7364 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 7365 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
c4ad648e | 7366 | arglist, target); |
6525c0e7 | 7367 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 7368 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
c4ad648e | 7369 | arglist, target); |
6525c0e7 | 7370 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 7371 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
c4ad648e | 7372 | arglist, target); |
6525c0e7 | 7373 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 7374 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
c4ad648e | 7375 | arglist, target); |
6525c0e7 AH |
7376 | default: |
7377 | break; | |
7378 | /* Fall through. */ | |
7379 | } | |
95385cbb | 7380 | |
92898235 | 7381 | *expandedp = false; |
0ac081f6 AH |
7382 | return NULL_RTX; |
7383 | } | |
7384 | ||
a3170dc6 AH |
7385 | /* Binops that need to be initialized manually, but can be expanded |
7386 | automagically by rs6000_expand_binop_builtin. */ | |
7387 | static struct builtin_description bdesc_2arg_spe[] = | |
7388 | { | |
7389 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
7390 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
7391 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
7392 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
7393 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
7394 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
7395 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
7396 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
7397 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
7398 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
7399 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
7400 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
7401 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
7402 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
7403 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
7404 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
7405 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
7406 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
7407 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
7408 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
7409 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
7410 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
7411 | }; | |
7412 | ||
7413 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
7414 | true in *EXPANDEDP if we found a builtin to expand. | |
7415 | ||
7416 | This expands the SPE builtins that are not simple unary and binary | |
7417 | operations. */ | |
7418 | static rtx | |
a2369ed3 | 7419 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 AH |
7420 | { |
7421 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
7422 | tree arglist = TREE_OPERAND (exp, 1); | |
7423 | tree arg1, arg0; | |
7424 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7425 | enum insn_code icode; | |
7426 | enum machine_mode tmode, mode0; | |
7427 | rtx pat, op0; | |
7428 | struct builtin_description *d; | |
7429 | size_t i; | |
7430 | ||
7431 | *expandedp = true; | |
7432 | ||
7433 | /* Syntax check for a 5-bit unsigned immediate. */ | |
7434 | switch (fcode) | |
7435 | { | |
7436 | case SPE_BUILTIN_EVSTDD: | |
7437 | case SPE_BUILTIN_EVSTDH: | |
7438 | case SPE_BUILTIN_EVSTDW: | |
7439 | case SPE_BUILTIN_EVSTWHE: | |
7440 | case SPE_BUILTIN_EVSTWHO: | |
7441 | case SPE_BUILTIN_EVSTWWE: | |
7442 | case SPE_BUILTIN_EVSTWWO: | |
7443 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7444 | if (TREE_CODE (arg1) != INTEGER_CST | |
7445 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
7446 | { | |
7447 | error ("argument 2 must be a 5-bit unsigned literal"); | |
7448 | return const0_rtx; | |
7449 | } | |
7450 | break; | |
7451 | default: | |
7452 | break; | |
7453 | } | |
7454 | ||
00332c9f AH |
7455 | /* The evsplat*i instructions are not quite generic. */ |
7456 | switch (fcode) | |
7457 | { | |
7458 | case SPE_BUILTIN_EVSPLATFI: | |
7459 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
7460 | arglist, target); | |
7461 | case SPE_BUILTIN_EVSPLATI: | |
7462 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
7463 | arglist, target); | |
7464 | default: | |
7465 | break; | |
7466 | } | |
7467 | ||
a3170dc6 AH |
7468 | d = (struct builtin_description *) bdesc_2arg_spe; |
7469 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
7470 | if (d->code == fcode) | |
7471 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
7472 | ||
7473 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7474 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
7475 | if (d->code == fcode) | |
7476 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
7477 | ||
7478 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7479 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
7480 | if (d->code == fcode) | |
7481 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
7482 | ||
7483 | switch (fcode) | |
7484 | { | |
7485 | case SPE_BUILTIN_EVSTDDX: | |
61bea3b0 | 7486 | return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); |
a3170dc6 | 7487 | case SPE_BUILTIN_EVSTDHX: |
61bea3b0 | 7488 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); |
a3170dc6 | 7489 | case SPE_BUILTIN_EVSTDWX: |
61bea3b0 | 7490 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); |
a3170dc6 | 7491 | case SPE_BUILTIN_EVSTWHEX: |
61bea3b0 | 7492 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); |
a3170dc6 | 7493 | case SPE_BUILTIN_EVSTWHOX: |
61bea3b0 | 7494 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); |
a3170dc6 | 7495 | case SPE_BUILTIN_EVSTWWEX: |
61bea3b0 | 7496 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); |
a3170dc6 | 7497 | case SPE_BUILTIN_EVSTWWOX: |
61bea3b0 | 7498 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); |
a3170dc6 | 7499 | case SPE_BUILTIN_EVSTDD: |
61bea3b0 | 7500 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); |
a3170dc6 | 7501 | case SPE_BUILTIN_EVSTDH: |
61bea3b0 | 7502 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); |
a3170dc6 | 7503 | case SPE_BUILTIN_EVSTDW: |
61bea3b0 | 7504 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); |
a3170dc6 | 7505 | case SPE_BUILTIN_EVSTWHE: |
61bea3b0 | 7506 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); |
a3170dc6 | 7507 | case SPE_BUILTIN_EVSTWHO: |
61bea3b0 | 7508 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); |
a3170dc6 | 7509 | case SPE_BUILTIN_EVSTWWE: |
61bea3b0 | 7510 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); |
a3170dc6 | 7511 | case SPE_BUILTIN_EVSTWWO: |
61bea3b0 | 7512 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); |
a3170dc6 AH |
7513 | case SPE_BUILTIN_MFSPEFSCR: |
7514 | icode = CODE_FOR_spe_mfspefscr; | |
7515 | tmode = insn_data[icode].operand[0].mode; | |
7516 | ||
7517 | if (target == 0 | |
7518 | || GET_MODE (target) != tmode | |
7519 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7520 | target = gen_reg_rtx (tmode); | |
f676971a | 7521 | |
a3170dc6 AH |
7522 | pat = GEN_FCN (icode) (target); |
7523 | if (! pat) | |
7524 | return 0; | |
7525 | emit_insn (pat); | |
7526 | return target; | |
7527 | case SPE_BUILTIN_MTSPEFSCR: | |
7528 | icode = CODE_FOR_spe_mtspefscr; | |
7529 | arg0 = TREE_VALUE (arglist); | |
7530 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7531 | mode0 = insn_data[icode].operand[0].mode; | |
7532 | ||
7533 | if (arg0 == error_mark_node) | |
7534 | return const0_rtx; | |
7535 | ||
7536 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
7537 | op0 = copy_to_mode_reg (mode0, op0); | |
7538 | ||
7539 | pat = GEN_FCN (icode) (op0); | |
7540 | if (pat) | |
7541 | emit_insn (pat); | |
7542 | return NULL_RTX; | |
7543 | default: | |
7544 | break; | |
7545 | } | |
7546 | ||
7547 | *expandedp = false; | |
7548 | return NULL_RTX; | |
7549 | } | |
7550 | ||
7551 | static rtx | |
a2369ed3 | 7552 | spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
7553 | { |
7554 | rtx pat, scratch, tmp; | |
7555 | tree form = TREE_VALUE (arglist); | |
7556 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7557 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7558 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7559 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7560 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7561 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7562 | int form_int; | |
7563 | enum rtx_code code; | |
7564 | ||
7565 | if (TREE_CODE (form) != INTEGER_CST) | |
7566 | { | |
7567 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
7568 | return const0_rtx; | |
7569 | } | |
7570 | else | |
7571 | form_int = TREE_INT_CST_LOW (form); | |
7572 | ||
37409796 | 7573 | gcc_assert (mode0 == mode1); |
a3170dc6 AH |
7574 | |
7575 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
7576 | return const0_rtx; | |
7577 | ||
7578 | if (target == 0 | |
7579 | || GET_MODE (target) != SImode | |
7580 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
7581 | target = gen_reg_rtx (SImode); | |
7582 | ||
7583 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7584 | op0 = copy_to_mode_reg (mode0, op0); | |
7585 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
7586 | op1 = copy_to_mode_reg (mode1, op1); | |
7587 | ||
7588 | scratch = gen_reg_rtx (CCmode); | |
7589 | ||
7590 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7591 | if (! pat) | |
7592 | return const0_rtx; | |
7593 | emit_insn (pat); | |
7594 | ||
7595 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
7596 | _lower_. We use one compare, but look in different bits of the | |
7597 | CR for each variant. | |
7598 | ||
7599 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
7600 | bits are set as follows: | |
7601 | ||
7602 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7603 | U | L | (U | L) | (U & L) | |
7604 | ||
7605 | So, for an "all" relationship, BIT 3 would be set. | |
7606 | For an "any" relationship, BIT 2 would be set. Etc. | |
7607 | ||
7608 | Following traditional nomenclature, these bits map to: | |
7609 | ||
7610 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7611 | LT | GT | EQ | OV | |
7612 | ||
7613 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
7614 | */ | |
7615 | ||
7616 | switch (form_int) | |
7617 | { | |
7618 | /* All variant. OV bit. */ | |
7619 | case 0: | |
7620 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
7621 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
992d08b1 | 7622 | that's ugly and will make validate_condition_mode die. |
a3170dc6 AH |
7623 | So let's just use another pattern. */ |
7624 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
7625 | return target; | |
7626 | /* Any variant. EQ bit. */ | |
7627 | case 1: | |
7628 | code = EQ; | |
7629 | break; | |
7630 | /* Upper variant. LT bit. */ | |
7631 | case 2: | |
7632 | code = LT; | |
7633 | break; | |
7634 | /* Lower variant. GT bit. */ | |
7635 | case 3: | |
7636 | code = GT; | |
7637 | break; | |
7638 | default: | |
7639 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
7640 | return const0_rtx; | |
7641 | } | |
7642 | ||
7643 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
7644 | emit_move_insn (target, tmp); | |
7645 | ||
7646 | return target; | |
7647 | } | |
7648 | ||
7649 | /* The evsel builtins look like this: | |
7650 | ||
7651 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
7652 | ||
7653 | and work like this: | |
7654 | ||
7655 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
7656 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
7657 | */ | |
7658 | ||
7659 | static rtx | |
a2369ed3 | 7660 | spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
7661 | { |
7662 | rtx pat, scratch; | |
7663 | tree arg0 = TREE_VALUE (arglist); | |
7664 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7665 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7666 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
7667 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7668 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7669 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
7670 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
7671 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7672 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7673 | ||
37409796 | 7674 | gcc_assert (mode0 == mode1); |
a3170dc6 AH |
7675 | |
7676 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
7677 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
7678 | return const0_rtx; | |
7679 | ||
7680 | if (target == 0 | |
7681 | || GET_MODE (target) != mode0 | |
7682 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
7683 | target = gen_reg_rtx (mode0); | |
7684 | ||
7685 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7686 | op0 = copy_to_mode_reg (mode0, op0); | |
7687 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
7688 | op1 = copy_to_mode_reg (mode0, op1); | |
7689 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
7690 | op2 = copy_to_mode_reg (mode0, op2); | |
7691 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
7692 | op3 = copy_to_mode_reg (mode0, op3); | |
7693 | ||
7694 | /* Generate the compare. */ | |
7695 | scratch = gen_reg_rtx (CCmode); | |
7696 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7697 | if (! pat) | |
7698 | return const0_rtx; | |
7699 | emit_insn (pat); | |
7700 | ||
7701 | if (mode0 == V2SImode) | |
7702 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
7703 | else | |
7704 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
7705 | ||
7706 | return target; | |
7707 | } | |
7708 | ||
0ac081f6 AH |
7709 | /* Expand an expression EXP that calls a built-in function, |
7710 | with result going to TARGET if that's convenient | |
7711 | (and in mode MODE if that's convenient). | |
7712 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
7713 | IGNORE is nonzero if the value is to be ignored. */ | |
7714 | ||
7715 | static rtx | |
a2369ed3 | 7716 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
c4ad648e AM |
7717 | enum machine_mode mode ATTRIBUTE_UNUSED, |
7718 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 7719 | { |
92898235 AH |
7720 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
7721 | tree arglist = TREE_OPERAND (exp, 1); | |
7722 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7723 | struct builtin_description *d; | |
7724 | size_t i; | |
7725 | rtx ret; | |
7726 | bool success; | |
f676971a | 7727 | |
7ccf35ed DN |
7728 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD |
7729 | || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7730 | { | |
7731 | int icode = (int) CODE_FOR_altivec_lvsr; | |
7732 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
7733 | enum machine_mode mode = insn_data[icode].operand[1].mode; | |
7734 | tree arg; | |
7735 | rtx op, addr, pat; | |
7736 | ||
37409796 | 7737 | gcc_assert (TARGET_ALTIVEC); |
7ccf35ed DN |
7738 | |
7739 | arg = TREE_VALUE (arglist); | |
37409796 | 7740 | gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE); |
7ccf35ed DN |
7741 | op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); |
7742 | addr = memory_address (mode, op); | |
7743 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7744 | op = addr; | |
7745 | else | |
7746 | { | |
7747 | /* For the load case need to negate the address. */ | |
7748 | op = gen_reg_rtx (GET_MODE (addr)); | |
7749 | emit_insn (gen_rtx_SET (VOIDmode, op, | |
7750 | gen_rtx_NEG (GET_MODE (addr), addr))); | |
c4ad648e | 7751 | } |
7ccf35ed DN |
7752 | op = gen_rtx_MEM (mode, op); |
7753 | ||
7754 | if (target == 0 | |
7755 | || GET_MODE (target) != tmode | |
7756 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7757 | target = gen_reg_rtx (tmode); | |
7758 | ||
7759 | /*pat = gen_altivec_lvsr (target, op);*/ | |
7760 | pat = GEN_FCN (icode) (target, op); | |
7761 | if (!pat) | |
7762 | return 0; | |
7763 | emit_insn (pat); | |
7764 | ||
7765 | return target; | |
7766 | } | |
7767 | ||
0ac081f6 | 7768 | if (TARGET_ALTIVEC) |
92898235 AH |
7769 | { |
7770 | ret = altivec_expand_builtin (exp, target, &success); | |
7771 | ||
a3170dc6 AH |
7772 | if (success) |
7773 | return ret; | |
7774 | } | |
7775 | if (TARGET_SPE) | |
7776 | { | |
7777 | ret = spe_expand_builtin (exp, target, &success); | |
7778 | ||
92898235 AH |
7779 | if (success) |
7780 | return ret; | |
7781 | } | |
7782 | ||
37409796 | 7783 | gcc_assert (TARGET_ALTIVEC || TARGET_SPE); |
bb8df8a6 | 7784 | |
37409796 NS |
7785 | /* Handle simple unary operations. */ |
7786 | d = (struct builtin_description *) bdesc_1arg; | |
7787 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
7788 | if (d->code == fcode) | |
7789 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
bb8df8a6 | 7790 | |
37409796 NS |
7791 | /* Handle simple binary operations. */ |
7792 | d = (struct builtin_description *) bdesc_2arg; | |
7793 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
7794 | if (d->code == fcode) | |
7795 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
0ac081f6 | 7796 | |
37409796 NS |
7797 | /* Handle simple ternary operations. */ |
7798 | d = (struct builtin_description *) bdesc_3arg; | |
7799 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
7800 | if (d->code == fcode) | |
7801 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
bb8df8a6 | 7802 | |
37409796 | 7803 | gcc_unreachable (); |
0ac081f6 AH |
7804 | } |
7805 | ||
7c62e993 PB |
7806 | static tree |
7807 | build_opaque_vector_type (tree node, int nunits) | |
7808 | { | |
7809 | node = copy_node (node); | |
7810 | TYPE_MAIN_VARIANT (node) = node; | |
7811 | return build_vector_type (node, nunits); | |
7812 | } | |
7813 | ||
0ac081f6 | 7814 | static void |
863d938c | 7815 | rs6000_init_builtins (void) |
0ac081f6 | 7816 | { |
4a5eab38 PB |
7817 | V2SI_type_node = build_vector_type (intSI_type_node, 2); |
7818 | V2SF_type_node = build_vector_type (float_type_node, 2); | |
7819 | V4HI_type_node = build_vector_type (intHI_type_node, 4); | |
7820 | V4SI_type_node = build_vector_type (intSI_type_node, 4); | |
7821 | V4SF_type_node = build_vector_type (float_type_node, 4); | |
7e463bda | 7822 | V8HI_type_node = build_vector_type (intHI_type_node, 8); |
4a5eab38 PB |
7823 | V16QI_type_node = build_vector_type (intQI_type_node, 16); |
7824 | ||
7825 | unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); | |
7826 | unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); | |
7827 | unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); | |
7828 | ||
7c62e993 PB |
7829 | opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); |
7830 | opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); | |
6035d635 | 7831 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
58646b77 | 7832 | opaque_V4SI_type_node = copy_node (V4SI_type_node); |
3fdaa45a | 7833 | |
8bb418a3 ZL |
7834 | /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' |
7835 | types, especially in C++ land. Similarly, 'vector pixel' is distinct from | |
7836 | 'vector unsigned short'. */ | |
7837 | ||
8dd16ecc NS |
7838 | bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); |
7839 | bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
7840 | bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); | |
7841 | pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
8bb418a3 | 7842 | |
58646b77 PB |
7843 | long_integer_type_internal_node = long_integer_type_node; |
7844 | long_unsigned_type_internal_node = long_unsigned_type_node; | |
7845 | intQI_type_internal_node = intQI_type_node; | |
7846 | uintQI_type_internal_node = unsigned_intQI_type_node; | |
7847 | intHI_type_internal_node = intHI_type_node; | |
7848 | uintHI_type_internal_node = unsigned_intHI_type_node; | |
7849 | intSI_type_internal_node = intSI_type_node; | |
7850 | uintSI_type_internal_node = unsigned_intSI_type_node; | |
7851 | float_type_internal_node = float_type_node; | |
7852 | void_type_internal_node = void_type_node; | |
7853 | ||
8bb418a3 ZL |
7854 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, |
7855 | get_identifier ("__bool char"), | |
7856 | bool_char_type_node)); | |
7857 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7858 | get_identifier ("__bool short"), | |
7859 | bool_short_type_node)); | |
7860 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7861 | get_identifier ("__bool int"), | |
7862 | bool_int_type_node)); | |
7863 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7864 | get_identifier ("__pixel"), | |
7865 | pixel_type_node)); | |
7866 | ||
4a5eab38 PB |
7867 | bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); |
7868 | bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); | |
7869 | bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); | |
7870 | pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); | |
8bb418a3 ZL |
7871 | |
7872 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7873 | get_identifier ("__vector unsigned char"), | |
7874 | unsigned_V16QI_type_node)); | |
7875 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7876 | get_identifier ("__vector signed char"), | |
7877 | V16QI_type_node)); | |
7878 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7879 | get_identifier ("__vector __bool char"), | |
7880 | bool_V16QI_type_node)); | |
7881 | ||
7882 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7883 | get_identifier ("__vector unsigned short"), | |
7884 | unsigned_V8HI_type_node)); | |
7885 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7886 | get_identifier ("__vector signed short"), | |
7887 | V8HI_type_node)); | |
7888 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7889 | get_identifier ("__vector __bool short"), | |
7890 | bool_V8HI_type_node)); | |
7891 | ||
7892 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7893 | get_identifier ("__vector unsigned int"), | |
7894 | unsigned_V4SI_type_node)); | |
7895 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7896 | get_identifier ("__vector signed int"), | |
7897 | V4SI_type_node)); | |
7898 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7899 | get_identifier ("__vector __bool int"), | |
7900 | bool_V4SI_type_node)); | |
7901 | ||
7902 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7903 | get_identifier ("__vector float"), | |
7904 | V4SF_type_node)); | |
7905 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7906 | get_identifier ("__vector __pixel"), | |
7907 | pixel_V8HI_type_node)); | |
7908 | ||
a3170dc6 | 7909 | if (TARGET_SPE) |
3fdaa45a | 7910 | spe_init_builtins (); |
0ac081f6 AH |
7911 | if (TARGET_ALTIVEC) |
7912 | altivec_init_builtins (); | |
0559cc77 DE |
7913 | if (TARGET_ALTIVEC || TARGET_SPE) |
7914 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
7915 | } |
7916 | ||
a3170dc6 AH |
7917 | /* Search through a set of builtins and enable the mask bits. |
7918 | DESC is an array of builtins. | |
b6d08ca1 | 7919 | SIZE is the total number of builtins. |
a3170dc6 AH |
7920 | START is the builtin enum at which to start. |
7921 | END is the builtin enum at which to end. */ | |
0ac081f6 | 7922 | static void |
a2369ed3 | 7923 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
f676971a | 7924 | enum rs6000_builtins start, |
a2369ed3 | 7925 | enum rs6000_builtins end) |
a3170dc6 AH |
7926 | { |
7927 | int i; | |
7928 | ||
7929 | for (i = 0; i < size; ++i) | |
7930 | if (desc[i].code == start) | |
7931 | break; | |
7932 | ||
7933 | if (i == size) | |
7934 | return; | |
7935 | ||
7936 | for (; i < size; ++i) | |
7937 | { | |
7938 | /* Flip all the bits on. */ | |
7939 | desc[i].mask = target_flags; | |
7940 | if (desc[i].code == end) | |
7941 | break; | |
7942 | } | |
7943 | } | |
7944 | ||
7945 | static void | |
863d938c | 7946 | spe_init_builtins (void) |
0ac081f6 | 7947 | { |
a3170dc6 AH |
7948 | tree endlink = void_list_node; |
7949 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
7950 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 7951 | struct builtin_description *d; |
0ac081f6 AH |
7952 | size_t i; |
7953 | ||
a3170dc6 AH |
7954 | tree v2si_ftype_4_v2si |
7955 | = build_function_type | |
3fdaa45a AH |
7956 | (opaque_V2SI_type_node, |
7957 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7958 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7959 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7960 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7961 | endlink))))); |
7962 | ||
7963 | tree v2sf_ftype_4_v2sf | |
7964 | = build_function_type | |
3fdaa45a AH |
7965 | (opaque_V2SF_type_node, |
7966 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7967 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7968 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7969 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7970 | endlink))))); |
7971 | ||
7972 | tree int_ftype_int_v2si_v2si | |
7973 | = build_function_type | |
7974 | (integer_type_node, | |
7975 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7976 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
7977 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7978 | endlink)))); |
7979 | ||
7980 | tree int_ftype_int_v2sf_v2sf | |
7981 | = build_function_type | |
7982 | (integer_type_node, | |
7983 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7984 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
7985 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7986 | endlink)))); |
7987 | ||
7988 | tree void_ftype_v2si_puint_int | |
7989 | = build_function_type (void_type_node, | |
3fdaa45a | 7990 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7991 | tree_cons (NULL_TREE, puint_type_node, |
7992 | tree_cons (NULL_TREE, | |
7993 | integer_type_node, | |
7994 | endlink)))); | |
7995 | ||
7996 | tree void_ftype_v2si_puint_char | |
7997 | = build_function_type (void_type_node, | |
3fdaa45a | 7998 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7999 | tree_cons (NULL_TREE, puint_type_node, |
8000 | tree_cons (NULL_TREE, | |
8001 | char_type_node, | |
8002 | endlink)))); | |
8003 | ||
8004 | tree void_ftype_v2si_pv2si_int | |
8005 | = build_function_type (void_type_node, | |
3fdaa45a | 8006 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 8007 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
8008 | tree_cons (NULL_TREE, |
8009 | integer_type_node, | |
8010 | endlink)))); | |
8011 | ||
8012 | tree void_ftype_v2si_pv2si_char | |
8013 | = build_function_type (void_type_node, | |
3fdaa45a | 8014 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 8015 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
8016 | tree_cons (NULL_TREE, |
8017 | char_type_node, | |
8018 | endlink)))); | |
8019 | ||
8020 | tree void_ftype_int | |
8021 | = build_function_type (void_type_node, | |
8022 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
8023 | ||
8024 | tree int_ftype_void | |
36e8d515 | 8025 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
8026 | |
8027 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 8028 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 8029 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
8030 | tree_cons (NULL_TREE, integer_type_node, |
8031 | endlink))); | |
8032 | ||
8033 | tree v2si_ftype_puint_int | |
3fdaa45a | 8034 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
8035 | tree_cons (NULL_TREE, puint_type_node, |
8036 | tree_cons (NULL_TREE, integer_type_node, | |
8037 | endlink))); | |
8038 | ||
8039 | tree v2si_ftype_pushort_int | |
3fdaa45a | 8040 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
8041 | tree_cons (NULL_TREE, pushort_type_node, |
8042 | tree_cons (NULL_TREE, integer_type_node, | |
8043 | endlink))); | |
8044 | ||
00332c9f AH |
8045 | tree v2si_ftype_signed_char |
8046 | = build_function_type (opaque_V2SI_type_node, | |
8047 | tree_cons (NULL_TREE, signed_char_type_node, | |
8048 | endlink)); | |
8049 | ||
a3170dc6 AH |
8050 | /* The initialization of the simple binary and unary builtins is |
8051 | done in rs6000_common_init_builtins, but we have to enable the | |
8052 | mask bits here manually because we have run out of `target_flags' | |
8053 | bits. We really need to redesign this mask business. */ | |
8054 | ||
8055 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
8056 | ARRAY_SIZE (bdesc_2arg), | |
8057 | SPE_BUILTIN_EVADDW, | |
8058 | SPE_BUILTIN_EVXOR); | |
8059 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
8060 | ARRAY_SIZE (bdesc_1arg), | |
8061 | SPE_BUILTIN_EVABS, | |
8062 | SPE_BUILTIN_EVSUBFUSIAAW); | |
8063 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
8064 | ARRAY_SIZE (bdesc_spe_predicates), | |
8065 | SPE_BUILTIN_EVCMPEQ, | |
8066 | SPE_BUILTIN_EVFSTSTLT); | |
8067 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
8068 | ARRAY_SIZE (bdesc_spe_evsel), | |
8069 | SPE_BUILTIN_EVSEL_CMPGTS, | |
8070 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
8071 | ||
36252949 AH |
8072 | (*lang_hooks.decls.pushdecl) |
8073 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
8074 | opaque_V2SI_type_node)); | |
8075 | ||
a3170dc6 | 8076 | /* Initialize irregular SPE builtins. */ |
f676971a | 8077 | |
a3170dc6 AH |
8078 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); |
8079 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
8080 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
8081 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
8082 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
8083 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
8084 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
8085 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
8086 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
8087 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
8088 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
8089 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
8090 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
8091 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
8092 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
8093 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
8094 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
8095 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
8096 | |
8097 | /* Loads. */ | |
8098 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
8099 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
8100 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
8101 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
8102 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
8103 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
8104 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
8105 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
8106 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
8107 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
8108 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
8109 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
8110 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
8111 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
8112 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
8113 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
8114 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
8115 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
8116 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
8117 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
8118 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
8119 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
8120 | ||
8121 | /* Predicates. */ | |
8122 | d = (struct builtin_description *) bdesc_spe_predicates; | |
8123 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
8124 | { | |
8125 | tree type; | |
8126 | ||
8127 | switch (insn_data[d->icode].operand[1].mode) | |
8128 | { | |
8129 | case V2SImode: | |
8130 | type = int_ftype_int_v2si_v2si; | |
8131 | break; | |
8132 | case V2SFmode: | |
8133 | type = int_ftype_int_v2sf_v2sf; | |
8134 | break; | |
8135 | default: | |
37409796 | 8136 | gcc_unreachable (); |
a3170dc6 AH |
8137 | } |
8138 | ||
8139 | def_builtin (d->mask, d->name, type, d->code); | |
8140 | } | |
8141 | ||
8142 | /* Evsel predicates. */ | |
8143 | d = (struct builtin_description *) bdesc_spe_evsel; | |
8144 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
8145 | { | |
8146 | tree type; | |
8147 | ||
8148 | switch (insn_data[d->icode].operand[1].mode) | |
8149 | { | |
8150 | case V2SImode: | |
8151 | type = v2si_ftype_4_v2si; | |
8152 | break; | |
8153 | case V2SFmode: | |
8154 | type = v2sf_ftype_4_v2sf; | |
8155 | break; | |
8156 | default: | |
37409796 | 8157 | gcc_unreachable (); |
a3170dc6 AH |
8158 | } |
8159 | ||
8160 | def_builtin (d->mask, d->name, type, d->code); | |
8161 | } | |
8162 | } | |
8163 | ||
8164 | static void | |
863d938c | 8165 | altivec_init_builtins (void) |
a3170dc6 AH |
8166 | { |
8167 | struct builtin_description *d; | |
8168 | struct builtin_description_predicates *dp; | |
8169 | size_t i; | |
7a4eca66 DE |
8170 | tree ftype; |
8171 | ||
a3170dc6 AH |
8172 | tree pfloat_type_node = build_pointer_type (float_type_node); |
8173 | tree pint_type_node = build_pointer_type (integer_type_node); | |
8174 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
8175 | tree pchar_type_node = build_pointer_type (char_type_node); | |
8176 | ||
8177 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
8178 | ||
0dbc3651 ZW |
8179 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
8180 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
8181 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
8182 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
8183 | ||
8184 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
8185 | ||
58646b77 PB |
8186 | tree int_ftype_opaque |
8187 | = build_function_type_list (integer_type_node, | |
8188 | opaque_V4SI_type_node, NULL_TREE); | |
8189 | ||
8190 | tree opaque_ftype_opaque_int | |
8191 | = build_function_type_list (opaque_V4SI_type_node, | |
8192 | opaque_V4SI_type_node, integer_type_node, NULL_TREE); | |
8193 | tree opaque_ftype_opaque_opaque_int | |
8194 | = build_function_type_list (opaque_V4SI_type_node, | |
8195 | opaque_V4SI_type_node, opaque_V4SI_type_node, | |
8196 | integer_type_node, NULL_TREE); | |
8197 | tree int_ftype_int_opaque_opaque | |
8198 | = build_function_type_list (integer_type_node, | |
8199 | integer_type_node, opaque_V4SI_type_node, | |
8200 | opaque_V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8201 | tree int_ftype_int_v4si_v4si |
8202 | = build_function_type_list (integer_type_node, | |
8203 | integer_type_node, V4SI_type_node, | |
8204 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
8205 | tree v4sf_ftype_pcfloat |
8206 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 8207 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 8208 | = build_function_type_list (void_type_node, |
a3170dc6 | 8209 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
8210 | tree v4si_ftype_pcint |
8211 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
8212 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
8213 | = build_function_type_list (void_type_node, |
8214 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
8215 | tree v8hi_ftype_pcshort |
8216 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 8217 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
8218 | = build_function_type_list (void_type_node, |
8219 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
8220 | tree v16qi_ftype_pcchar |
8221 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 8222 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
8223 | = build_function_type_list (void_type_node, |
8224 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 8225 | tree void_ftype_v4si |
b4de2f7d | 8226 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
8227 | tree v8hi_ftype_void |
8228 | = build_function_type (V8HI_type_node, void_list_node); | |
8229 | tree void_ftype_void | |
8230 | = build_function_type (void_type_node, void_list_node); | |
e34b6648 JJ |
8231 | tree void_ftype_int |
8232 | = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); | |
0dbc3651 | 8233 | |
58646b77 PB |
8234 | tree opaque_ftype_long_pcvoid |
8235 | = build_function_type_list (opaque_V4SI_type_node, | |
8236 | long_integer_type_node, pcvoid_type_node, NULL_TREE); | |
b4a62fa0 | 8237 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 8238 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
8239 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
8240 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 8241 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
8242 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
8243 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 8244 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 8245 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 8246 | |
58646b77 PB |
8247 | tree void_ftype_opaque_long_pvoid |
8248 | = build_function_type_list (void_type_node, | |
8249 | opaque_V4SI_type_node, long_integer_type_node, | |
8250 | pvoid_type_node, NULL_TREE); | |
b4a62fa0 | 8251 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 8252 | = build_function_type_list (void_type_node, |
b4a62fa0 | 8253 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 8254 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 8255 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 8256 | = build_function_type_list (void_type_node, |
b4a62fa0 | 8257 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 8258 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 8259 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 8260 | = build_function_type_list (void_type_node, |
b4a62fa0 | 8261 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 8262 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
8263 | tree int_ftype_int_v8hi_v8hi |
8264 | = build_function_type_list (integer_type_node, | |
8265 | integer_type_node, V8HI_type_node, | |
8266 | V8HI_type_node, NULL_TREE); | |
8267 | tree int_ftype_int_v16qi_v16qi | |
8268 | = build_function_type_list (integer_type_node, | |
8269 | integer_type_node, V16QI_type_node, | |
8270 | V16QI_type_node, NULL_TREE); | |
8271 | tree int_ftype_int_v4sf_v4sf | |
8272 | = build_function_type_list (integer_type_node, | |
8273 | integer_type_node, V4SF_type_node, | |
8274 | V4SF_type_node, NULL_TREE); | |
8275 | tree v4si_ftype_v4si | |
8276 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
8277 | tree v8hi_ftype_v8hi | |
8278 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
8279 | tree v16qi_ftype_v16qi | |
8280 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
8281 | tree v4sf_ftype_v4sf | |
8282 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8bb418a3 | 8283 | tree void_ftype_pcvoid_int_int |
a3170dc6 | 8284 | = build_function_type_list (void_type_node, |
0dbc3651 | 8285 | pcvoid_type_node, integer_type_node, |
8bb418a3 | 8286 | integer_type_node, NULL_TREE); |
8bb418a3 | 8287 | |
0dbc3651 ZW |
8288 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, |
8289 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
8290 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
8291 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
8292 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
8293 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
8294 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
8295 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
8296 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
8297 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
8298 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
8299 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
8300 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
8301 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
8302 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
8303 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
8304 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
8305 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
8306 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
e34b6648 | 8307 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); |
b4a62fa0 SB |
8308 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
8309 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
8310 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
8311 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
8312 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
8313 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
8314 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
8315 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
8316 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
8317 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
8318 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
8319 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
58646b77 PB |
8320 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD); |
8321 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE); | |
8322 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL); | |
8323 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL); | |
8324 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR); | |
8325 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX); | |
8326 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX); | |
8327 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX); | |
8328 | def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST); | |
8329 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE); | |
8330 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL); | |
8331 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX); | |
8332 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX); | |
8333 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX); | |
8334 | ||
8335 | def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP); | |
8336 | ||
8337 | def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD); | |
8338 | def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT); | |
8339 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW); | |
8340 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH); | |
8341 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB); | |
8342 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF); | |
8343 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX); | |
8344 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX); | |
8345 | def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS); | |
8346 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU); | |
8bb418a3 | 8347 | |
a3170dc6 AH |
8348 | /* Add the DST variants. */ |
8349 | d = (struct builtin_description *) bdesc_dst; | |
8350 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
8bb418a3 | 8351 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); |
a3170dc6 AH |
8352 | |
8353 | /* Initialize the predicates. */ | |
8354 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
8355 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
8356 | { | |
8357 | enum machine_mode mode1; | |
8358 | tree type; | |
58646b77 PB |
8359 | bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
8360 | && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
a3170dc6 | 8361 | |
58646b77 PB |
8362 | if (is_overloaded) |
8363 | mode1 = VOIDmode; | |
8364 | else | |
8365 | mode1 = insn_data[dp->icode].operand[1].mode; | |
a3170dc6 AH |
8366 | |
8367 | switch (mode1) | |
8368 | { | |
58646b77 PB |
8369 | case VOIDmode: |
8370 | type = int_ftype_int_opaque_opaque; | |
8371 | break; | |
a3170dc6 AH |
8372 | case V4SImode: |
8373 | type = int_ftype_int_v4si_v4si; | |
8374 | break; | |
8375 | case V8HImode: | |
8376 | type = int_ftype_int_v8hi_v8hi; | |
8377 | break; | |
8378 | case V16QImode: | |
8379 | type = int_ftype_int_v16qi_v16qi; | |
8380 | break; | |
8381 | case V4SFmode: | |
8382 | type = int_ftype_int_v4sf_v4sf; | |
8383 | break; | |
8384 | default: | |
37409796 | 8385 | gcc_unreachable (); |
a3170dc6 | 8386 | } |
f676971a | 8387 | |
a3170dc6 AH |
8388 | def_builtin (dp->mask, dp->name, type, dp->code); |
8389 | } | |
8390 | ||
8391 | /* Initialize the abs* operators. */ | |
8392 | d = (struct builtin_description *) bdesc_abs; | |
8393 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
8394 | { | |
8395 | enum machine_mode mode0; | |
8396 | tree type; | |
8397 | ||
8398 | mode0 = insn_data[d->icode].operand[0].mode; | |
8399 | ||
8400 | switch (mode0) | |
8401 | { | |
8402 | case V4SImode: | |
8403 | type = v4si_ftype_v4si; | |
8404 | break; | |
8405 | case V8HImode: | |
8406 | type = v8hi_ftype_v8hi; | |
8407 | break; | |
8408 | case V16QImode: | |
8409 | type = v16qi_ftype_v16qi; | |
8410 | break; | |
8411 | case V4SFmode: | |
8412 | type = v4sf_ftype_v4sf; | |
8413 | break; | |
8414 | default: | |
37409796 | 8415 | gcc_unreachable (); |
a3170dc6 | 8416 | } |
f676971a | 8417 | |
a3170dc6 AH |
8418 | def_builtin (d->mask, d->name, type, d->code); |
8419 | } | |
7ccf35ed | 8420 | |
13c62176 DN |
8421 | if (TARGET_ALTIVEC) |
8422 | { | |
8423 | tree decl; | |
8424 | ||
8425 | /* Initialize target builtin that implements | |
8426 | targetm.vectorize.builtin_mask_for_load. */ | |
8427 | ||
8428 | decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load", | |
8bb46326 DN |
8429 | v16qi_ftype_long_pcvoid, |
8430 | ALTIVEC_BUILTIN_MASK_FOR_LOAD, | |
8431 | BUILT_IN_MD, NULL, | |
8432 | tree_cons (get_identifier ("const"), | |
8433 | NULL_TREE, NULL_TREE)); | |
13c62176 DN |
8434 | /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ |
8435 | altivec_builtin_mask_for_load = decl; | |
13c62176 | 8436 | } |
7a4eca66 DE |
8437 | |
8438 | /* Access to the vec_init patterns. */ | |
8439 | ftype = build_function_type_list (V4SI_type_node, integer_type_node, | |
8440 | integer_type_node, integer_type_node, | |
8441 | integer_type_node, NULL_TREE); | |
8442 | def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype, | |
8443 | ALTIVEC_BUILTIN_VEC_INIT_V4SI); | |
8444 | ||
8445 | ftype = build_function_type_list (V8HI_type_node, short_integer_type_node, | |
8446 | short_integer_type_node, | |
8447 | short_integer_type_node, | |
8448 | short_integer_type_node, | |
8449 | short_integer_type_node, | |
8450 | short_integer_type_node, | |
8451 | short_integer_type_node, | |
8452 | short_integer_type_node, NULL_TREE); | |
8453 | def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype, | |
8454 | ALTIVEC_BUILTIN_VEC_INIT_V8HI); | |
8455 | ||
8456 | ftype = build_function_type_list (V16QI_type_node, char_type_node, | |
8457 | char_type_node, char_type_node, | |
8458 | char_type_node, char_type_node, | |
8459 | char_type_node, char_type_node, | |
8460 | char_type_node, char_type_node, | |
8461 | char_type_node, char_type_node, | |
8462 | char_type_node, char_type_node, | |
8463 | char_type_node, char_type_node, | |
8464 | char_type_node, NULL_TREE); | |
8465 | def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype, | |
8466 | ALTIVEC_BUILTIN_VEC_INIT_V16QI); | |
8467 | ||
8468 | ftype = build_function_type_list (V4SF_type_node, float_type_node, | |
8469 | float_type_node, float_type_node, | |
8470 | float_type_node, NULL_TREE); | |
8471 | def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype, | |
8472 | ALTIVEC_BUILTIN_VEC_INIT_V4SF); | |
8473 | ||
8474 | /* Access to the vec_set patterns. */ | |
8475 | ftype = build_function_type_list (V4SI_type_node, V4SI_type_node, | |
8476 | intSI_type_node, | |
8477 | integer_type_node, NULL_TREE); | |
8478 | def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype, | |
8479 | ALTIVEC_BUILTIN_VEC_SET_V4SI); | |
8480 | ||
8481 | ftype = build_function_type_list (V8HI_type_node, V8HI_type_node, | |
8482 | intHI_type_node, | |
8483 | integer_type_node, NULL_TREE); | |
8484 | def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype, | |
8485 | ALTIVEC_BUILTIN_VEC_SET_V8HI); | |
8486 | ||
8487 | ftype = build_function_type_list (V8HI_type_node, V16QI_type_node, | |
8488 | intQI_type_node, | |
8489 | integer_type_node, NULL_TREE); | |
8490 | def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype, | |
8491 | ALTIVEC_BUILTIN_VEC_SET_V16QI); | |
8492 | ||
8493 | ftype = build_function_type_list (V4SF_type_node, V4SF_type_node, | |
8494 | float_type_node, | |
8495 | integer_type_node, NULL_TREE); | |
8496 | def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype, | |
8497 | ALTIVEC_BUILTIN_VEC_SET_V4SF); | |
8498 | ||
8499 | /* Access to the vec_extract patterns. */ | |
8500 | ftype = build_function_type_list (intSI_type_node, V4SI_type_node, | |
8501 | integer_type_node, NULL_TREE); | |
8502 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype, | |
8503 | ALTIVEC_BUILTIN_VEC_EXT_V4SI); | |
8504 | ||
8505 | ftype = build_function_type_list (intHI_type_node, V8HI_type_node, | |
8506 | integer_type_node, NULL_TREE); | |
8507 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype, | |
8508 | ALTIVEC_BUILTIN_VEC_EXT_V8HI); | |
8509 | ||
8510 | ftype = build_function_type_list (intQI_type_node, V16QI_type_node, | |
8511 | integer_type_node, NULL_TREE); | |
8512 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype, | |
8513 | ALTIVEC_BUILTIN_VEC_EXT_V16QI); | |
8514 | ||
8515 | ftype = build_function_type_list (float_type_node, V4SF_type_node, | |
8516 | integer_type_node, NULL_TREE); | |
8517 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype, | |
8518 | ALTIVEC_BUILTIN_VEC_EXT_V4SF); | |
a3170dc6 AH |
8519 | } |
8520 | ||
8521 | static void | |
863d938c | 8522 | rs6000_common_init_builtins (void) |
a3170dc6 AH |
8523 | { |
8524 | struct builtin_description *d; | |
8525 | size_t i; | |
8526 | ||
8527 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
8528 | = build_function_type_list (V4SF_type_node, | |
8529 | V4SF_type_node, V4SF_type_node, | |
8530 | V16QI_type_node, NULL_TREE); | |
8531 | tree v4si_ftype_v4si_v4si_v16qi | |
8532 | = build_function_type_list (V4SI_type_node, | |
8533 | V4SI_type_node, V4SI_type_node, | |
8534 | V16QI_type_node, NULL_TREE); | |
8535 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
8536 | = build_function_type_list (V8HI_type_node, | |
8537 | V8HI_type_node, V8HI_type_node, | |
8538 | V16QI_type_node, NULL_TREE); | |
8539 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
8540 | = build_function_type_list (V16QI_type_node, | |
8541 | V16QI_type_node, V16QI_type_node, | |
8542 | V16QI_type_node, NULL_TREE); | |
b9e4e5d1 ZL |
8543 | tree v4si_ftype_int |
8544 | = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); | |
8545 | tree v8hi_ftype_int | |
8546 | = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); | |
8547 | tree v16qi_ftype_int | |
8548 | = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); | |
a3170dc6 AH |
8549 | tree v8hi_ftype_v16qi |
8550 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
8551 | tree v4sf_ftype_v4sf | |
8552 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8553 | ||
8554 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
8555 | = build_function_type_list (opaque_V2SI_type_node, |
8556 | opaque_V2SI_type_node, | |
8557 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8558 | |
8559 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
8560 | = build_function_type_list (opaque_V2SF_type_node, |
8561 | opaque_V2SF_type_node, | |
8562 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
8563 | |
8564 | tree v2si_ftype_int_int | |
2abe3e28 | 8565 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
8566 | integer_type_node, integer_type_node, |
8567 | NULL_TREE); | |
8568 | ||
58646b77 PB |
8569 | tree opaque_ftype_opaque |
8570 | = build_function_type_list (opaque_V4SI_type_node, | |
8571 | opaque_V4SI_type_node, NULL_TREE); | |
8572 | ||
a3170dc6 | 8573 | tree v2si_ftype_v2si |
2abe3e28 AH |
8574 | = build_function_type_list (opaque_V2SI_type_node, |
8575 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8576 | |
8577 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
8578 | = build_function_type_list (opaque_V2SF_type_node, |
8579 | opaque_V2SF_type_node, NULL_TREE); | |
f676971a | 8580 | |
a3170dc6 | 8581 | tree v2sf_ftype_v2si |
2abe3e28 AH |
8582 | = build_function_type_list (opaque_V2SF_type_node, |
8583 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8584 | |
8585 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
8586 | = build_function_type_list (opaque_V2SI_type_node, |
8587 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
8588 | |
8589 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
8590 | = build_function_type_list (opaque_V2SI_type_node, |
8591 | opaque_V2SI_type_node, | |
8592 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
8593 | |
8594 | tree v2si_ftype_int_char | |
2abe3e28 | 8595 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
8596 | integer_type_node, char_type_node, NULL_TREE); |
8597 | ||
8598 | tree v2si_ftype_char | |
2abe3e28 AH |
8599 | = build_function_type_list (opaque_V2SI_type_node, |
8600 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
8601 | |
8602 | tree int_ftype_int_int | |
8603 | = build_function_type_list (integer_type_node, | |
8604 | integer_type_node, integer_type_node, | |
8605 | NULL_TREE); | |
95385cbb | 8606 | |
58646b77 PB |
8607 | tree opaque_ftype_opaque_opaque |
8608 | = build_function_type_list (opaque_V4SI_type_node, | |
8609 | opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8610 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
8611 | = build_function_type_list (V4SI_type_node, |
8612 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
b9e4e5d1 | 8613 | tree v4sf_ftype_v4si_int |
b4de2f7d | 8614 | = build_function_type_list (V4SF_type_node, |
b9e4e5d1 ZL |
8615 | V4SI_type_node, integer_type_node, NULL_TREE); |
8616 | tree v4si_ftype_v4sf_int | |
b4de2f7d | 8617 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
8618 | V4SF_type_node, integer_type_node, NULL_TREE); |
8619 | tree v4si_ftype_v4si_int | |
b4de2f7d | 8620 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
8621 | V4SI_type_node, integer_type_node, NULL_TREE); |
8622 | tree v8hi_ftype_v8hi_int | |
b4de2f7d | 8623 | = build_function_type_list (V8HI_type_node, |
b9e4e5d1 ZL |
8624 | V8HI_type_node, integer_type_node, NULL_TREE); |
8625 | tree v16qi_ftype_v16qi_int | |
b4de2f7d | 8626 | = build_function_type_list (V16QI_type_node, |
b9e4e5d1 ZL |
8627 | V16QI_type_node, integer_type_node, NULL_TREE); |
8628 | tree v16qi_ftype_v16qi_v16qi_int | |
b4de2f7d AH |
8629 | = build_function_type_list (V16QI_type_node, |
8630 | V16QI_type_node, V16QI_type_node, | |
b9e4e5d1 ZL |
8631 | integer_type_node, NULL_TREE); |
8632 | tree v8hi_ftype_v8hi_v8hi_int | |
b4de2f7d AH |
8633 | = build_function_type_list (V8HI_type_node, |
8634 | V8HI_type_node, V8HI_type_node, | |
b9e4e5d1 ZL |
8635 | integer_type_node, NULL_TREE); |
8636 | tree v4si_ftype_v4si_v4si_int | |
b4de2f7d AH |
8637 | = build_function_type_list (V4SI_type_node, |
8638 | V4SI_type_node, V4SI_type_node, | |
b9e4e5d1 ZL |
8639 | integer_type_node, NULL_TREE); |
8640 | tree v4sf_ftype_v4sf_v4sf_int | |
b4de2f7d AH |
8641 | = build_function_type_list (V4SF_type_node, |
8642 | V4SF_type_node, V4SF_type_node, | |
b9e4e5d1 | 8643 | integer_type_node, NULL_TREE); |
0ac081f6 | 8644 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
8645 | = build_function_type_list (V4SF_type_node, |
8646 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
58646b77 PB |
8647 | tree opaque_ftype_opaque_opaque_opaque |
8648 | = build_function_type_list (opaque_V4SI_type_node, | |
8649 | opaque_V4SI_type_node, opaque_V4SI_type_node, | |
8650 | opaque_V4SI_type_node, NULL_TREE); | |
617e0e1d | 8651 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
8652 | = build_function_type_list (V4SF_type_node, |
8653 | V4SF_type_node, V4SF_type_node, | |
8654 | V4SI_type_node, NULL_TREE); | |
2212663f | 8655 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
8656 | = build_function_type_list (V4SF_type_node, |
8657 | V4SF_type_node, V4SF_type_node, | |
8658 | V4SF_type_node, NULL_TREE); | |
f676971a | 8659 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
8660 | = build_function_type_list (V4SI_type_node, |
8661 | V4SI_type_node, V4SI_type_node, | |
8662 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8663 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
8664 | = build_function_type_list (V8HI_type_node, |
8665 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 8666 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
8667 | = build_function_type_list (V8HI_type_node, |
8668 | V8HI_type_node, V8HI_type_node, | |
8669 | V8HI_type_node, NULL_TREE); | |
c4ad648e | 8670 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
8671 | = build_function_type_list (V4SI_type_node, |
8672 | V8HI_type_node, V8HI_type_node, | |
8673 | V4SI_type_node, NULL_TREE); | |
c4ad648e | 8674 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
8675 | = build_function_type_list (V4SI_type_node, |
8676 | V16QI_type_node, V16QI_type_node, | |
8677 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8678 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
8679 | = build_function_type_list (V16QI_type_node, |
8680 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8681 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
8682 | = build_function_type_list (V4SI_type_node, |
8683 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 8684 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
8685 | = build_function_type_list (V8HI_type_node, |
8686 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8687 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
8688 | = build_function_type_list (V4SI_type_node, |
8689 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8690 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
8691 | = build_function_type_list (V8HI_type_node, |
8692 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8693 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
8694 | = build_function_type_list (V16QI_type_node, |
8695 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8696 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
8697 | = build_function_type_list (V4SI_type_node, |
8698 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 8699 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
8700 | = build_function_type_list (V4SI_type_node, |
8701 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8702 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
8703 | = build_function_type_list (V4SI_type_node, |
8704 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8705 | tree v4si_ftype_v8hi |
8706 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
8707 | tree int_ftype_v4si_v4si | |
8708 | = build_function_type_list (integer_type_node, | |
8709 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
8710 | tree int_ftype_v4sf_v4sf | |
8711 | = build_function_type_list (integer_type_node, | |
8712 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8713 | tree int_ftype_v16qi_v16qi | |
8714 | = build_function_type_list (integer_type_node, | |
8715 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8716 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
8717 | = build_function_type_list (integer_type_node, |
8718 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8719 | |
6f317ef3 | 8720 | /* Add the simple ternary operators. */ |
2212663f | 8721 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 8722 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f | 8723 | { |
2212663f DB |
8724 | enum machine_mode mode0, mode1, mode2, mode3; |
8725 | tree type; | |
58646b77 PB |
8726 | bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
8727 | && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
2212663f | 8728 | |
58646b77 PB |
8729 | if (is_overloaded) |
8730 | { | |
8731 | mode0 = VOIDmode; | |
8732 | mode1 = VOIDmode; | |
8733 | mode2 = VOIDmode; | |
8734 | mode3 = VOIDmode; | |
8735 | } | |
8736 | else | |
8737 | { | |
8738 | if (d->name == 0 || d->icode == CODE_FOR_nothing) | |
8739 | continue; | |
f676971a | 8740 | |
58646b77 PB |
8741 | mode0 = insn_data[d->icode].operand[0].mode; |
8742 | mode1 = insn_data[d->icode].operand[1].mode; | |
8743 | mode2 = insn_data[d->icode].operand[2].mode; | |
8744 | mode3 = insn_data[d->icode].operand[3].mode; | |
8745 | } | |
bb8df8a6 | 8746 | |
2212663f DB |
8747 | /* When all four are of the same mode. */ |
8748 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
8749 | { | |
8750 | switch (mode0) | |
8751 | { | |
58646b77 PB |
8752 | case VOIDmode: |
8753 | type = opaque_ftype_opaque_opaque_opaque; | |
8754 | break; | |
617e0e1d DB |
8755 | case V4SImode: |
8756 | type = v4si_ftype_v4si_v4si_v4si; | |
8757 | break; | |
2212663f DB |
8758 | case V4SFmode: |
8759 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
8760 | break; | |
8761 | case V8HImode: | |
8762 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
f676971a | 8763 | break; |
2212663f DB |
8764 | case V16QImode: |
8765 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 8766 | break; |
2212663f | 8767 | default: |
37409796 | 8768 | gcc_unreachable (); |
2212663f DB |
8769 | } |
8770 | } | |
8771 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
c4ad648e | 8772 | { |
2212663f DB |
8773 | switch (mode0) |
8774 | { | |
8775 | case V4SImode: | |
8776 | type = v4si_ftype_v4si_v4si_v16qi; | |
8777 | break; | |
8778 | case V4SFmode: | |
8779 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
8780 | break; | |
8781 | case V8HImode: | |
8782 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
f676971a | 8783 | break; |
2212663f DB |
8784 | case V16QImode: |
8785 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 8786 | break; |
2212663f | 8787 | default: |
37409796 | 8788 | gcc_unreachable (); |
2212663f DB |
8789 | } |
8790 | } | |
f676971a | 8791 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode |
2212663f | 8792 | && mode3 == V4SImode) |
24408032 | 8793 | type = v4si_ftype_v16qi_v16qi_v4si; |
f676971a | 8794 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
2212663f | 8795 | && mode3 == V4SImode) |
24408032 | 8796 | type = v4si_ftype_v8hi_v8hi_v4si; |
f676971a | 8797 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
617e0e1d | 8798 | && mode3 == V4SImode) |
24408032 AH |
8799 | type = v4sf_ftype_v4sf_v4sf_v4si; |
8800 | ||
8801 | /* vchar, vchar, vchar, 4 bit literal. */ | |
8802 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
8803 | && mode3 == QImode) | |
b9e4e5d1 | 8804 | type = v16qi_ftype_v16qi_v16qi_int; |
24408032 AH |
8805 | |
8806 | /* vshort, vshort, vshort, 4 bit literal. */ | |
8807 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
8808 | && mode3 == QImode) | |
b9e4e5d1 | 8809 | type = v8hi_ftype_v8hi_v8hi_int; |
24408032 AH |
8810 | |
8811 | /* vint, vint, vint, 4 bit literal. */ | |
8812 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
8813 | && mode3 == QImode) | |
b9e4e5d1 | 8814 | type = v4si_ftype_v4si_v4si_int; |
24408032 AH |
8815 | |
8816 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
8817 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
8818 | && mode3 == QImode) | |
b9e4e5d1 | 8819 | type = v4sf_ftype_v4sf_v4sf_int; |
24408032 | 8820 | |
2212663f | 8821 | else |
37409796 | 8822 | gcc_unreachable (); |
2212663f DB |
8823 | |
8824 | def_builtin (d->mask, d->name, type, d->code); | |
8825 | } | |
8826 | ||
0ac081f6 | 8827 | /* Add the simple binary operators. */ |
00b960c7 | 8828 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 8829 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
8830 | { |
8831 | enum machine_mode mode0, mode1, mode2; | |
8832 | tree type; | |
58646b77 PB |
8833 | bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
8834 | && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
0ac081f6 | 8835 | |
58646b77 PB |
8836 | if (is_overloaded) |
8837 | { | |
8838 | mode0 = VOIDmode; | |
8839 | mode1 = VOIDmode; | |
8840 | mode2 = VOIDmode; | |
8841 | } | |
8842 | else | |
bb8df8a6 | 8843 | { |
58646b77 PB |
8844 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
8845 | continue; | |
f676971a | 8846 | |
58646b77 PB |
8847 | mode0 = insn_data[d->icode].operand[0].mode; |
8848 | mode1 = insn_data[d->icode].operand[1].mode; | |
8849 | mode2 = insn_data[d->icode].operand[2].mode; | |
8850 | } | |
0ac081f6 AH |
8851 | |
8852 | /* When all three operands are of the same mode. */ | |
8853 | if (mode0 == mode1 && mode1 == mode2) | |
8854 | { | |
8855 | switch (mode0) | |
8856 | { | |
58646b77 PB |
8857 | case VOIDmode: |
8858 | type = opaque_ftype_opaque_opaque; | |
8859 | break; | |
0ac081f6 AH |
8860 | case V4SFmode: |
8861 | type = v4sf_ftype_v4sf_v4sf; | |
8862 | break; | |
8863 | case V4SImode: | |
8864 | type = v4si_ftype_v4si_v4si; | |
8865 | break; | |
8866 | case V16QImode: | |
8867 | type = v16qi_ftype_v16qi_v16qi; | |
8868 | break; | |
8869 | case V8HImode: | |
8870 | type = v8hi_ftype_v8hi_v8hi; | |
8871 | break; | |
a3170dc6 AH |
8872 | case V2SImode: |
8873 | type = v2si_ftype_v2si_v2si; | |
8874 | break; | |
8875 | case V2SFmode: | |
8876 | type = v2sf_ftype_v2sf_v2sf; | |
8877 | break; | |
8878 | case SImode: | |
8879 | type = int_ftype_int_int; | |
8880 | break; | |
0ac081f6 | 8881 | default: |
37409796 | 8882 | gcc_unreachable (); |
0ac081f6 AH |
8883 | } |
8884 | } | |
8885 | ||
8886 | /* A few other combos we really don't want to do manually. */ | |
8887 | ||
8888 | /* vint, vfloat, vfloat. */ | |
8889 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
8890 | type = v4si_ftype_v4sf_v4sf; | |
8891 | ||
8892 | /* vshort, vchar, vchar. */ | |
8893 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
8894 | type = v8hi_ftype_v16qi_v16qi; | |
8895 | ||
8896 | /* vint, vshort, vshort. */ | |
8897 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
8898 | type = v4si_ftype_v8hi_v8hi; | |
8899 | ||
8900 | /* vshort, vint, vint. */ | |
8901 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
8902 | type = v8hi_ftype_v4si_v4si; | |
8903 | ||
8904 | /* vchar, vshort, vshort. */ | |
8905 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
8906 | type = v16qi_ftype_v8hi_v8hi; | |
8907 | ||
8908 | /* vint, vchar, vint. */ | |
8909 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
8910 | type = v4si_ftype_v16qi_v4si; | |
8911 | ||
fa066a23 AH |
8912 | /* vint, vchar, vchar. */ |
8913 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
8914 | type = v4si_ftype_v16qi_v16qi; | |
8915 | ||
0ac081f6 AH |
8916 | /* vint, vshort, vint. */ |
8917 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
8918 | type = v4si_ftype_v8hi_v4si; | |
f676971a | 8919 | |
2212663f DB |
8920 | /* vint, vint, 5 bit literal. */ |
8921 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8922 | type = v4si_ftype_v4si_int; |
f676971a | 8923 | |
2212663f DB |
8924 | /* vshort, vshort, 5 bit literal. */ |
8925 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
b9e4e5d1 | 8926 | type = v8hi_ftype_v8hi_int; |
f676971a | 8927 | |
2212663f DB |
8928 | /* vchar, vchar, 5 bit literal. */ |
8929 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
b9e4e5d1 | 8930 | type = v16qi_ftype_v16qi_int; |
0ac081f6 | 8931 | |
617e0e1d DB |
8932 | /* vfloat, vint, 5 bit literal. */ |
8933 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8934 | type = v4sf_ftype_v4si_int; |
f676971a | 8935 | |
617e0e1d DB |
8936 | /* vint, vfloat, 5 bit literal. */ |
8937 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
b9e4e5d1 | 8938 | type = v4si_ftype_v4sf_int; |
617e0e1d | 8939 | |
a3170dc6 AH |
8940 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
8941 | type = v2si_ftype_int_int; | |
8942 | ||
8943 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
8944 | type = v2si_ftype_v2si_char; | |
8945 | ||
8946 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
8947 | type = v2si_ftype_int_char; | |
8948 | ||
37409796 | 8949 | else |
0ac081f6 | 8950 | { |
37409796 NS |
8951 | /* int, x, x. */ |
8952 | gcc_assert (mode0 == SImode); | |
0ac081f6 AH |
8953 | switch (mode1) |
8954 | { | |
8955 | case V4SImode: | |
8956 | type = int_ftype_v4si_v4si; | |
8957 | break; | |
8958 | case V4SFmode: | |
8959 | type = int_ftype_v4sf_v4sf; | |
8960 | break; | |
8961 | case V16QImode: | |
8962 | type = int_ftype_v16qi_v16qi; | |
8963 | break; | |
8964 | case V8HImode: | |
8965 | type = int_ftype_v8hi_v8hi; | |
8966 | break; | |
8967 | default: | |
37409796 | 8968 | gcc_unreachable (); |
0ac081f6 AH |
8969 | } |
8970 | } | |
8971 | ||
2212663f DB |
8972 | def_builtin (d->mask, d->name, type, d->code); |
8973 | } | |
24408032 | 8974 | |
2212663f DB |
8975 | /* Add the simple unary operators. */ |
8976 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 8977 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
8978 | { |
8979 | enum machine_mode mode0, mode1; | |
8980 | tree type; | |
58646b77 PB |
8981 | bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
8982 | && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
8983 | ||
8984 | if (is_overloaded) | |
8985 | { | |
8986 | mode0 = VOIDmode; | |
8987 | mode1 = VOIDmode; | |
8988 | } | |
8989 | else | |
8990 | { | |
8991 | if (d->name == 0 || d->icode == CODE_FOR_nothing) | |
8992 | continue; | |
bb8df8a6 | 8993 | |
58646b77 PB |
8994 | mode0 = insn_data[d->icode].operand[0].mode; |
8995 | mode1 = insn_data[d->icode].operand[1].mode; | |
8996 | } | |
2212663f DB |
8997 | |
8998 | if (mode0 == V4SImode && mode1 == QImode) | |
c4ad648e | 8999 | type = v4si_ftype_int; |
2212663f | 9000 | else if (mode0 == V8HImode && mode1 == QImode) |
c4ad648e | 9001 | type = v8hi_ftype_int; |
2212663f | 9002 | else if (mode0 == V16QImode && mode1 == QImode) |
c4ad648e | 9003 | type = v16qi_ftype_int; |
58646b77 PB |
9004 | else if (mode0 == VOIDmode && mode1 == VOIDmode) |
9005 | type = opaque_ftype_opaque; | |
617e0e1d DB |
9006 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
9007 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
9008 | else if (mode0 == V8HImode && mode1 == V16QImode) |
9009 | type = v8hi_ftype_v16qi; | |
9010 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
9011 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
9012 | else if (mode0 == V2SImode && mode1 == V2SImode) |
9013 | type = v2si_ftype_v2si; | |
9014 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
9015 | type = v2sf_ftype_v2sf; | |
9016 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
9017 | type = v2sf_ftype_v2si; | |
9018 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
9019 | type = v2si_ftype_v2sf; | |
9020 | else if (mode0 == V2SImode && mode1 == QImode) | |
9021 | type = v2si_ftype_char; | |
2212663f | 9022 | else |
37409796 | 9023 | gcc_unreachable (); |
2212663f | 9024 | |
0ac081f6 AH |
9025 | def_builtin (d->mask, d->name, type, d->code); |
9026 | } | |
9027 | } | |
9028 | ||
c15c90bb ZW |
9029 | static void |
9030 | rs6000_init_libfuncs (void) | |
9031 | { | |
9032 | if (!TARGET_HARD_FLOAT) | |
9033 | return; | |
9034 | ||
c9034561 | 9035 | if (DEFAULT_ABI != ABI_V4) |
c15c90bb | 9036 | { |
c9034561 | 9037 | if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC) |
c15c90bb | 9038 | { |
c9034561 | 9039 | /* AIX library routines for float->int conversion. */ |
85363ca0 ZW |
9040 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); |
9041 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
4274207b DE |
9042 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); |
9043 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
c15c90bb ZW |
9044 | } |
9045 | ||
98c41d98 DE |
9046 | /* AIX/Darwin/64-bit Linux quad floating point routines. */ |
9047 | if (!TARGET_XL_COMPAT) | |
9048 | { | |
9049 | set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); | |
9050 | set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); | |
9051 | set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); | |
9052 | set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); | |
9053 | } | |
9054 | else | |
9055 | { | |
9056 | set_optab_libfunc (add_optab, TFmode, "_xlqadd"); | |
9057 | set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); | |
9058 | set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); | |
9059 | set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); | |
9060 | } | |
c15c90bb | 9061 | } |
c9034561 | 9062 | else |
c15c90bb | 9063 | { |
c9034561 | 9064 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
9065 | |
9066 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
9067 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
9068 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
9069 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
9070 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
9071 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
9072 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
9073 | ||
c9034561 ZW |
9074 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
9075 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
9076 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
9077 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
9078 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
9079 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
9080 | ||
85363ca0 ZW |
9081 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
9082 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
9083 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
9084 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
9085 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
9086 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
9087 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
57904aa7 | 9088 | set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq"); |
c15c90bb ZW |
9089 | } |
9090 | } | |
fba73eb1 DE |
9091 | |
9092 | \f | |
9093 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
9094 | if we should let the compiler generate normal code. | |
9095 | ||
9096 | operands[0] is the destination | |
9097 | operands[1] is the length | |
57e84f18 | 9098 | operands[3] is the alignment */ |
fba73eb1 DE |
9099 | |
9100 | int | |
9101 | expand_block_clear (rtx operands[]) | |
9102 | { | |
9103 | rtx orig_dest = operands[0]; | |
9104 | rtx bytes_rtx = operands[1]; | |
57e84f18 | 9105 | rtx align_rtx = operands[3]; |
5514620a GK |
9106 | bool constp = (GET_CODE (bytes_rtx) == CONST_INT); |
9107 | HOST_WIDE_INT align; | |
9108 | HOST_WIDE_INT bytes; | |
fba73eb1 DE |
9109 | int offset; |
9110 | int clear_bytes; | |
5514620a | 9111 | int clear_step; |
fba73eb1 DE |
9112 | |
9113 | /* If this is not a fixed size move, just call memcpy */ | |
9114 | if (! constp) | |
9115 | return 0; | |
9116 | ||
37409796 NS |
9117 | /* This must be a fixed size alignment */ |
9118 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
fba73eb1 DE |
9119 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
9120 | ||
9121 | /* Anything to clear? */ | |
9122 | bytes = INTVAL (bytes_rtx); | |
9123 | if (bytes <= 0) | |
9124 | return 1; | |
9125 | ||
5514620a GK |
9126 | /* Use the builtin memset after a point, to avoid huge code bloat. |
9127 | When optimize_size, avoid any significant code bloat; calling | |
9128 | memset is about 4 instructions, so allow for one instruction to | |
9129 | load zero and three to do clearing. */ | |
9130 | if (TARGET_ALTIVEC && align >= 128) | |
9131 | clear_step = 16; | |
9132 | else if (TARGET_POWERPC64 && align >= 32) | |
9133 | clear_step = 8; | |
9134 | else | |
9135 | clear_step = 4; | |
fba73eb1 | 9136 | |
5514620a GK |
9137 | if (optimize_size && bytes > 3 * clear_step) |
9138 | return 0; | |
9139 | if (! optimize_size && bytes > 8 * clear_step) | |
fba73eb1 DE |
9140 | return 0; |
9141 | ||
9142 | for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) | |
9143 | { | |
fba73eb1 DE |
9144 | enum machine_mode mode = BLKmode; |
9145 | rtx dest; | |
f676971a | 9146 | |
5514620a GK |
9147 | if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) |
9148 | { | |
9149 | clear_bytes = 16; | |
9150 | mode = V4SImode; | |
9151 | } | |
9152 | else if (bytes >= 8 && TARGET_POWERPC64 | |
9153 | /* 64-bit loads and stores require word-aligned | |
9154 | displacements. */ | |
9155 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) | |
fba73eb1 DE |
9156 | { |
9157 | clear_bytes = 8; | |
9158 | mode = DImode; | |
fba73eb1 | 9159 | } |
5514620a | 9160 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
9161 | { /* move 4 bytes */ |
9162 | clear_bytes = 4; | |
9163 | mode = SImode; | |
fba73eb1 | 9164 | } |
ec53fc93 | 9165 | else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
9166 | { /* move 2 bytes */ |
9167 | clear_bytes = 2; | |
9168 | mode = HImode; | |
fba73eb1 DE |
9169 | } |
9170 | else /* move 1 byte at a time */ | |
9171 | { | |
9172 | clear_bytes = 1; | |
9173 | mode = QImode; | |
fba73eb1 | 9174 | } |
f676971a | 9175 | |
fba73eb1 | 9176 | dest = adjust_address (orig_dest, mode, offset); |
f676971a | 9177 | |
5514620a | 9178 | emit_move_insn (dest, CONST0_RTX (mode)); |
fba73eb1 DE |
9179 | } |
9180 | ||
9181 | return 1; | |
9182 | } | |
9183 | ||
35aff10b | 9184 | \f |
7e69e155 MM |
9185 | /* Expand a block move operation, and return 1 if successful. Return 0 |
9186 | if we should let the compiler generate normal code. | |
9187 | ||
9188 | operands[0] is the destination | |
9189 | operands[1] is the source | |
9190 | operands[2] is the length | |
9191 | operands[3] is the alignment */ | |
9192 | ||
3933e0e1 MM |
9193 | #define MAX_MOVE_REG 4 |
9194 | ||
7e69e155 | 9195 | int |
a2369ed3 | 9196 | expand_block_move (rtx operands[]) |
7e69e155 | 9197 | { |
b6c9286a MM |
9198 | rtx orig_dest = operands[0]; |
9199 | rtx orig_src = operands[1]; | |
7e69e155 | 9200 | rtx bytes_rtx = operands[2]; |
7e69e155 | 9201 | rtx align_rtx = operands[3]; |
3933e0e1 | 9202 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 9203 | int align; |
3933e0e1 MM |
9204 | int bytes; |
9205 | int offset; | |
7e69e155 | 9206 | int move_bytes; |
cabfd258 GK |
9207 | rtx stores[MAX_MOVE_REG]; |
9208 | int num_reg = 0; | |
7e69e155 | 9209 | |
3933e0e1 | 9210 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 9211 | if (! constp) |
3933e0e1 MM |
9212 | return 0; |
9213 | ||
37409796 NS |
9214 | /* This must be a fixed size alignment */ |
9215 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
fba73eb1 | 9216 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
5ee95df6 | 9217 | |
7e69e155 | 9218 | /* Anything to move? */ |
3933e0e1 MM |
9219 | bytes = INTVAL (bytes_rtx); |
9220 | if (bytes <= 0) | |
7e69e155 MM |
9221 | return 1; |
9222 | ||
ea9982a8 | 9223 | /* store_one_arg depends on expand_block_move to handle at least the size of |
f676971a | 9224 | reg_parm_stack_space. */ |
ea9982a8 | 9225 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
9226 | return 0; |
9227 | ||
cabfd258 | 9228 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 9229 | { |
cabfd258 | 9230 | union { |
70128ad9 | 9231 | rtx (*movmemsi) (rtx, rtx, rtx, rtx); |
a2369ed3 | 9232 | rtx (*mov) (rtx, rtx); |
cabfd258 GK |
9233 | } gen_func; |
9234 | enum machine_mode mode = BLKmode; | |
9235 | rtx src, dest; | |
f676971a | 9236 | |
5514620a GK |
9237 | /* Altivec first, since it will be faster than a string move |
9238 | when it applies, and usually not significantly larger. */ | |
9239 | if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) | |
9240 | { | |
9241 | move_bytes = 16; | |
9242 | mode = V4SImode; | |
9243 | gen_func.mov = gen_movv4si; | |
9244 | } | |
9245 | else if (TARGET_STRING | |
cabfd258 GK |
9246 | && bytes > 24 /* move up to 32 bytes at a time */ |
9247 | && ! fixed_regs[5] | |
9248 | && ! fixed_regs[6] | |
9249 | && ! fixed_regs[7] | |
9250 | && ! fixed_regs[8] | |
9251 | && ! fixed_regs[9] | |
9252 | && ! fixed_regs[10] | |
9253 | && ! fixed_regs[11] | |
9254 | && ! fixed_regs[12]) | |
7e69e155 | 9255 | { |
cabfd258 | 9256 | move_bytes = (bytes > 32) ? 32 : bytes; |
70128ad9 | 9257 | gen_func.movmemsi = gen_movmemsi_8reg; |
cabfd258 GK |
9258 | } |
9259 | else if (TARGET_STRING | |
9260 | && bytes > 16 /* move up to 24 bytes at a time */ | |
9261 | && ! fixed_regs[5] | |
9262 | && ! fixed_regs[6] | |
9263 | && ! fixed_regs[7] | |
9264 | && ! fixed_regs[8] | |
9265 | && ! fixed_regs[9] | |
9266 | && ! fixed_regs[10]) | |
9267 | { | |
9268 | move_bytes = (bytes > 24) ? 24 : bytes; | |
70128ad9 | 9269 | gen_func.movmemsi = gen_movmemsi_6reg; |
cabfd258 GK |
9270 | } |
9271 | else if (TARGET_STRING | |
9272 | && bytes > 8 /* move up to 16 bytes at a time */ | |
9273 | && ! fixed_regs[5] | |
9274 | && ! fixed_regs[6] | |
9275 | && ! fixed_regs[7] | |
9276 | && ! fixed_regs[8]) | |
9277 | { | |
9278 | move_bytes = (bytes > 16) ? 16 : bytes; | |
70128ad9 | 9279 | gen_func.movmemsi = gen_movmemsi_4reg; |
cabfd258 GK |
9280 | } |
9281 | else if (bytes >= 8 && TARGET_POWERPC64 | |
9282 | /* 64-bit loads and stores require word-aligned | |
9283 | displacements. */ | |
fba73eb1 | 9284 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) |
cabfd258 GK |
9285 | { |
9286 | move_bytes = 8; | |
9287 | mode = DImode; | |
9288 | gen_func.mov = gen_movdi; | |
9289 | } | |
9290 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
9291 | { /* move up to 8 bytes at a time */ | |
9292 | move_bytes = (bytes > 8) ? 8 : bytes; | |
70128ad9 | 9293 | gen_func.movmemsi = gen_movmemsi_2reg; |
cabfd258 | 9294 | } |
cd7d9ca4 | 9295 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
9296 | { /* move 4 bytes */ |
9297 | move_bytes = 4; | |
9298 | mode = SImode; | |
9299 | gen_func.mov = gen_movsi; | |
9300 | } | |
ec53fc93 | 9301 | else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
9302 | { /* move 2 bytes */ |
9303 | move_bytes = 2; | |
9304 | mode = HImode; | |
9305 | gen_func.mov = gen_movhi; | |
9306 | } | |
9307 | else if (TARGET_STRING && bytes > 1) | |
9308 | { /* move up to 4 bytes at a time */ | |
9309 | move_bytes = (bytes > 4) ? 4 : bytes; | |
70128ad9 | 9310 | gen_func.movmemsi = gen_movmemsi_1reg; |
cabfd258 GK |
9311 | } |
9312 | else /* move 1 byte at a time */ | |
9313 | { | |
9314 | move_bytes = 1; | |
9315 | mode = QImode; | |
9316 | gen_func.mov = gen_movqi; | |
9317 | } | |
f676971a | 9318 | |
cabfd258 GK |
9319 | src = adjust_address (orig_src, mode, offset); |
9320 | dest = adjust_address (orig_dest, mode, offset); | |
f676971a EC |
9321 | |
9322 | if (mode != BLKmode) | |
cabfd258 GK |
9323 | { |
9324 | rtx tmp_reg = gen_reg_rtx (mode); | |
f676971a | 9325 | |
cabfd258 GK |
9326 | emit_insn ((*gen_func.mov) (tmp_reg, src)); |
9327 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 9328 | } |
3933e0e1 | 9329 | |
cabfd258 GK |
9330 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
9331 | { | |
9332 | int i; | |
9333 | for (i = 0; i < num_reg; i++) | |
9334 | emit_insn (stores[i]); | |
9335 | num_reg = 0; | |
9336 | } | |
35aff10b | 9337 | |
cabfd258 | 9338 | if (mode == BLKmode) |
7e69e155 | 9339 | { |
70128ad9 | 9340 | /* Move the address into scratch registers. The movmemsi |
cabfd258 GK |
9341 | patterns require zero offset. */ |
9342 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 9343 | { |
cabfd258 GK |
9344 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
9345 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 9346 | } |
cabfd258 | 9347 | set_mem_size (src, GEN_INT (move_bytes)); |
f676971a | 9348 | |
cabfd258 | 9349 | if (!REG_P (XEXP (dest, 0))) |
3933e0e1 | 9350 | { |
cabfd258 GK |
9351 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
9352 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 9353 | } |
cabfd258 | 9354 | set_mem_size (dest, GEN_INT (move_bytes)); |
f676971a | 9355 | |
70128ad9 | 9356 | emit_insn ((*gen_func.movmemsi) (dest, src, |
cabfd258 GK |
9357 | GEN_INT (move_bytes & 31), |
9358 | align_rtx)); | |
7e69e155 | 9359 | } |
7e69e155 MM |
9360 | } |
9361 | ||
9362 | return 1; | |
9363 | } | |
9364 | ||
d62294f5 | 9365 | \f |
9caa3eb2 DE |
9366 | /* Return a string to perform a load_multiple operation. |
9367 | operands[0] is the vector. | |
9368 | operands[1] is the source address. | |
9369 | operands[2] is the first destination register. */ | |
9370 | ||
9371 | const char * | |
a2369ed3 | 9372 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
9373 | { |
9374 | /* We have to handle the case where the pseudo used to contain the address | |
9375 | is assigned to one of the output registers. */ | |
9376 | int i, j; | |
9377 | int words = XVECLEN (operands[0], 0); | |
9378 | rtx xop[10]; | |
9379 | ||
9380 | if (XVECLEN (operands[0], 0) == 1) | |
9381 | return "{l|lwz} %2,0(%1)"; | |
9382 | ||
9383 | for (i = 0; i < words; i++) | |
9384 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
9385 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
9386 | { | |
9387 | if (i == words-1) | |
9388 | { | |
9389 | xop[0] = GEN_INT (4 * (words-1)); | |
9390 | xop[1] = operands[1]; | |
9391 | xop[2] = operands[2]; | |
9392 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
9393 | return ""; | |
9394 | } | |
9395 | else if (i == 0) | |
9396 | { | |
9397 | xop[0] = GEN_INT (4 * (words-1)); | |
9398 | xop[1] = operands[1]; | |
9399 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
9400 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
9401 | return ""; | |
9402 | } | |
9403 | else | |
9404 | { | |
9405 | for (j = 0; j < words; j++) | |
9406 | if (j != i) | |
9407 | { | |
9408 | xop[0] = GEN_INT (j * 4); | |
9409 | xop[1] = operands[1]; | |
9410 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
9411 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
9412 | } | |
9413 | xop[0] = GEN_INT (i * 4); | |
9414 | xop[1] = operands[1]; | |
9415 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
9416 | return ""; | |
9417 | } | |
9418 | } | |
9419 | ||
9420 | return "{lsi|lswi} %2,%1,%N0"; | |
9421 | } | |
9422 | ||
9878760c | 9423 | \f |
a4f6c312 SS |
9424 | /* A validation routine: say whether CODE, a condition code, and MODE |
9425 | match. The other alternatives either don't make sense or should | |
9426 | never be generated. */ | |
39a10a29 | 9427 | |
48d72335 | 9428 | void |
a2369ed3 | 9429 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 | 9430 | { |
37409796 NS |
9431 | gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE |
9432 | || GET_RTX_CLASS (code) == RTX_COMM_COMPARE) | |
9433 | && GET_MODE_CLASS (mode) == MODE_CC); | |
39a10a29 GK |
9434 | |
9435 | /* These don't make sense. */ | |
37409796 NS |
9436 | gcc_assert ((code != GT && code != LT && code != GE && code != LE) |
9437 | || mode != CCUNSmode); | |
39a10a29 | 9438 | |
37409796 NS |
9439 | gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU) |
9440 | || mode == CCUNSmode); | |
39a10a29 | 9441 | |
37409796 NS |
9442 | gcc_assert (mode == CCFPmode |
9443 | || (code != ORDERED && code != UNORDERED | |
9444 | && code != UNEQ && code != LTGT | |
9445 | && code != UNGT && code != UNLT | |
9446 | && code != UNGE && code != UNLE)); | |
f676971a EC |
9447 | |
9448 | /* These should never be generated except for | |
bc9ec0e0 | 9449 | flag_finite_math_only. */ |
37409796 NS |
9450 | gcc_assert (mode != CCFPmode |
9451 | || flag_finite_math_only | |
9452 | || (code != LE && code != GE | |
9453 | && code != UNEQ && code != LTGT | |
9454 | && code != UNGT && code != UNLT)); | |
39a10a29 GK |
9455 | |
9456 | /* These are invalid; the information is not there. */ | |
37409796 | 9457 | gcc_assert (mode != CCEQmode || code == EQ || code == NE); |
39a10a29 GK |
9458 | } |
9459 | ||
9878760c RK |
9460 | \f |
9461 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
9462 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 9463 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
9464 | |
9465 | int | |
a2369ed3 | 9466 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 9467 | { |
e2c953b6 DE |
9468 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9469 | ||
9470 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 9471 | |
b1765bde | 9472 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
9473 | } |
9474 | ||
9475 | /* Similar, but for right shift. */ | |
9476 | ||
9477 | int | |
a2369ed3 | 9478 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 9479 | { |
a7653a2c | 9480 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
9481 | |
9482 | shift_mask >>= INTVAL (shiftop); | |
9483 | ||
b1765bde | 9484 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
9485 | } |
9486 | ||
c5059423 AM |
9487 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
9488 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 9489 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
9490 | |
9491 | int | |
a2369ed3 | 9492 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 9493 | { |
c5059423 AM |
9494 | if (GET_CODE (andop) == CONST_INT) |
9495 | { | |
02071907 | 9496 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 9497 | |
c5059423 | 9498 | c = INTVAL (andop); |
02071907 | 9499 | if (c == 0 || c == ~0) |
c5059423 | 9500 | return 0; |
e2c953b6 | 9501 | |
02071907 | 9502 | shift_mask = ~0; |
c5059423 AM |
9503 | shift_mask <<= INTVAL (shiftop); |
9504 | ||
b6d08ca1 | 9505 | /* Find the least significant one bit. */ |
c5059423 AM |
9506 | lsb = c & -c; |
9507 | ||
9508 | /* It must coincide with the LSB of the shift mask. */ | |
9509 | if (-lsb != shift_mask) | |
9510 | return 0; | |
e2c953b6 | 9511 | |
c5059423 AM |
9512 | /* Invert to look for the next transition (if any). */ |
9513 | c = ~c; | |
9514 | ||
9515 | /* Remove the low group of ones (originally low group of zeros). */ | |
9516 | c &= -lsb; | |
9517 | ||
9518 | /* Again find the lsb, and check we have all 1's above. */ | |
9519 | lsb = c & -c; | |
9520 | return c == -lsb; | |
9521 | } | |
9522 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9523 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9524 | { | |
02071907 AM |
9525 | HOST_WIDE_INT low, high, lsb; |
9526 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
9527 | |
9528 | low = CONST_DOUBLE_LOW (andop); | |
9529 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9530 | high = CONST_DOUBLE_HIGH (andop); | |
9531 | ||
9532 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 9533 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
9534 | return 0; |
9535 | ||
9536 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9537 | { | |
02071907 | 9538 | shift_mask_high = ~0; |
c5059423 AM |
9539 | if (INTVAL (shiftop) > 32) |
9540 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9541 | ||
9542 | lsb = high & -high; | |
9543 | ||
9544 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
9545 | return 0; | |
9546 | ||
9547 | high = ~high; | |
9548 | high &= -lsb; | |
9549 | ||
9550 | lsb = high & -high; | |
9551 | return high == -lsb; | |
9552 | } | |
9553 | ||
02071907 | 9554 | shift_mask_low = ~0; |
c5059423 AM |
9555 | shift_mask_low <<= INTVAL (shiftop); |
9556 | ||
9557 | lsb = low & -low; | |
9558 | ||
9559 | if (-lsb != shift_mask_low) | |
9560 | return 0; | |
9561 | ||
9562 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9563 | high = ~high; | |
9564 | low = ~low; | |
9565 | low &= -lsb; | |
9566 | ||
9567 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9568 | { | |
9569 | lsb = high & -high; | |
9570 | return high == -lsb; | |
9571 | } | |
9572 | ||
9573 | lsb = low & -low; | |
9574 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
9575 | } | |
9576 | else | |
9577 | return 0; | |
9578 | } | |
e2c953b6 | 9579 | |
c5059423 AM |
9580 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
9581 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 9582 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 9583 | |
c5059423 | 9584 | int |
a2369ed3 | 9585 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 9586 | { |
e2c953b6 | 9587 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 9588 | { |
02071907 | 9589 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 9590 | |
02071907 | 9591 | shift_mask = ~0; |
c5059423 AM |
9592 | shift_mask <<= INTVAL (shiftop); |
9593 | c = INTVAL (andop); | |
9594 | ||
c1207243 | 9595 | /* Find the least significant one bit. */ |
c5059423 AM |
9596 | lsb = c & -c; |
9597 | ||
9598 | /* It must be covered by the shift mask. | |
a4f6c312 | 9599 | This test also rejects c == 0. */ |
c5059423 AM |
9600 | if ((lsb & shift_mask) == 0) |
9601 | return 0; | |
9602 | ||
9603 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
9604 | return c == -lsb && lsb != 1; | |
9605 | } | |
9606 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9607 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9608 | { | |
02071907 | 9609 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
9610 | |
9611 | low = CONST_DOUBLE_LOW (andop); | |
9612 | ||
9613 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9614 | { | |
02071907 | 9615 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
9616 | |
9617 | high = CONST_DOUBLE_HIGH (andop); | |
9618 | ||
9619 | if (low == 0) | |
9620 | { | |
02071907 | 9621 | shift_mask_high = ~0; |
c5059423 AM |
9622 | if (INTVAL (shiftop) > 32) |
9623 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9624 | ||
9625 | lsb = high & -high; | |
9626 | ||
9627 | if ((lsb & shift_mask_high) == 0) | |
9628 | return 0; | |
9629 | ||
9630 | return high == -lsb; | |
9631 | } | |
9632 | if (high != ~0) | |
9633 | return 0; | |
9634 | } | |
9635 | ||
02071907 | 9636 | shift_mask_low = ~0; |
c5059423 AM |
9637 | shift_mask_low <<= INTVAL (shiftop); |
9638 | ||
9639 | lsb = low & -low; | |
9640 | ||
9641 | if ((lsb & shift_mask_low) == 0) | |
9642 | return 0; | |
9643 | ||
9644 | return low == -lsb && lsb != 1; | |
9645 | } | |
e2c953b6 | 9646 | else |
c5059423 | 9647 | return 0; |
9878760c | 9648 | } |
35068b43 | 9649 | |
11ac38b2 DE |
9650 | /* Return 1 if operands will generate a valid arguments to rlwimi |
9651 | instruction for insert with right shift in 64-bit mode. The mask may | |
9652 | not start on the first bit or stop on the last bit because wrap-around | |
9653 | effects of instruction do not correspond to semantics of RTL insn. */ | |
9654 | ||
9655 | int | |
9656 | insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) | |
9657 | { | |
9658 | if (INTVAL (startop) < 64 | |
9659 | && INTVAL (startop) > 32 | |
9660 | && (INTVAL (sizeop) + INTVAL (startop) < 64) | |
9661 | && (INTVAL (sizeop) + INTVAL (startop) > 33) | |
9662 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96) | |
9663 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64) | |
9664 | && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) | |
9665 | return 1; | |
9666 | ||
9667 | return 0; | |
9668 | } | |
9669 | ||
35068b43 | 9670 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates |
90f81f99 | 9671 | for lfq and stfq insns iff the registers are hard registers. */ |
35068b43 RK |
9672 | |
9673 | int | |
a2369ed3 | 9674 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
9675 | { |
9676 | /* We might have been passed a SUBREG. */ | |
f676971a | 9677 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) |
35068b43 | 9678 | return 0; |
f676971a | 9679 | |
90f81f99 AP |
9680 | /* We might have been passed non floating point registers. */ |
9681 | if (!FP_REGNO_P (REGNO (reg1)) | |
9682 | || !FP_REGNO_P (REGNO (reg2))) | |
9683 | return 0; | |
35068b43 RK |
9684 | |
9685 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
9686 | } | |
9687 | ||
a4f6c312 SS |
9688 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
9689 | addr1 and addr2 must be in consecutive memory locations | |
9690 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
9691 | |
9692 | int | |
90f81f99 | 9693 | mems_ok_for_quad_peep (rtx mem1, rtx mem2) |
35068b43 | 9694 | { |
90f81f99 | 9695 | rtx addr1, addr2; |
bb8df8a6 EC |
9696 | unsigned int reg1, reg2; |
9697 | int offset1, offset2; | |
35068b43 | 9698 | |
90f81f99 AP |
9699 | /* The mems cannot be volatile. */ |
9700 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
9701 | return 0; | |
f676971a | 9702 | |
90f81f99 AP |
9703 | addr1 = XEXP (mem1, 0); |
9704 | addr2 = XEXP (mem2, 0); | |
9705 | ||
35068b43 RK |
9706 | /* Extract an offset (if used) from the first addr. */ |
9707 | if (GET_CODE (addr1) == PLUS) | |
9708 | { | |
9709 | /* If not a REG, return zero. */ | |
9710 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
9711 | return 0; | |
9712 | else | |
9713 | { | |
c4ad648e | 9714 | reg1 = REGNO (XEXP (addr1, 0)); |
35068b43 RK |
9715 | /* The offset must be constant! */ |
9716 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
c4ad648e AM |
9717 | return 0; |
9718 | offset1 = INTVAL (XEXP (addr1, 1)); | |
35068b43 RK |
9719 | } |
9720 | } | |
9721 | else if (GET_CODE (addr1) != REG) | |
9722 | return 0; | |
9723 | else | |
9724 | { | |
9725 | reg1 = REGNO (addr1); | |
9726 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
9727 | offset1 = 0; | |
9728 | } | |
9729 | ||
bb8df8a6 EC |
9730 | /* And now for the second addr. */ |
9731 | if (GET_CODE (addr2) == PLUS) | |
9732 | { | |
9733 | /* If not a REG, return zero. */ | |
9734 | if (GET_CODE (XEXP (addr2, 0)) != REG) | |
9735 | return 0; | |
9736 | else | |
9737 | { | |
9738 | reg2 = REGNO (XEXP (addr2, 0)); | |
9739 | /* The offset must be constant. */ | |
9740 | if (GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
9741 | return 0; | |
9742 | offset2 = INTVAL (XEXP (addr2, 1)); | |
9743 | } | |
9744 | } | |
9745 | else if (GET_CODE (addr2) != REG) | |
35068b43 | 9746 | return 0; |
bb8df8a6 EC |
9747 | else |
9748 | { | |
9749 | reg2 = REGNO (addr2); | |
9750 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
9751 | offset2 = 0; | |
9752 | } | |
35068b43 | 9753 | |
bb8df8a6 EC |
9754 | /* Both of these must have the same base register. */ |
9755 | if (reg1 != reg2) | |
35068b43 RK |
9756 | return 0; |
9757 | ||
9758 | /* The offset for the second addr must be 8 more than the first addr. */ | |
bb8df8a6 | 9759 | if (offset2 != offset1 + 8) |
35068b43 RK |
9760 | return 0; |
9761 | ||
9762 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
9763 | instructions. */ | |
9764 | return 1; | |
9765 | } | |
9878760c RK |
9766 | \f |
9767 | /* Return the register class of a scratch register needed to copy IN into | |
9768 | or out of a register in CLASS in MODE. If it can be done directly, | |
9769 | NO_REGS is returned. */ | |
9770 | ||
9771 | enum reg_class | |
3c4774e0 R |
9772 | rs6000_secondary_reload_class (enum reg_class class, |
9773 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
9774 | rtx in) | |
9878760c | 9775 | { |
5accd822 | 9776 | int regno; |
9878760c | 9777 | |
ab82a49f AP |
9778 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
9779 | #if TARGET_MACHO | |
c4ad648e | 9780 | && MACHOPIC_INDIRECT |
ab82a49f | 9781 | #endif |
c4ad648e | 9782 | )) |
46fad5b7 DJ |
9783 | { |
9784 | /* We cannot copy a symbolic operand directly into anything | |
c4ad648e AM |
9785 | other than BASE_REGS for TARGET_ELF. So indicate that a |
9786 | register from BASE_REGS is needed as an intermediate | |
9787 | register. | |
f676971a | 9788 | |
46fad5b7 DJ |
9789 | On Darwin, pic addresses require a load from memory, which |
9790 | needs a base register. */ | |
9791 | if (class != BASE_REGS | |
c4ad648e AM |
9792 | && (GET_CODE (in) == SYMBOL_REF |
9793 | || GET_CODE (in) == HIGH | |
9794 | || GET_CODE (in) == LABEL_REF | |
9795 | || GET_CODE (in) == CONST)) | |
9796 | return BASE_REGS; | |
46fad5b7 | 9797 | } |
e7b7998a | 9798 | |
5accd822 DE |
9799 | if (GET_CODE (in) == REG) |
9800 | { | |
9801 | regno = REGNO (in); | |
9802 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9803 | { | |
9804 | regno = true_regnum (in); | |
9805 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9806 | regno = -1; | |
9807 | } | |
9808 | } | |
9809 | else if (GET_CODE (in) == SUBREG) | |
9810 | { | |
9811 | regno = true_regnum (in); | |
9812 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9813 | regno = -1; | |
9814 | } | |
9815 | else | |
9816 | regno = -1; | |
9817 | ||
9878760c RK |
9818 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
9819 | into anything. */ | |
9820 | if (class == GENERAL_REGS || class == BASE_REGS | |
9821 | || (regno >= 0 && INT_REGNO_P (regno))) | |
9822 | return NO_REGS; | |
9823 | ||
9824 | /* Constants, memory, and FP registers can go into FP registers. */ | |
9825 | if ((regno == -1 || FP_REGNO_P (regno)) | |
9826 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
9827 | return NO_REGS; | |
9828 | ||
0ac081f6 AH |
9829 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
9830 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
9831 | && class == ALTIVEC_REGS) | |
9832 | return NO_REGS; | |
9833 | ||
9878760c RK |
9834 | /* We can copy among the CR registers. */ |
9835 | if ((class == CR_REGS || class == CR0_REGS) | |
9836 | && regno >= 0 && CR_REGNO_P (regno)) | |
9837 | return NO_REGS; | |
9838 | ||
9839 | /* Otherwise, we need GENERAL_REGS. */ | |
9840 | return GENERAL_REGS; | |
9841 | } | |
9842 | \f | |
9843 | /* Given a comparison operation, return the bit number in CCR to test. We | |
f676971a | 9844 | know this is a valid comparison. |
9878760c RK |
9845 | |
9846 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
9847 | used instead of %C, so the bits will be in different places. | |
9848 | ||
b4ac57ab | 9849 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
9850 | |
9851 | int | |
a2369ed3 | 9852 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
9853 | { |
9854 | enum rtx_code code = GET_CODE (op); | |
9855 | enum machine_mode cc_mode; | |
9856 | int cc_regnum; | |
9857 | int base_bit; | |
9ebbca7d | 9858 | rtx reg; |
9878760c | 9859 | |
ec8e098d | 9860 | if (!COMPARISON_P (op)) |
9878760c RK |
9861 | return -1; |
9862 | ||
9ebbca7d GK |
9863 | reg = XEXP (op, 0); |
9864 | ||
37409796 | 9865 | gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg))); |
9ebbca7d GK |
9866 | |
9867 | cc_mode = GET_MODE (reg); | |
9868 | cc_regnum = REGNO (reg); | |
9869 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 9870 | |
39a10a29 | 9871 | validate_condition_mode (code, cc_mode); |
c5defebb | 9872 | |
b7053a3f GK |
9873 | /* When generating a sCOND operation, only positive conditions are |
9874 | allowed. */ | |
37409796 NS |
9875 | gcc_assert (!scc_p |
9876 | || code == EQ || code == GT || code == LT || code == UNORDERED | |
9877 | || code == GTU || code == LTU); | |
f676971a | 9878 | |
9878760c RK |
9879 | switch (code) |
9880 | { | |
9881 | case NE: | |
9882 | return scc_p ? base_bit + 3 : base_bit + 2; | |
9883 | case EQ: | |
9884 | return base_bit + 2; | |
1c882ea4 | 9885 | case GT: case GTU: case UNLE: |
9878760c | 9886 | return base_bit + 1; |
1c882ea4 | 9887 | case LT: case LTU: case UNGE: |
9878760c | 9888 | return base_bit; |
1c882ea4 GK |
9889 | case ORDERED: case UNORDERED: |
9890 | return base_bit + 3; | |
9878760c RK |
9891 | |
9892 | case GE: case GEU: | |
39a10a29 | 9893 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
9894 | unordered position. So test that bit. For integer, this is ! LT |
9895 | unless this is an scc insn. */ | |
39a10a29 | 9896 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
9897 | |
9898 | case LE: case LEU: | |
39a10a29 | 9899 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 9900 | |
9878760c | 9901 | default: |
37409796 | 9902 | gcc_unreachable (); |
9878760c RK |
9903 | } |
9904 | } | |
1ff7789b | 9905 | \f |
8d30c4ee | 9906 | /* Return the GOT register. */ |
1ff7789b | 9907 | |
9390387d | 9908 | rtx |
a2369ed3 | 9909 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 9910 | { |
a4f6c312 SS |
9911 | /* The second flow pass currently (June 1999) can't update |
9912 | regs_ever_live without disturbing other parts of the compiler, so | |
9913 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
9914 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
9915 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 9916 | |
8d30c4ee | 9917 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 9918 | |
1ff7789b MM |
9919 | return pic_offset_table_rtx; |
9920 | } | |
a7df97e6 | 9921 | \f |
e2500fed GK |
9922 | /* Function to init struct machine_function. |
9923 | This will be called, via a pointer variable, | |
9924 | from push_function_context. */ | |
a7df97e6 | 9925 | |
e2500fed | 9926 | static struct machine_function * |
863d938c | 9927 | rs6000_init_machine_status (void) |
a7df97e6 | 9928 | { |
e2500fed | 9929 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 9930 | } |
9878760c | 9931 | \f |
0ba1b2ff AM |
9932 | /* These macros test for integers and extract the low-order bits. */ |
9933 | #define INT_P(X) \ | |
9934 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
9935 | && GET_MODE (X) == VOIDmode) | |
9936 | ||
9937 | #define INT_LOWPART(X) \ | |
9938 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
9939 | ||
9940 | int | |
a2369ed3 | 9941 | extract_MB (rtx op) |
0ba1b2ff AM |
9942 | { |
9943 | int i; | |
9944 | unsigned long val = INT_LOWPART (op); | |
9945 | ||
9946 | /* If the high bit is zero, the value is the first 1 bit we find | |
9947 | from the left. */ | |
9948 | if ((val & 0x80000000) == 0) | |
9949 | { | |
37409796 | 9950 | gcc_assert (val & 0xffffffff); |
0ba1b2ff AM |
9951 | |
9952 | i = 1; | |
9953 | while (((val <<= 1) & 0x80000000) == 0) | |
9954 | ++i; | |
9955 | return i; | |
9956 | } | |
9957 | ||
9958 | /* If the high bit is set and the low bit is not, or the mask is all | |
9959 | 1's, the value is zero. */ | |
9960 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9961 | return 0; | |
9962 | ||
9963 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9964 | from the right. */ | |
9965 | i = 31; | |
9966 | while (((val >>= 1) & 1) != 0) | |
9967 | --i; | |
9968 | ||
9969 | return i; | |
9970 | } | |
9971 | ||
9972 | int | |
a2369ed3 | 9973 | extract_ME (rtx op) |
0ba1b2ff AM |
9974 | { |
9975 | int i; | |
9976 | unsigned long val = INT_LOWPART (op); | |
9977 | ||
9978 | /* If the low bit is zero, the value is the first 1 bit we find from | |
9979 | the right. */ | |
9980 | if ((val & 1) == 0) | |
9981 | { | |
37409796 | 9982 | gcc_assert (val & 0xffffffff); |
0ba1b2ff AM |
9983 | |
9984 | i = 30; | |
9985 | while (((val >>= 1) & 1) == 0) | |
9986 | --i; | |
9987 | ||
9988 | return i; | |
9989 | } | |
9990 | ||
9991 | /* If the low bit is set and the high bit is not, or the mask is all | |
9992 | 1's, the value is 31. */ | |
9993 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9994 | return 31; | |
9995 | ||
9996 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9997 | from the left. */ | |
9998 | i = 0; | |
9999 | while (((val <<= 1) & 0x80000000) != 0) | |
10000 | ++i; | |
10001 | ||
10002 | return i; | |
10003 | } | |
10004 | ||
c4501e62 JJ |
10005 | /* Locate some local-dynamic symbol still in use by this function |
10006 | so that we can print its name in some tls_ld pattern. */ | |
10007 | ||
10008 | static const char * | |
863d938c | 10009 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
10010 | { |
10011 | rtx insn; | |
10012 | ||
10013 | if (cfun->machine->some_ld_name) | |
10014 | return cfun->machine->some_ld_name; | |
10015 | ||
10016 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
10017 | if (INSN_P (insn) | |
10018 | && for_each_rtx (&PATTERN (insn), | |
10019 | rs6000_get_some_local_dynamic_name_1, 0)) | |
10020 | return cfun->machine->some_ld_name; | |
10021 | ||
37409796 | 10022 | gcc_unreachable (); |
c4501e62 JJ |
10023 | } |
10024 | ||
10025 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
10026 | ||
10027 | static int | |
a2369ed3 | 10028 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
10029 | { |
10030 | rtx x = *px; | |
10031 | ||
10032 | if (GET_CODE (x) == SYMBOL_REF) | |
10033 | { | |
10034 | const char *str = XSTR (x, 0); | |
10035 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
10036 | { | |
10037 | cfun->machine->some_ld_name = str; | |
10038 | return 1; | |
10039 | } | |
10040 | } | |
10041 | ||
10042 | return 0; | |
10043 | } | |
10044 | ||
85b776df AM |
10045 | /* Write out a function code label. */ |
10046 | ||
10047 | void | |
10048 | rs6000_output_function_entry (FILE *file, const char *fname) | |
10049 | { | |
10050 | if (fname[0] != '.') | |
10051 | { | |
10052 | switch (DEFAULT_ABI) | |
10053 | { | |
10054 | default: | |
37409796 | 10055 | gcc_unreachable (); |
85b776df AM |
10056 | |
10057 | case ABI_AIX: | |
10058 | if (DOT_SYMBOLS) | |
10059 | putc ('.', file); | |
10060 | else | |
10061 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); | |
10062 | break; | |
10063 | ||
10064 | case ABI_V4: | |
10065 | case ABI_DARWIN: | |
10066 | break; | |
10067 | } | |
10068 | } | |
10069 | if (TARGET_AIX) | |
10070 | RS6000_OUTPUT_BASENAME (file, fname); | |
10071 | else | |
10072 | assemble_name (file, fname); | |
10073 | } | |
10074 | ||
9878760c RK |
10075 | /* Print an operand. Recognize special options, documented below. */ |
10076 | ||
38c1f2d7 | 10077 | #if TARGET_ELF |
d9407988 | 10078 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 10079 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
10080 | #else |
10081 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 10082 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
10083 | #endif |
10084 | ||
9878760c | 10085 | void |
a2369ed3 | 10086 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
10087 | { |
10088 | int i; | |
a260abc9 | 10089 | HOST_WIDE_INT val; |
0ba1b2ff | 10090 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
10091 | |
10092 | switch (code) | |
10093 | { | |
a8b3aeda | 10094 | case '.': |
a85d226b RK |
10095 | /* Write out an instruction after the call which may be replaced |
10096 | with glue code by the loader. This depends on the AIX version. */ | |
10097 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
10098 | return; |
10099 | ||
81eace42 GK |
10100 | /* %a is output_address. */ |
10101 | ||
9854d9ed RK |
10102 | case 'A': |
10103 | /* If X is a constant integer whose low-order 5 bits are zero, | |
10104 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 10105 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 10106 | writes a trash instruction. */ |
9854d9ed | 10107 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 10108 | putc ('l', file); |
9854d9ed | 10109 | else |
76229ac8 | 10110 | putc ('r', file); |
9854d9ed RK |
10111 | return; |
10112 | ||
10113 | case 'b': | |
e2c953b6 DE |
10114 | /* If constant, low-order 16 bits of constant, unsigned. |
10115 | Otherwise, write normally. */ | |
10116 | if (INT_P (x)) | |
10117 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
10118 | else | |
10119 | print_operand (file, x, 0); | |
cad12a8d RK |
10120 | return; |
10121 | ||
a260abc9 DE |
10122 | case 'B': |
10123 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
10124 | for 64-bit mask direction. */ | |
9390387d | 10125 | putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 10126 | return; |
a260abc9 | 10127 | |
81eace42 GK |
10128 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
10129 | output_operand. */ | |
10130 | ||
423c1189 AH |
10131 | case 'c': |
10132 | /* X is a CR register. Print the number of the GT bit of the CR. */ | |
10133 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10134 | output_operand_lossage ("invalid %%E value"); | |
10135 | else | |
10136 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); | |
10137 | return; | |
10138 | ||
10139 | case 'D': | |
6b1fedc3 | 10140 | /* Like 'J' but get to the EQ bit. */ |
37409796 | 10141 | gcc_assert (GET_CODE (x) == REG); |
423c1189 | 10142 | |
6b1fedc3 AH |
10143 | /* Bit 1 is EQ bit. */ |
10144 | i = 4 * (REGNO (x) - CR0_REGNO) + 2; | |
423c1189 | 10145 | |
64022b5d | 10146 | fprintf (file, "%d", i); |
423c1189 AH |
10147 | return; |
10148 | ||
9854d9ed | 10149 | case 'E': |
39a10a29 | 10150 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
10151 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
10152 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 10153 | else |
39a10a29 | 10154 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 10155 | return; |
9854d9ed RK |
10156 | |
10157 | case 'f': | |
10158 | /* X is a CR register. Print the shift count needed to move it | |
10159 | to the high-order four bits. */ | |
10160 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10161 | output_operand_lossage ("invalid %%f value"); | |
10162 | else | |
9ebbca7d | 10163 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
10164 | return; |
10165 | ||
10166 | case 'F': | |
10167 | /* Similar, but print the count for the rotate in the opposite | |
10168 | direction. */ | |
10169 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10170 | output_operand_lossage ("invalid %%F value"); | |
10171 | else | |
9ebbca7d | 10172 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
10173 | return; |
10174 | ||
10175 | case 'G': | |
10176 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 10177 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
10178 | if (GET_CODE (x) != CONST_INT) |
10179 | output_operand_lossage ("invalid %%G value"); | |
10180 | else if (INTVAL (x) >= 0) | |
76229ac8 | 10181 | putc ('z', file); |
9854d9ed | 10182 | else |
76229ac8 | 10183 | putc ('m', file); |
9854d9ed | 10184 | return; |
e2c953b6 | 10185 | |
9878760c | 10186 | case 'h': |
a4f6c312 SS |
10187 | /* If constant, output low-order five bits. Otherwise, write |
10188 | normally. */ | |
9878760c | 10189 | if (INT_P (x)) |
5f59ecb7 | 10190 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
10191 | else |
10192 | print_operand (file, x, 0); | |
10193 | return; | |
10194 | ||
64305719 | 10195 | case 'H': |
a4f6c312 SS |
10196 | /* If constant, output low-order six bits. Otherwise, write |
10197 | normally. */ | |
64305719 | 10198 | if (INT_P (x)) |
5f59ecb7 | 10199 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
10200 | else |
10201 | print_operand (file, x, 0); | |
10202 | return; | |
10203 | ||
9854d9ed RK |
10204 | case 'I': |
10205 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 10206 | if (INT_P (x)) |
76229ac8 | 10207 | putc ('i', file); |
9878760c RK |
10208 | return; |
10209 | ||
9854d9ed RK |
10210 | case 'j': |
10211 | /* Write the bit number in CCR for jump. */ | |
10212 | i = ccr_bit (x, 0); | |
10213 | if (i == -1) | |
10214 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 10215 | else |
9854d9ed | 10216 | fprintf (file, "%d", i); |
9878760c RK |
10217 | return; |
10218 | ||
9854d9ed RK |
10219 | case 'J': |
10220 | /* Similar, but add one for shift count in rlinm for scc and pass | |
10221 | scc flag to `ccr_bit'. */ | |
10222 | i = ccr_bit (x, 1); | |
10223 | if (i == -1) | |
10224 | output_operand_lossage ("invalid %%J code"); | |
10225 | else | |
a0466a68 RK |
10226 | /* If we want bit 31, write a shift count of zero, not 32. */ |
10227 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
10228 | return; |
10229 | ||
9854d9ed RK |
10230 | case 'k': |
10231 | /* X must be a constant. Write the 1's complement of the | |
10232 | constant. */ | |
9878760c | 10233 | if (! INT_P (x)) |
9854d9ed | 10234 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
10235 | else |
10236 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
10237 | return; |
10238 | ||
81eace42 | 10239 | case 'K': |
9ebbca7d GK |
10240 | /* X must be a symbolic constant on ELF. Write an |
10241 | expression suitable for an 'addi' that adds in the low 16 | |
10242 | bits of the MEM. */ | |
10243 | if (GET_CODE (x) != CONST) | |
10244 | { | |
10245 | print_operand_address (file, x); | |
10246 | fputs ("@l", file); | |
10247 | } | |
10248 | else | |
10249 | { | |
10250 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
10251 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
10252 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
10253 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 10254 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
10255 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
10256 | fputs ("@l", file); | |
ed8d2920 MM |
10257 | /* For GNU as, there must be a non-alphanumeric character |
10258 | between 'l' and the number. The '-' is added by | |
10259 | print_operand() already. */ | |
10260 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
10261 | fputs ("+", file); | |
9ebbca7d GK |
10262 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
10263 | } | |
81eace42 GK |
10264 | return; |
10265 | ||
10266 | /* %l is output_asm_label. */ | |
9ebbca7d | 10267 | |
9854d9ed RK |
10268 | case 'L': |
10269 | /* Write second word of DImode or DFmode reference. Works on register | |
10270 | or non-indexed memory only. */ | |
10271 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10272 | fputs (reg_names[REGNO (x) + 1], file); |
9854d9ed RK |
10273 | else if (GET_CODE (x) == MEM) |
10274 | { | |
10275 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 10276 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
10277 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
10278 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
10279 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
10280 | UNITS_PER_WORD)); | |
9854d9ed | 10281 | else |
d7624dc0 RK |
10282 | output_address (XEXP (adjust_address_nv (x, SImode, |
10283 | UNITS_PER_WORD), | |
10284 | 0)); | |
ed8908e7 | 10285 | |
ba5e43aa | 10286 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10287 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10288 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 10289 | } |
9878760c | 10290 | return; |
f676971a | 10291 | |
9878760c RK |
10292 | case 'm': |
10293 | /* MB value for a mask operand. */ | |
b1765bde | 10294 | if (! mask_operand (x, SImode)) |
9878760c RK |
10295 | output_operand_lossage ("invalid %%m value"); |
10296 | ||
0ba1b2ff | 10297 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
10298 | return; |
10299 | ||
10300 | case 'M': | |
10301 | /* ME value for a mask operand. */ | |
b1765bde | 10302 | if (! mask_operand (x, SImode)) |
a260abc9 | 10303 | output_operand_lossage ("invalid %%M value"); |
9878760c | 10304 | |
0ba1b2ff | 10305 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
10306 | return; |
10307 | ||
81eace42 GK |
10308 | /* %n outputs the negative of its operand. */ |
10309 | ||
9878760c RK |
10310 | case 'N': |
10311 | /* Write the number of elements in the vector times 4. */ | |
10312 | if (GET_CODE (x) != PARALLEL) | |
10313 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
10314 | else |
10315 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
10316 | return; |
10317 | ||
10318 | case 'O': | |
10319 | /* Similar, but subtract 1 first. */ | |
10320 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 10321 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
10322 | else |
10323 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
10324 | return; |
10325 | ||
9854d9ed RK |
10326 | case 'p': |
10327 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
10328 | if (! INT_P (x) | |
2bfcf297 | 10329 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
10330 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
10331 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
10332 | else |
10333 | fprintf (file, "%d", i); | |
9854d9ed RK |
10334 | return; |
10335 | ||
9878760c RK |
10336 | case 'P': |
10337 | /* The operand must be an indirect memory reference. The result | |
8bb418a3 | 10338 | is the register name. */ |
9878760c RK |
10339 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
10340 | || REGNO (XEXP (x, 0)) >= 32) | |
10341 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 | 10342 | else |
fb5c67a7 | 10343 | fputs (reg_names[REGNO (XEXP (x, 0))], file); |
9878760c RK |
10344 | return; |
10345 | ||
dfbdccdb GK |
10346 | case 'q': |
10347 | /* This outputs the logical code corresponding to a boolean | |
10348 | expression. The expression may have one or both operands | |
39a10a29 | 10349 | negated (if one, only the first one). For condition register |
c4ad648e AM |
10350 | logical operations, it will also treat the negated |
10351 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 10352 | { |
63bc1d05 | 10353 | const char *const *t = 0; |
dfbdccdb GK |
10354 | const char *s; |
10355 | enum rtx_code code = GET_CODE (x); | |
10356 | static const char * const tbl[3][3] = { | |
10357 | { "and", "andc", "nor" }, | |
10358 | { "or", "orc", "nand" }, | |
10359 | { "xor", "eqv", "xor" } }; | |
10360 | ||
10361 | if (code == AND) | |
10362 | t = tbl[0]; | |
10363 | else if (code == IOR) | |
10364 | t = tbl[1]; | |
10365 | else if (code == XOR) | |
10366 | t = tbl[2]; | |
10367 | else | |
10368 | output_operand_lossage ("invalid %%q value"); | |
10369 | ||
10370 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
10371 | s = t[0]; | |
10372 | else | |
10373 | { | |
10374 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
10375 | s = t[2]; | |
10376 | else | |
10377 | s = t[1]; | |
10378 | } | |
f676971a | 10379 | |
dfbdccdb GK |
10380 | fputs (s, file); |
10381 | } | |
10382 | return; | |
10383 | ||
2c4a9cff DE |
10384 | case 'Q': |
10385 | if (TARGET_MFCRF) | |
3b6ce0af | 10386 | fputc (',', file); |
5efb1046 | 10387 | /* FALLTHRU */ |
2c4a9cff DE |
10388 | else |
10389 | return; | |
10390 | ||
9854d9ed RK |
10391 | case 'R': |
10392 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
10393 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10394 | output_operand_lossage ("invalid %%R value"); | |
10395 | else | |
9ebbca7d | 10396 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 10397 | return; |
9854d9ed RK |
10398 | |
10399 | case 's': | |
10400 | /* Low 5 bits of 32 - value */ | |
10401 | if (! INT_P (x)) | |
10402 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
10403 | else |
10404 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 10405 | return; |
9854d9ed | 10406 | |
a260abc9 | 10407 | case 'S': |
0ba1b2ff | 10408 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
10409 | CONST_INT 32-bit mask is considered sign-extended so any |
10410 | transition must occur within the CONST_INT, not on the boundary. */ | |
1990cd79 | 10411 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
10412 | output_operand_lossage ("invalid %%S value"); |
10413 | ||
0ba1b2ff | 10414 | uval = INT_LOWPART (x); |
a260abc9 | 10415 | |
0ba1b2ff | 10416 | if (uval & 1) /* Clear Left */ |
a260abc9 | 10417 | { |
f099d360 GK |
10418 | #if HOST_BITS_PER_WIDE_INT > 64 |
10419 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
10420 | #endif | |
0ba1b2ff | 10421 | i = 64; |
a260abc9 | 10422 | } |
0ba1b2ff | 10423 | else /* Clear Right */ |
a260abc9 | 10424 | { |
0ba1b2ff | 10425 | uval = ~uval; |
f099d360 GK |
10426 | #if HOST_BITS_PER_WIDE_INT > 64 |
10427 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
10428 | #endif | |
0ba1b2ff | 10429 | i = 63; |
a260abc9 | 10430 | } |
0ba1b2ff AM |
10431 | while (uval != 0) |
10432 | --i, uval >>= 1; | |
37409796 | 10433 | gcc_assert (i >= 0); |
0ba1b2ff AM |
10434 | fprintf (file, "%d", i); |
10435 | return; | |
a260abc9 | 10436 | |
a3170dc6 AH |
10437 | case 't': |
10438 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
37409796 | 10439 | gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode); |
a3170dc6 AH |
10440 | |
10441 | /* Bit 3 is OV bit. */ | |
10442 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
10443 | ||
10444 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
10445 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
10446 | return; | |
10447 | ||
cccf3bdc DE |
10448 | case 'T': |
10449 | /* Print the symbolic name of a branch target register. */ | |
10450 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
10451 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
10452 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 10453 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
10454 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
10455 | else | |
10456 | fputs ("ctr", file); | |
10457 | return; | |
10458 | ||
9854d9ed | 10459 | case 'u': |
802a0058 | 10460 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
10461 | if (! INT_P (x)) |
10462 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 | 10463 | else |
f676971a | 10464 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
e2c953b6 | 10465 | (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
10466 | return; |
10467 | ||
802a0058 MM |
10468 | case 'v': |
10469 | /* High-order 16 bits of constant for use in signed operand. */ | |
10470 | if (! INT_P (x)) | |
10471 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 10472 | else |
134c32f6 DE |
10473 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
10474 | (INT_LOWPART (x) >> 16) & 0xffff); | |
10475 | return; | |
802a0058 | 10476 | |
9854d9ed RK |
10477 | case 'U': |
10478 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
10479 | if (GET_CODE (x) == MEM | |
10480 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
10481 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 10482 | putc ('u', file); |
9854d9ed | 10483 | return; |
9878760c | 10484 | |
e0cd0770 JC |
10485 | case 'V': |
10486 | /* Print the trap code for this operand. */ | |
10487 | switch (GET_CODE (x)) | |
10488 | { | |
10489 | case EQ: | |
10490 | fputs ("eq", file); /* 4 */ | |
10491 | break; | |
10492 | case NE: | |
10493 | fputs ("ne", file); /* 24 */ | |
10494 | break; | |
10495 | case LT: | |
10496 | fputs ("lt", file); /* 16 */ | |
10497 | break; | |
10498 | case LE: | |
10499 | fputs ("le", file); /* 20 */ | |
10500 | break; | |
10501 | case GT: | |
10502 | fputs ("gt", file); /* 8 */ | |
10503 | break; | |
10504 | case GE: | |
10505 | fputs ("ge", file); /* 12 */ | |
10506 | break; | |
10507 | case LTU: | |
10508 | fputs ("llt", file); /* 2 */ | |
10509 | break; | |
10510 | case LEU: | |
10511 | fputs ("lle", file); /* 6 */ | |
10512 | break; | |
10513 | case GTU: | |
10514 | fputs ("lgt", file); /* 1 */ | |
10515 | break; | |
10516 | case GEU: | |
10517 | fputs ("lge", file); /* 5 */ | |
10518 | break; | |
10519 | default: | |
37409796 | 10520 | gcc_unreachable (); |
e0cd0770 JC |
10521 | } |
10522 | break; | |
10523 | ||
9854d9ed RK |
10524 | case 'w': |
10525 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
10526 | normally. */ | |
10527 | if (INT_P (x)) | |
f676971a | 10528 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5f59ecb7 | 10529 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); |
9854d9ed RK |
10530 | else |
10531 | print_operand (file, x, 0); | |
9878760c RK |
10532 | return; |
10533 | ||
9854d9ed | 10534 | case 'W': |
e2c953b6 | 10535 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
10536 | val = (GET_CODE (x) == CONST_INT |
10537 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
10538 | ||
10539 | if (val < 0) | |
10540 | i = -1; | |
9854d9ed | 10541 | else |
e2c953b6 DE |
10542 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
10543 | if ((val <<= 1) < 0) | |
10544 | break; | |
10545 | ||
10546 | #if HOST_BITS_PER_WIDE_INT == 32 | |
10547 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
10548 | i += 32; /* zero-extend high-part was all 0's */ | |
10549 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
10550 | { | |
10551 | val = CONST_DOUBLE_LOW (x); | |
10552 | ||
37409796 NS |
10553 | gcc_assert (val); |
10554 | if (val < 0) | |
e2c953b6 DE |
10555 | --i; |
10556 | else | |
10557 | for ( ; i < 64; i++) | |
10558 | if ((val <<= 1) < 0) | |
10559 | break; | |
10560 | } | |
10561 | #endif | |
10562 | ||
10563 | fprintf (file, "%d", i + 1); | |
9854d9ed | 10564 | return; |
9878760c | 10565 | |
9854d9ed RK |
10566 | case 'X': |
10567 | if (GET_CODE (x) == MEM | |
4d588c14 | 10568 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 10569 | putc ('x', file); |
9854d9ed | 10570 | return; |
9878760c | 10571 | |
9854d9ed RK |
10572 | case 'Y': |
10573 | /* Like 'L', for third word of TImode */ | |
10574 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10575 | fputs (reg_names[REGNO (x) + 2], file); |
9854d9ed | 10576 | else if (GET_CODE (x) == MEM) |
9878760c | 10577 | { |
9854d9ed RK |
10578 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
10579 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10580 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 10581 | else |
d7624dc0 | 10582 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 10583 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10584 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10585 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
10586 | } |
10587 | return; | |
f676971a | 10588 | |
9878760c | 10589 | case 'z': |
b4ac57ab RS |
10590 | /* X is a SYMBOL_REF. Write out the name preceded by a |
10591 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
10592 | names. If we are configured for System V (or the embedded ABI) on |
10593 | the PowerPC, do not emit the period, since those systems do not use | |
10594 | TOCs and the like. */ | |
37409796 | 10595 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
9878760c | 10596 | |
c4ad648e AM |
10597 | /* Mark the decl as referenced so that cgraph will output the |
10598 | function. */ | |
9bf6462a | 10599 | if (SYMBOL_REF_DECL (x)) |
c4ad648e | 10600 | mark_decl_referenced (SYMBOL_REF_DECL (x)); |
9bf6462a | 10601 | |
85b776df | 10602 | /* For macho, check to see if we need a stub. */ |
f9da97f0 AP |
10603 | if (TARGET_MACHO) |
10604 | { | |
10605 | const char *name = XSTR (x, 0); | |
a031e781 | 10606 | #if TARGET_MACHO |
3b48085e | 10607 | if (MACHOPIC_INDIRECT |
11abc112 MM |
10608 | && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION) |
10609 | name = machopic_indirection_name (x, /*stub_p=*/true); | |
f9da97f0 AP |
10610 | #endif |
10611 | assemble_name (file, name); | |
10612 | } | |
85b776df | 10613 | else if (!DOT_SYMBOLS) |
9739c90c | 10614 | assemble_name (file, XSTR (x, 0)); |
85b776df AM |
10615 | else |
10616 | rs6000_output_function_entry (file, XSTR (x, 0)); | |
9878760c RK |
10617 | return; |
10618 | ||
9854d9ed RK |
10619 | case 'Z': |
10620 | /* Like 'L', for last word of TImode. */ | |
10621 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10622 | fputs (reg_names[REGNO (x) + 3], file); |
9854d9ed RK |
10623 | else if (GET_CODE (x) == MEM) |
10624 | { | |
10625 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
10626 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10627 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 10628 | else |
d7624dc0 | 10629 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 10630 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10631 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10632 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 10633 | } |
5c23c401 | 10634 | return; |
0ac081f6 | 10635 | |
a3170dc6 | 10636 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
10637 | case 'y': |
10638 | { | |
10639 | rtx tmp; | |
10640 | ||
37409796 | 10641 | gcc_assert (GET_CODE (x) == MEM); |
0ac081f6 AH |
10642 | |
10643 | tmp = XEXP (x, 0); | |
10644 | ||
993f19a8 | 10645 | if (TARGET_E500) |
a3170dc6 AH |
10646 | { |
10647 | /* Handle [reg]. */ | |
10648 | if (GET_CODE (tmp) == REG) | |
10649 | { | |
10650 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
10651 | break; | |
10652 | } | |
10653 | /* Handle [reg+UIMM]. */ | |
10654 | else if (GET_CODE (tmp) == PLUS && | |
10655 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
10656 | { | |
10657 | int x; | |
10658 | ||
37409796 | 10659 | gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG); |
a3170dc6 AH |
10660 | |
10661 | x = INTVAL (XEXP (tmp, 1)); | |
10662 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
10663 | break; | |
10664 | } | |
10665 | ||
10666 | /* Fall through. Must be [reg+reg]. */ | |
10667 | } | |
850e8d3d DN |
10668 | if (TARGET_ALTIVEC |
10669 | && GET_CODE (tmp) == AND | |
10670 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT | |
10671 | && INTVAL (XEXP (tmp, 1)) == -16) | |
10672 | tmp = XEXP (tmp, 0); | |
0ac081f6 | 10673 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 10674 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
37409796 | 10675 | else |
0ac081f6 | 10676 | { |
37409796 | 10677 | gcc_assert (GET_CODE (tmp) == PLUS |
9024f4b8 AM |
10678 | && REG_P (XEXP (tmp, 0)) |
10679 | && REG_P (XEXP (tmp, 1))); | |
bb8df8a6 | 10680 | |
0ac081f6 AH |
10681 | if (REGNO (XEXP (tmp, 0)) == 0) |
10682 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
10683 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
10684 | else | |
10685 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
10686 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
10687 | } | |
0ac081f6 AH |
10688 | break; |
10689 | } | |
f676971a | 10690 | |
9878760c RK |
10691 | case 0: |
10692 | if (GET_CODE (x) == REG) | |
10693 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
10694 | else if (GET_CODE (x) == MEM) | |
10695 | { | |
10696 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
10697 | know the width from the mode. */ | |
10698 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
10699 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
10700 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10701 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
10702 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
10703 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10704 | else |
a54d04b7 | 10705 | output_address (XEXP (x, 0)); |
9878760c RK |
10706 | } |
10707 | else | |
a54d04b7 | 10708 | output_addr_const (file, x); |
a85d226b | 10709 | return; |
9878760c | 10710 | |
c4501e62 JJ |
10711 | case '&': |
10712 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
10713 | return; | |
10714 | ||
9878760c RK |
10715 | default: |
10716 | output_operand_lossage ("invalid %%xn code"); | |
10717 | } | |
10718 | } | |
10719 | \f | |
10720 | /* Print the address of an operand. */ | |
10721 | ||
10722 | void | |
a2369ed3 | 10723 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
10724 | { |
10725 | if (GET_CODE (x) == REG) | |
4697a36c | 10726 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
10727 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
10728 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
10729 | { |
10730 | output_addr_const (file, x); | |
ba5e43aa | 10731 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10732 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10733 | reg_names[SMALL_DATA_REG]); | |
37409796 NS |
10734 | else |
10735 | gcc_assert (!TARGET_TOC); | |
9878760c RK |
10736 | } |
10737 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
10738 | { | |
9024f4b8 | 10739 | gcc_assert (REG_P (XEXP (x, 0))); |
9878760c | 10740 | if (REGNO (XEXP (x, 0)) == 0) |
4697a36c MM |
10741 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
10742 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 10743 | else |
4697a36c MM |
10744 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
10745 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
10746 | } |
10747 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
10748 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
10749 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
10750 | #if TARGET_ELF |
10751 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 10752 | && CONSTANT_P (XEXP (x, 1))) |
4697a36c MM |
10753 | { |
10754 | output_addr_const (file, XEXP (x, 1)); | |
10755 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10756 | } | |
c859cda6 DJ |
10757 | #endif |
10758 | #if TARGET_MACHO | |
10759 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 10760 | && CONSTANT_P (XEXP (x, 1))) |
c859cda6 DJ |
10761 | { |
10762 | fprintf (file, "lo16("); | |
10763 | output_addr_const (file, XEXP (x, 1)); | |
10764 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10765 | } | |
3cb999d8 | 10766 | #endif |
4d588c14 | 10767 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 10768 | { |
2bfcf297 | 10769 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 10770 | { |
2bfcf297 DB |
10771 | rtx contains_minus = XEXP (x, 1); |
10772 | rtx minus, symref; | |
10773 | const char *name; | |
f676971a | 10774 | |
9ebbca7d | 10775 | /* Find the (minus (sym) (toc)) buried in X, and temporarily |
a4f6c312 | 10776 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
10777 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
10778 | contains_minus = XEXP (contains_minus, 0); | |
10779 | ||
2bfcf297 DB |
10780 | minus = XEXP (contains_minus, 0); |
10781 | symref = XEXP (minus, 0); | |
10782 | XEXP (contains_minus, 0) = symref; | |
10783 | if (TARGET_ELF) | |
10784 | { | |
10785 | char *newname; | |
10786 | ||
10787 | name = XSTR (symref, 0); | |
10788 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
10789 | strcpy (newname, name); | |
10790 | strcat (newname, "@toc"); | |
10791 | XSTR (symref, 0) = newname; | |
10792 | } | |
10793 | output_addr_const (file, XEXP (x, 1)); | |
10794 | if (TARGET_ELF) | |
10795 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
10796 | XEXP (contains_minus, 0) = minus; |
10797 | } | |
10798 | else | |
10799 | output_addr_const (file, XEXP (x, 1)); | |
10800 | ||
10801 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
10802 | } | |
9878760c | 10803 | else |
37409796 | 10804 | gcc_unreachable (); |
9878760c RK |
10805 | } |
10806 | \f | |
88cad84b | 10807 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
10808 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
10809 | is defined. It also needs to handle DI-mode objects on 64-bit | |
10810 | targets. */ | |
10811 | ||
10812 | static bool | |
a2369ed3 | 10813 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 10814 | { |
f4f4921e | 10815 | #ifdef RELOCATABLE_NEEDS_FIXUP |
301d03af | 10816 | /* Special handling for SI values. */ |
84dcde01 | 10817 | if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p) |
301d03af | 10818 | { |
301d03af | 10819 | static int recurse = 0; |
f676971a | 10820 | |
301d03af RS |
10821 | /* For -mrelocatable, we mark all addresses that need to be fixed up |
10822 | in the .fixup section. */ | |
10823 | if (TARGET_RELOCATABLE | |
d6b5193b RS |
10824 | && in_section != toc_section |
10825 | && in_section != text_section | |
10826 | && unlikely_text_section_p (in_section) | |
301d03af RS |
10827 | && !recurse |
10828 | && GET_CODE (x) != CONST_INT | |
10829 | && GET_CODE (x) != CONST_DOUBLE | |
10830 | && CONSTANT_P (x)) | |
10831 | { | |
10832 | char buf[256]; | |
10833 | ||
10834 | recurse = 1; | |
10835 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
10836 | fixuplabelno++; | |
10837 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
10838 | fprintf (asm_out_file, "\t.long\t("); | |
10839 | output_addr_const (asm_out_file, x); | |
10840 | fprintf (asm_out_file, ")@fixup\n"); | |
10841 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
10842 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
10843 | fprintf (asm_out_file, "\t.long\t"); | |
10844 | assemble_name (asm_out_file, buf); | |
10845 | fprintf (asm_out_file, "\n\t.previous\n"); | |
10846 | recurse = 0; | |
10847 | return true; | |
10848 | } | |
10849 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
10850 | address into the address of the descriptor, not the function | |
10851 | itself. */ | |
10852 | else if (GET_CODE (x) == SYMBOL_REF | |
10853 | && XSTR (x, 0)[0] == '.' | |
10854 | && DEFAULT_ABI == ABI_AIX) | |
10855 | { | |
10856 | const char *name = XSTR (x, 0); | |
10857 | while (*name == '.') | |
10858 | name++; | |
10859 | ||
10860 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
10861 | return true; | |
10862 | } | |
10863 | } | |
f4f4921e | 10864 | #endif /* RELOCATABLE_NEEDS_FIXUP */ |
301d03af RS |
10865 | return default_assemble_integer (x, size, aligned_p); |
10866 | } | |
93638d7a AM |
10867 | |
10868 | #ifdef HAVE_GAS_HIDDEN | |
10869 | /* Emit an assembler directive to set symbol visibility for DECL to | |
10870 | VISIBILITY_TYPE. */ | |
10871 | ||
5add3202 | 10872 | static void |
a2369ed3 | 10873 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 10874 | { |
93638d7a AM |
10875 | /* Functions need to have their entry point symbol visibility set as |
10876 | well as their descriptor symbol visibility. */ | |
85b776df AM |
10877 | if (DEFAULT_ABI == ABI_AIX |
10878 | && DOT_SYMBOLS | |
10879 | && TREE_CODE (decl) == FUNCTION_DECL) | |
93638d7a | 10880 | { |
25fdb4dc | 10881 | static const char * const visibility_types[] = { |
c4ad648e | 10882 | NULL, "internal", "hidden", "protected" |
25fdb4dc RH |
10883 | }; |
10884 | ||
10885 | const char *name, *type; | |
93638d7a AM |
10886 | |
10887 | name = ((* targetm.strip_name_encoding) | |
10888 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 10889 | type = visibility_types[vis]; |
93638d7a | 10890 | |
25fdb4dc RH |
10891 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
10892 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 10893 | } |
25fdb4dc RH |
10894 | else |
10895 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
10896 | } |
10897 | #endif | |
301d03af | 10898 | \f |
39a10a29 | 10899 | enum rtx_code |
a2369ed3 | 10900 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
10901 | { |
10902 | /* Reversal of FP compares takes care -- an ordered compare | |
10903 | becomes an unordered compare and vice versa. */ | |
f676971a | 10904 | if (mode == CCFPmode |
bc9ec0e0 GK |
10905 | && (!flag_finite_math_only |
10906 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
10907 | || code == UNEQ || code == LTGT)) | |
bab6226b | 10908 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 10909 | else |
bab6226b | 10910 | return reverse_condition (code); |
39a10a29 GK |
10911 | } |
10912 | ||
39a10a29 GK |
10913 | /* Generate a compare for CODE. Return a brand-new rtx that |
10914 | represents the result of the compare. */ | |
a4f6c312 | 10915 | |
39a10a29 | 10916 | static rtx |
a2369ed3 | 10917 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
10918 | { |
10919 | enum machine_mode comp_mode; | |
10920 | rtx compare_result; | |
10921 | ||
10922 | if (rs6000_compare_fp_p) | |
10923 | comp_mode = CCFPmode; | |
10924 | else if (code == GTU || code == LTU | |
c4ad648e | 10925 | || code == GEU || code == LEU) |
39a10a29 | 10926 | comp_mode = CCUNSmode; |
60934f9c NS |
10927 | else if ((code == EQ || code == NE) |
10928 | && GET_CODE (rs6000_compare_op0) == SUBREG | |
10929 | && GET_CODE (rs6000_compare_op1) == SUBREG | |
10930 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0) | |
10931 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1)) | |
10932 | /* These are unsigned values, perhaps there will be a later | |
10933 | ordering compare that can be shared with this one. | |
10934 | Unfortunately we cannot detect the signedness of the operands | |
10935 | for non-subregs. */ | |
10936 | comp_mode = CCUNSmode; | |
39a10a29 GK |
10937 | else |
10938 | comp_mode = CCmode; | |
10939 | ||
10940 | /* First, the compare. */ | |
10941 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
10942 | |
10943 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
10944 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
10945 | && rs6000_compare_fp_p) | |
a3170dc6 | 10946 | { |
64022b5d | 10947 | rtx cmp, or_result, compare_result2; |
4d4cbc0e AH |
10948 | enum machine_mode op_mode = GET_MODE (rs6000_compare_op0); |
10949 | ||
10950 | if (op_mode == VOIDmode) | |
10951 | op_mode = GET_MODE (rs6000_compare_op1); | |
a3170dc6 | 10952 | |
423c1189 AH |
10953 | /* Note: The E500 comparison instructions set the GT bit (x + |
10954 | 1), on success. This explains the mess. */ | |
10955 | ||
a3170dc6 AH |
10956 | switch (code) |
10957 | { | |
423c1189 | 10958 | case EQ: case UNEQ: case NE: case LTGT: |
37409796 NS |
10959 | switch (op_mode) |
10960 | { | |
10961 | case SFmode: | |
10962 | cmp = flag_unsafe_math_optimizations | |
10963 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, | |
10964 | rs6000_compare_op1) | |
10965 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
10966 | rs6000_compare_op1); | |
10967 | break; | |
10968 | ||
10969 | case DFmode: | |
10970 | cmp = flag_unsafe_math_optimizations | |
10971 | ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, | |
10972 | rs6000_compare_op1) | |
10973 | : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, | |
10974 | rs6000_compare_op1); | |
10975 | break; | |
10976 | ||
10977 | default: | |
10978 | gcc_unreachable (); | |
10979 | } | |
a3170dc6 | 10980 | break; |
bb8df8a6 | 10981 | |
423c1189 | 10982 | case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: |
37409796 NS |
10983 | switch (op_mode) |
10984 | { | |
10985 | case SFmode: | |
10986 | cmp = flag_unsafe_math_optimizations | |
10987 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, | |
10988 | rs6000_compare_op1) | |
10989 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
10990 | rs6000_compare_op1); | |
10991 | break; | |
bb8df8a6 | 10992 | |
37409796 NS |
10993 | case DFmode: |
10994 | cmp = flag_unsafe_math_optimizations | |
10995 | ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, | |
10996 | rs6000_compare_op1) | |
10997 | : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, | |
10998 | rs6000_compare_op1); | |
10999 | break; | |
11000 | ||
11001 | default: | |
11002 | gcc_unreachable (); | |
11003 | } | |
a3170dc6 | 11004 | break; |
bb8df8a6 | 11005 | |
423c1189 | 11006 | case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: |
37409796 NS |
11007 | switch (op_mode) |
11008 | { | |
11009 | case SFmode: | |
11010 | cmp = flag_unsafe_math_optimizations | |
11011 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, | |
11012 | rs6000_compare_op1) | |
11013 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
11014 | rs6000_compare_op1); | |
11015 | break; | |
bb8df8a6 | 11016 | |
37409796 NS |
11017 | case DFmode: |
11018 | cmp = flag_unsafe_math_optimizations | |
11019 | ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, | |
11020 | rs6000_compare_op1) | |
11021 | : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, | |
11022 | rs6000_compare_op1); | |
11023 | break; | |
11024 | ||
11025 | default: | |
11026 | gcc_unreachable (); | |
11027 | } | |
a3170dc6 | 11028 | break; |
4d4cbc0e | 11029 | default: |
37409796 | 11030 | gcc_unreachable (); |
a3170dc6 AH |
11031 | } |
11032 | ||
11033 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
11034 | if (code == LE || code == GE || code == LEU || code == GEU) | |
11035 | { | |
a3170dc6 AH |
11036 | emit_insn (cmp); |
11037 | ||
11038 | switch (code) | |
11039 | { | |
11040 | case LE: code = LT; break; | |
11041 | case GE: code = GT; break; | |
11042 | case LEU: code = LT; break; | |
11043 | case GEU: code = GT; break; | |
37409796 | 11044 | default: gcc_unreachable (); |
a3170dc6 AH |
11045 | } |
11046 | ||
a3170dc6 AH |
11047 | compare_result2 = gen_reg_rtx (CCFPmode); |
11048 | ||
11049 | /* Do the EQ. */ | |
37409796 NS |
11050 | switch (op_mode) |
11051 | { | |
11052 | case SFmode: | |
11053 | cmp = flag_unsafe_math_optimizations | |
11054 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, | |
11055 | rs6000_compare_op1) | |
11056 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
11057 | rs6000_compare_op1); | |
11058 | break; | |
11059 | ||
11060 | case DFmode: | |
11061 | cmp = flag_unsafe_math_optimizations | |
11062 | ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, | |
11063 | rs6000_compare_op1) | |
11064 | : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, | |
11065 | rs6000_compare_op1); | |
11066 | break; | |
11067 | ||
11068 | default: | |
11069 | gcc_unreachable (); | |
11070 | } | |
a3170dc6 AH |
11071 | emit_insn (cmp); |
11072 | ||
a3170dc6 | 11073 | /* OR them together. */ |
64022b5d AH |
11074 | or_result = gen_reg_rtx (CCFPmode); |
11075 | cmp = gen_e500_cr_ior_compare (or_result, compare_result, | |
11076 | compare_result2); | |
a3170dc6 AH |
11077 | compare_result = or_result; |
11078 | code = EQ; | |
11079 | } | |
11080 | else | |
11081 | { | |
a3170dc6 | 11082 | if (code == NE || code == LTGT) |
a3170dc6 | 11083 | code = NE; |
423c1189 AH |
11084 | else |
11085 | code = EQ; | |
a3170dc6 AH |
11086 | } |
11087 | ||
11088 | emit_insn (cmp); | |
11089 | } | |
11090 | else | |
de17c25f DE |
11091 | { |
11092 | /* Generate XLC-compatible TFmode compare as PARALLEL with extra | |
11093 | CLOBBERs to match cmptf_internal2 pattern. */ | |
11094 | if (comp_mode == CCFPmode && TARGET_XL_COMPAT | |
11095 | && GET_MODE (rs6000_compare_op0) == TFmode | |
11096 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
11097 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128) | |
11098 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
11099 | gen_rtvec (9, | |
11100 | gen_rtx_SET (VOIDmode, | |
11101 | compare_result, | |
11102 | gen_rtx_COMPARE (comp_mode, | |
11103 | rs6000_compare_op0, | |
11104 | rs6000_compare_op1)), | |
11105 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
11106 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
11107 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
11108 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
11109 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
11110 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
11111 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
11112 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode))))); | |
3aebbe5f JJ |
11113 | else if (GET_CODE (rs6000_compare_op1) == UNSPEC |
11114 | && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST) | |
11115 | { | |
11116 | rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0); | |
11117 | comp_mode = CCEQmode; | |
11118 | compare_result = gen_reg_rtx (CCEQmode); | |
11119 | if (TARGET_64BIT) | |
11120 | emit_insn (gen_stack_protect_testdi (compare_result, | |
11121 | rs6000_compare_op0, op1)); | |
11122 | else | |
11123 | emit_insn (gen_stack_protect_testsi (compare_result, | |
11124 | rs6000_compare_op0, op1)); | |
11125 | } | |
de17c25f DE |
11126 | else |
11127 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
11128 | gen_rtx_COMPARE (comp_mode, | |
11129 | rs6000_compare_op0, | |
11130 | rs6000_compare_op1))); | |
11131 | } | |
f676971a | 11132 | |
ca5adc63 | 11133 | /* Some kinds of FP comparisons need an OR operation; |
e7108df9 | 11134 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 11135 | if (rs6000_compare_fp_p |
e7108df9 DE |
11136 | && !flag_finite_math_only |
11137 | && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) | |
39a10a29 GK |
11138 | && (code == LE || code == GE |
11139 | || code == UNEQ || code == LTGT | |
11140 | || code == UNGT || code == UNLT)) | |
11141 | { | |
11142 | enum rtx_code or1, or2; | |
11143 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
11144 | rtx or_result = gen_reg_rtx (CCEQmode); | |
f676971a | 11145 | |
39a10a29 GK |
11146 | switch (code) |
11147 | { | |
11148 | case LE: or1 = LT; or2 = EQ; break; | |
11149 | case GE: or1 = GT; or2 = EQ; break; | |
11150 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
11151 | case LTGT: or1 = LT; or2 = GT; break; | |
11152 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
11153 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
37409796 | 11154 | default: gcc_unreachable (); |
39a10a29 GK |
11155 | } |
11156 | validate_condition_mode (or1, comp_mode); | |
11157 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
11158 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
11159 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
11160 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
11161 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
11162 | const_true_rtx); | |
11163 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
11164 | ||
11165 | compare_result = or_result; | |
11166 | code = EQ; | |
11167 | } | |
11168 | ||
11169 | validate_condition_mode (code, GET_MODE (compare_result)); | |
f676971a | 11170 | |
1c563bed | 11171 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
11172 | } |
11173 | ||
11174 | ||
11175 | /* Emit the RTL for an sCOND pattern. */ | |
11176 | ||
11177 | void | |
a2369ed3 | 11178 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
11179 | { |
11180 | rtx condition_rtx; | |
11181 | enum machine_mode op_mode; | |
b7053a3f | 11182 | enum rtx_code cond_code; |
39a10a29 GK |
11183 | |
11184 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
11185 | cond_code = GET_CODE (condition_rtx); |
11186 | ||
423c1189 AH |
11187 | if (TARGET_E500 && rs6000_compare_fp_p |
11188 | && !TARGET_FPRS && TARGET_HARD_FLOAT) | |
11189 | { | |
11190 | rtx t; | |
11191 | ||
11192 | PUT_MODE (condition_rtx, SImode); | |
11193 | t = XEXP (condition_rtx, 0); | |
11194 | ||
37409796 | 11195 | gcc_assert (cond_code == NE || cond_code == EQ); |
423c1189 AH |
11196 | |
11197 | if (cond_code == NE) | |
64022b5d | 11198 | emit_insn (gen_e500_flip_gt_bit (t, t)); |
423c1189 | 11199 | |
64022b5d | 11200 | emit_insn (gen_move_from_CR_gt_bit (result, t)); |
423c1189 AH |
11201 | return; |
11202 | } | |
11203 | ||
b7053a3f GK |
11204 | if (cond_code == NE |
11205 | || cond_code == GE || cond_code == LE | |
11206 | || cond_code == GEU || cond_code == LEU | |
11207 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
11208 | { | |
11209 | rtx not_result = gen_reg_rtx (CCEQmode); | |
11210 | rtx not_op, rev_cond_rtx; | |
11211 | enum machine_mode cc_mode; | |
f676971a | 11212 | |
b7053a3f GK |
11213 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); |
11214 | ||
1c563bed | 11215 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 11216 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
11217 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
11218 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
11219 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
11220 | } | |
39a10a29 GK |
11221 | |
11222 | op_mode = GET_MODE (rs6000_compare_op0); | |
11223 | if (op_mode == VOIDmode) | |
11224 | op_mode = GET_MODE (rs6000_compare_op1); | |
11225 | ||
11226 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
11227 | { | |
11228 | PUT_MODE (condition_rtx, DImode); | |
11229 | convert_move (result, condition_rtx, 0); | |
11230 | } | |
11231 | else | |
11232 | { | |
11233 | PUT_MODE (condition_rtx, SImode); | |
11234 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
11235 | } | |
11236 | } | |
11237 | ||
39a10a29 GK |
11238 | /* Emit a branch of kind CODE to location LOC. */ |
11239 | ||
11240 | void | |
a2369ed3 | 11241 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
11242 | { |
11243 | rtx condition_rtx, loc_ref; | |
11244 | ||
11245 | condition_rtx = rs6000_generate_compare (code); | |
11246 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
11247 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
11248 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
11249 | loc_ref, pc_rtx))); | |
11250 | } | |
11251 | ||
12a4e8c5 GK |
11252 | /* Return the string to output a conditional branch to LABEL, which is |
11253 | the operand number of the label, or -1 if the branch is really a | |
f676971a | 11254 | conditional return. |
12a4e8c5 GK |
11255 | |
11256 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
11257 | condition code register and its mode specifies what kind of | |
11258 | comparison we made. | |
11259 | ||
a0ab749a | 11260 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
11261 | |
11262 | INSN is the insn. */ | |
11263 | ||
11264 | char * | |
a2369ed3 | 11265 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
11266 | { |
11267 | static char string[64]; | |
11268 | enum rtx_code code = GET_CODE (op); | |
11269 | rtx cc_reg = XEXP (op, 0); | |
11270 | enum machine_mode mode = GET_MODE (cc_reg); | |
11271 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 11272 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
11273 | int really_reversed = reversed ^ need_longbranch; |
11274 | char *s = string; | |
11275 | const char *ccode; | |
11276 | const char *pred; | |
11277 | rtx note; | |
11278 | ||
39a10a29 GK |
11279 | validate_condition_mode (code, mode); |
11280 | ||
11281 | /* Work out which way this really branches. We could use | |
11282 | reverse_condition_maybe_unordered here always but this | |
11283 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 11284 | if (really_reversed) |
de40e1df DJ |
11285 | { |
11286 | /* Reversal of FP compares takes care -- an ordered compare | |
11287 | becomes an unordered compare and vice versa. */ | |
11288 | if (mode == CCFPmode) | |
11289 | code = reverse_condition_maybe_unordered (code); | |
11290 | else | |
11291 | code = reverse_condition (code); | |
11292 | } | |
12a4e8c5 | 11293 | |
993f19a8 | 11294 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
11295 | { |
11296 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
11297 | to the GT bit. */ | |
37409796 NS |
11298 | switch (code) |
11299 | { | |
11300 | case EQ: | |
11301 | /* Opposite of GT. */ | |
11302 | code = GT; | |
11303 | break; | |
11304 | ||
11305 | case NE: | |
11306 | code = UNLE; | |
11307 | break; | |
11308 | ||
11309 | default: | |
11310 | gcc_unreachable (); | |
11311 | } | |
a3170dc6 AH |
11312 | } |
11313 | ||
39a10a29 | 11314 | switch (code) |
12a4e8c5 GK |
11315 | { |
11316 | /* Not all of these are actually distinct opcodes, but | |
11317 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
11318 | case NE: case LTGT: |
11319 | ccode = "ne"; break; | |
11320 | case EQ: case UNEQ: | |
11321 | ccode = "eq"; break; | |
f676971a | 11322 | case GE: case GEU: |
50a0b056 | 11323 | ccode = "ge"; break; |
f676971a | 11324 | case GT: case GTU: case UNGT: |
50a0b056 | 11325 | ccode = "gt"; break; |
f676971a | 11326 | case LE: case LEU: |
50a0b056 | 11327 | ccode = "le"; break; |
f676971a | 11328 | case LT: case LTU: case UNLT: |
50a0b056 | 11329 | ccode = "lt"; break; |
12a4e8c5 GK |
11330 | case UNORDERED: ccode = "un"; break; |
11331 | case ORDERED: ccode = "nu"; break; | |
11332 | case UNGE: ccode = "nl"; break; | |
11333 | case UNLE: ccode = "ng"; break; | |
11334 | default: | |
37409796 | 11335 | gcc_unreachable (); |
12a4e8c5 | 11336 | } |
f676971a EC |
11337 | |
11338 | /* Maybe we have a guess as to how likely the branch is. | |
94a54f47 | 11339 | The old mnemonics don't have a way to specify this information. */ |
f4857b9b | 11340 | pred = ""; |
12a4e8c5 GK |
11341 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
11342 | if (note != NULL_RTX) | |
11343 | { | |
11344 | /* PROB is the difference from 50%. */ | |
11345 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
11346 | |
11347 | /* Only hint for highly probable/improbable branches on newer | |
11348 | cpus as static prediction overrides processor dynamic | |
11349 | prediction. For older cpus we may as well always hint, but | |
11350 | assume not taken for branches that are very close to 50% as a | |
11351 | mispredicted taken branch is more expensive than a | |
f676971a | 11352 | mispredicted not-taken branch. */ |
ec507f2d | 11353 | if (rs6000_always_hint |
f4857b9b AM |
11354 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) |
11355 | { | |
11356 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
11357 | && ((prob > 0) ^ need_longbranch)) | |
c4ad648e | 11358 | pred = "+"; |
f4857b9b AM |
11359 | else |
11360 | pred = "-"; | |
11361 | } | |
12a4e8c5 | 11362 | } |
12a4e8c5 GK |
11363 | |
11364 | if (label == NULL) | |
94a54f47 | 11365 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 11366 | else |
94a54f47 | 11367 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 11368 | |
37c67319 | 11369 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 11370 | Assume they'd only be the first character.... */ |
37c67319 GK |
11371 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
11372 | *s++ = '%'; | |
94a54f47 | 11373 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
11374 | |
11375 | if (label != NULL) | |
11376 | { | |
11377 | /* If the branch distance was too far, we may have to use an | |
11378 | unconditional branch to go the distance. */ | |
11379 | if (need_longbranch) | |
44518ddd | 11380 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
11381 | else |
11382 | s += sprintf (s, ",%s", label); | |
11383 | } | |
11384 | ||
11385 | return string; | |
11386 | } | |
50a0b056 | 11387 | |
64022b5d | 11388 | /* Return the string to flip the GT bit on a CR. */ |
423c1189 | 11389 | char * |
64022b5d | 11390 | output_e500_flip_gt_bit (rtx dst, rtx src) |
423c1189 AH |
11391 | { |
11392 | static char string[64]; | |
11393 | int a, b; | |
11394 | ||
37409796 NS |
11395 | gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst)) |
11396 | && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src))); | |
423c1189 | 11397 | |
64022b5d AH |
11398 | /* GT bit. */ |
11399 | a = 4 * (REGNO (dst) - CR0_REGNO) + 1; | |
11400 | b = 4 * (REGNO (src) - CR0_REGNO) + 1; | |
423c1189 AH |
11401 | |
11402 | sprintf (string, "crnot %d,%d", a, b); | |
11403 | return string; | |
11404 | } | |
11405 | ||
21213b4c DP |
11406 | /* Return insn index for the vector compare instruction for given CODE, |
11407 | and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is | |
11408 | not available. */ | |
11409 | ||
11410 | static int | |
94ff898d | 11411 | get_vec_cmp_insn (enum rtx_code code, |
21213b4c DP |
11412 | enum machine_mode dest_mode, |
11413 | enum machine_mode op_mode) | |
11414 | { | |
11415 | if (!TARGET_ALTIVEC) | |
11416 | return INSN_NOT_AVAILABLE; | |
11417 | ||
11418 | switch (code) | |
11419 | { | |
11420 | case EQ: | |
11421 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
11422 | return UNSPEC_VCMPEQUB; | |
11423 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
11424 | return UNSPEC_VCMPEQUH; | |
11425 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
11426 | return UNSPEC_VCMPEQUW; | |
11427 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
11428 | return UNSPEC_VCMPEQFP; | |
11429 | break; | |
11430 | case GE: | |
11431 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
11432 | return UNSPEC_VCMPGEFP; | |
11433 | case GT: | |
11434 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
11435 | return UNSPEC_VCMPGTSB; | |
11436 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
11437 | return UNSPEC_VCMPGTSH; | |
11438 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
11439 | return UNSPEC_VCMPGTSW; | |
11440 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
11441 | return UNSPEC_VCMPGTFP; | |
11442 | break; | |
11443 | case GTU: | |
11444 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
11445 | return UNSPEC_VCMPGTUB; | |
11446 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
11447 | return UNSPEC_VCMPGTUH; | |
11448 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
11449 | return UNSPEC_VCMPGTUW; | |
11450 | break; | |
11451 | default: | |
11452 | break; | |
11453 | } | |
11454 | return INSN_NOT_AVAILABLE; | |
11455 | } | |
11456 | ||
11457 | /* Emit vector compare for operands OP0 and OP1 using code RCODE. | |
11458 | DMODE is expected destination mode. This is a recursive function. */ | |
11459 | ||
11460 | static rtx | |
11461 | rs6000_emit_vector_compare (enum rtx_code rcode, | |
11462 | rtx op0, rtx op1, | |
11463 | enum machine_mode dmode) | |
11464 | { | |
11465 | int vec_cmp_insn; | |
11466 | rtx mask; | |
11467 | enum machine_mode dest_mode; | |
11468 | enum machine_mode op_mode = GET_MODE (op1); | |
11469 | ||
37409796 NS |
11470 | gcc_assert (TARGET_ALTIVEC); |
11471 | gcc_assert (GET_MODE (op0) == GET_MODE (op1)); | |
21213b4c DP |
11472 | |
11473 | /* Floating point vector compare instructions uses destination V4SImode. | |
11474 | Move destination to appropriate mode later. */ | |
11475 | if (dmode == V4SFmode) | |
11476 | dest_mode = V4SImode; | |
11477 | else | |
11478 | dest_mode = dmode; | |
11479 | ||
11480 | mask = gen_reg_rtx (dest_mode); | |
11481 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
11482 | ||
11483 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
11484 | { | |
11485 | bool swap_operands = false; | |
11486 | bool try_again = false; | |
11487 | switch (rcode) | |
11488 | { | |
11489 | case LT: | |
11490 | rcode = GT; | |
11491 | swap_operands = true; | |
11492 | try_again = true; | |
11493 | break; | |
11494 | case LTU: | |
11495 | rcode = GTU; | |
11496 | swap_operands = true; | |
11497 | try_again = true; | |
11498 | break; | |
11499 | case NE: | |
11500 | /* Treat A != B as ~(A==B). */ | |
11501 | { | |
11502 | enum insn_code nor_code; | |
11503 | rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
11504 | dest_mode); | |
94ff898d | 11505 | |
21213b4c | 11506 | nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code; |
37409796 | 11507 | gcc_assert (nor_code != CODE_FOR_nothing); |
21213b4c DP |
11508 | emit_insn (GEN_FCN (nor_code) (mask, eq_rtx)); |
11509 | ||
11510 | if (dmode != dest_mode) | |
11511 | { | |
11512 | rtx temp = gen_reg_rtx (dest_mode); | |
11513 | convert_move (temp, mask, 0); | |
11514 | return temp; | |
11515 | } | |
11516 | return mask; | |
11517 | } | |
11518 | break; | |
11519 | case GE: | |
11520 | case GEU: | |
11521 | case LE: | |
11522 | case LEU: | |
11523 | /* Try GT/GTU/LT/LTU OR EQ */ | |
11524 | { | |
11525 | rtx c_rtx, eq_rtx; | |
11526 | enum insn_code ior_code; | |
11527 | enum rtx_code new_code; | |
11528 | ||
37409796 NS |
11529 | switch (rcode) |
11530 | { | |
11531 | case GE: | |
11532 | new_code = GT; | |
11533 | break; | |
11534 | ||
11535 | case GEU: | |
11536 | new_code = GTU; | |
11537 | break; | |
11538 | ||
11539 | case LE: | |
11540 | new_code = LT; | |
11541 | break; | |
11542 | ||
11543 | case LEU: | |
11544 | new_code = LTU; | |
11545 | break; | |
11546 | ||
11547 | default: | |
11548 | gcc_unreachable (); | |
11549 | } | |
21213b4c DP |
11550 | |
11551 | c_rtx = rs6000_emit_vector_compare (new_code, | |
11552 | op0, op1, dest_mode); | |
11553 | eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
11554 | dest_mode); | |
11555 | ||
11556 | ior_code = ior_optab->handlers[(int)dest_mode].insn_code; | |
37409796 | 11557 | gcc_assert (ior_code != CODE_FOR_nothing); |
21213b4c DP |
11558 | emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx)); |
11559 | if (dmode != dest_mode) | |
11560 | { | |
11561 | rtx temp = gen_reg_rtx (dest_mode); | |
11562 | convert_move (temp, mask, 0); | |
11563 | return temp; | |
11564 | } | |
11565 | return mask; | |
11566 | } | |
11567 | break; | |
11568 | default: | |
37409796 | 11569 | gcc_unreachable (); |
21213b4c DP |
11570 | } |
11571 | ||
11572 | if (try_again) | |
11573 | { | |
11574 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
37409796 NS |
11575 | /* You only get two chances. */ |
11576 | gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE); | |
21213b4c DP |
11577 | } |
11578 | ||
11579 | if (swap_operands) | |
11580 | { | |
11581 | rtx tmp; | |
11582 | tmp = op0; | |
11583 | op0 = op1; | |
11584 | op1 = tmp; | |
11585 | } | |
11586 | } | |
11587 | ||
915167f5 GK |
11588 | emit_insn (gen_rtx_SET (VOIDmode, mask, |
11589 | gen_rtx_UNSPEC (dest_mode, | |
11590 | gen_rtvec (2, op0, op1), | |
11591 | vec_cmp_insn))); | |
21213b4c DP |
11592 | if (dmode != dest_mode) |
11593 | { | |
11594 | rtx temp = gen_reg_rtx (dest_mode); | |
11595 | convert_move (temp, mask, 0); | |
11596 | return temp; | |
11597 | } | |
11598 | return mask; | |
11599 | } | |
11600 | ||
11601 | /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if | |
11602 | valid insn doesn exist for given mode. */ | |
11603 | ||
11604 | static int | |
11605 | get_vsel_insn (enum machine_mode mode) | |
11606 | { | |
11607 | switch (mode) | |
11608 | { | |
11609 | case V4SImode: | |
11610 | return UNSPEC_VSEL4SI; | |
11611 | break; | |
11612 | case V4SFmode: | |
11613 | return UNSPEC_VSEL4SF; | |
11614 | break; | |
11615 | case V8HImode: | |
11616 | return UNSPEC_VSEL8HI; | |
11617 | break; | |
11618 | case V16QImode: | |
11619 | return UNSPEC_VSEL16QI; | |
11620 | break; | |
11621 | default: | |
11622 | return INSN_NOT_AVAILABLE; | |
11623 | break; | |
11624 | } | |
11625 | return INSN_NOT_AVAILABLE; | |
11626 | } | |
11627 | ||
11628 | /* Emit vector select insn where DEST is destination using | |
11629 | operands OP1, OP2 and MASK. */ | |
11630 | ||
11631 | static void | |
11632 | rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask) | |
11633 | { | |
11634 | rtx t, temp; | |
11635 | enum machine_mode dest_mode = GET_MODE (dest); | |
11636 | int vsel_insn_index = get_vsel_insn (GET_MODE (dest)); | |
11637 | ||
11638 | temp = gen_reg_rtx (dest_mode); | |
94ff898d | 11639 | |
bb8df8a6 | 11640 | /* For each vector element, select op1 when mask is 1 otherwise |
19f1ebc7 | 11641 | select op2. */ |
915167f5 GK |
11642 | t = gen_rtx_SET (VOIDmode, temp, |
11643 | gen_rtx_UNSPEC (dest_mode, | |
11644 | gen_rtvec (3, op2, op1, mask), | |
11645 | vsel_insn_index)); | |
21213b4c DP |
11646 | emit_insn (t); |
11647 | emit_move_insn (dest, temp); | |
11648 | return; | |
11649 | } | |
11650 | ||
94ff898d | 11651 | /* Emit vector conditional expression. |
21213b4c DP |
11652 | DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands. |
11653 | CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */ | |
11654 | ||
11655 | int | |
11656 | rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2, | |
11657 | rtx cond, rtx cc_op0, rtx cc_op1) | |
11658 | { | |
11659 | enum machine_mode dest_mode = GET_MODE (dest); | |
11660 | enum rtx_code rcode = GET_CODE (cond); | |
11661 | rtx mask; | |
11662 | ||
11663 | if (!TARGET_ALTIVEC) | |
11664 | return 0; | |
11665 | ||
11666 | /* Get the vector mask for the given relational operations. */ | |
11667 | mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode); | |
11668 | ||
11669 | rs6000_emit_vector_select (dest, op1, op2, mask); | |
11670 | ||
11671 | return 1; | |
11672 | } | |
11673 | ||
50a0b056 GK |
11674 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the |
11675 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
11676 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 11677 | |
50a0b056 | 11678 | int |
a2369ed3 | 11679 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
11680 | { |
11681 | enum rtx_code code = GET_CODE (op); | |
11682 | rtx op0 = rs6000_compare_op0; | |
11683 | rtx op1 = rs6000_compare_op1; | |
11684 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
11685 | enum machine_mode compare_mode = GET_MODE (op0); |
11686 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 | 11687 | rtx temp; |
add2402e | 11688 | bool is_against_zero; |
50a0b056 | 11689 | |
a3c9585f | 11690 | /* These modes should always match. */ |
a3170dc6 AH |
11691 | if (GET_MODE (op1) != compare_mode |
11692 | /* In the isel case however, we can use a compare immediate, so | |
11693 | op1 may be a small constant. */ | |
11694 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 11695 | return 0; |
178c3eff | 11696 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 11697 | return 0; |
178c3eff | 11698 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
11699 | return 0; |
11700 | ||
50a0b056 | 11701 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 11702 | if it's too slow.... */ |
50a0b056 | 11703 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
11704 | { |
11705 | if (TARGET_ISEL) | |
11706 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
11707 | return 0; | |
11708 | } | |
fef98bf2 | 11709 | else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS |
ebb109ad | 11710 | && SCALAR_FLOAT_MODE_P (compare_mode)) |
fef98bf2 | 11711 | return 0; |
50a0b056 | 11712 | |
add2402e | 11713 | is_against_zero = op1 == CONST0_RTX (compare_mode); |
94ff898d | 11714 | |
add2402e GK |
11715 | /* A floating-point subtract might overflow, underflow, or produce |
11716 | an inexact result, thus changing the floating-point flags, so it | |
11717 | can't be generated if we care about that. It's safe if one side | |
11718 | of the construct is zero, since then no subtract will be | |
11719 | generated. */ | |
ebb109ad | 11720 | if (SCALAR_FLOAT_MODE_P (compare_mode) |
add2402e GK |
11721 | && flag_trapping_math && ! is_against_zero) |
11722 | return 0; | |
11723 | ||
50a0b056 GK |
11724 | /* Eliminate half of the comparisons by switching operands, this |
11725 | makes the remaining code simpler. */ | |
11726 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 11727 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
11728 | { |
11729 | code = reverse_condition_maybe_unordered (code); | |
11730 | temp = true_cond; | |
11731 | true_cond = false_cond; | |
11732 | false_cond = temp; | |
11733 | } | |
11734 | ||
11735 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
11736 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 11737 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 | 11738 | return 0; |
f676971a | 11739 | |
50a0b056 GK |
11740 | if (GET_CODE (op1) == CONST_DOUBLE) |
11741 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
f676971a | 11742 | |
b6d08ca1 | 11743 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
11744 | a subtract, then comparing against zero. Unfortunately, |
11745 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 11746 | know that the operand is finite and the comparison |
50a0b056 | 11747 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 11748 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 11749 | && code != GT && code != UNGE |
045572c7 | 11750 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
11751 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
11752 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
f676971a | 11753 | || (! rtx_equal_p (op0, true_cond) |
50a0b056 GK |
11754 | && ! rtx_equal_p (op1, true_cond)))) |
11755 | return 0; | |
add2402e | 11756 | |
50a0b056 GK |
11757 | /* At this point we know we can use fsel. */ |
11758 | ||
11759 | /* Reduce the comparison to a comparison against zero. */ | |
add2402e GK |
11760 | if (! is_against_zero) |
11761 | { | |
11762 | temp = gen_reg_rtx (compare_mode); | |
11763 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
11764 | gen_rtx_MINUS (compare_mode, op0, op1))); | |
11765 | op0 = temp; | |
11766 | op1 = CONST0_RTX (compare_mode); | |
11767 | } | |
50a0b056 GK |
11768 | |
11769 | /* If we don't care about NaNs we can reduce some of the comparisons | |
11770 | down to faster ones. */ | |
bc9ec0e0 | 11771 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
11772 | switch (code) |
11773 | { | |
11774 | case GT: | |
11775 | code = LE; | |
11776 | temp = true_cond; | |
11777 | true_cond = false_cond; | |
11778 | false_cond = temp; | |
11779 | break; | |
11780 | case UNGE: | |
11781 | code = GE; | |
11782 | break; | |
11783 | case UNEQ: | |
11784 | code = EQ; | |
11785 | break; | |
11786 | default: | |
11787 | break; | |
11788 | } | |
11789 | ||
11790 | /* Now, reduce everything down to a GE. */ | |
11791 | switch (code) | |
11792 | { | |
11793 | case GE: | |
11794 | break; | |
11795 | ||
11796 | case LE: | |
3148ad6d DJ |
11797 | temp = gen_reg_rtx (compare_mode); |
11798 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
11799 | op0 = temp; |
11800 | break; | |
11801 | ||
11802 | case ORDERED: | |
3148ad6d DJ |
11803 | temp = gen_reg_rtx (compare_mode); |
11804 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
11805 | op0 = temp; |
11806 | break; | |
11807 | ||
11808 | case EQ: | |
3148ad6d | 11809 | temp = gen_reg_rtx (compare_mode); |
f676971a | 11810 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
11811 | gen_rtx_NEG (compare_mode, |
11812 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
11813 | op0 = temp; |
11814 | break; | |
11815 | ||
11816 | case UNGE: | |
bc9ec0e0 | 11817 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 11818 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 11819 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 11820 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
11821 | gen_rtx_GE (VOIDmode, |
11822 | op0, op1), | |
11823 | true_cond, false_cond))); | |
bc9ec0e0 GK |
11824 | false_cond = true_cond; |
11825 | true_cond = temp; | |
50a0b056 | 11826 | |
3148ad6d DJ |
11827 | temp = gen_reg_rtx (compare_mode); |
11828 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
11829 | op0 = temp; |
11830 | break; | |
11831 | ||
11832 | case GT: | |
bc9ec0e0 | 11833 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 11834 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 11835 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
f676971a | 11836 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
11837 | gen_rtx_GE (VOIDmode, |
11838 | op0, op1), | |
11839 | true_cond, false_cond))); | |
bc9ec0e0 GK |
11840 | true_cond = false_cond; |
11841 | false_cond = temp; | |
50a0b056 | 11842 | |
3148ad6d DJ |
11843 | temp = gen_reg_rtx (compare_mode); |
11844 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
11845 | op0 = temp; |
11846 | break; | |
11847 | ||
11848 | default: | |
37409796 | 11849 | gcc_unreachable (); |
50a0b056 GK |
11850 | } |
11851 | ||
11852 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 11853 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
11854 | gen_rtx_GE (VOIDmode, |
11855 | op0, op1), | |
11856 | true_cond, false_cond))); | |
11857 | return 1; | |
11858 | } | |
11859 | ||
a3170dc6 AH |
11860 | /* Same as above, but for ints (isel). */ |
11861 | ||
11862 | static int | |
a2369ed3 | 11863 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
11864 | { |
11865 | rtx condition_rtx, cr; | |
11866 | ||
11867 | /* All isel implementations thus far are 32-bits. */ | |
11868 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
11869 | return 0; | |
11870 | ||
11871 | /* We still have to do the compare, because isel doesn't do a | |
11872 | compare, it just looks at the CRx bits set by a previous compare | |
11873 | instruction. */ | |
11874 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
11875 | cr = XEXP (condition_rtx, 0); | |
11876 | ||
11877 | if (GET_MODE (cr) == CCmode) | |
11878 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
11879 | true_cond, false_cond, cr)); | |
11880 | else | |
11881 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
11882 | true_cond, false_cond, cr)); | |
11883 | ||
11884 | return 1; | |
11885 | } | |
11886 | ||
11887 | const char * | |
a2369ed3 | 11888 | output_isel (rtx *operands) |
a3170dc6 AH |
11889 | { |
11890 | enum rtx_code code; | |
11891 | ||
11892 | code = GET_CODE (operands[1]); | |
11893 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
11894 | { | |
11895 | PUT_CODE (operands[1], reverse_condition (code)); | |
11896 | return "isel %0,%3,%2,%j1"; | |
11897 | } | |
11898 | else | |
11899 | return "isel %0,%2,%3,%j1"; | |
11900 | } | |
11901 | ||
50a0b056 | 11902 | void |
a2369ed3 | 11903 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
11904 | { |
11905 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 11906 | enum rtx_code c; |
50a0b056 | 11907 | rtx target; |
5dc8d536 AH |
11908 | |
11909 | if (code == SMAX || code == SMIN) | |
11910 | c = GE; | |
11911 | else | |
11912 | c = GEU; | |
11913 | ||
50a0b056 | 11914 | if (code == SMAX || code == UMAX) |
f676971a | 11915 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
11916 | op0, op1, mode, 0); |
11917 | else | |
f676971a | 11918 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 | 11919 | op1, op0, mode, 0); |
37409796 | 11920 | gcc_assert (target); |
50a0b056 GK |
11921 | if (target != dest) |
11922 | emit_move_insn (dest, target); | |
11923 | } | |
46c07df8 | 11924 | |
915167f5 GK |
11925 | /* Emit instructions to perform a load-reserved/store-conditional operation. |
11926 | The operation performed is an atomic | |
11927 | (set M (CODE:MODE M OP)) | |
11928 | If not NULL, BEFORE is atomically set to M before the operation, and | |
11929 | AFTER is set to M after the operation (that is, (CODE:MODE M OP)). | |
bb8df8a6 | 11930 | If SYNC_P then a memory barrier is emitted before the operation. |
915167f5 GK |
11931 | Either OP or M may be wrapped in a NOT operation. */ |
11932 | ||
11933 | void | |
11934 | rs6000_emit_sync (enum rtx_code code, enum machine_mode mode, | |
11935 | rtx m, rtx op, rtx before_param, rtx after_param, | |
11936 | bool sync_p) | |
11937 | { | |
11938 | enum machine_mode used_mode; | |
11939 | rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after; | |
11940 | rtx used_m; | |
11941 | rtvec vec; | |
11942 | HOST_WIDE_INT imask = GET_MODE_MASK (mode); | |
11943 | rtx shift = NULL_RTX; | |
bb8df8a6 | 11944 | |
915167f5 GK |
11945 | if (sync_p) |
11946 | emit_insn (gen_memory_barrier ()); | |
bb8df8a6 | 11947 | |
915167f5 GK |
11948 | if (GET_CODE (m) == NOT) |
11949 | used_m = XEXP (m, 0); | |
11950 | else | |
11951 | used_m = m; | |
11952 | ||
11953 | /* If this is smaller than SImode, we'll have to use SImode with | |
11954 | adjustments. */ | |
11955 | if (mode == QImode || mode == HImode) | |
11956 | { | |
11957 | rtx newop, oldop; | |
11958 | ||
11959 | if (MEM_ALIGN (used_m) >= 32) | |
11960 | { | |
11961 | int ishift = 0; | |
11962 | if (BYTES_BIG_ENDIAN) | |
11963 | ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode); | |
bb8df8a6 | 11964 | |
915167f5 GK |
11965 | shift = GEN_INT (ishift); |
11966 | } | |
11967 | else | |
11968 | { | |
11969 | rtx addrSI, aligned_addr; | |
a9c9d3fa | 11970 | int shift_mask = mode == QImode ? 0x18 : 0x10; |
bb8df8a6 | 11971 | |
915167f5 GK |
11972 | addrSI = force_reg (SImode, gen_lowpart_common (SImode, |
11973 | XEXP (used_m, 0))); | |
11974 | shift = gen_reg_rtx (SImode); | |
11975 | ||
11976 | emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3), | |
a9c9d3fa GK |
11977 | GEN_INT (shift_mask))); |
11978 | emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask))); | |
915167f5 GK |
11979 | |
11980 | aligned_addr = expand_binop (Pmode, and_optab, | |
11981 | XEXP (used_m, 0), | |
11982 | GEN_INT (-4), NULL_RTX, | |
11983 | 1, OPTAB_LIB_WIDEN); | |
11984 | used_m = change_address (used_m, SImode, aligned_addr); | |
11985 | set_mem_align (used_m, 32); | |
11986 | /* It's safe to keep the old alias set of USED_M, because | |
11987 | the operation is atomic and only affects the original | |
11988 | USED_M. */ | |
11989 | if (GET_CODE (m) == NOT) | |
11990 | m = gen_rtx_NOT (SImode, used_m); | |
11991 | else | |
11992 | m = used_m; | |
11993 | } | |
11994 | ||
11995 | if (GET_CODE (op) == NOT) | |
11996 | { | |
11997 | oldop = lowpart_subreg (SImode, XEXP (op, 0), mode); | |
11998 | oldop = gen_rtx_NOT (SImode, oldop); | |
11999 | } | |
12000 | else | |
12001 | oldop = lowpart_subreg (SImode, op, mode); | |
9f0076e5 | 12002 | |
915167f5 GK |
12003 | switch (code) |
12004 | { | |
12005 | case IOR: | |
12006 | case XOR: | |
12007 | newop = expand_binop (SImode, and_optab, | |
12008 | oldop, GEN_INT (imask), NULL_RTX, | |
12009 | 1, OPTAB_LIB_WIDEN); | |
12010 | emit_insn (gen_ashlsi3 (newop, newop, shift)); | |
12011 | break; | |
12012 | ||
12013 | case AND: | |
12014 | newop = expand_binop (SImode, ior_optab, | |
12015 | oldop, GEN_INT (~imask), NULL_RTX, | |
12016 | 1, OPTAB_LIB_WIDEN); | |
a9c9d3fa | 12017 | emit_insn (gen_rotlsi3 (newop, newop, shift)); |
915167f5 GK |
12018 | break; |
12019 | ||
12020 | case PLUS: | |
9f0076e5 | 12021 | case MINUS: |
915167f5 GK |
12022 | { |
12023 | rtx mask; | |
bb8df8a6 | 12024 | |
915167f5 GK |
12025 | newop = expand_binop (SImode, and_optab, |
12026 | oldop, GEN_INT (imask), NULL_RTX, | |
12027 | 1, OPTAB_LIB_WIDEN); | |
12028 | emit_insn (gen_ashlsi3 (newop, newop, shift)); | |
12029 | ||
12030 | mask = gen_reg_rtx (SImode); | |
12031 | emit_move_insn (mask, GEN_INT (imask)); | |
12032 | emit_insn (gen_ashlsi3 (mask, mask, shift)); | |
12033 | ||
9f0076e5 DE |
12034 | if (code == PLUS) |
12035 | newop = gen_rtx_PLUS (SImode, m, newop); | |
12036 | else | |
12037 | newop = gen_rtx_MINUS (SImode, m, newop); | |
12038 | newop = gen_rtx_AND (SImode, newop, mask); | |
915167f5 GK |
12039 | newop = gen_rtx_IOR (SImode, newop, |
12040 | gen_rtx_AND (SImode, | |
12041 | gen_rtx_NOT (SImode, mask), | |
12042 | m)); | |
12043 | break; | |
12044 | } | |
12045 | ||
12046 | default: | |
12047 | gcc_unreachable (); | |
12048 | } | |
12049 | ||
a9c9d3fa GK |
12050 | if (GET_CODE (m) == NOT) |
12051 | { | |
12052 | rtx mask, xorm; | |
12053 | ||
12054 | mask = gen_reg_rtx (SImode); | |
12055 | emit_move_insn (mask, GEN_INT (imask)); | |
12056 | emit_insn (gen_ashlsi3 (mask, mask, shift)); | |
12057 | ||
12058 | xorm = gen_rtx_XOR (SImode, used_m, mask); | |
12059 | /* Depending on the value of 'op', the XOR or the operation might | |
12060 | be able to be simplified away. */ | |
12061 | newop = simplify_gen_binary (code, SImode, xorm, newop); | |
12062 | } | |
915167f5 GK |
12063 | op = newop; |
12064 | used_mode = SImode; | |
12065 | before = gen_reg_rtx (used_mode); | |
12066 | after = gen_reg_rtx (used_mode); | |
12067 | } | |
12068 | else | |
12069 | { | |
12070 | used_mode = mode; | |
12071 | before = before_param; | |
12072 | after = after_param; | |
12073 | ||
12074 | if (before == NULL_RTX) | |
12075 | before = gen_reg_rtx (used_mode); | |
12076 | if (after == NULL_RTX) | |
12077 | after = gen_reg_rtx (used_mode); | |
12078 | } | |
bb8df8a6 | 12079 | |
9f0076e5 DE |
12080 | if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT) |
12081 | && used_mode != mode) | |
915167f5 GK |
12082 | the_op = op; /* Computed above. */ |
12083 | else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT) | |
12084 | the_op = gen_rtx_fmt_ee (code, used_mode, op, m); | |
12085 | else | |
12086 | the_op = gen_rtx_fmt_ee (code, used_mode, m, op); | |
12087 | ||
12088 | set_after = gen_rtx_SET (VOIDmode, after, the_op); | |
12089 | set_before = gen_rtx_SET (VOIDmode, before, used_m); | |
12090 | set_atomic = gen_rtx_SET (VOIDmode, used_m, | |
9f0076e5 DE |
12091 | gen_rtx_UNSPEC (used_mode, |
12092 | gen_rtvec (1, the_op), | |
12093 | UNSPEC_SYNC_OP)); | |
915167f5 GK |
12094 | cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode)); |
12095 | ||
9f0076e5 | 12096 | if ((code == PLUS || code == MINUS) && used_mode != mode) |
915167f5 GK |
12097 | vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch, |
12098 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); | |
12099 | else | |
12100 | vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch); | |
12101 | emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); | |
12102 | ||
12103 | /* Shift and mask the return values properly. */ | |
12104 | if (used_mode != mode && before_param) | |
12105 | { | |
12106 | emit_insn (gen_lshrsi3 (before, before, shift)); | |
12107 | convert_move (before_param, before, 1); | |
12108 | } | |
12109 | ||
12110 | if (used_mode != mode && after_param) | |
12111 | { | |
12112 | emit_insn (gen_lshrsi3 (after, after, shift)); | |
12113 | convert_move (after_param, after, 1); | |
12114 | } | |
12115 | ||
12116 | /* The previous sequence will end with a branch that's dependent on | |
12117 | the conditional store, so placing an isync will ensure that no | |
12118 | other instructions (especially, no load or store instructions) | |
12119 | can start before the atomic operation completes. */ | |
12120 | if (sync_p) | |
12121 | emit_insn (gen_isync ()); | |
12122 | } | |
12123 | ||
b52110d4 DE |
12124 | /* A subroutine of the atomic operation splitters. Jump to LABEL if |
12125 | COND is true. Mark the jump as unlikely to be taken. */ | |
12126 | ||
12127 | static void | |
12128 | emit_unlikely_jump (rtx cond, rtx label) | |
12129 | { | |
12130 | rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1); | |
12131 | rtx x; | |
12132 | ||
12133 | x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx); | |
12134 | x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x)); | |
12135 | REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX); | |
12136 | } | |
12137 | ||
12138 | /* A subroutine of the atomic operation splitters. Emit a load-locked | |
12139 | instruction in MODE. */ | |
12140 | ||
12141 | static void | |
12142 | emit_load_locked (enum machine_mode mode, rtx reg, rtx mem) | |
12143 | { | |
12144 | rtx (*fn) (rtx, rtx) = NULL; | |
12145 | if (mode == SImode) | |
12146 | fn = gen_load_locked_si; | |
12147 | else if (mode == DImode) | |
12148 | fn = gen_load_locked_di; | |
12149 | emit_insn (fn (reg, mem)); | |
12150 | } | |
12151 | ||
12152 | /* A subroutine of the atomic operation splitters. Emit a store-conditional | |
12153 | instruction in MODE. */ | |
12154 | ||
12155 | static void | |
12156 | emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val) | |
12157 | { | |
12158 | rtx (*fn) (rtx, rtx, rtx) = NULL; | |
12159 | if (mode == SImode) | |
12160 | fn = gen_store_conditional_si; | |
12161 | else if (mode == DImode) | |
12162 | fn = gen_store_conditional_di; | |
12163 | ||
9f0076e5 | 12164 | /* Emit sync before stwcx. to address PPC405 Erratum. */ |
b52110d4 DE |
12165 | if (PPC405_ERRATUM77) |
12166 | emit_insn (gen_memory_barrier ()); | |
12167 | ||
12168 | emit_insn (fn (res, mem, val)); | |
12169 | } | |
12170 | ||
9f0076e5 | 12171 | /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation |
bb8df8a6 | 12172 | to perform. MEM is the memory on which to operate. VAL is the second |
9f0076e5 DE |
12173 | operand of the binary operator. BEFORE and AFTER are optional locations to |
12174 | return the value of MEM either before of after the operation. SCRATCH is | |
12175 | a scratch register. */ | |
12176 | ||
12177 | void | |
12178 | rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val, | |
12179 | rtx before, rtx after, rtx scratch) | |
12180 | { | |
12181 | enum machine_mode mode = GET_MODE (mem); | |
12182 | rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); | |
12183 | ||
12184 | emit_insn (gen_memory_barrier ()); | |
12185 | ||
12186 | label = gen_label_rtx (); | |
12187 | emit_label (label); | |
12188 | label = gen_rtx_LABEL_REF (VOIDmode, label); | |
12189 | ||
12190 | if (before == NULL_RTX) | |
12191 | before = scratch; | |
12192 | emit_load_locked (mode, before, mem); | |
12193 | ||
12194 | if (code == NOT) | |
12195 | x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val); | |
12196 | else if (code == AND) | |
12197 | x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND); | |
12198 | else | |
12199 | x = gen_rtx_fmt_ee (code, mode, before, val); | |
12200 | ||
12201 | if (after != NULL_RTX) | |
12202 | emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x))); | |
12203 | emit_insn (gen_rtx_SET (VOIDmode, scratch, x)); | |
12204 | ||
12205 | emit_store_conditional (mode, cond, mem, scratch); | |
12206 | ||
12207 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
12208 | emit_unlikely_jump (x, label); | |
12209 | ||
12210 | emit_insn (gen_isync ()); | |
12211 | } | |
12212 | ||
b52110d4 DE |
12213 | /* Expand an atomic compare and swap operation. MEM is the memory on which |
12214 | to operate. OLDVAL is the old value to be compared. NEWVAL is the new | |
12215 | value to be stored. SCRATCH is a scratch GPR. */ | |
12216 | ||
12217 | void | |
12218 | rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval, | |
12219 | rtx scratch) | |
12220 | { | |
12221 | enum machine_mode mode = GET_MODE (mem); | |
12222 | rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); | |
12223 | ||
12224 | emit_insn (gen_memory_barrier ()); | |
12225 | ||
12226 | label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
12227 | label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
12228 | emit_label (XEXP (label1, 0)); | |
12229 | ||
12230 | emit_load_locked (mode, retval, mem); | |
12231 | ||
12232 | x = gen_rtx_COMPARE (CCmode, retval, oldval); | |
12233 | emit_insn (gen_rtx_SET (VOIDmode, cond, x)); | |
12234 | ||
12235 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
12236 | emit_unlikely_jump (x, label2); | |
12237 | ||
12238 | emit_move_insn (scratch, newval); | |
12239 | emit_store_conditional (mode, cond, mem, scratch); | |
12240 | ||
12241 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
12242 | emit_unlikely_jump (x, label1); | |
12243 | ||
12244 | emit_insn (gen_isync ()); | |
12245 | emit_label (XEXP (label2, 0)); | |
12246 | } | |
12247 | ||
12248 | /* Expand an atomic test and set operation. MEM is the memory on which | |
12249 | to operate. VAL is the value set. SCRATCH is a scratch GPR. */ | |
12250 | ||
12251 | void | |
12252 | rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch) | |
12253 | { | |
12254 | enum machine_mode mode = GET_MODE (mem); | |
12255 | rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); | |
12256 | ||
12257 | emit_insn (gen_memory_barrier ()); | |
12258 | ||
12259 | label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
12260 | emit_label (XEXP (label, 0)); | |
12261 | ||
12262 | emit_load_locked (mode, retval, mem); | |
12263 | emit_move_insn (scratch, val); | |
12264 | emit_store_conditional (mode, cond, mem, scratch); | |
12265 | ||
12266 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
12267 | emit_unlikely_jump (x, label); | |
12268 | ||
12269 | emit_insn (gen_isync ()); | |
12270 | } | |
12271 | ||
12272 | /* Emit instructions to move SRC to DST. Called by splitters for | |
a9baceb1 GK |
12273 | multi-register moves. It will emit at most one instruction for |
12274 | each register that is accessed; that is, it won't emit li/lis pairs | |
12275 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
12276 | register. */ | |
46c07df8 | 12277 | |
46c07df8 | 12278 | void |
a9baceb1 | 12279 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 12280 | { |
a9baceb1 GK |
12281 | /* The register number of the first register being moved. */ |
12282 | int reg; | |
12283 | /* The mode that is to be moved. */ | |
12284 | enum machine_mode mode; | |
12285 | /* The mode that the move is being done in, and its size. */ | |
12286 | enum machine_mode reg_mode; | |
12287 | int reg_mode_size; | |
12288 | /* The number of registers that will be moved. */ | |
12289 | int nregs; | |
12290 | ||
12291 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
12292 | mode = GET_MODE (dst); | |
c8b622ff | 12293 | nregs = hard_regno_nregs[reg][mode]; |
a9baceb1 GK |
12294 | if (FP_REGNO_P (reg)) |
12295 | reg_mode = DFmode; | |
12296 | else if (ALTIVEC_REGNO_P (reg)) | |
12297 | reg_mode = V16QImode; | |
12298 | else | |
12299 | reg_mode = word_mode; | |
12300 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
f676971a | 12301 | |
37409796 | 12302 | gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode)); |
f676971a | 12303 | |
a9baceb1 GK |
12304 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) |
12305 | { | |
12306 | /* Move register range backwards, if we might have destructive | |
12307 | overlap. */ | |
12308 | int i; | |
12309 | for (i = nregs - 1; i >= 0; i--) | |
f676971a | 12310 | emit_insn (gen_rtx_SET (VOIDmode, |
a9baceb1 GK |
12311 | simplify_gen_subreg (reg_mode, dst, mode, |
12312 | i * reg_mode_size), | |
12313 | simplify_gen_subreg (reg_mode, src, mode, | |
12314 | i * reg_mode_size))); | |
12315 | } | |
46c07df8 HP |
12316 | else |
12317 | { | |
a9baceb1 GK |
12318 | int i; |
12319 | int j = -1; | |
12320 | bool used_update = false; | |
46c07df8 | 12321 | |
c1e55850 | 12322 | if (MEM_P (src) && INT_REGNO_P (reg)) |
c4ad648e AM |
12323 | { |
12324 | rtx breg; | |
3a1f863f | 12325 | |
a9baceb1 GK |
12326 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
12327 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
12328 | { |
12329 | rtx delta_rtx; | |
a9baceb1 | 12330 | breg = XEXP (XEXP (src, 0), 0); |
c4ad648e AM |
12331 | delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC |
12332 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
12333 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)))); | |
a9baceb1 GK |
12334 | emit_insn (TARGET_32BIT |
12335 | ? gen_addsi3 (breg, breg, delta_rtx) | |
12336 | : gen_adddi3 (breg, breg, delta_rtx)); | |
13e2e16e | 12337 | src = replace_equiv_address (src, breg); |
3a1f863f | 12338 | } |
c1e55850 GK |
12339 | else if (! offsettable_memref_p (src)) |
12340 | { | |
13e2e16e | 12341 | rtx basereg; |
c1e55850 GK |
12342 | basereg = gen_rtx_REG (Pmode, reg); |
12343 | emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0))); | |
13e2e16e | 12344 | src = replace_equiv_address (src, basereg); |
c1e55850 | 12345 | } |
3a1f863f | 12346 | |
0423421f AM |
12347 | breg = XEXP (src, 0); |
12348 | if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM) | |
12349 | breg = XEXP (breg, 0); | |
12350 | ||
12351 | /* If the base register we are using to address memory is | |
12352 | also a destination reg, then change that register last. */ | |
12353 | if (REG_P (breg) | |
12354 | && REGNO (breg) >= REGNO (dst) | |
3a1f863f DE |
12355 | && REGNO (breg) < REGNO (dst) + nregs) |
12356 | j = REGNO (breg) - REGNO (dst); | |
c4ad648e | 12357 | } |
46c07df8 | 12358 | |
a9baceb1 | 12359 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
12360 | { |
12361 | rtx breg; | |
12362 | ||
a9baceb1 GK |
12363 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
12364 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
12365 | { |
12366 | rtx delta_rtx; | |
a9baceb1 | 12367 | breg = XEXP (XEXP (dst, 0), 0); |
c4ad648e AM |
12368 | delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC |
12369 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
12370 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)))); | |
3a1f863f DE |
12371 | |
12372 | /* We have to update the breg before doing the store. | |
12373 | Use store with update, if available. */ | |
12374 | ||
12375 | if (TARGET_UPDATE) | |
12376 | { | |
a9baceb1 | 12377 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
c4ad648e AM |
12378 | emit_insn (TARGET_32BIT |
12379 | ? (TARGET_POWERPC64 | |
12380 | ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc) | |
12381 | : gen_movsi_update (breg, breg, delta_rtx, nsrc)) | |
12382 | : gen_movdi_di_update (breg, breg, delta_rtx, nsrc)); | |
a9baceb1 | 12383 | used_update = true; |
3a1f863f DE |
12384 | } |
12385 | else | |
a9baceb1 GK |
12386 | emit_insn (TARGET_32BIT |
12387 | ? gen_addsi3 (breg, breg, delta_rtx) | |
12388 | : gen_adddi3 (breg, breg, delta_rtx)); | |
13e2e16e | 12389 | dst = replace_equiv_address (dst, breg); |
3a1f863f | 12390 | } |
37409796 NS |
12391 | else |
12392 | gcc_assert (offsettable_memref_p (dst)); | |
3a1f863f DE |
12393 | } |
12394 | ||
46c07df8 | 12395 | for (i = 0; i < nregs; i++) |
f676971a | 12396 | { |
3a1f863f DE |
12397 | /* Calculate index to next subword. */ |
12398 | ++j; | |
f676971a | 12399 | if (j == nregs) |
3a1f863f | 12400 | j = 0; |
46c07df8 | 12401 | |
112cdef5 | 12402 | /* If compiler already emitted move of first word by |
a9baceb1 | 12403 | store with update, no need to do anything. */ |
3a1f863f | 12404 | if (j == 0 && used_update) |
a9baceb1 | 12405 | continue; |
f676971a | 12406 | |
a9baceb1 GK |
12407 | emit_insn (gen_rtx_SET (VOIDmode, |
12408 | simplify_gen_subreg (reg_mode, dst, mode, | |
12409 | j * reg_mode_size), | |
12410 | simplify_gen_subreg (reg_mode, src, mode, | |
12411 | j * reg_mode_size))); | |
3a1f863f | 12412 | } |
46c07df8 HP |
12413 | } |
12414 | } | |
12415 | ||
12a4e8c5 | 12416 | \f |
a4f6c312 SS |
12417 | /* This page contains routines that are used to determine what the |
12418 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 12419 | |
a4f6c312 SS |
12420 | /* Return the first fixed-point register that is required to be |
12421 | saved. 32 if none. */ | |
9878760c RK |
12422 | |
12423 | int | |
863d938c | 12424 | first_reg_to_save (void) |
9878760c RK |
12425 | { |
12426 | int first_reg; | |
12427 | ||
12428 | /* Find lowest numbered live register. */ | |
12429 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
f676971a | 12430 | if (regs_ever_live[first_reg] |
a38d360d | 12431 | && (! call_used_regs[first_reg] |
1db02437 | 12432 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 12433 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
b4db40bf JJ |
12434 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) |
12435 | || (TARGET_TOC && TARGET_MINIMAL_TOC))))) | |
9878760c RK |
12436 | break; |
12437 | ||
ee890fe2 | 12438 | #if TARGET_MACHO |
93638d7a AM |
12439 | if (flag_pic |
12440 | && current_function_uses_pic_offset_table | |
12441 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 12442 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
12443 | #endif |
12444 | ||
9878760c RK |
12445 | return first_reg; |
12446 | } | |
12447 | ||
12448 | /* Similar, for FP regs. */ | |
12449 | ||
12450 | int | |
863d938c | 12451 | first_fp_reg_to_save (void) |
9878760c RK |
12452 | { |
12453 | int first_reg; | |
12454 | ||
12455 | /* Find lowest numbered live register. */ | |
12456 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
12457 | if (regs_ever_live[first_reg]) | |
12458 | break; | |
12459 | ||
12460 | return first_reg; | |
12461 | } | |
00b960c7 AH |
12462 | |
12463 | /* Similar, for AltiVec regs. */ | |
12464 | ||
12465 | static int | |
863d938c | 12466 | first_altivec_reg_to_save (void) |
00b960c7 AH |
12467 | { |
12468 | int i; | |
12469 | ||
12470 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
12471 | if (! TARGET_ALTIVEC_ABI) | |
12472 | return LAST_ALTIVEC_REGNO + 1; | |
12473 | ||
12474 | /* Find lowest numbered live register. */ | |
12475 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
12476 | if (regs_ever_live[i]) | |
12477 | break; | |
12478 | ||
12479 | return i; | |
12480 | } | |
12481 | ||
12482 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
12483 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
12484 | the 32-bit word is 0. */ | |
12485 | ||
12486 | static unsigned int | |
863d938c | 12487 | compute_vrsave_mask (void) |
00b960c7 AH |
12488 | { |
12489 | unsigned int i, mask = 0; | |
12490 | ||
12491 | /* First, find out if we use _any_ altivec registers. */ | |
12492 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
12493 | if (regs_ever_live[i]) | |
12494 | mask |= ALTIVEC_REG_BIT (i); | |
12495 | ||
12496 | if (mask == 0) | |
12497 | return mask; | |
12498 | ||
00b960c7 AH |
12499 | /* Next, remove the argument registers from the set. These must |
12500 | be in the VRSAVE mask set by the caller, so we don't need to add | |
12501 | them in again. More importantly, the mask we compute here is | |
12502 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
12503 | wish the argument registers to die. */ | |
a6cf80f2 | 12504 | for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
12505 | mask &= ~ALTIVEC_REG_BIT (i); |
12506 | ||
12507 | /* Similarly, remove the return value from the set. */ | |
12508 | { | |
12509 | bool yes = false; | |
12510 | diddle_return_value (is_altivec_return_reg, &yes); | |
12511 | if (yes) | |
12512 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
12513 | } | |
12514 | ||
12515 | return mask; | |
12516 | } | |
12517 | ||
d62294f5 | 12518 | /* For a very restricted set of circumstances, we can cut down the |
f57fe068 AM |
12519 | size of prologues/epilogues by calling our own save/restore-the-world |
12520 | routines. */ | |
d62294f5 FJ |
12521 | |
12522 | static void | |
f57fe068 AM |
12523 | compute_save_world_info (rs6000_stack_t *info_ptr) |
12524 | { | |
12525 | info_ptr->world_save_p = 1; | |
12526 | info_ptr->world_save_p | |
12527 | = (WORLD_SAVE_P (info_ptr) | |
12528 | && DEFAULT_ABI == ABI_DARWIN | |
12529 | && ! (current_function_calls_setjmp && flag_exceptions) | |
12530 | && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO | |
12531 | && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO | |
12532 | && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO | |
12533 | && info_ptr->cr_save_p); | |
f676971a | 12534 | |
d62294f5 FJ |
12535 | /* This will not work in conjunction with sibcalls. Make sure there |
12536 | are none. (This check is expensive, but seldom executed.) */ | |
f57fe068 | 12537 | if (WORLD_SAVE_P (info_ptr)) |
f676971a | 12538 | { |
d62294f5 FJ |
12539 | rtx insn; |
12540 | for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) | |
c4ad648e AM |
12541 | if ( GET_CODE (insn) == CALL_INSN |
12542 | && SIBLING_CALL_P (insn)) | |
12543 | { | |
12544 | info_ptr->world_save_p = 0; | |
12545 | break; | |
12546 | } | |
d62294f5 | 12547 | } |
f676971a | 12548 | |
f57fe068 | 12549 | if (WORLD_SAVE_P (info_ptr)) |
d62294f5 FJ |
12550 | { |
12551 | /* Even if we're not touching VRsave, make sure there's room on the | |
12552 | stack for it, if it looks like we're calling SAVE_WORLD, which | |
c4ad648e | 12553 | will attempt to save it. */ |
d62294f5 FJ |
12554 | info_ptr->vrsave_size = 4; |
12555 | ||
12556 | /* "Save" the VRsave register too if we're saving the world. */ | |
12557 | if (info_ptr->vrsave_mask == 0) | |
c4ad648e | 12558 | info_ptr->vrsave_mask = compute_vrsave_mask (); |
d62294f5 FJ |
12559 | |
12560 | /* Because the Darwin register save/restore routines only handle | |
c4ad648e | 12561 | F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency |
992d08b1 | 12562 | check. */ |
37409796 NS |
12563 | gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO |
12564 | && (info_ptr->first_altivec_reg_save | |
12565 | >= FIRST_SAVED_ALTIVEC_REGNO)); | |
d62294f5 | 12566 | } |
f676971a | 12567 | return; |
d62294f5 FJ |
12568 | } |
12569 | ||
12570 | ||
00b960c7 | 12571 | static void |
a2369ed3 | 12572 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
12573 | { |
12574 | bool *yes = (bool *) xyes; | |
12575 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
12576 | *yes = true; | |
12577 | } | |
12578 | ||
4697a36c MM |
12579 | \f |
12580 | /* Calculate the stack information for the current function. This is | |
12581 | complicated by having two separate calling sequences, the AIX calling | |
12582 | sequence and the V.4 calling sequence. | |
12583 | ||
592696dd | 12584 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 12585 | 32-bit 64-bit |
4697a36c | 12586 | SP----> +---------------------------------------+ |
a260abc9 | 12587 | | back chain to caller | 0 0 |
4697a36c | 12588 | +---------------------------------------+ |
a260abc9 | 12589 | | saved CR | 4 8 (8-11) |
4697a36c | 12590 | +---------------------------------------+ |
a260abc9 | 12591 | | saved LR | 8 16 |
4697a36c | 12592 | +---------------------------------------+ |
a260abc9 | 12593 | | reserved for compilers | 12 24 |
4697a36c | 12594 | +---------------------------------------+ |
a260abc9 | 12595 | | reserved for binders | 16 32 |
4697a36c | 12596 | +---------------------------------------+ |
a260abc9 | 12597 | | saved TOC pointer | 20 40 |
4697a36c | 12598 | +---------------------------------------+ |
a260abc9 | 12599 | | Parameter save area (P) | 24 48 |
4697a36c | 12600 | +---------------------------------------+ |
a260abc9 | 12601 | | Alloca space (A) | 24+P etc. |
802a0058 | 12602 | +---------------------------------------+ |
a7df97e6 | 12603 | | Local variable space (L) | 24+P+A |
4697a36c | 12604 | +---------------------------------------+ |
a7df97e6 | 12605 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 12606 | +---------------------------------------+ |
00b960c7 AH |
12607 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
12608 | +---------------------------------------+ | |
12609 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
12610 | +---------------------------------------+ | |
12611 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 12612 | +---------------------------------------+ |
00b960c7 AH |
12613 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
12614 | +---------------------------------------+ | |
12615 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
12616 | +---------------------------------------+ |
12617 | old SP->| back chain to caller's caller | | |
12618 | +---------------------------------------+ | |
12619 | ||
5376a30c KR |
12620 | The required alignment for AIX configurations is two words (i.e., 8 |
12621 | or 16 bytes). | |
12622 | ||
12623 | ||
4697a36c MM |
12624 | V.4 stack frames look like: |
12625 | ||
12626 | SP----> +---------------------------------------+ | |
12627 | | back chain to caller | 0 | |
12628 | +---------------------------------------+ | |
5eb387b8 | 12629 | | caller's saved LR | 4 |
4697a36c MM |
12630 | +---------------------------------------+ |
12631 | | Parameter save area (P) | 8 | |
12632 | +---------------------------------------+ | |
a7df97e6 | 12633 | | Alloca space (A) | 8+P |
f676971a | 12634 | +---------------------------------------+ |
a7df97e6 | 12635 | | Varargs save area (V) | 8+P+A |
f676971a | 12636 | +---------------------------------------+ |
a7df97e6 | 12637 | | Local variable space (L) | 8+P+A+V |
f676971a | 12638 | +---------------------------------------+ |
a7df97e6 | 12639 | | Float/int conversion temporary (X) | 8+P+A+V+L |
4697a36c | 12640 | +---------------------------------------+ |
00b960c7 AH |
12641 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
12642 | +---------------------------------------+ | |
12643 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
12644 | +---------------------------------------+ | |
12645 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
12646 | +---------------------------------------+ | |
c4ad648e AM |
12647 | | SPE: area for 64-bit GP registers | |
12648 | +---------------------------------------+ | |
12649 | | SPE alignment padding | | |
12650 | +---------------------------------------+ | |
00b960c7 | 12651 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
f676971a | 12652 | +---------------------------------------+ |
00b960c7 | 12653 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
f676971a | 12654 | +---------------------------------------+ |
00b960c7 | 12655 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
12656 | +---------------------------------------+ |
12657 | old SP->| back chain to caller's caller | | |
12658 | +---------------------------------------+ | |
b6c9286a | 12659 | |
5376a30c KR |
12660 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
12661 | given. (But note below and in sysv4.h that we require only 8 and | |
12662 | may round up the size of our stack frame anyways. The historical | |
12663 | reason is early versions of powerpc-linux which didn't properly | |
12664 | align the stack at program startup. A happy side-effect is that | |
12665 | -mno-eabi libraries can be used with -meabi programs.) | |
12666 | ||
50d440bc | 12667 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
12668 | the stack alignment requirements may differ. If -mno-eabi is not |
12669 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
12670 | given, the required alignment is 16 bytes. (But see V.4 comment | |
12671 | above.) */ | |
4697a36c | 12672 | |
61b2fbe7 MM |
12673 | #ifndef ABI_STACK_BOUNDARY |
12674 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
12675 | #endif | |
12676 | ||
d1d0c603 | 12677 | static rs6000_stack_t * |
863d938c | 12678 | rs6000_stack_info (void) |
4697a36c | 12679 | { |
022123e6 | 12680 | static rs6000_stack_t info; |
4697a36c | 12681 | rs6000_stack_t *info_ptr = &info; |
327e5343 | 12682 | int reg_size = TARGET_32BIT ? 4 : 8; |
83720594 | 12683 | int ehrd_size; |
64045029 | 12684 | int save_align; |
44688022 | 12685 | HOST_WIDE_INT non_fixed_size; |
4697a36c | 12686 | |
022123e6 | 12687 | memset (&info, 0, sizeof (info)); |
4697a36c | 12688 | |
c19de7aa AH |
12689 | if (TARGET_SPE) |
12690 | { | |
12691 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f | 12692 | if (cfun->machine->insn_chain_scanned_p == 0) |
b5a5beb9 AH |
12693 | cfun->machine->insn_chain_scanned_p |
12694 | = spe_func_has_64bit_regs_p () + 1; | |
12695 | info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1; | |
c19de7aa AH |
12696 | } |
12697 | ||
a4f6c312 | 12698 | /* Select which calling sequence. */ |
178274da | 12699 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 12700 | |
a4f6c312 | 12701 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 12702 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
f676971a | 12703 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 12704 | even if it currently looks like we won't. */ |
2bfcf297 | 12705 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
12706 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
12707 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
12708 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
12709 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
12710 | else |
12711 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 12712 | |
a3170dc6 AH |
12713 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
12714 | Ideally we should save the entire 64-bits only when the upper | |
12715 | half is used in SIMD instructions. Since we only record | |
12716 | registers live (not the size they are used in), this proves | |
12717 | difficult because we'd have to traverse the instruction chain at | |
12718 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
12719 | so we opt to save the GPRs in 64-bits always if but one register |
12720 | gets used in 64-bits. Otherwise, all the registers in the frame | |
12721 | get saved in 32-bits. | |
a3170dc6 | 12722 | |
c19de7aa | 12723 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 12724 | traditional GP save area will be empty. */ |
c19de7aa | 12725 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12726 | info_ptr->gp_size = 0; |
12727 | ||
4697a36c MM |
12728 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
12729 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
12730 | ||
00b960c7 AH |
12731 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
12732 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
12733 | - info_ptr->first_altivec_reg_save); | |
12734 | ||
592696dd | 12735 | /* Does this function call anything? */ |
71f123ca FS |
12736 | info_ptr->calls_p = (! current_function_is_leaf |
12737 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 12738 | |
a4f6c312 | 12739 | /* Determine if we need to save the link register. */ |
022123e6 AM |
12740 | if ((DEFAULT_ABI == ABI_AIX |
12741 | && current_function_profile | |
12742 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
12743 | #ifdef TARGET_RELOCATABLE |
12744 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
12745 | #endif | |
12746 | || (info_ptr->first_fp_reg_save != 64 | |
12747 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 12748 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 12749 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
022123e6 AM |
12750 | || info_ptr->calls_p |
12751 | || rs6000_ra_ever_killed ()) | |
4697a36c MM |
12752 | { |
12753 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 12754 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
12755 | } |
12756 | ||
9ebbca7d | 12757 | /* Determine if we need to save the condition code registers. */ |
f676971a | 12758 | if (regs_ever_live[CR2_REGNO] |
9ebbca7d GK |
12759 | || regs_ever_live[CR3_REGNO] |
12760 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
12761 | { |
12762 | info_ptr->cr_save_p = 1; | |
178274da | 12763 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
12764 | info_ptr->cr_size = reg_size; |
12765 | } | |
12766 | ||
83720594 RH |
12767 | /* If the current function calls __builtin_eh_return, then we need |
12768 | to allocate stack space for registers that will hold data for | |
12769 | the exception handler. */ | |
12770 | if (current_function_calls_eh_return) | |
12771 | { | |
12772 | unsigned int i; | |
12773 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
12774 | continue; | |
a3170dc6 AH |
12775 | |
12776 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
12777 | ehrd_size = i * (TARGET_SPE_ABI |
12778 | && info_ptr->spe_64bit_regs_used != 0 | |
12779 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
12780 | } |
12781 | else | |
12782 | ehrd_size = 0; | |
12783 | ||
592696dd | 12784 | /* Determine various sizes. */ |
4697a36c MM |
12785 | info_ptr->reg_size = reg_size; |
12786 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
189e03e3 | 12787 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 | 12788 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
03e007d7 | 12789 | TARGET_ALTIVEC ? 16 : 8); |
7d5175e1 JJ |
12790 | if (FRAME_GROWS_DOWNWARD) |
12791 | info_ptr->vars_size | |
5b667039 JJ |
12792 | += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size |
12793 | + info_ptr->parm_size, | |
7d5175e1 | 12794 | ABI_STACK_BOUNDARY / BITS_PER_UNIT) |
5b667039 JJ |
12795 | - (info_ptr->fixed_size + info_ptr->vars_size |
12796 | + info_ptr->parm_size); | |
00b960c7 | 12797 | |
c19de7aa | 12798 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12799 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
12800 | else | |
12801 | info_ptr->spe_gp_size = 0; | |
12802 | ||
4d774ff8 HP |
12803 | if (TARGET_ALTIVEC_ABI) |
12804 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 12805 | else |
4d774ff8 HP |
12806 | info_ptr->vrsave_mask = 0; |
12807 | ||
12808 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
12809 | info_ptr->vrsave_size = 4; | |
12810 | else | |
12811 | info_ptr->vrsave_size = 0; | |
b6c9286a | 12812 | |
d62294f5 FJ |
12813 | compute_save_world_info (info_ptr); |
12814 | ||
592696dd | 12815 | /* Calculate the offsets. */ |
178274da | 12816 | switch (DEFAULT_ABI) |
4697a36c | 12817 | { |
b6c9286a | 12818 | case ABI_NONE: |
24d304eb | 12819 | default: |
37409796 | 12820 | gcc_unreachable (); |
b6c9286a MM |
12821 | |
12822 | case ABI_AIX: | |
ee890fe2 | 12823 | case ABI_DARWIN: |
b6c9286a MM |
12824 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
12825 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
12826 | |
12827 | if (TARGET_ALTIVEC_ABI) | |
12828 | { | |
12829 | info_ptr->vrsave_save_offset | |
12830 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
12831 | ||
12832 | /* Align stack so vector save area is on a quadword boundary. */ | |
12833 | if (info_ptr->altivec_size != 0) | |
12834 | info_ptr->altivec_padding_size | |
12835 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
12836 | else | |
12837 | info_ptr->altivec_padding_size = 0; | |
12838 | ||
12839 | info_ptr->altivec_save_offset | |
12840 | = info_ptr->vrsave_save_offset | |
12841 | - info_ptr->altivec_padding_size | |
12842 | - info_ptr->altivec_size; | |
12843 | ||
12844 | /* Adjust for AltiVec case. */ | |
12845 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
12846 | } | |
12847 | else | |
12848 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
12849 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
12850 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
12851 | break; |
12852 | ||
12853 | case ABI_V4: | |
b6c9286a MM |
12854 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
12855 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 12856 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 12857 | |
c19de7aa | 12858 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
c4ad648e AM |
12859 | { |
12860 | /* Align stack so SPE GPR save area is aligned on a | |
12861 | double-word boundary. */ | |
12862 | if (info_ptr->spe_gp_size != 0) | |
12863 | info_ptr->spe_padding_size | |
12864 | = 8 - (-info_ptr->cr_save_offset % 8); | |
12865 | else | |
12866 | info_ptr->spe_padding_size = 0; | |
12867 | ||
12868 | info_ptr->spe_gp_save_offset | |
12869 | = info_ptr->cr_save_offset | |
12870 | - info_ptr->spe_padding_size | |
12871 | - info_ptr->spe_gp_size; | |
12872 | ||
12873 | /* Adjust for SPE case. */ | |
022123e6 | 12874 | info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset; |
c4ad648e | 12875 | } |
a3170dc6 | 12876 | else if (TARGET_ALTIVEC_ABI) |
00b960c7 AH |
12877 | { |
12878 | info_ptr->vrsave_save_offset | |
12879 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
12880 | ||
12881 | /* Align stack so vector save area is on a quadword boundary. */ | |
12882 | if (info_ptr->altivec_size != 0) | |
12883 | info_ptr->altivec_padding_size | |
12884 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
12885 | else | |
12886 | info_ptr->altivec_padding_size = 0; | |
12887 | ||
12888 | info_ptr->altivec_save_offset | |
12889 | = info_ptr->vrsave_save_offset | |
12890 | - info_ptr->altivec_padding_size | |
12891 | - info_ptr->altivec_size; | |
12892 | ||
12893 | /* Adjust for AltiVec case. */ | |
022123e6 | 12894 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset; |
00b960c7 AH |
12895 | } |
12896 | else | |
022123e6 AM |
12897 | info_ptr->ehrd_offset = info_ptr->cr_save_offset; |
12898 | info_ptr->ehrd_offset -= ehrd_size; | |
b6c9286a MM |
12899 | info_ptr->lr_save_offset = reg_size; |
12900 | break; | |
4697a36c MM |
12901 | } |
12902 | ||
64045029 | 12903 | save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8; |
00b960c7 AH |
12904 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
12905 | + info_ptr->gp_size | |
12906 | + info_ptr->altivec_size | |
12907 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
12908 | + info_ptr->spe_gp_size |
12909 | + info_ptr->spe_padding_size | |
00b960c7 AH |
12910 | + ehrd_size |
12911 | + info_ptr->cr_size | |
022123e6 | 12912 | + info_ptr->vrsave_size, |
64045029 | 12913 | save_align); |
00b960c7 | 12914 | |
44688022 | 12915 | non_fixed_size = (info_ptr->vars_size |
ff381587 | 12916 | + info_ptr->parm_size |
5b667039 | 12917 | + info_ptr->save_size); |
ff381587 | 12918 | |
44688022 AM |
12919 | info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, |
12920 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
12921 | |
12922 | /* Determine if we need to allocate any stack frame: | |
12923 | ||
a4f6c312 SS |
12924 | For AIX we need to push the stack if a frame pointer is needed |
12925 | (because the stack might be dynamically adjusted), if we are | |
12926 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
12927 | and local variables are more than the space needed to save all | |
12928 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
12929 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 12930 | |
a4f6c312 SS |
12931 | For V.4 we don't have the stack cushion that AIX uses, but assume |
12932 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
12933 | |
12934 | if (info_ptr->calls_p) | |
12935 | info_ptr->push_p = 1; | |
12936 | ||
178274da | 12937 | else if (DEFAULT_ABI == ABI_V4) |
44688022 | 12938 | info_ptr->push_p = non_fixed_size != 0; |
ff381587 | 12939 | |
178274da AM |
12940 | else if (frame_pointer_needed) |
12941 | info_ptr->push_p = 1; | |
12942 | ||
12943 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
12944 | info_ptr->push_p = 1; | |
12945 | ||
ff381587 | 12946 | else |
44688022 | 12947 | info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); |
ff381587 | 12948 | |
a4f6c312 | 12949 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 12950 | if (info_ptr->fp_size == 0) |
4697a36c MM |
12951 | info_ptr->fp_save_offset = 0; |
12952 | ||
8dda1a21 | 12953 | if (info_ptr->gp_size == 0) |
4697a36c MM |
12954 | info_ptr->gp_save_offset = 0; |
12955 | ||
00b960c7 AH |
12956 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
12957 | info_ptr->altivec_save_offset = 0; | |
12958 | ||
12959 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
12960 | info_ptr->vrsave_save_offset = 0; | |
12961 | ||
c19de7aa AH |
12962 | if (! TARGET_SPE_ABI |
12963 | || info_ptr->spe_64bit_regs_used == 0 | |
12964 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
12965 | info_ptr->spe_gp_save_offset = 0; |
12966 | ||
c81fc13e | 12967 | if (! info_ptr->lr_save_p) |
4697a36c MM |
12968 | info_ptr->lr_save_offset = 0; |
12969 | ||
c81fc13e | 12970 | if (! info_ptr->cr_save_p) |
4697a36c MM |
12971 | info_ptr->cr_save_offset = 0; |
12972 | ||
12973 | return info_ptr; | |
12974 | } | |
12975 | ||
c19de7aa AH |
12976 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
12977 | mode. */ | |
12978 | ||
12979 | static bool | |
863d938c | 12980 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
12981 | { |
12982 | rtx insns, insn; | |
12983 | ||
12984 | /* Functions that save and restore all the call-saved registers will | |
12985 | need to save/restore the registers in 64-bits. */ | |
12986 | if (current_function_calls_eh_return | |
12987 | || current_function_calls_setjmp | |
12988 | || current_function_has_nonlocal_goto) | |
12989 | return true; | |
12990 | ||
12991 | insns = get_insns (); | |
12992 | ||
12993 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
12994 | { | |
12995 | if (INSN_P (insn)) | |
12996 | { | |
12997 | rtx i; | |
12998 | ||
b5a5beb9 AH |
12999 | /* FIXME: This should be implemented with attributes... |
13000 | ||
13001 | (set_attr "spe64" "true")....then, | |
13002 | if (get_spe64(insn)) return true; | |
13003 | ||
13004 | It's the only reliable way to do the stuff below. */ | |
13005 | ||
c19de7aa | 13006 | i = PATTERN (insn); |
f82f556d AH |
13007 | if (GET_CODE (i) == SET) |
13008 | { | |
13009 | enum machine_mode mode = GET_MODE (SET_SRC (i)); | |
13010 | ||
13011 | if (SPE_VECTOR_MODE (mode)) | |
13012 | return true; | |
13013 | if (TARGET_E500_DOUBLE && mode == DFmode) | |
13014 | return true; | |
13015 | } | |
c19de7aa AH |
13016 | } |
13017 | } | |
13018 | ||
13019 | return false; | |
13020 | } | |
13021 | ||
d1d0c603 | 13022 | static void |
a2369ed3 | 13023 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 13024 | { |
d330fd93 | 13025 | const char *abi_string; |
24d304eb | 13026 | |
c81fc13e | 13027 | if (! info) |
4697a36c MM |
13028 | info = rs6000_stack_info (); |
13029 | ||
13030 | fprintf (stderr, "\nStack information for function %s:\n", | |
13031 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
13032 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
13033 | : "<unknown>")); | |
13034 | ||
24d304eb RK |
13035 | switch (info->abi) |
13036 | { | |
b6c9286a MM |
13037 | default: abi_string = "Unknown"; break; |
13038 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 13039 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 13040 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 13041 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
13042 | } |
13043 | ||
13044 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
13045 | ||
00b960c7 AH |
13046 | if (TARGET_ALTIVEC_ABI) |
13047 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
13048 | ||
a3170dc6 AH |
13049 | if (TARGET_SPE_ABI) |
13050 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
13051 | ||
4697a36c MM |
13052 | if (info->first_gp_reg_save != 32) |
13053 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
13054 | ||
13055 | if (info->first_fp_reg_save != 64) | |
13056 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 13057 | |
00b960c7 AH |
13058 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
13059 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
13060 | info->first_altivec_reg_save); | |
13061 | ||
4697a36c MM |
13062 | if (info->lr_save_p) |
13063 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 13064 | |
4697a36c MM |
13065 | if (info->cr_save_p) |
13066 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
13067 | ||
00b960c7 AH |
13068 | if (info->vrsave_mask) |
13069 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
13070 | ||
4697a36c MM |
13071 | if (info->push_p) |
13072 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
13073 | ||
13074 | if (info->calls_p) | |
13075 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
13076 | ||
4697a36c MM |
13077 | if (info->gp_save_offset) |
13078 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
13079 | ||
13080 | if (info->fp_save_offset) | |
13081 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
13082 | ||
00b960c7 AH |
13083 | if (info->altivec_save_offset) |
13084 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
13085 | info->altivec_save_offset); | |
13086 | ||
a3170dc6 AH |
13087 | if (info->spe_gp_save_offset) |
13088 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
13089 | info->spe_gp_save_offset); | |
13090 | ||
00b960c7 AH |
13091 | if (info->vrsave_save_offset) |
13092 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
13093 | info->vrsave_save_offset); | |
13094 | ||
4697a36c MM |
13095 | if (info->lr_save_offset) |
13096 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
13097 | ||
13098 | if (info->cr_save_offset) | |
13099 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
13100 | ||
13101 | if (info->varargs_save_offset) | |
13102 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
13103 | ||
13104 | if (info->total_size) | |
d1d0c603 JJ |
13105 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
13106 | info->total_size); | |
4697a36c | 13107 | |
4697a36c | 13108 | if (info->vars_size) |
d1d0c603 JJ |
13109 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
13110 | info->vars_size); | |
4697a36c MM |
13111 | |
13112 | if (info->parm_size) | |
13113 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
13114 | ||
13115 | if (info->fixed_size) | |
13116 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
13117 | ||
13118 | if (info->gp_size) | |
13119 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
13120 | ||
a3170dc6 AH |
13121 | if (info->spe_gp_size) |
13122 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
13123 | ||
4697a36c MM |
13124 | if (info->fp_size) |
13125 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
13126 | ||
00b960c7 AH |
13127 | if (info->altivec_size) |
13128 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
13129 | ||
13130 | if (info->vrsave_size) | |
13131 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
13132 | ||
13133 | if (info->altivec_padding_size) | |
13134 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
13135 | info->altivec_padding_size); | |
13136 | ||
a3170dc6 AH |
13137 | if (info->spe_padding_size) |
13138 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
13139 | info->spe_padding_size); | |
13140 | ||
4697a36c MM |
13141 | if (info->cr_size) |
13142 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
13143 | ||
13144 | if (info->save_size) | |
13145 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
13146 | ||
13147 | if (info->reg_size != 4) | |
13148 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
13149 | ||
13150 | fprintf (stderr, "\n"); | |
9878760c | 13151 | } |
71f123ca FS |
13152 | |
13153 | rtx | |
a2369ed3 | 13154 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 13155 | { |
a4f6c312 SS |
13156 | /* Currently we don't optimize very well between prolog and body |
13157 | code and for PIC code the code can be actually quite bad, so | |
13158 | don't try to be too clever here. */ | |
f1384257 | 13159 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
13160 | { |
13161 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
13162 | |
13163 | return | |
13164 | gen_rtx_MEM | |
13165 | (Pmode, | |
13166 | memory_address | |
13167 | (Pmode, | |
13168 | plus_constant (copy_to_reg | |
13169 | (gen_rtx_MEM (Pmode, | |
13170 | memory_address (Pmode, frame))), | |
13171 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
13172 | } |
13173 | ||
8c29550d | 13174 | cfun->machine->ra_need_lr = 1; |
9e2f7ec7 | 13175 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
13176 | } |
13177 | ||
5e1bf043 DJ |
13178 | /* Say whether a function is a candidate for sibcall handling or not. |
13179 | We do not allow indirect calls to be optimized into sibling calls. | |
13180 | Also, we can't do it if there are any vector parameters; there's | |
13181 | nowhere to put the VRsave code so it works; note that functions with | |
13182 | vector parameters are required to have a prototype, so the argument | |
13183 | type info must be available here. (The tail recursion case can work | |
13184 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 13185 | static bool |
a2369ed3 | 13186 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
13187 | { |
13188 | tree type; | |
4977bab6 | 13189 | if (decl) |
5e1bf043 DJ |
13190 | { |
13191 | if (TARGET_ALTIVEC_VRSAVE) | |
c4ad648e | 13192 | { |
4977bab6 | 13193 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
13194 | type; type = TREE_CHAIN (type)) |
13195 | { | |
c15b529f | 13196 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 13197 | return false; |
5e1bf043 | 13198 | } |
c4ad648e | 13199 | } |
5e1bf043 | 13200 | if (DEFAULT_ABI == ABI_DARWIN |
4977bab6 | 13201 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 13202 | { |
4977bab6 | 13203 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
13204 | |
13205 | if (!lookup_attribute ("longcall", attr_list) | |
13206 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 13207 | return true; |
2bcc50d0 | 13208 | } |
5e1bf043 | 13209 | } |
4977bab6 | 13210 | return false; |
5e1bf043 DJ |
13211 | } |
13212 | ||
e7e64a25 AS |
13213 | /* NULL if INSN insn is valid within a low-overhead loop. |
13214 | Otherwise return why doloop cannot be applied. | |
9419649c DE |
13215 | PowerPC uses the COUNT register for branch on table instructions. */ |
13216 | ||
e7e64a25 AS |
13217 | static const char * |
13218 | rs6000_invalid_within_doloop (rtx insn) | |
9419649c DE |
13219 | { |
13220 | if (CALL_P (insn)) | |
e7e64a25 | 13221 | return "Function call in the loop."; |
9419649c DE |
13222 | |
13223 | if (JUMP_P (insn) | |
13224 | && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
13225 | || GET_CODE (PATTERN (insn)) == ADDR_VEC)) | |
e7e64a25 | 13226 | return "Computed branch in the loop."; |
9419649c | 13227 | |
e7e64a25 | 13228 | return NULL; |
9419649c DE |
13229 | } |
13230 | ||
71f123ca | 13231 | static int |
863d938c | 13232 | rs6000_ra_ever_killed (void) |
71f123ca FS |
13233 | { |
13234 | rtx top; | |
5e1bf043 DJ |
13235 | rtx reg; |
13236 | rtx insn; | |
71f123ca | 13237 | |
dd292d0a | 13238 | if (current_function_is_thunk) |
71f123ca | 13239 | return 0; |
eb0424da | 13240 | |
36f7e964 AH |
13241 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
13242 | but this should not force saving and restoring in the | |
13243 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 13244 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 13245 | |
5e1bf043 DJ |
13246 | /* Also, the prologue can generate a store into LR that |
13247 | doesn't really count, like this: | |
36f7e964 | 13248 | |
5e1bf043 DJ |
13249 | move LR->R0 |
13250 | bcl to set PIC register | |
13251 | move LR->R31 | |
13252 | move R0->LR | |
36f7e964 AH |
13253 | |
13254 | When we're called from the epilogue, we need to avoid counting | |
13255 | this as a store. */ | |
f676971a | 13256 | |
71f123ca FS |
13257 | push_topmost_sequence (); |
13258 | top = get_insns (); | |
13259 | pop_topmost_sequence (); | |
5e1bf043 | 13260 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 13261 | |
5e1bf043 DJ |
13262 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
13263 | { | |
13264 | if (INSN_P (insn)) | |
13265 | { | |
022123e6 AM |
13266 | if (CALL_P (insn)) |
13267 | { | |
13268 | if (!SIBLING_CALL_P (insn)) | |
13269 | return 1; | |
13270 | } | |
13271 | else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM)) | |
5e1bf043 | 13272 | return 1; |
36f7e964 AH |
13273 | else if (set_of (reg, insn) != NULL_RTX |
13274 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
13275 | return 1; |
13276 | } | |
13277 | } | |
13278 | return 0; | |
71f123ca | 13279 | } |
4697a36c | 13280 | \f |
8cd8f856 GK |
13281 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
13282 | static void | |
a2369ed3 | 13283 | rs6000_maybe_dead (rtx insn) |
8cd8f856 GK |
13284 | { |
13285 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
13286 | const0_rtx, | |
13287 | REG_NOTES (insn)); | |
13288 | } | |
13289 | ||
9ebbca7d | 13290 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 13291 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 13292 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
13293 | |
13294 | void | |
a2369ed3 | 13295 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 13296 | { |
027fbf43 | 13297 | rtx dest, insn; |
1db02437 | 13298 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 13299 | |
7f970b70 | 13300 | if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic) |
20b71b17 | 13301 | { |
7f970b70 AM |
13302 | char buf[30]; |
13303 | rtx lab, tmp1, tmp2, got, tempLR; | |
13304 | ||
13305 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
13306 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
13307 | if (flag_pic == 2) | |
13308 | got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
13309 | else | |
13310 | got = rs6000_got_sym (); | |
13311 | tmp1 = tmp2 = dest; | |
13312 | if (!fromprolog) | |
13313 | { | |
13314 | tmp1 = gen_reg_rtx (Pmode); | |
13315 | tmp2 = gen_reg_rtx (Pmode); | |
13316 | } | |
13317 | tempLR = (fromprolog | |
13318 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
13319 | : gen_reg_rtx (Pmode)); | |
13320 | insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab)); | |
13321 | if (fromprolog) | |
13322 | rs6000_maybe_dead (insn); | |
13323 | insn = emit_move_insn (tmp1, tempLR); | |
13324 | if (fromprolog) | |
13325 | rs6000_maybe_dead (insn); | |
13326 | insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab)); | |
13327 | if (fromprolog) | |
13328 | rs6000_maybe_dead (insn); | |
13329 | insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab)); | |
13330 | if (fromprolog) | |
13331 | rs6000_maybe_dead (insn); | |
13332 | } | |
13333 | else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) | |
13334 | { | |
13335 | rtx tempLR = (fromprolog | |
13336 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
13337 | : gen_reg_rtx (Pmode)); | |
13338 | ||
13339 | insn = emit_insn (gen_load_toc_v4_pic_si (tempLR)); | |
027fbf43 JJ |
13340 | if (fromprolog) |
13341 | rs6000_maybe_dead (insn); | |
7f970b70 | 13342 | insn = emit_move_insn (dest, tempLR); |
027fbf43 JJ |
13343 | if (fromprolog) |
13344 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
13345 | } |
13346 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
13347 | { | |
13348 | char buf[30]; | |
13349 | rtx tempLR = (fromprolog | |
13350 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
13351 | : gen_reg_rtx (Pmode)); | |
13352 | rtx temp0 = (fromprolog | |
13353 | ? gen_rtx_REG (Pmode, 0) | |
13354 | : gen_reg_rtx (Pmode)); | |
20b71b17 | 13355 | |
20b71b17 AM |
13356 | if (fromprolog) |
13357 | { | |
ccbca5e4 | 13358 | rtx symF, symL; |
38c1f2d7 | 13359 | |
20b71b17 AM |
13360 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
13361 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 13362 | |
20b71b17 AM |
13363 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
13364 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
13365 | ||
13366 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
13367 | symF))); | |
13368 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
13369 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
13370 | symL, | |
13371 | symF))); | |
9ebbca7d GK |
13372 | } |
13373 | else | |
20b71b17 AM |
13374 | { |
13375 | rtx tocsym; | |
20b71b17 AM |
13376 | |
13377 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
ccbca5e4 | 13378 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym)); |
027fbf43 JJ |
13379 | emit_move_insn (dest, tempLR); |
13380 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 13381 | } |
027fbf43 JJ |
13382 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
13383 | if (fromprolog) | |
13384 | rs6000_maybe_dead (insn); | |
9ebbca7d | 13385 | } |
20b71b17 AM |
13386 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
13387 | { | |
13388 | /* This is for AIX code running in non-PIC ELF32. */ | |
13389 | char buf[30]; | |
13390 | rtx realsym; | |
13391 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
13392 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
13393 | ||
027fbf43 JJ |
13394 | insn = emit_insn (gen_elf_high (dest, realsym)); |
13395 | if (fromprolog) | |
13396 | rs6000_maybe_dead (insn); | |
13397 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
13398 | if (fromprolog) | |
13399 | rs6000_maybe_dead (insn); | |
20b71b17 | 13400 | } |
37409796 | 13401 | else |
9ebbca7d | 13402 | { |
37409796 | 13403 | gcc_assert (DEFAULT_ABI == ABI_AIX); |
bb8df8a6 | 13404 | |
9ebbca7d | 13405 | if (TARGET_32BIT) |
027fbf43 | 13406 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 13407 | else |
027fbf43 JJ |
13408 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
13409 | if (fromprolog) | |
13410 | rs6000_maybe_dead (insn); | |
9ebbca7d GK |
13411 | } |
13412 | } | |
13413 | ||
d1d0c603 JJ |
13414 | /* Emit instructions to restore the link register after determining where |
13415 | its value has been stored. */ | |
13416 | ||
13417 | void | |
13418 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
13419 | { | |
13420 | rs6000_stack_t *info = rs6000_stack_info (); | |
13421 | rtx operands[2]; | |
13422 | ||
13423 | operands[0] = source; | |
13424 | operands[1] = scratch; | |
13425 | ||
13426 | if (info->lr_save_p) | |
13427 | { | |
13428 | rtx frame_rtx = stack_pointer_rtx; | |
13429 | HOST_WIDE_INT sp_offset = 0; | |
13430 | rtx tmp; | |
13431 | ||
13432 | if (frame_pointer_needed | |
13433 | || current_function_calls_alloca | |
13434 | || info->total_size > 32767) | |
13435 | { | |
0be76840 | 13436 | tmp = gen_frame_mem (Pmode, frame_rtx); |
8308679f | 13437 | emit_move_insn (operands[1], tmp); |
d1d0c603 JJ |
13438 | frame_rtx = operands[1]; |
13439 | } | |
13440 | else if (info->push_p) | |
13441 | sp_offset = info->total_size; | |
13442 | ||
13443 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
0be76840 | 13444 | tmp = gen_frame_mem (Pmode, tmp); |
d1d0c603 JJ |
13445 | emit_move_insn (tmp, operands[0]); |
13446 | } | |
13447 | else | |
13448 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
13449 | } | |
13450 | ||
f103e34d GK |
13451 | static GTY(()) int set = -1; |
13452 | ||
f676971a | 13453 | int |
863d938c | 13454 | get_TOC_alias_set (void) |
9ebbca7d | 13455 | { |
f103e34d GK |
13456 | if (set == -1) |
13457 | set = new_alias_set (); | |
13458 | return set; | |
f676971a | 13459 | } |
9ebbca7d | 13460 | |
c1207243 | 13461 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
13462 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
13463 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 13464 | #if TARGET_ELF |
3c9eb5f4 | 13465 | static int |
f676971a | 13466 | uses_TOC (void) |
9ebbca7d | 13467 | { |
c4501e62 | 13468 | rtx insn; |
38c1f2d7 | 13469 | |
c4501e62 JJ |
13470 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
13471 | if (INSN_P (insn)) | |
13472 | { | |
13473 | rtx pat = PATTERN (insn); | |
13474 | int i; | |
9ebbca7d | 13475 | |
f676971a | 13476 | if (GET_CODE (pat) == PARALLEL) |
c4501e62 JJ |
13477 | for (i = 0; i < XVECLEN (pat, 0); i++) |
13478 | { | |
13479 | rtx sub = XVECEXP (pat, 0, i); | |
13480 | if (GET_CODE (sub) == USE) | |
13481 | { | |
13482 | sub = XEXP (sub, 0); | |
13483 | if (GET_CODE (sub) == UNSPEC | |
13484 | && XINT (sub, 1) == UNSPEC_TOC) | |
13485 | return 1; | |
13486 | } | |
13487 | } | |
13488 | } | |
13489 | return 0; | |
9ebbca7d | 13490 | } |
c954844a | 13491 | #endif |
38c1f2d7 | 13492 | |
9ebbca7d | 13493 | rtx |
f676971a | 13494 | create_TOC_reference (rtx symbol) |
9ebbca7d | 13495 | { |
f676971a | 13496 | return gen_rtx_PLUS (Pmode, |
a8a05998 | 13497 | gen_rtx_REG (Pmode, TOC_REGISTER), |
f676971a EC |
13498 | gen_rtx_CONST (Pmode, |
13499 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 13500 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 13501 | } |
38c1f2d7 | 13502 | |
fc4767bb JJ |
13503 | /* If _Unwind_* has been called from within the same module, |
13504 | toc register is not guaranteed to be saved to 40(1) on function | |
13505 | entry. Save it there in that case. */ | |
c7ca610e | 13506 | |
9ebbca7d | 13507 | void |
863d938c | 13508 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
13509 | { |
13510 | rtx mem; | |
13511 | rtx stack_top = gen_reg_rtx (Pmode); | |
13512 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
13513 | rtx opcode = gen_reg_rtx (SImode); |
13514 | rtx tocompare = gen_reg_rtx (SImode); | |
13515 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d | 13516 | |
8308679f | 13517 | mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx); |
9ebbca7d GK |
13518 | emit_move_insn (stack_top, mem); |
13519 | ||
8308679f DE |
13520 | mem = gen_frame_mem (Pmode, |
13521 | gen_rtx_PLUS (Pmode, stack_top, | |
13522 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
9ebbca7d | 13523 | emit_move_insn (opcode_addr, mem); |
fc4767bb JJ |
13524 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
13525 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 13526 | : 0xE8410028, SImode)); |
9ebbca7d | 13527 | |
fc4767bb | 13528 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 13529 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 13530 | no_toc_save_needed); |
9ebbca7d | 13531 | |
8308679f DE |
13532 | mem = gen_frame_mem (Pmode, |
13533 | gen_rtx_PLUS (Pmode, stack_top, | |
13534 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
fc4767bb JJ |
13535 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); |
13536 | emit_label (no_toc_save_needed); | |
9ebbca7d | 13537 | } |
38c1f2d7 | 13538 | \f |
0be76840 DE |
13539 | /* This ties together stack memory (MEM with an alias set of frame_alias_set) |
13540 | and the change to the stack pointer. */ | |
ba4828e0 | 13541 | |
9ebbca7d | 13542 | static void |
863d938c | 13543 | rs6000_emit_stack_tie (void) |
9ebbca7d | 13544 | { |
0be76840 DE |
13545 | rtx mem = gen_frame_mem (BLKmode, |
13546 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); | |
ba4828e0 | 13547 | |
9ebbca7d GK |
13548 | emit_insn (gen_stack_tie (mem)); |
13549 | } | |
38c1f2d7 | 13550 | |
9ebbca7d GK |
13551 | /* Emit the correct code for allocating stack space, as insns. |
13552 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
13553 | The generated code may use hard register 0 as a temporary. */ | |
13554 | ||
13555 | static void | |
a2369ed3 | 13556 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) |
38c1f2d7 | 13557 | { |
9ebbca7d GK |
13558 | rtx insn; |
13559 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
13560 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
61168ff1 RS |
13561 | rtx todec = gen_int_mode (-size, Pmode); |
13562 | ||
13563 | if (INTVAL (todec) != -size) | |
13564 | { | |
d4ee4d25 | 13565 | warning (0, "stack frame too large"); |
61168ff1 RS |
13566 | emit_insn (gen_trap ()); |
13567 | return; | |
13568 | } | |
a157febd GK |
13569 | |
13570 | if (current_function_limit_stack) | |
13571 | { | |
13572 | if (REG_P (stack_limit_rtx) | |
f676971a | 13573 | && REGNO (stack_limit_rtx) > 1 |
a157febd GK |
13574 | && REGNO (stack_limit_rtx) <= 31) |
13575 | { | |
5b71a4e7 | 13576 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
13577 | ? gen_addsi3 (tmp_reg, |
13578 | stack_limit_rtx, | |
13579 | GEN_INT (size)) | |
13580 | : gen_adddi3 (tmp_reg, | |
13581 | stack_limit_rtx, | |
13582 | GEN_INT (size))); | |
5b71a4e7 | 13583 | |
9ebbca7d GK |
13584 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
13585 | const0_rtx)); | |
a157febd GK |
13586 | } |
13587 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 13588 | && TARGET_32BIT |
f607bc57 | 13589 | && DEFAULT_ABI == ABI_V4) |
a157febd | 13590 | { |
9ebbca7d | 13591 | rtx toload = gen_rtx_CONST (VOIDmode, |
f676971a EC |
13592 | gen_rtx_PLUS (Pmode, |
13593 | stack_limit_rtx, | |
9ebbca7d | 13594 | GEN_INT (size))); |
5b71a4e7 | 13595 | |
9ebbca7d GK |
13596 | emit_insn (gen_elf_high (tmp_reg, toload)); |
13597 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
13598 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
13599 | const0_rtx)); | |
a157febd GK |
13600 | } |
13601 | else | |
d4ee4d25 | 13602 | warning (0, "stack limit expression is not supported"); |
a157febd GK |
13603 | } |
13604 | ||
9ebbca7d GK |
13605 | if (copy_r12 || ! TARGET_UPDATE) |
13606 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
13607 | ||
38c1f2d7 MM |
13608 | if (TARGET_UPDATE) |
13609 | { | |
9ebbca7d | 13610 | if (size > 32767) |
38c1f2d7 | 13611 | { |
9ebbca7d | 13612 | /* Need a note here so that try_split doesn't get confused. */ |
9390387d | 13613 | if (get_last_insn () == NULL_RTX) |
2e040219 | 13614 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d GK |
13615 | insn = emit_move_insn (tmp_reg, todec); |
13616 | try_split (PATTERN (insn), insn, 0); | |
13617 | todec = tmp_reg; | |
38c1f2d7 | 13618 | } |
5b71a4e7 DE |
13619 | |
13620 | insn = emit_insn (TARGET_32BIT | |
13621 | ? gen_movsi_update (stack_reg, stack_reg, | |
13622 | todec, stack_reg) | |
c4ad648e | 13623 | : gen_movdi_di_update (stack_reg, stack_reg, |
9ebbca7d | 13624 | todec, stack_reg)); |
38c1f2d7 MM |
13625 | } |
13626 | else | |
13627 | { | |
5b71a4e7 DE |
13628 | insn = emit_insn (TARGET_32BIT |
13629 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
13630 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
13631 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
13632 | gen_rtx_REG (Pmode, 12)); | |
13633 | } | |
f676971a | 13634 | |
9ebbca7d | 13635 | RTX_FRAME_RELATED_P (insn) = 1; |
f676971a | 13636 | REG_NOTES (insn) = |
9ebbca7d | 13637 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, |
f676971a | 13638 | gen_rtx_SET (VOIDmode, stack_reg, |
9ebbca7d GK |
13639 | gen_rtx_PLUS (Pmode, stack_reg, |
13640 | GEN_INT (-size))), | |
13641 | REG_NOTES (insn)); | |
13642 | } | |
13643 | ||
a4f6c312 SS |
13644 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
13645 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
13646 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
13647 | deduce these equivalences by itself so it wasn't necessary to hold | |
13648 | its hand so much. */ | |
9ebbca7d GK |
13649 | |
13650 | static void | |
f676971a | 13651 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
a2369ed3 | 13652 | rtx reg2, rtx rreg) |
9ebbca7d GK |
13653 | { |
13654 | rtx real, temp; | |
13655 | ||
e56c4463 JL |
13656 | /* copy_rtx will not make unique copies of registers, so we need to |
13657 | ensure we don't have unwanted sharing here. */ | |
13658 | if (reg == reg2) | |
13659 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
13660 | ||
13661 | if (reg == rreg) | |
13662 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
13663 | ||
9ebbca7d GK |
13664 | real = copy_rtx (PATTERN (insn)); |
13665 | ||
89e7058f AH |
13666 | if (reg2 != NULL_RTX) |
13667 | real = replace_rtx (real, reg2, rreg); | |
f676971a EC |
13668 | |
13669 | real = replace_rtx (real, reg, | |
9ebbca7d GK |
13670 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, |
13671 | STACK_POINTER_REGNUM), | |
13672 | GEN_INT (val))); | |
f676971a | 13673 | |
9ebbca7d GK |
13674 | /* We expect that 'real' is either a SET or a PARALLEL containing |
13675 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
13676 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
13677 | ||
13678 | if (GET_CODE (real) == SET) | |
13679 | { | |
13680 | rtx set = real; | |
f676971a | 13681 | |
9ebbca7d GK |
13682 | temp = simplify_rtx (SET_SRC (set)); |
13683 | if (temp) | |
13684 | SET_SRC (set) = temp; | |
13685 | temp = simplify_rtx (SET_DEST (set)); | |
13686 | if (temp) | |
13687 | SET_DEST (set) = temp; | |
13688 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 13689 | { |
9ebbca7d GK |
13690 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
13691 | if (temp) | |
13692 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 13693 | } |
38c1f2d7 | 13694 | } |
37409796 | 13695 | else |
9ebbca7d GK |
13696 | { |
13697 | int i; | |
37409796 NS |
13698 | |
13699 | gcc_assert (GET_CODE (real) == PARALLEL); | |
9ebbca7d GK |
13700 | for (i = 0; i < XVECLEN (real, 0); i++) |
13701 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
13702 | { | |
13703 | rtx set = XVECEXP (real, 0, i); | |
f676971a | 13704 | |
9ebbca7d GK |
13705 | temp = simplify_rtx (SET_SRC (set)); |
13706 | if (temp) | |
13707 | SET_SRC (set) = temp; | |
13708 | temp = simplify_rtx (SET_DEST (set)); | |
13709 | if (temp) | |
13710 | SET_DEST (set) = temp; | |
13711 | if (GET_CODE (SET_DEST (set)) == MEM) | |
13712 | { | |
13713 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
13714 | if (temp) | |
13715 | XEXP (SET_DEST (set), 0) = temp; | |
13716 | } | |
13717 | RTX_FRAME_RELATED_P (set) = 1; | |
13718 | } | |
13719 | } | |
c19de7aa AH |
13720 | |
13721 | if (TARGET_SPE) | |
13722 | real = spe_synthesize_frame_save (real); | |
13723 | ||
9ebbca7d GK |
13724 | RTX_FRAME_RELATED_P (insn) = 1; |
13725 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13726 | real, | |
13727 | REG_NOTES (insn)); | |
38c1f2d7 MM |
13728 | } |
13729 | ||
c19de7aa AH |
13730 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
13731 | original note, plus a synthetic register save. */ | |
13732 | ||
13733 | static rtx | |
a2369ed3 | 13734 | spe_synthesize_frame_save (rtx real) |
c19de7aa AH |
13735 | { |
13736 | rtx synth, offset, reg, real2; | |
13737 | ||
13738 | if (GET_CODE (real) != SET | |
13739 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
13740 | return real; | |
13741 | ||
13742 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
13743 | frame related note. The parallel contains a set of the register | |
41f3a930 | 13744 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
13745 | This is so we can differentiate between 64-bit and 32-bit saves. |
13746 | Words cannot describe this nastiness. */ | |
13747 | ||
37409796 NS |
13748 | gcc_assert (GET_CODE (SET_DEST (real)) == MEM |
13749 | && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS | |
13750 | && GET_CODE (SET_SRC (real)) == REG); | |
c19de7aa AH |
13751 | |
13752 | /* Transform: | |
13753 | (set (mem (plus (reg x) (const y))) | |
13754 | (reg z)) | |
13755 | into: | |
13756 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 13757 | (reg z+1200)) |
c19de7aa AH |
13758 | */ |
13759 | ||
13760 | real2 = copy_rtx (real); | |
13761 | PUT_MODE (SET_DEST (real2), SImode); | |
13762 | reg = SET_SRC (real2); | |
13763 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
13764 | synth = copy_rtx (real2); | |
13765 | ||
13766 | if (BYTES_BIG_ENDIAN) | |
13767 | { | |
13768 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
13769 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
13770 | } | |
13771 | ||
13772 | reg = SET_SRC (synth); | |
41f3a930 | 13773 | |
c19de7aa | 13774 | synth = replace_rtx (synth, reg, |
41f3a930 | 13775 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
13776 | |
13777 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
13778 | synth = replace_rtx (synth, offset, | |
13779 | GEN_INT (INTVAL (offset) | |
13780 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
13781 | ||
13782 | RTX_FRAME_RELATED_P (synth) = 1; | |
13783 | RTX_FRAME_RELATED_P (real2) = 1; | |
13784 | if (BYTES_BIG_ENDIAN) | |
13785 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
13786 | else | |
13787 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
13788 | ||
13789 | return real; | |
13790 | } | |
13791 | ||
00b960c7 AH |
13792 | /* Returns an insn that has a vrsave set operation with the |
13793 | appropriate CLOBBERs. */ | |
13794 | ||
13795 | static rtx | |
a2369ed3 | 13796 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
13797 | { |
13798 | int nclobs, i; | |
13799 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 13800 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 13801 | |
a004eb82 AH |
13802 | clobs[0] |
13803 | = gen_rtx_SET (VOIDmode, | |
13804 | vrsave, | |
13805 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
13806 | gen_rtvec (2, reg, vrsave), | |
3aca4bff | 13807 | UNSPECV_SET_VRSAVE)); |
00b960c7 AH |
13808 | |
13809 | nclobs = 1; | |
13810 | ||
9aa86737 AH |
13811 | /* We need to clobber the registers in the mask so the scheduler |
13812 | does not move sets to VRSAVE before sets of AltiVec registers. | |
13813 | ||
13814 | However, if the function receives nonlocal gotos, reload will set | |
13815 | all call saved registers live. We will end up with: | |
13816 | ||
13817 | (set (reg 999) (mem)) | |
13818 | (parallel [ (set (reg vrsave) (unspec blah)) | |
13819 | (clobber (reg 999))]) | |
13820 | ||
13821 | The clobber will cause the store into reg 999 to be dead, and | |
13822 | flow will attempt to delete an epilogue insn. In this case, we | |
13823 | need an unspec use/set of the register. */ | |
00b960c7 AH |
13824 | |
13825 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
44688022 | 13826 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) |
9aa86737 AH |
13827 | { |
13828 | if (!epiloguep || call_used_regs [i]) | |
13829 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
13830 | gen_rtx_REG (V4SImode, i)); | |
13831 | else | |
13832 | { | |
13833 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
13834 | |
13835 | clobs[nclobs++] | |
a004eb82 AH |
13836 | = gen_rtx_SET (VOIDmode, |
13837 | reg, | |
13838 | gen_rtx_UNSPEC (V4SImode, | |
13839 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
13840 | } |
13841 | } | |
00b960c7 AH |
13842 | |
13843 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
13844 | ||
13845 | for (i = 0; i < nclobs; ++i) | |
13846 | XVECEXP (insn, 0, i) = clobs[i]; | |
13847 | ||
13848 | return insn; | |
13849 | } | |
13850 | ||
89e7058f AH |
13851 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
13852 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
13853 | ||
13854 | static void | |
f676971a | 13855 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 13856 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
13857 | { |
13858 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
13859 | rtx replacea, replaceb; | |
13860 | ||
13861 | int_rtx = GEN_INT (offset); | |
13862 | ||
13863 | /* Some cases that need register indexed addressing. */ | |
13864 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
4d4cbc0e | 13865 | || (TARGET_E500_DOUBLE && mode == DFmode) |
a3170dc6 AH |
13866 | || (TARGET_SPE_ABI |
13867 | && SPE_VECTOR_MODE (mode) | |
13868 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
13869 | { |
13870 | /* Whomever calls us must make sure r11 is available in the | |
c4ad648e | 13871 | flow path of instructions in the prologue. */ |
89e7058f AH |
13872 | offset_rtx = gen_rtx_REG (Pmode, 11); |
13873 | emit_move_insn (offset_rtx, int_rtx); | |
13874 | ||
13875 | replacea = offset_rtx; | |
13876 | replaceb = int_rtx; | |
13877 | } | |
13878 | else | |
13879 | { | |
13880 | offset_rtx = int_rtx; | |
13881 | replacea = NULL_RTX; | |
13882 | replaceb = NULL_RTX; | |
13883 | } | |
13884 | ||
13885 | reg = gen_rtx_REG (mode, regno); | |
13886 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
0be76840 | 13887 | mem = gen_frame_mem (mode, addr); |
89e7058f AH |
13888 | |
13889 | insn = emit_move_insn (mem, reg); | |
13890 | ||
13891 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
13892 | } | |
13893 | ||
a3170dc6 AH |
13894 | /* Emit an offset memory reference suitable for a frame store, while |
13895 | converting to a valid addressing mode. */ | |
13896 | ||
13897 | static rtx | |
a2369ed3 | 13898 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
13899 | { |
13900 | rtx int_rtx, offset_rtx; | |
13901 | ||
13902 | int_rtx = GEN_INT (offset); | |
13903 | ||
4d4cbc0e AH |
13904 | if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) |
13905 | || (TARGET_E500_DOUBLE && mode == DFmode)) | |
a3170dc6 AH |
13906 | { |
13907 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13908 | emit_move_insn (offset_rtx, int_rtx); | |
13909 | } | |
13910 | else | |
13911 | offset_rtx = int_rtx; | |
13912 | ||
0be76840 | 13913 | return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); |
a3170dc6 AH |
13914 | } |
13915 | ||
6d0a8091 DJ |
13916 | /* Look for user-defined global regs. We should not save and restore these, |
13917 | and cannot use stmw/lmw if there are any in its range. */ | |
13918 | ||
13919 | static bool | |
13920 | no_global_regs_above (int first_greg) | |
13921 | { | |
13922 | int i; | |
13923 | for (i = 0; i < 32 - first_greg; i++) | |
13924 | if (global_regs[first_greg + i]) | |
13925 | return false; | |
13926 | return true; | |
13927 | } | |
13928 | ||
699c914a MS |
13929 | #ifndef TARGET_FIX_AND_CONTINUE |
13930 | #define TARGET_FIX_AND_CONTINUE 0 | |
13931 | #endif | |
13932 | ||
9ebbca7d GK |
13933 | /* Emit function prologue as insns. */ |
13934 | ||
9878760c | 13935 | void |
863d938c | 13936 | rs6000_emit_prologue (void) |
9878760c | 13937 | { |
4697a36c | 13938 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a | 13939 | enum machine_mode reg_mode = Pmode; |
327e5343 | 13940 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
13941 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
13942 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
13943 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 13944 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d GK |
13945 | rtx insn; |
13946 | int saving_FPRs_inline; | |
13947 | int using_store_multiple; | |
13948 | HOST_WIDE_INT sp_offset = 0; | |
f676971a | 13949 | |
699c914a MS |
13950 | if (TARGET_FIX_AND_CONTINUE) |
13951 | { | |
13952 | /* gdb on darwin arranges to forward a function from the old | |
de2ab0ca | 13953 | address by modifying the first 5 instructions of the function |
699c914a MS |
13954 | to branch to the overriding function. This is necessary to |
13955 | permit function pointers that point to the old function to | |
13956 | actually forward to the new function. */ | |
13957 | emit_insn (gen_nop ()); | |
13958 | emit_insn (gen_nop ()); | |
de2ab0ca | 13959 | emit_insn (gen_nop ()); |
699c914a MS |
13960 | emit_insn (gen_nop ()); |
13961 | emit_insn (gen_nop ()); | |
13962 | } | |
13963 | ||
13964 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
13965 | { | |
13966 | reg_mode = V2SImode; | |
13967 | reg_size = 8; | |
13968 | } | |
a3170dc6 | 13969 | |
9ebbca7d | 13970 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
13971 | && (!TARGET_SPE_ABI |
13972 | || info->spe_64bit_regs_used == 0) | |
6d0a8091 DJ |
13973 | && info->first_gp_reg_save < 31 |
13974 | && no_global_regs_above (info->first_gp_reg_save)); | |
9ebbca7d | 13975 | saving_FPRs_inline = (info->first_fp_reg_save == 64 |
8c29550d | 13976 | || FP_SAVE_INLINE (info->first_fp_reg_save) |
acd0b319 | 13977 | || current_function_calls_eh_return |
8c29550d | 13978 | || cfun->machine->ra_need_lr); |
9ebbca7d GK |
13979 | |
13980 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
fc4767bb | 13981 | if (info->push_p |
acd0b319 AM |
13982 | && (DEFAULT_ABI == ABI_V4 |
13983 | || current_function_calls_eh_return)) | |
9ebbca7d GK |
13984 | { |
13985 | if (info->total_size < 32767) | |
13986 | sp_offset = info->total_size; | |
13987 | else | |
13988 | frame_reg_rtx = frame_ptr_rtx; | |
f676971a | 13989 | rs6000_emit_allocate_stack (info->total_size, |
9ebbca7d GK |
13990 | (frame_reg_rtx != sp_reg_rtx |
13991 | && (info->cr_save_p | |
13992 | || info->lr_save_p | |
13993 | || info->first_fp_reg_save < 64 | |
13994 | || info->first_gp_reg_save < 32 | |
13995 | ))); | |
13996 | if (frame_reg_rtx != sp_reg_rtx) | |
13997 | rs6000_emit_stack_tie (); | |
13998 | } | |
13999 | ||
d62294f5 | 14000 | /* Handle world saves specially here. */ |
f57fe068 | 14001 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
14002 | { |
14003 | int i, j, sz; | |
14004 | rtx treg; | |
14005 | rtvec p; | |
14006 | ||
14007 | /* save_world expects lr in r0. */ | |
14008 | if (info->lr_save_p) | |
c4ad648e AM |
14009 | { |
14010 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
14011 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
14012 | RTX_FRAME_RELATED_P (insn) = 1; | |
14013 | } | |
d62294f5 FJ |
14014 | |
14015 | /* The SAVE_WORLD and RESTORE_WORLD routines make a number of | |
c4ad648e | 14016 | assumptions about the offsets of various bits of the stack |
992d08b1 | 14017 | frame. */ |
37409796 NS |
14018 | gcc_assert (info->gp_save_offset == -220 |
14019 | && info->fp_save_offset == -144 | |
14020 | && info->lr_save_offset == 8 | |
14021 | && info->cr_save_offset == 4 | |
14022 | && info->push_p | |
14023 | && info->lr_save_p | |
14024 | && (!current_function_calls_eh_return | |
14025 | || info->ehrd_offset == -432) | |
14026 | && info->vrsave_save_offset == -224 | |
14027 | && info->altivec_save_offset == (-224 -16 -192)); | |
d62294f5 FJ |
14028 | |
14029 | treg = gen_rtx_REG (SImode, 11); | |
14030 | emit_move_insn (treg, GEN_INT (-info->total_size)); | |
14031 | ||
14032 | /* SAVE_WORLD takes the caller's LR in R0 and the frame size | |
c4ad648e | 14033 | in R11. It also clobbers R12, so beware! */ |
d62294f5 FJ |
14034 | |
14035 | /* Preserve CR2 for save_world prologues */ | |
14036 | sz = 6; | |
14037 | sz += 32 - info->first_gp_reg_save; | |
14038 | sz += 64 - info->first_fp_reg_save; | |
14039 | sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1; | |
14040 | p = rtvec_alloc (sz); | |
14041 | j = 0; | |
14042 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, | |
c4ad648e AM |
14043 | gen_rtx_REG (Pmode, |
14044 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 14045 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, |
c4ad648e AM |
14046 | gen_rtx_SYMBOL_REF (Pmode, |
14047 | "*save_world")); | |
d62294f5 | 14048 | /* We do floats first so that the instruction pattern matches |
c4ad648e AM |
14049 | properly. */ |
14050 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
14051 | { | |
14052 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
14053 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14054 | GEN_INT (info->fp_save_offset | |
14055 | + sp_offset + 8 * i)); | |
0be76840 | 14056 | rtx mem = gen_frame_mem (DFmode, addr); |
c4ad648e AM |
14057 | |
14058 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
14059 | } | |
d62294f5 | 14060 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
14061 | { |
14062 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
14063 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14064 | GEN_INT (info->altivec_save_offset | |
14065 | + sp_offset + 16 * i)); | |
0be76840 | 14066 | rtx mem = gen_frame_mem (V4SImode, addr); |
c4ad648e AM |
14067 | |
14068 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
14069 | } | |
d62294f5 | 14070 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
c4ad648e AM |
14071 | { |
14072 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
14073 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14074 | GEN_INT (info->gp_save_offset | |
14075 | + sp_offset + reg_size * i)); | |
0be76840 | 14076 | rtx mem = gen_frame_mem (reg_mode, addr); |
c4ad648e AM |
14077 | |
14078 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
14079 | } | |
14080 | ||
14081 | { | |
14082 | /* CR register traditionally saved as CR2. */ | |
14083 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
14084 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14085 | GEN_INT (info->cr_save_offset | |
14086 | + sp_offset)); | |
0be76840 | 14087 | rtx mem = gen_frame_mem (reg_mode, addr); |
c4ad648e AM |
14088 | |
14089 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
14090 | } | |
d62294f5 FJ |
14091 | /* Prevent any attempt to delete the setting of r0 and treg! */ |
14092 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0)); | |
14093 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg); | |
14094 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx); | |
14095 | ||
14096 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
14097 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
c4ad648e | 14098 | NULL_RTX, NULL_RTX); |
d62294f5 FJ |
14099 | |
14100 | if (current_function_calls_eh_return) | |
c4ad648e AM |
14101 | { |
14102 | unsigned int i; | |
14103 | for (i = 0; ; ++i) | |
14104 | { | |
14105 | unsigned int regno = EH_RETURN_DATA_REGNO (i); | |
14106 | if (regno == INVALID_REGNUM) | |
14107 | break; | |
14108 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, | |
14109 | info->ehrd_offset + sp_offset | |
14110 | + reg_size * (int) i, | |
14111 | info->total_size); | |
14112 | } | |
14113 | } | |
d62294f5 FJ |
14114 | } |
14115 | ||
9aa86737 | 14116 | /* Save AltiVec registers if needed. */ |
f57fe068 | 14117 | if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0) |
9aa86737 AH |
14118 | { |
14119 | int i; | |
14120 | ||
14121 | /* There should be a non inline version of this, for when we | |
14122 | are saving lots of vector registers. */ | |
14123 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
14124 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
14125 | { | |
14126 | rtx areg, savereg, mem; | |
14127 | int offset; | |
14128 | ||
14129 | offset = info->altivec_save_offset + sp_offset | |
14130 | + 16 * (i - info->first_altivec_reg_save); | |
14131 | ||
14132 | savereg = gen_rtx_REG (V4SImode, i); | |
14133 | ||
14134 | areg = gen_rtx_REG (Pmode, 0); | |
14135 | emit_move_insn (areg, GEN_INT (offset)); | |
14136 | ||
14137 | /* AltiVec addressing mode is [reg+reg]. */ | |
0be76840 DE |
14138 | mem = gen_frame_mem (V4SImode, |
14139 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
9aa86737 AH |
14140 | |
14141 | insn = emit_move_insn (mem, savereg); | |
14142 | ||
5c242421 SB |
14143 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
14144 | areg, GEN_INT (offset)); | |
9aa86737 AH |
14145 | } |
14146 | } | |
14147 | ||
14148 | /* VRSAVE is a bit vector representing which AltiVec registers | |
14149 | are used. The OS uses this to determine which vector | |
14150 | registers to save on a context switch. We need to save | |
14151 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
14152 | used in this function, and do the corresponding magic in the | |
14153 | epilogue. */ | |
14154 | ||
4d774ff8 | 14155 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
bcb604b6 | 14156 | && info->vrsave_mask != 0) |
9aa86737 | 14157 | { |
a004eb82 | 14158 | rtx reg, mem, vrsave; |
9aa86737 AH |
14159 | int offset; |
14160 | ||
eab97e44 AM |
14161 | /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12 |
14162 | as frame_reg_rtx and r11 as the static chain pointer for | |
14163 | nested functions. */ | |
14164 | reg = gen_rtx_REG (SImode, 0); | |
a004eb82 | 14165 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
14166 | if (TARGET_MACHO) |
14167 | emit_insn (gen_get_vrsave_internal (reg)); | |
14168 | else | |
14169 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 | 14170 | |
bcb604b6 FJ |
14171 | if (!WORLD_SAVE_P (info)) |
14172 | { | |
14173 | /* Save VRSAVE. */ | |
14174 | offset = info->vrsave_save_offset + sp_offset; | |
0be76840 DE |
14175 | mem = gen_frame_mem (SImode, |
14176 | gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14177 | GEN_INT (offset))); | |
bcb604b6 FJ |
14178 | insn = emit_move_insn (mem, reg); |
14179 | } | |
9aa86737 AH |
14180 | |
14181 | /* Include the registers in the mask. */ | |
14182 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
14183 | ||
14184 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
14185 | } | |
14186 | ||
9ebbca7d | 14187 | /* If we use the link register, get it into r0. */ |
f57fe068 | 14188 | if (!WORLD_SAVE_P (info) && info->lr_save_p) |
f8a57be8 GK |
14189 | { |
14190 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
14191 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
14192 | RTX_FRAME_RELATED_P (insn) = 1; | |
14193 | } | |
9ebbca7d GK |
14194 | |
14195 | /* If we need to save CR, put it into r12. */ | |
f57fe068 | 14196 | if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) |
9ebbca7d | 14197 | { |
f8a57be8 | 14198 | rtx set; |
f676971a | 14199 | |
9ebbca7d | 14200 | cr_save_rtx = gen_rtx_REG (SImode, 12); |
f8a57be8 GK |
14201 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
14202 | RTX_FRAME_RELATED_P (insn) = 1; | |
14203 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
14204 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. | |
14205 | But that's OK. All we have to do is specify that _one_ condition | |
14206 | code register is saved in this stack slot. The thrower's epilogue | |
14207 | will then restore all the call-saved registers. | |
14208 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
14209 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, | |
14210 | gen_rtx_REG (SImode, CR2_REGNO)); | |
14211 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
14212 | set, | |
14213 | REG_NOTES (insn)); | |
9ebbca7d GK |
14214 | } |
14215 | ||
a4f6c312 SS |
14216 | /* Do any required saving of fpr's. If only one or two to save, do |
14217 | it ourselves. Otherwise, call function. */ | |
f57fe068 | 14218 | if (!WORLD_SAVE_P (info) && saving_FPRs_inline) |
9ebbca7d GK |
14219 | { |
14220 | int i; | |
14221 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 14222 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d | 14223 | && ! call_used_regs[info->first_fp_reg_save+i])) |
89e7058f AH |
14224 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
14225 | info->first_fp_reg_save + i, | |
14226 | info->fp_save_offset + sp_offset + 8 * i, | |
14227 | info->total_size); | |
9ebbca7d | 14228 | } |
f57fe068 | 14229 | else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64) |
9ebbca7d GK |
14230 | { |
14231 | int i; | |
14232 | char rname[30]; | |
520a57c8 | 14233 | const char *alloc_rname; |
9ebbca7d GK |
14234 | rtvec p; |
14235 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
f676971a EC |
14236 | |
14237 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
14238 | gen_rtx_REG (Pmode, | |
9ebbca7d GK |
14239 | LINK_REGISTER_REGNUM)); |
14240 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
14241 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 14242 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
14243 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
14244 | gen_rtx_SYMBOL_REF (Pmode, | |
14245 | alloc_rname)); | |
14246 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
14247 | { | |
14248 | rtx addr, reg, mem; | |
14249 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
14250 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a | 14251 | GEN_INT (info->fp_save_offset |
9ebbca7d | 14252 | + sp_offset + 8*i)); |
0be76840 | 14253 | mem = gen_frame_mem (DFmode, addr); |
9ebbca7d GK |
14254 | |
14255 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
14256 | } | |
14257 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 14258 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d GK |
14259 | NULL_RTX, NULL_RTX); |
14260 | } | |
b6c9286a | 14261 | |
9ebbca7d GK |
14262 | /* Save GPRs. This is done as a PARALLEL if we are using |
14263 | the store-multiple instructions. */ | |
f57fe068 | 14264 | if (!WORLD_SAVE_P (info) && using_store_multiple) |
b6c9286a | 14265 | { |
308c142a | 14266 | rtvec p; |
9ebbca7d GK |
14267 | int i; |
14268 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
14269 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
14270 | { | |
14271 | rtx addr, reg, mem; | |
14272 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
f676971a EC |
14273 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14274 | GEN_INT (info->gp_save_offset | |
14275 | + sp_offset | |
9ebbca7d | 14276 | + reg_size * i)); |
0be76840 | 14277 | mem = gen_frame_mem (reg_mode, addr); |
9ebbca7d GK |
14278 | |
14279 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
14280 | } | |
14281 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 14282 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d | 14283 | NULL_RTX, NULL_RTX); |
b6c9286a | 14284 | } |
f57fe068 | 14285 | else if (!WORLD_SAVE_P (info)) |
b6c9286a | 14286 | { |
9ebbca7d GK |
14287 | int i; |
14288 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6d0a8091 DJ |
14289 | if ((regs_ever_live[info->first_gp_reg_save + i] |
14290 | && (!call_used_regs[info->first_gp_reg_save + i] | |
14291 | || (i + info->first_gp_reg_save | |
b4db40bf JJ |
14292 | == RS6000_PIC_OFFSET_TABLE_REGNUM |
14293 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
6d0a8091 | 14294 | || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 14295 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 14296 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
14297 | { |
14298 | rtx addr, reg, mem; | |
14299 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
14300 | ||
c19de7aa | 14301 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
14302 | { |
14303 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
14304 | rtx b; | |
14305 | ||
14306 | if (!SPE_CONST_OFFSET_OK (offset)) | |
14307 | { | |
14308 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
14309 | emit_move_insn (b, GEN_INT (offset)); | |
14310 | } | |
14311 | else | |
14312 | b = GEN_INT (offset); | |
14313 | ||
14314 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
0be76840 | 14315 | mem = gen_frame_mem (V2SImode, addr); |
a3170dc6 AH |
14316 | insn = emit_move_insn (mem, reg); |
14317 | ||
14318 | if (GET_CODE (b) == CONST_INT) | |
14319 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
14320 | NULL_RTX, NULL_RTX); | |
14321 | else | |
14322 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
14323 | b, GEN_INT (offset)); | |
14324 | } | |
14325 | else | |
14326 | { | |
f676971a EC |
14327 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14328 | GEN_INT (info->gp_save_offset | |
14329 | + sp_offset | |
a3170dc6 | 14330 | + reg_size * i)); |
0be76840 | 14331 | mem = gen_frame_mem (reg_mode, addr); |
a3170dc6 AH |
14332 | |
14333 | insn = emit_move_insn (mem, reg); | |
f676971a | 14334 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a3170dc6 AH |
14335 | NULL_RTX, NULL_RTX); |
14336 | } | |
14337 | } | |
9ebbca7d GK |
14338 | } |
14339 | ||
83720594 RH |
14340 | /* ??? There's no need to emit actual instructions here, but it's the |
14341 | easiest way to get the frame unwind information emitted. */ | |
f57fe068 | 14342 | if (!WORLD_SAVE_P (info) && current_function_calls_eh_return) |
83720594 | 14343 | { |
78e1b90d DE |
14344 | unsigned int i, regno; |
14345 | ||
fc4767bb JJ |
14346 | /* In AIX ABI we need to pretend we save r2 here. */ |
14347 | if (TARGET_AIX) | |
14348 | { | |
14349 | rtx addr, reg, mem; | |
14350 | ||
14351 | reg = gen_rtx_REG (reg_mode, 2); | |
14352 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14353 | GEN_INT (sp_offset + 5 * reg_size)); | |
0be76840 | 14354 | mem = gen_frame_mem (reg_mode, addr); |
fc4767bb JJ |
14355 | |
14356 | insn = emit_move_insn (mem, reg); | |
f676971a | 14357 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
fc4767bb JJ |
14358 | NULL_RTX, NULL_RTX); |
14359 | PATTERN (insn) = gen_blockage (); | |
14360 | } | |
14361 | ||
83720594 RH |
14362 | for (i = 0; ; ++i) |
14363 | { | |
83720594 RH |
14364 | regno = EH_RETURN_DATA_REGNO (i); |
14365 | if (regno == INVALID_REGNUM) | |
14366 | break; | |
14367 | ||
89e7058f AH |
14368 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
14369 | info->ehrd_offset + sp_offset | |
14370 | + reg_size * (int) i, | |
14371 | info->total_size); | |
83720594 RH |
14372 | } |
14373 | } | |
14374 | ||
9ebbca7d | 14375 | /* Save lr if we used it. */ |
f57fe068 | 14376 | if (!WORLD_SAVE_P (info) && info->lr_save_p) |
9ebbca7d GK |
14377 | { |
14378 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14379 | GEN_INT (info->lr_save_offset + sp_offset)); | |
14380 | rtx reg = gen_rtx_REG (Pmode, 0); | |
14381 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
0be76840 | 14382 | /* This should not be of frame_alias_set, because of |
9ebbca7d | 14383 | __builtin_return_address. */ |
f676971a | 14384 | |
9ebbca7d | 14385 | insn = emit_move_insn (mem, reg); |
f676971a | 14386 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 14387 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
14388 | } |
14389 | ||
14390 | /* Save CR if we use any that must be preserved. */ | |
f57fe068 | 14391 | if (!WORLD_SAVE_P (info) && info->cr_save_p) |
9ebbca7d GK |
14392 | { |
14393 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14394 | GEN_INT (info->cr_save_offset + sp_offset)); | |
0be76840 | 14395 | rtx mem = gen_frame_mem (SImode, addr); |
f8a57be8 GK |
14396 | /* See the large comment above about why CR2_REGNO is used. */ |
14397 | rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); | |
ba4828e0 | 14398 | |
9ebbca7d GK |
14399 | /* If r12 was used to hold the original sp, copy cr into r0 now |
14400 | that it's free. */ | |
14401 | if (REGNO (frame_reg_rtx) == 12) | |
14402 | { | |
f8a57be8 GK |
14403 | rtx set; |
14404 | ||
9ebbca7d | 14405 | cr_save_rtx = gen_rtx_REG (SImode, 0); |
f8a57be8 GK |
14406 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
14407 | RTX_FRAME_RELATED_P (insn) = 1; | |
14408 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); | |
14409 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
14410 | set, | |
14411 | REG_NOTES (insn)); | |
f676971a | 14412 | |
9ebbca7d GK |
14413 | } |
14414 | insn = emit_move_insn (mem, cr_save_rtx); | |
14415 | ||
f676971a | 14416 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 14417 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
14418 | } |
14419 | ||
f676971a | 14420 | /* Update stack and set back pointer unless this is V.4, |
9ebbca7d | 14421 | for which it was done previously. */ |
f57fe068 | 14422 | if (!WORLD_SAVE_P (info) && info->push_p |
fc4767bb | 14423 | && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) |
9ebbca7d GK |
14424 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
14425 | ||
14426 | /* Set frame pointer, if needed. */ | |
14427 | if (frame_pointer_needed) | |
14428 | { | |
7d5175e1 | 14429 | insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), |
9ebbca7d GK |
14430 | sp_reg_rtx); |
14431 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 14432 | } |
9878760c | 14433 | |
1db02437 | 14434 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 14435 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
7f970b70 AM |
14436 | || (DEFAULT_ABI == ABI_V4 |
14437 | && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT)) | |
1db02437 | 14438 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
c4ad648e AM |
14439 | { |
14440 | /* If emit_load_toc_table will use the link register, we need to save | |
14441 | it. We use R12 for this purpose because emit_load_toc_table | |
14442 | can use register 0. This allows us to use a plain 'blr' to return | |
14443 | from the procedure more often. */ | |
14444 | int save_LR_around_toc_setup = (TARGET_ELF | |
14445 | && DEFAULT_ABI != ABI_AIX | |
14446 | && flag_pic | |
14447 | && ! info->lr_save_p | |
14448 | && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); | |
14449 | if (save_LR_around_toc_setup) | |
14450 | { | |
14451 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f8a57be8 | 14452 | |
c4ad648e AM |
14453 | insn = emit_move_insn (frame_ptr_rtx, lr); |
14454 | rs6000_maybe_dead (insn); | |
14455 | RTX_FRAME_RELATED_P (insn) = 1; | |
f8a57be8 | 14456 | |
c4ad648e | 14457 | rs6000_emit_load_toc_table (TRUE); |
f8a57be8 | 14458 | |
c4ad648e AM |
14459 | insn = emit_move_insn (lr, frame_ptr_rtx); |
14460 | rs6000_maybe_dead (insn); | |
14461 | RTX_FRAME_RELATED_P (insn) = 1; | |
14462 | } | |
14463 | else | |
14464 | rs6000_emit_load_toc_table (TRUE); | |
14465 | } | |
ee890fe2 | 14466 | |
fcce224d | 14467 | #if TARGET_MACHO |
ee890fe2 SS |
14468 | if (DEFAULT_ABI == ABI_DARWIN |
14469 | && flag_pic && current_function_uses_pic_offset_table) | |
14470 | { | |
f8a57be8 | 14471 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
11abc112 | 14472 | rtx src = machopic_function_base_sym (); |
ee890fe2 | 14473 | |
6d0a8091 DJ |
14474 | /* Save and restore LR locally around this call (in R0). */ |
14475 | if (!info->lr_save_p) | |
14476 | rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr)); | |
14477 | ||
f8a57be8 | 14478 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); |
ee890fe2 | 14479 | |
f676971a | 14480 | insn = emit_move_insn (gen_rtx_REG (Pmode, |
f8a57be8 GK |
14481 | RS6000_PIC_OFFSET_TABLE_REGNUM), |
14482 | lr); | |
14483 | rs6000_maybe_dead (insn); | |
6d0a8091 DJ |
14484 | |
14485 | if (!info->lr_save_p) | |
14486 | rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0))); | |
ee890fe2 | 14487 | } |
fcce224d | 14488 | #endif |
9ebbca7d GK |
14489 | } |
14490 | ||
9ebbca7d | 14491 | /* Write function prologue. */ |
a4f6c312 | 14492 | |
08c148a8 | 14493 | static void |
f676971a | 14494 | rs6000_output_function_prologue (FILE *file, |
a2369ed3 | 14495 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9ebbca7d GK |
14496 | { |
14497 | rs6000_stack_t *info = rs6000_stack_info (); | |
14498 | ||
4697a36c MM |
14499 | if (TARGET_DEBUG_STACK) |
14500 | debug_stack_info (info); | |
9878760c | 14501 | |
a4f6c312 SS |
14502 | /* Write .extern for any function we will call to save and restore |
14503 | fp values. */ | |
14504 | if (info->first_fp_reg_save < 64 | |
14505 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 14506 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 14507 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
14508 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
14509 | RESTORE_FP_SUFFIX); | |
9878760c | 14510 | |
c764f757 RK |
14511 | /* Write .extern for AIX common mode routines, if needed. */ |
14512 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
14513 | { | |
f6709c70 JW |
14514 | fputs ("\t.extern __mulh\n", file); |
14515 | fputs ("\t.extern __mull\n", file); | |
14516 | fputs ("\t.extern __divss\n", file); | |
14517 | fputs ("\t.extern __divus\n", file); | |
14518 | fputs ("\t.extern __quoss\n", file); | |
14519 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
14520 | common_mode_defined = 1; |
14521 | } | |
9878760c | 14522 | |
9ebbca7d | 14523 | if (! HAVE_prologue) |
979721f8 | 14524 | { |
9ebbca7d | 14525 | start_sequence (); |
9dda4cc8 | 14526 | |
a4f6c312 SS |
14527 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
14528 | the "toplevel" insn chain. */ | |
2e040219 | 14529 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 14530 | rs6000_emit_prologue (); |
2e040219 | 14531 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 14532 | |
a3c9585f | 14533 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
14534 | { |
14535 | rtx insn; | |
14536 | unsigned addr = 0; | |
14537 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
14538 | { | |
14539 | INSN_ADDRESSES_NEW (insn, addr); | |
14540 | addr += 4; | |
14541 | } | |
14542 | } | |
9dda4cc8 | 14543 | |
9ebbca7d | 14544 | if (TARGET_DEBUG_STACK) |
a4f6c312 | 14545 | debug_rtx_list (get_insns (), 100); |
c9d691e9 | 14546 | final (get_insns (), file, FALSE); |
9ebbca7d | 14547 | end_sequence (); |
979721f8 MM |
14548 | } |
14549 | ||
9ebbca7d GK |
14550 | rs6000_pic_labelno++; |
14551 | } | |
f676971a | 14552 | |
9ebbca7d | 14553 | /* Emit function epilogue as insns. |
9878760c | 14554 | |
9ebbca7d GK |
14555 | At present, dwarf2out_frame_debug_expr doesn't understand |
14556 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
14557 | anywhere in the epilogue. Most of the insns below would in any case | |
14558 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 14559 | |
9ebbca7d | 14560 | void |
a2369ed3 | 14561 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
14562 | { |
14563 | rs6000_stack_t *info; | |
14564 | int restoring_FPRs_inline; | |
14565 | int using_load_multiple; | |
14566 | int using_mfcr_multiple; | |
14567 | int use_backchain_to_restore_sp; | |
14568 | int sp_offset = 0; | |
14569 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
14570 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a | 14571 | enum machine_mode reg_mode = Pmode; |
327e5343 | 14572 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
14573 | int i; |
14574 | ||
c19de7aa AH |
14575 | info = rs6000_stack_info (); |
14576 | ||
14577 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
14578 | { |
14579 | reg_mode = V2SImode; | |
14580 | reg_size = 8; | |
14581 | } | |
14582 | ||
9ebbca7d | 14583 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
14584 | && (!TARGET_SPE_ABI |
14585 | || info->spe_64bit_regs_used == 0) | |
6d0a8091 DJ |
14586 | && info->first_gp_reg_save < 31 |
14587 | && no_global_regs_above (info->first_gp_reg_save)); | |
9ebbca7d | 14588 | restoring_FPRs_inline = (sibcall |
83720594 | 14589 | || current_function_calls_eh_return |
9ebbca7d GK |
14590 | || info->first_fp_reg_save == 64 |
14591 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
f676971a | 14592 | use_backchain_to_restore_sp = (frame_pointer_needed |
9ebbca7d GK |
14593 | || current_function_calls_alloca |
14594 | || info->total_size > 32767); | |
14595 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
14596 | || rs6000_cpu == PROCESSOR_PPC603 | |
14597 | || rs6000_cpu == PROCESSOR_PPC750 | |
14598 | || optimize_size); | |
14599 | ||
f57fe068 | 14600 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
14601 | { |
14602 | int i, j; | |
14603 | char rname[30]; | |
14604 | const char *alloc_rname; | |
14605 | rtvec p; | |
14606 | ||
14607 | /* eh_rest_world_r10 will return to the location saved in the LR | |
c4ad648e AM |
14608 | stack slot (which is not likely to be our caller.) |
14609 | Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8. | |
14610 | rest_world is similar, except any R10 parameter is ignored. | |
14611 | The exception-handling stuff that was here in 2.95 is no | |
14612 | longer necessary. */ | |
d62294f5 FJ |
14613 | |
14614 | p = rtvec_alloc (9 | |
14615 | + 1 | |
f676971a | 14616 | + 32 - info->first_gp_reg_save |
c4ad648e AM |
14617 | + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save |
14618 | + 63 + 1 - info->first_fp_reg_save); | |
d62294f5 | 14619 | |
c4ad648e AM |
14620 | strcpy (rname, ((current_function_calls_eh_return) ? |
14621 | "*eh_rest_world_r10" : "*rest_world")); | |
d62294f5 FJ |
14622 | alloc_rname = ggc_strdup (rname); |
14623 | ||
14624 | j = 0; | |
14625 | RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); | |
14626 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, | |
c4ad648e AM |
14627 | gen_rtx_REG (Pmode, |
14628 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 14629 | RTVEC_ELT (p, j++) |
c4ad648e | 14630 | = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname)); |
d62294f5 | 14631 | /* The instruction pattern requires a clobber here; |
c4ad648e | 14632 | it is shared with the restVEC helper. */ |
d62294f5 | 14633 | RTVEC_ELT (p, j++) |
c4ad648e | 14634 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11)); |
d62294f5 FJ |
14635 | |
14636 | { | |
c4ad648e AM |
14637 | /* CR register traditionally saved as CR2. */ |
14638 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
14639 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14640 | GEN_INT (info->cr_save_offset)); | |
0be76840 | 14641 | rtx mem = gen_frame_mem (reg_mode, addr); |
c4ad648e AM |
14642 | |
14643 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
d62294f5 FJ |
14644 | } |
14645 | ||
14646 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
c4ad648e AM |
14647 | { |
14648 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
14649 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14650 | GEN_INT (info->gp_save_offset | |
14651 | + reg_size * i)); | |
0be76840 | 14652 | rtx mem = gen_frame_mem (reg_mode, addr); |
c4ad648e AM |
14653 | |
14654 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14655 | } | |
d62294f5 | 14656 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
14657 | { |
14658 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
14659 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14660 | GEN_INT (info->altivec_save_offset | |
14661 | + 16 * i)); | |
0be76840 | 14662 | rtx mem = gen_frame_mem (V4SImode, addr); |
c4ad648e AM |
14663 | |
14664 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14665 | } | |
d62294f5 | 14666 | for (i = 0; info->first_fp_reg_save + i <= 63; i++) |
c4ad648e AM |
14667 | { |
14668 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
14669 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14670 | GEN_INT (info->fp_save_offset | |
14671 | + 8 * i)); | |
0be76840 | 14672 | rtx mem = gen_frame_mem (DFmode, addr); |
c4ad648e AM |
14673 | |
14674 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14675 | } | |
d62294f5 | 14676 | RTVEC_ELT (p, j++) |
c4ad648e | 14677 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0)); |
d62294f5 | 14678 | RTVEC_ELT (p, j++) |
c4ad648e | 14679 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12)); |
d62294f5 | 14680 | RTVEC_ELT (p, j++) |
c4ad648e | 14681 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7)); |
d62294f5 | 14682 | RTVEC_ELT (p, j++) |
c4ad648e | 14683 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8)); |
d62294f5 | 14684 | RTVEC_ELT (p, j++) |
c4ad648e | 14685 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10)); |
d62294f5 FJ |
14686 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
14687 | ||
14688 | return; | |
14689 | } | |
14690 | ||
9ebbca7d GK |
14691 | /* If we have a frame pointer, a call to alloca, or a large stack |
14692 | frame, restore the old stack pointer using the backchain. Otherwise, | |
14693 | we know what size to update it with. */ | |
14694 | if (use_backchain_to_restore_sp) | |
bacbde18 | 14695 | { |
9ebbca7d GK |
14696 | /* Under V.4, don't reset the stack pointer until after we're done |
14697 | loading the saved registers. */ | |
f607bc57 | 14698 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 14699 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 14700 | |
9ebbca7d GK |
14701 | emit_move_insn (frame_reg_rtx, |
14702 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
bacbde18 | 14703 | } |
9ebbca7d | 14704 | else if (info->push_p) |
85638c0d | 14705 | { |
fc4767bb JJ |
14706 | if (DEFAULT_ABI == ABI_V4 |
14707 | || current_function_calls_eh_return) | |
9ebbca7d GK |
14708 | sp_offset = info->total_size; |
14709 | else | |
14710 | { | |
14711 | emit_insn (TARGET_32BIT | |
14712 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
14713 | GEN_INT (info->total_size)) | |
14714 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
14715 | GEN_INT (info->total_size))); | |
14716 | } | |
85638c0d | 14717 | } |
f676971a | 14718 | |
9aa86737 AH |
14719 | /* Restore AltiVec registers if needed. */ |
14720 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
14721 | { | |
14722 | int i; | |
14723 | ||
14724 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
14725 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
14726 | { | |
14727 | rtx addr, areg, mem; | |
14728 | ||
14729 | areg = gen_rtx_REG (Pmode, 0); | |
14730 | emit_move_insn | |
14731 | (areg, GEN_INT (info->altivec_save_offset | |
14732 | + sp_offset | |
14733 | + 16 * (i - info->first_altivec_reg_save))); | |
14734 | ||
14735 | /* AltiVec addressing mode is [reg+reg]. */ | |
14736 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
0be76840 | 14737 | mem = gen_frame_mem (V4SImode, addr); |
9aa86737 AH |
14738 | |
14739 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
14740 | } | |
14741 | } | |
14742 | ||
14743 | /* Restore VRSAVE if needed. */ | |
44688022 | 14744 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
4d774ff8 | 14745 | && info->vrsave_mask != 0) |
9aa86737 AH |
14746 | { |
14747 | rtx addr, mem, reg; | |
14748 | ||
14749 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14750 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
0be76840 | 14751 | mem = gen_frame_mem (SImode, addr); |
9aa86737 AH |
14752 | reg = gen_rtx_REG (SImode, 12); |
14753 | emit_move_insn (reg, mem); | |
14754 | ||
14755 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
14756 | } | |
14757 | ||
9ebbca7d GK |
14758 | /* Get the old lr if we saved it. */ |
14759 | if (info->lr_save_p) | |
b6c9286a | 14760 | { |
a3170dc6 AH |
14761 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
14762 | info->lr_save_offset + sp_offset); | |
ba4828e0 | 14763 | |
9ebbca7d | 14764 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 14765 | } |
f676971a | 14766 | |
9ebbca7d GK |
14767 | /* Get the old cr if we saved it. */ |
14768 | if (info->cr_save_p) | |
14769 | { | |
14770 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14771 | GEN_INT (info->cr_save_offset + sp_offset)); | |
0be76840 | 14772 | rtx mem = gen_frame_mem (SImode, addr); |
b6c9286a | 14773 | |
9ebbca7d GK |
14774 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
14775 | } | |
f676971a | 14776 | |
9ebbca7d | 14777 | /* Set LR here to try to overlap restores below. */ |
4697a36c | 14778 | if (info->lr_save_p) |
9ebbca7d GK |
14779 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
14780 | gen_rtx_REG (Pmode, 0)); | |
f676971a | 14781 | |
83720594 RH |
14782 | /* Load exception handler data registers, if needed. */ |
14783 | if (current_function_calls_eh_return) | |
14784 | { | |
78e1b90d DE |
14785 | unsigned int i, regno; |
14786 | ||
fc4767bb JJ |
14787 | if (TARGET_AIX) |
14788 | { | |
14789 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14790 | GEN_INT (sp_offset + 5 * reg_size)); | |
0be76840 | 14791 | rtx mem = gen_frame_mem (reg_mode, addr); |
fc4767bb JJ |
14792 | |
14793 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
14794 | } | |
14795 | ||
83720594 RH |
14796 | for (i = 0; ; ++i) |
14797 | { | |
a3170dc6 | 14798 | rtx mem; |
83720594 RH |
14799 | |
14800 | regno = EH_RETURN_DATA_REGNO (i); | |
14801 | if (regno == INVALID_REGNUM) | |
14802 | break; | |
14803 | ||
a3170dc6 AH |
14804 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
14805 | info->ehrd_offset + sp_offset | |
14806 | + reg_size * (int) i); | |
83720594 RH |
14807 | |
14808 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
14809 | } | |
14810 | } | |
f676971a | 14811 | |
9ebbca7d GK |
14812 | /* Restore GPRs. This is done as a PARALLEL if we are using |
14813 | the load-multiple instructions. */ | |
14814 | if (using_load_multiple) | |
979721f8 | 14815 | { |
9ebbca7d GK |
14816 | rtvec p; |
14817 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
14818 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 14819 | { |
f676971a EC |
14820 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14821 | GEN_INT (info->gp_save_offset | |
14822 | + sp_offset | |
9ebbca7d | 14823 | + reg_size * i)); |
0be76840 | 14824 | rtx mem = gen_frame_mem (reg_mode, addr); |
9ebbca7d | 14825 | |
f676971a | 14826 | RTVEC_ELT (p, i) = |
9ebbca7d GK |
14827 | gen_rtx_SET (VOIDmode, |
14828 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
14829 | mem); | |
979721f8 | 14830 | } |
9ebbca7d | 14831 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 14832 | } |
9ebbca7d GK |
14833 | else |
14834 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6d0a8091 DJ |
14835 | if ((regs_ever_live[info->first_gp_reg_save + i] |
14836 | && (!call_used_regs[info->first_gp_reg_save + i] | |
14837 | || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM | |
b4db40bf | 14838 | && TARGET_TOC && TARGET_MINIMAL_TOC))) |
6d0a8091 | 14839 | || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 14840 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 14841 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d | 14842 | { |
f676971a EC |
14843 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14844 | GEN_INT (info->gp_save_offset | |
14845 | + sp_offset | |
9ebbca7d | 14846 | + reg_size * i)); |
0be76840 | 14847 | rtx mem = gen_frame_mem (reg_mode, addr); |
ba4828e0 | 14848 | |
a3170dc6 | 14849 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 14850 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
14851 | { |
14852 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
14853 | rtx b; | |
14854 | ||
14855 | if (!SPE_CONST_OFFSET_OK (offset)) | |
14856 | { | |
14857 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
14858 | emit_move_insn (b, GEN_INT (offset)); | |
14859 | } | |
14860 | else | |
14861 | b = GEN_INT (offset); | |
14862 | ||
14863 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
0be76840 | 14864 | mem = gen_frame_mem (V2SImode, addr); |
a3170dc6 AH |
14865 | } |
14866 | ||
f676971a | 14867 | emit_move_insn (gen_rtx_REG (reg_mode, |
a3170dc6 | 14868 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 14869 | } |
9878760c | 14870 | |
9ebbca7d GK |
14871 | /* Restore fpr's if we need to do it without calling a function. */ |
14872 | if (restoring_FPRs_inline) | |
14873 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 14874 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d GK |
14875 | && ! call_used_regs[info->first_fp_reg_save+i])) |
14876 | { | |
14877 | rtx addr, mem; | |
14878 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a EC |
14879 | GEN_INT (info->fp_save_offset |
14880 | + sp_offset | |
a4f6c312 | 14881 | + 8 * i)); |
0be76840 | 14882 | mem = gen_frame_mem (DFmode, addr); |
9ebbca7d | 14883 | |
f676971a | 14884 | emit_move_insn (gen_rtx_REG (DFmode, |
9ebbca7d GK |
14885 | info->first_fp_reg_save + i), |
14886 | mem); | |
14887 | } | |
8d30c4ee | 14888 | |
9ebbca7d GK |
14889 | /* If we saved cr, restore it here. Just those that were used. */ |
14890 | if (info->cr_save_p) | |
979721f8 | 14891 | { |
9ebbca7d | 14892 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 14893 | int count = 0; |
f676971a | 14894 | |
9ebbca7d | 14895 | if (using_mfcr_multiple) |
979721f8 | 14896 | { |
9ebbca7d GK |
14897 | for (i = 0; i < 8; i++) |
14898 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 14899 | count++; |
37409796 | 14900 | gcc_assert (count); |
e35b9579 GK |
14901 | } |
14902 | ||
14903 | if (using_mfcr_multiple && count > 1) | |
14904 | { | |
14905 | rtvec p; | |
14906 | int ndx; | |
f676971a | 14907 | |
e35b9579 | 14908 | p = rtvec_alloc (count); |
9ebbca7d | 14909 | |
e35b9579 | 14910 | ndx = 0; |
9ebbca7d GK |
14911 | for (i = 0; i < 8; i++) |
14912 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
14913 | { | |
14914 | rtvec r = rtvec_alloc (2); | |
14915 | RTVEC_ELT (r, 0) = r12_rtx; | |
14916 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 14917 | RTVEC_ELT (p, ndx) = |
f676971a | 14918 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 14919 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 14920 | ndx++; |
9ebbca7d GK |
14921 | } |
14922 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
37409796 | 14923 | gcc_assert (ndx == count); |
979721f8 MM |
14924 | } |
14925 | else | |
9ebbca7d GK |
14926 | for (i = 0; i < 8; i++) |
14927 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 14928 | { |
f676971a | 14929 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
9ebbca7d GK |
14930 | CR0_REGNO+i), |
14931 | r12_rtx)); | |
979721f8 | 14932 | } |
979721f8 MM |
14933 | } |
14934 | ||
9ebbca7d | 14935 | /* If this is V.4, unwind the stack pointer after all of the loads |
022123e6 AM |
14936 | have been done. */ |
14937 | if (frame_reg_rtx != sp_reg_rtx) | |
14938 | { | |
14939 | /* This blockage is needed so that sched doesn't decide to move | |
14940 | the sp change before the register restores. */ | |
14941 | rs6000_emit_stack_tie (); | |
14942 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); | |
14943 | } | |
14944 | else if (sp_offset != 0) | |
14945 | emit_insn (TARGET_32BIT | |
14946 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
14947 | GEN_INT (sp_offset)) | |
14948 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
14949 | GEN_INT (sp_offset))); | |
b6c9286a | 14950 | |
83720594 RH |
14951 | if (current_function_calls_eh_return) |
14952 | { | |
14953 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 14954 | emit_insn (TARGET_32BIT |
83720594 RH |
14955 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
14956 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
14957 | } | |
14958 | ||
9ebbca7d GK |
14959 | if (!sibcall) |
14960 | { | |
14961 | rtvec p; | |
14962 | if (! restoring_FPRs_inline) | |
14963 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
14964 | else | |
14965 | p = rtvec_alloc (2); | |
b6c9286a | 14966 | |
e35b9579 | 14967 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
f676971a EC |
14968 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
14969 | gen_rtx_REG (Pmode, | |
9ebbca7d | 14970 | LINK_REGISTER_REGNUM)); |
9ebbca7d GK |
14971 | |
14972 | /* If we have to restore more than two FP registers, branch to the | |
14973 | restore function. It will return to our caller. */ | |
14974 | if (! restoring_FPRs_inline) | |
14975 | { | |
14976 | int i; | |
14977 | char rname[30]; | |
520a57c8 | 14978 | const char *alloc_rname; |
979721f8 | 14979 | |
f676971a | 14980 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
9ebbca7d | 14981 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); |
a8a05998 | 14982 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
14983 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
14984 | gen_rtx_SYMBOL_REF (Pmode, | |
14985 | alloc_rname)); | |
b6c9286a | 14986 | |
9ebbca7d GK |
14987 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
14988 | { | |
14989 | rtx addr, mem; | |
14990 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
14991 | GEN_INT (info->fp_save_offset + 8*i)); | |
0be76840 | 14992 | mem = gen_frame_mem (DFmode, addr); |
9ebbca7d | 14993 | |
f676971a | 14994 | RTVEC_ELT (p, i+3) = |
9ebbca7d GK |
14995 | gen_rtx_SET (VOIDmode, |
14996 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
14997 | mem); | |
b6c9286a MM |
14998 | } |
14999 | } | |
f676971a | 15000 | |
9ebbca7d | 15001 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
3daf36a4 | 15002 | } |
9878760c RK |
15003 | } |
15004 | ||
15005 | /* Write function epilogue. */ | |
15006 | ||
08c148a8 | 15007 | static void |
f676971a | 15008 | rs6000_output_function_epilogue (FILE *file, |
a2369ed3 | 15009 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9878760c | 15010 | { |
4697a36c | 15011 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 15012 | |
9ebbca7d | 15013 | if (! HAVE_epilogue) |
9878760c | 15014 | { |
9ebbca7d GK |
15015 | rtx insn = get_last_insn (); |
15016 | /* If the last insn was a BARRIER, we don't have to write anything except | |
15017 | the trace table. */ | |
15018 | if (GET_CODE (insn) == NOTE) | |
15019 | insn = prev_nonnote_insn (insn); | |
15020 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 15021 | { |
9ebbca7d GK |
15022 | /* This is slightly ugly, but at least we don't have two |
15023 | copies of the epilogue-emitting code. */ | |
15024 | start_sequence (); | |
15025 | ||
15026 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
15027 | and end of the "toplevel" insn chain. */ | |
2e040219 | 15028 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 15029 | rs6000_emit_epilogue (FALSE); |
2e040219 | 15030 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 15031 | |
a3c9585f | 15032 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
15033 | { |
15034 | rtx insn; | |
15035 | unsigned addr = 0; | |
15036 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
15037 | { | |
15038 | INSN_ADDRESSES_NEW (insn, addr); | |
15039 | addr += 4; | |
15040 | } | |
15041 | } | |
15042 | ||
9ebbca7d | 15043 | if (TARGET_DEBUG_STACK) |
a4f6c312 | 15044 | debug_rtx_list (get_insns (), 100); |
c9d691e9 | 15045 | final (get_insns (), file, FALSE); |
9ebbca7d | 15046 | end_sequence (); |
4697a36c | 15047 | } |
9878760c | 15048 | } |
b4ac57ab | 15049 | |
efdba735 SH |
15050 | #if TARGET_MACHO |
15051 | macho_branch_islands (); | |
0e5da0be GK |
15052 | /* Mach-O doesn't support labels at the end of objects, so if |
15053 | it looks like we might want one, insert a NOP. */ | |
15054 | { | |
15055 | rtx insn = get_last_insn (); | |
15056 | while (insn | |
15057 | && NOTE_P (insn) | |
15058 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) | |
15059 | insn = PREV_INSN (insn); | |
f676971a EC |
15060 | if (insn |
15061 | && (LABEL_P (insn) | |
0e5da0be GK |
15062 | || (NOTE_P (insn) |
15063 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) | |
15064 | fputs ("\tnop\n", file); | |
15065 | } | |
15066 | #endif | |
15067 | ||
9b30bae2 | 15068 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
15069 | on its format. |
15070 | ||
15071 | We don't output a traceback table if -finhibit-size-directive was | |
15072 | used. The documentation for -finhibit-size-directive reads | |
15073 | ``don't output a @code{.size} assembler directive, or anything | |
15074 | else that would cause trouble if the function is split in the | |
15075 | middle, and the two halves are placed at locations far apart in | |
15076 | memory.'' The traceback table has this property, since it | |
15077 | includes the offset from the start of the function to the | |
4d30c363 MM |
15078 | traceback table itself. |
15079 | ||
15080 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 15081 | different traceback table. */ |
57ac7be9 AM |
15082 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
15083 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 15084 | { |
69c75916 | 15085 | const char *fname = NULL; |
3ac88239 | 15086 | const char *language_string = lang_hooks.name; |
6041bf2f | 15087 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 15088 | int i; |
57ac7be9 AM |
15089 | int optional_tbtab; |
15090 | ||
15091 | if (rs6000_traceback == traceback_full) | |
15092 | optional_tbtab = 1; | |
15093 | else if (rs6000_traceback == traceback_part) | |
15094 | optional_tbtab = 0; | |
15095 | else | |
15096 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 15097 | |
69c75916 AM |
15098 | if (optional_tbtab) |
15099 | { | |
15100 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
15101 | while (*fname == '.') /* V.4 encodes . in the name */ | |
15102 | fname++; | |
15103 | ||
15104 | /* Need label immediately before tbtab, so we can compute | |
15105 | its offset from the function start. */ | |
15106 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
15107 | ASM_OUTPUT_LABEL (file, fname); | |
15108 | } | |
314fc5a9 ILT |
15109 | |
15110 | /* The .tbtab pseudo-op can only be used for the first eight | |
15111 | expressions, since it can't handle the possibly variable | |
15112 | length fields that follow. However, if you omit the optional | |
15113 | fields, the assembler outputs zeros for all optional fields | |
15114 | anyways, giving each variable length field is minimum length | |
15115 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
15116 | pseudo-op at all. */ | |
15117 | ||
15118 | /* An all-zero word flags the start of the tbtab, for debuggers | |
15119 | that have to find it by searching forward from the entry | |
15120 | point or from the current pc. */ | |
19d2d16f | 15121 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
15122 | |
15123 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 15124 | fputs ("\t.byte 0,", file); |
314fc5a9 | 15125 | |
5fc921c1 DE |
15126 | /* Language type. Unfortunately, there does not seem to be any |
15127 | official way to discover the language being compiled, so we | |
15128 | use language_string. | |
15129 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
15130 | Java is 13. Objective-C is 14. */ | |
15131 | if (! strcmp (language_string, "GNU C")) | |
314fc5a9 | 15132 | i = 0; |
6de9cd9a DN |
15133 | else if (! strcmp (language_string, "GNU F77") |
15134 | || ! strcmp (language_string, "GNU F95")) | |
314fc5a9 | 15135 | i = 1; |
8b83775b | 15136 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 15137 | i = 2; |
5fc921c1 DE |
15138 | else if (! strcmp (language_string, "GNU Ada")) |
15139 | i = 3; | |
314fc5a9 ILT |
15140 | else if (! strcmp (language_string, "GNU C++")) |
15141 | i = 9; | |
9517ead8 AG |
15142 | else if (! strcmp (language_string, "GNU Java")) |
15143 | i = 13; | |
5fc921c1 DE |
15144 | else if (! strcmp (language_string, "GNU Objective-C")) |
15145 | i = 14; | |
314fc5a9 | 15146 | else |
37409796 | 15147 | gcc_unreachable (); |
314fc5a9 ILT |
15148 | fprintf (file, "%d,", i); |
15149 | ||
15150 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
15151 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
15152 | from start of procedure stored in tbtab, internal function, function | |
15153 | has controlled storage, function has no toc, function uses fp, | |
15154 | function logs/aborts fp operations. */ | |
15155 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
15156 | fprintf (file, "%d,", |
15157 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
15158 | |
15159 | /* 6 bitfields: function is interrupt handler, name present in | |
15160 | proc table, function calls alloca, on condition directives | |
15161 | (controls stack walks, 3 bits), saves condition reg, saves | |
15162 | link reg. */ | |
15163 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
15164 | set up as a frame pointer, even when there is no alloca call. */ | |
15165 | fprintf (file, "%d,", | |
6041bf2f DE |
15166 | ((optional_tbtab << 6) |
15167 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
15168 | | (info->cr_save_p << 1) | |
15169 | | (info->lr_save_p))); | |
314fc5a9 | 15170 | |
6041bf2f | 15171 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
15172 | (6 bits). */ |
15173 | fprintf (file, "%d,", | |
4697a36c | 15174 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
15175 | |
15176 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
15177 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
15178 | ||
6041bf2f DE |
15179 | if (optional_tbtab) |
15180 | { | |
15181 | /* Compute the parameter info from the function decl argument | |
15182 | list. */ | |
15183 | tree decl; | |
15184 | int next_parm_info_bit = 31; | |
314fc5a9 | 15185 | |
6041bf2f DE |
15186 | for (decl = DECL_ARGUMENTS (current_function_decl); |
15187 | decl; decl = TREE_CHAIN (decl)) | |
15188 | { | |
15189 | rtx parameter = DECL_INCOMING_RTL (decl); | |
15190 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 15191 | |
6041bf2f DE |
15192 | if (GET_CODE (parameter) == REG) |
15193 | { | |
ebb109ad | 15194 | if (SCALAR_FLOAT_MODE_P (mode)) |
6041bf2f DE |
15195 | { |
15196 | int bits; | |
15197 | ||
15198 | float_parms++; | |
15199 | ||
37409796 NS |
15200 | switch (mode) |
15201 | { | |
15202 | case SFmode: | |
15203 | bits = 0x2; | |
15204 | break; | |
15205 | ||
15206 | case DFmode: | |
15207 | case TFmode: | |
15208 | bits = 0x3; | |
15209 | break; | |
15210 | ||
15211 | default: | |
15212 | gcc_unreachable (); | |
15213 | } | |
6041bf2f DE |
15214 | |
15215 | /* If only one bit will fit, don't or in this entry. */ | |
15216 | if (next_parm_info_bit > 0) | |
15217 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
15218 | next_parm_info_bit -= 2; | |
15219 | } | |
15220 | else | |
15221 | { | |
15222 | fixed_parms += ((GET_MODE_SIZE (mode) | |
15223 | + (UNITS_PER_WORD - 1)) | |
15224 | / UNITS_PER_WORD); | |
15225 | next_parm_info_bit -= 1; | |
15226 | } | |
15227 | } | |
15228 | } | |
15229 | } | |
314fc5a9 ILT |
15230 | |
15231 | /* Number of fixed point parameters. */ | |
15232 | /* This is actually the number of words of fixed point parameters; thus | |
15233 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
15234 | fprintf (file, "%d,", fixed_parms); | |
15235 | ||
15236 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
15237 | all on stack. */ | |
15238 | /* This is actually the number of fp registers that hold parameters; | |
15239 | and thus the maximum value is 13. */ | |
15240 | /* Set parameters on stack bit if parameters are not in their original | |
15241 | registers, regardless of whether they are on the stack? Xlc | |
15242 | seems to set the bit when not optimizing. */ | |
15243 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
15244 | ||
6041bf2f DE |
15245 | if (! optional_tbtab) |
15246 | return; | |
15247 | ||
314fc5a9 ILT |
15248 | /* Optional fields follow. Some are variable length. */ |
15249 | ||
15250 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
15251 | 11 double float. */ | |
15252 | /* There is an entry for each parameter in a register, in the order that | |
15253 | they occur in the parameter list. Any intervening arguments on the | |
15254 | stack are ignored. If the list overflows a long (max possible length | |
15255 | 34 bits) then completely leave off all elements that don't fit. */ | |
15256 | /* Only emit this long if there was at least one parameter. */ | |
15257 | if (fixed_parms || float_parms) | |
15258 | fprintf (file, "\t.long %d\n", parm_info); | |
15259 | ||
15260 | /* Offset from start of code to tb table. */ | |
19d2d16f | 15261 | fputs ("\t.long ", file); |
314fc5a9 | 15262 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
85b776df AM |
15263 | if (TARGET_AIX) |
15264 | RS6000_OUTPUT_BASENAME (file, fname); | |
15265 | else | |
15266 | assemble_name (file, fname); | |
15267 | putc ('-', file); | |
15268 | rs6000_output_function_entry (file, fname); | |
19d2d16f | 15269 | putc ('\n', file); |
314fc5a9 ILT |
15270 | |
15271 | /* Interrupt handler mask. */ | |
15272 | /* Omit this long, since we never set the interrupt handler bit | |
15273 | above. */ | |
15274 | ||
15275 | /* Number of CTL (controlled storage) anchors. */ | |
15276 | /* Omit this long, since the has_ctl bit is never set above. */ | |
15277 | ||
15278 | /* Displacement into stack of each CTL anchor. */ | |
15279 | /* Omit this list of longs, because there are no CTL anchors. */ | |
15280 | ||
15281 | /* Length of function name. */ | |
69c75916 AM |
15282 | if (*fname == '*') |
15283 | ++fname; | |
296b8152 | 15284 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
15285 | |
15286 | /* Function name. */ | |
15287 | assemble_string (fname, strlen (fname)); | |
15288 | ||
15289 | /* Register for alloca automatic storage; this is always reg 31. | |
15290 | Only emit this if the alloca bit was set above. */ | |
15291 | if (frame_pointer_needed) | |
19d2d16f | 15292 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
15293 | |
15294 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 15295 | } |
9878760c | 15296 | } |
17167fd8 | 15297 | \f |
a4f6c312 SS |
15298 | /* A C compound statement that outputs the assembler code for a thunk |
15299 | function, used to implement C++ virtual function calls with | |
15300 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
15301 | function, adjusting the implicit object parameter before handing | |
15302 | control off to the real function. | |
15303 | ||
15304 | First, emit code to add the integer DELTA to the location that | |
15305 | contains the incoming first argument. Assume that this argument | |
15306 | contains a pointer, and is the one used to pass the `this' pointer | |
15307 | in C++. This is the incoming argument *before* the function | |
15308 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
15309 | values of all other incoming arguments. | |
17167fd8 MM |
15310 | |
15311 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
15312 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
15313 | not touch the return address. Hence returning from FUNCTION will | |
15314 | return to whoever called the current `thunk'. | |
17167fd8 | 15315 | |
a4f6c312 SS |
15316 | The effect must be as if FUNCTION had been called directly with the |
15317 | adjusted first argument. This macro is responsible for emitting | |
15318 | all of the code for a thunk function; output_function_prologue() | |
15319 | and output_function_epilogue() are not invoked. | |
17167fd8 | 15320 | |
a4f6c312 SS |
15321 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
15322 | been extracted from it.) It might possibly be useful on some | |
15323 | targets, but probably not. | |
17167fd8 | 15324 | |
a4f6c312 SS |
15325 | If you do not define this macro, the target-independent code in the |
15326 | C++ frontend will generate a less efficient heavyweight thunk that | |
15327 | calls FUNCTION instead of jumping to it. The generic approach does | |
15328 | not support varargs. */ | |
17167fd8 | 15329 | |
3961e8fe | 15330 | static void |
f676971a EC |
15331 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
15332 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
a2369ed3 | 15333 | tree function) |
17167fd8 | 15334 | { |
5b71a4e7 | 15335 | rtx this, insn, funexp; |
17167fd8 | 15336 | |
5b71a4e7 | 15337 | reload_completed = 1; |
fe3ad572 | 15338 | epilogue_completed = 1; |
5b71a4e7 | 15339 | no_new_pseudos = 1; |
6429e3be | 15340 | reset_block_changes (); |
56a7189a | 15341 | |
5b71a4e7 | 15342 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 15343 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 15344 | |
5b71a4e7 DE |
15345 | /* Find the "this" pointer. If the function returns a structure, |
15346 | the structure return pointer is in r3. */ | |
61f71b34 | 15347 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
5b71a4e7 | 15348 | this = gen_rtx_REG (Pmode, 4); |
56a7189a | 15349 | else |
5b71a4e7 | 15350 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 15351 | |
5b71a4e7 DE |
15352 | /* Apply the constant offset, if required. */ |
15353 | if (delta) | |
15354 | { | |
15355 | rtx delta_rtx = GEN_INT (delta); | |
15356 | emit_insn (TARGET_32BIT | |
15357 | ? gen_addsi3 (this, this, delta_rtx) | |
15358 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
15359 | } |
15360 | ||
5b71a4e7 DE |
15361 | /* Apply the offset from the vtable, if required. */ |
15362 | if (vcall_offset) | |
17167fd8 | 15363 | { |
5b71a4e7 DE |
15364 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
15365 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 15366 | |
5b71a4e7 | 15367 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
eeff9307 JJ |
15368 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
15369 | { | |
15370 | emit_insn (TARGET_32BIT | |
15371 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
15372 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
15373 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
15374 | } | |
15375 | else | |
15376 | { | |
15377 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
15378 | ||
15379 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
15380 | } | |
5b71a4e7 DE |
15381 | emit_insn (TARGET_32BIT |
15382 | ? gen_addsi3 (this, this, tmp) | |
15383 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
15384 | } |
15385 | ||
5b71a4e7 DE |
15386 | /* Generate a tail call to the target function. */ |
15387 | if (!TREE_USED (function)) | |
15388 | { | |
15389 | assemble_external (function); | |
15390 | TREE_USED (function) = 1; | |
15391 | } | |
15392 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 15393 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
15394 | |
15395 | #if TARGET_MACHO | |
ab82a49f | 15396 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 15397 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 15398 | #endif |
5b71a4e7 DE |
15399 | |
15400 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
992d08b1 | 15401 | generate sibcall RTL explicitly. */ |
5b71a4e7 DE |
15402 | insn = emit_call_insn ( |
15403 | gen_rtx_PARALLEL (VOIDmode, | |
15404 | gen_rtvec (4, | |
15405 | gen_rtx_CALL (VOIDmode, | |
15406 | funexp, const0_rtx), | |
15407 | gen_rtx_USE (VOIDmode, const0_rtx), | |
15408 | gen_rtx_USE (VOIDmode, | |
15409 | gen_rtx_REG (SImode, | |
15410 | LINK_REGISTER_REGNUM)), | |
15411 | gen_rtx_RETURN (VOIDmode)))); | |
15412 | SIBLING_CALL_P (insn) = 1; | |
15413 | emit_barrier (); | |
15414 | ||
15415 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
15416 | There's not really enough bulk here to make other passes such as | |
15417 | instruction scheduling worth while. Note that use_thunk calls | |
15418 | assemble_start_function and assemble_end_function. */ | |
15419 | insn = get_insns (); | |
a2855205 | 15420 | insn_locators_initialize (); |
5b71a4e7 DE |
15421 | shorten_branches (insn); |
15422 | final_start_function (insn, file, 1); | |
c9d691e9 | 15423 | final (insn, file, 1); |
5b71a4e7 DE |
15424 | final_end_function (); |
15425 | ||
15426 | reload_completed = 0; | |
fe3ad572 | 15427 | epilogue_completed = 0; |
5b71a4e7 | 15428 | no_new_pseudos = 0; |
9ebbca7d | 15429 | } |
9ebbca7d GK |
15430 | \f |
15431 | /* A quick summary of the various types of 'constant-pool tables' | |
15432 | under PowerPC: | |
15433 | ||
f676971a | 15434 | Target Flags Name One table per |
9ebbca7d GK |
15435 | AIX (none) AIX TOC object file |
15436 | AIX -mfull-toc AIX TOC object file | |
15437 | AIX -mminimal-toc AIX minimal TOC translation unit | |
15438 | SVR4/EABI (none) SVR4 SDATA object file | |
15439 | SVR4/EABI -fpic SVR4 pic object file | |
15440 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
15441 | SVR4/EABI -mrelocatable EABI TOC function | |
15442 | SVR4/EABI -maix AIX TOC object file | |
f676971a | 15443 | SVR4/EABI -maix -mminimal-toc |
9ebbca7d GK |
15444 | AIX minimal TOC translation unit |
15445 | ||
15446 | Name Reg. Set by entries contains: | |
15447 | made by addrs? fp? sum? | |
15448 | ||
15449 | AIX TOC 2 crt0 as Y option option | |
15450 | AIX minimal TOC 30 prolog gcc Y Y option | |
15451 | SVR4 SDATA 13 crt0 gcc N Y N | |
15452 | SVR4 pic 30 prolog ld Y not yet N | |
15453 | SVR4 PIC 30 prolog gcc Y option option | |
15454 | EABI TOC 30 prolog gcc Y option option | |
15455 | ||
15456 | */ | |
15457 | ||
9ebbca7d GK |
15458 | /* Hash functions for the hash table. */ |
15459 | ||
15460 | static unsigned | |
a2369ed3 | 15461 | rs6000_hash_constant (rtx k) |
9ebbca7d | 15462 | { |
46b33600 RH |
15463 | enum rtx_code code = GET_CODE (k); |
15464 | enum machine_mode mode = GET_MODE (k); | |
15465 | unsigned result = (code << 3) ^ mode; | |
15466 | const char *format; | |
15467 | int flen, fidx; | |
f676971a | 15468 | |
46b33600 RH |
15469 | format = GET_RTX_FORMAT (code); |
15470 | flen = strlen (format); | |
15471 | fidx = 0; | |
9ebbca7d | 15472 | |
46b33600 RH |
15473 | switch (code) |
15474 | { | |
15475 | case LABEL_REF: | |
15476 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
15477 | ||
15478 | case CONST_DOUBLE: | |
15479 | if (mode != VOIDmode) | |
15480 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
15481 | flen = 2; | |
15482 | break; | |
15483 | ||
15484 | case CODE_LABEL: | |
15485 | fidx = 3; | |
15486 | break; | |
15487 | ||
15488 | default: | |
15489 | break; | |
15490 | } | |
9ebbca7d GK |
15491 | |
15492 | for (; fidx < flen; fidx++) | |
15493 | switch (format[fidx]) | |
15494 | { | |
15495 | case 's': | |
15496 | { | |
15497 | unsigned i, len; | |
15498 | const char *str = XSTR (k, fidx); | |
15499 | len = strlen (str); | |
15500 | result = result * 613 + len; | |
15501 | for (i = 0; i < len; i++) | |
15502 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
15503 | break; |
15504 | } | |
9ebbca7d GK |
15505 | case 'u': |
15506 | case 'e': | |
15507 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
15508 | break; | |
15509 | case 'i': | |
15510 | case 'n': | |
15511 | result = result * 613 + (unsigned) XINT (k, fidx); | |
15512 | break; | |
15513 | case 'w': | |
15514 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
15515 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
15516 | else | |
15517 | { | |
15518 | size_t i; | |
9390387d | 15519 | for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++) |
9ebbca7d GK |
15520 | result = result * 613 + (unsigned) (XWINT (k, fidx) |
15521 | >> CHAR_BIT * i); | |
15522 | } | |
15523 | break; | |
09501938 DE |
15524 | case '0': |
15525 | break; | |
9ebbca7d | 15526 | default: |
37409796 | 15527 | gcc_unreachable (); |
9ebbca7d | 15528 | } |
46b33600 | 15529 | |
9ebbca7d GK |
15530 | return result; |
15531 | } | |
15532 | ||
15533 | static unsigned | |
a2369ed3 | 15534 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 15535 | { |
f676971a | 15536 | const struct toc_hash_struct *thc = |
a9098fd0 GK |
15537 | (const struct toc_hash_struct *) hash_entry; |
15538 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
15539 | } |
15540 | ||
15541 | /* Compare H1 and H2 for equivalence. */ | |
15542 | ||
15543 | static int | |
a2369ed3 | 15544 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
15545 | { |
15546 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
15547 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
15548 | ||
a9098fd0 GK |
15549 | if (((const struct toc_hash_struct *) h1)->key_mode |
15550 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
15551 | return 0; | |
15552 | ||
5692c7bc | 15553 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
15554 | } |
15555 | ||
28e510bd MM |
15556 | /* These are the names given by the C++ front-end to vtables, and |
15557 | vtable-like objects. Ideally, this logic should not be here; | |
15558 | instead, there should be some programmatic way of inquiring as | |
15559 | to whether or not an object is a vtable. */ | |
15560 | ||
15561 | #define VTABLE_NAME_P(NAME) \ | |
9390387d | 15562 | (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \ |
28e510bd MM |
15563 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ |
15564 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
26be75db | 15565 | || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ |
f676971a | 15566 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) |
28e510bd MM |
15567 | |
15568 | void | |
a2369ed3 | 15569 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
15570 | { |
15571 | /* Currently C++ toc references to vtables can be emitted before it | |
15572 | is decided whether the vtable is public or private. If this is | |
15573 | the case, then the linker will eventually complain that there is | |
f676971a | 15574 | a reference to an unknown section. Thus, for vtables only, |
28e510bd MM |
15575 | we emit the TOC reference to reference the symbol and not the |
15576 | section. */ | |
15577 | const char *name = XSTR (x, 0); | |
54ee9799 | 15578 | |
f676971a | 15579 | if (VTABLE_NAME_P (name)) |
54ee9799 DE |
15580 | { |
15581 | RS6000_OUTPUT_BASENAME (file, name); | |
15582 | } | |
15583 | else | |
15584 | assemble_name (file, name); | |
28e510bd MM |
15585 | } |
15586 | ||
a4f6c312 SS |
15587 | /* Output a TOC entry. We derive the entry name from what is being |
15588 | written. */ | |
9878760c RK |
15589 | |
15590 | void | |
a2369ed3 | 15591 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
15592 | { |
15593 | char buf[256]; | |
3cce094d | 15594 | const char *name = buf; |
ec940faa | 15595 | const char *real_name; |
9878760c | 15596 | rtx base = x; |
16fdeb48 | 15597 | HOST_WIDE_INT offset = 0; |
9878760c | 15598 | |
37409796 | 15599 | gcc_assert (!TARGET_NO_TOC); |
4697a36c | 15600 | |
9ebbca7d GK |
15601 | /* When the linker won't eliminate them, don't output duplicate |
15602 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
15603 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
15604 | CODE_LABELs. */ | |
15605 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
15606 | { |
15607 | struct toc_hash_struct *h; | |
15608 | void * * found; | |
f676971a | 15609 | |
17211ab5 | 15610 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
c4ad648e | 15611 | time because GGC is not initialized at that point. */ |
17211ab5 | 15612 | if (toc_hash_table == NULL) |
f676971a | 15613 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, |
17211ab5 GK |
15614 | toc_hash_eq, NULL); |
15615 | ||
9ebbca7d GK |
15616 | h = ggc_alloc (sizeof (*h)); |
15617 | h->key = x; | |
a9098fd0 | 15618 | h->key_mode = mode; |
9ebbca7d | 15619 | h->labelno = labelno; |
f676971a | 15620 | |
9ebbca7d GK |
15621 | found = htab_find_slot (toc_hash_table, h, 1); |
15622 | if (*found == NULL) | |
15623 | *found = h; | |
f676971a | 15624 | else /* This is indeed a duplicate. |
9ebbca7d GK |
15625 | Set this label equal to that label. */ |
15626 | { | |
15627 | fputs ("\t.set ", file); | |
15628 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
15629 | fprintf (file, "%d,", labelno); | |
15630 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
f676971a | 15631 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) |
9ebbca7d GK |
15632 | found)->labelno)); |
15633 | return; | |
15634 | } | |
15635 | } | |
15636 | ||
15637 | /* If we're going to put a double constant in the TOC, make sure it's | |
15638 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
15639 | if (GET_CODE (x) == CONST_DOUBLE |
15640 | && STRICT_ALIGNMENT | |
a9098fd0 | 15641 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
15642 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
15643 | ASM_OUTPUT_ALIGN (file, 3); | |
15644 | } | |
15645 | ||
4977bab6 | 15646 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 15647 | |
37c37a57 RK |
15648 | /* Handle FP constants specially. Note that if we have a minimal |
15649 | TOC, things we put here aren't actually in the TOC, so we can allow | |
15650 | FP constants. */ | |
fcce224d DE |
15651 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
15652 | { | |
15653 | REAL_VALUE_TYPE rv; | |
15654 | long k[4]; | |
15655 | ||
15656 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
15657 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
15658 | ||
15659 | if (TARGET_64BIT) | |
15660 | { | |
15661 | if (TARGET_MINIMAL_TOC) | |
15662 | fputs (DOUBLE_INT_ASM_OP, file); | |
15663 | else | |
15664 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
15665 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15666 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15667 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
15668 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15669 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15670 | return; | |
15671 | } | |
15672 | else | |
15673 | { | |
15674 | if (TARGET_MINIMAL_TOC) | |
15675 | fputs ("\t.long ", file); | |
15676 | else | |
15677 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
15678 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15679 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15680 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
15681 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15682 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15683 | return; | |
15684 | } | |
15685 | } | |
15686 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 15687 | { |
042259f2 DE |
15688 | REAL_VALUE_TYPE rv; |
15689 | long k[2]; | |
0adc764e | 15690 | |
042259f2 DE |
15691 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
15692 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 15693 | |
13ded975 DE |
15694 | if (TARGET_64BIT) |
15695 | { | |
15696 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15697 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 15698 | else |
2f0552b6 AM |
15699 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
15700 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
15701 | fprintf (file, "0x%lx%08lx\n", | |
15702 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
15703 | return; |
15704 | } | |
1875cc88 | 15705 | else |
13ded975 DE |
15706 | { |
15707 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15708 | fputs ("\t.long ", file); |
13ded975 | 15709 | else |
2f0552b6 AM |
15710 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
15711 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
15712 | fprintf (file, "0x%lx,0x%lx\n", | |
15713 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
15714 | return; |
15715 | } | |
9878760c | 15716 | } |
a9098fd0 | 15717 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 15718 | { |
042259f2 DE |
15719 | REAL_VALUE_TYPE rv; |
15720 | long l; | |
9878760c | 15721 | |
042259f2 DE |
15722 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
15723 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
15724 | ||
31bfaa0b DE |
15725 | if (TARGET_64BIT) |
15726 | { | |
15727 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15728 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 15729 | else |
2f0552b6 AM |
15730 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
15731 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
15732 | return; |
15733 | } | |
042259f2 | 15734 | else |
31bfaa0b DE |
15735 | { |
15736 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15737 | fputs ("\t.long ", file); |
31bfaa0b | 15738 | else |
2f0552b6 AM |
15739 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
15740 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
15741 | return; |
15742 | } | |
042259f2 | 15743 | } |
f176e826 | 15744 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 15745 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 15746 | { |
e2c953b6 | 15747 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
15748 | HOST_WIDE_INT high; |
15749 | ||
15750 | if (GET_CODE (x) == CONST_DOUBLE) | |
15751 | { | |
15752 | low = CONST_DOUBLE_LOW (x); | |
15753 | high = CONST_DOUBLE_HIGH (x); | |
15754 | } | |
15755 | else | |
15756 | #if HOST_BITS_PER_WIDE_INT == 32 | |
15757 | { | |
15758 | low = INTVAL (x); | |
0858c623 | 15759 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
15760 | } |
15761 | #else | |
15762 | { | |
c4ad648e AM |
15763 | low = INTVAL (x) & 0xffffffff; |
15764 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; | |
042259f2 DE |
15765 | } |
15766 | #endif | |
9878760c | 15767 | |
a9098fd0 GK |
15768 | /* TOC entries are always Pmode-sized, but since this |
15769 | is a bigendian machine then if we're putting smaller | |
15770 | integer constants in the TOC we have to pad them. | |
15771 | (This is still a win over putting the constants in | |
15772 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
15773 | to have both a TOC entry _and_ the actual constant.) |
15774 | ||
15775 | For a 32-bit target, CONST_INT values are loaded and shifted | |
15776 | entirely within `low' and can be stored in one TOC entry. */ | |
15777 | ||
37409796 NS |
15778 | /* It would be easy to make this work, but it doesn't now. */ |
15779 | gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode)); | |
02a4ec28 FS |
15780 | |
15781 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
15782 | { |
15783 | #if HOST_BITS_PER_WIDE_INT == 32 | |
15784 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
15785 | POINTER_SIZE, &low, &high, 0); | |
15786 | #else | |
15787 | low |= high << 32; | |
15788 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
15789 | high = (HOST_WIDE_INT) low >> 32; | |
15790 | low &= 0xffffffff; | |
15791 | #endif | |
15792 | } | |
a9098fd0 | 15793 | |
13ded975 DE |
15794 | if (TARGET_64BIT) |
15795 | { | |
15796 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15797 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 15798 | else |
2f0552b6 AM |
15799 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
15800 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
15801 | fprintf (file, "0x%lx%08lx\n", | |
15802 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
15803 | return; |
15804 | } | |
1875cc88 | 15805 | else |
13ded975 | 15806 | { |
02a4ec28 FS |
15807 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
15808 | { | |
15809 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15810 | fputs ("\t.long ", file); |
02a4ec28 | 15811 | else |
2bfcf297 | 15812 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
15813 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
15814 | fprintf (file, "0x%lx,0x%lx\n", | |
15815 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 15816 | } |
13ded975 | 15817 | else |
02a4ec28 FS |
15818 | { |
15819 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15820 | fputs ("\t.long ", file); |
02a4ec28 | 15821 | else |
2f0552b6 AM |
15822 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
15823 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 15824 | } |
13ded975 DE |
15825 | return; |
15826 | } | |
9878760c RK |
15827 | } |
15828 | ||
15829 | if (GET_CODE (x) == CONST) | |
15830 | { | |
37409796 | 15831 | gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS); |
2bfcf297 | 15832 | |
9878760c RK |
15833 | base = XEXP (XEXP (x, 0), 0); |
15834 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
15835 | } | |
f676971a | 15836 | |
37409796 NS |
15837 | switch (GET_CODE (base)) |
15838 | { | |
15839 | case SYMBOL_REF: | |
15840 | name = XSTR (base, 0); | |
15841 | break; | |
15842 | ||
15843 | case LABEL_REF: | |
15844 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", | |
15845 | CODE_LABEL_NUMBER (XEXP (base, 0))); | |
15846 | break; | |
15847 | ||
15848 | case CODE_LABEL: | |
15849 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
15850 | break; | |
15851 | ||
15852 | default: | |
15853 | gcc_unreachable (); | |
15854 | } | |
9878760c | 15855 | |
772c5265 | 15856 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 15857 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 15858 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
15859 | else |
15860 | { | |
b6c9286a | 15861 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 15862 | |
1875cc88 | 15863 | if (offset < 0) |
16fdeb48 | 15864 | fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset); |
1875cc88 | 15865 | else if (offset) |
16fdeb48 | 15866 | fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset); |
9878760c | 15867 | |
19d2d16f | 15868 | fputs ("[TC],", file); |
1875cc88 | 15869 | } |
581bc4de MM |
15870 | |
15871 | /* Currently C++ toc references to vtables can be emitted before it | |
15872 | is decided whether the vtable is public or private. If this is | |
15873 | the case, then the linker will eventually complain that there is | |
15874 | a TOC reference to an unknown section. Thus, for vtables only, | |
15875 | we emit the TOC reference to reference the symbol and not the | |
15876 | section. */ | |
28e510bd | 15877 | if (VTABLE_NAME_P (name)) |
581bc4de | 15878 | { |
54ee9799 | 15879 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de | 15880 | if (offset < 0) |
16fdeb48 | 15881 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset); |
581bc4de | 15882 | else if (offset > 0) |
16fdeb48 | 15883 | fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset); |
581bc4de MM |
15884 | } |
15885 | else | |
15886 | output_addr_const (file, x); | |
19d2d16f | 15887 | putc ('\n', file); |
9878760c RK |
15888 | } |
15889 | \f | |
15890 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
15891 | starting at P to FILE. | |
15892 | ||
15893 | On the RS/6000, we have to do this using the .byte operation and | |
15894 | write out special characters outside the quoted string. | |
15895 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 15896 | so we must artificially break them up early. */ |
9878760c RK |
15897 | |
15898 | void | |
a2369ed3 | 15899 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
15900 | { |
15901 | char c; | |
15902 | int i, count_string; | |
d330fd93 KG |
15903 | const char *for_string = "\t.byte \""; |
15904 | const char *for_decimal = "\t.byte "; | |
15905 | const char *to_close = NULL; | |
9878760c RK |
15906 | |
15907 | count_string = 0; | |
15908 | for (i = 0; i < n; i++) | |
15909 | { | |
15910 | c = *p++; | |
15911 | if (c >= ' ' && c < 0177) | |
15912 | { | |
15913 | if (for_string) | |
15914 | fputs (for_string, file); | |
15915 | putc (c, file); | |
15916 | ||
15917 | /* Write two quotes to get one. */ | |
15918 | if (c == '"') | |
15919 | { | |
15920 | putc (c, file); | |
15921 | ++count_string; | |
15922 | } | |
15923 | ||
15924 | for_string = NULL; | |
15925 | for_decimal = "\"\n\t.byte "; | |
15926 | to_close = "\"\n"; | |
15927 | ++count_string; | |
15928 | ||
15929 | if (count_string >= 512) | |
15930 | { | |
15931 | fputs (to_close, file); | |
15932 | ||
15933 | for_string = "\t.byte \""; | |
15934 | for_decimal = "\t.byte "; | |
15935 | to_close = NULL; | |
15936 | count_string = 0; | |
15937 | } | |
15938 | } | |
15939 | else | |
15940 | { | |
15941 | if (for_decimal) | |
15942 | fputs (for_decimal, file); | |
15943 | fprintf (file, "%d", c); | |
15944 | ||
15945 | for_string = "\n\t.byte \""; | |
15946 | for_decimal = ", "; | |
15947 | to_close = "\n"; | |
15948 | count_string = 0; | |
15949 | } | |
15950 | } | |
15951 | ||
15952 | /* Now close the string if we have written one. Then end the line. */ | |
15953 | if (to_close) | |
9ebbca7d | 15954 | fputs (to_close, file); |
9878760c RK |
15955 | } |
15956 | \f | |
15957 | /* Generate a unique section name for FILENAME for a section type | |
15958 | represented by SECTION_DESC. Output goes into BUF. | |
15959 | ||
15960 | SECTION_DESC can be any string, as long as it is different for each | |
15961 | possible section type. | |
15962 | ||
15963 | We name the section in the same manner as xlc. The name begins with an | |
15964 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
15965 | names) with the last period replaced by the string SECTION_DESC. If |
15966 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
15967 | the name. */ | |
9878760c RK |
15968 | |
15969 | void | |
f676971a | 15970 | rs6000_gen_section_name (char **buf, const char *filename, |
c4ad648e | 15971 | const char *section_desc) |
9878760c | 15972 | { |
9ebbca7d | 15973 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
15974 | char *p; |
15975 | int len; | |
9878760c RK |
15976 | |
15977 | after_last_slash = filename; | |
15978 | for (q = filename; *q; q++) | |
11e5fe42 RK |
15979 | { |
15980 | if (*q == '/') | |
15981 | after_last_slash = q + 1; | |
15982 | else if (*q == '.') | |
15983 | last_period = q; | |
15984 | } | |
9878760c | 15985 | |
11e5fe42 | 15986 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 15987 | *buf = (char *) xmalloc (len); |
9878760c RK |
15988 | |
15989 | p = *buf; | |
15990 | *p++ = '_'; | |
15991 | ||
15992 | for (q = after_last_slash; *q; q++) | |
15993 | { | |
11e5fe42 | 15994 | if (q == last_period) |
c4ad648e | 15995 | { |
9878760c RK |
15996 | strcpy (p, section_desc); |
15997 | p += strlen (section_desc); | |
e3981aab | 15998 | break; |
c4ad648e | 15999 | } |
9878760c | 16000 | |
e9a780ec | 16001 | else if (ISALNUM (*q)) |
c4ad648e | 16002 | *p++ = *q; |
9878760c RK |
16003 | } |
16004 | ||
11e5fe42 | 16005 | if (last_period == 0) |
9878760c RK |
16006 | strcpy (p, section_desc); |
16007 | else | |
16008 | *p = '\0'; | |
16009 | } | |
e165f3f0 | 16010 | \f |
a4f6c312 | 16011 | /* Emit profile function. */ |
411707f4 | 16012 | |
411707f4 | 16013 | void |
a2369ed3 | 16014 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 16015 | { |
858081ad AH |
16016 | /* Non-standard profiling for kernels, which just saves LR then calls |
16017 | _mcount without worrying about arg saves. The idea is to change | |
16018 | the function prologue as little as possible as it isn't easy to | |
16019 | account for arg save/restore code added just for _mcount. */ | |
ffcfcb5f AM |
16020 | if (TARGET_PROFILE_KERNEL) |
16021 | return; | |
16022 | ||
8480e480 CC |
16023 | if (DEFAULT_ABI == ABI_AIX) |
16024 | { | |
9739c90c JJ |
16025 | #ifndef NO_PROFILE_COUNTERS |
16026 | # define NO_PROFILE_COUNTERS 0 | |
16027 | #endif | |
f676971a | 16028 | if (NO_PROFILE_COUNTERS) |
9739c90c JJ |
16029 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); |
16030 | else | |
16031 | { | |
16032 | char buf[30]; | |
16033 | const char *label_name; | |
16034 | rtx fun; | |
411707f4 | 16035 | |
9739c90c JJ |
16036 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
16037 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
16038 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 16039 | |
9739c90c JJ |
16040 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
16041 | fun, Pmode); | |
16042 | } | |
8480e480 | 16043 | } |
ee890fe2 SS |
16044 | else if (DEFAULT_ABI == ABI_DARWIN) |
16045 | { | |
d5fa86ba | 16046 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
16047 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
16048 | ||
16049 | /* Be conservative and always set this, at least for now. */ | |
16050 | current_function_uses_pic_offset_table = 1; | |
16051 | ||
16052 | #if TARGET_MACHO | |
16053 | /* For PIC code, set up a stub and collect the caller's address | |
16054 | from r0, which is where the prologue puts it. */ | |
11abc112 MM |
16055 | if (MACHOPIC_INDIRECT |
16056 | && current_function_uses_pic_offset_table) | |
16057 | caller_addr_regno = 0; | |
ee890fe2 SS |
16058 | #endif |
16059 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
16060 | 0, VOIDmode, 1, | |
16061 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
16062 | } | |
411707f4 CC |
16063 | } |
16064 | ||
a4f6c312 | 16065 | /* Write function profiler code. */ |
e165f3f0 RK |
16066 | |
16067 | void | |
a2369ed3 | 16068 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 16069 | { |
3daf36a4 | 16070 | char buf[100]; |
e165f3f0 | 16071 | |
38c1f2d7 | 16072 | switch (DEFAULT_ABI) |
3daf36a4 | 16073 | { |
38c1f2d7 | 16074 | default: |
37409796 | 16075 | gcc_unreachable (); |
38c1f2d7 MM |
16076 | |
16077 | case ABI_V4: | |
09eeeacb AM |
16078 | if (!TARGET_32BIT) |
16079 | { | |
d4ee4d25 | 16080 | warning (0, "no profiling of 64-bit code for this ABI"); |
09eeeacb AM |
16081 | return; |
16082 | } | |
ffcfcb5f | 16083 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 16084 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
71625f3d AM |
16085 | if (NO_PROFILE_COUNTERS) |
16086 | { | |
16087 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
16088 | reg_names[0], reg_names[1]); | |
16089 | } | |
16090 | else if (TARGET_SECURE_PLT && flag_pic) | |
16091 | { | |
16092 | asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n", | |
16093 | reg_names[0], reg_names[1]); | |
16094 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); | |
16095 | asm_fprintf (file, "\t{cau|addis} %s,%s,", | |
16096 | reg_names[12], reg_names[12]); | |
16097 | assemble_name (file, buf); | |
16098 | asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]); | |
16099 | assemble_name (file, buf); | |
16100 | asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]); | |
16101 | } | |
16102 | else if (flag_pic == 1) | |
38c1f2d7 | 16103 | { |
dfdfa60f | 16104 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
71625f3d AM |
16105 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
16106 | reg_names[0], reg_names[1]); | |
17167fd8 | 16107 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 16108 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 16109 | assemble_name (file, buf); |
17167fd8 | 16110 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 16111 | } |
9ebbca7d | 16112 | else if (flag_pic > 1) |
38c1f2d7 | 16113 | { |
71625f3d AM |
16114 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
16115 | reg_names[0], reg_names[1]); | |
9ebbca7d | 16116 | /* Now, we need to get the address of the label. */ |
71625f3d | 16117 | fputs ("\tbcl 20,31,1f\n\t.long ", file); |
034e84c4 | 16118 | assemble_name (file, buf); |
9ebbca7d GK |
16119 | fputs ("-.\n1:", file); |
16120 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
f676971a | 16121 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", |
9ebbca7d GK |
16122 | reg_names[0], reg_names[11]); |
16123 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
16124 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 16125 | } |
38c1f2d7 MM |
16126 | else |
16127 | { | |
17167fd8 | 16128 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 16129 | assemble_name (file, buf); |
dfdfa60f | 16130 | fputs ("@ha\n", file); |
71625f3d AM |
16131 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
16132 | reg_names[0], reg_names[1]); | |
a260abc9 | 16133 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 16134 | assemble_name (file, buf); |
17167fd8 | 16135 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
16136 | } |
16137 | ||
50d440bc | 16138 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
3b6ce0af DE |
16139 | fprintf (file, "\tbl %s%s\n", |
16140 | RS6000_MCOUNT, flag_pic ? "@plt" : ""); | |
38c1f2d7 MM |
16141 | break; |
16142 | ||
16143 | case ABI_AIX: | |
ee890fe2 | 16144 | case ABI_DARWIN: |
ffcfcb5f AM |
16145 | if (!TARGET_PROFILE_KERNEL) |
16146 | { | |
a3c9585f | 16147 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
16148 | } |
16149 | else | |
16150 | { | |
37409796 | 16151 | gcc_assert (!TARGET_32BIT); |
ffcfcb5f AM |
16152 | |
16153 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
16154 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
16155 | ||
6de9cd9a | 16156 | if (cfun->static_chain_decl != NULL) |
ffcfcb5f AM |
16157 | { |
16158 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
16159 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
16160 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
16161 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
16162 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
16163 | } | |
16164 | else | |
16165 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
16166 | } | |
38c1f2d7 MM |
16167 | break; |
16168 | } | |
e165f3f0 | 16169 | } |
a251ffd0 | 16170 | |
b54cf83a | 16171 | \f |
b54cf83a DE |
16172 | /* Power4 load update and store update instructions are cracked into a |
16173 | load or store and an integer insn which are executed in the same cycle. | |
16174 | Branches have their own dispatch slot which does not count against the | |
16175 | GCC issue rate, but it changes the program flow so there are no other | |
16176 | instructions to issue in this cycle. */ | |
16177 | ||
16178 | static int | |
f676971a EC |
16179 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
16180 | int verbose ATTRIBUTE_UNUSED, | |
a2369ed3 | 16181 | rtx insn, int more) |
b54cf83a DE |
16182 | { |
16183 | if (GET_CODE (PATTERN (insn)) == USE | |
16184 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16185 | return more; | |
16186 | ||
ec507f2d | 16187 | if (rs6000_sched_groups) |
b54cf83a | 16188 | { |
cbe26ab8 | 16189 | if (is_microcoded_insn (insn)) |
c4ad648e | 16190 | return 0; |
cbe26ab8 | 16191 | else if (is_cracked_insn (insn)) |
c4ad648e | 16192 | return more > 2 ? more - 2 : 0; |
b54cf83a | 16193 | } |
165b263e DE |
16194 | |
16195 | return more - 1; | |
b54cf83a DE |
16196 | } |
16197 | ||
a251ffd0 TG |
16198 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
16199 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
16200 | ||
c237e94a | 16201 | static int |
0a4f0294 | 16202 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
a251ffd0 TG |
16203 | { |
16204 | if (! recog_memoized (insn)) | |
16205 | return 0; | |
16206 | ||
16207 | if (REG_NOTE_KIND (link) != 0) | |
16208 | return 0; | |
16209 | ||
16210 | if (REG_NOTE_KIND (link) == 0) | |
16211 | { | |
ed947a96 DJ |
16212 | /* Data dependency; DEP_INSN writes a register that INSN reads |
16213 | some cycles later. */ | |
c9dbf840 DE |
16214 | |
16215 | /* Separate a load from a narrower, dependent store. */ | |
16216 | if (rs6000_sched_groups | |
16217 | && GET_CODE (PATTERN (insn)) == SET | |
16218 | && GET_CODE (PATTERN (dep_insn)) == SET | |
16219 | && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM | |
16220 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM | |
16221 | && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1))) | |
16222 | > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0))))) | |
16223 | return cost + 14; | |
16224 | ||
ed947a96 DJ |
16225 | switch (get_attr_type (insn)) |
16226 | { | |
16227 | case TYPE_JMPREG: | |
309323c2 | 16228 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
16229 | a mtctr and bctr (and mtlr and br/blr). The first |
16230 | scheduling pass will not know about this latency since | |
16231 | the mtctr instruction, which has the latency associated | |
16232 | to it, will be generated by reload. */ | |
309323c2 | 16233 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
16234 | case TYPE_BRANCH: |
16235 | /* Leave some extra cycles between a compare and its | |
16236 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
16237 | if ((rs6000_cpu_attr == CPU_PPC603 |
16238 | || rs6000_cpu_attr == CPU_PPC604 | |
16239 | || rs6000_cpu_attr == CPU_PPC604E | |
16240 | || rs6000_cpu_attr == CPU_PPC620 | |
16241 | || rs6000_cpu_attr == CPU_PPC630 | |
16242 | || rs6000_cpu_attr == CPU_PPC750 | |
16243 | || rs6000_cpu_attr == CPU_PPC7400 | |
16244 | || rs6000_cpu_attr == CPU_PPC7450 | |
ec507f2d DE |
16245 | || rs6000_cpu_attr == CPU_POWER4 |
16246 | || rs6000_cpu_attr == CPU_POWER5) | |
ed947a96 DJ |
16247 | && recog_memoized (dep_insn) |
16248 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
16249 | && (get_attr_type (dep_insn) == TYPE_CMP |
16250 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 16251 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
16252 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
16253 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 16254 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
16255 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
16256 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
16257 | return cost + 2; |
16258 | default: | |
16259 | break; | |
16260 | } | |
a251ffd0 TG |
16261 | /* Fall out to return default cost. */ |
16262 | } | |
16263 | ||
16264 | return cost; | |
16265 | } | |
b6c9286a | 16266 | |
cbe26ab8 | 16267 | /* The function returns a true if INSN is microcoded. |
839a4992 | 16268 | Return false otherwise. */ |
cbe26ab8 DN |
16269 | |
16270 | static bool | |
16271 | is_microcoded_insn (rtx insn) | |
16272 | { | |
16273 | if (!insn || !INSN_P (insn) | |
16274 | || GET_CODE (PATTERN (insn)) == USE | |
16275 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16276 | return false; | |
16277 | ||
ec507f2d | 16278 | if (rs6000_sched_groups) |
cbe26ab8 DN |
16279 | { |
16280 | enum attr_type type = get_attr_type (insn); | |
16281 | if (type == TYPE_LOAD_EXT_U | |
16282 | || type == TYPE_LOAD_EXT_UX | |
16283 | || type == TYPE_LOAD_UX | |
16284 | || type == TYPE_STORE_UX | |
16285 | || type == TYPE_MFCR) | |
c4ad648e | 16286 | return true; |
cbe26ab8 DN |
16287 | } |
16288 | ||
16289 | return false; | |
16290 | } | |
16291 | ||
5c425df5 | 16292 | /* The function returns a nonzero value if INSN can be scheduled only |
cbe26ab8 DN |
16293 | as the first insn in a dispatch group ("dispatch-slot restricted"). |
16294 | In this case, the returned value indicates how many dispatch slots | |
16295 | the insn occupies (at the beginning of the group). | |
79ae11c4 DN |
16296 | Return 0 otherwise. */ |
16297 | ||
cbe26ab8 | 16298 | static int |
79ae11c4 DN |
16299 | is_dispatch_slot_restricted (rtx insn) |
16300 | { | |
16301 | enum attr_type type; | |
16302 | ||
ec507f2d | 16303 | if (!rs6000_sched_groups) |
79ae11c4 DN |
16304 | return 0; |
16305 | ||
16306 | if (!insn | |
16307 | || insn == NULL_RTX | |
16308 | || GET_CODE (insn) == NOTE | |
16309 | || GET_CODE (PATTERN (insn)) == USE | |
16310 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16311 | return 0; | |
16312 | ||
16313 | type = get_attr_type (insn); | |
16314 | ||
ec507f2d DE |
16315 | switch (type) |
16316 | { | |
16317 | case TYPE_MFCR: | |
16318 | case TYPE_MFCRF: | |
16319 | case TYPE_MTCR: | |
16320 | case TYPE_DELAYED_CR: | |
16321 | case TYPE_CR_LOGICAL: | |
16322 | case TYPE_MTJMPR: | |
16323 | case TYPE_MFJMPR: | |
16324 | return 1; | |
16325 | case TYPE_IDIV: | |
16326 | case TYPE_LDIV: | |
16327 | return 2; | |
b52110d4 DE |
16328 | case TYPE_LOAD_L: |
16329 | case TYPE_STORE_C: | |
16330 | case TYPE_ISYNC: | |
16331 | case TYPE_SYNC: | |
16332 | return 4; | |
ec507f2d DE |
16333 | default: |
16334 | if (rs6000_cpu == PROCESSOR_POWER5 | |
16335 | && is_cracked_insn (insn)) | |
16336 | return 2; | |
16337 | return 0; | |
16338 | } | |
79ae11c4 DN |
16339 | } |
16340 | ||
cbe26ab8 DN |
16341 | /* The function returns true if INSN is cracked into 2 instructions |
16342 | by the processor (and therefore occupies 2 issue slots). */ | |
16343 | ||
16344 | static bool | |
16345 | is_cracked_insn (rtx insn) | |
16346 | { | |
16347 | if (!insn || !INSN_P (insn) | |
16348 | || GET_CODE (PATTERN (insn)) == USE | |
16349 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16350 | return false; | |
16351 | ||
ec507f2d | 16352 | if (rs6000_sched_groups) |
cbe26ab8 DN |
16353 | { |
16354 | enum attr_type type = get_attr_type (insn); | |
16355 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
c4ad648e AM |
16356 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U |
16357 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
16358 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
16359 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
16360 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
16361 | || type == TYPE_IDIV || type == TYPE_LDIV | |
16362 | || type == TYPE_INSERT_WORD) | |
16363 | return true; | |
cbe26ab8 DN |
16364 | } |
16365 | ||
16366 | return false; | |
16367 | } | |
16368 | ||
16369 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 16370 | the branch slot. */ |
cbe26ab8 DN |
16371 | |
16372 | static bool | |
16373 | is_branch_slot_insn (rtx insn) | |
16374 | { | |
16375 | if (!insn || !INSN_P (insn) | |
16376 | || GET_CODE (PATTERN (insn)) == USE | |
16377 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16378 | return false; | |
16379 | ||
ec507f2d | 16380 | if (rs6000_sched_groups) |
cbe26ab8 DN |
16381 | { |
16382 | enum attr_type type = get_attr_type (insn); | |
16383 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
f676971a | 16384 | return true; |
cbe26ab8 DN |
16385 | return false; |
16386 | } | |
16387 | ||
16388 | return false; | |
16389 | } | |
79ae11c4 | 16390 | |
a4f6c312 | 16391 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
16392 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
16393 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
16394 | define this macro if you do not need to adjust the scheduling |
16395 | priorities of insns. */ | |
bef84347 | 16396 | |
c237e94a | 16397 | static int |
a2369ed3 | 16398 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 16399 | { |
a4f6c312 SS |
16400 | /* On machines (like the 750) which have asymmetric integer units, |
16401 | where one integer unit can do multiply and divides and the other | |
16402 | can't, reduce the priority of multiply/divide so it is scheduled | |
16403 | before other integer operations. */ | |
bef84347 VM |
16404 | |
16405 | #if 0 | |
2c3c49de | 16406 | if (! INSN_P (insn)) |
bef84347 VM |
16407 | return priority; |
16408 | ||
16409 | if (GET_CODE (PATTERN (insn)) == USE) | |
16410 | return priority; | |
16411 | ||
16412 | switch (rs6000_cpu_attr) { | |
16413 | case CPU_PPC750: | |
16414 | switch (get_attr_type (insn)) | |
16415 | { | |
16416 | default: | |
16417 | break; | |
16418 | ||
16419 | case TYPE_IMUL: | |
16420 | case TYPE_IDIV: | |
3cb999d8 DE |
16421 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
16422 | priority, priority); | |
bef84347 VM |
16423 | if (priority >= 0 && priority < 0x01000000) |
16424 | priority >>= 3; | |
16425 | break; | |
16426 | } | |
16427 | } | |
16428 | #endif | |
16429 | ||
79ae11c4 DN |
16430 | if (is_dispatch_slot_restricted (insn) |
16431 | && reload_completed | |
f676971a | 16432 | && current_sched_info->sched_max_insns_priority |
79ae11c4 DN |
16433 | && rs6000_sched_restricted_insns_priority) |
16434 | { | |
16435 | ||
c4ad648e AM |
16436 | /* Prioritize insns that can be dispatched only in the first |
16437 | dispatch slot. */ | |
79ae11c4 | 16438 | if (rs6000_sched_restricted_insns_priority == 1) |
f676971a EC |
16439 | /* Attach highest priority to insn. This means that in |
16440 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
79ae11c4 | 16441 | precede 'priority' (critical path) considerations. */ |
f676971a | 16442 | return current_sched_info->sched_max_insns_priority; |
79ae11c4 | 16443 | else if (rs6000_sched_restricted_insns_priority == 2) |
f676971a | 16444 | /* Increase priority of insn by a minimal amount. This means that in |
c4ad648e AM |
16445 | haifa-sched.c:ready_sort(), only 'priority' (critical path) |
16446 | considerations precede dispatch-slot restriction considerations. */ | |
f676971a EC |
16447 | return (priority + 1); |
16448 | } | |
79ae11c4 | 16449 | |
bef84347 VM |
16450 | return priority; |
16451 | } | |
16452 | ||
a4f6c312 SS |
16453 | /* Return how many instructions the machine can issue per cycle. */ |
16454 | ||
c237e94a | 16455 | static int |
863d938c | 16456 | rs6000_issue_rate (void) |
b6c9286a | 16457 | { |
3317bab1 DE |
16458 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
16459 | if (!reload_completed) | |
16460 | return 1; | |
16461 | ||
b6c9286a | 16462 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
16463 | case CPU_RIOS1: /* ? */ |
16464 | case CPU_RS64A: | |
16465 | case CPU_PPC601: /* ? */ | |
ed947a96 | 16466 | case CPU_PPC7450: |
3cb999d8 | 16467 | return 3; |
b54cf83a | 16468 | case CPU_PPC440: |
b6c9286a | 16469 | case CPU_PPC603: |
bef84347 | 16470 | case CPU_PPC750: |
ed947a96 | 16471 | case CPU_PPC7400: |
be12c2b0 | 16472 | case CPU_PPC8540: |
f676971a | 16473 | return 2; |
3cb999d8 | 16474 | case CPU_RIOS2: |
b6c9286a | 16475 | case CPU_PPC604: |
19684119 | 16476 | case CPU_PPC604E: |
b6c9286a | 16477 | case CPU_PPC620: |
3cb999d8 | 16478 | case CPU_PPC630: |
b6c9286a | 16479 | return 4; |
cbe26ab8 | 16480 | case CPU_POWER4: |
ec507f2d | 16481 | case CPU_POWER5: |
cbe26ab8 | 16482 | return 5; |
b6c9286a MM |
16483 | default: |
16484 | return 1; | |
16485 | } | |
16486 | } | |
16487 | ||
be12c2b0 VM |
16488 | /* Return how many instructions to look ahead for better insn |
16489 | scheduling. */ | |
16490 | ||
16491 | static int | |
863d938c | 16492 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
16493 | { |
16494 | if (rs6000_cpu_attr == CPU_PPC8540) | |
16495 | return 4; | |
16496 | return 0; | |
16497 | } | |
16498 | ||
569fa502 DN |
16499 | /* Determine is PAT refers to memory. */ |
16500 | ||
16501 | static bool | |
16502 | is_mem_ref (rtx pat) | |
16503 | { | |
16504 | const char * fmt; | |
16505 | int i, j; | |
16506 | bool ret = false; | |
16507 | ||
16508 | if (GET_CODE (pat) == MEM) | |
16509 | return true; | |
16510 | ||
16511 | /* Recursively process the pattern. */ | |
16512 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
16513 | ||
16514 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
16515 | { | |
16516 | if (fmt[i] == 'e') | |
16517 | ret |= is_mem_ref (XEXP (pat, i)); | |
16518 | else if (fmt[i] == 'E') | |
16519 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
16520 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
16521 | } | |
16522 | ||
16523 | return ret; | |
16524 | } | |
16525 | ||
16526 | /* Determine if PAT is a PATTERN of a load insn. */ | |
f676971a | 16527 | |
569fa502 DN |
16528 | static bool |
16529 | is_load_insn1 (rtx pat) | |
16530 | { | |
16531 | if (!pat || pat == NULL_RTX) | |
16532 | return false; | |
16533 | ||
16534 | if (GET_CODE (pat) == SET) | |
16535 | return is_mem_ref (SET_SRC (pat)); | |
16536 | ||
16537 | if (GET_CODE (pat) == PARALLEL) | |
16538 | { | |
16539 | int i; | |
16540 | ||
16541 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
16542 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
16543 | return true; | |
16544 | } | |
16545 | ||
16546 | return false; | |
16547 | } | |
16548 | ||
16549 | /* Determine if INSN loads from memory. */ | |
16550 | ||
16551 | static bool | |
16552 | is_load_insn (rtx insn) | |
16553 | { | |
16554 | if (!insn || !INSN_P (insn)) | |
16555 | return false; | |
16556 | ||
16557 | if (GET_CODE (insn) == CALL_INSN) | |
16558 | return false; | |
16559 | ||
16560 | return is_load_insn1 (PATTERN (insn)); | |
16561 | } | |
16562 | ||
16563 | /* Determine if PAT is a PATTERN of a store insn. */ | |
16564 | ||
16565 | static bool | |
16566 | is_store_insn1 (rtx pat) | |
16567 | { | |
16568 | if (!pat || pat == NULL_RTX) | |
16569 | return false; | |
16570 | ||
16571 | if (GET_CODE (pat) == SET) | |
16572 | return is_mem_ref (SET_DEST (pat)); | |
16573 | ||
16574 | if (GET_CODE (pat) == PARALLEL) | |
16575 | { | |
16576 | int i; | |
16577 | ||
16578 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
16579 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
16580 | return true; | |
16581 | } | |
16582 | ||
16583 | return false; | |
16584 | } | |
16585 | ||
16586 | /* Determine if INSN stores to memory. */ | |
16587 | ||
16588 | static bool | |
16589 | is_store_insn (rtx insn) | |
16590 | { | |
16591 | if (!insn || !INSN_P (insn)) | |
16592 | return false; | |
16593 | ||
16594 | return is_store_insn1 (PATTERN (insn)); | |
16595 | } | |
16596 | ||
16597 | /* Returns whether the dependence between INSN and NEXT is considered | |
16598 | costly by the given target. */ | |
16599 | ||
16600 | static bool | |
c4ad648e AM |
16601 | rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, |
16602 | int distance) | |
f676971a | 16603 | { |
aabcd309 | 16604 | /* If the flag is not enabled - no dependence is considered costly; |
f676971a | 16605 | allow all dependent insns in the same group. |
569fa502 DN |
16606 | This is the most aggressive option. */ |
16607 | if (rs6000_sched_costly_dep == no_dep_costly) | |
16608 | return false; | |
16609 | ||
f676971a | 16610 | /* If the flag is set to 1 - a dependence is always considered costly; |
569fa502 DN |
16611 | do not allow dependent instructions in the same group. |
16612 | This is the most conservative option. */ | |
16613 | if (rs6000_sched_costly_dep == all_deps_costly) | |
f676971a | 16614 | return true; |
569fa502 | 16615 | |
f676971a EC |
16616 | if (rs6000_sched_costly_dep == store_to_load_dep_costly |
16617 | && is_load_insn (next) | |
569fa502 DN |
16618 | && is_store_insn (insn)) |
16619 | /* Prevent load after store in the same group. */ | |
16620 | return true; | |
16621 | ||
16622 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
f676971a | 16623 | && is_load_insn (next) |
569fa502 DN |
16624 | && is_store_insn (insn) |
16625 | && (!link || (int) REG_NOTE_KIND (link) == 0)) | |
c4ad648e AM |
16626 | /* Prevent load after store in the same group if it is a true |
16627 | dependence. */ | |
569fa502 | 16628 | return true; |
f676971a EC |
16629 | |
16630 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
569fa502 DN |
16631 | and will not be scheduled in the same group. */ |
16632 | if (rs6000_sched_costly_dep <= max_dep_latency | |
16633 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
16634 | return true; | |
16635 | ||
16636 | return false; | |
16637 | } | |
16638 | ||
f676971a | 16639 | /* Return the next insn after INSN that is found before TAIL is reached, |
cbe26ab8 DN |
16640 | skipping any "non-active" insns - insns that will not actually occupy |
16641 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
16642 | ||
16643 | static rtx | |
16644 | get_next_active_insn (rtx insn, rtx tail) | |
16645 | { | |
f489aff8 | 16646 | if (insn == NULL_RTX || insn == tail) |
cbe26ab8 DN |
16647 | return NULL_RTX; |
16648 | ||
f489aff8 | 16649 | while (1) |
cbe26ab8 | 16650 | { |
f489aff8 AM |
16651 | insn = NEXT_INSN (insn); |
16652 | if (insn == NULL_RTX || insn == tail) | |
16653 | return NULL_RTX; | |
cbe26ab8 | 16654 | |
f489aff8 AM |
16655 | if (CALL_P (insn) |
16656 | || JUMP_P (insn) | |
16657 | || (NONJUMP_INSN_P (insn) | |
16658 | && GET_CODE (PATTERN (insn)) != USE | |
16659 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
309ebcd0 | 16660 | && INSN_CODE (insn) != CODE_FOR_stack_tie)) |
f489aff8 AM |
16661 | break; |
16662 | } | |
16663 | return insn; | |
cbe26ab8 DN |
16664 | } |
16665 | ||
839a4992 | 16666 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
16667 | of group WHICH_GROUP. |
16668 | ||
16669 | If WHICH_GROUP == current_group, this function will return true if INSN | |
16670 | causes the termination of the current group (i.e, the dispatch group to | |
16671 | which INSN belongs). This means that INSN will be the last insn in the | |
16672 | group it belongs to. | |
16673 | ||
16674 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
16675 | causes the termination of the previous group (i.e, the dispatch group that | |
16676 | precedes the group to which INSN belongs). This means that INSN will be | |
16677 | the first insn in the group it belongs to). */ | |
16678 | ||
16679 | static bool | |
16680 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
16681 | { | |
16682 | enum attr_type type; | |
16683 | ||
16684 | if (! insn) | |
16685 | return false; | |
569fa502 | 16686 | |
cbe26ab8 DN |
16687 | type = get_attr_type (insn); |
16688 | ||
16689 | if (is_microcoded_insn (insn)) | |
16690 | return true; | |
16691 | ||
16692 | if (which_group == current_group) | |
16693 | { | |
16694 | if (is_branch_slot_insn (insn)) | |
c4ad648e | 16695 | return true; |
cbe26ab8 DN |
16696 | return false; |
16697 | } | |
16698 | else if (which_group == previous_group) | |
16699 | { | |
16700 | if (is_dispatch_slot_restricted (insn)) | |
c4ad648e | 16701 | return true; |
cbe26ab8 DN |
16702 | return false; |
16703 | } | |
16704 | ||
16705 | return false; | |
16706 | } | |
16707 | ||
839a4992 | 16708 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
16709 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
16710 | ||
16711 | static bool | |
16712 | is_costly_group (rtx *group_insns, rtx next_insn) | |
16713 | { | |
16714 | int i; | |
16715 | rtx link; | |
16716 | int cost; | |
16717 | int issue_rate = rs6000_issue_rate (); | |
16718 | ||
16719 | for (i = 0; i < issue_rate; i++) | |
16720 | { | |
16721 | rtx insn = group_insns[i]; | |
16722 | if (!insn) | |
c4ad648e | 16723 | continue; |
cbe26ab8 | 16724 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) |
c4ad648e AM |
16725 | { |
16726 | rtx next = XEXP (link, 0); | |
16727 | if (next == next_insn) | |
16728 | { | |
16729 | cost = insn_cost (insn, link, next_insn); | |
16730 | if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) | |
16731 | return true; | |
16732 | } | |
16733 | } | |
cbe26ab8 DN |
16734 | } |
16735 | ||
16736 | return false; | |
16737 | } | |
16738 | ||
f676971a | 16739 | /* Utility of the function redefine_groups. |
cbe26ab8 DN |
16740 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS |
16741 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
16742 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
16743 | one of the following schemes, depending on the value of the flag | |
16744 | -minsert_sched_nops = X: | |
16745 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 16746 | in order to force NEXT_INSN into a separate group. |
f676971a EC |
16747 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
16748 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
cbe26ab8 DN |
16749 | insertion (has a group just ended, how many vacant issue slots remain in the |
16750 | last group, and how many dispatch groups were encountered so far). */ | |
16751 | ||
f676971a | 16752 | static int |
c4ad648e AM |
16753 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, |
16754 | rtx next_insn, bool *group_end, int can_issue_more, | |
16755 | int *group_count) | |
cbe26ab8 DN |
16756 | { |
16757 | rtx nop; | |
16758 | bool force; | |
16759 | int issue_rate = rs6000_issue_rate (); | |
16760 | bool end = *group_end; | |
16761 | int i; | |
16762 | ||
16763 | if (next_insn == NULL_RTX) | |
16764 | return can_issue_more; | |
16765 | ||
16766 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
16767 | return can_issue_more; | |
16768 | ||
16769 | force = is_costly_group (group_insns, next_insn); | |
16770 | if (!force) | |
16771 | return can_issue_more; | |
16772 | ||
16773 | if (sched_verbose > 6) | |
16774 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
c4ad648e | 16775 | *group_count ,can_issue_more); |
cbe26ab8 DN |
16776 | |
16777 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
16778 | { | |
16779 | if (*group_end) | |
c4ad648e | 16780 | can_issue_more = 0; |
cbe26ab8 DN |
16781 | |
16782 | /* Since only a branch can be issued in the last issue_slot, it is | |
16783 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
16784 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
c4ad648e AM |
16785 | in this case the last nop will start a new group and the branch |
16786 | will be forced to the new group. */ | |
cbe26ab8 | 16787 | if (can_issue_more && !is_branch_slot_insn (next_insn)) |
c4ad648e | 16788 | can_issue_more--; |
cbe26ab8 DN |
16789 | |
16790 | while (can_issue_more > 0) | |
c4ad648e | 16791 | { |
9390387d | 16792 | nop = gen_nop (); |
c4ad648e AM |
16793 | emit_insn_before (nop, next_insn); |
16794 | can_issue_more--; | |
16795 | } | |
cbe26ab8 DN |
16796 | |
16797 | *group_end = true; | |
16798 | return 0; | |
f676971a | 16799 | } |
cbe26ab8 DN |
16800 | |
16801 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
16802 | { | |
16803 | int n_nops = rs6000_sched_insert_nops; | |
16804 | ||
f676971a | 16805 | /* Nops can't be issued from the branch slot, so the effective |
c4ad648e | 16806 | issue_rate for nops is 'issue_rate - 1'. */ |
cbe26ab8 | 16807 | if (can_issue_more == 0) |
c4ad648e | 16808 | can_issue_more = issue_rate; |
cbe26ab8 DN |
16809 | can_issue_more--; |
16810 | if (can_issue_more == 0) | |
c4ad648e AM |
16811 | { |
16812 | can_issue_more = issue_rate - 1; | |
16813 | (*group_count)++; | |
16814 | end = true; | |
16815 | for (i = 0; i < issue_rate; i++) | |
16816 | { | |
16817 | group_insns[i] = 0; | |
16818 | } | |
16819 | } | |
cbe26ab8 DN |
16820 | |
16821 | while (n_nops > 0) | |
c4ad648e AM |
16822 | { |
16823 | nop = gen_nop (); | |
16824 | emit_insn_before (nop, next_insn); | |
16825 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
16826 | end = false; | |
16827 | can_issue_more--; | |
16828 | if (can_issue_more == 0) | |
16829 | { | |
16830 | can_issue_more = issue_rate - 1; | |
16831 | (*group_count)++; | |
16832 | end = true; | |
16833 | for (i = 0; i < issue_rate; i++) | |
16834 | { | |
16835 | group_insns[i] = 0; | |
16836 | } | |
16837 | } | |
16838 | n_nops--; | |
16839 | } | |
cbe26ab8 DN |
16840 | |
16841 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
f676971a | 16842 | can_issue_more++; |
cbe26ab8 | 16843 | |
c4ad648e AM |
16844 | /* Is next_insn going to start a new group? */ |
16845 | *group_end | |
16846 | = (end | |
cbe26ab8 DN |
16847 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) |
16848 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
16849 | || (can_issue_more < issue_rate && | |
c4ad648e | 16850 | insn_terminates_group_p (next_insn, previous_group))); |
cbe26ab8 | 16851 | if (*group_end && end) |
c4ad648e | 16852 | (*group_count)--; |
cbe26ab8 DN |
16853 | |
16854 | if (sched_verbose > 6) | |
c4ad648e AM |
16855 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", |
16856 | *group_count, can_issue_more); | |
f676971a EC |
16857 | return can_issue_more; |
16858 | } | |
cbe26ab8 DN |
16859 | |
16860 | return can_issue_more; | |
16861 | } | |
16862 | ||
16863 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
f676971a | 16864 | with the dispatch groups that the processor dispatcher is expected to |
cbe26ab8 DN |
16865 | form in practice. It tries to achieve this synchronization by forcing the |
16866 | estimated processor grouping on the compiler (as opposed to the function | |
16867 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
16868 | ||
16869 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
16870 | examines the (estimated) dispatch groups that will be formed by the processor | |
16871 | dispatcher. It marks these group boundaries to reflect the estimated | |
16872 | processor grouping, overriding the grouping that the scheduler had marked. | |
16873 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
16874 | force certain insns into separate groups or force a certain distance between | |
16875 | them by inserting nops, for example, if there exists a "costly dependence" | |
16876 | between the insns. | |
16877 | ||
16878 | The function estimates the group boundaries that the processor will form as | |
0fa2e4df | 16879 | follows: It keeps track of how many vacant issue slots are available after |
cbe26ab8 DN |
16880 | each insn. A subsequent insn will start a new group if one of the following |
16881 | 4 cases applies: | |
16882 | - no more vacant issue slots remain in the current dispatch group. | |
16883 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
16884 | insn is not a branch. | |
16885 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
16886 | which means that a cracked insn (which occupies two issue slots) can't be | |
16887 | issued in this group. | |
f676971a | 16888 | - less than 'issue_rate' slots are vacant, and the next insn always needs to |
cbe26ab8 DN |
16889 | start a new group. */ |
16890 | ||
16891 | static int | |
16892 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
16893 | { | |
16894 | rtx insn, next_insn; | |
16895 | int issue_rate; | |
16896 | int can_issue_more; | |
16897 | int slot, i; | |
16898 | bool group_end; | |
16899 | int group_count = 0; | |
16900 | rtx *group_insns; | |
16901 | ||
16902 | /* Initialize. */ | |
16903 | issue_rate = rs6000_issue_rate (); | |
16904 | group_insns = alloca (issue_rate * sizeof (rtx)); | |
f676971a | 16905 | for (i = 0; i < issue_rate; i++) |
cbe26ab8 DN |
16906 | { |
16907 | group_insns[i] = 0; | |
16908 | } | |
16909 | can_issue_more = issue_rate; | |
16910 | slot = 0; | |
16911 | insn = get_next_active_insn (prev_head_insn, tail); | |
16912 | group_end = false; | |
16913 | ||
16914 | while (insn != NULL_RTX) | |
16915 | { | |
16916 | slot = (issue_rate - can_issue_more); | |
16917 | group_insns[slot] = insn; | |
16918 | can_issue_more = | |
c4ad648e | 16919 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); |
cbe26ab8 | 16920 | if (insn_terminates_group_p (insn, current_group)) |
c4ad648e | 16921 | can_issue_more = 0; |
cbe26ab8 DN |
16922 | |
16923 | next_insn = get_next_active_insn (insn, tail); | |
16924 | if (next_insn == NULL_RTX) | |
c4ad648e | 16925 | return group_count + 1; |
cbe26ab8 | 16926 | |
c4ad648e AM |
16927 | /* Is next_insn going to start a new group? */ |
16928 | group_end | |
16929 | = (can_issue_more == 0 | |
16930 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
16931 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
16932 | || (can_issue_more < issue_rate && | |
16933 | insn_terminates_group_p (next_insn, previous_group))); | |
cbe26ab8 | 16934 | |
f676971a | 16935 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, |
c4ad648e AM |
16936 | next_insn, &group_end, can_issue_more, |
16937 | &group_count); | |
cbe26ab8 DN |
16938 | |
16939 | if (group_end) | |
c4ad648e AM |
16940 | { |
16941 | group_count++; | |
16942 | can_issue_more = 0; | |
16943 | for (i = 0; i < issue_rate; i++) | |
16944 | { | |
16945 | group_insns[i] = 0; | |
16946 | } | |
16947 | } | |
cbe26ab8 DN |
16948 | |
16949 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
9390387d | 16950 | PUT_MODE (next_insn, VOIDmode); |
cbe26ab8 | 16951 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) |
c4ad648e | 16952 | PUT_MODE (next_insn, TImode); |
cbe26ab8 DN |
16953 | |
16954 | insn = next_insn; | |
16955 | if (can_issue_more == 0) | |
c4ad648e AM |
16956 | can_issue_more = issue_rate; |
16957 | } /* while */ | |
cbe26ab8 DN |
16958 | |
16959 | return group_count; | |
16960 | } | |
16961 | ||
16962 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
16963 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
16964 | any dispatch groups which have vacant issue slots, in order to force the | |
16965 | scheduler's grouping on the processor dispatcher. The function | |
16966 | returns the number of dispatch groups found. */ | |
16967 | ||
16968 | static int | |
16969 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
16970 | { | |
16971 | rtx insn, next_insn; | |
16972 | rtx nop; | |
16973 | int issue_rate; | |
16974 | int can_issue_more; | |
16975 | int group_end; | |
16976 | int group_count = 0; | |
16977 | ||
16978 | /* Initialize issue_rate. */ | |
16979 | issue_rate = rs6000_issue_rate (); | |
16980 | can_issue_more = issue_rate; | |
16981 | ||
16982 | insn = get_next_active_insn (prev_head_insn, tail); | |
16983 | next_insn = get_next_active_insn (insn, tail); | |
16984 | ||
16985 | while (insn != NULL_RTX) | |
16986 | { | |
16987 | can_issue_more = | |
16988 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
16989 | ||
16990 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
16991 | ||
16992 | if (next_insn == NULL_RTX) | |
c4ad648e | 16993 | break; |
cbe26ab8 DN |
16994 | |
16995 | if (group_end) | |
c4ad648e AM |
16996 | { |
16997 | /* If the scheduler had marked group termination at this location | |
16998 | (between insn and next_indn), and neither insn nor next_insn will | |
16999 | force group termination, pad the group with nops to force group | |
17000 | termination. */ | |
17001 | if (can_issue_more | |
17002 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
17003 | && !insn_terminates_group_p (insn, current_group) | |
17004 | && !insn_terminates_group_p (next_insn, previous_group)) | |
17005 | { | |
9390387d | 17006 | if (!is_branch_slot_insn (next_insn)) |
c4ad648e AM |
17007 | can_issue_more--; |
17008 | ||
17009 | while (can_issue_more) | |
17010 | { | |
17011 | nop = gen_nop (); | |
17012 | emit_insn_before (nop, next_insn); | |
17013 | can_issue_more--; | |
17014 | } | |
17015 | } | |
17016 | ||
17017 | can_issue_more = issue_rate; | |
17018 | group_count++; | |
17019 | } | |
cbe26ab8 DN |
17020 | |
17021 | insn = next_insn; | |
17022 | next_insn = get_next_active_insn (insn, tail); | |
17023 | } | |
17024 | ||
17025 | return group_count; | |
17026 | } | |
17027 | ||
17028 | /* The following function is called at the end of scheduling BB. | |
17029 | After reload, it inserts nops at insn group bundling. */ | |
17030 | ||
17031 | static void | |
38f391a5 | 17032 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
17033 | { |
17034 | int n_groups; | |
17035 | ||
17036 | if (sched_verbose) | |
17037 | fprintf (dump, "=== Finishing schedule.\n"); | |
17038 | ||
ec507f2d | 17039 | if (reload_completed && rs6000_sched_groups) |
cbe26ab8 DN |
17040 | { |
17041 | if (rs6000_sched_insert_nops == sched_finish_none) | |
c4ad648e | 17042 | return; |
cbe26ab8 DN |
17043 | |
17044 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
c4ad648e AM |
17045 | n_groups = pad_groups (dump, sched_verbose, |
17046 | current_sched_info->prev_head, | |
17047 | current_sched_info->next_tail); | |
cbe26ab8 | 17048 | else |
c4ad648e AM |
17049 | n_groups = redefine_groups (dump, sched_verbose, |
17050 | current_sched_info->prev_head, | |
17051 | current_sched_info->next_tail); | |
cbe26ab8 DN |
17052 | |
17053 | if (sched_verbose >= 6) | |
17054 | { | |
17055 | fprintf (dump, "ngroups = %d\n", n_groups); | |
17056 | print_rtl (dump, current_sched_info->prev_head); | |
17057 | fprintf (dump, "Done finish_sched\n"); | |
17058 | } | |
17059 | } | |
17060 | } | |
b6c9286a | 17061 | \f |
b6c9286a MM |
17062 | /* Length in units of the trampoline for entering a nested function. */ |
17063 | ||
17064 | int | |
863d938c | 17065 | rs6000_trampoline_size (void) |
b6c9286a MM |
17066 | { |
17067 | int ret = 0; | |
17068 | ||
17069 | switch (DEFAULT_ABI) | |
17070 | { | |
17071 | default: | |
37409796 | 17072 | gcc_unreachable (); |
b6c9286a MM |
17073 | |
17074 | case ABI_AIX: | |
8f802bfb | 17075 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
17076 | break; |
17077 | ||
4dabc42d | 17078 | case ABI_DARWIN: |
b6c9286a | 17079 | case ABI_V4: |
03a7e1a5 | 17080 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 17081 | break; |
b6c9286a MM |
17082 | } |
17083 | ||
17084 | return ret; | |
17085 | } | |
17086 | ||
17087 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
17088 | FNADDR is an RTX for the address of the function's pure code. | |
17089 | CXT is an RTX for the static chain value for the function. */ | |
17090 | ||
17091 | void | |
a2369ed3 | 17092 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 17093 | { |
ac2a93a1 | 17094 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
17095 | int regsize = (TARGET_32BIT) ? 4 : 8; |
17096 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
17097 | |
17098 | switch (DEFAULT_ABI) | |
17099 | { | |
17100 | default: | |
37409796 | 17101 | gcc_unreachable (); |
b6c9286a | 17102 | |
8bd04c56 | 17103 | /* Macros to shorten the code expansions below. */ |
39403d82 | 17104 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
17105 | #define MEM_PLUS(addr,offset) \ |
17106 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 17107 | |
b6c9286a MM |
17108 | /* Under AIX, just build the 3 word function descriptor */ |
17109 | case ABI_AIX: | |
8bd04c56 MM |
17110 | { |
17111 | rtx fn_reg = gen_reg_rtx (pmode); | |
17112 | rtx toc_reg = gen_reg_rtx (pmode); | |
17113 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 17114 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
17115 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
17116 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
17117 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
17118 | } | |
b6c9286a MM |
17119 | break; |
17120 | ||
4dabc42d TC |
17121 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
17122 | case ABI_DARWIN: | |
b6c9286a | 17123 | case ABI_V4: |
39403d82 | 17124 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
17125 | FALSE, VOIDmode, 4, |
17126 | addr, pmode, | |
17127 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
17128 | fnaddr, pmode, | |
17129 | ctx_reg, pmode); | |
b6c9286a | 17130 | break; |
b6c9286a MM |
17131 | } |
17132 | ||
17133 | return; | |
17134 | } | |
7509c759 MM |
17135 | |
17136 | \f | |
91d231cb | 17137 | /* Table of valid machine attributes. */ |
a4f6c312 | 17138 | |
91d231cb | 17139 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 17140 | { |
91d231cb | 17141 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8bb418a3 | 17142 | { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, |
a5c76ee6 ZW |
17143 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
17144 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
005c1a13 GK |
17145 | #ifdef SUBTARGET_ATTRIBUTE_TABLE |
17146 | SUBTARGET_ATTRIBUTE_TABLE, | |
17147 | #endif | |
a5c76ee6 | 17148 | { NULL, 0, 0, false, false, false, NULL } |
91d231cb | 17149 | }; |
7509c759 | 17150 | |
8bb418a3 ZL |
17151 | /* Handle the "altivec" attribute. The attribute may have |
17152 | arguments as follows: | |
f676971a | 17153 | |
8bb418a3 ZL |
17154 | __attribute__((altivec(vector__))) |
17155 | __attribute__((altivec(pixel__))) (always followed by 'unsigned short') | |
17156 | __attribute__((altivec(bool__))) (always followed by 'unsigned') | |
17157 | ||
17158 | and may appear more than once (e.g., 'vector bool char') in a | |
17159 | given declaration. */ | |
17160 | ||
17161 | static tree | |
f90ac3f0 UP |
17162 | rs6000_handle_altivec_attribute (tree *node, |
17163 | tree name ATTRIBUTE_UNUSED, | |
17164 | tree args, | |
8bb418a3 ZL |
17165 | int flags ATTRIBUTE_UNUSED, |
17166 | bool *no_add_attrs) | |
17167 | { | |
17168 | tree type = *node, result = NULL_TREE; | |
17169 | enum machine_mode mode; | |
17170 | int unsigned_p; | |
17171 | char altivec_type | |
17172 | = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) | |
17173 | && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) | |
17174 | ? *IDENTIFIER_POINTER (TREE_VALUE (args)) | |
f676971a | 17175 | : '?'); |
8bb418a3 ZL |
17176 | |
17177 | while (POINTER_TYPE_P (type) | |
17178 | || TREE_CODE (type) == FUNCTION_TYPE | |
17179 | || TREE_CODE (type) == METHOD_TYPE | |
17180 | || TREE_CODE (type) == ARRAY_TYPE) | |
17181 | type = TREE_TYPE (type); | |
17182 | ||
17183 | mode = TYPE_MODE (type); | |
17184 | ||
f90ac3f0 UP |
17185 | /* Check for invalid AltiVec type qualifiers. */ |
17186 | if (type == long_unsigned_type_node || type == long_integer_type_node) | |
17187 | { | |
17188 | if (TARGET_64BIT) | |
17189 | error ("use of %<long%> in AltiVec types is invalid for 64-bit code"); | |
17190 | else if (rs6000_warn_altivec_long) | |
d4ee4d25 | 17191 | warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>"); |
f90ac3f0 UP |
17192 | } |
17193 | else if (type == long_long_unsigned_type_node | |
17194 | || type == long_long_integer_type_node) | |
17195 | error ("use of %<long long%> in AltiVec types is invalid"); | |
17196 | else if (type == double_type_node) | |
17197 | error ("use of %<double%> in AltiVec types is invalid"); | |
17198 | else if (type == long_double_type_node) | |
17199 | error ("use of %<long double%> in AltiVec types is invalid"); | |
17200 | else if (type == boolean_type_node) | |
17201 | error ("use of boolean types in AltiVec types is invalid"); | |
17202 | else if (TREE_CODE (type) == COMPLEX_TYPE) | |
17203 | error ("use of %<complex%> in AltiVec types is invalid"); | |
8bb418a3 ZL |
17204 | |
17205 | switch (altivec_type) | |
17206 | { | |
17207 | case 'v': | |
8df83eae | 17208 | unsigned_p = TYPE_UNSIGNED (type); |
8bb418a3 ZL |
17209 | switch (mode) |
17210 | { | |
c4ad648e AM |
17211 | case SImode: |
17212 | result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); | |
17213 | break; | |
17214 | case HImode: | |
17215 | result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); | |
17216 | break; | |
17217 | case QImode: | |
17218 | result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); | |
17219 | break; | |
17220 | case SFmode: result = V4SF_type_node; break; | |
17221 | /* If the user says 'vector int bool', we may be handed the 'bool' | |
17222 | attribute _before_ the 'vector' attribute, and so select the | |
17223 | proper type in the 'b' case below. */ | |
17224 | case V4SImode: case V8HImode: case V16QImode: case V4SFmode: | |
17225 | result = type; | |
17226 | default: break; | |
8bb418a3 ZL |
17227 | } |
17228 | break; | |
17229 | case 'b': | |
17230 | switch (mode) | |
17231 | { | |
c4ad648e AM |
17232 | case SImode: case V4SImode: result = bool_V4SI_type_node; break; |
17233 | case HImode: case V8HImode: result = bool_V8HI_type_node; break; | |
17234 | case QImode: case V16QImode: result = bool_V16QI_type_node; | |
17235 | default: break; | |
8bb418a3 ZL |
17236 | } |
17237 | break; | |
17238 | case 'p': | |
17239 | switch (mode) | |
17240 | { | |
c4ad648e AM |
17241 | case V8HImode: result = pixel_V8HI_type_node; |
17242 | default: break; | |
8bb418a3 ZL |
17243 | } |
17244 | default: break; | |
17245 | } | |
17246 | ||
7958a2a6 FJ |
17247 | if (result && result != type && TYPE_READONLY (type)) |
17248 | result = build_qualified_type (result, TYPE_QUAL_CONST); | |
17249 | ||
8bb418a3 ZL |
17250 | *no_add_attrs = true; /* No need to hang on to the attribute. */ |
17251 | ||
f90ac3f0 | 17252 | if (result) |
8bb418a3 ZL |
17253 | *node = reconstruct_complex_type (*node, result); |
17254 | ||
17255 | return NULL_TREE; | |
17256 | } | |
17257 | ||
f18eca82 ZL |
17258 | /* AltiVec defines four built-in scalar types that serve as vector |
17259 | elements; we must teach the compiler how to mangle them. */ | |
17260 | ||
17261 | static const char * | |
17262 | rs6000_mangle_fundamental_type (tree type) | |
17263 | { | |
17264 | if (type == bool_char_type_node) return "U6__boolc"; | |
17265 | if (type == bool_short_type_node) return "U6__bools"; | |
17266 | if (type == pixel_type_node) return "u7__pixel"; | |
17267 | if (type == bool_int_type_node) return "U6__booli"; | |
17268 | ||
17269 | /* For all other types, use normal C++ mangling. */ | |
17270 | return NULL; | |
17271 | } | |
17272 | ||
a5c76ee6 ZW |
17273 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
17274 | struct attribute_spec.handler. */ | |
a4f6c312 | 17275 | |
91d231cb | 17276 | static tree |
f676971a EC |
17277 | rs6000_handle_longcall_attribute (tree *node, tree name, |
17278 | tree args ATTRIBUTE_UNUSED, | |
17279 | int flags ATTRIBUTE_UNUSED, | |
a2369ed3 | 17280 | bool *no_add_attrs) |
91d231cb JM |
17281 | { |
17282 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
17283 | && TREE_CODE (*node) != FIELD_DECL | |
17284 | && TREE_CODE (*node) != TYPE_DECL) | |
17285 | { | |
5c498b10 | 17286 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
91d231cb JM |
17287 | IDENTIFIER_POINTER (name)); |
17288 | *no_add_attrs = true; | |
17289 | } | |
6a4cee5f | 17290 | |
91d231cb | 17291 | return NULL_TREE; |
7509c759 MM |
17292 | } |
17293 | ||
a5c76ee6 ZW |
17294 | /* Set longcall attributes on all functions declared when |
17295 | rs6000_default_long_calls is true. */ | |
17296 | static void | |
a2369ed3 | 17297 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
17298 | { |
17299 | if (rs6000_default_long_calls | |
17300 | && (TREE_CODE (type) == FUNCTION_TYPE | |
17301 | || TREE_CODE (type) == METHOD_TYPE)) | |
17302 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
17303 | NULL_TREE, | |
17304 | TYPE_ATTRIBUTES (type)); | |
17305 | } | |
17306 | ||
3cb999d8 DE |
17307 | /* Return a reference suitable for calling a function with the |
17308 | longcall attribute. */ | |
a4f6c312 | 17309 | |
9390387d | 17310 | rtx |
a2369ed3 | 17311 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 17312 | { |
d330fd93 | 17313 | const char *call_name; |
6a4cee5f MM |
17314 | tree node; |
17315 | ||
17316 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
17317 | return call_ref; | |
17318 | ||
17319 | /* System V adds '.' to the internal name, so skip them. */ | |
17320 | call_name = XSTR (call_ref, 0); | |
17321 | if (*call_name == '.') | |
17322 | { | |
17323 | while (*call_name == '.') | |
17324 | call_name++; | |
17325 | ||
17326 | node = get_identifier (call_name); | |
39403d82 | 17327 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
17328 | } |
17329 | ||
17330 | return force_reg (Pmode, call_ref); | |
17331 | } | |
7509c759 | 17332 | \f |
b64a1b53 RH |
17333 | #ifdef USING_ELFOS_H |
17334 | ||
d6b5193b | 17335 | /* A get_unnamed_section callback, used for switching to toc_section. */ |
7509c759 | 17336 | |
d6b5193b RS |
17337 | static void |
17338 | rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
17339 | { | |
17340 | if (DEFAULT_ABI == ABI_AIX | |
17341 | && TARGET_MINIMAL_TOC | |
17342 | && !TARGET_RELOCATABLE) | |
17343 | { | |
17344 | if (!toc_initialized) | |
17345 | { | |
17346 | toc_initialized = 1; | |
17347 | fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP); | |
17348 | (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0); | |
17349 | fprintf (asm_out_file, "\t.tc "); | |
17350 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],"); | |
17351 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1"); | |
17352 | fprintf (asm_out_file, "\n"); | |
17353 | ||
17354 | fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
17355 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1"); | |
17356 | fprintf (asm_out_file, " = .+32768\n"); | |
17357 | } | |
17358 | else | |
17359 | fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
17360 | } | |
17361 | else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE) | |
17362 | fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP); | |
17363 | else | |
17364 | { | |
17365 | fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
17366 | if (!toc_initialized) | |
17367 | { | |
17368 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1"); | |
17369 | fprintf (asm_out_file, " = .+32768\n"); | |
17370 | toc_initialized = 1; | |
17371 | } | |
17372 | } | |
17373 | } | |
17374 | ||
17375 | /* Implement TARGET_ASM_INIT_SECTIONS. */ | |
7509c759 | 17376 | |
b64a1b53 | 17377 | static void |
d6b5193b RS |
17378 | rs6000_elf_asm_init_sections (void) |
17379 | { | |
17380 | toc_section | |
17381 | = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL); | |
17382 | ||
17383 | sdata2_section | |
17384 | = get_unnamed_section (SECTION_WRITE, output_section_asm_op, | |
17385 | SDATA2_SECTION_ASM_OP); | |
17386 | } | |
17387 | ||
17388 | /* Implement TARGET_SELECT_RTX_SECTION. */ | |
17389 | ||
17390 | static section * | |
f676971a | 17391 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
a2369ed3 | 17392 | unsigned HOST_WIDE_INT align) |
7509c759 | 17393 | { |
a9098fd0 | 17394 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
d6b5193b | 17395 | return toc_section; |
7509c759 | 17396 | else |
d6b5193b | 17397 | return default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
17398 | } |
17399 | ||
d6b5193b | 17400 | /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */ |
7509c759 | 17401 | |
d6b5193b | 17402 | static section * |
f676971a | 17403 | rs6000_elf_select_section (tree decl, int reloc, |
a2369ed3 | 17404 | unsigned HOST_WIDE_INT align) |
7509c759 | 17405 | { |
f1384257 AM |
17406 | /* Pretend that we're always building for a shared library when |
17407 | ABI_AIX, because otherwise we end up with dynamic relocations | |
17408 | in read-only sections. This happens for function pointers, | |
17409 | references to vtables in typeinfo, and probably other cases. */ | |
d6b5193b RS |
17410 | return default_elf_select_section_1 (decl, reloc, align, |
17411 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
17412 | } |
17413 | ||
17414 | /* A C statement to build up a unique section name, expressed as a | |
17415 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
17416 | RELOC indicates whether the initial value of EXP requires | |
17417 | link-time relocations. If you do not define this macro, GCC will use | |
17418 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 17419 | macro can now be called for uninitialized data items as well as |
4912a07c | 17420 | initialized data and functions. */ |
63019373 | 17421 | |
ae46c4e0 | 17422 | static void |
a2369ed3 | 17423 | rs6000_elf_unique_section (tree decl, int reloc) |
63019373 | 17424 | { |
f1384257 AM |
17425 | /* As above, pretend that we're always building for a shared library |
17426 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
17427 | default_unique_section_1 (decl, reloc, |
17428 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 17429 | } |
d9407988 | 17430 | \f |
d1908feb JJ |
17431 | /* For a SYMBOL_REF, set generic flags and then perform some |
17432 | target-specific processing. | |
17433 | ||
d1908feb JJ |
17434 | When the AIX ABI is requested on a non-AIX system, replace the |
17435 | function name with the real name (with a leading .) rather than the | |
17436 | function descriptor name. This saves a lot of overriding code to | |
17437 | read the prefixes. */ | |
d9407988 | 17438 | |
fb49053f | 17439 | static void |
a2369ed3 | 17440 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 17441 | { |
d1908feb | 17442 | default_encode_section_info (decl, rtl, first); |
b2003250 | 17443 | |
d1908feb JJ |
17444 | if (first |
17445 | && TREE_CODE (decl) == FUNCTION_DECL | |
17446 | && !TARGET_AIX | |
17447 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 17448 | { |
c6a2438a | 17449 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
17450 | size_t len = strlen (XSTR (sym_ref, 0)); |
17451 | char *str = alloca (len + 2); | |
17452 | str[0] = '.'; | |
17453 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
17454 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 17455 | } |
d9407988 MM |
17456 | } |
17457 | ||
c1b7d95a | 17458 | bool |
a2369ed3 | 17459 | rs6000_elf_in_small_data_p (tree decl) |
0e5dbd9b DE |
17460 | { |
17461 | if (rs6000_sdata == SDATA_NONE) | |
17462 | return false; | |
17463 | ||
7482ad25 AF |
17464 | /* We want to merge strings, so we never consider them small data. */ |
17465 | if (TREE_CODE (decl) == STRING_CST) | |
17466 | return false; | |
17467 | ||
17468 | /* Functions are never in the small data area. */ | |
17469 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
17470 | return false; | |
17471 | ||
0e5dbd9b DE |
17472 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) |
17473 | { | |
17474 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
17475 | if (strcmp (section, ".sdata") == 0 | |
17476 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
17477 | || strcmp (section, ".sbss") == 0 |
17478 | || strcmp (section, ".sbss2") == 0 | |
17479 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
17480 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
17481 | return true; |
17482 | } | |
17483 | else | |
17484 | { | |
17485 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
17486 | ||
17487 | if (size > 0 | |
307b599c | 17488 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
17489 | /* If it's not public, and we're not going to reference it there, |
17490 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
17491 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
17492 | return true; | |
17493 | } | |
17494 | ||
17495 | return false; | |
17496 | } | |
17497 | ||
b91da81f | 17498 | #endif /* USING_ELFOS_H */ |
000034eb | 17499 | |
a6c2a102 | 17500 | \f |
000034eb | 17501 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
17502 | ADDR can be effectively incremented by incrementing REG. |
17503 | ||
17504 | r0 is special and we must not select it as an address | |
17505 | register by this routine since our caller will try to | |
17506 | increment the returned register via an "la" instruction. */ | |
000034eb | 17507 | |
9390387d | 17508 | rtx |
a2369ed3 | 17509 | find_addr_reg (rtx addr) |
000034eb DE |
17510 | { |
17511 | while (GET_CODE (addr) == PLUS) | |
17512 | { | |
02441cd6 JL |
17513 | if (GET_CODE (XEXP (addr, 0)) == REG |
17514 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 17515 | addr = XEXP (addr, 0); |
02441cd6 JL |
17516 | else if (GET_CODE (XEXP (addr, 1)) == REG |
17517 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
17518 | addr = XEXP (addr, 1); |
17519 | else if (CONSTANT_P (XEXP (addr, 0))) | |
17520 | addr = XEXP (addr, 1); | |
17521 | else if (CONSTANT_P (XEXP (addr, 1))) | |
17522 | addr = XEXP (addr, 0); | |
17523 | else | |
37409796 | 17524 | gcc_unreachable (); |
000034eb | 17525 | } |
37409796 NS |
17526 | gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0); |
17527 | return addr; | |
000034eb DE |
17528 | } |
17529 | ||
a6c2a102 | 17530 | void |
a2369ed3 | 17531 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
17532 | { |
17533 | fatal_insn ("bad address", op); | |
17534 | } | |
c8023011 | 17535 | |
ee890fe2 SS |
17536 | #if TARGET_MACHO |
17537 | ||
efdba735 | 17538 | static tree branch_island_list = 0; |
ee890fe2 | 17539 | |
efdba735 SH |
17540 | /* Remember to generate a branch island for far calls to the given |
17541 | function. */ | |
ee890fe2 | 17542 | |
f676971a | 17543 | static void |
c4ad648e AM |
17544 | add_compiler_branch_island (tree label_name, tree function_name, |
17545 | int line_number) | |
ee890fe2 | 17546 | { |
efdba735 | 17547 | tree branch_island = build_tree_list (function_name, label_name); |
7d60be94 | 17548 | TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number); |
efdba735 SH |
17549 | TREE_CHAIN (branch_island) = branch_island_list; |
17550 | branch_island_list = branch_island; | |
ee890fe2 SS |
17551 | } |
17552 | ||
efdba735 SH |
17553 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
17554 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
17555 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
17556 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 17557 | |
efdba735 SH |
17558 | /* Generate far-jump branch islands for everything on the |
17559 | branch_island_list. Invoked immediately after the last instruction | |
17560 | of the epilogue has been emitted; the branch-islands must be | |
17561 | appended to, and contiguous with, the function body. Mach-O stubs | |
17562 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 17563 | |
efdba735 SH |
17564 | static void |
17565 | macho_branch_islands (void) | |
17566 | { | |
17567 | char tmp_buf[512]; | |
17568 | tree branch_island; | |
17569 | ||
17570 | for (branch_island = branch_island_list; | |
17571 | branch_island; | |
17572 | branch_island = TREE_CHAIN (branch_island)) | |
17573 | { | |
17574 | const char *label = | |
17575 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
17576 | const char *name = | |
11abc112 | 17577 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)); |
efdba735 SH |
17578 | char name_buf[512]; |
17579 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
17580 | if (name[0] == '*' || name[0] == '&') | |
17581 | strcpy (name_buf, name+1); | |
17582 | else | |
17583 | { | |
17584 | name_buf[0] = '_'; | |
17585 | strcpy (name_buf+1, name); | |
17586 | } | |
17587 | strcpy (tmp_buf, "\n"); | |
17588 | strcat (tmp_buf, label); | |
ee890fe2 | 17589 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 17590 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 17591 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 17592 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
17593 | if (flag_pic) |
17594 | { | |
17595 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
17596 | strcat (tmp_buf, label); | |
17597 | strcat (tmp_buf, "_pic\n"); | |
17598 | strcat (tmp_buf, label); | |
17599 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
f676971a | 17600 | |
efdba735 SH |
17601 | strcat (tmp_buf, "\taddis r11,r11,ha16("); |
17602 | strcat (tmp_buf, name_buf); | |
17603 | strcat (tmp_buf, " - "); | |
17604 | strcat (tmp_buf, label); | |
17605 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 17606 | |
efdba735 | 17607 | strcat (tmp_buf, "\tmtlr r0\n"); |
f676971a | 17608 | |
efdba735 SH |
17609 | strcat (tmp_buf, "\taddi r12,r11,lo16("); |
17610 | strcat (tmp_buf, name_buf); | |
17611 | strcat (tmp_buf, " - "); | |
17612 | strcat (tmp_buf, label); | |
17613 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 17614 | |
efdba735 SH |
17615 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); |
17616 | } | |
17617 | else | |
17618 | { | |
17619 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
17620 | strcat (tmp_buf, name_buf); | |
17621 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
17622 | strcat (tmp_buf, name_buf); | |
17623 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
17624 | } | |
17625 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 17626 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 17627 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 17628 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 17629 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 17630 | } |
ee890fe2 | 17631 | |
efdba735 | 17632 | branch_island_list = 0; |
ee890fe2 SS |
17633 | } |
17634 | ||
17635 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
17636 | already there or not. */ | |
17637 | ||
efdba735 | 17638 | static int |
a2369ed3 | 17639 | no_previous_def (tree function_name) |
ee890fe2 | 17640 | { |
efdba735 SH |
17641 | tree branch_island; |
17642 | for (branch_island = branch_island_list; | |
17643 | branch_island; | |
17644 | branch_island = TREE_CHAIN (branch_island)) | |
17645 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
17646 | return 0; |
17647 | return 1; | |
17648 | } | |
17649 | ||
17650 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
17651 | the function. */ | |
17652 | ||
efdba735 | 17653 | static tree |
a2369ed3 | 17654 | get_prev_label (tree function_name) |
ee890fe2 | 17655 | { |
efdba735 SH |
17656 | tree branch_island; |
17657 | for (branch_island = branch_island_list; | |
17658 | branch_island; | |
17659 | branch_island = TREE_CHAIN (branch_island)) | |
17660 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
17661 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
17662 | return 0; |
17663 | } | |
17664 | ||
17665 | /* INSN is either a function call or a millicode call. It may have an | |
f676971a | 17666 | unconditional jump in its delay slot. |
ee890fe2 SS |
17667 | |
17668 | CALL_DEST is the routine we are calling. */ | |
17669 | ||
17670 | char * | |
c4ad648e AM |
17671 | output_call (rtx insn, rtx *operands, int dest_operand_number, |
17672 | int cookie_operand_number) | |
ee890fe2 SS |
17673 | { |
17674 | static char buf[256]; | |
efdba735 SH |
17675 | if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF |
17676 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) | |
ee890fe2 SS |
17677 | { |
17678 | tree labelname; | |
efdba735 | 17679 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
f676971a | 17680 | |
ee890fe2 SS |
17681 | if (no_previous_def (funname)) |
17682 | { | |
308c142a | 17683 | int line_number = 0; |
ee890fe2 SS |
17684 | rtx label_rtx = gen_label_rtx (); |
17685 | char *label_buf, temp_buf[256]; | |
17686 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
17687 | CODE_LABEL_NUMBER (label_rtx)); | |
17688 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
17689 | labelname = get_identifier (label_buf); | |
17690 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
17691 | if (insn) | |
17692 | line_number = NOTE_LINE_NUMBER (insn); | |
efdba735 | 17693 | add_compiler_branch_island (labelname, funname, line_number); |
ee890fe2 SS |
17694 | } |
17695 | else | |
17696 | labelname = get_prev_label (funname); | |
17697 | ||
efdba735 SH |
17698 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
17699 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
17700 | "L42" should be a 'branch island', that will do a far jump to | |
17701 | 'foo'. Branch islands are generated in | |
17702 | macho_branch_islands(). */ | |
ee890fe2 | 17703 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 17704 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
17705 | } |
17706 | else | |
efdba735 SH |
17707 | sprintf (buf, "bl %%z%d", dest_operand_number); |
17708 | return buf; | |
ee890fe2 SS |
17709 | } |
17710 | ||
ee890fe2 SS |
17711 | /* Generate PIC and indirect symbol stubs. */ |
17712 | ||
17713 | void | |
a2369ed3 | 17714 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
17715 | { |
17716 | unsigned int length; | |
a4f6c312 SS |
17717 | char *symbol_name, *lazy_ptr_name; |
17718 | char *local_label_0; | |
ee890fe2 SS |
17719 | static int label = 0; |
17720 | ||
df56a27f | 17721 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 17722 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 17723 | |
ee890fe2 | 17724 | |
ee890fe2 SS |
17725 | length = strlen (symb); |
17726 | symbol_name = alloca (length + 32); | |
17727 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
17728 | ||
17729 | lazy_ptr_name = alloca (length + 32); | |
17730 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
17731 | ||
ee890fe2 | 17732 | if (flag_pic == 2) |
d6b5193b | 17733 | switch_to_section (machopic_picsymbol_stub1_section); |
ee890fe2 | 17734 | else |
d6b5193b | 17735 | switch_to_section (machopic_symbol_stub1_section); |
ee890fe2 SS |
17736 | |
17737 | if (flag_pic == 2) | |
17738 | { | |
d974312d DJ |
17739 | fprintf (file, "\t.align 5\n"); |
17740 | ||
17741 | fprintf (file, "%s:\n", stub); | |
17742 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
17743 | ||
876455fa | 17744 | label++; |
89da1f32 | 17745 | local_label_0 = alloca (sizeof ("\"L00000000000$spb\"")); |
876455fa | 17746 | sprintf (local_label_0, "\"L%011d$spb\"", label); |
f676971a | 17747 | |
ee890fe2 SS |
17748 | fprintf (file, "\tmflr r0\n"); |
17749 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
17750 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
17751 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
17752 | lazy_ptr_name, local_label_0); | |
17753 | fprintf (file, "\tmtlr r0\n"); | |
3d0e2d58 SS |
17754 | fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n", |
17755 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
ee890fe2 SS |
17756 | lazy_ptr_name, local_label_0); |
17757 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
17758 | fprintf (file, "\tbctr\n"); |
17759 | } | |
17760 | else | |
d974312d DJ |
17761 | { |
17762 | fprintf (file, "\t.align 4\n"); | |
17763 | ||
17764 | fprintf (file, "%s:\n", stub); | |
17765 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
17766 | ||
17767 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
d9e4e4f5 SS |
17768 | fprintf (file, "\t%s r12,lo16(%s)(r11)\n", |
17769 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
17770 | lazy_ptr_name); | |
d974312d DJ |
17771 | fprintf (file, "\tmtctr r12\n"); |
17772 | fprintf (file, "\tbctr\n"); | |
17773 | } | |
f676971a | 17774 | |
d6b5193b | 17775 | switch_to_section (machopic_lazy_symbol_ptr_section); |
ee890fe2 SS |
17776 | fprintf (file, "%s:\n", lazy_ptr_name); |
17777 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
49bd1d27 SS |
17778 | fprintf (file, "%sdyld_stub_binding_helper\n", |
17779 | (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t")); | |
ee890fe2 SS |
17780 | } |
17781 | ||
17782 | /* Legitimize PIC addresses. If the address is already | |
17783 | position-independent, we return ORIG. Newly generated | |
17784 | position-independent addresses go into a reg. This is REG if non | |
17785 | zero, otherwise we allocate register(s) as necessary. */ | |
17786 | ||
9390387d | 17787 | #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000) |
ee890fe2 SS |
17788 | |
17789 | rtx | |
f676971a | 17790 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
a2369ed3 | 17791 | rtx reg) |
ee890fe2 SS |
17792 | { |
17793 | rtx base, offset; | |
17794 | ||
17795 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
17796 | reg = gen_reg_rtx (Pmode); | |
17797 | ||
17798 | if (GET_CODE (orig) == CONST) | |
17799 | { | |
37409796 NS |
17800 | rtx reg_temp; |
17801 | ||
ee890fe2 SS |
17802 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
17803 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
17804 | return orig; | |
17805 | ||
37409796 | 17806 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
bb8df8a6 | 17807 | |
37409796 NS |
17808 | /* Use a different reg for the intermediate value, as |
17809 | it will be marked UNCHANGING. */ | |
17810 | reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); | |
17811 | base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
17812 | Pmode, reg_temp); | |
17813 | offset = | |
17814 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
17815 | Pmode, reg); | |
bb8df8a6 | 17816 | |
ee890fe2 SS |
17817 | if (GET_CODE (offset) == CONST_INT) |
17818 | { | |
17819 | if (SMALL_INT (offset)) | |
ed8908e7 | 17820 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
17821 | else if (! reload_in_progress && ! reload_completed) |
17822 | offset = force_reg (Pmode, offset); | |
17823 | else | |
c859cda6 DJ |
17824 | { |
17825 | rtx mem = force_const_mem (Pmode, orig); | |
17826 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
17827 | } | |
ee890fe2 | 17828 | } |
f1c25d3b | 17829 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
17830 | } |
17831 | ||
17832 | /* Fall back on generic machopic code. */ | |
17833 | return machopic_legitimize_pic_address (orig, mode, reg); | |
17834 | } | |
17835 | ||
c4e18b1c GK |
17836 | /* Output a .machine directive for the Darwin assembler, and call |
17837 | the generic start_file routine. */ | |
17838 | ||
17839 | static void | |
17840 | rs6000_darwin_file_start (void) | |
17841 | { | |
94ff898d | 17842 | static const struct |
c4e18b1c GK |
17843 | { |
17844 | const char *arg; | |
17845 | const char *name; | |
17846 | int if_set; | |
17847 | } mapping[] = { | |
55dbfb48 | 17848 | { "ppc64", "ppc64", MASK_64BIT }, |
c4e18b1c GK |
17849 | { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, |
17850 | { "power4", "ppc970", 0 }, | |
17851 | { "G5", "ppc970", 0 }, | |
17852 | { "7450", "ppc7450", 0 }, | |
17853 | { "7400", "ppc7400", MASK_ALTIVEC }, | |
17854 | { "G4", "ppc7400", 0 }, | |
17855 | { "750", "ppc750", 0 }, | |
17856 | { "740", "ppc750", 0 }, | |
17857 | { "G3", "ppc750", 0 }, | |
17858 | { "604e", "ppc604e", 0 }, | |
17859 | { "604", "ppc604", 0 }, | |
17860 | { "603e", "ppc603", 0 }, | |
17861 | { "603", "ppc603", 0 }, | |
17862 | { "601", "ppc601", 0 }, | |
17863 | { NULL, "ppc", 0 } }; | |
17864 | const char *cpu_id = ""; | |
17865 | size_t i; | |
94ff898d | 17866 | |
9390387d | 17867 | rs6000_file_start (); |
c4e18b1c GK |
17868 | |
17869 | /* Determine the argument to -mcpu=. Default to G3 if not specified. */ | |
17870 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) | |
17871 | if (rs6000_select[i].set_arch_p && rs6000_select[i].string | |
17872 | && rs6000_select[i].string[0] != '\0') | |
17873 | cpu_id = rs6000_select[i].string; | |
17874 | ||
17875 | /* Look through the mapping array. Pick the first name that either | |
17876 | matches the argument, has a bit set in IF_SET that is also set | |
17877 | in the target flags, or has a NULL name. */ | |
17878 | ||
17879 | i = 0; | |
17880 | while (mapping[i].arg != NULL | |
17881 | && strcmp (mapping[i].arg, cpu_id) != 0 | |
17882 | && (mapping[i].if_set & target_flags) == 0) | |
17883 | i++; | |
17884 | ||
17885 | fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); | |
17886 | } | |
17887 | ||
ee890fe2 | 17888 | #endif /* TARGET_MACHO */ |
7c262518 RH |
17889 | |
17890 | #if TARGET_ELF | |
17891 | static unsigned int | |
a2369ed3 | 17892 | rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) |
7c262518 | 17893 | { |
1ff8f81a AM |
17894 | return default_section_type_flags_1 (decl, name, reloc, |
17895 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 17896 | } |
d9f6800d RH |
17897 | |
17898 | /* Record an element in the table of global constructors. SYMBOL is | |
17899 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
17900 | between 0 and MAX_INIT_PRIORITY. | |
17901 | ||
17902 | This differs from default_named_section_asm_out_constructor in | |
17903 | that we have special handling for -mrelocatable. */ | |
17904 | ||
17905 | static void | |
a2369ed3 | 17906 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
17907 | { |
17908 | const char *section = ".ctors"; | |
17909 | char buf[16]; | |
17910 | ||
17911 | if (priority != DEFAULT_INIT_PRIORITY) | |
17912 | { | |
17913 | sprintf (buf, ".ctors.%.5u", | |
c4ad648e AM |
17914 | /* Invert the numbering so the linker puts us in the proper |
17915 | order; constructors are run from right to left, and the | |
17916 | linker sorts in increasing order. */ | |
17917 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
17918 | section = buf; |
17919 | } | |
17920 | ||
d6b5193b | 17921 | switch_to_section (get_section (section, SECTION_WRITE, NULL)); |
715bdd29 | 17922 | assemble_align (POINTER_SIZE); |
d9f6800d RH |
17923 | |
17924 | if (TARGET_RELOCATABLE) | |
17925 | { | |
17926 | fputs ("\t.long (", asm_out_file); | |
17927 | output_addr_const (asm_out_file, symbol); | |
17928 | fputs (")@fixup\n", asm_out_file); | |
17929 | } | |
17930 | else | |
c8af3574 | 17931 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
17932 | } |
17933 | ||
17934 | static void | |
a2369ed3 | 17935 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
17936 | { |
17937 | const char *section = ".dtors"; | |
17938 | char buf[16]; | |
17939 | ||
17940 | if (priority != DEFAULT_INIT_PRIORITY) | |
17941 | { | |
17942 | sprintf (buf, ".dtors.%.5u", | |
c4ad648e AM |
17943 | /* Invert the numbering so the linker puts us in the proper |
17944 | order; constructors are run from right to left, and the | |
17945 | linker sorts in increasing order. */ | |
17946 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
17947 | section = buf; |
17948 | } | |
17949 | ||
d6b5193b | 17950 | switch_to_section (get_section (section, SECTION_WRITE, NULL)); |
715bdd29 | 17951 | assemble_align (POINTER_SIZE); |
d9f6800d RH |
17952 | |
17953 | if (TARGET_RELOCATABLE) | |
17954 | { | |
17955 | fputs ("\t.long (", asm_out_file); | |
17956 | output_addr_const (asm_out_file, symbol); | |
17957 | fputs (")@fixup\n", asm_out_file); | |
17958 | } | |
17959 | else | |
c8af3574 | 17960 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 17961 | } |
9739c90c JJ |
17962 | |
17963 | void | |
a2369ed3 | 17964 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
17965 | { |
17966 | if (TARGET_64BIT) | |
17967 | { | |
17968 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
17969 | ASM_OUTPUT_LABEL (file, name); | |
17970 | fputs (DOUBLE_INT_ASM_OP, file); | |
85b776df AM |
17971 | rs6000_output_function_entry (file, name); |
17972 | fputs (",.TOC.@tocbase,0\n\t.previous\n", file); | |
17973 | if (DOT_SYMBOLS) | |
9739c90c | 17974 | { |
85b776df | 17975 | fputs ("\t.size\t", file); |
9739c90c | 17976 | assemble_name (file, name); |
85b776df AM |
17977 | fputs (",24\n\t.type\t.", file); |
17978 | assemble_name (file, name); | |
17979 | fputs (",@function\n", file); | |
17980 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
17981 | { | |
17982 | fputs ("\t.globl\t.", file); | |
17983 | assemble_name (file, name); | |
17984 | putc ('\n', file); | |
17985 | } | |
9739c90c | 17986 | } |
85b776df AM |
17987 | else |
17988 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
9739c90c | 17989 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); |
85b776df AM |
17990 | rs6000_output_function_entry (file, name); |
17991 | fputs (":\n", file); | |
9739c90c JJ |
17992 | return; |
17993 | } | |
17994 | ||
17995 | if (TARGET_RELOCATABLE | |
7f970b70 | 17996 | && !TARGET_SECURE_PLT |
9739c90c | 17997 | && (get_pool_size () != 0 || current_function_profile) |
3c9eb5f4 | 17998 | && uses_TOC ()) |
9739c90c JJ |
17999 | { |
18000 | char buf[256]; | |
18001 | ||
18002 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
18003 | ||
18004 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
18005 | fprintf (file, "\t.long "); | |
18006 | assemble_name (file, buf); | |
18007 | putc ('-', file); | |
18008 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
18009 | assemble_name (file, buf); | |
18010 | putc ('\n', file); | |
18011 | } | |
18012 | ||
18013 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
18014 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
18015 | ||
18016 | if (DEFAULT_ABI == ABI_AIX) | |
18017 | { | |
18018 | const char *desc_name, *orig_name; | |
18019 | ||
18020 | orig_name = (*targetm.strip_name_encoding) (name); | |
18021 | desc_name = orig_name; | |
18022 | while (*desc_name == '.') | |
18023 | desc_name++; | |
18024 | ||
18025 | if (TREE_PUBLIC (decl)) | |
18026 | fprintf (file, "\t.globl %s\n", desc_name); | |
18027 | ||
18028 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
18029 | fprintf (file, "%s:\n", desc_name); | |
18030 | fprintf (file, "\t.long %s\n", orig_name); | |
18031 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
18032 | if (DEFAULT_ABI == ABI_AIX) | |
18033 | fputs ("\t.long 0\n", file); | |
18034 | fprintf (file, "\t.previous\n"); | |
18035 | } | |
18036 | ASM_OUTPUT_LABEL (file, name); | |
18037 | } | |
1334b570 AM |
18038 | |
18039 | static void | |
18040 | rs6000_elf_end_indicate_exec_stack (void) | |
18041 | { | |
18042 | if (TARGET_32BIT) | |
18043 | file_end_indicate_exec_stack (); | |
18044 | } | |
7c262518 RH |
18045 | #endif |
18046 | ||
cbaaba19 | 18047 | #if TARGET_XCOFF |
7c262518 | 18048 | static void |
a2369ed3 | 18049 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
18050 | { |
18051 | fputs (GLOBAL_ASM_OP, stream); | |
18052 | RS6000_OUTPUT_BASENAME (stream, name); | |
18053 | putc ('\n', stream); | |
18054 | } | |
18055 | ||
d6b5193b RS |
18056 | /* A get_unnamed_decl callback, used for read-only sections. PTR |
18057 | points to the section string variable. */ | |
18058 | ||
18059 | static void | |
18060 | rs6000_xcoff_output_readonly_section_asm_op (const void *directive) | |
18061 | { | |
18062 | fprintf (asm_out_file, "\t.csect %s[RO],3\n", | |
18063 | *(const char *const *) directive); | |
18064 | } | |
18065 | ||
18066 | /* Likewise for read-write sections. */ | |
18067 | ||
18068 | static void | |
18069 | rs6000_xcoff_output_readwrite_section_asm_op (const void *directive) | |
18070 | { | |
18071 | fprintf (asm_out_file, "\t.csect %s[RW],3\n", | |
18072 | *(const char *const *) directive); | |
18073 | } | |
18074 | ||
18075 | /* A get_unnamed_section callback, used for switching to toc_section. */ | |
18076 | ||
18077 | static void | |
18078 | rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
18079 | { | |
18080 | if (TARGET_MINIMAL_TOC) | |
18081 | { | |
18082 | /* toc_section is always selected at least once from | |
18083 | rs6000_xcoff_file_start, so this is guaranteed to | |
18084 | always be defined once and only once in each file. */ | |
18085 | if (!toc_initialized) | |
18086 | { | |
18087 | fputs ("\t.toc\nLCTOC..1:\n", asm_out_file); | |
18088 | fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file); | |
18089 | toc_initialized = 1; | |
18090 | } | |
18091 | fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n", | |
18092 | (TARGET_32BIT ? "" : ",3")); | |
18093 | } | |
18094 | else | |
18095 | fputs ("\t.toc\n", asm_out_file); | |
18096 | } | |
18097 | ||
18098 | /* Implement TARGET_ASM_INIT_SECTIONS. */ | |
18099 | ||
18100 | static void | |
18101 | rs6000_xcoff_asm_init_sections (void) | |
18102 | { | |
18103 | read_only_data_section | |
18104 | = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op, | |
18105 | &xcoff_read_only_section_name); | |
18106 | ||
18107 | private_data_section | |
18108 | = get_unnamed_section (SECTION_WRITE, | |
18109 | rs6000_xcoff_output_readwrite_section_asm_op, | |
18110 | &xcoff_private_data_section_name); | |
18111 | ||
18112 | read_only_private_data_section | |
18113 | = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op, | |
18114 | &xcoff_private_data_section_name); | |
18115 | ||
18116 | toc_section | |
18117 | = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL); | |
18118 | ||
18119 | readonly_data_section = read_only_data_section; | |
18120 | exception_section = data_section; | |
18121 | } | |
18122 | ||
b275d088 | 18123 | static void |
c18a5b6c MM |
18124 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags, |
18125 | tree decl ATTRIBUTE_UNUSED) | |
7c262518 | 18126 | { |
0e5dbd9b DE |
18127 | int smclass; |
18128 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
18129 | ||
18130 | if (flags & SECTION_CODE) | |
18131 | smclass = 0; | |
18132 | else if (flags & SECTION_WRITE) | |
18133 | smclass = 2; | |
18134 | else | |
18135 | smclass = 1; | |
18136 | ||
5b5198f7 | 18137 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 18138 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 18139 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 18140 | } |
ae46c4e0 | 18141 | |
d6b5193b | 18142 | static section * |
f676971a | 18143 | rs6000_xcoff_select_section (tree decl, int reloc, |
c4ad648e | 18144 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
ae46c4e0 | 18145 | { |
5add3202 | 18146 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 18147 | { |
0e5dbd9b | 18148 | if (TREE_PUBLIC (decl)) |
d6b5193b | 18149 | return read_only_data_section; |
ae46c4e0 | 18150 | else |
d6b5193b | 18151 | return read_only_private_data_section; |
ae46c4e0 RH |
18152 | } |
18153 | else | |
18154 | { | |
0e5dbd9b | 18155 | if (TREE_PUBLIC (decl)) |
d6b5193b | 18156 | return data_section; |
ae46c4e0 | 18157 | else |
d6b5193b | 18158 | return private_data_section; |
ae46c4e0 RH |
18159 | } |
18160 | } | |
18161 | ||
18162 | static void | |
a2369ed3 | 18163 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
18164 | { |
18165 | const char *name; | |
ae46c4e0 | 18166 | |
5b5198f7 DE |
18167 | /* Use select_section for private and uninitialized data. */ |
18168 | if (!TREE_PUBLIC (decl) | |
18169 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
18170 | || DECL_INITIAL (decl) == NULL_TREE |
18171 | || DECL_INITIAL (decl) == error_mark_node | |
18172 | || (flag_zero_initialized_in_bss | |
18173 | && initializer_zerop (DECL_INITIAL (decl)))) | |
18174 | return; | |
18175 | ||
18176 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
18177 | name = (*targetm.strip_name_encoding) (name); | |
18178 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 18179 | } |
b64a1b53 | 18180 | |
fb49053f RH |
18181 | /* Select section for constant in constant pool. |
18182 | ||
18183 | On RS/6000, all constants are in the private read-only data area. | |
18184 | However, if this is being placed in the TOC it must be output as a | |
18185 | toc entry. */ | |
18186 | ||
d6b5193b | 18187 | static section * |
f676971a | 18188 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
c4ad648e | 18189 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
b64a1b53 RH |
18190 | { |
18191 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
d6b5193b | 18192 | return toc_section; |
b64a1b53 | 18193 | else |
d6b5193b | 18194 | return read_only_private_data_section; |
b64a1b53 | 18195 | } |
772c5265 RH |
18196 | |
18197 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
18198 | ||
18199 | static const char * | |
a2369ed3 | 18200 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
18201 | { |
18202 | size_t len; | |
18203 | if (*name == '*') | |
18204 | name++; | |
18205 | len = strlen (name); | |
18206 | if (name[len - 1] == ']') | |
18207 | return ggc_alloc_string (name, len - 4); | |
18208 | else | |
18209 | return name; | |
18210 | } | |
18211 | ||
5add3202 DE |
18212 | /* Section attributes. AIX is always PIC. */ |
18213 | ||
18214 | static unsigned int | |
a2369ed3 | 18215 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 18216 | { |
5b5198f7 DE |
18217 | unsigned int align; |
18218 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
18219 | ||
18220 | /* Align to at least UNIT size. */ | |
18221 | if (flags & SECTION_CODE) | |
18222 | align = MIN_UNITS_PER_WORD; | |
18223 | else | |
18224 | /* Increase alignment of large objects if not already stricter. */ | |
18225 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
18226 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
18227 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
18228 | ||
18229 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 18230 | } |
a5fe455b | 18231 | |
1bc7c5b6 ZW |
18232 | /* Output at beginning of assembler file. |
18233 | ||
18234 | Initialize the section names for the RS/6000 at this point. | |
18235 | ||
18236 | Specify filename, including full path, to assembler. | |
18237 | ||
18238 | We want to go into the TOC section so at least one .toc will be emitted. | |
18239 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
18240 | [RW] section emitted. | |
18241 | ||
18242 | Finally, declare mcount when profiling to make the assembler happy. */ | |
18243 | ||
18244 | static void | |
863d938c | 18245 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
18246 | { |
18247 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
18248 | main_input_filename, ".bss_"); | |
18249 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
18250 | main_input_filename, ".rw_"); | |
18251 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
18252 | main_input_filename, ".ro_"); | |
18253 | ||
18254 | fputs ("\t.file\t", asm_out_file); | |
18255 | output_quoted_string (asm_out_file, main_input_filename); | |
18256 | fputc ('\n', asm_out_file); | |
1bc7c5b6 | 18257 | if (write_symbols != NO_DEBUG) |
d6b5193b RS |
18258 | switch_to_section (private_data_section); |
18259 | switch_to_section (text_section); | |
1bc7c5b6 ZW |
18260 | if (profile_flag) |
18261 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
18262 | rs6000_file_start (); | |
18263 | } | |
18264 | ||
a5fe455b ZW |
18265 | /* Output at end of assembler file. |
18266 | On the RS/6000, referencing data should automatically pull in text. */ | |
18267 | ||
18268 | static void | |
863d938c | 18269 | rs6000_xcoff_file_end (void) |
a5fe455b | 18270 | { |
d6b5193b | 18271 | switch_to_section (text_section); |
a5fe455b | 18272 | fputs ("_section_.text:\n", asm_out_file); |
d6b5193b | 18273 | switch_to_section (data_section); |
a5fe455b ZW |
18274 | fputs (TARGET_32BIT |
18275 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
18276 | asm_out_file); | |
18277 | } | |
f1384257 | 18278 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 18279 | |
3c50106f RH |
18280 | /* Compute a (partial) cost for rtx X. Return true if the complete |
18281 | cost has been computed, and false if subexpressions should be | |
18282 | scanned. In either case, *TOTAL contains the cost result. */ | |
18283 | ||
18284 | static bool | |
1494c534 | 18285 | rs6000_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f | 18286 | { |
f0517163 RS |
18287 | enum machine_mode mode = GET_MODE (x); |
18288 | ||
3c50106f RH |
18289 | switch (code) |
18290 | { | |
30a555d9 | 18291 | /* On the RS/6000, if it is valid in the insn, it is free. */ |
3c50106f | 18292 | case CONST_INT: |
066cd967 DE |
18293 | if (((outer_code == SET |
18294 | || outer_code == PLUS | |
18295 | || outer_code == MINUS) | |
18296 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
18297 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))) | |
066cd967 DE |
18298 | || (outer_code == AND |
18299 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
22e54023 DE |
18300 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), |
18301 | mode == SImode ? 'L' : 'J')) | |
1990cd79 AM |
18302 | || mask_operand (x, mode) |
18303 | || (mode == DImode | |
18304 | && mask64_operand (x, DImode)))) | |
22e54023 DE |
18305 | || ((outer_code == IOR || outer_code == XOR) |
18306 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
18307 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), | |
18308 | mode == SImode ? 'L' : 'J')))) | |
066cd967 DE |
18309 | || outer_code == ASHIFT |
18310 | || outer_code == ASHIFTRT | |
18311 | || outer_code == LSHIFTRT | |
18312 | || outer_code == ROTATE | |
18313 | || outer_code == ROTATERT | |
d5861a7a | 18314 | || outer_code == ZERO_EXTRACT |
066cd967 DE |
18315 | || (outer_code == MULT |
18316 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
22e54023 DE |
18317 | || ((outer_code == DIV || outer_code == UDIV |
18318 | || outer_code == MOD || outer_code == UMOD) | |
18319 | && exact_log2 (INTVAL (x)) >= 0) | |
066cd967 DE |
18320 | || (outer_code == COMPARE |
18321 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
22e54023 DE |
18322 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K'))) |
18323 | || (outer_code == EQ | |
18324 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
18325 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
18326 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), | |
18327 | mode == SImode ? 'L' : 'J')))) | |
18328 | || (outer_code == GTU | |
18329 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
18330 | || (outer_code == LTU | |
18331 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P'))) | |
066cd967 DE |
18332 | { |
18333 | *total = 0; | |
18334 | return true; | |
18335 | } | |
18336 | else if ((outer_code == PLUS | |
4ae234b0 | 18337 | && reg_or_add_cint_operand (x, VOIDmode)) |
066cd967 | 18338 | || (outer_code == MINUS |
4ae234b0 | 18339 | && reg_or_sub_cint_operand (x, VOIDmode)) |
066cd967 DE |
18340 | || ((outer_code == SET |
18341 | || outer_code == IOR | |
18342 | || outer_code == XOR) | |
18343 | && (INTVAL (x) | |
18344 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0)) | |
18345 | { | |
18346 | *total = COSTS_N_INSNS (1); | |
18347 | return true; | |
18348 | } | |
18349 | /* FALLTHRU */ | |
18350 | ||
18351 | case CONST_DOUBLE: | |
18352 | if (mode == DImode | |
18353 | && ((outer_code == AND | |
18354 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
18355 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L') | |
1990cd79 AM |
18356 | || mask_operand (x, DImode) |
18357 | || mask64_operand (x, DImode))) | |
066cd967 DE |
18358 | || ((outer_code == IOR || outer_code == XOR) |
18359 | && CONST_DOUBLE_HIGH (x) == 0 | |
18360 | && (CONST_DOUBLE_LOW (x) | |
18361 | & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0))) | |
18362 | { | |
18363 | *total = 0; | |
18364 | return true; | |
18365 | } | |
18366 | else if (mode == DImode | |
18367 | && (outer_code == SET | |
18368 | || outer_code == IOR | |
18369 | || outer_code == XOR) | |
18370 | && CONST_DOUBLE_HIGH (x) == 0) | |
18371 | { | |
18372 | *total = COSTS_N_INSNS (1); | |
18373 | return true; | |
18374 | } | |
18375 | /* FALLTHRU */ | |
18376 | ||
3c50106f | 18377 | case CONST: |
066cd967 | 18378 | case HIGH: |
3c50106f | 18379 | case SYMBOL_REF: |
066cd967 DE |
18380 | case MEM: |
18381 | /* When optimizing for size, MEM should be slightly more expensive | |
18382 | than generating address, e.g., (plus (reg) (const)). | |
c112cf2b | 18383 | L1 cache latency is about two instructions. */ |
066cd967 | 18384 | *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); |
3c50106f RH |
18385 | return true; |
18386 | ||
30a555d9 DE |
18387 | case LABEL_REF: |
18388 | *total = 0; | |
18389 | return true; | |
18390 | ||
3c50106f | 18391 | case PLUS: |
f0517163 | 18392 | if (mode == DFmode) |
066cd967 DE |
18393 | { |
18394 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
18395 | { | |
18396 | /* FNMA accounted in outer NEG. */ | |
18397 | if (outer_code == NEG) | |
18398 | *total = rs6000_cost->dmul - rs6000_cost->fp; | |
18399 | else | |
18400 | *total = rs6000_cost->dmul; | |
18401 | } | |
18402 | else | |
18403 | *total = rs6000_cost->fp; | |
18404 | } | |
f0517163 | 18405 | else if (mode == SFmode) |
066cd967 DE |
18406 | { |
18407 | /* FNMA accounted in outer NEG. */ | |
18408 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
18409 | *total = 0; | |
18410 | else | |
18411 | *total = rs6000_cost->fp; | |
18412 | } | |
f0517163 | 18413 | else |
066cd967 DE |
18414 | *total = COSTS_N_INSNS (1); |
18415 | return false; | |
3c50106f | 18416 | |
52190329 | 18417 | case MINUS: |
f0517163 | 18418 | if (mode == DFmode) |
066cd967 DE |
18419 | { |
18420 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
18421 | { | |
18422 | /* FNMA accounted in outer NEG. */ | |
18423 | if (outer_code == NEG) | |
18424 | *total = 0; | |
18425 | else | |
18426 | *total = rs6000_cost->dmul; | |
18427 | } | |
18428 | else | |
18429 | *total = rs6000_cost->fp; | |
18430 | } | |
f0517163 | 18431 | else if (mode == SFmode) |
066cd967 DE |
18432 | { |
18433 | /* FNMA accounted in outer NEG. */ | |
18434 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
18435 | *total = 0; | |
18436 | else | |
18437 | *total = rs6000_cost->fp; | |
18438 | } | |
f0517163 | 18439 | else |
c4ad648e | 18440 | *total = COSTS_N_INSNS (1); |
066cd967 | 18441 | return false; |
3c50106f RH |
18442 | |
18443 | case MULT: | |
c9dbf840 DE |
18444 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
18445 | && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I')) | |
3c50106f | 18446 | { |
8b897cfa RS |
18447 | if (INTVAL (XEXP (x, 1)) >= -256 |
18448 | && INTVAL (XEXP (x, 1)) <= 255) | |
06a67bdd | 18449 | *total = rs6000_cost->mulsi_const9; |
8b897cfa | 18450 | else |
06a67bdd | 18451 | *total = rs6000_cost->mulsi_const; |
3c50106f | 18452 | } |
066cd967 DE |
18453 | /* FMA accounted in outer PLUS/MINUS. */ |
18454 | else if ((mode == DFmode || mode == SFmode) | |
18455 | && (outer_code == PLUS || outer_code == MINUS)) | |
18456 | *total = 0; | |
f0517163 | 18457 | else if (mode == DFmode) |
06a67bdd | 18458 | *total = rs6000_cost->dmul; |
f0517163 | 18459 | else if (mode == SFmode) |
06a67bdd | 18460 | *total = rs6000_cost->fp; |
f0517163 | 18461 | else if (mode == DImode) |
06a67bdd | 18462 | *total = rs6000_cost->muldi; |
8b897cfa | 18463 | else |
06a67bdd | 18464 | *total = rs6000_cost->mulsi; |
066cd967 | 18465 | return false; |
3c50106f RH |
18466 | |
18467 | case DIV: | |
18468 | case MOD: | |
f0517163 RS |
18469 | if (FLOAT_MODE_P (mode)) |
18470 | { | |
06a67bdd RS |
18471 | *total = mode == DFmode ? rs6000_cost->ddiv |
18472 | : rs6000_cost->sdiv; | |
066cd967 | 18473 | return false; |
f0517163 | 18474 | } |
5efb1046 | 18475 | /* FALLTHRU */ |
3c50106f RH |
18476 | |
18477 | case UDIV: | |
18478 | case UMOD: | |
627b6fe2 DJ |
18479 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
18480 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
18481 | { | |
18482 | if (code == DIV || code == MOD) | |
18483 | /* Shift, addze */ | |
18484 | *total = COSTS_N_INSNS (2); | |
18485 | else | |
18486 | /* Shift */ | |
18487 | *total = COSTS_N_INSNS (1); | |
18488 | } | |
c4ad648e | 18489 | else |
627b6fe2 DJ |
18490 | { |
18491 | if (GET_MODE (XEXP (x, 1)) == DImode) | |
18492 | *total = rs6000_cost->divdi; | |
18493 | else | |
18494 | *total = rs6000_cost->divsi; | |
18495 | } | |
18496 | /* Add in shift and subtract for MOD. */ | |
18497 | if (code == MOD || code == UMOD) | |
18498 | *total += COSTS_N_INSNS (2); | |
066cd967 | 18499 | return false; |
3c50106f RH |
18500 | |
18501 | case FFS: | |
18502 | *total = COSTS_N_INSNS (4); | |
066cd967 | 18503 | return false; |
3c50106f | 18504 | |
06a67bdd | 18505 | case NOT: |
066cd967 DE |
18506 | if (outer_code == AND || outer_code == IOR || outer_code == XOR) |
18507 | { | |
18508 | *total = 0; | |
18509 | return false; | |
18510 | } | |
18511 | /* FALLTHRU */ | |
18512 | ||
18513 | case AND: | |
18514 | case IOR: | |
18515 | case XOR: | |
d5861a7a DE |
18516 | case ZERO_EXTRACT: |
18517 | *total = COSTS_N_INSNS (1); | |
18518 | return false; | |
18519 | ||
066cd967 DE |
18520 | case ASHIFT: |
18521 | case ASHIFTRT: | |
18522 | case LSHIFTRT: | |
18523 | case ROTATE: | |
18524 | case ROTATERT: | |
d5861a7a | 18525 | /* Handle mul_highpart. */ |
066cd967 DE |
18526 | if (outer_code == TRUNCATE |
18527 | && GET_CODE (XEXP (x, 0)) == MULT) | |
18528 | { | |
18529 | if (mode == DImode) | |
18530 | *total = rs6000_cost->muldi; | |
18531 | else | |
18532 | *total = rs6000_cost->mulsi; | |
18533 | return true; | |
18534 | } | |
d5861a7a DE |
18535 | else if (outer_code == AND) |
18536 | *total = 0; | |
18537 | else | |
18538 | *total = COSTS_N_INSNS (1); | |
18539 | return false; | |
18540 | ||
18541 | case SIGN_EXTEND: | |
18542 | case ZERO_EXTEND: | |
18543 | if (GET_CODE (XEXP (x, 0)) == MEM) | |
18544 | *total = 0; | |
18545 | else | |
18546 | *total = COSTS_N_INSNS (1); | |
066cd967 | 18547 | return false; |
06a67bdd | 18548 | |
066cd967 DE |
18549 | case COMPARE: |
18550 | case NEG: | |
18551 | case ABS: | |
18552 | if (!FLOAT_MODE_P (mode)) | |
18553 | { | |
18554 | *total = COSTS_N_INSNS (1); | |
18555 | return false; | |
18556 | } | |
18557 | /* FALLTHRU */ | |
18558 | ||
18559 | case FLOAT: | |
18560 | case UNSIGNED_FLOAT: | |
18561 | case FIX: | |
18562 | case UNSIGNED_FIX: | |
06a67bdd RS |
18563 | case FLOAT_TRUNCATE: |
18564 | *total = rs6000_cost->fp; | |
066cd967 | 18565 | return false; |
06a67bdd | 18566 | |
a2af5043 DJ |
18567 | case FLOAT_EXTEND: |
18568 | if (mode == DFmode) | |
18569 | *total = 0; | |
18570 | else | |
18571 | *total = rs6000_cost->fp; | |
18572 | return false; | |
18573 | ||
06a67bdd RS |
18574 | case UNSPEC: |
18575 | switch (XINT (x, 1)) | |
18576 | { | |
18577 | case UNSPEC_FRSP: | |
18578 | *total = rs6000_cost->fp; | |
18579 | return true; | |
18580 | ||
18581 | default: | |
18582 | break; | |
18583 | } | |
18584 | break; | |
18585 | ||
18586 | case CALL: | |
18587 | case IF_THEN_ELSE: | |
18588 | if (optimize_size) | |
18589 | { | |
18590 | *total = COSTS_N_INSNS (1); | |
18591 | return true; | |
18592 | } | |
066cd967 DE |
18593 | else if (FLOAT_MODE_P (mode) |
18594 | && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS) | |
18595 | { | |
18596 | *total = rs6000_cost->fp; | |
18597 | return false; | |
18598 | } | |
06a67bdd RS |
18599 | break; |
18600 | ||
c0600ecd DE |
18601 | case EQ: |
18602 | case GTU: | |
18603 | case LTU: | |
22e54023 DE |
18604 | /* Carry bit requires mode == Pmode. |
18605 | NEG or PLUS already counted so only add one. */ | |
18606 | if (mode == Pmode | |
18607 | && (outer_code == NEG || outer_code == PLUS)) | |
c0600ecd | 18608 | { |
22e54023 DE |
18609 | *total = COSTS_N_INSNS (1); |
18610 | return true; | |
18611 | } | |
18612 | if (outer_code == SET) | |
18613 | { | |
18614 | if (XEXP (x, 1) == const0_rtx) | |
c0600ecd | 18615 | { |
22e54023 | 18616 | *total = COSTS_N_INSNS (2); |
c0600ecd | 18617 | return true; |
c0600ecd | 18618 | } |
22e54023 DE |
18619 | else if (mode == Pmode) |
18620 | { | |
18621 | *total = COSTS_N_INSNS (3); | |
18622 | return false; | |
18623 | } | |
18624 | } | |
18625 | /* FALLTHRU */ | |
18626 | ||
18627 | case GT: | |
18628 | case LT: | |
18629 | case UNORDERED: | |
18630 | if (outer_code == SET && (XEXP (x, 1) == const0_rtx)) | |
18631 | { | |
18632 | *total = COSTS_N_INSNS (2); | |
18633 | return true; | |
c0600ecd | 18634 | } |
22e54023 DE |
18635 | /* CC COMPARE. */ |
18636 | if (outer_code == COMPARE) | |
18637 | { | |
18638 | *total = 0; | |
18639 | return true; | |
18640 | } | |
18641 | break; | |
c0600ecd | 18642 | |
3c50106f | 18643 | default: |
06a67bdd | 18644 | break; |
3c50106f | 18645 | } |
06a67bdd RS |
18646 | |
18647 | return false; | |
3c50106f RH |
18648 | } |
18649 | ||
34bb030a DE |
18650 | /* A C expression returning the cost of moving data from a register of class |
18651 | CLASS1 to one of CLASS2. */ | |
18652 | ||
18653 | int | |
f676971a | 18654 | rs6000_register_move_cost (enum machine_mode mode, |
a2369ed3 | 18655 | enum reg_class from, enum reg_class to) |
34bb030a DE |
18656 | { |
18657 | /* Moves from/to GENERAL_REGS. */ | |
18658 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
18659 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
18660 | { | |
18661 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
18662 | from = to; | |
18663 | ||
18664 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
18665 | return (rs6000_memory_move_cost (mode, from, 0) | |
18666 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
18667 | ||
c4ad648e AM |
18668 | /* It's more expensive to move CR_REGS than CR0_REGS because of the |
18669 | shift. */ | |
34bb030a DE |
18670 | else if (from == CR_REGS) |
18671 | return 4; | |
18672 | ||
18673 | else | |
c4ad648e | 18674 | /* A move will cost one instruction per GPR moved. */ |
c8b622ff | 18675 | return 2 * hard_regno_nregs[0][mode]; |
34bb030a DE |
18676 | } |
18677 | ||
c4ad648e | 18678 | /* Moving between two similar registers is just one instruction. */ |
34bb030a DE |
18679 | else if (reg_classes_intersect_p (to, from)) |
18680 | return mode == TFmode ? 4 : 2; | |
18681 | ||
c4ad648e | 18682 | /* Everything else has to go through GENERAL_REGS. */ |
34bb030a | 18683 | else |
f676971a | 18684 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) |
34bb030a DE |
18685 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); |
18686 | } | |
18687 | ||
18688 | /* A C expressions returning the cost of moving data of MODE from a register to | |
18689 | or from memory. */ | |
18690 | ||
18691 | int | |
f676971a | 18692 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, |
a2369ed3 | 18693 | int in ATTRIBUTE_UNUSED) |
34bb030a DE |
18694 | { |
18695 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
c8b622ff | 18696 | return 4 * hard_regno_nregs[0][mode]; |
34bb030a | 18697 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) |
c8b622ff | 18698 | return 4 * hard_regno_nregs[32][mode]; |
34bb030a | 18699 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) |
c8b622ff | 18700 | return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode]; |
34bb030a DE |
18701 | else |
18702 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
18703 | } | |
18704 | ||
ef765ea9 DE |
18705 | /* Newton-Raphson approximation of single-precision floating point divide n/d. |
18706 | Assumes no trapping math and finite arguments. */ | |
18707 | ||
18708 | void | |
18709 | rs6000_emit_swdivsf (rtx res, rtx n, rtx d) | |
18710 | { | |
18711 | rtx x0, e0, e1, y1, u0, v0, one; | |
18712 | ||
18713 | x0 = gen_reg_rtx (SFmode); | |
18714 | e0 = gen_reg_rtx (SFmode); | |
18715 | e1 = gen_reg_rtx (SFmode); | |
18716 | y1 = gen_reg_rtx (SFmode); | |
18717 | u0 = gen_reg_rtx (SFmode); | |
18718 | v0 = gen_reg_rtx (SFmode); | |
18719 | one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode)); | |
18720 | ||
18721 | /* x0 = 1./d estimate */ | |
18722 | emit_insn (gen_rtx_SET (VOIDmode, x0, | |
18723 | gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d), | |
18724 | UNSPEC_FRES))); | |
18725 | /* e0 = 1. - d * x0 */ | |
18726 | emit_insn (gen_rtx_SET (VOIDmode, e0, | |
18727 | gen_rtx_MINUS (SFmode, one, | |
18728 | gen_rtx_MULT (SFmode, d, x0)))); | |
18729 | /* e1 = e0 + e0 * e0 */ | |
18730 | emit_insn (gen_rtx_SET (VOIDmode, e1, | |
18731 | gen_rtx_PLUS (SFmode, | |
18732 | gen_rtx_MULT (SFmode, e0, e0), e0))); | |
18733 | /* y1 = x0 + e1 * x0 */ | |
18734 | emit_insn (gen_rtx_SET (VOIDmode, y1, | |
18735 | gen_rtx_PLUS (SFmode, | |
18736 | gen_rtx_MULT (SFmode, e1, x0), x0))); | |
18737 | /* u0 = n * y1 */ | |
18738 | emit_insn (gen_rtx_SET (VOIDmode, u0, | |
18739 | gen_rtx_MULT (SFmode, n, y1))); | |
18740 | /* v0 = n - d * u0 */ | |
18741 | emit_insn (gen_rtx_SET (VOIDmode, v0, | |
18742 | gen_rtx_MINUS (SFmode, n, | |
18743 | gen_rtx_MULT (SFmode, d, u0)))); | |
18744 | /* res = u0 + v0 * y1 */ | |
18745 | emit_insn (gen_rtx_SET (VOIDmode, res, | |
18746 | gen_rtx_PLUS (SFmode, | |
18747 | gen_rtx_MULT (SFmode, v0, y1), u0))); | |
18748 | } | |
18749 | ||
18750 | /* Newton-Raphson approximation of double-precision floating point divide n/d. | |
18751 | Assumes no trapping math and finite arguments. */ | |
18752 | ||
18753 | void | |
18754 | rs6000_emit_swdivdf (rtx res, rtx n, rtx d) | |
18755 | { | |
18756 | rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one; | |
18757 | ||
18758 | x0 = gen_reg_rtx (DFmode); | |
18759 | e0 = gen_reg_rtx (DFmode); | |
18760 | e1 = gen_reg_rtx (DFmode); | |
18761 | e2 = gen_reg_rtx (DFmode); | |
18762 | y1 = gen_reg_rtx (DFmode); | |
18763 | y2 = gen_reg_rtx (DFmode); | |
18764 | y3 = gen_reg_rtx (DFmode); | |
18765 | u0 = gen_reg_rtx (DFmode); | |
18766 | v0 = gen_reg_rtx (DFmode); | |
18767 | one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode)); | |
18768 | ||
18769 | /* x0 = 1./d estimate */ | |
18770 | emit_insn (gen_rtx_SET (VOIDmode, x0, | |
18771 | gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d), | |
18772 | UNSPEC_FRES))); | |
18773 | /* e0 = 1. - d * x0 */ | |
18774 | emit_insn (gen_rtx_SET (VOIDmode, e0, | |
18775 | gen_rtx_MINUS (DFmode, one, | |
18776 | gen_rtx_MULT (SFmode, d, x0)))); | |
18777 | /* y1 = x0 + e0 * x0 */ | |
18778 | emit_insn (gen_rtx_SET (VOIDmode, y1, | |
18779 | gen_rtx_PLUS (DFmode, | |
18780 | gen_rtx_MULT (DFmode, e0, x0), x0))); | |
18781 | /* e1 = e0 * e0 */ | |
18782 | emit_insn (gen_rtx_SET (VOIDmode, e1, | |
18783 | gen_rtx_MULT (DFmode, e0, e0))); | |
18784 | /* y2 = y1 + e1 * y1 */ | |
18785 | emit_insn (gen_rtx_SET (VOIDmode, y2, | |
18786 | gen_rtx_PLUS (DFmode, | |
18787 | gen_rtx_MULT (DFmode, e1, y1), y1))); | |
18788 | /* e2 = e1 * e1 */ | |
18789 | emit_insn (gen_rtx_SET (VOIDmode, e2, | |
18790 | gen_rtx_MULT (DFmode, e1, e1))); | |
18791 | /* y3 = y2 + e2 * y2 */ | |
18792 | emit_insn (gen_rtx_SET (VOIDmode, y3, | |
18793 | gen_rtx_PLUS (DFmode, | |
18794 | gen_rtx_MULT (DFmode, e2, y2), y2))); | |
18795 | /* u0 = n * y3 */ | |
18796 | emit_insn (gen_rtx_SET (VOIDmode, u0, | |
18797 | gen_rtx_MULT (DFmode, n, y3))); | |
18798 | /* v0 = n - d * u0 */ | |
18799 | emit_insn (gen_rtx_SET (VOIDmode, v0, | |
18800 | gen_rtx_MINUS (DFmode, n, | |
18801 | gen_rtx_MULT (DFmode, d, u0)))); | |
18802 | /* res = u0 + v0 * y3 */ | |
18803 | emit_insn (gen_rtx_SET (VOIDmode, res, | |
18804 | gen_rtx_PLUS (DFmode, | |
18805 | gen_rtx_MULT (DFmode, v0, y3), u0))); | |
18806 | } | |
18807 | ||
ded9bf77 AH |
18808 | /* Return an RTX representing where to find the function value of a |
18809 | function returning MODE. */ | |
18810 | static rtx | |
18811 | rs6000_complex_function_value (enum machine_mode mode) | |
18812 | { | |
18813 | unsigned int regno; | |
18814 | rtx r1, r2; | |
18815 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 18816 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 | 18817 | |
18f63bfa AH |
18818 | if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
18819 | regno = FP_ARG_RETURN; | |
354ed18f AH |
18820 | else |
18821 | { | |
18f63bfa | 18822 | regno = GP_ARG_RETURN; |
ded9bf77 | 18823 | |
18f63bfa AH |
18824 | /* 32-bit is OK since it'll go in r3/r4. */ |
18825 | if (TARGET_32BIT && inner_bytes >= 4) | |
ded9bf77 AH |
18826 | return gen_rtx_REG (mode, regno); |
18827 | } | |
18828 | ||
18f63bfa AH |
18829 | if (inner_bytes >= 8) |
18830 | return gen_rtx_REG (mode, regno); | |
18831 | ||
ded9bf77 AH |
18832 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
18833 | const0_rtx); | |
18834 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 18835 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
18836 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
18837 | } | |
18838 | ||
a6ebc39a AH |
18839 | /* Define how to find the value returned by a function. |
18840 | VALTYPE is the data type of the value (as a tree). | |
18841 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
18842 | otherwise, FUNC is 0. | |
18843 | ||
18844 | On the SPE, both FPs and vectors are returned in r3. | |
18845 | ||
18846 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
18847 | fp1, unless -msoft-float. */ | |
18848 | ||
18849 | rtx | |
18850 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
18851 | { | |
18852 | enum machine_mode mode; | |
2a8fa26c | 18853 | unsigned int regno; |
a6ebc39a | 18854 | |
594a51fe SS |
18855 | /* Special handling for structs in darwin64. */ |
18856 | if (rs6000_darwin64_abi | |
18857 | && TYPE_MODE (valtype) == BLKmode | |
0b5383eb DJ |
18858 | && TREE_CODE (valtype) == RECORD_TYPE |
18859 | && int_size_in_bytes (valtype) > 0) | |
594a51fe SS |
18860 | { |
18861 | CUMULATIVE_ARGS valcum; | |
18862 | rtx valret; | |
18863 | ||
0b5383eb | 18864 | valcum.words = 0; |
594a51fe SS |
18865 | valcum.fregno = FP_ARG_MIN_REG; |
18866 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
0b5383eb DJ |
18867 | /* Do a trial code generation as if this were going to be passed as |
18868 | an argument; if any part goes in memory, we return NULL. */ | |
18869 | valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true); | |
594a51fe SS |
18870 | if (valret) |
18871 | return valret; | |
18872 | /* Otherwise fall through to standard ABI rules. */ | |
18873 | } | |
18874 | ||
0e67400a FJ |
18875 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
18876 | { | |
18877 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
18878 | return gen_rtx_PARALLEL (DImode, | |
18879 | gen_rtvec (2, | |
18880 | gen_rtx_EXPR_LIST (VOIDmode, | |
18881 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
18882 | const0_rtx), | |
18883 | gen_rtx_EXPR_LIST (VOIDmode, | |
18884 | gen_rtx_REG (SImode, | |
18885 | GP_ARG_RETURN + 1), | |
18886 | GEN_INT (4)))); | |
18887 | } | |
0f086e42 FJ |
18888 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode) |
18889 | { | |
18890 | return gen_rtx_PARALLEL (DCmode, | |
18891 | gen_rtvec (4, | |
18892 | gen_rtx_EXPR_LIST (VOIDmode, | |
18893 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
18894 | const0_rtx), | |
18895 | gen_rtx_EXPR_LIST (VOIDmode, | |
18896 | gen_rtx_REG (SImode, | |
18897 | GP_ARG_RETURN + 1), | |
18898 | GEN_INT (4)), | |
18899 | gen_rtx_EXPR_LIST (VOIDmode, | |
18900 | gen_rtx_REG (SImode, | |
18901 | GP_ARG_RETURN + 2), | |
18902 | GEN_INT (8)), | |
18903 | gen_rtx_EXPR_LIST (VOIDmode, | |
18904 | gen_rtx_REG (SImode, | |
18905 | GP_ARG_RETURN + 3), | |
18906 | GEN_INT (12)))); | |
18907 | } | |
a6ebc39a AH |
18908 | if ((INTEGRAL_TYPE_P (valtype) |
18909 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
18910 | || POINTER_TYPE_P (valtype)) | |
b78d48dd | 18911 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a AH |
18912 | else |
18913 | mode = TYPE_MODE (valtype); | |
18914 | ||
4ed78545 | 18915 | if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) |
2a8fa26c | 18916 | regno = FP_ARG_RETURN; |
ded9bf77 | 18917 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
42ba5130 | 18918 | && targetm.calls.split_complex_arg) |
ded9bf77 | 18919 | return rs6000_complex_function_value (mode); |
44688022 | 18920 | else if (TREE_CODE (valtype) == VECTOR_TYPE |
d0b2079e | 18921 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI |
23ba09f0 | 18922 | && ALTIVEC_VECTOR_MODE (mode)) |
a6ebc39a | 18923 | regno = ALTIVEC_ARG_RETURN; |
18f63bfa AH |
18924 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
18925 | && (mode == DFmode || mode == DCmode)) | |
18926 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
a6ebc39a AH |
18927 | else |
18928 | regno = GP_ARG_RETURN; | |
18929 | ||
18930 | return gen_rtx_REG (mode, regno); | |
18931 | } | |
18932 | ||
ded9bf77 AH |
18933 | /* Define how to find the value returned by a library function |
18934 | assuming the value has mode MODE. */ | |
18935 | rtx | |
18936 | rs6000_libcall_value (enum machine_mode mode) | |
18937 | { | |
18938 | unsigned int regno; | |
18939 | ||
2e6c9641 FJ |
18940 | if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode) |
18941 | { | |
18942 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
18943 | return gen_rtx_PARALLEL (DImode, | |
18944 | gen_rtvec (2, | |
18945 | gen_rtx_EXPR_LIST (VOIDmode, | |
18946 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
18947 | const0_rtx), | |
18948 | gen_rtx_EXPR_LIST (VOIDmode, | |
18949 | gen_rtx_REG (SImode, | |
18950 | GP_ARG_RETURN + 1), | |
18951 | GEN_INT (4)))); | |
18952 | } | |
18953 | ||
ebb109ad | 18954 | if (SCALAR_FLOAT_MODE_P (mode) |
ded9bf77 AH |
18955 | && TARGET_HARD_FLOAT && TARGET_FPRS) |
18956 | regno = FP_ARG_RETURN; | |
44688022 AM |
18957 | else if (ALTIVEC_VECTOR_MODE (mode) |
18958 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
ded9bf77 | 18959 | regno = ALTIVEC_ARG_RETURN; |
42ba5130 | 18960 | else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) |
ded9bf77 | 18961 | return rs6000_complex_function_value (mode); |
18f63bfa AH |
18962 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
18963 | && (mode == DFmode || mode == DCmode)) | |
18964 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
ded9bf77 AH |
18965 | else |
18966 | regno = GP_ARG_RETURN; | |
18967 | ||
18968 | return gen_rtx_REG (mode, regno); | |
18969 | } | |
18970 | ||
d1d0c603 JJ |
18971 | /* Define the offset between two registers, FROM to be eliminated and its |
18972 | replacement TO, at the start of a routine. */ | |
18973 | HOST_WIDE_INT | |
18974 | rs6000_initial_elimination_offset (int from, int to) | |
18975 | { | |
18976 | rs6000_stack_t *info = rs6000_stack_info (); | |
18977 | HOST_WIDE_INT offset; | |
18978 | ||
7d5175e1 | 18979 | if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
d1d0c603 | 18980 | offset = info->push_p ? 0 : -info->total_size; |
7d5175e1 JJ |
18981 | else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
18982 | { | |
18983 | offset = info->push_p ? 0 : -info->total_size; | |
18984 | if (FRAME_GROWS_DOWNWARD) | |
5b667039 | 18985 | offset += info->fixed_size + info->vars_size + info->parm_size; |
7d5175e1 JJ |
18986 | } |
18987 | else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
18988 | offset = FRAME_GROWS_DOWNWARD | |
5b667039 | 18989 | ? info->fixed_size + info->vars_size + info->parm_size |
7d5175e1 JJ |
18990 | : 0; |
18991 | else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
d1d0c603 JJ |
18992 | offset = info->total_size; |
18993 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
18994 | offset = info->push_p ? info->total_size : 0; | |
18995 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
18996 | offset = 0; | |
18997 | else | |
37409796 | 18998 | gcc_unreachable (); |
d1d0c603 JJ |
18999 | |
19000 | return offset; | |
19001 | } | |
19002 | ||
58646b77 | 19003 | /* Return true if TYPE is a SPE or AltiVec opaque type. */ |
62e1dfcf | 19004 | |
c8e4f0e9 | 19005 | static bool |
58646b77 | 19006 | rs6000_is_opaque_type (tree type) |
62e1dfcf | 19007 | { |
58646b77 | 19008 | return (type == opaque_V2SI_type_node |
2abe3e28 | 19009 | || type == opaque_V2SF_type_node |
58646b77 PB |
19010 | || type == opaque_p_V2SI_type_node |
19011 | || type == opaque_V4SI_type_node); | |
62e1dfcf NC |
19012 | } |
19013 | ||
96714395 | 19014 | static rtx |
a2369ed3 | 19015 | rs6000_dwarf_register_span (rtx reg) |
96714395 AH |
19016 | { |
19017 | unsigned regno; | |
19018 | ||
4d4cbc0e AH |
19019 | if (TARGET_SPE |
19020 | && (SPE_VECTOR_MODE (GET_MODE (reg)) | |
19021 | || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode))) | |
19022 | ; | |
19023 | else | |
96714395 AH |
19024 | return NULL_RTX; |
19025 | ||
19026 | regno = REGNO (reg); | |
19027 | ||
19028 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
19029 | This is a way of distinguishing r0 in 32-bits from r0 in | |
19030 | 64-bits. */ | |
19031 | return | |
19032 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
19033 | BYTES_BIG_ENDIAN |
19034 | ? gen_rtvec (2, | |
19035 | gen_rtx_REG (SImode, regno + 1200), | |
19036 | gen_rtx_REG (SImode, regno)) | |
19037 | : gen_rtvec (2, | |
19038 | gen_rtx_REG (SImode, regno), | |
19039 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
19040 | } |
19041 | ||
93c9d1ba AM |
19042 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
19043 | ||
19044 | unsigned int | |
19045 | rs6000_dbx_register_number (unsigned int regno) | |
19046 | { | |
19047 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
19048 | return regno; | |
19049 | if (regno == MQ_REGNO) | |
19050 | return 100; | |
19051 | if (regno == LINK_REGISTER_REGNUM) | |
19052 | return 108; | |
19053 | if (regno == COUNT_REGISTER_REGNUM) | |
19054 | return 109; | |
19055 | if (CR_REGNO_P (regno)) | |
19056 | return regno - CR0_REGNO + 86; | |
19057 | if (regno == XER_REGNO) | |
19058 | return 101; | |
19059 | if (ALTIVEC_REGNO_P (regno)) | |
19060 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
19061 | if (regno == VRSAVE_REGNO) | |
19062 | return 356; | |
19063 | if (regno == VSCR_REGNO) | |
19064 | return 67; | |
19065 | if (regno == SPE_ACC_REGNO) | |
19066 | return 99; | |
19067 | if (regno == SPEFSCR_REGNO) | |
19068 | return 612; | |
19069 | /* SPE high reg number. We get these values of regno from | |
19070 | rs6000_dwarf_register_span. */ | |
37409796 NS |
19071 | gcc_assert (regno >= 1200 && regno < 1232); |
19072 | return regno; | |
93c9d1ba AM |
19073 | } |
19074 | ||
93f90be6 | 19075 | /* target hook eh_return_filter_mode */ |
f676971a | 19076 | static enum machine_mode |
93f90be6 FJ |
19077 | rs6000_eh_return_filter_mode (void) |
19078 | { | |
19079 | return TARGET_32BIT ? SImode : word_mode; | |
19080 | } | |
19081 | ||
f676971a EC |
19082 | /* Target hook for vector_mode_supported_p. */ |
19083 | static bool | |
19084 | rs6000_vector_mode_supported_p (enum machine_mode mode) | |
19085 | { | |
19086 | ||
19087 | if (TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
19088 | return true; | |
19089 | ||
19090 | else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
19091 | return true; | |
19092 | ||
19093 | else | |
19094 | return false; | |
19095 | } | |
19096 | ||
bb8df8a6 EC |
19097 | /* Target hook for invalid_arg_for_unprototyped_fn. */ |
19098 | static const char * | |
4d3e6fae FJ |
19099 | invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val) |
19100 | { | |
19101 | return (!rs6000_darwin64_abi | |
19102 | && typelist == 0 | |
19103 | && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE | |
19104 | && (funcdecl == NULL_TREE | |
19105 | || (TREE_CODE (funcdecl) == FUNCTION_DECL | |
19106 | && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD))) | |
19107 | ? N_("AltiVec argument passed to unprototyped function") | |
19108 | : NULL; | |
19109 | } | |
19110 | ||
3aebbe5f JJ |
19111 | /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register |
19112 | setup by using __stack_chk_fail_local hidden function instead of | |
19113 | calling __stack_chk_fail directly. Otherwise it is better to call | |
19114 | __stack_chk_fail directly. */ | |
19115 | ||
19116 | static tree | |
19117 | rs6000_stack_protect_fail (void) | |
19118 | { | |
19119 | return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic) | |
19120 | ? default_hidden_stack_protect_fail () | |
19121 | : default_external_stack_protect_fail (); | |
19122 | } | |
19123 | ||
17211ab5 | 19124 | #include "gt-rs6000.h" |