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Commit | Line | Data |
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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
93c9d1ba | 3 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
cd3ce9b4 | 55 | #include "tree-gimple.h" |
1bc7c5b6 ZW |
56 | #if TARGET_XCOFF |
57 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
58 | #endif | |
9b30bae2 | 59 | |
7509c759 MM |
60 | #ifndef TARGET_NO_PROTOTYPE |
61 | #define TARGET_NO_PROTOTYPE 0 | |
62 | #endif | |
63 | ||
452a7d36 HP |
64 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
65 | #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e \ | |
66 | && !((n) & 1)) | |
d744e06e | 67 | |
9878760c RK |
68 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
69 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
70 | ||
d1d0c603 JJ |
71 | /* Structure used to define the rs6000 stack */ |
72 | typedef struct rs6000_stack { | |
73 | int first_gp_reg_save; /* first callee saved GP register used */ | |
74 | int first_fp_reg_save; /* first callee saved FP register used */ | |
75 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
76 | int lr_save_p; /* true if the link reg needs to be saved */ | |
77 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
78 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
79 | int toc_save_p; /* true if the TOC needs to be saved */ | |
80 | int push_p; /* true if we need to allocate stack space */ | |
81 | int calls_p; /* true if the function makes any calls */ | |
82 | enum rs6000_abi abi; /* which ABI to use */ | |
83 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
84 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
85 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
86 | int lr_save_offset; /* offset to save LR from initial SP */ | |
87 | int cr_save_offset; /* offset to save CR from initial SP */ | |
88 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
89 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
90 | int toc_save_offset; /* offset to save the TOC pointer */ | |
91 | int varargs_save_offset; /* offset to save the varargs registers */ | |
92 | int ehrd_offset; /* offset to EH return data */ | |
93 | int reg_size; /* register size (4 or 8) */ | |
94 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
95 | HOST_WIDE_INT vars_size; /* variable save area size */ | |
96 | int parm_size; /* outgoing parameter size */ | |
97 | int save_size; /* save area size */ | |
98 | int fixed_size; /* fixed size of stack frame */ | |
99 | int gp_size; /* size of saved GP registers */ | |
100 | int fp_size; /* size of saved FP registers */ | |
101 | int altivec_size; /* size of saved AltiVec registers */ | |
102 | int cr_size; /* size to hold CR if not in save_size */ | |
103 | int lr_size; /* size to hold LR if not in save_size */ | |
104 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ | |
105 | int altivec_padding_size; /* size of altivec alignment padding if | |
106 | not in save_size */ | |
107 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
108 | int spe_padding_size; | |
109 | int toc_size; /* size to hold TOC if not in save_size */ | |
110 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ | |
111 | int spe_64bit_regs_used; | |
112 | } rs6000_stack_t; | |
113 | ||
5248c961 RK |
114 | /* Target cpu type */ |
115 | ||
116 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
117 | struct rs6000_cpu_select rs6000_select[3] = |
118 | { | |
815cdc52 MM |
119 | /* switch name, tune arch */ |
120 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
121 | { (const char *)0, "-mcpu=", 1, 1 }, | |
122 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 123 | }; |
5248c961 | 124 | |
ec507f2d DE |
125 | /* Always emit branch hint bits. */ |
126 | static GTY(()) bool rs6000_always_hint; | |
127 | ||
128 | /* Schedule instructions for group formation. */ | |
129 | static GTY(()) bool rs6000_sched_groups; | |
130 | ||
79ae11c4 DN |
131 | /* Support adjust_priority scheduler hook |
132 | and -mprioritize-restricted-insns= option. */ | |
133 | const char *rs6000_sched_restricted_insns_priority_str; | |
134 | int rs6000_sched_restricted_insns_priority; | |
135 | ||
569fa502 DN |
136 | /* Support for -msched-costly-dep option. */ |
137 | const char *rs6000_sched_costly_dep_str; | |
138 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
139 | ||
cbe26ab8 DN |
140 | /* Support for -minsert-sched-nops option. */ |
141 | const char *rs6000_sched_insert_nops_str; | |
142 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
143 | ||
6fa3f289 ZW |
144 | /* Size of long double */ |
145 | const char *rs6000_long_double_size_string; | |
146 | int rs6000_long_double_type_size; | |
147 | ||
148 | /* Whether -mabi=altivec has appeared */ | |
149 | int rs6000_altivec_abi; | |
150 | ||
08b57fb3 AH |
151 | /* Whether VRSAVE instructions should be generated. */ |
152 | int rs6000_altivec_vrsave; | |
153 | ||
154 | /* String from -mvrsave= option. */ | |
155 | const char *rs6000_altivec_vrsave_string; | |
156 | ||
a3170dc6 AH |
157 | /* Nonzero if we want SPE ABI extensions. */ |
158 | int rs6000_spe_abi; | |
159 | ||
160 | /* Whether isel instructions should be generated. */ | |
161 | int rs6000_isel; | |
162 | ||
993f19a8 AH |
163 | /* Whether SPE simd instructions should be generated. */ |
164 | int rs6000_spe; | |
165 | ||
5da702b1 AH |
166 | /* Nonzero if floating point operations are done in the GPRs. */ |
167 | int rs6000_float_gprs = 0; | |
168 | ||
169 | /* String from -mfloat-gprs=. */ | |
170 | const char *rs6000_float_gprs_string; | |
a3170dc6 AH |
171 | |
172 | /* String from -misel=. */ | |
173 | const char *rs6000_isel_string; | |
174 | ||
993f19a8 AH |
175 | /* String from -mspe=. */ |
176 | const char *rs6000_spe_string; | |
177 | ||
a0ab749a | 178 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 179 | static GTY(()) int common_mode_defined; |
c81bebd7 | 180 | |
9878760c RK |
181 | /* Save information from a "cmpxx" operation until the branch or scc is |
182 | emitted. */ | |
9878760c RK |
183 | rtx rs6000_compare_op0, rs6000_compare_op1; |
184 | int rs6000_compare_fp_p; | |
874a0744 | 185 | |
874a0744 MM |
186 | /* Label number of label created for -mrelocatable, to call to so we can |
187 | get the address of the GOT section */ | |
188 | int rs6000_pic_labelno; | |
c81bebd7 | 189 | |
b91da81f | 190 | #ifdef USING_ELFOS_H |
c81bebd7 | 191 | /* Which abi to adhere to */ |
9739c90c | 192 | const char *rs6000_abi_name; |
d9407988 MM |
193 | |
194 | /* Semantics of the small data area */ | |
195 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
196 | ||
197 | /* Which small data model to use */ | |
815cdc52 | 198 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
199 | |
200 | /* Counter for labels which are to be placed in .fixup. */ | |
201 | int fixuplabelno = 0; | |
874a0744 | 202 | #endif |
4697a36c | 203 | |
c4501e62 JJ |
204 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
205 | int rs6000_tls_size = 32; | |
206 | const char *rs6000_tls_size_string; | |
207 | ||
b6c9286a MM |
208 | /* ABI enumeration available for subtarget to use. */ |
209 | enum rs6000_abi rs6000_current_abi; | |
210 | ||
0ac081f6 AH |
211 | /* ABI string from -mabi= option. */ |
212 | const char *rs6000_abi_string; | |
213 | ||
38c1f2d7 | 214 | /* Debug flags */ |
815cdc52 | 215 | const char *rs6000_debug_name; |
38c1f2d7 MM |
216 | int rs6000_debug_stack; /* debug stack applications */ |
217 | int rs6000_debug_arg; /* debug argument handling */ | |
218 | ||
0d1fbc8c AH |
219 | /* Value is TRUE if register/mode pair is accepatable. */ |
220 | bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; | |
221 | ||
6035d635 | 222 | /* Opaque types. */ |
2abe3e28 | 223 | static GTY(()) tree opaque_V2SI_type_node; |
2abe3e28 | 224 | static GTY(()) tree opaque_V2SF_type_node; |
6035d635 | 225 | static GTY(()) tree opaque_p_V2SI_type_node; |
4a5eab38 PB |
226 | static GTY(()) tree V16QI_type_node; |
227 | static GTY(()) tree V2SI_type_node; | |
228 | static GTY(()) tree V2SF_type_node; | |
229 | static GTY(()) tree V4HI_type_node; | |
230 | static GTY(()) tree V4SI_type_node; | |
231 | static GTY(()) tree V4SF_type_node; | |
232 | static GTY(()) tree V8HI_type_node; | |
233 | static GTY(()) tree unsigned_V16QI_type_node; | |
234 | static GTY(()) tree unsigned_V8HI_type_node; | |
235 | static GTY(()) tree unsigned_V4SI_type_node; | |
8bb418a3 ZL |
236 | static GTY(()) tree bool_char_type_node; /* __bool char */ |
237 | static GTY(()) tree bool_short_type_node; /* __bool short */ | |
238 | static GTY(()) tree bool_int_type_node; /* __bool int */ | |
239 | static GTY(()) tree pixel_type_node; /* __pixel */ | |
240 | static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */ | |
241 | static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */ | |
242 | static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */ | |
243 | static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */ | |
244 | ||
245 | int rs6000_warn_altivec_long = 1; /* On by default. */ | |
246 | const char *rs6000_warn_altivec_long_switch; | |
247 | ||
57ac7be9 AM |
248 | const char *rs6000_traceback_name; |
249 | static enum { | |
250 | traceback_default = 0, | |
251 | traceback_none, | |
252 | traceback_part, | |
253 | traceback_full | |
254 | } rs6000_traceback; | |
255 | ||
38c1f2d7 MM |
256 | /* Flag to say the TOC is initialized */ |
257 | int toc_initialized; | |
9ebbca7d | 258 | char toc_label_name[10]; |
38c1f2d7 | 259 | |
9ebbca7d | 260 | /* Alias set for saves and restores from the rs6000 stack. */ |
f103e34d | 261 | static GTY(()) int rs6000_sr_alias_set; |
c8023011 | 262 | |
a5c76ee6 ZW |
263 | /* Call distance, overridden by -mlongcall and #pragma longcall(1). |
264 | The only place that looks at this is rs6000_set_default_type_attributes; | |
265 | everywhere else should rely on the presence or absence of a longcall | |
266 | attribute on the function declaration. */ | |
267 | int rs6000_default_long_calls; | |
268 | const char *rs6000_longcall_switch; | |
269 | ||
a3c9585f KH |
270 | /* Control alignment for fields within structures. */ |
271 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
272 | const char *rs6000_alignment_string; |
273 | int rs6000_alignment_flags; | |
274 | ||
a3170dc6 AH |
275 | struct builtin_description |
276 | { | |
277 | /* mask is not const because we're going to alter it below. This | |
278 | nonsense will go away when we rewrite the -march infrastructure | |
279 | to give us more target flag bits. */ | |
280 | unsigned int mask; | |
281 | const enum insn_code icode; | |
282 | const char *const name; | |
283 | const enum rs6000_builtins code; | |
284 | }; | |
8b897cfa RS |
285 | \f |
286 | /* Target cpu costs. */ | |
287 | ||
288 | struct processor_costs { | |
289 | const int mulsi; /* cost of SImode multiplication. */ | |
290 | const int mulsi_const; /* cost of SImode multiplication by constant. */ | |
291 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
292 | const int muldi; /* cost of DImode multiplication. */ | |
293 | const int divsi; /* cost of SImode division. */ | |
294 | const int divdi; /* cost of DImode division. */ | |
f0517163 RS |
295 | const int fp; /* cost of simple SFmode and DFmode insns. */ |
296 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
297 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
298 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
8b897cfa RS |
299 | }; |
300 | ||
301 | const struct processor_costs *rs6000_cost; | |
302 | ||
303 | /* Processor costs (relative to an add) */ | |
304 | ||
305 | /* Instruction size costs on 32bit processors. */ | |
306 | static const | |
307 | struct processor_costs size32_cost = { | |
06a67bdd RS |
308 | COSTS_N_INSNS (1), /* mulsi */ |
309 | COSTS_N_INSNS (1), /* mulsi_const */ | |
310 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
311 | COSTS_N_INSNS (1), /* muldi */ | |
312 | COSTS_N_INSNS (1), /* divsi */ | |
313 | COSTS_N_INSNS (1), /* divdi */ | |
314 | COSTS_N_INSNS (1), /* fp */ | |
315 | COSTS_N_INSNS (1), /* dmul */ | |
316 | COSTS_N_INSNS (1), /* sdiv */ | |
317 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
318 | }; |
319 | ||
320 | /* Instruction size costs on 64bit processors. */ | |
321 | static const | |
322 | struct processor_costs size64_cost = { | |
06a67bdd RS |
323 | COSTS_N_INSNS (1), /* mulsi */ |
324 | COSTS_N_INSNS (1), /* mulsi_const */ | |
325 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
326 | COSTS_N_INSNS (1), /* muldi */ | |
327 | COSTS_N_INSNS (1), /* divsi */ | |
328 | COSTS_N_INSNS (1), /* divdi */ | |
329 | COSTS_N_INSNS (1), /* fp */ | |
330 | COSTS_N_INSNS (1), /* dmul */ | |
331 | COSTS_N_INSNS (1), /* sdiv */ | |
332 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
333 | }; |
334 | ||
335 | /* Instruction costs on RIOS1 processors. */ | |
336 | static const | |
337 | struct processor_costs rios1_cost = { | |
06a67bdd RS |
338 | COSTS_N_INSNS (5), /* mulsi */ |
339 | COSTS_N_INSNS (4), /* mulsi_const */ | |
340 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
341 | COSTS_N_INSNS (5), /* muldi */ | |
342 | COSTS_N_INSNS (19), /* divsi */ | |
343 | COSTS_N_INSNS (19), /* divdi */ | |
344 | COSTS_N_INSNS (2), /* fp */ | |
345 | COSTS_N_INSNS (2), /* dmul */ | |
346 | COSTS_N_INSNS (19), /* sdiv */ | |
347 | COSTS_N_INSNS (19), /* ddiv */ | |
8b897cfa RS |
348 | }; |
349 | ||
350 | /* Instruction costs on RIOS2 processors. */ | |
351 | static const | |
352 | struct processor_costs rios2_cost = { | |
06a67bdd RS |
353 | COSTS_N_INSNS (2), /* mulsi */ |
354 | COSTS_N_INSNS (2), /* mulsi_const */ | |
355 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
356 | COSTS_N_INSNS (2), /* muldi */ | |
357 | COSTS_N_INSNS (13), /* divsi */ | |
358 | COSTS_N_INSNS (13), /* divdi */ | |
359 | COSTS_N_INSNS (2), /* fp */ | |
360 | COSTS_N_INSNS (2), /* dmul */ | |
361 | COSTS_N_INSNS (17), /* sdiv */ | |
362 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
363 | }; |
364 | ||
365 | /* Instruction costs on RS64A processors. */ | |
366 | static const | |
367 | struct processor_costs rs64a_cost = { | |
06a67bdd RS |
368 | COSTS_N_INSNS (20), /* mulsi */ |
369 | COSTS_N_INSNS (12), /* mulsi_const */ | |
370 | COSTS_N_INSNS (8), /* mulsi_const9 */ | |
371 | COSTS_N_INSNS (34), /* muldi */ | |
372 | COSTS_N_INSNS (65), /* divsi */ | |
373 | COSTS_N_INSNS (67), /* divdi */ | |
374 | COSTS_N_INSNS (4), /* fp */ | |
375 | COSTS_N_INSNS (4), /* dmul */ | |
376 | COSTS_N_INSNS (31), /* sdiv */ | |
377 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
378 | }; |
379 | ||
380 | /* Instruction costs on MPCCORE processors. */ | |
381 | static const | |
382 | struct processor_costs mpccore_cost = { | |
06a67bdd RS |
383 | COSTS_N_INSNS (2), /* mulsi */ |
384 | COSTS_N_INSNS (2), /* mulsi_const */ | |
385 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
386 | COSTS_N_INSNS (2), /* muldi */ | |
387 | COSTS_N_INSNS (6), /* divsi */ | |
388 | COSTS_N_INSNS (6), /* divdi */ | |
389 | COSTS_N_INSNS (4), /* fp */ | |
390 | COSTS_N_INSNS (5), /* dmul */ | |
391 | COSTS_N_INSNS (10), /* sdiv */ | |
392 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
393 | }; |
394 | ||
395 | /* Instruction costs on PPC403 processors. */ | |
396 | static const | |
397 | struct processor_costs ppc403_cost = { | |
06a67bdd RS |
398 | COSTS_N_INSNS (4), /* mulsi */ |
399 | COSTS_N_INSNS (4), /* mulsi_const */ | |
400 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
401 | COSTS_N_INSNS (4), /* muldi */ | |
402 | COSTS_N_INSNS (33), /* divsi */ | |
403 | COSTS_N_INSNS (33), /* divdi */ | |
404 | COSTS_N_INSNS (11), /* fp */ | |
405 | COSTS_N_INSNS (11), /* dmul */ | |
406 | COSTS_N_INSNS (11), /* sdiv */ | |
407 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
408 | }; |
409 | ||
410 | /* Instruction costs on PPC405 processors. */ | |
411 | static const | |
412 | struct processor_costs ppc405_cost = { | |
06a67bdd RS |
413 | COSTS_N_INSNS (5), /* mulsi */ |
414 | COSTS_N_INSNS (4), /* mulsi_const */ | |
415 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
416 | COSTS_N_INSNS (5), /* muldi */ | |
417 | COSTS_N_INSNS (35), /* divsi */ | |
418 | COSTS_N_INSNS (35), /* divdi */ | |
419 | COSTS_N_INSNS (11), /* fp */ | |
420 | COSTS_N_INSNS (11), /* dmul */ | |
421 | COSTS_N_INSNS (11), /* sdiv */ | |
422 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
423 | }; |
424 | ||
425 | /* Instruction costs on PPC440 processors. */ | |
426 | static const | |
427 | struct processor_costs ppc440_cost = { | |
06a67bdd RS |
428 | COSTS_N_INSNS (3), /* mulsi */ |
429 | COSTS_N_INSNS (2), /* mulsi_const */ | |
430 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
431 | COSTS_N_INSNS (3), /* muldi */ | |
432 | COSTS_N_INSNS (34), /* divsi */ | |
433 | COSTS_N_INSNS (34), /* divdi */ | |
434 | COSTS_N_INSNS (5), /* fp */ | |
435 | COSTS_N_INSNS (5), /* dmul */ | |
436 | COSTS_N_INSNS (19), /* sdiv */ | |
437 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
438 | }; |
439 | ||
440 | /* Instruction costs on PPC601 processors. */ | |
441 | static const | |
442 | struct processor_costs ppc601_cost = { | |
06a67bdd RS |
443 | COSTS_N_INSNS (5), /* mulsi */ |
444 | COSTS_N_INSNS (5), /* mulsi_const */ | |
445 | COSTS_N_INSNS (5), /* mulsi_const9 */ | |
446 | COSTS_N_INSNS (5), /* muldi */ | |
447 | COSTS_N_INSNS (36), /* divsi */ | |
448 | COSTS_N_INSNS (36), /* divdi */ | |
449 | COSTS_N_INSNS (4), /* fp */ | |
450 | COSTS_N_INSNS (5), /* dmul */ | |
451 | COSTS_N_INSNS (17), /* sdiv */ | |
452 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
453 | }; |
454 | ||
455 | /* Instruction costs on PPC603 processors. */ | |
456 | static const | |
457 | struct processor_costs ppc603_cost = { | |
06a67bdd RS |
458 | COSTS_N_INSNS (5), /* mulsi */ |
459 | COSTS_N_INSNS (3), /* mulsi_const */ | |
460 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
461 | COSTS_N_INSNS (5), /* muldi */ | |
462 | COSTS_N_INSNS (37), /* divsi */ | |
463 | COSTS_N_INSNS (37), /* divdi */ | |
464 | COSTS_N_INSNS (3), /* fp */ | |
465 | COSTS_N_INSNS (4), /* dmul */ | |
466 | COSTS_N_INSNS (18), /* sdiv */ | |
467 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
468 | }; |
469 | ||
470 | /* Instruction costs on PPC604 processors. */ | |
471 | static const | |
472 | struct processor_costs ppc604_cost = { | |
06a67bdd RS |
473 | COSTS_N_INSNS (4), /* mulsi */ |
474 | COSTS_N_INSNS (4), /* mulsi_const */ | |
475 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
476 | COSTS_N_INSNS (4), /* muldi */ | |
477 | COSTS_N_INSNS (20), /* divsi */ | |
478 | COSTS_N_INSNS (20), /* divdi */ | |
479 | COSTS_N_INSNS (3), /* fp */ | |
480 | COSTS_N_INSNS (3), /* dmul */ | |
481 | COSTS_N_INSNS (18), /* sdiv */ | |
482 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
483 | }; |
484 | ||
485 | /* Instruction costs on PPC604e processors. */ | |
486 | static const | |
487 | struct processor_costs ppc604e_cost = { | |
06a67bdd RS |
488 | COSTS_N_INSNS (2), /* mulsi */ |
489 | COSTS_N_INSNS (2), /* mulsi_const */ | |
490 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
491 | COSTS_N_INSNS (2), /* muldi */ | |
492 | COSTS_N_INSNS (20), /* divsi */ | |
493 | COSTS_N_INSNS (20), /* divdi */ | |
494 | COSTS_N_INSNS (3), /* fp */ | |
495 | COSTS_N_INSNS (3), /* dmul */ | |
496 | COSTS_N_INSNS (18), /* sdiv */ | |
497 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
498 | }; |
499 | ||
f0517163 | 500 | /* Instruction costs on PPC620 processors. */ |
8b897cfa RS |
501 | static const |
502 | struct processor_costs ppc620_cost = { | |
06a67bdd RS |
503 | COSTS_N_INSNS (5), /* mulsi */ |
504 | COSTS_N_INSNS (4), /* mulsi_const */ | |
505 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
506 | COSTS_N_INSNS (7), /* muldi */ | |
507 | COSTS_N_INSNS (21), /* divsi */ | |
508 | COSTS_N_INSNS (37), /* divdi */ | |
509 | COSTS_N_INSNS (3), /* fp */ | |
510 | COSTS_N_INSNS (3), /* dmul */ | |
511 | COSTS_N_INSNS (18), /* sdiv */ | |
512 | COSTS_N_INSNS (32), /* ddiv */ | |
f0517163 RS |
513 | }; |
514 | ||
515 | /* Instruction costs on PPC630 processors. */ | |
516 | static const | |
517 | struct processor_costs ppc630_cost = { | |
06a67bdd RS |
518 | COSTS_N_INSNS (5), /* mulsi */ |
519 | COSTS_N_INSNS (4), /* mulsi_const */ | |
520 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
521 | COSTS_N_INSNS (7), /* muldi */ | |
522 | COSTS_N_INSNS (21), /* divsi */ | |
523 | COSTS_N_INSNS (37), /* divdi */ | |
524 | COSTS_N_INSNS (3), /* fp */ | |
525 | COSTS_N_INSNS (3), /* dmul */ | |
526 | COSTS_N_INSNS (17), /* sdiv */ | |
527 | COSTS_N_INSNS (21), /* ddiv */ | |
8b897cfa RS |
528 | }; |
529 | ||
530 | /* Instruction costs on PPC750 and PPC7400 processors. */ | |
531 | static const | |
532 | struct processor_costs ppc750_cost = { | |
06a67bdd RS |
533 | COSTS_N_INSNS (5), /* mulsi */ |
534 | COSTS_N_INSNS (3), /* mulsi_const */ | |
535 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
536 | COSTS_N_INSNS (5), /* muldi */ | |
537 | COSTS_N_INSNS (17), /* divsi */ | |
538 | COSTS_N_INSNS (17), /* divdi */ | |
539 | COSTS_N_INSNS (3), /* fp */ | |
540 | COSTS_N_INSNS (3), /* dmul */ | |
541 | COSTS_N_INSNS (17), /* sdiv */ | |
542 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
543 | }; |
544 | ||
545 | /* Instruction costs on PPC7450 processors. */ | |
546 | static const | |
547 | struct processor_costs ppc7450_cost = { | |
06a67bdd RS |
548 | COSTS_N_INSNS (4), /* mulsi */ |
549 | COSTS_N_INSNS (3), /* mulsi_const */ | |
550 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
551 | COSTS_N_INSNS (4), /* muldi */ | |
552 | COSTS_N_INSNS (23), /* divsi */ | |
553 | COSTS_N_INSNS (23), /* divdi */ | |
554 | COSTS_N_INSNS (5), /* fp */ | |
555 | COSTS_N_INSNS (5), /* dmul */ | |
556 | COSTS_N_INSNS (21), /* sdiv */ | |
557 | COSTS_N_INSNS (35), /* ddiv */ | |
8b897cfa | 558 | }; |
a3170dc6 | 559 | |
8b897cfa RS |
560 | /* Instruction costs on PPC8540 processors. */ |
561 | static const | |
562 | struct processor_costs ppc8540_cost = { | |
06a67bdd RS |
563 | COSTS_N_INSNS (4), /* mulsi */ |
564 | COSTS_N_INSNS (4), /* mulsi_const */ | |
565 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
566 | COSTS_N_INSNS (4), /* muldi */ | |
567 | COSTS_N_INSNS (19), /* divsi */ | |
568 | COSTS_N_INSNS (19), /* divdi */ | |
569 | COSTS_N_INSNS (4), /* fp */ | |
570 | COSTS_N_INSNS (4), /* dmul */ | |
571 | COSTS_N_INSNS (29), /* sdiv */ | |
572 | COSTS_N_INSNS (29), /* ddiv */ | |
8b897cfa RS |
573 | }; |
574 | ||
575 | /* Instruction costs on POWER4 and POWER5 processors. */ | |
576 | static const | |
577 | struct processor_costs power4_cost = { | |
06a67bdd RS |
578 | COSTS_N_INSNS (3), /* mulsi */ |
579 | COSTS_N_INSNS (2), /* mulsi_const */ | |
580 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
581 | COSTS_N_INSNS (4), /* muldi */ | |
582 | COSTS_N_INSNS (18), /* divsi */ | |
583 | COSTS_N_INSNS (34), /* divdi */ | |
584 | COSTS_N_INSNS (3), /* fp */ | |
585 | COSTS_N_INSNS (3), /* dmul */ | |
586 | COSTS_N_INSNS (17), /* sdiv */ | |
587 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
588 | }; |
589 | ||
590 | \f | |
a2369ed3 DJ |
591 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
592 | static int num_insns_constant_wide (HOST_WIDE_INT); | |
593 | static void validate_condition_mode (enum rtx_code, enum machine_mode); | |
594 | static rtx rs6000_generate_compare (enum rtx_code); | |
595 | static void rs6000_maybe_dead (rtx); | |
596 | static void rs6000_emit_stack_tie (void); | |
597 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
598 | static rtx spe_synthesize_frame_save (rtx); | |
599 | static bool spe_func_has_64bit_regs_p (void); | |
b20a9cca | 600 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 601 | int, HOST_WIDE_INT); |
a2369ed3 DJ |
602 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
603 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); | |
604 | static unsigned rs6000_hash_constant (rtx); | |
605 | static unsigned toc_hash_function (const void *); | |
606 | static int toc_hash_eq (const void *, const void *); | |
607 | static int constant_pool_expr_1 (rtx, int *, int *); | |
608 | static bool constant_pool_expr_p (rtx); | |
609 | static bool toc_relative_expr_p (rtx); | |
610 | static bool legitimate_small_data_p (enum machine_mode, rtx); | |
a2369ed3 DJ |
611 | static bool legitimate_indexed_address_p (rtx, int); |
612 | static bool legitimate_indirect_address_p (rtx, int); | |
4c81e946 | 613 | static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode); |
a2369ed3 DJ |
614 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
615 | static struct machine_function * rs6000_init_machine_status (void); | |
616 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
5add3202 | 617 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 618 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 619 | #endif |
a2369ed3 DJ |
620 | static int rs6000_ra_ever_killed (void); |
621 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
8bb418a3 | 622 | static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); |
76d2b81d | 623 | static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); |
f18eca82 | 624 | static const char *rs6000_mangle_fundamental_type (tree); |
b86fe7b4 | 625 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 DJ |
626 | static void rs6000_set_default_type_attributes (tree); |
627 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); | |
628 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
629 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
630 | tree); | |
a2369ed3 | 631 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
c6e8c921 | 632 | static bool rs6000_return_in_memory (tree, tree); |
a2369ed3 | 633 | static void rs6000_file_start (void); |
7c262518 | 634 | #if TARGET_ELF |
a2369ed3 DJ |
635 | static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); |
636 | static void rs6000_elf_asm_out_constructor (rtx, int); | |
637 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
638 | static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); | |
639 | static void rs6000_elf_unique_section (tree, int); | |
640 | static void rs6000_elf_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 641 | unsigned HOST_WIDE_INT); |
a56d7372 | 642 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 643 | ATTRIBUTE_UNUSED; |
a2369ed3 | 644 | static bool rs6000_elf_in_small_data_p (tree); |
7c262518 | 645 | #endif |
cbaaba19 | 646 | #if TARGET_XCOFF |
a2369ed3 DJ |
647 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
648 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int); | |
649 | static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT); | |
650 | static void rs6000_xcoff_unique_section (tree, int); | |
651 | static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 652 | unsigned HOST_WIDE_INT); |
a2369ed3 DJ |
653 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
654 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
655 | static void rs6000_xcoff_file_start (void); | |
656 | static void rs6000_xcoff_file_end (void); | |
f1384257 AM |
657 | #endif |
658 | #if TARGET_MACHO | |
a2369ed3 | 659 | static bool rs6000_binds_local_p (tree); |
f1384257 | 660 | #endif |
a2369ed3 DJ |
661 | static int rs6000_variable_issue (FILE *, int, rtx, int); |
662 | static bool rs6000_rtx_costs (rtx, int, int, int *); | |
663 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); | |
cbe26ab8 | 664 | static bool is_microcoded_insn (rtx); |
79ae11c4 | 665 | static int is_dispatch_slot_restricted (rtx); |
cbe26ab8 DN |
666 | static bool is_cracked_insn (rtx); |
667 | static bool is_branch_slot_insn (rtx); | |
a2369ed3 DJ |
668 | static int rs6000_adjust_priority (rtx, int); |
669 | static int rs6000_issue_rate (void); | |
569fa502 | 670 | static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); |
cbe26ab8 DN |
671 | static rtx get_next_active_insn (rtx, rtx); |
672 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
673 | static bool is_costly_group (rtx *, rtx); | |
674 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
675 | static int redefine_groups (FILE *, int, rtx, rtx); | |
676 | static int pad_groups (FILE *, int, rtx, rtx); | |
677 | static void rs6000_sched_finish (FILE *, int); | |
a2369ed3 DJ |
678 | static int rs6000_use_sched_lookahead (void); |
679 | ||
680 | static void rs6000_init_builtins (void); | |
681 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
682 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
683 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
684 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
685 | static void altivec_init_builtins (void); | |
686 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 687 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 688 | |
b20a9cca AM |
689 | static void enable_mask_for_builtins (struct builtin_description *, int, |
690 | enum rs6000_builtins, | |
691 | enum rs6000_builtins); | |
7c62e993 | 692 | static tree build_opaque_vector_type (tree, int); |
a2369ed3 DJ |
693 | static void spe_init_builtins (void); |
694 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
61bea3b0 | 695 | static rtx spe_expand_stv_builtin (enum insn_code, tree); |
a2369ed3 DJ |
696 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); |
697 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
698 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
699 | static rs6000_stack_t *rs6000_stack_info (void); |
700 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
701 | |
702 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
703 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
704 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
705 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
706 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
707 | static rtx altivec_expand_predicate_builtin (enum insn_code, | |
708 | const char *, tree, rtx); | |
b4a62fa0 | 709 | static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); |
a2369ed3 DJ |
710 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
711 | static void rs6000_parse_abi_options (void); | |
712 | static void rs6000_parse_alignment_option (void); | |
713 | static void rs6000_parse_tls_size_option (void); | |
5da702b1 | 714 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
a2369ed3 DJ |
715 | static int first_altivec_reg_to_save (void); |
716 | static unsigned int compute_vrsave_mask (void); | |
717 | static void is_altivec_return_reg (rtx, void *); | |
718 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
719 | int easy_vector_constant (rtx, enum machine_mode); | |
720 | static int easy_vector_same (rtx, enum machine_mode); | |
452a7d36 | 721 | static int easy_vector_splat_const (int, enum machine_mode); |
a2369ed3 DJ |
722 | static bool is_ev64_opaque_type (tree); |
723 | static rtx rs6000_dwarf_register_span (rtx); | |
724 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); | |
725 | static rtx rs6000_tls_get_addr (void); | |
726 | static rtx rs6000_got_sym (void); | |
727 | static inline int rs6000_tls_symbol_ref_1 (rtx *, void *); | |
728 | static const char *rs6000_get_some_local_dynamic_name (void); | |
729 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 730 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 731 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 732 | enum machine_mode, tree); |
ec6376ab | 733 | static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); |
b1917422 | 734 | static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); |
c6e8c921 GK |
735 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
736 | enum machine_mode, tree, | |
737 | int *, int); | |
8cd5a4e0 RH |
738 | static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
739 | tree, bool); | |
efdba735 SH |
740 | #if TARGET_MACHO |
741 | static void macho_branch_islands (void); | |
742 | static void add_compiler_branch_island (tree, tree, int); | |
743 | static int no_previous_def (tree function_name); | |
744 | static tree get_prev_label (tree function_name); | |
745 | #endif | |
746 | ||
c35d187f | 747 | static tree rs6000_build_builtin_va_list (void); |
23a60a04 | 748 | static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); |
fe984136 | 749 | static bool rs6000_must_pass_in_stack (enum machine_mode, tree); |
17211ab5 GK |
750 | |
751 | /* Hash table stuff for keeping track of TOC entries. */ | |
752 | ||
753 | struct toc_hash_struct GTY(()) | |
754 | { | |
755 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
756 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
757 | rtx key; | |
758 | enum machine_mode key_mode; | |
759 | int labelno; | |
760 | }; | |
761 | ||
762 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
763 | \f |
764 | /* Default register names. */ | |
765 | char rs6000_reg_names[][8] = | |
766 | { | |
802a0058 MM |
767 | "0", "1", "2", "3", "4", "5", "6", "7", |
768 | "8", "9", "10", "11", "12", "13", "14", "15", | |
769 | "16", "17", "18", "19", "20", "21", "22", "23", | |
770 | "24", "25", "26", "27", "28", "29", "30", "31", | |
771 | "0", "1", "2", "3", "4", "5", "6", "7", | |
772 | "8", "9", "10", "11", "12", "13", "14", "15", | |
773 | "16", "17", "18", "19", "20", "21", "22", "23", | |
774 | "24", "25", "26", "27", "28", "29", "30", "31", | |
775 | "mq", "lr", "ctr","ap", | |
776 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
777 | "xer", |
778 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
779 | "0", "1", "2", "3", "4", "5", "6", "7", |
780 | "8", "9", "10", "11", "12", "13", "14", "15", | |
781 | "16", "17", "18", "19", "20", "21", "22", "23", | |
782 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
783 | "vrsave", "vscr", |
784 | /* SPE registers. */ | |
785 | "spe_acc", "spefscr" | |
c81bebd7 MM |
786 | }; |
787 | ||
788 | #ifdef TARGET_REGNAMES | |
8b60264b | 789 | static const char alt_reg_names[][8] = |
c81bebd7 | 790 | { |
802a0058 MM |
791 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
792 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
793 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
794 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
795 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
796 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
797 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
798 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
799 | "mq", "lr", "ctr", "ap", | |
800 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 801 | "xer", |
59a4c851 | 802 | /* AltiVec registers. */ |
0ac081f6 | 803 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
804 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
805 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
806 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
807 | "vrsave", "vscr", | |
808 | /* SPE registers. */ | |
809 | "spe_acc", "spefscr" | |
c81bebd7 MM |
810 | }; |
811 | #endif | |
9878760c | 812 | \f |
daf11973 MM |
813 | #ifndef MASK_STRICT_ALIGN |
814 | #define MASK_STRICT_ALIGN 0 | |
815 | #endif | |
ffcfcb5f AM |
816 | #ifndef TARGET_PROFILE_KERNEL |
817 | #define TARGET_PROFILE_KERNEL 0 | |
818 | #endif | |
3961e8fe RH |
819 | |
820 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
821 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
c4501e62 JJ |
822 | |
823 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ | |
824 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
825 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
672a6f42 NB |
826 | \f |
827 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
828 | #undef TARGET_ATTRIBUTE_TABLE |
829 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
830 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
831 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 832 | |
301d03af RS |
833 | #undef TARGET_ASM_ALIGNED_DI_OP |
834 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
835 | ||
836 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
837 | for non-ELF systems. */ | |
838 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 839 | #if TARGET_XCOFF |
ae6c1efd | 840 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
841 | 64-bit targets. */ |
842 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
843 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
844 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
845 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
846 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
847 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
848 | #else | |
849 | /* For Darwin. */ | |
850 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
851 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
852 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
853 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
854 | #endif | |
855 | #endif | |
856 | ||
857 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
858 | in 64-bit code. */ | |
859 | #undef TARGET_ASM_INTEGER | |
860 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
861 | ||
93638d7a AM |
862 | #ifdef HAVE_GAS_HIDDEN |
863 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
864 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
865 | #endif | |
866 | ||
c4501e62 JJ |
867 | #undef TARGET_HAVE_TLS |
868 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
869 | ||
870 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
871 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p | |
872 | ||
08c148a8 NB |
873 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
874 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
875 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
876 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
877 | ||
b54cf83a | 878 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
11ac38b2 | 879 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1 |
b54cf83a DE |
880 | #undef TARGET_SCHED_VARIABLE_ISSUE |
881 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
882 | ||
c237e94a ZW |
883 | #undef TARGET_SCHED_ISSUE_RATE |
884 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
885 | #undef TARGET_SCHED_ADJUST_COST | |
886 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
887 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
888 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
569fa502 DN |
889 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
890 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence | |
cbe26ab8 DN |
891 | #undef TARGET_SCHED_FINISH |
892 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
c237e94a | 893 | |
be12c2b0 VM |
894 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
895 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
896 | ||
0ac081f6 AH |
897 | #undef TARGET_INIT_BUILTINS |
898 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
899 | ||
900 | #undef TARGET_EXPAND_BUILTIN | |
901 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
902 | ||
f18eca82 ZL |
903 | #undef TARGET_MANGLE_FUNDAMENTAL_TYPE |
904 | #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type | |
905 | ||
c15c90bb ZW |
906 | #undef TARGET_INIT_LIBFUNCS |
907 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
908 | ||
f1384257 | 909 | #if TARGET_MACHO |
0e5dbd9b DE |
910 | #undef TARGET_BINDS_LOCAL_P |
911 | #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p | |
f1384257 | 912 | #endif |
0e5dbd9b | 913 | |
3961e8fe RH |
914 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
915 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
916 | ||
3961e8fe | 917 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 918 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 919 | |
4977bab6 ZW |
920 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
921 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
922 | ||
3c50106f RH |
923 | #undef TARGET_RTX_COSTS |
924 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
925 | #undef TARGET_ADDRESS_COST |
926 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 927 | |
c8e4f0e9 AH |
928 | #undef TARGET_VECTOR_OPAQUE_P |
929 | #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type | |
62e1dfcf | 930 | |
96714395 AH |
931 | #undef TARGET_DWARF_REGISTER_SPAN |
932 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
933 | ||
c6e8c921 GK |
934 | /* On rs6000, function arguments are promoted, as are function return |
935 | values. */ | |
936 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
937 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
938 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
939 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
940 | ||
c6e8c921 GK |
941 | #undef TARGET_RETURN_IN_MEMORY |
942 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
943 | ||
944 | #undef TARGET_SETUP_INCOMING_VARARGS | |
945 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
946 | ||
947 | /* Always strict argument naming on rs6000. */ | |
948 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
949 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
950 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
951 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
42ba5130 RH |
952 | #undef TARGET_SPLIT_COMPLEX_ARG |
953 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true | |
fe984136 RH |
954 | #undef TARGET_MUST_PASS_IN_STACK |
955 | #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack | |
8cd5a4e0 RH |
956 | #undef TARGET_PASS_BY_REFERENCE |
957 | #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference | |
c6e8c921 | 958 | |
c35d187f RH |
959 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
960 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
961 | ||
cd3ce9b4 JM |
962 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
963 | #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg | |
964 | ||
f6897b10 | 965 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 966 | \f |
0d1fbc8c AH |
967 | |
968 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
969 | MODE. */ | |
970 | static int | |
971 | rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
972 | { | |
973 | /* The GPRs can hold any mode, but values bigger than one register | |
974 | cannot go past R31. */ | |
975 | if (INT_REGNO_P (regno)) | |
976 | return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); | |
977 | ||
978 | /* The float registers can only hold floating modes and DImode. */ | |
979 | if (FP_REGNO_P (regno)) | |
980 | return | |
981 | (GET_MODE_CLASS (mode) == MODE_FLOAT | |
982 | && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) | |
983 | || (GET_MODE_CLASS (mode) == MODE_INT | |
984 | && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD); | |
985 | ||
986 | /* The CR register can only hold CC modes. */ | |
987 | if (CR_REGNO_P (regno)) | |
988 | return GET_MODE_CLASS (mode) == MODE_CC; | |
989 | ||
990 | if (XER_REGNO_P (regno)) | |
991 | return mode == PSImode; | |
992 | ||
993 | /* AltiVec only in AldyVec registers. */ | |
994 | if (ALTIVEC_REGNO_P (regno)) | |
995 | return ALTIVEC_VECTOR_MODE (mode); | |
996 | ||
997 | /* ...but GPRs can hold SIMD data on the SPE in one register. */ | |
998 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
999 | return 1; | |
1000 | ||
1001 | /* We cannot put TImode anywhere except general register and it must be | |
1002 | able to fit within the register set. */ | |
1003 | ||
1004 | return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; | |
1005 | } | |
1006 | ||
1007 | /* Initialize rs6000_hard_regno_mode_ok_p table. */ | |
1008 | static void | |
1009 | rs6000_init_hard_regno_mode_ok (void) | |
1010 | { | |
1011 | int r, m; | |
1012 | ||
1013 | for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) | |
1014 | for (m = 0; m < NUM_MACHINE_MODES; ++m) | |
1015 | if (rs6000_hard_regno_mode_ok (r, m)) | |
1016 | rs6000_hard_regno_mode_ok_p[m][r] = true; | |
1017 | } | |
1018 | ||
5248c961 RK |
1019 | /* Override command line options. Mostly we process the processor |
1020 | type and sometimes adjust other TARGET_ options. */ | |
1021 | ||
1022 | void | |
d779d0dc | 1023 | rs6000_override_options (const char *default_cpu) |
5248c961 | 1024 | { |
c4d38ccb | 1025 | size_t i, j; |
8e3f41e7 | 1026 | struct rs6000_cpu_select *ptr; |
66188a7e | 1027 | int set_masks; |
5248c961 | 1028 | |
66188a7e | 1029 | /* Simplifications for entries below. */ |
85638c0d | 1030 | |
66188a7e GK |
1031 | enum { |
1032 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
1033 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
1034 | }; | |
85638c0d | 1035 | |
66188a7e GK |
1036 | /* This table occasionally claims that a processor does not support |
1037 | a particular feature even though it does, but the feature is slower | |
1038 | than the alternative. Thus, it shouldn't be relied on as a | |
1039 | complete description of the processor's support. | |
1040 | ||
1041 | Please keep this list in order, and don't forget to update the | |
1042 | documentation in invoke.texi when adding a new processor or | |
1043 | flag. */ | |
5248c961 RK |
1044 | static struct ptt |
1045 | { | |
8b60264b KG |
1046 | const char *const name; /* Canonical processor name. */ |
1047 | const enum processor_type processor; /* Processor type enum value. */ | |
1048 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 1049 | } const processor_target_table[] |
66188a7e | 1050 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 1051 | {"403", PROCESSOR_PPC403, |
66188a7e GK |
1052 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
1053 | {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1054 | {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK}, | |
1055 | {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1056 | {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK}, | |
1057 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, | |
5248c961 | 1058 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
1059 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
1060 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1061 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1062 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1063 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1064 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
1065 | {"620", PROCESSOR_PPC620, |
1066 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1067 | {"630", PROCESSOR_PPC630, | |
1068 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
1069 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
1070 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
1071 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
1072 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1073 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1074 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1075 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1076 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1077 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
7177e720 | 1078 | {"970", PROCESSOR_POWER4, |
66188a7e GK |
1079 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1080 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, | |
1081 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1082 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1083 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 1084 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
1085 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1086 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1087 | {"power2", PROCESSOR_POWER, | |
1088 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
1089 | {"power3", PROCESSOR_PPC630, |
1090 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1091 | {"power4", PROCESSOR_POWER4, | |
fc091c8e | 1092 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
ec507f2d | 1093 | {"power5", PROCESSOR_POWER5, |
fc091c8e | 1094 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
66188a7e GK |
1095 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
1096 | {"powerpc64", PROCESSOR_POWERPC64, | |
1097 | POWERPC_BASE_MASK | MASK_POWERPC64}, | |
1098 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1099 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1100 | {"rios2", PROCESSOR_RIOS2, | |
1101 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
1102 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1103 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 | 1104 | {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64}, |
66188a7e | 1105 | }; |
5248c961 | 1106 | |
ca7558fc | 1107 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 1108 | |
66188a7e GK |
1109 | /* Some OSs don't support saving the high part of 64-bit registers on |
1110 | context switch. Other OSs don't support saving Altivec registers. | |
1111 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
1112 | settings; if the user wants either, the user must explicitly specify | |
1113 | them and we won't interfere with the user's specification. */ | |
1114 | ||
1115 | enum { | |
1116 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
1117 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | |
1118 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC | |
1119 | | MASK_MFCRF) | |
1120 | }; | |
0d1fbc8c AH |
1121 | |
1122 | rs6000_init_hard_regno_mode_ok (); | |
1123 | ||
66188a7e GK |
1124 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; |
1125 | #ifdef OS_MISSING_POWERPC64 | |
1126 | if (OS_MISSING_POWERPC64) | |
1127 | set_masks &= ~MASK_POWERPC64; | |
1128 | #endif | |
1129 | #ifdef OS_MISSING_ALTIVEC | |
1130 | if (OS_MISSING_ALTIVEC) | |
1131 | set_masks &= ~MASK_ALTIVEC; | |
1132 | #endif | |
1133 | ||
957211c3 AM |
1134 | /* Don't override these by the processor default if given explicitly. */ |
1135 | set_masks &= ~(target_flags_explicit | |
1136 | & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT)); | |
1137 | ||
a4f6c312 | 1138 | /* Identify the processor type. */ |
8e3f41e7 | 1139 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 1140 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 1141 | |
b6a1cbae | 1142 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 1143 | { |
8e3f41e7 MM |
1144 | ptr = &rs6000_select[i]; |
1145 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 1146 | { |
8e3f41e7 MM |
1147 | for (j = 0; j < ptt_size; j++) |
1148 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
1149 | { | |
1150 | if (ptr->set_tune_p) | |
1151 | rs6000_cpu = processor_target_table[j].processor; | |
1152 | ||
1153 | if (ptr->set_arch_p) | |
1154 | { | |
66188a7e GK |
1155 | target_flags &= ~set_masks; |
1156 | target_flags |= (processor_target_table[j].target_enable | |
1157 | & set_masks); | |
8e3f41e7 MM |
1158 | } |
1159 | break; | |
1160 | } | |
1161 | ||
4406229e | 1162 | if (j == ptt_size) |
8e3f41e7 | 1163 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
1164 | } |
1165 | } | |
8a61d227 | 1166 | |
993f19a8 | 1167 | if (TARGET_E500) |
a3170dc6 AH |
1168 | rs6000_isel = 1; |
1169 | ||
dff9f1b6 DE |
1170 | /* If we are optimizing big endian systems for space, use the load/store |
1171 | multiple and string instructions. */ | |
ef792183 | 1172 | if (BYTES_BIG_ENDIAN && optimize_size) |
957211c3 | 1173 | target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); |
938937d8 | 1174 | |
a4f6c312 SS |
1175 | /* Don't allow -mmultiple or -mstring on little endian systems |
1176 | unless the cpu is a 750, because the hardware doesn't support the | |
1177 | instructions used in little endian mode, and causes an alignment | |
1178 | trap. The 750 does not cause an alignment trap (except when the | |
1179 | target is unaligned). */ | |
bef84347 | 1180 | |
b21fb038 | 1181 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
1182 | { |
1183 | if (TARGET_MULTIPLE) | |
1184 | { | |
1185 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 1186 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
7e69e155 MM |
1187 | warning ("-mmultiple is not supported on little endian systems"); |
1188 | } | |
1189 | ||
1190 | if (TARGET_STRING) | |
1191 | { | |
1192 | target_flags &= ~MASK_STRING; | |
b21fb038 | 1193 | if ((target_flags_explicit & MASK_STRING) != 0) |
938937d8 | 1194 | warning ("-mstring is not supported on little endian systems"); |
7e69e155 MM |
1195 | } |
1196 | } | |
3933e0e1 | 1197 | |
38c1f2d7 MM |
1198 | /* Set debug flags */ |
1199 | if (rs6000_debug_name) | |
1200 | { | |
bfc79d3b | 1201 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 1202 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 1203 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 1204 | rs6000_debug_stack = 1; |
bfc79d3b | 1205 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
1206 | rs6000_debug_arg = 1; |
1207 | else | |
c725bd79 | 1208 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
1209 | } |
1210 | ||
57ac7be9 AM |
1211 | if (rs6000_traceback_name) |
1212 | { | |
1213 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
1214 | rs6000_traceback = traceback_full; | |
1215 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
1216 | rs6000_traceback = traceback_part; | |
1217 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
1218 | rs6000_traceback = traceback_none; | |
1219 | else | |
1220 | error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'", | |
1221 | rs6000_traceback_name); | |
1222 | } | |
1223 | ||
6fa3f289 ZW |
1224 | /* Set size of long double */ |
1225 | rs6000_long_double_type_size = 64; | |
1226 | if (rs6000_long_double_size_string) | |
1227 | { | |
1228 | char *tail; | |
1229 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
1230 | if (*tail != '\0' || (size != 64 && size != 128)) | |
1231 | error ("Unknown switch -mlong-double-%s", | |
1232 | rs6000_long_double_size_string); | |
1233 | else | |
1234 | rs6000_long_double_type_size = size; | |
1235 | } | |
1236 | ||
6d0ef01e HP |
1237 | /* Set Altivec ABI as default for powerpc64 linux. */ |
1238 | if (TARGET_ELF && TARGET_64BIT) | |
1239 | { | |
1240 | rs6000_altivec_abi = 1; | |
1241 | rs6000_altivec_vrsave = 1; | |
1242 | } | |
1243 | ||
0ac081f6 AH |
1244 | /* Handle -mabi= options. */ |
1245 | rs6000_parse_abi_options (); | |
1246 | ||
025d9908 KH |
1247 | /* Handle -malign-XXXXX option. */ |
1248 | rs6000_parse_alignment_option (); | |
1249 | ||
5da702b1 AH |
1250 | /* Handle generic -mFOO=YES/NO options. */ |
1251 | rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string, | |
1252 | &rs6000_altivec_vrsave); | |
1253 | rs6000_parse_yes_no_option ("isel", rs6000_isel_string, | |
1254 | &rs6000_isel); | |
1255 | rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe); | |
1256 | rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string, | |
1257 | &rs6000_float_gprs); | |
993f19a8 | 1258 | |
c4501e62 JJ |
1259 | /* Handle -mtls-size option. */ |
1260 | rs6000_parse_tls_size_option (); | |
1261 | ||
a7ae18e2 AH |
1262 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1263 | SUBTARGET_OVERRIDE_OPTIONS; | |
1264 | #endif | |
1265 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
1266 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
1267 | #endif | |
1268 | ||
5da702b1 AH |
1269 | if (TARGET_E500) |
1270 | { | |
e4463bf1 AH |
1271 | if (TARGET_ALTIVEC) |
1272 | error ("AltiVec and E500 instructions cannot coexist"); | |
1273 | ||
5da702b1 AH |
1274 | /* The e500 does not have string instructions, and we set |
1275 | MASK_STRING above when optimizing for size. */ | |
1276 | if ((target_flags & MASK_STRING) != 0) | |
1277 | target_flags = target_flags & ~MASK_STRING; | |
b6e59a3a AH |
1278 | |
1279 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
1280 | if (rs6000_spe_string != 0 | |
1281 | && !strcmp (rs6000_spe_string, "no")) | |
1282 | rs6000_long_double_type_size = 64; | |
5da702b1 AH |
1283 | } |
1284 | else if (rs6000_select[1].string != NULL) | |
1285 | { | |
1286 | /* For the powerpc-eabispe configuration, we set all these by | |
1287 | default, so let's unset them if we manually set another | |
1288 | CPU that is not the E500. */ | |
1289 | if (rs6000_abi_string == 0) | |
1290 | rs6000_spe_abi = 0; | |
1291 | if (rs6000_spe_string == 0) | |
1292 | rs6000_spe = 0; | |
1293 | if (rs6000_float_gprs_string == 0) | |
1294 | rs6000_float_gprs = 0; | |
1295 | if (rs6000_isel_string == 0) | |
1296 | rs6000_isel = 0; | |
b6e59a3a AH |
1297 | if (rs6000_long_double_size_string == 0) |
1298 | rs6000_long_double_type_size = 64; | |
5da702b1 | 1299 | } |
b5044283 | 1300 | |
ec507f2d DE |
1301 | rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 |
1302 | && rs6000_cpu != PROCESSOR_POWER5); | |
1303 | rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 | |
1304 | || rs6000_cpu == PROCESSOR_POWER5); | |
1305 | ||
a5c76ee6 ZW |
1306 | /* Handle -m(no-)longcall option. This is a bit of a cheap hack, |
1307 | using TARGET_OPTIONS to handle a toggle switch, but we're out of | |
1308 | bits in target_flags so TARGET_SWITCHES cannot be used. | |
1309 | Assumption here is that rs6000_longcall_switch points into the | |
1310 | text of the complete option, rather than being a copy, so we can | |
1311 | scan back for the presence or absence of the no- modifier. */ | |
1312 | if (rs6000_longcall_switch) | |
1313 | { | |
1314 | const char *base = rs6000_longcall_switch; | |
1315 | while (base[-1] != 'm') base--; | |
1316 | ||
1317 | if (*rs6000_longcall_switch != '\0') | |
1318 | error ("invalid option `%s'", base); | |
1319 | rs6000_default_long_calls = (base[0] != 'n'); | |
1320 | } | |
1321 | ||
8bb418a3 ZL |
1322 | /* Handle -m(no-)warn-altivec-long similarly. */ |
1323 | if (rs6000_warn_altivec_long_switch) | |
1324 | { | |
1325 | const char *base = rs6000_warn_altivec_long_switch; | |
1326 | while (base[-1] != 'm') base--; | |
1327 | ||
1328 | if (*rs6000_warn_altivec_long_switch != '\0') | |
1329 | error ("invalid option `%s'", base); | |
1330 | rs6000_warn_altivec_long = (base[0] != 'n'); | |
1331 | } | |
1332 | ||
cbe26ab8 | 1333 | /* Handle -mprioritize-restricted-insns option. */ |
ec507f2d DE |
1334 | rs6000_sched_restricted_insns_priority |
1335 | = (rs6000_sched_groups ? 1 : 0); | |
79ae11c4 DN |
1336 | if (rs6000_sched_restricted_insns_priority_str) |
1337 | rs6000_sched_restricted_insns_priority = | |
1338 | atoi (rs6000_sched_restricted_insns_priority_str); | |
1339 | ||
569fa502 | 1340 | /* Handle -msched-costly-dep option. */ |
ec507f2d DE |
1341 | rs6000_sched_costly_dep |
1342 | = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); | |
569fa502 DN |
1343 | if (rs6000_sched_costly_dep_str) |
1344 | { | |
1345 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) | |
1346 | rs6000_sched_costly_dep = no_dep_costly; | |
1347 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) | |
1348 | rs6000_sched_costly_dep = all_deps_costly; | |
1349 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) | |
1350 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; | |
1351 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) | |
1352 | rs6000_sched_costly_dep = store_to_load_dep_costly; | |
cbe26ab8 DN |
1353 | else |
1354 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); | |
1355 | } | |
1356 | ||
1357 | /* Handle -minsert-sched-nops option. */ | |
ec507f2d DE |
1358 | rs6000_sched_insert_nops |
1359 | = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); | |
cbe26ab8 DN |
1360 | if (rs6000_sched_insert_nops_str) |
1361 | { | |
1362 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
1363 | rs6000_sched_insert_nops = sched_finish_none; | |
1364 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) | |
1365 | rs6000_sched_insert_nops = sched_finish_pad_groups; | |
1366 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) | |
1367 | rs6000_sched_insert_nops = sched_finish_regroup_exact; | |
1368 | else | |
1369 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); | |
569fa502 DN |
1370 | } |
1371 | ||
c81bebd7 | 1372 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
1373 | /* If the user desires alternate register names, copy in the |
1374 | alternate names now. */ | |
c81bebd7 | 1375 | if (TARGET_REGNAMES) |
4e135bdd | 1376 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
1377 | #endif |
1378 | ||
6fa3f289 ZW |
1379 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
1380 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
1381 | used, don't override with the ABI default. */ | |
b21fb038 | 1382 | if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0) |
6fa3f289 ZW |
1383 | { |
1384 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
1385 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
1386 | else | |
1387 | target_flags |= MASK_AIX_STRUCT_RET; | |
1388 | } | |
1389 | ||
fcce224d DE |
1390 | if (TARGET_LONG_DOUBLE_128 |
1391 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
70a01792 | 1392 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 1393 | |
9ebbca7d GK |
1394 | /* Allocate an alias set for register saves & restores from stack. */ |
1395 | rs6000_sr_alias_set = new_alias_set (); | |
1396 | ||
1397 | if (TARGET_TOC) | |
1398 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca | 1399 | |
301d03af RS |
1400 | /* We can only guarantee the availability of DI pseudo-ops when |
1401 | assembling for 64-bit targets. */ | |
ae6c1efd | 1402 | if (!TARGET_64BIT) |
301d03af RS |
1403 | { |
1404 | targetm.asm_out.aligned_op.di = NULL; | |
1405 | targetm.asm_out.unaligned_op.di = NULL; | |
1406 | } | |
1407 | ||
2792d578 DE |
1408 | /* Set maximum branch target alignment at two instructions, eight bytes. */ |
1409 | align_jumps_max_skip = 8; | |
1410 | align_loops_max_skip = 8; | |
1411 | ||
71f123ca FS |
1412 | /* Arrange to save and restore machine status around nested functions. */ |
1413 | init_machine_status = rs6000_init_machine_status; | |
42ba5130 RH |
1414 | |
1415 | /* We should always be splitting complex arguments, but we can't break | |
1416 | Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ | |
1417 | if (DEFAULT_ABI != ABI_AIX) | |
1418 | targetm.calls.split_complex_arg = NULL; | |
8b897cfa RS |
1419 | |
1420 | /* Initialize rs6000_cost with the appropriate target costs. */ | |
1421 | if (optimize_size) | |
1422 | rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; | |
1423 | else | |
1424 | switch (rs6000_cpu) | |
1425 | { | |
1426 | case PROCESSOR_RIOS1: | |
1427 | rs6000_cost = &rios1_cost; | |
1428 | break; | |
1429 | ||
1430 | case PROCESSOR_RIOS2: | |
1431 | rs6000_cost = &rios2_cost; | |
1432 | break; | |
1433 | ||
1434 | case PROCESSOR_RS64A: | |
1435 | rs6000_cost = &rs64a_cost; | |
1436 | break; | |
1437 | ||
1438 | case PROCESSOR_MPCCORE: | |
1439 | rs6000_cost = &mpccore_cost; | |
1440 | break; | |
1441 | ||
1442 | case PROCESSOR_PPC403: | |
1443 | rs6000_cost = &ppc403_cost; | |
1444 | break; | |
1445 | ||
1446 | case PROCESSOR_PPC405: | |
1447 | rs6000_cost = &ppc405_cost; | |
1448 | break; | |
1449 | ||
1450 | case PROCESSOR_PPC440: | |
1451 | rs6000_cost = &ppc440_cost; | |
1452 | break; | |
1453 | ||
1454 | case PROCESSOR_PPC601: | |
1455 | rs6000_cost = &ppc601_cost; | |
1456 | break; | |
1457 | ||
1458 | case PROCESSOR_PPC603: | |
1459 | rs6000_cost = &ppc603_cost; | |
1460 | break; | |
1461 | ||
1462 | case PROCESSOR_PPC604: | |
1463 | rs6000_cost = &ppc604_cost; | |
1464 | break; | |
1465 | ||
1466 | case PROCESSOR_PPC604e: | |
1467 | rs6000_cost = &ppc604e_cost; | |
1468 | break; | |
1469 | ||
1470 | case PROCESSOR_PPC620: | |
8b897cfa RS |
1471 | rs6000_cost = &ppc620_cost; |
1472 | break; | |
1473 | ||
f0517163 RS |
1474 | case PROCESSOR_PPC630: |
1475 | rs6000_cost = &ppc630_cost; | |
1476 | break; | |
1477 | ||
8b897cfa RS |
1478 | case PROCESSOR_PPC750: |
1479 | case PROCESSOR_PPC7400: | |
1480 | rs6000_cost = &ppc750_cost; | |
1481 | break; | |
1482 | ||
1483 | case PROCESSOR_PPC7450: | |
1484 | rs6000_cost = &ppc7450_cost; | |
1485 | break; | |
1486 | ||
1487 | case PROCESSOR_PPC8540: | |
1488 | rs6000_cost = &ppc8540_cost; | |
1489 | break; | |
1490 | ||
1491 | case PROCESSOR_POWER4: | |
1492 | case PROCESSOR_POWER5: | |
1493 | rs6000_cost = &power4_cost; | |
1494 | break; | |
1495 | ||
1496 | default: | |
1497 | abort (); | |
1498 | } | |
5248c961 | 1499 | } |
5accd822 | 1500 | |
5da702b1 AH |
1501 | /* Handle generic options of the form -mfoo=yes/no. |
1502 | NAME is the option name. | |
1503 | VALUE is the option value. | |
1504 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
1505 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 1506 | static void |
5da702b1 | 1507 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 1508 | { |
5da702b1 | 1509 | if (value == 0) |
993f19a8 | 1510 | return; |
5da702b1 AH |
1511 | else if (!strcmp (value, "yes")) |
1512 | *flag = 1; | |
1513 | else if (!strcmp (value, "no")) | |
1514 | *flag = 0; | |
08b57fb3 | 1515 | else |
5da702b1 | 1516 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
1517 | } |
1518 | ||
0ac081f6 | 1519 | /* Handle -mabi= options. */ |
00b960c7 | 1520 | static void |
863d938c | 1521 | rs6000_parse_abi_options (void) |
0ac081f6 AH |
1522 | { |
1523 | if (rs6000_abi_string == 0) | |
1524 | return; | |
1525 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
5cc73f91 AH |
1526 | { |
1527 | rs6000_altivec_abi = 1; | |
1528 | rs6000_spe_abi = 0; | |
1529 | } | |
76a773f3 AH |
1530 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
1531 | rs6000_altivec_abi = 0; | |
a3170dc6 | 1532 | else if (! strcmp (rs6000_abi_string, "spe")) |
01f4962d NS |
1533 | { |
1534 | rs6000_spe_abi = 1; | |
5cc73f91 | 1535 | rs6000_altivec_abi = 0; |
01f4962d NS |
1536 | if (!TARGET_SPE_ABI) |
1537 | error ("not configured for ABI: '%s'", rs6000_abi_string); | |
1538 | } | |
1539 | ||
a3170dc6 AH |
1540 | else if (! strcmp (rs6000_abi_string, "no-spe")) |
1541 | rs6000_spe_abi = 0; | |
0ac081f6 | 1542 | else |
c725bd79 | 1543 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
1544 | } |
1545 | ||
025d9908 KH |
1546 | /* Handle -malign-XXXXXX options. */ |
1547 | static void | |
863d938c | 1548 | rs6000_parse_alignment_option (void) |
025d9908 | 1549 | { |
b20a9cca AM |
1550 | if (rs6000_alignment_string == 0) |
1551 | return; | |
1552 | else if (! strcmp (rs6000_alignment_string, "power")) | |
025d9908 KH |
1553 | rs6000_alignment_flags = MASK_ALIGN_POWER; |
1554 | else if (! strcmp (rs6000_alignment_string, "natural")) | |
1555 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
1556 | else | |
1557 | error ("unknown -malign-XXXXX option specified: '%s'", | |
1558 | rs6000_alignment_string); | |
1559 | } | |
1560 | ||
c4501e62 JJ |
1561 | /* Validate and record the size specified with the -mtls-size option. */ |
1562 | ||
1563 | static void | |
863d938c | 1564 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
1565 | { |
1566 | if (rs6000_tls_size_string == 0) | |
1567 | return; | |
1568 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
1569 | rs6000_tls_size = 16; | |
1570 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
1571 | rs6000_tls_size = 32; | |
1572 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
1573 | rs6000_tls_size = 64; | |
1574 | else | |
1575 | error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string); | |
1576 | } | |
1577 | ||
5accd822 | 1578 | void |
a2369ed3 | 1579 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 1580 | { |
5accd822 | 1581 | } |
3cfa4909 MM |
1582 | \f |
1583 | /* Do anything needed at the start of the asm file. */ | |
1584 | ||
1bc7c5b6 | 1585 | static void |
863d938c | 1586 | rs6000_file_start (void) |
3cfa4909 | 1587 | { |
c4d38ccb | 1588 | size_t i; |
3cfa4909 | 1589 | char buffer[80]; |
d330fd93 | 1590 | const char *start = buffer; |
3cfa4909 | 1591 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
1592 | const char *default_cpu = TARGET_CPU_DEFAULT; |
1593 | FILE *file = asm_out_file; | |
1594 | ||
1595 | default_file_start (); | |
1596 | ||
1597 | #ifdef TARGET_BI_ARCH | |
1598 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
1599 | default_cpu = 0; | |
1600 | #endif | |
3cfa4909 MM |
1601 | |
1602 | if (flag_verbose_asm) | |
1603 | { | |
1604 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
1605 | rs6000_select[0].string = default_cpu; | |
1606 | ||
b6a1cbae | 1607 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
1608 | { |
1609 | ptr = &rs6000_select[i]; | |
1610 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
1611 | { | |
1612 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
1613 | start = ""; | |
1614 | } | |
1615 | } | |
1616 | ||
b91da81f | 1617 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
1618 | switch (rs6000_sdata) |
1619 | { | |
1620 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
1621 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
1622 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
1623 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
1624 | } | |
1625 | ||
1626 | if (rs6000_sdata && g_switch_value) | |
1627 | { | |
307b599c MK |
1628 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
1629 | g_switch_value); | |
3cfa4909 MM |
1630 | start = ""; |
1631 | } | |
1632 | #endif | |
1633 | ||
1634 | if (*start == '\0') | |
949ea356 | 1635 | putc ('\n', file); |
3cfa4909 MM |
1636 | } |
1637 | } | |
5248c961 | 1638 | \f |
a0ab749a | 1639 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1640 | |
1641 | int | |
863d938c | 1642 | direct_return (void) |
9878760c | 1643 | { |
4697a36c MM |
1644 | if (reload_completed) |
1645 | { | |
1646 | rs6000_stack_t *info = rs6000_stack_info (); | |
1647 | ||
1648 | if (info->first_gp_reg_save == 32 | |
1649 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1650 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1651 | && ! info->lr_save_p |
1652 | && ! info->cr_save_p | |
00b960c7 | 1653 | && info->vrsave_mask == 0 |
c81fc13e | 1654 | && ! info->push_p) |
4697a36c MM |
1655 | return 1; |
1656 | } | |
1657 | ||
1658 | return 0; | |
9878760c RK |
1659 | } |
1660 | ||
1661 | /* Returns 1 always. */ | |
1662 | ||
1663 | int | |
a2369ed3 DJ |
1664 | any_operand (rtx op ATTRIBUTE_UNUSED, |
1665 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
9878760c RK |
1666 | { |
1667 | return 1; | |
1668 | } | |
1669 | ||
a4f6c312 | 1670 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 1671 | int |
a2369ed3 | 1672 | count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
b6c9286a MM |
1673 | { |
1674 | if (GET_CODE (op) != REG) | |
1675 | return 0; | |
1676 | ||
1677 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
1678 | return 1; | |
1679 | ||
1680 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
1681 | return 1; | |
1682 | ||
1683 | return 0; | |
1684 | } | |
1685 | ||
0ec4e2a8 AH |
1686 | /* Returns 1 if op is an altivec register. */ |
1687 | int | |
a2369ed3 | 1688 | altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ec4e2a8 AH |
1689 | { |
1690 | ||
1691 | return (register_operand (op, mode) | |
1692 | && (GET_CODE (op) != REG | |
1693 | || REGNO (op) > FIRST_PSEUDO_REGISTER | |
1694 | || ALTIVEC_REGNO_P (REGNO (op)))); | |
1695 | } | |
1696 | ||
38c1f2d7 | 1697 | int |
a2369ed3 | 1698 | xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
802a0058 MM |
1699 | { |
1700 | if (GET_CODE (op) != REG) | |
1701 | return 0; | |
1702 | ||
9ebbca7d | 1703 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
1704 | return 1; |
1705 | ||
802a0058 MM |
1706 | return 0; |
1707 | } | |
1708 | ||
c859cda6 | 1709 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 1710 | by such constants completes more quickly. */ |
c859cda6 DJ |
1711 | |
1712 | int | |
a2369ed3 | 1713 | s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c859cda6 DJ |
1714 | { |
1715 | return ( GET_CODE (op) == CONST_INT | |
1716 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); | |
1717 | } | |
1718 | ||
9878760c RK |
1719 | /* Return 1 if OP is a constant that can fit in a D field. */ |
1720 | ||
1721 | int | |
a2369ed3 | 1722 | short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1723 | { |
5f59ecb7 DE |
1724 | return (GET_CODE (op) == CONST_INT |
1725 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
1726 | } |
1727 | ||
5519a4f9 | 1728 | /* Similar for an unsigned D field. */ |
9878760c RK |
1729 | |
1730 | int | |
a2369ed3 | 1731 | u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1732 | { |
19684119 | 1733 | return (GET_CODE (op) == CONST_INT |
c1f11548 | 1734 | && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K')); |
9878760c RK |
1735 | } |
1736 | ||
dcfedcd0 RK |
1737 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
1738 | ||
1739 | int | |
a2369ed3 | 1740 | non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
1741 | { |
1742 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1743 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
1744 | } |
1745 | ||
2bfcf297 DB |
1746 | /* Returns 1 if OP is a CONST_INT that is a positive value |
1747 | and an exact power of 2. */ | |
1748 | ||
1749 | int | |
a2369ed3 | 1750 | exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bfcf297 DB |
1751 | { |
1752 | return (GET_CODE (op) == CONST_INT | |
1753 | && INTVAL (op) > 0 | |
1754 | && exact_log2 (INTVAL (op)) >= 0); | |
1755 | } | |
1756 | ||
9878760c RK |
1757 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
1758 | ctr, or lr). */ | |
1759 | ||
1760 | int | |
a2369ed3 | 1761 | gpc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1762 | { |
1763 | return (register_operand (op, mode) | |
802a0058 | 1764 | && (GET_CODE (op) != REG |
9ebbca7d GK |
1765 | || (REGNO (op) >= ARG_POINTER_REGNUM |
1766 | && !XER_REGNO_P (REGNO (op))) | |
1767 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
1768 | } |
1769 | ||
1770 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
1771 | CR field. */ | |
1772 | ||
1773 | int | |
a2369ed3 | 1774 | cc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1775 | { |
1776 | return (register_operand (op, mode) | |
1777 | && (GET_CODE (op) != REG | |
1778 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1779 | || CR_REGNO_P (REGNO (op)))); | |
1780 | } | |
1781 | ||
815cdc52 MM |
1782 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
1783 | CR field that isn't CR0. */ | |
1784 | ||
1785 | int | |
a2369ed3 | 1786 | cc_reg_not_cr0_operand (rtx op, enum machine_mode mode) |
815cdc52 MM |
1787 | { |
1788 | return (register_operand (op, mode) | |
1789 | && (GET_CODE (op) != REG | |
1790 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1791 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
1792 | } | |
1793 | ||
a4f6c312 SS |
1794 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
1795 | a non-special register. If a register, it must be in the proper | |
1796 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
1797 | |
1798 | int | |
a2369ed3 | 1799 | reg_or_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1800 | { |
f5a28898 | 1801 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1802 | } |
1803 | ||
a4f6c312 | 1804 | /* Similar, except check if the negation of the constant would be |
42f806e5 AM |
1805 | valid for a D-field. Don't allow a constant zero, since all the |
1806 | patterns that call this predicate use "addic r1,r2,-constant" on | |
1807 | a constant value to set a carry when r2 is greater or equal to | |
1808 | "constant". That doesn't work for zero. */ | |
9878760c RK |
1809 | |
1810 | int | |
a2369ed3 | 1811 | reg_or_neg_short_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1812 | { |
1813 | if (GET_CODE (op) == CONST_INT) | |
42f806e5 | 1814 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0; |
9878760c | 1815 | |
cd2b37d9 | 1816 | return gpc_reg_operand (op, mode); |
9878760c RK |
1817 | } |
1818 | ||
768070a0 TR |
1819 | /* Returns 1 if OP is either a constant integer valid for a DS-field or |
1820 | a non-special register. If a register, it must be in the proper | |
1821 | mode unless MODE is VOIDmode. */ | |
1822 | ||
1823 | int | |
a2369ed3 | 1824 | reg_or_aligned_short_operand (rtx op, enum machine_mode mode) |
768070a0 TR |
1825 | { |
1826 | if (gpc_reg_operand (op, mode)) | |
1827 | return 1; | |
1828 | else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3)) | |
1829 | return 1; | |
1830 | ||
1831 | return 0; | |
1832 | } | |
1833 | ||
1834 | ||
a4f6c312 SS |
1835 | /* Return 1 if the operand is either a register or an integer whose |
1836 | high-order 16 bits are zero. */ | |
9878760c RK |
1837 | |
1838 | int | |
a2369ed3 | 1839 | reg_or_u_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1840 | { |
e675f625 | 1841 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1842 | } |
1843 | ||
1844 | /* Return 1 is the operand is either a non-special register or ANY | |
1845 | constant integer. */ | |
1846 | ||
1847 | int | |
a2369ed3 | 1848 | reg_or_cint_operand (rtx op, enum machine_mode mode) |
9878760c | 1849 | { |
a4f6c312 | 1850 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
1851 | } |
1852 | ||
1853 | /* Return 1 is the operand is either a non-special register or ANY | |
1854 | 32-bit signed constant integer. */ | |
1855 | ||
1856 | int | |
a2369ed3 | 1857 | reg_or_arith_cint_operand (rtx op, enum machine_mode mode) |
f6bf7de2 | 1858 | { |
a4f6c312 SS |
1859 | return (gpc_reg_operand (op, mode) |
1860 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 1861 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
1862 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
1863 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 1864 | #endif |
a4f6c312 | 1865 | )); |
9878760c RK |
1866 | } |
1867 | ||
2bfcf297 DB |
1868 | /* Return 1 is the operand is either a non-special register or a 32-bit |
1869 | signed constant integer valid for 64-bit addition. */ | |
1870 | ||
1871 | int | |
a2369ed3 | 1872 | reg_or_add_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 1873 | { |
a4f6c312 SS |
1874 | return (gpc_reg_operand (op, mode) |
1875 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1876 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1877 | && INTVAL (op) < 0x7fff8000 |
a65c591c | 1878 | #else |
a4f6c312 SS |
1879 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
1880 | < 0x100000000ll) | |
2bfcf297 | 1881 | #endif |
a4f6c312 | 1882 | )); |
2bfcf297 DB |
1883 | } |
1884 | ||
1885 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
1886 | signed constant integer valid for 64-bit subtraction. */ | |
1887 | ||
1888 | int | |
a2369ed3 | 1889 | reg_or_sub_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 1890 | { |
a4f6c312 SS |
1891 | return (gpc_reg_operand (op, mode) |
1892 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1893 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1894 | && (- INTVAL (op)) < 0x7fff8000 |
a65c591c | 1895 | #else |
a4f6c312 SS |
1896 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
1897 | < 0x100000000ll) | |
2bfcf297 | 1898 | #endif |
a4f6c312 | 1899 | )); |
2bfcf297 DB |
1900 | } |
1901 | ||
9ebbca7d GK |
1902 | /* Return 1 is the operand is either a non-special register or ANY |
1903 | 32-bit unsigned constant integer. */ | |
1904 | ||
1905 | int | |
a2369ed3 | 1906 | reg_or_logical_cint_operand (rtx op, enum machine_mode mode) |
9ebbca7d | 1907 | { |
1d328b19 GK |
1908 | if (GET_CODE (op) == CONST_INT) |
1909 | { | |
1910 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
1911 | { | |
1912 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 1913 | abort (); |
1d328b19 GK |
1914 | |
1915 | if (INTVAL (op) < 0) | |
1916 | return 0; | |
1917 | } | |
1918 | ||
1919 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 1920 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
1921 | } |
1922 | else if (GET_CODE (op) == CONST_DOUBLE) | |
1923 | { | |
1924 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
1925 | || mode != DImode) | |
a4f6c312 | 1926 | abort (); |
1d328b19 GK |
1927 | |
1928 | return CONST_DOUBLE_HIGH (op) == 0; | |
1929 | } | |
1930 | else | |
1931 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
1932 | } |
1933 | ||
51d3e7d6 | 1934 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
1935 | |
1936 | int | |
a2369ed3 | 1937 | got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
766a866c MM |
1938 | { |
1939 | return (GET_CODE (op) == SYMBOL_REF | |
1940 | || GET_CODE (op) == CONST | |
1941 | || GET_CODE (op) == LABEL_REF); | |
1942 | } | |
1943 | ||
38c1f2d7 MM |
1944 | /* Return 1 if the operand is a simple references that can be loaded via |
1945 | the GOT (labels involving addition aren't allowed). */ | |
1946 | ||
1947 | int | |
a2369ed3 | 1948 | got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
38c1f2d7 MM |
1949 | { |
1950 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
1951 | } | |
1952 | ||
4e74d8ec MM |
1953 | /* Return the number of instructions it takes to form a constant in an |
1954 | integer register. */ | |
1955 | ||
1956 | static int | |
a2369ed3 | 1957 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
1958 | { |
1959 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1960 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1961 | return 1; |
1962 | ||
4e74d8ec | 1963 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1964 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1965 | return 1; |
1966 | ||
5f59ecb7 | 1967 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1968 | else if (TARGET_POWERPC64) |
4e74d8ec | 1969 | { |
a65c591c DE |
1970 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1971 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 1972 | |
a65c591c | 1973 | if (high == 0 || high == -1) |
4e74d8ec MM |
1974 | return 2; |
1975 | ||
a65c591c | 1976 | high >>= 1; |
4e74d8ec | 1977 | |
a65c591c | 1978 | if (low == 0) |
4e74d8ec | 1979 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
1980 | else |
1981 | return (num_insns_constant_wide (high) | |
e396202a | 1982 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1983 | } |
1984 | #endif | |
1985 | ||
1986 | else | |
1987 | return 2; | |
1988 | } | |
1989 | ||
1990 | int | |
a2369ed3 | 1991 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 1992 | { |
4e74d8ec | 1993 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
1994 | { |
1995 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
1996 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1997 | && mask64_operand (op, mode)) | |
0d30d435 DE |
1998 | return 2; |
1999 | else | |
2000 | #endif | |
2001 | return num_insns_constant_wide (INTVAL (op)); | |
2002 | } | |
4e74d8ec | 2003 | |
6fc48950 MM |
2004 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
2005 | { | |
2006 | long l; | |
2007 | REAL_VALUE_TYPE rv; | |
2008 | ||
2009 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2010 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
e72247f4 | 2011 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
6fc48950 MM |
2012 | } |
2013 | ||
47ad8c61 | 2014 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 2015 | { |
47ad8c61 MM |
2016 | HOST_WIDE_INT low; |
2017 | HOST_WIDE_INT high; | |
2018 | long l[2]; | |
2019 | REAL_VALUE_TYPE rv; | |
2020 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 2021 | |
47ad8c61 MM |
2022 | if (mode == VOIDmode || mode == DImode) |
2023 | { | |
2024 | high = CONST_DOUBLE_HIGH (op); | |
2025 | low = CONST_DOUBLE_LOW (op); | |
2026 | } | |
2027 | else | |
2028 | { | |
2029 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2030 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
2031 | high = l[endian]; | |
2032 | low = l[1 - endian]; | |
2033 | } | |
4e74d8ec | 2034 | |
47ad8c61 MM |
2035 | if (TARGET_32BIT) |
2036 | return (num_insns_constant_wide (low) | |
2037 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
2038 | |
2039 | else | |
47ad8c61 | 2040 | { |
e72247f4 | 2041 | if (high == 0 && low >= 0) |
47ad8c61 MM |
2042 | return num_insns_constant_wide (low); |
2043 | ||
e72247f4 | 2044 | else if (high == -1 && low < 0) |
47ad8c61 MM |
2045 | return num_insns_constant_wide (low); |
2046 | ||
a260abc9 DE |
2047 | else if (mask64_operand (op, mode)) |
2048 | return 2; | |
2049 | ||
47ad8c61 MM |
2050 | else if (low == 0) |
2051 | return num_insns_constant_wide (high) + 1; | |
2052 | ||
2053 | else | |
2054 | return (num_insns_constant_wide (high) | |
2055 | + num_insns_constant_wide (low) + 1); | |
2056 | } | |
4e74d8ec MM |
2057 | } |
2058 | ||
2059 | else | |
2060 | abort (); | |
2061 | } | |
2062 | ||
a4f6c312 SS |
2063 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
2064 | register with one instruction per word. We only do this if we can | |
2065 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
2066 | |
2067 | int | |
a2369ed3 | 2068 | easy_fp_constant (rtx op, enum machine_mode mode) |
9878760c | 2069 | { |
9878760c RK |
2070 | if (GET_CODE (op) != CONST_DOUBLE |
2071 | || GET_MODE (op) != mode | |
4e74d8ec | 2072 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
2073 | return 0; |
2074 | ||
a4f6c312 | 2075 | /* Consider all constants with -msoft-float to be easy. */ |
a3170dc6 AH |
2076 | if ((TARGET_SOFT_FLOAT || !TARGET_FPRS) |
2077 | && mode != DImode) | |
b6c9286a MM |
2078 | return 1; |
2079 | ||
a4f6c312 | 2080 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 2081 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
2082 | return 0; |
2083 | ||
5ae4759c | 2084 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
2085 | /* Similarly if we are using -mrelocatable, consider all constants |
2086 | to be hard. */ | |
5ae4759c MM |
2087 | if (TARGET_RELOCATABLE) |
2088 | return 0; | |
2089 | #endif | |
2090 | ||
fcce224d DE |
2091 | if (mode == TFmode) |
2092 | { | |
2093 | long k[4]; | |
2094 | REAL_VALUE_TYPE rv; | |
2095 | ||
2096 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2097 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
2098 | ||
2099 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
2100 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
2101 | && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
2102 | && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
2103 | } | |
2104 | ||
2105 | else if (mode == DFmode) | |
042259f2 DE |
2106 | { |
2107 | long k[2]; | |
2108 | REAL_VALUE_TYPE rv; | |
2109 | ||
2110 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2111 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 2112 | |
a65c591c DE |
2113 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 |
2114 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
042259f2 | 2115 | } |
4e74d8ec MM |
2116 | |
2117 | else if (mode == SFmode) | |
042259f2 DE |
2118 | { |
2119 | long l; | |
2120 | REAL_VALUE_TYPE rv; | |
2121 | ||
2122 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2123 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 2124 | |
4e74d8ec | 2125 | return num_insns_constant_wide (l) == 1; |
042259f2 | 2126 | } |
4e74d8ec | 2127 | |
a260abc9 | 2128 | else if (mode == DImode) |
c81fc13e | 2129 | return ((TARGET_POWERPC64 |
a260abc9 DE |
2130 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
2131 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 2132 | |
a9098fd0 GK |
2133 | else if (mode == SImode) |
2134 | return 1; | |
4e74d8ec MM |
2135 | else |
2136 | abort (); | |
9878760c | 2137 | } |
8f75773e | 2138 | |
effa5d5d | 2139 | /* Returns the constant for the splat instruction, if exists. */ |
452a7d36 HP |
2140 | |
2141 | static int | |
2142 | easy_vector_splat_const (int cst, enum machine_mode mode) | |
2143 | { | |
2144 | switch (mode) | |
2145 | { | |
2146 | case V4SImode: | |
2147 | if (EASY_VECTOR_15 (cst) | |
2148 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
2149 | return cst; | |
2150 | if ((cst & 0xffff) != ((cst >> 16) & 0xffff)) | |
2151 | break; | |
2152 | cst = cst >> 16; | |
2153 | case V8HImode: | |
2154 | if (EASY_VECTOR_15 (cst) | |
2155 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
2156 | return cst; | |
2157 | if ((cst & 0xff) != ((cst >> 8) & 0xff)) | |
2158 | break; | |
2159 | cst = cst >> 8; | |
2160 | case V16QImode: | |
2161 | if (EASY_VECTOR_15 (cst) | |
2162 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
2163 | return cst; | |
2164 | default: | |
2165 | break; | |
2166 | } | |
2167 | return 0; | |
2168 | } | |
2169 | ||
2170 | ||
72ac76be | 2171 | /* Return nonzero if all elements of a vector have the same value. */ |
69ef87e2 AH |
2172 | |
2173 | static int | |
a2369ed3 | 2174 | easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d744e06e AH |
2175 | { |
2176 | int units, i, cst; | |
2177 | ||
2178 | units = CONST_VECTOR_NUNITS (op); | |
2179 | ||
2180 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
2181 | for (i = 1; i < units; ++i) | |
2182 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
2183 | break; | |
452a7d36 | 2184 | if (i == units && easy_vector_splat_const (cst, mode)) |
d744e06e AH |
2185 | return 1; |
2186 | return 0; | |
2187 | } | |
2188 | ||
2189 | /* Return 1 if the operand is a CONST_INT and can be put into a | |
2190 | register without using memory. */ | |
2191 | ||
2192 | int | |
a2369ed3 | 2193 | easy_vector_constant (rtx op, enum machine_mode mode) |
69ef87e2 | 2194 | { |
d744e06e | 2195 | int cst, cst2; |
69ef87e2 | 2196 | |
d744e06e AH |
2197 | if (GET_CODE (op) != CONST_VECTOR |
2198 | || (!TARGET_ALTIVEC | |
2199 | && !TARGET_SPE)) | |
69ef87e2 AH |
2200 | return 0; |
2201 | ||
d744e06e AH |
2202 | if (zero_constant (op, mode) |
2203 | && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
2204 | || (TARGET_SPE && SPE_VECTOR_MODE (mode)))) | |
2205 | return 1; | |
69ef87e2 | 2206 | |
d744e06e AH |
2207 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) |
2208 | return 0; | |
2209 | ||
f5119d10 AH |
2210 | if (TARGET_SPE && mode == V1DImode) |
2211 | return 0; | |
2212 | ||
d744e06e AH |
2213 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); |
2214 | cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
2215 | ||
2216 | /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
2217 | li r0, CONSTANT1 | |
2218 | evmergelo r0, r0, r0 | |
2219 | li r0, CONSTANT2 | |
2220 | ||
2221 | I don't know how efficient it would be to allow bigger constants, | |
2222 | considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
2223 | instructions is better than a 64-bit memory load, but I don't | |
2224 | have the e500 timing specs. */ | |
2225 | if (TARGET_SPE && mode == V2SImode | |
2226 | && cst >= -0x7fff && cst <= 0x7fff | |
f5119d10 | 2227 | && cst2 >= -0x7fff && cst2 <= 0x7fff) |
d744e06e AH |
2228 | return 1; |
2229 | ||
452a7d36 HP |
2230 | if (TARGET_ALTIVEC |
2231 | && easy_vector_same (op, mode)) | |
2232 | { | |
2233 | cst = easy_vector_splat_const (cst, mode); | |
2234 | if (EASY_VECTOR_15_ADD_SELF (cst) | |
2235 | || EASY_VECTOR_15 (cst)) | |
2236 | return 1; | |
2237 | } | |
d744e06e AH |
2238 | return 0; |
2239 | } | |
2240 | ||
2241 | /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */ | |
2242 | ||
2243 | int | |
a2369ed3 | 2244 | easy_vector_constant_add_self (rtx op, enum machine_mode mode) |
d744e06e AH |
2245 | { |
2246 | int cst; | |
452a7d36 HP |
2247 | if (TARGET_ALTIVEC |
2248 | && GET_CODE (op) == CONST_VECTOR | |
2249 | && easy_vector_same (op, mode)) | |
2250 | { | |
2251 | cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode); | |
2252 | if (EASY_VECTOR_15_ADD_SELF (cst)) | |
2253 | return 1; | |
2254 | } | |
2255 | return 0; | |
2256 | } | |
d744e06e | 2257 | |
452a7d36 | 2258 | /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */ |
d744e06e | 2259 | |
452a7d36 HP |
2260 | rtx |
2261 | gen_easy_vector_constant_add_self (rtx op) | |
2262 | { | |
2263 | int i, units; | |
2264 | rtvec v; | |
2265 | units = GET_MODE_NUNITS (GET_MODE (op)); | |
2266 | v = rtvec_alloc (units); | |
2267 | ||
2268 | for (i = 0; i < units; i++) | |
2269 | RTVEC_ELT (v, i) = | |
2270 | GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1); | |
2271 | return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v); | |
d744e06e AH |
2272 | } |
2273 | ||
2274 | const char * | |
a2369ed3 | 2275 | output_vec_const_move (rtx *operands) |
d744e06e AH |
2276 | { |
2277 | int cst, cst2; | |
2278 | enum machine_mode mode; | |
2279 | rtx dest, vec; | |
2280 | ||
2281 | dest = operands[0]; | |
2282 | vec = operands[1]; | |
69ef87e2 | 2283 | |
d744e06e AH |
2284 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
2285 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
2286 | mode = GET_MODE (dest); | |
69ef87e2 | 2287 | |
d744e06e AH |
2288 | if (TARGET_ALTIVEC) |
2289 | { | |
2290 | if (zero_constant (vec, mode)) | |
2291 | return "vxor %0,%0,%0"; | |
ce1f50b2 | 2292 | else if (easy_vector_constant (vec, mode)) |
98ef3137 | 2293 | { |
d744e06e AH |
2294 | operands[1] = GEN_INT (cst); |
2295 | switch (mode) | |
2296 | { | |
2297 | case V4SImode: | |
452a7d36 | 2298 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2299 | { |
2300 | operands[1] = GEN_INT (cst); | |
2301 | return "vspltisw %0,%1"; | |
2302 | } | |
452a7d36 HP |
2303 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2304 | return "#"; | |
ce1f50b2 | 2305 | cst = cst >> 16; |
d744e06e | 2306 | case V8HImode: |
452a7d36 | 2307 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2308 | { |
2309 | operands[1] = GEN_INT (cst); | |
2310 | return "vspltish %0,%1"; | |
2311 | } | |
452a7d36 HP |
2312 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2313 | return "#"; | |
ce1f50b2 | 2314 | cst = cst >> 8; |
d744e06e | 2315 | case V16QImode: |
452a7d36 | 2316 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2317 | { |
2318 | operands[1] = GEN_INT (cst); | |
2319 | return "vspltisb %0,%1"; | |
2320 | } | |
452a7d36 HP |
2321 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2322 | return "#"; | |
d744e06e AH |
2323 | default: |
2324 | abort (); | |
2325 | } | |
98ef3137 | 2326 | } |
d744e06e AH |
2327 | else |
2328 | abort (); | |
69ef87e2 AH |
2329 | } |
2330 | ||
d744e06e AH |
2331 | if (TARGET_SPE) |
2332 | { | |
2333 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
2334 | pattern of V1DI, V4HI, and V2SF. | |
2335 | ||
c1207243 | 2336 | FIXME: We should probably return # and add post reload |
d744e06e AH |
2337 | splitters for these, but this way is so easy ;-). |
2338 | */ | |
2339 | operands[1] = GEN_INT (cst); | |
2340 | operands[2] = GEN_INT (cst2); | |
2341 | if (cst == cst2) | |
2342 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
2343 | else | |
2344 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
2345 | } | |
2346 | ||
2347 | abort (); | |
69ef87e2 AH |
2348 | } |
2349 | ||
2350 | /* Return 1 if the operand is the constant 0. This works for scalars | |
2351 | as well as vectors. */ | |
2352 | int | |
a2369ed3 | 2353 | zero_constant (rtx op, enum machine_mode mode) |
69ef87e2 AH |
2354 | { |
2355 | return op == CONST0_RTX (mode); | |
2356 | } | |
2357 | ||
50a0b056 GK |
2358 | /* Return 1 if the operand is 0.0. */ |
2359 | int | |
a2369ed3 | 2360 | zero_fp_constant (rtx op, enum machine_mode mode) |
50a0b056 GK |
2361 | { |
2362 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
2363 | } | |
2364 | ||
a4f6c312 SS |
2365 | /* Return 1 if the operand is in volatile memory. Note that during |
2366 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
2367 | volatile memory references. So this function allows us to |
2368 | recognize volatile references where its safe. */ | |
2369 | ||
2370 | int | |
a2369ed3 | 2371 | volatile_mem_operand (rtx op, enum machine_mode mode) |
b6c9286a MM |
2372 | { |
2373 | if (GET_CODE (op) != MEM) | |
2374 | return 0; | |
2375 | ||
2376 | if (!MEM_VOLATILE_P (op)) | |
2377 | return 0; | |
2378 | ||
2379 | if (mode != GET_MODE (op)) | |
2380 | return 0; | |
2381 | ||
2382 | if (reload_completed) | |
2383 | return memory_operand (op, mode); | |
2384 | ||
2385 | if (reload_in_progress) | |
2386 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
2387 | ||
2388 | return memory_address_p (mode, XEXP (op, 0)); | |
2389 | } | |
2390 | ||
97f6e72f | 2391 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
2392 | |
2393 | int | |
a2369ed3 | 2394 | offsettable_mem_operand (rtx op, enum machine_mode mode) |
914c2e77 | 2395 | { |
97f6e72f | 2396 | return ((GET_CODE (op) == MEM) |
677a9668 | 2397 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 2398 | mode, XEXP (op, 0))); |
914c2e77 RK |
2399 | } |
2400 | ||
9878760c RK |
2401 | /* Return 1 if the operand is either an easy FP constant (see above) or |
2402 | memory. */ | |
2403 | ||
2404 | int | |
a2369ed3 | 2405 | mem_or_easy_const_operand (rtx op, enum machine_mode mode) |
9878760c RK |
2406 | { |
2407 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
2408 | } | |
2409 | ||
2410 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 2411 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
2412 | |
2413 | int | |
a2369ed3 | 2414 | add_operand (rtx op, enum machine_mode mode) |
9878760c | 2415 | { |
2bfcf297 | 2416 | if (GET_CODE (op) == CONST_INT) |
e72247f4 DE |
2417 | return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
2418 | || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
2bfcf297 DB |
2419 | |
2420 | return gpc_reg_operand (op, mode); | |
9878760c RK |
2421 | } |
2422 | ||
dcfedcd0 RK |
2423 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
2424 | ||
2425 | int | |
a2369ed3 | 2426 | non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
2427 | { |
2428 | return (GET_CODE (op) == CONST_INT | |
e72247f4 DE |
2429 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
2430 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
dcfedcd0 RK |
2431 | } |
2432 | ||
9878760c RK |
2433 | /* Return 1 if the operand is a non-special register or a constant that |
2434 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
2435 | ||
2436 | int | |
a2369ed3 | 2437 | logical_operand (rtx op, enum machine_mode mode) |
9878760c | 2438 | { |
40501e5f | 2439 | HOST_WIDE_INT opl, oph; |
1d328b19 | 2440 | |
dfbdccdb GK |
2441 | if (gpc_reg_operand (op, mode)) |
2442 | return 1; | |
1d328b19 | 2443 | |
dfbdccdb | 2444 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
2445 | { |
2446 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
2447 | ||
2448 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
2449 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
2450 | return 0; | |
2451 | #endif | |
2452 | } | |
dfbdccdb GK |
2453 | else if (GET_CODE (op) == CONST_DOUBLE) |
2454 | { | |
1d328b19 | 2455 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 2456 | abort (); |
1d328b19 GK |
2457 | |
2458 | opl = CONST_DOUBLE_LOW (op); | |
2459 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 2460 | if (oph != 0) |
38886f37 | 2461 | return 0; |
dfbdccdb GK |
2462 | } |
2463 | else | |
2464 | return 0; | |
1d328b19 | 2465 | |
40501e5f AM |
2466 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
2467 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
2468 | } |
2469 | ||
dcfedcd0 | 2470 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 2471 | above), but could be split into one. */ |
dcfedcd0 RK |
2472 | |
2473 | int | |
a2369ed3 | 2474 | non_logical_cint_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 2475 | { |
dfbdccdb | 2476 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
2477 | && ! logical_operand (op, mode) |
2478 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
2479 | } |
2480 | ||
19ba8161 | 2481 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
2482 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
2483 | Reject all ones and all zeros, since these should have been optimized | |
2484 | away and confuse the making of MB and ME. */ | |
2485 | ||
2486 | int | |
a2369ed3 | 2487 | mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 2488 | { |
02071907 | 2489 | HOST_WIDE_INT c, lsb; |
9878760c | 2490 | |
19ba8161 DE |
2491 | if (GET_CODE (op) != CONST_INT) |
2492 | return 0; | |
2493 | ||
2494 | c = INTVAL (op); | |
2495 | ||
57deb3a1 AM |
2496 | /* Fail in 64-bit mode if the mask wraps around because the upper |
2497 | 32-bits of the mask will all be 1s, contrary to GCC's internal view. */ | |
2498 | if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001) | |
2499 | return 0; | |
2500 | ||
c5059423 AM |
2501 | /* We don't change the number of transitions by inverting, |
2502 | so make sure we start with the LS bit zero. */ | |
2503 | if (c & 1) | |
2504 | c = ~c; | |
2505 | ||
2506 | /* Reject all zeros or all ones. */ | |
2507 | if (c == 0) | |
9878760c RK |
2508 | return 0; |
2509 | ||
c5059423 AM |
2510 | /* Find the first transition. */ |
2511 | lsb = c & -c; | |
2512 | ||
2513 | /* Invert to look for a second transition. */ | |
2514 | c = ~c; | |
9878760c | 2515 | |
c5059423 AM |
2516 | /* Erase first transition. */ |
2517 | c &= -lsb; | |
9878760c | 2518 | |
c5059423 AM |
2519 | /* Find the second transition (if any). */ |
2520 | lsb = c & -c; | |
2521 | ||
2522 | /* Match if all the bits above are 1's (or c is zero). */ | |
2523 | return c == -lsb; | |
9878760c RK |
2524 | } |
2525 | ||
0ba1b2ff AM |
2526 | /* Return 1 for the PowerPC64 rlwinm corner case. */ |
2527 | ||
2528 | int | |
a2369ed3 | 2529 | mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ba1b2ff AM |
2530 | { |
2531 | HOST_WIDE_INT c, lsb; | |
2532 | ||
2533 | if (GET_CODE (op) != CONST_INT) | |
2534 | return 0; | |
2535 | ||
2536 | c = INTVAL (op); | |
2537 | ||
2538 | if ((c & 0x80000001) != 0x80000001) | |
2539 | return 0; | |
2540 | ||
2541 | c = ~c; | |
2542 | if (c == 0) | |
2543 | return 0; | |
2544 | ||
2545 | lsb = c & -c; | |
2546 | c = ~c; | |
2547 | c &= -lsb; | |
2548 | lsb = c & -c; | |
2549 | return c == -lsb; | |
2550 | } | |
2551 | ||
a260abc9 DE |
2552 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
2553 | It is if there are no more than one 1->0 or 0->1 transitions. | |
0ba1b2ff AM |
2554 | Reject all zeros, since zero should have been optimized away and |
2555 | confuses the making of MB and ME. */ | |
9878760c RK |
2556 | |
2557 | int | |
a2369ed3 | 2558 | mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
a260abc9 DE |
2559 | { |
2560 | if (GET_CODE (op) == CONST_INT) | |
2561 | { | |
02071907 | 2562 | HOST_WIDE_INT c, lsb; |
a260abc9 | 2563 | |
c5059423 | 2564 | c = INTVAL (op); |
a260abc9 | 2565 | |
0ba1b2ff | 2566 | /* Reject all zeros. */ |
c5059423 | 2567 | if (c == 0) |
e2c953b6 DE |
2568 | return 0; |
2569 | ||
0ba1b2ff AM |
2570 | /* We don't change the number of transitions by inverting, |
2571 | so make sure we start with the LS bit zero. */ | |
2572 | if (c & 1) | |
2573 | c = ~c; | |
2574 | ||
c5059423 AM |
2575 | /* Find the transition, and check that all bits above are 1's. */ |
2576 | lsb = c & -c; | |
e3981aab DE |
2577 | |
2578 | /* Match if all the bits above are 1's (or c is zero). */ | |
c5059423 | 2579 | return c == -lsb; |
e2c953b6 | 2580 | } |
0ba1b2ff AM |
2581 | return 0; |
2582 | } | |
2583 | ||
2584 | /* Like mask64_operand, but allow up to three transitions. This | |
2585 | predicate is used by insn patterns that generate two rldicl or | |
2586 | rldicr machine insns. */ | |
2587 | ||
2588 | int | |
a2369ed3 | 2589 | mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ba1b2ff AM |
2590 | { |
2591 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 2592 | { |
0ba1b2ff | 2593 | HOST_WIDE_INT c, lsb; |
a260abc9 | 2594 | |
0ba1b2ff | 2595 | c = INTVAL (op); |
a260abc9 | 2596 | |
0ba1b2ff AM |
2597 | /* Disallow all zeros. */ |
2598 | if (c == 0) | |
2599 | return 0; | |
a260abc9 | 2600 | |
0ba1b2ff AM |
2601 | /* We don't change the number of transitions by inverting, |
2602 | so make sure we start with the LS bit zero. */ | |
2603 | if (c & 1) | |
2604 | c = ~c; | |
a260abc9 | 2605 | |
0ba1b2ff AM |
2606 | /* Find the first transition. */ |
2607 | lsb = c & -c; | |
a260abc9 | 2608 | |
0ba1b2ff AM |
2609 | /* Invert to look for a second transition. */ |
2610 | c = ~c; | |
2611 | ||
2612 | /* Erase first transition. */ | |
2613 | c &= -lsb; | |
2614 | ||
2615 | /* Find the second transition. */ | |
2616 | lsb = c & -c; | |
2617 | ||
2618 | /* Invert to look for a third transition. */ | |
2619 | c = ~c; | |
2620 | ||
2621 | /* Erase second transition. */ | |
2622 | c &= -lsb; | |
2623 | ||
2624 | /* Find the third transition (if any). */ | |
2625 | lsb = c & -c; | |
2626 | ||
2627 | /* Match if all the bits above are 1's (or c is zero). */ | |
2628 | return c == -lsb; | |
2629 | } | |
2630 | return 0; | |
2631 | } | |
2632 | ||
2633 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to | |
2634 | implement ANDing by the mask IN. */ | |
2635 | void | |
a2369ed3 | 2636 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
2637 | { |
2638 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2639 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2640 | int shift; | |
2641 | ||
2642 | if (GET_CODE (in) != CONST_INT) | |
2643 | abort (); | |
2644 | ||
2645 | c = INTVAL (in); | |
2646 | if (c & 1) | |
2647 | { | |
2648 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2649 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2650 | is at the MS end and can be cleared with an rldicl mask. We then | |
2651 | rotate back and clear off the MS ^^ group of zeros with a | |
2652 | second rldicl. */ | |
2653 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2654 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2655 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2656 | c = ~c; /* c == 0x00fff000000fffff */ | |
2657 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2658 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2659 | c = ~c; /* c == 0xff000fffffffffff */ | |
2660 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2661 | shift = 0; | |
2662 | while ((lsb >>= 1) != 0) | |
2663 | shift++; /* shift == 44 on exit from loop */ | |
2664 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2665 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2666 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2667 | } |
2668 | else | |
0ba1b2ff AM |
2669 | { |
2670 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2671 | is to rotate the word so that the ^^^ middle group of zeros | |
2672 | is at the LS end and can be cleared with an rldicr mask. We then | |
2673 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2674 | a second rldicr. */ | |
2675 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2676 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2677 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2678 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2679 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2680 | c = ~c; /* c == 0xff000fffffffffff */ | |
2681 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2682 | shift = 0; | |
2683 | while ((lsb >>= 1) != 0) | |
2684 | shift++; /* shift == 44 on exit from loop */ | |
2685 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2686 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2687 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2688 | } | |
2689 | ||
2690 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2691 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2692 | out[0] = GEN_INT (64 - shift); | |
2693 | out[1] = GEN_INT (m1); | |
2694 | out[2] = GEN_INT (shift); | |
2695 | out[3] = GEN_INT (m2); | |
2696 | #else | |
045572c7 GK |
2697 | (void)in; |
2698 | (void)out; | |
0ba1b2ff AM |
2699 | abort (); |
2700 | #endif | |
a260abc9 DE |
2701 | } |
2702 | ||
2703 | /* Return 1 if the operand is either a non-special register or a constant | |
2704 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
2705 | ||
2706 | int | |
a2369ed3 | 2707 | and64_operand (rtx op, enum machine_mode mode) |
9878760c | 2708 | { |
a4f6c312 | 2709 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2710 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
2711 | ||
2712 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
2713 | } |
2714 | ||
0ba1b2ff AM |
2715 | /* Like the above, but also match constants that can be implemented |
2716 | with two rldicl or rldicr insns. */ | |
2717 | ||
2718 | int | |
a2369ed3 | 2719 | and64_2_operand (rtx op, enum machine_mode mode) |
0ba1b2ff | 2720 | { |
a3c9585f | 2721 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
0ba1b2ff AM |
2722 | return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode); |
2723 | ||
2724 | return logical_operand (op, mode) || mask64_2_operand (op, mode); | |
2725 | } | |
2726 | ||
a260abc9 DE |
2727 | /* Return 1 if the operand is either a non-special register or a |
2728 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
2729 | |
2730 | int | |
a2369ed3 | 2731 | and_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 2732 | { |
a4f6c312 | 2733 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2734 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
2735 | ||
2736 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
2737 | } |
2738 | ||
9878760c RK |
2739 | /* Return 1 if the operand is a general register or memory operand. */ |
2740 | ||
2741 | int | |
a2369ed3 | 2742 | reg_or_mem_operand (rtx op, enum machine_mode mode) |
9878760c | 2743 | { |
b6c9286a MM |
2744 | return (gpc_reg_operand (op, mode) |
2745 | || memory_operand (op, mode) | |
4c81e946 | 2746 | || macho_lo_sum_memory_operand (op, mode) |
b6c9286a | 2747 | || volatile_mem_operand (op, mode)); |
9878760c RK |
2748 | } |
2749 | ||
a7a813f7 | 2750 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 2751 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
2752 | instruction. */ |
2753 | ||
2754 | int | |
a2369ed3 | 2755 | lwa_operand (rtx op, enum machine_mode mode) |
a7a813f7 RK |
2756 | { |
2757 | rtx inner = op; | |
2758 | ||
2759 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
2760 | inner = SUBREG_REG (inner); | |
2761 | ||
2762 | return gpc_reg_operand (inner, mode) | |
2763 | || (memory_operand (inner, mode) | |
2764 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
2765 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
2766 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
2767 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
2768 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
2769 | } |
2770 | ||
cc4d5fec JH |
2771 | /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */ |
2772 | ||
2773 | int | |
a2369ed3 | 2774 | symbol_ref_operand (rtx op, enum machine_mode mode) |
cc4d5fec JH |
2775 | { |
2776 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2777 | return 0; | |
2778 | ||
473f51b6 DE |
2779 | return (GET_CODE (op) == SYMBOL_REF |
2780 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))); | |
cc4d5fec JH |
2781 | } |
2782 | ||
9878760c | 2783 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
cc4d5fec | 2784 | to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */ |
9878760c RK |
2785 | |
2786 | int | |
a2369ed3 | 2787 | call_operand (rtx op, enum machine_mode mode) |
9878760c RK |
2788 | { |
2789 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2790 | return 0; | |
2791 | ||
2792 | return (GET_CODE (op) == SYMBOL_REF | |
cc4d5fec JH |
2793 | || (GET_CODE (op) == REG |
2794 | && (REGNO (op) == LINK_REGISTER_REGNUM | |
2795 | || REGNO (op) == COUNT_REGISTER_REGNUM | |
2796 | || REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
9878760c RK |
2797 | } |
2798 | ||
2af3d377 | 2799 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
d1908feb | 2800 | this file. */ |
2af3d377 RK |
2801 | |
2802 | int | |
a2369ed3 DJ |
2803 | current_file_function_operand (rtx op, |
2804 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
2af3d377 | 2805 | { |
473f51b6 DE |
2806 | return (GET_CODE (op) == SYMBOL_REF |
2807 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
2808 | && (SYMBOL_REF_LOCAL_P (op) | |
2809 | || (op == XEXP (DECL_RTL (current_function_decl), 0)))); | |
2af3d377 RK |
2810 | } |
2811 | ||
9878760c RK |
2812 | /* Return 1 if this operand is a valid input for a move insn. */ |
2813 | ||
2814 | int | |
a2369ed3 | 2815 | input_operand (rtx op, enum machine_mode mode) |
9878760c | 2816 | { |
eb4e8003 | 2817 | /* Memory is always valid. */ |
9878760c RK |
2818 | if (memory_operand (op, mode)) |
2819 | return 1; | |
2820 | ||
eb4e8003 RK |
2821 | /* For floating-point, easy constants are valid. */ |
2822 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2823 | && CONSTANT_P (op) | |
2824 | && easy_fp_constant (op, mode)) | |
2825 | return 1; | |
2826 | ||
4e74d8ec MM |
2827 | /* Allow any integer constant. */ |
2828 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 2829 | && (GET_CODE (op) == CONST_INT |
e675f625 | 2830 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
2831 | return 1; |
2832 | ||
d744e06e AH |
2833 | /* Allow easy vector constants. */ |
2834 | if (GET_CODE (op) == CONST_VECTOR | |
2835 | && easy_vector_constant (op, mode)) | |
2836 | return 1; | |
2837 | ||
eb4e8003 RK |
2838 | /* For floating-point or multi-word mode, the only remaining valid type |
2839 | is a register. */ | |
9878760c RK |
2840 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
2841 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 2842 | return register_operand (op, mode); |
9878760c | 2843 | |
88fe15a1 RK |
2844 | /* The only cases left are integral modes one word or smaller (we |
2845 | do not get called for MODE_CC values). These can be in any | |
2846 | register. */ | |
2847 | if (register_operand (op, mode)) | |
a8b3aeda | 2848 | return 1; |
88fe15a1 | 2849 | |
84cf9dda | 2850 | /* A SYMBOL_REF referring to the TOC is valid. */ |
4d588c14 | 2851 | if (legitimate_constant_pool_address_p (op)) |
84cf9dda RK |
2852 | return 1; |
2853 | ||
9ebbca7d | 2854 | /* A constant pool expression (relative to the TOC) is valid */ |
4d588c14 | 2855 | if (toc_relative_expr_p (op)) |
b6c9286a MM |
2856 | return 1; |
2857 | ||
88228c4b MM |
2858 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
2859 | to be valid. */ | |
f607bc57 | 2860 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
2861 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
2862 | && small_data_operand (op, Pmode)) | |
2863 | return 1; | |
2864 | ||
042259f2 | 2865 | return 0; |
9878760c | 2866 | } |
7509c759 | 2867 | |
95727fb8 AP |
2868 | |
2869 | /* Darwin, AIX increases natural record alignment to doubleword if the first | |
2870 | field is an FP double while the FP fields remain word aligned. */ | |
2871 | ||
19d66194 | 2872 | unsigned int |
95727fb8 AP |
2873 | rs6000_special_round_type_align (tree type, int computed, int specified) |
2874 | { | |
2875 | tree field = TYPE_FIELDS (type); | |
95727fb8 AP |
2876 | |
2877 | /* Skip all the static variables only if ABI is greater than | |
71cc389b | 2878 | 1 or equal to 0. */ |
3ce5437a | 2879 | while (field != NULL && TREE_CODE (field) == VAR_DECL) |
95727fb8 AP |
2880 | field = TREE_CHAIN (field); |
2881 | ||
3ce5437a | 2882 | if (field == NULL || field == type || DECL_MODE (field) != DFmode) |
95727fb8 AP |
2883 | return MAX (computed, specified); |
2884 | ||
2885 | return MAX (MAX (computed, specified), 64); | |
2886 | } | |
2887 | ||
a4f6c312 | 2888 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
2889 | |
2890 | int | |
a2369ed3 DJ |
2891 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
2892 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
7509c759 | 2893 | { |
38c1f2d7 | 2894 | #if TARGET_ELF |
5f59ecb7 | 2895 | rtx sym_ref; |
7509c759 | 2896 | |
d9407988 | 2897 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 2898 | return 0; |
a54d04b7 | 2899 | |
f607bc57 | 2900 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
2901 | return 0; |
2902 | ||
88228c4b MM |
2903 | if (GET_CODE (op) == SYMBOL_REF) |
2904 | sym_ref = op; | |
2905 | ||
2906 | else if (GET_CODE (op) != CONST | |
2907 | || GET_CODE (XEXP (op, 0)) != PLUS | |
2908 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
2909 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
2910 | return 0; |
2911 | ||
88228c4b | 2912 | else |
dbf55e53 MM |
2913 | { |
2914 | rtx sum = XEXP (op, 0); | |
2915 | HOST_WIDE_INT summand; | |
2916 | ||
2917 | /* We have to be careful here, because it is the referenced address | |
2918 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
2919 | summand = INTVAL (XEXP (sum, 1)); | |
307b599c | 2920 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
dbf55e53 MM |
2921 | return 0; |
2922 | ||
2923 | sym_ref = XEXP (sum, 0); | |
2924 | } | |
88228c4b | 2925 | |
20bfcd69 | 2926 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
2927 | #else |
2928 | return 0; | |
2929 | #endif | |
7509c759 | 2930 | } |
46c07df8 | 2931 | |
d2288d5d HP |
2932 | /* Return true, if operand is a memory operand and has a |
2933 | displacement divisible by 4. */ | |
2934 | ||
2935 | int | |
2936 | word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2937 | { | |
2938 | rtx addr; | |
2939 | int off = 0; | |
2940 | ||
2941 | if (!memory_operand (op, mode)) | |
2942 | return 0; | |
2943 | ||
2944 | addr = XEXP (op, 0); | |
2945 | if (GET_CODE (addr) == PLUS | |
2946 | && GET_CODE (XEXP (addr, 0)) == REG | |
2947 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2948 | off = INTVAL (XEXP (addr, 1)); | |
2949 | ||
2950 | return (off % 4) == 0; | |
2951 | } | |
2952 | ||
3a1f863f | 2953 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 2954 | |
3a1f863f DE |
2955 | bool |
2956 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 2957 | { |
3a1f863f DE |
2958 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
2959 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
2960 | } |
2961 | ||
9ebbca7d | 2962 | \f |
4d588c14 RH |
2963 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
2964 | ||
9ebbca7d | 2965 | static int |
a2369ed3 | 2966 | constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) |
9ebbca7d GK |
2967 | { |
2968 | switch (GET_CODE(op)) | |
2969 | { | |
2970 | case SYMBOL_REF: | |
c4501e62 JJ |
2971 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
2972 | return 0; | |
2973 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
2974 | { |
2975 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
2976 | { | |
2977 | *have_sym = 1; | |
2978 | return 1; | |
2979 | } | |
2980 | else | |
2981 | return 0; | |
2982 | } | |
2983 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
2984 | { | |
2985 | *have_toc = 1; | |
2986 | return 1; | |
2987 | } | |
2988 | else | |
2989 | return 0; | |
9ebbca7d GK |
2990 | case PLUS: |
2991 | case MINUS: | |
c1f11548 DE |
2992 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
2993 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 2994 | case CONST: |
a4f6c312 | 2995 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 2996 | case CONST_INT: |
a4f6c312 | 2997 | return 1; |
9ebbca7d | 2998 | default: |
a4f6c312 | 2999 | return 0; |
9ebbca7d GK |
3000 | } |
3001 | } | |
3002 | ||
4d588c14 | 3003 | static bool |
a2369ed3 | 3004 | constant_pool_expr_p (rtx op) |
9ebbca7d GK |
3005 | { |
3006 | int have_sym = 0; | |
3007 | int have_toc = 0; | |
3008 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
3009 | } | |
3010 | ||
4d588c14 | 3011 | static bool |
a2369ed3 | 3012 | toc_relative_expr_p (rtx op) |
9ebbca7d | 3013 | { |
4d588c14 RH |
3014 | int have_sym = 0; |
3015 | int have_toc = 0; | |
3016 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
3017 | } | |
3018 | ||
4d588c14 | 3019 | bool |
a2369ed3 | 3020 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
3021 | { |
3022 | return (TARGET_TOC | |
3023 | && GET_CODE (x) == PLUS | |
3024 | && GET_CODE (XEXP (x, 0)) == REG | |
3025 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
3026 | && constant_pool_expr_p (XEXP (x, 1))); | |
3027 | } | |
3028 | ||
3029 | static bool | |
a2369ed3 | 3030 | legitimate_small_data_p (enum machine_mode mode, rtx x) |
4d588c14 RH |
3031 | { |
3032 | return (DEFAULT_ABI == ABI_V4 | |
3033 | && !flag_pic && !TARGET_TOC | |
3034 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
3035 | && small_data_operand (x, mode)); | |
3036 | } | |
3037 | ||
60cdabab DE |
3038 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
3039 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
3040 | ||
76d2b81d DJ |
3041 | bool |
3042 | rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) | |
4d588c14 RH |
3043 | { |
3044 | unsigned HOST_WIDE_INT offset, extra; | |
3045 | ||
3046 | if (GET_CODE (x) != PLUS) | |
3047 | return false; | |
3048 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3049 | return false; | |
3050 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
3051 | return false; | |
60cdabab DE |
3052 | if (legitimate_constant_pool_address_p (x)) |
3053 | return true; | |
4d588c14 RH |
3054 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
3055 | return false; | |
3056 | ||
3057 | offset = INTVAL (XEXP (x, 1)); | |
3058 | extra = 0; | |
3059 | switch (mode) | |
3060 | { | |
3061 | case V16QImode: | |
3062 | case V8HImode: | |
3063 | case V4SFmode: | |
3064 | case V4SImode: | |
3065 | /* AltiVec vector modes. Only reg+reg addressing is valid here, | |
3066 | which leaves the only valid constant offset of zero, which by | |
3067 | canonicalization rules is also invalid. */ | |
3068 | return false; | |
3069 | ||
3070 | case V4HImode: | |
3071 | case V2SImode: | |
3072 | case V1DImode: | |
3073 | case V2SFmode: | |
3074 | /* SPE vector modes. */ | |
3075 | return SPE_CONST_OFFSET_OK (offset); | |
3076 | ||
3077 | case DFmode: | |
3078 | case DImode: | |
3364872d | 3079 | if (mode == DFmode || !TARGET_POWERPC64) |
4d588c14 RH |
3080 | extra = 4; |
3081 | else if (offset & 3) | |
3082 | return false; | |
3083 | break; | |
3084 | ||
3085 | case TFmode: | |
3086 | case TImode: | |
3364872d | 3087 | if (mode == TFmode || !TARGET_POWERPC64) |
4d588c14 RH |
3088 | extra = 12; |
3089 | else if (offset & 3) | |
3090 | return false; | |
3091 | else | |
3092 | extra = 8; | |
3093 | break; | |
3094 | ||
3095 | default: | |
3096 | break; | |
3097 | } | |
3098 | ||
b1917422 AM |
3099 | offset += 0x8000; |
3100 | return (offset < 0x10000) && (offset + extra < 0x10000); | |
4d588c14 RH |
3101 | } |
3102 | ||
3103 | static bool | |
a2369ed3 | 3104 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
3105 | { |
3106 | rtx op0, op1; | |
3107 | ||
3108 | if (GET_CODE (x) != PLUS) | |
3109 | return false; | |
3110 | op0 = XEXP (x, 0); | |
3111 | op1 = XEXP (x, 1); | |
3112 | ||
3113 | if (!REG_P (op0) || !REG_P (op1)) | |
3114 | return false; | |
3115 | ||
3116 | return ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
3117 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
3118 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
3119 | && INT_REG_OK_FOR_INDEX_P (op0, strict))); | |
9ebbca7d GK |
3120 | } |
3121 | ||
4d588c14 | 3122 | static inline bool |
a2369ed3 | 3123 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
3124 | { |
3125 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
3126 | } | |
3127 | ||
4c81e946 FJ |
3128 | static bool |
3129 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) | |
3130 | { | |
3131 | if (!TARGET_MACHO || !flag_pic | |
3132 | || mode != SImode || GET_CODE(x) != MEM) | |
3133 | return false; | |
3134 | x = XEXP (x, 0); | |
3135 | ||
3136 | if (GET_CODE (x) != LO_SUM) | |
3137 | return false; | |
3138 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3139 | return false; | |
3140 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
3141 | return false; | |
3142 | x = XEXP (x, 1); | |
3143 | ||
3144 | return CONSTANT_P (x); | |
3145 | } | |
3146 | ||
4d588c14 | 3147 | static bool |
a2369ed3 | 3148 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
3149 | { |
3150 | if (GET_CODE (x) != LO_SUM) | |
3151 | return false; | |
3152 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3153 | return false; | |
3154 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
3155 | return false; | |
3156 | x = XEXP (x, 1); | |
3157 | ||
8622e235 | 3158 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 3159 | { |
a29077da | 3160 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
3161 | return false; |
3162 | if (TARGET_TOC) | |
3163 | return false; | |
3164 | if (GET_MODE_NUNITS (mode) != 1) | |
3165 | return false; | |
3166 | if (GET_MODE_BITSIZE (mode) > 32 | |
3167 | && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)) | |
3168 | return false; | |
3169 | ||
3170 | return CONSTANT_P (x); | |
3171 | } | |
3172 | ||
3173 | return false; | |
3174 | } | |
3175 | ||
3176 | ||
9ebbca7d GK |
3177 | /* Try machine-dependent ways of modifying an illegitimate address |
3178 | to be legitimate. If we find one, return the new, valid address. | |
3179 | This is used from only one place: `memory_address' in explow.c. | |
3180 | ||
a4f6c312 SS |
3181 | OLDX is the address as it was before break_out_memory_refs was |
3182 | called. In some cases it is useful to look at this to decide what | |
3183 | needs to be done. | |
9ebbca7d | 3184 | |
a4f6c312 | 3185 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 3186 | |
a4f6c312 SS |
3187 | It is always safe for this function to do nothing. It exists to |
3188 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
3189 | |
3190 | On RS/6000, first check for the sum of a register with a constant | |
3191 | integer that is out of range. If so, generate code to add the | |
3192 | constant with the low-order 16 bits masked to the register and force | |
3193 | this result into another register (this can be done with `cau'). | |
3194 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
3195 | possibility of bit 16 being a one. | |
3196 | ||
3197 | Then check for the sum of a register and something not constant, try to | |
3198 | load the other things into a register and return the sum. */ | |
4d588c14 | 3199 | |
9ebbca7d | 3200 | rtx |
a2369ed3 DJ |
3201 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
3202 | enum machine_mode mode) | |
0ac081f6 | 3203 | { |
c4501e62 JJ |
3204 | if (GET_CODE (x) == SYMBOL_REF) |
3205 | { | |
3206 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
3207 | if (model != 0) | |
3208 | return rs6000_legitimize_tls_address (x, model); | |
3209 | } | |
3210 | ||
9ebbca7d GK |
3211 | if (GET_CODE (x) == PLUS |
3212 | && GET_CODE (XEXP (x, 0)) == REG | |
3213 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3214 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
3215 | { | |
3216 | HOST_WIDE_INT high_int, low_int; | |
3217 | rtx sum; | |
a65c591c DE |
3218 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
3219 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
3220 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
3221 | GEN_INT (high_int)), 0); | |
3222 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
3223 | } | |
3224 | else if (GET_CODE (x) == PLUS | |
3225 | && GET_CODE (XEXP (x, 0)) == REG | |
3226 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 3227 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
3228 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3229 | || TARGET_POWERPC64 | |
fcce224d | 3230 | || (mode != DFmode && mode != TFmode)) |
9ebbca7d GK |
3231 | && (TARGET_POWERPC64 || mode != DImode) |
3232 | && mode != TImode) | |
3233 | { | |
3234 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3235 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
3236 | } | |
0ac081f6 AH |
3237 | else if (ALTIVEC_VECTOR_MODE (mode)) |
3238 | { | |
3239 | rtx reg; | |
3240 | ||
3241 | /* Make sure both operands are registers. */ | |
3242 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 3243 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
3244 | force_reg (Pmode, XEXP (x, 1))); |
3245 | ||
3246 | reg = force_reg (Pmode, x); | |
3247 | return reg; | |
3248 | } | |
a3170dc6 AH |
3249 | else if (SPE_VECTOR_MODE (mode)) |
3250 | { | |
3251 | /* We accept [reg + reg] and [reg + OFFSET]. */ | |
3252 | ||
3253 | if (GET_CODE (x) == PLUS) | |
3254 | { | |
3255 | rtx op1 = XEXP (x, 0); | |
3256 | rtx op2 = XEXP (x, 1); | |
3257 | ||
3258 | op1 = force_reg (Pmode, op1); | |
3259 | ||
3260 | if (GET_CODE (op2) != REG | |
3261 | && (GET_CODE (op2) != CONST_INT | |
3262 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
3263 | op2 = force_reg (Pmode, op2); | |
3264 | ||
3265 | return gen_rtx_PLUS (Pmode, op1, op2); | |
3266 | } | |
3267 | ||
3268 | return force_reg (Pmode, x); | |
3269 | } | |
f1384257 AM |
3270 | else if (TARGET_ELF |
3271 | && TARGET_32BIT | |
3272 | && TARGET_NO_TOC | |
3273 | && ! flag_pic | |
9ebbca7d GK |
3274 | && GET_CODE (x) != CONST_INT |
3275 | && GET_CODE (x) != CONST_DOUBLE | |
3276 | && CONSTANT_P (x) | |
6ac7bf2c GK |
3277 | && GET_MODE_NUNITS (mode) == 1 |
3278 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 3279 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
3280 | { |
3281 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3282 | emit_insn (gen_elf_high (reg, x)); |
3283 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 3284 | } |
ee890fe2 SS |
3285 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
3286 | && ! flag_pic | |
ab82a49f AP |
3287 | #if TARGET_MACHO |
3288 | && ! MACHO_DYNAMIC_NO_PIC_P | |
3289 | #endif | |
ee890fe2 SS |
3290 | && GET_CODE (x) != CONST_INT |
3291 | && GET_CODE (x) != CONST_DOUBLE | |
3292 | && CONSTANT_P (x) | |
a3170dc6 | 3293 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
ee890fe2 SS |
3294 | && mode != DImode |
3295 | && mode != TImode) | |
3296 | { | |
3297 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3298 | emit_insn (gen_macho_high (reg, x)); |
3299 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 3300 | } |
9ebbca7d | 3301 | else if (TARGET_TOC |
4d588c14 | 3302 | && constant_pool_expr_p (x) |
a9098fd0 | 3303 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
3304 | { |
3305 | return create_TOC_reference (x); | |
3306 | } | |
3307 | else | |
3308 | return NULL_RTX; | |
3309 | } | |
258bfae2 | 3310 | |
c973d557 JJ |
3311 | /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. |
3312 | We need to emit DTP-relative relocations. */ | |
3313 | ||
3314 | void | |
3315 | rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
3316 | { | |
3317 | switch (size) | |
3318 | { | |
3319 | case 4: | |
3320 | fputs ("\t.long\t", file); | |
3321 | break; | |
3322 | case 8: | |
3323 | fputs (DOUBLE_INT_ASM_OP, file); | |
3324 | break; | |
3325 | default: | |
3326 | abort (); | |
3327 | } | |
3328 | output_addr_const (file, x); | |
3329 | fputs ("@dtprel+0x8000", file); | |
3330 | } | |
3331 | ||
c4501e62 JJ |
3332 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
3333 | ||
3334 | static GTY(()) rtx rs6000_tls_symbol; | |
3335 | static rtx | |
863d938c | 3336 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
3337 | { |
3338 | if (!rs6000_tls_symbol) | |
3339 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
3340 | ||
3341 | return rs6000_tls_symbol; | |
3342 | } | |
3343 | ||
3344 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
3345 | ||
3346 | static GTY(()) rtx rs6000_got_symbol; | |
3347 | static rtx | |
863d938c | 3348 | rs6000_got_sym (void) |
c4501e62 JJ |
3349 | { |
3350 | if (!rs6000_got_symbol) | |
3351 | { | |
3352 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3353 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
3354 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
3355 | } | |
3356 | ||
3357 | return rs6000_got_symbol; | |
3358 | } | |
3359 | ||
3360 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3361 | this (thread-local) address. */ | |
3362 | ||
3363 | static rtx | |
a2369ed3 | 3364 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
3365 | { |
3366 | rtx dest, insn; | |
3367 | ||
3368 | dest = gen_reg_rtx (Pmode); | |
3369 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
3370 | { | |
3371 | rtx tlsreg; | |
3372 | ||
3373 | if (TARGET_64BIT) | |
3374 | { | |
3375 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3376 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
3377 | } | |
3378 | else | |
3379 | { | |
3380 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3381 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
3382 | } | |
3383 | emit_insn (insn); | |
3384 | } | |
3385 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
3386 | { | |
3387 | rtx tlsreg, tmp; | |
3388 | ||
3389 | tmp = gen_reg_rtx (Pmode); | |
3390 | if (TARGET_64BIT) | |
3391 | { | |
3392 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3393 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
3394 | } | |
3395 | else | |
3396 | { | |
3397 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3398 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
3399 | } | |
3400 | emit_insn (insn); | |
3401 | if (TARGET_64BIT) | |
3402 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
3403 | else | |
3404 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
3405 | emit_insn (insn); | |
3406 | } | |
3407 | else | |
3408 | { | |
3409 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
3410 | ||
3411 | if (TARGET_64BIT) | |
3412 | got = gen_rtx_REG (Pmode, TOC_REGISTER); | |
3413 | else | |
3414 | { | |
3415 | if (flag_pic == 1) | |
3416 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
3417 | else | |
3418 | { | |
3419 | rtx gsym = rs6000_got_sym (); | |
3420 | got = gen_reg_rtx (Pmode); | |
3421 | if (flag_pic == 0) | |
3422 | rs6000_emit_move (got, gsym, Pmode); | |
3423 | else | |
3424 | { | |
3425 | char buf[30]; | |
3426 | static int tls_got_labelno = 0; | |
3427 | rtx tempLR, lab, tmp3, mem; | |
3428 | rtx first, last; | |
3429 | ||
3430 | ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++); | |
3431 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
3432 | tempLR = gen_reg_rtx (Pmode); | |
3433 | tmp1 = gen_reg_rtx (Pmode); | |
3434 | tmp2 = gen_reg_rtx (Pmode); | |
3435 | tmp3 = gen_reg_rtx (Pmode); | |
3436 | mem = gen_rtx_MEM (Pmode, tmp1); | |
3437 | RTX_UNCHANGING_P (mem) = 1; | |
3438 | ||
3439 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab, | |
3440 | gsym)); | |
3441 | emit_move_insn (tmp1, tempLR); | |
3442 | emit_move_insn (tmp2, mem); | |
3443 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
3444 | last = emit_move_insn (got, tmp3); | |
3445 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
3446 | REG_NOTES (last)); | |
3447 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
3448 | REG_NOTES (first)); | |
3449 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
3450 | REG_NOTES (last)); | |
3451 | } | |
3452 | } | |
3453 | } | |
3454 | ||
3455 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
3456 | { | |
3457 | r3 = gen_rtx_REG (Pmode, 3); | |
3458 | if (TARGET_64BIT) | |
3459 | insn = gen_tls_gd_64 (r3, got, addr); | |
3460 | else | |
3461 | insn = gen_tls_gd_32 (r3, got, addr); | |
3462 | start_sequence (); | |
3463 | emit_insn (insn); | |
3464 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3465 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3466 | insn = emit_call_insn (insn); | |
3467 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3468 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3469 | insn = get_insns (); | |
3470 | end_sequence (); | |
3471 | emit_libcall_block (insn, dest, r3, addr); | |
3472 | } | |
3473 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
3474 | { | |
3475 | r3 = gen_rtx_REG (Pmode, 3); | |
3476 | if (TARGET_64BIT) | |
3477 | insn = gen_tls_ld_64 (r3, got); | |
3478 | else | |
3479 | insn = gen_tls_ld_32 (r3, got); | |
3480 | start_sequence (); | |
3481 | emit_insn (insn); | |
3482 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3483 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3484 | insn = emit_call_insn (insn); | |
3485 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3486 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3487 | insn = get_insns (); | |
3488 | end_sequence (); | |
3489 | tmp1 = gen_reg_rtx (Pmode); | |
3490 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
3491 | UNSPEC_TLSLD); | |
3492 | emit_libcall_block (insn, tmp1, r3, eqv); | |
3493 | if (rs6000_tls_size == 16) | |
3494 | { | |
3495 | if (TARGET_64BIT) | |
3496 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
3497 | else | |
3498 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
3499 | } | |
3500 | else if (rs6000_tls_size == 32) | |
3501 | { | |
3502 | tmp2 = gen_reg_rtx (Pmode); | |
3503 | if (TARGET_64BIT) | |
3504 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
3505 | else | |
3506 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
3507 | emit_insn (insn); | |
3508 | if (TARGET_64BIT) | |
3509 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
3510 | else | |
3511 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
3512 | } | |
3513 | else | |
3514 | { | |
3515 | tmp2 = gen_reg_rtx (Pmode); | |
3516 | if (TARGET_64BIT) | |
3517 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
3518 | else | |
3519 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
3520 | emit_insn (insn); | |
3521 | insn = gen_rtx_SET (Pmode, dest, | |
3522 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
3523 | } | |
3524 | emit_insn (insn); | |
3525 | } | |
3526 | else | |
3527 | { | |
3528 | /* IE, or 64 bit offset LE. */ | |
3529 | tmp2 = gen_reg_rtx (Pmode); | |
3530 | if (TARGET_64BIT) | |
3531 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
3532 | else | |
3533 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
3534 | emit_insn (insn); | |
3535 | if (TARGET_64BIT) | |
3536 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
3537 | else | |
3538 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
3539 | emit_insn (insn); | |
3540 | } | |
3541 | } | |
3542 | ||
3543 | return dest; | |
3544 | } | |
3545 | ||
3546 | /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in | |
3547 | instruction definitions. */ | |
3548 | ||
3549 | int | |
a2369ed3 | 3550 | rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
c4501e62 JJ |
3551 | { |
3552 | return RS6000_SYMBOL_REF_TLS_P (x); | |
3553 | } | |
3554 | ||
3555 | /* Return 1 if X contains a thread-local symbol. */ | |
3556 | ||
3557 | bool | |
a2369ed3 | 3558 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 3559 | { |
cd413cab AP |
3560 | if (! TARGET_HAVE_TLS) |
3561 | return false; | |
3562 | ||
c4501e62 JJ |
3563 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
3564 | } | |
3565 | ||
3566 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
3567 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
3568 | ||
3569 | static inline int | |
a2369ed3 | 3570 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
3571 | { |
3572 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
3573 | } | |
3574 | ||
24ea750e DJ |
3575 | /* The convention appears to be to define this wherever it is used. |
3576 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
3577 | is now used here. */ | |
3578 | #ifndef REG_MODE_OK_FOR_BASE_P | |
3579 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
3580 | #endif | |
3581 | ||
3582 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
3583 | replace the input X, or the original X if no replacement is called for. | |
3584 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
3585 | 0 if it should not. | |
3586 | ||
3587 | For RS/6000, we wish to handle large displacements off a base | |
3588 | register by splitting the addend across an addiu/addis and the mem insn. | |
3589 | This cuts number of extra insns needed from 3 to 1. | |
3590 | ||
3591 | On Darwin, we use this to generate code for floating point constants. | |
3592 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
3593 | The Darwin code is inside #if TARGET_MACHO because only then is | |
3594 | machopic_function_base_name() defined. */ | |
3595 | rtx | |
a2369ed3 DJ |
3596 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
3597 | int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e DJ |
3598 | { |
3599 | /* We must recognize output that we have already generated ourselves. */ | |
3600 | if (GET_CODE (x) == PLUS | |
3601 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3602 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
3603 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3604 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3605 | { | |
3606 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3607 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
3608 | opnum, (enum reload_type)type); | |
3609 | *win = 1; | |
3610 | return x; | |
3611 | } | |
3deb2758 | 3612 | |
24ea750e DJ |
3613 | #if TARGET_MACHO |
3614 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
3615 | && GET_CODE (x) == LO_SUM | |
3616 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3617 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
3618 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
3619 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
3620 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
3621 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
3622 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
3623 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
3624 | { | |
3625 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 3626 | floating point constant. */ |
24ea750e DJ |
3627 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
3628 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
3629 | opnum, (enum reload_type)type); | |
3630 | *win = 1; | |
3631 | return x; | |
3632 | } | |
3633 | #endif | |
3634 | if (GET_CODE (x) == PLUS | |
3635 | && GET_CODE (XEXP (x, 0)) == REG | |
3636 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
3637 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 3638 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 3639 | && !SPE_VECTOR_MODE (mode) |
78c875e8 | 3640 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
3641 | { |
3642 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
3643 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
3644 | HOST_WIDE_INT high | |
3645 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
3646 | ||
3647 | /* Check for 32-bit overflow. */ | |
3648 | if (high + low != val) | |
3649 | { | |
3650 | *win = 0; | |
3651 | return x; | |
3652 | } | |
3653 | ||
3654 | /* Reload the high part into a base reg; leave the low part | |
3655 | in the mem directly. */ | |
3656 | ||
3657 | x = gen_rtx_PLUS (GET_MODE (x), | |
3658 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
3659 | GEN_INT (high)), | |
3660 | GEN_INT (low)); | |
3661 | ||
3662 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3663 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
3664 | opnum, (enum reload_type)type); | |
3665 | *win = 1; | |
3666 | return x; | |
3667 | } | |
3668 | #if TARGET_MACHO | |
3669 | if (GET_CODE (x) == SYMBOL_REF | |
3670 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 3671 | && !ALTIVEC_VECTOR_MODE (mode) |
a29077da GK |
3672 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
3673 | /* Don't do this for TFmode, since the result isn't offsettable. */ | |
3674 | && mode != TFmode) | |
24ea750e | 3675 | { |
a29077da GK |
3676 | if (flag_pic) |
3677 | { | |
3678 | rtx offset = gen_rtx_CONST (Pmode, | |
3679 | gen_rtx_MINUS (Pmode, x, | |
3680 | gen_rtx_SYMBOL_REF (Pmode, | |
3681 | machopic_function_base_name ()))); | |
3682 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
3683 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
3684 | gen_rtx_HIGH (Pmode, offset)), offset); | |
3685 | } | |
3686 | else | |
3687 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
3688 | gen_rtx_HIGH (Pmode, x), x); | |
3689 | ||
24ea750e | 3690 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
3691 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3692 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3693 | *win = 1; |
3694 | return x; | |
3695 | } | |
3696 | #endif | |
3697 | if (TARGET_TOC | |
4d588c14 | 3698 | && constant_pool_expr_p (x) |
c1f11548 | 3699 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3700 | { |
3701 | (x) = create_TOC_reference (x); | |
3702 | *win = 1; | |
3703 | return x; | |
3704 | } | |
3705 | *win = 0; | |
3706 | return x; | |
3707 | } | |
3708 | ||
258bfae2 FS |
3709 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3710 | that is a valid memory address for an instruction. | |
3711 | The MODE argument is the machine mode for the MEM expression | |
3712 | that wants to use this address. | |
3713 | ||
3714 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3715 | refers to a constant pool entry of an address (or the sum of it | |
3716 | plus a constant), a short (16-bit signed) constant plus a register, | |
3717 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3718 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3719 | we must ensure that both words are addressable or PowerPC64 with offset |
3720 | word aligned. | |
3721 | ||
3722 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
76d2b81d | 3723 | 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because |
258bfae2 FS |
3724 | adjacent memory cells are accessed by adding word-sized offsets |
3725 | during assembly output. */ | |
3726 | int | |
a2369ed3 | 3727 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 3728 | { |
c4501e62 JJ |
3729 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3730 | return 0; | |
4d588c14 | 3731 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3732 | return 1; |
3733 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3734 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3735 | && !SPE_VECTOR_MODE (mode) |
258bfae2 | 3736 | && TARGET_UPDATE |
4d588c14 | 3737 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3738 | return 1; |
4d588c14 | 3739 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 3740 | return 1; |
4d588c14 | 3741 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3742 | return 1; |
3743 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3744 | if (! reg_ok_strict | |
3745 | && GET_CODE (x) == PLUS | |
3746 | && GET_CODE (XEXP (x, 0)) == REG | |
708d2456 HP |
3747 | && (XEXP (x, 0) == virtual_stack_vars_rtx |
3748 | || XEXP (x, 0) == arg_pointer_rtx) | |
258bfae2 FS |
3749 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
3750 | return 1; | |
76d2b81d | 3751 | if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3752 | return 1; |
3753 | if (mode != TImode | |
76d2b81d | 3754 | && mode != TFmode |
a3170dc6 AH |
3755 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3756 | || TARGET_POWERPC64 | |
fcce224d | 3757 | || (mode != DFmode && mode != TFmode)) |
258bfae2 | 3758 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3759 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3760 | return 1; |
4d588c14 | 3761 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3762 | return 1; |
3763 | return 0; | |
3764 | } | |
4d588c14 RH |
3765 | |
3766 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3767 | has an effect that depends on the machine mode it is used for. | |
3768 | ||
3769 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3770 | modes don't allow them) or is a pre-increment or decrement. | |
3771 | ||
3772 | ??? Except that due to conceptual problems in offsettable_address_p | |
3773 | we can't really report the problems of integral offsets. So leave | |
3774 | this assuming that the adjustable offset must be valid for the | |
3775 | sub-words of a TFmode operand, which is what we had before. */ | |
3776 | ||
3777 | bool | |
a2369ed3 | 3778 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
3779 | { |
3780 | switch (GET_CODE (addr)) | |
3781 | { | |
3782 | case PLUS: | |
3783 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3784 | { | |
3785 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3786 | return val + 12 + 0x8000 >= 0x10000; | |
3787 | } | |
3788 | break; | |
3789 | ||
3790 | case LO_SUM: | |
3791 | return true; | |
3792 | ||
3793 | case PRE_INC: | |
3794 | case PRE_DEC: | |
3795 | return TARGET_UPDATE; | |
3796 | ||
3797 | default: | |
3798 | break; | |
3799 | } | |
3800 | ||
3801 | return false; | |
3802 | } | |
d8ecbcdb AH |
3803 | |
3804 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
3805 | to hold something of mode MODE. | |
3806 | This is ordinarily the length in words of a value of mode MODE | |
3807 | but can be less for certain modes in special long registers. | |
3808 | ||
3809 | For the SPE, GPRs are 64 bits but only 32 bits are visible in | |
3810 | scalar instructions. The upper 32 bits are only available to the | |
3811 | SIMD instructions. | |
3812 | ||
3813 | POWER and PowerPC GPRs hold 32 bits worth; | |
3814 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
3815 | ||
3816 | int | |
3817 | rs6000_hard_regno_nregs (int regno, enum machine_mode mode) | |
3818 | { | |
3819 | if (FP_REGNO_P (regno)) | |
3820 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; | |
3821 | ||
3822 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
3823 | return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; | |
3824 | ||
3825 | if (ALTIVEC_REGNO_P (regno)) | |
3826 | return | |
3827 | (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; | |
3828 | ||
3829 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3830 | } | |
2aa4498c AH |
3831 | |
3832 | /* Change register usage conditional on target flags. */ | |
3833 | void | |
3834 | rs6000_conditional_register_usage (void) | |
3835 | { | |
3836 | int i; | |
3837 | ||
3838 | /* Set MQ register fixed (already call_used) if not POWER | |
3839 | architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not | |
3840 | be allocated. */ | |
3841 | if (! TARGET_POWER) | |
3842 | fixed_regs[64] = 1; | |
3843 | ||
3844 | /* 64-bit AIX reserves GPR13 for thread-private data. */ | |
3845 | if (TARGET_64BIT) | |
3846 | fixed_regs[13] = call_used_regs[13] | |
3847 | = call_really_used_regs[13] = 1; | |
3848 | ||
3849 | /* Conditionally disable FPRs. */ | |
3850 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
3851 | for (i = 32; i < 64; i++) | |
3852 | fixed_regs[i] = call_used_regs[i] | |
3853 | = call_really_used_regs[i] = 1; | |
3854 | ||
3855 | if (DEFAULT_ABI == ABI_V4 | |
3856 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3857 | && flag_pic == 2) | |
3858 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3859 | ||
3860 | if (DEFAULT_ABI == ABI_V4 | |
3861 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3862 | && flag_pic == 1) | |
3863 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3864 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3865 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3866 | ||
3867 | if (DEFAULT_ABI == ABI_DARWIN | |
3868 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
3869 | global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3870 | = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3871 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3872 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3873 | ||
b4db40bf JJ |
3874 | if (TARGET_TOC && TARGET_MINIMAL_TOC) |
3875 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3876 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3877 | ||
2aa4498c AH |
3878 | if (TARGET_ALTIVEC) |
3879 | global_regs[VSCR_REGNO] = 1; | |
3880 | ||
3881 | if (TARGET_SPE) | |
3882 | { | |
3883 | global_regs[SPEFSCR_REGNO] = 1; | |
3884 | fixed_regs[FIXED_SCRATCH] | |
3885 | = call_used_regs[FIXED_SCRATCH] | |
3886 | = call_really_used_regs[FIXED_SCRATCH] = 1; | |
3887 | } | |
3888 | ||
3889 | if (! TARGET_ALTIVEC) | |
3890 | { | |
3891 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
3892 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
3893 | call_really_used_regs[VRSAVE_REGNO] = 1; | |
3894 | } | |
3895 | ||
3896 | if (TARGET_ALTIVEC_ABI) | |
3897 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) | |
3898 | call_used_regs[i] = call_really_used_regs[i] = 1; | |
3899 | } | |
fb4d4348 | 3900 | \f |
a4f6c312 SS |
3901 | /* Try to output insns to set TARGET equal to the constant C if it can |
3902 | be done in less than N insns. Do all computations in MODE. | |
3903 | Returns the place where the output has been placed if it can be | |
3904 | done and the insns have been emitted. If it would take more than N | |
3905 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
3906 | |
3907 | rtx | |
a2369ed3 DJ |
3908 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
3909 | rtx source, int n ATTRIBUTE_UNUSED) | |
2bfcf297 | 3910 | { |
af8cb5c5 | 3911 | rtx result, insn, set; |
2bfcf297 DB |
3912 | HOST_WIDE_INT c0, c1; |
3913 | ||
af8cb5c5 | 3914 | if (mode == QImode || mode == HImode) |
2bfcf297 DB |
3915 | { |
3916 | if (dest == NULL) | |
3917 | dest = gen_reg_rtx (mode); | |
3918 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
3919 | return dest; | |
3920 | } | |
af8cb5c5 | 3921 | else if (mode == SImode) |
2bfcf297 | 3922 | { |
af8cb5c5 DE |
3923 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
3924 | ||
3925 | emit_insn (gen_rtx_SET (VOIDmode, result, | |
3926 | GEN_INT (INTVAL (source) | |
3927 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
3928 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3929 | gen_rtx_IOR (SImode, result, | |
3930 | GEN_INT (INTVAL (source) & 0xffff)))); | |
3931 | result = dest; | |
2bfcf297 | 3932 | } |
af8cb5c5 | 3933 | else if (mode == DImode) |
2bfcf297 | 3934 | { |
af8cb5c5 DE |
3935 | if (GET_CODE (source) == CONST_INT) |
3936 | { | |
3937 | c0 = INTVAL (source); | |
3938 | c1 = -(c0 < 0); | |
3939 | } | |
3940 | else if (GET_CODE (source) == CONST_DOUBLE) | |
3941 | { | |
2bfcf297 | 3942 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
3943 | c0 = CONST_DOUBLE_LOW (source); |
3944 | c1 = -(c0 < 0); | |
2bfcf297 | 3945 | #else |
af8cb5c5 DE |
3946 | c0 = CONST_DOUBLE_LOW (source); |
3947 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 3948 | #endif |
af8cb5c5 DE |
3949 | } |
3950 | else | |
3951 | abort (); | |
3952 | ||
3953 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
2bfcf297 DB |
3954 | } |
3955 | else | |
a4f6c312 | 3956 | abort (); |
2bfcf297 | 3957 | |
af8cb5c5 DE |
3958 | insn = get_last_insn (); |
3959 | set = single_set (insn); | |
3960 | if (! CONSTANT_P (SET_SRC (set))) | |
3961 | set_unique_reg_note (insn, REG_EQUAL, source); | |
3962 | ||
3963 | return result; | |
2bfcf297 DB |
3964 | } |
3965 | ||
3966 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
3967 | fall back to a straight forward decomposition. We do this to avoid | |
3968 | exponential run times encountered when looking for longer sequences | |
3969 | with rs6000_emit_set_const. */ | |
3970 | static rtx | |
a2369ed3 | 3971 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
3972 | { |
3973 | if (!TARGET_POWERPC64) | |
3974 | { | |
3975 | rtx operand1, operand2; | |
3976 | ||
3977 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
3978 | DImode); | |
3979 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
3980 | DImode); | |
3981 | emit_move_insn (operand1, GEN_INT (c1)); | |
3982 | emit_move_insn (operand2, GEN_INT (c2)); | |
3983 | } | |
3984 | else | |
3985 | { | |
bc06712d | 3986 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 3987 | |
bc06712d | 3988 | ud1 = c1 & 0xffff; |
f921c9c9 | 3989 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 3990 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 3991 | c2 = c1 >> 32; |
2bfcf297 | 3992 | #endif |
bc06712d | 3993 | ud3 = c2 & 0xffff; |
f921c9c9 | 3994 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 3995 | |
bc06712d TR |
3996 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
3997 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) | |
2bfcf297 | 3998 | { |
bc06712d | 3999 | if (ud1 & 0x8000) |
b78d48dd | 4000 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
4001 | else |
4002 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 4003 | } |
2bfcf297 | 4004 | |
bc06712d TR |
4005 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
4006 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) | |
252b88f7 | 4007 | { |
bc06712d TR |
4008 | if (ud2 & 0x8000) |
4009 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) | |
4010 | - 0x80000000)); | |
252b88f7 | 4011 | else |
bc06712d TR |
4012 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
4013 | if (ud1 != 0) | |
4014 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 4015 | } |
bc06712d TR |
4016 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
4017 | || (ud4 == 0 && ! (ud3 & 0x8000))) | |
4018 | { | |
4019 | if (ud3 & 0x8000) | |
4020 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) | |
4021 | - 0x80000000)); | |
4022 | else | |
4023 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
4024 | ||
4025 | if (ud2 != 0) | |
4026 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
4027 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
4028 | if (ud1 != 0) | |
4029 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
4030 | } | |
4031 | else | |
4032 | { | |
4033 | if (ud4 & 0x8000) | |
4034 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) | |
4035 | - 0x80000000)); | |
4036 | else | |
4037 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
4038 | ||
4039 | if (ud3 != 0) | |
4040 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 4041 | |
bc06712d TR |
4042 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
4043 | if (ud2 != 0) | |
4044 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, | |
4045 | GEN_INT (ud2 << 16))); | |
4046 | if (ud1 != 0) | |
4047 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
4048 | } | |
4049 | } | |
2bfcf297 DB |
4050 | return dest; |
4051 | } | |
4052 | ||
76d2b81d DJ |
4053 | /* Helper for the following. Get rid of [r+r] memory refs |
4054 | in cases where it won't work (TImode, TFmode). */ | |
4055 | ||
4056 | static void | |
4057 | rs6000_eliminate_indexed_memrefs (rtx operands[2]) | |
4058 | { | |
4059 | if (GET_CODE (operands[0]) == MEM | |
4060 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
4061 | && ! reload_in_progress) | |
4062 | operands[0] | |
4063 | = replace_equiv_address (operands[0], | |
4064 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
4065 | ||
4066 | if (GET_CODE (operands[1]) == MEM | |
4067 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
4068 | && ! reload_in_progress) | |
4069 | operands[1] | |
4070 | = replace_equiv_address (operands[1], | |
4071 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
4072 | } | |
4073 | ||
fb4d4348 GK |
4074 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
4075 | void | |
a2369ed3 | 4076 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
4077 | { |
4078 | rtx operands[2]; | |
4079 | operands[0] = dest; | |
4080 | operands[1] = source; | |
4081 | ||
4082 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
4083 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
4084 | && ! FLOAT_MODE_P (mode) | |
4085 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
4086 | { | |
4087 | /* FIXME. This should never happen. */ | |
4088 | /* Since it seems that it does, do the safe thing and convert | |
4089 | to a CONST_INT. */ | |
2496c7bd | 4090 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 GK |
4091 | } |
4092 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
4093 | && ! FLOAT_MODE_P (mode) | |
4094 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
4095 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
4096 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
4097 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
4098 | abort (); | |
c9e8cb32 DD |
4099 | |
4100 | /* Check if GCC is setting up a block move that will end up using FP | |
4101 | registers as temporaries. We must make sure this is acceptable. */ | |
4102 | if (GET_CODE (operands[0]) == MEM | |
4103 | && GET_CODE (operands[1]) == MEM | |
4104 | && mode == DImode | |
41543739 GK |
4105 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
4106 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
4107 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
4108 | ? 32 : MEM_ALIGN (operands[0]))) | |
4109 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
4110 | ? 32 | |
4111 | : MEM_ALIGN (operands[1])))) | |
4112 | && ! MEM_VOLATILE_P (operands [0]) | |
4113 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 4114 | { |
41543739 GK |
4115 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
4116 | adjust_address (operands[1], SImode, 0)); | |
4117 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
4118 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
4119 | return; |
4120 | } | |
630d42a0 | 4121 | |
67cef334 DE |
4122 | if (!no_new_pseudos) |
4123 | { | |
4124 | if (GET_CODE (operands[1]) == MEM && optimize > 0 | |
4125 | && (mode == QImode || mode == HImode || mode == SImode) | |
4126 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode)) | |
4127 | { | |
4128 | rtx reg = gen_reg_rtx (word_mode); | |
4129 | ||
4130 | emit_insn (gen_rtx_SET (word_mode, reg, | |
4131 | gen_rtx_ZERO_EXTEND (word_mode, | |
4132 | operands[1]))); | |
4133 | operands[1] = gen_lowpart (mode, reg); | |
4134 | } | |
4135 | if (GET_CODE (operands[0]) != REG) | |
4136 | operands[1] = force_reg (mode, operands[1]); | |
4137 | } | |
a9098fd0 | 4138 | |
a3170dc6 AH |
4139 | if (mode == SFmode && ! TARGET_POWERPC |
4140 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 4141 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 4142 | { |
ffc14f31 GK |
4143 | int regnum; |
4144 | ||
4145 | if (reload_in_progress || reload_completed) | |
4146 | regnum = true_regnum (operands[1]); | |
4147 | else if (GET_CODE (operands[1]) == REG) | |
4148 | regnum = REGNO (operands[1]); | |
4149 | else | |
4150 | regnum = -1; | |
fb4d4348 GK |
4151 | |
4152 | /* If operands[1] is a register, on POWER it may have | |
4153 | double-precision data in it, so truncate it to single | |
4154 | precision. */ | |
4155 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
4156 | { | |
4157 | rtx newreg; | |
4158 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
4159 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
4160 | operands[1] = newreg; | |
4161 | } | |
4162 | } | |
4163 | ||
c4501e62 JJ |
4164 | /* Recognize the case where operand[1] is a reference to thread-local |
4165 | data and load its address to a register. */ | |
4166 | if (GET_CODE (operands[1]) == SYMBOL_REF) | |
4167 | { | |
4168 | enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]); | |
4169 | if (model != 0) | |
4170 | operands[1] = rs6000_legitimize_tls_address (operands[1], model); | |
4171 | } | |
4172 | ||
8f4e6caf RH |
4173 | /* Handle the case where reload calls us with an invalid address. */ |
4174 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 4175 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
4176 | || ! nonimmediate_operand (operands[0], mode))) |
4177 | goto emit_set; | |
4178 | ||
a9baceb1 GK |
4179 | /* 128-bit constant floating-point values on Darwin should really be |
4180 | loaded as two parts. */ | |
4181 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
4182 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
4183 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) | |
4184 | { | |
4185 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
4186 | know how to get a DFmode SUBREG of a TFmode. */ | |
4187 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), | |
4188 | simplify_gen_subreg (DImode, operands[1], mode, 0), | |
4189 | DImode); | |
4190 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, | |
4191 | GET_MODE_SIZE (DImode)), | |
4192 | simplify_gen_subreg (DImode, operands[1], mode, | |
4193 | GET_MODE_SIZE (DImode)), | |
4194 | DImode); | |
4195 | return; | |
4196 | } | |
4197 | ||
fb4d4348 GK |
4198 | /* FIXME: In the long term, this switch statement should go away |
4199 | and be replaced by a sequence of tests based on things like | |
4200 | mode == Pmode. */ | |
4201 | switch (mode) | |
4202 | { | |
4203 | case HImode: | |
4204 | case QImode: | |
4205 | if (CONSTANT_P (operands[1]) | |
4206 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 4207 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
4208 | break; |
4209 | ||
06f4e019 | 4210 | case TFmode: |
76d2b81d DJ |
4211 | rs6000_eliminate_indexed_memrefs (operands); |
4212 | /* fall through */ | |
4213 | ||
fb4d4348 GK |
4214 | case DFmode: |
4215 | case SFmode: | |
4216 | if (CONSTANT_P (operands[1]) | |
4217 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 4218 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
4219 | break; |
4220 | ||
0ac081f6 AH |
4221 | case V16QImode: |
4222 | case V8HImode: | |
4223 | case V4SFmode: | |
4224 | case V4SImode: | |
a3170dc6 AH |
4225 | case V4HImode: |
4226 | case V2SFmode: | |
4227 | case V2SImode: | |
00a892b8 | 4228 | case V1DImode: |
69ef87e2 | 4229 | if (CONSTANT_P (operands[1]) |
d744e06e | 4230 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
4231 | operands[1] = force_const_mem (mode, operands[1]); |
4232 | break; | |
4233 | ||
fb4d4348 | 4234 | case SImode: |
a9098fd0 | 4235 | case DImode: |
fb4d4348 GK |
4236 | /* Use default pattern for address of ELF small data */ |
4237 | if (TARGET_ELF | |
a9098fd0 | 4238 | && mode == Pmode |
f607bc57 | 4239 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
4240 | && (GET_CODE (operands[1]) == SYMBOL_REF |
4241 | || GET_CODE (operands[1]) == CONST) | |
4242 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
4243 | { |
4244 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
4245 | return; | |
4246 | } | |
4247 | ||
f607bc57 | 4248 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
4249 | && mode == Pmode && mode == SImode |
4250 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
4251 | { |
4252 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
4253 | return; | |
4254 | } | |
4255 | ||
ee890fe2 | 4256 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
4257 | && TARGET_NO_TOC |
4258 | && ! flag_pic | |
a9098fd0 | 4259 | && mode == Pmode |
fb4d4348 GK |
4260 | && CONSTANT_P (operands[1]) |
4261 | && GET_CODE (operands[1]) != HIGH | |
4262 | && GET_CODE (operands[1]) != CONST_INT) | |
4263 | { | |
a9098fd0 | 4264 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
4265 | |
4266 | /* If this is a function address on -mcall-aixdesc, | |
4267 | convert it to the address of the descriptor. */ | |
4268 | if (DEFAULT_ABI == ABI_AIX | |
4269 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4270 | && XSTR (operands[1], 0)[0] == '.') | |
4271 | { | |
4272 | const char *name = XSTR (operands[1], 0); | |
4273 | rtx new_ref; | |
4274 | while (*name == '.') | |
4275 | name++; | |
4276 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
4277 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
4278 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 4279 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 4280 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 4281 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
4282 | operands[1] = new_ref; |
4283 | } | |
7509c759 | 4284 | |
ee890fe2 SS |
4285 | if (DEFAULT_ABI == ABI_DARWIN) |
4286 | { | |
ab82a49f AP |
4287 | #if TARGET_MACHO |
4288 | if (MACHO_DYNAMIC_NO_PIC_P) | |
4289 | { | |
4290 | /* Take care of any required data indirection. */ | |
4291 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
4292 | operands[1], mode, operands[0]); | |
4293 | if (operands[0] != operands[1]) | |
4294 | emit_insn (gen_rtx_SET (VOIDmode, | |
4295 | operands[0], operands[1])); | |
4296 | return; | |
4297 | } | |
4298 | #endif | |
ee890fe2 SS |
4299 | emit_insn (gen_macho_high (target, operands[1])); |
4300 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
4301 | return; | |
4302 | } | |
4303 | ||
fb4d4348 GK |
4304 | emit_insn (gen_elf_high (target, operands[1])); |
4305 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
4306 | return; | |
4307 | } | |
4308 | ||
a9098fd0 GK |
4309 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
4310 | and we have put it in the TOC, we just need to make a TOC-relative | |
4311 | reference to it. */ | |
4312 | if (TARGET_TOC | |
4313 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 4314 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
4315 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
4316 | get_pool_mode (operands[1]))) | |
fb4d4348 | 4317 | { |
a9098fd0 | 4318 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 4319 | } |
a9098fd0 GK |
4320 | else if (mode == Pmode |
4321 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
4322 | && ((GET_CODE (operands[1]) != CONST_INT |
4323 | && ! easy_fp_constant (operands[1], mode)) | |
4324 | || (GET_CODE (operands[1]) == CONST_INT | |
4325 | && num_insns_constant (operands[1], mode) > 2) | |
4326 | || (GET_CODE (operands[0]) == REG | |
4327 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 4328 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
4329 | && ! legitimate_constant_pool_address_p (operands[1]) |
4330 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
4331 | { |
4332 | /* Emit a USE operation so that the constant isn't deleted if | |
4333 | expensive optimizations are turned on because nobody | |
4334 | references it. This should only be done for operands that | |
4335 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
4336 | This should not be done for operands that contain LABEL_REFs. | |
4337 | For now, we just handle the obvious case. */ | |
4338 | if (GET_CODE (operands[1]) != LABEL_REF) | |
4339 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
4340 | ||
c859cda6 | 4341 | #if TARGET_MACHO |
ee890fe2 | 4342 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 4343 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 4344 | { |
ee890fe2 SS |
4345 | operands[1] = |
4346 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
4347 | operands[0]); |
4348 | if (operands[0] != operands[1]) | |
4349 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
4350 | return; |
4351 | } | |
c859cda6 | 4352 | #endif |
ee890fe2 | 4353 | |
fb4d4348 GK |
4354 | /* If we are to limit the number of things we put in the TOC and |
4355 | this is a symbol plus a constant we can add in one insn, | |
4356 | just put the symbol in the TOC and add the constant. Don't do | |
4357 | this if reload is in progress. */ | |
4358 | if (GET_CODE (operands[1]) == CONST | |
4359 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
4360 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 4361 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
4362 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
4363 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
4364 | && ! side_effects_p (operands[0])) | |
4365 | { | |
a4f6c312 SS |
4366 | rtx sym = |
4367 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
4368 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
4369 | ||
a9098fd0 GK |
4370 | sym = force_reg (mode, sym); |
4371 | if (mode == SImode) | |
4372 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
4373 | else | |
4374 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
4375 | return; |
4376 | } | |
4377 | ||
a9098fd0 | 4378 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
4379 | |
4380 | if (TARGET_TOC | |
4d588c14 | 4381 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
4382 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
4383 | get_pool_constant (XEXP (operands[1], 0)), | |
4384 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 4385 | { |
ba4828e0 RK |
4386 | operands[1] |
4387 | = gen_rtx_MEM (mode, | |
4388 | create_TOC_reference (XEXP (operands[1], 0))); | |
4389 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 4390 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 4391 | } |
fb4d4348 GK |
4392 | } |
4393 | break; | |
a9098fd0 | 4394 | |
fb4d4348 | 4395 | case TImode: |
76d2b81d DJ |
4396 | rs6000_eliminate_indexed_memrefs (operands); |
4397 | ||
27dc0551 DE |
4398 | if (TARGET_POWER) |
4399 | { | |
4400 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
4401 | gen_rtvec (2, | |
4402 | gen_rtx_SET (VOIDmode, | |
4403 | operands[0], operands[1]), | |
4404 | gen_rtx_CLOBBER (VOIDmode, | |
4405 | gen_rtx_SCRATCH (SImode))))); | |
4406 | return; | |
4407 | } | |
fb4d4348 GK |
4408 | break; |
4409 | ||
4410 | default: | |
4411 | abort (); | |
4412 | } | |
4413 | ||
a9098fd0 GK |
4414 | /* Above, we may have called force_const_mem which may have returned |
4415 | an invalid address. If we can, fix this up; otherwise, reload will | |
4416 | have to deal with it. */ | |
8f4e6caf RH |
4417 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
4418 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 4419 | |
8f4e6caf | 4420 | emit_set: |
fb4d4348 GK |
4421 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
4422 | } | |
4697a36c | 4423 | \f |
2858f73a GK |
4424 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
4425 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
4426 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
4427 | && (CUM)->fregno <= FP_ARG_MAX_REG \ | |
4428 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
4429 | ||
4430 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
4431 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
4432 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
4433 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
4434 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 4435 | && (NAMED)) |
2858f73a | 4436 | |
c6e8c921 GK |
4437 | /* Return a nonzero value to say to return the function value in |
4438 | memory, just as large structures are always returned. TYPE will be | |
4439 | the data type of the value, and FNTYPE will be the type of the | |
4440 | function doing the returning, or @code{NULL} for libcalls. | |
4441 | ||
4442 | The AIX ABI for the RS/6000 specifies that all structures are | |
4443 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
4444 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
4445 | draft put them in memory, and GCC used to implement the draft | |
4446 | instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET | |
4447 | controls this instead of DEFAULT_ABI; V.4 targets needing backward | |
4448 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
4449 | default, and -m switches get the final word. See | |
4450 | rs6000_override_options for more details. | |
4451 | ||
4452 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
4453 | long double support is enabled. These values are returned in memory. | |
4454 | ||
4455 | int_size_in_bytes returns -1 for variable size objects, which go in | |
4456 | memory always. The cast to unsigned makes -1 > 8. */ | |
4457 | ||
4458 | static bool | |
4459 | rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
4460 | { | |
4461 | if (AGGREGATE_TYPE_P (type) | |
4462 | && (TARGET_AIX_STRUCT_RET | |
4463 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) | |
4464 | return true; | |
4465 | if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode) | |
4466 | return true; | |
4467 | return false; | |
4468 | } | |
4469 | ||
4697a36c MM |
4470 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
4471 | for a call to a function whose data type is FNTYPE. | |
4472 | For a library call, FNTYPE is 0. | |
4473 | ||
4474 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 4475 | so we never return a PARALLEL. */ |
4697a36c MM |
4476 | |
4477 | void | |
a2369ed3 | 4478 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
4479 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
4480 | int libcall, int n_named_args) | |
4697a36c MM |
4481 | { |
4482 | static CUMULATIVE_ARGS zero_cumulative; | |
4483 | ||
4484 | *cum = zero_cumulative; | |
4485 | cum->words = 0; | |
4486 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 4487 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 4488 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
4489 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
4490 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 4491 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
4492 | cum->stdarg = fntype |
4493 | && (TYPE_ARG_TYPES (fntype) != 0 | |
4494 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
4495 | != void_type_node)); | |
4697a36c | 4496 | |
0f6937fe AM |
4497 | cum->nargs_prototype = 0; |
4498 | if (incoming || cum->prototype) | |
4499 | cum->nargs_prototype = n_named_args; | |
4697a36c | 4500 | |
a5c76ee6 ZW |
4501 | /* Check for a longcall attribute. */ |
4502 | if (fntype | |
4503 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
4504 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
4505 | cum->call_cookie = CALL_LONG; |
4506 | ||
4697a36c MM |
4507 | if (TARGET_DEBUG_ARG) |
4508 | { | |
4509 | fprintf (stderr, "\ninit_cumulative_args:"); | |
4510 | if (fntype) | |
4511 | { | |
4512 | tree ret_type = TREE_TYPE (fntype); | |
4513 | fprintf (stderr, " ret code = %s,", | |
4514 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
4515 | } | |
4516 | ||
6a4cee5f MM |
4517 | if (cum->call_cookie & CALL_LONG) |
4518 | fprintf (stderr, " longcall,"); | |
4519 | ||
4697a36c MM |
4520 | fprintf (stderr, " proto = %d, nargs = %d\n", |
4521 | cum->prototype, cum->nargs_prototype); | |
4522 | } | |
6d0ef01e HP |
4523 | |
4524 | if (fntype | |
4525 | && !TARGET_ALTIVEC | |
4526 | && TARGET_ALTIVEC_ABI | |
4527 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) | |
4528 | { | |
4529 | error ("Cannot return value in vector register because" | |
4530 | " altivec instructions are disabled, use -maltivec" | |
4531 | " to enable them."); | |
4532 | } | |
4697a36c MM |
4533 | } |
4534 | \f | |
fe984136 RH |
4535 | /* Return true if TYPE must be passed on the stack and not in registers. */ |
4536 | ||
4537 | static bool | |
4538 | rs6000_must_pass_in_stack (enum machine_mode mode, tree type) | |
4539 | { | |
4540 | if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT) | |
4541 | return must_pass_in_stack_var_size (mode, type); | |
4542 | else | |
4543 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
4544 | } | |
4545 | ||
c229cba9 DE |
4546 | /* If defined, a C expression which determines whether, and in which |
4547 | direction, to pad out an argument with extra space. The value | |
4548 | should be of type `enum direction': either `upward' to pad above | |
4549 | the argument, `downward' to pad below, or `none' to inhibit | |
4550 | padding. | |
4551 | ||
4552 | For the AIX ABI structs are always stored left shifted in their | |
4553 | argument slot. */ | |
4554 | ||
9ebbca7d | 4555 | enum direction |
a2369ed3 | 4556 | function_arg_padding (enum machine_mode mode, tree type) |
c229cba9 | 4557 | { |
6e985040 AM |
4558 | #ifndef AGGREGATE_PADDING_FIXED |
4559 | #define AGGREGATE_PADDING_FIXED 0 | |
4560 | #endif | |
4561 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
4562 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
4563 | #endif | |
4564 | ||
4565 | if (!AGGREGATE_PADDING_FIXED) | |
4566 | { | |
4567 | /* GCC used to pass structures of the same size as integer types as | |
4568 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
4569 | ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were | |
4570 | passed padded downward, except that -mstrict-align further | |
4571 | muddied the water in that multi-component structures of 2 and 4 | |
4572 | bytes in size were passed padded upward. | |
4573 | ||
4574 | The following arranges for best compatibility with previous | |
4575 | versions of gcc, but removes the -mstrict-align dependency. */ | |
4576 | if (BYTES_BIG_ENDIAN) | |
4577 | { | |
4578 | HOST_WIDE_INT size = 0; | |
4579 | ||
4580 | if (mode == BLKmode) | |
4581 | { | |
4582 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
4583 | size = int_size_in_bytes (type); | |
4584 | } | |
4585 | else | |
4586 | size = GET_MODE_SIZE (mode); | |
4587 | ||
4588 | if (size == 1 || size == 2 || size == 4) | |
4589 | return downward; | |
4590 | } | |
4591 | return upward; | |
4592 | } | |
4593 | ||
4594 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
4595 | { | |
4596 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
4597 | return upward; | |
4598 | } | |
c229cba9 | 4599 | |
95674810 DE |
4600 | /* SFmode parameters are not padded. */ |
4601 | if (TARGET_64BIT && mode == SFmode) | |
4602 | return none; | |
4603 | ||
d3704c46 KH |
4604 | /* Fall back to the default. */ |
4605 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
4606 | } |
4607 | ||
b6c9286a MM |
4608 | /* If defined, a C expression that gives the alignment boundary, in bits, |
4609 | of an argument with the specified mode and type. If it is not defined, | |
4610 | PARM_BOUNDARY is used for all arguments. | |
4611 | ||
2310f99a | 4612 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
4613 | |
4614 | int | |
a2369ed3 | 4615 | function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED) |
b6c9286a | 4616 | { |
4ed78545 AM |
4617 | if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8) |
4618 | return 64; | |
4619 | else if (SPE_VECTOR_MODE (mode)) | |
e1f83b4d | 4620 | return 64; |
b2d04ecf | 4621 | else if (ALTIVEC_VECTOR_MODE (mode)) |
0ac081f6 | 4622 | return 128; |
9ebbca7d | 4623 | else |
b6c9286a | 4624 | return PARM_BOUNDARY; |
b6c9286a | 4625 | } |
c53bdcf5 AM |
4626 | |
4627 | /* Compute the size (in words) of a function argument. */ | |
4628 | ||
4629 | static unsigned long | |
4630 | rs6000_arg_size (enum machine_mode mode, tree type) | |
4631 | { | |
4632 | unsigned long size; | |
4633 | ||
4634 | if (mode != BLKmode) | |
4635 | size = GET_MODE_SIZE (mode); | |
4636 | else | |
4637 | size = int_size_in_bytes (type); | |
4638 | ||
4639 | if (TARGET_32BIT) | |
4640 | return (size + 3) >> 2; | |
4641 | else | |
4642 | return (size + 7) >> 3; | |
4643 | } | |
b6c9286a | 4644 | \f |
4697a36c MM |
4645 | /* Update the data in CUM to advance over an argument |
4646 | of mode MODE and data type TYPE. | |
b2d04ecf AM |
4647 | (TYPE is null for libcalls where that information may not be available.) |
4648 | ||
4649 | Note that for args passed by reference, function_arg will be called | |
4650 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4651 | itself. */ | |
4697a36c MM |
4652 | |
4653 | void | |
a2369ed3 DJ |
4654 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4655 | tree type, int named) | |
4697a36c MM |
4656 | { |
4657 | cum->nargs_prototype--; | |
4658 | ||
0ac081f6 AH |
4659 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
4660 | { | |
4ed78545 AM |
4661 | bool stack = false; |
4662 | ||
2858f73a | 4663 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
6d0ef01e HP |
4664 | { |
4665 | cum->vregno++; | |
4666 | if (!TARGET_ALTIVEC) | |
4667 | error ("Cannot pass argument in vector register because" | |
4668 | " altivec instructions are disabled, use -maltivec" | |
4669 | " to enable them."); | |
4ed78545 AM |
4670 | |
4671 | /* PowerPC64 Linux and AIX allocate GPRs for a vector argument | |
4672 | even if it is going to be passed in a vector register. | |
4673 | Darwin does the same for variable-argument functions. */ | |
4674 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4675 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
4676 | stack = true; | |
6d0ef01e | 4677 | } |
4ed78545 AM |
4678 | else |
4679 | stack = true; | |
4680 | ||
4681 | if (stack) | |
c72d6c26 | 4682 | { |
a594a19c GK |
4683 | int align; |
4684 | ||
2858f73a GK |
4685 | /* Vector parameters must be 16-byte aligned. This places |
4686 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
4687 | the parameter save area starts at offset 24 from the | |
4688 | stack. In 64-bit mode, they just have to start on an | |
4689 | even word, since the parameter save area is 16-byte | |
4690 | aligned. Space for GPRs is reserved even if the argument | |
4691 | will be passed in memory. */ | |
4692 | if (TARGET_32BIT) | |
4ed78545 | 4693 | align = (2 - cum->words) & 3; |
2858f73a GK |
4694 | else |
4695 | align = cum->words & 1; | |
c53bdcf5 | 4696 | cum->words += align + rs6000_arg_size (mode, type); |
2858f73a | 4697 | |
a594a19c GK |
4698 | if (TARGET_DEBUG_ARG) |
4699 | { | |
4700 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", | |
4701 | cum->words, align); | |
4702 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
2858f73a GK |
4703 | cum->nargs_prototype, cum->prototype, |
4704 | GET_MODE_NAME (mode)); | |
a594a19c GK |
4705 | } |
4706 | } | |
0ac081f6 | 4707 | } |
a4b0320c | 4708 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
4709 | && !cum->stdarg |
4710 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 4711 | cum->sysv_gregno++; |
f607bc57 | 4712 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4713 | { |
a3170dc6 | 4714 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 4715 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 4716 | { |
4cc833b7 RH |
4717 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
4718 | cum->fregno++; | |
4719 | else | |
4720 | { | |
4721 | if (mode == DFmode) | |
4722 | cum->words += cum->words & 1; | |
c53bdcf5 | 4723 | cum->words += rs6000_arg_size (mode, type); |
4cc833b7 | 4724 | } |
4697a36c | 4725 | } |
4cc833b7 RH |
4726 | else |
4727 | { | |
b2d04ecf | 4728 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4729 | int gregno = cum->sysv_gregno; |
4730 | ||
4ed78545 AM |
4731 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4732 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4733 | as complex int due to a historical mistake. */ | |
4734 | if (n_words == 2) | |
4735 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4736 | |
4ed78545 | 4737 | /* Multi-reg args are not split between registers and stack. */ |
4cc833b7 RH |
4738 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
4739 | { | |
4ed78545 AM |
4740 | /* Long long and SPE vectors are aligned on the stack. |
4741 | So are other 2 word items such as complex int due to | |
4742 | a historical mistake. */ | |
4cc833b7 RH |
4743 | if (n_words == 2) |
4744 | cum->words += cum->words & 1; | |
4745 | cum->words += n_words; | |
4746 | } | |
4697a36c | 4747 | |
4cc833b7 RH |
4748 | /* Note: continuing to accumulate gregno past when we've started |
4749 | spilling to the stack indicates the fact that we've started | |
4750 | spilling to the stack to expand_builtin_saveregs. */ | |
4751 | cum->sysv_gregno = gregno + n_words; | |
4752 | } | |
4697a36c | 4753 | |
4cc833b7 RH |
4754 | if (TARGET_DEBUG_ARG) |
4755 | { | |
4756 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4757 | cum->words, cum->fregno); | |
4758 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
4759 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
4760 | fprintf (stderr, "mode = %4s, named = %d\n", | |
4761 | GET_MODE_NAME (mode), named); | |
4762 | } | |
4697a36c MM |
4763 | } |
4764 | else | |
4cc833b7 | 4765 | { |
b2d04ecf AM |
4766 | int n_words = rs6000_arg_size (mode, type); |
4767 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; | |
a4f6c312 | 4768 | |
b2d04ecf AM |
4769 | /* The simple alignment calculation here works because |
4770 | function_arg_boundary / PARM_BOUNDARY will only be 1 or 2. | |
4771 | If we ever want to handle alignments larger than 8 bytes for | |
4772 | 32-bit or 16 bytes for 64-bit, then we'll need to take into | |
4773 | account the offset to the start of the parm save area. */ | |
4774 | align &= cum->words; | |
4775 | cum->words += align + n_words; | |
4697a36c | 4776 | |
a3170dc6 AH |
4777 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
4778 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
c53bdcf5 | 4779 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; |
4cc833b7 RH |
4780 | |
4781 | if (TARGET_DEBUG_ARG) | |
4782 | { | |
4783 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4784 | cum->words, cum->fregno); | |
4785 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
4786 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
4787 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
4788 | } | |
4789 | } | |
4697a36c | 4790 | } |
a6c9bed4 AH |
4791 | |
4792 | /* Determine where to put a SIMD argument on the SPE. */ | |
b78d48dd | 4793 | |
a6c9bed4 | 4794 | static rtx |
a2369ed3 DJ |
4795 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4796 | tree type) | |
a6c9bed4 AH |
4797 | { |
4798 | if (cum->stdarg) | |
4799 | { | |
4800 | int gregno = cum->sysv_gregno; | |
c53bdcf5 | 4801 | int n_words = rs6000_arg_size (mode, type); |
a6c9bed4 AH |
4802 | |
4803 | /* SPE vectors are put in odd registers. */ | |
4804 | if (n_words == 2 && (gregno & 1) == 0) | |
4805 | gregno += 1; | |
4806 | ||
4807 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
4808 | { | |
4809 | rtx r1, r2; | |
4810 | enum machine_mode m = SImode; | |
4811 | ||
4812 | r1 = gen_rtx_REG (m, gregno); | |
4813 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
4814 | r2 = gen_rtx_REG (m, gregno + 1); | |
4815 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
4816 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
4817 | } | |
4818 | else | |
b78d48dd | 4819 | return NULL_RTX; |
a6c9bed4 AH |
4820 | } |
4821 | else | |
4822 | { | |
4823 | if (cum->sysv_gregno <= GP_ARG_MAX_REG) | |
4824 | return gen_rtx_REG (mode, cum->sysv_gregno); | |
4825 | else | |
b78d48dd | 4826 | return NULL_RTX; |
a6c9bed4 AH |
4827 | } |
4828 | } | |
4829 | ||
b78d48dd FJ |
4830 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
4831 | ||
4832 | static rtx | |
ec6376ab | 4833 | rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) |
b78d48dd | 4834 | { |
ec6376ab AM |
4835 | int n_units; |
4836 | int i, k; | |
4837 | rtx rvec[GP_ARG_NUM_REG + 1]; | |
4838 | ||
4839 | if (align_words >= GP_ARG_NUM_REG) | |
4840 | return NULL_RTX; | |
4841 | ||
4842 | n_units = rs6000_arg_size (mode, type); | |
4843 | ||
4844 | /* Optimize the simple case where the arg fits in one gpr, except in | |
4845 | the case of BLKmode due to assign_parms assuming that registers are | |
4846 | BITS_PER_WORD wide. */ | |
4847 | if (n_units == 0 | |
4848 | || (n_units == 1 && mode != BLKmode)) | |
4849 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4850 | ||
4851 | k = 0; | |
4852 | if (align_words + n_units > GP_ARG_NUM_REG) | |
4853 | /* Not all of the arg fits in gprs. Say that it goes in memory too, | |
4854 | using a magic NULL_RTX component. | |
4855 | FIXME: This is not strictly correct. Only some of the arg | |
4856 | belongs in memory, not all of it. However, there isn't any way | |
4857 | to do this currently, apart from building rtx descriptions for | |
4858 | the pieces of memory we want stored. Due to bugs in the generic | |
4859 | code we can't use the normal function_arg_partial_nregs scheme | |
4860 | with the PARALLEL arg description we emit here. | |
4861 | In any case, the code to store the whole arg to memory is often | |
4862 | more efficient than code to store pieces, and we know that space | |
4863 | is available in the right place for the whole arg. */ | |
4864 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4865 | ||
4866 | i = 0; | |
4867 | do | |
36a454e1 | 4868 | { |
ec6376ab AM |
4869 | rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); |
4870 | rtx off = GEN_INT (i++ * 4); | |
4871 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
36a454e1 | 4872 | } |
ec6376ab AM |
4873 | while (++align_words < GP_ARG_NUM_REG && --n_units != 0); |
4874 | ||
4875 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
b78d48dd FJ |
4876 | } |
4877 | ||
4697a36c MM |
4878 | /* Determine where to put an argument to a function. |
4879 | Value is zero to push the argument on the stack, | |
4880 | or a hard register in which to store the argument. | |
4881 | ||
4882 | MODE is the argument's machine mode. | |
4883 | TYPE is the data type of the argument (as a tree). | |
4884 | This is null for libcalls where that information may | |
4885 | not be available. | |
4886 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4887 | the preceding args and about the function being called. | |
4888 | NAMED is nonzero if this argument is a named parameter | |
4889 | (otherwise it is an extra parameter matching an ellipsis). | |
4890 | ||
4891 | On RS/6000 the first eight words of non-FP are normally in registers | |
4892 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
4893 | Under V.4, the first 8 FP args are in registers. | |
4894 | ||
4895 | If this is floating-point and no prototype is specified, we use | |
4896 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 4897 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 4898 | so we can pass the FP value just in one register. emit_library_function |
b2d04ecf AM |
4899 | doesn't support PARALLEL anyway. |
4900 | ||
4901 | Note that for args passed by reference, function_arg will be called | |
4902 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4903 | itself. */ | |
4697a36c MM |
4904 | |
4905 | struct rtx_def * | |
a2369ed3 DJ |
4906 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4907 | tree type, int named) | |
4697a36c | 4908 | { |
4cc833b7 | 4909 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 4910 | |
a4f6c312 SS |
4911 | /* Return a marker to indicate whether CR1 needs to set or clear the |
4912 | bit that V.4 uses to say fp args were passed in registers. | |
4913 | Assume that we don't need the marker for software floating point, | |
4914 | or compiler generated library calls. */ | |
4697a36c MM |
4915 | if (mode == VOIDmode) |
4916 | { | |
f607bc57 | 4917 | if (abi == ABI_V4 |
7509c759 | 4918 | && cum->nargs_prototype < 0 |
b9599e46 FS |
4919 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
4920 | && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
7509c759 | 4921 | { |
a3170dc6 AH |
4922 | /* For the SPE, we need to crxor CR6 always. */ |
4923 | if (TARGET_SPE_ABI) | |
4924 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
4925 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
4926 | return GEN_INT (cum->call_cookie | |
4927 | | ((cum->fregno == FP_ARG_MIN_REG) | |
4928 | ? CALL_V4_SET_FP_ARGS | |
4929 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 4930 | } |
4697a36c | 4931 | |
7509c759 | 4932 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
4933 | } |
4934 | ||
2858f73a | 4935 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
4936 | if (TARGET_64BIT && ! cum->prototype) |
4937 | { | |
4938 | /* Vector parameters get passed in vector register | |
4939 | and also in GPRs or memory, in absence of prototype. */ | |
4940 | int align_words; | |
4941 | rtx slot; | |
4942 | align_words = (cum->words + 1) & ~1; | |
4943 | ||
4944 | if (align_words >= GP_ARG_NUM_REG) | |
4945 | { | |
4946 | slot = NULL_RTX; | |
4947 | } | |
4948 | else | |
4949 | { | |
4950 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4951 | } | |
4952 | return gen_rtx_PARALLEL (mode, | |
4953 | gen_rtvec (2, | |
4954 | gen_rtx_EXPR_LIST (VOIDmode, | |
4955 | slot, const0_rtx), | |
4956 | gen_rtx_EXPR_LIST (VOIDmode, | |
4957 | gen_rtx_REG (mode, cum->vregno), | |
4958 | const0_rtx))); | |
4959 | } | |
4960 | else | |
4961 | return gen_rtx_REG (mode, cum->vregno); | |
2858f73a | 4962 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
0ac081f6 | 4963 | { |
2858f73a | 4964 | if (named || abi == ABI_V4) |
a594a19c | 4965 | return NULL_RTX; |
0ac081f6 | 4966 | else |
a594a19c GK |
4967 | { |
4968 | /* Vector parameters to varargs functions under AIX or Darwin | |
4969 | get passed in memory and possibly also in GPRs. */ | |
ec6376ab AM |
4970 | int align, align_words, n_words; |
4971 | enum machine_mode part_mode; | |
a594a19c GK |
4972 | |
4973 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
4974 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
4975 | save area starts at offset 24 from the stack. In 64-bit mode, | |
4976 | they just have to start on an even word, since the parameter | |
4977 | save area is 16-byte aligned. */ | |
4978 | if (TARGET_32BIT) | |
4ed78545 | 4979 | align = (2 - cum->words) & 3; |
2858f73a GK |
4980 | else |
4981 | align = cum->words & 1; | |
a594a19c GK |
4982 | align_words = cum->words + align; |
4983 | ||
4984 | /* Out of registers? Memory, then. */ | |
4985 | if (align_words >= GP_ARG_NUM_REG) | |
4986 | return NULL_RTX; | |
ec6376ab AM |
4987 | |
4988 | if (TARGET_32BIT && TARGET_POWERPC64) | |
4989 | return rs6000_mixed_function_arg (mode, type, align_words); | |
4990 | ||
2858f73a GK |
4991 | /* The vector value goes in GPRs. Only the part of the |
4992 | value in GPRs is reported here. */ | |
ec6376ab AM |
4993 | part_mode = mode; |
4994 | n_words = rs6000_arg_size (mode, type); | |
4995 | if (align_words + n_words > GP_ARG_NUM_REG) | |
839a4992 | 4996 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
4997 | is either wholly in GPRs or half in GPRs and half not. */ |
4998 | part_mode = DImode; | |
ec6376ab AM |
4999 | |
5000 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 5001 | } |
0ac081f6 | 5002 | } |
a6c9bed4 AH |
5003 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
5004 | return rs6000_spe_function_arg (cum, mode, type); | |
f607bc57 | 5005 | else if (abi == ABI_V4) |
4697a36c | 5006 | { |
a3170dc6 | 5007 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
5008 | && (mode == SFmode || mode == DFmode)) |
5009 | { | |
5010 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
5011 | return gen_rtx_REG (mode, cum->fregno); | |
5012 | else | |
b78d48dd | 5013 | return NULL_RTX; |
4cc833b7 RH |
5014 | } |
5015 | else | |
5016 | { | |
b2d04ecf | 5017 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
5018 | int gregno = cum->sysv_gregno; |
5019 | ||
4ed78545 AM |
5020 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
5021 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
5022 | as complex int due to a historical mistake. */ | |
5023 | if (n_words == 2) | |
5024 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 5025 | |
4ed78545 | 5026 | /* Multi-reg args are not split between registers and stack. */ |
ec6376ab | 5027 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
b78d48dd | 5028 | return NULL_RTX; |
ec6376ab AM |
5029 | |
5030 | if (TARGET_32BIT && TARGET_POWERPC64) | |
5031 | return rs6000_mixed_function_arg (mode, type, | |
5032 | gregno - GP_ARG_MIN_REG); | |
5033 | return gen_rtx_REG (mode, gregno); | |
4cc833b7 | 5034 | } |
4697a36c | 5035 | } |
4cc833b7 RH |
5036 | else |
5037 | { | |
b2d04ecf AM |
5038 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
5039 | int align_words = cum->words + (cum->words & align); | |
b78d48dd | 5040 | |
2858f73a | 5041 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 | 5042 | { |
ec6376ab AM |
5043 | rtx rvec[GP_ARG_NUM_REG + 1]; |
5044 | rtx r; | |
5045 | int k; | |
c53bdcf5 AM |
5046 | bool needs_psave; |
5047 | enum machine_mode fmode = mode; | |
c53bdcf5 AM |
5048 | unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; |
5049 | ||
5050 | if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) | |
5051 | { | |
c53bdcf5 AM |
5052 | /* Currently, we only ever need one reg here because complex |
5053 | doubles are split. */ | |
ec6376ab | 5054 | if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode) |
c53bdcf5 | 5055 | abort (); |
ec6376ab AM |
5056 | |
5057 | /* Long double split over regs and memory. */ | |
5058 | fmode = DFmode; | |
c53bdcf5 | 5059 | } |
c53bdcf5 AM |
5060 | |
5061 | /* Do we also need to pass this arg in the parameter save | |
5062 | area? */ | |
5063 | needs_psave = (type | |
5064 | && (cum->nargs_prototype <= 0 | |
5065 | || (DEFAULT_ABI == ABI_AIX | |
5066 | && TARGET_XL_CALL | |
5067 | && align_words >= GP_ARG_NUM_REG))); | |
5068 | ||
5069 | if (!needs_psave && mode == fmode) | |
ec6376ab | 5070 | return gen_rtx_REG (fmode, cum->fregno); |
c53bdcf5 | 5071 | |
ec6376ab | 5072 | k = 0; |
c53bdcf5 AM |
5073 | if (needs_psave) |
5074 | { | |
ec6376ab | 5075 | /* Describe the part that goes in gprs or the stack. |
c53bdcf5 | 5076 | This piece must come first, before the fprs. */ |
c53bdcf5 AM |
5077 | if (align_words < GP_ARG_NUM_REG) |
5078 | { | |
5079 | unsigned long n_words = rs6000_arg_size (mode, type); | |
ec6376ab AM |
5080 | |
5081 | if (align_words + n_words > GP_ARG_NUM_REG | |
5082 | || (TARGET_32BIT && TARGET_POWERPC64)) | |
5083 | { | |
5084 | /* If this is partially on the stack, then we only | |
5085 | include the portion actually in registers here. */ | |
5086 | enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; | |
5087 | rtx off; | |
5088 | do | |
5089 | { | |
5090 | r = gen_rtx_REG (rmode, | |
5091 | GP_ARG_MIN_REG + align_words); | |
5092 | off = GEN_INT (k * GET_MODE_SIZE (rmode)); | |
5093 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
5094 | } | |
5095 | while (++align_words < GP_ARG_NUM_REG && --n_words != 0); | |
5096 | } | |
5097 | else | |
5098 | { | |
5099 | /* The whole arg fits in gprs. */ | |
5100 | r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5101 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5102 | } | |
c53bdcf5 | 5103 | } |
ec6376ab AM |
5104 | else |
5105 | /* It's entirely in memory. */ | |
5106 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
c53bdcf5 AM |
5107 | } |
5108 | ||
ec6376ab AM |
5109 | /* Describe where this piece goes in the fprs. */ |
5110 | r = gen_rtx_REG (fmode, cum->fregno); | |
5111 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5112 | ||
5113 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
4cc833b7 RH |
5114 | } |
5115 | else if (align_words < GP_ARG_NUM_REG) | |
b2d04ecf | 5116 | { |
ec6376ab AM |
5117 | if (TARGET_32BIT && TARGET_POWERPC64) |
5118 | return rs6000_mixed_function_arg (mode, type, align_words); | |
b2d04ecf AM |
5119 | |
5120 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5121 | } | |
4cc833b7 RH |
5122 | else |
5123 | return NULL_RTX; | |
4697a36c | 5124 | } |
4697a36c MM |
5125 | } |
5126 | \f | |
ec6376ab AM |
5127 | /* For an arg passed partly in registers and partly in memory, this is |
5128 | the number of registers used. For args passed entirely in registers | |
5129 | or entirely in memory, zero. When an arg is described by a PARALLEL, | |
5130 | perhaps using more than one register type, this function returns the | |
5131 | number of registers used by the first element of the PARALLEL. */ | |
4697a36c MM |
5132 | |
5133 | int | |
a2369ed3 | 5134 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
2858f73a | 5135 | tree type, int named) |
4697a36c | 5136 | { |
c53bdcf5 | 5137 | int ret = 0; |
ec6376ab AM |
5138 | int align; |
5139 | int parm_offset; | |
5140 | int align_words; | |
c53bdcf5 | 5141 | |
f607bc57 | 5142 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 5143 | return 0; |
4697a36c | 5144 | |
c53bdcf5 AM |
5145 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) |
5146 | && cum->nargs_prototype >= 0) | |
5147 | return 0; | |
5148 | ||
ec6376ab AM |
5149 | align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
5150 | parm_offset = TARGET_32BIT ? 2 : 0; | |
5151 | align_words = cum->words + ((parm_offset - cum->words) & align); | |
5152 | ||
5153 | if (USE_FP_FOR_ARG_P (cum, mode, type) | |
5154 | /* If we are passing this arg in gprs as well, then this function | |
5155 | should return the number of gprs (or memory) partially passed, | |
5156 | *not* the number of fprs. */ | |
5157 | && !(type | |
5158 | && (cum->nargs_prototype <= 0 | |
5159 | || (DEFAULT_ABI == ABI_AIX | |
5160 | && TARGET_XL_CALL | |
5161 | && align_words >= GP_ARG_NUM_REG)))) | |
4697a36c | 5162 | { |
c53bdcf5 | 5163 | if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1) |
ec6376ab | 5164 | ret = FP_ARG_MAX_REG + 1 - cum->fregno; |
c53bdcf5 | 5165 | else if (cum->nargs_prototype >= 0) |
4697a36c MM |
5166 | return 0; |
5167 | } | |
5168 | ||
ec6376ab AM |
5169 | if (align_words < GP_ARG_NUM_REG |
5170 | && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) | |
5171 | ret = GP_ARG_NUM_REG - align_words; | |
4697a36c | 5172 | |
c53bdcf5 AM |
5173 | if (ret != 0 && TARGET_DEBUG_ARG) |
5174 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
4697a36c | 5175 | |
c53bdcf5 | 5176 | return ret; |
4697a36c MM |
5177 | } |
5178 | \f | |
5179 | /* A C expression that indicates when an argument must be passed by | |
5180 | reference. If nonzero for an argument, a copy of that argument is | |
5181 | made in memory and a pointer to the argument is passed instead of | |
5182 | the argument itself. The pointer is passed in whatever way is | |
5183 | appropriate for passing a pointer to that type. | |
5184 | ||
b2d04ecf AM |
5185 | Under V.4, aggregates and long double are passed by reference. |
5186 | ||
5187 | As an extension to all 32-bit ABIs, AltiVec vectors are passed by | |
5188 | reference unless the AltiVec vector extension ABI is in force. | |
c8c99a68 DE |
5189 | |
5190 | As an extension to all ABIs, variable sized types are passed by | |
5191 | reference. */ | |
4697a36c | 5192 | |
8cd5a4e0 RH |
5193 | static bool |
5194 | rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
5195 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
5196 | tree type, bool named ATTRIBUTE_UNUSED) | |
4697a36c | 5197 | { |
b2d04ecf AM |
5198 | if ((DEFAULT_ABI == ABI_V4 |
5199 | && ((type && AGGREGATE_TYPE_P (type)) | |
5200 | || mode == TFmode)) | |
5201 | || (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
5202 | || (type && int_size_in_bytes (type) < 0)) | |
4697a36c MM |
5203 | { |
5204 | if (TARGET_DEBUG_ARG) | |
b2d04ecf | 5205 | fprintf (stderr, "function_arg_pass_by_reference\n"); |
4697a36c MM |
5206 | |
5207 | return 1; | |
5208 | } | |
b2d04ecf | 5209 | return 0; |
4697a36c | 5210 | } |
5985c7a6 FJ |
5211 | |
5212 | static void | |
2d9db8eb | 5213 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
5214 | { |
5215 | int i; | |
5216 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
5217 | ||
5218 | if (nregs == 0) | |
5219 | return; | |
5220 | ||
5221 | for (i = 0; i < nregs; i++) | |
5222 | { | |
5223 | rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode)); | |
5224 | if (reload_completed) | |
5225 | { | |
5226 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
5227 | tem = NULL_RTX; | |
5228 | else | |
5229 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
5230 | i * GET_MODE_SIZE(reg_mode)); | |
5231 | } | |
5232 | else | |
5233 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
5234 | ||
5235 | if (tem == NULL_RTX) | |
5236 | abort (); | |
5237 | ||
5238 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
5239 | } | |
5240 | } | |
5241 | ||
4697a36c MM |
5242 | \f |
5243 | /* Perform any needed actions needed for a function that is receiving a | |
5244 | variable number of arguments. | |
5245 | ||
5246 | CUM is as above. | |
5247 | ||
5248 | MODE and TYPE are the mode and type of the current parameter. | |
5249 | ||
5250 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
5251 | that must be pushed by the prolog to pretend that our caller pushed | |
5252 | it. | |
5253 | ||
5254 | Normally, this macro will push all remaining incoming registers on the | |
5255 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
5256 | ||
c6e8c921 | 5257 | static void |
a2369ed3 DJ |
5258 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
5259 | tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl) | |
4697a36c | 5260 | { |
4cc833b7 RH |
5261 | CUMULATIVE_ARGS next_cum; |
5262 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 5263 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 5264 | int first_reg_offset, set; |
4697a36c | 5265 | |
f31bf321 | 5266 | /* Skip the last named argument. */ |
d34c5b80 | 5267 | next_cum = *cum; |
f31bf321 | 5268 | function_arg_advance (&next_cum, mode, type, 1); |
4cc833b7 | 5269 | |
f607bc57 | 5270 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 5271 | { |
4cc833b7 | 5272 | /* Indicate to allocate space on the stack for varargs save area. */ |
00dba523 | 5273 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 5274 | if (! no_rtl) |
2c4974b7 | 5275 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 5276 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
5277 | |
5278 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 5279 | } |
60e2d0ca | 5280 | else |
4697a36c | 5281 | { |
d34c5b80 | 5282 | first_reg_offset = next_cum.words; |
4cc833b7 | 5283 | save_area = virtual_incoming_args_rtx; |
00dba523 | 5284 | cfun->machine->sysv_varargs_p = 0; |
4697a36c | 5285 | |
fe984136 | 5286 | if (targetm.calls.must_pass_in_stack (mode, type)) |
c53bdcf5 | 5287 | first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); |
4cc833b7 | 5288 | } |
4697a36c | 5289 | |
dfafc897 | 5290 | set = get_varargs_alias_set (); |
c81fc13e | 5291 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 5292 | { |
dfafc897 FS |
5293 | mem = gen_rtx_MEM (BLKmode, |
5294 | plus_constant (save_area, | |
5295 | first_reg_offset * reg_size)), | |
ba4828e0 | 5296 | set_mem_alias_set (mem, set); |
8ac61af7 | 5297 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 5298 | |
5985c7a6 FJ |
5299 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
5300 | GP_ARG_NUM_REG - first_reg_offset); | |
4697a36c MM |
5301 | } |
5302 | ||
4697a36c | 5303 | /* Save FP registers if needed. */ |
f607bc57 | 5304 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
5305 | && TARGET_HARD_FLOAT && TARGET_FPRS |
5306 | && ! no_rtl | |
4cc833b7 | 5307 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 5308 | { |
4cc833b7 | 5309 | int fregno = next_cum.fregno; |
9ebbca7d | 5310 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
5311 | rtx lab = gen_label_rtx (); |
5312 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 5313 | |
4cc833b7 | 5314 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 5315 | pc_rtx, |
39403d82 | 5316 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
5317 | gen_rtx_NE (VOIDmode, cr1, |
5318 | const0_rtx), | |
39403d82 | 5319 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
5320 | pc_rtx))); |
5321 | ||
4cc833b7 RH |
5322 | while (fregno <= FP_ARG_V4_MAX_REG) |
5323 | { | |
dfafc897 | 5324 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 5325 | set_mem_alias_set (mem, set); |
dfafc897 | 5326 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
5327 | fregno++; |
5328 | off += 8; | |
4697a36c | 5329 | } |
4cc833b7 RH |
5330 | |
5331 | emit_label (lab); | |
4697a36c | 5332 | } |
4697a36c | 5333 | } |
4697a36c | 5334 | |
dfafc897 | 5335 | /* Create the va_list data type. */ |
2c4974b7 | 5336 | |
c35d187f RH |
5337 | static tree |
5338 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 5339 | { |
64c2816f | 5340 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 5341 | |
9ebbca7d GK |
5342 | /* For AIX, prefer 'char *' because that's what the system |
5343 | header files like. */ | |
f607bc57 | 5344 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 5345 | return build_pointer_type (char_type_node); |
dfafc897 | 5346 | |
f1e639b1 | 5347 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 5348 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 5349 | |
9ebbca7d GK |
5350 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
5351 | unsigned_char_type_node); | |
5352 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
5353 | unsigned_char_type_node); | |
64c2816f DT |
5354 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
5355 | every user file. */ | |
5356 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
5357 | short_unsigned_type_node); | |
dfafc897 FS |
5358 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
5359 | ptr_type_node); | |
5360 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
5361 | ptr_type_node); | |
5362 | ||
5363 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
5364 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 5365 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
5366 | DECL_FIELD_CONTEXT (f_ovf) = record; |
5367 | DECL_FIELD_CONTEXT (f_sav) = record; | |
5368 | ||
bab45a51 FS |
5369 | TREE_CHAIN (record) = type_decl; |
5370 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
5371 | TYPE_FIELDS (record) = f_gpr; |
5372 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
5373 | TREE_CHAIN (f_fpr) = f_res; |
5374 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
5375 | TREE_CHAIN (f_ovf) = f_sav; |
5376 | ||
5377 | layout_type (record); | |
5378 | ||
5379 | /* The correct type is an array type of one element. */ | |
5380 | return build_array_type (record, build_index_type (size_zero_node)); | |
5381 | } | |
5382 | ||
5383 | /* Implement va_start. */ | |
5384 | ||
5385 | void | |
a2369ed3 | 5386 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 5387 | { |
dfafc897 | 5388 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 5389 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 5390 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 5391 | |
dfafc897 | 5392 | /* Only SVR4 needs something special. */ |
f607bc57 | 5393 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 5394 | { |
e5faf155 | 5395 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
5396 | return; |
5397 | } | |
5398 | ||
973a648b | 5399 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 5400 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
5401 | f_res = TREE_CHAIN (f_fpr); |
5402 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
5403 | f_sav = TREE_CHAIN (f_ovf); |
5404 | ||
8ebecc3b | 5405 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
44de5aeb RK |
5406 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5407 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5408 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5409 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
dfafc897 FS |
5410 | |
5411 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 5412 | words = current_function_args_info.words; |
dfafc897 FS |
5413 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
5414 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
5415 | ||
5416 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
5417 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
5418 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
5419 | words, n_gpr, n_fpr); | |
dfafc897 FS |
5420 | |
5421 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
5422 | TREE_SIDE_EFFECTS (t) = 1; | |
5423 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5424 | ||
5425 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
5426 | TREE_SIDE_EFFECTS (t) = 1; | |
5427 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5428 | ||
5429 | /* Find the overflow area. */ | |
5430 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
5431 | if (words != 0) | |
5432 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
5433 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
5434 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
5435 | TREE_SIDE_EFFECTS (t) = 1; | |
5436 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5437 | ||
5438 | /* Find the register save area. */ | |
5439 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
5440 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
5441 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
5442 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
5443 | TREE_SIDE_EFFECTS (t) = 1; | |
5444 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5445 | } | |
5446 | ||
5447 | /* Implement va_arg. */ | |
5448 | ||
23a60a04 JM |
5449 | tree |
5450 | rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) | |
cd3ce9b4 | 5451 | { |
cd3ce9b4 JM |
5452 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
5453 | tree gpr, fpr, ovf, sav, reg, t, u; | |
08b0dc1b | 5454 | int size, rsize, n_reg, sav_ofs, sav_scale; |
cd3ce9b4 JM |
5455 | tree lab_false, lab_over, addr; |
5456 | int align; | |
5457 | tree ptrtype = build_pointer_type (type); | |
5458 | ||
08b0dc1b RH |
5459 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
5460 | { | |
5461 | t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); | |
5462 | return build_fold_indirect_ref (t); | |
5463 | } | |
5464 | ||
cd3ce9b4 JM |
5465 | if (DEFAULT_ABI != ABI_V4) |
5466 | { | |
08b0dc1b | 5467 | if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) |
cd3ce9b4 JM |
5468 | { |
5469 | tree elem_type = TREE_TYPE (type); | |
5470 | enum machine_mode elem_mode = TYPE_MODE (elem_type); | |
5471 | int elem_size = GET_MODE_SIZE (elem_mode); | |
5472 | ||
5473 | if (elem_size < UNITS_PER_WORD) | |
5474 | { | |
23a60a04 | 5475 | tree real_part, imag_part; |
cd3ce9b4 JM |
5476 | tree post = NULL_TREE; |
5477 | ||
23a60a04 JM |
5478 | real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5479 | &post); | |
5480 | /* Copy the value into a temporary, lest the formal temporary | |
5481 | be reused out from under us. */ | |
5482 | real_part = get_initialized_tmp_var (real_part, pre_p, &post); | |
cd3ce9b4 JM |
5483 | append_to_statement_list (post, pre_p); |
5484 | ||
23a60a04 JM |
5485 | imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5486 | post_p); | |
cd3ce9b4 | 5487 | |
23a60a04 | 5488 | return build (COMPLEX_EXPR, type, real_part, imag_part); |
cd3ce9b4 JM |
5489 | } |
5490 | } | |
5491 | ||
23a60a04 | 5492 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 JM |
5493 | } |
5494 | ||
5495 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
5496 | f_fpr = TREE_CHAIN (f_gpr); | |
5497 | f_res = TREE_CHAIN (f_fpr); | |
5498 | f_ovf = TREE_CHAIN (f_res); | |
5499 | f_sav = TREE_CHAIN (f_ovf); | |
5500 | ||
5501 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); | |
44de5aeb RK |
5502 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5503 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5504 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5505 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
cd3ce9b4 JM |
5506 | |
5507 | size = int_size_in_bytes (type); | |
5508 | rsize = (size + 3) / 4; | |
5509 | align = 1; | |
5510 | ||
08b0dc1b RH |
5511 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
5512 | && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode)) | |
cd3ce9b4 JM |
5513 | { |
5514 | /* FP args go in FP registers, if present. */ | |
cd3ce9b4 JM |
5515 | reg = fpr; |
5516 | n_reg = 1; | |
5517 | sav_ofs = 8*4; | |
5518 | sav_scale = 8; | |
5519 | if (TYPE_MODE (type) == DFmode) | |
5520 | align = 8; | |
5521 | } | |
5522 | else | |
5523 | { | |
5524 | /* Otherwise into GP registers. */ | |
cd3ce9b4 JM |
5525 | reg = gpr; |
5526 | n_reg = rsize; | |
5527 | sav_ofs = 0; | |
5528 | sav_scale = 4; | |
5529 | if (n_reg == 2) | |
5530 | align = 8; | |
5531 | } | |
5532 | ||
5533 | /* Pull the value out of the saved registers.... */ | |
5534 | ||
5535 | lab_over = NULL; | |
5536 | addr = create_tmp_var (ptr_type_node, "addr"); | |
5537 | DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); | |
5538 | ||
5539 | /* AltiVec vectors never go in registers when -mabi=altivec. */ | |
5540 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
5541 | align = 16; | |
5542 | else | |
5543 | { | |
5544 | lab_false = create_artificial_label (); | |
5545 | lab_over = create_artificial_label (); | |
5546 | ||
5547 | /* Long long and SPE vectors are aligned in the registers. | |
5548 | As are any other 2 gpr item such as complex int due to a | |
5549 | historical mistake. */ | |
5550 | u = reg; | |
5551 | if (n_reg == 2) | |
5552 | { | |
5553 | u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
95674810 | 5554 | size_int (n_reg - 1)); |
cd3ce9b4 JM |
5555 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u); |
5556 | } | |
5557 | ||
95674810 | 5558 | t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); |
cd3ce9b4 JM |
5559 | t = build2 (GE_EXPR, boolean_type_node, u, t); |
5560 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
5561 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
5562 | gimplify_and_add (t, pre_p); | |
5563 | ||
5564 | t = sav; | |
5565 | if (sav_ofs) | |
95674810 | 5566 | t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs)); |
cd3ce9b4 | 5567 | |
95674810 | 5568 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg)); |
cd3ce9b4 | 5569 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
95674810 | 5570 | u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale)); |
cd3ce9b4 JM |
5571 | t = build2 (PLUS_EXPR, ptr_type_node, t, u); |
5572 | ||
5573 | t = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5574 | gimplify_and_add (t, pre_p); | |
5575 | ||
5576 | t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
5577 | gimplify_and_add (t, pre_p); | |
5578 | ||
5579 | t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
5580 | append_to_statement_list (t, pre_p); | |
5581 | ||
5582 | if (n_reg > 2) | |
5583 | { | |
5584 | /* Ensure that we don't find any more args in regs. | |
5585 | Alignment has taken care of the n_reg == 2 case. */ | |
95674810 | 5586 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8)); |
cd3ce9b4 JM |
5587 | gimplify_and_add (t, pre_p); |
5588 | } | |
5589 | } | |
5590 | ||
5591 | /* ... otherwise out of the overflow area. */ | |
5592 | ||
5593 | /* Care for on-stack alignment if needed. */ | |
5594 | t = ovf; | |
5595 | if (align != 1) | |
5596 | { | |
95674810 | 5597 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1)); |
cd3ce9b4 JM |
5598 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1)); |
5599 | } | |
5600 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
5601 | ||
5602 | u = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5603 | gimplify_and_add (u, pre_p); | |
5604 | ||
95674810 | 5605 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); |
cd3ce9b4 JM |
5606 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5607 | gimplify_and_add (t, pre_p); | |
5608 | ||
5609 | if (lab_over) | |
5610 | { | |
5611 | t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
5612 | append_to_statement_list (t, pre_p); | |
5613 | } | |
5614 | ||
08b0dc1b | 5615 | addr = fold_convert (ptrtype, addr); |
23a60a04 | 5616 | return build_fold_indirect_ref (addr); |
cd3ce9b4 JM |
5617 | } |
5618 | ||
0ac081f6 AH |
5619 | /* Builtins. */ |
5620 | ||
6a2dd09a RS |
5621 | #define def_builtin(MASK, NAME, TYPE, CODE) \ |
5622 | do { \ | |
5623 | if ((MASK) & target_flags) \ | |
5624 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ | |
5625 | NULL, NULL_TREE); \ | |
0ac081f6 AH |
5626 | } while (0) |
5627 | ||
24408032 AH |
5628 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
5629 | ||
2212663f | 5630 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
5631 | { |
5632 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
5633 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
5634 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
5635 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
5636 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
5637 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
5638 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
5639 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
5640 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
5641 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
5642 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, | |
5643 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, | |
5644 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
5645 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
5646 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
5647 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
5648 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
5649 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
5650 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
5651 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
5652 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
5653 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
5654 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
5655 | }; | |
2212663f | 5656 | |
95385cbb AH |
5657 | /* DST operations: void foo (void *, const int, const char). */ |
5658 | ||
5659 | static const struct builtin_description bdesc_dst[] = | |
5660 | { | |
5661 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
5662 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
5663 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
5664 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
5665 | }; | |
5666 | ||
2212663f | 5667 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 5668 | |
a3170dc6 | 5669 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 5670 | { |
f18c054f DB |
5671 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
5672 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
5673 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
5674 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
5675 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
5676 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
5677 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
5678 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
5679 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
5680 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
5681 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 5682 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
5683 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
5684 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
5685 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
5686 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
5687 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
5688 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
5689 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
5690 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
5691 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
5692 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
5693 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
5694 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
5695 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
5696 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
5697 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
5698 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
5699 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
5700 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
5701 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
5702 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
5703 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
5704 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
5705 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
5706 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
5707 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
5708 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
5709 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
5710 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
5711 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
5712 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
5713 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
5714 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
5715 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
5716 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
5717 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
5718 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
5719 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
5720 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
5721 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
5722 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
5723 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
5724 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
5725 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
5726 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
5727 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
5728 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
5729 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
5730 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
5731 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
5732 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
5733 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
5734 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
5735 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 5736 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
5737 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
5738 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
5739 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
5740 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
5741 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
5742 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
5743 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
5744 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
5745 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
5746 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
5747 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
5748 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
5749 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
5750 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
5751 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
5752 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
5753 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
5754 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
5755 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
5756 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
5757 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
5758 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 5759 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
5760 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
5761 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
5762 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
5763 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
5764 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
5765 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
5766 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
5767 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
5768 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
5769 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
5770 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
5771 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
5772 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
5773 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
5774 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
5775 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
5776 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
5777 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
5778 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
5779 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
5780 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
5781 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
5782 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 5783 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 AH |
5784 | |
5785 | /* Place holder, leave as first spe builtin. */ | |
5786 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
5787 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
5788 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
5789 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
5790 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
5791 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
5792 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
5793 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
5794 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
5795 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
5796 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
5797 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
5798 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
5799 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
5800 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
5801 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
5802 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
5803 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
5804 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
5805 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
5806 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
5807 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
5808 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
5809 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
5810 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
5811 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
5812 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
5813 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
5814 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
5815 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
5816 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
5817 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
5818 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
5819 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
5820 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
5821 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
5822 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
5823 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
5824 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
5825 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
5826 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
5827 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
5828 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
5829 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
5830 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
5831 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
5832 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
5833 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
5834 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
5835 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
5836 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
5837 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
5838 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
5839 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
5840 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
5841 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
5842 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
5843 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
5844 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
5845 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
5846 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
5847 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
5848 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
5849 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
5850 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
5851 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
5852 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
5853 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
5854 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
5855 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
5856 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
5857 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
5858 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
5859 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
5860 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
5861 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
5862 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
5863 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
5864 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
5865 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
5866 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
5867 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
5868 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
5869 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
5870 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
5871 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
5872 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
5873 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
5874 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
5875 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
5876 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
5877 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
5878 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
5879 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
5880 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
5881 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
5882 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
5883 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
5884 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
5885 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
5886 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
5887 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
5888 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
5889 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
5890 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
5891 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
5892 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
5893 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
5894 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
5895 | ||
5896 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
5897 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
5898 | ||
5899 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
5900 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
5901 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
5902 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
5903 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
5904 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
5905 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
5906 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
5907 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
5908 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
5909 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
5910 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
5911 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
5912 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
5913 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
5914 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
5915 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
5916 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
5917 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
5918 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
5919 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
5920 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
5921 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
5922 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
5923 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
5924 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
5925 | ||
5926 | /* Place-holder. Leave as last binary SPE builtin. */ | |
17edbda5 | 5927 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, |
ae4b4a02 AH |
5928 | }; |
5929 | ||
5930 | /* AltiVec predicates. */ | |
5931 | ||
5932 | struct builtin_description_predicates | |
5933 | { | |
5934 | const unsigned int mask; | |
5935 | const enum insn_code icode; | |
5936 | const char *opcode; | |
5937 | const char *const name; | |
5938 | const enum rs6000_builtins code; | |
5939 | }; | |
5940 | ||
5941 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
5942 | { | |
5943 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
5944 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
5945 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
5946 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
5947 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
5948 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
5949 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
5950 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
5951 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
5952 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
5953 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
5954 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
5955 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 5956 | }; |
24408032 | 5957 | |
a3170dc6 AH |
5958 | /* SPE predicates. */ |
5959 | static struct builtin_description bdesc_spe_predicates[] = | |
5960 | { | |
5961 | /* Place-holder. Leave as first. */ | |
5962 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
5963 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
5964 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
5965 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
5966 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
5967 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
5968 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
5969 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
5970 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
5971 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
5972 | /* Place-holder. Leave as last. */ | |
5973 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
5974 | }; | |
5975 | ||
5976 | /* SPE evsel predicates. */ | |
5977 | static struct builtin_description bdesc_spe_evsel[] = | |
5978 | { | |
5979 | /* Place-holder. Leave as first. */ | |
5980 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
5981 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
5982 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
5983 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
5984 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
5985 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
5986 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
5987 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
5988 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
5989 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
5990 | /* Place-holder. Leave as last. */ | |
5991 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
5992 | }; | |
5993 | ||
b6d08ca1 | 5994 | /* ABS* operations. */ |
100c4561 AH |
5995 | |
5996 | static const struct builtin_description bdesc_abs[] = | |
5997 | { | |
5998 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
5999 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
6000 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
6001 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
6002 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
6003 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
6004 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
6005 | }; | |
6006 | ||
617e0e1d DB |
6007 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
6008 | foo (VECa). */ | |
24408032 | 6009 | |
a3170dc6 | 6010 | static struct builtin_description bdesc_1arg[] = |
2212663f | 6011 | { |
617e0e1d DB |
6012 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
6013 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
6014 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
6015 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
6016 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
6017 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
6018 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
6019 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
6020 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
6021 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
6022 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
6023 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
6024 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
6025 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
6026 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
6027 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
6028 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 AH |
6029 | |
6030 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and | |
6031 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
6032 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
6033 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
6034 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
6035 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
6036 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
6037 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
6038 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
6039 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
6040 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
6041 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
6042 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
6043 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
6044 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
6045 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
6046 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
6047 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
6048 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
6049 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
6050 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
6051 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
6052 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
6053 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
6054 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
6a599451 | 6055 | { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, |
a3170dc6 AH |
6056 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, |
6057 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
6058 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
6059 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
6060 | |
6061 | /* Place-holder. Leave as last unary SPE builtin. */ | |
6062 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, | |
2212663f DB |
6063 | }; |
6064 | ||
6065 | static rtx | |
a2369ed3 | 6066 | rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6067 | { |
6068 | rtx pat; | |
6069 | tree arg0 = TREE_VALUE (arglist); | |
6070 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6071 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6072 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6073 | ||
0559cc77 DE |
6074 | if (icode == CODE_FOR_nothing) |
6075 | /* Builtin not supported on this processor. */ | |
6076 | return 0; | |
6077 | ||
20e26713 AH |
6078 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6079 | if (arg0 == error_mark_node) | |
9a171fcd | 6080 | return const0_rtx; |
20e26713 | 6081 | |
0559cc77 DE |
6082 | if (icode == CODE_FOR_altivec_vspltisb |
6083 | || icode == CODE_FOR_altivec_vspltish | |
6084 | || icode == CODE_FOR_altivec_vspltisw | |
6085 | || icode == CODE_FOR_spe_evsplatfi | |
6086 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
6087 | { |
6088 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 AH |
6089 | if (GET_CODE (op0) != CONST_INT |
6090 | || INTVAL (op0) > 0x1f | |
6091 | || INTVAL (op0) < -0x1f) | |
6092 | { | |
6093 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 6094 | return const0_rtx; |
b44140e7 | 6095 | } |
b44140e7 AH |
6096 | } |
6097 | ||
c62f2db5 | 6098 | if (target == 0 |
2212663f DB |
6099 | || GET_MODE (target) != tmode |
6100 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6101 | target = gen_reg_rtx (tmode); | |
6102 | ||
6103 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6104 | op0 = copy_to_mode_reg (mode0, op0); | |
6105 | ||
6106 | pat = GEN_FCN (icode) (target, op0); | |
6107 | if (! pat) | |
6108 | return 0; | |
6109 | emit_insn (pat); | |
0ac081f6 | 6110 | |
2212663f DB |
6111 | return target; |
6112 | } | |
ae4b4a02 | 6113 | |
100c4561 | 6114 | static rtx |
a2369ed3 | 6115 | altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) |
100c4561 AH |
6116 | { |
6117 | rtx pat, scratch1, scratch2; | |
6118 | tree arg0 = TREE_VALUE (arglist); | |
6119 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6120 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6121 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6122 | ||
6123 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6124 | if (arg0 == error_mark_node) | |
9a171fcd | 6125 | return const0_rtx; |
100c4561 AH |
6126 | |
6127 | if (target == 0 | |
6128 | || GET_MODE (target) != tmode | |
6129 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6130 | target = gen_reg_rtx (tmode); | |
6131 | ||
6132 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6133 | op0 = copy_to_mode_reg (mode0, op0); | |
6134 | ||
6135 | scratch1 = gen_reg_rtx (mode0); | |
6136 | scratch2 = gen_reg_rtx (mode0); | |
6137 | ||
6138 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
6139 | if (! pat) | |
6140 | return 0; | |
6141 | emit_insn (pat); | |
6142 | ||
6143 | return target; | |
6144 | } | |
6145 | ||
0ac081f6 | 6146 | static rtx |
a2369ed3 | 6147 | rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
0ac081f6 AH |
6148 | { |
6149 | rtx pat; | |
6150 | tree arg0 = TREE_VALUE (arglist); | |
6151 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6152 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6153 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6154 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6155 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6156 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6157 | ||
0559cc77 DE |
6158 | if (icode == CODE_FOR_nothing) |
6159 | /* Builtin not supported on this processor. */ | |
6160 | return 0; | |
6161 | ||
20e26713 AH |
6162 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6163 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6164 | return const0_rtx; |
20e26713 | 6165 | |
0559cc77 DE |
6166 | if (icode == CODE_FOR_altivec_vcfux |
6167 | || icode == CODE_FOR_altivec_vcfsx | |
6168 | || icode == CODE_FOR_altivec_vctsxs | |
6169 | || icode == CODE_FOR_altivec_vctuxs | |
6170 | || icode == CODE_FOR_altivec_vspltb | |
6171 | || icode == CODE_FOR_altivec_vsplth | |
6172 | || icode == CODE_FOR_altivec_vspltw | |
6173 | || icode == CODE_FOR_spe_evaddiw | |
6174 | || icode == CODE_FOR_spe_evldd | |
6175 | || icode == CODE_FOR_spe_evldh | |
6176 | || icode == CODE_FOR_spe_evldw | |
6177 | || icode == CODE_FOR_spe_evlhhesplat | |
6178 | || icode == CODE_FOR_spe_evlhhossplat | |
6179 | || icode == CODE_FOR_spe_evlhhousplat | |
6180 | || icode == CODE_FOR_spe_evlwhe | |
6181 | || icode == CODE_FOR_spe_evlwhos | |
6182 | || icode == CODE_FOR_spe_evlwhou | |
6183 | || icode == CODE_FOR_spe_evlwhsplat | |
6184 | || icode == CODE_FOR_spe_evlwwsplat | |
6185 | || icode == CODE_FOR_spe_evrlwi | |
6186 | || icode == CODE_FOR_spe_evslwi | |
6187 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 6188 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 6189 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
6190 | { |
6191 | /* Only allow 5-bit unsigned literals. */ | |
8bb418a3 | 6192 | STRIP_NOPS (arg1); |
b44140e7 AH |
6193 | if (TREE_CODE (arg1) != INTEGER_CST |
6194 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6195 | { | |
6196 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 6197 | return const0_rtx; |
b44140e7 | 6198 | } |
b44140e7 AH |
6199 | } |
6200 | ||
c62f2db5 | 6201 | if (target == 0 |
0ac081f6 AH |
6202 | || GET_MODE (target) != tmode |
6203 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6204 | target = gen_reg_rtx (tmode); | |
6205 | ||
6206 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6207 | op0 = copy_to_mode_reg (mode0, op0); | |
6208 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6209 | op1 = copy_to_mode_reg (mode1, op1); | |
6210 | ||
6211 | pat = GEN_FCN (icode) (target, op0, op1); | |
6212 | if (! pat) | |
6213 | return 0; | |
6214 | emit_insn (pat); | |
6215 | ||
6216 | return target; | |
6217 | } | |
6525c0e7 | 6218 | |
ae4b4a02 | 6219 | static rtx |
a2369ed3 DJ |
6220 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
6221 | tree arglist, rtx target) | |
ae4b4a02 AH |
6222 | { |
6223 | rtx pat, scratch; | |
6224 | tree cr6_form = TREE_VALUE (arglist); | |
6225 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6226 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6227 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6228 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6229 | enum machine_mode tmode = SImode; | |
6230 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6231 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6232 | int cr6_form_int; | |
6233 | ||
6234 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
6235 | { | |
6236 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 6237 | return const0_rtx; |
ae4b4a02 AH |
6238 | } |
6239 | else | |
6240 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
6241 | ||
6242 | if (mode0 != mode1) | |
6243 | abort (); | |
6244 | ||
6245 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6246 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6247 | return const0_rtx; |
ae4b4a02 AH |
6248 | |
6249 | if (target == 0 | |
6250 | || GET_MODE (target) != tmode | |
6251 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6252 | target = gen_reg_rtx (tmode); | |
6253 | ||
6254 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6255 | op0 = copy_to_mode_reg (mode0, op0); | |
6256 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6257 | op1 = copy_to_mode_reg (mode1, op1); | |
6258 | ||
6259 | scratch = gen_reg_rtx (mode0); | |
6260 | ||
6261 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 6262 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
6263 | if (! pat) |
6264 | return 0; | |
6265 | emit_insn (pat); | |
6266 | ||
6267 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
6268 | different operations, but the bits in CR6 will be different | |
6269 | depending on what information we want. So we have to play tricks | |
6270 | with CR6 to get the right bits out. | |
6271 | ||
6272 | If you think this is disgusting, look at the specs for the | |
6273 | AltiVec predicates. */ | |
6274 | ||
6275 | switch (cr6_form_int) | |
6276 | { | |
6277 | case 0: | |
6278 | emit_insn (gen_cr6_test_for_zero (target)); | |
6279 | break; | |
6280 | case 1: | |
6281 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
6282 | break; | |
6283 | case 2: | |
6284 | emit_insn (gen_cr6_test_for_lt (target)); | |
6285 | break; | |
6286 | case 3: | |
6287 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
6288 | break; | |
6289 | default: | |
6290 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
6291 | break; | |
6292 | } | |
6293 | ||
6294 | return target; | |
6295 | } | |
6296 | ||
b4a62fa0 | 6297 | static rtx |
38f391a5 | 6298 | altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) |
b4a62fa0 SB |
6299 | { |
6300 | rtx pat, addr; | |
6301 | tree arg0 = TREE_VALUE (arglist); | |
6302 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6303 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6304 | enum machine_mode mode0 = Pmode; | |
6305 | enum machine_mode mode1 = Pmode; | |
6306 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6307 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6308 | ||
6309 | if (icode == CODE_FOR_nothing) | |
6310 | /* Builtin not supported on this processor. */ | |
6311 | return 0; | |
6312 | ||
6313 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6314 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6315 | return const0_rtx; | |
6316 | ||
6317 | if (target == 0 | |
6318 | || GET_MODE (target) != tmode | |
6319 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6320 | target = gen_reg_rtx (tmode); | |
6321 | ||
6322 | op1 = copy_to_mode_reg (mode1, op1); | |
6323 | ||
6324 | if (op0 == const0_rtx) | |
6325 | { | |
6326 | addr = gen_rtx_MEM (tmode, op1); | |
6327 | } | |
6328 | else | |
6329 | { | |
6330 | op0 = copy_to_mode_reg (mode0, op0); | |
6331 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
6332 | } | |
6333 | ||
6334 | pat = GEN_FCN (icode) (target, addr); | |
6335 | ||
6336 | if (! pat) | |
6337 | return 0; | |
6338 | emit_insn (pat); | |
6339 | ||
6340 | return target; | |
6341 | } | |
6342 | ||
61bea3b0 AH |
6343 | static rtx |
6344 | spe_expand_stv_builtin (enum insn_code icode, tree arglist) | |
6345 | { | |
6346 | tree arg0 = TREE_VALUE (arglist); | |
6347 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6348 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6349 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6350 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6351 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6352 | rtx pat; | |
6353 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
6354 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
6355 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
6356 | ||
6357 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6358 | if (arg0 == error_mark_node | |
6359 | || arg1 == error_mark_node | |
6360 | || arg2 == error_mark_node) | |
6361 | return const0_rtx; | |
6362 | ||
6363 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
6364 | op0 = copy_to_mode_reg (mode2, op0); | |
6365 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
6366 | op1 = copy_to_mode_reg (mode0, op1); | |
6367 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6368 | op2 = copy_to_mode_reg (mode1, op2); | |
6369 | ||
6370 | pat = GEN_FCN (icode) (op1, op2, op0); | |
6371 | if (pat) | |
6372 | emit_insn (pat); | |
6373 | return NULL_RTX; | |
6374 | } | |
6375 | ||
6525c0e7 | 6376 | static rtx |
a2369ed3 | 6377 | altivec_expand_stv_builtin (enum insn_code icode, tree arglist) |
6525c0e7 AH |
6378 | { |
6379 | tree arg0 = TREE_VALUE (arglist); | |
6380 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6381 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6382 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6383 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6384 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
b4a62fa0 SB |
6385 | rtx pat, addr; |
6386 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6387 | enum machine_mode mode1 = Pmode; | |
6388 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
6389 | |
6390 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6391 | if (arg0 == error_mark_node | |
6392 | || arg1 == error_mark_node | |
6393 | || arg2 == error_mark_node) | |
9a171fcd | 6394 | return const0_rtx; |
6525c0e7 | 6395 | |
b4a62fa0 SB |
6396 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
6397 | op0 = copy_to_mode_reg (tmode, op0); | |
6398 | ||
6399 | op2 = copy_to_mode_reg (mode2, op2); | |
6400 | ||
6401 | if (op1 == const0_rtx) | |
6402 | { | |
6403 | addr = gen_rtx_MEM (tmode, op2); | |
6404 | } | |
6405 | else | |
6406 | { | |
6407 | op1 = copy_to_mode_reg (mode1, op1); | |
6408 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
6409 | } | |
6525c0e7 | 6410 | |
b4a62fa0 | 6411 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
6412 | if (pat) |
6413 | emit_insn (pat); | |
6414 | return NULL_RTX; | |
6415 | } | |
6416 | ||
2212663f | 6417 | static rtx |
a2369ed3 | 6418 | rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6419 | { |
6420 | rtx pat; | |
6421 | tree arg0 = TREE_VALUE (arglist); | |
6422 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6423 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6424 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6425 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6426 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6427 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6428 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6429 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6430 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 6431 | |
774b5662 DE |
6432 | if (icode == CODE_FOR_nothing) |
6433 | /* Builtin not supported on this processor. */ | |
6434 | return 0; | |
6435 | ||
20e26713 AH |
6436 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6437 | if (arg0 == error_mark_node | |
6438 | || arg1 == error_mark_node | |
6439 | || arg2 == error_mark_node) | |
9a171fcd | 6440 | return const0_rtx; |
20e26713 | 6441 | |
774b5662 DE |
6442 | if (icode == CODE_FOR_altivec_vsldoi_4sf |
6443 | || icode == CODE_FOR_altivec_vsldoi_4si | |
6444 | || icode == CODE_FOR_altivec_vsldoi_8hi | |
6445 | || icode == CODE_FOR_altivec_vsldoi_16qi) | |
b44140e7 AH |
6446 | { |
6447 | /* Only allow 4-bit unsigned literals. */ | |
8bb418a3 | 6448 | STRIP_NOPS (arg2); |
b44140e7 AH |
6449 | if (TREE_CODE (arg2) != INTEGER_CST |
6450 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
6451 | { | |
6452 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 6453 | return const0_rtx; |
b44140e7 | 6454 | } |
b44140e7 AH |
6455 | } |
6456 | ||
c62f2db5 | 6457 | if (target == 0 |
2212663f DB |
6458 | || GET_MODE (target) != tmode |
6459 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6460 | target = gen_reg_rtx (tmode); | |
6461 | ||
6462 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6463 | op0 = copy_to_mode_reg (mode0, op0); | |
6464 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6465 | op1 = copy_to_mode_reg (mode1, op1); | |
6466 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
6467 | op2 = copy_to_mode_reg (mode2, op2); | |
6468 | ||
6469 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
6470 | if (! pat) | |
6471 | return 0; | |
6472 | emit_insn (pat); | |
6473 | ||
6474 | return target; | |
6475 | } | |
92898235 | 6476 | |
3a9b8c7e | 6477 | /* Expand the lvx builtins. */ |
0ac081f6 | 6478 | static rtx |
a2369ed3 | 6479 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 6480 | { |
0ac081f6 AH |
6481 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6482 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 6483 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
6484 | tree arg0; |
6485 | enum machine_mode tmode, mode0; | |
7c3abc73 | 6486 | rtx pat, op0; |
3a9b8c7e | 6487 | enum insn_code icode; |
92898235 | 6488 | |
0ac081f6 AH |
6489 | switch (fcode) |
6490 | { | |
f18c054f DB |
6491 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
6492 | icode = CODE_FOR_altivec_lvx_16qi; | |
3a9b8c7e | 6493 | break; |
f18c054f DB |
6494 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
6495 | icode = CODE_FOR_altivec_lvx_8hi; | |
3a9b8c7e AH |
6496 | break; |
6497 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
6498 | icode = CODE_FOR_altivec_lvx_4si; | |
6499 | break; | |
6500 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
6501 | icode = CODE_FOR_altivec_lvx_4sf; | |
6502 | break; | |
6503 | default: | |
6504 | *expandedp = false; | |
6505 | return NULL_RTX; | |
6506 | } | |
0ac081f6 | 6507 | |
3a9b8c7e | 6508 | *expandedp = true; |
f18c054f | 6509 | |
3a9b8c7e AH |
6510 | arg0 = TREE_VALUE (arglist); |
6511 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6512 | tmode = insn_data[icode].operand[0].mode; | |
6513 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 6514 | |
3a9b8c7e AH |
6515 | if (target == 0 |
6516 | || GET_MODE (target) != tmode | |
6517 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6518 | target = gen_reg_rtx (tmode); | |
24408032 | 6519 | |
3a9b8c7e AH |
6520 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
6521 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 6522 | |
3a9b8c7e AH |
6523 | pat = GEN_FCN (icode) (target, op0); |
6524 | if (! pat) | |
6525 | return 0; | |
6526 | emit_insn (pat); | |
6527 | return target; | |
6528 | } | |
f18c054f | 6529 | |
3a9b8c7e AH |
6530 | /* Expand the stvx builtins. */ |
6531 | static rtx | |
a2369ed3 DJ |
6532 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
6533 | bool *expandedp) | |
3a9b8c7e AH |
6534 | { |
6535 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6536 | tree arglist = TREE_OPERAND (exp, 1); | |
6537 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6538 | tree arg0, arg1; | |
6539 | enum machine_mode mode0, mode1; | |
7c3abc73 | 6540 | rtx pat, op0, op1; |
3a9b8c7e | 6541 | enum insn_code icode; |
f18c054f | 6542 | |
3a9b8c7e AH |
6543 | switch (fcode) |
6544 | { | |
6545 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
6546 | icode = CODE_FOR_altivec_stvx_16qi; | |
6547 | break; | |
6548 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
6549 | icode = CODE_FOR_altivec_stvx_8hi; | |
6550 | break; | |
6551 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
6552 | icode = CODE_FOR_altivec_stvx_4si; | |
6553 | break; | |
6554 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
6555 | icode = CODE_FOR_altivec_stvx_4sf; | |
6556 | break; | |
6557 | default: | |
6558 | *expandedp = false; | |
6559 | return NULL_RTX; | |
6560 | } | |
24408032 | 6561 | |
3a9b8c7e AH |
6562 | arg0 = TREE_VALUE (arglist); |
6563 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6564 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6565 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6566 | mode0 = insn_data[icode].operand[0].mode; | |
6567 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 6568 | |
3a9b8c7e AH |
6569 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6570 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
6571 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
6572 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 6573 | |
3a9b8c7e AH |
6574 | pat = GEN_FCN (icode) (op0, op1); |
6575 | if (pat) | |
6576 | emit_insn (pat); | |
f18c054f | 6577 | |
3a9b8c7e AH |
6578 | *expandedp = true; |
6579 | return NULL_RTX; | |
6580 | } | |
f18c054f | 6581 | |
3a9b8c7e AH |
6582 | /* Expand the dst builtins. */ |
6583 | static rtx | |
a2369ed3 DJ |
6584 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
6585 | bool *expandedp) | |
3a9b8c7e AH |
6586 | { |
6587 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6588 | tree arglist = TREE_OPERAND (exp, 1); | |
6589 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6590 | tree arg0, arg1, arg2; | |
6591 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 6592 | rtx pat, op0, op1, op2; |
3a9b8c7e | 6593 | struct builtin_description *d; |
a3170dc6 | 6594 | size_t i; |
f18c054f | 6595 | |
3a9b8c7e | 6596 | *expandedp = false; |
f18c054f | 6597 | |
3a9b8c7e AH |
6598 | /* Handle DST variants. */ |
6599 | d = (struct builtin_description *) bdesc_dst; | |
6600 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
6601 | if (d->code == fcode) | |
6602 | { | |
6603 | arg0 = TREE_VALUE (arglist); | |
6604 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6605 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6606 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6607 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6608 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6609 | mode0 = insn_data[d->icode].operand[0].mode; | |
6610 | mode1 = insn_data[d->icode].operand[1].mode; | |
6611 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 6612 | |
3a9b8c7e AH |
6613 | /* Invalid arguments, bail out before generating bad rtl. */ |
6614 | if (arg0 == error_mark_node | |
6615 | || arg1 == error_mark_node | |
6616 | || arg2 == error_mark_node) | |
6617 | return const0_rtx; | |
f18c054f | 6618 | |
86e7df90 | 6619 | *expandedp = true; |
8bb418a3 | 6620 | STRIP_NOPS (arg2); |
3a9b8c7e AH |
6621 | if (TREE_CODE (arg2) != INTEGER_CST |
6622 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
6623 | { | |
6624 | error ("argument to `%s' must be a 2-bit unsigned literal", d->name); | |
6625 | return const0_rtx; | |
6626 | } | |
f18c054f | 6627 | |
3a9b8c7e | 6628 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
b4a62fa0 | 6629 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); |
3a9b8c7e AH |
6630 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
6631 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 6632 | |
3a9b8c7e AH |
6633 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
6634 | if (pat != 0) | |
6635 | emit_insn (pat); | |
f18c054f | 6636 | |
3a9b8c7e AH |
6637 | return NULL_RTX; |
6638 | } | |
f18c054f | 6639 | |
3a9b8c7e AH |
6640 | return NULL_RTX; |
6641 | } | |
24408032 | 6642 | |
3a9b8c7e AH |
6643 | /* Expand the builtin in EXP and store the result in TARGET. Store |
6644 | true in *EXPANDEDP if we found a builtin to expand. */ | |
6645 | static rtx | |
a2369ed3 | 6646 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e AH |
6647 | { |
6648 | struct builtin_description *d; | |
6649 | struct builtin_description_predicates *dp; | |
6650 | size_t i; | |
6651 | enum insn_code icode; | |
6652 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6653 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
6654 | tree arg0; |
6655 | rtx op0, pat; | |
6656 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 6657 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 6658 | |
3a9b8c7e AH |
6659 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
6660 | if (*expandedp) | |
6661 | return target; | |
0ac081f6 | 6662 | |
3a9b8c7e AH |
6663 | target = altivec_expand_st_builtin (exp, target, expandedp); |
6664 | if (*expandedp) | |
6665 | return target; | |
6666 | ||
6667 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
6668 | if (*expandedp) | |
6669 | return target; | |
6670 | ||
6671 | *expandedp = true; | |
95385cbb | 6672 | |
3a9b8c7e AH |
6673 | switch (fcode) |
6674 | { | |
6525c0e7 AH |
6675 | case ALTIVEC_BUILTIN_STVX: |
6676 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
6677 | case ALTIVEC_BUILTIN_STVEBX: | |
6678 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
6679 | case ALTIVEC_BUILTIN_STVEHX: | |
6680 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
6681 | case ALTIVEC_BUILTIN_STVEWX: | |
6682 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
6683 | case ALTIVEC_BUILTIN_STVXL: | |
6684 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 6685 | |
95385cbb AH |
6686 | case ALTIVEC_BUILTIN_MFVSCR: |
6687 | icode = CODE_FOR_altivec_mfvscr; | |
6688 | tmode = insn_data[icode].operand[0].mode; | |
6689 | ||
6690 | if (target == 0 | |
6691 | || GET_MODE (target) != tmode | |
6692 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6693 | target = gen_reg_rtx (tmode); | |
6694 | ||
6695 | pat = GEN_FCN (icode) (target); | |
0ac081f6 AH |
6696 | if (! pat) |
6697 | return 0; | |
6698 | emit_insn (pat); | |
95385cbb AH |
6699 | return target; |
6700 | ||
6701 | case ALTIVEC_BUILTIN_MTVSCR: | |
6702 | icode = CODE_FOR_altivec_mtvscr; | |
6703 | arg0 = TREE_VALUE (arglist); | |
6704 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6705 | mode0 = insn_data[icode].operand[0].mode; | |
6706 | ||
6707 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6708 | if (arg0 == error_mark_node) | |
9a171fcd | 6709 | return const0_rtx; |
95385cbb AH |
6710 | |
6711 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6712 | op0 = copy_to_mode_reg (mode0, op0); | |
6713 | ||
6714 | pat = GEN_FCN (icode) (op0); | |
6715 | if (pat) | |
6716 | emit_insn (pat); | |
6717 | return NULL_RTX; | |
3a9b8c7e | 6718 | |
95385cbb AH |
6719 | case ALTIVEC_BUILTIN_DSSALL: |
6720 | emit_insn (gen_altivec_dssall ()); | |
6721 | return NULL_RTX; | |
6722 | ||
6723 | case ALTIVEC_BUILTIN_DSS: | |
6724 | icode = CODE_FOR_altivec_dss; | |
6725 | arg0 = TREE_VALUE (arglist); | |
8bb418a3 | 6726 | STRIP_NOPS (arg0); |
95385cbb AH |
6727 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
6728 | mode0 = insn_data[icode].operand[0].mode; | |
6729 | ||
6730 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6731 | if (arg0 == error_mark_node) | |
9a171fcd | 6732 | return const0_rtx; |
95385cbb | 6733 | |
b44140e7 AH |
6734 | if (TREE_CODE (arg0) != INTEGER_CST |
6735 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
6736 | { | |
6737 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 6738 | return const0_rtx; |
b44140e7 AH |
6739 | } |
6740 | ||
95385cbb AH |
6741 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6742 | op0 = copy_to_mode_reg (mode0, op0); | |
6743 | ||
6744 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 | 6745 | return NULL_RTX; |
8bb418a3 ZL |
6746 | |
6747 | case ALTIVEC_BUILTIN_COMPILETIME_ERROR: | |
6748 | arg0 = TREE_VALUE (arglist); | |
6749 | while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR) | |
6750 | arg0 = TREE_OPERAND (arg0, 0); | |
6751 | error ("invalid parameter combination for `%s' AltiVec intrinsic", | |
6752 | TREE_STRING_POINTER (arg0)); | |
6753 | ||
6754 | return const0_rtx; | |
0ac081f6 | 6755 | } |
24408032 | 6756 | |
100c4561 AH |
6757 | /* Expand abs* operations. */ |
6758 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 6759 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
6760 | if (d->code == fcode) |
6761 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
6762 | ||
ae4b4a02 AH |
6763 | /* Expand the AltiVec predicates. */ |
6764 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 6765 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 AH |
6766 | if (dp->code == fcode) |
6767 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target); | |
6768 | ||
6525c0e7 AH |
6769 | /* LV* are funky. We initialized them differently. */ |
6770 | switch (fcode) | |
6771 | { | |
6772 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 6773 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
6525c0e7 AH |
6774 | arglist, target); |
6775 | case ALTIVEC_BUILTIN_LVSR: | |
b4a62fa0 | 6776 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
92898235 | 6777 | arglist, target); |
6525c0e7 | 6778 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 6779 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
92898235 | 6780 | arglist, target); |
6525c0e7 | 6781 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 6782 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
92898235 | 6783 | arglist, target); |
6525c0e7 | 6784 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 6785 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
92898235 | 6786 | arglist, target); |
6525c0e7 | 6787 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 6788 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
92898235 | 6789 | arglist, target); |
6525c0e7 | 6790 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 6791 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
92898235 | 6792 | arglist, target); |
6525c0e7 AH |
6793 | default: |
6794 | break; | |
6795 | /* Fall through. */ | |
6796 | } | |
95385cbb | 6797 | |
92898235 | 6798 | *expandedp = false; |
0ac081f6 AH |
6799 | return NULL_RTX; |
6800 | } | |
6801 | ||
a3170dc6 AH |
6802 | /* Binops that need to be initialized manually, but can be expanded |
6803 | automagically by rs6000_expand_binop_builtin. */ | |
6804 | static struct builtin_description bdesc_2arg_spe[] = | |
6805 | { | |
6806 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
6807 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
6808 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
6809 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
6810 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
6811 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
6812 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
6813 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
6814 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
6815 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
6816 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
6817 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
6818 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
6819 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
6820 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
6821 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
6822 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
6823 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
6824 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
6825 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
6826 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
6827 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
6828 | }; | |
6829 | ||
6830 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
6831 | true in *EXPANDEDP if we found a builtin to expand. | |
6832 | ||
6833 | This expands the SPE builtins that are not simple unary and binary | |
6834 | operations. */ | |
6835 | static rtx | |
a2369ed3 | 6836 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 AH |
6837 | { |
6838 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6839 | tree arglist = TREE_OPERAND (exp, 1); | |
6840 | tree arg1, arg0; | |
6841 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6842 | enum insn_code icode; | |
6843 | enum machine_mode tmode, mode0; | |
6844 | rtx pat, op0; | |
6845 | struct builtin_description *d; | |
6846 | size_t i; | |
6847 | ||
6848 | *expandedp = true; | |
6849 | ||
6850 | /* Syntax check for a 5-bit unsigned immediate. */ | |
6851 | switch (fcode) | |
6852 | { | |
6853 | case SPE_BUILTIN_EVSTDD: | |
6854 | case SPE_BUILTIN_EVSTDH: | |
6855 | case SPE_BUILTIN_EVSTDW: | |
6856 | case SPE_BUILTIN_EVSTWHE: | |
6857 | case SPE_BUILTIN_EVSTWHO: | |
6858 | case SPE_BUILTIN_EVSTWWE: | |
6859 | case SPE_BUILTIN_EVSTWWO: | |
6860 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6861 | if (TREE_CODE (arg1) != INTEGER_CST | |
6862 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6863 | { | |
6864 | error ("argument 2 must be a 5-bit unsigned literal"); | |
6865 | return const0_rtx; | |
6866 | } | |
6867 | break; | |
6868 | default: | |
6869 | break; | |
6870 | } | |
6871 | ||
00332c9f AH |
6872 | /* The evsplat*i instructions are not quite generic. */ |
6873 | switch (fcode) | |
6874 | { | |
6875 | case SPE_BUILTIN_EVSPLATFI: | |
6876 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
6877 | arglist, target); | |
6878 | case SPE_BUILTIN_EVSPLATI: | |
6879 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
6880 | arglist, target); | |
6881 | default: | |
6882 | break; | |
6883 | } | |
6884 | ||
a3170dc6 AH |
6885 | d = (struct builtin_description *) bdesc_2arg_spe; |
6886 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
6887 | if (d->code == fcode) | |
6888 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
6889 | ||
6890 | d = (struct builtin_description *) bdesc_spe_predicates; | |
6891 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
6892 | if (d->code == fcode) | |
6893 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
6894 | ||
6895 | d = (struct builtin_description *) bdesc_spe_evsel; | |
6896 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
6897 | if (d->code == fcode) | |
6898 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
6899 | ||
6900 | switch (fcode) | |
6901 | { | |
6902 | case SPE_BUILTIN_EVSTDDX: | |
61bea3b0 | 6903 | return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); |
a3170dc6 | 6904 | case SPE_BUILTIN_EVSTDHX: |
61bea3b0 | 6905 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); |
a3170dc6 | 6906 | case SPE_BUILTIN_EVSTDWX: |
61bea3b0 | 6907 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); |
a3170dc6 | 6908 | case SPE_BUILTIN_EVSTWHEX: |
61bea3b0 | 6909 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); |
a3170dc6 | 6910 | case SPE_BUILTIN_EVSTWHOX: |
61bea3b0 | 6911 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); |
a3170dc6 | 6912 | case SPE_BUILTIN_EVSTWWEX: |
61bea3b0 | 6913 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); |
a3170dc6 | 6914 | case SPE_BUILTIN_EVSTWWOX: |
61bea3b0 | 6915 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); |
a3170dc6 | 6916 | case SPE_BUILTIN_EVSTDD: |
61bea3b0 | 6917 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); |
a3170dc6 | 6918 | case SPE_BUILTIN_EVSTDH: |
61bea3b0 | 6919 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); |
a3170dc6 | 6920 | case SPE_BUILTIN_EVSTDW: |
61bea3b0 | 6921 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); |
a3170dc6 | 6922 | case SPE_BUILTIN_EVSTWHE: |
61bea3b0 | 6923 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); |
a3170dc6 | 6924 | case SPE_BUILTIN_EVSTWHO: |
61bea3b0 | 6925 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); |
a3170dc6 | 6926 | case SPE_BUILTIN_EVSTWWE: |
61bea3b0 | 6927 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); |
a3170dc6 | 6928 | case SPE_BUILTIN_EVSTWWO: |
61bea3b0 | 6929 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); |
a3170dc6 AH |
6930 | case SPE_BUILTIN_MFSPEFSCR: |
6931 | icode = CODE_FOR_spe_mfspefscr; | |
6932 | tmode = insn_data[icode].operand[0].mode; | |
6933 | ||
6934 | if (target == 0 | |
6935 | || GET_MODE (target) != tmode | |
6936 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6937 | target = gen_reg_rtx (tmode); | |
6938 | ||
6939 | pat = GEN_FCN (icode) (target); | |
6940 | if (! pat) | |
6941 | return 0; | |
6942 | emit_insn (pat); | |
6943 | return target; | |
6944 | case SPE_BUILTIN_MTSPEFSCR: | |
6945 | icode = CODE_FOR_spe_mtspefscr; | |
6946 | arg0 = TREE_VALUE (arglist); | |
6947 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6948 | mode0 = insn_data[icode].operand[0].mode; | |
6949 | ||
6950 | if (arg0 == error_mark_node) | |
6951 | return const0_rtx; | |
6952 | ||
6953 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6954 | op0 = copy_to_mode_reg (mode0, op0); | |
6955 | ||
6956 | pat = GEN_FCN (icode) (op0); | |
6957 | if (pat) | |
6958 | emit_insn (pat); | |
6959 | return NULL_RTX; | |
6960 | default: | |
6961 | break; | |
6962 | } | |
6963 | ||
6964 | *expandedp = false; | |
6965 | return NULL_RTX; | |
6966 | } | |
6967 | ||
6968 | static rtx | |
a2369ed3 | 6969 | spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
6970 | { |
6971 | rtx pat, scratch, tmp; | |
6972 | tree form = TREE_VALUE (arglist); | |
6973 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6974 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6975 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6976 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6977 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6978 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6979 | int form_int; | |
6980 | enum rtx_code code; | |
6981 | ||
6982 | if (TREE_CODE (form) != INTEGER_CST) | |
6983 | { | |
6984 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
6985 | return const0_rtx; | |
6986 | } | |
6987 | else | |
6988 | form_int = TREE_INT_CST_LOW (form); | |
6989 | ||
6990 | if (mode0 != mode1) | |
6991 | abort (); | |
6992 | ||
6993 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6994 | return const0_rtx; | |
6995 | ||
6996 | if (target == 0 | |
6997 | || GET_MODE (target) != SImode | |
6998 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
6999 | target = gen_reg_rtx (SImode); | |
7000 | ||
7001 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7002 | op0 = copy_to_mode_reg (mode0, op0); | |
7003 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
7004 | op1 = copy_to_mode_reg (mode1, op1); | |
7005 | ||
7006 | scratch = gen_reg_rtx (CCmode); | |
7007 | ||
7008 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7009 | if (! pat) | |
7010 | return const0_rtx; | |
7011 | emit_insn (pat); | |
7012 | ||
7013 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
7014 | _lower_. We use one compare, but look in different bits of the | |
7015 | CR for each variant. | |
7016 | ||
7017 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
7018 | bits are set as follows: | |
7019 | ||
7020 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7021 | U | L | (U | L) | (U & L) | |
7022 | ||
7023 | So, for an "all" relationship, BIT 3 would be set. | |
7024 | For an "any" relationship, BIT 2 would be set. Etc. | |
7025 | ||
7026 | Following traditional nomenclature, these bits map to: | |
7027 | ||
7028 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7029 | LT | GT | EQ | OV | |
7030 | ||
7031 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
7032 | */ | |
7033 | ||
7034 | switch (form_int) | |
7035 | { | |
7036 | /* All variant. OV bit. */ | |
7037 | case 0: | |
7038 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
7039 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
7040 | that's ugly and will trigger a validate_condition_mode abort. | |
7041 | So let's just use another pattern. */ | |
7042 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
7043 | return target; | |
7044 | /* Any variant. EQ bit. */ | |
7045 | case 1: | |
7046 | code = EQ; | |
7047 | break; | |
7048 | /* Upper variant. LT bit. */ | |
7049 | case 2: | |
7050 | code = LT; | |
7051 | break; | |
7052 | /* Lower variant. GT bit. */ | |
7053 | case 3: | |
7054 | code = GT; | |
7055 | break; | |
7056 | default: | |
7057 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
7058 | return const0_rtx; | |
7059 | } | |
7060 | ||
7061 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
7062 | emit_move_insn (target, tmp); | |
7063 | ||
7064 | return target; | |
7065 | } | |
7066 | ||
7067 | /* The evsel builtins look like this: | |
7068 | ||
7069 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
7070 | ||
7071 | and work like this: | |
7072 | ||
7073 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
7074 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
7075 | */ | |
7076 | ||
7077 | static rtx | |
a2369ed3 | 7078 | spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
7079 | { |
7080 | rtx pat, scratch; | |
7081 | tree arg0 = TREE_VALUE (arglist); | |
7082 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7083 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7084 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
7085 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7086 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7087 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
7088 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
7089 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7090 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7091 | ||
7092 | if (mode0 != mode1) | |
7093 | abort (); | |
7094 | ||
7095 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
7096 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
7097 | return const0_rtx; | |
7098 | ||
7099 | if (target == 0 | |
7100 | || GET_MODE (target) != mode0 | |
7101 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
7102 | target = gen_reg_rtx (mode0); | |
7103 | ||
7104 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7105 | op0 = copy_to_mode_reg (mode0, op0); | |
7106 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
7107 | op1 = copy_to_mode_reg (mode0, op1); | |
7108 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
7109 | op2 = copy_to_mode_reg (mode0, op2); | |
7110 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
7111 | op3 = copy_to_mode_reg (mode0, op3); | |
7112 | ||
7113 | /* Generate the compare. */ | |
7114 | scratch = gen_reg_rtx (CCmode); | |
7115 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7116 | if (! pat) | |
7117 | return const0_rtx; | |
7118 | emit_insn (pat); | |
7119 | ||
7120 | if (mode0 == V2SImode) | |
7121 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
7122 | else | |
7123 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
7124 | ||
7125 | return target; | |
7126 | } | |
7127 | ||
0ac081f6 AH |
7128 | /* Expand an expression EXP that calls a built-in function, |
7129 | with result going to TARGET if that's convenient | |
7130 | (and in mode MODE if that's convenient). | |
7131 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
7132 | IGNORE is nonzero if the value is to be ignored. */ | |
7133 | ||
7134 | static rtx | |
a2369ed3 DJ |
7135 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
7136 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
7137 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 7138 | { |
92898235 AH |
7139 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
7140 | tree arglist = TREE_OPERAND (exp, 1); | |
7141 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7142 | struct builtin_description *d; | |
7143 | size_t i; | |
7144 | rtx ret; | |
7145 | bool success; | |
7146 | ||
0ac081f6 | 7147 | if (TARGET_ALTIVEC) |
92898235 AH |
7148 | { |
7149 | ret = altivec_expand_builtin (exp, target, &success); | |
7150 | ||
a3170dc6 AH |
7151 | if (success) |
7152 | return ret; | |
7153 | } | |
7154 | if (TARGET_SPE) | |
7155 | { | |
7156 | ret = spe_expand_builtin (exp, target, &success); | |
7157 | ||
92898235 AH |
7158 | if (success) |
7159 | return ret; | |
7160 | } | |
7161 | ||
0559cc77 DE |
7162 | if (TARGET_ALTIVEC || TARGET_SPE) |
7163 | { | |
7164 | /* Handle simple unary operations. */ | |
7165 | d = (struct builtin_description *) bdesc_1arg; | |
7166 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
7167 | if (d->code == fcode) | |
7168 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
7169 | ||
7170 | /* Handle simple binary operations. */ | |
7171 | d = (struct builtin_description *) bdesc_2arg; | |
7172 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
7173 | if (d->code == fcode) | |
7174 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
7175 | ||
7176 | /* Handle simple ternary operations. */ | |
7177 | d = (struct builtin_description *) bdesc_3arg; | |
7178 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
7179 | if (d->code == fcode) | |
7180 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
7181 | } | |
0ac081f6 AH |
7182 | |
7183 | abort (); | |
92898235 | 7184 | return NULL_RTX; |
0ac081f6 AH |
7185 | } |
7186 | ||
7c62e993 PB |
7187 | static tree |
7188 | build_opaque_vector_type (tree node, int nunits) | |
7189 | { | |
7190 | node = copy_node (node); | |
7191 | TYPE_MAIN_VARIANT (node) = node; | |
7192 | return build_vector_type (node, nunits); | |
7193 | } | |
7194 | ||
0ac081f6 | 7195 | static void |
863d938c | 7196 | rs6000_init_builtins (void) |
0ac081f6 | 7197 | { |
4a5eab38 PB |
7198 | V2SI_type_node = build_vector_type (intSI_type_node, 2); |
7199 | V2SF_type_node = build_vector_type (float_type_node, 2); | |
7200 | V4HI_type_node = build_vector_type (intHI_type_node, 4); | |
7201 | V4SI_type_node = build_vector_type (intSI_type_node, 4); | |
7202 | V4SF_type_node = build_vector_type (float_type_node, 4); | |
7e463bda | 7203 | V8HI_type_node = build_vector_type (intHI_type_node, 8); |
4a5eab38 PB |
7204 | V16QI_type_node = build_vector_type (intQI_type_node, 16); |
7205 | ||
7206 | unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); | |
7207 | unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); | |
7208 | unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); | |
7209 | ||
7c62e993 PB |
7210 | opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); |
7211 | opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); | |
6035d635 | 7212 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
3fdaa45a | 7213 | |
8bb418a3 ZL |
7214 | /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' |
7215 | types, especially in C++ land. Similarly, 'vector pixel' is distinct from | |
7216 | 'vector unsigned short'. */ | |
7217 | ||
7218 | bool_char_type_node = copy_node (unsigned_intQI_type_node); | |
7219 | TYPE_MAIN_VARIANT (bool_char_type_node) = bool_char_type_node; | |
7220 | bool_short_type_node = copy_node (unsigned_intHI_type_node); | |
7221 | TYPE_MAIN_VARIANT (bool_short_type_node) = bool_short_type_node; | |
7222 | bool_int_type_node = copy_node (unsigned_intSI_type_node); | |
7223 | TYPE_MAIN_VARIANT (bool_int_type_node) = bool_int_type_node; | |
7224 | pixel_type_node = copy_node (unsigned_intHI_type_node); | |
7225 | TYPE_MAIN_VARIANT (pixel_type_node) = pixel_type_node; | |
7226 | ||
7227 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7228 | get_identifier ("__bool char"), | |
7229 | bool_char_type_node)); | |
7230 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7231 | get_identifier ("__bool short"), | |
7232 | bool_short_type_node)); | |
7233 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7234 | get_identifier ("__bool int"), | |
7235 | bool_int_type_node)); | |
7236 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7237 | get_identifier ("__pixel"), | |
7238 | pixel_type_node)); | |
7239 | ||
4a5eab38 PB |
7240 | bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); |
7241 | bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); | |
7242 | bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); | |
7243 | pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); | |
8bb418a3 ZL |
7244 | |
7245 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7246 | get_identifier ("__vector unsigned char"), | |
7247 | unsigned_V16QI_type_node)); | |
7248 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7249 | get_identifier ("__vector signed char"), | |
7250 | V16QI_type_node)); | |
7251 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7252 | get_identifier ("__vector __bool char"), | |
7253 | bool_V16QI_type_node)); | |
7254 | ||
7255 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7256 | get_identifier ("__vector unsigned short"), | |
7257 | unsigned_V8HI_type_node)); | |
7258 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7259 | get_identifier ("__vector signed short"), | |
7260 | V8HI_type_node)); | |
7261 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7262 | get_identifier ("__vector __bool short"), | |
7263 | bool_V8HI_type_node)); | |
7264 | ||
7265 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7266 | get_identifier ("__vector unsigned int"), | |
7267 | unsigned_V4SI_type_node)); | |
7268 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7269 | get_identifier ("__vector signed int"), | |
7270 | V4SI_type_node)); | |
7271 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7272 | get_identifier ("__vector __bool int"), | |
7273 | bool_V4SI_type_node)); | |
7274 | ||
7275 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7276 | get_identifier ("__vector float"), | |
7277 | V4SF_type_node)); | |
7278 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7279 | get_identifier ("__vector __pixel"), | |
7280 | pixel_V8HI_type_node)); | |
7281 | ||
a3170dc6 | 7282 | if (TARGET_SPE) |
3fdaa45a | 7283 | spe_init_builtins (); |
0ac081f6 AH |
7284 | if (TARGET_ALTIVEC) |
7285 | altivec_init_builtins (); | |
0559cc77 DE |
7286 | if (TARGET_ALTIVEC || TARGET_SPE) |
7287 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
7288 | } |
7289 | ||
a3170dc6 AH |
7290 | /* Search through a set of builtins and enable the mask bits. |
7291 | DESC is an array of builtins. | |
b6d08ca1 | 7292 | SIZE is the total number of builtins. |
a3170dc6 AH |
7293 | START is the builtin enum at which to start. |
7294 | END is the builtin enum at which to end. */ | |
0ac081f6 | 7295 | static void |
a2369ed3 DJ |
7296 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
7297 | enum rs6000_builtins start, | |
7298 | enum rs6000_builtins end) | |
a3170dc6 AH |
7299 | { |
7300 | int i; | |
7301 | ||
7302 | for (i = 0; i < size; ++i) | |
7303 | if (desc[i].code == start) | |
7304 | break; | |
7305 | ||
7306 | if (i == size) | |
7307 | return; | |
7308 | ||
7309 | for (; i < size; ++i) | |
7310 | { | |
7311 | /* Flip all the bits on. */ | |
7312 | desc[i].mask = target_flags; | |
7313 | if (desc[i].code == end) | |
7314 | break; | |
7315 | } | |
7316 | } | |
7317 | ||
7318 | static void | |
863d938c | 7319 | spe_init_builtins (void) |
0ac081f6 | 7320 | { |
a3170dc6 AH |
7321 | tree endlink = void_list_node; |
7322 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
7323 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 7324 | struct builtin_description *d; |
0ac081f6 AH |
7325 | size_t i; |
7326 | ||
a3170dc6 AH |
7327 | tree v2si_ftype_4_v2si |
7328 | = build_function_type | |
3fdaa45a AH |
7329 | (opaque_V2SI_type_node, |
7330 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7331 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7332 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7333 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7334 | endlink))))); |
7335 | ||
7336 | tree v2sf_ftype_4_v2sf | |
7337 | = build_function_type | |
3fdaa45a AH |
7338 | (opaque_V2SF_type_node, |
7339 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7340 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7341 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7342 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7343 | endlink))))); |
7344 | ||
7345 | tree int_ftype_int_v2si_v2si | |
7346 | = build_function_type | |
7347 | (integer_type_node, | |
7348 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7349 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
7350 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7351 | endlink)))); |
7352 | ||
7353 | tree int_ftype_int_v2sf_v2sf | |
7354 | = build_function_type | |
7355 | (integer_type_node, | |
7356 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7357 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
7358 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7359 | endlink)))); |
7360 | ||
7361 | tree void_ftype_v2si_puint_int | |
7362 | = build_function_type (void_type_node, | |
3fdaa45a | 7363 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7364 | tree_cons (NULL_TREE, puint_type_node, |
7365 | tree_cons (NULL_TREE, | |
7366 | integer_type_node, | |
7367 | endlink)))); | |
7368 | ||
7369 | tree void_ftype_v2si_puint_char | |
7370 | = build_function_type (void_type_node, | |
3fdaa45a | 7371 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7372 | tree_cons (NULL_TREE, puint_type_node, |
7373 | tree_cons (NULL_TREE, | |
7374 | char_type_node, | |
7375 | endlink)))); | |
7376 | ||
7377 | tree void_ftype_v2si_pv2si_int | |
7378 | = build_function_type (void_type_node, | |
3fdaa45a | 7379 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7380 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7381 | tree_cons (NULL_TREE, |
7382 | integer_type_node, | |
7383 | endlink)))); | |
7384 | ||
7385 | tree void_ftype_v2si_pv2si_char | |
7386 | = build_function_type (void_type_node, | |
3fdaa45a | 7387 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7388 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7389 | tree_cons (NULL_TREE, |
7390 | char_type_node, | |
7391 | endlink)))); | |
7392 | ||
7393 | tree void_ftype_int | |
7394 | = build_function_type (void_type_node, | |
7395 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
7396 | ||
7397 | tree int_ftype_void | |
36e8d515 | 7398 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
7399 | |
7400 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 7401 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 7402 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7403 | tree_cons (NULL_TREE, integer_type_node, |
7404 | endlink))); | |
7405 | ||
7406 | tree v2si_ftype_puint_int | |
3fdaa45a | 7407 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7408 | tree_cons (NULL_TREE, puint_type_node, |
7409 | tree_cons (NULL_TREE, integer_type_node, | |
7410 | endlink))); | |
7411 | ||
7412 | tree v2si_ftype_pushort_int | |
3fdaa45a | 7413 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7414 | tree_cons (NULL_TREE, pushort_type_node, |
7415 | tree_cons (NULL_TREE, integer_type_node, | |
7416 | endlink))); | |
7417 | ||
00332c9f AH |
7418 | tree v2si_ftype_signed_char |
7419 | = build_function_type (opaque_V2SI_type_node, | |
7420 | tree_cons (NULL_TREE, signed_char_type_node, | |
7421 | endlink)); | |
7422 | ||
a3170dc6 AH |
7423 | /* The initialization of the simple binary and unary builtins is |
7424 | done in rs6000_common_init_builtins, but we have to enable the | |
7425 | mask bits here manually because we have run out of `target_flags' | |
7426 | bits. We really need to redesign this mask business. */ | |
7427 | ||
7428 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
7429 | ARRAY_SIZE (bdesc_2arg), | |
7430 | SPE_BUILTIN_EVADDW, | |
7431 | SPE_BUILTIN_EVXOR); | |
7432 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
7433 | ARRAY_SIZE (bdesc_1arg), | |
7434 | SPE_BUILTIN_EVABS, | |
7435 | SPE_BUILTIN_EVSUBFUSIAAW); | |
7436 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
7437 | ARRAY_SIZE (bdesc_spe_predicates), | |
7438 | SPE_BUILTIN_EVCMPEQ, | |
7439 | SPE_BUILTIN_EVFSTSTLT); | |
7440 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
7441 | ARRAY_SIZE (bdesc_spe_evsel), | |
7442 | SPE_BUILTIN_EVSEL_CMPGTS, | |
7443 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
7444 | ||
36252949 AH |
7445 | (*lang_hooks.decls.pushdecl) |
7446 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
7447 | opaque_V2SI_type_node)); | |
7448 | ||
a3170dc6 AH |
7449 | /* Initialize irregular SPE builtins. */ |
7450 | ||
7451 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); | |
7452 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
7453 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
7454 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
7455 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
7456 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
7457 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
7458 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
7459 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
7460 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
7461 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
7462 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
7463 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
7464 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
7465 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
7466 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
7467 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
7468 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
7469 | |
7470 | /* Loads. */ | |
7471 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
7472 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
7473 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
7474 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
7475 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
7476 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
7477 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
7478 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
7479 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
7480 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
7481 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
7482 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
7483 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
7484 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
7485 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
7486 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
7487 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
7488 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
7489 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
7490 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
7491 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
7492 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
7493 | ||
7494 | /* Predicates. */ | |
7495 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7496 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
7497 | { | |
7498 | tree type; | |
7499 | ||
7500 | switch (insn_data[d->icode].operand[1].mode) | |
7501 | { | |
7502 | case V2SImode: | |
7503 | type = int_ftype_int_v2si_v2si; | |
7504 | break; | |
7505 | case V2SFmode: | |
7506 | type = int_ftype_int_v2sf_v2sf; | |
7507 | break; | |
7508 | default: | |
7509 | abort (); | |
7510 | } | |
7511 | ||
7512 | def_builtin (d->mask, d->name, type, d->code); | |
7513 | } | |
7514 | ||
7515 | /* Evsel predicates. */ | |
7516 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7517 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
7518 | { | |
7519 | tree type; | |
7520 | ||
7521 | switch (insn_data[d->icode].operand[1].mode) | |
7522 | { | |
7523 | case V2SImode: | |
7524 | type = v2si_ftype_4_v2si; | |
7525 | break; | |
7526 | case V2SFmode: | |
7527 | type = v2sf_ftype_4_v2sf; | |
7528 | break; | |
7529 | default: | |
7530 | abort (); | |
7531 | } | |
7532 | ||
7533 | def_builtin (d->mask, d->name, type, d->code); | |
7534 | } | |
7535 | } | |
7536 | ||
7537 | static void | |
863d938c | 7538 | altivec_init_builtins (void) |
a3170dc6 AH |
7539 | { |
7540 | struct builtin_description *d; | |
7541 | struct builtin_description_predicates *dp; | |
7542 | size_t i; | |
7543 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
7544 | tree pint_type_node = build_pointer_type (integer_type_node); | |
7545 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
7546 | tree pchar_type_node = build_pointer_type (char_type_node); | |
7547 | ||
7548 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
7549 | ||
0dbc3651 ZW |
7550 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
7551 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
7552 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
7553 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
7554 | ||
7555 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
7556 | ||
a3170dc6 AH |
7557 | tree int_ftype_int_v4si_v4si |
7558 | = build_function_type_list (integer_type_node, | |
7559 | integer_type_node, V4SI_type_node, | |
7560 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7561 | tree v4sf_ftype_pcfloat |
7562 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 7563 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 7564 | = build_function_type_list (void_type_node, |
a3170dc6 | 7565 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
7566 | tree v4si_ftype_pcint |
7567 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
7568 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
7569 | = build_function_type_list (void_type_node, |
7570 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7571 | tree v8hi_ftype_pcshort |
7572 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 7573 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
7574 | = build_function_type_list (void_type_node, |
7575 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7576 | tree v16qi_ftype_pcchar |
7577 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 7578 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
7579 | = build_function_type_list (void_type_node, |
7580 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 7581 | tree void_ftype_v4si |
b4de2f7d | 7582 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
7583 | tree v8hi_ftype_void |
7584 | = build_function_type (V8HI_type_node, void_list_node); | |
7585 | tree void_ftype_void | |
7586 | = build_function_type (void_type_node, void_list_node); | |
7587 | tree void_ftype_qi | |
7588 | = build_function_type_list (void_type_node, char_type_node, NULL_TREE); | |
0dbc3651 | 7589 | |
b4a62fa0 | 7590 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 7591 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
7592 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7593 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 7594 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
7595 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7596 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 7597 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 7598 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 7599 | |
b4a62fa0 | 7600 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 7601 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7602 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 7603 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7604 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 7605 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7606 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 7607 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7608 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 7609 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7610 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 7611 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
7612 | tree int_ftype_int_v8hi_v8hi |
7613 | = build_function_type_list (integer_type_node, | |
7614 | integer_type_node, V8HI_type_node, | |
7615 | V8HI_type_node, NULL_TREE); | |
7616 | tree int_ftype_int_v16qi_v16qi | |
7617 | = build_function_type_list (integer_type_node, | |
7618 | integer_type_node, V16QI_type_node, | |
7619 | V16QI_type_node, NULL_TREE); | |
7620 | tree int_ftype_int_v4sf_v4sf | |
7621 | = build_function_type_list (integer_type_node, | |
7622 | integer_type_node, V4SF_type_node, | |
7623 | V4SF_type_node, NULL_TREE); | |
7624 | tree v4si_ftype_v4si | |
7625 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7626 | tree v8hi_ftype_v8hi | |
7627 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
7628 | tree v16qi_ftype_v16qi | |
7629 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
7630 | tree v4sf_ftype_v4sf | |
7631 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8bb418a3 | 7632 | tree void_ftype_pcvoid_int_int |
a3170dc6 | 7633 | = build_function_type_list (void_type_node, |
0dbc3651 | 7634 | pcvoid_type_node, integer_type_node, |
8bb418a3 ZL |
7635 | integer_type_node, NULL_TREE); |
7636 | tree int_ftype_pcchar | |
7637 | = build_function_type_list (integer_type_node, | |
7638 | pcchar_type_node, NULL_TREE); | |
7639 | ||
0dbc3651 ZW |
7640 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, |
7641 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
7642 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
7643 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
7644 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
7645 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
7646 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
7647 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
7648 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
7649 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
7650 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
7651 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
7652 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
7653 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
7654 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
7655 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
7656 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
7657 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
7658 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
7659 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); | |
b4a62fa0 SB |
7660 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
7661 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
7662 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
7663 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
7664 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
7665 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
7666 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
7667 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
7668 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
7669 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
7670 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
7671 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
a3170dc6 | 7672 | |
8bb418a3 ZL |
7673 | /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */ |
7674 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar, | |
7675 | ALTIVEC_BUILTIN_COMPILETIME_ERROR); | |
7676 | ||
a3170dc6 AH |
7677 | /* Add the DST variants. */ |
7678 | d = (struct builtin_description *) bdesc_dst; | |
7679 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
8bb418a3 | 7680 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); |
a3170dc6 AH |
7681 | |
7682 | /* Initialize the predicates. */ | |
7683 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
7684 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
7685 | { | |
7686 | enum machine_mode mode1; | |
7687 | tree type; | |
7688 | ||
7689 | mode1 = insn_data[dp->icode].operand[1].mode; | |
7690 | ||
7691 | switch (mode1) | |
7692 | { | |
7693 | case V4SImode: | |
7694 | type = int_ftype_int_v4si_v4si; | |
7695 | break; | |
7696 | case V8HImode: | |
7697 | type = int_ftype_int_v8hi_v8hi; | |
7698 | break; | |
7699 | case V16QImode: | |
7700 | type = int_ftype_int_v16qi_v16qi; | |
7701 | break; | |
7702 | case V4SFmode: | |
7703 | type = int_ftype_int_v4sf_v4sf; | |
7704 | break; | |
7705 | default: | |
7706 | abort (); | |
7707 | } | |
7708 | ||
7709 | def_builtin (dp->mask, dp->name, type, dp->code); | |
7710 | } | |
7711 | ||
7712 | /* Initialize the abs* operators. */ | |
7713 | d = (struct builtin_description *) bdesc_abs; | |
7714 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
7715 | { | |
7716 | enum machine_mode mode0; | |
7717 | tree type; | |
7718 | ||
7719 | mode0 = insn_data[d->icode].operand[0].mode; | |
7720 | ||
7721 | switch (mode0) | |
7722 | { | |
7723 | case V4SImode: | |
7724 | type = v4si_ftype_v4si; | |
7725 | break; | |
7726 | case V8HImode: | |
7727 | type = v8hi_ftype_v8hi; | |
7728 | break; | |
7729 | case V16QImode: | |
7730 | type = v16qi_ftype_v16qi; | |
7731 | break; | |
7732 | case V4SFmode: | |
7733 | type = v4sf_ftype_v4sf; | |
7734 | break; | |
7735 | default: | |
7736 | abort (); | |
7737 | } | |
7738 | ||
7739 | def_builtin (d->mask, d->name, type, d->code); | |
7740 | } | |
7741 | } | |
7742 | ||
7743 | static void | |
863d938c | 7744 | rs6000_common_init_builtins (void) |
a3170dc6 AH |
7745 | { |
7746 | struct builtin_description *d; | |
7747 | size_t i; | |
7748 | ||
7749 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
7750 | = build_function_type_list (V4SF_type_node, | |
7751 | V4SF_type_node, V4SF_type_node, | |
7752 | V16QI_type_node, NULL_TREE); | |
7753 | tree v4si_ftype_v4si_v4si_v16qi | |
7754 | = build_function_type_list (V4SI_type_node, | |
7755 | V4SI_type_node, V4SI_type_node, | |
7756 | V16QI_type_node, NULL_TREE); | |
7757 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
7758 | = build_function_type_list (V8HI_type_node, | |
7759 | V8HI_type_node, V8HI_type_node, | |
7760 | V16QI_type_node, NULL_TREE); | |
7761 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
7762 | = build_function_type_list (V16QI_type_node, | |
7763 | V16QI_type_node, V16QI_type_node, | |
7764 | V16QI_type_node, NULL_TREE); | |
b9e4e5d1 ZL |
7765 | tree v4si_ftype_int |
7766 | = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); | |
7767 | tree v8hi_ftype_int | |
7768 | = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); | |
7769 | tree v16qi_ftype_int | |
7770 | = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); | |
a3170dc6 AH |
7771 | tree v8hi_ftype_v16qi |
7772 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
7773 | tree v4sf_ftype_v4sf | |
7774 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7775 | ||
7776 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
7777 | = build_function_type_list (opaque_V2SI_type_node, |
7778 | opaque_V2SI_type_node, | |
7779 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7780 | |
7781 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
7782 | = build_function_type_list (opaque_V2SF_type_node, |
7783 | opaque_V2SF_type_node, | |
7784 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7785 | |
7786 | tree v2si_ftype_int_int | |
2abe3e28 | 7787 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
7788 | integer_type_node, integer_type_node, |
7789 | NULL_TREE); | |
7790 | ||
7791 | tree v2si_ftype_v2si | |
2abe3e28 AH |
7792 | = build_function_type_list (opaque_V2SI_type_node, |
7793 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7794 | |
7795 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
7796 | = build_function_type_list (opaque_V2SF_type_node, |
7797 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7798 | |
7799 | tree v2sf_ftype_v2si | |
2abe3e28 AH |
7800 | = build_function_type_list (opaque_V2SF_type_node, |
7801 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7802 | |
7803 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
7804 | = build_function_type_list (opaque_V2SI_type_node, |
7805 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7806 | |
7807 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
7808 | = build_function_type_list (opaque_V2SI_type_node, |
7809 | opaque_V2SI_type_node, | |
7810 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
7811 | |
7812 | tree v2si_ftype_int_char | |
2abe3e28 | 7813 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
7814 | integer_type_node, char_type_node, NULL_TREE); |
7815 | ||
7816 | tree v2si_ftype_char | |
2abe3e28 AH |
7817 | = build_function_type_list (opaque_V2SI_type_node, |
7818 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
7819 | |
7820 | tree int_ftype_int_int | |
7821 | = build_function_type_list (integer_type_node, | |
7822 | integer_type_node, integer_type_node, | |
7823 | NULL_TREE); | |
95385cbb | 7824 | |
0ac081f6 | 7825 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
7826 | = build_function_type_list (V4SI_type_node, |
7827 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
b9e4e5d1 | 7828 | tree v4sf_ftype_v4si_int |
b4de2f7d | 7829 | = build_function_type_list (V4SF_type_node, |
b9e4e5d1 ZL |
7830 | V4SI_type_node, integer_type_node, NULL_TREE); |
7831 | tree v4si_ftype_v4sf_int | |
b4de2f7d | 7832 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
7833 | V4SF_type_node, integer_type_node, NULL_TREE); |
7834 | tree v4si_ftype_v4si_int | |
b4de2f7d | 7835 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
7836 | V4SI_type_node, integer_type_node, NULL_TREE); |
7837 | tree v8hi_ftype_v8hi_int | |
b4de2f7d | 7838 | = build_function_type_list (V8HI_type_node, |
b9e4e5d1 ZL |
7839 | V8HI_type_node, integer_type_node, NULL_TREE); |
7840 | tree v16qi_ftype_v16qi_int | |
b4de2f7d | 7841 | = build_function_type_list (V16QI_type_node, |
b9e4e5d1 ZL |
7842 | V16QI_type_node, integer_type_node, NULL_TREE); |
7843 | tree v16qi_ftype_v16qi_v16qi_int | |
b4de2f7d AH |
7844 | = build_function_type_list (V16QI_type_node, |
7845 | V16QI_type_node, V16QI_type_node, | |
b9e4e5d1 ZL |
7846 | integer_type_node, NULL_TREE); |
7847 | tree v8hi_ftype_v8hi_v8hi_int | |
b4de2f7d AH |
7848 | = build_function_type_list (V8HI_type_node, |
7849 | V8HI_type_node, V8HI_type_node, | |
b9e4e5d1 ZL |
7850 | integer_type_node, NULL_TREE); |
7851 | tree v4si_ftype_v4si_v4si_int | |
b4de2f7d AH |
7852 | = build_function_type_list (V4SI_type_node, |
7853 | V4SI_type_node, V4SI_type_node, | |
b9e4e5d1 ZL |
7854 | integer_type_node, NULL_TREE); |
7855 | tree v4sf_ftype_v4sf_v4sf_int | |
b4de2f7d AH |
7856 | = build_function_type_list (V4SF_type_node, |
7857 | V4SF_type_node, V4SF_type_node, | |
b9e4e5d1 | 7858 | integer_type_node, NULL_TREE); |
0ac081f6 | 7859 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
7860 | = build_function_type_list (V4SF_type_node, |
7861 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
617e0e1d | 7862 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
7863 | = build_function_type_list (V4SF_type_node, |
7864 | V4SF_type_node, V4SF_type_node, | |
7865 | V4SI_type_node, NULL_TREE); | |
2212663f | 7866 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
7867 | = build_function_type_list (V4SF_type_node, |
7868 | V4SF_type_node, V4SF_type_node, | |
7869 | V4SF_type_node, NULL_TREE); | |
617e0e1d | 7870 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
7871 | = build_function_type_list (V4SI_type_node, |
7872 | V4SI_type_node, V4SI_type_node, | |
7873 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7874 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
7875 | = build_function_type_list (V8HI_type_node, |
7876 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 7877 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
7878 | = build_function_type_list (V8HI_type_node, |
7879 | V8HI_type_node, V8HI_type_node, | |
7880 | V8HI_type_node, NULL_TREE); | |
2212663f | 7881 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
7882 | = build_function_type_list (V4SI_type_node, |
7883 | V8HI_type_node, V8HI_type_node, | |
7884 | V4SI_type_node, NULL_TREE); | |
2212663f | 7885 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
7886 | = build_function_type_list (V4SI_type_node, |
7887 | V16QI_type_node, V16QI_type_node, | |
7888 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7889 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
7890 | = build_function_type_list (V16QI_type_node, |
7891 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7892 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
7893 | = build_function_type_list (V4SI_type_node, |
7894 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 7895 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
7896 | = build_function_type_list (V8HI_type_node, |
7897 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7898 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
7899 | = build_function_type_list (V4SI_type_node, |
7900 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7901 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
7902 | = build_function_type_list (V8HI_type_node, |
7903 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7904 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
7905 | = build_function_type_list (V16QI_type_node, |
7906 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7907 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
7908 | = build_function_type_list (V4SI_type_node, |
7909 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 7910 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
7911 | = build_function_type_list (V4SI_type_node, |
7912 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7913 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
7914 | = build_function_type_list (V4SI_type_node, |
7915 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7916 | tree v4si_ftype_v8hi |
7917 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
7918 | tree int_ftype_v4si_v4si | |
7919 | = build_function_type_list (integer_type_node, | |
7920 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7921 | tree int_ftype_v4sf_v4sf | |
7922 | = build_function_type_list (integer_type_node, | |
7923 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7924 | tree int_ftype_v16qi_v16qi | |
7925 | = build_function_type_list (integer_type_node, | |
7926 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7927 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
7928 | = build_function_type_list (integer_type_node, |
7929 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7930 | |
6f317ef3 | 7931 | /* Add the simple ternary operators. */ |
2212663f | 7932 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 7933 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f DB |
7934 | { |
7935 | ||
7936 | enum machine_mode mode0, mode1, mode2, mode3; | |
7937 | tree type; | |
7938 | ||
0559cc77 | 7939 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
7940 | continue; |
7941 | ||
7942 | mode0 = insn_data[d->icode].operand[0].mode; | |
7943 | mode1 = insn_data[d->icode].operand[1].mode; | |
7944 | mode2 = insn_data[d->icode].operand[2].mode; | |
7945 | mode3 = insn_data[d->icode].operand[3].mode; | |
7946 | ||
7947 | /* When all four are of the same mode. */ | |
7948 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
7949 | { | |
7950 | switch (mode0) | |
7951 | { | |
617e0e1d DB |
7952 | case V4SImode: |
7953 | type = v4si_ftype_v4si_v4si_v4si; | |
7954 | break; | |
2212663f DB |
7955 | case V4SFmode: |
7956 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
7957 | break; | |
7958 | case V8HImode: | |
7959 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
7960 | break; | |
7961 | case V16QImode: | |
7962 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
7963 | break; | |
7964 | default: | |
7965 | abort(); | |
7966 | } | |
7967 | } | |
7968 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
7969 | { | |
7970 | switch (mode0) | |
7971 | { | |
7972 | case V4SImode: | |
7973 | type = v4si_ftype_v4si_v4si_v16qi; | |
7974 | break; | |
7975 | case V4SFmode: | |
7976 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
7977 | break; | |
7978 | case V8HImode: | |
7979 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
7980 | break; | |
7981 | case V16QImode: | |
7982 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
7983 | break; | |
7984 | default: | |
7985 | abort(); | |
7986 | } | |
7987 | } | |
7988 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode | |
7989 | && mode3 == V4SImode) | |
24408032 | 7990 | type = v4si_ftype_v16qi_v16qi_v4si; |
2212663f DB |
7991 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
7992 | && mode3 == V4SImode) | |
24408032 | 7993 | type = v4si_ftype_v8hi_v8hi_v4si; |
617e0e1d DB |
7994 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
7995 | && mode3 == V4SImode) | |
24408032 AH |
7996 | type = v4sf_ftype_v4sf_v4sf_v4si; |
7997 | ||
7998 | /* vchar, vchar, vchar, 4 bit literal. */ | |
7999 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
8000 | && mode3 == QImode) | |
b9e4e5d1 | 8001 | type = v16qi_ftype_v16qi_v16qi_int; |
24408032 AH |
8002 | |
8003 | /* vshort, vshort, vshort, 4 bit literal. */ | |
8004 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
8005 | && mode3 == QImode) | |
b9e4e5d1 | 8006 | type = v8hi_ftype_v8hi_v8hi_int; |
24408032 AH |
8007 | |
8008 | /* vint, vint, vint, 4 bit literal. */ | |
8009 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
8010 | && mode3 == QImode) | |
b9e4e5d1 | 8011 | type = v4si_ftype_v4si_v4si_int; |
24408032 AH |
8012 | |
8013 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
8014 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
8015 | && mode3 == QImode) | |
b9e4e5d1 | 8016 | type = v4sf_ftype_v4sf_v4sf_int; |
24408032 | 8017 | |
2212663f DB |
8018 | else |
8019 | abort (); | |
8020 | ||
8021 | def_builtin (d->mask, d->name, type, d->code); | |
8022 | } | |
8023 | ||
0ac081f6 | 8024 | /* Add the simple binary operators. */ |
00b960c7 | 8025 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 8026 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
8027 | { |
8028 | enum machine_mode mode0, mode1, mode2; | |
8029 | tree type; | |
8030 | ||
0559cc77 | 8031 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
0ac081f6 AH |
8032 | continue; |
8033 | ||
8034 | mode0 = insn_data[d->icode].operand[0].mode; | |
8035 | mode1 = insn_data[d->icode].operand[1].mode; | |
8036 | mode2 = insn_data[d->icode].operand[2].mode; | |
8037 | ||
8038 | /* When all three operands are of the same mode. */ | |
8039 | if (mode0 == mode1 && mode1 == mode2) | |
8040 | { | |
8041 | switch (mode0) | |
8042 | { | |
8043 | case V4SFmode: | |
8044 | type = v4sf_ftype_v4sf_v4sf; | |
8045 | break; | |
8046 | case V4SImode: | |
8047 | type = v4si_ftype_v4si_v4si; | |
8048 | break; | |
8049 | case V16QImode: | |
8050 | type = v16qi_ftype_v16qi_v16qi; | |
8051 | break; | |
8052 | case V8HImode: | |
8053 | type = v8hi_ftype_v8hi_v8hi; | |
8054 | break; | |
a3170dc6 AH |
8055 | case V2SImode: |
8056 | type = v2si_ftype_v2si_v2si; | |
8057 | break; | |
8058 | case V2SFmode: | |
8059 | type = v2sf_ftype_v2sf_v2sf; | |
8060 | break; | |
8061 | case SImode: | |
8062 | type = int_ftype_int_int; | |
8063 | break; | |
0ac081f6 AH |
8064 | default: |
8065 | abort (); | |
8066 | } | |
8067 | } | |
8068 | ||
8069 | /* A few other combos we really don't want to do manually. */ | |
8070 | ||
8071 | /* vint, vfloat, vfloat. */ | |
8072 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
8073 | type = v4si_ftype_v4sf_v4sf; | |
8074 | ||
8075 | /* vshort, vchar, vchar. */ | |
8076 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
8077 | type = v8hi_ftype_v16qi_v16qi; | |
8078 | ||
8079 | /* vint, vshort, vshort. */ | |
8080 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
8081 | type = v4si_ftype_v8hi_v8hi; | |
8082 | ||
8083 | /* vshort, vint, vint. */ | |
8084 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
8085 | type = v8hi_ftype_v4si_v4si; | |
8086 | ||
8087 | /* vchar, vshort, vshort. */ | |
8088 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
8089 | type = v16qi_ftype_v8hi_v8hi; | |
8090 | ||
8091 | /* vint, vchar, vint. */ | |
8092 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
8093 | type = v4si_ftype_v16qi_v4si; | |
8094 | ||
fa066a23 AH |
8095 | /* vint, vchar, vchar. */ |
8096 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
8097 | type = v4si_ftype_v16qi_v16qi; | |
8098 | ||
0ac081f6 AH |
8099 | /* vint, vshort, vint. */ |
8100 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
8101 | type = v4si_ftype_v8hi_v4si; | |
2212663f DB |
8102 | |
8103 | /* vint, vint, 5 bit literal. */ | |
8104 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8105 | type = v4si_ftype_v4si_int; |
2212663f DB |
8106 | |
8107 | /* vshort, vshort, 5 bit literal. */ | |
8108 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
b9e4e5d1 | 8109 | type = v8hi_ftype_v8hi_int; |
2212663f DB |
8110 | |
8111 | /* vchar, vchar, 5 bit literal. */ | |
8112 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
b9e4e5d1 | 8113 | type = v16qi_ftype_v16qi_int; |
0ac081f6 | 8114 | |
617e0e1d DB |
8115 | /* vfloat, vint, 5 bit literal. */ |
8116 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8117 | type = v4sf_ftype_v4si_int; |
617e0e1d DB |
8118 | |
8119 | /* vint, vfloat, 5 bit literal. */ | |
8120 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
b9e4e5d1 | 8121 | type = v4si_ftype_v4sf_int; |
617e0e1d | 8122 | |
a3170dc6 AH |
8123 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
8124 | type = v2si_ftype_int_int; | |
8125 | ||
8126 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
8127 | type = v2si_ftype_v2si_char; | |
8128 | ||
8129 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
8130 | type = v2si_ftype_int_char; | |
8131 | ||
0ac081f6 AH |
8132 | /* int, x, x. */ |
8133 | else if (mode0 == SImode) | |
8134 | { | |
8135 | switch (mode1) | |
8136 | { | |
8137 | case V4SImode: | |
8138 | type = int_ftype_v4si_v4si; | |
8139 | break; | |
8140 | case V4SFmode: | |
8141 | type = int_ftype_v4sf_v4sf; | |
8142 | break; | |
8143 | case V16QImode: | |
8144 | type = int_ftype_v16qi_v16qi; | |
8145 | break; | |
8146 | case V8HImode: | |
8147 | type = int_ftype_v8hi_v8hi; | |
8148 | break; | |
8149 | default: | |
8150 | abort (); | |
8151 | } | |
8152 | } | |
8153 | ||
8154 | else | |
8155 | abort (); | |
8156 | ||
2212663f DB |
8157 | def_builtin (d->mask, d->name, type, d->code); |
8158 | } | |
24408032 | 8159 | |
2212663f DB |
8160 | /* Add the simple unary operators. */ |
8161 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 8162 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
8163 | { |
8164 | enum machine_mode mode0, mode1; | |
8165 | tree type; | |
8166 | ||
0559cc77 | 8167 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
8168 | continue; |
8169 | ||
8170 | mode0 = insn_data[d->icode].operand[0].mode; | |
8171 | mode1 = insn_data[d->icode].operand[1].mode; | |
8172 | ||
8173 | if (mode0 == V4SImode && mode1 == QImode) | |
b9e4e5d1 | 8174 | type = v4si_ftype_int; |
2212663f | 8175 | else if (mode0 == V8HImode && mode1 == QImode) |
b9e4e5d1 | 8176 | type = v8hi_ftype_int; |
2212663f | 8177 | else if (mode0 == V16QImode && mode1 == QImode) |
b9e4e5d1 | 8178 | type = v16qi_ftype_int; |
617e0e1d DB |
8179 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
8180 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
8181 | else if (mode0 == V8HImode && mode1 == V16QImode) |
8182 | type = v8hi_ftype_v16qi; | |
8183 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
8184 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
8185 | else if (mode0 == V2SImode && mode1 == V2SImode) |
8186 | type = v2si_ftype_v2si; | |
8187 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
8188 | type = v2sf_ftype_v2sf; | |
8189 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
8190 | type = v2sf_ftype_v2si; | |
8191 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
8192 | type = v2si_ftype_v2sf; | |
8193 | else if (mode0 == V2SImode && mode1 == QImode) | |
8194 | type = v2si_ftype_char; | |
2212663f DB |
8195 | else |
8196 | abort (); | |
8197 | ||
0ac081f6 AH |
8198 | def_builtin (d->mask, d->name, type, d->code); |
8199 | } | |
8200 | } | |
8201 | ||
c15c90bb ZW |
8202 | static void |
8203 | rs6000_init_libfuncs (void) | |
8204 | { | |
8205 | if (!TARGET_HARD_FLOAT) | |
8206 | return; | |
8207 | ||
c9034561 | 8208 | if (DEFAULT_ABI != ABI_V4) |
c15c90bb | 8209 | { |
c9034561 | 8210 | if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC) |
c15c90bb | 8211 | { |
c9034561 | 8212 | /* AIX library routines for float->int conversion. */ |
85363ca0 ZW |
8213 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); |
8214 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
4274207b DE |
8215 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); |
8216 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
c15c90bb ZW |
8217 | } |
8218 | ||
c9034561 | 8219 | /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8220 | set_optab_libfunc (add_optab, TFmode, "_xlqadd"); |
8221 | set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); | |
8222 | set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); | |
8223 | set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); | |
8224 | } | |
c9034561 | 8225 | else |
c15c90bb | 8226 | { |
c9034561 | 8227 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8228 | |
8229 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
8230 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
8231 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
8232 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
8233 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
8234 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
8235 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
8236 | ||
c9034561 ZW |
8237 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
8238 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
8239 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
8240 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
8241 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
8242 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
8243 | ||
85363ca0 ZW |
8244 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
8245 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
8246 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
8247 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
8248 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
8249 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
8250 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
c15c90bb ZW |
8251 | } |
8252 | } | |
35aff10b | 8253 | \f |
7e69e155 MM |
8254 | /* Expand a block move operation, and return 1 if successful. Return 0 |
8255 | if we should let the compiler generate normal code. | |
8256 | ||
8257 | operands[0] is the destination | |
8258 | operands[1] is the source | |
8259 | operands[2] is the length | |
8260 | operands[3] is the alignment */ | |
8261 | ||
3933e0e1 MM |
8262 | #define MAX_MOVE_REG 4 |
8263 | ||
7e69e155 | 8264 | int |
a2369ed3 | 8265 | expand_block_move (rtx operands[]) |
7e69e155 | 8266 | { |
b6c9286a MM |
8267 | rtx orig_dest = operands[0]; |
8268 | rtx orig_src = operands[1]; | |
7e69e155 | 8269 | rtx bytes_rtx = operands[2]; |
7e69e155 | 8270 | rtx align_rtx = operands[3]; |
3933e0e1 | 8271 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 8272 | int align; |
3933e0e1 MM |
8273 | int bytes; |
8274 | int offset; | |
7e69e155 | 8275 | int move_bytes; |
cabfd258 GK |
8276 | rtx stores[MAX_MOVE_REG]; |
8277 | int num_reg = 0; | |
7e69e155 | 8278 | |
3933e0e1 | 8279 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 8280 | if (! constp) |
3933e0e1 MM |
8281 | return 0; |
8282 | ||
5ee95df6 FS |
8283 | /* If this is not a fixed size alignment, abort */ |
8284 | if (GET_CODE (align_rtx) != CONST_INT) | |
8285 | abort (); | |
8286 | align = INTVAL (align_rtx); | |
8287 | ||
7e69e155 | 8288 | /* Anything to move? */ |
3933e0e1 MM |
8289 | bytes = INTVAL (bytes_rtx); |
8290 | if (bytes <= 0) | |
7e69e155 MM |
8291 | return 1; |
8292 | ||
ea9982a8 | 8293 | /* store_one_arg depends on expand_block_move to handle at least the size of |
6f317ef3 | 8294 | reg_parm_stack_space. */ |
ea9982a8 | 8295 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
8296 | return 0; |
8297 | ||
cabfd258 | 8298 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 8299 | { |
cabfd258 | 8300 | union { |
70128ad9 | 8301 | rtx (*movmemsi) (rtx, rtx, rtx, rtx); |
a2369ed3 | 8302 | rtx (*mov) (rtx, rtx); |
cabfd258 GK |
8303 | } gen_func; |
8304 | enum machine_mode mode = BLKmode; | |
8305 | rtx src, dest; | |
8306 | ||
8307 | if (TARGET_STRING | |
8308 | && bytes > 24 /* move up to 32 bytes at a time */ | |
8309 | && ! fixed_regs[5] | |
8310 | && ! fixed_regs[6] | |
8311 | && ! fixed_regs[7] | |
8312 | && ! fixed_regs[8] | |
8313 | && ! fixed_regs[9] | |
8314 | && ! fixed_regs[10] | |
8315 | && ! fixed_regs[11] | |
8316 | && ! fixed_regs[12]) | |
7e69e155 | 8317 | { |
cabfd258 | 8318 | move_bytes = (bytes > 32) ? 32 : bytes; |
70128ad9 | 8319 | gen_func.movmemsi = gen_movmemsi_8reg; |
cabfd258 GK |
8320 | } |
8321 | else if (TARGET_STRING | |
8322 | && bytes > 16 /* move up to 24 bytes at a time */ | |
8323 | && ! fixed_regs[5] | |
8324 | && ! fixed_regs[6] | |
8325 | && ! fixed_regs[7] | |
8326 | && ! fixed_regs[8] | |
8327 | && ! fixed_regs[9] | |
8328 | && ! fixed_regs[10]) | |
8329 | { | |
8330 | move_bytes = (bytes > 24) ? 24 : bytes; | |
70128ad9 | 8331 | gen_func.movmemsi = gen_movmemsi_6reg; |
cabfd258 GK |
8332 | } |
8333 | else if (TARGET_STRING | |
8334 | && bytes > 8 /* move up to 16 bytes at a time */ | |
8335 | && ! fixed_regs[5] | |
8336 | && ! fixed_regs[6] | |
8337 | && ! fixed_regs[7] | |
8338 | && ! fixed_regs[8]) | |
8339 | { | |
8340 | move_bytes = (bytes > 16) ? 16 : bytes; | |
70128ad9 | 8341 | gen_func.movmemsi = gen_movmemsi_4reg; |
cabfd258 GK |
8342 | } |
8343 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8344 | /* 64-bit loads and stores require word-aligned | |
8345 | displacements. */ | |
8346 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
8347 | { | |
8348 | move_bytes = 8; | |
8349 | mode = DImode; | |
8350 | gen_func.mov = gen_movdi; | |
8351 | } | |
8352 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
8353 | { /* move up to 8 bytes at a time */ | |
8354 | move_bytes = (bytes > 8) ? 8 : bytes; | |
70128ad9 | 8355 | gen_func.movmemsi = gen_movmemsi_2reg; |
cabfd258 GK |
8356 | } |
8357 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) | |
8358 | { /* move 4 bytes */ | |
8359 | move_bytes = 4; | |
8360 | mode = SImode; | |
8361 | gen_func.mov = gen_movsi; | |
8362 | } | |
8363 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) | |
8364 | { /* move 2 bytes */ | |
8365 | move_bytes = 2; | |
8366 | mode = HImode; | |
8367 | gen_func.mov = gen_movhi; | |
8368 | } | |
8369 | else if (TARGET_STRING && bytes > 1) | |
8370 | { /* move up to 4 bytes at a time */ | |
8371 | move_bytes = (bytes > 4) ? 4 : bytes; | |
70128ad9 | 8372 | gen_func.movmemsi = gen_movmemsi_1reg; |
cabfd258 GK |
8373 | } |
8374 | else /* move 1 byte at a time */ | |
8375 | { | |
8376 | move_bytes = 1; | |
8377 | mode = QImode; | |
8378 | gen_func.mov = gen_movqi; | |
8379 | } | |
8380 | ||
8381 | src = adjust_address (orig_src, mode, offset); | |
8382 | dest = adjust_address (orig_dest, mode, offset); | |
8383 | ||
8384 | if (mode != BLKmode) | |
8385 | { | |
8386 | rtx tmp_reg = gen_reg_rtx (mode); | |
8387 | ||
8388 | emit_insn ((*gen_func.mov) (tmp_reg, src)); | |
8389 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 8390 | } |
3933e0e1 | 8391 | |
cabfd258 GK |
8392 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
8393 | { | |
8394 | int i; | |
8395 | for (i = 0; i < num_reg; i++) | |
8396 | emit_insn (stores[i]); | |
8397 | num_reg = 0; | |
8398 | } | |
35aff10b | 8399 | |
cabfd258 | 8400 | if (mode == BLKmode) |
7e69e155 | 8401 | { |
70128ad9 | 8402 | /* Move the address into scratch registers. The movmemsi |
cabfd258 GK |
8403 | patterns require zero offset. */ |
8404 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 8405 | { |
cabfd258 GK |
8406 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
8407 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 8408 | } |
cabfd258 GK |
8409 | set_mem_size (src, GEN_INT (move_bytes)); |
8410 | ||
8411 | if (!REG_P (XEXP (dest, 0))) | |
3933e0e1 | 8412 | { |
cabfd258 GK |
8413 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
8414 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 8415 | } |
cabfd258 GK |
8416 | set_mem_size (dest, GEN_INT (move_bytes)); |
8417 | ||
70128ad9 | 8418 | emit_insn ((*gen_func.movmemsi) (dest, src, |
cabfd258 GK |
8419 | GEN_INT (move_bytes & 31), |
8420 | align_rtx)); | |
7e69e155 | 8421 | } |
7e69e155 MM |
8422 | } |
8423 | ||
8424 | return 1; | |
8425 | } | |
8426 | ||
9878760c RK |
8427 | \f |
8428 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
8429 | PARALLEL and the first section will be tested. */ | |
8430 | ||
8431 | int | |
a2369ed3 | 8432 | load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
8433 | { |
8434 | int count = XVECLEN (op, 0); | |
e2c953b6 | 8435 | unsigned int dest_regno; |
9878760c RK |
8436 | rtx src_addr; |
8437 | int i; | |
8438 | ||
8439 | /* Perform a quick check so we don't blow up below. */ | |
8440 | if (count <= 1 | |
8441 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8442 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
8443 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
8444 | return 0; | |
8445 | ||
8446 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
8447 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
8448 | ||
8449 | for (i = 1; i < count; i++) | |
8450 | { | |
8451 | rtx elt = XVECEXP (op, 0, i); | |
8452 | ||
8453 | if (GET_CODE (elt) != SET | |
8454 | || GET_CODE (SET_DEST (elt)) != REG | |
8455 | || GET_MODE (SET_DEST (elt)) != SImode | |
8456 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
8457 | || GET_CODE (SET_SRC (elt)) != MEM | |
8458 | || GET_MODE (SET_SRC (elt)) != SImode | |
8459 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
8460 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
8461 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
8462 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
8463 | return 0; | |
8464 | } | |
8465 | ||
8466 | return 1; | |
8467 | } | |
8468 | ||
8469 | /* Similar, but tests for store multiple. Here, the second vector element | |
8470 | is a CLOBBER. It will be tested later. */ | |
8471 | ||
8472 | int | |
a2369ed3 | 8473 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
8474 | { |
8475 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 8476 | unsigned int src_regno; |
9878760c RK |
8477 | rtx dest_addr; |
8478 | int i; | |
8479 | ||
8480 | /* Perform a quick check so we don't blow up below. */ | |
8481 | if (count <= 1 | |
8482 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8483 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
8484 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
8485 | return 0; | |
8486 | ||
8487 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
8488 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
8489 | ||
8490 | for (i = 1; i < count; i++) | |
8491 | { | |
8492 | rtx elt = XVECEXP (op, 0, i + 1); | |
8493 | ||
8494 | if (GET_CODE (elt) != SET | |
8495 | || GET_CODE (SET_SRC (elt)) != REG | |
8496 | || GET_MODE (SET_SRC (elt)) != SImode | |
8497 | || REGNO (SET_SRC (elt)) != src_regno + i | |
8498 | || GET_CODE (SET_DEST (elt)) != MEM | |
8499 | || GET_MODE (SET_DEST (elt)) != SImode | |
8500 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
8501 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
8502 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
8503 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
8504 | return 0; | |
8505 | } | |
8506 | ||
8507 | return 1; | |
8508 | } | |
9ebbca7d | 8509 | |
9caa3eb2 DE |
8510 | /* Return a string to perform a load_multiple operation. |
8511 | operands[0] is the vector. | |
8512 | operands[1] is the source address. | |
8513 | operands[2] is the first destination register. */ | |
8514 | ||
8515 | const char * | |
a2369ed3 | 8516 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
8517 | { |
8518 | /* We have to handle the case where the pseudo used to contain the address | |
8519 | is assigned to one of the output registers. */ | |
8520 | int i, j; | |
8521 | int words = XVECLEN (operands[0], 0); | |
8522 | rtx xop[10]; | |
8523 | ||
8524 | if (XVECLEN (operands[0], 0) == 1) | |
8525 | return "{l|lwz} %2,0(%1)"; | |
8526 | ||
8527 | for (i = 0; i < words; i++) | |
8528 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
8529 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
8530 | { | |
8531 | if (i == words-1) | |
8532 | { | |
8533 | xop[0] = GEN_INT (4 * (words-1)); | |
8534 | xop[1] = operands[1]; | |
8535 | xop[2] = operands[2]; | |
8536 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
8537 | return ""; | |
8538 | } | |
8539 | else if (i == 0) | |
8540 | { | |
8541 | xop[0] = GEN_INT (4 * (words-1)); | |
8542 | xop[1] = operands[1]; | |
8543 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8544 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
8545 | return ""; | |
8546 | } | |
8547 | else | |
8548 | { | |
8549 | for (j = 0; j < words; j++) | |
8550 | if (j != i) | |
8551 | { | |
8552 | xop[0] = GEN_INT (j * 4); | |
8553 | xop[1] = operands[1]; | |
8554 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
8555 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
8556 | } | |
8557 | xop[0] = GEN_INT (i * 4); | |
8558 | xop[1] = operands[1]; | |
8559 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
8560 | return ""; | |
8561 | } | |
8562 | } | |
8563 | ||
8564 | return "{lsi|lswi} %2,%1,%N0"; | |
8565 | } | |
8566 | ||
00b960c7 AH |
8567 | /* Return 1 for a parallel vrsave operation. */ |
8568 | ||
8569 | int | |
a2369ed3 | 8570 | vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
00b960c7 AH |
8571 | { |
8572 | int count = XVECLEN (op, 0); | |
8573 | unsigned int dest_regno, src_regno; | |
8574 | int i; | |
8575 | ||
8576 | if (count <= 1 | |
8577 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8578 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 8579 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
8580 | return 0; |
8581 | ||
8582 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
8583 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
8584 | ||
8585 | if (dest_regno != VRSAVE_REGNO | |
8586 | && src_regno != VRSAVE_REGNO) | |
8587 | return 0; | |
8588 | ||
8589 | for (i = 1; i < count; i++) | |
8590 | { | |
8591 | rtx elt = XVECEXP (op, 0, i); | |
8592 | ||
9aa86737 AH |
8593 | if (GET_CODE (elt) != CLOBBER |
8594 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
8595 | return 0; |
8596 | } | |
8597 | ||
8598 | return 1; | |
8599 | } | |
8600 | ||
2c4a9cff DE |
8601 | /* Return 1 for an PARALLEL suitable for mfcr. */ |
8602 | ||
8603 | int | |
a2369ed3 | 8604 | mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2c4a9cff DE |
8605 | { |
8606 | int count = XVECLEN (op, 0); | |
8607 | int i; | |
8608 | ||
8609 | /* Perform a quick check so we don't blow up below. */ | |
8610 | if (count < 1 | |
8611 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8612 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
8613 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
8614 | return 0; | |
8615 | ||
8616 | for (i = 0; i < count; i++) | |
8617 | { | |
8618 | rtx exp = XVECEXP (op, 0, i); | |
8619 | rtx unspec; | |
8620 | int maskval; | |
8621 | rtx src_reg; | |
8622 | ||
8623 | src_reg = XVECEXP (SET_SRC (exp), 0, 0); | |
8624 | ||
8625 | if (GET_CODE (src_reg) != REG | |
8626 | || GET_MODE (src_reg) != CCmode | |
8627 | || ! CR_REGNO_P (REGNO (src_reg))) | |
8628 | return 0; | |
8629 | ||
8630 | if (GET_CODE (exp) != SET | |
8631 | || GET_CODE (SET_DEST (exp)) != REG | |
8632 | || GET_MODE (SET_DEST (exp)) != SImode | |
8633 | || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) | |
8634 | return 0; | |
8635 | unspec = SET_SRC (exp); | |
8636 | maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); | |
8637 | ||
8638 | if (GET_CODE (unspec) != UNSPEC | |
8639 | || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR | |
8640 | || XVECLEN (unspec, 0) != 2 | |
8641 | || XVECEXP (unspec, 0, 0) != src_reg | |
8642 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
8643 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
8644 | return 0; | |
8645 | } | |
8646 | return 1; | |
8647 | } | |
8648 | ||
a4f6c312 | 8649 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
8650 | |
8651 | int | |
a2369ed3 | 8652 | mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
8653 | { |
8654 | int count = XVECLEN (op, 0); | |
8655 | int i; | |
9ebbca7d GK |
8656 | rtx src_reg; |
8657 | ||
8658 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
8659 | if (count < 1 |
8660 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8661 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
8662 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 8663 | return 0; |
e35b9579 | 8664 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
8665 | |
8666 | if (GET_CODE (src_reg) != REG | |
8667 | || GET_MODE (src_reg) != SImode | |
8668 | || ! INT_REGNO_P (REGNO (src_reg))) | |
8669 | return 0; | |
8670 | ||
e35b9579 | 8671 | for (i = 0; i < count; i++) |
9ebbca7d GK |
8672 | { |
8673 | rtx exp = XVECEXP (op, 0, i); | |
8674 | rtx unspec; | |
8675 | int maskval; | |
8676 | ||
8677 | if (GET_CODE (exp) != SET | |
8678 | || GET_CODE (SET_DEST (exp)) != REG | |
8679 | || GET_MODE (SET_DEST (exp)) != CCmode | |
8680 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
8681 | return 0; | |
8682 | unspec = SET_SRC (exp); | |
8683 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
8684 | |
8685 | if (GET_CODE (unspec) != UNSPEC | |
615158e2 | 8686 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR |
9ebbca7d GK |
8687 | || XVECLEN (unspec, 0) != 2 |
8688 | || XVECEXP (unspec, 0, 0) != src_reg | |
8689 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
8690 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
8691 | return 0; | |
8692 | } | |
e35b9579 | 8693 | return 1; |
9ebbca7d GK |
8694 | } |
8695 | ||
a4f6c312 | 8696 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
8697 | |
8698 | int | |
a2369ed3 | 8699 | lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
8700 | { |
8701 | int count = XVECLEN (op, 0); | |
e2c953b6 | 8702 | unsigned int dest_regno; |
9ebbca7d | 8703 | rtx src_addr; |
e2c953b6 | 8704 | unsigned int base_regno; |
9ebbca7d GK |
8705 | HOST_WIDE_INT offset; |
8706 | int i; | |
8707 | ||
8708 | /* Perform a quick check so we don't blow up below. */ | |
8709 | if (count <= 1 | |
8710 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8711 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
8712 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
8713 | return 0; | |
8714 | ||
8715 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
8716 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
8717 | ||
8718 | if (dest_regno > 31 | |
e2c953b6 | 8719 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
8720 | return 0; |
8721 | ||
4d588c14 | 8722 | if (legitimate_indirect_address_p (src_addr, 0)) |
9ebbca7d GK |
8723 | { |
8724 | offset = 0; | |
8725 | base_regno = REGNO (src_addr); | |
8726 | if (base_regno == 0) | |
8727 | return 0; | |
8728 | } | |
76d2b81d | 8729 | else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0)) |
9ebbca7d GK |
8730 | { |
8731 | offset = INTVAL (XEXP (src_addr, 1)); | |
8732 | base_regno = REGNO (XEXP (src_addr, 0)); | |
8733 | } | |
8734 | else | |
8735 | return 0; | |
8736 | ||
8737 | for (i = 0; i < count; i++) | |
8738 | { | |
8739 | rtx elt = XVECEXP (op, 0, i); | |
8740 | rtx newaddr; | |
8741 | rtx addr_reg; | |
8742 | HOST_WIDE_INT newoffset; | |
8743 | ||
8744 | if (GET_CODE (elt) != SET | |
8745 | || GET_CODE (SET_DEST (elt)) != REG | |
8746 | || GET_MODE (SET_DEST (elt)) != SImode | |
8747 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
8748 | || GET_CODE (SET_SRC (elt)) != MEM | |
8749 | || GET_MODE (SET_SRC (elt)) != SImode) | |
8750 | return 0; | |
8751 | newaddr = XEXP (SET_SRC (elt), 0); | |
4d588c14 | 8752 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
8753 | { |
8754 | newoffset = 0; | |
8755 | addr_reg = newaddr; | |
8756 | } | |
76d2b81d | 8757 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
8758 | { |
8759 | addr_reg = XEXP (newaddr, 0); | |
8760 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
8761 | } | |
8762 | else | |
8763 | return 0; | |
8764 | if (REGNO (addr_reg) != base_regno | |
8765 | || newoffset != offset + 4 * i) | |
8766 | return 0; | |
8767 | } | |
8768 | ||
8769 | return 1; | |
8770 | } | |
8771 | ||
a4f6c312 | 8772 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
8773 | |
8774 | int | |
a2369ed3 | 8775 | stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
8776 | { |
8777 | int count = XVECLEN (op, 0); | |
e2c953b6 | 8778 | unsigned int src_regno; |
9ebbca7d | 8779 | rtx dest_addr; |
e2c953b6 | 8780 | unsigned int base_regno; |
9ebbca7d GK |
8781 | HOST_WIDE_INT offset; |
8782 | int i; | |
8783 | ||
8784 | /* Perform a quick check so we don't blow up below. */ | |
8785 | if (count <= 1 | |
8786 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8787 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
8788 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
8789 | return 0; | |
8790 | ||
8791 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
8792 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
8793 | ||
8794 | if (src_regno > 31 | |
e2c953b6 | 8795 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
8796 | return 0; |
8797 | ||
4d588c14 | 8798 | if (legitimate_indirect_address_p (dest_addr, 0)) |
9ebbca7d GK |
8799 | { |
8800 | offset = 0; | |
8801 | base_regno = REGNO (dest_addr); | |
8802 | if (base_regno == 0) | |
8803 | return 0; | |
8804 | } | |
76d2b81d | 8805 | else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0)) |
9ebbca7d GK |
8806 | { |
8807 | offset = INTVAL (XEXP (dest_addr, 1)); | |
8808 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
8809 | } | |
8810 | else | |
8811 | return 0; | |
8812 | ||
8813 | for (i = 0; i < count; i++) | |
8814 | { | |
8815 | rtx elt = XVECEXP (op, 0, i); | |
8816 | rtx newaddr; | |
8817 | rtx addr_reg; | |
8818 | HOST_WIDE_INT newoffset; | |
8819 | ||
8820 | if (GET_CODE (elt) != SET | |
8821 | || GET_CODE (SET_SRC (elt)) != REG | |
8822 | || GET_MODE (SET_SRC (elt)) != SImode | |
8823 | || REGNO (SET_SRC (elt)) != src_regno + i | |
8824 | || GET_CODE (SET_DEST (elt)) != MEM | |
8825 | || GET_MODE (SET_DEST (elt)) != SImode) | |
8826 | return 0; | |
8827 | newaddr = XEXP (SET_DEST (elt), 0); | |
4d588c14 | 8828 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
8829 | { |
8830 | newoffset = 0; | |
8831 | addr_reg = newaddr; | |
8832 | } | |
76d2b81d | 8833 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
8834 | { |
8835 | addr_reg = XEXP (newaddr, 0); | |
8836 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
8837 | } | |
8838 | else | |
8839 | return 0; | |
8840 | if (REGNO (addr_reg) != base_regno | |
8841 | || newoffset != offset + 4 * i) | |
8842 | return 0; | |
8843 | } | |
8844 | ||
8845 | return 1; | |
8846 | } | |
9878760c | 8847 | \f |
a4f6c312 SS |
8848 | /* A validation routine: say whether CODE, a condition code, and MODE |
8849 | match. The other alternatives either don't make sense or should | |
8850 | never be generated. */ | |
39a10a29 | 8851 | |
39a10a29 | 8852 | static void |
a2369ed3 | 8853 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 | 8854 | { |
ec8e098d PB |
8855 | if ((GET_RTX_CLASS (code) != RTX_COMPARE |
8856 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE) | |
39a10a29 GK |
8857 | || GET_MODE_CLASS (mode) != MODE_CC) |
8858 | abort (); | |
8859 | ||
8860 | /* These don't make sense. */ | |
8861 | if ((code == GT || code == LT || code == GE || code == LE) | |
8862 | && mode == CCUNSmode) | |
8863 | abort (); | |
8864 | ||
8865 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
8866 | && mode != CCUNSmode) | |
8867 | abort (); | |
8868 | ||
8869 | if (mode != CCFPmode | |
8870 | && (code == ORDERED || code == UNORDERED | |
8871 | || code == UNEQ || code == LTGT | |
8872 | || code == UNGT || code == UNLT | |
8873 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 8874 | abort (); |
39a10a29 | 8875 | |
de6c5979 | 8876 | /* These should never be generated except for |
bc9ec0e0 | 8877 | flag_finite_math_only. */ |
39a10a29 | 8878 | if (mode == CCFPmode |
ad72b533 | 8879 | && ! flag_finite_math_only |
39a10a29 GK |
8880 | && (code == LE || code == GE |
8881 | || code == UNEQ || code == LTGT | |
8882 | || code == UNGT || code == UNLT)) | |
8883 | abort (); | |
8884 | ||
8885 | /* These are invalid; the information is not there. */ | |
8886 | if (mode == CCEQmode | |
8887 | && code != EQ && code != NE) | |
8888 | abort (); | |
8889 | } | |
8890 | ||
9878760c RK |
8891 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
8892 | We only check the opcode against the mode of the CC value here. */ | |
8893 | ||
8894 | int | |
a2369ed3 | 8895 | branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
8896 | { |
8897 | enum rtx_code code = GET_CODE (op); | |
8898 | enum machine_mode cc_mode; | |
8899 | ||
ec8e098d | 8900 | if (!COMPARISON_P (op)) |
9878760c RK |
8901 | return 0; |
8902 | ||
8903 | cc_mode = GET_MODE (XEXP (op, 0)); | |
8904 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
8905 | return 0; | |
8906 | ||
39a10a29 | 8907 | validate_condition_mode (code, cc_mode); |
9878760c | 8908 | |
39a10a29 GK |
8909 | return 1; |
8910 | } | |
8911 | ||
8912 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
8913 | insn and which is true if the corresponding bit in the CC register | |
8914 | is set. */ | |
8915 | ||
8916 | int | |
a2369ed3 | 8917 | branch_positive_comparison_operator (rtx op, enum machine_mode mode) |
39a10a29 GK |
8918 | { |
8919 | enum rtx_code code; | |
8920 | ||
8daf2e65 | 8921 | if (! branch_comparison_operator (op, mode)) |
9878760c RK |
8922 | return 0; |
8923 | ||
39a10a29 GK |
8924 | code = GET_CODE (op); |
8925 | return (code == EQ || code == LT || code == GT | |
8926 | || code == LTU || code == GTU | |
8927 | || code == UNORDERED); | |
9878760c RK |
8928 | } |
8929 | ||
b7053a3f GK |
8930 | /* Return 1 if OP is a comparison operation that is valid for an scc |
8931 | insn: it must be a positive comparison. */ | |
9878760c RK |
8932 | |
8933 | int | |
a2369ed3 | 8934 | scc_comparison_operator (rtx op, enum machine_mode mode) |
9878760c | 8935 | { |
b7053a3f | 8936 | return branch_positive_comparison_operator (op, mode); |
9878760c | 8937 | } |
e0cd0770 JC |
8938 | |
8939 | int | |
a2369ed3 | 8940 | trap_comparison_operator (rtx op, enum machine_mode mode) |
e0cd0770 JC |
8941 | { |
8942 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
8943 | return 0; | |
ec8e098d | 8944 | return COMPARISON_P (op); |
e0cd0770 | 8945 | } |
dfbdccdb GK |
8946 | |
8947 | int | |
a2369ed3 | 8948 | boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dfbdccdb GK |
8949 | { |
8950 | enum rtx_code code = GET_CODE (op); | |
8951 | return (code == AND || code == IOR || code == XOR); | |
8952 | } | |
1d328b19 GK |
8953 | |
8954 | int | |
a2369ed3 | 8955 | boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
1d328b19 GK |
8956 | { |
8957 | enum rtx_code code = GET_CODE (op); | |
8958 | return (code == IOR || code == XOR); | |
8959 | } | |
50a0b056 GK |
8960 | |
8961 | int | |
a2369ed3 | 8962 | min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
50a0b056 GK |
8963 | { |
8964 | enum rtx_code code = GET_CODE (op); | |
8965 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
8966 | } | |
9878760c RK |
8967 | \f |
8968 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
8969 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 8970 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
8971 | |
8972 | int | |
a2369ed3 | 8973 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 8974 | { |
e2c953b6 DE |
8975 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
8976 | ||
8977 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 8978 | |
b1765bde | 8979 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
8980 | } |
8981 | ||
8982 | /* Similar, but for right shift. */ | |
8983 | ||
8984 | int | |
a2369ed3 | 8985 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 8986 | { |
a7653a2c | 8987 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
8988 | |
8989 | shift_mask >>= INTVAL (shiftop); | |
8990 | ||
b1765bde | 8991 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
8992 | } |
8993 | ||
c5059423 AM |
8994 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
8995 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 8996 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
8997 | |
8998 | int | |
a2369ed3 | 8999 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 9000 | { |
c5059423 AM |
9001 | if (GET_CODE (andop) == CONST_INT) |
9002 | { | |
02071907 | 9003 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 9004 | |
c5059423 | 9005 | c = INTVAL (andop); |
02071907 | 9006 | if (c == 0 || c == ~0) |
c5059423 | 9007 | return 0; |
e2c953b6 | 9008 | |
02071907 | 9009 | shift_mask = ~0; |
c5059423 AM |
9010 | shift_mask <<= INTVAL (shiftop); |
9011 | ||
b6d08ca1 | 9012 | /* Find the least significant one bit. */ |
c5059423 AM |
9013 | lsb = c & -c; |
9014 | ||
9015 | /* It must coincide with the LSB of the shift mask. */ | |
9016 | if (-lsb != shift_mask) | |
9017 | return 0; | |
e2c953b6 | 9018 | |
c5059423 AM |
9019 | /* Invert to look for the next transition (if any). */ |
9020 | c = ~c; | |
9021 | ||
9022 | /* Remove the low group of ones (originally low group of zeros). */ | |
9023 | c &= -lsb; | |
9024 | ||
9025 | /* Again find the lsb, and check we have all 1's above. */ | |
9026 | lsb = c & -c; | |
9027 | return c == -lsb; | |
9028 | } | |
9029 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9030 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9031 | { | |
02071907 AM |
9032 | HOST_WIDE_INT low, high, lsb; |
9033 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
9034 | |
9035 | low = CONST_DOUBLE_LOW (andop); | |
9036 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9037 | high = CONST_DOUBLE_HIGH (andop); | |
9038 | ||
9039 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 9040 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
9041 | return 0; |
9042 | ||
9043 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9044 | { | |
02071907 | 9045 | shift_mask_high = ~0; |
c5059423 AM |
9046 | if (INTVAL (shiftop) > 32) |
9047 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9048 | ||
9049 | lsb = high & -high; | |
9050 | ||
9051 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
9052 | return 0; | |
9053 | ||
9054 | high = ~high; | |
9055 | high &= -lsb; | |
9056 | ||
9057 | lsb = high & -high; | |
9058 | return high == -lsb; | |
9059 | } | |
9060 | ||
02071907 | 9061 | shift_mask_low = ~0; |
c5059423 AM |
9062 | shift_mask_low <<= INTVAL (shiftop); |
9063 | ||
9064 | lsb = low & -low; | |
9065 | ||
9066 | if (-lsb != shift_mask_low) | |
9067 | return 0; | |
9068 | ||
9069 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9070 | high = ~high; | |
9071 | low = ~low; | |
9072 | low &= -lsb; | |
9073 | ||
9074 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9075 | { | |
9076 | lsb = high & -high; | |
9077 | return high == -lsb; | |
9078 | } | |
9079 | ||
9080 | lsb = low & -low; | |
9081 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
9082 | } | |
9083 | else | |
9084 | return 0; | |
9085 | } | |
e2c953b6 | 9086 | |
c5059423 AM |
9087 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
9088 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 9089 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 9090 | |
c5059423 | 9091 | int |
a2369ed3 | 9092 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 9093 | { |
e2c953b6 | 9094 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 9095 | { |
02071907 | 9096 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 9097 | |
02071907 | 9098 | shift_mask = ~0; |
c5059423 AM |
9099 | shift_mask <<= INTVAL (shiftop); |
9100 | c = INTVAL (andop); | |
9101 | ||
c1207243 | 9102 | /* Find the least significant one bit. */ |
c5059423 AM |
9103 | lsb = c & -c; |
9104 | ||
9105 | /* It must be covered by the shift mask. | |
a4f6c312 | 9106 | This test also rejects c == 0. */ |
c5059423 AM |
9107 | if ((lsb & shift_mask) == 0) |
9108 | return 0; | |
9109 | ||
9110 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
9111 | return c == -lsb && lsb != 1; | |
9112 | } | |
9113 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9114 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9115 | { | |
02071907 | 9116 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
9117 | |
9118 | low = CONST_DOUBLE_LOW (andop); | |
9119 | ||
9120 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9121 | { | |
02071907 | 9122 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
9123 | |
9124 | high = CONST_DOUBLE_HIGH (andop); | |
9125 | ||
9126 | if (low == 0) | |
9127 | { | |
02071907 | 9128 | shift_mask_high = ~0; |
c5059423 AM |
9129 | if (INTVAL (shiftop) > 32) |
9130 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9131 | ||
9132 | lsb = high & -high; | |
9133 | ||
9134 | if ((lsb & shift_mask_high) == 0) | |
9135 | return 0; | |
9136 | ||
9137 | return high == -lsb; | |
9138 | } | |
9139 | if (high != ~0) | |
9140 | return 0; | |
9141 | } | |
9142 | ||
02071907 | 9143 | shift_mask_low = ~0; |
c5059423 AM |
9144 | shift_mask_low <<= INTVAL (shiftop); |
9145 | ||
9146 | lsb = low & -low; | |
9147 | ||
9148 | if ((lsb & shift_mask_low) == 0) | |
9149 | return 0; | |
9150 | ||
9151 | return low == -lsb && lsb != 1; | |
9152 | } | |
e2c953b6 | 9153 | else |
c5059423 | 9154 | return 0; |
9878760c | 9155 | } |
35068b43 | 9156 | |
11ac38b2 DE |
9157 | /* Return 1 if operands will generate a valid arguments to rlwimi |
9158 | instruction for insert with right shift in 64-bit mode. The mask may | |
9159 | not start on the first bit or stop on the last bit because wrap-around | |
9160 | effects of instruction do not correspond to semantics of RTL insn. */ | |
9161 | ||
9162 | int | |
9163 | insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) | |
9164 | { | |
9165 | if (INTVAL (startop) < 64 | |
9166 | && INTVAL (startop) > 32 | |
9167 | && (INTVAL (sizeop) + INTVAL (startop) < 64) | |
9168 | && (INTVAL (sizeop) + INTVAL (startop) > 33) | |
9169 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96) | |
9170 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64) | |
9171 | && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) | |
9172 | return 1; | |
9173 | ||
9174 | return 0; | |
9175 | } | |
9176 | ||
35068b43 | 9177 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates |
90f81f99 | 9178 | for lfq and stfq insns iff the registers are hard registers. */ |
35068b43 RK |
9179 | |
9180 | int | |
a2369ed3 | 9181 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
9182 | { |
9183 | /* We might have been passed a SUBREG. */ | |
9184 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
9185 | return 0; | |
90f81f99 AP |
9186 | |
9187 | /* We might have been passed non floating point registers. */ | |
9188 | if (!FP_REGNO_P (REGNO (reg1)) | |
9189 | || !FP_REGNO_P (REGNO (reg2))) | |
9190 | return 0; | |
35068b43 RK |
9191 | |
9192 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
9193 | } | |
9194 | ||
a4f6c312 SS |
9195 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
9196 | addr1 and addr2 must be in consecutive memory locations | |
9197 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
9198 | |
9199 | int | |
90f81f99 | 9200 | mems_ok_for_quad_peep (rtx mem1, rtx mem2) |
35068b43 | 9201 | { |
90f81f99 | 9202 | rtx addr1, addr2; |
e2c953b6 | 9203 | unsigned int reg1; |
35068b43 RK |
9204 | int offset1; |
9205 | ||
90f81f99 AP |
9206 | /* The mems cannot be volatile. */ |
9207 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
9208 | return 0; | |
9209 | ||
9210 | addr1 = XEXP (mem1, 0); | |
9211 | addr2 = XEXP (mem2, 0); | |
9212 | ||
35068b43 RK |
9213 | /* Extract an offset (if used) from the first addr. */ |
9214 | if (GET_CODE (addr1) == PLUS) | |
9215 | { | |
9216 | /* If not a REG, return zero. */ | |
9217 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
9218 | return 0; | |
9219 | else | |
9220 | { | |
9221 | reg1 = REGNO (XEXP (addr1, 0)); | |
9222 | /* The offset must be constant! */ | |
9223 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
9224 | return 0; | |
9225 | offset1 = INTVAL (XEXP (addr1, 1)); | |
9226 | } | |
9227 | } | |
9228 | else if (GET_CODE (addr1) != REG) | |
9229 | return 0; | |
9230 | else | |
9231 | { | |
9232 | reg1 = REGNO (addr1); | |
9233 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
9234 | offset1 = 0; | |
9235 | } | |
9236 | ||
a2369ed3 | 9237 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
0f6937fe AM |
9238 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same |
9239 | register as addr1. */ | |
984e25ac | 9240 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) |
0f6937fe | 9241 | return 1; |
35068b43 RK |
9242 | if (GET_CODE (addr2) != PLUS) |
9243 | return 0; | |
9244 | ||
9245 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
9246 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
9247 | return 0; | |
9248 | ||
9249 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
9250 | return 0; | |
9251 | ||
9252 | /* The offset for the second addr must be 8 more than the first addr. */ | |
9253 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
9254 | return 0; | |
9255 | ||
9256 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
9257 | instructions. */ | |
9258 | return 1; | |
9259 | } | |
9878760c RK |
9260 | \f |
9261 | /* Return the register class of a scratch register needed to copy IN into | |
9262 | or out of a register in CLASS in MODE. If it can be done directly, | |
9263 | NO_REGS is returned. */ | |
9264 | ||
9265 | enum reg_class | |
a2369ed3 | 9266 | secondary_reload_class (enum reg_class class, |
a9baceb1 GK |
9267 | enum machine_mode mode ATTRIBUTE_UNUSED, |
9268 | rtx in) | |
9878760c | 9269 | { |
5accd822 | 9270 | int regno; |
9878760c | 9271 | |
ab82a49f AP |
9272 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
9273 | #if TARGET_MACHO | |
9274 | && MACHOPIC_INDIRECT | |
9275 | #endif | |
9276 | )) | |
46fad5b7 DJ |
9277 | { |
9278 | /* We cannot copy a symbolic operand directly into anything | |
9279 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
9280 | register from BASE_REGS is needed as an intermediate | |
9281 | register. | |
9282 | ||
9283 | On Darwin, pic addresses require a load from memory, which | |
9284 | needs a base register. */ | |
9285 | if (class != BASE_REGS | |
9286 | && (GET_CODE (in) == SYMBOL_REF | |
9287 | || GET_CODE (in) == HIGH | |
9288 | || GET_CODE (in) == LABEL_REF | |
9289 | || GET_CODE (in) == CONST)) | |
9290 | return BASE_REGS; | |
9291 | } | |
e7b7998a | 9292 | |
5accd822 DE |
9293 | if (GET_CODE (in) == REG) |
9294 | { | |
9295 | regno = REGNO (in); | |
9296 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9297 | { | |
9298 | regno = true_regnum (in); | |
9299 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9300 | regno = -1; | |
9301 | } | |
9302 | } | |
9303 | else if (GET_CODE (in) == SUBREG) | |
9304 | { | |
9305 | regno = true_regnum (in); | |
9306 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9307 | regno = -1; | |
9308 | } | |
9309 | else | |
9310 | regno = -1; | |
9311 | ||
9878760c RK |
9312 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
9313 | into anything. */ | |
9314 | if (class == GENERAL_REGS || class == BASE_REGS | |
9315 | || (regno >= 0 && INT_REGNO_P (regno))) | |
9316 | return NO_REGS; | |
9317 | ||
9318 | /* Constants, memory, and FP registers can go into FP registers. */ | |
9319 | if ((regno == -1 || FP_REGNO_P (regno)) | |
9320 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
9321 | return NO_REGS; | |
9322 | ||
0ac081f6 AH |
9323 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
9324 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
9325 | && class == ALTIVEC_REGS) | |
9326 | return NO_REGS; | |
9327 | ||
9878760c RK |
9328 | /* We can copy among the CR registers. */ |
9329 | if ((class == CR_REGS || class == CR0_REGS) | |
9330 | && regno >= 0 && CR_REGNO_P (regno)) | |
9331 | return NO_REGS; | |
9332 | ||
9333 | /* Otherwise, we need GENERAL_REGS. */ | |
9334 | return GENERAL_REGS; | |
9335 | } | |
9336 | \f | |
9337 | /* Given a comparison operation, return the bit number in CCR to test. We | |
9338 | know this is a valid comparison. | |
9339 | ||
9340 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
9341 | used instead of %C, so the bits will be in different places. | |
9342 | ||
b4ac57ab | 9343 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
9344 | |
9345 | int | |
a2369ed3 | 9346 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
9347 | { |
9348 | enum rtx_code code = GET_CODE (op); | |
9349 | enum machine_mode cc_mode; | |
9350 | int cc_regnum; | |
9351 | int base_bit; | |
9ebbca7d | 9352 | rtx reg; |
9878760c | 9353 | |
ec8e098d | 9354 | if (!COMPARISON_P (op)) |
9878760c RK |
9355 | return -1; |
9356 | ||
9ebbca7d GK |
9357 | reg = XEXP (op, 0); |
9358 | ||
9359 | if (GET_CODE (reg) != REG | |
9360 | || ! CR_REGNO_P (REGNO (reg))) | |
9361 | abort (); | |
9362 | ||
9363 | cc_mode = GET_MODE (reg); | |
9364 | cc_regnum = REGNO (reg); | |
9365 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 9366 | |
39a10a29 | 9367 | validate_condition_mode (code, cc_mode); |
c5defebb | 9368 | |
b7053a3f GK |
9369 | /* When generating a sCOND operation, only positive conditions are |
9370 | allowed. */ | |
9371 | if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED | |
9372 | && code != GTU && code != LTU) | |
9373 | abort (); | |
9374 | ||
9878760c RK |
9375 | switch (code) |
9376 | { | |
9377 | case NE: | |
9378 | return scc_p ? base_bit + 3 : base_bit + 2; | |
9379 | case EQ: | |
9380 | return base_bit + 2; | |
1c882ea4 | 9381 | case GT: case GTU: case UNLE: |
9878760c | 9382 | return base_bit + 1; |
1c882ea4 | 9383 | case LT: case LTU: case UNGE: |
9878760c | 9384 | return base_bit; |
1c882ea4 GK |
9385 | case ORDERED: case UNORDERED: |
9386 | return base_bit + 3; | |
9878760c RK |
9387 | |
9388 | case GE: case GEU: | |
39a10a29 | 9389 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
9390 | unordered position. So test that bit. For integer, this is ! LT |
9391 | unless this is an scc insn. */ | |
39a10a29 | 9392 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
9393 | |
9394 | case LE: case LEU: | |
39a10a29 | 9395 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 9396 | |
9878760c RK |
9397 | default: |
9398 | abort (); | |
9399 | } | |
9400 | } | |
1ff7789b | 9401 | \f |
8d30c4ee | 9402 | /* Return the GOT register. */ |
1ff7789b MM |
9403 | |
9404 | struct rtx_def * | |
a2369ed3 | 9405 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 9406 | { |
a4f6c312 SS |
9407 | /* The second flow pass currently (June 1999) can't update |
9408 | regs_ever_live without disturbing other parts of the compiler, so | |
9409 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
9410 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
9411 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 9412 | |
8d30c4ee | 9413 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 9414 | |
1ff7789b MM |
9415 | return pic_offset_table_rtx; |
9416 | } | |
a7df97e6 | 9417 | \f |
e2500fed GK |
9418 | /* Function to init struct machine_function. |
9419 | This will be called, via a pointer variable, | |
9420 | from push_function_context. */ | |
a7df97e6 | 9421 | |
e2500fed | 9422 | static struct machine_function * |
863d938c | 9423 | rs6000_init_machine_status (void) |
a7df97e6 | 9424 | { |
e2500fed | 9425 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 9426 | } |
9878760c | 9427 | \f |
0ba1b2ff AM |
9428 | /* These macros test for integers and extract the low-order bits. */ |
9429 | #define INT_P(X) \ | |
9430 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
9431 | && GET_MODE (X) == VOIDmode) | |
9432 | ||
9433 | #define INT_LOWPART(X) \ | |
9434 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
9435 | ||
9436 | int | |
a2369ed3 | 9437 | extract_MB (rtx op) |
0ba1b2ff AM |
9438 | { |
9439 | int i; | |
9440 | unsigned long val = INT_LOWPART (op); | |
9441 | ||
9442 | /* If the high bit is zero, the value is the first 1 bit we find | |
9443 | from the left. */ | |
9444 | if ((val & 0x80000000) == 0) | |
9445 | { | |
9446 | if ((val & 0xffffffff) == 0) | |
9447 | abort (); | |
9448 | ||
9449 | i = 1; | |
9450 | while (((val <<= 1) & 0x80000000) == 0) | |
9451 | ++i; | |
9452 | return i; | |
9453 | } | |
9454 | ||
9455 | /* If the high bit is set and the low bit is not, or the mask is all | |
9456 | 1's, the value is zero. */ | |
9457 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9458 | return 0; | |
9459 | ||
9460 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9461 | from the right. */ | |
9462 | i = 31; | |
9463 | while (((val >>= 1) & 1) != 0) | |
9464 | --i; | |
9465 | ||
9466 | return i; | |
9467 | } | |
9468 | ||
9469 | int | |
a2369ed3 | 9470 | extract_ME (rtx op) |
0ba1b2ff AM |
9471 | { |
9472 | int i; | |
9473 | unsigned long val = INT_LOWPART (op); | |
9474 | ||
9475 | /* If the low bit is zero, the value is the first 1 bit we find from | |
9476 | the right. */ | |
9477 | if ((val & 1) == 0) | |
9478 | { | |
9479 | if ((val & 0xffffffff) == 0) | |
9480 | abort (); | |
9481 | ||
9482 | i = 30; | |
9483 | while (((val >>= 1) & 1) == 0) | |
9484 | --i; | |
9485 | ||
9486 | return i; | |
9487 | } | |
9488 | ||
9489 | /* If the low bit is set and the high bit is not, or the mask is all | |
9490 | 1's, the value is 31. */ | |
9491 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9492 | return 31; | |
9493 | ||
9494 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9495 | from the left. */ | |
9496 | i = 0; | |
9497 | while (((val <<= 1) & 0x80000000) != 0) | |
9498 | ++i; | |
9499 | ||
9500 | return i; | |
9501 | } | |
9502 | ||
c4501e62 JJ |
9503 | /* Locate some local-dynamic symbol still in use by this function |
9504 | so that we can print its name in some tls_ld pattern. */ | |
9505 | ||
9506 | static const char * | |
863d938c | 9507 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
9508 | { |
9509 | rtx insn; | |
9510 | ||
9511 | if (cfun->machine->some_ld_name) | |
9512 | return cfun->machine->some_ld_name; | |
9513 | ||
9514 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
9515 | if (INSN_P (insn) | |
9516 | && for_each_rtx (&PATTERN (insn), | |
9517 | rs6000_get_some_local_dynamic_name_1, 0)) | |
9518 | return cfun->machine->some_ld_name; | |
9519 | ||
9520 | abort (); | |
9521 | } | |
9522 | ||
9523 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
9524 | ||
9525 | static int | |
a2369ed3 | 9526 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
9527 | { |
9528 | rtx x = *px; | |
9529 | ||
9530 | if (GET_CODE (x) == SYMBOL_REF) | |
9531 | { | |
9532 | const char *str = XSTR (x, 0); | |
9533 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
9534 | { | |
9535 | cfun->machine->some_ld_name = str; | |
9536 | return 1; | |
9537 | } | |
9538 | } | |
9539 | ||
9540 | return 0; | |
9541 | } | |
9542 | ||
9878760c RK |
9543 | /* Print an operand. Recognize special options, documented below. */ |
9544 | ||
38c1f2d7 | 9545 | #if TARGET_ELF |
d9407988 | 9546 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 9547 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
9548 | #else |
9549 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 9550 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
9551 | #endif |
9552 | ||
9878760c | 9553 | void |
a2369ed3 | 9554 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
9555 | { |
9556 | int i; | |
a260abc9 | 9557 | HOST_WIDE_INT val; |
0ba1b2ff | 9558 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
9559 | |
9560 | switch (code) | |
9561 | { | |
a8b3aeda | 9562 | case '.': |
a85d226b RK |
9563 | /* Write out an instruction after the call which may be replaced |
9564 | with glue code by the loader. This depends on the AIX version. */ | |
9565 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
9566 | return; |
9567 | ||
81eace42 GK |
9568 | /* %a is output_address. */ |
9569 | ||
9854d9ed RK |
9570 | case 'A': |
9571 | /* If X is a constant integer whose low-order 5 bits are zero, | |
9572 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 9573 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 9574 | writes a trash instruction. */ |
9854d9ed | 9575 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 9576 | putc ('l', file); |
9854d9ed | 9577 | else |
76229ac8 | 9578 | putc ('r', file); |
9854d9ed RK |
9579 | return; |
9580 | ||
9581 | case 'b': | |
e2c953b6 DE |
9582 | /* If constant, low-order 16 bits of constant, unsigned. |
9583 | Otherwise, write normally. */ | |
9584 | if (INT_P (x)) | |
9585 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
9586 | else | |
9587 | print_operand (file, x, 0); | |
cad12a8d RK |
9588 | return; |
9589 | ||
a260abc9 DE |
9590 | case 'B': |
9591 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
9592 | for 64-bit mask direction. */ | |
296b8152 | 9593 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 9594 | return; |
a260abc9 | 9595 | |
81eace42 GK |
9596 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
9597 | output_operand. */ | |
9598 | ||
423c1189 AH |
9599 | case 'c': |
9600 | /* X is a CR register. Print the number of the GT bit of the CR. */ | |
9601 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9602 | output_operand_lossage ("invalid %%E value"); | |
9603 | else | |
9604 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); | |
9605 | return; | |
9606 | ||
9607 | case 'D': | |
9608 | /* Like 'J' but get to the GT bit. */ | |
9609 | if (GET_CODE (x) != REG) | |
9610 | abort (); | |
9611 | ||
9612 | /* Bit 1 is GT bit. */ | |
9613 | i = 4 * (REGNO (x) - CR0_REGNO) + 1; | |
9614 | ||
9615 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
9616 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9617 | return; | |
9618 | ||
9854d9ed | 9619 | case 'E': |
39a10a29 | 9620 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
9621 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
9622 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 9623 | else |
39a10a29 | 9624 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 9625 | return; |
9854d9ed RK |
9626 | |
9627 | case 'f': | |
9628 | /* X is a CR register. Print the shift count needed to move it | |
9629 | to the high-order four bits. */ | |
9630 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9631 | output_operand_lossage ("invalid %%f value"); | |
9632 | else | |
9ebbca7d | 9633 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9634 | return; |
9635 | ||
9636 | case 'F': | |
9637 | /* Similar, but print the count for the rotate in the opposite | |
9638 | direction. */ | |
9639 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9640 | output_operand_lossage ("invalid %%F value"); | |
9641 | else | |
9ebbca7d | 9642 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9643 | return; |
9644 | ||
9645 | case 'G': | |
9646 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 9647 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
9648 | if (GET_CODE (x) != CONST_INT) |
9649 | output_operand_lossage ("invalid %%G value"); | |
9650 | else if (INTVAL (x) >= 0) | |
76229ac8 | 9651 | putc ('z', file); |
9854d9ed | 9652 | else |
76229ac8 | 9653 | putc ('m', file); |
9854d9ed | 9654 | return; |
e2c953b6 | 9655 | |
9878760c | 9656 | case 'h': |
a4f6c312 SS |
9657 | /* If constant, output low-order five bits. Otherwise, write |
9658 | normally. */ | |
9878760c | 9659 | if (INT_P (x)) |
5f59ecb7 | 9660 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
9661 | else |
9662 | print_operand (file, x, 0); | |
9663 | return; | |
9664 | ||
64305719 | 9665 | case 'H': |
a4f6c312 SS |
9666 | /* If constant, output low-order six bits. Otherwise, write |
9667 | normally. */ | |
64305719 | 9668 | if (INT_P (x)) |
5f59ecb7 | 9669 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
9670 | else |
9671 | print_operand (file, x, 0); | |
9672 | return; | |
9673 | ||
9854d9ed RK |
9674 | case 'I': |
9675 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 9676 | if (INT_P (x)) |
76229ac8 | 9677 | putc ('i', file); |
9878760c RK |
9678 | return; |
9679 | ||
9854d9ed RK |
9680 | case 'j': |
9681 | /* Write the bit number in CCR for jump. */ | |
9682 | i = ccr_bit (x, 0); | |
9683 | if (i == -1) | |
9684 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 9685 | else |
9854d9ed | 9686 | fprintf (file, "%d", i); |
9878760c RK |
9687 | return; |
9688 | ||
9854d9ed RK |
9689 | case 'J': |
9690 | /* Similar, but add one for shift count in rlinm for scc and pass | |
9691 | scc flag to `ccr_bit'. */ | |
9692 | i = ccr_bit (x, 1); | |
9693 | if (i == -1) | |
9694 | output_operand_lossage ("invalid %%J code"); | |
9695 | else | |
a0466a68 RK |
9696 | /* If we want bit 31, write a shift count of zero, not 32. */ |
9697 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
9698 | return; |
9699 | ||
9854d9ed RK |
9700 | case 'k': |
9701 | /* X must be a constant. Write the 1's complement of the | |
9702 | constant. */ | |
9878760c | 9703 | if (! INT_P (x)) |
9854d9ed | 9704 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
9705 | else |
9706 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
9707 | return; |
9708 | ||
81eace42 | 9709 | case 'K': |
9ebbca7d GK |
9710 | /* X must be a symbolic constant on ELF. Write an |
9711 | expression suitable for an 'addi' that adds in the low 16 | |
9712 | bits of the MEM. */ | |
9713 | if (GET_CODE (x) != CONST) | |
9714 | { | |
9715 | print_operand_address (file, x); | |
9716 | fputs ("@l", file); | |
9717 | } | |
9718 | else | |
9719 | { | |
9720 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
9721 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
9722 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
9723 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 9724 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
9725 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
9726 | fputs ("@l", file); | |
ed8d2920 MM |
9727 | /* For GNU as, there must be a non-alphanumeric character |
9728 | between 'l' and the number. The '-' is added by | |
9729 | print_operand() already. */ | |
9730 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
9731 | fputs ("+", file); | |
9ebbca7d GK |
9732 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
9733 | } | |
81eace42 GK |
9734 | return; |
9735 | ||
9736 | /* %l is output_asm_label. */ | |
9ebbca7d | 9737 | |
9854d9ed RK |
9738 | case 'L': |
9739 | /* Write second word of DImode or DFmode reference. Works on register | |
9740 | or non-indexed memory only. */ | |
9741 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 9742 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
9743 | else if (GET_CODE (x) == MEM) |
9744 | { | |
9745 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 9746 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
9747 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
9748 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
9749 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
9750 | UNITS_PER_WORD)); | |
9854d9ed | 9751 | else |
d7624dc0 RK |
9752 | output_address (XEXP (adjust_address_nv (x, SImode, |
9753 | UNITS_PER_WORD), | |
9754 | 0)); | |
ed8908e7 | 9755 | |
ba5e43aa | 9756 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9757 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9758 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 9759 | } |
9878760c | 9760 | return; |
9854d9ed | 9761 | |
9878760c RK |
9762 | case 'm': |
9763 | /* MB value for a mask operand. */ | |
b1765bde | 9764 | if (! mask_operand (x, SImode)) |
9878760c RK |
9765 | output_operand_lossage ("invalid %%m value"); |
9766 | ||
0ba1b2ff | 9767 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
9768 | return; |
9769 | ||
9770 | case 'M': | |
9771 | /* ME value for a mask operand. */ | |
b1765bde | 9772 | if (! mask_operand (x, SImode)) |
a260abc9 | 9773 | output_operand_lossage ("invalid %%M value"); |
9878760c | 9774 | |
0ba1b2ff | 9775 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
9776 | return; |
9777 | ||
81eace42 GK |
9778 | /* %n outputs the negative of its operand. */ |
9779 | ||
9878760c RK |
9780 | case 'N': |
9781 | /* Write the number of elements in the vector times 4. */ | |
9782 | if (GET_CODE (x) != PARALLEL) | |
9783 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
9784 | else |
9785 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
9786 | return; |
9787 | ||
9788 | case 'O': | |
9789 | /* Similar, but subtract 1 first. */ | |
9790 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 9791 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
9792 | else |
9793 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
9794 | return; |
9795 | ||
9854d9ed RK |
9796 | case 'p': |
9797 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
9798 | if (! INT_P (x) | |
2bfcf297 | 9799 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
9800 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
9801 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
9802 | else |
9803 | fprintf (file, "%d", i); | |
9854d9ed RK |
9804 | return; |
9805 | ||
9878760c RK |
9806 | case 'P': |
9807 | /* The operand must be an indirect memory reference. The result | |
8bb418a3 | 9808 | is the register name. */ |
9878760c RK |
9809 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
9810 | || REGNO (XEXP (x, 0)) >= 32) | |
9811 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 | 9812 | else |
8bb418a3 | 9813 | fprintf (file, "%s", reg_names[REGNO (XEXP (x, 0))]); |
9878760c RK |
9814 | return; |
9815 | ||
dfbdccdb GK |
9816 | case 'q': |
9817 | /* This outputs the logical code corresponding to a boolean | |
9818 | expression. The expression may have one or both operands | |
39a10a29 GK |
9819 | negated (if one, only the first one). For condition register |
9820 | logical operations, it will also treat the negated | |
9821 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 9822 | { |
63bc1d05 | 9823 | const char *const *t = 0; |
dfbdccdb GK |
9824 | const char *s; |
9825 | enum rtx_code code = GET_CODE (x); | |
9826 | static const char * const tbl[3][3] = { | |
9827 | { "and", "andc", "nor" }, | |
9828 | { "or", "orc", "nand" }, | |
9829 | { "xor", "eqv", "xor" } }; | |
9830 | ||
9831 | if (code == AND) | |
9832 | t = tbl[0]; | |
9833 | else if (code == IOR) | |
9834 | t = tbl[1]; | |
9835 | else if (code == XOR) | |
9836 | t = tbl[2]; | |
9837 | else | |
9838 | output_operand_lossage ("invalid %%q value"); | |
9839 | ||
9840 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
9841 | s = t[0]; | |
9842 | else | |
9843 | { | |
9844 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
9845 | s = t[2]; | |
9846 | else | |
9847 | s = t[1]; | |
9848 | } | |
9849 | ||
9850 | fputs (s, file); | |
9851 | } | |
9852 | return; | |
9853 | ||
2c4a9cff DE |
9854 | case 'Q': |
9855 | if (TARGET_MFCRF) | |
3b6ce0af | 9856 | fputc (',', file); |
5efb1046 | 9857 | /* FALLTHRU */ |
2c4a9cff DE |
9858 | else |
9859 | return; | |
9860 | ||
9854d9ed RK |
9861 | case 'R': |
9862 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
9863 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9864 | output_operand_lossage ("invalid %%R value"); | |
9865 | else | |
9ebbca7d | 9866 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 9867 | return; |
9854d9ed RK |
9868 | |
9869 | case 's': | |
9870 | /* Low 5 bits of 32 - value */ | |
9871 | if (! INT_P (x)) | |
9872 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
9873 | else |
9874 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 9875 | return; |
9854d9ed | 9876 | |
a260abc9 | 9877 | case 'S': |
0ba1b2ff | 9878 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
9879 | CONST_INT 32-bit mask is considered sign-extended so any |
9880 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 9881 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
9882 | output_operand_lossage ("invalid %%S value"); |
9883 | ||
0ba1b2ff | 9884 | uval = INT_LOWPART (x); |
a260abc9 | 9885 | |
0ba1b2ff | 9886 | if (uval & 1) /* Clear Left */ |
a260abc9 | 9887 | { |
f099d360 GK |
9888 | #if HOST_BITS_PER_WIDE_INT > 64 |
9889 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9890 | #endif | |
0ba1b2ff | 9891 | i = 64; |
a260abc9 | 9892 | } |
0ba1b2ff | 9893 | else /* Clear Right */ |
a260abc9 | 9894 | { |
0ba1b2ff | 9895 | uval = ~uval; |
f099d360 GK |
9896 | #if HOST_BITS_PER_WIDE_INT > 64 |
9897 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9898 | #endif | |
0ba1b2ff | 9899 | i = 63; |
a260abc9 | 9900 | } |
0ba1b2ff AM |
9901 | while (uval != 0) |
9902 | --i, uval >>= 1; | |
9903 | if (i < 0) | |
9904 | abort (); | |
9905 | fprintf (file, "%d", i); | |
9906 | return; | |
a260abc9 | 9907 | |
a3170dc6 AH |
9908 | case 't': |
9909 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
9910 | if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) | |
9911 | abort (); | |
9912 | ||
9913 | /* Bit 3 is OV bit. */ | |
9914 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
9915 | ||
9916 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
9917 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9918 | return; | |
9919 | ||
cccf3bdc DE |
9920 | case 'T': |
9921 | /* Print the symbolic name of a branch target register. */ | |
9922 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
9923 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
9924 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 9925 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
9926 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
9927 | else | |
9928 | fputs ("ctr", file); | |
9929 | return; | |
9930 | ||
9854d9ed | 9931 | case 'u': |
802a0058 | 9932 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
9933 | if (! INT_P (x)) |
9934 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
9935 | else |
9936 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
9937 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
9938 | return; |
9939 | ||
802a0058 MM |
9940 | case 'v': |
9941 | /* High-order 16 bits of constant for use in signed operand. */ | |
9942 | if (! INT_P (x)) | |
9943 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 9944 | else |
134c32f6 DE |
9945 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
9946 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9947 | return; | |
802a0058 | 9948 | |
9854d9ed RK |
9949 | case 'U': |
9950 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
9951 | if (GET_CODE (x) == MEM | |
9952 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
9953 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 9954 | putc ('u', file); |
9854d9ed | 9955 | return; |
9878760c | 9956 | |
e0cd0770 JC |
9957 | case 'V': |
9958 | /* Print the trap code for this operand. */ | |
9959 | switch (GET_CODE (x)) | |
9960 | { | |
9961 | case EQ: | |
9962 | fputs ("eq", file); /* 4 */ | |
9963 | break; | |
9964 | case NE: | |
9965 | fputs ("ne", file); /* 24 */ | |
9966 | break; | |
9967 | case LT: | |
9968 | fputs ("lt", file); /* 16 */ | |
9969 | break; | |
9970 | case LE: | |
9971 | fputs ("le", file); /* 20 */ | |
9972 | break; | |
9973 | case GT: | |
9974 | fputs ("gt", file); /* 8 */ | |
9975 | break; | |
9976 | case GE: | |
9977 | fputs ("ge", file); /* 12 */ | |
9978 | break; | |
9979 | case LTU: | |
9980 | fputs ("llt", file); /* 2 */ | |
9981 | break; | |
9982 | case LEU: | |
9983 | fputs ("lle", file); /* 6 */ | |
9984 | break; | |
9985 | case GTU: | |
9986 | fputs ("lgt", file); /* 1 */ | |
9987 | break; | |
9988 | case GEU: | |
9989 | fputs ("lge", file); /* 5 */ | |
9990 | break; | |
9991 | default: | |
9992 | abort (); | |
9993 | } | |
9994 | break; | |
9995 | ||
9854d9ed RK |
9996 | case 'w': |
9997 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
9998 | normally. */ | |
9999 | if (INT_P (x)) | |
5f59ecb7 DE |
10000 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
10001 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
10002 | else |
10003 | print_operand (file, x, 0); | |
9878760c RK |
10004 | return; |
10005 | ||
9854d9ed | 10006 | case 'W': |
e2c953b6 | 10007 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
10008 | val = (GET_CODE (x) == CONST_INT |
10009 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
10010 | ||
10011 | if (val < 0) | |
10012 | i = -1; | |
9854d9ed | 10013 | else |
e2c953b6 DE |
10014 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
10015 | if ((val <<= 1) < 0) | |
10016 | break; | |
10017 | ||
10018 | #if HOST_BITS_PER_WIDE_INT == 32 | |
10019 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
10020 | i += 32; /* zero-extend high-part was all 0's */ | |
10021 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
10022 | { | |
10023 | val = CONST_DOUBLE_LOW (x); | |
10024 | ||
10025 | if (val == 0) | |
a4f6c312 | 10026 | abort (); |
e2c953b6 DE |
10027 | else if (val < 0) |
10028 | --i; | |
10029 | else | |
10030 | for ( ; i < 64; i++) | |
10031 | if ((val <<= 1) < 0) | |
10032 | break; | |
10033 | } | |
10034 | #endif | |
10035 | ||
10036 | fprintf (file, "%d", i + 1); | |
9854d9ed | 10037 | return; |
9878760c | 10038 | |
9854d9ed RK |
10039 | case 'X': |
10040 | if (GET_CODE (x) == MEM | |
4d588c14 | 10041 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 10042 | putc ('x', file); |
9854d9ed | 10043 | return; |
9878760c | 10044 | |
9854d9ed RK |
10045 | case 'Y': |
10046 | /* Like 'L', for third word of TImode */ | |
10047 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 10048 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 10049 | else if (GET_CODE (x) == MEM) |
9878760c | 10050 | { |
9854d9ed RK |
10051 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
10052 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10053 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 10054 | else |
d7624dc0 | 10055 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 10056 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10057 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10058 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
10059 | } |
10060 | return; | |
9854d9ed | 10061 | |
9878760c | 10062 | case 'z': |
b4ac57ab RS |
10063 | /* X is a SYMBOL_REF. Write out the name preceded by a |
10064 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
10065 | names. If we are configured for System V (or the embedded ABI) on |
10066 | the PowerPC, do not emit the period, since those systems do not use | |
10067 | TOCs and the like. */ | |
9878760c RK |
10068 | if (GET_CODE (x) != SYMBOL_REF) |
10069 | abort (); | |
10070 | ||
9bf6462a AP |
10071 | /* Mark the decl as referenced so that cgraph will output the function. */ |
10072 | if (SYMBOL_REF_DECL (x)) | |
10073 | mark_decl_referenced (SYMBOL_REF_DECL (x)); | |
10074 | ||
b6c9286a MM |
10075 | if (XSTR (x, 0)[0] != '.') |
10076 | { | |
10077 | switch (DEFAULT_ABI) | |
10078 | { | |
10079 | default: | |
10080 | abort (); | |
10081 | ||
10082 | case ABI_AIX: | |
10083 | putc ('.', file); | |
10084 | break; | |
10085 | ||
10086 | case ABI_V4: | |
ee890fe2 | 10087 | case ABI_DARWIN: |
b6c9286a | 10088 | break; |
b6c9286a MM |
10089 | } |
10090 | } | |
f9da97f0 AP |
10091 | /* For macho, we need to check it see if we need a stub. */ |
10092 | if (TARGET_MACHO) | |
10093 | { | |
10094 | const char *name = XSTR (x, 0); | |
a031e781 | 10095 | #if TARGET_MACHO |
3b48085e AP |
10096 | if (MACHOPIC_INDIRECT |
10097 | && machopic_classify_name (name) == MACHOPIC_UNDEFINED_FUNCTION) | |
f9da97f0 AP |
10098 | name = machopic_stub_name (name); |
10099 | #endif | |
10100 | assemble_name (file, name); | |
10101 | } | |
10102 | else if (TARGET_AIX) | |
9739c90c JJ |
10103 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
10104 | else | |
10105 | assemble_name (file, XSTR (x, 0)); | |
9878760c RK |
10106 | return; |
10107 | ||
9854d9ed RK |
10108 | case 'Z': |
10109 | /* Like 'L', for last word of TImode. */ | |
10110 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 10111 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
10112 | else if (GET_CODE (x) == MEM) |
10113 | { | |
10114 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
10115 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10116 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 10117 | else |
d7624dc0 | 10118 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 10119 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10120 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10121 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 10122 | } |
5c23c401 | 10123 | return; |
0ac081f6 | 10124 | |
a3170dc6 | 10125 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
10126 | case 'y': |
10127 | { | |
10128 | rtx tmp; | |
10129 | ||
10130 | if (GET_CODE (x) != MEM) | |
10131 | abort (); | |
10132 | ||
10133 | tmp = XEXP (x, 0); | |
10134 | ||
993f19a8 | 10135 | if (TARGET_E500) |
a3170dc6 AH |
10136 | { |
10137 | /* Handle [reg]. */ | |
10138 | if (GET_CODE (tmp) == REG) | |
10139 | { | |
10140 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
10141 | break; | |
10142 | } | |
10143 | /* Handle [reg+UIMM]. */ | |
10144 | else if (GET_CODE (tmp) == PLUS && | |
10145 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
10146 | { | |
10147 | int x; | |
10148 | ||
10149 | if (GET_CODE (XEXP (tmp, 0)) != REG) | |
10150 | abort (); | |
10151 | ||
10152 | x = INTVAL (XEXP (tmp, 1)); | |
10153 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
10154 | break; | |
10155 | } | |
10156 | ||
10157 | /* Fall through. Must be [reg+reg]. */ | |
10158 | } | |
0ac081f6 | 10159 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 10160 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
10161 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
10162 | { | |
10163 | if (REGNO (XEXP (tmp, 0)) == 0) | |
10164 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
10165 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
10166 | else | |
10167 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
10168 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
10169 | } | |
10170 | else | |
10171 | abort (); | |
10172 | break; | |
10173 | } | |
9854d9ed | 10174 | |
9878760c RK |
10175 | case 0: |
10176 | if (GET_CODE (x) == REG) | |
10177 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
10178 | else if (GET_CODE (x) == MEM) | |
10179 | { | |
10180 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
10181 | know the width from the mode. */ | |
10182 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
10183 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
10184 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10185 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
10186 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
10187 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10188 | else |
a54d04b7 | 10189 | output_address (XEXP (x, 0)); |
9878760c RK |
10190 | } |
10191 | else | |
a54d04b7 | 10192 | output_addr_const (file, x); |
a85d226b | 10193 | return; |
9878760c | 10194 | |
c4501e62 JJ |
10195 | case '&': |
10196 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
10197 | return; | |
10198 | ||
9878760c RK |
10199 | default: |
10200 | output_operand_lossage ("invalid %%xn code"); | |
10201 | } | |
10202 | } | |
10203 | \f | |
10204 | /* Print the address of an operand. */ | |
10205 | ||
10206 | void | |
a2369ed3 | 10207 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
10208 | { |
10209 | if (GET_CODE (x) == REG) | |
4697a36c | 10210 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
10211 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
10212 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
10213 | { |
10214 | output_addr_const (file, x); | |
ba5e43aa | 10215 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10216 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10217 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 10218 | else if (TARGET_TOC) |
a4f6c312 | 10219 | abort (); |
9878760c RK |
10220 | } |
10221 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
10222 | { | |
10223 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
10224 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
10225 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 10226 | else |
4697a36c MM |
10227 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
10228 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
10229 | } |
10230 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
10231 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
10232 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
10233 | #if TARGET_ELF |
10234 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
10235 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
10236 | { |
10237 | output_addr_const (file, XEXP (x, 1)); | |
10238 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10239 | } | |
c859cda6 DJ |
10240 | #endif |
10241 | #if TARGET_MACHO | |
10242 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
10243 | && CONSTANT_P (XEXP (x, 1))) | |
10244 | { | |
10245 | fprintf (file, "lo16("); | |
10246 | output_addr_const (file, XEXP (x, 1)); | |
10247 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10248 | } | |
3cb999d8 | 10249 | #endif |
4d588c14 | 10250 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 10251 | { |
2bfcf297 | 10252 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 10253 | { |
2bfcf297 DB |
10254 | rtx contains_minus = XEXP (x, 1); |
10255 | rtx minus, symref; | |
10256 | const char *name; | |
9ebbca7d GK |
10257 | |
10258 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 10259 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
10260 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
10261 | contains_minus = XEXP (contains_minus, 0); | |
10262 | ||
2bfcf297 DB |
10263 | minus = XEXP (contains_minus, 0); |
10264 | symref = XEXP (minus, 0); | |
10265 | XEXP (contains_minus, 0) = symref; | |
10266 | if (TARGET_ELF) | |
10267 | { | |
10268 | char *newname; | |
10269 | ||
10270 | name = XSTR (symref, 0); | |
10271 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
10272 | strcpy (newname, name); | |
10273 | strcat (newname, "@toc"); | |
10274 | XSTR (symref, 0) = newname; | |
10275 | } | |
10276 | output_addr_const (file, XEXP (x, 1)); | |
10277 | if (TARGET_ELF) | |
10278 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
10279 | XEXP (contains_minus, 0) = minus; |
10280 | } | |
10281 | else | |
10282 | output_addr_const (file, XEXP (x, 1)); | |
10283 | ||
10284 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
10285 | } | |
9878760c RK |
10286 | else |
10287 | abort (); | |
10288 | } | |
10289 | \f | |
88cad84b | 10290 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
10291 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
10292 | is defined. It also needs to handle DI-mode objects on 64-bit | |
10293 | targets. */ | |
10294 | ||
10295 | static bool | |
a2369ed3 | 10296 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
10297 | { |
10298 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
10299 | /* Special handling for SI values. */ | |
10300 | if (size == 4 && aligned_p) | |
10301 | { | |
a2369ed3 | 10302 | extern int in_toc_section (void); |
301d03af RS |
10303 | static int recurse = 0; |
10304 | ||
10305 | /* For -mrelocatable, we mark all addresses that need to be fixed up | |
10306 | in the .fixup section. */ | |
10307 | if (TARGET_RELOCATABLE | |
10308 | && !in_toc_section () | |
10309 | && !in_text_section () | |
642af3be | 10310 | && !in_unlikely_text_section () |
301d03af RS |
10311 | && !recurse |
10312 | && GET_CODE (x) != CONST_INT | |
10313 | && GET_CODE (x) != CONST_DOUBLE | |
10314 | && CONSTANT_P (x)) | |
10315 | { | |
10316 | char buf[256]; | |
10317 | ||
10318 | recurse = 1; | |
10319 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
10320 | fixuplabelno++; | |
10321 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
10322 | fprintf (asm_out_file, "\t.long\t("); | |
10323 | output_addr_const (asm_out_file, x); | |
10324 | fprintf (asm_out_file, ")@fixup\n"); | |
10325 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
10326 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
10327 | fprintf (asm_out_file, "\t.long\t"); | |
10328 | assemble_name (asm_out_file, buf); | |
10329 | fprintf (asm_out_file, "\n\t.previous\n"); | |
10330 | recurse = 0; | |
10331 | return true; | |
10332 | } | |
10333 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
10334 | address into the address of the descriptor, not the function | |
10335 | itself. */ | |
10336 | else if (GET_CODE (x) == SYMBOL_REF | |
10337 | && XSTR (x, 0)[0] == '.' | |
10338 | && DEFAULT_ABI == ABI_AIX) | |
10339 | { | |
10340 | const char *name = XSTR (x, 0); | |
10341 | while (*name == '.') | |
10342 | name++; | |
10343 | ||
10344 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
10345 | return true; | |
10346 | } | |
10347 | } | |
10348 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
10349 | return default_assemble_integer (x, size, aligned_p); | |
10350 | } | |
93638d7a AM |
10351 | |
10352 | #ifdef HAVE_GAS_HIDDEN | |
10353 | /* Emit an assembler directive to set symbol visibility for DECL to | |
10354 | VISIBILITY_TYPE. */ | |
10355 | ||
5add3202 | 10356 | static void |
a2369ed3 | 10357 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 10358 | { |
93638d7a AM |
10359 | /* Functions need to have their entry point symbol visibility set as |
10360 | well as their descriptor symbol visibility. */ | |
10361 | if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL) | |
10362 | { | |
25fdb4dc RH |
10363 | static const char * const visibility_types[] = { |
10364 | NULL, "internal", "hidden", "protected" | |
10365 | }; | |
10366 | ||
10367 | const char *name, *type; | |
93638d7a AM |
10368 | |
10369 | name = ((* targetm.strip_name_encoding) | |
10370 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 10371 | type = visibility_types[vis]; |
93638d7a | 10372 | |
25fdb4dc RH |
10373 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
10374 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 10375 | } |
25fdb4dc RH |
10376 | else |
10377 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
10378 | } |
10379 | #endif | |
301d03af | 10380 | \f |
39a10a29 | 10381 | enum rtx_code |
a2369ed3 | 10382 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
10383 | { |
10384 | /* Reversal of FP compares takes care -- an ordered compare | |
10385 | becomes an unordered compare and vice versa. */ | |
bc9ec0e0 GK |
10386 | if (mode == CCFPmode |
10387 | && (!flag_finite_math_only | |
10388 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
10389 | || code == UNEQ || code == LTGT)) | |
bab6226b | 10390 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 10391 | else |
bab6226b | 10392 | return reverse_condition (code); |
39a10a29 GK |
10393 | } |
10394 | ||
39a10a29 GK |
10395 | /* Generate a compare for CODE. Return a brand-new rtx that |
10396 | represents the result of the compare. */ | |
a4f6c312 | 10397 | |
39a10a29 | 10398 | static rtx |
a2369ed3 | 10399 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
10400 | { |
10401 | enum machine_mode comp_mode; | |
10402 | rtx compare_result; | |
10403 | ||
10404 | if (rs6000_compare_fp_p) | |
10405 | comp_mode = CCFPmode; | |
10406 | else if (code == GTU || code == LTU | |
10407 | || code == GEU || code == LEU) | |
10408 | comp_mode = CCUNSmode; | |
10409 | else | |
10410 | comp_mode = CCmode; | |
10411 | ||
10412 | /* First, the compare. */ | |
10413 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
10414 | |
10415 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
10416 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
10417 | && rs6000_compare_fp_p) | |
a3170dc6 AH |
10418 | { |
10419 | rtx cmp, or1, or2, or_result, compare_result2; | |
10420 | ||
423c1189 AH |
10421 | /* Note: The E500 comparison instructions set the GT bit (x + |
10422 | 1), on success. This explains the mess. */ | |
10423 | ||
a3170dc6 AH |
10424 | switch (code) |
10425 | { | |
423c1189 | 10426 | case EQ: case UNEQ: case NE: case LTGT: |
bc9ec0e0 | 10427 | cmp = flag_finite_math_only |
a3170dc6 AH |
10428 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, |
10429 | rs6000_compare_op1) | |
10430 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
10431 | rs6000_compare_op1); | |
10432 | break; | |
423c1189 | 10433 | case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: |
bc9ec0e0 | 10434 | cmp = flag_finite_math_only |
a3170dc6 AH |
10435 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, |
10436 | rs6000_compare_op1) | |
10437 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
10438 | rs6000_compare_op1); | |
10439 | break; | |
423c1189 | 10440 | case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: |
bc9ec0e0 | 10441 | cmp = flag_finite_math_only |
a3170dc6 AH |
10442 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, |
10443 | rs6000_compare_op1) | |
10444 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
10445 | rs6000_compare_op1); | |
10446 | break; | |
10447 | default: | |
10448 | abort (); | |
10449 | } | |
10450 | ||
10451 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
10452 | if (code == LE || code == GE || code == LEU || code == GEU) | |
10453 | { | |
a3170dc6 AH |
10454 | emit_insn (cmp); |
10455 | ||
10456 | switch (code) | |
10457 | { | |
10458 | case LE: code = LT; break; | |
10459 | case GE: code = GT; break; | |
10460 | case LEU: code = LT; break; | |
10461 | case GEU: code = GT; break; | |
10462 | default: abort (); | |
10463 | } | |
10464 | ||
10465 | or1 = gen_reg_rtx (SImode); | |
10466 | or2 = gen_reg_rtx (SImode); | |
10467 | or_result = gen_reg_rtx (CCEQmode); | |
10468 | compare_result2 = gen_reg_rtx (CCFPmode); | |
10469 | ||
10470 | /* Do the EQ. */ | |
bc9ec0e0 | 10471 | cmp = flag_finite_math_only |
a3170dc6 AH |
10472 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, |
10473 | rs6000_compare_op1) | |
10474 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
10475 | rs6000_compare_op1); | |
10476 | emit_insn (cmp); | |
10477 | ||
423c1189 AH |
10478 | or1 = gen_rtx_GT (SImode, compare_result, const0_rtx); |
10479 | or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx); | |
a3170dc6 AH |
10480 | |
10481 | /* OR them together. */ | |
10482 | cmp = gen_rtx_SET (VOIDmode, or_result, | |
10483 | gen_rtx_COMPARE (CCEQmode, | |
10484 | gen_rtx_IOR (SImode, or1, or2), | |
10485 | const_true_rtx)); | |
10486 | compare_result = or_result; | |
10487 | code = EQ; | |
10488 | } | |
10489 | else | |
10490 | { | |
a3170dc6 | 10491 | if (code == NE || code == LTGT) |
a3170dc6 | 10492 | code = NE; |
423c1189 AH |
10493 | else |
10494 | code = EQ; | |
a3170dc6 AH |
10495 | } |
10496 | ||
10497 | emit_insn (cmp); | |
10498 | } | |
10499 | else | |
10500 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
10501 | gen_rtx_COMPARE (comp_mode, | |
10502 | rs6000_compare_op0, | |
10503 | rs6000_compare_op1))); | |
39a10a29 | 10504 | |
ca5adc63 | 10505 | /* Some kinds of FP comparisons need an OR operation; |
bc9ec0e0 | 10506 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 10507 | if (rs6000_compare_fp_p |
bc9ec0e0 | 10508 | && ! flag_finite_math_only |
993f19a8 | 10509 | && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) |
39a10a29 GK |
10510 | && (code == LE || code == GE |
10511 | || code == UNEQ || code == LTGT | |
10512 | || code == UNGT || code == UNLT)) | |
10513 | { | |
10514 | enum rtx_code or1, or2; | |
10515 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
10516 | rtx or_result = gen_reg_rtx (CCEQmode); | |
10517 | ||
10518 | switch (code) | |
10519 | { | |
10520 | case LE: or1 = LT; or2 = EQ; break; | |
10521 | case GE: or1 = GT; or2 = EQ; break; | |
10522 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
10523 | case LTGT: or1 = LT; or2 = GT; break; | |
10524 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
10525 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
10526 | default: abort (); | |
10527 | } | |
10528 | validate_condition_mode (or1, comp_mode); | |
10529 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
10530 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
10531 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
10532 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
10533 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
10534 | const_true_rtx); | |
10535 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
10536 | ||
10537 | compare_result = or_result; | |
10538 | code = EQ; | |
10539 | } | |
10540 | ||
10541 | validate_condition_mode (code, GET_MODE (compare_result)); | |
10542 | ||
1c563bed | 10543 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
10544 | } |
10545 | ||
10546 | ||
10547 | /* Emit the RTL for an sCOND pattern. */ | |
10548 | ||
10549 | void | |
a2369ed3 | 10550 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
10551 | { |
10552 | rtx condition_rtx; | |
10553 | enum machine_mode op_mode; | |
b7053a3f | 10554 | enum rtx_code cond_code; |
39a10a29 GK |
10555 | |
10556 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
10557 | cond_code = GET_CODE (condition_rtx); |
10558 | ||
423c1189 AH |
10559 | if (TARGET_E500 && rs6000_compare_fp_p |
10560 | && !TARGET_FPRS && TARGET_HARD_FLOAT) | |
10561 | { | |
10562 | rtx t; | |
10563 | ||
10564 | PUT_MODE (condition_rtx, SImode); | |
10565 | t = XEXP (condition_rtx, 0); | |
10566 | ||
10567 | if (cond_code != NE && cond_code != EQ) | |
10568 | abort (); | |
10569 | ||
10570 | if (cond_code == NE) | |
10571 | emit_insn (gen_e500_flip_gt_bit (t, t)); | |
10572 | ||
10573 | emit_insn (gen_move_from_CR_gt_bit (result, t)); | |
10574 | return; | |
10575 | } | |
10576 | ||
b7053a3f GK |
10577 | if (cond_code == NE |
10578 | || cond_code == GE || cond_code == LE | |
10579 | || cond_code == GEU || cond_code == LEU | |
10580 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
10581 | { | |
10582 | rtx not_result = gen_reg_rtx (CCEQmode); | |
10583 | rtx not_op, rev_cond_rtx; | |
10584 | enum machine_mode cc_mode; | |
10585 | ||
10586 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); | |
10587 | ||
1c563bed | 10588 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 10589 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
10590 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
10591 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
10592 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
10593 | } | |
39a10a29 GK |
10594 | |
10595 | op_mode = GET_MODE (rs6000_compare_op0); | |
10596 | if (op_mode == VOIDmode) | |
10597 | op_mode = GET_MODE (rs6000_compare_op1); | |
10598 | ||
10599 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10600 | { | |
10601 | PUT_MODE (condition_rtx, DImode); | |
10602 | convert_move (result, condition_rtx, 0); | |
10603 | } | |
10604 | else | |
10605 | { | |
10606 | PUT_MODE (condition_rtx, SImode); | |
10607 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
10608 | } | |
10609 | } | |
10610 | ||
39a10a29 GK |
10611 | /* Emit a branch of kind CODE to location LOC. */ |
10612 | ||
10613 | void | |
a2369ed3 | 10614 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
10615 | { |
10616 | rtx condition_rtx, loc_ref; | |
10617 | ||
10618 | condition_rtx = rs6000_generate_compare (code); | |
10619 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
10620 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
10621 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
10622 | loc_ref, pc_rtx))); | |
10623 | } | |
10624 | ||
12a4e8c5 GK |
10625 | /* Return the string to output a conditional branch to LABEL, which is |
10626 | the operand number of the label, or -1 if the branch is really a | |
10627 | conditional return. | |
10628 | ||
10629 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
10630 | condition code register and its mode specifies what kind of | |
10631 | comparison we made. | |
10632 | ||
a0ab749a | 10633 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
10634 | |
10635 | INSN is the insn. */ | |
10636 | ||
10637 | char * | |
a2369ed3 | 10638 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
10639 | { |
10640 | static char string[64]; | |
10641 | enum rtx_code code = GET_CODE (op); | |
10642 | rtx cc_reg = XEXP (op, 0); | |
10643 | enum machine_mode mode = GET_MODE (cc_reg); | |
10644 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 10645 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
10646 | int really_reversed = reversed ^ need_longbranch; |
10647 | char *s = string; | |
10648 | const char *ccode; | |
10649 | const char *pred; | |
10650 | rtx note; | |
10651 | ||
39a10a29 GK |
10652 | validate_condition_mode (code, mode); |
10653 | ||
10654 | /* Work out which way this really branches. We could use | |
10655 | reverse_condition_maybe_unordered here always but this | |
10656 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 10657 | if (really_reversed) |
de40e1df DJ |
10658 | { |
10659 | /* Reversal of FP compares takes care -- an ordered compare | |
10660 | becomes an unordered compare and vice versa. */ | |
10661 | if (mode == CCFPmode) | |
10662 | code = reverse_condition_maybe_unordered (code); | |
10663 | else | |
10664 | code = reverse_condition (code); | |
10665 | } | |
12a4e8c5 | 10666 | |
993f19a8 | 10667 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
10668 | { |
10669 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
10670 | to the GT bit. */ | |
10671 | if (code == EQ) | |
10672 | /* Opposite of GT. */ | |
a3170dc6 | 10673 | code = GT; |
423c1189 AH |
10674 | else if (code == NE) |
10675 | code = UNLE; | |
a3170dc6 AH |
10676 | else |
10677 | abort (); | |
10678 | } | |
10679 | ||
39a10a29 | 10680 | switch (code) |
12a4e8c5 GK |
10681 | { |
10682 | /* Not all of these are actually distinct opcodes, but | |
10683 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
10684 | case NE: case LTGT: |
10685 | ccode = "ne"; break; | |
10686 | case EQ: case UNEQ: | |
10687 | ccode = "eq"; break; | |
10688 | case GE: case GEU: | |
10689 | ccode = "ge"; break; | |
10690 | case GT: case GTU: case UNGT: | |
10691 | ccode = "gt"; break; | |
10692 | case LE: case LEU: | |
10693 | ccode = "le"; break; | |
10694 | case LT: case LTU: case UNLT: | |
10695 | ccode = "lt"; break; | |
12a4e8c5 GK |
10696 | case UNORDERED: ccode = "un"; break; |
10697 | case ORDERED: ccode = "nu"; break; | |
10698 | case UNGE: ccode = "nl"; break; | |
10699 | case UNLE: ccode = "ng"; break; | |
10700 | default: | |
a4f6c312 | 10701 | abort (); |
12a4e8c5 GK |
10702 | } |
10703 | ||
94a54f47 GK |
10704 | /* Maybe we have a guess as to how likely the branch is. |
10705 | The old mnemonics don't have a way to specify this information. */ | |
f4857b9b | 10706 | pred = ""; |
12a4e8c5 GK |
10707 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
10708 | if (note != NULL_RTX) | |
10709 | { | |
10710 | /* PROB is the difference from 50%. */ | |
10711 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
10712 | |
10713 | /* Only hint for highly probable/improbable branches on newer | |
10714 | cpus as static prediction overrides processor dynamic | |
10715 | prediction. For older cpus we may as well always hint, but | |
10716 | assume not taken for branches that are very close to 50% as a | |
10717 | mispredicted taken branch is more expensive than a | |
10718 | mispredicted not-taken branch. */ | |
ec507f2d | 10719 | if (rs6000_always_hint |
f4857b9b AM |
10720 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) |
10721 | { | |
10722 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
10723 | && ((prob > 0) ^ need_longbranch)) | |
7f3d8013 | 10724 | pred = "+"; |
f4857b9b AM |
10725 | else |
10726 | pred = "-"; | |
10727 | } | |
12a4e8c5 | 10728 | } |
12a4e8c5 GK |
10729 | |
10730 | if (label == NULL) | |
94a54f47 | 10731 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 10732 | else |
94a54f47 | 10733 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 10734 | |
37c67319 | 10735 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 10736 | Assume they'd only be the first character.... */ |
37c67319 GK |
10737 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
10738 | *s++ = '%'; | |
94a54f47 | 10739 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
10740 | |
10741 | if (label != NULL) | |
10742 | { | |
10743 | /* If the branch distance was too far, we may have to use an | |
10744 | unconditional branch to go the distance. */ | |
10745 | if (need_longbranch) | |
44518ddd | 10746 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
10747 | else |
10748 | s += sprintf (s, ",%s", label); | |
10749 | } | |
10750 | ||
10751 | return string; | |
10752 | } | |
50a0b056 | 10753 | |
423c1189 AH |
10754 | /* Return the string to flip the GT bit on a CR. */ |
10755 | char * | |
10756 | output_e500_flip_gt_bit (rtx dst, rtx src) | |
10757 | { | |
10758 | static char string[64]; | |
10759 | int a, b; | |
10760 | ||
10761 | if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst)) | |
10762 | || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src))) | |
10763 | abort (); | |
10764 | ||
10765 | /* GT bit. */ | |
10766 | a = 4 * (REGNO (dst) - CR0_REGNO) + 1; | |
10767 | b = 4 * (REGNO (src) - CR0_REGNO) + 1; | |
10768 | ||
10769 | sprintf (string, "crnot %d,%d", a, b); | |
10770 | return string; | |
10771 | } | |
10772 | ||
50a0b056 GK |
10773 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the |
10774 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
10775 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 10776 | |
50a0b056 | 10777 | int |
a2369ed3 | 10778 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
10779 | { |
10780 | enum rtx_code code = GET_CODE (op); | |
10781 | rtx op0 = rs6000_compare_op0; | |
10782 | rtx op1 = rs6000_compare_op1; | |
10783 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
10784 | enum machine_mode compare_mode = GET_MODE (op0); |
10785 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 GK |
10786 | rtx temp; |
10787 | ||
a3c9585f | 10788 | /* These modes should always match. */ |
a3170dc6 AH |
10789 | if (GET_MODE (op1) != compare_mode |
10790 | /* In the isel case however, we can use a compare immediate, so | |
10791 | op1 may be a small constant. */ | |
10792 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 10793 | return 0; |
178c3eff | 10794 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 10795 | return 0; |
178c3eff | 10796 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
10797 | return 0; |
10798 | ||
50a0b056 | 10799 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 10800 | if it's too slow.... */ |
50a0b056 | 10801 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
10802 | { |
10803 | if (TARGET_ISEL) | |
10804 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
10805 | return 0; | |
10806 | } | |
fef98bf2 AH |
10807 | else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS |
10808 | && GET_MODE_CLASS (compare_mode) == MODE_FLOAT) | |
10809 | return 0; | |
50a0b056 GK |
10810 | |
10811 | /* Eliminate half of the comparisons by switching operands, this | |
10812 | makes the remaining code simpler. */ | |
10813 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 10814 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
10815 | { |
10816 | code = reverse_condition_maybe_unordered (code); | |
10817 | temp = true_cond; | |
10818 | true_cond = false_cond; | |
10819 | false_cond = temp; | |
10820 | } | |
10821 | ||
10822 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
10823 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 10824 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 GK |
10825 | return 0; |
10826 | ||
10827 | if (GET_CODE (op1) == CONST_DOUBLE) | |
10828 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
10829 | ||
b6d08ca1 | 10830 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
10831 | a subtract, then comparing against zero. Unfortunately, |
10832 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 10833 | know that the operand is finite and the comparison |
50a0b056 | 10834 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 10835 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 10836 | && code != GT && code != UNGE |
045572c7 | 10837 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
10838 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
10839 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
10840 | || (! rtx_equal_p (op0, true_cond) | |
10841 | && ! rtx_equal_p (op1, true_cond)))) | |
10842 | return 0; | |
10843 | /* At this point we know we can use fsel. */ | |
10844 | ||
10845 | /* Reduce the comparison to a comparison against zero. */ | |
3148ad6d | 10846 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 10847 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 10848 | gen_rtx_MINUS (compare_mode, op0, op1))); |
50a0b056 | 10849 | op0 = temp; |
3148ad6d | 10850 | op1 = CONST0_RTX (compare_mode); |
50a0b056 GK |
10851 | |
10852 | /* If we don't care about NaNs we can reduce some of the comparisons | |
10853 | down to faster ones. */ | |
bc9ec0e0 | 10854 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
10855 | switch (code) |
10856 | { | |
10857 | case GT: | |
10858 | code = LE; | |
10859 | temp = true_cond; | |
10860 | true_cond = false_cond; | |
10861 | false_cond = temp; | |
10862 | break; | |
10863 | case UNGE: | |
10864 | code = GE; | |
10865 | break; | |
10866 | case UNEQ: | |
10867 | code = EQ; | |
10868 | break; | |
10869 | default: | |
10870 | break; | |
10871 | } | |
10872 | ||
10873 | /* Now, reduce everything down to a GE. */ | |
10874 | switch (code) | |
10875 | { | |
10876 | case GE: | |
10877 | break; | |
10878 | ||
10879 | case LE: | |
3148ad6d DJ |
10880 | temp = gen_reg_rtx (compare_mode); |
10881 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10882 | op0 = temp; |
10883 | break; | |
10884 | ||
10885 | case ORDERED: | |
3148ad6d DJ |
10886 | temp = gen_reg_rtx (compare_mode); |
10887 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
10888 | op0 = temp; |
10889 | break; | |
10890 | ||
10891 | case EQ: | |
3148ad6d | 10892 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 10893 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
10894 | gen_rtx_NEG (compare_mode, |
10895 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
10896 | op0 = temp; |
10897 | break; | |
10898 | ||
10899 | case UNGE: | |
bc9ec0e0 | 10900 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 10901 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 10902 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 10903 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10904 | gen_rtx_GE (VOIDmode, |
10905 | op0, op1), | |
10906 | true_cond, false_cond))); | |
bc9ec0e0 GK |
10907 | false_cond = true_cond; |
10908 | true_cond = temp; | |
50a0b056 | 10909 | |
3148ad6d DJ |
10910 | temp = gen_reg_rtx (compare_mode); |
10911 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10912 | op0 = temp; |
10913 | break; | |
10914 | ||
10915 | case GT: | |
bc9ec0e0 | 10916 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 10917 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 10918 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 10919 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10920 | gen_rtx_GE (VOIDmode, |
10921 | op0, op1), | |
10922 | true_cond, false_cond))); | |
bc9ec0e0 GK |
10923 | true_cond = false_cond; |
10924 | false_cond = temp; | |
50a0b056 | 10925 | |
3148ad6d DJ |
10926 | temp = gen_reg_rtx (compare_mode); |
10927 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10928 | op0 = temp; |
10929 | break; | |
10930 | ||
10931 | default: | |
10932 | abort (); | |
10933 | } | |
10934 | ||
10935 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 10936 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10937 | gen_rtx_GE (VOIDmode, |
10938 | op0, op1), | |
10939 | true_cond, false_cond))); | |
10940 | return 1; | |
10941 | } | |
10942 | ||
a3170dc6 AH |
10943 | /* Same as above, but for ints (isel). */ |
10944 | ||
10945 | static int | |
a2369ed3 | 10946 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
10947 | { |
10948 | rtx condition_rtx, cr; | |
10949 | ||
10950 | /* All isel implementations thus far are 32-bits. */ | |
10951 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
10952 | return 0; | |
10953 | ||
10954 | /* We still have to do the compare, because isel doesn't do a | |
10955 | compare, it just looks at the CRx bits set by a previous compare | |
10956 | instruction. */ | |
10957 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
10958 | cr = XEXP (condition_rtx, 0); | |
10959 | ||
10960 | if (GET_MODE (cr) == CCmode) | |
10961 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
10962 | true_cond, false_cond, cr)); | |
10963 | else | |
10964 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
10965 | true_cond, false_cond, cr)); | |
10966 | ||
10967 | return 1; | |
10968 | } | |
10969 | ||
10970 | const char * | |
a2369ed3 | 10971 | output_isel (rtx *operands) |
a3170dc6 AH |
10972 | { |
10973 | enum rtx_code code; | |
10974 | ||
10975 | code = GET_CODE (operands[1]); | |
10976 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
10977 | { | |
10978 | PUT_CODE (operands[1], reverse_condition (code)); | |
10979 | return "isel %0,%3,%2,%j1"; | |
10980 | } | |
10981 | else | |
10982 | return "isel %0,%2,%3,%j1"; | |
10983 | } | |
10984 | ||
50a0b056 | 10985 | void |
a2369ed3 | 10986 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
10987 | { |
10988 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 10989 | enum rtx_code c; |
50a0b056 | 10990 | rtx target; |
5dc8d536 AH |
10991 | |
10992 | if (code == SMAX || code == SMIN) | |
10993 | c = GE; | |
10994 | else | |
10995 | c = GEU; | |
10996 | ||
50a0b056 | 10997 | if (code == SMAX || code == UMAX) |
5dc8d536 | 10998 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
10999 | op0, op1, mode, 0); |
11000 | else | |
5dc8d536 | 11001 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
11002 | op1, op0, mode, 0); |
11003 | if (target == NULL_RTX) | |
11004 | abort (); | |
11005 | if (target != dest) | |
11006 | emit_move_insn (dest, target); | |
11007 | } | |
46c07df8 | 11008 | |
a9baceb1 GK |
11009 | /* Emit instructions to move SRC to DST. Called by splitters for |
11010 | multi-register moves. It will emit at most one instruction for | |
11011 | each register that is accessed; that is, it won't emit li/lis pairs | |
11012 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
11013 | register. */ | |
46c07df8 | 11014 | |
46c07df8 | 11015 | void |
a9baceb1 | 11016 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 11017 | { |
a9baceb1 GK |
11018 | /* The register number of the first register being moved. */ |
11019 | int reg; | |
11020 | /* The mode that is to be moved. */ | |
11021 | enum machine_mode mode; | |
11022 | /* The mode that the move is being done in, and its size. */ | |
11023 | enum machine_mode reg_mode; | |
11024 | int reg_mode_size; | |
11025 | /* The number of registers that will be moved. */ | |
11026 | int nregs; | |
11027 | ||
11028 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
11029 | mode = GET_MODE (dst); | |
11030 | nregs = HARD_REGNO_NREGS (reg, mode); | |
11031 | if (FP_REGNO_P (reg)) | |
11032 | reg_mode = DFmode; | |
11033 | else if (ALTIVEC_REGNO_P (reg)) | |
11034 | reg_mode = V16QImode; | |
11035 | else | |
11036 | reg_mode = word_mode; | |
11037 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
46c07df8 | 11038 | |
a9baceb1 GK |
11039 | if (reg_mode_size * nregs != GET_MODE_SIZE (mode)) |
11040 | abort (); | |
11041 | ||
11042 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) | |
11043 | { | |
11044 | /* Move register range backwards, if we might have destructive | |
11045 | overlap. */ | |
11046 | int i; | |
11047 | for (i = nregs - 1; i >= 0; i--) | |
11048 | emit_insn (gen_rtx_SET (VOIDmode, | |
11049 | simplify_gen_subreg (reg_mode, dst, mode, | |
11050 | i * reg_mode_size), | |
11051 | simplify_gen_subreg (reg_mode, src, mode, | |
11052 | i * reg_mode_size))); | |
11053 | } | |
46c07df8 HP |
11054 | else |
11055 | { | |
a9baceb1 GK |
11056 | int i; |
11057 | int j = -1; | |
11058 | bool used_update = false; | |
46c07df8 | 11059 | |
a9baceb1 | 11060 | if (GET_CODE (src) == MEM && INT_REGNO_P (reg)) |
46c07df8 HP |
11061 | { |
11062 | rtx breg; | |
3a1f863f | 11063 | |
a9baceb1 GK |
11064 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
11065 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
11066 | { |
11067 | rtx delta_rtx; | |
a9baceb1 GK |
11068 | breg = XEXP (XEXP (src, 0), 0); |
11069 | delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC | |
11070 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
11071 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))); | |
11072 | emit_insn (TARGET_32BIT | |
11073 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11074 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11075 | src = gen_rtx_MEM (mode, breg); |
11076 | } | |
11077 | ||
11078 | /* We have now address involving an base register only. | |
11079 | If we use one of the registers to address memory, | |
11080 | we have change that register last. */ | |
11081 | ||
11082 | breg = (GET_CODE (XEXP (src, 0)) == PLUS | |
11083 | ? XEXP (XEXP (src, 0), 0) | |
11084 | : XEXP (src, 0)); | |
11085 | ||
11086 | if (!REG_P (breg)) | |
11087 | abort(); | |
11088 | ||
11089 | if (REGNO (breg) >= REGNO (dst) | |
11090 | && REGNO (breg) < REGNO (dst) + nregs) | |
11091 | j = REGNO (breg) - REGNO (dst); | |
46c07df8 HP |
11092 | } |
11093 | ||
a9baceb1 | 11094 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
11095 | { |
11096 | rtx breg; | |
11097 | ||
a9baceb1 GK |
11098 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11099 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
11100 | { |
11101 | rtx delta_rtx; | |
a9baceb1 GK |
11102 | breg = XEXP (XEXP (dst, 0), 0); |
11103 | delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC | |
11104 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
11105 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))); | |
3a1f863f DE |
11106 | |
11107 | /* We have to update the breg before doing the store. | |
11108 | Use store with update, if available. */ | |
11109 | ||
11110 | if (TARGET_UPDATE) | |
11111 | { | |
a9baceb1 GK |
11112 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
11113 | emit_insn (TARGET_32BIT | |
11114 | ? gen_movsi_update (breg, breg, delta_rtx, nsrc) | |
11115 | : gen_movdi_update (breg, breg, delta_rtx, nsrc)); | |
11116 | used_update = true; | |
3a1f863f DE |
11117 | } |
11118 | else | |
a9baceb1 GK |
11119 | emit_insn (TARGET_32BIT |
11120 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11121 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11122 | dst = gen_rtx_MEM (mode, breg); |
11123 | } | |
11124 | } | |
11125 | ||
46c07df8 | 11126 | for (i = 0; i < nregs; i++) |
3a1f863f DE |
11127 | { |
11128 | /* Calculate index to next subword. */ | |
11129 | ++j; | |
11130 | if (j == nregs) | |
11131 | j = 0; | |
46c07df8 | 11132 | |
a9baceb1 GK |
11133 | /* If compiler already emited move of first word by |
11134 | store with update, no need to do anything. */ | |
3a1f863f | 11135 | if (j == 0 && used_update) |
a9baceb1 GK |
11136 | continue; |
11137 | ||
11138 | emit_insn (gen_rtx_SET (VOIDmode, | |
11139 | simplify_gen_subreg (reg_mode, dst, mode, | |
11140 | j * reg_mode_size), | |
11141 | simplify_gen_subreg (reg_mode, src, mode, | |
11142 | j * reg_mode_size))); | |
3a1f863f | 11143 | } |
46c07df8 HP |
11144 | } |
11145 | } | |
11146 | ||
12a4e8c5 | 11147 | \f |
a4f6c312 SS |
11148 | /* This page contains routines that are used to determine what the |
11149 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 11150 | |
a4f6c312 SS |
11151 | /* Return the first fixed-point register that is required to be |
11152 | saved. 32 if none. */ | |
9878760c RK |
11153 | |
11154 | int | |
863d938c | 11155 | first_reg_to_save (void) |
9878760c RK |
11156 | { |
11157 | int first_reg; | |
11158 | ||
11159 | /* Find lowest numbered live register. */ | |
11160 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
11161 | if (regs_ever_live[first_reg] |
11162 | && (! call_used_regs[first_reg] | |
1db02437 | 11163 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11164 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
b4db40bf JJ |
11165 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) |
11166 | || (TARGET_TOC && TARGET_MINIMAL_TOC))))) | |
9878760c RK |
11167 | break; |
11168 | ||
ee890fe2 | 11169 | #if TARGET_MACHO |
93638d7a AM |
11170 | if (flag_pic |
11171 | && current_function_uses_pic_offset_table | |
11172 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 11173 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
11174 | #endif |
11175 | ||
9878760c RK |
11176 | return first_reg; |
11177 | } | |
11178 | ||
11179 | /* Similar, for FP regs. */ | |
11180 | ||
11181 | int | |
863d938c | 11182 | first_fp_reg_to_save (void) |
9878760c RK |
11183 | { |
11184 | int first_reg; | |
11185 | ||
11186 | /* Find lowest numbered live register. */ | |
11187 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
11188 | if (regs_ever_live[first_reg]) | |
11189 | break; | |
11190 | ||
11191 | return first_reg; | |
11192 | } | |
00b960c7 AH |
11193 | |
11194 | /* Similar, for AltiVec regs. */ | |
11195 | ||
11196 | static int | |
863d938c | 11197 | first_altivec_reg_to_save (void) |
00b960c7 AH |
11198 | { |
11199 | int i; | |
11200 | ||
11201 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
11202 | if (! TARGET_ALTIVEC_ABI) | |
11203 | return LAST_ALTIVEC_REGNO + 1; | |
11204 | ||
11205 | /* Find lowest numbered live register. */ | |
11206 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
11207 | if (regs_ever_live[i]) | |
11208 | break; | |
11209 | ||
11210 | return i; | |
11211 | } | |
11212 | ||
11213 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
11214 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
11215 | the 32-bit word is 0. */ | |
11216 | ||
11217 | static unsigned int | |
863d938c | 11218 | compute_vrsave_mask (void) |
00b960c7 AH |
11219 | { |
11220 | unsigned int i, mask = 0; | |
11221 | ||
11222 | /* First, find out if we use _any_ altivec registers. */ | |
11223 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
11224 | if (regs_ever_live[i]) | |
11225 | mask |= ALTIVEC_REG_BIT (i); | |
11226 | ||
11227 | if (mask == 0) | |
11228 | return mask; | |
11229 | ||
00b960c7 AH |
11230 | /* Next, remove the argument registers from the set. These must |
11231 | be in the VRSAVE mask set by the caller, so we don't need to add | |
11232 | them in again. More importantly, the mask we compute here is | |
11233 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
11234 | wish the argument registers to die. */ | |
a6cf80f2 | 11235 | for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
11236 | mask &= ~ALTIVEC_REG_BIT (i); |
11237 | ||
11238 | /* Similarly, remove the return value from the set. */ | |
11239 | { | |
11240 | bool yes = false; | |
11241 | diddle_return_value (is_altivec_return_reg, &yes); | |
11242 | if (yes) | |
11243 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
11244 | } | |
11245 | ||
11246 | return mask; | |
11247 | } | |
11248 | ||
11249 | static void | |
a2369ed3 | 11250 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
11251 | { |
11252 | bool *yes = (bool *) xyes; | |
11253 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
11254 | *yes = true; | |
11255 | } | |
11256 | ||
4697a36c MM |
11257 | \f |
11258 | /* Calculate the stack information for the current function. This is | |
11259 | complicated by having two separate calling sequences, the AIX calling | |
11260 | sequence and the V.4 calling sequence. | |
11261 | ||
592696dd | 11262 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 11263 | 32-bit 64-bit |
4697a36c | 11264 | SP----> +---------------------------------------+ |
a260abc9 | 11265 | | back chain to caller | 0 0 |
4697a36c | 11266 | +---------------------------------------+ |
a260abc9 | 11267 | | saved CR | 4 8 (8-11) |
4697a36c | 11268 | +---------------------------------------+ |
a260abc9 | 11269 | | saved LR | 8 16 |
4697a36c | 11270 | +---------------------------------------+ |
a260abc9 | 11271 | | reserved for compilers | 12 24 |
4697a36c | 11272 | +---------------------------------------+ |
a260abc9 | 11273 | | reserved for binders | 16 32 |
4697a36c | 11274 | +---------------------------------------+ |
a260abc9 | 11275 | | saved TOC pointer | 20 40 |
4697a36c | 11276 | +---------------------------------------+ |
a260abc9 | 11277 | | Parameter save area (P) | 24 48 |
4697a36c | 11278 | +---------------------------------------+ |
a260abc9 | 11279 | | Alloca space (A) | 24+P etc. |
802a0058 | 11280 | +---------------------------------------+ |
a7df97e6 | 11281 | | Local variable space (L) | 24+P+A |
4697a36c | 11282 | +---------------------------------------+ |
a7df97e6 | 11283 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 11284 | +---------------------------------------+ |
00b960c7 AH |
11285 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
11286 | +---------------------------------------+ | |
11287 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
11288 | +---------------------------------------+ | |
11289 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 11290 | +---------------------------------------+ |
00b960c7 AH |
11291 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
11292 | +---------------------------------------+ | |
11293 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
11294 | +---------------------------------------+ |
11295 | old SP->| back chain to caller's caller | | |
11296 | +---------------------------------------+ | |
11297 | ||
5376a30c KR |
11298 | The required alignment for AIX configurations is two words (i.e., 8 |
11299 | or 16 bytes). | |
11300 | ||
11301 | ||
4697a36c MM |
11302 | V.4 stack frames look like: |
11303 | ||
11304 | SP----> +---------------------------------------+ | |
11305 | | back chain to caller | 0 | |
11306 | +---------------------------------------+ | |
5eb387b8 | 11307 | | caller's saved LR | 4 |
4697a36c MM |
11308 | +---------------------------------------+ |
11309 | | Parameter save area (P) | 8 | |
11310 | +---------------------------------------+ | |
a7df97e6 MM |
11311 | | Alloca space (A) | 8+P |
11312 | +---------------------------------------+ | |
11313 | | Varargs save area (V) | 8+P+A | |
11314 | +---------------------------------------+ | |
11315 | | Local variable space (L) | 8+P+A+V | |
11316 | +---------------------------------------+ | |
11317 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 11318 | +---------------------------------------+ |
00b960c7 AH |
11319 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
11320 | +---------------------------------------+ | |
11321 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
11322 | +---------------------------------------+ | |
11323 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
11324 | +---------------------------------------+ | |
a3170dc6 AH |
11325 | | SPE: area for 64-bit GP registers | |
11326 | +---------------------------------------+ | |
11327 | | SPE alignment padding | | |
11328 | +---------------------------------------+ | |
00b960c7 | 11329 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
a7df97e6 | 11330 | +---------------------------------------+ |
00b960c7 | 11331 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 11332 | +---------------------------------------+ |
00b960c7 | 11333 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
11334 | +---------------------------------------+ |
11335 | old SP->| back chain to caller's caller | | |
11336 | +---------------------------------------+ | |
b6c9286a | 11337 | |
5376a30c KR |
11338 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
11339 | given. (But note below and in sysv4.h that we require only 8 and | |
11340 | may round up the size of our stack frame anyways. The historical | |
11341 | reason is early versions of powerpc-linux which didn't properly | |
11342 | align the stack at program startup. A happy side-effect is that | |
11343 | -mno-eabi libraries can be used with -meabi programs.) | |
11344 | ||
50d440bc | 11345 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
11346 | the stack alignment requirements may differ. If -mno-eabi is not |
11347 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
11348 | given, the required alignment is 16 bytes. (But see V.4 comment | |
11349 | above.) */ | |
4697a36c | 11350 | |
61b2fbe7 MM |
11351 | #ifndef ABI_STACK_BOUNDARY |
11352 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
11353 | #endif | |
11354 | ||
d1d0c603 | 11355 | static rs6000_stack_t * |
863d938c | 11356 | rs6000_stack_info (void) |
4697a36c MM |
11357 | { |
11358 | static rs6000_stack_t info, zero_info; | |
11359 | rs6000_stack_t *info_ptr = &info; | |
327e5343 | 11360 | int reg_size = TARGET_32BIT ? 4 : 8; |
83720594 | 11361 | int ehrd_size; |
44688022 | 11362 | HOST_WIDE_INT non_fixed_size; |
4697a36c | 11363 | |
a4f6c312 | 11364 | /* Zero all fields portably. */ |
4697a36c MM |
11365 | info = zero_info; |
11366 | ||
c19de7aa AH |
11367 | if (TARGET_SPE) |
11368 | { | |
11369 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f AH |
11370 | if (cfun->machine->insn_chain_scanned_p == 0) |
11371 | { | |
11372 | cfun->machine->insn_chain_scanned_p = 1; | |
11373 | info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p (); | |
11374 | } | |
c19de7aa AH |
11375 | } |
11376 | ||
a4f6c312 | 11377 | /* Select which calling sequence. */ |
178274da | 11378 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 11379 | |
a4f6c312 | 11380 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 11381 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
1db02437 | 11382 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 11383 | even if it currently looks like we won't. */ |
2bfcf297 | 11384 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
11385 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
11386 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
11387 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
11388 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
11389 | else |
11390 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 11391 | |
a3170dc6 AH |
11392 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
11393 | Ideally we should save the entire 64-bits only when the upper | |
11394 | half is used in SIMD instructions. Since we only record | |
11395 | registers live (not the size they are used in), this proves | |
11396 | difficult because we'd have to traverse the instruction chain at | |
11397 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
11398 | so we opt to save the GPRs in 64-bits always if but one register |
11399 | gets used in 64-bits. Otherwise, all the registers in the frame | |
11400 | get saved in 32-bits. | |
a3170dc6 | 11401 | |
c19de7aa | 11402 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 11403 | traditional GP save area will be empty. */ |
c19de7aa | 11404 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11405 | info_ptr->gp_size = 0; |
11406 | ||
4697a36c MM |
11407 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
11408 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
11409 | ||
00b960c7 AH |
11410 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
11411 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
11412 | - info_ptr->first_altivec_reg_save); | |
11413 | ||
592696dd | 11414 | /* Does this function call anything? */ |
71f123ca FS |
11415 | info_ptr->calls_p = (! current_function_is_leaf |
11416 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 11417 | |
a4f6c312 | 11418 | /* Determine if we need to save the link register. */ |
71f123ca | 11419 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
11420 | || (DEFAULT_ABI == ABI_AIX |
11421 | && current_function_profile | |
11422 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
11423 | #ifdef TARGET_RELOCATABLE |
11424 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
11425 | #endif | |
11426 | || (info_ptr->first_fp_reg_save != 64 | |
11427 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 11428 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 11429 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
11430 | || (DEFAULT_ABI == ABI_DARWIN |
11431 | && flag_pic | |
11432 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
11433 | || info_ptr->calls_p) |
11434 | { | |
11435 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 11436 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
11437 | } |
11438 | ||
9ebbca7d GK |
11439 | /* Determine if we need to save the condition code registers. */ |
11440 | if (regs_ever_live[CR2_REGNO] | |
11441 | || regs_ever_live[CR3_REGNO] | |
11442 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
11443 | { |
11444 | info_ptr->cr_save_p = 1; | |
178274da | 11445 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
11446 | info_ptr->cr_size = reg_size; |
11447 | } | |
11448 | ||
83720594 RH |
11449 | /* If the current function calls __builtin_eh_return, then we need |
11450 | to allocate stack space for registers that will hold data for | |
11451 | the exception handler. */ | |
11452 | if (current_function_calls_eh_return) | |
11453 | { | |
11454 | unsigned int i; | |
11455 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
11456 | continue; | |
a3170dc6 AH |
11457 | |
11458 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
11459 | ehrd_size = i * (TARGET_SPE_ABI |
11460 | && info_ptr->spe_64bit_regs_used != 0 | |
11461 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
11462 | } |
11463 | else | |
11464 | ehrd_size = 0; | |
11465 | ||
592696dd | 11466 | /* Determine various sizes. */ |
4697a36c MM |
11467 | info_ptr->reg_size = reg_size; |
11468 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
11469 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 11470 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 | 11471 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
03e007d7 | 11472 | TARGET_ALTIVEC ? 16 : 8); |
00b960c7 | 11473 | |
c19de7aa | 11474 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11475 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
11476 | else | |
11477 | info_ptr->spe_gp_size = 0; | |
11478 | ||
4d774ff8 HP |
11479 | if (TARGET_ALTIVEC_ABI) |
11480 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 11481 | else |
4d774ff8 HP |
11482 | info_ptr->vrsave_mask = 0; |
11483 | ||
11484 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
11485 | info_ptr->vrsave_size = 4; | |
11486 | else | |
11487 | info_ptr->vrsave_size = 0; | |
b6c9286a | 11488 | |
592696dd | 11489 | /* Calculate the offsets. */ |
178274da | 11490 | switch (DEFAULT_ABI) |
4697a36c | 11491 | { |
b6c9286a | 11492 | case ABI_NONE: |
24d304eb | 11493 | default: |
b6c9286a MM |
11494 | abort (); |
11495 | ||
11496 | case ABI_AIX: | |
ee890fe2 | 11497 | case ABI_DARWIN: |
b6c9286a MM |
11498 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
11499 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
11500 | |
11501 | if (TARGET_ALTIVEC_ABI) | |
11502 | { | |
11503 | info_ptr->vrsave_save_offset | |
11504 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
11505 | ||
11506 | /* Align stack so vector save area is on a quadword boundary. */ | |
11507 | if (info_ptr->altivec_size != 0) | |
11508 | info_ptr->altivec_padding_size | |
11509 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
11510 | else | |
11511 | info_ptr->altivec_padding_size = 0; | |
11512 | ||
11513 | info_ptr->altivec_save_offset | |
11514 | = info_ptr->vrsave_save_offset | |
11515 | - info_ptr->altivec_padding_size | |
11516 | - info_ptr->altivec_size; | |
11517 | ||
11518 | /* Adjust for AltiVec case. */ | |
11519 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
11520 | } | |
11521 | else | |
11522 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
11523 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
11524 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
11525 | break; |
11526 | ||
11527 | case ABI_V4: | |
b6c9286a MM |
11528 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
11529 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 11530 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 11531 | |
c19de7aa | 11532 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11533 | { |
11534 | /* Align stack so SPE GPR save area is aligned on a | |
11535 | double-word boundary. */ | |
11536 | if (info_ptr->spe_gp_size != 0) | |
11537 | info_ptr->spe_padding_size | |
11538 | = 8 - (-info_ptr->cr_save_offset % 8); | |
11539 | else | |
11540 | info_ptr->spe_padding_size = 0; | |
11541 | ||
11542 | info_ptr->spe_gp_save_offset | |
11543 | = info_ptr->cr_save_offset | |
11544 | - info_ptr->spe_padding_size | |
11545 | - info_ptr->spe_gp_size; | |
11546 | ||
11547 | /* Adjust for SPE case. */ | |
11548 | info_ptr->toc_save_offset | |
11549 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
11550 | } | |
11551 | else if (TARGET_ALTIVEC_ABI) | |
00b960c7 AH |
11552 | { |
11553 | info_ptr->vrsave_save_offset | |
11554 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
11555 | ||
11556 | /* Align stack so vector save area is on a quadword boundary. */ | |
11557 | if (info_ptr->altivec_size != 0) | |
11558 | info_ptr->altivec_padding_size | |
11559 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
11560 | else | |
11561 | info_ptr->altivec_padding_size = 0; | |
11562 | ||
11563 | info_ptr->altivec_save_offset | |
11564 | = info_ptr->vrsave_save_offset | |
11565 | - info_ptr->altivec_padding_size | |
11566 | - info_ptr->altivec_size; | |
11567 | ||
11568 | /* Adjust for AltiVec case. */ | |
11569 | info_ptr->toc_save_offset | |
11570 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
11571 | } | |
11572 | else | |
11573 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 11574 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
11575 | info_ptr->lr_save_offset = reg_size; |
11576 | break; | |
4697a36c MM |
11577 | } |
11578 | ||
00b960c7 AH |
11579 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
11580 | + info_ptr->gp_size | |
11581 | + info_ptr->altivec_size | |
11582 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
11583 | + info_ptr->spe_gp_size |
11584 | + info_ptr->spe_padding_size | |
00b960c7 AH |
11585 | + ehrd_size |
11586 | + info_ptr->cr_size | |
11587 | + info_ptr->lr_size | |
11588 | + info_ptr->vrsave_size | |
11589 | + info_ptr->toc_size, | |
11590 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
11591 | ? 16 : 8); | |
11592 | ||
44688022 | 11593 | non_fixed_size = (info_ptr->vars_size |
ff381587 | 11594 | + info_ptr->parm_size |
ff381587 | 11595 | + info_ptr->save_size |
44688022 | 11596 | + info_ptr->varargs_size); |
ff381587 | 11597 | |
44688022 AM |
11598 | info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, |
11599 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
11600 | |
11601 | /* Determine if we need to allocate any stack frame: | |
11602 | ||
a4f6c312 SS |
11603 | For AIX we need to push the stack if a frame pointer is needed |
11604 | (because the stack might be dynamically adjusted), if we are | |
11605 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
11606 | and local variables are more than the space needed to save all | |
11607 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
11608 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 11609 | |
a4f6c312 SS |
11610 | For V.4 we don't have the stack cushion that AIX uses, but assume |
11611 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
11612 | |
11613 | if (info_ptr->calls_p) | |
11614 | info_ptr->push_p = 1; | |
11615 | ||
178274da | 11616 | else if (DEFAULT_ABI == ABI_V4) |
44688022 | 11617 | info_ptr->push_p = non_fixed_size != 0; |
ff381587 | 11618 | |
178274da AM |
11619 | else if (frame_pointer_needed) |
11620 | info_ptr->push_p = 1; | |
11621 | ||
11622 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
11623 | info_ptr->push_p = 1; | |
11624 | ||
ff381587 | 11625 | else |
44688022 | 11626 | info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); |
ff381587 | 11627 | |
a4f6c312 | 11628 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 11629 | if (info_ptr->fp_size == 0) |
4697a36c MM |
11630 | info_ptr->fp_save_offset = 0; |
11631 | ||
8dda1a21 | 11632 | if (info_ptr->gp_size == 0) |
4697a36c MM |
11633 | info_ptr->gp_save_offset = 0; |
11634 | ||
00b960c7 AH |
11635 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
11636 | info_ptr->altivec_save_offset = 0; | |
11637 | ||
11638 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
11639 | info_ptr->vrsave_save_offset = 0; | |
11640 | ||
c19de7aa AH |
11641 | if (! TARGET_SPE_ABI |
11642 | || info_ptr->spe_64bit_regs_used == 0 | |
11643 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
11644 | info_ptr->spe_gp_save_offset = 0; |
11645 | ||
c81fc13e | 11646 | if (! info_ptr->lr_save_p) |
4697a36c MM |
11647 | info_ptr->lr_save_offset = 0; |
11648 | ||
c81fc13e | 11649 | if (! info_ptr->cr_save_p) |
4697a36c MM |
11650 | info_ptr->cr_save_offset = 0; |
11651 | ||
c81fc13e | 11652 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
11653 | info_ptr->toc_save_offset = 0; |
11654 | ||
4697a36c MM |
11655 | return info_ptr; |
11656 | } | |
11657 | ||
c19de7aa AH |
11658 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
11659 | mode. */ | |
11660 | ||
11661 | static bool | |
863d938c | 11662 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
11663 | { |
11664 | rtx insns, insn; | |
11665 | ||
11666 | /* Functions that save and restore all the call-saved registers will | |
11667 | need to save/restore the registers in 64-bits. */ | |
11668 | if (current_function_calls_eh_return | |
11669 | || current_function_calls_setjmp | |
11670 | || current_function_has_nonlocal_goto) | |
11671 | return true; | |
11672 | ||
11673 | insns = get_insns (); | |
11674 | ||
11675 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
11676 | { | |
11677 | if (INSN_P (insn)) | |
11678 | { | |
11679 | rtx i; | |
11680 | ||
11681 | i = PATTERN (insn); | |
11682 | if (GET_CODE (i) == SET | |
11683 | && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i)))) | |
11684 | return true; | |
11685 | } | |
11686 | } | |
11687 | ||
11688 | return false; | |
11689 | } | |
11690 | ||
d1d0c603 | 11691 | static void |
a2369ed3 | 11692 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 11693 | { |
d330fd93 | 11694 | const char *abi_string; |
24d304eb | 11695 | |
c81fc13e | 11696 | if (! info) |
4697a36c MM |
11697 | info = rs6000_stack_info (); |
11698 | ||
11699 | fprintf (stderr, "\nStack information for function %s:\n", | |
11700 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
11701 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
11702 | : "<unknown>")); | |
11703 | ||
24d304eb RK |
11704 | switch (info->abi) |
11705 | { | |
b6c9286a MM |
11706 | default: abi_string = "Unknown"; break; |
11707 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 11708 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 11709 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 11710 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
11711 | } |
11712 | ||
11713 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
11714 | ||
00b960c7 AH |
11715 | if (TARGET_ALTIVEC_ABI) |
11716 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
11717 | ||
a3170dc6 AH |
11718 | if (TARGET_SPE_ABI) |
11719 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
11720 | ||
4697a36c MM |
11721 | if (info->first_gp_reg_save != 32) |
11722 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
11723 | ||
11724 | if (info->first_fp_reg_save != 64) | |
11725 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 11726 | |
00b960c7 AH |
11727 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
11728 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
11729 | info->first_altivec_reg_save); | |
11730 | ||
4697a36c MM |
11731 | if (info->lr_save_p) |
11732 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 11733 | |
4697a36c MM |
11734 | if (info->cr_save_p) |
11735 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
11736 | ||
b6c9286a MM |
11737 | if (info->toc_save_p) |
11738 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
11739 | ||
00b960c7 AH |
11740 | if (info->vrsave_mask) |
11741 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
11742 | ||
4697a36c MM |
11743 | if (info->push_p) |
11744 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
11745 | ||
11746 | if (info->calls_p) | |
11747 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
11748 | ||
4697a36c MM |
11749 | if (info->gp_save_offset) |
11750 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
11751 | ||
11752 | if (info->fp_save_offset) | |
11753 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
11754 | ||
00b960c7 AH |
11755 | if (info->altivec_save_offset) |
11756 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
11757 | info->altivec_save_offset); | |
11758 | ||
a3170dc6 AH |
11759 | if (info->spe_gp_save_offset) |
11760 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
11761 | info->spe_gp_save_offset); | |
11762 | ||
00b960c7 AH |
11763 | if (info->vrsave_save_offset) |
11764 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
11765 | info->vrsave_save_offset); | |
11766 | ||
4697a36c MM |
11767 | if (info->lr_save_offset) |
11768 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
11769 | ||
11770 | if (info->cr_save_offset) | |
11771 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
11772 | ||
b6c9286a MM |
11773 | if (info->toc_save_offset) |
11774 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
11775 | ||
4697a36c MM |
11776 | if (info->varargs_save_offset) |
11777 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
11778 | ||
11779 | if (info->total_size) | |
d1d0c603 JJ |
11780 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
11781 | info->total_size); | |
4697a36c MM |
11782 | |
11783 | if (info->varargs_size) | |
11784 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
11785 | ||
11786 | if (info->vars_size) | |
d1d0c603 JJ |
11787 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
11788 | info->vars_size); | |
4697a36c MM |
11789 | |
11790 | if (info->parm_size) | |
11791 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
11792 | ||
11793 | if (info->fixed_size) | |
11794 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
11795 | ||
11796 | if (info->gp_size) | |
11797 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
11798 | ||
a3170dc6 AH |
11799 | if (info->spe_gp_size) |
11800 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
11801 | ||
4697a36c MM |
11802 | if (info->fp_size) |
11803 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
11804 | ||
00b960c7 AH |
11805 | if (info->altivec_size) |
11806 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
11807 | ||
11808 | if (info->vrsave_size) | |
11809 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
11810 | ||
11811 | if (info->altivec_padding_size) | |
11812 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
11813 | info->altivec_padding_size); | |
11814 | ||
a3170dc6 AH |
11815 | if (info->spe_padding_size) |
11816 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
11817 | info->spe_padding_size); | |
11818 | ||
a4f6c312 | 11819 | if (info->lr_size) |
ed947a96 | 11820 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 11821 | |
4697a36c MM |
11822 | if (info->cr_size) |
11823 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
11824 | ||
a4f6c312 | 11825 | if (info->toc_size) |
b6c9286a MM |
11826 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
11827 | ||
4697a36c MM |
11828 | if (info->save_size) |
11829 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
11830 | ||
11831 | if (info->reg_size != 4) | |
11832 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
11833 | ||
11834 | fprintf (stderr, "\n"); | |
9878760c | 11835 | } |
71f123ca FS |
11836 | |
11837 | rtx | |
a2369ed3 | 11838 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 11839 | { |
a4f6c312 SS |
11840 | /* Currently we don't optimize very well between prolog and body |
11841 | code and for PIC code the code can be actually quite bad, so | |
11842 | don't try to be too clever here. */ | |
f1384257 | 11843 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
11844 | { |
11845 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
11846 | |
11847 | return | |
11848 | gen_rtx_MEM | |
11849 | (Pmode, | |
11850 | memory_address | |
11851 | (Pmode, | |
11852 | plus_constant (copy_to_reg | |
11853 | (gen_rtx_MEM (Pmode, | |
11854 | memory_address (Pmode, frame))), | |
11855 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
11856 | } |
11857 | ||
8c29550d | 11858 | cfun->machine->ra_need_lr = 1; |
9e2f7ec7 | 11859 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
11860 | } |
11861 | ||
5e1bf043 DJ |
11862 | /* Say whether a function is a candidate for sibcall handling or not. |
11863 | We do not allow indirect calls to be optimized into sibling calls. | |
11864 | Also, we can't do it if there are any vector parameters; there's | |
11865 | nowhere to put the VRsave code so it works; note that functions with | |
11866 | vector parameters are required to have a prototype, so the argument | |
11867 | type info must be available here. (The tail recursion case can work | |
11868 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 11869 | static bool |
a2369ed3 | 11870 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
11871 | { |
11872 | tree type; | |
4977bab6 | 11873 | if (decl) |
5e1bf043 DJ |
11874 | { |
11875 | if (TARGET_ALTIVEC_VRSAVE) | |
11876 | { | |
4977bab6 | 11877 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
11878 | type; type = TREE_CHAIN (type)) |
11879 | { | |
c15b529f | 11880 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 11881 | return false; |
5e1bf043 DJ |
11882 | } |
11883 | } | |
11884 | if (DEFAULT_ABI == ABI_DARWIN | |
4977bab6 | 11885 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 11886 | { |
4977bab6 | 11887 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
11888 | |
11889 | if (!lookup_attribute ("longcall", attr_list) | |
11890 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 11891 | return true; |
2bcc50d0 | 11892 | } |
5e1bf043 | 11893 | } |
4977bab6 | 11894 | return false; |
5e1bf043 DJ |
11895 | } |
11896 | ||
71f123ca | 11897 | static int |
863d938c | 11898 | rs6000_ra_ever_killed (void) |
71f123ca FS |
11899 | { |
11900 | rtx top; | |
5e1bf043 DJ |
11901 | rtx reg; |
11902 | rtx insn; | |
71f123ca | 11903 | |
dd292d0a | 11904 | if (current_function_is_thunk) |
71f123ca | 11905 | return 0; |
eb0424da | 11906 | |
36f7e964 AH |
11907 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
11908 | but this should not force saving and restoring in the | |
11909 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 11910 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 11911 | |
5e1bf043 DJ |
11912 | /* Also, the prologue can generate a store into LR that |
11913 | doesn't really count, like this: | |
36f7e964 | 11914 | |
5e1bf043 DJ |
11915 | move LR->R0 |
11916 | bcl to set PIC register | |
11917 | move LR->R31 | |
11918 | move R0->LR | |
36f7e964 AH |
11919 | |
11920 | When we're called from the epilogue, we need to avoid counting | |
11921 | this as a store. */ | |
5e1bf043 | 11922 | |
71f123ca FS |
11923 | push_topmost_sequence (); |
11924 | top = get_insns (); | |
11925 | pop_topmost_sequence (); | |
5e1bf043 | 11926 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 11927 | |
5e1bf043 DJ |
11928 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
11929 | { | |
11930 | if (INSN_P (insn)) | |
11931 | { | |
11932 | if (FIND_REG_INC_NOTE (insn, reg)) | |
11933 | return 1; | |
11934 | else if (GET_CODE (insn) == CALL_INSN | |
c15b529f | 11935 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 11936 | return 1; |
36f7e964 AH |
11937 | else if (set_of (reg, insn) != NULL_RTX |
11938 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
11939 | return 1; |
11940 | } | |
11941 | } | |
11942 | return 0; | |
71f123ca | 11943 | } |
4697a36c | 11944 | \f |
8cd8f856 GK |
11945 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
11946 | static void | |
a2369ed3 | 11947 | rs6000_maybe_dead (rtx insn) |
8cd8f856 GK |
11948 | { |
11949 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
11950 | const0_rtx, | |
11951 | REG_NOTES (insn)); | |
11952 | } | |
11953 | ||
9ebbca7d | 11954 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 11955 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 11956 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
11957 | |
11958 | void | |
a2369ed3 | 11959 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 11960 | { |
027fbf43 | 11961 | rtx dest, insn; |
1db02437 | 11962 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 11963 | |
20b71b17 AM |
11964 | if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
11965 | { | |
11966 | rtx temp = (fromprolog | |
11967 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
11968 | : gen_reg_rtx (Pmode)); | |
027fbf43 JJ |
11969 | insn = emit_insn (gen_load_toc_v4_pic_si (temp)); |
11970 | if (fromprolog) | |
11971 | rs6000_maybe_dead (insn); | |
11972 | insn = emit_move_insn (dest, temp); | |
11973 | if (fromprolog) | |
11974 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
11975 | } |
11976 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
11977 | { | |
11978 | char buf[30]; | |
11979 | rtx tempLR = (fromprolog | |
11980 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
11981 | : gen_reg_rtx (Pmode)); | |
11982 | rtx temp0 = (fromprolog | |
11983 | ? gen_rtx_REG (Pmode, 0) | |
11984 | : gen_reg_rtx (Pmode)); | |
11985 | rtx symF; | |
11986 | ||
11987 | /* possibly create the toc section */ | |
11988 | if (! toc_initialized) | |
38c1f2d7 | 11989 | { |
20b71b17 AM |
11990 | toc_section (); |
11991 | function_section (current_function_decl); | |
38c1f2d7 | 11992 | } |
9ebbca7d | 11993 | |
20b71b17 AM |
11994 | if (fromprolog) |
11995 | { | |
11996 | rtx symL; | |
38c1f2d7 | 11997 | |
20b71b17 AM |
11998 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
11999 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 12000 | |
20b71b17 AM |
12001 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
12002 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12003 | ||
12004 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
12005 | symF))); | |
12006 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
12007 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
12008 | symL, | |
12009 | symF))); | |
9ebbca7d GK |
12010 | } |
12011 | else | |
20b71b17 AM |
12012 | { |
12013 | rtx tocsym; | |
12014 | static int reload_toc_labelno = 0; | |
12015 | ||
12016 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
12017 | ||
12018 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); | |
12019 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12020 | ||
027fbf43 JJ |
12021 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym)); |
12022 | emit_move_insn (dest, tempLR); | |
12023 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 12024 | } |
027fbf43 JJ |
12025 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
12026 | if (fromprolog) | |
12027 | rs6000_maybe_dead (insn); | |
9ebbca7d | 12028 | } |
20b71b17 AM |
12029 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
12030 | { | |
12031 | /* This is for AIX code running in non-PIC ELF32. */ | |
12032 | char buf[30]; | |
12033 | rtx realsym; | |
12034 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
12035 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12036 | ||
027fbf43 JJ |
12037 | insn = emit_insn (gen_elf_high (dest, realsym)); |
12038 | if (fromprolog) | |
12039 | rs6000_maybe_dead (insn); | |
12040 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
12041 | if (fromprolog) | |
12042 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
12043 | } |
12044 | else if (DEFAULT_ABI == ABI_AIX) | |
9ebbca7d GK |
12045 | { |
12046 | if (TARGET_32BIT) | |
027fbf43 | 12047 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 12048 | else |
027fbf43 JJ |
12049 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
12050 | if (fromprolog) | |
12051 | rs6000_maybe_dead (insn); | |
9ebbca7d | 12052 | } |
20b71b17 AM |
12053 | else |
12054 | abort (); | |
9ebbca7d GK |
12055 | } |
12056 | ||
d1d0c603 JJ |
12057 | /* Emit instructions to restore the link register after determining where |
12058 | its value has been stored. */ | |
12059 | ||
12060 | void | |
12061 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
12062 | { | |
12063 | rs6000_stack_t *info = rs6000_stack_info (); | |
12064 | rtx operands[2]; | |
12065 | ||
12066 | operands[0] = source; | |
12067 | operands[1] = scratch; | |
12068 | ||
12069 | if (info->lr_save_p) | |
12070 | { | |
12071 | rtx frame_rtx = stack_pointer_rtx; | |
12072 | HOST_WIDE_INT sp_offset = 0; | |
12073 | rtx tmp; | |
12074 | ||
12075 | if (frame_pointer_needed | |
12076 | || current_function_calls_alloca | |
12077 | || info->total_size > 32767) | |
12078 | { | |
12079 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
12080 | frame_rtx = operands[1]; | |
12081 | } | |
12082 | else if (info->push_p) | |
12083 | sp_offset = info->total_size; | |
12084 | ||
12085 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
12086 | tmp = gen_rtx_MEM (Pmode, tmp); | |
12087 | emit_move_insn (tmp, operands[0]); | |
12088 | } | |
12089 | else | |
12090 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
12091 | } | |
12092 | ||
f103e34d GK |
12093 | static GTY(()) int set = -1; |
12094 | ||
9ebbca7d | 12095 | int |
863d938c | 12096 | get_TOC_alias_set (void) |
9ebbca7d | 12097 | { |
f103e34d GK |
12098 | if (set == -1) |
12099 | set = new_alias_set (); | |
12100 | return set; | |
9ebbca7d GK |
12101 | } |
12102 | ||
c1207243 | 12103 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
12104 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
12105 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 12106 | #if TARGET_ELF |
3c9eb5f4 | 12107 | static int |
38f391a5 | 12108 | uses_TOC (void) |
9ebbca7d | 12109 | { |
c4501e62 | 12110 | rtx insn; |
38c1f2d7 | 12111 | |
c4501e62 JJ |
12112 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
12113 | if (INSN_P (insn)) | |
12114 | { | |
12115 | rtx pat = PATTERN (insn); | |
12116 | int i; | |
9ebbca7d | 12117 | |
c4501e62 JJ |
12118 | if (GET_CODE (pat) == PARALLEL) |
12119 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
12120 | { | |
12121 | rtx sub = XVECEXP (pat, 0, i); | |
12122 | if (GET_CODE (sub) == USE) | |
12123 | { | |
12124 | sub = XEXP (sub, 0); | |
12125 | if (GET_CODE (sub) == UNSPEC | |
12126 | && XINT (sub, 1) == UNSPEC_TOC) | |
12127 | return 1; | |
12128 | } | |
12129 | } | |
12130 | } | |
12131 | return 0; | |
9ebbca7d | 12132 | } |
c954844a | 12133 | #endif |
38c1f2d7 | 12134 | |
9ebbca7d | 12135 | rtx |
a2369ed3 | 12136 | create_TOC_reference (rtx symbol) |
9ebbca7d | 12137 | { |
a8a05998 ZW |
12138 | return gen_rtx_PLUS (Pmode, |
12139 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
12140 | gen_rtx_CONST (Pmode, | |
12141 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 12142 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 12143 | } |
38c1f2d7 | 12144 | |
fc4767bb JJ |
12145 | /* If _Unwind_* has been called from within the same module, |
12146 | toc register is not guaranteed to be saved to 40(1) on function | |
12147 | entry. Save it there in that case. */ | |
c7ca610e | 12148 | |
9ebbca7d | 12149 | void |
863d938c | 12150 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
12151 | { |
12152 | rtx mem; | |
12153 | rtx stack_top = gen_reg_rtx (Pmode); | |
12154 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
12155 | rtx opcode = gen_reg_rtx (SImode); |
12156 | rtx tocompare = gen_reg_rtx (SImode); | |
12157 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d GK |
12158 | |
12159 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
12160 | emit_move_insn (stack_top, mem); | |
12161 | ||
fc4767bb JJ |
12162 | mem = gen_rtx_MEM (Pmode, |
12163 | gen_rtx_PLUS (Pmode, stack_top, | |
9ebbca7d GK |
12164 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); |
12165 | emit_move_insn (opcode_addr, mem); | |
fc4767bb JJ |
12166 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
12167 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 12168 | : 0xE8410028, SImode)); |
9ebbca7d | 12169 | |
fc4767bb | 12170 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 12171 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 12172 | no_toc_save_needed); |
9ebbca7d | 12173 | |
fc4767bb JJ |
12174 | mem = gen_rtx_MEM (Pmode, |
12175 | gen_rtx_PLUS (Pmode, stack_top, | |
12176 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
12177 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); | |
12178 | emit_label (no_toc_save_needed); | |
9ebbca7d | 12179 | } |
38c1f2d7 | 12180 | \f |
ba4828e0 RK |
12181 | /* This ties together stack memory (MEM with an alias set of |
12182 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
12183 | ||
9ebbca7d | 12184 | static void |
863d938c | 12185 | rs6000_emit_stack_tie (void) |
9ebbca7d | 12186 | { |
ba4828e0 RK |
12187 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
12188 | ||
12189 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
12190 | emit_insn (gen_stack_tie (mem)); |
12191 | } | |
38c1f2d7 | 12192 | |
9ebbca7d GK |
12193 | /* Emit the correct code for allocating stack space, as insns. |
12194 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
12195 | The generated code may use hard register 0 as a temporary. */ | |
12196 | ||
12197 | static void | |
a2369ed3 | 12198 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) |
38c1f2d7 | 12199 | { |
9ebbca7d GK |
12200 | rtx insn; |
12201 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
12202 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
12203 | rtx todec = GEN_INT (-size); | |
a157febd GK |
12204 | |
12205 | if (current_function_limit_stack) | |
12206 | { | |
12207 | if (REG_P (stack_limit_rtx) | |
12208 | && REGNO (stack_limit_rtx) > 1 | |
12209 | && REGNO (stack_limit_rtx) <= 31) | |
12210 | { | |
5b71a4e7 | 12211 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
12212 | ? gen_addsi3 (tmp_reg, |
12213 | stack_limit_rtx, | |
12214 | GEN_INT (size)) | |
12215 | : gen_adddi3 (tmp_reg, | |
12216 | stack_limit_rtx, | |
12217 | GEN_INT (size))); | |
5b71a4e7 | 12218 | |
9ebbca7d GK |
12219 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
12220 | const0_rtx)); | |
a157febd GK |
12221 | } |
12222 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 12223 | && TARGET_32BIT |
f607bc57 | 12224 | && DEFAULT_ABI == ABI_V4) |
a157febd | 12225 | { |
9ebbca7d GK |
12226 | rtx toload = gen_rtx_CONST (VOIDmode, |
12227 | gen_rtx_PLUS (Pmode, | |
12228 | stack_limit_rtx, | |
12229 | GEN_INT (size))); | |
5b71a4e7 | 12230 | |
9ebbca7d GK |
12231 | emit_insn (gen_elf_high (tmp_reg, toload)); |
12232 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
12233 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
12234 | const0_rtx)); | |
a157febd GK |
12235 | } |
12236 | else | |
12237 | warning ("stack limit expression is not supported"); | |
12238 | } | |
12239 | ||
9ebbca7d GK |
12240 | if (copy_r12 || ! TARGET_UPDATE) |
12241 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
12242 | ||
38c1f2d7 MM |
12243 | if (TARGET_UPDATE) |
12244 | { | |
9ebbca7d | 12245 | if (size > 32767) |
38c1f2d7 | 12246 | { |
9ebbca7d GK |
12247 | /* Need a note here so that try_split doesn't get confused. */ |
12248 | if (get_last_insn() == NULL_RTX) | |
2e040219 | 12249 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d GK |
12250 | insn = emit_move_insn (tmp_reg, todec); |
12251 | try_split (PATTERN (insn), insn, 0); | |
12252 | todec = tmp_reg; | |
38c1f2d7 | 12253 | } |
5b71a4e7 DE |
12254 | |
12255 | insn = emit_insn (TARGET_32BIT | |
12256 | ? gen_movsi_update (stack_reg, stack_reg, | |
12257 | todec, stack_reg) | |
12258 | : gen_movdi_update (stack_reg, stack_reg, | |
9ebbca7d | 12259 | todec, stack_reg)); |
38c1f2d7 MM |
12260 | } |
12261 | else | |
12262 | { | |
5b71a4e7 DE |
12263 | insn = emit_insn (TARGET_32BIT |
12264 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
12265 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
12266 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
12267 | gen_rtx_REG (Pmode, 12)); | |
12268 | } | |
5b71a4e7 | 12269 | |
9ebbca7d GK |
12270 | RTX_FRAME_RELATED_P (insn) = 1; |
12271 | REG_NOTES (insn) = | |
12272 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12273 | gen_rtx_SET (VOIDmode, stack_reg, | |
12274 | gen_rtx_PLUS (Pmode, stack_reg, | |
12275 | GEN_INT (-size))), | |
12276 | REG_NOTES (insn)); | |
12277 | } | |
12278 | ||
a4f6c312 SS |
12279 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
12280 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
12281 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
12282 | deduce these equivalences by itself so it wasn't necessary to hold | |
12283 | its hand so much. */ | |
9ebbca7d GK |
12284 | |
12285 | static void | |
a2369ed3 DJ |
12286 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
12287 | rtx reg2, rtx rreg) | |
9ebbca7d GK |
12288 | { |
12289 | rtx real, temp; | |
12290 | ||
e56c4463 JL |
12291 | /* copy_rtx will not make unique copies of registers, so we need to |
12292 | ensure we don't have unwanted sharing here. */ | |
12293 | if (reg == reg2) | |
12294 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12295 | ||
12296 | if (reg == rreg) | |
12297 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12298 | ||
9ebbca7d GK |
12299 | real = copy_rtx (PATTERN (insn)); |
12300 | ||
89e7058f AH |
12301 | if (reg2 != NULL_RTX) |
12302 | real = replace_rtx (real, reg2, rreg); | |
12303 | ||
9ebbca7d GK |
12304 | real = replace_rtx (real, reg, |
12305 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
12306 | STACK_POINTER_REGNUM), | |
12307 | GEN_INT (val))); | |
12308 | ||
12309 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
12310 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
12311 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
12312 | ||
12313 | if (GET_CODE (real) == SET) | |
12314 | { | |
12315 | rtx set = real; | |
12316 | ||
12317 | temp = simplify_rtx (SET_SRC (set)); | |
12318 | if (temp) | |
12319 | SET_SRC (set) = temp; | |
12320 | temp = simplify_rtx (SET_DEST (set)); | |
12321 | if (temp) | |
12322 | SET_DEST (set) = temp; | |
12323 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 12324 | { |
9ebbca7d GK |
12325 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
12326 | if (temp) | |
12327 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 12328 | } |
38c1f2d7 | 12329 | } |
9ebbca7d GK |
12330 | else if (GET_CODE (real) == PARALLEL) |
12331 | { | |
12332 | int i; | |
12333 | for (i = 0; i < XVECLEN (real, 0); i++) | |
12334 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
12335 | { | |
12336 | rtx set = XVECEXP (real, 0, i); | |
12337 | ||
12338 | temp = simplify_rtx (SET_SRC (set)); | |
12339 | if (temp) | |
12340 | SET_SRC (set) = temp; | |
12341 | temp = simplify_rtx (SET_DEST (set)); | |
12342 | if (temp) | |
12343 | SET_DEST (set) = temp; | |
12344 | if (GET_CODE (SET_DEST (set)) == MEM) | |
12345 | { | |
12346 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
12347 | if (temp) | |
12348 | XEXP (SET_DEST (set), 0) = temp; | |
12349 | } | |
12350 | RTX_FRAME_RELATED_P (set) = 1; | |
12351 | } | |
12352 | } | |
12353 | else | |
a4f6c312 | 12354 | abort (); |
c19de7aa AH |
12355 | |
12356 | if (TARGET_SPE) | |
12357 | real = spe_synthesize_frame_save (real); | |
12358 | ||
9ebbca7d GK |
12359 | RTX_FRAME_RELATED_P (insn) = 1; |
12360 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12361 | real, | |
12362 | REG_NOTES (insn)); | |
38c1f2d7 MM |
12363 | } |
12364 | ||
c19de7aa AH |
12365 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
12366 | original note, plus a synthetic register save. */ | |
12367 | ||
12368 | static rtx | |
a2369ed3 | 12369 | spe_synthesize_frame_save (rtx real) |
c19de7aa AH |
12370 | { |
12371 | rtx synth, offset, reg, real2; | |
12372 | ||
12373 | if (GET_CODE (real) != SET | |
12374 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
12375 | return real; | |
12376 | ||
12377 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
12378 | frame related note. The parallel contains a set of the register | |
41f3a930 | 12379 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
12380 | This is so we can differentiate between 64-bit and 32-bit saves. |
12381 | Words cannot describe this nastiness. */ | |
12382 | ||
12383 | if (GET_CODE (SET_DEST (real)) != MEM | |
12384 | || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS | |
12385 | || GET_CODE (SET_SRC (real)) != REG) | |
12386 | abort (); | |
12387 | ||
12388 | /* Transform: | |
12389 | (set (mem (plus (reg x) (const y))) | |
12390 | (reg z)) | |
12391 | into: | |
12392 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 12393 | (reg z+1200)) |
c19de7aa AH |
12394 | */ |
12395 | ||
12396 | real2 = copy_rtx (real); | |
12397 | PUT_MODE (SET_DEST (real2), SImode); | |
12398 | reg = SET_SRC (real2); | |
12399 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
12400 | synth = copy_rtx (real2); | |
12401 | ||
12402 | if (BYTES_BIG_ENDIAN) | |
12403 | { | |
12404 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
12405 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
12406 | } | |
12407 | ||
12408 | reg = SET_SRC (synth); | |
41f3a930 | 12409 | |
c19de7aa | 12410 | synth = replace_rtx (synth, reg, |
41f3a930 | 12411 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
12412 | |
12413 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
12414 | synth = replace_rtx (synth, offset, | |
12415 | GEN_INT (INTVAL (offset) | |
12416 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
12417 | ||
12418 | RTX_FRAME_RELATED_P (synth) = 1; | |
12419 | RTX_FRAME_RELATED_P (real2) = 1; | |
12420 | if (BYTES_BIG_ENDIAN) | |
12421 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
12422 | else | |
12423 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
12424 | ||
12425 | return real; | |
12426 | } | |
12427 | ||
00b960c7 AH |
12428 | /* Returns an insn that has a vrsave set operation with the |
12429 | appropriate CLOBBERs. */ | |
12430 | ||
12431 | static rtx | |
a2369ed3 | 12432 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
12433 | { |
12434 | int nclobs, i; | |
12435 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 12436 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 12437 | |
a004eb82 AH |
12438 | clobs[0] |
12439 | = gen_rtx_SET (VOIDmode, | |
12440 | vrsave, | |
12441 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
12442 | gen_rtvec (2, reg, vrsave), | |
12443 | 30)); | |
00b960c7 AH |
12444 | |
12445 | nclobs = 1; | |
12446 | ||
9aa86737 AH |
12447 | /* We need to clobber the registers in the mask so the scheduler |
12448 | does not move sets to VRSAVE before sets of AltiVec registers. | |
12449 | ||
12450 | However, if the function receives nonlocal gotos, reload will set | |
12451 | all call saved registers live. We will end up with: | |
12452 | ||
12453 | (set (reg 999) (mem)) | |
12454 | (parallel [ (set (reg vrsave) (unspec blah)) | |
12455 | (clobber (reg 999))]) | |
12456 | ||
12457 | The clobber will cause the store into reg 999 to be dead, and | |
12458 | flow will attempt to delete an epilogue insn. In this case, we | |
12459 | need an unspec use/set of the register. */ | |
00b960c7 AH |
12460 | |
12461 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
44688022 | 12462 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) |
9aa86737 AH |
12463 | { |
12464 | if (!epiloguep || call_used_regs [i]) | |
12465 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
12466 | gen_rtx_REG (V4SImode, i)); | |
12467 | else | |
12468 | { | |
12469 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
12470 | |
12471 | clobs[nclobs++] | |
a004eb82 AH |
12472 | = gen_rtx_SET (VOIDmode, |
12473 | reg, | |
12474 | gen_rtx_UNSPEC (V4SImode, | |
12475 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
12476 | } |
12477 | } | |
00b960c7 AH |
12478 | |
12479 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
12480 | ||
12481 | for (i = 0; i < nclobs; ++i) | |
12482 | XVECEXP (insn, 0, i) = clobs[i]; | |
12483 | ||
12484 | return insn; | |
12485 | } | |
12486 | ||
89e7058f AH |
12487 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
12488 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
12489 | ||
12490 | static void | |
a2369ed3 | 12491 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 12492 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
12493 | { |
12494 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
12495 | rtx replacea, replaceb; | |
12496 | ||
12497 | int_rtx = GEN_INT (offset); | |
12498 | ||
12499 | /* Some cases that need register indexed addressing. */ | |
12500 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
a3170dc6 AH |
12501 | || (TARGET_SPE_ABI |
12502 | && SPE_VECTOR_MODE (mode) | |
12503 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
12504 | { |
12505 | /* Whomever calls us must make sure r11 is available in the | |
12506 | flow path of instructions in the prologue. */ | |
12507 | offset_rtx = gen_rtx_REG (Pmode, 11); | |
12508 | emit_move_insn (offset_rtx, int_rtx); | |
12509 | ||
12510 | replacea = offset_rtx; | |
12511 | replaceb = int_rtx; | |
12512 | } | |
12513 | else | |
12514 | { | |
12515 | offset_rtx = int_rtx; | |
12516 | replacea = NULL_RTX; | |
12517 | replaceb = NULL_RTX; | |
12518 | } | |
12519 | ||
12520 | reg = gen_rtx_REG (mode, regno); | |
12521 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
12522 | mem = gen_rtx_MEM (mode, addr); | |
12523 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12524 | ||
12525 | insn = emit_move_insn (mem, reg); | |
12526 | ||
12527 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
12528 | } | |
12529 | ||
a3170dc6 AH |
12530 | /* Emit an offset memory reference suitable for a frame store, while |
12531 | converting to a valid addressing mode. */ | |
12532 | ||
12533 | static rtx | |
a2369ed3 | 12534 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
12535 | { |
12536 | rtx int_rtx, offset_rtx; | |
12537 | ||
12538 | int_rtx = GEN_INT (offset); | |
12539 | ||
12540 | if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) | |
12541 | { | |
12542 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
12543 | emit_move_insn (offset_rtx, int_rtx); | |
12544 | } | |
12545 | else | |
12546 | offset_rtx = int_rtx; | |
12547 | ||
12548 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
12549 | } | |
12550 | ||
9ebbca7d GK |
12551 | /* Emit function prologue as insns. */ |
12552 | ||
9878760c | 12553 | void |
863d938c | 12554 | rs6000_emit_prologue (void) |
9878760c | 12555 | { |
4697a36c | 12556 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a | 12557 | enum machine_mode reg_mode = Pmode; |
327e5343 | 12558 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
12559 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
12560 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
12561 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 12562 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d GK |
12563 | rtx insn; |
12564 | int saving_FPRs_inline; | |
12565 | int using_store_multiple; | |
12566 | HOST_WIDE_INT sp_offset = 0; | |
12567 | ||
c19de7aa | 12568 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12569 | { |
12570 | reg_mode = V2SImode; | |
12571 | reg_size = 8; | |
12572 | } | |
12573 | ||
9ebbca7d | 12574 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
12575 | && (!TARGET_SPE_ABI |
12576 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
12577 | && info->first_gp_reg_save < 31); |
12578 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8c29550d | 12579 | || FP_SAVE_INLINE (info->first_fp_reg_save) |
acd0b319 | 12580 | || current_function_calls_eh_return |
8c29550d | 12581 | || cfun->machine->ra_need_lr); |
9ebbca7d GK |
12582 | |
12583 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
fc4767bb | 12584 | if (info->push_p |
acd0b319 AM |
12585 | && (DEFAULT_ABI == ABI_V4 |
12586 | || current_function_calls_eh_return)) | |
9ebbca7d GK |
12587 | { |
12588 | if (info->total_size < 32767) | |
12589 | sp_offset = info->total_size; | |
12590 | else | |
12591 | frame_reg_rtx = frame_ptr_rtx; | |
12592 | rs6000_emit_allocate_stack (info->total_size, | |
12593 | (frame_reg_rtx != sp_reg_rtx | |
12594 | && (info->cr_save_p | |
12595 | || info->lr_save_p | |
12596 | || info->first_fp_reg_save < 64 | |
12597 | || info->first_gp_reg_save < 32 | |
12598 | ))); | |
12599 | if (frame_reg_rtx != sp_reg_rtx) | |
12600 | rs6000_emit_stack_tie (); | |
12601 | } | |
12602 | ||
9aa86737 AH |
12603 | /* Save AltiVec registers if needed. */ |
12604 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
12605 | { | |
12606 | int i; | |
12607 | ||
12608 | /* There should be a non inline version of this, for when we | |
12609 | are saving lots of vector registers. */ | |
12610 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
12611 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
12612 | { | |
12613 | rtx areg, savereg, mem; | |
12614 | int offset; | |
12615 | ||
12616 | offset = info->altivec_save_offset + sp_offset | |
12617 | + 16 * (i - info->first_altivec_reg_save); | |
12618 | ||
12619 | savereg = gen_rtx_REG (V4SImode, i); | |
12620 | ||
12621 | areg = gen_rtx_REG (Pmode, 0); | |
12622 | emit_move_insn (areg, GEN_INT (offset)); | |
12623 | ||
12624 | /* AltiVec addressing mode is [reg+reg]. */ | |
12625 | mem = gen_rtx_MEM (V4SImode, | |
12626 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
12627 | ||
12628 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12629 | ||
12630 | insn = emit_move_insn (mem, savereg); | |
12631 | ||
5c242421 SB |
12632 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
12633 | areg, GEN_INT (offset)); | |
9aa86737 AH |
12634 | } |
12635 | } | |
12636 | ||
12637 | /* VRSAVE is a bit vector representing which AltiVec registers | |
12638 | are used. The OS uses this to determine which vector | |
12639 | registers to save on a context switch. We need to save | |
12640 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
12641 | used in this function, and do the corresponding magic in the | |
12642 | epilogue. */ | |
12643 | ||
4d774ff8 HP |
12644 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
12645 | && info->vrsave_mask != 0) | |
9aa86737 | 12646 | { |
a004eb82 | 12647 | rtx reg, mem, vrsave; |
9aa86737 AH |
12648 | int offset; |
12649 | ||
12650 | /* Get VRSAVE onto a GPR. */ | |
12651 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 | 12652 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
12653 | if (TARGET_MACHO) |
12654 | emit_insn (gen_get_vrsave_internal (reg)); | |
12655 | else | |
12656 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
12657 | |
12658 | /* Save VRSAVE. */ | |
12659 | offset = info->vrsave_save_offset + sp_offset; | |
12660 | mem | |
12661 | = gen_rtx_MEM (SImode, | |
12662 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
12663 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12664 | insn = emit_move_insn (mem, reg); | |
12665 | ||
12666 | /* Include the registers in the mask. */ | |
12667 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
12668 | ||
12669 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
12670 | } | |
12671 | ||
9ebbca7d GK |
12672 | /* If we use the link register, get it into r0. */ |
12673 | if (info->lr_save_p) | |
f8a57be8 GK |
12674 | { |
12675 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
12676 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
12677 | RTX_FRAME_RELATED_P (insn) = 1; | |
12678 | } | |
9ebbca7d GK |
12679 | |
12680 | /* If we need to save CR, put it into r12. */ | |
12681 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
12682 | { | |
f8a57be8 GK |
12683 | rtx set; |
12684 | ||
9ebbca7d | 12685 | cr_save_rtx = gen_rtx_REG (SImode, 12); |
f8a57be8 GK |
12686 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
12687 | RTX_FRAME_RELATED_P (insn) = 1; | |
12688 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
12689 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. | |
12690 | But that's OK. All we have to do is specify that _one_ condition | |
12691 | code register is saved in this stack slot. The thrower's epilogue | |
12692 | will then restore all the call-saved registers. | |
12693 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
12694 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, | |
12695 | gen_rtx_REG (SImode, CR2_REGNO)); | |
12696 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12697 | set, | |
12698 | REG_NOTES (insn)); | |
9ebbca7d GK |
12699 | } |
12700 | ||
a4f6c312 SS |
12701 | /* Do any required saving of fpr's. If only one or two to save, do |
12702 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
12703 | if (saving_FPRs_inline) |
12704 | { | |
12705 | int i; | |
12706 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
12707 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
12708 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
89e7058f AH |
12709 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
12710 | info->first_fp_reg_save + i, | |
12711 | info->fp_save_offset + sp_offset + 8 * i, | |
12712 | info->total_size); | |
9ebbca7d GK |
12713 | } |
12714 | else if (info->first_fp_reg_save != 64) | |
12715 | { | |
12716 | int i; | |
12717 | char rname[30]; | |
520a57c8 | 12718 | const char *alloc_rname; |
9ebbca7d GK |
12719 | rtvec p; |
12720 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
12721 | ||
12722 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
12723 | gen_rtx_REG (Pmode, | |
12724 | LINK_REGISTER_REGNUM)); | |
12725 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
12726 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 12727 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
12728 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
12729 | gen_rtx_SYMBOL_REF (Pmode, | |
12730 | alloc_rname)); | |
12731 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
12732 | { | |
12733 | rtx addr, reg, mem; | |
12734 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
12735 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12736 | GEN_INT (info->fp_save_offset | |
12737 | + sp_offset + 8*i)); | |
12738 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 12739 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
12740 | |
12741 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
12742 | } | |
12743 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
12744 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12745 | NULL_RTX, NULL_RTX); | |
12746 | } | |
b6c9286a | 12747 | |
9ebbca7d GK |
12748 | /* Save GPRs. This is done as a PARALLEL if we are using |
12749 | the store-multiple instructions. */ | |
12750 | if (using_store_multiple) | |
b6c9286a | 12751 | { |
308c142a | 12752 | rtvec p; |
9ebbca7d GK |
12753 | int i; |
12754 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
12755 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
12756 | { | |
12757 | rtx addr, reg, mem; | |
12758 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
12759 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12760 | GEN_INT (info->gp_save_offset | |
12761 | + sp_offset | |
12762 | + reg_size * i)); | |
12763 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 12764 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
12765 | |
12766 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
12767 | } | |
12768 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
12769 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12770 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
12771 | } |
12772 | else | |
12773 | { | |
9ebbca7d GK |
12774 | int i; |
12775 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
12776 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
b4db40bf JJ |
12777 | && (! call_used_regs[info->first_gp_reg_save+i] |
12778 | || (i+info->first_gp_reg_save | |
12779 | == RS6000_PIC_OFFSET_TABLE_REGNUM | |
12780 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 12781 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 12782 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 12783 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
12784 | { |
12785 | rtx addr, reg, mem; | |
12786 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
12787 | ||
c19de7aa | 12788 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12789 | { |
12790 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
12791 | rtx b; | |
12792 | ||
12793 | if (!SPE_CONST_OFFSET_OK (offset)) | |
12794 | { | |
12795 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
12796 | emit_move_insn (b, GEN_INT (offset)); | |
12797 | } | |
12798 | else | |
12799 | b = GEN_INT (offset); | |
12800 | ||
12801 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
12802 | mem = gen_rtx_MEM (V2SImode, addr); | |
12803 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12804 | insn = emit_move_insn (mem, reg); | |
12805 | ||
12806 | if (GET_CODE (b) == CONST_INT) | |
12807 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12808 | NULL_RTX, NULL_RTX); | |
12809 | else | |
12810 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12811 | b, GEN_INT (offset)); | |
12812 | } | |
12813 | else | |
12814 | { | |
12815 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12816 | GEN_INT (info->gp_save_offset | |
12817 | + sp_offset | |
12818 | + reg_size * i)); | |
12819 | mem = gen_rtx_MEM (reg_mode, addr); | |
12820 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12821 | ||
12822 | insn = emit_move_insn (mem, reg); | |
12823 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12824 | NULL_RTX, NULL_RTX); | |
12825 | } | |
12826 | } | |
9ebbca7d GK |
12827 | } |
12828 | ||
83720594 RH |
12829 | /* ??? There's no need to emit actual instructions here, but it's the |
12830 | easiest way to get the frame unwind information emitted. */ | |
12831 | if (current_function_calls_eh_return) | |
12832 | { | |
78e1b90d DE |
12833 | unsigned int i, regno; |
12834 | ||
fc4767bb JJ |
12835 | /* In AIX ABI we need to pretend we save r2 here. */ |
12836 | if (TARGET_AIX) | |
12837 | { | |
12838 | rtx addr, reg, mem; | |
12839 | ||
12840 | reg = gen_rtx_REG (reg_mode, 2); | |
12841 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12842 | GEN_INT (sp_offset + 5 * reg_size)); | |
12843 | mem = gen_rtx_MEM (reg_mode, addr); | |
12844 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12845 | ||
12846 | insn = emit_move_insn (mem, reg); | |
12847 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12848 | NULL_RTX, NULL_RTX); | |
12849 | PATTERN (insn) = gen_blockage (); | |
12850 | } | |
12851 | ||
83720594 RH |
12852 | for (i = 0; ; ++i) |
12853 | { | |
83720594 RH |
12854 | regno = EH_RETURN_DATA_REGNO (i); |
12855 | if (regno == INVALID_REGNUM) | |
12856 | break; | |
12857 | ||
89e7058f AH |
12858 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
12859 | info->ehrd_offset + sp_offset | |
12860 | + reg_size * (int) i, | |
12861 | info->total_size); | |
83720594 RH |
12862 | } |
12863 | } | |
12864 | ||
9ebbca7d GK |
12865 | /* Save lr if we used it. */ |
12866 | if (info->lr_save_p) | |
12867 | { | |
12868 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12869 | GEN_INT (info->lr_save_offset + sp_offset)); | |
12870 | rtx reg = gen_rtx_REG (Pmode, 0); | |
12871 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
12872 | /* This should not be of rs6000_sr_alias_set, because of | |
12873 | __builtin_return_address. */ | |
12874 | ||
12875 | insn = emit_move_insn (mem, reg); | |
12876 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
f8a57be8 | 12877 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
12878 | } |
12879 | ||
12880 | /* Save CR if we use any that must be preserved. */ | |
12881 | if (info->cr_save_p) | |
12882 | { | |
12883 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12884 | GEN_INT (info->cr_save_offset + sp_offset)); | |
12885 | rtx mem = gen_rtx_MEM (SImode, addr); | |
f8a57be8 GK |
12886 | /* See the large comment above about why CR2_REGNO is used. */ |
12887 | rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); | |
ba4828e0 RK |
12888 | |
12889 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
12890 | |
12891 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
12892 | that it's free. */ | |
12893 | if (REGNO (frame_reg_rtx) == 12) | |
12894 | { | |
f8a57be8 GK |
12895 | rtx set; |
12896 | ||
9ebbca7d | 12897 | cr_save_rtx = gen_rtx_REG (SImode, 0); |
f8a57be8 GK |
12898 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
12899 | RTX_FRAME_RELATED_P (insn) = 1; | |
12900 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); | |
12901 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12902 | set, | |
12903 | REG_NOTES (insn)); | |
12904 | ||
9ebbca7d GK |
12905 | } |
12906 | insn = emit_move_insn (mem, cr_save_rtx); | |
12907 | ||
9ebbca7d | 12908 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 12909 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
12910 | } |
12911 | ||
12912 | /* Update stack and set back pointer unless this is V.4, | |
12913 | for which it was done previously. */ | |
fc4767bb JJ |
12914 | if (info->push_p |
12915 | && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) | |
9ebbca7d GK |
12916 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
12917 | ||
12918 | /* Set frame pointer, if needed. */ | |
12919 | if (frame_pointer_needed) | |
12920 | { | |
a3170dc6 | 12921 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
12922 | sp_reg_rtx); |
12923 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 12924 | } |
9878760c | 12925 | |
1db02437 | 12926 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 12927 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
f607bc57 | 12928 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
1db02437 | 12929 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
9ebbca7d GK |
12930 | { |
12931 | /* If emit_load_toc_table will use the link register, we need to save | |
c4501e62 | 12932 | it. We use R12 for this purpose because emit_load_toc_table |
9ebbca7d GK |
12933 | can use register 0. This allows us to use a plain 'blr' to return |
12934 | from the procedure more often. */ | |
f1384257 AM |
12935 | int save_LR_around_toc_setup = (TARGET_ELF |
12936 | && DEFAULT_ABI != ABI_AIX | |
12937 | && flag_pic | |
d5fa86ba GK |
12938 | && ! info->lr_save_p |
12939 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d | 12940 | if (save_LR_around_toc_setup) |
c4501e62 JJ |
12941 | { |
12942 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f8a57be8 GK |
12943 | |
12944 | insn = emit_move_insn (frame_ptr_rtx, lr); | |
12945 | rs6000_maybe_dead (insn); | |
12946 | RTX_FRAME_RELATED_P (insn) = 1; | |
12947 | ||
c4501e62 | 12948 | rs6000_emit_load_toc_table (TRUE); |
f8a57be8 GK |
12949 | |
12950 | insn = emit_move_insn (lr, frame_ptr_rtx); | |
12951 | rs6000_maybe_dead (insn); | |
12952 | RTX_FRAME_RELATED_P (insn) = 1; | |
c4501e62 JJ |
12953 | } |
12954 | else | |
12955 | rs6000_emit_load_toc_table (TRUE); | |
9ebbca7d | 12956 | } |
ee890fe2 | 12957 | |
fcce224d | 12958 | #if TARGET_MACHO |
ee890fe2 SS |
12959 | if (DEFAULT_ABI == ABI_DARWIN |
12960 | && flag_pic && current_function_uses_pic_offset_table) | |
12961 | { | |
f8a57be8 | 12962 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
f099d360 | 12963 | const char *picbase = machopic_function_base_name (); |
6788f5ca | 12964 | rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase); |
ee890fe2 | 12965 | |
f8a57be8 | 12966 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); |
ee890fe2 | 12967 | |
f8a57be8 GK |
12968 | insn = emit_move_insn (gen_rtx_REG (Pmode, |
12969 | RS6000_PIC_OFFSET_TABLE_REGNUM), | |
12970 | lr); | |
12971 | rs6000_maybe_dead (insn); | |
ee890fe2 | 12972 | } |
fcce224d | 12973 | #endif |
9ebbca7d GK |
12974 | } |
12975 | ||
9ebbca7d | 12976 | /* Write function prologue. */ |
a4f6c312 | 12977 | |
08c148a8 | 12978 | static void |
a2369ed3 DJ |
12979 | rs6000_output_function_prologue (FILE *file, |
12980 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
9ebbca7d GK |
12981 | { |
12982 | rs6000_stack_t *info = rs6000_stack_info (); | |
12983 | ||
4697a36c MM |
12984 | if (TARGET_DEBUG_STACK) |
12985 | debug_stack_info (info); | |
9878760c | 12986 | |
a4f6c312 SS |
12987 | /* Write .extern for any function we will call to save and restore |
12988 | fp values. */ | |
12989 | if (info->first_fp_reg_save < 64 | |
12990 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 12991 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 12992 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
12993 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
12994 | RESTORE_FP_SUFFIX); | |
9878760c | 12995 | |
c764f757 RK |
12996 | /* Write .extern for AIX common mode routines, if needed. */ |
12997 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
12998 | { | |
f6709c70 JW |
12999 | fputs ("\t.extern __mulh\n", file); |
13000 | fputs ("\t.extern __mull\n", file); | |
13001 | fputs ("\t.extern __divss\n", file); | |
13002 | fputs ("\t.extern __divus\n", file); | |
13003 | fputs ("\t.extern __quoss\n", file); | |
13004 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
13005 | common_mode_defined = 1; |
13006 | } | |
9878760c | 13007 | |
9ebbca7d | 13008 | if (! HAVE_prologue) |
979721f8 | 13009 | { |
9ebbca7d | 13010 | start_sequence (); |
9dda4cc8 | 13011 | |
a4f6c312 SS |
13012 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
13013 | the "toplevel" insn chain. */ | |
2e040219 | 13014 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13015 | rs6000_emit_prologue (); |
2e040219 | 13016 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 13017 | |
a3c9585f | 13018 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
13019 | { |
13020 | rtx insn; | |
13021 | unsigned addr = 0; | |
13022 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
13023 | { | |
13024 | INSN_ADDRESSES_NEW (insn, addr); | |
13025 | addr += 4; | |
13026 | } | |
13027 | } | |
9dda4cc8 | 13028 | |
9ebbca7d | 13029 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
13030 | debug_rtx_list (get_insns (), 100); |
13031 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 13032 | end_sequence (); |
979721f8 MM |
13033 | } |
13034 | ||
9ebbca7d GK |
13035 | rs6000_pic_labelno++; |
13036 | } | |
13037 | ||
13038 | /* Emit function epilogue as insns. | |
9878760c | 13039 | |
9ebbca7d GK |
13040 | At present, dwarf2out_frame_debug_expr doesn't understand |
13041 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
13042 | anywhere in the epilogue. Most of the insns below would in any case | |
13043 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 13044 | |
9ebbca7d | 13045 | void |
a2369ed3 | 13046 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
13047 | { |
13048 | rs6000_stack_t *info; | |
13049 | int restoring_FPRs_inline; | |
13050 | int using_load_multiple; | |
13051 | int using_mfcr_multiple; | |
13052 | int use_backchain_to_restore_sp; | |
13053 | int sp_offset = 0; | |
13054 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
13055 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a | 13056 | enum machine_mode reg_mode = Pmode; |
327e5343 | 13057 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
13058 | int i; |
13059 | ||
c19de7aa AH |
13060 | info = rs6000_stack_info (); |
13061 | ||
13062 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
13063 | { |
13064 | reg_mode = V2SImode; | |
13065 | reg_size = 8; | |
13066 | } | |
13067 | ||
9ebbca7d | 13068 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
13069 | && (!TARGET_SPE_ABI |
13070 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
13071 | && info->first_gp_reg_save < 31); |
13072 | restoring_FPRs_inline = (sibcall | |
83720594 | 13073 | || current_function_calls_eh_return |
9ebbca7d GK |
13074 | || info->first_fp_reg_save == 64 |
13075 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
13076 | use_backchain_to_restore_sp = (frame_pointer_needed | |
13077 | || current_function_calls_alloca | |
13078 | || info->total_size > 32767); | |
13079 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
13080 | || rs6000_cpu == PROCESSOR_PPC603 | |
13081 | || rs6000_cpu == PROCESSOR_PPC750 | |
13082 | || optimize_size); | |
13083 | ||
13084 | /* If we have a frame pointer, a call to alloca, or a large stack | |
13085 | frame, restore the old stack pointer using the backchain. Otherwise, | |
13086 | we know what size to update it with. */ | |
13087 | if (use_backchain_to_restore_sp) | |
bacbde18 | 13088 | { |
9ebbca7d GK |
13089 | /* Under V.4, don't reset the stack pointer until after we're done |
13090 | loading the saved registers. */ | |
f607bc57 | 13091 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 13092 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 13093 | |
9ebbca7d GK |
13094 | emit_move_insn (frame_reg_rtx, |
13095 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
13096 | ||
bacbde18 | 13097 | } |
9ebbca7d | 13098 | else if (info->push_p) |
85638c0d | 13099 | { |
fc4767bb JJ |
13100 | if (DEFAULT_ABI == ABI_V4 |
13101 | || current_function_calls_eh_return) | |
9ebbca7d GK |
13102 | sp_offset = info->total_size; |
13103 | else | |
13104 | { | |
13105 | emit_insn (TARGET_32BIT | |
13106 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
13107 | GEN_INT (info->total_size)) | |
13108 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
13109 | GEN_INT (info->total_size))); | |
13110 | } | |
85638c0d | 13111 | } |
9ebbca7d | 13112 | |
9aa86737 AH |
13113 | /* Restore AltiVec registers if needed. */ |
13114 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
13115 | { | |
13116 | int i; | |
13117 | ||
13118 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
13119 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
13120 | { | |
13121 | rtx addr, areg, mem; | |
13122 | ||
13123 | areg = gen_rtx_REG (Pmode, 0); | |
13124 | emit_move_insn | |
13125 | (areg, GEN_INT (info->altivec_save_offset | |
13126 | + sp_offset | |
13127 | + 16 * (i - info->first_altivec_reg_save))); | |
13128 | ||
13129 | /* AltiVec addressing mode is [reg+reg]. */ | |
13130 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
13131 | mem = gen_rtx_MEM (V4SImode, addr); | |
13132 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13133 | ||
13134 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
13135 | } | |
13136 | } | |
13137 | ||
13138 | /* Restore VRSAVE if needed. */ | |
44688022 | 13139 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
4d774ff8 | 13140 | && info->vrsave_mask != 0) |
9aa86737 AH |
13141 | { |
13142 | rtx addr, mem, reg; | |
13143 | ||
13144 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13145 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
13146 | mem = gen_rtx_MEM (SImode, addr); | |
13147 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13148 | reg = gen_rtx_REG (SImode, 12); | |
13149 | emit_move_insn (reg, mem); | |
13150 | ||
13151 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
13152 | } | |
13153 | ||
9ebbca7d GK |
13154 | /* Get the old lr if we saved it. */ |
13155 | if (info->lr_save_p) | |
b6c9286a | 13156 | { |
a3170dc6 AH |
13157 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
13158 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
13159 | |
13160 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 13161 | |
9ebbca7d | 13162 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 13163 | } |
9ebbca7d GK |
13164 | |
13165 | /* Get the old cr if we saved it. */ | |
13166 | if (info->cr_save_p) | |
13167 | { | |
13168 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13169 | GEN_INT (info->cr_save_offset + sp_offset)); | |
13170 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
13171 | |
13172 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 13173 | |
9ebbca7d GK |
13174 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
13175 | } | |
13176 | ||
13177 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 13178 | if (info->lr_save_p) |
9ebbca7d GK |
13179 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
13180 | gen_rtx_REG (Pmode, 0)); | |
13181 | ||
83720594 RH |
13182 | /* Load exception handler data registers, if needed. */ |
13183 | if (current_function_calls_eh_return) | |
13184 | { | |
78e1b90d DE |
13185 | unsigned int i, regno; |
13186 | ||
fc4767bb JJ |
13187 | if (TARGET_AIX) |
13188 | { | |
13189 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13190 | GEN_INT (sp_offset + 5 * reg_size)); | |
13191 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13192 | ||
13193 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13194 | ||
13195 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
13196 | } | |
13197 | ||
83720594 RH |
13198 | for (i = 0; ; ++i) |
13199 | { | |
a3170dc6 | 13200 | rtx mem; |
83720594 RH |
13201 | |
13202 | regno = EH_RETURN_DATA_REGNO (i); | |
13203 | if (regno == INVALID_REGNUM) | |
13204 | break; | |
13205 | ||
a3170dc6 AH |
13206 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
13207 | info->ehrd_offset + sp_offset | |
13208 | + reg_size * (int) i); | |
ba4828e0 | 13209 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
13210 | |
13211 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
13212 | } | |
13213 | } | |
9ebbca7d GK |
13214 | |
13215 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
13216 | the load-multiple instructions. */ | |
13217 | if (using_load_multiple) | |
979721f8 | 13218 | { |
9ebbca7d GK |
13219 | rtvec p; |
13220 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
13221 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 13222 | { |
9ebbca7d GK |
13223 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13224 | GEN_INT (info->gp_save_offset | |
13225 | + sp_offset | |
13226 | + reg_size * i)); | |
13227 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
13228 | |
13229 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
13230 | |
13231 | RTVEC_ELT (p, i) = | |
13232 | gen_rtx_SET (VOIDmode, | |
13233 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
13234 | mem); | |
979721f8 | 13235 | } |
9ebbca7d | 13236 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 13237 | } |
9ebbca7d GK |
13238 | else |
13239 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
13240 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
b4db40bf JJ |
13241 | && (! call_used_regs[info->first_gp_reg_save+i] |
13242 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM | |
13243 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 13244 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 13245 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 13246 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d GK |
13247 | { |
13248 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13249 | GEN_INT (info->gp_save_offset | |
13250 | + sp_offset | |
13251 | + reg_size * i)); | |
13252 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 13253 | |
a3170dc6 | 13254 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 13255 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
13256 | { |
13257 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
13258 | rtx b; | |
13259 | ||
13260 | if (!SPE_CONST_OFFSET_OK (offset)) | |
13261 | { | |
13262 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13263 | emit_move_insn (b, GEN_INT (offset)); | |
13264 | } | |
13265 | else | |
13266 | b = GEN_INT (offset); | |
13267 | ||
13268 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
13269 | mem = gen_rtx_MEM (V2SImode, addr); | |
13270 | } | |
13271 | ||
ba4828e0 | 13272 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13273 | |
13274 | emit_move_insn (gen_rtx_REG (reg_mode, | |
a3170dc6 | 13275 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 13276 | } |
9878760c | 13277 | |
9ebbca7d GK |
13278 | /* Restore fpr's if we need to do it without calling a function. */ |
13279 | if (restoring_FPRs_inline) | |
13280 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
13281 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
13282 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
13283 | { | |
13284 | rtx addr, mem; | |
13285 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13286 | GEN_INT (info->fp_save_offset | |
13287 | + sp_offset | |
a4f6c312 | 13288 | + 8 * i)); |
9ebbca7d | 13289 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 13290 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13291 | |
13292 | emit_move_insn (gen_rtx_REG (DFmode, | |
13293 | info->first_fp_reg_save + i), | |
13294 | mem); | |
13295 | } | |
8d30c4ee | 13296 | |
9ebbca7d GK |
13297 | /* If we saved cr, restore it here. Just those that were used. */ |
13298 | if (info->cr_save_p) | |
979721f8 | 13299 | { |
9ebbca7d | 13300 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 13301 | int count = 0; |
9ebbca7d GK |
13302 | |
13303 | if (using_mfcr_multiple) | |
979721f8 | 13304 | { |
9ebbca7d GK |
13305 | for (i = 0; i < 8; i++) |
13306 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 13307 | count++; |
9ebbca7d | 13308 | if (count == 0) |
e35b9579 GK |
13309 | abort (); |
13310 | } | |
13311 | ||
13312 | if (using_mfcr_multiple && count > 1) | |
13313 | { | |
13314 | rtvec p; | |
13315 | int ndx; | |
9ebbca7d | 13316 | |
e35b9579 | 13317 | p = rtvec_alloc (count); |
9ebbca7d | 13318 | |
e35b9579 | 13319 | ndx = 0; |
9ebbca7d GK |
13320 | for (i = 0; i < 8; i++) |
13321 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
13322 | { | |
13323 | rtvec r = rtvec_alloc (2); | |
13324 | RTVEC_ELT (r, 0) = r12_rtx; | |
13325 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 13326 | RTVEC_ELT (p, ndx) = |
9ebbca7d | 13327 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 13328 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 13329 | ndx++; |
9ebbca7d GK |
13330 | } |
13331 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
13332 | if (ndx != count) |
13333 | abort (); | |
979721f8 MM |
13334 | } |
13335 | else | |
9ebbca7d GK |
13336 | for (i = 0; i < 8; i++) |
13337 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 13338 | { |
9ebbca7d GK |
13339 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
13340 | CR0_REGNO+i), | |
13341 | r12_rtx)); | |
979721f8 | 13342 | } |
979721f8 MM |
13343 | } |
13344 | ||
9ebbca7d GK |
13345 | /* If this is V.4, unwind the stack pointer after all of the loads |
13346 | have been done. We need to emit a block here so that sched | |
13347 | doesn't decide to move the sp change before the register restores | |
13348 | (which may not have any obvious dependency on the stack). This | |
13349 | doesn't hurt performance, because there is no scheduling that can | |
13350 | be done after this point. */ | |
fc4767bb JJ |
13351 | if (DEFAULT_ABI == ABI_V4 |
13352 | || current_function_calls_eh_return) | |
b6c9286a | 13353 | { |
9ebbca7d GK |
13354 | if (frame_reg_rtx != sp_reg_rtx) |
13355 | rs6000_emit_stack_tie (); | |
b6c9286a | 13356 | |
9ebbca7d | 13357 | if (use_backchain_to_restore_sp) |
b6c9286a | 13358 | { |
9ebbca7d | 13359 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 13360 | } |
9ebbca7d | 13361 | else if (sp_offset != 0) |
13f1623b | 13362 | { |
5b71a4e7 | 13363 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
13364 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
13365 | GEN_INT (sp_offset)) | |
13366 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
13367 | GEN_INT (sp_offset))); | |
13f1623b | 13368 | } |
9ebbca7d | 13369 | } |
b6c9286a | 13370 | |
83720594 RH |
13371 | if (current_function_calls_eh_return) |
13372 | { | |
13373 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 13374 | emit_insn (TARGET_32BIT |
83720594 RH |
13375 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
13376 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
13377 | } | |
13378 | ||
9ebbca7d GK |
13379 | if (!sibcall) |
13380 | { | |
13381 | rtvec p; | |
13382 | if (! restoring_FPRs_inline) | |
13383 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
13384 | else | |
13385 | p = rtvec_alloc (2); | |
b6c9286a | 13386 | |
e35b9579 GK |
13387 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
13388 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
13389 | gen_rtx_REG (Pmode, |
13390 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
13391 | |
13392 | /* If we have to restore more than two FP registers, branch to the | |
13393 | restore function. It will return to our caller. */ | |
13394 | if (! restoring_FPRs_inline) | |
13395 | { | |
13396 | int i; | |
13397 | char rname[30]; | |
520a57c8 | 13398 | const char *alloc_rname; |
979721f8 | 13399 | |
9ebbca7d GK |
13400 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
13401 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 13402 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
13403 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
13404 | gen_rtx_SYMBOL_REF (Pmode, | |
13405 | alloc_rname)); | |
b6c9286a | 13406 | |
9ebbca7d GK |
13407 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
13408 | { | |
13409 | rtx addr, mem; | |
13410 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
13411 | GEN_INT (info->fp_save_offset + 8*i)); | |
13412 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 13413 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13414 | |
13415 | RTVEC_ELT (p, i+3) = | |
13416 | gen_rtx_SET (VOIDmode, | |
13417 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
13418 | mem); | |
b6c9286a MM |
13419 | } |
13420 | } | |
9ebbca7d GK |
13421 | |
13422 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 13423 | } |
9878760c RK |
13424 | } |
13425 | ||
13426 | /* Write function epilogue. */ | |
13427 | ||
08c148a8 | 13428 | static void |
a2369ed3 DJ |
13429 | rs6000_output_function_epilogue (FILE *file, |
13430 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
9878760c | 13431 | { |
4697a36c | 13432 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 13433 | |
9ebbca7d | 13434 | if (! HAVE_epilogue) |
9878760c | 13435 | { |
9ebbca7d GK |
13436 | rtx insn = get_last_insn (); |
13437 | /* If the last insn was a BARRIER, we don't have to write anything except | |
13438 | the trace table. */ | |
13439 | if (GET_CODE (insn) == NOTE) | |
13440 | insn = prev_nonnote_insn (insn); | |
13441 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 13442 | { |
9ebbca7d GK |
13443 | /* This is slightly ugly, but at least we don't have two |
13444 | copies of the epilogue-emitting code. */ | |
13445 | start_sequence (); | |
13446 | ||
13447 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
13448 | and end of the "toplevel" insn chain. */ | |
2e040219 | 13449 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13450 | rs6000_emit_epilogue (FALSE); |
2e040219 | 13451 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13452 | |
a3c9585f | 13453 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
13454 | { |
13455 | rtx insn; | |
13456 | unsigned addr = 0; | |
13457 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
13458 | { | |
13459 | INSN_ADDRESSES_NEW (insn, addr); | |
13460 | addr += 4; | |
13461 | } | |
13462 | } | |
13463 | ||
9ebbca7d | 13464 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
13465 | debug_rtx_list (get_insns (), 100); |
13466 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 13467 | end_sequence (); |
4697a36c | 13468 | } |
9878760c | 13469 | } |
b4ac57ab | 13470 | |
efdba735 SH |
13471 | #if TARGET_MACHO |
13472 | macho_branch_islands (); | |
0e5da0be GK |
13473 | /* Mach-O doesn't support labels at the end of objects, so if |
13474 | it looks like we might want one, insert a NOP. */ | |
13475 | { | |
13476 | rtx insn = get_last_insn (); | |
13477 | while (insn | |
13478 | && NOTE_P (insn) | |
13479 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) | |
13480 | insn = PREV_INSN (insn); | |
13481 | if (insn | |
13482 | && (LABEL_P (insn) | |
13483 | || (NOTE_P (insn) | |
13484 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) | |
13485 | fputs ("\tnop\n", file); | |
13486 | } | |
13487 | #endif | |
13488 | ||
9b30bae2 | 13489 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
13490 | on its format. |
13491 | ||
13492 | We don't output a traceback table if -finhibit-size-directive was | |
13493 | used. The documentation for -finhibit-size-directive reads | |
13494 | ``don't output a @code{.size} assembler directive, or anything | |
13495 | else that would cause trouble if the function is split in the | |
13496 | middle, and the two halves are placed at locations far apart in | |
13497 | memory.'' The traceback table has this property, since it | |
13498 | includes the offset from the start of the function to the | |
4d30c363 MM |
13499 | traceback table itself. |
13500 | ||
13501 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 13502 | different traceback table. */ |
57ac7be9 AM |
13503 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
13504 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 13505 | { |
69c75916 | 13506 | const char *fname = NULL; |
3ac88239 | 13507 | const char *language_string = lang_hooks.name; |
6041bf2f | 13508 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 13509 | int i; |
57ac7be9 AM |
13510 | int optional_tbtab; |
13511 | ||
13512 | if (rs6000_traceback == traceback_full) | |
13513 | optional_tbtab = 1; | |
13514 | else if (rs6000_traceback == traceback_part) | |
13515 | optional_tbtab = 0; | |
13516 | else | |
13517 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 13518 | |
69c75916 AM |
13519 | if (optional_tbtab) |
13520 | { | |
13521 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
13522 | while (*fname == '.') /* V.4 encodes . in the name */ | |
13523 | fname++; | |
13524 | ||
13525 | /* Need label immediately before tbtab, so we can compute | |
13526 | its offset from the function start. */ | |
13527 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
13528 | ASM_OUTPUT_LABEL (file, fname); | |
13529 | } | |
314fc5a9 ILT |
13530 | |
13531 | /* The .tbtab pseudo-op can only be used for the first eight | |
13532 | expressions, since it can't handle the possibly variable | |
13533 | length fields that follow. However, if you omit the optional | |
13534 | fields, the assembler outputs zeros for all optional fields | |
13535 | anyways, giving each variable length field is minimum length | |
13536 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
13537 | pseudo-op at all. */ | |
13538 | ||
13539 | /* An all-zero word flags the start of the tbtab, for debuggers | |
13540 | that have to find it by searching forward from the entry | |
13541 | point or from the current pc. */ | |
19d2d16f | 13542 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
13543 | |
13544 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 13545 | fputs ("\t.byte 0,", file); |
314fc5a9 | 13546 | |
5fc921c1 DE |
13547 | /* Language type. Unfortunately, there does not seem to be any |
13548 | official way to discover the language being compiled, so we | |
13549 | use language_string. | |
13550 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
13551 | Java is 13. Objective-C is 14. */ | |
13552 | if (! strcmp (language_string, "GNU C")) | |
314fc5a9 | 13553 | i = 0; |
6de9cd9a DN |
13554 | else if (! strcmp (language_string, "GNU F77") |
13555 | || ! strcmp (language_string, "GNU F95")) | |
314fc5a9 | 13556 | i = 1; |
8b83775b | 13557 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 13558 | i = 2; |
5fc921c1 DE |
13559 | else if (! strcmp (language_string, "GNU Ada")) |
13560 | i = 3; | |
314fc5a9 ILT |
13561 | else if (! strcmp (language_string, "GNU C++")) |
13562 | i = 9; | |
9517ead8 AG |
13563 | else if (! strcmp (language_string, "GNU Java")) |
13564 | i = 13; | |
5fc921c1 DE |
13565 | else if (! strcmp (language_string, "GNU Objective-C")) |
13566 | i = 14; | |
314fc5a9 ILT |
13567 | else |
13568 | abort (); | |
13569 | fprintf (file, "%d,", i); | |
13570 | ||
13571 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
13572 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
13573 | from start of procedure stored in tbtab, internal function, function | |
13574 | has controlled storage, function has no toc, function uses fp, | |
13575 | function logs/aborts fp operations. */ | |
13576 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
13577 | fprintf (file, "%d,", |
13578 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
13579 | |
13580 | /* 6 bitfields: function is interrupt handler, name present in | |
13581 | proc table, function calls alloca, on condition directives | |
13582 | (controls stack walks, 3 bits), saves condition reg, saves | |
13583 | link reg. */ | |
13584 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
13585 | set up as a frame pointer, even when there is no alloca call. */ | |
13586 | fprintf (file, "%d,", | |
6041bf2f DE |
13587 | ((optional_tbtab << 6) |
13588 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
13589 | | (info->cr_save_p << 1) | |
13590 | | (info->lr_save_p))); | |
314fc5a9 | 13591 | |
6041bf2f | 13592 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
13593 | (6 bits). */ |
13594 | fprintf (file, "%d,", | |
4697a36c | 13595 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
13596 | |
13597 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
13598 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
13599 | ||
6041bf2f DE |
13600 | if (optional_tbtab) |
13601 | { | |
13602 | /* Compute the parameter info from the function decl argument | |
13603 | list. */ | |
13604 | tree decl; | |
13605 | int next_parm_info_bit = 31; | |
314fc5a9 | 13606 | |
6041bf2f DE |
13607 | for (decl = DECL_ARGUMENTS (current_function_decl); |
13608 | decl; decl = TREE_CHAIN (decl)) | |
13609 | { | |
13610 | rtx parameter = DECL_INCOMING_RTL (decl); | |
13611 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 13612 | |
6041bf2f DE |
13613 | if (GET_CODE (parameter) == REG) |
13614 | { | |
13615 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
13616 | { | |
13617 | int bits; | |
13618 | ||
13619 | float_parms++; | |
13620 | ||
13621 | if (mode == SFmode) | |
13622 | bits = 0x2; | |
fcce224d | 13623 | else if (mode == DFmode || mode == TFmode) |
6041bf2f DE |
13624 | bits = 0x3; |
13625 | else | |
13626 | abort (); | |
13627 | ||
13628 | /* If only one bit will fit, don't or in this entry. */ | |
13629 | if (next_parm_info_bit > 0) | |
13630 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
13631 | next_parm_info_bit -= 2; | |
13632 | } | |
13633 | else | |
13634 | { | |
13635 | fixed_parms += ((GET_MODE_SIZE (mode) | |
13636 | + (UNITS_PER_WORD - 1)) | |
13637 | / UNITS_PER_WORD); | |
13638 | next_parm_info_bit -= 1; | |
13639 | } | |
13640 | } | |
13641 | } | |
13642 | } | |
314fc5a9 ILT |
13643 | |
13644 | /* Number of fixed point parameters. */ | |
13645 | /* This is actually the number of words of fixed point parameters; thus | |
13646 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
13647 | fprintf (file, "%d,", fixed_parms); | |
13648 | ||
13649 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
13650 | all on stack. */ | |
13651 | /* This is actually the number of fp registers that hold parameters; | |
13652 | and thus the maximum value is 13. */ | |
13653 | /* Set parameters on stack bit if parameters are not in their original | |
13654 | registers, regardless of whether they are on the stack? Xlc | |
13655 | seems to set the bit when not optimizing. */ | |
13656 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
13657 | ||
6041bf2f DE |
13658 | if (! optional_tbtab) |
13659 | return; | |
13660 | ||
314fc5a9 ILT |
13661 | /* Optional fields follow. Some are variable length. */ |
13662 | ||
13663 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
13664 | 11 double float. */ | |
13665 | /* There is an entry for each parameter in a register, in the order that | |
13666 | they occur in the parameter list. Any intervening arguments on the | |
13667 | stack are ignored. If the list overflows a long (max possible length | |
13668 | 34 bits) then completely leave off all elements that don't fit. */ | |
13669 | /* Only emit this long if there was at least one parameter. */ | |
13670 | if (fixed_parms || float_parms) | |
13671 | fprintf (file, "\t.long %d\n", parm_info); | |
13672 | ||
13673 | /* Offset from start of code to tb table. */ | |
19d2d16f | 13674 | fputs ("\t.long ", file); |
314fc5a9 | 13675 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
13676 | #if TARGET_AIX |
13677 | RS6000_OUTPUT_BASENAME (file, fname); | |
13678 | #else | |
9ebbca7d | 13679 | assemble_name (file, fname); |
54ee9799 | 13680 | #endif |
19d2d16f | 13681 | fputs ("-.", file); |
54ee9799 DE |
13682 | #if TARGET_AIX |
13683 | RS6000_OUTPUT_BASENAME (file, fname); | |
13684 | #else | |
9ebbca7d | 13685 | assemble_name (file, fname); |
54ee9799 | 13686 | #endif |
19d2d16f | 13687 | putc ('\n', file); |
314fc5a9 ILT |
13688 | |
13689 | /* Interrupt handler mask. */ | |
13690 | /* Omit this long, since we never set the interrupt handler bit | |
13691 | above. */ | |
13692 | ||
13693 | /* Number of CTL (controlled storage) anchors. */ | |
13694 | /* Omit this long, since the has_ctl bit is never set above. */ | |
13695 | ||
13696 | /* Displacement into stack of each CTL anchor. */ | |
13697 | /* Omit this list of longs, because there are no CTL anchors. */ | |
13698 | ||
13699 | /* Length of function name. */ | |
69c75916 AM |
13700 | if (*fname == '*') |
13701 | ++fname; | |
296b8152 | 13702 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
13703 | |
13704 | /* Function name. */ | |
13705 | assemble_string (fname, strlen (fname)); | |
13706 | ||
13707 | /* Register for alloca automatic storage; this is always reg 31. | |
13708 | Only emit this if the alloca bit was set above. */ | |
13709 | if (frame_pointer_needed) | |
19d2d16f | 13710 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
13711 | |
13712 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 13713 | } |
9878760c | 13714 | } |
17167fd8 | 13715 | \f |
a4f6c312 SS |
13716 | /* A C compound statement that outputs the assembler code for a thunk |
13717 | function, used to implement C++ virtual function calls with | |
13718 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
13719 | function, adjusting the implicit object parameter before handing | |
13720 | control off to the real function. | |
13721 | ||
13722 | First, emit code to add the integer DELTA to the location that | |
13723 | contains the incoming first argument. Assume that this argument | |
13724 | contains a pointer, and is the one used to pass the `this' pointer | |
13725 | in C++. This is the incoming argument *before* the function | |
13726 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
13727 | values of all other incoming arguments. | |
17167fd8 MM |
13728 | |
13729 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
13730 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
13731 | not touch the return address. Hence returning from FUNCTION will | |
13732 | return to whoever called the current `thunk'. | |
17167fd8 | 13733 | |
a4f6c312 SS |
13734 | The effect must be as if FUNCTION had been called directly with the |
13735 | adjusted first argument. This macro is responsible for emitting | |
13736 | all of the code for a thunk function; output_function_prologue() | |
13737 | and output_function_epilogue() are not invoked. | |
17167fd8 | 13738 | |
a4f6c312 SS |
13739 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
13740 | been extracted from it.) It might possibly be useful on some | |
13741 | targets, but probably not. | |
17167fd8 | 13742 | |
a4f6c312 SS |
13743 | If you do not define this macro, the target-independent code in the |
13744 | C++ frontend will generate a less efficient heavyweight thunk that | |
13745 | calls FUNCTION instead of jumping to it. The generic approach does | |
13746 | not support varargs. */ | |
17167fd8 | 13747 | |
3961e8fe | 13748 | static void |
a2369ed3 DJ |
13749 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
13750 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
13751 | tree function) | |
17167fd8 | 13752 | { |
5b71a4e7 | 13753 | rtx this, insn, funexp; |
17167fd8 | 13754 | |
5b71a4e7 | 13755 | reload_completed = 1; |
fe3ad572 | 13756 | epilogue_completed = 1; |
5b71a4e7 | 13757 | no_new_pseudos = 1; |
6429e3be | 13758 | reset_block_changes (); |
56a7189a | 13759 | |
5b71a4e7 | 13760 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 13761 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 13762 | |
5b71a4e7 DE |
13763 | /* Find the "this" pointer. If the function returns a structure, |
13764 | the structure return pointer is in r3. */ | |
61f71b34 | 13765 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
5b71a4e7 | 13766 | this = gen_rtx_REG (Pmode, 4); |
56a7189a | 13767 | else |
5b71a4e7 | 13768 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 13769 | |
5b71a4e7 DE |
13770 | /* Apply the constant offset, if required. */ |
13771 | if (delta) | |
13772 | { | |
13773 | rtx delta_rtx = GEN_INT (delta); | |
13774 | emit_insn (TARGET_32BIT | |
13775 | ? gen_addsi3 (this, this, delta_rtx) | |
13776 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
13777 | } |
13778 | ||
5b71a4e7 DE |
13779 | /* Apply the offset from the vtable, if required. */ |
13780 | if (vcall_offset) | |
17167fd8 | 13781 | { |
5b71a4e7 DE |
13782 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
13783 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 13784 | |
5b71a4e7 | 13785 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
eeff9307 JJ |
13786 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
13787 | { | |
13788 | emit_insn (TARGET_32BIT | |
13789 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
13790 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
13791 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
13792 | } | |
13793 | else | |
13794 | { | |
13795 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
13796 | ||
13797 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
13798 | } | |
5b71a4e7 DE |
13799 | emit_insn (TARGET_32BIT |
13800 | ? gen_addsi3 (this, this, tmp) | |
13801 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
13802 | } |
13803 | ||
5b71a4e7 DE |
13804 | /* Generate a tail call to the target function. */ |
13805 | if (!TREE_USED (function)) | |
13806 | { | |
13807 | assemble_external (function); | |
13808 | TREE_USED (function) = 1; | |
13809 | } | |
13810 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 13811 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
13812 | |
13813 | #if TARGET_MACHO | |
ab82a49f | 13814 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 13815 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 13816 | #endif |
5b71a4e7 DE |
13817 | |
13818 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
13819 | generate sibcall RTL explicitly to avoid constraint abort. */ | |
13820 | insn = emit_call_insn ( | |
13821 | gen_rtx_PARALLEL (VOIDmode, | |
13822 | gen_rtvec (4, | |
13823 | gen_rtx_CALL (VOIDmode, | |
13824 | funexp, const0_rtx), | |
13825 | gen_rtx_USE (VOIDmode, const0_rtx), | |
13826 | gen_rtx_USE (VOIDmode, | |
13827 | gen_rtx_REG (SImode, | |
13828 | LINK_REGISTER_REGNUM)), | |
13829 | gen_rtx_RETURN (VOIDmode)))); | |
13830 | SIBLING_CALL_P (insn) = 1; | |
13831 | emit_barrier (); | |
13832 | ||
13833 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
13834 | There's not really enough bulk here to make other passes such as | |
13835 | instruction scheduling worth while. Note that use_thunk calls | |
13836 | assemble_start_function and assemble_end_function. */ | |
13837 | insn = get_insns (); | |
a2855205 | 13838 | insn_locators_initialize (); |
5b71a4e7 DE |
13839 | shorten_branches (insn); |
13840 | final_start_function (insn, file, 1); | |
13841 | final (insn, file, 1, 0); | |
13842 | final_end_function (); | |
13843 | ||
13844 | reload_completed = 0; | |
fe3ad572 | 13845 | epilogue_completed = 0; |
5b71a4e7 | 13846 | no_new_pseudos = 0; |
9ebbca7d | 13847 | } |
9ebbca7d GK |
13848 | \f |
13849 | /* A quick summary of the various types of 'constant-pool tables' | |
13850 | under PowerPC: | |
13851 | ||
13852 | Target Flags Name One table per | |
13853 | AIX (none) AIX TOC object file | |
13854 | AIX -mfull-toc AIX TOC object file | |
13855 | AIX -mminimal-toc AIX minimal TOC translation unit | |
13856 | SVR4/EABI (none) SVR4 SDATA object file | |
13857 | SVR4/EABI -fpic SVR4 pic object file | |
13858 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
13859 | SVR4/EABI -mrelocatable EABI TOC function | |
13860 | SVR4/EABI -maix AIX TOC object file | |
13861 | SVR4/EABI -maix -mminimal-toc | |
13862 | AIX minimal TOC translation unit | |
13863 | ||
13864 | Name Reg. Set by entries contains: | |
13865 | made by addrs? fp? sum? | |
13866 | ||
13867 | AIX TOC 2 crt0 as Y option option | |
13868 | AIX minimal TOC 30 prolog gcc Y Y option | |
13869 | SVR4 SDATA 13 crt0 gcc N Y N | |
13870 | SVR4 pic 30 prolog ld Y not yet N | |
13871 | SVR4 PIC 30 prolog gcc Y option option | |
13872 | EABI TOC 30 prolog gcc Y option option | |
13873 | ||
13874 | */ | |
13875 | ||
9ebbca7d GK |
13876 | /* Hash functions for the hash table. */ |
13877 | ||
13878 | static unsigned | |
a2369ed3 | 13879 | rs6000_hash_constant (rtx k) |
9ebbca7d | 13880 | { |
46b33600 RH |
13881 | enum rtx_code code = GET_CODE (k); |
13882 | enum machine_mode mode = GET_MODE (k); | |
13883 | unsigned result = (code << 3) ^ mode; | |
13884 | const char *format; | |
13885 | int flen, fidx; | |
9ebbca7d | 13886 | |
46b33600 RH |
13887 | format = GET_RTX_FORMAT (code); |
13888 | flen = strlen (format); | |
13889 | fidx = 0; | |
9ebbca7d | 13890 | |
46b33600 RH |
13891 | switch (code) |
13892 | { | |
13893 | case LABEL_REF: | |
13894 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
13895 | ||
13896 | case CONST_DOUBLE: | |
13897 | if (mode != VOIDmode) | |
13898 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
13899 | flen = 2; | |
13900 | break; | |
13901 | ||
13902 | case CODE_LABEL: | |
13903 | fidx = 3; | |
13904 | break; | |
13905 | ||
13906 | default: | |
13907 | break; | |
13908 | } | |
9ebbca7d GK |
13909 | |
13910 | for (; fidx < flen; fidx++) | |
13911 | switch (format[fidx]) | |
13912 | { | |
13913 | case 's': | |
13914 | { | |
13915 | unsigned i, len; | |
13916 | const char *str = XSTR (k, fidx); | |
13917 | len = strlen (str); | |
13918 | result = result * 613 + len; | |
13919 | for (i = 0; i < len; i++) | |
13920 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
13921 | break; |
13922 | } | |
9ebbca7d GK |
13923 | case 'u': |
13924 | case 'e': | |
13925 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
13926 | break; | |
13927 | case 'i': | |
13928 | case 'n': | |
13929 | result = result * 613 + (unsigned) XINT (k, fidx); | |
13930 | break; | |
13931 | case 'w': | |
13932 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
13933 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
13934 | else | |
13935 | { | |
13936 | size_t i; | |
13937 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
13938 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
13939 | >> CHAR_BIT * i); | |
13940 | } | |
13941 | break; | |
09501938 DE |
13942 | case '0': |
13943 | break; | |
9ebbca7d | 13944 | default: |
a4f6c312 | 13945 | abort (); |
9ebbca7d | 13946 | } |
46b33600 | 13947 | |
9ebbca7d GK |
13948 | return result; |
13949 | } | |
13950 | ||
13951 | static unsigned | |
a2369ed3 | 13952 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 13953 | { |
a9098fd0 GK |
13954 | const struct toc_hash_struct *thc = |
13955 | (const struct toc_hash_struct *) hash_entry; | |
13956 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
13957 | } |
13958 | ||
13959 | /* Compare H1 and H2 for equivalence. */ | |
13960 | ||
13961 | static int | |
a2369ed3 | 13962 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
13963 | { |
13964 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
13965 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
13966 | ||
a9098fd0 GK |
13967 | if (((const struct toc_hash_struct *) h1)->key_mode |
13968 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
13969 | return 0; | |
13970 | ||
5692c7bc | 13971 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
13972 | } |
13973 | ||
28e510bd MM |
13974 | /* These are the names given by the C++ front-end to vtables, and |
13975 | vtable-like objects. Ideally, this logic should not be here; | |
13976 | instead, there should be some programmatic way of inquiring as | |
13977 | to whether or not an object is a vtable. */ | |
13978 | ||
13979 | #define VTABLE_NAME_P(NAME) \ | |
13980 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
13981 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
13982 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
26be75db | 13983 | || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ |
28e510bd MM |
13984 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) |
13985 | ||
13986 | void | |
a2369ed3 | 13987 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
13988 | { |
13989 | /* Currently C++ toc references to vtables can be emitted before it | |
13990 | is decided whether the vtable is public or private. If this is | |
13991 | the case, then the linker will eventually complain that there is | |
13992 | a reference to an unknown section. Thus, for vtables only, | |
13993 | we emit the TOC reference to reference the symbol and not the | |
13994 | section. */ | |
13995 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
13996 | |
13997 | if (VTABLE_NAME_P (name)) | |
13998 | { | |
13999 | RS6000_OUTPUT_BASENAME (file, name); | |
14000 | } | |
14001 | else | |
14002 | assemble_name (file, name); | |
28e510bd MM |
14003 | } |
14004 | ||
a4f6c312 SS |
14005 | /* Output a TOC entry. We derive the entry name from what is being |
14006 | written. */ | |
9878760c RK |
14007 | |
14008 | void | |
a2369ed3 | 14009 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
14010 | { |
14011 | char buf[256]; | |
3cce094d | 14012 | const char *name = buf; |
ec940faa | 14013 | const char *real_name; |
9878760c RK |
14014 | rtx base = x; |
14015 | int offset = 0; | |
14016 | ||
4697a36c MM |
14017 | if (TARGET_NO_TOC) |
14018 | abort (); | |
14019 | ||
9ebbca7d GK |
14020 | /* When the linker won't eliminate them, don't output duplicate |
14021 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
14022 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
14023 | CODE_LABELs. */ | |
14024 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
14025 | { |
14026 | struct toc_hash_struct *h; | |
14027 | void * * found; | |
14028 | ||
17211ab5 | 14029 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
39e3f58c | 14030 | time because GGC is not initialized at that point. */ |
17211ab5 GK |
14031 | if (toc_hash_table == NULL) |
14032 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, | |
14033 | toc_hash_eq, NULL); | |
14034 | ||
9ebbca7d GK |
14035 | h = ggc_alloc (sizeof (*h)); |
14036 | h->key = x; | |
a9098fd0 | 14037 | h->key_mode = mode; |
9ebbca7d GK |
14038 | h->labelno = labelno; |
14039 | ||
14040 | found = htab_find_slot (toc_hash_table, h, 1); | |
14041 | if (*found == NULL) | |
14042 | *found = h; | |
14043 | else /* This is indeed a duplicate. | |
14044 | Set this label equal to that label. */ | |
14045 | { | |
14046 | fputs ("\t.set ", file); | |
14047 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
14048 | fprintf (file, "%d,", labelno); | |
14049 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
14050 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
14051 | found)->labelno)); | |
14052 | return; | |
14053 | } | |
14054 | } | |
14055 | ||
14056 | /* If we're going to put a double constant in the TOC, make sure it's | |
14057 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
14058 | if (GET_CODE (x) == CONST_DOUBLE |
14059 | && STRICT_ALIGNMENT | |
a9098fd0 | 14060 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
14061 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
14062 | ASM_OUTPUT_ALIGN (file, 3); | |
14063 | } | |
14064 | ||
4977bab6 | 14065 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 14066 | |
37c37a57 RK |
14067 | /* Handle FP constants specially. Note that if we have a minimal |
14068 | TOC, things we put here aren't actually in the TOC, so we can allow | |
14069 | FP constants. */ | |
fcce224d DE |
14070 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
14071 | { | |
14072 | REAL_VALUE_TYPE rv; | |
14073 | long k[4]; | |
14074 | ||
14075 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
14076 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
14077 | ||
14078 | if (TARGET_64BIT) | |
14079 | { | |
14080 | if (TARGET_MINIMAL_TOC) | |
14081 | fputs (DOUBLE_INT_ASM_OP, file); | |
14082 | else | |
14083 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
14084 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14085 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14086 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
14087 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14088 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14089 | return; | |
14090 | } | |
14091 | else | |
14092 | { | |
14093 | if (TARGET_MINIMAL_TOC) | |
14094 | fputs ("\t.long ", file); | |
14095 | else | |
14096 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
14097 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14098 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14099 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
14100 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14101 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14102 | return; | |
14103 | } | |
14104 | } | |
14105 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 14106 | { |
042259f2 DE |
14107 | REAL_VALUE_TYPE rv; |
14108 | long k[2]; | |
0adc764e | 14109 | |
042259f2 DE |
14110 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
14111 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 14112 | |
13ded975 DE |
14113 | if (TARGET_64BIT) |
14114 | { | |
14115 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14116 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 14117 | else |
2f0552b6 AM |
14118 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
14119 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
14120 | fprintf (file, "0x%lx%08lx\n", | |
14121 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
14122 | return; |
14123 | } | |
1875cc88 | 14124 | else |
13ded975 DE |
14125 | { |
14126 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14127 | fputs ("\t.long ", file); |
13ded975 | 14128 | else |
2f0552b6 AM |
14129 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
14130 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
14131 | fprintf (file, "0x%lx,0x%lx\n", | |
14132 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
14133 | return; |
14134 | } | |
9878760c | 14135 | } |
a9098fd0 | 14136 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 14137 | { |
042259f2 DE |
14138 | REAL_VALUE_TYPE rv; |
14139 | long l; | |
9878760c | 14140 | |
042259f2 DE |
14141 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
14142 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
14143 | ||
31bfaa0b DE |
14144 | if (TARGET_64BIT) |
14145 | { | |
14146 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14147 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 14148 | else |
2f0552b6 AM |
14149 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
14150 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
14151 | return; |
14152 | } | |
042259f2 | 14153 | else |
31bfaa0b DE |
14154 | { |
14155 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14156 | fputs ("\t.long ", file); |
31bfaa0b | 14157 | else |
2f0552b6 AM |
14158 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
14159 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
14160 | return; |
14161 | } | |
042259f2 | 14162 | } |
f176e826 | 14163 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 14164 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 14165 | { |
e2c953b6 | 14166 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
14167 | HOST_WIDE_INT high; |
14168 | ||
14169 | if (GET_CODE (x) == CONST_DOUBLE) | |
14170 | { | |
14171 | low = CONST_DOUBLE_LOW (x); | |
14172 | high = CONST_DOUBLE_HIGH (x); | |
14173 | } | |
14174 | else | |
14175 | #if HOST_BITS_PER_WIDE_INT == 32 | |
14176 | { | |
14177 | low = INTVAL (x); | |
0858c623 | 14178 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
14179 | } |
14180 | #else | |
14181 | { | |
0858c623 | 14182 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
14183 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
14184 | } | |
14185 | #endif | |
9878760c | 14186 | |
a9098fd0 GK |
14187 | /* TOC entries are always Pmode-sized, but since this |
14188 | is a bigendian machine then if we're putting smaller | |
14189 | integer constants in the TOC we have to pad them. | |
14190 | (This is still a win over putting the constants in | |
14191 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
14192 | to have both a TOC entry _and_ the actual constant.) |
14193 | ||
14194 | For a 32-bit target, CONST_INT values are loaded and shifted | |
14195 | entirely within `low' and can be stored in one TOC entry. */ | |
14196 | ||
14197 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 14198 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
14199 | |
14200 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
14201 | { |
14202 | #if HOST_BITS_PER_WIDE_INT == 32 | |
14203 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
14204 | POINTER_SIZE, &low, &high, 0); | |
14205 | #else | |
14206 | low |= high << 32; | |
14207 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
14208 | high = (HOST_WIDE_INT) low >> 32; | |
14209 | low &= 0xffffffff; | |
14210 | #endif | |
14211 | } | |
a9098fd0 | 14212 | |
13ded975 DE |
14213 | if (TARGET_64BIT) |
14214 | { | |
14215 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14216 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 14217 | else |
2f0552b6 AM |
14218 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
14219 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
14220 | fprintf (file, "0x%lx%08lx\n", | |
14221 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
14222 | return; |
14223 | } | |
1875cc88 | 14224 | else |
13ded975 | 14225 | { |
02a4ec28 FS |
14226 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
14227 | { | |
14228 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14229 | fputs ("\t.long ", file); |
02a4ec28 | 14230 | else |
2bfcf297 | 14231 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
14232 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
14233 | fprintf (file, "0x%lx,0x%lx\n", | |
14234 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 14235 | } |
13ded975 | 14236 | else |
02a4ec28 FS |
14237 | { |
14238 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14239 | fputs ("\t.long ", file); |
02a4ec28 | 14240 | else |
2f0552b6 AM |
14241 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
14242 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 14243 | } |
13ded975 DE |
14244 | return; |
14245 | } | |
9878760c RK |
14246 | } |
14247 | ||
14248 | if (GET_CODE (x) == CONST) | |
14249 | { | |
2bfcf297 DB |
14250 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
14251 | abort (); | |
14252 | ||
9878760c RK |
14253 | base = XEXP (XEXP (x, 0), 0); |
14254 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
14255 | } | |
14256 | ||
14257 | if (GET_CODE (base) == SYMBOL_REF) | |
14258 | name = XSTR (base, 0); | |
14259 | else if (GET_CODE (base) == LABEL_REF) | |
14260 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
14261 | else if (GET_CODE (base) == CODE_LABEL) | |
14262 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
14263 | else | |
14264 | abort (); | |
14265 | ||
772c5265 | 14266 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 14267 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 14268 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
14269 | else |
14270 | { | |
b6c9286a | 14271 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 14272 | |
1875cc88 JW |
14273 | if (offset < 0) |
14274 | fprintf (file, ".N%d", - offset); | |
14275 | else if (offset) | |
14276 | fprintf (file, ".P%d", offset); | |
9878760c | 14277 | |
19d2d16f | 14278 | fputs ("[TC],", file); |
1875cc88 | 14279 | } |
581bc4de MM |
14280 | |
14281 | /* Currently C++ toc references to vtables can be emitted before it | |
14282 | is decided whether the vtable is public or private. If this is | |
14283 | the case, then the linker will eventually complain that there is | |
14284 | a TOC reference to an unknown section. Thus, for vtables only, | |
14285 | we emit the TOC reference to reference the symbol and not the | |
14286 | section. */ | |
28e510bd | 14287 | if (VTABLE_NAME_P (name)) |
581bc4de | 14288 | { |
54ee9799 | 14289 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
14290 | if (offset < 0) |
14291 | fprintf (file, "%d", offset); | |
14292 | else if (offset > 0) | |
14293 | fprintf (file, "+%d", offset); | |
14294 | } | |
14295 | else | |
14296 | output_addr_const (file, x); | |
19d2d16f | 14297 | putc ('\n', file); |
9878760c RK |
14298 | } |
14299 | \f | |
14300 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
14301 | starting at P to FILE. | |
14302 | ||
14303 | On the RS/6000, we have to do this using the .byte operation and | |
14304 | write out special characters outside the quoted string. | |
14305 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 14306 | so we must artificially break them up early. */ |
9878760c RK |
14307 | |
14308 | void | |
a2369ed3 | 14309 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
14310 | { |
14311 | char c; | |
14312 | int i, count_string; | |
d330fd93 KG |
14313 | const char *for_string = "\t.byte \""; |
14314 | const char *for_decimal = "\t.byte "; | |
14315 | const char *to_close = NULL; | |
9878760c RK |
14316 | |
14317 | count_string = 0; | |
14318 | for (i = 0; i < n; i++) | |
14319 | { | |
14320 | c = *p++; | |
14321 | if (c >= ' ' && c < 0177) | |
14322 | { | |
14323 | if (for_string) | |
14324 | fputs (for_string, file); | |
14325 | putc (c, file); | |
14326 | ||
14327 | /* Write two quotes to get one. */ | |
14328 | if (c == '"') | |
14329 | { | |
14330 | putc (c, file); | |
14331 | ++count_string; | |
14332 | } | |
14333 | ||
14334 | for_string = NULL; | |
14335 | for_decimal = "\"\n\t.byte "; | |
14336 | to_close = "\"\n"; | |
14337 | ++count_string; | |
14338 | ||
14339 | if (count_string >= 512) | |
14340 | { | |
14341 | fputs (to_close, file); | |
14342 | ||
14343 | for_string = "\t.byte \""; | |
14344 | for_decimal = "\t.byte "; | |
14345 | to_close = NULL; | |
14346 | count_string = 0; | |
14347 | } | |
14348 | } | |
14349 | else | |
14350 | { | |
14351 | if (for_decimal) | |
14352 | fputs (for_decimal, file); | |
14353 | fprintf (file, "%d", c); | |
14354 | ||
14355 | for_string = "\n\t.byte \""; | |
14356 | for_decimal = ", "; | |
14357 | to_close = "\n"; | |
14358 | count_string = 0; | |
14359 | } | |
14360 | } | |
14361 | ||
14362 | /* Now close the string if we have written one. Then end the line. */ | |
14363 | if (to_close) | |
9ebbca7d | 14364 | fputs (to_close, file); |
9878760c RK |
14365 | } |
14366 | \f | |
14367 | /* Generate a unique section name for FILENAME for a section type | |
14368 | represented by SECTION_DESC. Output goes into BUF. | |
14369 | ||
14370 | SECTION_DESC can be any string, as long as it is different for each | |
14371 | possible section type. | |
14372 | ||
14373 | We name the section in the same manner as xlc. The name begins with an | |
14374 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
14375 | names) with the last period replaced by the string SECTION_DESC. If |
14376 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
14377 | the name. */ | |
9878760c RK |
14378 | |
14379 | void | |
a2369ed3 DJ |
14380 | rs6000_gen_section_name (char **buf, const char *filename, |
14381 | const char *section_desc) | |
9878760c | 14382 | { |
9ebbca7d | 14383 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
14384 | char *p; |
14385 | int len; | |
9878760c RK |
14386 | |
14387 | after_last_slash = filename; | |
14388 | for (q = filename; *q; q++) | |
11e5fe42 RK |
14389 | { |
14390 | if (*q == '/') | |
14391 | after_last_slash = q + 1; | |
14392 | else if (*q == '.') | |
14393 | last_period = q; | |
14394 | } | |
9878760c | 14395 | |
11e5fe42 | 14396 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 14397 | *buf = (char *) xmalloc (len); |
9878760c RK |
14398 | |
14399 | p = *buf; | |
14400 | *p++ = '_'; | |
14401 | ||
14402 | for (q = after_last_slash; *q; q++) | |
14403 | { | |
11e5fe42 | 14404 | if (q == last_period) |
9878760c RK |
14405 | { |
14406 | strcpy (p, section_desc); | |
14407 | p += strlen (section_desc); | |
e3981aab | 14408 | break; |
9878760c RK |
14409 | } |
14410 | ||
e9a780ec | 14411 | else if (ISALNUM (*q)) |
9878760c RK |
14412 | *p++ = *q; |
14413 | } | |
14414 | ||
11e5fe42 | 14415 | if (last_period == 0) |
9878760c RK |
14416 | strcpy (p, section_desc); |
14417 | else | |
14418 | *p = '\0'; | |
14419 | } | |
e165f3f0 | 14420 | \f |
a4f6c312 | 14421 | /* Emit profile function. */ |
411707f4 | 14422 | |
411707f4 | 14423 | void |
a2369ed3 | 14424 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 14425 | { |
ffcfcb5f AM |
14426 | if (TARGET_PROFILE_KERNEL) |
14427 | return; | |
14428 | ||
8480e480 CC |
14429 | if (DEFAULT_ABI == ABI_AIX) |
14430 | { | |
9739c90c JJ |
14431 | #ifndef NO_PROFILE_COUNTERS |
14432 | # define NO_PROFILE_COUNTERS 0 | |
14433 | #endif | |
14434 | if (NO_PROFILE_COUNTERS) | |
14435 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); | |
14436 | else | |
14437 | { | |
14438 | char buf[30]; | |
14439 | const char *label_name; | |
14440 | rtx fun; | |
411707f4 | 14441 | |
9739c90c JJ |
14442 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
14443 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
14444 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 14445 | |
9739c90c JJ |
14446 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
14447 | fun, Pmode); | |
14448 | } | |
8480e480 | 14449 | } |
ee890fe2 SS |
14450 | else if (DEFAULT_ABI == ABI_DARWIN) |
14451 | { | |
d5fa86ba | 14452 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
14453 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
14454 | ||
14455 | /* Be conservative and always set this, at least for now. */ | |
14456 | current_function_uses_pic_offset_table = 1; | |
14457 | ||
14458 | #if TARGET_MACHO | |
14459 | /* For PIC code, set up a stub and collect the caller's address | |
14460 | from r0, which is where the prologue puts it. */ | |
ab82a49f | 14461 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
14462 | { |
14463 | mcount_name = machopic_stub_name (mcount_name); | |
14464 | if (current_function_uses_pic_offset_table) | |
14465 | caller_addr_regno = 0; | |
14466 | } | |
14467 | #endif | |
14468 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
14469 | 0, VOIDmode, 1, | |
14470 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
14471 | } | |
411707f4 CC |
14472 | } |
14473 | ||
a4f6c312 | 14474 | /* Write function profiler code. */ |
e165f3f0 RK |
14475 | |
14476 | void | |
a2369ed3 | 14477 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 14478 | { |
3daf36a4 | 14479 | char buf[100]; |
09eeeacb | 14480 | int save_lr = 8; |
e165f3f0 | 14481 | |
38c1f2d7 | 14482 | switch (DEFAULT_ABI) |
3daf36a4 | 14483 | { |
38c1f2d7 MM |
14484 | default: |
14485 | abort (); | |
14486 | ||
14487 | case ABI_V4: | |
09eeeacb | 14488 | save_lr = 4; |
09eeeacb AM |
14489 | if (!TARGET_32BIT) |
14490 | { | |
14491 | warning ("no profiling of 64-bit code for this ABI"); | |
14492 | return; | |
14493 | } | |
ffcfcb5f | 14494 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 MM |
14495 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
14496 | if (flag_pic == 1) | |
14497 | { | |
dfdfa60f | 14498 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
09eeeacb AM |
14499 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14500 | reg_names[0], save_lr, reg_names[1]); | |
17167fd8 | 14501 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 14502 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 14503 | assemble_name (file, buf); |
17167fd8 | 14504 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 14505 | } |
9ebbca7d | 14506 | else if (flag_pic > 1) |
38c1f2d7 | 14507 | { |
09eeeacb AM |
14508 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14509 | reg_names[0], save_lr, reg_names[1]); | |
9ebbca7d GK |
14510 | /* Now, we need to get the address of the label. */ |
14511 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 14512 | assemble_name (file, buf); |
9ebbca7d GK |
14513 | fputs ("-.\n1:", file); |
14514 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
14515 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
14516 | reg_names[0], reg_names[11]); | |
14517 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
14518 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 14519 | } |
38c1f2d7 MM |
14520 | else |
14521 | { | |
17167fd8 | 14522 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 14523 | assemble_name (file, buf); |
dfdfa60f | 14524 | fputs ("@ha\n", file); |
09eeeacb AM |
14525 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14526 | reg_names[0], save_lr, reg_names[1]); | |
a260abc9 | 14527 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 14528 | assemble_name (file, buf); |
17167fd8 | 14529 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
14530 | } |
14531 | ||
50d440bc | 14532 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
3b6ce0af DE |
14533 | fprintf (file, "\tbl %s%s\n", |
14534 | RS6000_MCOUNT, flag_pic ? "@plt" : ""); | |
38c1f2d7 MM |
14535 | break; |
14536 | ||
14537 | case ABI_AIX: | |
ee890fe2 | 14538 | case ABI_DARWIN: |
ffcfcb5f AM |
14539 | if (!TARGET_PROFILE_KERNEL) |
14540 | { | |
a3c9585f | 14541 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
14542 | } |
14543 | else | |
14544 | { | |
14545 | if (TARGET_32BIT) | |
14546 | abort (); | |
14547 | ||
14548 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
14549 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
14550 | ||
6de9cd9a | 14551 | if (cfun->static_chain_decl != NULL) |
ffcfcb5f AM |
14552 | { |
14553 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
14554 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
14555 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
14556 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
14557 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
14558 | } | |
14559 | else | |
14560 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
14561 | } | |
38c1f2d7 MM |
14562 | break; |
14563 | } | |
e165f3f0 | 14564 | } |
a251ffd0 | 14565 | |
b54cf83a | 14566 | \f |
b54cf83a DE |
14567 | /* Power4 load update and store update instructions are cracked into a |
14568 | load or store and an integer insn which are executed in the same cycle. | |
14569 | Branches have their own dispatch slot which does not count against the | |
14570 | GCC issue rate, but it changes the program flow so there are no other | |
14571 | instructions to issue in this cycle. */ | |
14572 | ||
14573 | static int | |
a2369ed3 DJ |
14574 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
14575 | int verbose ATTRIBUTE_UNUSED, | |
14576 | rtx insn, int more) | |
b54cf83a DE |
14577 | { |
14578 | if (GET_CODE (PATTERN (insn)) == USE | |
14579 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14580 | return more; | |
14581 | ||
ec507f2d | 14582 | if (rs6000_sched_groups) |
b54cf83a | 14583 | { |
cbe26ab8 DN |
14584 | if (is_microcoded_insn (insn)) |
14585 | return 0; | |
14586 | else if (is_cracked_insn (insn)) | |
14587 | return more > 2 ? more - 2 : 0; | |
b54cf83a | 14588 | } |
165b263e DE |
14589 | |
14590 | return more - 1; | |
b54cf83a DE |
14591 | } |
14592 | ||
a251ffd0 TG |
14593 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
14594 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
14595 | ||
c237e94a | 14596 | static int |
a2369ed3 DJ |
14597 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED, |
14598 | int cost) | |
a251ffd0 TG |
14599 | { |
14600 | if (! recog_memoized (insn)) | |
14601 | return 0; | |
14602 | ||
14603 | if (REG_NOTE_KIND (link) != 0) | |
14604 | return 0; | |
14605 | ||
14606 | if (REG_NOTE_KIND (link) == 0) | |
14607 | { | |
ed947a96 DJ |
14608 | /* Data dependency; DEP_INSN writes a register that INSN reads |
14609 | some cycles later. */ | |
14610 | switch (get_attr_type (insn)) | |
14611 | { | |
14612 | case TYPE_JMPREG: | |
309323c2 | 14613 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
14614 | a mtctr and bctr (and mtlr and br/blr). The first |
14615 | scheduling pass will not know about this latency since | |
14616 | the mtctr instruction, which has the latency associated | |
14617 | to it, will be generated by reload. */ | |
309323c2 | 14618 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
14619 | case TYPE_BRANCH: |
14620 | /* Leave some extra cycles between a compare and its | |
14621 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
14622 | if ((rs6000_cpu_attr == CPU_PPC603 |
14623 | || rs6000_cpu_attr == CPU_PPC604 | |
14624 | || rs6000_cpu_attr == CPU_PPC604E | |
14625 | || rs6000_cpu_attr == CPU_PPC620 | |
14626 | || rs6000_cpu_attr == CPU_PPC630 | |
14627 | || rs6000_cpu_attr == CPU_PPC750 | |
14628 | || rs6000_cpu_attr == CPU_PPC7400 | |
14629 | || rs6000_cpu_attr == CPU_PPC7450 | |
ec507f2d DE |
14630 | || rs6000_cpu_attr == CPU_POWER4 |
14631 | || rs6000_cpu_attr == CPU_POWER5) | |
ed947a96 DJ |
14632 | && recog_memoized (dep_insn) |
14633 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
14634 | && (get_attr_type (dep_insn) == TYPE_CMP |
14635 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 14636 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
14637 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
14638 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 14639 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
14640 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
14641 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
14642 | return cost + 2; |
14643 | default: | |
14644 | break; | |
14645 | } | |
a251ffd0 TG |
14646 | /* Fall out to return default cost. */ |
14647 | } | |
14648 | ||
14649 | return cost; | |
14650 | } | |
b6c9286a | 14651 | |
cbe26ab8 | 14652 | /* The function returns a true if INSN is microcoded. |
839a4992 | 14653 | Return false otherwise. */ |
cbe26ab8 DN |
14654 | |
14655 | static bool | |
14656 | is_microcoded_insn (rtx insn) | |
14657 | { | |
14658 | if (!insn || !INSN_P (insn) | |
14659 | || GET_CODE (PATTERN (insn)) == USE | |
14660 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14661 | return false; | |
14662 | ||
ec507f2d | 14663 | if (rs6000_sched_groups) |
cbe26ab8 DN |
14664 | { |
14665 | enum attr_type type = get_attr_type (insn); | |
14666 | if (type == TYPE_LOAD_EXT_U | |
14667 | || type == TYPE_LOAD_EXT_UX | |
14668 | || type == TYPE_LOAD_UX | |
14669 | || type == TYPE_STORE_UX | |
14670 | || type == TYPE_MFCR) | |
14671 | return true; | |
14672 | } | |
14673 | ||
14674 | return false; | |
14675 | } | |
14676 | ||
5c425df5 | 14677 | /* The function returns a nonzero value if INSN can be scheduled only |
cbe26ab8 DN |
14678 | as the first insn in a dispatch group ("dispatch-slot restricted"). |
14679 | In this case, the returned value indicates how many dispatch slots | |
14680 | the insn occupies (at the beginning of the group). | |
79ae11c4 DN |
14681 | Return 0 otherwise. */ |
14682 | ||
cbe26ab8 | 14683 | static int |
79ae11c4 DN |
14684 | is_dispatch_slot_restricted (rtx insn) |
14685 | { | |
14686 | enum attr_type type; | |
14687 | ||
ec507f2d | 14688 | if (!rs6000_sched_groups) |
79ae11c4 DN |
14689 | return 0; |
14690 | ||
14691 | if (!insn | |
14692 | || insn == NULL_RTX | |
14693 | || GET_CODE (insn) == NOTE | |
14694 | || GET_CODE (PATTERN (insn)) == USE | |
14695 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14696 | return 0; | |
14697 | ||
14698 | type = get_attr_type (insn); | |
14699 | ||
ec507f2d DE |
14700 | switch (type) |
14701 | { | |
14702 | case TYPE_MFCR: | |
14703 | case TYPE_MFCRF: | |
14704 | case TYPE_MTCR: | |
14705 | case TYPE_DELAYED_CR: | |
14706 | case TYPE_CR_LOGICAL: | |
14707 | case TYPE_MTJMPR: | |
14708 | case TYPE_MFJMPR: | |
14709 | return 1; | |
14710 | case TYPE_IDIV: | |
14711 | case TYPE_LDIV: | |
14712 | return 2; | |
14713 | default: | |
14714 | if (rs6000_cpu == PROCESSOR_POWER5 | |
14715 | && is_cracked_insn (insn)) | |
14716 | return 2; | |
14717 | return 0; | |
14718 | } | |
79ae11c4 DN |
14719 | } |
14720 | ||
cbe26ab8 DN |
14721 | /* The function returns true if INSN is cracked into 2 instructions |
14722 | by the processor (and therefore occupies 2 issue slots). */ | |
14723 | ||
14724 | static bool | |
14725 | is_cracked_insn (rtx insn) | |
14726 | { | |
14727 | if (!insn || !INSN_P (insn) | |
14728 | || GET_CODE (PATTERN (insn)) == USE | |
14729 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14730 | return false; | |
14731 | ||
ec507f2d | 14732 | if (rs6000_sched_groups) |
cbe26ab8 DN |
14733 | { |
14734 | enum attr_type type = get_attr_type (insn); | |
14735 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
14736 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U | |
14737 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
14738 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
14739 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
14740 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
14741 | || type == TYPE_IDIV || type == TYPE_LDIV | |
14742 | || type == TYPE_INSERT_WORD) | |
14743 | return true; | |
14744 | } | |
14745 | ||
14746 | return false; | |
14747 | } | |
14748 | ||
14749 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 14750 | the branch slot. */ |
cbe26ab8 DN |
14751 | |
14752 | static bool | |
14753 | is_branch_slot_insn (rtx insn) | |
14754 | { | |
14755 | if (!insn || !INSN_P (insn) | |
14756 | || GET_CODE (PATTERN (insn)) == USE | |
14757 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14758 | return false; | |
14759 | ||
ec507f2d | 14760 | if (rs6000_sched_groups) |
cbe26ab8 DN |
14761 | { |
14762 | enum attr_type type = get_attr_type (insn); | |
14763 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
14764 | return true; | |
14765 | return false; | |
14766 | } | |
14767 | ||
14768 | return false; | |
14769 | } | |
79ae11c4 | 14770 | |
a4f6c312 | 14771 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
14772 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
14773 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
14774 | define this macro if you do not need to adjust the scheduling |
14775 | priorities of insns. */ | |
bef84347 | 14776 | |
c237e94a | 14777 | static int |
a2369ed3 | 14778 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 14779 | { |
a4f6c312 SS |
14780 | /* On machines (like the 750) which have asymmetric integer units, |
14781 | where one integer unit can do multiply and divides and the other | |
14782 | can't, reduce the priority of multiply/divide so it is scheduled | |
14783 | before other integer operations. */ | |
bef84347 VM |
14784 | |
14785 | #if 0 | |
2c3c49de | 14786 | if (! INSN_P (insn)) |
bef84347 VM |
14787 | return priority; |
14788 | ||
14789 | if (GET_CODE (PATTERN (insn)) == USE) | |
14790 | return priority; | |
14791 | ||
14792 | switch (rs6000_cpu_attr) { | |
14793 | case CPU_PPC750: | |
14794 | switch (get_attr_type (insn)) | |
14795 | { | |
14796 | default: | |
14797 | break; | |
14798 | ||
14799 | case TYPE_IMUL: | |
14800 | case TYPE_IDIV: | |
3cb999d8 DE |
14801 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
14802 | priority, priority); | |
bef84347 VM |
14803 | if (priority >= 0 && priority < 0x01000000) |
14804 | priority >>= 3; | |
14805 | break; | |
14806 | } | |
14807 | } | |
14808 | #endif | |
14809 | ||
79ae11c4 DN |
14810 | if (is_dispatch_slot_restricted (insn) |
14811 | && reload_completed | |
14812 | && current_sched_info->sched_max_insns_priority | |
14813 | && rs6000_sched_restricted_insns_priority) | |
14814 | { | |
14815 | ||
14816 | /* Prioritize insns that can be dispatched only in the first dispatch slot. */ | |
14817 | if (rs6000_sched_restricted_insns_priority == 1) | |
14818 | /* Attach highest priority to insn. This means that in | |
14819 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
14820 | precede 'priority' (critical path) considerations. */ | |
14821 | return current_sched_info->sched_max_insns_priority; | |
14822 | else if (rs6000_sched_restricted_insns_priority == 2) | |
14823 | /* Increase priority of insn by a minimal amount. This means that in | |
14824 | haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations | |
14825 | precede dispatch-slot restriction considerations. */ | |
14826 | return (priority + 1); | |
14827 | } | |
14828 | ||
bef84347 VM |
14829 | return priority; |
14830 | } | |
14831 | ||
a4f6c312 SS |
14832 | /* Return how many instructions the machine can issue per cycle. */ |
14833 | ||
c237e94a | 14834 | static int |
863d938c | 14835 | rs6000_issue_rate (void) |
b6c9286a | 14836 | { |
3317bab1 DE |
14837 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
14838 | if (!reload_completed) | |
14839 | return 1; | |
14840 | ||
b6c9286a | 14841 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
14842 | case CPU_RIOS1: /* ? */ |
14843 | case CPU_RS64A: | |
14844 | case CPU_PPC601: /* ? */ | |
ed947a96 | 14845 | case CPU_PPC7450: |
3cb999d8 | 14846 | return 3; |
b54cf83a | 14847 | case CPU_PPC440: |
b6c9286a | 14848 | case CPU_PPC603: |
bef84347 | 14849 | case CPU_PPC750: |
ed947a96 | 14850 | case CPU_PPC7400: |
be12c2b0 | 14851 | case CPU_PPC8540: |
bef84347 | 14852 | return 2; |
3cb999d8 | 14853 | case CPU_RIOS2: |
b6c9286a | 14854 | case CPU_PPC604: |
19684119 | 14855 | case CPU_PPC604E: |
b6c9286a | 14856 | case CPU_PPC620: |
3cb999d8 | 14857 | case CPU_PPC630: |
b6c9286a | 14858 | return 4; |
cbe26ab8 | 14859 | case CPU_POWER4: |
ec507f2d | 14860 | case CPU_POWER5: |
cbe26ab8 | 14861 | return 5; |
b6c9286a MM |
14862 | default: |
14863 | return 1; | |
14864 | } | |
14865 | } | |
14866 | ||
be12c2b0 VM |
14867 | /* Return how many instructions to look ahead for better insn |
14868 | scheduling. */ | |
14869 | ||
14870 | static int | |
863d938c | 14871 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
14872 | { |
14873 | if (rs6000_cpu_attr == CPU_PPC8540) | |
14874 | return 4; | |
14875 | return 0; | |
14876 | } | |
14877 | ||
569fa502 DN |
14878 | /* Determine is PAT refers to memory. */ |
14879 | ||
14880 | static bool | |
14881 | is_mem_ref (rtx pat) | |
14882 | { | |
14883 | const char * fmt; | |
14884 | int i, j; | |
14885 | bool ret = false; | |
14886 | ||
14887 | if (GET_CODE (pat) == MEM) | |
14888 | return true; | |
14889 | ||
14890 | /* Recursively process the pattern. */ | |
14891 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
14892 | ||
14893 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
14894 | { | |
14895 | if (fmt[i] == 'e') | |
14896 | ret |= is_mem_ref (XEXP (pat, i)); | |
14897 | else if (fmt[i] == 'E') | |
14898 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
14899 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
14900 | } | |
14901 | ||
14902 | return ret; | |
14903 | } | |
14904 | ||
14905 | /* Determine if PAT is a PATTERN of a load insn. */ | |
14906 | ||
14907 | static bool | |
14908 | is_load_insn1 (rtx pat) | |
14909 | { | |
14910 | if (!pat || pat == NULL_RTX) | |
14911 | return false; | |
14912 | ||
14913 | if (GET_CODE (pat) == SET) | |
14914 | return is_mem_ref (SET_SRC (pat)); | |
14915 | ||
14916 | if (GET_CODE (pat) == PARALLEL) | |
14917 | { | |
14918 | int i; | |
14919 | ||
14920 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
14921 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
14922 | return true; | |
14923 | } | |
14924 | ||
14925 | return false; | |
14926 | } | |
14927 | ||
14928 | /* Determine if INSN loads from memory. */ | |
14929 | ||
14930 | static bool | |
14931 | is_load_insn (rtx insn) | |
14932 | { | |
14933 | if (!insn || !INSN_P (insn)) | |
14934 | return false; | |
14935 | ||
14936 | if (GET_CODE (insn) == CALL_INSN) | |
14937 | return false; | |
14938 | ||
14939 | return is_load_insn1 (PATTERN (insn)); | |
14940 | } | |
14941 | ||
14942 | /* Determine if PAT is a PATTERN of a store insn. */ | |
14943 | ||
14944 | static bool | |
14945 | is_store_insn1 (rtx pat) | |
14946 | { | |
14947 | if (!pat || pat == NULL_RTX) | |
14948 | return false; | |
14949 | ||
14950 | if (GET_CODE (pat) == SET) | |
14951 | return is_mem_ref (SET_DEST (pat)); | |
14952 | ||
14953 | if (GET_CODE (pat) == PARALLEL) | |
14954 | { | |
14955 | int i; | |
14956 | ||
14957 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
14958 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
14959 | return true; | |
14960 | } | |
14961 | ||
14962 | return false; | |
14963 | } | |
14964 | ||
14965 | /* Determine if INSN stores to memory. */ | |
14966 | ||
14967 | static bool | |
14968 | is_store_insn (rtx insn) | |
14969 | { | |
14970 | if (!insn || !INSN_P (insn)) | |
14971 | return false; | |
14972 | ||
14973 | return is_store_insn1 (PATTERN (insn)); | |
14974 | } | |
14975 | ||
14976 | /* Returns whether the dependence between INSN and NEXT is considered | |
14977 | costly by the given target. */ | |
14978 | ||
14979 | static bool | |
14980 | rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance) | |
14981 | { | |
14982 | /* If the flag is not enbled - no dependence is considered costly; | |
14983 | allow all dependent insns in the same group. | |
14984 | This is the most aggressive option. */ | |
14985 | if (rs6000_sched_costly_dep == no_dep_costly) | |
14986 | return false; | |
14987 | ||
14988 | /* If the flag is set to 1 - a dependence is always considered costly; | |
14989 | do not allow dependent instructions in the same group. | |
14990 | This is the most conservative option. */ | |
14991 | if (rs6000_sched_costly_dep == all_deps_costly) | |
14992 | return true; | |
14993 | ||
14994 | if (rs6000_sched_costly_dep == store_to_load_dep_costly | |
14995 | && is_load_insn (next) | |
14996 | && is_store_insn (insn)) | |
14997 | /* Prevent load after store in the same group. */ | |
14998 | return true; | |
14999 | ||
15000 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
15001 | && is_load_insn (next) | |
15002 | && is_store_insn (insn) | |
15003 | && (!link || (int) REG_NOTE_KIND (link) == 0)) | |
15004 | /* Prevent load after store in the same group if it is a true dependence. */ | |
15005 | return true; | |
15006 | ||
15007 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
15008 | and will not be scheduled in the same group. */ | |
15009 | if (rs6000_sched_costly_dep <= max_dep_latency | |
15010 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
15011 | return true; | |
15012 | ||
15013 | return false; | |
15014 | } | |
15015 | ||
cbe26ab8 DN |
15016 | /* Return the next insn after INSN that is found before TAIL is reached, |
15017 | skipping any "non-active" insns - insns that will not actually occupy | |
15018 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
15019 | ||
15020 | static rtx | |
15021 | get_next_active_insn (rtx insn, rtx tail) | |
15022 | { | |
15023 | rtx next_insn; | |
15024 | ||
15025 | if (!insn || insn == tail) | |
15026 | return NULL_RTX; | |
15027 | ||
15028 | next_insn = NEXT_INSN (insn); | |
15029 | ||
15030 | while (next_insn | |
15031 | && next_insn != tail | |
15032 | && (GET_CODE(next_insn) == NOTE | |
15033 | || GET_CODE (PATTERN (next_insn)) == USE | |
15034 | || GET_CODE (PATTERN (next_insn)) == CLOBBER)) | |
15035 | { | |
15036 | next_insn = NEXT_INSN (next_insn); | |
15037 | } | |
15038 | ||
15039 | if (!next_insn || next_insn == tail) | |
15040 | return NULL_RTX; | |
15041 | ||
15042 | return next_insn; | |
15043 | } | |
15044 | ||
839a4992 | 15045 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
15046 | of group WHICH_GROUP. |
15047 | ||
15048 | If WHICH_GROUP == current_group, this function will return true if INSN | |
15049 | causes the termination of the current group (i.e, the dispatch group to | |
15050 | which INSN belongs). This means that INSN will be the last insn in the | |
15051 | group it belongs to. | |
15052 | ||
15053 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
15054 | causes the termination of the previous group (i.e, the dispatch group that | |
15055 | precedes the group to which INSN belongs). This means that INSN will be | |
15056 | the first insn in the group it belongs to). */ | |
15057 | ||
15058 | static bool | |
15059 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
15060 | { | |
15061 | enum attr_type type; | |
15062 | ||
15063 | if (! insn) | |
15064 | return false; | |
569fa502 | 15065 | |
cbe26ab8 DN |
15066 | type = get_attr_type (insn); |
15067 | ||
15068 | if (is_microcoded_insn (insn)) | |
15069 | return true; | |
15070 | ||
15071 | if (which_group == current_group) | |
15072 | { | |
15073 | if (is_branch_slot_insn (insn)) | |
15074 | return true; | |
15075 | return false; | |
15076 | } | |
15077 | else if (which_group == previous_group) | |
15078 | { | |
15079 | if (is_dispatch_slot_restricted (insn)) | |
15080 | return true; | |
15081 | return false; | |
15082 | } | |
15083 | ||
15084 | return false; | |
15085 | } | |
15086 | ||
839a4992 | 15087 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
15088 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
15089 | ||
15090 | static bool | |
15091 | is_costly_group (rtx *group_insns, rtx next_insn) | |
15092 | { | |
15093 | int i; | |
15094 | rtx link; | |
15095 | int cost; | |
15096 | int issue_rate = rs6000_issue_rate (); | |
15097 | ||
15098 | for (i = 0; i < issue_rate; i++) | |
15099 | { | |
15100 | rtx insn = group_insns[i]; | |
15101 | if (!insn) | |
15102 | continue; | |
15103 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) | |
15104 | { | |
15105 | rtx next = XEXP (link, 0); | |
15106 | if (next == next_insn) | |
15107 | { | |
15108 | cost = insn_cost (insn, link, next_insn); | |
15109 | if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) | |
15110 | return true; | |
15111 | } | |
15112 | } | |
15113 | } | |
15114 | ||
15115 | return false; | |
15116 | } | |
15117 | ||
15118 | /* Utility of the function redefine_groups. | |
15119 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS | |
15120 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
15121 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
15122 | one of the following schemes, depending on the value of the flag | |
15123 | -minsert_sched_nops = X: | |
15124 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 15125 | in order to force NEXT_INSN into a separate group. |
cbe26ab8 DN |
15126 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
15127 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
15128 | insertion (has a group just ended, how many vacant issue slots remain in the | |
15129 | last group, and how many dispatch groups were encountered so far). */ | |
15130 | ||
15131 | static int | |
15132 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn, | |
15133 | bool *group_end, int can_issue_more, int *group_count) | |
15134 | { | |
15135 | rtx nop; | |
15136 | bool force; | |
15137 | int issue_rate = rs6000_issue_rate (); | |
15138 | bool end = *group_end; | |
15139 | int i; | |
15140 | ||
15141 | if (next_insn == NULL_RTX) | |
15142 | return can_issue_more; | |
15143 | ||
15144 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
15145 | return can_issue_more; | |
15146 | ||
15147 | force = is_costly_group (group_insns, next_insn); | |
15148 | if (!force) | |
15149 | return can_issue_more; | |
15150 | ||
15151 | if (sched_verbose > 6) | |
15152 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
15153 | *group_count ,can_issue_more); | |
15154 | ||
15155 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
15156 | { | |
15157 | if (*group_end) | |
15158 | can_issue_more = 0; | |
15159 | ||
15160 | /* Since only a branch can be issued in the last issue_slot, it is | |
15161 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
15162 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
15163 | in this case the last nop will start a new group and the branch will be | |
15164 | forced to the new group. */ | |
15165 | if (can_issue_more && !is_branch_slot_insn (next_insn)) | |
15166 | can_issue_more--; | |
15167 | ||
15168 | while (can_issue_more > 0) | |
15169 | { | |
15170 | nop = gen_nop(); | |
15171 | emit_insn_before (nop, next_insn); | |
15172 | can_issue_more--; | |
15173 | } | |
15174 | ||
15175 | *group_end = true; | |
15176 | return 0; | |
15177 | } | |
15178 | ||
15179 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
15180 | { | |
15181 | int n_nops = rs6000_sched_insert_nops; | |
15182 | ||
15183 | /* Nops can't be issued from the branch slot, so the effective | |
15184 | issue_rate for nops is 'issue_rate - 1'. */ | |
15185 | if (can_issue_more == 0) | |
15186 | can_issue_more = issue_rate; | |
15187 | can_issue_more--; | |
15188 | if (can_issue_more == 0) | |
15189 | { | |
15190 | can_issue_more = issue_rate - 1; | |
15191 | (*group_count)++; | |
15192 | end = true; | |
15193 | for (i = 0; i < issue_rate; i++) | |
15194 | { | |
15195 | group_insns[i] = 0; | |
15196 | } | |
15197 | } | |
15198 | ||
15199 | while (n_nops > 0) | |
15200 | { | |
15201 | nop = gen_nop (); | |
15202 | emit_insn_before (nop, next_insn); | |
15203 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
15204 | end = false; | |
15205 | can_issue_more--; | |
15206 | if (can_issue_more == 0) | |
15207 | { | |
15208 | can_issue_more = issue_rate - 1; | |
15209 | (*group_count)++; | |
15210 | end = true; | |
15211 | for (i = 0; i < issue_rate; i++) | |
15212 | { | |
15213 | group_insns[i] = 0; | |
15214 | } | |
15215 | } | |
15216 | n_nops--; | |
15217 | } | |
15218 | ||
15219 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
15220 | can_issue_more++; | |
15221 | ||
15222 | *group_end = /* Is next_insn going to start a new group? */ | |
15223 | (end | |
15224 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
15225 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
15226 | || (can_issue_more < issue_rate && | |
15227 | insn_terminates_group_p (next_insn, previous_group))); | |
15228 | if (*group_end && end) | |
15229 | (*group_count)--; | |
15230 | ||
15231 | if (sched_verbose > 6) | |
15232 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", | |
15233 | *group_count, can_issue_more); | |
15234 | return can_issue_more; | |
15235 | } | |
15236 | ||
15237 | return can_issue_more; | |
15238 | } | |
15239 | ||
15240 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
15241 | with the dispatch groups that the processor dispatcher is expected to | |
15242 | form in practice. It tries to achieve this synchronization by forcing the | |
15243 | estimated processor grouping on the compiler (as opposed to the function | |
15244 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
15245 | ||
15246 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
15247 | examines the (estimated) dispatch groups that will be formed by the processor | |
15248 | dispatcher. It marks these group boundaries to reflect the estimated | |
15249 | processor grouping, overriding the grouping that the scheduler had marked. | |
15250 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
15251 | force certain insns into separate groups or force a certain distance between | |
15252 | them by inserting nops, for example, if there exists a "costly dependence" | |
15253 | between the insns. | |
15254 | ||
15255 | The function estimates the group boundaries that the processor will form as | |
15256 | folllows: It keeps track of how many vacant issue slots are available after | |
15257 | each insn. A subsequent insn will start a new group if one of the following | |
15258 | 4 cases applies: | |
15259 | - no more vacant issue slots remain in the current dispatch group. | |
15260 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
15261 | insn is not a branch. | |
15262 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
15263 | which means that a cracked insn (which occupies two issue slots) can't be | |
15264 | issued in this group. | |
15265 | - less than 'issue_rate' slots are vacant, and the next insn always needs to | |
15266 | start a new group. */ | |
15267 | ||
15268 | static int | |
15269 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
15270 | { | |
15271 | rtx insn, next_insn; | |
15272 | int issue_rate; | |
15273 | int can_issue_more; | |
15274 | int slot, i; | |
15275 | bool group_end; | |
15276 | int group_count = 0; | |
15277 | rtx *group_insns; | |
15278 | ||
15279 | /* Initialize. */ | |
15280 | issue_rate = rs6000_issue_rate (); | |
15281 | group_insns = alloca (issue_rate * sizeof (rtx)); | |
15282 | for (i = 0; i < issue_rate; i++) | |
15283 | { | |
15284 | group_insns[i] = 0; | |
15285 | } | |
15286 | can_issue_more = issue_rate; | |
15287 | slot = 0; | |
15288 | insn = get_next_active_insn (prev_head_insn, tail); | |
15289 | group_end = false; | |
15290 | ||
15291 | while (insn != NULL_RTX) | |
15292 | { | |
15293 | slot = (issue_rate - can_issue_more); | |
15294 | group_insns[slot] = insn; | |
15295 | can_issue_more = | |
15296 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
15297 | if (insn_terminates_group_p (insn, current_group)) | |
15298 | can_issue_more = 0; | |
15299 | ||
15300 | next_insn = get_next_active_insn (insn, tail); | |
15301 | if (next_insn == NULL_RTX) | |
15302 | return group_count + 1; | |
15303 | ||
15304 | group_end = /* Is next_insn going to start a new group? */ | |
15305 | (can_issue_more == 0 | |
15306 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
15307 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
15308 | || (can_issue_more < issue_rate && | |
15309 | insn_terminates_group_p (next_insn, previous_group))); | |
15310 | ||
15311 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, | |
15312 | next_insn, &group_end, can_issue_more, &group_count); | |
15313 | ||
15314 | if (group_end) | |
15315 | { | |
15316 | group_count++; | |
15317 | can_issue_more = 0; | |
15318 | for (i = 0; i < issue_rate; i++) | |
15319 | { | |
15320 | group_insns[i] = 0; | |
15321 | } | |
15322 | } | |
15323 | ||
15324 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
15325 | PUT_MODE(next_insn, VOIDmode); | |
15326 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) | |
15327 | PUT_MODE (next_insn, TImode); | |
15328 | ||
15329 | insn = next_insn; | |
15330 | if (can_issue_more == 0) | |
15331 | can_issue_more = issue_rate; | |
15332 | } /* while */ | |
15333 | ||
15334 | return group_count; | |
15335 | } | |
15336 | ||
15337 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
15338 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
15339 | any dispatch groups which have vacant issue slots, in order to force the | |
15340 | scheduler's grouping on the processor dispatcher. The function | |
15341 | returns the number of dispatch groups found. */ | |
15342 | ||
15343 | static int | |
15344 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
15345 | { | |
15346 | rtx insn, next_insn; | |
15347 | rtx nop; | |
15348 | int issue_rate; | |
15349 | int can_issue_more; | |
15350 | int group_end; | |
15351 | int group_count = 0; | |
15352 | ||
15353 | /* Initialize issue_rate. */ | |
15354 | issue_rate = rs6000_issue_rate (); | |
15355 | can_issue_more = issue_rate; | |
15356 | ||
15357 | insn = get_next_active_insn (prev_head_insn, tail); | |
15358 | next_insn = get_next_active_insn (insn, tail); | |
15359 | ||
15360 | while (insn != NULL_RTX) | |
15361 | { | |
15362 | can_issue_more = | |
15363 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
15364 | ||
15365 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
15366 | ||
15367 | if (next_insn == NULL_RTX) | |
15368 | break; | |
15369 | ||
15370 | if (group_end) | |
15371 | { | |
15372 | /* If the scheduler had marked group termination at this location | |
15373 | (between insn and next_indn), and neither insn nor next_insn will | |
15374 | force group termination, pad the group with nops to force group | |
15375 | termination. */ | |
15376 | if (can_issue_more | |
15377 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
15378 | && !insn_terminates_group_p (insn, current_group) | |
15379 | && !insn_terminates_group_p (next_insn, previous_group)) | |
15380 | { | |
15381 | if (!is_branch_slot_insn(next_insn)) | |
15382 | can_issue_more--; | |
15383 | ||
15384 | while (can_issue_more) | |
15385 | { | |
15386 | nop = gen_nop (); | |
15387 | emit_insn_before (nop, next_insn); | |
15388 | can_issue_more--; | |
15389 | } | |
15390 | } | |
15391 | ||
15392 | can_issue_more = issue_rate; | |
15393 | group_count++; | |
15394 | } | |
15395 | ||
15396 | insn = next_insn; | |
15397 | next_insn = get_next_active_insn (insn, tail); | |
15398 | } | |
15399 | ||
15400 | return group_count; | |
15401 | } | |
15402 | ||
15403 | /* The following function is called at the end of scheduling BB. | |
15404 | After reload, it inserts nops at insn group bundling. */ | |
15405 | ||
15406 | static void | |
38f391a5 | 15407 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
15408 | { |
15409 | int n_groups; | |
15410 | ||
15411 | if (sched_verbose) | |
15412 | fprintf (dump, "=== Finishing schedule.\n"); | |
15413 | ||
ec507f2d | 15414 | if (reload_completed && rs6000_sched_groups) |
cbe26ab8 DN |
15415 | { |
15416 | if (rs6000_sched_insert_nops == sched_finish_none) | |
15417 | return; | |
15418 | ||
15419 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
15420 | n_groups = pad_groups (dump, sched_verbose, | |
15421 | current_sched_info->prev_head, | |
15422 | current_sched_info->next_tail); | |
15423 | else | |
15424 | n_groups = redefine_groups (dump, sched_verbose, | |
15425 | current_sched_info->prev_head, | |
15426 | current_sched_info->next_tail); | |
15427 | ||
15428 | if (sched_verbose >= 6) | |
15429 | { | |
15430 | fprintf (dump, "ngroups = %d\n", n_groups); | |
15431 | print_rtl (dump, current_sched_info->prev_head); | |
15432 | fprintf (dump, "Done finish_sched\n"); | |
15433 | } | |
15434 | } | |
15435 | } | |
b6c9286a | 15436 | \f |
b6c9286a MM |
15437 | /* Length in units of the trampoline for entering a nested function. */ |
15438 | ||
15439 | int | |
863d938c | 15440 | rs6000_trampoline_size (void) |
b6c9286a MM |
15441 | { |
15442 | int ret = 0; | |
15443 | ||
15444 | switch (DEFAULT_ABI) | |
15445 | { | |
15446 | default: | |
15447 | abort (); | |
15448 | ||
15449 | case ABI_AIX: | |
8f802bfb | 15450 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
15451 | break; |
15452 | ||
4dabc42d | 15453 | case ABI_DARWIN: |
b6c9286a | 15454 | case ABI_V4: |
03a7e1a5 | 15455 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 15456 | break; |
b6c9286a MM |
15457 | } |
15458 | ||
15459 | return ret; | |
15460 | } | |
15461 | ||
15462 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
15463 | FNADDR is an RTX for the address of the function's pure code. | |
15464 | CXT is an RTX for the static chain value for the function. */ | |
15465 | ||
15466 | void | |
a2369ed3 | 15467 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 15468 | { |
ac2a93a1 | 15469 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
15470 | int regsize = (TARGET_32BIT) ? 4 : 8; |
15471 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
15472 | |
15473 | switch (DEFAULT_ABI) | |
15474 | { | |
15475 | default: | |
15476 | abort (); | |
15477 | ||
8bd04c56 | 15478 | /* Macros to shorten the code expansions below. */ |
39403d82 | 15479 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
15480 | #define MEM_PLUS(addr,offset) \ |
15481 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 15482 | |
b6c9286a MM |
15483 | /* Under AIX, just build the 3 word function descriptor */ |
15484 | case ABI_AIX: | |
8bd04c56 MM |
15485 | { |
15486 | rtx fn_reg = gen_reg_rtx (pmode); | |
15487 | rtx toc_reg = gen_reg_rtx (pmode); | |
15488 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 15489 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
15490 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
15491 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
15492 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
15493 | } | |
b6c9286a MM |
15494 | break; |
15495 | ||
4dabc42d TC |
15496 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
15497 | case ABI_DARWIN: | |
b6c9286a | 15498 | case ABI_V4: |
39403d82 | 15499 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
15500 | FALSE, VOIDmode, 4, |
15501 | addr, pmode, | |
15502 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
15503 | fnaddr, pmode, | |
15504 | ctx_reg, pmode); | |
b6c9286a | 15505 | break; |
b6c9286a MM |
15506 | } |
15507 | ||
15508 | return; | |
15509 | } | |
7509c759 MM |
15510 | |
15511 | \f | |
91d231cb | 15512 | /* Table of valid machine attributes. */ |
a4f6c312 | 15513 | |
91d231cb | 15514 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 15515 | { |
91d231cb | 15516 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8bb418a3 | 15517 | { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, |
a5c76ee6 ZW |
15518 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
15519 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
15520 | { NULL, 0, 0, false, false, false, NULL } | |
91d231cb | 15521 | }; |
7509c759 | 15522 | |
8bb418a3 ZL |
15523 | /* Handle the "altivec" attribute. The attribute may have |
15524 | arguments as follows: | |
15525 | ||
15526 | __attribute__((altivec(vector__))) | |
15527 | __attribute__((altivec(pixel__))) (always followed by 'unsigned short') | |
15528 | __attribute__((altivec(bool__))) (always followed by 'unsigned') | |
15529 | ||
15530 | and may appear more than once (e.g., 'vector bool char') in a | |
15531 | given declaration. */ | |
15532 | ||
15533 | static tree | |
15534 | rs6000_handle_altivec_attribute (tree *node, tree name, tree args, | |
15535 | int flags ATTRIBUTE_UNUSED, | |
15536 | bool *no_add_attrs) | |
15537 | { | |
15538 | tree type = *node, result = NULL_TREE; | |
15539 | enum machine_mode mode; | |
15540 | int unsigned_p; | |
15541 | char altivec_type | |
15542 | = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) | |
15543 | && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) | |
15544 | ? *IDENTIFIER_POINTER (TREE_VALUE (args)) | |
15545 | : '?'); | |
15546 | ||
15547 | while (POINTER_TYPE_P (type) | |
15548 | || TREE_CODE (type) == FUNCTION_TYPE | |
15549 | || TREE_CODE (type) == METHOD_TYPE | |
15550 | || TREE_CODE (type) == ARRAY_TYPE) | |
15551 | type = TREE_TYPE (type); | |
15552 | ||
15553 | mode = TYPE_MODE (type); | |
15554 | ||
15555 | if (rs6000_warn_altivec_long | |
15556 | && (type == long_unsigned_type_node || type == long_integer_type_node)) | |
15557 | warning ("use of 'long' in AltiVec types is deprecated; use 'int'"); | |
15558 | ||
15559 | switch (altivec_type) | |
15560 | { | |
15561 | case 'v': | |
8df83eae | 15562 | unsigned_p = TYPE_UNSIGNED (type); |
8bb418a3 ZL |
15563 | switch (mode) |
15564 | { | |
15565 | case SImode: | |
15566 | result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); | |
15567 | break; | |
15568 | case HImode: | |
15569 | result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); | |
15570 | break; | |
15571 | case QImode: | |
15572 | result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); | |
15573 | break; | |
15574 | case SFmode: result = V4SF_type_node; break; | |
15575 | /* If the user says 'vector int bool', we may be handed the 'bool' | |
15576 | attribute _before_ the 'vector' attribute, and so select the proper | |
15577 | type in the 'b' case below. */ | |
15578 | case V4SImode: case V8HImode: case V16QImode: result = type; | |
15579 | default: break; | |
15580 | } | |
15581 | break; | |
15582 | case 'b': | |
15583 | switch (mode) | |
15584 | { | |
15585 | case SImode: case V4SImode: result = bool_V4SI_type_node; break; | |
15586 | case HImode: case V8HImode: result = bool_V8HI_type_node; break; | |
15587 | case QImode: case V16QImode: result = bool_V16QI_type_node; | |
15588 | default: break; | |
15589 | } | |
15590 | break; | |
15591 | case 'p': | |
15592 | switch (mode) | |
15593 | { | |
15594 | case V8HImode: result = pixel_V8HI_type_node; | |
15595 | default: break; | |
15596 | } | |
15597 | default: break; | |
15598 | } | |
15599 | ||
7958a2a6 FJ |
15600 | if (result && result != type && TYPE_READONLY (type)) |
15601 | result = build_qualified_type (result, TYPE_QUAL_CONST); | |
15602 | ||
8bb418a3 ZL |
15603 | *no_add_attrs = true; /* No need to hang on to the attribute. */ |
15604 | ||
15605 | if (!result) | |
15606 | warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); | |
15607 | else | |
15608 | *node = reconstruct_complex_type (*node, result); | |
15609 | ||
15610 | return NULL_TREE; | |
15611 | } | |
15612 | ||
f18eca82 ZL |
15613 | /* AltiVec defines four built-in scalar types that serve as vector |
15614 | elements; we must teach the compiler how to mangle them. */ | |
15615 | ||
15616 | static const char * | |
15617 | rs6000_mangle_fundamental_type (tree type) | |
15618 | { | |
15619 | if (type == bool_char_type_node) return "U6__boolc"; | |
15620 | if (type == bool_short_type_node) return "U6__bools"; | |
15621 | if (type == pixel_type_node) return "u7__pixel"; | |
15622 | if (type == bool_int_type_node) return "U6__booli"; | |
15623 | ||
15624 | /* For all other types, use normal C++ mangling. */ | |
15625 | return NULL; | |
15626 | } | |
15627 | ||
a5c76ee6 ZW |
15628 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
15629 | struct attribute_spec.handler. */ | |
a4f6c312 | 15630 | |
91d231cb | 15631 | static tree |
a2369ed3 DJ |
15632 | rs6000_handle_longcall_attribute (tree *node, tree name, |
15633 | tree args ATTRIBUTE_UNUSED, | |
15634 | int flags ATTRIBUTE_UNUSED, | |
15635 | bool *no_add_attrs) | |
91d231cb JM |
15636 | { |
15637 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
15638 | && TREE_CODE (*node) != FIELD_DECL | |
15639 | && TREE_CODE (*node) != TYPE_DECL) | |
15640 | { | |
15641 | warning ("`%s' attribute only applies to functions", | |
15642 | IDENTIFIER_POINTER (name)); | |
15643 | *no_add_attrs = true; | |
15644 | } | |
6a4cee5f | 15645 | |
91d231cb | 15646 | return NULL_TREE; |
7509c759 MM |
15647 | } |
15648 | ||
a5c76ee6 ZW |
15649 | /* Set longcall attributes on all functions declared when |
15650 | rs6000_default_long_calls is true. */ | |
15651 | static void | |
a2369ed3 | 15652 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
15653 | { |
15654 | if (rs6000_default_long_calls | |
15655 | && (TREE_CODE (type) == FUNCTION_TYPE | |
15656 | || TREE_CODE (type) == METHOD_TYPE)) | |
15657 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
15658 | NULL_TREE, | |
15659 | TYPE_ATTRIBUTES (type)); | |
15660 | } | |
15661 | ||
3cb999d8 DE |
15662 | /* Return a reference suitable for calling a function with the |
15663 | longcall attribute. */ | |
a4f6c312 | 15664 | |
6a4cee5f | 15665 | struct rtx_def * |
a2369ed3 | 15666 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 15667 | { |
d330fd93 | 15668 | const char *call_name; |
6a4cee5f MM |
15669 | tree node; |
15670 | ||
15671 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
15672 | return call_ref; | |
15673 | ||
15674 | /* System V adds '.' to the internal name, so skip them. */ | |
15675 | call_name = XSTR (call_ref, 0); | |
15676 | if (*call_name == '.') | |
15677 | { | |
15678 | while (*call_name == '.') | |
15679 | call_name++; | |
15680 | ||
15681 | node = get_identifier (call_name); | |
39403d82 | 15682 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
15683 | } |
15684 | ||
15685 | return force_reg (Pmode, call_ref); | |
15686 | } | |
7509c759 | 15687 | \f |
b64a1b53 RH |
15688 | #ifdef USING_ELFOS_H |
15689 | ||
7509c759 MM |
15690 | /* A C statement or statements to switch to the appropriate section |
15691 | for output of RTX in mode MODE. You can assume that RTX is some | |
15692 | kind of constant in RTL. The argument MODE is redundant except in | |
15693 | the case of a `const_int' rtx. Select the section by calling | |
15694 | `text_section' or one of the alternatives for other sections. | |
15695 | ||
15696 | Do not define this macro if you put all constants in the read-only | |
15697 | data section. */ | |
15698 | ||
b64a1b53 | 15699 | static void |
a2369ed3 DJ |
15700 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
15701 | unsigned HOST_WIDE_INT align) | |
7509c759 | 15702 | { |
a9098fd0 | 15703 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 15704 | toc_section (); |
7509c759 | 15705 | else |
b64a1b53 | 15706 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
15707 | } |
15708 | ||
15709 | /* A C statement or statements to switch to the appropriate | |
15710 | section for output of DECL. DECL is either a `VAR_DECL' node | |
15711 | or a constant of some sort. RELOC indicates whether forming | |
15712 | the initial value of DECL requires link-time relocations. */ | |
15713 | ||
ae46c4e0 | 15714 | static void |
a2369ed3 DJ |
15715 | rs6000_elf_select_section (tree decl, int reloc, |
15716 | unsigned HOST_WIDE_INT align) | |
7509c759 | 15717 | { |
f1384257 AM |
15718 | /* Pretend that we're always building for a shared library when |
15719 | ABI_AIX, because otherwise we end up with dynamic relocations | |
15720 | in read-only sections. This happens for function pointers, | |
15721 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
15722 | default_elf_select_section_1 (decl, reloc, align, |
15723 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
15724 | } |
15725 | ||
15726 | /* A C statement to build up a unique section name, expressed as a | |
15727 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
15728 | RELOC indicates whether the initial value of EXP requires | |
15729 | link-time relocations. If you do not define this macro, GCC will use | |
15730 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 15731 | macro can now be called for uninitialized data items as well as |
4912a07c | 15732 | initialized data and functions. */ |
63019373 | 15733 | |
ae46c4e0 | 15734 | static void |
a2369ed3 | 15735 | rs6000_elf_unique_section (tree decl, int reloc) |
63019373 | 15736 | { |
f1384257 AM |
15737 | /* As above, pretend that we're always building for a shared library |
15738 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
15739 | default_unique_section_1 (decl, reloc, |
15740 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 15741 | } |
d9407988 | 15742 | \f |
d1908feb JJ |
15743 | /* For a SYMBOL_REF, set generic flags and then perform some |
15744 | target-specific processing. | |
15745 | ||
d1908feb JJ |
15746 | When the AIX ABI is requested on a non-AIX system, replace the |
15747 | function name with the real name (with a leading .) rather than the | |
15748 | function descriptor name. This saves a lot of overriding code to | |
15749 | read the prefixes. */ | |
d9407988 | 15750 | |
fb49053f | 15751 | static void |
a2369ed3 | 15752 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 15753 | { |
d1908feb | 15754 | default_encode_section_info (decl, rtl, first); |
b2003250 | 15755 | |
d1908feb JJ |
15756 | if (first |
15757 | && TREE_CODE (decl) == FUNCTION_DECL | |
15758 | && !TARGET_AIX | |
15759 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 15760 | { |
c6a2438a | 15761 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
15762 | size_t len = strlen (XSTR (sym_ref, 0)); |
15763 | char *str = alloca (len + 2); | |
15764 | str[0] = '.'; | |
15765 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
15766 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 15767 | } |
d9407988 MM |
15768 | } |
15769 | ||
0e5dbd9b | 15770 | static bool |
a2369ed3 | 15771 | rs6000_elf_in_small_data_p (tree decl) |
0e5dbd9b DE |
15772 | { |
15773 | if (rs6000_sdata == SDATA_NONE) | |
15774 | return false; | |
15775 | ||
15776 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) | |
15777 | { | |
15778 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
15779 | if (strcmp (section, ".sdata") == 0 | |
15780 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
15781 | || strcmp (section, ".sbss") == 0 |
15782 | || strcmp (section, ".sbss2") == 0 | |
15783 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
15784 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
15785 | return true; |
15786 | } | |
15787 | else | |
15788 | { | |
15789 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
15790 | ||
15791 | if (size > 0 | |
307b599c | 15792 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
15793 | /* If it's not public, and we're not going to reference it there, |
15794 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
15795 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
15796 | return true; | |
15797 | } | |
15798 | ||
15799 | return false; | |
15800 | } | |
15801 | ||
b91da81f | 15802 | #endif /* USING_ELFOS_H */ |
000034eb | 15803 | |
a6c2a102 | 15804 | \f |
000034eb | 15805 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
15806 | ADDR can be effectively incremented by incrementing REG. |
15807 | ||
15808 | r0 is special and we must not select it as an address | |
15809 | register by this routine since our caller will try to | |
15810 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
15811 | |
15812 | struct rtx_def * | |
a2369ed3 | 15813 | find_addr_reg (rtx addr) |
000034eb DE |
15814 | { |
15815 | while (GET_CODE (addr) == PLUS) | |
15816 | { | |
02441cd6 JL |
15817 | if (GET_CODE (XEXP (addr, 0)) == REG |
15818 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 15819 | addr = XEXP (addr, 0); |
02441cd6 JL |
15820 | else if (GET_CODE (XEXP (addr, 1)) == REG |
15821 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
15822 | addr = XEXP (addr, 1); |
15823 | else if (CONSTANT_P (XEXP (addr, 0))) | |
15824 | addr = XEXP (addr, 1); | |
15825 | else if (CONSTANT_P (XEXP (addr, 1))) | |
15826 | addr = XEXP (addr, 0); | |
15827 | else | |
15828 | abort (); | |
15829 | } | |
02441cd6 | 15830 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
15831 | return addr; |
15832 | abort (); | |
15833 | } | |
15834 | ||
a6c2a102 | 15835 | void |
a2369ed3 | 15836 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
15837 | { |
15838 | fatal_insn ("bad address", op); | |
15839 | } | |
c8023011 | 15840 | |
ee890fe2 SS |
15841 | #if TARGET_MACHO |
15842 | ||
15843 | #if 0 | |
15844 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
15845 | reference and a constant. */ | |
15846 | ||
15847 | int | |
a2369ed3 | 15848 | symbolic_operand (rtx op) |
ee890fe2 SS |
15849 | { |
15850 | switch (GET_CODE (op)) | |
15851 | { | |
15852 | case SYMBOL_REF: | |
15853 | case LABEL_REF: | |
15854 | return 1; | |
15855 | case CONST: | |
15856 | op = XEXP (op, 0); | |
15857 | return (GET_CODE (op) == SYMBOL_REF || | |
15858 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
15859 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
15860 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
15861 | default: | |
15862 | return 0; | |
15863 | } | |
c8023011 | 15864 | } |
ee890fe2 SS |
15865 | #endif |
15866 | ||
efdba735 | 15867 | #if TARGET_MACHO |
ee890fe2 | 15868 | |
efdba735 | 15869 | static tree branch_island_list = 0; |
ee890fe2 | 15870 | |
efdba735 SH |
15871 | /* Remember to generate a branch island for far calls to the given |
15872 | function. */ | |
ee890fe2 | 15873 | |
efdba735 SH |
15874 | static void |
15875 | add_compiler_branch_island (tree label_name, tree function_name, int line_number) | |
ee890fe2 | 15876 | { |
efdba735 SH |
15877 | tree branch_island = build_tree_list (function_name, label_name); |
15878 | TREE_TYPE (branch_island) = build_int_2 (line_number, 0); | |
15879 | TREE_CHAIN (branch_island) = branch_island_list; | |
15880 | branch_island_list = branch_island; | |
ee890fe2 SS |
15881 | } |
15882 | ||
efdba735 SH |
15883 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
15884 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
15885 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
15886 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 15887 | |
efdba735 SH |
15888 | /* Generate far-jump branch islands for everything on the |
15889 | branch_island_list. Invoked immediately after the last instruction | |
15890 | of the epilogue has been emitted; the branch-islands must be | |
15891 | appended to, and contiguous with, the function body. Mach-O stubs | |
15892 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 15893 | |
efdba735 SH |
15894 | static void |
15895 | macho_branch_islands (void) | |
15896 | { | |
15897 | char tmp_buf[512]; | |
15898 | tree branch_island; | |
15899 | ||
15900 | for (branch_island = branch_island_list; | |
15901 | branch_island; | |
15902 | branch_island = TREE_CHAIN (branch_island)) | |
15903 | { | |
15904 | const char *label = | |
15905 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
15906 | const char *name = | |
15907 | darwin_strip_name_encoding ( | |
15908 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island))); | |
15909 | char name_buf[512]; | |
15910 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
15911 | if (name[0] == '*' || name[0] == '&') | |
15912 | strcpy (name_buf, name+1); | |
15913 | else | |
15914 | { | |
15915 | name_buf[0] = '_'; | |
15916 | strcpy (name_buf+1, name); | |
15917 | } | |
15918 | strcpy (tmp_buf, "\n"); | |
15919 | strcat (tmp_buf, label); | |
ee890fe2 | 15920 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 15921 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
f7efd730 | 15922 | fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n", |
efdba735 | 15923 | BRANCH_ISLAND_LINE_NUMBER(branch_island)); |
ee890fe2 | 15924 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
15925 | if (flag_pic) |
15926 | { | |
15927 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
15928 | strcat (tmp_buf, label); | |
15929 | strcat (tmp_buf, "_pic\n"); | |
15930 | strcat (tmp_buf, label); | |
15931 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
15932 | ||
15933 | strcat (tmp_buf, "\taddis r11,r11,ha16("); | |
15934 | strcat (tmp_buf, name_buf); | |
15935 | strcat (tmp_buf, " - "); | |
15936 | strcat (tmp_buf, label); | |
15937 | strcat (tmp_buf, "_pic)\n"); | |
15938 | ||
15939 | strcat (tmp_buf, "\tmtlr r0\n"); | |
15940 | ||
15941 | strcat (tmp_buf, "\taddi r12,r11,lo16("); | |
15942 | strcat (tmp_buf, name_buf); | |
15943 | strcat (tmp_buf, " - "); | |
15944 | strcat (tmp_buf, label); | |
15945 | strcat (tmp_buf, "_pic)\n"); | |
15946 | ||
15947 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); | |
15948 | } | |
15949 | else | |
15950 | { | |
15951 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
15952 | strcat (tmp_buf, name_buf); | |
15953 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
15954 | strcat (tmp_buf, name_buf); | |
15955 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
15956 | } | |
15957 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 15958 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 15959 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
f7efd730 | 15960 | fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n", |
efdba735 | 15961 | BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 15962 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 15963 | } |
ee890fe2 | 15964 | |
efdba735 | 15965 | branch_island_list = 0; |
ee890fe2 SS |
15966 | } |
15967 | ||
15968 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
15969 | already there or not. */ | |
15970 | ||
efdba735 | 15971 | static int |
a2369ed3 | 15972 | no_previous_def (tree function_name) |
ee890fe2 | 15973 | { |
efdba735 SH |
15974 | tree branch_island; |
15975 | for (branch_island = branch_island_list; | |
15976 | branch_island; | |
15977 | branch_island = TREE_CHAIN (branch_island)) | |
15978 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
15979 | return 0; |
15980 | return 1; | |
15981 | } | |
15982 | ||
15983 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
15984 | the function. */ | |
15985 | ||
efdba735 | 15986 | static tree |
a2369ed3 | 15987 | get_prev_label (tree function_name) |
ee890fe2 | 15988 | { |
efdba735 SH |
15989 | tree branch_island; |
15990 | for (branch_island = branch_island_list; | |
15991 | branch_island; | |
15992 | branch_island = TREE_CHAIN (branch_island)) | |
15993 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
15994 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
15995 | return 0; |
15996 | } | |
15997 | ||
15998 | /* INSN is either a function call or a millicode call. It may have an | |
15999 | unconditional jump in its delay slot. | |
16000 | ||
16001 | CALL_DEST is the routine we are calling. */ | |
16002 | ||
16003 | char * | |
efdba735 | 16004 | output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number) |
ee890fe2 SS |
16005 | { |
16006 | static char buf[256]; | |
efdba735 SH |
16007 | if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF |
16008 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) | |
ee890fe2 SS |
16009 | { |
16010 | tree labelname; | |
efdba735 | 16011 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
ee890fe2 SS |
16012 | |
16013 | if (no_previous_def (funname)) | |
16014 | { | |
308c142a | 16015 | int line_number = 0; |
ee890fe2 SS |
16016 | rtx label_rtx = gen_label_rtx (); |
16017 | char *label_buf, temp_buf[256]; | |
16018 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
16019 | CODE_LABEL_NUMBER (label_rtx)); | |
16020 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
16021 | labelname = get_identifier (label_buf); | |
16022 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
16023 | if (insn) | |
16024 | line_number = NOTE_LINE_NUMBER (insn); | |
efdba735 | 16025 | add_compiler_branch_island (labelname, funname, line_number); |
ee890fe2 SS |
16026 | } |
16027 | else | |
16028 | labelname = get_prev_label (funname); | |
16029 | ||
efdba735 SH |
16030 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
16031 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
16032 | "L42" should be a 'branch island', that will do a far jump to | |
16033 | 'foo'. Branch islands are generated in | |
16034 | macho_branch_islands(). */ | |
ee890fe2 | 16035 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 16036 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
16037 | } |
16038 | else | |
efdba735 SH |
16039 | sprintf (buf, "bl %%z%d", dest_operand_number); |
16040 | return buf; | |
ee890fe2 SS |
16041 | } |
16042 | ||
efdba735 | 16043 | #endif /* TARGET_MACHO */ |
ee890fe2 | 16044 | |
ee890fe2 SS |
16045 | /* Generate PIC and indirect symbol stubs. */ |
16046 | ||
16047 | void | |
a2369ed3 | 16048 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
16049 | { |
16050 | unsigned int length; | |
a4f6c312 SS |
16051 | char *symbol_name, *lazy_ptr_name; |
16052 | char *local_label_0; | |
ee890fe2 SS |
16053 | static int label = 0; |
16054 | ||
df56a27f | 16055 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 16056 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 16057 | |
ee890fe2 | 16058 | |
ee890fe2 SS |
16059 | length = strlen (symb); |
16060 | symbol_name = alloca (length + 32); | |
16061 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
16062 | ||
16063 | lazy_ptr_name = alloca (length + 32); | |
16064 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
16065 | ||
ee890fe2 | 16066 | if (flag_pic == 2) |
d3c300d2 | 16067 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 16068 | else |
d3c300d2 DJ |
16069 | machopic_symbol_stub1_section (); |
16070 | fprintf (file, "\t.align 2\n"); | |
ee890fe2 SS |
16071 | |
16072 | fprintf (file, "%s:\n", stub); | |
16073 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
16074 | ||
16075 | if (flag_pic == 2) | |
16076 | { | |
876455fa AP |
16077 | label++; |
16078 | local_label_0 = alloca (sizeof("\"L0000000000$spb\"")); | |
16079 | sprintf (local_label_0, "\"L%011d$spb\"", label); | |
16080 | ||
ee890fe2 SS |
16081 | fprintf (file, "\tmflr r0\n"); |
16082 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
16083 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
16084 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
16085 | lazy_ptr_name, local_label_0); | |
16086 | fprintf (file, "\tmtlr r0\n"); | |
d3c300d2 | 16087 | fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n", |
ee890fe2 SS |
16088 | lazy_ptr_name, local_label_0); |
16089 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
16090 | fprintf (file, "\tbctr\n"); |
16091 | } | |
16092 | else | |
ab82a49f AP |
16093 | { |
16094 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
16095 | fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name); | |
16096 | fprintf (file, "\tmtctr r12\n"); | |
16097 | fprintf (file, "\tbctr\n"); | |
16098 | } | |
ee890fe2 SS |
16099 | |
16100 | machopic_lazy_symbol_ptr_section (); | |
16101 | fprintf (file, "%s:\n", lazy_ptr_name); | |
16102 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
16103 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
16104 | } | |
16105 | ||
16106 | /* Legitimize PIC addresses. If the address is already | |
16107 | position-independent, we return ORIG. Newly generated | |
16108 | position-independent addresses go into a reg. This is REG if non | |
16109 | zero, otherwise we allocate register(s) as necessary. */ | |
16110 | ||
c859cda6 | 16111 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
16112 | |
16113 | rtx | |
a2369ed3 DJ |
16114 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
16115 | rtx reg) | |
ee890fe2 SS |
16116 | { |
16117 | rtx base, offset; | |
16118 | ||
16119 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
16120 | reg = gen_reg_rtx (Pmode); | |
16121 | ||
16122 | if (GET_CODE (orig) == CONST) | |
16123 | { | |
16124 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
16125 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
16126 | return orig; | |
16127 | ||
16128 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
16129 | { | |
2cf520bf | 16130 | /* Use a different reg for the intermediate value, as |
a3c9585f | 16131 | it will be marked UNCHANGING. */ |
2cf520bf GK |
16132 | rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); |
16133 | ||
a4f6c312 SS |
16134 | base = |
16135 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
2cf520bf | 16136 | Pmode, reg_temp); |
a4f6c312 SS |
16137 | offset = |
16138 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
16139 | Pmode, reg); | |
ee890fe2 SS |
16140 | } |
16141 | else | |
16142 | abort (); | |
16143 | ||
16144 | if (GET_CODE (offset) == CONST_INT) | |
16145 | { | |
16146 | if (SMALL_INT (offset)) | |
ed8908e7 | 16147 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
16148 | else if (! reload_in_progress && ! reload_completed) |
16149 | offset = force_reg (Pmode, offset); | |
16150 | else | |
c859cda6 DJ |
16151 | { |
16152 | rtx mem = force_const_mem (Pmode, orig); | |
16153 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
16154 | } | |
ee890fe2 | 16155 | } |
f1c25d3b | 16156 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
16157 | } |
16158 | ||
16159 | /* Fall back on generic machopic code. */ | |
16160 | return machopic_legitimize_pic_address (orig, mode, reg); | |
16161 | } | |
16162 | ||
16163 | /* This is just a placeholder to make linking work without having to | |
16164 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
16165 | ever needed for Darwin (not too likely!) this would have to get a | |
16166 | real definition. */ | |
16167 | ||
16168 | void | |
863d938c | 16169 | toc_section (void) |
ee890fe2 SS |
16170 | { |
16171 | } | |
16172 | ||
16173 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
16174 | |
16175 | #if TARGET_ELF | |
16176 | static unsigned int | |
a2369ed3 | 16177 | rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) |
7c262518 | 16178 | { |
1ff8f81a AM |
16179 | return default_section_type_flags_1 (decl, name, reloc, |
16180 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 16181 | } |
d9f6800d RH |
16182 | |
16183 | /* Record an element in the table of global constructors. SYMBOL is | |
16184 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
16185 | between 0 and MAX_INIT_PRIORITY. | |
16186 | ||
16187 | This differs from default_named_section_asm_out_constructor in | |
16188 | that we have special handling for -mrelocatable. */ | |
16189 | ||
16190 | static void | |
a2369ed3 | 16191 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
16192 | { |
16193 | const char *section = ".ctors"; | |
16194 | char buf[16]; | |
16195 | ||
16196 | if (priority != DEFAULT_INIT_PRIORITY) | |
16197 | { | |
16198 | sprintf (buf, ".ctors.%.5u", | |
16199 | /* Invert the numbering so the linker puts us in the proper | |
16200 | order; constructors are run from right to left, and the | |
16201 | linker sorts in increasing order. */ | |
16202 | MAX_INIT_PRIORITY - priority); | |
16203 | section = buf; | |
16204 | } | |
16205 | ||
715bdd29 RH |
16206 | named_section_flags (section, SECTION_WRITE); |
16207 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
16208 | |
16209 | if (TARGET_RELOCATABLE) | |
16210 | { | |
16211 | fputs ("\t.long (", asm_out_file); | |
16212 | output_addr_const (asm_out_file, symbol); | |
16213 | fputs (")@fixup\n", asm_out_file); | |
16214 | } | |
16215 | else | |
c8af3574 | 16216 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
16217 | } |
16218 | ||
16219 | static void | |
a2369ed3 | 16220 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
16221 | { |
16222 | const char *section = ".dtors"; | |
16223 | char buf[16]; | |
16224 | ||
16225 | if (priority != DEFAULT_INIT_PRIORITY) | |
16226 | { | |
16227 | sprintf (buf, ".dtors.%.5u", | |
16228 | /* Invert the numbering so the linker puts us in the proper | |
16229 | order; constructors are run from right to left, and the | |
16230 | linker sorts in increasing order. */ | |
16231 | MAX_INIT_PRIORITY - priority); | |
16232 | section = buf; | |
16233 | } | |
16234 | ||
715bdd29 RH |
16235 | named_section_flags (section, SECTION_WRITE); |
16236 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
16237 | |
16238 | if (TARGET_RELOCATABLE) | |
16239 | { | |
16240 | fputs ("\t.long (", asm_out_file); | |
16241 | output_addr_const (asm_out_file, symbol); | |
16242 | fputs (")@fixup\n", asm_out_file); | |
16243 | } | |
16244 | else | |
c8af3574 | 16245 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 16246 | } |
9739c90c JJ |
16247 | |
16248 | void | |
a2369ed3 | 16249 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
16250 | { |
16251 | if (TARGET_64BIT) | |
16252 | { | |
16253 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
16254 | ASM_OUTPUT_LABEL (file, name); | |
16255 | fputs (DOUBLE_INT_ASM_OP, file); | |
16256 | putc ('.', file); | |
16257 | assemble_name (file, name); | |
16258 | fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file); | |
16259 | assemble_name (file, name); | |
16260 | fputs (",24\n\t.type\t.", file); | |
16261 | assemble_name (file, name); | |
16262 | fputs (",@function\n", file); | |
16263 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
16264 | { | |
16265 | fputs ("\t.globl\t.", file); | |
16266 | assemble_name (file, name); | |
16267 | putc ('\n', file); | |
16268 | } | |
16269 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
16270 | putc ('.', file); | |
16271 | ASM_OUTPUT_LABEL (file, name); | |
16272 | return; | |
16273 | } | |
16274 | ||
16275 | if (TARGET_RELOCATABLE | |
16276 | && (get_pool_size () != 0 || current_function_profile) | |
3c9eb5f4 | 16277 | && uses_TOC ()) |
9739c90c JJ |
16278 | { |
16279 | char buf[256]; | |
16280 | ||
16281 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
16282 | ||
16283 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
16284 | fprintf (file, "\t.long "); | |
16285 | assemble_name (file, buf); | |
16286 | putc ('-', file); | |
16287 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
16288 | assemble_name (file, buf); | |
16289 | putc ('\n', file); | |
16290 | } | |
16291 | ||
16292 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
16293 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
16294 | ||
16295 | if (DEFAULT_ABI == ABI_AIX) | |
16296 | { | |
16297 | const char *desc_name, *orig_name; | |
16298 | ||
16299 | orig_name = (*targetm.strip_name_encoding) (name); | |
16300 | desc_name = orig_name; | |
16301 | while (*desc_name == '.') | |
16302 | desc_name++; | |
16303 | ||
16304 | if (TREE_PUBLIC (decl)) | |
16305 | fprintf (file, "\t.globl %s\n", desc_name); | |
16306 | ||
16307 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
16308 | fprintf (file, "%s:\n", desc_name); | |
16309 | fprintf (file, "\t.long %s\n", orig_name); | |
16310 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
16311 | if (DEFAULT_ABI == ABI_AIX) | |
16312 | fputs ("\t.long 0\n", file); | |
16313 | fprintf (file, "\t.previous\n"); | |
16314 | } | |
16315 | ASM_OUTPUT_LABEL (file, name); | |
16316 | } | |
7c262518 RH |
16317 | #endif |
16318 | ||
cbaaba19 | 16319 | #if TARGET_XCOFF |
7c262518 | 16320 | static void |
a2369ed3 | 16321 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
16322 | { |
16323 | fputs (GLOBAL_ASM_OP, stream); | |
16324 | RS6000_OUTPUT_BASENAME (stream, name); | |
16325 | putc ('\n', stream); | |
16326 | } | |
16327 | ||
16328 | static void | |
a2369ed3 | 16329 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags) |
7c262518 | 16330 | { |
0e5dbd9b DE |
16331 | int smclass; |
16332 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
16333 | ||
16334 | if (flags & SECTION_CODE) | |
16335 | smclass = 0; | |
16336 | else if (flags & SECTION_WRITE) | |
16337 | smclass = 2; | |
16338 | else | |
16339 | smclass = 1; | |
16340 | ||
5b5198f7 | 16341 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 16342 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 16343 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 16344 | } |
ae46c4e0 RH |
16345 | |
16346 | static void | |
a2369ed3 DJ |
16347 | rs6000_xcoff_select_section (tree decl, int reloc, |
16348 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
ae46c4e0 | 16349 | { |
5add3202 | 16350 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 16351 | { |
0e5dbd9b | 16352 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
16353 | read_only_data_section (); |
16354 | else | |
16355 | read_only_private_data_section (); | |
16356 | } | |
16357 | else | |
16358 | { | |
0e5dbd9b | 16359 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
16360 | data_section (); |
16361 | else | |
16362 | private_data_section (); | |
16363 | } | |
16364 | } | |
16365 | ||
16366 | static void | |
a2369ed3 | 16367 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
16368 | { |
16369 | const char *name; | |
ae46c4e0 | 16370 | |
5b5198f7 DE |
16371 | /* Use select_section for private and uninitialized data. */ |
16372 | if (!TREE_PUBLIC (decl) | |
16373 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
16374 | || DECL_INITIAL (decl) == NULL_TREE |
16375 | || DECL_INITIAL (decl) == error_mark_node | |
16376 | || (flag_zero_initialized_in_bss | |
16377 | && initializer_zerop (DECL_INITIAL (decl)))) | |
16378 | return; | |
16379 | ||
16380 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
16381 | name = (*targetm.strip_name_encoding) (name); | |
16382 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 16383 | } |
b64a1b53 | 16384 | |
fb49053f RH |
16385 | /* Select section for constant in constant pool. |
16386 | ||
16387 | On RS/6000, all constants are in the private read-only data area. | |
16388 | However, if this is being placed in the TOC it must be output as a | |
16389 | toc entry. */ | |
16390 | ||
b64a1b53 | 16391 | static void |
a2369ed3 DJ |
16392 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
16393 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
b64a1b53 RH |
16394 | { |
16395 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
16396 | toc_section (); | |
16397 | else | |
16398 | read_only_private_data_section (); | |
16399 | } | |
772c5265 RH |
16400 | |
16401 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
16402 | ||
16403 | static const char * | |
a2369ed3 | 16404 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
16405 | { |
16406 | size_t len; | |
16407 | if (*name == '*') | |
16408 | name++; | |
16409 | len = strlen (name); | |
16410 | if (name[len - 1] == ']') | |
16411 | return ggc_alloc_string (name, len - 4); | |
16412 | else | |
16413 | return name; | |
16414 | } | |
16415 | ||
5add3202 DE |
16416 | /* Section attributes. AIX is always PIC. */ |
16417 | ||
16418 | static unsigned int | |
a2369ed3 | 16419 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 16420 | { |
5b5198f7 DE |
16421 | unsigned int align; |
16422 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
16423 | ||
16424 | /* Align to at least UNIT size. */ | |
16425 | if (flags & SECTION_CODE) | |
16426 | align = MIN_UNITS_PER_WORD; | |
16427 | else | |
16428 | /* Increase alignment of large objects if not already stricter. */ | |
16429 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
16430 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
16431 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
16432 | ||
16433 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 16434 | } |
a5fe455b | 16435 | |
1bc7c5b6 ZW |
16436 | /* Output at beginning of assembler file. |
16437 | ||
16438 | Initialize the section names for the RS/6000 at this point. | |
16439 | ||
16440 | Specify filename, including full path, to assembler. | |
16441 | ||
16442 | We want to go into the TOC section so at least one .toc will be emitted. | |
16443 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
16444 | [RW] section emitted. | |
16445 | ||
16446 | Finally, declare mcount when profiling to make the assembler happy. */ | |
16447 | ||
16448 | static void | |
863d938c | 16449 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
16450 | { |
16451 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
16452 | main_input_filename, ".bss_"); | |
16453 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
16454 | main_input_filename, ".rw_"); | |
16455 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
16456 | main_input_filename, ".ro_"); | |
16457 | ||
16458 | fputs ("\t.file\t", asm_out_file); | |
16459 | output_quoted_string (asm_out_file, main_input_filename); | |
16460 | fputc ('\n', asm_out_file); | |
16461 | toc_section (); | |
16462 | if (write_symbols != NO_DEBUG) | |
16463 | private_data_section (); | |
16464 | text_section (); | |
16465 | if (profile_flag) | |
16466 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
16467 | rs6000_file_start (); | |
16468 | } | |
16469 | ||
a5fe455b ZW |
16470 | /* Output at end of assembler file. |
16471 | On the RS/6000, referencing data should automatically pull in text. */ | |
16472 | ||
16473 | static void | |
863d938c | 16474 | rs6000_xcoff_file_end (void) |
a5fe455b ZW |
16475 | { |
16476 | text_section (); | |
16477 | fputs ("_section_.text:\n", asm_out_file); | |
16478 | data_section (); | |
16479 | fputs (TARGET_32BIT | |
16480 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
16481 | asm_out_file); | |
16482 | } | |
f1384257 | 16483 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 16484 | |
f1384257 AM |
16485 | #if TARGET_MACHO |
16486 | /* Cross-module name binding. Darwin does not support overriding | |
7f3d8013 | 16487 | functions at dynamic-link time. */ |
0e5dbd9b | 16488 | |
2bcc50d0 | 16489 | static bool |
a2369ed3 | 16490 | rs6000_binds_local_p (tree decl) |
0e5dbd9b | 16491 | { |
f1384257 | 16492 | return default_binds_local_p_1 (decl, 0); |
0e5dbd9b | 16493 | } |
f1384257 | 16494 | #endif |
34bb030a | 16495 | |
3c50106f RH |
16496 | /* Compute a (partial) cost for rtx X. Return true if the complete |
16497 | cost has been computed, and false if subexpressions should be | |
16498 | scanned. In either case, *TOTAL contains the cost result. */ | |
16499 | ||
16500 | static bool | |
a2369ed3 DJ |
16501 | rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, |
16502 | int *total) | |
3c50106f | 16503 | { |
f0517163 RS |
16504 | enum machine_mode mode = GET_MODE (x); |
16505 | ||
3c50106f RH |
16506 | switch (code) |
16507 | { | |
16508 | /* On the RS/6000, if it is valid in the insn, it is free. | |
16509 | So this always returns 0. */ | |
16510 | case CONST_INT: | |
16511 | case CONST: | |
16512 | case LABEL_REF: | |
16513 | case SYMBOL_REF: | |
16514 | case CONST_DOUBLE: | |
16515 | case HIGH: | |
16516 | *total = 0; | |
16517 | return true; | |
16518 | ||
16519 | case PLUS: | |
f0517163 RS |
16520 | if (mode == DFmode) |
16521 | *total = GET_CODE (XEXP (x, 0)) == MULT | |
06a67bdd RS |
16522 | ? rs6000_cost->dmul |
16523 | : rs6000_cost->fp; | |
f0517163 | 16524 | else if (mode == SFmode) |
06a67bdd | 16525 | *total = rs6000_cost->fp; |
938bf747 RS |
16526 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
16527 | { | |
16528 | /* The rs6000 doesn't have shift-and-add instructions. */ | |
16529 | rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total); | |
16530 | *total += COSTS_N_INSNS (1); | |
16531 | } | |
f0517163 RS |
16532 | else |
16533 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
16534 | && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) | |
16535 | + 0x8000) >= 0x10000) | |
16536 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
16537 | ? COSTS_N_INSNS (2) | |
16538 | : COSTS_N_INSNS (1)); | |
3c50106f RH |
16539 | return true; |
16540 | ||
52190329 | 16541 | case MINUS: |
f0517163 RS |
16542 | if (mode == DFmode) |
16543 | *total = GET_CODE (XEXP (x, 0)) == MULT | |
06a67bdd RS |
16544 | ? rs6000_cost->dmul |
16545 | : rs6000_cost->fp; | |
f0517163 | 16546 | else if (mode == SFmode) |
06a67bdd | 16547 | *total = rs6000_cost->fp; |
938bf747 RS |
16548 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
16549 | { | |
16550 | /* The rs6000 doesn't have shift-and-sub instructions. */ | |
16551 | rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total); | |
16552 | *total += COSTS_N_INSNS (1); | |
16553 | } | |
f0517163 RS |
16554 | else |
16555 | *total = COSTS_N_INSNS (1); | |
52190329 RS |
16556 | return true; |
16557 | ||
3c50106f RH |
16558 | case AND: |
16559 | case IOR: | |
16560 | case XOR: | |
16561 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
16562 | && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 | |
16563 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
16564 | ? COSTS_N_INSNS (2) | |
16565 | : COSTS_N_INSNS (1)); | |
16566 | return true; | |
16567 | ||
16568 | case MULT: | |
8b897cfa | 16569 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
3c50106f | 16570 | { |
8b897cfa RS |
16571 | if (INTVAL (XEXP (x, 1)) >= -256 |
16572 | && INTVAL (XEXP (x, 1)) <= 255) | |
06a67bdd | 16573 | *total = rs6000_cost->mulsi_const9; |
8b897cfa | 16574 | else |
06a67bdd | 16575 | *total = rs6000_cost->mulsi_const; |
3c50106f | 16576 | } |
f0517163 | 16577 | else if (mode == DFmode) |
06a67bdd | 16578 | *total = rs6000_cost->dmul; |
f0517163 | 16579 | else if (mode == SFmode) |
06a67bdd | 16580 | *total = rs6000_cost->fp; |
f0517163 | 16581 | else if (mode == DImode) |
06a67bdd | 16582 | *total = rs6000_cost->muldi; |
8b897cfa | 16583 | else |
06a67bdd | 16584 | *total = rs6000_cost->mulsi; |
8b897cfa | 16585 | return true; |
3c50106f RH |
16586 | |
16587 | case DIV: | |
16588 | case MOD: | |
f0517163 RS |
16589 | if (FLOAT_MODE_P (mode)) |
16590 | { | |
06a67bdd RS |
16591 | *total = mode == DFmode ? rs6000_cost->ddiv |
16592 | : rs6000_cost->sdiv; | |
f0517163 RS |
16593 | return true; |
16594 | } | |
3c50106f RH |
16595 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
16596 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
16597 | { | |
16598 | *total = COSTS_N_INSNS (2); | |
16599 | return true; | |
16600 | } | |
5efb1046 | 16601 | /* FALLTHRU */ |
3c50106f RH |
16602 | |
16603 | case UDIV: | |
16604 | case UMOD: | |
8b897cfa | 16605 | if (GET_MODE (XEXP (x, 1)) == DImode) |
06a67bdd | 16606 | *total = rs6000_cost->divdi; |
8b897cfa | 16607 | else |
06a67bdd | 16608 | *total = rs6000_cost->divsi; |
8b897cfa | 16609 | return true; |
3c50106f RH |
16610 | |
16611 | case FFS: | |
16612 | *total = COSTS_N_INSNS (4); | |
16613 | return true; | |
16614 | ||
f0517163 RS |
16615 | case NEG: |
16616 | case ABS: | |
16617 | if (FLOAT_MODE_P (mode)) | |
06a67bdd | 16618 | *total = rs6000_cost->fp; |
f0517163 RS |
16619 | else |
16620 | *total = COSTS_N_INSNS (1); | |
16621 | return true; | |
16622 | ||
3c50106f | 16623 | case MEM: |
a3c9585f | 16624 | /* MEM should be slightly more expensive than (plus (reg) (const)). */ |
f0517163 | 16625 | *total = COSTS_N_INSNS (1) + 1; |
3c50106f RH |
16626 | return true; |
16627 | ||
06a67bdd RS |
16628 | case NOT: |
16629 | case SIGN_EXTEND: | |
16630 | case ZERO_EXTEND: | |
16631 | case COMPARE: | |
16632 | *total = COSTS_N_INSNS (1); | |
16633 | break; | |
16634 | ||
16635 | case FLOAT_TRUNCATE: | |
16636 | *total = rs6000_cost->fp; | |
16637 | return true; | |
16638 | ||
16639 | case UNSPEC: | |
16640 | switch (XINT (x, 1)) | |
16641 | { | |
16642 | case UNSPEC_FRSP: | |
16643 | *total = rs6000_cost->fp; | |
16644 | return true; | |
16645 | ||
16646 | default: | |
16647 | break; | |
16648 | } | |
16649 | break; | |
16650 | ||
16651 | case CALL: | |
16652 | case IF_THEN_ELSE: | |
16653 | if (optimize_size) | |
16654 | { | |
16655 | *total = COSTS_N_INSNS (1); | |
16656 | return true; | |
16657 | } | |
16658 | break; | |
16659 | ||
3c50106f | 16660 | default: |
06a67bdd | 16661 | break; |
3c50106f | 16662 | } |
06a67bdd RS |
16663 | |
16664 | return false; | |
3c50106f RH |
16665 | } |
16666 | ||
34bb030a DE |
16667 | /* A C expression returning the cost of moving data from a register of class |
16668 | CLASS1 to one of CLASS2. */ | |
16669 | ||
16670 | int | |
a2369ed3 DJ |
16671 | rs6000_register_move_cost (enum machine_mode mode, |
16672 | enum reg_class from, enum reg_class to) | |
34bb030a DE |
16673 | { |
16674 | /* Moves from/to GENERAL_REGS. */ | |
16675 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
16676 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
16677 | { | |
16678 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
16679 | from = to; | |
16680 | ||
16681 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
16682 | return (rs6000_memory_move_cost (mode, from, 0) | |
16683 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
16684 | ||
a3c9585f | 16685 | /* It's more expensive to move CR_REGS than CR0_REGS because of the shift.... */ |
34bb030a DE |
16686 | else if (from == CR_REGS) |
16687 | return 4; | |
16688 | ||
16689 | else | |
16690 | /* A move will cost one instruction per GPR moved. */ | |
16691 | return 2 * HARD_REGNO_NREGS (0, mode); | |
16692 | } | |
16693 | ||
16694 | /* Moving between two similar registers is just one instruction. */ | |
16695 | else if (reg_classes_intersect_p (to, from)) | |
16696 | return mode == TFmode ? 4 : 2; | |
16697 | ||
16698 | /* Everything else has to go through GENERAL_REGS. */ | |
16699 | else | |
16700 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) | |
16701 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); | |
16702 | } | |
16703 | ||
16704 | /* A C expressions returning the cost of moving data of MODE from a register to | |
16705 | or from memory. */ | |
16706 | ||
16707 | int | |
a2369ed3 DJ |
16708 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, |
16709 | int in ATTRIBUTE_UNUSED) | |
34bb030a DE |
16710 | { |
16711 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
16712 | return 4 * HARD_REGNO_NREGS (0, mode); | |
16713 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) | |
16714 | return 4 * HARD_REGNO_NREGS (32, mode); | |
16715 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) | |
16716 | return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); | |
16717 | else | |
16718 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
16719 | } | |
16720 | ||
ded9bf77 AH |
16721 | /* Return an RTX representing where to find the function value of a |
16722 | function returning MODE. */ | |
16723 | static rtx | |
16724 | rs6000_complex_function_value (enum machine_mode mode) | |
16725 | { | |
16726 | unsigned int regno; | |
16727 | rtx r1, r2; | |
16728 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 16729 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 | 16730 | |
4ed78545 | 16731 | if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
ded9bf77 AH |
16732 | regno = FP_ARG_RETURN; |
16733 | else | |
16734 | { | |
16735 | regno = GP_ARG_RETURN; | |
16736 | ||
16737 | /* 32-bit is OK since it'll go in r3/r4. */ | |
fb7e4164 | 16738 | if (TARGET_32BIT && inner_bytes >= 4) |
ded9bf77 AH |
16739 | return gen_rtx_REG (mode, regno); |
16740 | } | |
16741 | ||
fb7e4164 AM |
16742 | if (inner_bytes >= 8) |
16743 | return gen_rtx_REG (mode, regno); | |
16744 | ||
ded9bf77 AH |
16745 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
16746 | const0_rtx); | |
16747 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 16748 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
16749 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
16750 | } | |
16751 | ||
a6ebc39a AH |
16752 | /* Define how to find the value returned by a function. |
16753 | VALTYPE is the data type of the value (as a tree). | |
16754 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
16755 | otherwise, FUNC is 0. | |
16756 | ||
16757 | On the SPE, both FPs and vectors are returned in r3. | |
16758 | ||
16759 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
16760 | fp1, unless -msoft-float. */ | |
16761 | ||
16762 | rtx | |
16763 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
16764 | { | |
16765 | enum machine_mode mode; | |
2a8fa26c | 16766 | unsigned int regno; |
a6ebc39a | 16767 | |
0e67400a FJ |
16768 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
16769 | { | |
16770 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
16771 | return gen_rtx_PARALLEL (DImode, | |
16772 | gen_rtvec (2, | |
16773 | gen_rtx_EXPR_LIST (VOIDmode, | |
16774 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
16775 | const0_rtx), | |
16776 | gen_rtx_EXPR_LIST (VOIDmode, | |
16777 | gen_rtx_REG (SImode, | |
16778 | GP_ARG_RETURN + 1), | |
16779 | GEN_INT (4)))); | |
16780 | } | |
16781 | ||
a6ebc39a AH |
16782 | if ((INTEGRAL_TYPE_P (valtype) |
16783 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
16784 | || POINTER_TYPE_P (valtype)) | |
b78d48dd | 16785 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a AH |
16786 | else |
16787 | mode = TYPE_MODE (valtype); | |
16788 | ||
4ed78545 | 16789 | if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) |
2a8fa26c | 16790 | regno = FP_ARG_RETURN; |
ded9bf77 | 16791 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
42ba5130 | 16792 | && targetm.calls.split_complex_arg) |
ded9bf77 | 16793 | return rs6000_complex_function_value (mode); |
44688022 AM |
16794 | else if (TREE_CODE (valtype) == VECTOR_TYPE |
16795 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
a6ebc39a AH |
16796 | regno = ALTIVEC_ARG_RETURN; |
16797 | else | |
16798 | regno = GP_ARG_RETURN; | |
16799 | ||
16800 | return gen_rtx_REG (mode, regno); | |
16801 | } | |
16802 | ||
ded9bf77 AH |
16803 | /* Define how to find the value returned by a library function |
16804 | assuming the value has mode MODE. */ | |
16805 | rtx | |
16806 | rs6000_libcall_value (enum machine_mode mode) | |
16807 | { | |
16808 | unsigned int regno; | |
16809 | ||
16810 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
16811 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
16812 | regno = FP_ARG_RETURN; | |
44688022 AM |
16813 | else if (ALTIVEC_VECTOR_MODE (mode) |
16814 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
ded9bf77 | 16815 | regno = ALTIVEC_ARG_RETURN; |
42ba5130 | 16816 | else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) |
ded9bf77 AH |
16817 | return rs6000_complex_function_value (mode); |
16818 | else | |
16819 | regno = GP_ARG_RETURN; | |
16820 | ||
16821 | return gen_rtx_REG (mode, regno); | |
16822 | } | |
16823 | ||
d1d0c603 JJ |
16824 | /* Define the offset between two registers, FROM to be eliminated and its |
16825 | replacement TO, at the start of a routine. */ | |
16826 | HOST_WIDE_INT | |
16827 | rs6000_initial_elimination_offset (int from, int to) | |
16828 | { | |
16829 | rs6000_stack_t *info = rs6000_stack_info (); | |
16830 | HOST_WIDE_INT offset; | |
16831 | ||
16832 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
16833 | offset = info->push_p ? 0 : -info->total_size; | |
16834 | else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
16835 | offset = info->total_size; | |
16836 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
16837 | offset = info->push_p ? info->total_size : 0; | |
16838 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
16839 | offset = 0; | |
16840 | else | |
16841 | abort (); | |
16842 | ||
16843 | return offset; | |
16844 | } | |
16845 | ||
62e1dfcf NC |
16846 | /* Return true if TYPE is of type __ev64_opaque__. */ |
16847 | ||
c8e4f0e9 | 16848 | static bool |
a2369ed3 | 16849 | is_ev64_opaque_type (tree type) |
62e1dfcf | 16850 | { |
c8e4f0e9 | 16851 | return (TARGET_SPE |
2abe3e28 AH |
16852 | && (type == opaque_V2SI_type_node |
16853 | || type == opaque_V2SF_type_node | |
36252949 | 16854 | || type == opaque_p_V2SI_type_node)); |
62e1dfcf NC |
16855 | } |
16856 | ||
96714395 | 16857 | static rtx |
a2369ed3 | 16858 | rs6000_dwarf_register_span (rtx reg) |
96714395 AH |
16859 | { |
16860 | unsigned regno; | |
16861 | ||
16862 | if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg))) | |
16863 | return NULL_RTX; | |
16864 | ||
16865 | regno = REGNO (reg); | |
16866 | ||
16867 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
16868 | This is a way of distinguishing r0 in 32-bits from r0 in | |
16869 | 64-bits. */ | |
16870 | return | |
16871 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
16872 | BYTES_BIG_ENDIAN |
16873 | ? gen_rtvec (2, | |
16874 | gen_rtx_REG (SImode, regno + 1200), | |
16875 | gen_rtx_REG (SImode, regno)) | |
16876 | : gen_rtvec (2, | |
16877 | gen_rtx_REG (SImode, regno), | |
16878 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
16879 | } |
16880 | ||
93c9d1ba AM |
16881 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
16882 | ||
16883 | unsigned int | |
16884 | rs6000_dbx_register_number (unsigned int regno) | |
16885 | { | |
16886 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
16887 | return regno; | |
16888 | if (regno == MQ_REGNO) | |
16889 | return 100; | |
16890 | if (regno == LINK_REGISTER_REGNUM) | |
16891 | return 108; | |
16892 | if (regno == COUNT_REGISTER_REGNUM) | |
16893 | return 109; | |
16894 | if (CR_REGNO_P (regno)) | |
16895 | return regno - CR0_REGNO + 86; | |
16896 | if (regno == XER_REGNO) | |
16897 | return 101; | |
16898 | if (ALTIVEC_REGNO_P (regno)) | |
16899 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
16900 | if (regno == VRSAVE_REGNO) | |
16901 | return 356; | |
16902 | if (regno == VSCR_REGNO) | |
16903 | return 67; | |
16904 | if (regno == SPE_ACC_REGNO) | |
16905 | return 99; | |
16906 | if (regno == SPEFSCR_REGNO) | |
16907 | return 612; | |
16908 | /* SPE high reg number. We get these values of regno from | |
16909 | rs6000_dwarf_register_span. */ | |
16910 | if (regno >= 1200 && regno < 1232) | |
16911 | return regno; | |
16912 | ||
16913 | abort (); | |
16914 | } | |
16915 | ||
17211ab5 | 16916 | #include "gt-rs6000.h" |