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[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.c
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9878760c 1/* Subroutines used for code generation on IBM RS/6000.
f676971a 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5b86a469 3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
fab3bcc3 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
9878760c 5
5de601cf 6 This file is part of GCC.
9878760c 7
5de601cf
NC		 8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
9878760c 12
5de601cf
NC		 13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
9878760c 17
5de601cf
NC		 18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
9878760c 22
956d6950 23#include "config.h"
c4d38ccb 24#include "system.h"
4977bab6
ZW		 25#include "coretypes.h"
26#include "tm.h"
9878760c
RK		 27#include "rtl.h"
28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
9878760c
RK		 33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
9878760c 36#include "obstack.h"
9b30bae2 37#include "tree.h"
dfafc897 38#include "expr.h"
2fc1c679 39#include "optabs.h"
2a430ec1 40#include "except.h"
a7df97e6 41#include "function.h"
296b8152 42#include "output.h"
d5fa86ba 43#include "basic-block.h"
d0101753 44#include "integrate.h"
296b8152 45#include "toplev.h"
c8023011 46#include "ggc.h"
9ebbca7d
GK		 47#include "hashtab.h"
48#include "tm_p.h"
672a6f42
NB		 49#include "target.h"
50#include "target-def.h"
3ac88239 51#include "langhooks.h"
24ea750e 52#include "reload.h"
117dca74 53#include "cfglayout.h"
79ae11c4 54#include "sched-int.h"
cd3ce9b4 55#include "tree-gimple.h"
4d3e6fae 56#include "intl.h"
1bc7c5b6
ZW		 57#if TARGET_XCOFF
58#include "xcoffout.h" /* get declarations of xcoff_*_section_name */
59#endif
93a27b7b
ZW		 60#if TARGET_MACHO
61#include "gstab.h" /* for N_SLINE */
62#endif
9b30bae2 63
7509c759
MM		 64#ifndef TARGET_NO_PROTOTYPE
65#define TARGET_NO_PROTOTYPE 0
66#endif
67
9878760c
RK		 68#define min(A,B) ((A) < (B) ? (A) : (B))
69#define max(A,B) ((A) > (B) ? (A) : (B))
70
d1d0c603
JJ		 71/* Structure used to define the rs6000 stack */
72typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
c4ad648e 82 int world_save_p; /* true if we're saving *everything*:
d62294f5 83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
d1d0c603
JJ		 84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
108 not in save_size */
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
114} rs6000_stack_t;
115
5248c961
RK		 116/* Target cpu type */
117
118enum processor_type rs6000_cpu;
8e3f41e7
MM		 119struct rs6000_cpu_select rs6000_select[3] =
120{
815cdc52
MM		 121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
8e3f41e7 125};
5248c961 126
ec507f2d
DE		 127/* Always emit branch hint bits. */
128static GTY(()) bool rs6000_always_hint;
129
130/* Schedule instructions for group formation. */
131static GTY(()) bool rs6000_sched_groups;
132
f676971a 133/* Support adjust_priority scheduler hook
79ae11c4
DN		 134 and -mprioritize-restricted-insns= option. */
135const char *rs6000_sched_restricted_insns_priority_str;
136int rs6000_sched_restricted_insns_priority;
137
569fa502
DN		 138/* Support for -msched-costly-dep option. */
139const char *rs6000_sched_costly_dep_str;
140enum rs6000_dependence_cost rs6000_sched_costly_dep;
141
cbe26ab8
DN		 142/* Support for -minsert-sched-nops option. */
143const char *rs6000_sched_insert_nops_str;
144enum rs6000_nop_insertion rs6000_sched_insert_nops;
145
7ccf35ed 146/* Support targetm.vectorize.builtin_mask_for_load. */
13c62176 147static GTY(()) tree altivec_builtin_mask_for_load;
7ccf35ed 148
6fa3f289
ZW		 149/* Size of long double */
150const char *rs6000_long_double_size_string;
151int rs6000_long_double_type_size;
152
153/* Whether -mabi=altivec has appeared */
154int rs6000_altivec_abi;
155
08b57fb3
AH		 156/* Whether VRSAVE instructions should be generated. */
157int rs6000_altivec_vrsave;
158
159/* String from -mvrsave= option. */
160const char *rs6000_altivec_vrsave_string;
161
a3170dc6
AH		 162/* Nonzero if we want SPE ABI extensions. */
163int rs6000_spe_abi;
164
165/* Whether isel instructions should be generated. */
166int rs6000_isel;
167
993f19a8
AH		 168/* Whether SPE simd instructions should be generated. */
169int rs6000_spe;
170
5da702b1
AH		 171/* Nonzero if floating point operations are done in the GPRs. */
172int rs6000_float_gprs = 0;
173
594a51fe
SS		 174/* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175int rs6000_darwin64_abi;
176
5da702b1
AH		 177/* String from -mfloat-gprs=. */
178const char *rs6000_float_gprs_string;
a3170dc6
AH		 179
180/* String from -misel=. */
181const char *rs6000_isel_string;
182
993f19a8
AH		 183/* String from -mspe=. */
184const char *rs6000_spe_string;
185
a0ab749a 186/* Set to nonzero once AIX common-mode calls have been defined. */
bbfb86aa 187static GTY(()) int common_mode_defined;
c81bebd7 188
9878760c
RK		 189/* Save information from a "cmpxx" operation until the branch or scc is
190 emitted. */
9878760c
RK		 191rtx rs6000_compare_op0, rs6000_compare_op1;
192int rs6000_compare_fp_p;
874a0744 193
874a0744
MM		 194/* Label number of label created for -mrelocatable, to call to so we can
195 get the address of the GOT section */
196int rs6000_pic_labelno;
c81bebd7 197
b91da81f 198#ifdef USING_ELFOS_H
c81bebd7 199/* Which abi to adhere to */
9739c90c 200const char *rs6000_abi_name;
d9407988
MM		 201
202/* Semantics of the small data area */
203enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
204
205/* Which small data model to use */
815cdc52 206const char *rs6000_sdata_name = (char *)0;
9ebbca7d
GK		 207
208/* Counter for labels which are to be placed in .fixup. */
209int fixuplabelno = 0;
874a0744 210#endif
4697a36c 211
c4501e62
JJ		 212/* Bit size of immediate TLS offsets and string from which it is decoded. */
213int rs6000_tls_size = 32;
214const char *rs6000_tls_size_string;
215
b6c9286a
MM		 216/* ABI enumeration available for subtarget to use. */
217enum rs6000_abi rs6000_current_abi;
218
0ac081f6
AH		 219/* ABI string from -mabi= option. */
220const char *rs6000_abi_string;
221
85b776df
AM		 222/* Whether to use variant of AIX ABI for PowerPC64 Linux. */
223int dot_symbols;
224
38c1f2d7 225/* Debug flags */
815cdc52 226const char *rs6000_debug_name;
38c1f2d7
MM		 227int rs6000_debug_stack; /* debug stack applications */
228int rs6000_debug_arg; /* debug argument handling */
229
0d1fbc8c
AH		 230/* Value is TRUE if register/mode pair is accepatable. */
231bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
232
6035d635 233/* Opaque types. */
2abe3e28 234static GTY(()) tree opaque_V2SI_type_node;
2abe3e28 235static GTY(()) tree opaque_V2SF_type_node;
6035d635 236static GTY(()) tree opaque_p_V2SI_type_node;
4a5eab38
PB		 237static GTY(()) tree V16QI_type_node;
238static GTY(()) tree V2SI_type_node;
239static GTY(()) tree V2SF_type_node;
240static GTY(()) tree V4HI_type_node;
241static GTY(()) tree V4SI_type_node;
242static GTY(()) tree V4SF_type_node;
243static GTY(()) tree V8HI_type_node;
244static GTY(()) tree unsigned_V16QI_type_node;
245static GTY(()) tree unsigned_V8HI_type_node;
246static GTY(()) tree unsigned_V4SI_type_node;
8bb418a3
ZL		 247static GTY(()) tree bool_char_type_node; /* __bool char */
248static GTY(()) tree bool_short_type_node; /* __bool short */
249static GTY(()) tree bool_int_type_node; /* __bool int */
250static GTY(()) tree pixel_type_node; /* __pixel */
251static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
252static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
253static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
254static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
255
256int rs6000_warn_altivec_long = 1; /* On by default. */
257const char *rs6000_warn_altivec_long_switch;
258
57ac7be9
AM		 259const char *rs6000_traceback_name;
260static enum {
261 traceback_default = 0,
262 traceback_none,
263 traceback_part,
264 traceback_full
265} rs6000_traceback;
266
38c1f2d7
MM		 267/* Flag to say the TOC is initialized */
268int toc_initialized;
9ebbca7d 269char toc_label_name[10];
38c1f2d7 270
9ebbca7d 271/* Alias set for saves and restores from the rs6000 stack. */
f103e34d 272static GTY(()) int rs6000_sr_alias_set;
c8023011 273
a5c76ee6
ZW		 274/* Call distance, overridden by -mlongcall and #pragma longcall(1).
275 The only place that looks at this is rs6000_set_default_type_attributes;
276 everywhere else should rely on the presence or absence of a longcall
3eb4e360
AM		 277 attribute on the function declaration. Exception: init_cumulative_args
278 looks at it too, for libcalls. */
a5c76ee6
ZW		 279int rs6000_default_long_calls;
280const char *rs6000_longcall_switch;
281
a3c9585f
KH		 282/* Control alignment for fields within structures. */
283/* String from -malign-XXXXX. */
025d9908
KH		 284const char *rs6000_alignment_string;
285int rs6000_alignment_flags;
286
a3170dc6
AH		 287struct builtin_description
288{
289 /* mask is not const because we're going to alter it below. This
290 nonsense will go away when we rewrite the -march infrastructure
291 to give us more target flag bits. */
292 unsigned int mask;
293 const enum insn_code icode;
294 const char *const name;
295 const enum rs6000_builtins code;
296};
8b897cfa
RS		 297\f
298/* Target cpu costs. */
299
300struct processor_costs {
c4ad648e 301 const int mulsi; /* cost of SImode multiplication. */
8b897cfa
RS		 302 const int mulsi_const; /* cost of SImode multiplication by constant. */
303 const int mulsi_const9; /* cost of SImode mult by short constant. */
c4ad648e
AM		 304 const int muldi; /* cost of DImode multiplication. */
305 const int divsi; /* cost of SImode division. */
306 const int divdi; /* cost of DImode division. */
307 const int fp; /* cost of simple SFmode and DFmode insns. */
308 const int dmul; /* cost of DFmode multiplication (and fmadd). */
309 const int sdiv; /* cost of SFmode division (fdivs). */
310 const int ddiv; /* cost of DFmode division (fdiv). */
8b897cfa
RS		 311};
312
313const struct processor_costs *rs6000_cost;
314
315/* Processor costs (relative to an add) */
316
317/* Instruction size costs on 32bit processors. */
318static const
319struct processor_costs size32_cost = {
06a67bdd
RS		 320 COSTS_N_INSNS (1), /* mulsi */
321 COSTS_N_INSNS (1), /* mulsi_const */
322 COSTS_N_INSNS (1), /* mulsi_const9 */
323 COSTS_N_INSNS (1), /* muldi */
324 COSTS_N_INSNS (1), /* divsi */
325 COSTS_N_INSNS (1), /* divdi */
326 COSTS_N_INSNS (1), /* fp */
327 COSTS_N_INSNS (1), /* dmul */
328 COSTS_N_INSNS (1), /* sdiv */
329 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 330};
331
332/* Instruction size costs on 64bit processors. */
333static const
334struct processor_costs size64_cost = {
06a67bdd
RS		 335 COSTS_N_INSNS (1), /* mulsi */
336 COSTS_N_INSNS (1), /* mulsi_const */
337 COSTS_N_INSNS (1), /* mulsi_const9 */
338 COSTS_N_INSNS (1), /* muldi */
339 COSTS_N_INSNS (1), /* divsi */
340 COSTS_N_INSNS (1), /* divdi */
341 COSTS_N_INSNS (1), /* fp */
342 COSTS_N_INSNS (1), /* dmul */
343 COSTS_N_INSNS (1), /* sdiv */
344 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 345};
346
347/* Instruction costs on RIOS1 processors. */
348static const
349struct processor_costs rios1_cost = {
06a67bdd
RS		 350 COSTS_N_INSNS (5), /* mulsi */
351 COSTS_N_INSNS (4), /* mulsi_const */
352 COSTS_N_INSNS (3), /* mulsi_const9 */
353 COSTS_N_INSNS (5), /* muldi */
354 COSTS_N_INSNS (19), /* divsi */
355 COSTS_N_INSNS (19), /* divdi */
356 COSTS_N_INSNS (2), /* fp */
357 COSTS_N_INSNS (2), /* dmul */
358 COSTS_N_INSNS (19), /* sdiv */
359 COSTS_N_INSNS (19), /* ddiv */
8b897cfa
RS		 360};
361
362/* Instruction costs on RIOS2 processors. */
363static const
364struct processor_costs rios2_cost = {
06a67bdd
RS		 365 COSTS_N_INSNS (2), /* mulsi */
366 COSTS_N_INSNS (2), /* mulsi_const */
367 COSTS_N_INSNS (2), /* mulsi_const9 */
368 COSTS_N_INSNS (2), /* muldi */
369 COSTS_N_INSNS (13), /* divsi */
370 COSTS_N_INSNS (13), /* divdi */
371 COSTS_N_INSNS (2), /* fp */
372 COSTS_N_INSNS (2), /* dmul */
373 COSTS_N_INSNS (17), /* sdiv */
374 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 375};
376
377/* Instruction costs on RS64A processors. */
378static const
379struct processor_costs rs64a_cost = {
06a67bdd
RS		 380 COSTS_N_INSNS (20), /* mulsi */
381 COSTS_N_INSNS (12), /* mulsi_const */
382 COSTS_N_INSNS (8), /* mulsi_const9 */
383 COSTS_N_INSNS (34), /* muldi */
384 COSTS_N_INSNS (65), /* divsi */
385 COSTS_N_INSNS (67), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (4), /* dmul */
388 COSTS_N_INSNS (31), /* sdiv */
389 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 390};
391
392/* Instruction costs on MPCCORE processors. */
393static const
394struct processor_costs mpccore_cost = {
06a67bdd
RS		 395 COSTS_N_INSNS (2), /* mulsi */
396 COSTS_N_INSNS (2), /* mulsi_const */
397 COSTS_N_INSNS (2), /* mulsi_const9 */
398 COSTS_N_INSNS (2), /* muldi */
399 COSTS_N_INSNS (6), /* divsi */
400 COSTS_N_INSNS (6), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (5), /* dmul */
403 COSTS_N_INSNS (10), /* sdiv */
404 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 405};
406
407/* Instruction costs on PPC403 processors. */
408static const
409struct processor_costs ppc403_cost = {
06a67bdd
RS		 410 COSTS_N_INSNS (4), /* mulsi */
411 COSTS_N_INSNS (4), /* mulsi_const */
412 COSTS_N_INSNS (4), /* mulsi_const9 */
413 COSTS_N_INSNS (4), /* muldi */
414 COSTS_N_INSNS (33), /* divsi */
415 COSTS_N_INSNS (33), /* divdi */
416 COSTS_N_INSNS (11), /* fp */
417 COSTS_N_INSNS (11), /* dmul */
418 COSTS_N_INSNS (11), /* sdiv */
419 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 420};
421
422/* Instruction costs on PPC405 processors. */
423static const
424struct processor_costs ppc405_cost = {
06a67bdd
RS		 425 COSTS_N_INSNS (5), /* mulsi */
426 COSTS_N_INSNS (4), /* mulsi_const */
427 COSTS_N_INSNS (3), /* mulsi_const9 */
428 COSTS_N_INSNS (5), /* muldi */
429 COSTS_N_INSNS (35), /* divsi */
430 COSTS_N_INSNS (35), /* divdi */
431 COSTS_N_INSNS (11), /* fp */
432 COSTS_N_INSNS (11), /* dmul */
433 COSTS_N_INSNS (11), /* sdiv */
434 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 435};
436
437/* Instruction costs on PPC440 processors. */
438static const
439struct processor_costs ppc440_cost = {
06a67bdd
RS		 440 COSTS_N_INSNS (3), /* mulsi */
441 COSTS_N_INSNS (2), /* mulsi_const */
442 COSTS_N_INSNS (2), /* mulsi_const9 */
443 COSTS_N_INSNS (3), /* muldi */
444 COSTS_N_INSNS (34), /* divsi */
445 COSTS_N_INSNS (34), /* divdi */
446 COSTS_N_INSNS (5), /* fp */
447 COSTS_N_INSNS (5), /* dmul */
448 COSTS_N_INSNS (19), /* sdiv */
449 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 450};
451
452/* Instruction costs on PPC601 processors. */
453static const
454struct processor_costs ppc601_cost = {
06a67bdd
RS		 455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (5), /* mulsi_const */
457 COSTS_N_INSNS (5), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (36), /* divsi */
460 COSTS_N_INSNS (36), /* divdi */
461 COSTS_N_INSNS (4), /* fp */
462 COSTS_N_INSNS (5), /* dmul */
463 COSTS_N_INSNS (17), /* sdiv */
464 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 465};
466
467/* Instruction costs on PPC603 processors. */
468static const
469struct processor_costs ppc603_cost = {
06a67bdd
RS		 470 COSTS_N_INSNS (5), /* mulsi */
471 COSTS_N_INSNS (3), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (5), /* muldi */
474 COSTS_N_INSNS (37), /* divsi */
475 COSTS_N_INSNS (37), /* divdi */
476 COSTS_N_INSNS (3), /* fp */
477 COSTS_N_INSNS (4), /* dmul */
478 COSTS_N_INSNS (18), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 480};
481
482/* Instruction costs on PPC604 processors. */
483static const
484struct processor_costs ppc604_cost = {
06a67bdd
RS		 485 COSTS_N_INSNS (4), /* mulsi */
486 COSTS_N_INSNS (4), /* mulsi_const */
487 COSTS_N_INSNS (4), /* mulsi_const9 */
488 COSTS_N_INSNS (4), /* muldi */
489 COSTS_N_INSNS (20), /* divsi */
490 COSTS_N_INSNS (20), /* divdi */
491 COSTS_N_INSNS (3), /* fp */
492 COSTS_N_INSNS (3), /* dmul */
493 COSTS_N_INSNS (18), /* sdiv */
494 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 495};
496
497/* Instruction costs on PPC604e processors. */
498static const
499struct processor_costs ppc604e_cost = {
06a67bdd
RS		 500 COSTS_N_INSNS (2), /* mulsi */
501 COSTS_N_INSNS (2), /* mulsi_const */
502 COSTS_N_INSNS (2), /* mulsi_const9 */
503 COSTS_N_INSNS (2), /* muldi */
504 COSTS_N_INSNS (20), /* divsi */
505 COSTS_N_INSNS (20), /* divdi */
506 COSTS_N_INSNS (3), /* fp */
507 COSTS_N_INSNS (3), /* dmul */
508 COSTS_N_INSNS (18), /* sdiv */
509 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 510};
511
f0517163 512/* Instruction costs on PPC620 processors. */
8b897cfa
RS		 513static const
514struct processor_costs ppc620_cost = {
06a67bdd
RS		 515 COSTS_N_INSNS (5), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (3), /* mulsi_const9 */
518 COSTS_N_INSNS (7), /* muldi */
519 COSTS_N_INSNS (21), /* divsi */
520 COSTS_N_INSNS (37), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
f0517163
RS		 525};
526
527/* Instruction costs on PPC630 processors. */
528static const
529struct processor_costs ppc630_cost = {
06a67bdd
RS		 530 COSTS_N_INSNS (5), /* mulsi */
531 COSTS_N_INSNS (4), /* mulsi_const */
532 COSTS_N_INSNS (3), /* mulsi_const9 */
533 COSTS_N_INSNS (7), /* muldi */
534 COSTS_N_INSNS (21), /* divsi */
535 COSTS_N_INSNS (37), /* divdi */
536 COSTS_N_INSNS (3), /* fp */
537 COSTS_N_INSNS (3), /* dmul */
538 COSTS_N_INSNS (17), /* sdiv */
539 COSTS_N_INSNS (21), /* ddiv */
8b897cfa
RS		 540};
541
542/* Instruction costs on PPC750 and PPC7400 processors. */
543static const
544struct processor_costs ppc750_cost = {
06a67bdd
RS		 545 COSTS_N_INSNS (5), /* mulsi */
546 COSTS_N_INSNS (3), /* mulsi_const */
547 COSTS_N_INSNS (2), /* mulsi_const9 */
548 COSTS_N_INSNS (5), /* muldi */
549 COSTS_N_INSNS (17), /* divsi */
550 COSTS_N_INSNS (17), /* divdi */
551 COSTS_N_INSNS (3), /* fp */
552 COSTS_N_INSNS (3), /* dmul */
553 COSTS_N_INSNS (17), /* sdiv */
554 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 555};
556
557/* Instruction costs on PPC7450 processors. */
558static const
559struct processor_costs ppc7450_cost = {
06a67bdd
RS		 560 COSTS_N_INSNS (4), /* mulsi */
561 COSTS_N_INSNS (3), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (4), /* muldi */
564 COSTS_N_INSNS (23), /* divsi */
565 COSTS_N_INSNS (23), /* divdi */
566 COSTS_N_INSNS (5), /* fp */
567 COSTS_N_INSNS (5), /* dmul */
568 COSTS_N_INSNS (21), /* sdiv */
569 COSTS_N_INSNS (35), /* ddiv */
8b897cfa 570};
a3170dc6 571
8b897cfa
RS		 572/* Instruction costs on PPC8540 processors. */
573static const
574struct processor_costs ppc8540_cost = {
06a67bdd
RS		 575 COSTS_N_INSNS (4), /* mulsi */
576 COSTS_N_INSNS (4), /* mulsi_const */
577 COSTS_N_INSNS (4), /* mulsi_const9 */
578 COSTS_N_INSNS (4), /* muldi */
579 COSTS_N_INSNS (19), /* divsi */
580 COSTS_N_INSNS (19), /* divdi */
581 COSTS_N_INSNS (4), /* fp */
582 COSTS_N_INSNS (4), /* dmul */
583 COSTS_N_INSNS (29), /* sdiv */
584 COSTS_N_INSNS (29), /* ddiv */
8b897cfa
RS		 585};
586
587/* Instruction costs on POWER4 and POWER5 processors. */
588static const
589struct processor_costs power4_cost = {
06a67bdd
RS		 590 COSTS_N_INSNS (3), /* mulsi */
591 COSTS_N_INSNS (2), /* mulsi_const */
592 COSTS_N_INSNS (2), /* mulsi_const9 */
593 COSTS_N_INSNS (4), /* muldi */
594 COSTS_N_INSNS (18), /* divsi */
595 COSTS_N_INSNS (34), /* divdi */
596 COSTS_N_INSNS (3), /* fp */
597 COSTS_N_INSNS (3), /* dmul */
598 COSTS_N_INSNS (17), /* sdiv */
599 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 600};
601
602\f
a2369ed3 603static bool rs6000_function_ok_for_sibcall (tree, tree);
a2369ed3
DJ		 604static rtx rs6000_generate_compare (enum rtx_code);
605static void rs6000_maybe_dead (rtx);
606static void rs6000_emit_stack_tie (void);
607static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
608static rtx spe_synthesize_frame_save (rtx);
609static bool spe_func_has_64bit_regs_p (void);
b20a9cca 610static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
d1d0c603 611 int, HOST_WIDE_INT);
a2369ed3
DJ		 612static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
613static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
614static unsigned rs6000_hash_constant (rtx);
615static unsigned toc_hash_function (const void *);
616static int toc_hash_eq (const void *, const void *);
617static int constant_pool_expr_1 (rtx, int *, int *);
618static bool constant_pool_expr_p (rtx);
a2369ed3 619static bool legitimate_small_data_p (enum machine_mode, rtx);
a2369ed3 620static bool legitimate_indexed_address_p (rtx, int);
a2369ed3
DJ		 621static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
622static struct machine_function * rs6000_init_machine_status (void);
623static bool rs6000_assemble_integer (rtx, unsigned int, int);
5add3202 624#ifdef HAVE_GAS_HIDDEN
a2369ed3 625static void rs6000_assemble_visibility (tree, int);
5add3202 626#endif
a2369ed3
DJ		 627static int rs6000_ra_ever_killed (void);
628static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
8bb418a3 629static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
76d2b81d 630static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
f18eca82 631static const char *rs6000_mangle_fundamental_type (tree);
b86fe7b4 632extern const struct attribute_spec rs6000_attribute_table[];
a2369ed3
DJ		 633static void rs6000_set_default_type_attributes (tree);
634static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
635static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
b20a9cca
AM		 636static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
637 tree);
a2369ed3 638static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
c6e8c921 639static bool rs6000_return_in_memory (tree, tree);
a2369ed3 640static void rs6000_file_start (void);
7c262518 641#if TARGET_ELF
a2369ed3
DJ		 642static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
643static void rs6000_elf_asm_out_constructor (rtx, int);
644static void rs6000_elf_asm_out_destructor (rtx, int);
645static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
646static void rs6000_elf_unique_section (tree, int);
647static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
b20a9cca 648 unsigned HOST_WIDE_INT);
a56d7372 649static void rs6000_elf_encode_section_info (tree, rtx, int)
0e5dbd9b 650 ATTRIBUTE_UNUSED;
a2369ed3 651static bool rs6000_elf_in_small_data_p (tree);
7c262518 652#endif
cbaaba19 653#if TARGET_XCOFF
a2369ed3 654static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
8210e4c4 655static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
a2369ed3
DJ		 656static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
657static void rs6000_xcoff_unique_section (tree, int);
658static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
b20a9cca 659 unsigned HOST_WIDE_INT);
a2369ed3
DJ		 660static const char * rs6000_xcoff_strip_name_encoding (const char *);
661static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
662static void rs6000_xcoff_file_start (void);
663static void rs6000_xcoff_file_end (void);
f1384257
AM		 664#endif
665#if TARGET_MACHO
a2369ed3 666static bool rs6000_binds_local_p (tree);
f1384257 667#endif
a2369ed3
DJ		 668static int rs6000_variable_issue (FILE *, int, rtx, int);
669static bool rs6000_rtx_costs (rtx, int, int, int *);
670static int rs6000_adjust_cost (rtx, rtx, rtx, int);
cbe26ab8 671static bool is_microcoded_insn (rtx);
79ae11c4 672static int is_dispatch_slot_restricted (rtx);
cbe26ab8
DN		 673static bool is_cracked_insn (rtx);
674static bool is_branch_slot_insn (rtx);
a2369ed3
DJ		 675static int rs6000_adjust_priority (rtx, int);
676static int rs6000_issue_rate (void);
569fa502 677static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
cbe26ab8
DN		 678static rtx get_next_active_insn (rtx, rtx);
679static bool insn_terminates_group_p (rtx , enum group_termination);
680static bool is_costly_group (rtx *, rtx);
681static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
682static int redefine_groups (FILE *, int, rtx, rtx);
683static int pad_groups (FILE *, int, rtx, rtx);
684static void rs6000_sched_finish (FILE *, int);
a2369ed3 685static int rs6000_use_sched_lookahead (void);
7ccf35ed 686static tree rs6000_builtin_mask_for_load (void);
a2369ed3
DJ		 687
688static void rs6000_init_builtins (void);
689static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
690static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
691static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
692static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
693static void altivec_init_builtins (void);
694static void rs6000_common_init_builtins (void);
c15c90bb 695static void rs6000_init_libfuncs (void);
a2369ed3 696
b20a9cca
AM		 697static void enable_mask_for_builtins (struct builtin_description *, int,
698 enum rs6000_builtins,
699 enum rs6000_builtins);
7c62e993 700static tree build_opaque_vector_type (tree, int);
a2369ed3
DJ		 701static void spe_init_builtins (void);
702static rtx spe_expand_builtin (tree, rtx, bool *);
61bea3b0 703static rtx spe_expand_stv_builtin (enum insn_code, tree);
a2369ed3
DJ		 704static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
705static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
706static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
d1d0c603
JJ		 707static rs6000_stack_t *rs6000_stack_info (void);
708static void debug_stack_info (rs6000_stack_t *);
a2369ed3
DJ		 709
710static rtx altivec_expand_builtin (tree, rtx, bool *);
711static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
712static rtx altivec_expand_st_builtin (tree, rtx, bool *);
713static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
714static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
f676971a 715static rtx altivec_expand_predicate_builtin (enum insn_code,
c4ad648e 716 const char *, tree, rtx);
b4a62fa0 717static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
a2369ed3
DJ		 718static rtx altivec_expand_stv_builtin (enum insn_code, tree);
719static void rs6000_parse_abi_options (void);
720static void rs6000_parse_alignment_option (void);
721static void rs6000_parse_tls_size_option (void);
5da702b1 722static void rs6000_parse_yes_no_option (const char *, const char *, int *);
4d4cbc0e 723static void rs6000_parse_float_gprs_option (void);
a2369ed3
DJ		 724static int first_altivec_reg_to_save (void);
725static unsigned int compute_vrsave_mask (void);
9390387d 726static void compute_save_world_info (rs6000_stack_t *info_ptr);
a2369ed3
DJ		 727static void is_altivec_return_reg (rtx, void *);
728static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
729int easy_vector_constant (rtx, enum machine_mode);
a2369ed3
DJ		 730static bool is_ev64_opaque_type (tree);
731static rtx rs6000_dwarf_register_span (rtx);
732static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
733static rtx rs6000_tls_get_addr (void);
734static rtx rs6000_got_sym (void);
9390387d 735static int rs6000_tls_symbol_ref_1 (rtx *, void *);
a2369ed3
DJ		 736static const char *rs6000_get_some_local_dynamic_name (void);
737static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
ded9bf77 738static rtx rs6000_complex_function_value (enum machine_mode);
b20a9cca 739static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
a2369ed3 740 enum machine_mode, tree);
0b5383eb
DJ		 741static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
742 HOST_WIDE_INT);
743static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
744 tree, HOST_WIDE_INT);
745static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
746 HOST_WIDE_INT,
747 rtx[], int *);
748static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
749 tree, HOST_WIDE_INT,
750 rtx[], int *);
751static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
ec6376ab 752static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
b1917422 753static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
c6e8c921
GK		 754static void setup_incoming_varargs (CUMULATIVE_ARGS *,
755 enum machine_mode, tree,
756 int *, int);
8cd5a4e0
RH		 757static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
758 tree, bool);
78a52f11
RH		 759static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
760 tree, bool);
4d3e6fae 761static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
efdba735
SH		 762#if TARGET_MACHO
763static void macho_branch_islands (void);
764static void add_compiler_branch_island (tree, tree, int);
765static int no_previous_def (tree function_name);
766static tree get_prev_label (tree function_name);
c4e18b1c 767static void rs6000_darwin_file_start (void);
efdba735
SH		 768#endif
769
c35d187f 770static tree rs6000_build_builtin_va_list (void);
23a60a04 771static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
fe984136 772static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
f676971a 773static bool rs6000_vector_mode_supported_p (enum machine_mode);
94ff898d 774static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
21213b4c 775 enum machine_mode);
94ff898d 776static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
21213b4c
DP		 777 enum machine_mode);
778static int get_vsel_insn (enum machine_mode);
779static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
17211ab5 780
21213b4c
DP		 781
782const int INSN_NOT_AVAILABLE = -1;
93f90be6
FJ		 783static enum machine_mode rs6000_eh_return_filter_mode (void);
784
17211ab5
GK		 785/* Hash table stuff for keeping track of TOC entries. */
786
787struct toc_hash_struct GTY(())
788{
789 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
790 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
791 rtx key;
792 enum machine_mode key_mode;
793 int labelno;
794};
795
796static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
c81bebd7
MM		 797\f
798/* Default register names. */
799char rs6000_reg_names[][8] =
800{
802a0058
MM		 801 "0", "1", "2", "3", "4", "5", "6", "7",
802 "8", "9", "10", "11", "12", "13", "14", "15",
803 "16", "17", "18", "19", "20", "21", "22", "23",
804 "24", "25", "26", "27", "28", "29", "30", "31",
805 "0", "1", "2", "3", "4", "5", "6", "7",
806 "8", "9", "10", "11", "12", "13", "14", "15",
807 "16", "17", "18", "19", "20", "21", "22", "23",
808 "24", "25", "26", "27", "28", "29", "30", "31",
809 "mq", "lr", "ctr","ap",
810 "0", "1", "2", "3", "4", "5", "6", "7",
0ac081f6
AH		 811 "xer",
812 /* AltiVec registers. */
0cd5e3a1
AH		 813 "0", "1", "2", "3", "4", "5", "6", "7",
814 "8", "9", "10", "11", "12", "13", "14", "15",
815 "16", "17", "18", "19", "20", "21", "22", "23",
816 "24", "25", "26", "27", "28", "29", "30", "31",
59a4c851
AH		 817 "vrsave", "vscr",
818 /* SPE registers. */
819 "spe_acc", "spefscr"
c81bebd7
MM		 820};
821
822#ifdef TARGET_REGNAMES
8b60264b 823static const char alt_reg_names[][8] =
c81bebd7 824{
802a0058
MM		 825 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
826 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
827 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
828 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
829 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
830 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
831 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
832 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
833 "mq", "lr", "ctr", "ap",
834 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
0ac081f6 835 "xer",
59a4c851 836 /* AltiVec registers. */
0ac081f6 837 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
59a4c851
AH		 838 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
839 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
840 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
841 "vrsave", "vscr",
842 /* SPE registers. */
843 "spe_acc", "spefscr"
c81bebd7
MM		 844};
845#endif
9878760c 846\f
daf11973
MM		 847#ifndef MASK_STRICT_ALIGN
848#define MASK_STRICT_ALIGN 0
849#endif
ffcfcb5f
AM		 850#ifndef TARGET_PROFILE_KERNEL
851#define TARGET_PROFILE_KERNEL 0
852#endif
3961e8fe
RH		 853
854/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
855#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
672a6f42
NB		 856\f
857/* Initialize the GCC target structure. */
91d231cb
JM		 858#undef TARGET_ATTRIBUTE_TABLE
859#define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
a5c76ee6
ZW		 860#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
861#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
daf11973 862
301d03af
RS		 863#undef TARGET_ASM_ALIGNED_DI_OP
864#define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
865
866/* Default unaligned ops are only provided for ELF. Find the ops needed
867 for non-ELF systems. */
868#ifndef OBJECT_FORMAT_ELF
cbaaba19 869#if TARGET_XCOFF
ae6c1efd 870/* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
301d03af
RS		 871 64-bit targets. */
872#undef TARGET_ASM_UNALIGNED_HI_OP
873#define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
874#undef TARGET_ASM_UNALIGNED_SI_OP
875#define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
876#undef TARGET_ASM_UNALIGNED_DI_OP
877#define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
878#else
879/* For Darwin. */
880#undef TARGET_ASM_UNALIGNED_HI_OP
881#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
882#undef TARGET_ASM_UNALIGNED_SI_OP
883#define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
49bd1d27
SS		 884#undef TARGET_ASM_UNALIGNED_DI_OP
885#define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
886#undef TARGET_ASM_ALIGNED_DI_OP
887#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
301d03af
RS		 888#endif
889#endif
890
891/* This hook deals with fixups for relocatable code and DI-mode objects
892 in 64-bit code. */
893#undef TARGET_ASM_INTEGER
894#define TARGET_ASM_INTEGER rs6000_assemble_integer
895
93638d7a
AM		 896#ifdef HAVE_GAS_HIDDEN
897#undef TARGET_ASM_ASSEMBLE_VISIBILITY
898#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
899#endif
900
c4501e62
JJ		 901#undef TARGET_HAVE_TLS
902#define TARGET_HAVE_TLS HAVE_AS_TLS
903
904#undef TARGET_CANNOT_FORCE_CONST_MEM
905#define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
906
08c148a8
NB		 907#undef TARGET_ASM_FUNCTION_PROLOGUE
908#define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
909#undef TARGET_ASM_FUNCTION_EPILOGUE
910#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
911
b54cf83a
DE		 912#undef TARGET_SCHED_VARIABLE_ISSUE
913#define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
914
c237e94a
ZW		 915#undef TARGET_SCHED_ISSUE_RATE
916#define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
917#undef TARGET_SCHED_ADJUST_COST
918#define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
919#undef TARGET_SCHED_ADJUST_PRIORITY
920#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
f676971a 921#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
569fa502 922#define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
cbe26ab8
DN		 923#undef TARGET_SCHED_FINISH
924#define TARGET_SCHED_FINISH rs6000_sched_finish
c237e94a 925
be12c2b0
VM		 926#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
927#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
928
7ccf35ed
DN		 929#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
930#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
931
0ac081f6
AH		 932#undef TARGET_INIT_BUILTINS
933#define TARGET_INIT_BUILTINS rs6000_init_builtins
934
935#undef TARGET_EXPAND_BUILTIN
936#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
937
f18eca82
ZL		 938#undef TARGET_MANGLE_FUNDAMENTAL_TYPE
939#define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
940
c15c90bb
ZW		 941#undef TARGET_INIT_LIBFUNCS
942#define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
943
f1384257 944#if TARGET_MACHO
0e5dbd9b
DE		 945#undef TARGET_BINDS_LOCAL_P
946#define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
f1384257 947#endif
0e5dbd9b 948
3961e8fe
RH		 949#undef TARGET_ASM_OUTPUT_MI_THUNK
950#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
951
3961e8fe 952#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5b71a4e7 953#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
00b960c7 954
4977bab6
ZW		 955#undef TARGET_FUNCTION_OK_FOR_SIBCALL
956#define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
957
3c50106f
RH		 958#undef TARGET_RTX_COSTS
959#define TARGET_RTX_COSTS rs6000_rtx_costs
dcefdf67
RH		 960#undef TARGET_ADDRESS_COST
961#define TARGET_ADDRESS_COST hook_int_rtx_0
3c50106f 962
c8e4f0e9
AH		 963#undef TARGET_VECTOR_OPAQUE_P
964#define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
62e1dfcf 965
96714395
AH		 966#undef TARGET_DWARF_REGISTER_SPAN
967#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
968
c6e8c921
GK		 969/* On rs6000, function arguments are promoted, as are function return
970 values. */
971#undef TARGET_PROMOTE_FUNCTION_ARGS
972#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
973#undef TARGET_PROMOTE_FUNCTION_RETURN
974#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
975
c6e8c921
GK		 976#undef TARGET_RETURN_IN_MEMORY
977#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
978
979#undef TARGET_SETUP_INCOMING_VARARGS
980#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
981
982/* Always strict argument naming on rs6000. */
983#undef TARGET_STRICT_ARGUMENT_NAMING
984#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
985#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
986#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
42ba5130
RH		 987#undef TARGET_SPLIT_COMPLEX_ARG
988#define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
fe984136
RH		 989#undef TARGET_MUST_PASS_IN_STACK
990#define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
8cd5a4e0
RH		 991#undef TARGET_PASS_BY_REFERENCE
992#define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
78a52f11
RH		 993#undef TARGET_ARG_PARTIAL_BYTES
994#define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
c6e8c921 995
c35d187f
RH		 996#undef TARGET_BUILD_BUILTIN_VA_LIST
997#define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
998
cd3ce9b4
JM		 999#undef TARGET_GIMPLIFY_VA_ARG_EXPR
1000#define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1001
93f90be6
FJ		 1002#undef TARGET_EH_RETURN_FILTER_MODE
1003#define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1004
f676971a
EC		 1005#undef TARGET_VECTOR_MODE_SUPPORTED_P
1006#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1007
4d3e6fae
FJ		 1008#undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1009#define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1010
445cf5eb
JM		 1011/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1012 The PowerPC architecture requires only weak consistency among
1013 processors--that is, memory accesses between processors need not be
1014 sequentially consistent and memory accesses among processors can occur
1015 in any order. The ability to order memory accesses weakly provides
1016 opportunities for more efficient use of the system bus. Unless a
1017 dependency exists, the 604e allows read operations to precede store
1018 operations. */
1019#undef TARGET_RELAXED_ORDERING
1020#define TARGET_RELAXED_ORDERING true
1021
f6897b10 1022struct gcc_target targetm = TARGET_INITIALIZER;
672a6f42 1023\f
0d1fbc8c
AH		 1024
1025/* Value is 1 if hard register REGNO can hold a value of machine-mode
1026 MODE. */
1027static int
1028rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1029{
1030 /* The GPRs can hold any mode, but values bigger than one register
1031 cannot go past R31. */
1032 if (INT_REGNO_P (regno))
1033 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1034
1035 /* The float registers can only hold floating modes and DImode. */
1036 if (FP_REGNO_P (regno))
1037 return
1038 (GET_MODE_CLASS (mode) == MODE_FLOAT
1039 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1040 || (GET_MODE_CLASS (mode) == MODE_INT
1041 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1042
1043 /* The CR register can only hold CC modes. */
1044 if (CR_REGNO_P (regno))
1045 return GET_MODE_CLASS (mode) == MODE_CC;
1046
1047 if (XER_REGNO_P (regno))
1048 return mode == PSImode;
1049
1050 /* AltiVec only in AldyVec registers. */
1051 if (ALTIVEC_REGNO_P (regno))
1052 return ALTIVEC_VECTOR_MODE (mode);
1053
1054 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1055 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1056 return 1;
1057
1058 /* We cannot put TImode anywhere except general register and it must be
1059 able to fit within the register set. */
1060
1061 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1062}
1063
1064/* Initialize rs6000_hard_regno_mode_ok_p table. */
1065static void
1066rs6000_init_hard_regno_mode_ok (void)
1067{
1068 int r, m;
1069
1070 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1071 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1072 if (rs6000_hard_regno_mode_ok (r, m))
1073 rs6000_hard_regno_mode_ok_p[m][r] = true;
1074}
1075
c1e55850
GK		 1076/* If not otherwise specified by a target, make 'long double' equivalent to
1077 'double'. */
1078
1079#ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1080#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1081#endif
1082
5248c961
RK		 1083/* Override command line options. Mostly we process the processor
1084 type and sometimes adjust other TARGET_ options. */
1085
1086void
d779d0dc 1087rs6000_override_options (const char *default_cpu)
5248c961 1088{
c4d38ccb 1089 size_t i, j;
8e3f41e7 1090 struct rs6000_cpu_select *ptr;
66188a7e 1091 int set_masks;
5248c961 1092
66188a7e 1093 /* Simplifications for entries below. */
85638c0d 1094
66188a7e
GK		 1095 enum {
1096 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1097 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1098 };
85638c0d 1099
66188a7e
GK		 1100 /* This table occasionally claims that a processor does not support
1101 a particular feature even though it does, but the feature is slower
1102 than the alternative. Thus, it shouldn't be relied on as a
f676971a 1103 complete description of the processor's support.
66188a7e
GK		 1104
1105 Please keep this list in order, and don't forget to update the
1106 documentation in invoke.texi when adding a new processor or
1107 flag. */
5248c961
RK		 1108 static struct ptt
1109 {
8b60264b
KG		 1110 const char *const name; /* Canonical processor name. */
1111 const enum processor_type processor; /* Processor type enum value. */
1112 const int target_enable; /* Target flags to enable. */
8b60264b 1113 } const processor_target_table[]
66188a7e 1114 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
49a0b204 1115 {"403", PROCESSOR_PPC403,
66188a7e
GK		 1116 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1117 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1118 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1119 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1120 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1121 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
5248c961 1122 {"601", PROCESSOR_PPC601,
66188a7e
GK		 1123 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1124 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1125 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1127 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
7ddb6568
AM		 1129 {"620", PROCESSOR_PPC620,
1130 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1131 {"630", PROCESSOR_PPC630,
1132 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
66188a7e
GK		 1133 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1135 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1136 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1137 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1138 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1139 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
4d4cbc0e
AH		 1141 /* 8548 has a dummy entry for now. */
1142 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
66188a7e 1143 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
7177e720 1144 {"970", PROCESSOR_POWER4,
66188a7e
GK		 1145 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1146 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1147 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1148 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1149 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
49ffe578 1150 {"G5", PROCESSOR_POWER4,
66188a7e
GK		 1151 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1152 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1153 {"power2", PROCESSOR_POWER,
1154 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
7ddb6568
AM		 1155 {"power3", PROCESSOR_PPC630,
1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1157 {"power4", PROCESSOR_POWER4,
fc091c8e 1158 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
ec507f2d 1159 {"power5", PROCESSOR_POWER5,
fc091c8e 1160 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
66188a7e
GK		 1161 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1162 {"powerpc64", PROCESSOR_POWERPC64,
1163 POWERPC_BASE_MASK | MASK_POWERPC64},
1164 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1165 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1166 {"rios2", PROCESSOR_RIOS2,
1167 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1168 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1169 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
7ddb6568 1170 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
66188a7e 1171 };
5248c961 1172
ca7558fc 1173 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
5248c961 1174
66188a7e
GK		 1175 /* Some OSs don't support saving the high part of 64-bit registers on
1176 context switch. Other OSs don't support saving Altivec registers.
1177 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1178 settings; if the user wants either, the user must explicitly specify
1179 them and we won't interfere with the user's specification. */
1180
1181 enum {
1182 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
f676971a 1183 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
66188a7e
GK		 1184 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1185 | MASK_MFCRF)
1186 };
0d1fbc8c
AH		 1187
1188 rs6000_init_hard_regno_mode_ok ();
1189
c4ad648e 1190 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
66188a7e
GK		 1191#ifdef OS_MISSING_POWERPC64
1192 if (OS_MISSING_POWERPC64)
1193 set_masks &= ~MASK_POWERPC64;
1194#endif
1195#ifdef OS_MISSING_ALTIVEC
1196 if (OS_MISSING_ALTIVEC)
1197 set_masks &= ~MASK_ALTIVEC;
1198#endif
1199
768875a8
AM		 1200 /* Don't override by the processor default if given explicitly. */
1201 set_masks &= ~target_flags_explicit;
957211c3 1202
a4f6c312 1203 /* Identify the processor type. */
8e3f41e7 1204 rs6000_select[0].string = default_cpu;
3cb999d8 1205 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
8e3f41e7 1206
b6a1cbae 1207 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
5248c961 1208 {
8e3f41e7
MM		 1209 ptr = &rs6000_select[i];
1210 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
5248c961 1211 {
8e3f41e7
MM		 1212 for (j = 0; j < ptt_size; j++)
1213 if (! strcmp (ptr->string, processor_target_table[j].name))
1214 {
1215 if (ptr->set_tune_p)
1216 rs6000_cpu = processor_target_table[j].processor;
1217
1218 if (ptr->set_arch_p)
1219 {
66188a7e
GK		 1220 target_flags &= ~set_masks;
1221 target_flags |= (processor_target_table[j].target_enable
1222 & set_masks);
8e3f41e7
MM		 1223 }
1224 break;
1225 }
1226
4406229e 1227 if (j == ptt_size)
8e3f41e7 1228 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
5248c961
RK		 1229 }
1230 }
8a61d227 1231
993f19a8 1232 if (TARGET_E500)
a3170dc6
AH		 1233 rs6000_isel = 1;
1234
dff9f1b6
DE		 1235 /* If we are optimizing big endian systems for space, use the load/store
1236 multiple and string instructions. */
ef792183 1237 if (BYTES_BIG_ENDIAN && optimize_size)
957211c3 1238 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
938937d8 1239
a4f6c312
SS		 1240 /* Don't allow -mmultiple or -mstring on little endian systems
1241 unless the cpu is a 750, because the hardware doesn't support the
1242 instructions used in little endian mode, and causes an alignment
1243 trap. The 750 does not cause an alignment trap (except when the
1244 target is unaligned). */
bef84347 1245
b21fb038 1246 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
7e69e155
MM		 1247 {
1248 if (TARGET_MULTIPLE)
1249 {
1250 target_flags &= ~MASK_MULTIPLE;
b21fb038 1251 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
7e69e155
MM		 1252 warning ("-mmultiple is not supported on little endian systems");
1253 }
1254
1255 if (TARGET_STRING)
1256 {
1257 target_flags &= ~MASK_STRING;
b21fb038 1258 if ((target_flags_explicit & MASK_STRING) != 0)
938937d8 1259 warning ("-mstring is not supported on little endian systems");
7e69e155
MM		 1260 }
1261 }
3933e0e1 1262
38c1f2d7
MM		 1263 /* Set debug flags */
1264 if (rs6000_debug_name)
1265 {
bfc79d3b 1266 if (! strcmp (rs6000_debug_name, "all"))
38c1f2d7 1267 rs6000_debug_stack = rs6000_debug_arg = 1;
bfc79d3b 1268 else if (! strcmp (rs6000_debug_name, "stack"))
38c1f2d7 1269 rs6000_debug_stack = 1;
bfc79d3b 1270 else if (! strcmp (rs6000_debug_name, "arg"))
38c1f2d7
MM		 1271 rs6000_debug_arg = 1;
1272 else
c725bd79 1273 error ("unknown -mdebug-%s switch", rs6000_debug_name);
38c1f2d7
MM		 1274 }
1275
57ac7be9
AM		 1276 if (rs6000_traceback_name)
1277 {
1278 if (! strncmp (rs6000_traceback_name, "full", 4))
1279 rs6000_traceback = traceback_full;
1280 else if (! strncmp (rs6000_traceback_name, "part", 4))
1281 rs6000_traceback = traceback_part;
1282 else if (! strncmp (rs6000_traceback_name, "no", 2))
1283 rs6000_traceback = traceback_none;
1284 else
9e637a26 1285 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
57ac7be9
AM		 1286 rs6000_traceback_name);
1287 }
1288
6fa3f289 1289 /* Set size of long double */
c1e55850 1290 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
6fa3f289
ZW		 1291 if (rs6000_long_double_size_string)
1292 {
1293 char *tail;
1294 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1295 if (*tail != '\0' || (size != 64 && size != 128))
1296 error ("Unknown switch -mlong-double-%s",
1297 rs6000_long_double_size_string);
1298 else
1299 rs6000_long_double_type_size = size;
1300 }
1301
6d0ef01e
HP		 1302 /* Set Altivec ABI as default for powerpc64 linux. */
1303 if (TARGET_ELF && TARGET_64BIT)
1304 {
1305 rs6000_altivec_abi = 1;
1306 rs6000_altivec_vrsave = 1;
1307 }
1308
594a51fe
SS		 1309 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1310 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1311 {
1312 rs6000_darwin64_abi = 1;
7bd3a493 1313 /* Setting to empty string is same as "-mone-byte-bool". */
9c7956fd 1314#if TARGET_MACHO
7bd3a493 1315 darwin_one_byte_bool = "";
9c7956fd 1316#endif
d9168963
SS		 1317 /* Default to natural alignment, for better performance. */
1318 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
594a51fe
SS		 1319 }
1320
0ac081f6
AH		 1321 /* Handle -mabi= options. */
1322 rs6000_parse_abi_options ();
1323
025d9908
KH		 1324 /* Handle -malign-XXXXX option. */
1325 rs6000_parse_alignment_option ();
1326
4d4cbc0e
AH		 1327 rs6000_parse_float_gprs_option ();
1328
5da702b1
AH		 1329 /* Handle generic -mFOO=YES/NO options. */
1330 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1331 &rs6000_altivec_vrsave);
1332 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1333 &rs6000_isel);
1334 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
993f19a8 1335
c4501e62
JJ		 1336 /* Handle -mtls-size option. */
1337 rs6000_parse_tls_size_option ();
1338
a7ae18e2
AH		 1339#ifdef SUBTARGET_OVERRIDE_OPTIONS
1340 SUBTARGET_OVERRIDE_OPTIONS;
1341#endif
1342#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1343 SUBSUBTARGET_OVERRIDE_OPTIONS;
1344#endif
4d4cbc0e
AH		 1345#ifdef SUB3TARGET_OVERRIDE_OPTIONS
1346 SUB3TARGET_OVERRIDE_OPTIONS;
1347#endif
a7ae18e2 1348
5da702b1
AH		 1349 if (TARGET_E500)
1350 {
e4463bf1
AH		 1351 if (TARGET_ALTIVEC)
1352 error ("AltiVec and E500 instructions cannot coexist");
1353
5da702b1
AH		 1354 /* The e500 does not have string instructions, and we set
1355 MASK_STRING above when optimizing for size. */
1356 if ((target_flags & MASK_STRING) != 0)
1357 target_flags = target_flags & ~MASK_STRING;
b6e59a3a
AH		 1358
1359 /* No SPE means 64-bit long doubles, even if an E500. */
1360 if (rs6000_spe_string != 0
c4ad648e 1361 && !strcmp (rs6000_spe_string, "no"))
b6e59a3a 1362 rs6000_long_double_type_size = 64;
5da702b1
AH		 1363 }
1364 else if (rs6000_select[1].string != NULL)
1365 {
1366 /* For the powerpc-eabispe configuration, we set all these by
1367 default, so let's unset them if we manually set another
1368 CPU that is not the E500. */
1369 if (rs6000_abi_string == 0)
1370 rs6000_spe_abi = 0;
1371 if (rs6000_spe_string == 0)
1372 rs6000_spe = 0;
1373 if (rs6000_float_gprs_string == 0)
1374 rs6000_float_gprs = 0;
1375 if (rs6000_isel_string == 0)
1376 rs6000_isel = 0;
b6e59a3a 1377 if (rs6000_long_double_size_string == 0)
c1e55850 1378 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
5da702b1 1379 }
b5044283 1380
ec507f2d
DE		 1381 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1382 && rs6000_cpu != PROCESSOR_POWER5);
1383 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1384 || rs6000_cpu == PROCESSOR_POWER5);
1385
a5c76ee6
ZW		 1386 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1387 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1388 bits in target_flags so TARGET_SWITCHES cannot be used.
1389 Assumption here is that rs6000_longcall_switch points into the
1390 text of the complete option, rather than being a copy, so we can
1391 scan back for the presence or absence of the no- modifier. */
1392 if (rs6000_longcall_switch)
1393 {
1394 const char *base = rs6000_longcall_switch;
1395 while (base[-1] != 'm') base--;
1396
1397 if (*rs6000_longcall_switch != '\0')
9e637a26 1398 error ("invalid option %qs", base);
a5c76ee6
ZW		 1399 rs6000_default_long_calls = (base[0] != 'n');
1400 }
1401
8bb418a3
ZL		 1402 /* Handle -m(no-)warn-altivec-long similarly. */
1403 if (rs6000_warn_altivec_long_switch)
1404 {
1405 const char *base = rs6000_warn_altivec_long_switch;
1406 while (base[-1] != 'm') base--;
1407
1408 if (*rs6000_warn_altivec_long_switch != '\0')
9e637a26 1409 error ("invalid option %qs", base);
8bb418a3
ZL		 1410 rs6000_warn_altivec_long = (base[0] != 'n');
1411 }
1412
cbe26ab8 1413 /* Handle -mprioritize-restricted-insns option. */
ec507f2d
DE		 1414 rs6000_sched_restricted_insns_priority
1415 = (rs6000_sched_groups ? 1 : 0);
79ae11c4
DN		 1416 if (rs6000_sched_restricted_insns_priority_str)
1417 rs6000_sched_restricted_insns_priority =
1418 atoi (rs6000_sched_restricted_insns_priority_str);
1419
569fa502 1420 /* Handle -msched-costly-dep option. */
ec507f2d
DE		 1421 rs6000_sched_costly_dep
1422 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
569fa502
DN		 1423 if (rs6000_sched_costly_dep_str)
1424 {
f676971a 1425 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
c4ad648e 1426 rs6000_sched_costly_dep = no_dep_costly;
569fa502 1427 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
c4ad648e 1428 rs6000_sched_costly_dep = all_deps_costly;
569fa502 1429 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
c4ad648e 1430 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
569fa502 1431 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
c4ad648e 1432 rs6000_sched_costly_dep = store_to_load_dep_costly;
f676971a 1433 else
c4ad648e 1434 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
cbe26ab8
DN		 1435 }
1436
1437 /* Handle -minsert-sched-nops option. */
ec507f2d
DE		 1438 rs6000_sched_insert_nops
1439 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
cbe26ab8
DN		 1440 if (rs6000_sched_insert_nops_str)
1441 {
1442 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
c4ad648e 1443 rs6000_sched_insert_nops = sched_finish_none;
cbe26ab8 1444 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
c4ad648e 1445 rs6000_sched_insert_nops = sched_finish_pad_groups;
cbe26ab8 1446 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
c4ad648e 1447 rs6000_sched_insert_nops = sched_finish_regroup_exact;
cbe26ab8 1448 else
c4ad648e 1449 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
569fa502
DN		 1450 }
1451
c81bebd7 1452#ifdef TARGET_REGNAMES
a4f6c312
SS		 1453 /* If the user desires alternate register names, copy in the
1454 alternate names now. */
c81bebd7 1455 if (TARGET_REGNAMES)
4e135bdd 1456 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
c81bebd7
MM		 1457#endif
1458
6fa3f289
ZW		 1459 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1460 If -maix-struct-return or -msvr4-struct-return was explicitly
1461 used, don't override with the ABI default. */
b21fb038 1462 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
6fa3f289
ZW		 1463 {
1464 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1465 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1466 else
1467 target_flags |= MASK_AIX_STRUCT_RET;
1468 }
1469
fcce224d
DE		 1470 if (TARGET_LONG_DOUBLE_128
1471 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
70a01792 1472 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
fcce224d 1473
9ebbca7d
GK		 1474 /* Allocate an alias set for register saves & restores from stack. */
1475 rs6000_sr_alias_set = new_alias_set ();
1476
f676971a 1477 if (TARGET_TOC)
9ebbca7d 1478 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
71f123ca 1479
301d03af
RS		 1480 /* We can only guarantee the availability of DI pseudo-ops when
1481 assembling for 64-bit targets. */
ae6c1efd 1482 if (!TARGET_64BIT)
301d03af
RS		 1483 {
1484 targetm.asm_out.aligned_op.di = NULL;
1485 targetm.asm_out.unaligned_op.di = NULL;
1486 }
1487
1494c534
DE		 1488 /* Set branch target alignment, if not optimizing for size. */
1489 if (!optimize_size)
1490 {
1491 if (rs6000_sched_groups)
1492 {
1493 if (align_functions <= 0)
1494 align_functions = 16;
1495 if (align_jumps <= 0)
1496 align_jumps = 16;
1497 if (align_loops <= 0)
1498 align_loops = 16;
1499 }
1500 if (align_jumps_max_skip <= 0)
1501 align_jumps_max_skip = 15;
1502 if (align_loops_max_skip <= 0)
1503 align_loops_max_skip = 15;
1504 }
2792d578 1505
71f123ca
FS		 1506 /* Arrange to save and restore machine status around nested functions. */
1507 init_machine_status = rs6000_init_machine_status;
42ba5130
RH		 1508
1509 /* We should always be splitting complex arguments, but we can't break
1510 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
18f63bfa 1511 if (DEFAULT_ABI != ABI_AIX)
42ba5130 1512 targetm.calls.split_complex_arg = NULL;
8b897cfa
RS		 1513
1514 /* Initialize rs6000_cost with the appropriate target costs. */
1515 if (optimize_size)
1516 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1517 else
1518 switch (rs6000_cpu)
1519 {
1520 case PROCESSOR_RIOS1:
1521 rs6000_cost = &rios1_cost;
1522 break;
1523
1524 case PROCESSOR_RIOS2:
1525 rs6000_cost = &rios2_cost;
1526 break;
1527
1528 case PROCESSOR_RS64A:
1529 rs6000_cost = &rs64a_cost;
1530 break;
1531
1532 case PROCESSOR_MPCCORE:
1533 rs6000_cost = &mpccore_cost;
1534 break;
1535
1536 case PROCESSOR_PPC403:
1537 rs6000_cost = &ppc403_cost;
1538 break;
1539
1540 case PROCESSOR_PPC405:
1541 rs6000_cost = &ppc405_cost;
1542 break;
1543
1544 case PROCESSOR_PPC440:
1545 rs6000_cost = &ppc440_cost;
1546 break;
1547
1548 case PROCESSOR_PPC601:
1549 rs6000_cost = &ppc601_cost;
1550 break;
1551
1552 case PROCESSOR_PPC603:
1553 rs6000_cost = &ppc603_cost;
1554 break;
1555
1556 case PROCESSOR_PPC604:
1557 rs6000_cost = &ppc604_cost;
1558 break;
1559
1560 case PROCESSOR_PPC604e:
1561 rs6000_cost = &ppc604e_cost;
1562 break;
1563
1564 case PROCESSOR_PPC620:
8b897cfa
RS		 1565 rs6000_cost = &ppc620_cost;
1566 break;
1567
f0517163
RS		 1568 case PROCESSOR_PPC630:
1569 rs6000_cost = &ppc630_cost;
1570 break;
1571
8b897cfa
RS		 1572 case PROCESSOR_PPC750:
1573 case PROCESSOR_PPC7400:
1574 rs6000_cost = &ppc750_cost;
1575 break;
1576
1577 case PROCESSOR_PPC7450:
1578 rs6000_cost = &ppc7450_cost;
1579 break;
1580
1581 case PROCESSOR_PPC8540:
1582 rs6000_cost = &ppc8540_cost;
1583 break;
1584
1585 case PROCESSOR_POWER4:
1586 case PROCESSOR_POWER5:
1587 rs6000_cost = &power4_cost;
1588 break;
1589
1590 default:
1591 abort ();
1592 }
5248c961 1593}
5accd822 1594
7ccf35ed
DN		 1595/* Implement targetm.vectorize.builtin_mask_for_load. */
1596static tree
1597rs6000_builtin_mask_for_load (void)
1598{
1599 if (TARGET_ALTIVEC)
1600 return altivec_builtin_mask_for_load;
1601 else
1602 return 0;
1603}
1604
5da702b1
AH		 1605/* Handle generic options of the form -mfoo=yes/no.
1606 NAME is the option name.
1607 VALUE is the option value.
1608 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1609 whether the option value is 'yes' or 'no' respectively. */
993f19a8 1610static void
5da702b1 1611rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
993f19a8 1612{
5da702b1 1613 if (value == 0)
993f19a8 1614 return;
5da702b1
AH		 1615 else if (!strcmp (value, "yes"))
1616 *flag = 1;
1617 else if (!strcmp (value, "no"))
1618 *flag = 0;
08b57fb3 1619 else
5da702b1 1620 error ("unknown -m%s= option specified: '%s'", name, value);
08b57fb3
AH		 1621}
1622
0ac081f6 1623/* Handle -mabi= options. */
00b960c7 1624static void
863d938c 1625rs6000_parse_abi_options (void)
0ac081f6
AH		 1626{
1627 if (rs6000_abi_string == 0)
1628 return;
1629 else if (! strcmp (rs6000_abi_string, "altivec"))
5cc73f91
AH		 1630 {
1631 rs6000_altivec_abi = 1;
1632 rs6000_spe_abi = 0;
1633 }
76a773f3
AH		 1634 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1635 rs6000_altivec_abi = 0;
a3170dc6 1636 else if (! strcmp (rs6000_abi_string, "spe"))
01f4962d
NS		 1637 {
1638 rs6000_spe_abi = 1;
5cc73f91 1639 rs6000_altivec_abi = 0;
01f4962d
NS		 1640 if (!TARGET_SPE_ABI)
1641 error ("not configured for ABI: '%s'", rs6000_abi_string);
1642 }
f676971a 1643
594a51fe
SS		 1644 /* These are here for testing during development only, do not
1645 document in the manual please. */
1646 else if (! strcmp (rs6000_abi_string, "d64"))
1647 {
1648 rs6000_darwin64_abi = 1;
1649 warning ("Using darwin64 ABI");
1650 }
1651 else if (! strcmp (rs6000_abi_string, "d32"))
1652 {
1653 rs6000_darwin64_abi = 0;
1654 warning ("Using old darwin ABI");
1655 }
1656
a3170dc6
AH		 1657 else if (! strcmp (rs6000_abi_string, "no-spe"))
1658 rs6000_spe_abi = 0;
0ac081f6 1659 else
c725bd79 1660 error ("unknown ABI specified: '%s'", rs6000_abi_string);
0ac081f6
AH		 1661}
1662
4d4cbc0e
AH		 1663/* Handle -mfloat-gprs= options. */
1664static void
1665rs6000_parse_float_gprs_option (void)
1666{
1667 if (rs6000_float_gprs_string == 0)
1668 return;
1669 else if (! strcmp (rs6000_float_gprs_string, "yes")
1670 || ! strcmp (rs6000_float_gprs_string, "single"))
1671 rs6000_float_gprs = 1;
1672 else if (! strcmp (rs6000_float_gprs_string, "double"))
1673 rs6000_float_gprs = 2;
1674 else if (! strcmp (rs6000_float_gprs_string, "no"))
1675 rs6000_float_gprs = 0;
1676 else
1677 error ("invalid option for -mfloat-gprs");
1678}
1679
025d9908
KH		 1680/* Handle -malign-XXXXXX options. */
1681static void
863d938c 1682rs6000_parse_alignment_option (void)
025d9908 1683{
b20a9cca
AM		 1684 if (rs6000_alignment_string == 0)
1685 return;
1686 else if (! strcmp (rs6000_alignment_string, "power"))
d9168963
SS		 1687 {
1688 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1689 some C library functions, so warn about it. The flag may be
1690 useful for performance studies from time to time though, so
1691 don't disable it entirely. */
1692 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1693 warning ("-malign-power is not supported for 64-bit Darwin;"
1694 " it is incompatible with the installed C and C++ libraries");
1695 rs6000_alignment_flags = MASK_ALIGN_POWER;
1696 }
025d9908
KH		 1697 else if (! strcmp (rs6000_alignment_string, "natural"))
1698 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1699 else
1700 error ("unknown -malign-XXXXX option specified: '%s'",
1701 rs6000_alignment_string);
1702}
1703
c4501e62
JJ		 1704/* Validate and record the size specified with the -mtls-size option. */
1705
1706static void
863d938c 1707rs6000_parse_tls_size_option (void)
c4501e62
JJ		 1708{
1709 if (rs6000_tls_size_string == 0)
1710 return;
1711 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1712 rs6000_tls_size = 16;
1713 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1714 rs6000_tls_size = 32;
1715 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1716 rs6000_tls_size = 64;
1717 else
9e637a26 1718 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
c4501e62
JJ		 1719}
1720
5accd822 1721void
a2369ed3 1722optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
5accd822 1723{
5accd822 1724}
3cfa4909
MM		 1725\f
1726/* Do anything needed at the start of the asm file. */
1727
1bc7c5b6 1728static void
863d938c 1729rs6000_file_start (void)
3cfa4909 1730{
c4d38ccb 1731 size_t i;
3cfa4909 1732 char buffer[80];
d330fd93 1733 const char *start = buffer;
3cfa4909 1734 struct rs6000_cpu_select *ptr;
1bc7c5b6
ZW		 1735 const char *default_cpu = TARGET_CPU_DEFAULT;
1736 FILE *file = asm_out_file;
1737
1738 default_file_start ();
1739
1740#ifdef TARGET_BI_ARCH
1741 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1742 default_cpu = 0;
1743#endif
3cfa4909
MM		 1744
1745 if (flag_verbose_asm)
1746 {
1747 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1748 rs6000_select[0].string = default_cpu;
1749
b6a1cbae 1750 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
3cfa4909
MM		 1751 {
1752 ptr = &rs6000_select[i];
1753 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1754 {
1755 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1756 start = "";
1757 }
1758 }
1759
b91da81f 1760#ifdef USING_ELFOS_H
3cfa4909
MM		 1761 switch (rs6000_sdata)
1762 {
1763 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1764 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1765 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1766 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1767 }
1768
1769 if (rs6000_sdata && g_switch_value)
1770 {
307b599c
MK		 1771 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1772 g_switch_value);
3cfa4909
MM		 1773 start = "";
1774 }
1775#endif
1776
1777 if (*start == '\0')
949ea356 1778 putc ('\n', file);
3cfa4909 1779 }
b723e82f
JJ		 1780
1781 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1782 {
1783 toc_section ();
1784 text_section ();
1785 }
3cfa4909 1786}
c4e18b1c 1787
5248c961 1788\f
a0ab749a 1789/* Return nonzero if this function is known to have a null epilogue. */
9878760c
RK		 1790
1791int
863d938c 1792direct_return (void)
9878760c 1793{
4697a36c
MM		 1794 if (reload_completed)
1795 {
1796 rs6000_stack_t *info = rs6000_stack_info ();
1797
1798 if (info->first_gp_reg_save == 32
1799 && info->first_fp_reg_save == 64
00b960c7 1800 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
c81fc13e
DE		 1801 && ! info->lr_save_p
1802 && ! info->cr_save_p
00b960c7 1803 && info->vrsave_mask == 0
c81fc13e 1804 && ! info->push_p)
4697a36c
MM		 1805 return 1;
1806 }
1807
1808 return 0;
9878760c
RK		 1809}
1810
4e74d8ec
MM		 1811/* Return the number of instructions it takes to form a constant in an
1812 integer register. */
1813
48d72335 1814int
a2369ed3 1815num_insns_constant_wide (HOST_WIDE_INT value)
4e74d8ec
MM		 1816{
1817 /* signed constant loadable with {cal|addi} */
5f59ecb7 1818 if (CONST_OK_FOR_LETTER_P (value, 'I'))
0865c631
GK		 1819 return 1;
1820
4e74d8ec 1821 /* constant loadable with {cau|addis} */
5f59ecb7 1822 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
4e74d8ec
MM		 1823 return 1;
1824
5f59ecb7 1825#if HOST_BITS_PER_WIDE_INT == 64
c81fc13e 1826 else if (TARGET_POWERPC64)
4e74d8ec 1827 {
a65c591c
DE		 1828 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1829 HOST_WIDE_INT high = value >> 31;
4e74d8ec 1830
a65c591c 1831 if (high == 0 || high == -1)
4e74d8ec
MM		 1832 return 2;
1833
a65c591c 1834 high >>= 1;
4e74d8ec 1835
a65c591c 1836 if (low == 0)
4e74d8ec 1837 return num_insns_constant_wide (high) + 1;
4e74d8ec
MM		 1838 else
1839 return (num_insns_constant_wide (high)
e396202a 1840 + num_insns_constant_wide (low) + 1);
4e74d8ec
MM		 1841 }
1842#endif
1843
1844 else
1845 return 2;
1846}
1847
1848int
a2369ed3 1849num_insns_constant (rtx op, enum machine_mode mode)
4e74d8ec 1850{
4e74d8ec 1851 if (GET_CODE (op) == CONST_INT)
0d30d435
DE		 1852 {
1853#if HOST_BITS_PER_WIDE_INT == 64
4e2c1c44
DE		 1854 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1855 && mask64_operand (op, mode))
c4ad648e 1856 return 2;
0d30d435
DE		 1857 else
1858#endif
1859 return num_insns_constant_wide (INTVAL (op));
1860 }
4e74d8ec 1861
6fc48950
MM		 1862 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1863 {
1864 long l;
1865 REAL_VALUE_TYPE rv;
1866
1867 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1868 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
e72247f4 1869 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6fc48950
MM		 1870 }
1871
47ad8c61 1872 else if (GET_CODE (op) == CONST_DOUBLE)
4e74d8ec 1873 {
47ad8c61
MM		 1874 HOST_WIDE_INT low;
1875 HOST_WIDE_INT high;
1876 long l[2];
1877 REAL_VALUE_TYPE rv;
1878 int endian = (WORDS_BIG_ENDIAN == 0);
4e74d8ec 1879
47ad8c61
MM		 1880 if (mode == VOIDmode || mode == DImode)
1881 {
1882 high = CONST_DOUBLE_HIGH (op);
1883 low = CONST_DOUBLE_LOW (op);
1884 }
1885 else
1886 {
1887 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1888 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1889 high = l[endian];
1890 low = l[1 - endian];
1891 }
4e74d8ec 1892
47ad8c61
MM		 1893 if (TARGET_32BIT)
1894 return (num_insns_constant_wide (low)
1895 + num_insns_constant_wide (high));
4e74d8ec
MM		 1896
1897 else
47ad8c61 1898 {
e72247f4 1899 if (high == 0 && low >= 0)
47ad8c61
MM		 1900 return num_insns_constant_wide (low);
1901
e72247f4 1902 else if (high == -1 && low < 0)
47ad8c61
MM		 1903 return num_insns_constant_wide (low);
1904
a260abc9
DE		 1905 else if (mask64_operand (op, mode))
1906 return 2;
1907
47ad8c61
MM		 1908 else if (low == 0)
1909 return num_insns_constant_wide (high) + 1;
1910
1911 else
1912 return (num_insns_constant_wide (high)
1913 + num_insns_constant_wide (low) + 1);
1914 }
4e74d8ec
MM		 1915 }
1916
1917 else
1918 abort ();
1919}
1920
effa5d5d 1921/* Returns the constant for the splat instruction, if exists. */
452a7d36 1922
48d72335 1923int
452a7d36
HP		 1924easy_vector_splat_const (int cst, enum machine_mode mode)
1925{
f676971a 1926 switch (mode)
452a7d36
HP		 1927 {
1928 case V4SImode:
f676971a
EC		 1929 if (EASY_VECTOR_15 (cst)
1930 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 1931 return cst;
1932 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1933 break;
1934 cst = cst >> 16;
c4ad648e
AM		 1935 /* Fall thru */
1936
452a7d36 1937 case V8HImode:
f676971a
EC		 1938 if (EASY_VECTOR_15 (cst)
1939 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 1940 return cst;
1941 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1942 break;
1943 cst = cst >> 8;
c4ad648e
AM		 1944 /* Fall thru */
1945
452a7d36 1946 case V16QImode:
c4ad648e
AM		 1947 if (EASY_VECTOR_15 (cst)
1948 || EASY_VECTOR_15_ADD_SELF (cst))
1949 return cst;
f676971a 1950 default:
452a7d36
HP		 1951 break;
1952 }
1953 return 0;
1954}
1955
72ac76be 1956/* Return nonzero if all elements of a vector have the same value. */
69ef87e2 1957
48d72335 1958int
a2369ed3 1959easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d744e06e
AH		 1960{
1961 int units, i, cst;
1962
1963 units = CONST_VECTOR_NUNITS (op);
1964
1965 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1966 for (i = 1; i < units; ++i)
1967 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1968 break;
452a7d36 1969 if (i == units && easy_vector_splat_const (cst, mode))
d744e06e
AH		 1970 return 1;
1971 return 0;
1972}
1973
452a7d36 1974/* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
d744e06e 1975
f676971a 1976rtx
452a7d36
HP		 1977gen_easy_vector_constant_add_self (rtx op)
1978{
1979 int i, units;
1980 rtvec v;
1981 units = GET_MODE_NUNITS (GET_MODE (op));
1982 v = rtvec_alloc (units);
1983
1984 for (i = 0; i < units; i++)
f676971a 1985 RTVEC_ELT (v, i) =
452a7d36
HP		 1986 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1987 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
d744e06e
AH		 1988}
1989
1990const char *
a2369ed3 1991output_vec_const_move (rtx *operands)
d744e06e
AH		 1992{
1993 int cst, cst2;
1994 enum machine_mode mode;
1995 rtx dest, vec;
1996
1997 dest = operands[0];
1998 vec = operands[1];
69ef87e2 1999
d744e06e
AH		 2000 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2001 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2002 mode = GET_MODE (dest);
69ef87e2 2003
d744e06e
AH		 2004 if (TARGET_ALTIVEC)
2005 {
2006 if (zero_constant (vec, mode))
2007 return "vxor %0,%0,%0";
ce1f50b2 2008 else if (easy_vector_constant (vec, mode))
98ef3137 2009 {
d744e06e
AH		 2010 operands[1] = GEN_INT (cst);
2011 switch (mode)
2012 {
2013 case V4SImode:
452a7d36 2014 if (EASY_VECTOR_15 (cst))
ce1f50b2
HP		 2015 {
2016 operands[1] = GEN_INT (cst);
2017 return "vspltisw %0,%1";
2018 }
452a7d36
HP		 2019 else if (EASY_VECTOR_15_ADD_SELF (cst))
2020 return "#";
ce1f50b2 2021 cst = cst >> 16;
c4ad648e
AM		 2022 /* Fall thru */
2023
d744e06e 2024 case V8HImode:
452a7d36 2025 if (EASY_VECTOR_15 (cst))
ce1f50b2
HP		 2026 {
2027 operands[1] = GEN_INT (cst);
2028 return "vspltish %0,%1";
2029 }
452a7d36
HP		 2030 else if (EASY_VECTOR_15_ADD_SELF (cst))
2031 return "#";
ce1f50b2 2032 cst = cst >> 8;
c4ad648e
AM		 2033 /* Fall thru */
2034
d744e06e 2035 case V16QImode:
452a7d36 2036 if (EASY_VECTOR_15 (cst))
ce1f50b2
HP		 2037 {
2038 operands[1] = GEN_INT (cst);
2039 return "vspltisb %0,%1";
2040 }
452a7d36
HP		 2041 else if (EASY_VECTOR_15_ADD_SELF (cst))
2042 return "#";
c4ad648e 2043
d744e06e
AH		 2044 default:
2045 abort ();
2046 }
98ef3137 2047 }
d744e06e
AH		 2048 else
2049 abort ();
69ef87e2
AH		 2050 }
2051
d744e06e
AH		 2052 if (TARGET_SPE)
2053 {
2054 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2055 pattern of V1DI, V4HI, and V2SF.
2056
c1207243 2057 FIXME: We should probably return # and add post reload
c4ad648e 2058 splitters for these, but this way is so easy ;-). */
d744e06e
AH		 2059 operands[1] = GEN_INT (cst);
2060 operands[2] = GEN_INT (cst2);
2061 if (cst == cst2)
2062 return "li %0,%1\n\tevmergelo %0,%0,%0";
2063 else
2064 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2065 }
2066
2067 abort ();
69ef87e2
AH		 2068}
2069
914c2e77 2070int
e1e2e653
NS		 2071mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2072 bool allow_one)
0ba1b2ff
AM		 2073{
2074 if (GET_CODE (op) == CONST_INT)
a260abc9 2075 {
0ba1b2ff 2076 HOST_WIDE_INT c, lsb;
e1e2e653
NS		 2077 bool one_ok;
2078
0ba1b2ff 2079 c = INTVAL (op);
a260abc9 2080
0ba1b2ff
AM		 2081 /* Disallow all zeros. */
2082 if (c == 0)
2083 return 0;
a260abc9 2084
e1e2e653
NS		 2085 /* We can use a single rlwinm insn if no upper bits of C are set
2086 AND there are zero, one or two transitions in the _whole_ of
2087 C. */
2088 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2089
0ba1b2ff
AM		 2090 /* We don't change the number of transitions by inverting,
2091 so make sure we start with the LS bit zero. */
2092 if (c & 1)
2093 c = ~c;
a260abc9 2094
0ba1b2ff
AM		 2095 /* Find the first transition. */
2096 lsb = c & -c;
a260abc9 2097
0ba1b2ff
AM		 2098 /* Invert to look for a second transition. */
2099 c = ~c;
2100
2101 /* Erase first transition. */
2102 c &= -lsb;
2103
2104 /* Find the second transition. */
2105 lsb = c & -c;
2106
2107 /* Invert to look for a third transition. */
2108 c = ~c;
2109
2110 /* Erase second transition. */
2111 c &= -lsb;
2112
e1e2e653
NS		 2113 if (one_ok && !(allow_one || c))
2114 return 0;
2115
0ba1b2ff
AM		 2116 /* Find the third transition (if any). */
2117 lsb = c & -c;
2118
2119 /* Match if all the bits above are 1's (or c is zero). */
2120 return c == -lsb;
2121 }
2122 return 0;
2123}
2124
2125/* Generates shifts and masks for a pair of rldicl or rldicr insns to
2126 implement ANDing by the mask IN. */
2127void
a2369ed3 2128build_mask64_2_operands (rtx in, rtx *out)
0ba1b2ff
AM		 2129{
2130#if HOST_BITS_PER_WIDE_INT >= 64
2131 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2132 int shift;
2133
2134 if (GET_CODE (in) != CONST_INT)
2135 abort ();
2136
2137 c = INTVAL (in);
2138 if (c & 1)
2139 {
2140 /* Assume c initially something like 0x00fff000000fffff. The idea
2141 is to rotate the word so that the middle ^^^^^^ group of zeros
2142 is at the MS end and can be cleared with an rldicl mask. We then
2143 rotate back and clear off the MS ^^ group of zeros with a
2144 second rldicl. */
2145 c = ~c; /* c == 0xff000ffffff00000 */
2146 lsb = c & -c; /* lsb == 0x0000000000100000 */
2147 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2148 c = ~c; /* c == 0x00fff000000fffff */
2149 c &= -lsb; /* c == 0x00fff00000000000 */
2150 lsb = c & -c; /* lsb == 0x0000100000000000 */
2151 c = ~c; /* c == 0xff000fffffffffff */
2152 c &= -lsb; /* c == 0xff00000000000000 */
2153 shift = 0;
2154 while ((lsb >>= 1) != 0)
2155 shift++; /* shift == 44 on exit from loop */
2156 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2157 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2158 m2 = ~c; /* m2 == 0x00ffffffffffffff */
a260abc9
DE		 2159 }
2160 else
0ba1b2ff
AM		 2161 {
2162 /* Assume c initially something like 0xff000f0000000000. The idea
2163 is to rotate the word so that the ^^^ middle group of zeros
2164 is at the LS end and can be cleared with an rldicr mask. We then
2165 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2166 a second rldicr. */
2167 lsb = c & -c; /* lsb == 0x0000010000000000 */
2168 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2169 c = ~c; /* c == 0x00fff0ffffffffff */
2170 c &= -lsb; /* c == 0x00fff00000000000 */
2171 lsb = c & -c; /* lsb == 0x0000100000000000 */
2172 c = ~c; /* c == 0xff000fffffffffff */
2173 c &= -lsb; /* c == 0xff00000000000000 */
2174 shift = 0;
2175 while ((lsb >>= 1) != 0)
2176 shift++; /* shift == 44 on exit from loop */
2177 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2178 m1 >>= shift; /* m1 == 0x0000000000000fff */
2179 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2180 }
2181
2182 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2183 masks will be all 1's. We are guaranteed more than one transition. */
2184 out[0] = GEN_INT (64 - shift);
2185 out[1] = GEN_INT (m1);
2186 out[2] = GEN_INT (shift);
2187 out[3] = GEN_INT (m2);
2188#else
045572c7
GK		 2189 (void)in;
2190 (void)out;
0ba1b2ff
AM		 2191 abort ();
2192#endif
a260abc9
DE		 2193}
2194
54b695e7 2195/* Return TRUE if OP is an invalid SUBREG operation on the e500. */
48d72335
DE		 2196
2197bool
54b695e7
AH		 2198invalid_e500_subreg (rtx op, enum machine_mode mode)
2199{
2200 /* Reject (subreg:SI (reg:DF)). */
2201 if (GET_CODE (op) == SUBREG
2202 && mode == SImode
2203 && REG_P (SUBREG_REG (op))
2204 && GET_MODE (SUBREG_REG (op)) == DFmode)
2205 return true;
2206
2207 /* Reject (subreg:DF (reg:DI)). */
2208 if (GET_CODE (op) == SUBREG
2209 && mode == DFmode
2210 && REG_P (SUBREG_REG (op))
2211 && GET_MODE (SUBREG_REG (op)) == DImode)
2212 return true;
2213
2214 return false;
2215}
2216
95727fb8
AP		 2217/* Darwin, AIX increases natural record alignment to doubleword if the first
2218 field is an FP double while the FP fields remain word aligned. */
2219
19d66194 2220unsigned int
95727fb8
AP		 2221rs6000_special_round_type_align (tree type, int computed, int specified)
2222{
2223 tree field = TYPE_FIELDS (type);
95727fb8 2224
85962ac8
AP		 2225 /* Skip all non field decls */
2226 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
95727fb8
AP		 2227 field = TREE_CHAIN (field);
2228
3ce5437a 2229 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
95727fb8
AP		 2230 return MAX (computed, specified);
2231
2232 return MAX (MAX (computed, specified), 64);
2233}
2234
a4f6c312 2235/* Return 1 for an operand in small memory on V.4/eabi. */
7509c759
MM		 2236
2237int
f676971a 2238small_data_operand (rtx op ATTRIBUTE_UNUSED,
a2369ed3 2239 enum machine_mode mode ATTRIBUTE_UNUSED)
7509c759 2240{
38c1f2d7 2241#if TARGET_ELF
5f59ecb7 2242 rtx sym_ref;
7509c759 2243
d9407988 2244 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
a54d04b7 2245 return 0;
a54d04b7 2246
f607bc57 2247 if (DEFAULT_ABI != ABI_V4)
7509c759
MM		 2248 return 0;
2249
88228c4b
MM		 2250 if (GET_CODE (op) == SYMBOL_REF)
2251 sym_ref = op;
2252
2253 else if (GET_CODE (op) != CONST
2254 || GET_CODE (XEXP (op, 0)) != PLUS
2255 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2256 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7509c759
MM		 2257 return 0;
2258
88228c4b 2259 else
dbf55e53
MM		 2260 {
2261 rtx sum = XEXP (op, 0);
2262 HOST_WIDE_INT summand;
2263
2264 /* We have to be careful here, because it is the referenced address
c4ad648e 2265 that must be 32k from _SDA_BASE_, not just the symbol. */
dbf55e53 2266 summand = INTVAL (XEXP (sum, 1));
307b599c 2267 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
9390387d 2268 return 0;
dbf55e53
MM		 2269
2270 sym_ref = XEXP (sum, 0);
2271 }
88228c4b 2272
20bfcd69 2273 return SYMBOL_REF_SMALL_P (sym_ref);
d9407988
MM		 2274#else
2275 return 0;
2276#endif
7509c759 2277}
46c07df8 2278
d2288d5d
HP		 2279/* Return true, if operand is a memory operand and has a
2280 displacement divisible by 4. */
2281
2282int
2283word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2284{
2285 rtx addr;
2286 int off = 0;
2287
2288 if (!memory_operand (op, mode))
2289 return 0;
2290
2291 addr = XEXP (op, 0);
2292 if (GET_CODE (addr) == PLUS
2293 && GET_CODE (XEXP (addr, 0)) == REG
2294 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
2295 off = INTVAL (XEXP (addr, 1));
2296
2297 return (off % 4) == 0;
2298}
2299
da4c340c
GK		 2300/* Return true if the operand is an indirect or indexed memory operand. */
2301
2302int
2303indexed_or_indirect_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2304{
2305 rtx addr;
2306 if (!memory_operand (op, mode))
2307 return 0;
2308
2309 addr = XEXP (op, 0);
2310 if (GET_CODE (addr) == REG)
2311 return 1;
2312 if (GET_CODE (addr) == PLUS
2313 && GET_CODE (XEXP (addr, 0)) == REG
2314 && GET_CODE (XEXP (addr, 1)) == REG)
2315 return 1;
2316 return 0;
2317}
2318
3a1f863f 2319/* Return true if either operand is a general purpose register. */
46c07df8 2320
3a1f863f
DE		 2321bool
2322gpr_or_gpr_p (rtx op0, rtx op1)
46c07df8 2323{
3a1f863f
DE		 2324 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2325 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
46c07df8
HP		 2326}
2327
9ebbca7d 2328\f
4d588c14
RH		 2329/* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2330
f676971a
EC		 2331static int
2332constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
9ebbca7d 2333{
9390387d 2334 switch (GET_CODE (op))
9ebbca7d
GK		 2335 {
2336 case SYMBOL_REF:
c4501e62
JJ		 2337 if (RS6000_SYMBOL_REF_TLS_P (op))
2338 return 0;
2339 else if (CONSTANT_POOL_ADDRESS_P (op))
a4f6c312
SS		 2340 {
2341 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2342 {
2343 *have_sym = 1;
2344 return 1;
2345 }
2346 else
2347 return 0;
2348 }
2349 else if (! strcmp (XSTR (op, 0), toc_label_name))
2350 {
2351 *have_toc = 1;
2352 return 1;
2353 }
2354 else
2355 return 0;
9ebbca7d
GK		 2356 case PLUS:
2357 case MINUS:
c1f11548
DE		 2358 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2359 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
9ebbca7d 2360 case CONST:
a4f6c312 2361 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
9ebbca7d 2362 case CONST_INT:
a4f6c312 2363 return 1;
9ebbca7d 2364 default:
a4f6c312 2365 return 0;
9ebbca7d
GK		 2366 }
2367}
2368
4d588c14 2369static bool
a2369ed3 2370constant_pool_expr_p (rtx op)
9ebbca7d
GK		 2371{
2372 int have_sym = 0;
2373 int have_toc = 0;
2374 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2375}
2376
48d72335 2377bool
a2369ed3 2378toc_relative_expr_p (rtx op)
9ebbca7d 2379{
4d588c14
RH		 2380 int have_sym = 0;
2381 int have_toc = 0;
2382 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2383}
2384
4d588c14 2385bool
a2369ed3 2386legitimate_constant_pool_address_p (rtx x)
4d588c14
RH		 2387{
2388 return (TARGET_TOC
2389 && GET_CODE (x) == PLUS
2390 && GET_CODE (XEXP (x, 0)) == REG
2391 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2392 && constant_pool_expr_p (XEXP (x, 1)));
2393}
2394
2395static bool
a2369ed3 2396legitimate_small_data_p (enum machine_mode mode, rtx x)
4d588c14
RH		 2397{
2398 return (DEFAULT_ABI == ABI_V4
2399 && !flag_pic && !TARGET_TOC
2400 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2401 && small_data_operand (x, mode));
2402}
2403
60cdabab
DE		 2404/* SPE offset addressing is limited to 5-bits worth of double words. */
2405#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2406
76d2b81d
DJ		 2407bool
2408rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2409{
2410 unsigned HOST_WIDE_INT offset, extra;
2411
2412 if (GET_CODE (x) != PLUS)
2413 return false;
2414 if (GET_CODE (XEXP (x, 0)) != REG)
2415 return false;
2416 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2417 return false;
60cdabab
DE		 2418 if (legitimate_constant_pool_address_p (x))
2419 return true;
4d588c14
RH		 2420 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2421 return false;
2422
2423 offset = INTVAL (XEXP (x, 1));
2424 extra = 0;
2425 switch (mode)
2426 {
2427 case V16QImode:
2428 case V8HImode:
2429 case V4SFmode:
2430 case V4SImode:
2431 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2432 which leaves the only valid constant offset of zero, which by
2433 canonicalization rules is also invalid. */
2434 return false;
2435
2436 case V4HImode:
2437 case V2SImode:
2438 case V1DImode:
2439 case V2SFmode:
2440 /* SPE vector modes. */
2441 return SPE_CONST_OFFSET_OK (offset);
2442
2443 case DFmode:
4d4cbc0e
AH		 2444 if (TARGET_E500_DOUBLE)
2445 return SPE_CONST_OFFSET_OK (offset);
2446
4d588c14 2447 case DImode:
54b695e7
AH		 2448 /* On e500v2, we may have:
2449
2450 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2451
2452 Which gets addressed with evldd instructions. */
2453 if (TARGET_E500_DOUBLE)
2454 return SPE_CONST_OFFSET_OK (offset);
2455
3364872d 2456 if (mode == DFmode || !TARGET_POWERPC64)
4d588c14
RH		 2457 extra = 4;
2458 else if (offset & 3)
2459 return false;
2460 break;
2461
2462 case TFmode:
2463 case TImode:
3364872d 2464 if (mode == TFmode || !TARGET_POWERPC64)
4d588c14
RH		 2465 extra = 12;
2466 else if (offset & 3)
2467 return false;
2468 else
2469 extra = 8;
2470 break;
2471
2472 default:
2473 break;
2474 }
2475
b1917422
AM		 2476 offset += 0x8000;
2477 return (offset < 0x10000) && (offset + extra < 0x10000);
4d588c14
RH		 2478}
2479
2480static bool
a2369ed3 2481legitimate_indexed_address_p (rtx x, int strict)
4d588c14
RH		 2482{
2483 rtx op0, op1;
2484
2485 if (GET_CODE (x) != PLUS)
2486 return false;
850e8d3d 2487
4d588c14
RH		 2488 op0 = XEXP (x, 0);
2489 op1 = XEXP (x, 1);
2490
2491 if (!REG_P (op0) || !REG_P (op1))
2492 return false;
2493
2494 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2495 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2496 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2497 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
9ebbca7d
GK		 2498}
2499
48d72335 2500inline bool
a2369ed3 2501legitimate_indirect_address_p (rtx x, int strict)
4d588c14
RH		 2502{
2503 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2504}
2505
48d72335 2506bool
4c81e946
FJ		 2507macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2508{
c4ad648e 2509 if (!TARGET_MACHO || !flag_pic
9390387d 2510 || mode != SImode || GET_CODE (x) != MEM)
c4ad648e
AM		 2511 return false;
2512 x = XEXP (x, 0);
4c81e946
FJ		 2513
2514 if (GET_CODE (x) != LO_SUM)
2515 return false;
2516 if (GET_CODE (XEXP (x, 0)) != REG)
2517 return false;
2518 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2519 return false;
2520 x = XEXP (x, 1);
2521
2522 return CONSTANT_P (x);
2523}
2524
4d588c14 2525static bool
a2369ed3 2526legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2527{
2528 if (GET_CODE (x) != LO_SUM)
2529 return false;
2530 if (GET_CODE (XEXP (x, 0)) != REG)
2531 return false;
2532 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2533 return false;
54b695e7
AH		 2534 /* Restrict addressing for DI because of our SUBREG hackery. */
2535 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
f82f556d 2536 return false;
4d588c14
RH		 2537 x = XEXP (x, 1);
2538
8622e235 2539 if (TARGET_ELF || TARGET_MACHO)
4d588c14 2540 {
a29077da 2541 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
4d588c14
RH		 2542 return false;
2543 if (TARGET_TOC)
2544 return false;
2545 if (GET_MODE_NUNITS (mode) != 1)
2546 return false;
5e5f01b9 2547 if (GET_MODE_BITSIZE (mode) > 64
3c028f65
AM		 2548 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2549 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
4d588c14
RH		 2550 return false;
2551
2552 return CONSTANT_P (x);
2553 }
2554
2555 return false;
2556}
2557
2558
9ebbca7d
GK		 2559/* Try machine-dependent ways of modifying an illegitimate address
2560 to be legitimate. If we find one, return the new, valid address.
2561 This is used from only one place: `memory_address' in explow.c.
2562
a4f6c312
SS		 2563 OLDX is the address as it was before break_out_memory_refs was
2564 called. In some cases it is useful to look at this to decide what
2565 needs to be done.
9ebbca7d 2566
a4f6c312 2567 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
9ebbca7d 2568
a4f6c312
SS		 2569 It is always safe for this function to do nothing. It exists to
2570 recognize opportunities to optimize the output.
9ebbca7d
GK		 2571
2572 On RS/6000, first check for the sum of a register with a constant
2573 integer that is out of range. If so, generate code to add the
2574 constant with the low-order 16 bits masked to the register and force
2575 this result into another register (this can be done with `cau').
2576 Then generate an address of REG+(CONST&0xffff), allowing for the
2577 possibility of bit 16 being a one.
2578
2579 Then check for the sum of a register and something not constant, try to
2580 load the other things into a register and return the sum. */
4d588c14 2581
9ebbca7d 2582rtx
a2369ed3
DJ		 2583rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2584 enum machine_mode mode)
0ac081f6 2585{
c4501e62
JJ		 2586 if (GET_CODE (x) == SYMBOL_REF)
2587 {
2588 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2589 if (model != 0)
2590 return rs6000_legitimize_tls_address (x, model);
2591 }
2592
f676971a 2593 if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2594 && GET_CODE (XEXP (x, 0)) == REG
2595 && GET_CODE (XEXP (x, 1)) == CONST_INT
2596 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
f676971a 2597 {
9ebbca7d
GK		 2598 HOST_WIDE_INT high_int, low_int;
2599 rtx sum;
a65c591c
DE		 2600 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2601 high_int = INTVAL (XEXP (x, 1)) - low_int;
9ebbca7d
GK		 2602 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2603 GEN_INT (high_int)), 0);
2604 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2605 }
f676971a 2606 else if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2607 && GET_CODE (XEXP (x, 0)) == REG
2608 && GET_CODE (XEXP (x, 1)) != CONST_INT
6ac7bf2c 2609 && GET_MODE_NUNITS (mode) == 1
a3170dc6
AH		 2610 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2611 || TARGET_POWERPC64
54b695e7
AH		 2612 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2613 && mode != TFmode))
9ebbca7d
GK		 2614 && (TARGET_POWERPC64 || mode != DImode)
2615 && mode != TImode)
2616 {
2617 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2618 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2619 }
0ac081f6
AH		 2620 else if (ALTIVEC_VECTOR_MODE (mode))
2621 {
2622 rtx reg;
2623
2624 /* Make sure both operands are registers. */
2625 if (GET_CODE (x) == PLUS)
9f85ed45 2626 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
0ac081f6
AH		 2627 force_reg (Pmode, XEXP (x, 1)));
2628
2629 reg = force_reg (Pmode, x);
2630 return reg;
2631 }
4d4cbc0e 2632 else if (SPE_VECTOR_MODE (mode)
54b695e7
AH		 2633 || (TARGET_E500_DOUBLE && (mode == DFmode
2634 || mode == DImode)))
a3170dc6 2635 {
54b695e7
AH		 2636 if (mode == DImode)
2637 return NULL_RTX;
a3170dc6
AH		 2638 /* We accept [reg + reg] and [reg + OFFSET]. */
2639
2640 if (GET_CODE (x) == PLUS)
c4ad648e
AM		 2641 {
2642 rtx op1 = XEXP (x, 0);
2643 rtx op2 = XEXP (x, 1);
a3170dc6 2644
c4ad648e 2645 op1 = force_reg (Pmode, op1);
a3170dc6 2646
c4ad648e
AM		 2647 if (GET_CODE (op2) != REG
2648 && (GET_CODE (op2) != CONST_INT
2649 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2650 op2 = force_reg (Pmode, op2);
a3170dc6 2651
c4ad648e
AM		 2652 return gen_rtx_PLUS (Pmode, op1, op2);
2653 }
a3170dc6
AH		 2654
2655 return force_reg (Pmode, x);
2656 }
f1384257
AM		 2657 else if (TARGET_ELF
2658 && TARGET_32BIT
2659 && TARGET_NO_TOC
2660 && ! flag_pic
9ebbca7d 2661 && GET_CODE (x) != CONST_INT
f676971a 2662 && GET_CODE (x) != CONST_DOUBLE
9ebbca7d 2663 && CONSTANT_P (x)
6ac7bf2c
GK		 2664 && GET_MODE_NUNITS (mode) == 1
2665 && (GET_MODE_BITSIZE (mode) <= 32
a3170dc6 2666 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
9ebbca7d
GK		 2667 {
2668 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2669 emit_insn (gen_elf_high (reg, x));
2670 return gen_rtx_LO_SUM (Pmode, reg, x);
9ebbca7d 2671 }
ee890fe2
SS		 2672 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2673 && ! flag_pic
ab82a49f
AP		 2674#if TARGET_MACHO
2675 && ! MACHO_DYNAMIC_NO_PIC_P
2676#endif
ee890fe2 2677 && GET_CODE (x) != CONST_INT
f676971a 2678 && GET_CODE (x) != CONST_DOUBLE
ee890fe2 2679 && CONSTANT_P (x)
f82f556d 2680 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
f676971a 2681 && mode != DImode
ee890fe2
SS		 2682 && mode != TImode)
2683 {
2684 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2685 emit_insn (gen_macho_high (reg, x));
2686 return gen_rtx_LO_SUM (Pmode, reg, x);
ee890fe2 2687 }
f676971a 2688 else if (TARGET_TOC
4d588c14 2689 && constant_pool_expr_p (x)
a9098fd0 2690 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
9ebbca7d
GK		 2691 {
2692 return create_TOC_reference (x);
2693 }
2694 else
2695 return NULL_RTX;
2696}
258bfae2 2697
c973d557
JJ		 2698/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2699 We need to emit DTP-relative relocations. */
2700
2701void
2702rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2703{
2704 switch (size)
2705 {
2706 case 4:
2707 fputs ("\t.long\t", file);
2708 break;
2709 case 8:
2710 fputs (DOUBLE_INT_ASM_OP, file);
2711 break;
2712 default:
2713 abort ();
2714 }
2715 output_addr_const (file, x);
2716 fputs ("@dtprel+0x8000", file);
2717}
2718
c4501e62
JJ		 2719/* Construct the SYMBOL_REF for the tls_get_addr function. */
2720
2721static GTY(()) rtx rs6000_tls_symbol;
2722static rtx
863d938c 2723rs6000_tls_get_addr (void)
c4501e62
JJ		 2724{
2725 if (!rs6000_tls_symbol)
2726 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2727
2728 return rs6000_tls_symbol;
2729}
2730
2731/* Construct the SYMBOL_REF for TLS GOT references. */
2732
2733static GTY(()) rtx rs6000_got_symbol;
2734static rtx
863d938c 2735rs6000_got_sym (void)
c4501e62
JJ		 2736{
2737 if (!rs6000_got_symbol)
2738 {
2739 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2740 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2741 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
f676971a 2742 }
c4501e62
JJ		 2743
2744 return rs6000_got_symbol;
2745}
2746
2747/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2748 this (thread-local) address. */
2749
2750static rtx
a2369ed3 2751rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
c4501e62
JJ		 2752{
2753 rtx dest, insn;
2754
2755 dest = gen_reg_rtx (Pmode);
2756 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2757 {
2758 rtx tlsreg;
2759
2760 if (TARGET_64BIT)
2761 {
2762 tlsreg = gen_rtx_REG (Pmode, 13);
2763 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2764 }
2765 else
2766 {
2767 tlsreg = gen_rtx_REG (Pmode, 2);
2768 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2769 }
2770 emit_insn (insn);
2771 }
2772 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2773 {
2774 rtx tlsreg, tmp;
2775
2776 tmp = gen_reg_rtx (Pmode);
2777 if (TARGET_64BIT)
2778 {
2779 tlsreg = gen_rtx_REG (Pmode, 13);
2780 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2781 }
2782 else
2783 {
2784 tlsreg = gen_rtx_REG (Pmode, 2);
2785 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2786 }
2787 emit_insn (insn);
2788 if (TARGET_64BIT)
2789 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2790 else
2791 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2792 emit_insn (insn);
2793 }
2794 else
2795 {
2796 rtx r3, got, tga, tmp1, tmp2, eqv;
2797
2798 if (TARGET_64BIT)
2799 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2800 else
2801 {
2802 if (flag_pic == 1)
2803 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2804 else
2805 {
2806 rtx gsym = rs6000_got_sym ();
2807 got = gen_reg_rtx (Pmode);
2808 if (flag_pic == 0)
2809 rs6000_emit_move (got, gsym, Pmode);
2810 else
2811 {
2812 char buf[30];
2813 static int tls_got_labelno = 0;
2814 rtx tempLR, lab, tmp3, mem;
2815 rtx first, last;
2816
2817 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2818 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2819 tempLR = gen_reg_rtx (Pmode);
2820 tmp1 = gen_reg_rtx (Pmode);
2821 tmp2 = gen_reg_rtx (Pmode);
2822 tmp3 = gen_reg_rtx (Pmode);
542a8afa 2823 mem = gen_const_mem (Pmode, tmp1);
c4501e62
JJ		 2824
2825 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2826 gsym));
2827 emit_move_insn (tmp1, tempLR);
2828 emit_move_insn (tmp2, mem);
2829 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2830 last = emit_move_insn (got, tmp3);
2831 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2832 REG_NOTES (last));
2833 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2834 REG_NOTES (first));
2835 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2836 REG_NOTES (last));
2837 }
2838 }
2839 }
2840
2841 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2842 {
2843 r3 = gen_rtx_REG (Pmode, 3);
2844 if (TARGET_64BIT)
2845 insn = gen_tls_gd_64 (r3, got, addr);
2846 else
2847 insn = gen_tls_gd_32 (r3, got, addr);
2848 start_sequence ();
2849 emit_insn (insn);
2850 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2851 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2852 insn = emit_call_insn (insn);
2853 CONST_OR_PURE_CALL_P (insn) = 1;
2854 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2855 insn = get_insns ();
2856 end_sequence ();
2857 emit_libcall_block (insn, dest, r3, addr);
2858 }
2859 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2860 {
2861 r3 = gen_rtx_REG (Pmode, 3);
2862 if (TARGET_64BIT)
2863 insn = gen_tls_ld_64 (r3, got);
2864 else
2865 insn = gen_tls_ld_32 (r3, got);
2866 start_sequence ();
2867 emit_insn (insn);
2868 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2869 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2870 insn = emit_call_insn (insn);
2871 CONST_OR_PURE_CALL_P (insn) = 1;
2872 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2873 insn = get_insns ();
2874 end_sequence ();
2875 tmp1 = gen_reg_rtx (Pmode);
2876 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2877 UNSPEC_TLSLD);
2878 emit_libcall_block (insn, tmp1, r3, eqv);
2879 if (rs6000_tls_size == 16)
2880 {
2881 if (TARGET_64BIT)
2882 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2883 else
2884 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2885 }
2886 else if (rs6000_tls_size == 32)
2887 {
2888 tmp2 = gen_reg_rtx (Pmode);
2889 if (TARGET_64BIT)
2890 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2891 else
2892 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2893 emit_insn (insn);
2894 if (TARGET_64BIT)
2895 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2896 else
2897 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2898 }
2899 else
2900 {
2901 tmp2 = gen_reg_rtx (Pmode);
2902 if (TARGET_64BIT)
2903 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2904 else
2905 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2906 emit_insn (insn);
2907 insn = gen_rtx_SET (Pmode, dest,
2908 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2909 }
2910 emit_insn (insn);
2911 }
2912 else
2913 {
2914 /* IE, or 64 bit offset LE. */
2915 tmp2 = gen_reg_rtx (Pmode);
2916 if (TARGET_64BIT)
2917 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2918 else
2919 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2920 emit_insn (insn);
2921 if (TARGET_64BIT)
2922 insn = gen_tls_tls_64 (dest, tmp2, addr);
2923 else
2924 insn = gen_tls_tls_32 (dest, tmp2, addr);
2925 emit_insn (insn);
2926 }
2927 }
2928
2929 return dest;
2930}
2931
c4501e62
JJ		 2932/* Return 1 if X contains a thread-local symbol. */
2933
2934bool
a2369ed3 2935rs6000_tls_referenced_p (rtx x)
c4501e62 2936{
cd413cab
AP		 2937 if (! TARGET_HAVE_TLS)
2938 return false;
2939
c4501e62
JJ		 2940 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2941}
2942
2943/* Return 1 if *X is a thread-local symbol. This is the same as
2944 rs6000_tls_symbol_ref except for the type of the unused argument. */
2945
9390387d 2946static int
a2369ed3 2947rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 2948{
2949 return RS6000_SYMBOL_REF_TLS_P (*x);
2950}
2951
24ea750e
DJ		 2952/* The convention appears to be to define this wherever it is used.
2953 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2954 is now used here. */
2955#ifndef REG_MODE_OK_FOR_BASE_P
2956#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2957#endif
2958
2959/* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2960 replace the input X, or the original X if no replacement is called for.
2961 The output parameter *WIN is 1 if the calling macro should goto WIN,
2962 0 if it should not.
2963
2964 For RS/6000, we wish to handle large displacements off a base
2965 register by splitting the addend across an addiu/addis and the mem insn.
2966 This cuts number of extra insns needed from 3 to 1.
2967
2968 On Darwin, we use this to generate code for floating point constants.
2969 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2970 The Darwin code is inside #if TARGET_MACHO because only then is
2971 machopic_function_base_name() defined. */
2972rtx
f676971a 2973rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
c4ad648e
AM		 2974 int opnum, int type,
2975 int ind_levels ATTRIBUTE_UNUSED, int *win)
24ea750e 2976{
f676971a 2977 /* We must recognize output that we have already generated ourselves. */
24ea750e
DJ		 2978 if (GET_CODE (x) == PLUS
2979 && GET_CODE (XEXP (x, 0)) == PLUS
2980 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2981 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2982 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2983 {
2984 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 2985 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2986 opnum, (enum reload_type)type);
24ea750e
DJ		 2987 *win = 1;
2988 return x;
2989 }
3deb2758 2990
24ea750e
DJ		 2991#if TARGET_MACHO
2992 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2993 && GET_CODE (x) == LO_SUM
2994 && GET_CODE (XEXP (x, 0)) == PLUS
2995 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2996 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2997 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2998 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2999 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3000 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3001 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3002 {
3003 /* Result of previous invocation of this function on Darwin
6f317ef3 3004 floating point constant. */
24ea750e 3005 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 3006 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3007 opnum, (enum reload_type)type);
24ea750e
DJ		 3008 *win = 1;
3009 return x;
3010 }
3011#endif
4937d02d
DE		 3012
3013 /* Force ld/std non-word aligned offset into base register by wrapping
3014 in offset 0. */
3015 if (GET_CODE (x) == PLUS
3016 && GET_CODE (XEXP (x, 0)) == REG
3017 && REGNO (XEXP (x, 0)) < 32
3018 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3019 && GET_CODE (XEXP (x, 1)) == CONST_INT
3020 && (INTVAL (XEXP (x, 1)) & 3) != 0
78796ad5 3021 && !ALTIVEC_VECTOR_MODE (mode)
4937d02d
DE		 3022 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3023 && TARGET_POWERPC64)
3024 {
3025 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3026 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3027 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3028 opnum, (enum reload_type) type);
3029 *win = 1;
3030 return x;
3031 }
3032
24ea750e
DJ		 3033 if (GET_CODE (x) == PLUS
3034 && GET_CODE (XEXP (x, 0)) == REG
3035 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3036 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
78c875e8 3037 && GET_CODE (XEXP (x, 1)) == CONST_INT
93638d7a 3038 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 3039 && !(TARGET_E500_DOUBLE && (mode == DFmode
3040 || mode == DImode))
78c875e8 3041 && !ALTIVEC_VECTOR_MODE (mode))
24ea750e
DJ		 3042 {
3043 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3044 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3045 HOST_WIDE_INT high
c4ad648e 3046 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
24ea750e
DJ		 3047
3048 /* Check for 32-bit overflow. */
3049 if (high + low != val)
c4ad648e 3050 {
24ea750e
DJ		 3051 *win = 0;
3052 return x;
3053 }
3054
3055 /* Reload the high part into a base reg; leave the low part
c4ad648e 3056 in the mem directly. */
24ea750e
DJ		 3057
3058 x = gen_rtx_PLUS (GET_MODE (x),
c4ad648e
AM		 3059 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3060 GEN_INT (high)),
3061 GEN_INT (low));
24ea750e
DJ		 3062
3063 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 3064 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3065 opnum, (enum reload_type)type);
24ea750e
DJ		 3066 *win = 1;
3067 return x;
3068 }
4937d02d 3069
24ea750e
DJ		 3070#if TARGET_MACHO
3071 if (GET_CODE (x) == SYMBOL_REF
3072 && DEFAULT_ABI == ABI_DARWIN
69ef87e2 3073 && !ALTIVEC_VECTOR_MODE (mode)
a29077da 3074 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
0d8c1c97
AM		 3075 /* Don't do this for TFmode, since the result isn't offsettable.
3076 The same goes for DImode without 64-bit gprs. */
3077 && mode != TFmode
3078 && (mode != DImode || TARGET_POWERPC64))
24ea750e 3079 {
a29077da
GK		 3080 if (flag_pic)
3081 {
3082 rtx offset = gen_rtx_CONST (Pmode,
3083 gen_rtx_MINUS (Pmode, x,
11abc112 3084 machopic_function_base_sym ()));
a29077da
GK		 3085 x = gen_rtx_LO_SUM (GET_MODE (x),
3086 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3087 gen_rtx_HIGH (Pmode, offset)), offset);
3088 }
3089 else
3090 x = gen_rtx_LO_SUM (GET_MODE (x),
c4ad648e 3091 gen_rtx_HIGH (Pmode, x), x);
a29077da 3092
24ea750e 3093 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
a29077da
GK		 3094 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3095 opnum, (enum reload_type)type);
24ea750e
DJ		 3096 *win = 1;
3097 return x;
3098 }
3099#endif
4937d02d 3100
24ea750e 3101 if (TARGET_TOC
4d588c14 3102 && constant_pool_expr_p (x)
c1f11548 3103 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
24ea750e
DJ		 3104 {
3105 (x) = create_TOC_reference (x);
3106 *win = 1;
3107 return x;
3108 }
3109 *win = 0;
3110 return x;
f676971a 3111}
24ea750e 3112
258bfae2
FS		 3113/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3114 that is a valid memory address for an instruction.
3115 The MODE argument is the machine mode for the MEM expression
3116 that wants to use this address.
3117
3118 On the RS/6000, there are four valid address: a SYMBOL_REF that
3119 refers to a constant pool entry of an address (or the sum of it
3120 plus a constant), a short (16-bit signed) constant plus a register,
3121 the sum of two registers, or a register indirect, possibly with an
5bdc5878 3122 auto-increment. For DFmode and DImode with a constant plus register,
258bfae2
FS		 3123 we must ensure that both words are addressable or PowerPC64 with offset
3124 word aligned.
3125
3126 For modes spanning multiple registers (DFmode in 32-bit GPRs,
76d2b81d 3127 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
258bfae2
FS		 3128 adjacent memory cells are accessed by adding word-sized offsets
3129 during assembly output. */
3130int
a2369ed3 3131rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
258bfae2 3132{
850e8d3d
DN		 3133 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3134 if (TARGET_ALTIVEC
3135 && ALTIVEC_VECTOR_MODE (mode)
3136 && GET_CODE (x) == AND
3137 && GET_CODE (XEXP (x, 1)) == CONST_INT
3138 && INTVAL (XEXP (x, 1)) == -16)
3139 x = XEXP (x, 0);
3140
c4501e62
JJ		 3141 if (RS6000_SYMBOL_REF_TLS_P (x))
3142 return 0;
4d588c14 3143 if (legitimate_indirect_address_p (x, reg_ok_strict))
258bfae2
FS		 3144 return 1;
3145 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
0d6d6892 3146 && !ALTIVEC_VECTOR_MODE (mode)
a3170dc6 3147 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 3148 /* Restrict addressing for DI because of our SUBREG hackery. */
3149 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
258bfae2 3150 && TARGET_UPDATE
4d588c14 3151 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
258bfae2 3152 return 1;
4d588c14 3153 if (legitimate_small_data_p (mode, x))
258bfae2 3154 return 1;
4d588c14 3155 if (legitimate_constant_pool_address_p (x))
258bfae2
FS		 3156 return 1;
3157 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3158 if (! reg_ok_strict
3159 && GET_CODE (x) == PLUS
3160 && GET_CODE (XEXP (x, 0)) == REG
708d2456 3161 && (XEXP (x, 0) == virtual_stack_vars_rtx
c4ad648e 3162 || XEXP (x, 0) == arg_pointer_rtx)
258bfae2
FS		 3163 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3164 return 1;
76d2b81d 3165 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3166 return 1;
3167 if (mode != TImode
76d2b81d 3168 && mode != TFmode
a3170dc6
AH		 3169 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3170 || TARGET_POWERPC64
4d4cbc0e 3171 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
258bfae2 3172 && (TARGET_POWERPC64 || mode != DImode)
4d588c14 3173 && legitimate_indexed_address_p (x, reg_ok_strict))
258bfae2 3174 return 1;
4d588c14 3175 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3176 return 1;
3177 return 0;
3178}
4d588c14
RH		 3179
3180/* Go to LABEL if ADDR (a legitimate address expression)
3181 has an effect that depends on the machine mode it is used for.
3182
3183 On the RS/6000 this is true of all integral offsets (since AltiVec
3184 modes don't allow them) or is a pre-increment or decrement.
3185
3186 ??? Except that due to conceptual problems in offsettable_address_p
3187 we can't really report the problems of integral offsets. So leave
f676971a 3188 this assuming that the adjustable offset must be valid for the
4d588c14
RH		 3189 sub-words of a TFmode operand, which is what we had before. */
3190
3191bool
a2369ed3 3192rs6000_mode_dependent_address (rtx addr)
4d588c14
RH		 3193{
3194 switch (GET_CODE (addr))
3195 {
3196 case PLUS:
3197 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3198 {
3199 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3200 return val + 12 + 0x8000 >= 0x10000;
3201 }
3202 break;
3203
3204 case LO_SUM:
3205 return true;
3206
3207 case PRE_INC:
3208 case PRE_DEC:
3209 return TARGET_UPDATE;
3210
3211 default:
3212 break;
3213 }
3214
3215 return false;
3216}
d8ecbcdb
AH		 3217
3218/* Return number of consecutive hard regs needed starting at reg REGNO
3219 to hold something of mode MODE.
3220 This is ordinarily the length in words of a value of mode MODE
3221 but can be less for certain modes in special long registers.
3222
3223 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3224 scalar instructions. The upper 32 bits are only available to the
3225 SIMD instructions.
3226
3227 POWER and PowerPC GPRs hold 32 bits worth;
3228 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3229
3230int
3231rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3232{
3233 if (FP_REGNO_P (regno))
3234 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3235
4d4cbc0e
AH		 3236 if (TARGET_E500_DOUBLE && mode == DFmode)
3237 return 1;
3238
d8ecbcdb
AH		 3239 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3240 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3241
3242 if (ALTIVEC_REGNO_P (regno))
3243 return
3244 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3245
3246 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3247}
2aa4498c
AH		 3248
3249/* Change register usage conditional on target flags. */
3250void
3251rs6000_conditional_register_usage (void)
3252{
3253 int i;
3254
3255 /* Set MQ register fixed (already call_used) if not POWER
3256 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3257 be allocated. */
3258 if (! TARGET_POWER)
3259 fixed_regs[64] = 1;
3260
3261 /* 64-bit AIX reserves GPR13 for thread-private data. */
3262 if (TARGET_64BIT)
3263 fixed_regs[13] = call_used_regs[13]
3264 = call_really_used_regs[13] = 1;
3265
3266 /* Conditionally disable FPRs. */
3267 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3268 for (i = 32; i < 64; i++)
3269 fixed_regs[i] = call_used_regs[i]
c4ad648e 3270 = call_really_used_regs[i] = 1;
2aa4498c
AH		 3271
3272 if (DEFAULT_ABI == ABI_V4
3273 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3274 && flag_pic == 2)
3275 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3276
3277 if (DEFAULT_ABI == ABI_V4
3278 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3279 && flag_pic == 1)
3280 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3281 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3282 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3283
3284 if (DEFAULT_ABI == ABI_DARWIN
3285 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3286 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3287 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3288 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3289 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3290
b4db40bf
JJ		 3291 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3292 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3293 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3294
2aa4498c
AH		 3295 if (TARGET_ALTIVEC)
3296 global_regs[VSCR_REGNO] = 1;
3297
3298 if (TARGET_SPE)
3299 {
3300 global_regs[SPEFSCR_REGNO] = 1;
3301 fixed_regs[FIXED_SCRATCH]
c4ad648e 3302 = call_used_regs[FIXED_SCRATCH]
2aa4498c
AH		 3303 = call_really_used_regs[FIXED_SCRATCH] = 1;
3304 }
3305
3306 if (! TARGET_ALTIVEC)
3307 {
3308 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3309 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3310 call_really_used_regs[VRSAVE_REGNO] = 1;
3311 }
3312
3313 if (TARGET_ALTIVEC_ABI)
3314 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3315 call_used_regs[i] = call_really_used_regs[i] = 1;
3316}
fb4d4348 3317\f
a4f6c312
SS		 3318/* Try to output insns to set TARGET equal to the constant C if it can
3319 be done in less than N insns. Do all computations in MODE.
3320 Returns the place where the output has been placed if it can be
3321 done and the insns have been emitted. If it would take more than N
3322 insns, zero is returned and no insns and emitted. */
2bfcf297
DB		 3323
3324rtx
f676971a 3325rs6000_emit_set_const (rtx dest, enum machine_mode mode,
a2369ed3 3326 rtx source, int n ATTRIBUTE_UNUSED)
2bfcf297 3327{
af8cb5c5 3328 rtx result, insn, set;
2bfcf297
DB		 3329 HOST_WIDE_INT c0, c1;
3330
af8cb5c5 3331 if (mode == QImode || mode == HImode)
2bfcf297
DB		 3332 {
3333 if (dest == NULL)
c4ad648e 3334 dest = gen_reg_rtx (mode);
2bfcf297
DB		 3335 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3336 return dest;
3337 }
af8cb5c5 3338 else if (mode == SImode)
2bfcf297 3339 {
af8cb5c5
DE		 3340 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3341
3342 emit_insn (gen_rtx_SET (VOIDmode, result,
3343 GEN_INT (INTVAL (source)
3344 & (~ (HOST_WIDE_INT) 0xffff))));
3345 emit_insn (gen_rtx_SET (VOIDmode, dest,
3346 gen_rtx_IOR (SImode, result,
3347 GEN_INT (INTVAL (source) & 0xffff))));
3348 result = dest;
2bfcf297 3349 }
af8cb5c5 3350 else if (mode == DImode)
2bfcf297 3351 {
af8cb5c5
DE		 3352 if (GET_CODE (source) == CONST_INT)
3353 {
3354 c0 = INTVAL (source);
3355 c1 = -(c0 < 0);
3356 }
3357 else if (GET_CODE (source) == CONST_DOUBLE)
3358 {
2bfcf297 3359#if HOST_BITS_PER_WIDE_INT >= 64
af8cb5c5
DE		 3360 c0 = CONST_DOUBLE_LOW (source);
3361 c1 = -(c0 < 0);
2bfcf297 3362#else
af8cb5c5
DE		 3363 c0 = CONST_DOUBLE_LOW (source);
3364 c1 = CONST_DOUBLE_HIGH (source);
2bfcf297 3365#endif
af8cb5c5
DE		 3366 }
3367 else
3368 abort ();
3369
3370 result = rs6000_emit_set_long_const (dest, c0, c1);
2bfcf297
DB		 3371 }
3372 else
a4f6c312 3373 abort ();
2bfcf297 3374
af8cb5c5
DE		 3375 insn = get_last_insn ();
3376 set = single_set (insn);
3377 if (! CONSTANT_P (SET_SRC (set)))
3378 set_unique_reg_note (insn, REG_EQUAL, source);
3379
3380 return result;
2bfcf297
DB		 3381}
3382
3383/* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3384 fall back to a straight forward decomposition. We do this to avoid
3385 exponential run times encountered when looking for longer sequences
3386 with rs6000_emit_set_const. */
3387static rtx
a2369ed3 3388rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
2bfcf297
DB		 3389{
3390 if (!TARGET_POWERPC64)
3391 {
3392 rtx operand1, operand2;
3393
3394 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3395 DImode);
3396 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3397 DImode);
3398 emit_move_insn (operand1, GEN_INT (c1));
3399 emit_move_insn (operand2, GEN_INT (c2));
3400 }
3401 else
3402 {
bc06712d 3403 HOST_WIDE_INT ud1, ud2, ud3, ud4;
252b88f7 3404
bc06712d 3405 ud1 = c1 & 0xffff;
f921c9c9 3406 ud2 = (c1 & 0xffff0000) >> 16;
2bfcf297 3407#if HOST_BITS_PER_WIDE_INT >= 64
bc06712d 3408 c2 = c1 >> 32;
2bfcf297 3409#endif
bc06712d 3410 ud3 = c2 & 0xffff;
f921c9c9 3411 ud4 = (c2 & 0xffff0000) >> 16;
2bfcf297 3412
f676971a 3413 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
bc06712d 3414 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
2bfcf297 3415 {
bc06712d 3416 if (ud1 & 0x8000)
b78d48dd 3417 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
bc06712d
TR		 3418 else
3419 emit_move_insn (dest, GEN_INT (ud1));
2bfcf297 3420 }
2bfcf297 3421
f676971a 3422 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
bc06712d 3423 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
252b88f7 3424 {
bc06712d 3425 if (ud2 & 0x8000)
f676971a 3426 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
bc06712d 3427 - 0x80000000));
252b88f7 3428 else
bc06712d
TR		 3429 emit_move_insn (dest, GEN_INT (ud2 << 16));
3430 if (ud1 != 0)
3431 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
252b88f7 3432 }
f676971a 3433 else if ((ud4 == 0xffff && (ud3 & 0x8000))
bc06712d
TR		 3434 || (ud4 == 0 && ! (ud3 & 0x8000)))
3435 {
3436 if (ud3 & 0x8000)
f676971a 3437 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
bc06712d
TR		 3438 - 0x80000000));
3439 else
3440 emit_move_insn (dest, GEN_INT (ud3 << 16));
3441
3442 if (ud2 != 0)
3443 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3444 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3445 if (ud1 != 0)
3446 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3447 }
f676971a 3448 else
bc06712d
TR		 3449 {
3450 if (ud4 & 0x8000)
f676971a 3451 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
bc06712d
TR		 3452 - 0x80000000));
3453 else
3454 emit_move_insn (dest, GEN_INT (ud4 << 16));
3455
3456 if (ud3 != 0)
3457 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
2bfcf297 3458
bc06712d
TR		 3459 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3460 if (ud2 != 0)
f676971a
EC		 3461 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3462 GEN_INT (ud2 << 16)));
bc06712d
TR		 3463 if (ud1 != 0)
3464 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3465 }
3466 }
2bfcf297
DB		 3467 return dest;
3468}
3469
76d2b81d
DJ		 3470/* Helper for the following. Get rid of [r+r] memory refs
3471 in cases where it won't work (TImode, TFmode). */
3472
3473static void
3474rs6000_eliminate_indexed_memrefs (rtx operands[2])
3475{
3476 if (GET_CODE (operands[0]) == MEM
3477 && GET_CODE (XEXP (operands[0], 0)) != REG
55aa0757 3478 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
76d2b81d
DJ		 3479 && ! reload_in_progress)
3480 operands[0]
3481 = replace_equiv_address (operands[0],
3482 copy_addr_to_reg (XEXP (operands[0], 0)));
3483
3484 if (GET_CODE (operands[1]) == MEM
3485 && GET_CODE (XEXP (operands[1], 0)) != REG
55aa0757 3486 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
76d2b81d
DJ		 3487 && ! reload_in_progress)
3488 operands[1]
3489 = replace_equiv_address (operands[1],
3490 copy_addr_to_reg (XEXP (operands[1], 0)));
3491}
3492
fb4d4348
GK		 3493/* Emit a move from SOURCE to DEST in mode MODE. */
3494void
a2369ed3 3495rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
fb4d4348
GK		 3496{
3497 rtx operands[2];
3498 operands[0] = dest;
3499 operands[1] = source;
f676971a 3500
fb4d4348
GK		 3501 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3502 if (GET_CODE (operands[1]) == CONST_DOUBLE
3503 && ! FLOAT_MODE_P (mode)
3504 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3505 {
3506 /* FIXME. This should never happen. */
3507 /* Since it seems that it does, do the safe thing and convert
3508 to a CONST_INT. */
2496c7bd 3509 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
fb4d4348
GK		 3510 }
3511 if (GET_CODE (operands[1]) == CONST_DOUBLE
3512 && ! FLOAT_MODE_P (mode)
3513 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3514 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3515 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3516 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3517 abort ();
c9e8cb32
DD		 3518
3519 /* Check if GCC is setting up a block move that will end up using FP
3520 registers as temporaries. We must make sure this is acceptable. */
3521 if (GET_CODE (operands[0]) == MEM
3522 && GET_CODE (operands[1]) == MEM
3523 && mode == DImode
41543739
GK		 3524 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3525 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3526 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3527 ? 32 : MEM_ALIGN (operands[0])))
3528 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
f676971a 3529 ? 32
41543739
GK		 3530 : MEM_ALIGN (operands[1]))))
3531 && ! MEM_VOLATILE_P (operands [0])
3532 && ! MEM_VOLATILE_P (operands [1]))
c9e8cb32 3533 {
41543739
GK		 3534 emit_move_insn (adjust_address (operands[0], SImode, 0),
3535 adjust_address (operands[1], SImode, 0));
3536 emit_move_insn (adjust_address (operands[0], SImode, 4),
3537 adjust_address (operands[1], SImode, 4));
c9e8cb32
DD		 3538 return;
3539 }
630d42a0 3540
55aa0757 3541 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
c9dbf840 3542 && !gpc_reg_operand (operands[1], mode))
f6219a5e 3543 operands[1] = force_reg (mode, operands[1]);
a9098fd0 3544
a3170dc6
AH		 3545 if (mode == SFmode && ! TARGET_POWERPC
3546 && TARGET_HARD_FLOAT && TARGET_FPRS
ffc14f31 3547 && GET_CODE (operands[0]) == MEM)
fb4d4348 3548 {
ffc14f31
GK		 3549 int regnum;
3550
3551 if (reload_in_progress || reload_completed)
3552 regnum = true_regnum (operands[1]);
3553 else if (GET_CODE (operands[1]) == REG)
3554 regnum = REGNO (operands[1]);
3555 else
3556 regnum = -1;
f676971a 3557
fb4d4348
GK		 3558 /* If operands[1] is a register, on POWER it may have
3559 double-precision data in it, so truncate it to single
3560 precision. */
3561 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3562 {
3563 rtx newreg;
3564 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3565 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3566 operands[1] = newreg;
3567 }
3568 }
3569
c4501e62
JJ		 3570 /* Recognize the case where operand[1] is a reference to thread-local
3571 data and load its address to a register. */
3572 if (GET_CODE (operands[1]) == SYMBOL_REF)
3573 {
3574 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3575 if (model != 0)
3576 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3577 }
3578
8f4e6caf
RH		 3579 /* Handle the case where reload calls us with an invalid address. */
3580 if (reload_in_progress && mode == Pmode
69ef87e2 3581 && (! general_operand (operands[1], mode)
8f4e6caf
RH		 3582 || ! nonimmediate_operand (operands[0], mode)))
3583 goto emit_set;
3584
a9baceb1
GK		 3585 /* 128-bit constant floating-point values on Darwin should really be
3586 loaded as two parts. */
3587 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3588 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3589 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3590 {
3591 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3592 know how to get a DFmode SUBREG of a TFmode. */
3593 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3594 simplify_gen_subreg (DImode, operands[1], mode, 0),
3595 DImode);
3596 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3597 GET_MODE_SIZE (DImode)),
3598 simplify_gen_subreg (DImode, operands[1], mode,
3599 GET_MODE_SIZE (DImode)),
3600 DImode);
3601 return;
3602 }
3603
fb4d4348
GK		 3604 /* FIXME: In the long term, this switch statement should go away
3605 and be replaced by a sequence of tests based on things like
3606 mode == Pmode. */
3607 switch (mode)
3608 {
3609 case HImode:
3610 case QImode:
3611 if (CONSTANT_P (operands[1])
3612 && GET_CODE (operands[1]) != CONST_INT)
a9098fd0 3613 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348
GK		 3614 break;
3615
06f4e019 3616 case TFmode:
76d2b81d
DJ		 3617 rs6000_eliminate_indexed_memrefs (operands);
3618 /* fall through */
3619
fb4d4348
GK		 3620 case DFmode:
3621 case SFmode:
f676971a 3622 if (CONSTANT_P (operands[1])
fb4d4348 3623 && ! easy_fp_constant (operands[1], mode))
a9098fd0 3624 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3625 break;
f676971a 3626
0ac081f6
AH		 3627 case V16QImode:
3628 case V8HImode:
3629 case V4SFmode:
3630 case V4SImode:
a3170dc6
AH		 3631 case V4HImode:
3632 case V2SFmode:
3633 case V2SImode:
00a892b8 3634 case V1DImode:
69ef87e2 3635 if (CONSTANT_P (operands[1])
d744e06e 3636 && !easy_vector_constant (operands[1], mode))
0ac081f6
AH		 3637 operands[1] = force_const_mem (mode, operands[1]);
3638 break;
f676971a 3639
fb4d4348 3640 case SImode:
a9098fd0 3641 case DImode:
fb4d4348
GK		 3642 /* Use default pattern for address of ELF small data */
3643 if (TARGET_ELF
a9098fd0 3644 && mode == Pmode
f607bc57 3645 && DEFAULT_ABI == ABI_V4
f676971a 3646 && (GET_CODE (operands[1]) == SYMBOL_REF
a9098fd0
GK		 3647 || GET_CODE (operands[1]) == CONST)
3648 && small_data_operand (operands[1], mode))
fb4d4348
GK		 3649 {
3650 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3651 return;
3652 }
3653
f607bc57 3654 if (DEFAULT_ABI == ABI_V4
a9098fd0
GK		 3655 && mode == Pmode && mode == SImode
3656 && flag_pic == 1 && got_operand (operands[1], mode))
fb4d4348
GK		 3657 {
3658 emit_insn (gen_movsi_got (operands[0], operands[1]));
3659 return;
3660 }
3661
ee890fe2 3662 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
f1384257
AM		 3663 && TARGET_NO_TOC
3664 && ! flag_pic
a9098fd0 3665 && mode == Pmode
fb4d4348
GK		 3666 && CONSTANT_P (operands[1])
3667 && GET_CODE (operands[1]) != HIGH
3668 && GET_CODE (operands[1]) != CONST_INT)
3669 {
a9098fd0 3670 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
fb4d4348
GK		 3671
3672 /* If this is a function address on -mcall-aixdesc,
3673 convert it to the address of the descriptor. */
3674 if (DEFAULT_ABI == ABI_AIX
3675 && GET_CODE (operands[1]) == SYMBOL_REF
3676 && XSTR (operands[1], 0)[0] == '.')
3677 {
3678 const char *name = XSTR (operands[1], 0);
3679 rtx new_ref;
3680 while (*name == '.')
3681 name++;
3682 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3683 CONSTANT_POOL_ADDRESS_P (new_ref)
3684 = CONSTANT_POOL_ADDRESS_P (operands[1]);
d1908feb 3685 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
fb4d4348 3686 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
d1908feb 3687 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
fb4d4348
GK		 3688 operands[1] = new_ref;
3689 }
7509c759 3690
ee890fe2
SS		 3691 if (DEFAULT_ABI == ABI_DARWIN)
3692 {
ab82a49f
AP		 3693#if TARGET_MACHO
3694 if (MACHO_DYNAMIC_NO_PIC_P)
3695 {
3696 /* Take care of any required data indirection. */
3697 operands[1] = rs6000_machopic_legitimize_pic_address (
3698 operands[1], mode, operands[0]);
3699 if (operands[0] != operands[1])
3700 emit_insn (gen_rtx_SET (VOIDmode,
c4ad648e 3701 operands[0], operands[1]));
ab82a49f
AP		 3702 return;
3703 }
3704#endif
b8a55285
AP		 3705 emit_insn (gen_macho_high (target, operands[1]));
3706 emit_insn (gen_macho_low (operands[0], target, operands[1]));
ee890fe2
SS		 3707 return;
3708 }
3709
fb4d4348
GK		 3710 emit_insn (gen_elf_high (target, operands[1]));
3711 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3712 return;
3713 }
3714
a9098fd0
GK		 3715 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3716 and we have put it in the TOC, we just need to make a TOC-relative
3717 reference to it. */
3718 if (TARGET_TOC
3719 && GET_CODE (operands[1]) == SYMBOL_REF
4d588c14 3720 && constant_pool_expr_p (operands[1])
a9098fd0
GK		 3721 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3722 get_pool_mode (operands[1])))
fb4d4348 3723 {
a9098fd0 3724 operands[1] = create_TOC_reference (operands[1]);
fb4d4348 3725 }
a9098fd0
GK		 3726 else if (mode == Pmode
3727 && CONSTANT_P (operands[1])
38886f37
AO		 3728 && ((GET_CODE (operands[1]) != CONST_INT
3729 && ! easy_fp_constant (operands[1], mode))
3730 || (GET_CODE (operands[1]) == CONST_INT
3731 && num_insns_constant (operands[1], mode) > 2)
3732 || (GET_CODE (operands[0]) == REG
3733 && FP_REGNO_P (REGNO (operands[0]))))
a9098fd0 3734 && GET_CODE (operands[1]) != HIGH
4d588c14
RH		 3735 && ! legitimate_constant_pool_address_p (operands[1])
3736 && ! toc_relative_expr_p (operands[1]))
fb4d4348
GK		 3737 {
3738 /* Emit a USE operation so that the constant isn't deleted if
3739 expensive optimizations are turned on because nobody
3740 references it. This should only be done for operands that
3741 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3742 This should not be done for operands that contain LABEL_REFs.
3743 For now, we just handle the obvious case. */
3744 if (GET_CODE (operands[1]) != LABEL_REF)
3745 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3746
c859cda6 3747#if TARGET_MACHO
ee890fe2 3748 /* Darwin uses a special PIC legitimizer. */
ab82a49f 3749 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
ee890fe2 3750 {
ee890fe2
SS		 3751 operands[1] =
3752 rs6000_machopic_legitimize_pic_address (operands[1], mode,
c859cda6
DJ		 3753 operands[0]);
3754 if (operands[0] != operands[1])
3755 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
ee890fe2
SS		 3756 return;
3757 }
c859cda6 3758#endif
ee890fe2 3759
fb4d4348
GK		 3760 /* If we are to limit the number of things we put in the TOC and
3761 this is a symbol plus a constant we can add in one insn,
3762 just put the symbol in the TOC and add the constant. Don't do
3763 this if reload is in progress. */
3764 if (GET_CODE (operands[1]) == CONST
3765 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3766 && GET_CODE (XEXP (operands[1], 0)) == PLUS
a9098fd0 3767 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
fb4d4348
GK		 3768 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3769 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3770 && ! side_effects_p (operands[0]))
3771 {
a4f6c312
SS		 3772 rtx sym =
3773 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
fb4d4348
GK		 3774 rtx other = XEXP (XEXP (operands[1], 0), 1);
3775
a9098fd0
GK		 3776 sym = force_reg (mode, sym);
3777 if (mode == SImode)
3778 emit_insn (gen_addsi3 (operands[0], sym, other));
3779 else
3780 emit_insn (gen_adddi3 (operands[0], sym, other));
fb4d4348
GK		 3781 return;
3782 }
3783
a9098fd0 3784 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3785
f676971a 3786 if (TARGET_TOC
4d588c14 3787 && constant_pool_expr_p (XEXP (operands[1], 0))
d34c5b80
DE		 3788 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3789 get_pool_constant (XEXP (operands[1], 0)),
3790 get_pool_mode (XEXP (operands[1], 0))))
a9098fd0 3791 {
ba4828e0 3792 operands[1]
542a8afa 3793 = gen_const_mem (mode,
c4ad648e 3794 create_TOC_reference (XEXP (operands[1], 0)));
ba4828e0 3795 set_mem_alias_set (operands[1], get_TOC_alias_set ());
a9098fd0 3796 }
fb4d4348
GK		 3797 }
3798 break;
a9098fd0 3799
fb4d4348 3800 case TImode:
76d2b81d
DJ		 3801 rs6000_eliminate_indexed_memrefs (operands);
3802
27dc0551
DE		 3803 if (TARGET_POWER)
3804 {
3805 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3806 gen_rtvec (2,
3807 gen_rtx_SET (VOIDmode,
3808 operands[0], operands[1]),
3809 gen_rtx_CLOBBER (VOIDmode,
3810 gen_rtx_SCRATCH (SImode)))));
3811 return;
3812 }
fb4d4348
GK		 3813 break;
3814
3815 default:
3816 abort ();
3817 }
3818
a9098fd0
GK		 3819 /* Above, we may have called force_const_mem which may have returned
3820 an invalid address. If we can, fix this up; otherwise, reload will
3821 have to deal with it. */
8f4e6caf
RH		 3822 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3823 operands[1] = validize_mem (operands[1]);
a9098fd0 3824
8f4e6caf 3825 emit_set:
fb4d4348
GK		 3826 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3827}
4697a36c 3828\f
2858f73a
GK		 3829/* Nonzero if we can use a floating-point register to pass this arg. */
3830#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3831 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3832 && (CUM)->fregno <= FP_ARG_MAX_REG \
3833 && TARGET_HARD_FLOAT && TARGET_FPRS)
3834
3835/* Nonzero if we can use an AltiVec register to pass this arg. */
3836#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3837 (ALTIVEC_VECTOR_MODE (MODE) \
3838 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3839 && TARGET_ALTIVEC_ABI \
83953138 3840 && (NAMED))
2858f73a 3841
c6e8c921
GK		 3842/* Return a nonzero value to say to return the function value in
3843 memory, just as large structures are always returned. TYPE will be
3844 the data type of the value, and FNTYPE will be the type of the
3845 function doing the returning, or @code{NULL} for libcalls.
3846
3847 The AIX ABI for the RS/6000 specifies that all structures are
3848 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3849 specifies that structures <= 8 bytes are returned in r3/r4, but a
3850 draft put them in memory, and GCC used to implement the draft
3851 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3852 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3853 compatibility can change DRAFT_V4_STRUCT_RET to override the
3854 default, and -m switches get the final word. See
3855 rs6000_override_options for more details.
3856
3857 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3858 long double support is enabled. These values are returned in memory.
3859
3860 int_size_in_bytes returns -1 for variable size objects, which go in
3861 memory always. The cast to unsigned makes -1 > 8. */
3862
3863static bool
3864rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3865{
594a51fe
SS		 3866 /* In the darwin64 abi, try to use registers for larger structs
3867 if possible. */
0b5383eb 3868 if (rs6000_darwin64_abi
594a51fe 3869 && TREE_CODE (type) == RECORD_TYPE
0b5383eb
DJ		 3870 && int_size_in_bytes (type) > 0)
3871 {
3872 CUMULATIVE_ARGS valcum;
3873 rtx valret;
3874
3875 valcum.words = 0;
3876 valcum.fregno = FP_ARG_MIN_REG;
3877 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3878 /* Do a trial code generation as if this were going to be passed
3879 as an argument; if any part goes in memory, we return NULL. */
3880 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3881 if (valret)
3882 return false;
3883 /* Otherwise fall through to more conventional ABI rules. */
3884 }
594a51fe 3885
c6e8c921
GK		 3886 if (AGGREGATE_TYPE_P (type)
3887 && (TARGET_AIX_STRUCT_RET
3888 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3889 return true;
b693336b 3890
bada2eb8
DE		 3891 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3892 modes only exist for GCC vector types if -maltivec. */
3893 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3894 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3895 return false;
3896
b693336b
PB		 3897 /* Return synthetic vectors in memory. */
3898 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 3899 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 3900 {
3901 static bool warned_for_return_big_vectors = false;
3902 if (!warned_for_return_big_vectors)
3903 {
bada2eb8 3904 warning ("GCC vector returned by reference: "
b693336b
PB		 3905 "non-standard ABI extension with no compatibility guarantee");
3906 warned_for_return_big_vectors = true;
3907 }
3908 return true;
3909 }
3910
c6e8c921
GK		 3911 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3912 return true;
ad630bef 3913
c6e8c921
GK		 3914 return false;
3915}
3916
4697a36c
MM		 3917/* Initialize a variable CUM of type CUMULATIVE_ARGS
3918 for a call to a function whose data type is FNTYPE.
3919 For a library call, FNTYPE is 0.
3920
3921 For incoming args we set the number of arguments in the prototype large
1c20ae99 3922 so we never return a PARALLEL. */
4697a36c
MM		 3923
3924void
f676971a 3925init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
0f6937fe
AM		 3926 rtx libname ATTRIBUTE_UNUSED, int incoming,
3927 int libcall, int n_named_args)
4697a36c
MM		 3928{
3929 static CUMULATIVE_ARGS zero_cumulative;
3930
3931 *cum = zero_cumulative;
3932 cum->words = 0;
3933 cum->fregno = FP_ARG_MIN_REG;
0ac081f6 3934 cum->vregno = ALTIVEC_ARG_MIN_REG;
4697a36c 3935 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
ddcc8263
DE		 3936 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3937 ? CALL_LIBCALL : CALL_NORMAL);
4cc833b7 3938 cum->sysv_gregno = GP_ARG_MIN_REG;
a6c9bed4
AH		 3939 cum->stdarg = fntype
3940 && (TYPE_ARG_TYPES (fntype) != 0
3941 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3942 != void_type_node));
4697a36c 3943
0f6937fe
AM		 3944 cum->nargs_prototype = 0;
3945 if (incoming || cum->prototype)
3946 cum->nargs_prototype = n_named_args;
4697a36c 3947
a5c76ee6 3948 /* Check for a longcall attribute. */
3eb4e360
AM		 3949 if ((!fntype && rs6000_default_long_calls)
3950 || (fntype
3951 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3952 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
3953 cum->call_cookie |= CALL_LONG;
6a4cee5f 3954
4697a36c
MM		 3955 if (TARGET_DEBUG_ARG)
3956 {
3957 fprintf (stderr, "\ninit_cumulative_args:");
3958 if (fntype)
3959 {
3960 tree ret_type = TREE_TYPE (fntype);
3961 fprintf (stderr, " ret code = %s,",
3962 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3963 }
3964
6a4cee5f
MM		 3965 if (cum->call_cookie & CALL_LONG)
3966 fprintf (stderr, " longcall,");
3967
4697a36c
MM		 3968 fprintf (stderr, " proto = %d, nargs = %d\n",
3969 cum->prototype, cum->nargs_prototype);
3970 }
f676971a 3971
c4ad648e
AM		 3972 if (fntype
3973 && !TARGET_ALTIVEC
3974 && TARGET_ALTIVEC_ABI
3975 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3976 {
3977 error ("Cannot return value in vector register because"
3978 " altivec instructions are disabled, use -maltivec"
3979 " to enable them.");
3980 }
4697a36c
MM		 3981}
3982\f
fe984136
RH		 3983/* Return true if TYPE must be passed on the stack and not in registers. */
3984
3985static bool
3986rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
3987{
3988 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
3989 return must_pass_in_stack_var_size (mode, type);
3990 else
3991 return must_pass_in_stack_var_size_or_pad (mode, type);
3992}
3993
c229cba9
DE		 3994/* If defined, a C expression which determines whether, and in which
3995 direction, to pad out an argument with extra space. The value
3996 should be of type `enum direction': either `upward' to pad above
3997 the argument, `downward' to pad below, or `none' to inhibit
3998 padding.
3999
4000 For the AIX ABI structs are always stored left shifted in their
4001 argument slot. */
4002
9ebbca7d 4003enum direction
a2369ed3 4004function_arg_padding (enum machine_mode mode, tree type)
c229cba9 4005{
6e985040
AM		 4006#ifndef AGGREGATE_PADDING_FIXED
4007#define AGGREGATE_PADDING_FIXED 0
4008#endif
4009#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4010#define AGGREGATES_PAD_UPWARD_ALWAYS 0
4011#endif
4012
4013 if (!AGGREGATE_PADDING_FIXED)
4014 {
4015 /* GCC used to pass structures of the same size as integer types as
4016 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
19525b57 4017 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
6e985040
AM		 4018 passed padded downward, except that -mstrict-align further
4019 muddied the water in that multi-component structures of 2 and 4
4020 bytes in size were passed padded upward.
4021
4022 The following arranges for best compatibility with previous
4023 versions of gcc, but removes the -mstrict-align dependency. */
4024 if (BYTES_BIG_ENDIAN)
4025 {
4026 HOST_WIDE_INT size = 0;
4027
4028 if (mode == BLKmode)
4029 {
4030 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4031 size = int_size_in_bytes (type);
4032 }
4033 else
4034 size = GET_MODE_SIZE (mode);
4035
4036 if (size == 1 || size == 2 || size == 4)
4037 return downward;
4038 }
4039 return upward;
4040 }
4041
4042 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4043 {
4044 if (type != 0 && AGGREGATE_TYPE_P (type))
4045 return upward;
4046 }
c229cba9 4047
d3704c46
KH		 4048 /* Fall back to the default. */
4049 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
c229cba9
DE		 4050}
4051
b6c9286a 4052/* If defined, a C expression that gives the alignment boundary, in bits,
f676971a 4053 of an argument with the specified mode and type. If it is not defined,
b6c9286a 4054 PARM_BOUNDARY is used for all arguments.
f676971a 4055
b693336b
PB		 4056 V.4 wants long longs to be double word aligned.
4057 Doubleword align SPE vectors.
4058 Quadword align Altivec vectors.
4059 Quadword align large synthetic vector types. */
b6c9286a
MM		 4060
4061int
b693336b 4062function_arg_boundary (enum machine_mode mode, tree type)
b6c9286a 4063{
4ed78545
AM		 4064 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4065 return 64;
ad630bef
DE		 4066 else if (SPE_VECTOR_MODE (mode)
4067 || (type && TREE_CODE (type) == VECTOR_TYPE
4068 && int_size_in_bytes (type) >= 8
4069 && int_size_in_bytes (type) < 16))
e1f83b4d 4070 return 64;
ad630bef
DE		 4071 else if (ALTIVEC_VECTOR_MODE (mode)
4072 || (type && TREE_CODE (type) == VECTOR_TYPE
4073 && int_size_in_bytes (type) >= 16))
0ac081f6 4074 return 128;
0b5383eb
DJ		 4075 else if (rs6000_darwin64_abi && mode == BLKmode
4076 && type && TYPE_ALIGN (type) > 64)
4077 return 128;
9ebbca7d 4078 else
b6c9286a 4079 return PARM_BOUNDARY;
b6c9286a 4080}
c53bdcf5 4081
294bd182
AM		 4082/* For a function parm of MODE and TYPE, return the starting word in
4083 the parameter area. NWORDS of the parameter area are already used. */
4084
4085static unsigned int
4086rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4087{
4088 unsigned int align;
4089 unsigned int parm_offset;
4090
4091 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4092 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4093 return nwords + (-(parm_offset + nwords) & align);
4094}
4095
c53bdcf5
AM		 4096/* Compute the size (in words) of a function argument. */
4097
4098static unsigned long
4099rs6000_arg_size (enum machine_mode mode, tree type)
4100{
4101 unsigned long size;
4102
4103 if (mode != BLKmode)
4104 size = GET_MODE_SIZE (mode);
4105 else
4106 size = int_size_in_bytes (type);
4107
4108 if (TARGET_32BIT)
4109 return (size + 3) >> 2;
4110 else
4111 return (size + 7) >> 3;
4112}
b6c9286a 4113\f
0b5383eb 4114/* Use this to flush pending int fields. */
594a51fe
SS		 4115
4116static void
0b5383eb
DJ		 4117rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4118 HOST_WIDE_INT bitpos)
594a51fe 4119{
0b5383eb
DJ		 4120 unsigned int startbit, endbit;
4121 int intregs, intoffset;
4122 enum machine_mode mode;
594a51fe 4123
0b5383eb
DJ		 4124 if (cum->intoffset == -1)
4125 return;
594a51fe 4126
0b5383eb
DJ		 4127 intoffset = cum->intoffset;
4128 cum->intoffset = -1;
4129
4130 if (intoffset % BITS_PER_WORD != 0)
4131 {
4132 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4133 MODE_INT, 0);
4134 if (mode == BLKmode)
594a51fe 4135 {
0b5383eb
DJ		 4136 /* We couldn't find an appropriate mode, which happens,
4137 e.g., in packed structs when there are 3 bytes to load.
4138 Back intoffset back to the beginning of the word in this
4139 case. */
4140 intoffset = intoffset & -BITS_PER_WORD;
594a51fe 4141 }
594a51fe 4142 }
0b5383eb
DJ		 4143
4144 startbit = intoffset & -BITS_PER_WORD;
4145 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4146 intregs = (endbit - startbit) / BITS_PER_WORD;
4147 cum->words += intregs;
4148}
4149
4150/* The darwin64 ABI calls for us to recurse down through structs,
4151 looking for elements passed in registers. Unfortunately, we have
4152 to track int register count here also because of misalignments
4153 in powerpc alignment mode. */
4154
4155static void
4156rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4157 tree type,
4158 HOST_WIDE_INT startbitpos)
4159{
4160 tree f;
4161
4162 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4163 if (TREE_CODE (f) == FIELD_DECL)
4164 {
4165 HOST_WIDE_INT bitpos = startbitpos;
4166 tree ftype = TREE_TYPE (f);
4167 enum machine_mode mode = TYPE_MODE (ftype);
4168
4169 if (DECL_SIZE (f) != 0
4170 && host_integerp (bit_position (f), 1))
4171 bitpos += int_bit_position (f);
4172
4173 /* ??? FIXME: else assume zero offset. */
4174
4175 if (TREE_CODE (ftype) == RECORD_TYPE)
4176 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4177 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4178 {
4179 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4180 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4181 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4182 }
4183 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4184 {
4185 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4186 cum->vregno++;
4187 cum->words += 2;
4188 }
4189 else if (cum->intoffset == -1)
4190 cum->intoffset = bitpos;
4191 }
594a51fe
SS		 4192}
4193
4697a36c
MM		 4194/* Update the data in CUM to advance over an argument
4195 of mode MODE and data type TYPE.
b2d04ecf
AM		 4196 (TYPE is null for libcalls where that information may not be available.)
4197
4198 Note that for args passed by reference, function_arg will be called
4199 with MODE and TYPE set to that of the pointer to the arg, not the arg
4200 itself. */
4697a36c
MM		 4201
4202void
f676971a 4203function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
594a51fe 4204 tree type, int named, int depth)
4697a36c 4205{
0b5383eb
DJ		 4206 int size;
4207
594a51fe
SS		 4208 /* Only tick off an argument if we're not recursing. */
4209 if (depth == 0)
4210 cum->nargs_prototype--;
4697a36c 4211
ad630bef
DE		 4212 if (TARGET_ALTIVEC_ABI
4213 && (ALTIVEC_VECTOR_MODE (mode)
4214 || (type && TREE_CODE (type) == VECTOR_TYPE
4215 && int_size_in_bytes (type) == 16)))
0ac081f6 4216 {
4ed78545
AM		 4217 bool stack = false;
4218
2858f73a 4219 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c4ad648e 4220 {
6d0ef01e
HP		 4221 cum->vregno++;
4222 if (!TARGET_ALTIVEC)
4223 error ("Cannot pass argument in vector register because"
4224 " altivec instructions are disabled, use -maltivec"
4225 " to enable them.");
4ed78545
AM		 4226
4227 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
f676971a 4228 even if it is going to be passed in a vector register.
4ed78545
AM		 4229 Darwin does the same for variable-argument functions. */
4230 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4231 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4232 stack = true;
6d0ef01e 4233 }
4ed78545
AM		 4234 else
4235 stack = true;
4236
4237 if (stack)
c4ad648e 4238 {
a594a19c 4239 int align;
f676971a 4240
2858f73a
GK		 4241 /* Vector parameters must be 16-byte aligned. This places
4242 them at 2 mod 4 in terms of words in 32-bit mode, since
4243 the parameter save area starts at offset 24 from the
4244 stack. In 64-bit mode, they just have to start on an
4245 even word, since the parameter save area is 16-byte
4246 aligned. Space for GPRs is reserved even if the argument
4247 will be passed in memory. */
4248 if (TARGET_32BIT)
4ed78545 4249 align = (2 - cum->words) & 3;
2858f73a
GK		 4250 else
4251 align = cum->words & 1;
c53bdcf5 4252 cum->words += align + rs6000_arg_size (mode, type);
f676971a 4253
a594a19c
GK		 4254 if (TARGET_DEBUG_ARG)
4255 {
f676971a 4256 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
a594a19c
GK		 4257 cum->words, align);
4258 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
f676971a 4259 cum->nargs_prototype, cum->prototype,
2858f73a 4260 GET_MODE_NAME (mode));
a594a19c
GK		 4261 }
4262 }
0ac081f6 4263 }
a4b0320c 4264 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
a6c9bed4
AH		 4265 && !cum->stdarg
4266 && cum->sysv_gregno <= GP_ARG_MAX_REG)
a4b0320c 4267 cum->sysv_gregno++;
594a51fe
SS		 4268
4269 else if (rs6000_darwin64_abi
4270 && mode == BLKmode
0b5383eb
DJ		 4271 && TREE_CODE (type) == RECORD_TYPE
4272 && (size = int_size_in_bytes (type)) > 0)
4273 {
4274 /* Variable sized types have size == -1 and are
4275 treated as if consisting entirely of ints.
4276 Pad to 16 byte boundary if needed. */
4277 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4278 && (cum->words % 2) != 0)
4279 cum->words++;
4280 /* For varargs, we can just go up by the size of the struct. */
4281 if (!named)
4282 cum->words += (size + 7) / 8;
4283 else
4284 {
4285 /* It is tempting to say int register count just goes up by
4286 sizeof(type)/8, but this is wrong in a case such as
4287 { int; double; int; } [powerpc alignment]. We have to
4288 grovel through the fields for these too. */
4289 cum->intoffset = 0;
4290 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4291 rs6000_darwin64_record_arg_advance_flush (cum,
4292 size * BITS_PER_UNIT);
4293 }
4294 }
f607bc57 4295 else if (DEFAULT_ABI == ABI_V4)
4697a36c 4296 {
a3170dc6 4297 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7 4298 && (mode == SFmode || mode == DFmode))
4697a36c 4299 {
4cc833b7
RH		 4300 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4301 cum->fregno++;
4302 else
4303 {
4304 if (mode == DFmode)
c4ad648e 4305 cum->words += cum->words & 1;
c53bdcf5 4306 cum->words += rs6000_arg_size (mode, type);
4cc833b7 4307 }
4697a36c 4308 }
4cc833b7
RH		 4309 else
4310 {
b2d04ecf 4311 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4312 int gregno = cum->sysv_gregno;
4313
4ed78545
AM		 4314 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4315 (r7,r8) or (r9,r10). As does any other 2 word item such
4316 as complex int due to a historical mistake. */
4317 if (n_words == 2)
4318 gregno += (1 - gregno) & 1;
4cc833b7 4319
4ed78545 4320 /* Multi-reg args are not split between registers and stack. */
4cc833b7
RH		 4321 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4322 {
4ed78545
AM		 4323 /* Long long and SPE vectors are aligned on the stack.
4324 So are other 2 word items such as complex int due to
4325 a historical mistake. */
4cc833b7
RH		 4326 if (n_words == 2)
4327 cum->words += cum->words & 1;
4328 cum->words += n_words;
4329 }
4697a36c 4330
4cc833b7
RH		 4331 /* Note: continuing to accumulate gregno past when we've started
4332 spilling to the stack indicates the fact that we've started
4333 spilling to the stack to expand_builtin_saveregs. */
4334 cum->sysv_gregno = gregno + n_words;
4335 }
4697a36c 4336
4cc833b7
RH		 4337 if (TARGET_DEBUG_ARG)
4338 {
4339 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4340 cum->words, cum->fregno);
4341 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4342 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4343 fprintf (stderr, "mode = %4s, named = %d\n",
4344 GET_MODE_NAME (mode), named);
4345 }
4697a36c
MM		 4346 }
4347 else
4cc833b7 4348 {
b2d04ecf 4349 int n_words = rs6000_arg_size (mode, type);
294bd182
AM		 4350 int start_words = cum->words;
4351 int align_words = rs6000_parm_start (mode, type, start_words);
a4f6c312 4352
294bd182 4353 cum->words = align_words + n_words;
4697a36c 4354
a3170dc6
AH		 4355 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4356 && TARGET_HARD_FLOAT && TARGET_FPRS)
c53bdcf5 4357 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4cc833b7
RH		 4358
4359 if (TARGET_DEBUG_ARG)
4360 {
4361 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4362 cum->words, cum->fregno);
4363 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4364 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
594a51fe 4365 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
294bd182 4366 named, align_words - start_words, depth);
4cc833b7
RH		 4367 }
4368 }
4697a36c 4369}
a6c9bed4 4370
f82f556d
AH		 4371static rtx
4372spe_build_register_parallel (enum machine_mode mode, int gregno)
4373{
54b695e7 4374 rtx r1, r3;
f82f556d
AH		 4375
4376 if (mode == DFmode)
4377 {
54b695e7
AH		 4378 r1 = gen_rtx_REG (DImode, gregno);
4379 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4380 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
18f63bfa
AH		 4381 }
4382 else if (mode == DCmode)
4383 {
54b695e7
AH		 4384 r1 = gen_rtx_REG (DImode, gregno);
4385 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4386 r3 = gen_rtx_REG (DImode, gregno + 2);
4387 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4388 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
f82f556d 4389 }
9390387d 4390 abort ();
18f63bfa 4391 return NULL_RTX;
f82f556d 4392}
b78d48dd 4393
f82f556d 4394/* Determine where to put a SIMD argument on the SPE. */
a6c9bed4 4395static rtx
f676971a 4396rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4397 tree type)
a6c9bed4 4398{
f82f556d
AH		 4399 int gregno = cum->sysv_gregno;
4400
4401 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
600e1f95 4402 are passed and returned in a pair of GPRs for ABI compatibility. */
18f63bfa 4403 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
f82f556d 4404 {
b5870bee
AH		 4405 int n_words = rs6000_arg_size (mode, type);
4406
f82f556d 4407 /* Doubles go in an odd/even register pair (r5/r6, etc). */
b5870bee
AH		 4408 if (mode == DFmode)
4409 gregno += (1 - gregno) & 1;
f82f556d 4410
b5870bee
AH		 4411 /* Multi-reg args are not split between registers and stack. */
4412 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
f82f556d
AH		 4413 return NULL_RTX;
4414
4415 return spe_build_register_parallel (mode, gregno);
4416 }
a6c9bed4
AH		 4417 if (cum->stdarg)
4418 {
c53bdcf5 4419 int n_words = rs6000_arg_size (mode, type);
a6c9bed4
AH		 4420
4421 /* SPE vectors are put in odd registers. */
4422 if (n_words == 2 && (gregno & 1) == 0)
4423 gregno += 1;
4424
4425 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4426 {
4427 rtx r1, r2;
4428 enum machine_mode m = SImode;
4429
4430 r1 = gen_rtx_REG (m, gregno);
4431 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4432 r2 = gen_rtx_REG (m, gregno + 1);
4433 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4434 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4435 }
4436 else
b78d48dd 4437 return NULL_RTX;
a6c9bed4
AH		 4438 }
4439 else
4440 {
f82f556d
AH		 4441 if (gregno <= GP_ARG_MAX_REG)
4442 return gen_rtx_REG (mode, gregno);
a6c9bed4 4443 else
b78d48dd 4444 return NULL_RTX;
a6c9bed4
AH		 4445 }
4446}
4447
0b5383eb
DJ		 4448/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4449 structure between cum->intoffset and bitpos to integer registers. */
594a51fe 4450
0b5383eb
DJ		 4451static void
4452rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4453 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
594a51fe 4454{
0b5383eb
DJ		 4455 enum machine_mode mode;
4456 unsigned int regno;
4457 unsigned int startbit, endbit;
4458 int this_regno, intregs, intoffset;
4459 rtx reg;
594a51fe 4460
0b5383eb
DJ		 4461 if (cum->intoffset == -1)
4462 return;
4463
4464 intoffset = cum->intoffset;
4465 cum->intoffset = -1;
4466
4467 /* If this is the trailing part of a word, try to only load that
4468 much into the register. Otherwise load the whole register. Note
4469 that in the latter case we may pick up unwanted bits. It's not a
4470 problem at the moment but may wish to revisit. */
4471
4472 if (intoffset % BITS_PER_WORD != 0)
594a51fe 4473 {
0b5383eb
DJ		 4474 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4475 MODE_INT, 0);
4476 if (mode == BLKmode)
4477 {
4478 /* We couldn't find an appropriate mode, which happens,
4479 e.g., in packed structs when there are 3 bytes to load.
4480 Back intoffset back to the beginning of the word in this
4481 case. */
4482 intoffset = intoffset & -BITS_PER_WORD;
4483 mode = word_mode;
4484 }
4485 }
4486 else
4487 mode = word_mode;
4488
4489 startbit = intoffset & -BITS_PER_WORD;
4490 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4491 intregs = (endbit - startbit) / BITS_PER_WORD;
4492 this_regno = cum->words + intoffset / BITS_PER_WORD;
4493
4494 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4495 cum->use_stack = 1;
4496
4497 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4498 if (intregs <= 0)
4499 return;
4500
4501 intoffset /= BITS_PER_UNIT;
4502 do
4503 {
4504 regno = GP_ARG_MIN_REG + this_regno;
4505 reg = gen_rtx_REG (mode, regno);
4506 rvec[(*k)++] =
4507 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4508
4509 this_regno += 1;
4510 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4511 mode = word_mode;
4512 intregs -= 1;
4513 }
4514 while (intregs > 0);
4515}
4516
4517/* Recursive workhorse for the following. */
4518
4519static void
4520rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4521 HOST_WIDE_INT startbitpos, rtx rvec[],
4522 int *k)
4523{
4524 tree f;
4525
4526 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4527 if (TREE_CODE (f) == FIELD_DECL)
4528 {
4529 HOST_WIDE_INT bitpos = startbitpos;
4530 tree ftype = TREE_TYPE (f);
4531 enum machine_mode mode = TYPE_MODE (ftype);
4532
4533 if (DECL_SIZE (f) != 0
4534 && host_integerp (bit_position (f), 1))
4535 bitpos += int_bit_position (f);
4536
4537 /* ??? FIXME: else assume zero offset. */
4538
4539 if (TREE_CODE (ftype) == RECORD_TYPE)
4540 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4541 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
594a51fe 4542 {
0b5383eb
DJ		 4543#if 0
4544 switch (mode)
594a51fe 4545 {
0b5383eb
DJ		 4546 case SCmode: mode = SFmode; break;
4547 case DCmode: mode = DFmode; break;
4548 case TCmode: mode = TFmode; break;
4549 default: break;
594a51fe 4550 }
0b5383eb
DJ		 4551#endif
4552 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4553 rvec[(*k)++]
4554 = gen_rtx_EXPR_LIST (VOIDmode,
4555 gen_rtx_REG (mode, cum->fregno++),
4556 GEN_INT (bitpos / BITS_PER_UNIT));
4557 if (mode == TFmode)
4558 cum->fregno++;
594a51fe 4559 }
0b5383eb
DJ		 4560 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4561 {
4562 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4563 rvec[(*k)++]
4564 = gen_rtx_EXPR_LIST (VOIDmode,
4565 gen_rtx_REG (mode, cum->vregno++),
4566 GEN_INT (bitpos / BITS_PER_UNIT));
4567 }
4568 else if (cum->intoffset == -1)
4569 cum->intoffset = bitpos;
4570 }
4571}
594a51fe 4572
0b5383eb
DJ		 4573/* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4574 the register(s) to be used for each field and subfield of a struct
4575 being passed by value, along with the offset of where the
4576 register's value may be found in the block. FP fields go in FP
4577 register, vector fields go in vector registers, and everything
4578 else goes in int registers, packed as in memory.
8ff40a74 4579
0b5383eb
DJ		 4580 This code is also used for function return values. RETVAL indicates
4581 whether this is the case.
8ff40a74 4582
0b5383eb
DJ		 4583 Much of this is taken from the Sparc V9 port, which has a similar
4584 calling convention. */
594a51fe 4585
0b5383eb
DJ		 4586static rtx
4587rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4588 int named, bool retval)
4589{
4590 rtx rvec[FIRST_PSEUDO_REGISTER];
4591 int k = 1, kbase = 1;
4592 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4593 /* This is a copy; modifications are not visible to our caller. */
4594 CUMULATIVE_ARGS copy_cum = *orig_cum;
4595 CUMULATIVE_ARGS *cum = &copy_cum;
4596
4597 /* Pad to 16 byte boundary if needed. */
4598 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4599 && (cum->words % 2) != 0)
4600 cum->words++;
4601
4602 cum->intoffset = 0;
4603 cum->use_stack = 0;
4604 cum->named = named;
4605
4606 /* Put entries into rvec[] for individual FP and vector fields, and
4607 for the chunks of memory that go in int regs. Note we start at
4608 element 1; 0 is reserved for an indication of using memory, and
4609 may or may not be filled in below. */
4610 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4611 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4612
4613 /* If any part of the struct went on the stack put all of it there.
4614 This hack is because the generic code for
4615 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4616 parts of the struct are not at the beginning. */
4617 if (cum->use_stack)
4618 {
4619 if (retval)
4620 return NULL_RTX; /* doesn't go in registers at all */
4621 kbase = 0;
4622 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4623 }
4624 if (k > 1 || cum->use_stack)
4625 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
594a51fe
SS		 4626 else
4627 return NULL_RTX;
4628}
4629
b78d48dd
FJ		 4630/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4631
4632static rtx
ec6376ab 4633rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
b78d48dd 4634{
ec6376ab
AM		 4635 int n_units;
4636 int i, k;
4637 rtx rvec[GP_ARG_NUM_REG + 1];
4638
4639 if (align_words >= GP_ARG_NUM_REG)
4640 return NULL_RTX;
4641
4642 n_units = rs6000_arg_size (mode, type);
4643
4644 /* Optimize the simple case where the arg fits in one gpr, except in
4645 the case of BLKmode due to assign_parms assuming that registers are
4646 BITS_PER_WORD wide. */
4647 if (n_units == 0
4648 || (n_units == 1 && mode != BLKmode))
4649 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4650
4651 k = 0;
4652 if (align_words + n_units > GP_ARG_NUM_REG)
4653 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4654 using a magic NULL_RTX component.
4655 FIXME: This is not strictly correct. Only some of the arg
4656 belongs in memory, not all of it. However, there isn't any way
4657 to do this currently, apart from building rtx descriptions for
4658 the pieces of memory we want stored. Due to bugs in the generic
4659 code we can't use the normal function_arg_partial_nregs scheme
4660 with the PARALLEL arg description we emit here.
4661 In any case, the code to store the whole arg to memory is often
4662 more efficient than code to store pieces, and we know that space
4663 is available in the right place for the whole arg. */
78a52f11
RH		 4664 /* FIXME: This should be fixed since the conversion to
4665 TARGET_ARG_PARTIAL_BYTES. */
ec6376ab
AM		 4666 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4667
4668 i = 0;
4669 do
36a454e1 4670 {
ec6376ab
AM		 4671 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4672 rtx off = GEN_INT (i++ * 4);
4673 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36a454e1 4674 }
ec6376ab
AM		 4675 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4676
4677 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
b78d48dd
FJ		 4678}
4679
4697a36c
MM		 4680/* Determine where to put an argument to a function.
4681 Value is zero to push the argument on the stack,
4682 or a hard register in which to store the argument.
4683
4684 MODE is the argument's machine mode.
4685 TYPE is the data type of the argument (as a tree).
4686 This is null for libcalls where that information may
4687 not be available.
4688 CUM is a variable of type CUMULATIVE_ARGS which gives info about
0b5383eb
DJ		 4689 the preceding args and about the function being called. It is
4690 not modified in this routine.
4697a36c
MM		 4691 NAMED is nonzero if this argument is a named parameter
4692 (otherwise it is an extra parameter matching an ellipsis).
4693
4694 On RS/6000 the first eight words of non-FP are normally in registers
4695 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4696 Under V.4, the first 8 FP args are in registers.
4697
4698 If this is floating-point and no prototype is specified, we use
4699 both an FP and integer register (or possibly FP reg and stack). Library
b9599e46 4700 functions (when CALL_LIBCALL is set) always have the proper types for args,
4697a36c 4701 so we can pass the FP value just in one register. emit_library_function
b2d04ecf
AM		 4702 doesn't support PARALLEL anyway.
4703
4704 Note that for args passed by reference, function_arg will be called
4705 with MODE and TYPE set to that of the pointer to the arg, not the arg
4706 itself. */
4697a36c 4707
9390387d 4708rtx
f676971a 4709function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4710 tree type, int named)
4697a36c 4711{
4cc833b7 4712 enum rs6000_abi abi = DEFAULT_ABI;
4697a36c 4713
a4f6c312
SS		 4714 /* Return a marker to indicate whether CR1 needs to set or clear the
4715 bit that V.4 uses to say fp args were passed in registers.
4716 Assume that we don't need the marker for software floating point,
4717 or compiler generated library calls. */
4697a36c
MM		 4718 if (mode == VOIDmode)
4719 {
f607bc57 4720 if (abi == ABI_V4
7509c759 4721 && cum->nargs_prototype < 0
b9599e46
FS		 4722 && (cum->call_cookie & CALL_LIBCALL) == 0
4723 && (cum->prototype || TARGET_NO_PROTOTYPE))
7509c759 4724 {
a3170dc6
AH		 4725 /* For the SPE, we need to crxor CR6 always. */
4726 if (TARGET_SPE_ABI)
4727 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4728 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4729 return GEN_INT (cum->call_cookie
4730 | ((cum->fregno == FP_ARG_MIN_REG)
4731 ? CALL_V4_SET_FP_ARGS
4732 : CALL_V4_CLEAR_FP_ARGS));
7509c759 4733 }
4697a36c 4734
7509c759 4735 return GEN_INT (cum->call_cookie);
4697a36c
MM		 4736 }
4737
0b5383eb
DJ		 4738 if (rs6000_darwin64_abi && mode == BLKmode
4739 && TREE_CODE (type) == RECORD_TYPE)
8ff40a74 4740 {
0b5383eb 4741 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
8ff40a74
SS		 4742 if (rslt != NULL_RTX)
4743 return rslt;
4744 /* Else fall through to usual handling. */
4745 }
4746
2858f73a 4747 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c72d6c26
HP		 4748 if (TARGET_64BIT && ! cum->prototype)
4749 {
c4ad648e
AM		 4750 /* Vector parameters get passed in vector register
4751 and also in GPRs or memory, in absence of prototype. */
4752 int align_words;
4753 rtx slot;
4754 align_words = (cum->words + 1) & ~1;
4755
4756 if (align_words >= GP_ARG_NUM_REG)
4757 {
4758 slot = NULL_RTX;
4759 }
4760 else
4761 {
4762 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4763 }
4764 return gen_rtx_PARALLEL (mode,
4765 gen_rtvec (2,
4766 gen_rtx_EXPR_LIST (VOIDmode,
4767 slot, const0_rtx),
4768 gen_rtx_EXPR_LIST (VOIDmode,
4769 gen_rtx_REG (mode, cum->vregno),
4770 const0_rtx)));
c72d6c26
HP		 4771 }
4772 else
4773 return gen_rtx_REG (mode, cum->vregno);
ad630bef
DE		 4774 else if (TARGET_ALTIVEC_ABI
4775 && (ALTIVEC_VECTOR_MODE (mode)
4776 || (type && TREE_CODE (type) == VECTOR_TYPE
4777 && int_size_in_bytes (type) == 16)))
0ac081f6 4778 {
2858f73a 4779 if (named || abi == ABI_V4)
a594a19c 4780 return NULL_RTX;
0ac081f6 4781 else
a594a19c
GK		 4782 {
4783 /* Vector parameters to varargs functions under AIX or Darwin
4784 get passed in memory and possibly also in GPRs. */
ec6376ab
AM		 4785 int align, align_words, n_words;
4786 enum machine_mode part_mode;
a594a19c
GK		 4787
4788 /* Vector parameters must be 16-byte aligned. This places them at
2858f73a
GK		 4789 2 mod 4 in terms of words in 32-bit mode, since the parameter
4790 save area starts at offset 24 from the stack. In 64-bit mode,
4791 they just have to start on an even word, since the parameter
4792 save area is 16-byte aligned. */
4793 if (TARGET_32BIT)
4ed78545 4794 align = (2 - cum->words) & 3;
2858f73a
GK		 4795 else
4796 align = cum->words & 1;
a594a19c
GK		 4797 align_words = cum->words + align;
4798
4799 /* Out of registers? Memory, then. */
4800 if (align_words >= GP_ARG_NUM_REG)
4801 return NULL_RTX;
ec6376ab
AM		 4802
4803 if (TARGET_32BIT && TARGET_POWERPC64)
4804 return rs6000_mixed_function_arg (mode, type, align_words);
4805
2858f73a
GK		 4806 /* The vector value goes in GPRs. Only the part of the
4807 value in GPRs is reported here. */
ec6376ab
AM		 4808 part_mode = mode;
4809 n_words = rs6000_arg_size (mode, type);
4810 if (align_words + n_words > GP_ARG_NUM_REG)
839a4992 4811 /* Fortunately, there are only two possibilities, the value
2858f73a
GK		 4812 is either wholly in GPRs or half in GPRs and half not. */
4813 part_mode = DImode;
ec6376ab
AM		 4814
4815 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
a594a19c 4816 }
0ac081f6 4817 }
f82f556d
AH		 4818 else if (TARGET_SPE_ABI && TARGET_SPE
4819 && (SPE_VECTOR_MODE (mode)
18f63bfa
AH		 4820 || (TARGET_E500_DOUBLE && (mode == DFmode
4821 || mode == DCmode))))
a6c9bed4 4822 return rs6000_spe_function_arg (cum, mode, type);
594a51fe 4823
f607bc57 4824 else if (abi == ABI_V4)
4697a36c 4825 {
a3170dc6 4826 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7
RH		 4827 && (mode == SFmode || mode == DFmode))
4828 {
4829 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4830 return gen_rtx_REG (mode, cum->fregno);
4831 else
b78d48dd 4832 return NULL_RTX;
4cc833b7
RH		 4833 }
4834 else
4835 {
b2d04ecf 4836 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4837 int gregno = cum->sysv_gregno;
4838
4ed78545
AM		 4839 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4840 (r7,r8) or (r9,r10). As does any other 2 word item such
4841 as complex int due to a historical mistake. */
4842 if (n_words == 2)
4843 gregno += (1 - gregno) & 1;
4cc833b7 4844
4ed78545 4845 /* Multi-reg args are not split between registers and stack. */
ec6376ab 4846 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
b78d48dd 4847 return NULL_RTX;
ec6376ab
AM		 4848
4849 if (TARGET_32BIT && TARGET_POWERPC64)
4850 return rs6000_mixed_function_arg (mode, type,
4851 gregno - GP_ARG_MIN_REG);
4852 return gen_rtx_REG (mode, gregno);
4cc833b7 4853 }
4697a36c 4854 }
4cc833b7
RH		 4855 else
4856 {
294bd182 4857 int align_words = rs6000_parm_start (mode, type, cum->words);
b78d48dd 4858
2858f73a 4859 if (USE_FP_FOR_ARG_P (cum, mode, type))
4cc833b7 4860 {
ec6376ab
AM		 4861 rtx rvec[GP_ARG_NUM_REG + 1];
4862 rtx r;
4863 int k;
c53bdcf5
AM		 4864 bool needs_psave;
4865 enum machine_mode fmode = mode;
c53bdcf5
AM		 4866 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4867
4868 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4869 {
c53bdcf5
AM		 4870 /* Currently, we only ever need one reg here because complex
4871 doubles are split. */
ec6376ab 4872 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
c53bdcf5 4873 abort ();
ec6376ab
AM		 4874
4875 /* Long double split over regs and memory. */
4876 fmode = DFmode;
c53bdcf5 4877 }
c53bdcf5
AM		 4878
4879 /* Do we also need to pass this arg in the parameter save
4880 area? */
4881 needs_psave = (type
4882 && (cum->nargs_prototype <= 0
4883 || (DEFAULT_ABI == ABI_AIX
de17c25f 4884 && TARGET_XL_COMPAT
c53bdcf5
AM		 4885 && align_words >= GP_ARG_NUM_REG)));
4886
4887 if (!needs_psave && mode == fmode)
ec6376ab 4888 return gen_rtx_REG (fmode, cum->fregno);
c53bdcf5 4889
ec6376ab 4890 k = 0;
c53bdcf5
AM		 4891 if (needs_psave)
4892 {
ec6376ab 4893 /* Describe the part that goes in gprs or the stack.
c53bdcf5 4894 This piece must come first, before the fprs. */
c53bdcf5
AM		 4895 if (align_words < GP_ARG_NUM_REG)
4896 {
4897 unsigned long n_words = rs6000_arg_size (mode, type);
ec6376ab
AM		 4898
4899 if (align_words + n_words > GP_ARG_NUM_REG
4900 || (TARGET_32BIT && TARGET_POWERPC64))
4901 {
4902 /* If this is partially on the stack, then we only
4903 include the portion actually in registers here. */
4904 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4905 rtx off;
2e6c9641 4906 int i=0;
c4ad648e
AM		 4907 if (align_words + n_words > GP_ARG_NUM_REG
4908 && (TARGET_32BIT && TARGET_POWERPC64))
4909 /* Not all of the arg fits in gprs. Say that it
4910 goes in memory too, using a magic NULL_RTX
4911 component. Also see comment in
4912 rs6000_mixed_function_arg for why the normal
4913 function_arg_partial_nregs scheme doesn't work
4914 in this case. */
4915 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4916 const0_rtx);
ec6376ab
AM		 4917 do
4918 {
4919 r = gen_rtx_REG (rmode,
4920 GP_ARG_MIN_REG + align_words);
2e6c9641 4921 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
ec6376ab
AM		 4922 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4923 }
4924 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
4925 }
4926 else
4927 {
4928 /* The whole arg fits in gprs. */
4929 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4930 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4931 }
c53bdcf5 4932 }
ec6376ab
AM		 4933 else
4934 /* It's entirely in memory. */
4935 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
c53bdcf5
AM		 4936 }
4937
ec6376ab
AM		 4938 /* Describe where this piece goes in the fprs. */
4939 r = gen_rtx_REG (fmode, cum->fregno);
4940 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4941
4942 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4cc833b7
RH		 4943 }
4944 else if (align_words < GP_ARG_NUM_REG)
b2d04ecf 4945 {
ec6376ab
AM		 4946 if (TARGET_32BIT && TARGET_POWERPC64)
4947 return rs6000_mixed_function_arg (mode, type, align_words);
b2d04ecf 4948
4eeca74f
AM		 4949 if (mode == BLKmode)
4950 mode = Pmode;
4951
b2d04ecf
AM		 4952 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4953 }
4cc833b7
RH		 4954 else
4955 return NULL_RTX;
4697a36c 4956 }
4697a36c
MM		 4957}
4958\f
ec6376ab 4959/* For an arg passed partly in registers and partly in memory, this is
fb63c729
AM		 4960 the number of bytes passed in registers. For args passed entirely in
4961 registers or entirely in memory, zero. When an arg is described by a
4962 PARALLEL, perhaps using more than one register type, this function
4963 returns the number of bytes used by the first element of the PARALLEL. */
4697a36c 4964
78a52f11
RH		 4965static int
4966rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4967 tree type, bool named)
4697a36c 4968{
c53bdcf5 4969 int ret = 0;
ec6376ab 4970 int align_words;
c53bdcf5 4971
f607bc57 4972 if (DEFAULT_ABI == ABI_V4)
4697a36c 4973 return 0;
4697a36c 4974
c53bdcf5
AM		 4975 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4976 && cum->nargs_prototype >= 0)
4977 return 0;
4978
0b5383eb
DJ		 4979 /* In this complicated case we just disable the partial_nregs code. */
4980 if (rs6000_darwin64_abi && mode == BLKmode
4981 && TREE_CODE (type) == RECORD_TYPE
4982 && int_size_in_bytes (type) > 0)
4983 return 0;
4984
294bd182 4985 align_words = rs6000_parm_start (mode, type, cum->words);
ec6376ab
AM		 4986
4987 if (USE_FP_FOR_ARG_P (cum, mode, type)
fb63c729
AM		 4988 /* If we are passing this arg in the fixed parameter save area
4989 (gprs or memory) as well as fprs, then this function should
4990 return the number of bytes passed in the parameter save area
4991 rather than bytes passed in fprs. */
ec6376ab
AM		 4992 && !(type
4993 && (cum->nargs_prototype <= 0
4994 || (DEFAULT_ABI == ABI_AIX
de17c25f 4995 && TARGET_XL_COMPAT
ec6376ab 4996 && align_words >= GP_ARG_NUM_REG))))
4697a36c 4997 {
c53bdcf5 4998 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
ec6376ab 4999 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
c53bdcf5 5000 else if (cum->nargs_prototype >= 0)
4697a36c
MM		 5001 return 0;
5002 }
5003
ec6376ab
AM		 5004 if (align_words < GP_ARG_NUM_REG
5005 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5006 ret = GP_ARG_NUM_REG - align_words;
4697a36c 5007
78a52f11
RH		 5008 ret *= (TARGET_32BIT ? 4 : 8);
5009
c53bdcf5 5010 if (ret != 0 && TARGET_DEBUG_ARG)
78a52f11 5011 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
4697a36c 5012
c53bdcf5 5013 return ret;
4697a36c
MM		 5014}
5015\f
5016/* A C expression that indicates when an argument must be passed by
5017 reference. If nonzero for an argument, a copy of that argument is
5018 made in memory and a pointer to the argument is passed instead of
5019 the argument itself. The pointer is passed in whatever way is
5020 appropriate for passing a pointer to that type.
5021
b2d04ecf
AM		 5022 Under V.4, aggregates and long double are passed by reference.
5023
5024 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5025 reference unless the AltiVec vector extension ABI is in force.
c8c99a68
DE		 5026
5027 As an extension to all ABIs, variable sized types are passed by
5028 reference. */
4697a36c 5029
8cd5a4e0 5030static bool
f676971a 5031rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
bada2eb8
DE		 5032 enum machine_mode mode, tree type,
5033 bool named ATTRIBUTE_UNUSED)
4697a36c 5034{
bada2eb8 5035 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
4697a36c
MM		 5036 {
5037 if (TARGET_DEBUG_ARG)
bada2eb8
DE		 5038 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5039 return 1;
5040 }
5041
5042 if (!type)
5043 return 0;
4697a36c 5044
bada2eb8
DE		 5045 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5046 {
5047 if (TARGET_DEBUG_ARG)
5048 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5049 return 1;
5050 }
5051
5052 if (int_size_in_bytes (type) < 0)
5053 {
5054 if (TARGET_DEBUG_ARG)
5055 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5056 return 1;
5057 }
5058
5059 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5060 modes only exist for GCC vector types if -maltivec. */
5061 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5062 {
5063 if (TARGET_DEBUG_ARG)
5064 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
4697a36c
MM		 5065 return 1;
5066 }
b693336b
PB		 5067
5068 /* Pass synthetic vectors in memory. */
bada2eb8 5069 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 5070 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 5071 {
5072 static bool warned_for_pass_big_vectors = false;
5073 if (TARGET_DEBUG_ARG)
5074 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5075 if (!warned_for_pass_big_vectors)
5076 {
bada2eb8 5077 warning ("GCC vector passed by reference: "
b693336b
PB		 5078 "non-standard ABI extension with no compatibility guarantee");
5079 warned_for_pass_big_vectors = true;
5080 }
5081 return 1;
5082 }
5083
b2d04ecf 5084 return 0;
4697a36c 5085}
5985c7a6
FJ		 5086
5087static void
2d9db8eb 5088rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5985c7a6
FJ		 5089{
5090 int i;
5091 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5092
5093 if (nregs == 0)
5094 return;
5095
c4ad648e 5096 for (i = 0; i < nregs; i++)
5985c7a6 5097 {
9390387d 5098 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5985c7a6 5099 if (reload_completed)
c4ad648e
AM		 5100 {
5101 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5102 tem = NULL_RTX;
5103 else
5104 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
9390387d 5105 i * GET_MODE_SIZE (reg_mode));
c4ad648e 5106 }
5985c7a6
FJ		 5107 else
5108 tem = replace_equiv_address (tem, XEXP (tem, 0));
5109
5110 if (tem == NULL_RTX)
c4ad648e 5111 abort ();
5985c7a6
FJ		 5112
5113 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5114 }
5115}
4697a36c
MM		 5116\f
5117/* Perform any needed actions needed for a function that is receiving a
f676971a 5118 variable number of arguments.
4697a36c
MM		 5119
5120 CUM is as above.
5121
5122 MODE and TYPE are the mode and type of the current parameter.
5123
5124 PRETEND_SIZE is a variable that should be set to the amount of stack
5125 that must be pushed by the prolog to pretend that our caller pushed
5126 it.
5127
5128 Normally, this macro will push all remaining incoming registers on the
5129 stack and set PRETEND_SIZE to the length of the registers pushed. */
5130
c6e8c921 5131static void
f676971a 5132setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
c4ad648e
AM		 5133 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5134 int no_rtl)
4697a36c 5135{
4cc833b7
RH		 5136 CUMULATIVE_ARGS next_cum;
5137 int reg_size = TARGET_32BIT ? 4 : 8;
ca5adc63 5138 rtx save_area = NULL_RTX, mem;
dfafc897 5139 int first_reg_offset, set;
4697a36c 5140
f31bf321 5141 /* Skip the last named argument. */
d34c5b80 5142 next_cum = *cum;
594a51fe 5143 function_arg_advance (&next_cum, mode, type, 1, 0);
4cc833b7 5144
f607bc57 5145 if (DEFAULT_ABI == ABI_V4)
d34c5b80 5146 {
60e2d0ca 5147 if (! no_rtl)
2c4974b7 5148 save_area = plus_constant (virtual_stack_vars_rtx,
bd227acc 5149 - RS6000_VARARGS_SIZE);
4cc833b7
RH		 5150
5151 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4697a36c 5152 }
60e2d0ca 5153 else
4697a36c 5154 {
d34c5b80 5155 first_reg_offset = next_cum.words;
4cc833b7 5156 save_area = virtual_incoming_args_rtx;
4697a36c 5157
fe984136 5158 if (targetm.calls.must_pass_in_stack (mode, type))
c53bdcf5 5159 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
4cc833b7 5160 }
4697a36c 5161
dfafc897 5162 set = get_varargs_alias_set ();
5496b36f 5163 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4cc833b7 5164 {
dfafc897 5165 mem = gen_rtx_MEM (BLKmode,
c4ad648e 5166 plus_constant (save_area,
dfafc897 5167 first_reg_offset * reg_size)),
ba4828e0 5168 set_mem_alias_set (mem, set);
8ac61af7 5169 set_mem_align (mem, BITS_PER_WORD);
dfafc897 5170
f676971a 5171 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
c4ad648e 5172 GP_ARG_NUM_REG - first_reg_offset);
4697a36c
MM		 5173 }
5174
4697a36c 5175 /* Save FP registers if needed. */
f607bc57 5176 if (DEFAULT_ABI == ABI_V4
a3170dc6
AH		 5177 && TARGET_HARD_FLOAT && TARGET_FPRS
5178 && ! no_rtl
5496b36f 5179 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4697a36c 5180 {
5496b36f 5181 int fregno = next_cum.fregno;
9ebbca7d 5182 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4cc833b7
RH		 5183 rtx lab = gen_label_rtx ();
5184 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4697a36c 5185
c4ad648e
AM		 5186 emit_jump_insn
5187 (gen_rtx_SET (VOIDmode,
5188 pc_rtx,
5189 gen_rtx_IF_THEN_ELSE (VOIDmode,
4cc833b7 5190 gen_rtx_NE (VOIDmode, cr1,
c4ad648e 5191 const0_rtx),
39403d82 5192 gen_rtx_LABEL_REF (VOIDmode, lab),
4697a36c
MM		 5193 pc_rtx)));
5194
5496b36f 5195 while (fregno <= FP_ARG_V4_MAX_REG)
4cc833b7 5196 {
5496b36f 5197 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
c4ad648e 5198 set_mem_alias_set (mem, set);
94ff898d 5199 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
dfafc897 5200 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5496b36f
JJ		 5201 fregno++;
5202 off += 8;
4697a36c 5203 }
4cc833b7
RH		 5204
5205 emit_label (lab);
4697a36c 5206 }
4697a36c 5207}
4697a36c 5208
dfafc897 5209/* Create the va_list data type. */
2c4974b7 5210
c35d187f
RH		 5211static tree
5212rs6000_build_builtin_va_list (void)
dfafc897 5213{
64c2816f 5214 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4697a36c 5215
9ebbca7d
GK		 5216 /* For AIX, prefer 'char *' because that's what the system
5217 header files like. */
f607bc57 5218 if (DEFAULT_ABI != ABI_V4)
9ebbca7d 5219 return build_pointer_type (char_type_node);
dfafc897 5220
f1e639b1 5221 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
bab45a51 5222 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
0f4fd75d 5223
f676971a 5224 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
9ebbca7d 5225 unsigned_char_type_node);
f676971a 5226 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
9ebbca7d 5227 unsigned_char_type_node);
64c2816f
DT		 5228 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5229 every user file. */
5230 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5231 short_unsigned_type_node);
dfafc897
FS		 5232 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5233 ptr_type_node);
5234 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5235 ptr_type_node);
5236
5237 DECL_FIELD_CONTEXT (f_gpr) = record;
5238 DECL_FIELD_CONTEXT (f_fpr) = record;
64c2816f 5239 DECL_FIELD_CONTEXT (f_res) = record;
dfafc897
FS		 5240 DECL_FIELD_CONTEXT (f_ovf) = record;
5241 DECL_FIELD_CONTEXT (f_sav) = record;
5242
bab45a51
FS		 5243 TREE_CHAIN (record) = type_decl;
5244 TYPE_NAME (record) = type_decl;
dfafc897
FS		 5245 TYPE_FIELDS (record) = f_gpr;
5246 TREE_CHAIN (f_gpr) = f_fpr;
64c2816f
DT		 5247 TREE_CHAIN (f_fpr) = f_res;
5248 TREE_CHAIN (f_res) = f_ovf;
dfafc897
FS		 5249 TREE_CHAIN (f_ovf) = f_sav;
5250
5251 layout_type (record);
5252
5253 /* The correct type is an array type of one element. */
5254 return build_array_type (record, build_index_type (size_zero_node));
5255}
5256
5257/* Implement va_start. */
5258
5259void
a2369ed3 5260rs6000_va_start (tree valist, rtx nextarg)
4697a36c 5261{
dfafc897 5262 HOST_WIDE_INT words, n_gpr, n_fpr;
c566f9bd 5263 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
dfafc897 5264 tree gpr, fpr, ovf, sav, t;
2c4974b7 5265
dfafc897 5266 /* Only SVR4 needs something special. */
f607bc57 5267 if (DEFAULT_ABI != ABI_V4)
dfafc897 5268 {
e5faf155 5269 std_expand_builtin_va_start (valist, nextarg);
dfafc897
FS		 5270 return;
5271 }
5272
973a648b 5273 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
dfafc897 5274 f_fpr = TREE_CHAIN (f_gpr);
c566f9bd
DT		 5275 f_res = TREE_CHAIN (f_fpr);
5276 f_ovf = TREE_CHAIN (f_res);
dfafc897
FS		 5277 f_sav = TREE_CHAIN (f_ovf);
5278
872a65b5 5279 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5280 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5281 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5282 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5283 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
dfafc897
FS		 5284
5285 /* Count number of gp and fp argument registers used. */
4cc833b7 5286 words = current_function_args_info.words;
987732e0
DE		 5287 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5288 GP_ARG_NUM_REG);
5289 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5290 FP_ARG_NUM_REG);
dfafc897
FS		 5291
5292 if (TARGET_DEBUG_ARG)
4a0a75dd
KG		 5293 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5294 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5295 words, n_gpr, n_fpr);
dfafc897 5296
5496b36f
JJ		 5297 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5298 build_int_cst (NULL_TREE, n_gpr));
5299 TREE_SIDE_EFFECTS (t) = 1;
5300 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
58c8adc1 5301
5496b36f
JJ		 5302 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5303 build_int_cst (NULL_TREE, n_fpr));
5304 TREE_SIDE_EFFECTS (t) = 1;
5305 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
dfafc897
FS		 5306
5307 /* Find the overflow area. */
5308 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5309 if (words != 0)
5310 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
7d60be94 5311 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
dfafc897
FS		 5312 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5313 TREE_SIDE_EFFECTS (t) = 1;
5314 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5315
5316 /* Find the register save area. */
5317 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5318 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
7d60be94 5319 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
dfafc897
FS		 5320 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5321 TREE_SIDE_EFFECTS (t) = 1;
5322 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5323}
5324
5325/* Implement va_arg. */
5326
23a60a04
JM		 5327tree
5328rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
cd3ce9b4 5329{
cd3ce9b4
JM		 5330 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5331 tree gpr, fpr, ovf, sav, reg, t, u;
08b0dc1b 5332 int size, rsize, n_reg, sav_ofs, sav_scale;
cd3ce9b4
JM		 5333 tree lab_false, lab_over, addr;
5334 int align;
5335 tree ptrtype = build_pointer_type (type);
5336
08b0dc1b
RH		 5337 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5338 {
5339 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
872a65b5 5340 return build_va_arg_indirect_ref (t);
08b0dc1b
RH		 5341 }
5342
cd3ce9b4
JM		 5343 if (DEFAULT_ABI != ABI_V4)
5344 {
08b0dc1b 5345 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
cd3ce9b4
JM		 5346 {
5347 tree elem_type = TREE_TYPE (type);
5348 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5349 int elem_size = GET_MODE_SIZE (elem_mode);
5350
5351 if (elem_size < UNITS_PER_WORD)
5352 {
23a60a04 5353 tree real_part, imag_part;
cd3ce9b4
JM		 5354 tree post = NULL_TREE;
5355
23a60a04
JM		 5356 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5357 &post);
5358 /* Copy the value into a temporary, lest the formal temporary
5359 be reused out from under us. */
5360 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
cd3ce9b4
JM		 5361 append_to_statement_list (post, pre_p);
5362
23a60a04
JM		 5363 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5364 post_p);
cd3ce9b4 5365
23a60a04 5366 return build (COMPLEX_EXPR, type, real_part, imag_part);
cd3ce9b4
JM		 5367 }
5368 }
5369
23a60a04 5370 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
cd3ce9b4
JM		 5371 }
5372
5373 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5374 f_fpr = TREE_CHAIN (f_gpr);
5375 f_res = TREE_CHAIN (f_fpr);
5376 f_ovf = TREE_CHAIN (f_res);
5377 f_sav = TREE_CHAIN (f_ovf);
5378
872a65b5 5379 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5380 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5381 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5382 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5383 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
cd3ce9b4
JM		 5384
5385 size = int_size_in_bytes (type);
5386 rsize = (size + 3) / 4;
5387 align = 1;
5388
08b0dc1b
RH		 5389 if (TARGET_HARD_FLOAT && TARGET_FPRS
5390 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
cd3ce9b4
JM		 5391 {
5392 /* FP args go in FP registers, if present. */
cd3ce9b4
JM		 5393 reg = fpr;
5394 n_reg = 1;
5395 sav_ofs = 8*4;
5396 sav_scale = 8;
5397 if (TYPE_MODE (type) == DFmode)
5398 align = 8;
5399 }
5400 else
5401 {
5402 /* Otherwise into GP registers. */
cd3ce9b4
JM		 5403 reg = gpr;
5404 n_reg = rsize;
5405 sav_ofs = 0;
5406 sav_scale = 4;
5407 if (n_reg == 2)
5408 align = 8;
5409 }
5410
5411 /* Pull the value out of the saved registers.... */
5412
5413 lab_over = NULL;
5414 addr = create_tmp_var (ptr_type_node, "addr");
5415 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5416
5417 /* AltiVec vectors never go in registers when -mabi=altivec. */
5418 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5419 align = 16;
5420 else
5421 {
5422 lab_false = create_artificial_label ();
5423 lab_over = create_artificial_label ();
5424
5425 /* Long long and SPE vectors are aligned in the registers.
5426 As are any other 2 gpr item such as complex int due to a
5427 historical mistake. */
5428 u = reg;
5429 if (n_reg == 2)
5430 {
5431 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
95674810 5432 size_int (n_reg - 1));
cd3ce9b4
JM		 5433 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5434 }
5435
95674810 5436 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
cd3ce9b4
JM		 5437 t = build2 (GE_EXPR, boolean_type_node, u, t);
5438 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5439 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5440 gimplify_and_add (t, pre_p);
5441
5442 t = sav;
5443 if (sav_ofs)
95674810 5444 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
cd3ce9b4 5445
95674810 5446 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
cd3ce9b4 5447 u = build1 (CONVERT_EXPR, integer_type_node, u);
95674810 5448 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
cd3ce9b4
JM		 5449 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5450
5451 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5452 gimplify_and_add (t, pre_p);
5453
5454 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5455 gimplify_and_add (t, pre_p);
5456
5457 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5458 append_to_statement_list (t, pre_p);
5459
5460 if (n_reg > 2)
5461 {
5462 /* Ensure that we don't find any more args in regs.
5463 Alignment has taken care of the n_reg == 2 case. */
95674810 5464 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
cd3ce9b4
JM		 5465 gimplify_and_add (t, pre_p);
5466 }
5467 }
5468
5469 /* ... otherwise out of the overflow area. */
5470
5471 /* Care for on-stack alignment if needed. */
5472 t = ovf;
5473 if (align != 1)
5474 {
95674810 5475 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
4a90aeeb 5476 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7d60be94 5477 build_int_cst (NULL_TREE, -align));
cd3ce9b4
JM		 5478 }
5479 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5480
5481 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5482 gimplify_and_add (u, pre_p);
5483
95674810 5484 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
cd3ce9b4
JM		 5485 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5486 gimplify_and_add (t, pre_p);
5487
5488 if (lab_over)
5489 {
5490 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5491 append_to_statement_list (t, pre_p);
5492 }
5493
08b0dc1b 5494 addr = fold_convert (ptrtype, addr);
872a65b5 5495 return build_va_arg_indirect_ref (addr);
cd3ce9b4
JM		 5496}
5497
0ac081f6
AH		 5498/* Builtins. */
5499
6e34d3a3
JM		 5500#define def_builtin(MASK, NAME, TYPE, CODE) \
5501do { \
5502 if ((MASK) & target_flags) \
5503 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5504 NULL, NULL_TREE); \
0ac081f6
AH		 5505} while (0)
5506
24408032
AH		 5507/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5508
2212663f 5509static const struct builtin_description bdesc_3arg[] =
24408032
AH		 5510{
5511 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5512 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5513 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5514 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5515 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5516 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5517 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5518 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5519 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5520 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
f676971a 5521 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
aba5fb01
NS		 5522 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5523 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5524 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5525 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5526 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5527 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5528 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5529 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5530 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5531 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5532 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5533 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
24408032 5534};
2212663f 5535
95385cbb
AH		 5536/* DST operations: void foo (void *, const int, const char). */
5537
5538static const struct builtin_description bdesc_dst[] =
5539{
5540 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5541 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5542 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5543 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5544};
5545
2212663f 5546/* Simple binary operations: VECc = foo (VECa, VECb). */
24408032 5547
a3170dc6 5548static struct builtin_description bdesc_2arg[] =
0ac081f6 5549{
f18c054f
DB		 5550 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5551 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5552 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5553 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
0ac081f6
AH		 5554 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5555 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5556 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5557 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5558 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5559 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5560 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
f18c054f 5561 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
aba5fb01 5562 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
0ac081f6
AH		 5563 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5564 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5565 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5566 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5567 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5568 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
617e0e1d
DB		 5569 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5570 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
0ac081f6
AH		 5571 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5572 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5573 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5574 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5575 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5576 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5577 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5578 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5579 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5580 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5581 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5582 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5583 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
617e0e1d
DB		 5584 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5585 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
f18c054f
DB		 5586 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5587 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
df966bff
AH		 5588 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5589 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5590 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5591 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5592 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
0ac081f6
AH		 5593 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5594 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5595 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5596 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5597 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5598 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
f18c054f
DB		 5599 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5600 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5601 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5602 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5603 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5604 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5605 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
0ac081f6
AH		 5606 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5607 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5608 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5609 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5610 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5611 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5612 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5613 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
f96bc213 5614 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
f18c054f 5615 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
0ac081f6
AH		 5616 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5617 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5618 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5619 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5620 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5621 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5622 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5623 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5624 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5625 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5626 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5627 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5628 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5629 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5630 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5631 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5632 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5633 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5634 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
2212663f
DB		 5635 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5636 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5637 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
0ac081f6 5638 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
f18c054f
DB		 5639 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5640 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
0ac081f6
AH		 5641 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5642 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5643 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5644 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5645 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
f18c054f
DB		 5646 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5647 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5648 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5649 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
0ac081f6
AH		 5650 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5651 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5652 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5653 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5654 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5655 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5656 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5657 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5658 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5659 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5660 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5661 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
f18c054f 5662 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
a3170dc6
AH		 5663
5664 /* Place holder, leave as first spe builtin. */
5665 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5666 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5667 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5668 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5669 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5670 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5671 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5672 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5673 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5674 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5675 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5676 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5677 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5678 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5679 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5680 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5681 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5682 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5683 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5684 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5685 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5686 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5687 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5688 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5689 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5690 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5691 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5692 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5693 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5694 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5695 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5696 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5697 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5698 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5699 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5700 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5701 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5702 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5703 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5704 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5705 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5706 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5707 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5708 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5709 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5710 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5711 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5712 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5713 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5714 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5715 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5716 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5717 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5718 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5719 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5720 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5721 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5722 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5723 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5724 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5725 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5726 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5727 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5728 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5729 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5730 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5731 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5732 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5733 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5734 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5735 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5736 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5737 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5738 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
a3170dc6
AH		 5739 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5740 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
a3170dc6
AH		 5741 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5742 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5743 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5744 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5745 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5746 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5747 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5748 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5749 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5750 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5751 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5752 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5753 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5754 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5755 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5756 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5757 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5758 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5759 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5760 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5761 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5762 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5763 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5764 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5765 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5766 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5767 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5768 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5769 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5770 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5771 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5772 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5773 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5774
5775 /* SPE binary operations expecting a 5-bit unsigned literal. */
5776 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5777
5778 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5779 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5780 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5781 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5782 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5783 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5784 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5785 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5786 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5787 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5788 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5789 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5790 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5791 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5792 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5793 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5794 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5795 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5796 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5797 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5798 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5799 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5800 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5801 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5802 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5803 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5804
5805 /* Place-holder. Leave as last binary SPE builtin. */
17edbda5 5806 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
ae4b4a02
AH		 5807};
5808
5809/* AltiVec predicates. */
5810
5811struct builtin_description_predicates
5812{
5813 const unsigned int mask;
5814 const enum insn_code icode;
5815 const char *opcode;
5816 const char *const name;
5817 const enum rs6000_builtins code;
5818};
5819
5820static const struct builtin_description_predicates bdesc_altivec_preds[] =
5821{
5822 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5823 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5824 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5825 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5826 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5827 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5828 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5829 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5830 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5831 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5832 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5833 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5834 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
0ac081f6 5835};
24408032 5836
a3170dc6
AH		 5837/* SPE predicates. */
5838static struct builtin_description bdesc_spe_predicates[] =
5839{
5840 /* Place-holder. Leave as first. */
5841 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5842 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5843 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5844 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5845 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5846 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5847 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5848 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5849 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5850 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5851 /* Place-holder. Leave as last. */
5852 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5853};
5854
5855/* SPE evsel predicates. */
5856static struct builtin_description bdesc_spe_evsel[] =
5857{
5858 /* Place-holder. Leave as first. */
5859 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5860 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5861 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5862 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5863 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5864 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5865 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5866 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5867 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5868 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5869 /* Place-holder. Leave as last. */
5870 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5871};
5872
b6d08ca1 5873/* ABS* operations. */
100c4561
AH		 5874
5875static const struct builtin_description bdesc_abs[] =
5876{
5877 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5878 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5879 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5880 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5881 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5882 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5883 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5884};
5885
617e0e1d
DB		 5886/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5887 foo (VECa). */
24408032 5888
a3170dc6 5889static struct builtin_description bdesc_1arg[] =
2212663f 5890{
617e0e1d
DB		 5891 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5892 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5893 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5894 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5895 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5896 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5897 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5898 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
2212663f
DB		 5899 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5900 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5901 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
20e26713
AH		 5902 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5903 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5904 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5905 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5906 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5907 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
a3170dc6
AH		 5908
5909 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5910 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5911 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5912 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5913 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5914 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5915 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5916 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5917 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5918 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5919 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5920 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5921 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5922 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5923 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5924 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5925 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5926 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5927 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5928 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5929 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5930 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5931 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5932 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5933 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6a599451 5934 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
a3170dc6
AH		 5935 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5936 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5937 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5938 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
a3170dc6
AH		 5939
5940 /* Place-holder. Leave as last unary SPE builtin. */
5941 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
2212663f
DB		 5942};
5943
5944static rtx
a2369ed3 5945rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 5946{
5947 rtx pat;
5948 tree arg0 = TREE_VALUE (arglist);
5949 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5950 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5951 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5952
0559cc77
DE		 5953 if (icode == CODE_FOR_nothing)
5954 /* Builtin not supported on this processor. */
5955 return 0;
5956
20e26713
AH		 5957 /* If we got invalid arguments bail out before generating bad rtl. */
5958 if (arg0 == error_mark_node)
9a171fcd 5959 return const0_rtx;
20e26713 5960
0559cc77
DE		 5961 if (icode == CODE_FOR_altivec_vspltisb
5962 || icode == CODE_FOR_altivec_vspltish
5963 || icode == CODE_FOR_altivec_vspltisw
5964 || icode == CODE_FOR_spe_evsplatfi
5965 || icode == CODE_FOR_spe_evsplati)
b44140e7
AH		 5966 {
5967 /* Only allow 5-bit *signed* literals. */
b44140e7
AH		 5968 if (GET_CODE (op0) != CONST_INT
5969 || INTVAL (op0) > 0x1f
5970 || INTVAL (op0) < -0x1f)
5971 {
5972 error ("argument 1 must be a 5-bit signed literal");
9a171fcd 5973 return const0_rtx;
b44140e7 5974 }
b44140e7
AH		 5975 }
5976
c62f2db5 5977 if (target == 0
2212663f
DB		 5978 || GET_MODE (target) != tmode
5979 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5980 target = gen_reg_rtx (tmode);
5981
5982 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5983 op0 = copy_to_mode_reg (mode0, op0);
5984
5985 pat = GEN_FCN (icode) (target, op0);
5986 if (! pat)
5987 return 0;
5988 emit_insn (pat);
0ac081f6 5989
2212663f
DB		 5990 return target;
5991}
ae4b4a02 5992
100c4561 5993static rtx
a2369ed3 5994altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
100c4561
AH		 5995{
5996 rtx pat, scratch1, scratch2;
5997 tree arg0 = TREE_VALUE (arglist);
5998 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5999 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6000 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6001
6002 /* If we have invalid arguments, bail out before generating bad rtl. */
6003 if (arg0 == error_mark_node)
9a171fcd 6004 return const0_rtx;
100c4561
AH		 6005
6006 if (target == 0
6007 || GET_MODE (target) != tmode
6008 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6009 target = gen_reg_rtx (tmode);
6010
6011 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6012 op0 = copy_to_mode_reg (mode0, op0);
6013
6014 scratch1 = gen_reg_rtx (mode0);
6015 scratch2 = gen_reg_rtx (mode0);
6016
6017 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6018 if (! pat)
6019 return 0;
6020 emit_insn (pat);
6021
6022 return target;
6023}
6024
0ac081f6 6025static rtx
a2369ed3 6026rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
0ac081f6
AH		 6027{
6028 rtx pat;
6029 tree arg0 = TREE_VALUE (arglist);
6030 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6031 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6032 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6033 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6034 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6035 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6036
0559cc77
DE		 6037 if (icode == CODE_FOR_nothing)
6038 /* Builtin not supported on this processor. */
6039 return 0;
6040
20e26713
AH		 6041 /* If we got invalid arguments bail out before generating bad rtl. */
6042 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6043 return const0_rtx;
20e26713 6044
0559cc77
DE		 6045 if (icode == CODE_FOR_altivec_vcfux
6046 || icode == CODE_FOR_altivec_vcfsx
6047 || icode == CODE_FOR_altivec_vctsxs
6048 || icode == CODE_FOR_altivec_vctuxs
6049 || icode == CODE_FOR_altivec_vspltb
6050 || icode == CODE_FOR_altivec_vsplth
6051 || icode == CODE_FOR_altivec_vspltw
6052 || icode == CODE_FOR_spe_evaddiw
6053 || icode == CODE_FOR_spe_evldd
6054 || icode == CODE_FOR_spe_evldh
6055 || icode == CODE_FOR_spe_evldw
6056 || icode == CODE_FOR_spe_evlhhesplat
6057 || icode == CODE_FOR_spe_evlhhossplat
6058 || icode == CODE_FOR_spe_evlhhousplat
6059 || icode == CODE_FOR_spe_evlwhe
6060 || icode == CODE_FOR_spe_evlwhos
6061 || icode == CODE_FOR_spe_evlwhou
6062 || icode == CODE_FOR_spe_evlwhsplat
6063 || icode == CODE_FOR_spe_evlwwsplat
6064 || icode == CODE_FOR_spe_evrlwi
6065 || icode == CODE_FOR_spe_evslwi
6066 || icode == CODE_FOR_spe_evsrwis
f5119d10 6067 || icode == CODE_FOR_spe_evsubifw
0559cc77 6068 || icode == CODE_FOR_spe_evsrwiu)
b44140e7
AH		 6069 {
6070 /* Only allow 5-bit unsigned literals. */
8bb418a3 6071 STRIP_NOPS (arg1);
b44140e7
AH		 6072 if (TREE_CODE (arg1) != INTEGER_CST
6073 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6074 {
6075 error ("argument 2 must be a 5-bit unsigned literal");
9a171fcd 6076 return const0_rtx;
b44140e7 6077 }
b44140e7
AH		 6078 }
6079
c62f2db5 6080 if (target == 0
0ac081f6
AH		 6081 || GET_MODE (target) != tmode
6082 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6083 target = gen_reg_rtx (tmode);
6084
6085 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6086 op0 = copy_to_mode_reg (mode0, op0);
6087 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6088 op1 = copy_to_mode_reg (mode1, op1);
6089
6090 pat = GEN_FCN (icode) (target, op0, op1);
6091 if (! pat)
6092 return 0;
6093 emit_insn (pat);
6094
6095 return target;
6096}
6525c0e7 6097
ae4b4a02 6098static rtx
f676971a 6099altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
a2369ed3 6100 tree arglist, rtx target)
ae4b4a02
AH		 6101{
6102 rtx pat, scratch;
6103 tree cr6_form = TREE_VALUE (arglist);
6104 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6105 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6106 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6107 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6108 enum machine_mode tmode = SImode;
6109 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6110 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6111 int cr6_form_int;
6112
6113 if (TREE_CODE (cr6_form) != INTEGER_CST)
6114 {
6115 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9a171fcd 6116 return const0_rtx;
ae4b4a02
AH		 6117 }
6118 else
6119 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6120
6121 if (mode0 != mode1)
6122 abort ();
6123
6124 /* If we have invalid arguments, bail out before generating bad rtl. */
6125 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6126 return const0_rtx;
ae4b4a02
AH		 6127
6128 if (target == 0
6129 || GET_MODE (target) != tmode
6130 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6131 target = gen_reg_rtx (tmode);
6132
6133 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6134 op0 = copy_to_mode_reg (mode0, op0);
6135 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6136 op1 = copy_to_mode_reg (mode1, op1);
6137
6138 scratch = gen_reg_rtx (mode0);
6139
6140 pat = GEN_FCN (icode) (scratch, op0, op1,
f1c25d3b 6141 gen_rtx_SYMBOL_REF (Pmode, opcode));
ae4b4a02
AH		 6142 if (! pat)
6143 return 0;
6144 emit_insn (pat);
6145
6146 /* The vec_any* and vec_all* predicates use the same opcodes for two
6147 different operations, but the bits in CR6 will be different
6148 depending on what information we want. So we have to play tricks
6149 with CR6 to get the right bits out.
6150
6151 If you think this is disgusting, look at the specs for the
6152 AltiVec predicates. */
6153
c4ad648e
AM		 6154 switch (cr6_form_int)
6155 {
6156 case 0:
6157 emit_insn (gen_cr6_test_for_zero (target));
6158 break;
6159 case 1:
6160 emit_insn (gen_cr6_test_for_zero_reverse (target));
6161 break;
6162 case 2:
6163 emit_insn (gen_cr6_test_for_lt (target));
6164 break;
6165 case 3:
6166 emit_insn (gen_cr6_test_for_lt_reverse (target));
6167 break;
6168 default:
6169 error ("argument 1 of __builtin_altivec_predicate is out of range");
6170 break;
6171 }
ae4b4a02
AH		 6172
6173 return target;
6174}
6175
b4a62fa0 6176static rtx
38f391a5 6177altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
b4a62fa0
SB		 6178{
6179 rtx pat, addr;
6180 tree arg0 = TREE_VALUE (arglist);
6181 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6182 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6183 enum machine_mode mode0 = Pmode;
6184 enum machine_mode mode1 = Pmode;
6185 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6186 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6187
6188 if (icode == CODE_FOR_nothing)
6189 /* Builtin not supported on this processor. */
6190 return 0;
6191
6192 /* If we got invalid arguments bail out before generating bad rtl. */
6193 if (arg0 == error_mark_node || arg1 == error_mark_node)
6194 return const0_rtx;
6195
6196 if (target == 0
6197 || GET_MODE (target) != tmode
6198 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6199 target = gen_reg_rtx (tmode);
6200
f676971a 6201 op1 = copy_to_mode_reg (mode1, op1);
b4a62fa0
SB		 6202
6203 if (op0 == const0_rtx)
6204 {
6205 addr = gen_rtx_MEM (tmode, op1);
6206 }
6207 else
6208 {
6209 op0 = copy_to_mode_reg (mode0, op0);
6210 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6211 }
6212
6213 pat = GEN_FCN (icode) (target, addr);
6214
6215 if (! pat)
6216 return 0;
6217 emit_insn (pat);
6218
6219 return target;
6220}
6221
61bea3b0
AH		 6222static rtx
6223spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6224{
6225 tree arg0 = TREE_VALUE (arglist);
6226 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6227 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6228 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6229 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6230 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6231 rtx pat;
6232 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6233 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6234 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6235
6236 /* Invalid arguments. Bail before doing anything stoopid! */
6237 if (arg0 == error_mark_node
6238 || arg1 == error_mark_node
6239 || arg2 == error_mark_node)
6240 return const0_rtx;
6241
6242 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6243 op0 = copy_to_mode_reg (mode2, op0);
6244 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6245 op1 = copy_to_mode_reg (mode0, op1);
6246 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6247 op2 = copy_to_mode_reg (mode1, op2);
6248
6249 pat = GEN_FCN (icode) (op1, op2, op0);
6250 if (pat)
6251 emit_insn (pat);
6252 return NULL_RTX;
6253}
6254
6525c0e7 6255static rtx
a2369ed3 6256altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6525c0e7
AH		 6257{
6258 tree arg0 = TREE_VALUE (arglist);
6259 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6260 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6261 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6262 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6263 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
b4a62fa0
SB		 6264 rtx pat, addr;
6265 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6266 enum machine_mode mode1 = Pmode;
6267 enum machine_mode mode2 = Pmode;
6525c0e7
AH		 6268
6269 /* Invalid arguments. Bail before doing anything stoopid! */
6270 if (arg0 == error_mark_node
6271 || arg1 == error_mark_node
6272 || arg2 == error_mark_node)
9a171fcd 6273 return const0_rtx;
6525c0e7 6274
b4a62fa0
SB		 6275 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6276 op0 = copy_to_mode_reg (tmode, op0);
6277
f676971a 6278 op2 = copy_to_mode_reg (mode2, op2);
b4a62fa0
SB		 6279
6280 if (op1 == const0_rtx)
6281 {
6282 addr = gen_rtx_MEM (tmode, op2);
6283 }
6284 else
6285 {
6286 op1 = copy_to_mode_reg (mode1, op1);
6287 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6288 }
6525c0e7 6289
b4a62fa0 6290 pat = GEN_FCN (icode) (addr, op0);
6525c0e7
AH		 6291 if (pat)
6292 emit_insn (pat);
6293 return NULL_RTX;
6294}
6295
2212663f 6296static rtx
a2369ed3 6297rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 6298{
6299 rtx pat;
6300 tree arg0 = TREE_VALUE (arglist);
6301 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6302 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6303 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6304 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6305 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6306 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6307 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6308 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6309 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
0ac081f6 6310
774b5662
DE		 6311 if (icode == CODE_FOR_nothing)
6312 /* Builtin not supported on this processor. */
6313 return 0;
6314
20e26713
AH		 6315 /* If we got invalid arguments bail out before generating bad rtl. */
6316 if (arg0 == error_mark_node
6317 || arg1 == error_mark_node
6318 || arg2 == error_mark_node)
9a171fcd 6319 return const0_rtx;
20e26713 6320
aba5fb01
NS		 6321 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6322 || icode == CODE_FOR_altivec_vsldoi_v4si
6323 || icode == CODE_FOR_altivec_vsldoi_v8hi
6324 || icode == CODE_FOR_altivec_vsldoi_v16qi)
b44140e7
AH		 6325 {
6326 /* Only allow 4-bit unsigned literals. */
8bb418a3 6327 STRIP_NOPS (arg2);
b44140e7
AH		 6328 if (TREE_CODE (arg2) != INTEGER_CST
6329 || TREE_INT_CST_LOW (arg2) & ~0xf)
6330 {
6331 error ("argument 3 must be a 4-bit unsigned literal");
e3277ffb 6332 return const0_rtx;
b44140e7 6333 }
b44140e7
AH		 6334 }
6335
c62f2db5 6336 if (target == 0
2212663f
DB		 6337 || GET_MODE (target) != tmode
6338 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6339 target = gen_reg_rtx (tmode);
6340
6341 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6342 op0 = copy_to_mode_reg (mode0, op0);
6343 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6344 op1 = copy_to_mode_reg (mode1, op1);
6345 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6346 op2 = copy_to_mode_reg (mode2, op2);
6347
6348 pat = GEN_FCN (icode) (target, op0, op1, op2);
6349 if (! pat)
6350 return 0;
6351 emit_insn (pat);
6352
6353 return target;
6354}
92898235 6355
3a9b8c7e 6356/* Expand the lvx builtins. */
0ac081f6 6357static rtx
a2369ed3 6358altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
0ac081f6 6359{
0ac081f6
AH		 6360 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6361 tree arglist = TREE_OPERAND (exp, 1);
0ac081f6 6362 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3a9b8c7e
AH		 6363 tree arg0;
6364 enum machine_mode tmode, mode0;
7c3abc73 6365 rtx pat, op0;
3a9b8c7e 6366 enum insn_code icode;
92898235 6367
0ac081f6
AH		 6368 switch (fcode)
6369 {
f18c054f 6370 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
81466555 6371 icode = CODE_FOR_altivec_lvx_v16qi;
3a9b8c7e 6372 break;
f18c054f 6373 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
81466555 6374 icode = CODE_FOR_altivec_lvx_v8hi;
3a9b8c7e
AH		 6375 break;
6376 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
81466555 6377 icode = CODE_FOR_altivec_lvx_v4si;
3a9b8c7e
AH		 6378 break;
6379 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
81466555 6380 icode = CODE_FOR_altivec_lvx_v4sf;
3a9b8c7e
AH		 6381 break;
6382 default:
6383 *expandedp = false;
6384 return NULL_RTX;
6385 }
0ac081f6 6386
3a9b8c7e 6387 *expandedp = true;
f18c054f 6388
3a9b8c7e
AH		 6389 arg0 = TREE_VALUE (arglist);
6390 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6391 tmode = insn_data[icode].operand[0].mode;
6392 mode0 = insn_data[icode].operand[1].mode;
f18c054f 6393
3a9b8c7e
AH		 6394 if (target == 0
6395 || GET_MODE (target) != tmode
6396 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6397 target = gen_reg_rtx (tmode);
24408032 6398
3a9b8c7e
AH		 6399 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6400 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
f18c054f 6401
3a9b8c7e
AH		 6402 pat = GEN_FCN (icode) (target, op0);
6403 if (! pat)
6404 return 0;
6405 emit_insn (pat);
6406 return target;
6407}
f18c054f 6408
3a9b8c7e
AH		 6409/* Expand the stvx builtins. */
6410static rtx
f676971a 6411altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6412 bool *expandedp)
3a9b8c7e
AH		 6413{
6414 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6415 tree arglist = TREE_OPERAND (exp, 1);
6416 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6417 tree arg0, arg1;
6418 enum machine_mode mode0, mode1;
7c3abc73 6419 rtx pat, op0, op1;
3a9b8c7e 6420 enum insn_code icode;
f18c054f 6421
3a9b8c7e
AH		 6422 switch (fcode)
6423 {
6424 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
81466555 6425 icode = CODE_FOR_altivec_stvx_v16qi;
3a9b8c7e
AH		 6426 break;
6427 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
81466555 6428 icode = CODE_FOR_altivec_stvx_v8hi;
3a9b8c7e
AH		 6429 break;
6430 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
81466555 6431 icode = CODE_FOR_altivec_stvx_v4si;
3a9b8c7e
AH		 6432 break;
6433 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
81466555 6434 icode = CODE_FOR_altivec_stvx_v4sf;
3a9b8c7e
AH		 6435 break;
6436 default:
6437 *expandedp = false;
6438 return NULL_RTX;
6439 }
24408032 6440
3a9b8c7e
AH		 6441 arg0 = TREE_VALUE (arglist);
6442 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6443 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6444 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6445 mode0 = insn_data[icode].operand[0].mode;
6446 mode1 = insn_data[icode].operand[1].mode;
f18c054f 6447
3a9b8c7e
AH		 6448 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6449 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6450 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6451 op1 = copy_to_mode_reg (mode1, op1);
f18c054f 6452
3a9b8c7e
AH		 6453 pat = GEN_FCN (icode) (op0, op1);
6454 if (pat)
6455 emit_insn (pat);
f18c054f 6456
3a9b8c7e
AH		 6457 *expandedp = true;
6458 return NULL_RTX;
6459}
f18c054f 6460
3a9b8c7e
AH		 6461/* Expand the dst builtins. */
6462static rtx
f676971a 6463altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6464 bool *expandedp)
3a9b8c7e
AH		 6465{
6466 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6467 tree arglist = TREE_OPERAND (exp, 1);
6468 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6469 tree arg0, arg1, arg2;
6470 enum machine_mode mode0, mode1, mode2;
7c3abc73 6471 rtx pat, op0, op1, op2;
3a9b8c7e 6472 struct builtin_description *d;
a3170dc6 6473 size_t i;
f18c054f 6474
3a9b8c7e 6475 *expandedp = false;
f18c054f 6476
3a9b8c7e
AH		 6477 /* Handle DST variants. */
6478 d = (struct builtin_description *) bdesc_dst;
6479 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6480 if (d->code == fcode)
6481 {
6482 arg0 = TREE_VALUE (arglist);
6483 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6484 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6485 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6486 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6487 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6488 mode0 = insn_data[d->icode].operand[0].mode;
6489 mode1 = insn_data[d->icode].operand[1].mode;
6490 mode2 = insn_data[d->icode].operand[2].mode;
24408032 6491
3a9b8c7e
AH		 6492 /* Invalid arguments, bail out before generating bad rtl. */
6493 if (arg0 == error_mark_node
6494 || arg1 == error_mark_node
6495 || arg2 == error_mark_node)
6496 return const0_rtx;
f18c054f 6497
86e7df90 6498 *expandedp = true;
8bb418a3 6499 STRIP_NOPS (arg2);
3a9b8c7e
AH		 6500 if (TREE_CODE (arg2) != INTEGER_CST
6501 || TREE_INT_CST_LOW (arg2) & ~0x3)
6502 {
9e637a26 6503 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
3a9b8c7e
AH		 6504 return const0_rtx;
6505 }
f18c054f 6506
3a9b8c7e 6507 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
666158b9 6508 op0 = copy_to_mode_reg (Pmode, op0);
3a9b8c7e
AH		 6509 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6510 op1 = copy_to_mode_reg (mode1, op1);
24408032 6511
3a9b8c7e
AH		 6512 pat = GEN_FCN (d->icode) (op0, op1, op2);
6513 if (pat != 0)
6514 emit_insn (pat);
f18c054f 6515
3a9b8c7e
AH		 6516 return NULL_RTX;
6517 }
f18c054f 6518
3a9b8c7e
AH		 6519 return NULL_RTX;
6520}
24408032 6521
3a9b8c7e
AH		 6522/* Expand the builtin in EXP and store the result in TARGET. Store
6523 true in *EXPANDEDP if we found a builtin to expand. */
6524static rtx
a2369ed3 6525altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
3a9b8c7e
AH		 6526{
6527 struct builtin_description *d;
6528 struct builtin_description_predicates *dp;
6529 size_t i;
6530 enum insn_code icode;
6531 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6532 tree arglist = TREE_OPERAND (exp, 1);
7c3abc73
AH		 6533 tree arg0;
6534 rtx op0, pat;
6535 enum machine_mode tmode, mode0;
3a9b8c7e 6536 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
0ac081f6 6537
3a9b8c7e
AH		 6538 target = altivec_expand_ld_builtin (exp, target, expandedp);
6539 if (*expandedp)
6540 return target;
0ac081f6 6541
3a9b8c7e
AH		 6542 target = altivec_expand_st_builtin (exp, target, expandedp);
6543 if (*expandedp)
6544 return target;
6545
6546 target = altivec_expand_dst_builtin (exp, target, expandedp);
6547 if (*expandedp)
6548 return target;
6549
6550 *expandedp = true;
95385cbb 6551
3a9b8c7e
AH		 6552 switch (fcode)
6553 {
6525c0e7
AH		 6554 case ALTIVEC_BUILTIN_STVX:
6555 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6556 case ALTIVEC_BUILTIN_STVEBX:
6557 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6558 case ALTIVEC_BUILTIN_STVEHX:
6559 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6560 case ALTIVEC_BUILTIN_STVEWX:
6561 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6562 case ALTIVEC_BUILTIN_STVXL:
6563 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
3a9b8c7e 6564
95385cbb
AH		 6565 case ALTIVEC_BUILTIN_MFVSCR:
6566 icode = CODE_FOR_altivec_mfvscr;
6567 tmode = insn_data[icode].operand[0].mode;
6568
6569 if (target == 0
6570 || GET_MODE (target) != tmode
6571 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6572 target = gen_reg_rtx (tmode);
f676971a 6573
95385cbb 6574 pat = GEN_FCN (icode) (target);
0ac081f6
AH		 6575 if (! pat)
6576 return 0;
6577 emit_insn (pat);
95385cbb
AH		 6578 return target;
6579
6580 case ALTIVEC_BUILTIN_MTVSCR:
6581 icode = CODE_FOR_altivec_mtvscr;
6582 arg0 = TREE_VALUE (arglist);
6583 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6584 mode0 = insn_data[icode].operand[0].mode;
6585
6586 /* If we got invalid arguments bail out before generating bad rtl. */
6587 if (arg0 == error_mark_node)
9a171fcd 6588 return const0_rtx;
95385cbb
AH		 6589
6590 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6591 op0 = copy_to_mode_reg (mode0, op0);
6592
6593 pat = GEN_FCN (icode) (op0);
6594 if (pat)
6595 emit_insn (pat);
6596 return NULL_RTX;
3a9b8c7e 6597
95385cbb
AH		 6598 case ALTIVEC_BUILTIN_DSSALL:
6599 emit_insn (gen_altivec_dssall ());
6600 return NULL_RTX;
6601
6602 case ALTIVEC_BUILTIN_DSS:
6603 icode = CODE_FOR_altivec_dss;
6604 arg0 = TREE_VALUE (arglist);
8bb418a3 6605 STRIP_NOPS (arg0);
95385cbb
AH		 6606 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6607 mode0 = insn_data[icode].operand[0].mode;
6608
6609 /* If we got invalid arguments bail out before generating bad rtl. */
6610 if (arg0 == error_mark_node)
9a171fcd 6611 return const0_rtx;
95385cbb 6612
b44140e7
AH		 6613 if (TREE_CODE (arg0) != INTEGER_CST
6614 || TREE_INT_CST_LOW (arg0) & ~0x3)
6615 {
6616 error ("argument to dss must be a 2-bit unsigned literal");
9a171fcd 6617 return const0_rtx;
b44140e7
AH		 6618 }
6619
95385cbb
AH		 6620 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6621 op0 = copy_to_mode_reg (mode0, op0);
6622
6623 emit_insn (gen_altivec_dss (op0));
0ac081f6 6624 return NULL_RTX;
f676971a 6625
8bb418a3
ZL		 6626 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6627 arg0 = TREE_VALUE (arglist);
97dc04b3 6628 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
c4ad648e 6629 || TREE_CODE (arg0) == ARRAY_REF)
8bb418a3 6630 arg0 = TREE_OPERAND (arg0, 0);
9e637a26 6631 error ("invalid parameter combination for %qs AltiVec intrinsic",
8bb418a3
ZL		 6632 TREE_STRING_POINTER (arg0));
6633
6634 return const0_rtx;
0ac081f6 6635 }
24408032 6636
100c4561
AH		 6637 /* Expand abs* operations. */
6638 d = (struct builtin_description *) bdesc_abs;
ca7558fc 6639 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
100c4561
AH		 6640 if (d->code == fcode)
6641 return altivec_expand_abs_builtin (d->icode, arglist, target);
6642
ae4b4a02
AH		 6643 /* Expand the AltiVec predicates. */
6644 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
ca7558fc 6645 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
ae4b4a02 6646 if (dp->code == fcode)
c4ad648e
AM		 6647 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6648 arglist, target);
ae4b4a02 6649
6525c0e7
AH		 6650 /* LV* are funky. We initialized them differently. */
6651 switch (fcode)
6652 {
6653 case ALTIVEC_BUILTIN_LVSL:
b4a62fa0 6654 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
c4ad648e 6655 arglist, target);
6525c0e7 6656 case ALTIVEC_BUILTIN_LVSR:
b4a62fa0 6657 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
c4ad648e 6658 arglist, target);
6525c0e7 6659 case ALTIVEC_BUILTIN_LVEBX:
b4a62fa0 6660 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
c4ad648e 6661 arglist, target);
6525c0e7 6662 case ALTIVEC_BUILTIN_LVEHX:
b4a62fa0 6663 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
c4ad648e 6664 arglist, target);
6525c0e7 6665 case ALTIVEC_BUILTIN_LVEWX:
b4a62fa0 6666 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
c4ad648e 6667 arglist, target);
6525c0e7 6668 case ALTIVEC_BUILTIN_LVXL:
b4a62fa0 6669 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
c4ad648e 6670 arglist, target);
6525c0e7 6671 case ALTIVEC_BUILTIN_LVX:
b4a62fa0 6672 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
c4ad648e 6673 arglist, target);
6525c0e7
AH		 6674 default:
6675 break;
6676 /* Fall through. */
6677 }
95385cbb 6678
92898235 6679 *expandedp = false;
0ac081f6
AH		 6680 return NULL_RTX;
6681}
6682
a3170dc6
AH		 6683/* Binops that need to be initialized manually, but can be expanded
6684 automagically by rs6000_expand_binop_builtin. */
6685static struct builtin_description bdesc_2arg_spe[] =
6686{
6687 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6688 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6689 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6690 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6691 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6692 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6693 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6694 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6695 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6696 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6697 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6698 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6699 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6700 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6701 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6702 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6703 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6704 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6705 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6706 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6707 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6708 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6709};
6710
6711/* Expand the builtin in EXP and store the result in TARGET. Store
6712 true in *EXPANDEDP if we found a builtin to expand.
6713
6714 This expands the SPE builtins that are not simple unary and binary
6715 operations. */
6716static rtx
a2369ed3 6717spe_expand_builtin (tree exp, rtx target, bool *expandedp)
a3170dc6
AH		 6718{
6719 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6720 tree arglist = TREE_OPERAND (exp, 1);
6721 tree arg1, arg0;
6722 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6723 enum insn_code icode;
6724 enum machine_mode tmode, mode0;
6725 rtx pat, op0;
6726 struct builtin_description *d;
6727 size_t i;
6728
6729 *expandedp = true;
6730
6731 /* Syntax check for a 5-bit unsigned immediate. */
6732 switch (fcode)
6733 {
6734 case SPE_BUILTIN_EVSTDD:
6735 case SPE_BUILTIN_EVSTDH:
6736 case SPE_BUILTIN_EVSTDW:
6737 case SPE_BUILTIN_EVSTWHE:
6738 case SPE_BUILTIN_EVSTWHO:
6739 case SPE_BUILTIN_EVSTWWE:
6740 case SPE_BUILTIN_EVSTWWO:
6741 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6742 if (TREE_CODE (arg1) != INTEGER_CST
6743 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6744 {
6745 error ("argument 2 must be a 5-bit unsigned literal");
6746 return const0_rtx;
6747 }
6748 break;
6749 default:
6750 break;
6751 }
6752
00332c9f
AH		 6753 /* The evsplat*i instructions are not quite generic. */
6754 switch (fcode)
6755 {
6756 case SPE_BUILTIN_EVSPLATFI:
6757 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6758 arglist, target);
6759 case SPE_BUILTIN_EVSPLATI:
6760 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6761 arglist, target);
6762 default:
6763 break;
6764 }
6765
a3170dc6
AH		 6766 d = (struct builtin_description *) bdesc_2arg_spe;
6767 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6768 if (d->code == fcode)
6769 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6770
6771 d = (struct builtin_description *) bdesc_spe_predicates;
6772 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6773 if (d->code == fcode)
6774 return spe_expand_predicate_builtin (d->icode, arglist, target);
6775
6776 d = (struct builtin_description *) bdesc_spe_evsel;
6777 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6778 if (d->code == fcode)
6779 return spe_expand_evsel_builtin (d->icode, arglist, target);
6780
6781 switch (fcode)
6782 {
6783 case SPE_BUILTIN_EVSTDDX:
61bea3b0 6784 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
a3170dc6 6785 case SPE_BUILTIN_EVSTDHX:
61bea3b0 6786 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
a3170dc6 6787 case SPE_BUILTIN_EVSTDWX:
61bea3b0 6788 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
a3170dc6 6789 case SPE_BUILTIN_EVSTWHEX:
61bea3b0 6790 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
a3170dc6 6791 case SPE_BUILTIN_EVSTWHOX:
61bea3b0 6792 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
a3170dc6 6793 case SPE_BUILTIN_EVSTWWEX:
61bea3b0 6794 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
a3170dc6 6795 case SPE_BUILTIN_EVSTWWOX:
61bea3b0 6796 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
a3170dc6 6797 case SPE_BUILTIN_EVSTDD:
61bea3b0 6798 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
a3170dc6 6799 case SPE_BUILTIN_EVSTDH:
61bea3b0 6800 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
a3170dc6 6801 case SPE_BUILTIN_EVSTDW:
61bea3b0 6802 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
a3170dc6 6803 case SPE_BUILTIN_EVSTWHE:
61bea3b0 6804 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
a3170dc6 6805 case SPE_BUILTIN_EVSTWHO:
61bea3b0 6806 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
a3170dc6 6807 case SPE_BUILTIN_EVSTWWE:
61bea3b0 6808 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
a3170dc6 6809 case SPE_BUILTIN_EVSTWWO:
61bea3b0 6810 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
a3170dc6
AH		 6811 case SPE_BUILTIN_MFSPEFSCR:
6812 icode = CODE_FOR_spe_mfspefscr;
6813 tmode = insn_data[icode].operand[0].mode;
6814
6815 if (target == 0
6816 || GET_MODE (target) != tmode
6817 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6818 target = gen_reg_rtx (tmode);
f676971a 6819
a3170dc6
AH		 6820 pat = GEN_FCN (icode) (target);
6821 if (! pat)
6822 return 0;
6823 emit_insn (pat);
6824 return target;
6825 case SPE_BUILTIN_MTSPEFSCR:
6826 icode = CODE_FOR_spe_mtspefscr;
6827 arg0 = TREE_VALUE (arglist);
6828 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6829 mode0 = insn_data[icode].operand[0].mode;
6830
6831 if (arg0 == error_mark_node)
6832 return const0_rtx;
6833
6834 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6835 op0 = copy_to_mode_reg (mode0, op0);
6836
6837 pat = GEN_FCN (icode) (op0);
6838 if (pat)
6839 emit_insn (pat);
6840 return NULL_RTX;
6841 default:
6842 break;
6843 }
6844
6845 *expandedp = false;
6846 return NULL_RTX;
6847}
6848
6849static rtx
a2369ed3 6850spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 6851{
6852 rtx pat, scratch, tmp;
6853 tree form = TREE_VALUE (arglist);
6854 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6855 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6856 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6857 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6858 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6859 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6860 int form_int;
6861 enum rtx_code code;
6862
6863 if (TREE_CODE (form) != INTEGER_CST)
6864 {
6865 error ("argument 1 of __builtin_spe_predicate must be a constant");
6866 return const0_rtx;
6867 }
6868 else
6869 form_int = TREE_INT_CST_LOW (form);
6870
6871 if (mode0 != mode1)
6872 abort ();
6873
6874 if (arg0 == error_mark_node || arg1 == error_mark_node)
6875 return const0_rtx;
6876
6877 if (target == 0
6878 || GET_MODE (target) != SImode
6879 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6880 target = gen_reg_rtx (SImode);
6881
6882 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6883 op0 = copy_to_mode_reg (mode0, op0);
6884 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6885 op1 = copy_to_mode_reg (mode1, op1);
6886
6887 scratch = gen_reg_rtx (CCmode);
6888
6889 pat = GEN_FCN (icode) (scratch, op0, op1);
6890 if (! pat)
6891 return const0_rtx;
6892 emit_insn (pat);
6893
6894 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6895 _lower_. We use one compare, but look in different bits of the
6896 CR for each variant.
6897
6898 There are 2 elements in each SPE simd type (upper/lower). The CR
6899 bits are set as follows:
6900
6901 BIT0 | BIT 1 | BIT 2 | BIT 3
6902 U | L | (U | L) | (U & L)
6903
6904 So, for an "all" relationship, BIT 3 would be set.
6905 For an "any" relationship, BIT 2 would be set. Etc.
6906
6907 Following traditional nomenclature, these bits map to:
6908
6909 BIT0 | BIT 1 | BIT 2 | BIT 3
6910 LT | GT | EQ | OV
6911
6912 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6913 */
6914
6915 switch (form_int)
6916 {
6917 /* All variant. OV bit. */
6918 case 0:
6919 /* We need to get to the OV bit, which is the ORDERED bit. We
6920 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6921 that's ugly and will trigger a validate_condition_mode abort.
6922 So let's just use another pattern. */
6923 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6924 return target;
6925 /* Any variant. EQ bit. */
6926 case 1:
6927 code = EQ;
6928 break;
6929 /* Upper variant. LT bit. */
6930 case 2:
6931 code = LT;
6932 break;
6933 /* Lower variant. GT bit. */
6934 case 3:
6935 code = GT;
6936 break;
6937 default:
6938 error ("argument 1 of __builtin_spe_predicate is out of range");
6939 return const0_rtx;
6940 }
6941
6942 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6943 emit_move_insn (target, tmp);
6944
6945 return target;
6946}
6947
6948/* The evsel builtins look like this:
6949
6950 e = __builtin_spe_evsel_OP (a, b, c, d);
6951
6952 and work like this:
6953
6954 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6955 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6956*/
6957
6958static rtx
a2369ed3 6959spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 6960{
6961 rtx pat, scratch;
6962 tree arg0 = TREE_VALUE (arglist);
6963 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6964 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6965 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6966 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6967 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6968 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6969 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6970 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6971 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6972
6973 if (mode0 != mode1)
6974 abort ();
6975
6976 if (arg0 == error_mark_node || arg1 == error_mark_node
6977 || arg2 == error_mark_node || arg3 == error_mark_node)
6978 return const0_rtx;
6979
6980 if (target == 0
6981 || GET_MODE (target) != mode0
6982 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6983 target = gen_reg_rtx (mode0);
6984
6985 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6986 op0 = copy_to_mode_reg (mode0, op0);
6987 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6988 op1 = copy_to_mode_reg (mode0, op1);
6989 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6990 op2 = copy_to_mode_reg (mode0, op2);
6991 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6992 op3 = copy_to_mode_reg (mode0, op3);
6993
6994 /* Generate the compare. */
6995 scratch = gen_reg_rtx (CCmode);
6996 pat = GEN_FCN (icode) (scratch, op0, op1);
6997 if (! pat)
6998 return const0_rtx;
6999 emit_insn (pat);
7000
7001 if (mode0 == V2SImode)
7002 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7003 else
7004 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7005
7006 return target;
7007}
7008
0ac081f6
AH		 7009/* Expand an expression EXP that calls a built-in function,
7010 with result going to TARGET if that's convenient
7011 (and in mode MODE if that's convenient).
7012 SUBTARGET may be used as the target for computing one of EXP's operands.
7013 IGNORE is nonzero if the value is to be ignored. */
7014
7015static rtx
a2369ed3 7016rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
c4ad648e
AM		 7017 enum machine_mode mode ATTRIBUTE_UNUSED,
7018 int ignore ATTRIBUTE_UNUSED)
0ac081f6 7019{
92898235
AH		 7020 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7021 tree arglist = TREE_OPERAND (exp, 1);
7022 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7023 struct builtin_description *d;
7024 size_t i;
7025 rtx ret;
7026 bool success;
f676971a 7027
7ccf35ed
DN		 7028 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7029 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7030 {
7031 int icode = (int) CODE_FOR_altivec_lvsr;
7032 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7033 enum machine_mode mode = insn_data[icode].operand[1].mode;
7034 tree arg;
7035 rtx op, addr, pat;
7036
7037 if (!TARGET_ALTIVEC)
7038 abort ();
7039
7040 arg = TREE_VALUE (arglist);
7041 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7042 abort ();
7043 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7044 addr = memory_address (mode, op);
7045 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7046 op = addr;
7047 else
7048 {
7049 /* For the load case need to negate the address. */
7050 op = gen_reg_rtx (GET_MODE (addr));
7051 emit_insn (gen_rtx_SET (VOIDmode, op,
7052 gen_rtx_NEG (GET_MODE (addr), addr)));
c4ad648e 7053 }
7ccf35ed
DN		 7054 op = gen_rtx_MEM (mode, op);
7055
7056 if (target == 0
7057 || GET_MODE (target) != tmode
7058 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7059 target = gen_reg_rtx (tmode);
7060
7061 /*pat = gen_altivec_lvsr (target, op);*/
7062 pat = GEN_FCN (icode) (target, op);
7063 if (!pat)
7064 return 0;
7065 emit_insn (pat);
7066
7067 return target;
7068 }
7069
0ac081f6 7070 if (TARGET_ALTIVEC)
92898235
AH		 7071 {
7072 ret = altivec_expand_builtin (exp, target, &success);
7073
a3170dc6
AH		 7074 if (success)
7075 return ret;
7076 }
7077 if (TARGET_SPE)
7078 {
7079 ret = spe_expand_builtin (exp, target, &success);
7080
92898235
AH		 7081 if (success)
7082 return ret;
7083 }
7084
0559cc77
DE		 7085 if (TARGET_ALTIVEC || TARGET_SPE)
7086 {
7087 /* Handle simple unary operations. */
7088 d = (struct builtin_description *) bdesc_1arg;
7089 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7090 if (d->code == fcode)
7091 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7092
7093 /* Handle simple binary operations. */
7094 d = (struct builtin_description *) bdesc_2arg;
7095 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7096 if (d->code == fcode)
7097 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7098
7099 /* Handle simple ternary operations. */
7100 d = (struct builtin_description *) bdesc_3arg;
7101 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7102 if (d->code == fcode)
7103 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7104 }
0ac081f6
AH		 7105
7106 abort ();
92898235 7107 return NULL_RTX;
0ac081f6
AH		 7108}
7109
7c62e993
PB		 7110static tree
7111build_opaque_vector_type (tree node, int nunits)
7112{
7113 node = copy_node (node);
7114 TYPE_MAIN_VARIANT (node) = node;
7115 return build_vector_type (node, nunits);
7116}
7117
0ac081f6 7118static void
863d938c 7119rs6000_init_builtins (void)
0ac081f6 7120{
4a5eab38
PB		 7121 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7122 V2SF_type_node = build_vector_type (float_type_node, 2);
7123 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7124 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7125 V4SF_type_node = build_vector_type (float_type_node, 4);
7e463bda 7126 V8HI_type_node = build_vector_type (intHI_type_node, 8);
4a5eab38
PB		 7127 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7128
7129 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7130 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7131 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7132
7c62e993
PB		 7133 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7134 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
6035d635 7135 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
3fdaa45a 7136
8bb418a3
ZL		 7137 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7138 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7139 'vector unsigned short'. */
7140
8dd16ecc
NS		 7141 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7142 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7143 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7144 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8bb418a3
ZL		 7145
7146 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7147 get_identifier ("__bool char"),
7148 bool_char_type_node));
7149 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7150 get_identifier ("__bool short"),
7151 bool_short_type_node));
7152 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7153 get_identifier ("__bool int"),
7154 bool_int_type_node));
7155 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7156 get_identifier ("__pixel"),
7157 pixel_type_node));
7158
4a5eab38
PB		 7159 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7160 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7161 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7162 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8bb418a3
ZL		 7163
7164 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7165 get_identifier ("__vector unsigned char"),
7166 unsigned_V16QI_type_node));
7167 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7168 get_identifier ("__vector signed char"),
7169 V16QI_type_node));
7170 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7171 get_identifier ("__vector __bool char"),
7172 bool_V16QI_type_node));
7173
7174 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7175 get_identifier ("__vector unsigned short"),
7176 unsigned_V8HI_type_node));
7177 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7178 get_identifier ("__vector signed short"),
7179 V8HI_type_node));
7180 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7181 get_identifier ("__vector __bool short"),
7182 bool_V8HI_type_node));
7183
7184 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7185 get_identifier ("__vector unsigned int"),
7186 unsigned_V4SI_type_node));
7187 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7188 get_identifier ("__vector signed int"),
7189 V4SI_type_node));
7190 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7191 get_identifier ("__vector __bool int"),
7192 bool_V4SI_type_node));
7193
7194 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7195 get_identifier ("__vector float"),
7196 V4SF_type_node));
7197 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7198 get_identifier ("__vector __pixel"),
7199 pixel_V8HI_type_node));
7200
a3170dc6 7201 if (TARGET_SPE)
3fdaa45a 7202 spe_init_builtins ();
0ac081f6
AH		 7203 if (TARGET_ALTIVEC)
7204 altivec_init_builtins ();
0559cc77
DE		 7205 if (TARGET_ALTIVEC || TARGET_SPE)
7206 rs6000_common_init_builtins ();
0ac081f6
AH		 7207}
7208
a3170dc6
AH		 7209/* Search through a set of builtins and enable the mask bits.
7210 DESC is an array of builtins.
b6d08ca1 7211 SIZE is the total number of builtins.
a3170dc6
AH		 7212 START is the builtin enum at which to start.
7213 END is the builtin enum at which to end. */
0ac081f6 7214static void
a2369ed3 7215enable_mask_for_builtins (struct builtin_description *desc, int size,
f676971a 7216 enum rs6000_builtins start,
a2369ed3 7217 enum rs6000_builtins end)
a3170dc6
AH		 7218{
7219 int i;
7220
7221 for (i = 0; i < size; ++i)
7222 if (desc[i].code == start)
7223 break;
7224
7225 if (i == size)
7226 return;
7227
7228 for (; i < size; ++i)
7229 {
7230 /* Flip all the bits on. */
7231 desc[i].mask = target_flags;
7232 if (desc[i].code == end)
7233 break;
7234 }
7235}
7236
7237static void
863d938c 7238spe_init_builtins (void)
0ac081f6 7239{
a3170dc6
AH		 7240 tree endlink = void_list_node;
7241 tree puint_type_node = build_pointer_type (unsigned_type_node);
7242 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
ae4b4a02 7243 struct builtin_description *d;
0ac081f6
AH		 7244 size_t i;
7245
a3170dc6
AH		 7246 tree v2si_ftype_4_v2si
7247 = build_function_type
3fdaa45a
AH		 7248 (opaque_V2SI_type_node,
7249 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7250 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7251 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7252 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7253 endlink)))));
7254
7255 tree v2sf_ftype_4_v2sf
7256 = build_function_type
3fdaa45a
AH		 7257 (opaque_V2SF_type_node,
7258 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7259 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7260 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7261 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7262 endlink)))));
7263
7264 tree int_ftype_int_v2si_v2si
7265 = build_function_type
7266 (integer_type_node,
7267 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7268 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7269 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7270 endlink))));
7271
7272 tree int_ftype_int_v2sf_v2sf
7273 = build_function_type
7274 (integer_type_node,
7275 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7276 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7277 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7278 endlink))));
7279
7280 tree void_ftype_v2si_puint_int
7281 = build_function_type (void_type_node,
3fdaa45a 7282 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7283 tree_cons (NULL_TREE, puint_type_node,
7284 tree_cons (NULL_TREE,
7285 integer_type_node,
7286 endlink))));
7287
7288 tree void_ftype_v2si_puint_char
7289 = build_function_type (void_type_node,
3fdaa45a 7290 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7291 tree_cons (NULL_TREE, puint_type_node,
7292 tree_cons (NULL_TREE,
7293 char_type_node,
7294 endlink))));
7295
7296 tree void_ftype_v2si_pv2si_int
7297 = build_function_type (void_type_node,
3fdaa45a 7298 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7299 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7300 tree_cons (NULL_TREE,
7301 integer_type_node,
7302 endlink))));
7303
7304 tree void_ftype_v2si_pv2si_char
7305 = build_function_type (void_type_node,
3fdaa45a 7306 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7307 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7308 tree_cons (NULL_TREE,
7309 char_type_node,
7310 endlink))));
7311
7312 tree void_ftype_int
7313 = build_function_type (void_type_node,
7314 tree_cons (NULL_TREE, integer_type_node, endlink));
7315
7316 tree int_ftype_void
36e8d515 7317 = build_function_type (integer_type_node, endlink);
a3170dc6
AH		 7318
7319 tree v2si_ftype_pv2si_int
3fdaa45a 7320 = build_function_type (opaque_V2SI_type_node,
6035d635 7321 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7322 tree_cons (NULL_TREE, integer_type_node,
7323 endlink)));
7324
7325 tree v2si_ftype_puint_int
3fdaa45a 7326 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7327 tree_cons (NULL_TREE, puint_type_node,
7328 tree_cons (NULL_TREE, integer_type_node,
7329 endlink)));
7330
7331 tree v2si_ftype_pushort_int
3fdaa45a 7332 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7333 tree_cons (NULL_TREE, pushort_type_node,
7334 tree_cons (NULL_TREE, integer_type_node,
7335 endlink)));
7336
00332c9f
AH		 7337 tree v2si_ftype_signed_char
7338 = build_function_type (opaque_V2SI_type_node,
7339 tree_cons (NULL_TREE, signed_char_type_node,
7340 endlink));
7341
a3170dc6
AH		 7342 /* The initialization of the simple binary and unary builtins is
7343 done in rs6000_common_init_builtins, but we have to enable the
7344 mask bits here manually because we have run out of `target_flags'
7345 bits. We really need to redesign this mask business. */
7346
7347 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7348 ARRAY_SIZE (bdesc_2arg),
7349 SPE_BUILTIN_EVADDW,
7350 SPE_BUILTIN_EVXOR);
7351 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7352 ARRAY_SIZE (bdesc_1arg),
7353 SPE_BUILTIN_EVABS,
7354 SPE_BUILTIN_EVSUBFUSIAAW);
7355 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7356 ARRAY_SIZE (bdesc_spe_predicates),
7357 SPE_BUILTIN_EVCMPEQ,
7358 SPE_BUILTIN_EVFSTSTLT);
7359 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7360 ARRAY_SIZE (bdesc_spe_evsel),
7361 SPE_BUILTIN_EVSEL_CMPGTS,
7362 SPE_BUILTIN_EVSEL_FSTSTEQ);
7363
36252949
AH		 7364 (*lang_hooks.decls.pushdecl)
7365 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7366 opaque_V2SI_type_node));
7367
a3170dc6 7368 /* Initialize irregular SPE builtins. */
f676971a 7369
a3170dc6
AH		 7370 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7371 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7372 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7373 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7374 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7375 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7376 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7377 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7378 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7379 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7380 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7381 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7382 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7383 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7384 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7385 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
00332c9f
AH		 7386 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7387 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
a3170dc6
AH		 7388
7389 /* Loads. */
7390 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7391 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7392 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7393 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7394 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7395 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7396 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7397 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7398 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7399 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7400 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7401 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7402 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7403 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7404 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7405 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7406 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7407 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7408 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7409 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7410 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7411 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7412
7413 /* Predicates. */
7414 d = (struct builtin_description *) bdesc_spe_predicates;
7415 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7416 {
7417 tree type;
7418
7419 switch (insn_data[d->icode].operand[1].mode)
7420 {
7421 case V2SImode:
7422 type = int_ftype_int_v2si_v2si;
7423 break;
7424 case V2SFmode:
7425 type = int_ftype_int_v2sf_v2sf;
7426 break;
7427 default:
7428 abort ();
7429 }
7430
7431 def_builtin (d->mask, d->name, type, d->code);
7432 }
7433
7434 /* Evsel predicates. */
7435 d = (struct builtin_description *) bdesc_spe_evsel;
7436 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7437 {
7438 tree type;
7439
7440 switch (insn_data[d->icode].operand[1].mode)
7441 {
7442 case V2SImode:
7443 type = v2si_ftype_4_v2si;
7444 break;
7445 case V2SFmode:
7446 type = v2sf_ftype_4_v2sf;
7447 break;
7448 default:
7449 abort ();
7450 }
7451
7452 def_builtin (d->mask, d->name, type, d->code);
7453 }
7454}
7455
7456static void
863d938c 7457altivec_init_builtins (void)
a3170dc6
AH		 7458{
7459 struct builtin_description *d;
7460 struct builtin_description_predicates *dp;
7461 size_t i;
7462 tree pfloat_type_node = build_pointer_type (float_type_node);
7463 tree pint_type_node = build_pointer_type (integer_type_node);
7464 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7465 tree pchar_type_node = build_pointer_type (char_type_node);
7466
7467 tree pvoid_type_node = build_pointer_type (void_type_node);
7468
0dbc3651
ZW		 7469 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7470 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7471 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7472 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7473
7474 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7475
a3170dc6
AH		 7476 tree int_ftype_int_v4si_v4si
7477 = build_function_type_list (integer_type_node,
7478 integer_type_node, V4SI_type_node,
7479 V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7480 tree v4sf_ftype_pcfloat
7481 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
a3170dc6 7482 tree void_ftype_pfloat_v4sf
b4de2f7d 7483 = build_function_type_list (void_type_node,
a3170dc6 7484 pfloat_type_node, V4SF_type_node, NULL_TREE);
0dbc3651
ZW		 7485 tree v4si_ftype_pcint
7486 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7487 tree void_ftype_pint_v4si
b4de2f7d
AH		 7488 = build_function_type_list (void_type_node,
7489 pint_type_node, V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7490 tree v8hi_ftype_pcshort
7491 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
f18c054f 7492 tree void_ftype_pshort_v8hi
b4de2f7d
AH		 7493 = build_function_type_list (void_type_node,
7494 pshort_type_node, V8HI_type_node, NULL_TREE);
0dbc3651
ZW		 7495 tree v16qi_ftype_pcchar
7496 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
f18c054f 7497 tree void_ftype_pchar_v16qi
b4de2f7d
AH		 7498 = build_function_type_list (void_type_node,
7499 pchar_type_node, V16QI_type_node, NULL_TREE);
95385cbb 7500 tree void_ftype_v4si
b4de2f7d 7501 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7502 tree v8hi_ftype_void
7503 = build_function_type (V8HI_type_node, void_list_node);
7504 tree void_ftype_void
7505 = build_function_type (void_type_node, void_list_node);
e34b6648
JJ		 7506 tree void_ftype_int
7507 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
0dbc3651 7508
b4a62fa0 7509 tree v16qi_ftype_long_pcvoid
a3170dc6 7510 = build_function_type_list (V16QI_type_node,
b4a62fa0
SB		 7511 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7512 tree v8hi_ftype_long_pcvoid
a3170dc6 7513 = build_function_type_list (V8HI_type_node,
b4a62fa0
SB		 7514 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7515 tree v4si_ftype_long_pcvoid
a3170dc6 7516 = build_function_type_list (V4SI_type_node,
b4a62fa0 7517 long_integer_type_node, pcvoid_type_node, NULL_TREE);
0dbc3651 7518
b4a62fa0 7519 tree void_ftype_v4si_long_pvoid
b4de2f7d 7520 = build_function_type_list (void_type_node,
b4a62fa0 7521 V4SI_type_node, long_integer_type_node,
b4de2f7d 7522 pvoid_type_node, NULL_TREE);
b4a62fa0 7523 tree void_ftype_v16qi_long_pvoid
b4de2f7d 7524 = build_function_type_list (void_type_node,
b4a62fa0 7525 V16QI_type_node, long_integer_type_node,
b4de2f7d 7526 pvoid_type_node, NULL_TREE);
b4a62fa0 7527 tree void_ftype_v8hi_long_pvoid
b4de2f7d 7528 = build_function_type_list (void_type_node,
b4a62fa0 7529 V8HI_type_node, long_integer_type_node,
b4de2f7d 7530 pvoid_type_node, NULL_TREE);
a3170dc6
AH		 7531 tree int_ftype_int_v8hi_v8hi
7532 = build_function_type_list (integer_type_node,
7533 integer_type_node, V8HI_type_node,
7534 V8HI_type_node, NULL_TREE);
7535 tree int_ftype_int_v16qi_v16qi
7536 = build_function_type_list (integer_type_node,
7537 integer_type_node, V16QI_type_node,
7538 V16QI_type_node, NULL_TREE);
7539 tree int_ftype_int_v4sf_v4sf
7540 = build_function_type_list (integer_type_node,
7541 integer_type_node, V4SF_type_node,
7542 V4SF_type_node, NULL_TREE);
7543 tree v4si_ftype_v4si
7544 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7545 tree v8hi_ftype_v8hi
7546 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7547 tree v16qi_ftype_v16qi
7548 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7549 tree v4sf_ftype_v4sf
7550 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8bb418a3 7551 tree void_ftype_pcvoid_int_int
a3170dc6 7552 = build_function_type_list (void_type_node,
0dbc3651 7553 pcvoid_type_node, integer_type_node,
8bb418a3
ZL		 7554 integer_type_node, NULL_TREE);
7555 tree int_ftype_pcchar
7556 = build_function_type_list (integer_type_node,
7557 pcchar_type_node, NULL_TREE);
7558
0dbc3651
ZW		 7559 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7560 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7561 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7562 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7563 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7564 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7565 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7566 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7567 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7568 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7569 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7570 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7571 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7572 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7573 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7574 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
a3170dc6
AH		 7575 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7576 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7577 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
e34b6648 7578 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
b4a62fa0
SB		 7579 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7580 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7581 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7582 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7583 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7584 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7585 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7586 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7587 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7588 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7589 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7590 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
a3170dc6 7591
8bb418a3
ZL		 7592 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7593 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7594 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7595
a3170dc6
AH		 7596 /* Add the DST variants. */
7597 d = (struct builtin_description *) bdesc_dst;
7598 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8bb418a3 7599 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
a3170dc6
AH		 7600
7601 /* Initialize the predicates. */
7602 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7603 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7604 {
7605 enum machine_mode mode1;
7606 tree type;
7607
7608 mode1 = insn_data[dp->icode].operand[1].mode;
7609
7610 switch (mode1)
7611 {
7612 case V4SImode:
7613 type = int_ftype_int_v4si_v4si;
7614 break;
7615 case V8HImode:
7616 type = int_ftype_int_v8hi_v8hi;
7617 break;
7618 case V16QImode:
7619 type = int_ftype_int_v16qi_v16qi;
7620 break;
7621 case V4SFmode:
7622 type = int_ftype_int_v4sf_v4sf;
7623 break;
7624 default:
7625 abort ();
7626 }
f676971a 7627
a3170dc6
AH		 7628 def_builtin (dp->mask, dp->name, type, dp->code);
7629 }
7630
7631 /* Initialize the abs* operators. */
7632 d = (struct builtin_description *) bdesc_abs;
7633 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7634 {
7635 enum machine_mode mode0;
7636 tree type;
7637
7638 mode0 = insn_data[d->icode].operand[0].mode;
7639
7640 switch (mode0)
7641 {
7642 case V4SImode:
7643 type = v4si_ftype_v4si;
7644 break;
7645 case V8HImode:
7646 type = v8hi_ftype_v8hi;
7647 break;
7648 case V16QImode:
7649 type = v16qi_ftype_v16qi;
7650 break;
7651 case V4SFmode:
7652 type = v4sf_ftype_v4sf;
7653 break;
7654 default:
7655 abort ();
7656 }
f676971a 7657
a3170dc6
AH		 7658 def_builtin (d->mask, d->name, type, d->code);
7659 }
7ccf35ed 7660
13c62176
DN		 7661 if (TARGET_ALTIVEC)
7662 {
7663 tree decl;
7664
7665 /* Initialize target builtin that implements
7666 targetm.vectorize.builtin_mask_for_load. */
7667
7668 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8bb46326
DN		 7669 v16qi_ftype_long_pcvoid,
7670 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7671 BUILT_IN_MD, NULL,
7672 tree_cons (get_identifier ("const"),
7673 NULL_TREE, NULL_TREE));
13c62176
DN		 7674 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7675 altivec_builtin_mask_for_load = decl;
13c62176 7676 }
a3170dc6
AH		 7677}
7678
7679static void
863d938c 7680rs6000_common_init_builtins (void)
a3170dc6
AH		 7681{
7682 struct builtin_description *d;
7683 size_t i;
7684
7685 tree v4sf_ftype_v4sf_v4sf_v16qi
7686 = build_function_type_list (V4SF_type_node,
7687 V4SF_type_node, V4SF_type_node,
7688 V16QI_type_node, NULL_TREE);
7689 tree v4si_ftype_v4si_v4si_v16qi
7690 = build_function_type_list (V4SI_type_node,
7691 V4SI_type_node, V4SI_type_node,
7692 V16QI_type_node, NULL_TREE);
7693 tree v8hi_ftype_v8hi_v8hi_v16qi
7694 = build_function_type_list (V8HI_type_node,
7695 V8HI_type_node, V8HI_type_node,
7696 V16QI_type_node, NULL_TREE);
7697 tree v16qi_ftype_v16qi_v16qi_v16qi
7698 = build_function_type_list (V16QI_type_node,
7699 V16QI_type_node, V16QI_type_node,
7700 V16QI_type_node, NULL_TREE);
b9e4e5d1
ZL		 7701 tree v4si_ftype_int
7702 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7703 tree v8hi_ftype_int
7704 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7705 tree v16qi_ftype_int
7706 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
a3170dc6
AH		 7707 tree v8hi_ftype_v16qi
7708 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7709 tree v4sf_ftype_v4sf
7710 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7711
7712 tree v2si_ftype_v2si_v2si
2abe3e28
AH		 7713 = build_function_type_list (opaque_V2SI_type_node,
7714 opaque_V2SI_type_node,
7715 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7716
7717 tree v2sf_ftype_v2sf_v2sf
2abe3e28
AH		 7718 = build_function_type_list (opaque_V2SF_type_node,
7719 opaque_V2SF_type_node,
7720 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 7721
7722 tree v2si_ftype_int_int
2abe3e28 7723 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 7724 integer_type_node, integer_type_node,
7725 NULL_TREE);
7726
7727 tree v2si_ftype_v2si
2abe3e28
AH		 7728 = build_function_type_list (opaque_V2SI_type_node,
7729 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7730
7731 tree v2sf_ftype_v2sf
2abe3e28
AH		 7732 = build_function_type_list (opaque_V2SF_type_node,
7733 opaque_V2SF_type_node, NULL_TREE);
f676971a 7734
a3170dc6 7735 tree v2sf_ftype_v2si
2abe3e28
AH		 7736 = build_function_type_list (opaque_V2SF_type_node,
7737 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7738
7739 tree v2si_ftype_v2sf
2abe3e28
AH		 7740 = build_function_type_list (opaque_V2SI_type_node,
7741 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 7742
7743 tree v2si_ftype_v2si_char
2abe3e28
AH		 7744 = build_function_type_list (opaque_V2SI_type_node,
7745 opaque_V2SI_type_node,
7746 char_type_node, NULL_TREE);
a3170dc6
AH		 7747
7748 tree v2si_ftype_int_char
2abe3e28 7749 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 7750 integer_type_node, char_type_node, NULL_TREE);
7751
7752 tree v2si_ftype_char
2abe3e28
AH		 7753 = build_function_type_list (opaque_V2SI_type_node,
7754 char_type_node, NULL_TREE);
a3170dc6
AH		 7755
7756 tree int_ftype_int_int
7757 = build_function_type_list (integer_type_node,
7758 integer_type_node, integer_type_node,
7759 NULL_TREE);
95385cbb 7760
0ac081f6 7761 tree v4si_ftype_v4si_v4si
b4de2f7d
AH		 7762 = build_function_type_list (V4SI_type_node,
7763 V4SI_type_node, V4SI_type_node, NULL_TREE);
b9e4e5d1 7764 tree v4sf_ftype_v4si_int
b4de2f7d 7765 = build_function_type_list (V4SF_type_node,
b9e4e5d1
ZL		 7766 V4SI_type_node, integer_type_node, NULL_TREE);
7767 tree v4si_ftype_v4sf_int
b4de2f7d 7768 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 7769 V4SF_type_node, integer_type_node, NULL_TREE);
7770 tree v4si_ftype_v4si_int
b4de2f7d 7771 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 7772 V4SI_type_node, integer_type_node, NULL_TREE);
7773 tree v8hi_ftype_v8hi_int
b4de2f7d 7774 = build_function_type_list (V8HI_type_node,
b9e4e5d1
ZL		 7775 V8HI_type_node, integer_type_node, NULL_TREE);
7776 tree v16qi_ftype_v16qi_int
b4de2f7d 7777 = build_function_type_list (V16QI_type_node,
b9e4e5d1
ZL		 7778 V16QI_type_node, integer_type_node, NULL_TREE);
7779 tree v16qi_ftype_v16qi_v16qi_int
b4de2f7d
AH		 7780 = build_function_type_list (V16QI_type_node,
7781 V16QI_type_node, V16QI_type_node,
b9e4e5d1
ZL		 7782 integer_type_node, NULL_TREE);
7783 tree v8hi_ftype_v8hi_v8hi_int
b4de2f7d
AH		 7784 = build_function_type_list (V8HI_type_node,
7785 V8HI_type_node, V8HI_type_node,
b9e4e5d1
ZL		 7786 integer_type_node, NULL_TREE);
7787 tree v4si_ftype_v4si_v4si_int
b4de2f7d
AH		 7788 = build_function_type_list (V4SI_type_node,
7789 V4SI_type_node, V4SI_type_node,
b9e4e5d1
ZL		 7790 integer_type_node, NULL_TREE);
7791 tree v4sf_ftype_v4sf_v4sf_int
b4de2f7d
AH		 7792 = build_function_type_list (V4SF_type_node,
7793 V4SF_type_node, V4SF_type_node,
b9e4e5d1 7794 integer_type_node, NULL_TREE);
0ac081f6 7795 tree v4sf_ftype_v4sf_v4sf
b4de2f7d
AH		 7796 = build_function_type_list (V4SF_type_node,
7797 V4SF_type_node, V4SF_type_node, NULL_TREE);
617e0e1d 7798 tree v4sf_ftype_v4sf_v4sf_v4si
b4de2f7d
AH		 7799 = build_function_type_list (V4SF_type_node,
7800 V4SF_type_node, V4SF_type_node,
7801 V4SI_type_node, NULL_TREE);
2212663f 7802 tree v4sf_ftype_v4sf_v4sf_v4sf
b4de2f7d
AH		 7803 = build_function_type_list (V4SF_type_node,
7804 V4SF_type_node, V4SF_type_node,
7805 V4SF_type_node, NULL_TREE);
f676971a 7806 tree v4si_ftype_v4si_v4si_v4si
b4de2f7d
AH		 7807 = build_function_type_list (V4SI_type_node,
7808 V4SI_type_node, V4SI_type_node,
7809 V4SI_type_node, NULL_TREE);
0ac081f6 7810 tree v8hi_ftype_v8hi_v8hi
b4de2f7d
AH		 7811 = build_function_type_list (V8HI_type_node,
7812 V8HI_type_node, V8HI_type_node, NULL_TREE);
2212663f 7813 tree v8hi_ftype_v8hi_v8hi_v8hi
b4de2f7d
AH		 7814 = build_function_type_list (V8HI_type_node,
7815 V8HI_type_node, V8HI_type_node,
7816 V8HI_type_node, NULL_TREE);
c4ad648e 7817 tree v4si_ftype_v8hi_v8hi_v4si
b4de2f7d
AH		 7818 = build_function_type_list (V4SI_type_node,
7819 V8HI_type_node, V8HI_type_node,
7820 V4SI_type_node, NULL_TREE);
c4ad648e 7821 tree v4si_ftype_v16qi_v16qi_v4si
b4de2f7d
AH		 7822 = build_function_type_list (V4SI_type_node,
7823 V16QI_type_node, V16QI_type_node,
7824 V4SI_type_node, NULL_TREE);
0ac081f6 7825 tree v16qi_ftype_v16qi_v16qi
b4de2f7d
AH		 7826 = build_function_type_list (V16QI_type_node,
7827 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 7828 tree v4si_ftype_v4sf_v4sf
b4de2f7d
AH		 7829 = build_function_type_list (V4SI_type_node,
7830 V4SF_type_node, V4SF_type_node, NULL_TREE);
0ac081f6 7831 tree v8hi_ftype_v16qi_v16qi
b4de2f7d
AH		 7832 = build_function_type_list (V8HI_type_node,
7833 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 7834 tree v4si_ftype_v8hi_v8hi
b4de2f7d
AH		 7835 = build_function_type_list (V4SI_type_node,
7836 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 7837 tree v8hi_ftype_v4si_v4si
b4de2f7d
AH		 7838 = build_function_type_list (V8HI_type_node,
7839 V4SI_type_node, V4SI_type_node, NULL_TREE);
0ac081f6 7840 tree v16qi_ftype_v8hi_v8hi
b4de2f7d
AH		 7841 = build_function_type_list (V16QI_type_node,
7842 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 7843 tree v4si_ftype_v16qi_v4si
b4de2f7d
AH		 7844 = build_function_type_list (V4SI_type_node,
7845 V16QI_type_node, V4SI_type_node, NULL_TREE);
fa066a23 7846 tree v4si_ftype_v16qi_v16qi
b4de2f7d
AH		 7847 = build_function_type_list (V4SI_type_node,
7848 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 7849 tree v4si_ftype_v8hi_v4si
b4de2f7d
AH		 7850 = build_function_type_list (V4SI_type_node,
7851 V8HI_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7852 tree v4si_ftype_v8hi
7853 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7854 tree int_ftype_v4si_v4si
7855 = build_function_type_list (integer_type_node,
7856 V4SI_type_node, V4SI_type_node, NULL_TREE);
7857 tree int_ftype_v4sf_v4sf
7858 = build_function_type_list (integer_type_node,
7859 V4SF_type_node, V4SF_type_node, NULL_TREE);
7860 tree int_ftype_v16qi_v16qi
7861 = build_function_type_list (integer_type_node,
7862 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 7863 tree int_ftype_v8hi_v8hi
b4de2f7d
AH		 7864 = build_function_type_list (integer_type_node,
7865 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 7866
6f317ef3 7867 /* Add the simple ternary operators. */
2212663f 7868 d = (struct builtin_description *) bdesc_3arg;
ca7558fc 7869 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
2212663f 7870 {
f676971a 7871
2212663f
DB		 7872 enum machine_mode mode0, mode1, mode2, mode3;
7873 tree type;
7874
0559cc77 7875 if (d->name == 0 || d->icode == CODE_FOR_nothing)
2212663f 7876 continue;
f676971a 7877
2212663f
DB		 7878 mode0 = insn_data[d->icode].operand[0].mode;
7879 mode1 = insn_data[d->icode].operand[1].mode;
7880 mode2 = insn_data[d->icode].operand[2].mode;
7881 mode3 = insn_data[d->icode].operand[3].mode;
f676971a 7882
2212663f
DB		 7883 /* When all four are of the same mode. */
7884 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7885 {
7886 switch (mode0)
7887 {
617e0e1d
DB		 7888 case V4SImode:
7889 type = v4si_ftype_v4si_v4si_v4si;
7890 break;
2212663f
DB		 7891 case V4SFmode:
7892 type = v4sf_ftype_v4sf_v4sf_v4sf;
7893 break;
7894 case V8HImode:
7895 type = v8hi_ftype_v8hi_v8hi_v8hi;
f676971a 7896 break;
2212663f
DB		 7897 case V16QImode:
7898 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 7899 break;
2212663f 7900 default:
9390387d 7901 abort ();
2212663f
DB		 7902 }
7903 }
7904 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
c4ad648e 7905 {
2212663f
DB		 7906 switch (mode0)
7907 {
7908 case V4SImode:
7909 type = v4si_ftype_v4si_v4si_v16qi;
7910 break;
7911 case V4SFmode:
7912 type = v4sf_ftype_v4sf_v4sf_v16qi;
7913 break;
7914 case V8HImode:
7915 type = v8hi_ftype_v8hi_v8hi_v16qi;
f676971a 7916 break;
2212663f
DB		 7917 case V16QImode:
7918 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 7919 break;
2212663f 7920 default:
9390387d 7921 abort ();
2212663f
DB		 7922 }
7923 }
f676971a 7924 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
2212663f 7925 && mode3 == V4SImode)
24408032 7926 type = v4si_ftype_v16qi_v16qi_v4si;
f676971a 7927 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
2212663f 7928 && mode3 == V4SImode)
24408032 7929 type = v4si_ftype_v8hi_v8hi_v4si;
f676971a 7930 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
617e0e1d 7931 && mode3 == V4SImode)
24408032
AH		 7932 type = v4sf_ftype_v4sf_v4sf_v4si;
7933
7934 /* vchar, vchar, vchar, 4 bit literal. */
7935 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7936 && mode3 == QImode)
b9e4e5d1 7937 type = v16qi_ftype_v16qi_v16qi_int;
24408032
AH		 7938
7939 /* vshort, vshort, vshort, 4 bit literal. */
7940 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7941 && mode3 == QImode)
b9e4e5d1 7942 type = v8hi_ftype_v8hi_v8hi_int;
24408032
AH		 7943
7944 /* vint, vint, vint, 4 bit literal. */
7945 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7946 && mode3 == QImode)
b9e4e5d1 7947 type = v4si_ftype_v4si_v4si_int;
24408032
AH		 7948
7949 /* vfloat, vfloat, vfloat, 4 bit literal. */
7950 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7951 && mode3 == QImode)
b9e4e5d1 7952 type = v4sf_ftype_v4sf_v4sf_int;
24408032 7953
2212663f
DB		 7954 else
7955 abort ();
7956
7957 def_builtin (d->mask, d->name, type, d->code);
7958 }
7959
0ac081f6 7960 /* Add the simple binary operators. */
00b960c7 7961 d = (struct builtin_description *) bdesc_2arg;
ca7558fc 7962 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
0ac081f6
AH		 7963 {
7964 enum machine_mode mode0, mode1, mode2;
7965 tree type;
7966
0559cc77 7967 if (d->name == 0 || d->icode == CODE_FOR_nothing)
0ac081f6 7968 continue;
f676971a 7969
0ac081f6
AH		 7970 mode0 = insn_data[d->icode].operand[0].mode;
7971 mode1 = insn_data[d->icode].operand[1].mode;
7972 mode2 = insn_data[d->icode].operand[2].mode;
7973
7974 /* When all three operands are of the same mode. */
7975 if (mode0 == mode1 && mode1 == mode2)
7976 {
7977 switch (mode0)
7978 {
7979 case V4SFmode:
7980 type = v4sf_ftype_v4sf_v4sf;
7981 break;
7982 case V4SImode:
7983 type = v4si_ftype_v4si_v4si;
7984 break;
7985 case V16QImode:
7986 type = v16qi_ftype_v16qi_v16qi;
7987 break;
7988 case V8HImode:
7989 type = v8hi_ftype_v8hi_v8hi;
7990 break;
a3170dc6
AH		 7991 case V2SImode:
7992 type = v2si_ftype_v2si_v2si;
7993 break;
7994 case V2SFmode:
7995 type = v2sf_ftype_v2sf_v2sf;
7996 break;
7997 case SImode:
7998 type = int_ftype_int_int;
7999 break;
0ac081f6
AH		 8000 default:
8001 abort ();
8002 }
8003 }
8004
8005 /* A few other combos we really don't want to do manually. */
8006
8007 /* vint, vfloat, vfloat. */
8008 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8009 type = v4si_ftype_v4sf_v4sf;
8010
8011 /* vshort, vchar, vchar. */
8012 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8013 type = v8hi_ftype_v16qi_v16qi;
8014
8015 /* vint, vshort, vshort. */
8016 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8017 type = v4si_ftype_v8hi_v8hi;
8018
8019 /* vshort, vint, vint. */
8020 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8021 type = v8hi_ftype_v4si_v4si;
8022
8023 /* vchar, vshort, vshort. */
8024 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8025 type = v16qi_ftype_v8hi_v8hi;
8026
8027 /* vint, vchar, vint. */
8028 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8029 type = v4si_ftype_v16qi_v4si;
8030
fa066a23
AH		 8031 /* vint, vchar, vchar. */
8032 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8033 type = v4si_ftype_v16qi_v16qi;
8034
0ac081f6
AH		 8035 /* vint, vshort, vint. */
8036 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8037 type = v4si_ftype_v8hi_v4si;
f676971a 8038
2212663f
DB		 8039 /* vint, vint, 5 bit literal. */
8040 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8041 type = v4si_ftype_v4si_int;
f676971a 8042
2212663f
DB		 8043 /* vshort, vshort, 5 bit literal. */
8044 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
b9e4e5d1 8045 type = v8hi_ftype_v8hi_int;
f676971a 8046
2212663f
DB		 8047 /* vchar, vchar, 5 bit literal. */
8048 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
b9e4e5d1 8049 type = v16qi_ftype_v16qi_int;
0ac081f6 8050
617e0e1d
DB		 8051 /* vfloat, vint, 5 bit literal. */
8052 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8053 type = v4sf_ftype_v4si_int;
f676971a 8054
617e0e1d
DB		 8055 /* vint, vfloat, 5 bit literal. */
8056 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
b9e4e5d1 8057 type = v4si_ftype_v4sf_int;
617e0e1d 8058
a3170dc6
AH		 8059 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8060 type = v2si_ftype_int_int;
8061
8062 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8063 type = v2si_ftype_v2si_char;
8064
8065 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8066 type = v2si_ftype_int_char;
8067
0ac081f6
AH		 8068 /* int, x, x. */
8069 else if (mode0 == SImode)
8070 {
8071 switch (mode1)
8072 {
8073 case V4SImode:
8074 type = int_ftype_v4si_v4si;
8075 break;
8076 case V4SFmode:
8077 type = int_ftype_v4sf_v4sf;
8078 break;
8079 case V16QImode:
8080 type = int_ftype_v16qi_v16qi;
8081 break;
8082 case V8HImode:
8083 type = int_ftype_v8hi_v8hi;
8084 break;
8085 default:
8086 abort ();
8087 }
8088 }
8089
8090 else
8091 abort ();
8092
2212663f
DB		 8093 def_builtin (d->mask, d->name, type, d->code);
8094 }
24408032 8095
2212663f
DB		 8096 /* Add the simple unary operators. */
8097 d = (struct builtin_description *) bdesc_1arg;
ca7558fc 8098 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
2212663f
DB		 8099 {
8100 enum machine_mode mode0, mode1;
8101 tree type;
8102
0559cc77 8103 if (d->name == 0 || d->icode == CODE_FOR_nothing)
2212663f 8104 continue;
f676971a 8105
2212663f
DB		 8106 mode0 = insn_data[d->icode].operand[0].mode;
8107 mode1 = insn_data[d->icode].operand[1].mode;
8108
8109 if (mode0 == V4SImode && mode1 == QImode)
c4ad648e 8110 type = v4si_ftype_int;
2212663f 8111 else if (mode0 == V8HImode && mode1 == QImode)
c4ad648e 8112 type = v8hi_ftype_int;
2212663f 8113 else if (mode0 == V16QImode && mode1 == QImode)
c4ad648e 8114 type = v16qi_ftype_int;
617e0e1d
DB		 8115 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8116 type = v4sf_ftype_v4sf;
20e26713
AH		 8117 else if (mode0 == V8HImode && mode1 == V16QImode)
8118 type = v8hi_ftype_v16qi;
8119 else if (mode0 == V4SImode && mode1 == V8HImode)
8120 type = v4si_ftype_v8hi;
a3170dc6
AH		 8121 else if (mode0 == V2SImode && mode1 == V2SImode)
8122 type = v2si_ftype_v2si;
8123 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8124 type = v2sf_ftype_v2sf;
8125 else if (mode0 == V2SFmode && mode1 == V2SImode)
8126 type = v2sf_ftype_v2si;
8127 else if (mode0 == V2SImode && mode1 == V2SFmode)
8128 type = v2si_ftype_v2sf;
8129 else if (mode0 == V2SImode && mode1 == QImode)
8130 type = v2si_ftype_char;
2212663f
DB		 8131 else
8132 abort ();
8133
0ac081f6
AH		 8134 def_builtin (d->mask, d->name, type, d->code);
8135 }
8136}
8137
c15c90bb
ZW		 8138static void
8139rs6000_init_libfuncs (void)
8140{
8141 if (!TARGET_HARD_FLOAT)
8142 return;
8143
c9034561 8144 if (DEFAULT_ABI != ABI_V4)
c15c90bb 8145 {
c9034561 8146 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
c15c90bb 8147 {
c9034561 8148 /* AIX library routines for float->int conversion. */
85363ca0
ZW		 8149 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8150 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
4274207b
DE		 8151 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8152 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
c15c90bb
ZW		 8153 }
8154
c9034561 8155 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
6f85d0c4
DE		 8156 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8157 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8158 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8159 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
c15c90bb 8160 }
c9034561 8161 else
c15c90bb 8162 {
c9034561 8163 /* 32-bit SVR4 quad floating point routines. */
c15c90bb
ZW		 8164
8165 set_optab_libfunc (add_optab, TFmode, "_q_add");
8166 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8167 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8168 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8169 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8170 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8171 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8172
c9034561
ZW		 8173 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8174 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8175 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8176 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8177 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8178 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8179
85363ca0
ZW		 8180 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8181 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8182 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8183 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8184 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8185 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8186 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
c15c90bb
ZW		 8187 }
8188}
fba73eb1
DE		 8189
8190\f
8191/* Expand a block clear operation, and return 1 if successful. Return 0
8192 if we should let the compiler generate normal code.
8193
8194 operands[0] is the destination
8195 operands[1] is the length
8196 operands[2] is the alignment */
8197
8198int
8199expand_block_clear (rtx operands[])
8200{
8201 rtx orig_dest = operands[0];
8202 rtx bytes_rtx = operands[1];
8203 rtx align_rtx = operands[2];
5514620a
GK		 8204 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8205 HOST_WIDE_INT align;
8206 HOST_WIDE_INT bytes;
fba73eb1
DE		 8207 int offset;
8208 int clear_bytes;
5514620a 8209 int clear_step;
fba73eb1
DE		 8210
8211 /* If this is not a fixed size move, just call memcpy */
8212 if (! constp)
8213 return 0;
8214
8215 /* If this is not a fixed size alignment, abort */
8216 if (GET_CODE (align_rtx) != CONST_INT)
8217 abort ();
8218 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8219
8220 /* Anything to clear? */
8221 bytes = INTVAL (bytes_rtx);
8222 if (bytes <= 0)
8223 return 1;
8224
5514620a
GK		 8225 /* Use the builtin memset after a point, to avoid huge code bloat.
8226 When optimize_size, avoid any significant code bloat; calling
8227 memset is about 4 instructions, so allow for one instruction to
8228 load zero and three to do clearing. */
8229 if (TARGET_ALTIVEC && align >= 128)
8230 clear_step = 16;
8231 else if (TARGET_POWERPC64 && align >= 32)
8232 clear_step = 8;
8233 else
8234 clear_step = 4;
fba73eb1 8235
5514620a
GK		 8236 if (optimize_size && bytes > 3 * clear_step)
8237 return 0;
8238 if (! optimize_size && bytes > 8 * clear_step)
fba73eb1
DE		 8239 return 0;
8240
8241 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8242 {
fba73eb1
DE		 8243 enum machine_mode mode = BLKmode;
8244 rtx dest;
f676971a 8245
5514620a
GK		 8246 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8247 {
8248 clear_bytes = 16;
8249 mode = V4SImode;
8250 }
8251 else if (bytes >= 8 && TARGET_POWERPC64
8252 /* 64-bit loads and stores require word-aligned
8253 displacements. */
8254 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
fba73eb1
DE		 8255 {
8256 clear_bytes = 8;
8257 mode = DImode;
fba73eb1 8258 }
5514620a 8259 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8260 { /* move 4 bytes */
8261 clear_bytes = 4;
8262 mode = SImode;
fba73eb1 8263 }
5514620a 8264 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8265 { /* move 2 bytes */
8266 clear_bytes = 2;
8267 mode = HImode;
fba73eb1
DE		 8268 }
8269 else /* move 1 byte at a time */
8270 {
8271 clear_bytes = 1;
8272 mode = QImode;
fba73eb1 8273 }
f676971a 8274
fba73eb1 8275 dest = adjust_address (orig_dest, mode, offset);
f676971a 8276
5514620a 8277 emit_move_insn (dest, CONST0_RTX (mode));
fba73eb1
DE		 8278 }
8279
8280 return 1;
8281}
8282
35aff10b 8283\f
7e69e155
MM		 8284/* Expand a block move operation, and return 1 if successful. Return 0
8285 if we should let the compiler generate normal code.
8286
8287 operands[0] is the destination
8288 operands[1] is the source
8289 operands[2] is the length
8290 operands[3] is the alignment */
8291
3933e0e1
MM		 8292#define MAX_MOVE_REG 4
8293
7e69e155 8294int
a2369ed3 8295expand_block_move (rtx operands[])
7e69e155 8296{
b6c9286a
MM		 8297 rtx orig_dest = operands[0];
8298 rtx orig_src = operands[1];
7e69e155 8299 rtx bytes_rtx = operands[2];
7e69e155 8300 rtx align_rtx = operands[3];
3933e0e1 8301 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
5ee95df6 8302 int align;
3933e0e1
MM		 8303 int bytes;
8304 int offset;
7e69e155 8305 int move_bytes;
cabfd258
GK		 8306 rtx stores[MAX_MOVE_REG];
8307 int num_reg = 0;
7e69e155 8308
3933e0e1 8309 /* If this is not a fixed size move, just call memcpy */
cc0d9ba8 8310 if (! constp)
3933e0e1
MM		 8311 return 0;
8312
5ee95df6
FS		 8313 /* If this is not a fixed size alignment, abort */
8314 if (GET_CODE (align_rtx) != CONST_INT)
8315 abort ();
fba73eb1 8316 align = INTVAL (align_rtx) * BITS_PER_UNIT;
5ee95df6 8317
7e69e155 8318 /* Anything to move? */
3933e0e1
MM		 8319 bytes = INTVAL (bytes_rtx);
8320 if (bytes <= 0)
7e69e155
MM		 8321 return 1;
8322
ea9982a8 8323 /* store_one_arg depends on expand_block_move to handle at least the size of
f676971a 8324 reg_parm_stack_space. */
ea9982a8 8325 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7e69e155
MM		 8326 return 0;
8327
cabfd258 8328 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7e69e155 8329 {
cabfd258 8330 union {
70128ad9 8331 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
a2369ed3 8332 rtx (*mov) (rtx, rtx);
cabfd258
GK		 8333 } gen_func;
8334 enum machine_mode mode = BLKmode;
8335 rtx src, dest;
f676971a 8336
5514620a
GK		 8337 /* Altivec first, since it will be faster than a string move
8338 when it applies, and usually not significantly larger. */
8339 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8340 {
8341 move_bytes = 16;
8342 mode = V4SImode;
8343 gen_func.mov = gen_movv4si;
8344 }
8345 else if (TARGET_STRING
cabfd258
GK		 8346 && bytes > 24 /* move up to 32 bytes at a time */
8347 && ! fixed_regs[5]
8348 && ! fixed_regs[6]
8349 && ! fixed_regs[7]
8350 && ! fixed_regs[8]
8351 && ! fixed_regs[9]
8352 && ! fixed_regs[10]
8353 && ! fixed_regs[11]
8354 && ! fixed_regs[12])
7e69e155 8355 {
cabfd258 8356 move_bytes = (bytes > 32) ? 32 : bytes;
70128ad9 8357 gen_func.movmemsi = gen_movmemsi_8reg;
cabfd258
GK		 8358 }
8359 else if (TARGET_STRING
8360 && bytes > 16 /* move up to 24 bytes at a time */
8361 && ! fixed_regs[5]
8362 && ! fixed_regs[6]
8363 && ! fixed_regs[7]
8364 && ! fixed_regs[8]
8365 && ! fixed_regs[9]
8366 && ! fixed_regs[10])
8367 {
8368 move_bytes = (bytes > 24) ? 24 : bytes;
70128ad9 8369 gen_func.movmemsi = gen_movmemsi_6reg;
cabfd258
GK		 8370 }
8371 else if (TARGET_STRING
8372 && bytes > 8 /* move up to 16 bytes at a time */
8373 && ! fixed_regs[5]
8374 && ! fixed_regs[6]
8375 && ! fixed_regs[7]
8376 && ! fixed_regs[8])
8377 {
8378 move_bytes = (bytes > 16) ? 16 : bytes;
70128ad9 8379 gen_func.movmemsi = gen_movmemsi_4reg;
cabfd258
GK		 8380 }
8381 else if (bytes >= 8 && TARGET_POWERPC64
8382 /* 64-bit loads and stores require word-aligned
8383 displacements. */
fba73eb1 8384 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
cabfd258
GK		 8385 {
8386 move_bytes = 8;
8387 mode = DImode;
8388 gen_func.mov = gen_movdi;
8389 }
8390 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8391 { /* move up to 8 bytes at a time */
8392 move_bytes = (bytes > 8) ? 8 : bytes;
70128ad9 8393 gen_func.movmemsi = gen_movmemsi_2reg;
cabfd258 8394 }
cd7d9ca4 8395 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
cabfd258
GK		 8396 { /* move 4 bytes */
8397 move_bytes = 4;
8398 mode = SImode;
8399 gen_func.mov = gen_movsi;
8400 }
cd7d9ca4 8401 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
cabfd258
GK		 8402 { /* move 2 bytes */
8403 move_bytes = 2;
8404 mode = HImode;
8405 gen_func.mov = gen_movhi;
8406 }
8407 else if (TARGET_STRING && bytes > 1)
8408 { /* move up to 4 bytes at a time */
8409 move_bytes = (bytes > 4) ? 4 : bytes;
70128ad9 8410 gen_func.movmemsi = gen_movmemsi_1reg;
cabfd258
GK		 8411 }
8412 else /* move 1 byte at a time */
8413 {
8414 move_bytes = 1;
8415 mode = QImode;
8416 gen_func.mov = gen_movqi;
8417 }
f676971a 8418
cabfd258
GK		 8419 src = adjust_address (orig_src, mode, offset);
8420 dest = adjust_address (orig_dest, mode, offset);
f676971a
EC		 8421
8422 if (mode != BLKmode)
cabfd258
GK		 8423 {
8424 rtx tmp_reg = gen_reg_rtx (mode);
f676971a 8425
cabfd258
GK		 8426 emit_insn ((*gen_func.mov) (tmp_reg, src));
8427 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
4c64a852 8428 }
3933e0e1 8429
cabfd258
GK		 8430 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8431 {
8432 int i;
8433 for (i = 0; i < num_reg; i++)
8434 emit_insn (stores[i]);
8435 num_reg = 0;
8436 }
35aff10b 8437
cabfd258 8438 if (mode == BLKmode)
7e69e155 8439 {
70128ad9 8440 /* Move the address into scratch registers. The movmemsi
cabfd258
GK		 8441 patterns require zero offset. */
8442 if (!REG_P (XEXP (src, 0)))
b6c9286a 8443 {
cabfd258
GK		 8444 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8445 src = replace_equiv_address (src, src_reg);
b6c9286a 8446 }
cabfd258 8447 set_mem_size (src, GEN_INT (move_bytes));
f676971a 8448
cabfd258 8449 if (!REG_P (XEXP (dest, 0)))
3933e0e1 8450 {
cabfd258
GK		 8451 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8452 dest = replace_equiv_address (dest, dest_reg);
7e69e155 8453 }
cabfd258 8454 set_mem_size (dest, GEN_INT (move_bytes));
f676971a 8455
70128ad9 8456 emit_insn ((*gen_func.movmemsi) (dest, src,
cabfd258
GK		 8457 GEN_INT (move_bytes & 31),
8458 align_rtx));
7e69e155 8459 }
7e69e155
MM		 8460 }
8461
8462 return 1;
8463}
8464
d62294f5 8465\f
9caa3eb2
DE		 8466/* Return a string to perform a load_multiple operation.
8467 operands[0] is the vector.
8468 operands[1] is the source address.
8469 operands[2] is the first destination register. */
8470
8471const char *
a2369ed3 8472rs6000_output_load_multiple (rtx operands[3])
9caa3eb2
DE		 8473{
8474 /* We have to handle the case where the pseudo used to contain the address
8475 is assigned to one of the output registers. */
8476 int i, j;
8477 int words = XVECLEN (operands[0], 0);
8478 rtx xop[10];
8479
8480 if (XVECLEN (operands[0], 0) == 1)
8481 return "{l|lwz} %2,0(%1)";
8482
8483 for (i = 0; i < words; i++)
8484 if (refers_to_regno_p (REGNO (operands[2]) + i,
8485 REGNO (operands[2]) + i + 1, operands[1], 0))
8486 {
8487 if (i == words-1)
8488 {
8489 xop[0] = GEN_INT (4 * (words-1));
8490 xop[1] = operands[1];
8491 xop[2] = operands[2];
8492 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8493 return "";
8494 }
8495 else if (i == 0)
8496 {
8497 xop[0] = GEN_INT (4 * (words-1));
8498 xop[1] = operands[1];
8499 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8500 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8501 return "";
8502 }
8503 else
8504 {
8505 for (j = 0; j < words; j++)
8506 if (j != i)
8507 {
8508 xop[0] = GEN_INT (j * 4);
8509 xop[1] = operands[1];
8510 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8511 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8512 }
8513 xop[0] = GEN_INT (i * 4);
8514 xop[1] = operands[1];
8515 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8516 return "";
8517 }
8518 }
8519
8520 return "{lsi|lswi} %2,%1,%N0";
8521}
8522
9878760c 8523\f
a4f6c312
SS		 8524/* A validation routine: say whether CODE, a condition code, and MODE
8525 match. The other alternatives either don't make sense or should
8526 never be generated. */
39a10a29 8527
48d72335 8528void
a2369ed3 8529validate_condition_mode (enum rtx_code code, enum machine_mode mode)
39a10a29 8530{
ec8e098d
PB		 8531 if ((GET_RTX_CLASS (code) != RTX_COMPARE
8532 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
39a10a29
GK		 8533 || GET_MODE_CLASS (mode) != MODE_CC)
8534 abort ();
8535
8536 /* These don't make sense. */
8537 if ((code == GT || code == LT || code == GE || code == LE)
8538 && mode == CCUNSmode)
8539 abort ();
8540
8541 if ((code == GTU || code == LTU || code == GEU || code == LEU)
8542 && mode != CCUNSmode)
8543 abort ();
8544
8545 if (mode != CCFPmode
8546 && (code == ORDERED || code == UNORDERED
8547 || code == UNEQ || code == LTGT
8548 || code == UNGT || code == UNLT
8549 || code == UNGE || code == UNLE))
a4f6c312 8550 abort ();
f676971a
EC		 8551
8552 /* These should never be generated except for
bc9ec0e0 8553 flag_finite_math_only. */
39a10a29 8554 if (mode == CCFPmode
ad72b533 8555 && ! flag_finite_math_only
39a10a29
GK		 8556 && (code == LE || code == GE
8557 || code == UNEQ || code == LTGT
8558 || code == UNGT || code == UNLT))
8559 abort ();
8560
8561 /* These are invalid; the information is not there. */
f676971a 8562 if (mode == CCEQmode
39a10a29
GK		 8563 && code != EQ && code != NE)
8564 abort ();
8565}
8566
9878760c
RK		 8567\f
8568/* Return 1 if ANDOP is a mask that has no bits on that are not in the
8569 mask required to convert the result of a rotate insn into a shift
b1765bde 8570 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9878760c
RK		 8571
8572int
a2369ed3 8573includes_lshift_p (rtx shiftop, rtx andop)
9878760c 8574{
e2c953b6
DE		 8575 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8576
8577 shift_mask <<= INTVAL (shiftop);
9878760c 8578
b1765bde 8579 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9878760c
RK		 8580}
8581
8582/* Similar, but for right shift. */
8583
8584int
a2369ed3 8585includes_rshift_p (rtx shiftop, rtx andop)
9878760c 8586{
a7653a2c 8587 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9878760c
RK		 8588
8589 shift_mask >>= INTVAL (shiftop);
8590
b1765bde 8591 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
e2c953b6
DE		 8592}
8593
c5059423
AM		 8594/* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8595 to perform a left shift. It must have exactly SHIFTOP least
b6d08ca1 8596 significant 0's, then one or more 1's, then zero or more 0's. */
e2c953b6
DE		 8597
8598int
a2369ed3 8599includes_rldic_lshift_p (rtx shiftop, rtx andop)
e2c953b6 8600{
c5059423
AM		 8601 if (GET_CODE (andop) == CONST_INT)
8602 {
02071907 8603 HOST_WIDE_INT c, lsb, shift_mask;
e2c953b6 8604
c5059423 8605 c = INTVAL (andop);
02071907 8606 if (c == 0 || c == ~0)
c5059423 8607 return 0;
e2c953b6 8608
02071907 8609 shift_mask = ~0;
c5059423
AM		 8610 shift_mask <<= INTVAL (shiftop);
8611
b6d08ca1 8612 /* Find the least significant one bit. */
c5059423
AM		 8613 lsb = c & -c;
8614
8615 /* It must coincide with the LSB of the shift mask. */
8616 if (-lsb != shift_mask)
8617 return 0;
e2c953b6 8618
c5059423
AM		 8619 /* Invert to look for the next transition (if any). */
8620 c = ~c;
8621
8622 /* Remove the low group of ones (originally low group of zeros). */
8623 c &= -lsb;
8624
8625 /* Again find the lsb, and check we have all 1's above. */
8626 lsb = c & -c;
8627 return c == -lsb;
8628 }
8629 else if (GET_CODE (andop) == CONST_DOUBLE
8630 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8631 {
02071907
AM		 8632 HOST_WIDE_INT low, high, lsb;
8633 HOST_WIDE_INT shift_mask_low, shift_mask_high;
c5059423
AM		 8634
8635 low = CONST_DOUBLE_LOW (andop);
8636 if (HOST_BITS_PER_WIDE_INT < 64)
8637 high = CONST_DOUBLE_HIGH (andop);
8638
8639 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
02071907 8640 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
c5059423
AM		 8641 return 0;
8642
8643 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8644 {
02071907 8645 shift_mask_high = ~0;
c5059423
AM		 8646 if (INTVAL (shiftop) > 32)
8647 shift_mask_high <<= INTVAL (shiftop) - 32;
8648
8649 lsb = high & -high;
8650
8651 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8652 return 0;
8653
8654 high = ~high;
8655 high &= -lsb;
8656
8657 lsb = high & -high;
8658 return high == -lsb;
8659 }
8660
02071907 8661 shift_mask_low = ~0;
c5059423
AM		 8662 shift_mask_low <<= INTVAL (shiftop);
8663
8664 lsb = low & -low;
8665
8666 if (-lsb != shift_mask_low)
8667 return 0;
8668
8669 if (HOST_BITS_PER_WIDE_INT < 64)
8670 high = ~high;
8671 low = ~low;
8672 low &= -lsb;
8673
8674 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8675 {
8676 lsb = high & -high;
8677 return high == -lsb;
8678 }
8679
8680 lsb = low & -low;
8681 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8682 }
8683 else
8684 return 0;
8685}
e2c953b6 8686
c5059423
AM		 8687/* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8688 to perform a left shift. It must have SHIFTOP or more least
c1207243 8689 significant 0's, with the remainder of the word 1's. */
e2c953b6 8690
c5059423 8691int
a2369ed3 8692includes_rldicr_lshift_p (rtx shiftop, rtx andop)
c5059423 8693{
e2c953b6 8694 if (GET_CODE (andop) == CONST_INT)
c5059423 8695 {
02071907 8696 HOST_WIDE_INT c, lsb, shift_mask;
c5059423 8697
02071907 8698 shift_mask = ~0;
c5059423
AM		 8699 shift_mask <<= INTVAL (shiftop);
8700 c = INTVAL (andop);
8701
c1207243 8702 /* Find the least significant one bit. */
c5059423
AM		 8703 lsb = c & -c;
8704
8705 /* It must be covered by the shift mask.
a4f6c312 8706 This test also rejects c == 0. */
c5059423
AM		 8707 if ((lsb & shift_mask) == 0)
8708 return 0;
8709
8710 /* Check we have all 1's above the transition, and reject all 1's. */
8711 return c == -lsb && lsb != 1;
8712 }
8713 else if (GET_CODE (andop) == CONST_DOUBLE
8714 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8715 {
02071907 8716 HOST_WIDE_INT low, lsb, shift_mask_low;
c5059423
AM		 8717
8718 low = CONST_DOUBLE_LOW (andop);
8719
8720 if (HOST_BITS_PER_WIDE_INT < 64)
8721 {
02071907 8722 HOST_WIDE_INT high, shift_mask_high;
c5059423
AM		 8723
8724 high = CONST_DOUBLE_HIGH (andop);
8725
8726 if (low == 0)
8727 {
02071907 8728 shift_mask_high = ~0;
c5059423
AM		 8729 if (INTVAL (shiftop) > 32)
8730 shift_mask_high <<= INTVAL (shiftop) - 32;
8731
8732 lsb = high & -high;
8733
8734 if ((lsb & shift_mask_high) == 0)
8735 return 0;
8736
8737 return high == -lsb;
8738 }
8739 if (high != ~0)
8740 return 0;
8741 }
8742
02071907 8743 shift_mask_low = ~0;
c5059423
AM		 8744 shift_mask_low <<= INTVAL (shiftop);
8745
8746 lsb = low & -low;
8747
8748 if ((lsb & shift_mask_low) == 0)
8749 return 0;
8750
8751 return low == -lsb && lsb != 1;
8752 }
e2c953b6 8753 else
c5059423 8754 return 0;
9878760c 8755}
35068b43 8756
11ac38b2
DE		 8757/* Return 1 if operands will generate a valid arguments to rlwimi
8758instruction for insert with right shift in 64-bit mode. The mask may
8759not start on the first bit or stop on the last bit because wrap-around
8760effects of instruction do not correspond to semantics of RTL insn. */
8761
8762int
8763insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
8764{
8765 if (INTVAL (startop) < 64
8766 && INTVAL (startop) > 32
8767 && (INTVAL (sizeop) + INTVAL (startop) < 64)
8768 && (INTVAL (sizeop) + INTVAL (startop) > 33)
8769 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
8770 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
8771 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
8772 return 1;
8773
8774 return 0;
8775}
8776
35068b43 8777/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
90f81f99 8778 for lfq and stfq insns iff the registers are hard registers. */
35068b43
RK		 8779
8780int
a2369ed3 8781registers_ok_for_quad_peep (rtx reg1, rtx reg2)
35068b43
RK		 8782{
8783 /* We might have been passed a SUBREG. */
f676971a 8784 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
35068b43 8785 return 0;
f676971a 8786
90f81f99
AP		 8787 /* We might have been passed non floating point registers. */
8788 if (!FP_REGNO_P (REGNO (reg1))
8789 || !FP_REGNO_P (REGNO (reg2)))
8790 return 0;
35068b43
RK		 8791
8792 return (REGNO (reg1) == REGNO (reg2) - 1);
8793}
8794
a4f6c312
SS		 8795/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8796 addr1 and addr2 must be in consecutive memory locations
8797 (addr2 == addr1 + 8). */
35068b43
RK		 8798
8799int
90f81f99 8800mems_ok_for_quad_peep (rtx mem1, rtx mem2)
35068b43 8801{
90f81f99 8802 rtx addr1, addr2;
e2c953b6 8803 unsigned int reg1;
35068b43
RK		 8804 int offset1;
8805
90f81f99
AP		 8806 /* The mems cannot be volatile. */
8807 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
8808 return 0;
f676971a 8809
90f81f99
AP		 8810 addr1 = XEXP (mem1, 0);
8811 addr2 = XEXP (mem2, 0);
8812
35068b43
RK		 8813 /* Extract an offset (if used) from the first addr. */
8814 if (GET_CODE (addr1) == PLUS)
8815 {
8816 /* If not a REG, return zero. */
8817 if (GET_CODE (XEXP (addr1, 0)) != REG)
8818 return 0;
8819 else
8820 {
c4ad648e 8821 reg1 = REGNO (XEXP (addr1, 0));
35068b43
RK		 8822 /* The offset must be constant! */
8823 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
c4ad648e
AM		 8824 return 0;
8825 offset1 = INTVAL (XEXP (addr1, 1));
35068b43
RK		 8826 }
8827 }
8828 else if (GET_CODE (addr1) != REG)
8829 return 0;
8830 else
8831 {
8832 reg1 = REGNO (addr1);
8833 /* This was a simple (mem (reg)) expression. Offset is 0. */
8834 offset1 = 0;
8835 }
8836
a2369ed3 8837 /* Make sure the second address is a (mem (plus (reg) (const_int)))
f676971a 8838 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
0f6937fe 8839 register as addr1. */
984e25ac 8840 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
0f6937fe 8841 return 1;
35068b43
RK		 8842 if (GET_CODE (addr2) != PLUS)
8843 return 0;
8844
8845 if (GET_CODE (XEXP (addr2, 0)) != REG
8846 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8847 return 0;
8848
8849 if (reg1 != REGNO (XEXP (addr2, 0)))
8850 return 0;
8851
8852 /* The offset for the second addr must be 8 more than the first addr. */
8853 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8854 return 0;
8855
8856 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8857 instructions. */
8858 return 1;
8859}
9878760c
RK		 8860\f
8861/* Return the register class of a scratch register needed to copy IN into
8862 or out of a register in CLASS in MODE. If it can be done directly,
8863 NO_REGS is returned. */
8864
8865enum reg_class
f676971a 8866secondary_reload_class (enum reg_class class,
a9baceb1
GK		 8867 enum machine_mode mode ATTRIBUTE_UNUSED,
8868 rtx in)
9878760c 8869{
5accd822 8870 int regno;
9878760c 8871
ab82a49f
AP		 8872 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8873#if TARGET_MACHO
c4ad648e 8874 && MACHOPIC_INDIRECT
ab82a49f 8875#endif
c4ad648e 8876 ))
46fad5b7
DJ		 8877 {
8878 /* We cannot copy a symbolic operand directly into anything
c4ad648e
AM		 8879 other than BASE_REGS for TARGET_ELF. So indicate that a
8880 register from BASE_REGS is needed as an intermediate
8881 register.
f676971a 8882
46fad5b7
DJ		 8883 On Darwin, pic addresses require a load from memory, which
8884 needs a base register. */
8885 if (class != BASE_REGS
c4ad648e
AM		 8886 && (GET_CODE (in) == SYMBOL_REF
8887 || GET_CODE (in) == HIGH
8888 || GET_CODE (in) == LABEL_REF
8889 || GET_CODE (in) == CONST))
8890 return BASE_REGS;
46fad5b7 8891 }
e7b7998a 8892
5accd822
DE		 8893 if (GET_CODE (in) == REG)
8894 {
8895 regno = REGNO (in);
8896 if (regno >= FIRST_PSEUDO_REGISTER)
8897 {
8898 regno = true_regnum (in);
8899 if (regno >= FIRST_PSEUDO_REGISTER)
8900 regno = -1;
8901 }
8902 }
8903 else if (GET_CODE (in) == SUBREG)
8904 {
8905 regno = true_regnum (in);
8906 if (regno >= FIRST_PSEUDO_REGISTER)
8907 regno = -1;
8908 }
8909 else
8910 regno = -1;
8911
9878760c
RK		 8912 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8913 into anything. */
8914 if (class == GENERAL_REGS || class == BASE_REGS
8915 || (regno >= 0 && INT_REGNO_P (regno)))
8916 return NO_REGS;
8917
8918 /* Constants, memory, and FP registers can go into FP registers. */
8919 if ((regno == -1 || FP_REGNO_P (regno))
8920 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8921 return NO_REGS;
8922
0ac081f6
AH		 8923 /* Memory, and AltiVec registers can go into AltiVec registers. */
8924 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8925 && class == ALTIVEC_REGS)
8926 return NO_REGS;
8927
9878760c
RK		 8928 /* We can copy among the CR registers. */
8929 if ((class == CR_REGS || class == CR0_REGS)
8930 && regno >= 0 && CR_REGNO_P (regno))
8931 return NO_REGS;
8932
8933 /* Otherwise, we need GENERAL_REGS. */
8934 return GENERAL_REGS;
8935}
8936\f
8937/* Given a comparison operation, return the bit number in CCR to test. We
f676971a 8938 know this is a valid comparison.
9878760c
RK		 8939
8940 SCC_P is 1 if this is for an scc. That means that %D will have been
8941 used instead of %C, so the bits will be in different places.
8942
b4ac57ab 8943 Return -1 if OP isn't a valid comparison for some reason. */
9878760c
RK		 8944
8945int
a2369ed3 8946ccr_bit (rtx op, int scc_p)
9878760c
RK		 8947{
8948 enum rtx_code code = GET_CODE (op);
8949 enum machine_mode cc_mode;
8950 int cc_regnum;
8951 int base_bit;
9ebbca7d 8952 rtx reg;
9878760c 8953
ec8e098d 8954 if (!COMPARISON_P (op))
9878760c
RK		 8955 return -1;
8956
9ebbca7d
GK		 8957 reg = XEXP (op, 0);
8958
8959 if (GET_CODE (reg) != REG
8960 || ! CR_REGNO_P (REGNO (reg)))
8961 abort ();
8962
8963 cc_mode = GET_MODE (reg);
8964 cc_regnum = REGNO (reg);
8965 base_bit = 4 * (cc_regnum - CR0_REGNO);
9878760c 8966
39a10a29 8967 validate_condition_mode (code, cc_mode);
c5defebb 8968
b7053a3f
GK		 8969 /* When generating a sCOND operation, only positive conditions are
8970 allowed. */
8971 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8972 && code != GTU && code != LTU)
8973 abort ();
f676971a 8974
9878760c
RK		 8975 switch (code)
8976 {
8977 case NE:
8978 return scc_p ? base_bit + 3 : base_bit + 2;
8979 case EQ:
8980 return base_bit + 2;
1c882ea4 8981 case GT: case GTU: case UNLE:
9878760c 8982 return base_bit + 1;
1c882ea4 8983 case LT: case LTU: case UNGE:
9878760c 8984 return base_bit;
1c882ea4
GK		 8985 case ORDERED: case UNORDERED:
8986 return base_bit + 3;
9878760c
RK		 8987
8988 case GE: case GEU:
39a10a29 8989 /* If scc, we will have done a cror to put the bit in the
9878760c
RK		 8990 unordered position. So test that bit. For integer, this is ! LT
8991 unless this is an scc insn. */
39a10a29 8992 return scc_p ? base_bit + 3 : base_bit;
9878760c
RK		 8993
8994 case LE: case LEU:
39a10a29 8995 return scc_p ? base_bit + 3 : base_bit + 1;
1c882ea4 8996
9878760c
RK		 8997 default:
8998 abort ();
8999 }
9000}
1ff7789b 9001\f
8d30c4ee 9002/* Return the GOT register. */
1ff7789b 9003
9390387d 9004rtx
a2369ed3 9005rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
1ff7789b 9006{
a4f6c312
SS		 9007 /* The second flow pass currently (June 1999) can't update
9008 regs_ever_live without disturbing other parts of the compiler, so
9009 update it here to make the prolog/epilogue code happy. */
1db02437
FS		 9010 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9011 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
1ff7789b 9012
8d30c4ee 9013 current_function_uses_pic_offset_table = 1;
3cb999d8 9014
1ff7789b
MM		 9015 return pic_offset_table_rtx;
9016}
a7df97e6 9017\f
e2500fed
GK		 9018/* Function to init struct machine_function.
9019 This will be called, via a pointer variable,
9020 from push_function_context. */
a7df97e6 9021
e2500fed 9022static struct machine_function *
863d938c 9023rs6000_init_machine_status (void)
a7df97e6 9024{
e2500fed 9025 return ggc_alloc_cleared (sizeof (machine_function));
a7df97e6 9026}
9878760c 9027\f
0ba1b2ff
AM		 9028/* These macros test for integers and extract the low-order bits. */
9029#define INT_P(X) \
9030((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9031 && GET_MODE (X) == VOIDmode)
9032
9033#define INT_LOWPART(X) \
9034 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9035
9036int
a2369ed3 9037extract_MB (rtx op)
0ba1b2ff
AM		 9038{
9039 int i;
9040 unsigned long val = INT_LOWPART (op);
9041
9042 /* If the high bit is zero, the value is the first 1 bit we find
9043 from the left. */
9044 if ((val & 0x80000000) == 0)
9045 {
9046 if ((val & 0xffffffff) == 0)
9047 abort ();
9048
9049 i = 1;
9050 while (((val <<= 1) & 0x80000000) == 0)
9051 ++i;
9052 return i;
9053 }
9054
9055 /* If the high bit is set and the low bit is not, or the mask is all
9056 1's, the value is zero. */
9057 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9058 return 0;
9059
9060 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9061 from the right. */
9062 i = 31;
9063 while (((val >>= 1) & 1) != 0)
9064 --i;
9065
9066 return i;
9067}
9068
9069int
a2369ed3 9070extract_ME (rtx op)
0ba1b2ff
AM		 9071{
9072 int i;
9073 unsigned long val = INT_LOWPART (op);
9074
9075 /* If the low bit is zero, the value is the first 1 bit we find from
9076 the right. */
9077 if ((val & 1) == 0)
9078 {
9079 if ((val & 0xffffffff) == 0)
9080 abort ();
9081
9082 i = 30;
9083 while (((val >>= 1) & 1) == 0)
9084 --i;
9085
9086 return i;
9087 }
9088
9089 /* If the low bit is set and the high bit is not, or the mask is all
9090 1's, the value is 31. */
9091 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9092 return 31;
9093
9094 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9095 from the left. */
9096 i = 0;
9097 while (((val <<= 1) & 0x80000000) != 0)
9098 ++i;
9099
9100 return i;
9101}
9102
c4501e62
JJ		 9103/* Locate some local-dynamic symbol still in use by this function
9104 so that we can print its name in some tls_ld pattern. */
9105
9106static const char *
863d938c 9107rs6000_get_some_local_dynamic_name (void)
c4501e62
JJ		 9108{
9109 rtx insn;
9110
9111 if (cfun->machine->some_ld_name)
9112 return cfun->machine->some_ld_name;
9113
9114 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9115 if (INSN_P (insn)
9116 && for_each_rtx (&PATTERN (insn),
9117 rs6000_get_some_local_dynamic_name_1, 0))
9118 return cfun->machine->some_ld_name;
9119
9120 abort ();
9121}
9122
9123/* Helper function for rs6000_get_some_local_dynamic_name. */
9124
9125static int
a2369ed3 9126rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 9127{
9128 rtx x = *px;
9129
9130 if (GET_CODE (x) == SYMBOL_REF)
9131 {
9132 const char *str = XSTR (x, 0);
9133 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9134 {
9135 cfun->machine->some_ld_name = str;
9136 return 1;
9137 }
9138 }
9139
9140 return 0;
9141}
9142
85b776df
AM		 9143/* Write out a function code label. */
9144
9145void
9146rs6000_output_function_entry (FILE *file, const char *fname)
9147{
9148 if (fname[0] != '.')
9149 {
9150 switch (DEFAULT_ABI)
9151 {
9152 default:
9153 abort ();
9154
9155 case ABI_AIX:
9156 if (DOT_SYMBOLS)
9157 putc ('.', file);
9158 else
9159 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9160 break;
9161
9162 case ABI_V4:
9163 case ABI_DARWIN:
9164 break;
9165 }
9166 }
9167 if (TARGET_AIX)
9168 RS6000_OUTPUT_BASENAME (file, fname);
9169 else
9170 assemble_name (file, fname);
9171}
9172
9878760c
RK		 9173/* Print an operand. Recognize special options, documented below. */
9174
38c1f2d7 9175#if TARGET_ELF
d9407988 9176#define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8fbd2dc7 9177#define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
ba5e43aa
MM		 9178#else
9179#define SMALL_DATA_RELOC "sda21"
8fbd2dc7 9180#define SMALL_DATA_REG 0
ba5e43aa
MM		 9181#endif
9182
9878760c 9183void
a2369ed3 9184print_operand (FILE *file, rtx x, int code)
9878760c
RK		 9185{
9186 int i;
a260abc9 9187 HOST_WIDE_INT val;
0ba1b2ff 9188 unsigned HOST_WIDE_INT uval;
9878760c
RK		 9189
9190 switch (code)
9191 {
a8b3aeda 9192 case '.':
a85d226b
RK		 9193 /* Write out an instruction after the call which may be replaced
9194 with glue code by the loader. This depends on the AIX version. */
9195 asm_fprintf (file, RS6000_CALL_GLUE);
a8b3aeda
RK		 9196 return;
9197
81eace42
GK		 9198 /* %a is output_address. */
9199
9854d9ed
RK		 9200 case 'A':
9201 /* If X is a constant integer whose low-order 5 bits are zero,
9202 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
76229ac8 9203 in the AIX assembler where "sri" with a zero shift count
20e26713 9204 writes a trash instruction. */
9854d9ed 9205 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
76229ac8 9206 putc ('l', file);
9854d9ed 9207 else
76229ac8 9208 putc ('r', file);
9854d9ed
RK		 9209 return;
9210
9211 case 'b':
e2c953b6
DE		 9212 /* If constant, low-order 16 bits of constant, unsigned.
9213 Otherwise, write normally. */
9214 if (INT_P (x))
9215 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9216 else
9217 print_operand (file, x, 0);
cad12a8d
RK		 9218 return;
9219
a260abc9
DE		 9220 case 'B':
9221 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9222 for 64-bit mask direction. */
9390387d 9223 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
a238cd8b 9224 return;
a260abc9 9225
81eace42
GK		 9226 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9227 output_operand. */
9228
423c1189
AH		 9229 case 'c':
9230 /* X is a CR register. Print the number of the GT bit of the CR. */
9231 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9232 output_operand_lossage ("invalid %%E value");
9233 else
9234 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9235 return;
9236
9237 case 'D':
6b1fedc3 9238 /* Like 'J' but get to the EQ bit. */
423c1189
AH		 9239 if (GET_CODE (x) != REG)
9240 abort ();
9241
6b1fedc3
AH		 9242 /* Bit 1 is EQ bit. */
9243 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
423c1189 9244
64022b5d 9245 fprintf (file, "%d", i);
423c1189
AH		 9246 return;
9247
9854d9ed 9248 case 'E':
39a10a29 9249 /* X is a CR register. Print the number of the EQ bit of the CR */
9854d9ed
RK		 9250 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9251 output_operand_lossage ("invalid %%E value");
78fbdbf7 9252 else
39a10a29 9253 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
a85d226b 9254 return;
9854d9ed
RK		 9255
9256 case 'f':
9257 /* X is a CR register. Print the shift count needed to move it
9258 to the high-order four bits. */
9259 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9260 output_operand_lossage ("invalid %%f value");
9261 else
9ebbca7d 9262 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9263 return;
9264
9265 case 'F':
9266 /* Similar, but print the count for the rotate in the opposite
9267 direction. */
9268 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9269 output_operand_lossage ("invalid %%F value");
9270 else
9ebbca7d 9271 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9272 return;
9273
9274 case 'G':
9275 /* X is a constant integer. If it is negative, print "m",
43aa4e05 9276 otherwise print "z". This is to make an aze or ame insn. */
9854d9ed
RK		 9277 if (GET_CODE (x) != CONST_INT)
9278 output_operand_lossage ("invalid %%G value");
9279 else if (INTVAL (x) >= 0)
76229ac8 9280 putc ('z', file);
9854d9ed 9281 else
76229ac8 9282 putc ('m', file);
9854d9ed 9283 return;
e2c953b6 9284
9878760c 9285 case 'h':
a4f6c312
SS		 9286 /* If constant, output low-order five bits. Otherwise, write
9287 normally. */
9878760c 9288 if (INT_P (x))
5f59ecb7 9289 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9878760c
RK		 9290 else
9291 print_operand (file, x, 0);
9292 return;
9293
64305719 9294 case 'H':
a4f6c312
SS		 9295 /* If constant, output low-order six bits. Otherwise, write
9296 normally. */
64305719 9297 if (INT_P (x))
5f59ecb7 9298 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
64305719
DE		 9299 else
9300 print_operand (file, x, 0);
9301 return;
9302
9854d9ed
RK		 9303 case 'I':
9304 /* Print `i' if this is a constant, else nothing. */
9878760c 9305 if (INT_P (x))
76229ac8 9306 putc ('i', file);
9878760c
RK		 9307 return;
9308
9854d9ed
RK		 9309 case 'j':
9310 /* Write the bit number in CCR for jump. */
9311 i = ccr_bit (x, 0);
9312 if (i == -1)
9313 output_operand_lossage ("invalid %%j code");
9878760c 9314 else
9854d9ed 9315 fprintf (file, "%d", i);
9878760c
RK		 9316 return;
9317
9854d9ed
RK		 9318 case 'J':
9319 /* Similar, but add one for shift count in rlinm for scc and pass
9320 scc flag to `ccr_bit'. */
9321 i = ccr_bit (x, 1);
9322 if (i == -1)
9323 output_operand_lossage ("invalid %%J code");
9324 else
a0466a68
RK		 9325 /* If we want bit 31, write a shift count of zero, not 32. */
9326 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9878760c
RK		 9327 return;
9328
9854d9ed
RK		 9329 case 'k':
9330 /* X must be a constant. Write the 1's complement of the
9331 constant. */
9878760c 9332 if (! INT_P (x))
9854d9ed 9333 output_operand_lossage ("invalid %%k value");
e2c953b6
DE		 9334 else
9335 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9878760c
RK		 9336 return;
9337
81eace42 9338 case 'K':
9ebbca7d
GK		 9339 /* X must be a symbolic constant on ELF. Write an
9340 expression suitable for an 'addi' that adds in the low 16
9341 bits of the MEM. */
9342 if (GET_CODE (x) != CONST)
9343 {
9344 print_operand_address (file, x);
9345 fputs ("@l", file);
9346 }
9347 else
9348 {
9349 if (GET_CODE (XEXP (x, 0)) != PLUS
9350 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9351 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9352 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
53cd5d6c 9353 output_operand_lossage ("invalid %%K value");
9ebbca7d
GK		 9354 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9355 fputs ("@l", file);
ed8d2920
MM		 9356 /* For GNU as, there must be a non-alphanumeric character
9357 between 'l' and the number. The '-' is added by
9358 print_operand() already. */
9359 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9360 fputs ("+", file);
9ebbca7d
GK		 9361 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9362 }
81eace42
GK		 9363 return;
9364
9365 /* %l is output_asm_label. */
9ebbca7d 9366
9854d9ed
RK		 9367 case 'L':
9368 /* Write second word of DImode or DFmode reference. Works on register
9369 or non-indexed memory only. */
9370 if (GET_CODE (x) == REG)
fb5c67a7 9371 fputs (reg_names[REGNO (x) + 1], file);
9854d9ed
RK		 9372 else if (GET_CODE (x) == MEM)
9373 {
9374 /* Handle possible auto-increment. Since it is pre-increment and
1427100a 9375 we have already done it, we can just use an offset of word. */
9854d9ed
RK		 9376 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9377 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
ed8908e7
RK		 9378 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9379 UNITS_PER_WORD));
9854d9ed 9380 else
d7624dc0
RK		 9381 output_address (XEXP (adjust_address_nv (x, SImode,
9382 UNITS_PER_WORD),
9383 0));
ed8908e7 9384
ba5e43aa 9385 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9386 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9387 reg_names[SMALL_DATA_REG]);
9854d9ed 9388 }
9878760c 9389 return;
f676971a 9390
9878760c
RK		 9391 case 'm':
9392 /* MB value for a mask operand. */
b1765bde 9393 if (! mask_operand (x, SImode))
9878760c
RK		 9394 output_operand_lossage ("invalid %%m value");
9395
0ba1b2ff 9396 fprintf (file, "%d", extract_MB (x));
9878760c
RK		 9397 return;
9398
9399 case 'M':
9400 /* ME value for a mask operand. */
b1765bde 9401 if (! mask_operand (x, SImode))
a260abc9 9402 output_operand_lossage ("invalid %%M value");
9878760c 9403
0ba1b2ff 9404 fprintf (file, "%d", extract_ME (x));
9878760c
RK		 9405 return;
9406
81eace42
GK		 9407 /* %n outputs the negative of its operand. */
9408
9878760c
RK		 9409 case 'N':
9410 /* Write the number of elements in the vector times 4. */
9411 if (GET_CODE (x) != PARALLEL)
9412 output_operand_lossage ("invalid %%N value");
e2c953b6
DE		 9413 else
9414 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9878760c
RK		 9415 return;
9416
9417 case 'O':
9418 /* Similar, but subtract 1 first. */
9419 if (GET_CODE (x) != PARALLEL)
1427100a 9420 output_operand_lossage ("invalid %%O value");
e2c953b6
DE		 9421 else
9422 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9878760c
RK		 9423 return;
9424
9854d9ed
RK		 9425 case 'p':
9426 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9427 if (! INT_P (x)
2bfcf297 9428 || INT_LOWPART (x) < 0
9854d9ed
RK		 9429 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9430 output_operand_lossage ("invalid %%p value");
e2c953b6
DE		 9431 else
9432 fprintf (file, "%d", i);
9854d9ed
RK		 9433 return;
9434
9878760c
RK		 9435 case 'P':
9436 /* The operand must be an indirect memory reference. The result
8bb418a3 9437 is the register name. */
9878760c
RK		 9438 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9439 || REGNO (XEXP (x, 0)) >= 32)
9440 output_operand_lossage ("invalid %%P value");
e2c953b6 9441 else
fb5c67a7 9442 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9878760c
RK		 9443 return;
9444
dfbdccdb
GK		 9445 case 'q':
9446 /* This outputs the logical code corresponding to a boolean
9447 expression. The expression may have one or both operands
39a10a29 9448 negated (if one, only the first one). For condition register
c4ad648e
AM		 9449 logical operations, it will also treat the negated
9450 CR codes as NOTs, but not handle NOTs of them. */
dfbdccdb 9451 {
63bc1d05 9452 const char *const *t = 0;
dfbdccdb
GK		 9453 const char *s;
9454 enum rtx_code code = GET_CODE (x);
9455 static const char * const tbl[3][3] = {
9456 { "and", "andc", "nor" },
9457 { "or", "orc", "nand" },
9458 { "xor", "eqv", "xor" } };
9459
9460 if (code == AND)
9461 t = tbl[0];
9462 else if (code == IOR)
9463 t = tbl[1];
9464 else if (code == XOR)
9465 t = tbl[2];
9466 else
9467 output_operand_lossage ("invalid %%q value");
9468
9469 if (GET_CODE (XEXP (x, 0)) != NOT)
9470 s = t[0];
9471 else
9472 {
9473 if (GET_CODE (XEXP (x, 1)) == NOT)
9474 s = t[2];
9475 else
9476 s = t[1];
9477 }
f676971a 9478
dfbdccdb
GK		 9479 fputs (s, file);
9480 }
9481 return;
9482
2c4a9cff
DE		 9483 case 'Q':
9484 if (TARGET_MFCRF)
3b6ce0af 9485 fputc (',', file);
5efb1046 9486 /* FALLTHRU */
2c4a9cff
DE		 9487 else
9488 return;
9489
9854d9ed
RK		 9490 case 'R':
9491 /* X is a CR register. Print the mask for `mtcrf'. */
9492 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9493 output_operand_lossage ("invalid %%R value");
9494 else
9ebbca7d 9495 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9878760c 9496 return;
9854d9ed
RK		 9497
9498 case 's':
9499 /* Low 5 bits of 32 - value */
9500 if (! INT_P (x))
9501 output_operand_lossage ("invalid %%s value");
e2c953b6
DE		 9502 else
9503 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9878760c 9504 return;
9854d9ed 9505
a260abc9 9506 case 'S':
0ba1b2ff 9507 /* PowerPC64 mask position. All 0's is excluded.
a260abc9
DE		 9508 CONST_INT 32-bit mask is considered sign-extended so any
9509 transition must occur within the CONST_INT, not on the boundary. */
b1765bde 9510 if (! mask64_operand (x, DImode))
a260abc9
DE		 9511 output_operand_lossage ("invalid %%S value");
9512
0ba1b2ff 9513 uval = INT_LOWPART (x);
a260abc9 9514
0ba1b2ff 9515 if (uval & 1) /* Clear Left */
a260abc9 9516 {
f099d360
GK		 9517#if HOST_BITS_PER_WIDE_INT > 64
9518 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9519#endif
0ba1b2ff 9520 i = 64;
a260abc9 9521 }
0ba1b2ff 9522 else /* Clear Right */
a260abc9 9523 {
0ba1b2ff 9524 uval = ~uval;
f099d360
GK		 9525#if HOST_BITS_PER_WIDE_INT > 64
9526 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9527#endif
0ba1b2ff 9528 i = 63;
a260abc9 9529 }
0ba1b2ff
AM		 9530 while (uval != 0)
9531 --i, uval >>= 1;
9532 if (i < 0)
9533 abort ();
9534 fprintf (file, "%d", i);
9535 return;
a260abc9 9536
a3170dc6
AH		 9537 case 't':
9538 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
9539 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
9540 abort ();
9541
9542 /* Bit 3 is OV bit. */
9543 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9544
9545 /* If we want bit 31, write a shift count of zero, not 32. */
9546 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9547 return;
9548
cccf3bdc
DE		 9549 case 'T':
9550 /* Print the symbolic name of a branch target register. */
9551 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9552 && REGNO (x) != COUNT_REGISTER_REGNUM))
9553 output_operand_lossage ("invalid %%T value");
e2c953b6 9554 else if (REGNO (x) == LINK_REGISTER_REGNUM)
cccf3bdc
DE		 9555 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9556 else
9557 fputs ("ctr", file);
9558 return;
9559
9854d9ed 9560 case 'u':
802a0058 9561 /* High-order 16 bits of constant for use in unsigned operand. */
9854d9ed
RK		 9562 if (! INT_P (x))
9563 output_operand_lossage ("invalid %%u value");
e2c953b6 9564 else
f676971a 9565 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
e2c953b6 9566 (INT_LOWPART (x) >> 16) & 0xffff);
9878760c
RK		 9567 return;
9568
802a0058
MM		 9569 case 'v':
9570 /* High-order 16 bits of constant for use in signed operand. */
9571 if (! INT_P (x))
9572 output_operand_lossage ("invalid %%v value");
e2c953b6 9573 else
134c32f6
DE		 9574 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9575 (INT_LOWPART (x) >> 16) & 0xffff);
9576 return;
802a0058 9577
9854d9ed
RK		 9578 case 'U':
9579 /* Print `u' if this has an auto-increment or auto-decrement. */
9580 if (GET_CODE (x) == MEM
9581 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9582 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
76229ac8 9583 putc ('u', file);
9854d9ed 9584 return;
9878760c 9585
e0cd0770
JC		 9586 case 'V':
9587 /* Print the trap code for this operand. */
9588 switch (GET_CODE (x))
9589 {
9590 case EQ:
9591 fputs ("eq", file); /* 4 */
9592 break;
9593 case NE:
9594 fputs ("ne", file); /* 24 */
9595 break;
9596 case LT:
9597 fputs ("lt", file); /* 16 */
9598 break;
9599 case LE:
9600 fputs ("le", file); /* 20 */
9601 break;
9602 case GT:
9603 fputs ("gt", file); /* 8 */
9604 break;
9605 case GE:
9606 fputs ("ge", file); /* 12 */
9607 break;
9608 case LTU:
9609 fputs ("llt", file); /* 2 */
9610 break;
9611 case LEU:
9612 fputs ("lle", file); /* 6 */
9613 break;
9614 case GTU:
9615 fputs ("lgt", file); /* 1 */
9616 break;
9617 case GEU:
9618 fputs ("lge", file); /* 5 */
9619 break;
9620 default:
9621 abort ();
9622 }
9623 break;
9624
9854d9ed
RK		 9625 case 'w':
9626 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9627 normally. */
9628 if (INT_P (x))
f676971a 9629 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5f59ecb7 9630 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9854d9ed
RK		 9631 else
9632 print_operand (file, x, 0);
9878760c
RK		 9633 return;
9634
9854d9ed 9635 case 'W':
e2c953b6 9636 /* MB value for a PowerPC64 rldic operand. */
e2c953b6
DE		 9637 val = (GET_CODE (x) == CONST_INT
9638 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9639
9640 if (val < 0)
9641 i = -1;
9854d9ed 9642 else
e2c953b6
DE		 9643 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9644 if ((val <<= 1) < 0)
9645 break;
9646
9647#if HOST_BITS_PER_WIDE_INT == 32
9648 if (GET_CODE (x) == CONST_INT && i >= 0)
9649 i += 32; /* zero-extend high-part was all 0's */
9650 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9651 {
9652 val = CONST_DOUBLE_LOW (x);
9653
9654 if (val == 0)
a4f6c312 9655 abort ();
e2c953b6
DE		 9656 else if (val < 0)
9657 --i;
9658 else
9659 for ( ; i < 64; i++)
9660 if ((val <<= 1) < 0)
9661 break;
9662 }
9663#endif
9664
9665 fprintf (file, "%d", i + 1);
9854d9ed 9666 return;
9878760c 9667
9854d9ed
RK		 9668 case 'X':
9669 if (GET_CODE (x) == MEM
4d588c14 9670 && legitimate_indexed_address_p (XEXP (x, 0), 0))
76229ac8 9671 putc ('x', file);
9854d9ed 9672 return;
9878760c 9673
9854d9ed
RK		 9674 case 'Y':
9675 /* Like 'L', for third word of TImode */
9676 if (GET_CODE (x) == REG)
fb5c67a7 9677 fputs (reg_names[REGNO (x) + 2], file);
9854d9ed 9678 else if (GET_CODE (x) == MEM)
9878760c 9679 {
9854d9ed
RK		 9680 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9681 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 9682 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9854d9ed 9683 else
d7624dc0 9684 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
ba5e43aa 9685 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9686 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9687 reg_names[SMALL_DATA_REG]);
9878760c
RK		 9688 }
9689 return;
f676971a 9690
9878760c 9691 case 'z':
b4ac57ab
RS		 9692 /* X is a SYMBOL_REF. Write out the name preceded by a
9693 period and without any trailing data in brackets. Used for function
4d30c363
MM		 9694 names. If we are configured for System V (or the embedded ABI) on
9695 the PowerPC, do not emit the period, since those systems do not use
9696 TOCs and the like. */
9878760c
RK		 9697 if (GET_CODE (x) != SYMBOL_REF)
9698 abort ();
9699
c4ad648e
AM		 9700 /* Mark the decl as referenced so that cgraph will output the
9701 function. */
9bf6462a 9702 if (SYMBOL_REF_DECL (x))
c4ad648e 9703 mark_decl_referenced (SYMBOL_REF_DECL (x));
9bf6462a 9704
85b776df 9705 /* For macho, check to see if we need a stub. */
f9da97f0
AP		 9706 if (TARGET_MACHO)
9707 {
9708 const char *name = XSTR (x, 0);
a031e781 9709#if TARGET_MACHO
3b48085e 9710 if (MACHOPIC_INDIRECT
11abc112
MM		 9711 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9712 name = machopic_indirection_name (x, /*stub_p=*/true);
f9da97f0
AP		 9713#endif
9714 assemble_name (file, name);
9715 }
85b776df 9716 else if (!DOT_SYMBOLS)
9739c90c 9717 assemble_name (file, XSTR (x, 0));
85b776df
AM		 9718 else
9719 rs6000_output_function_entry (file, XSTR (x, 0));
9878760c
RK		 9720 return;
9721
9854d9ed
RK		 9722 case 'Z':
9723 /* Like 'L', for last word of TImode. */
9724 if (GET_CODE (x) == REG)
fb5c67a7 9725 fputs (reg_names[REGNO (x) + 3], file);
9854d9ed
RK		 9726 else if (GET_CODE (x) == MEM)
9727 {
9728 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9729 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 9730 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9854d9ed 9731 else
d7624dc0 9732 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
ba5e43aa 9733 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9734 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9735 reg_names[SMALL_DATA_REG]);
9854d9ed 9736 }
5c23c401 9737 return;
0ac081f6 9738
a3170dc6 9739 /* Print AltiVec or SPE memory operand. */
0ac081f6
AH		 9740 case 'y':
9741 {
9742 rtx tmp;
9743
9744 if (GET_CODE (x) != MEM)
9745 abort ();
9746
9747 tmp = XEXP (x, 0);
9748
993f19a8 9749 if (TARGET_E500)
a3170dc6
AH		 9750 {
9751 /* Handle [reg]. */
9752 if (GET_CODE (tmp) == REG)
9753 {
9754 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9755 break;
9756 }
9757 /* Handle [reg+UIMM]. */
9758 else if (GET_CODE (tmp) == PLUS &&
9759 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9760 {
9761 int x;
9762
9763 if (GET_CODE (XEXP (tmp, 0)) != REG)
9764 abort ();
9765
9766 x = INTVAL (XEXP (tmp, 1));
9767 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9768 break;
9769 }
9770
9771 /* Fall through. Must be [reg+reg]. */
9772 }
850e8d3d
DN		 9773 if (TARGET_ALTIVEC
9774 && GET_CODE (tmp) == AND
9775 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
9776 && INTVAL (XEXP (tmp, 1)) == -16)
9777 tmp = XEXP (tmp, 0);
0ac081f6 9778 if (GET_CODE (tmp) == REG)
c62f2db5 9779 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
0ac081f6
AH		 9780 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9781 {
9782 if (REGNO (XEXP (tmp, 0)) == 0)
9783 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9784 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9785 else
9786 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9787 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9788 }
9789 else
9790 abort ();
9791 break;
9792 }
f676971a 9793
9878760c
RK		 9794 case 0:
9795 if (GET_CODE (x) == REG)
9796 fprintf (file, "%s", reg_names[REGNO (x)]);
9797 else if (GET_CODE (x) == MEM)
9798 {
9799 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9800 know the width from the mode. */
9801 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
79ba6d34
MM		 9802 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9803 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 9804 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
79ba6d34
MM		 9805 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9806 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 9807 else
a54d04b7 9808 output_address (XEXP (x, 0));
9878760c
RK		 9809 }
9810 else
a54d04b7 9811 output_addr_const (file, x);
a85d226b 9812 return;
9878760c 9813
c4501e62
JJ		 9814 case '&':
9815 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9816 return;
9817
9878760c
RK		 9818 default:
9819 output_operand_lossage ("invalid %%xn code");
9820 }
9821}
9822\f
9823/* Print the address of an operand. */
9824
9825void
a2369ed3 9826print_operand_address (FILE *file, rtx x)
9878760c
RK		 9827{
9828 if (GET_CODE (x) == REG)
4697a36c 9829 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9ebbca7d
GK		 9830 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9831 || GET_CODE (x) == LABEL_REF)
9878760c
RK		 9832 {
9833 output_addr_const (file, x);
ba5e43aa 9834 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9835 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9836 reg_names[SMALL_DATA_REG]);
9ebbca7d 9837 else if (TARGET_TOC)
a4f6c312 9838 abort ();
9878760c
RK		 9839 }
9840 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9841 {
9842 if (REGNO (XEXP (x, 0)) == 0)
4697a36c
MM		 9843 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9844 reg_names[ REGNO (XEXP (x, 0)) ]);
9878760c 9845 else
4697a36c
MM		 9846 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9847 reg_names[ REGNO (XEXP (x, 1)) ]);
9878760c
RK		 9848 }
9849 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
4a0a75dd
KG		 9850 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9851 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
3cb999d8
DE		 9852#if TARGET_ELF
9853 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 9854 && CONSTANT_P (XEXP (x, 1)))
4697a36c
MM		 9855 {
9856 output_addr_const (file, XEXP (x, 1));
9857 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9858 }
c859cda6
DJ		 9859#endif
9860#if TARGET_MACHO
9861 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 9862 && CONSTANT_P (XEXP (x, 1)))
c859cda6
DJ		 9863 {
9864 fprintf (file, "lo16(");
9865 output_addr_const (file, XEXP (x, 1));
9866 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9867 }
3cb999d8 9868#endif
4d588c14 9869 else if (legitimate_constant_pool_address_p (x))
9ebbca7d 9870 {
2bfcf297 9871 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9ebbca7d 9872 {
2bfcf297
DB		 9873 rtx contains_minus = XEXP (x, 1);
9874 rtx minus, symref;
9875 const char *name;
f676971a 9876
9ebbca7d 9877 /* Find the (minus (sym) (toc)) buried in X, and temporarily
a4f6c312 9878 turn it into (sym) for output_addr_const. */
9ebbca7d
GK		 9879 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9880 contains_minus = XEXP (contains_minus, 0);
9881
2bfcf297
DB		 9882 minus = XEXP (contains_minus, 0);
9883 symref = XEXP (minus, 0);
9884 XEXP (contains_minus, 0) = symref;
9885 if (TARGET_ELF)
9886 {
9887 char *newname;
9888
9889 name = XSTR (symref, 0);
9890 newname = alloca (strlen (name) + sizeof ("@toc"));
9891 strcpy (newname, name);
9892 strcat (newname, "@toc");
9893 XSTR (symref, 0) = newname;
9894 }
9895 output_addr_const (file, XEXP (x, 1));
9896 if (TARGET_ELF)
9897 XSTR (symref, 0) = name;
9ebbca7d
GK		 9898 XEXP (contains_minus, 0) = minus;
9899 }
9900 else
9901 output_addr_const (file, XEXP (x, 1));
9902
9903 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9904 }
9878760c
RK		 9905 else
9906 abort ();
9907}
9908\f
88cad84b 9909/* Target hook for assembling integer objects. The PowerPC version has
301d03af
RS		 9910 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9911 is defined. It also needs to handle DI-mode objects on 64-bit
9912 targets. */
9913
9914static bool
a2369ed3 9915rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
301d03af 9916{
f4f4921e 9917#ifdef RELOCATABLE_NEEDS_FIXUP
301d03af 9918 /* Special handling for SI values. */
84dcde01 9919 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
301d03af 9920 {
a2369ed3 9921 extern int in_toc_section (void);
301d03af 9922 static int recurse = 0;
f676971a 9923
301d03af
RS		 9924 /* For -mrelocatable, we mark all addresses that need to be fixed up
9925 in the .fixup section. */
9926 if (TARGET_RELOCATABLE
9927 && !in_toc_section ()
9928 && !in_text_section ()
642af3be 9929 && !in_unlikely_text_section ()
301d03af
RS		 9930 && !recurse
9931 && GET_CODE (x) != CONST_INT
9932 && GET_CODE (x) != CONST_DOUBLE
9933 && CONSTANT_P (x))
9934 {
9935 char buf[256];
9936
9937 recurse = 1;
9938 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9939 fixuplabelno++;
9940 ASM_OUTPUT_LABEL (asm_out_file, buf);
9941 fprintf (asm_out_file, "\t.long\t(");
9942 output_addr_const (asm_out_file, x);
9943 fprintf (asm_out_file, ")@fixup\n");
9944 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9945 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9946 fprintf (asm_out_file, "\t.long\t");
9947 assemble_name (asm_out_file, buf);
9948 fprintf (asm_out_file, "\n\t.previous\n");
9949 recurse = 0;
9950 return true;
9951 }
9952 /* Remove initial .'s to turn a -mcall-aixdesc function
9953 address into the address of the descriptor, not the function
9954 itself. */
9955 else if (GET_CODE (x) == SYMBOL_REF
9956 && XSTR (x, 0)[0] == '.'
9957 && DEFAULT_ABI == ABI_AIX)
9958 {
9959 const char *name = XSTR (x, 0);
9960 while (*name == '.')
9961 name++;
9962
9963 fprintf (asm_out_file, "\t.long\t%s\n", name);
9964 return true;
9965 }
9966 }
f4f4921e 9967#endif /* RELOCATABLE_NEEDS_FIXUP */
301d03af
RS		 9968 return default_assemble_integer (x, size, aligned_p);
9969}
93638d7a
AM		 9970
9971#ifdef HAVE_GAS_HIDDEN
9972/* Emit an assembler directive to set symbol visibility for DECL to
9973 VISIBILITY_TYPE. */
9974
5add3202 9975static void
a2369ed3 9976rs6000_assemble_visibility (tree decl, int vis)
93638d7a 9977{
93638d7a
AM		 9978 /* Functions need to have their entry point symbol visibility set as
9979 well as their descriptor symbol visibility. */
85b776df
AM		 9980 if (DEFAULT_ABI == ABI_AIX
9981 && DOT_SYMBOLS
9982 && TREE_CODE (decl) == FUNCTION_DECL)
93638d7a 9983 {
25fdb4dc 9984 static const char * const visibility_types[] = {
c4ad648e 9985 NULL, "internal", "hidden", "protected"
25fdb4dc
RH		 9986 };
9987
9988 const char *name, *type;
93638d7a
AM		 9989
9990 name = ((* targetm.strip_name_encoding)
9991 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
25fdb4dc 9992 type = visibility_types[vis];
93638d7a 9993
25fdb4dc
RH		 9994 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9995 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
93638d7a 9996 }
25fdb4dc
RH		 9997 else
9998 default_assemble_visibility (decl, vis);
93638d7a
AM		 9999}
10000#endif
301d03af 10001\f
39a10a29 10002enum rtx_code
a2369ed3 10003rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
39a10a29
GK		 10004{
10005 /* Reversal of FP compares takes care -- an ordered compare
10006 becomes an unordered compare and vice versa. */
f676971a 10007 if (mode == CCFPmode
bc9ec0e0
GK		 10008 && (!flag_finite_math_only
10009 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10010 || code == UNEQ || code == LTGT))
bab6226b 10011 return reverse_condition_maybe_unordered (code);
39a10a29 10012 else
bab6226b 10013 return reverse_condition (code);
39a10a29
GK		 10014}
10015
39a10a29
GK		 10016/* Generate a compare for CODE. Return a brand-new rtx that
10017 represents the result of the compare. */
a4f6c312 10018
39a10a29 10019static rtx
a2369ed3 10020rs6000_generate_compare (enum rtx_code code)
39a10a29
GK		 10021{
10022 enum machine_mode comp_mode;
10023 rtx compare_result;
10024
10025 if (rs6000_compare_fp_p)
10026 comp_mode = CCFPmode;
10027 else if (code == GTU || code == LTU
c4ad648e 10028 || code == GEU || code == LEU)
39a10a29 10029 comp_mode = CCUNSmode;
60934f9c
NS		 10030 else if ((code == EQ || code == NE)
10031 && GET_CODE (rs6000_compare_op0) == SUBREG
10032 && GET_CODE (rs6000_compare_op1) == SUBREG
10033 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10034 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10035 /* These are unsigned values, perhaps there will be a later
10036 ordering compare that can be shared with this one.
10037 Unfortunately we cannot detect the signedness of the operands
10038 for non-subregs. */
10039 comp_mode = CCUNSmode;
39a10a29
GK		 10040 else
10041 comp_mode = CCmode;
10042
10043 /* First, the compare. */
10044 compare_result = gen_reg_rtx (comp_mode);
a3170dc6
AH		 10045
10046 /* SPE FP compare instructions on the GPRs. Yuck! */
993f19a8
AH		 10047 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10048 && rs6000_compare_fp_p)
a3170dc6 10049 {
64022b5d 10050 rtx cmp, or_result, compare_result2;
4d4cbc0e
AH		 10051 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10052
10053 if (op_mode == VOIDmode)
10054 op_mode = GET_MODE (rs6000_compare_op1);
a3170dc6 10055
423c1189
AH		 10056 /* Note: The E500 comparison instructions set the GT bit (x +
10057 1), on success. This explains the mess. */
10058
a3170dc6
AH		 10059 switch (code)
10060 {
423c1189 10061 case EQ: case UNEQ: case NE: case LTGT:
4d4cbc0e 10062 if (op_mode == SFmode)
5ca18999 10063 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10064 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10065 rs6000_compare_op1)
10066 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10067 rs6000_compare_op1);
10068 else if (op_mode == DFmode)
5ca18999 10069 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10070 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10071 rs6000_compare_op1)
10072 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10073 rs6000_compare_op1);
10074 else abort ();
a3170dc6 10075 break;
423c1189 10076 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
4d4cbc0e 10077 if (op_mode == SFmode)
5ca18999 10078 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10079 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10080 rs6000_compare_op1)
10081 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10082 rs6000_compare_op1);
10083 else if (op_mode == DFmode)
5ca18999 10084 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10085 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10086 rs6000_compare_op1)
10087 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10088 rs6000_compare_op1);
10089 else abort ();
a3170dc6 10090 break;
423c1189 10091 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
4d4cbc0e 10092 if (op_mode == SFmode)
5ca18999 10093 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10094 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10095 rs6000_compare_op1)
10096 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10097 rs6000_compare_op1);
10098 else if (op_mode == DFmode)
5ca18999 10099 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10100 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10101 rs6000_compare_op1)
10102 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10103 rs6000_compare_op1);
10104 else abort ();
a3170dc6 10105 break;
4d4cbc0e
AH		 10106 default:
10107 abort ();
a3170dc6
AH		 10108 }
10109
10110 /* Synthesize LE and GE from LT/GT || EQ. */
10111 if (code == LE || code == GE || code == LEU || code == GEU)
10112 {
a3170dc6
AH		 10113 emit_insn (cmp);
10114
10115 switch (code)
10116 {
10117 case LE: code = LT; break;
10118 case GE: code = GT; break;
10119 case LEU: code = LT; break;
10120 case GEU: code = GT; break;
10121 default: abort ();
10122 }
10123
a3170dc6
AH		 10124 compare_result2 = gen_reg_rtx (CCFPmode);
10125
10126 /* Do the EQ. */
4d4cbc0e 10127 if (op_mode == SFmode)
5ca18999 10128 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10129 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10130 rs6000_compare_op1)
10131 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10132 rs6000_compare_op1);
10133 else if (op_mode == DFmode)
5ca18999 10134 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10135 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10136 rs6000_compare_op1)
10137 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10138 rs6000_compare_op1);
10139 else abort ();
a3170dc6
AH		 10140 emit_insn (cmp);
10141
a3170dc6 10142 /* OR them together. */
64022b5d
AH		 10143 or_result = gen_reg_rtx (CCFPmode);
10144 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
10145 compare_result2);
a3170dc6
AH		 10146 compare_result = or_result;
10147 code = EQ;
10148 }
10149 else
10150 {
a3170dc6 10151 if (code == NE || code == LTGT)
a3170dc6 10152 code = NE;
423c1189
AH		 10153 else
10154 code = EQ;
a3170dc6
AH		 10155 }
10156
10157 emit_insn (cmp);
10158 }
10159 else
de17c25f
DE		 10160 {
10161 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10162 CLOBBERs to match cmptf_internal2 pattern. */
10163 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10164 && GET_MODE (rs6000_compare_op0) == TFmode
10165 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10166 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10167 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10168 gen_rtvec (9,
10169 gen_rtx_SET (VOIDmode,
10170 compare_result,
10171 gen_rtx_COMPARE (comp_mode,
10172 rs6000_compare_op0,
10173 rs6000_compare_op1)),
10174 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10175 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10176 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10177 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10178 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10179 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10180 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10181 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10182 else
10183 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10184 gen_rtx_COMPARE (comp_mode,
10185 rs6000_compare_op0,
10186 rs6000_compare_op1)));
10187 }
f676971a 10188
ca5adc63 10189 /* Some kinds of FP comparisons need an OR operation;
e7108df9 10190 under flag_finite_math_only we don't bother. */
39a10a29 10191 if (rs6000_compare_fp_p
e7108df9
DE		 10192 && !flag_finite_math_only
10193 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
39a10a29
GK		 10194 && (code == LE || code == GE
10195 || code == UNEQ || code == LTGT
10196 || code == UNGT || code == UNLT))
10197 {
10198 enum rtx_code or1, or2;
10199 rtx or1_rtx, or2_rtx, compare2_rtx;
10200 rtx or_result = gen_reg_rtx (CCEQmode);
f676971a 10201
39a10a29
GK		 10202 switch (code)
10203 {
10204 case LE: or1 = LT; or2 = EQ; break;
10205 case GE: or1 = GT; or2 = EQ; break;
10206 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10207 case LTGT: or1 = LT; or2 = GT; break;
10208 case UNGT: or1 = UNORDERED; or2 = GT; break;
10209 case UNLT: or1 = UNORDERED; or2 = LT; break;
10210 default: abort ();
10211 }
10212 validate_condition_mode (or1, comp_mode);
10213 validate_condition_mode (or2, comp_mode);
1c563bed
KH		 10214 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10215 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
39a10a29
GK		 10216 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10217 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10218 const_true_rtx);
10219 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10220
10221 compare_result = or_result;
10222 code = EQ;
10223 }
10224
10225 validate_condition_mode (code, GET_MODE (compare_result));
f676971a 10226
1c563bed 10227 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
39a10a29
GK		 10228}
10229
10230
10231/* Emit the RTL for an sCOND pattern. */
10232
10233void
a2369ed3 10234rs6000_emit_sCOND (enum rtx_code code, rtx result)
39a10a29
GK		 10235{
10236 rtx condition_rtx;
10237 enum machine_mode op_mode;
b7053a3f 10238 enum rtx_code cond_code;
39a10a29
GK		 10239
10240 condition_rtx = rs6000_generate_compare (code);
b7053a3f
GK		 10241 cond_code = GET_CODE (condition_rtx);
10242
423c1189
AH		 10243 if (TARGET_E500 && rs6000_compare_fp_p
10244 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10245 {
10246 rtx t;
10247
10248 PUT_MODE (condition_rtx, SImode);
10249 t = XEXP (condition_rtx, 0);
10250
10251 if (cond_code != NE && cond_code != EQ)
10252 abort ();
10253
10254 if (cond_code == NE)
64022b5d 10255 emit_insn (gen_e500_flip_gt_bit (t, t));
423c1189 10256
64022b5d 10257 emit_insn (gen_move_from_CR_gt_bit (result, t));
423c1189
AH		 10258 return;
10259 }
10260
b7053a3f
GK		 10261 if (cond_code == NE
10262 || cond_code == GE || cond_code == LE
10263 || cond_code == GEU || cond_code == LEU
10264 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10265 {
10266 rtx not_result = gen_reg_rtx (CCEQmode);
10267 rtx not_op, rev_cond_rtx;
10268 enum machine_mode cc_mode;
f676971a 10269
b7053a3f
GK		 10270 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10271
1c563bed 10272 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
0f4c242b 10273 SImode, XEXP (condition_rtx, 0), const0_rtx);
b7053a3f
GK		 10274 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10275 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10276 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10277 }
39a10a29
GK		 10278
10279 op_mode = GET_MODE (rs6000_compare_op0);
10280 if (op_mode == VOIDmode)
10281 op_mode = GET_MODE (rs6000_compare_op1);
10282
10283 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10284 {
10285 PUT_MODE (condition_rtx, DImode);
10286 convert_move (result, condition_rtx, 0);
10287 }
10288 else
10289 {
10290 PUT_MODE (condition_rtx, SImode);
10291 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10292 }
10293}
10294
39a10a29
GK		 10295/* Emit a branch of kind CODE to location LOC. */
10296
10297void
a2369ed3 10298rs6000_emit_cbranch (enum rtx_code code, rtx loc)
39a10a29
GK		 10299{
10300 rtx condition_rtx, loc_ref;
10301
10302 condition_rtx = rs6000_generate_compare (code);
10303 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10304 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10305 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10306 loc_ref, pc_rtx)));
10307}
10308
12a4e8c5
GK		 10309/* Return the string to output a conditional branch to LABEL, which is
10310 the operand number of the label, or -1 if the branch is really a
f676971a 10311 conditional return.
12a4e8c5
GK		 10312
10313 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10314 condition code register and its mode specifies what kind of
10315 comparison we made.
10316
a0ab749a 10317 REVERSED is nonzero if we should reverse the sense of the comparison.
12a4e8c5
GK		 10318
10319 INSN is the insn. */
10320
10321char *
a2369ed3 10322output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12a4e8c5
GK		 10323{
10324 static char string[64];
10325 enum rtx_code code = GET_CODE (op);
10326 rtx cc_reg = XEXP (op, 0);
10327 enum machine_mode mode = GET_MODE (cc_reg);
10328 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
39a10a29 10329 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12a4e8c5
GK		 10330 int really_reversed = reversed ^ need_longbranch;
10331 char *s = string;
10332 const char *ccode;
10333 const char *pred;
10334 rtx note;
10335
39a10a29
GK		 10336 validate_condition_mode (code, mode);
10337
10338 /* Work out which way this really branches. We could use
10339 reverse_condition_maybe_unordered here always but this
10340 makes the resulting assembler clearer. */
12a4e8c5 10341 if (really_reversed)
de40e1df
DJ		 10342 {
10343 /* Reversal of FP compares takes care -- an ordered compare
10344 becomes an unordered compare and vice versa. */
10345 if (mode == CCFPmode)
10346 code = reverse_condition_maybe_unordered (code);
10347 else
10348 code = reverse_condition (code);
10349 }
12a4e8c5 10350
993f19a8 10351 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
a3170dc6
AH		 10352 {
10353 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10354 to the GT bit. */
10355 if (code == EQ)
10356 /* Opposite of GT. */
a3170dc6 10357 code = GT;
423c1189
AH		 10358 else if (code == NE)
10359 code = UNLE;
a3170dc6
AH		 10360 else
10361 abort ();
10362 }
10363
39a10a29 10364 switch (code)
12a4e8c5
GK		 10365 {
10366 /* Not all of these are actually distinct opcodes, but
10367 we distinguish them for clarity of the resulting assembler. */
50a0b056
GK		 10368 case NE: case LTGT:
10369 ccode = "ne"; break;
10370 case EQ: case UNEQ:
10371 ccode = "eq"; break;
f676971a 10372 case GE: case GEU:
50a0b056 10373 ccode = "ge"; break;
f676971a 10374 case GT: case GTU: case UNGT:
50a0b056 10375 ccode = "gt"; break;
f676971a 10376 case LE: case LEU:
50a0b056 10377 ccode = "le"; break;
f676971a 10378 case LT: case LTU: case UNLT:
50a0b056 10379 ccode = "lt"; break;
12a4e8c5
GK		 10380 case UNORDERED: ccode = "un"; break;
10381 case ORDERED: ccode = "nu"; break;
10382 case UNGE: ccode = "nl"; break;
10383 case UNLE: ccode = "ng"; break;
10384 default:
a4f6c312 10385 abort ();
12a4e8c5 10386 }
f676971a
EC		 10387
10388 /* Maybe we have a guess as to how likely the branch is.
94a54f47 10389 The old mnemonics don't have a way to specify this information. */
f4857b9b 10390 pred = "";
12a4e8c5
GK		 10391 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10392 if (note != NULL_RTX)
10393 {
10394 /* PROB is the difference from 50%. */
10395 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
f4857b9b
AM		 10396
10397 /* Only hint for highly probable/improbable branches on newer
10398 cpus as static prediction overrides processor dynamic
10399 prediction. For older cpus we may as well always hint, but
10400 assume not taken for branches that are very close to 50% as a
10401 mispredicted taken branch is more expensive than a
f676971a 10402 mispredicted not-taken branch. */
ec507f2d 10403 if (rs6000_always_hint
f4857b9b
AM		 10404 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10405 {
10406 if (abs (prob) > REG_BR_PROB_BASE / 20
10407 && ((prob > 0) ^ need_longbranch))
c4ad648e 10408 pred = "+";
f4857b9b
AM		 10409 else
10410 pred = "-";
10411 }
12a4e8c5 10412 }
12a4e8c5
GK		 10413
10414 if (label == NULL)
94a54f47 10415 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12a4e8c5 10416 else
94a54f47 10417 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12a4e8c5 10418
37c67319 10419 /* We need to escape any '%' characters in the reg_names string.
a3c9585f 10420 Assume they'd only be the first character.... */
37c67319
GK		 10421 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10422 *s++ = '%';
94a54f47 10423 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12a4e8c5
GK		 10424
10425 if (label != NULL)
10426 {
10427 /* If the branch distance was too far, we may have to use an
10428 unconditional branch to go the distance. */
10429 if (need_longbranch)
44518ddd 10430 s += sprintf (s, ",$+8\n\tb %s", label);
12a4e8c5
GK		 10431 else
10432 s += sprintf (s, ",%s", label);
10433 }
10434
10435 return string;
10436}
50a0b056 10437
64022b5d 10438/* Return the string to flip the GT bit on a CR. */
423c1189 10439char *
64022b5d 10440output_e500_flip_gt_bit (rtx dst, rtx src)
423c1189
AH		 10441{
10442 static char string[64];
10443 int a, b;
10444
10445 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
10446 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
10447 abort ();
10448
64022b5d
AH		 10449 /* GT bit. */
10450 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10451 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
423c1189
AH		 10452
10453 sprintf (string, "crnot %d,%d", a, b);
10454 return string;
10455}
10456
21213b4c
DP		 10457/* Return insn index for the vector compare instruction for given CODE,
10458 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10459 not available. */
10460
10461static int
94ff898d 10462get_vec_cmp_insn (enum rtx_code code,
21213b4c
DP		 10463 enum machine_mode dest_mode,
10464 enum machine_mode op_mode)
10465{
10466 if (!TARGET_ALTIVEC)
10467 return INSN_NOT_AVAILABLE;
10468
10469 switch (code)
10470 {
10471 case EQ:
10472 if (dest_mode == V16QImode && op_mode == V16QImode)
10473 return UNSPEC_VCMPEQUB;
10474 if (dest_mode == V8HImode && op_mode == V8HImode)
10475 return UNSPEC_VCMPEQUH;
10476 if (dest_mode == V4SImode && op_mode == V4SImode)
10477 return UNSPEC_VCMPEQUW;
10478 if (dest_mode == V4SImode && op_mode == V4SFmode)
10479 return UNSPEC_VCMPEQFP;
10480 break;
10481 case GE:
10482 if (dest_mode == V4SImode && op_mode == V4SFmode)
10483 return UNSPEC_VCMPGEFP;
10484 case GT:
10485 if (dest_mode == V16QImode && op_mode == V16QImode)
10486 return UNSPEC_VCMPGTSB;
10487 if (dest_mode == V8HImode && op_mode == V8HImode)
10488 return UNSPEC_VCMPGTSH;
10489 if (dest_mode == V4SImode && op_mode == V4SImode)
10490 return UNSPEC_VCMPGTSW;
10491 if (dest_mode == V4SImode && op_mode == V4SFmode)
10492 return UNSPEC_VCMPGTFP;
10493 break;
10494 case GTU:
10495 if (dest_mode == V16QImode && op_mode == V16QImode)
10496 return UNSPEC_VCMPGTUB;
10497 if (dest_mode == V8HImode && op_mode == V8HImode)
10498 return UNSPEC_VCMPGTUH;
10499 if (dest_mode == V4SImode && op_mode == V4SImode)
10500 return UNSPEC_VCMPGTUW;
10501 break;
10502 default:
10503 break;
10504 }
10505 return INSN_NOT_AVAILABLE;
10506}
10507
10508/* Emit vector compare for operands OP0 and OP1 using code RCODE.
10509 DMODE is expected destination mode. This is a recursive function. */
10510
10511static rtx
10512rs6000_emit_vector_compare (enum rtx_code rcode,
10513 rtx op0, rtx op1,
10514 enum machine_mode dmode)
10515{
10516 int vec_cmp_insn;
10517 rtx mask;
10518 enum machine_mode dest_mode;
10519 enum machine_mode op_mode = GET_MODE (op1);
10520
10521#ifdef ENABLE_CHECKING
10522 if (!TARGET_ALTIVEC)
10523 abort ();
10524
10525 if (GET_MODE (op0) != GET_MODE (op1))
10526 abort ();
10527#endif
10528
10529 /* Floating point vector compare instructions uses destination V4SImode.
10530 Move destination to appropriate mode later. */
10531 if (dmode == V4SFmode)
10532 dest_mode = V4SImode;
10533 else
10534 dest_mode = dmode;
10535
10536 mask = gen_reg_rtx (dest_mode);
10537 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10538
10539 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10540 {
10541 bool swap_operands = false;
10542 bool try_again = false;
10543 switch (rcode)
10544 {
10545 case LT:
10546 rcode = GT;
10547 swap_operands = true;
10548 try_again = true;
10549 break;
10550 case LTU:
10551 rcode = GTU;
10552 swap_operands = true;
10553 try_again = true;
10554 break;
10555 case NE:
10556 /* Treat A != B as ~(A==B). */
10557 {
10558 enum insn_code nor_code;
10559 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10560 dest_mode);
94ff898d 10561
21213b4c
DP		 10562 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
10563 if (nor_code == CODE_FOR_nothing)
10564 abort ();
10565 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10566
10567 if (dmode != dest_mode)
10568 {
10569 rtx temp = gen_reg_rtx (dest_mode);
10570 convert_move (temp, mask, 0);
10571 return temp;
10572 }
10573 return mask;
10574 }
10575 break;
10576 case GE:
10577 case GEU:
10578 case LE:
10579 case LEU:
10580 /* Try GT/GTU/LT/LTU OR EQ */
10581 {
10582 rtx c_rtx, eq_rtx;
10583 enum insn_code ior_code;
10584 enum rtx_code new_code;
10585
10586 if (rcode == GE)
10587 new_code = GT;
10588 else if (rcode == GEU)
10589 new_code = GTU;
10590 else if (rcode == LE)
10591 new_code = LT;
10592 else if (rcode == LEU)
10593 new_code = LTU;
10594 else
10595 abort ();
10596
10597 c_rtx = rs6000_emit_vector_compare (new_code,
10598 op0, op1, dest_mode);
10599 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10600 dest_mode);
10601
10602 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
10603 if (ior_code == CODE_FOR_nothing)
10604 abort ();
10605 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
10606 if (dmode != dest_mode)
10607 {
10608 rtx temp = gen_reg_rtx (dest_mode);
10609 convert_move (temp, mask, 0);
10610 return temp;
10611 }
10612 return mask;
10613 }
10614 break;
10615 default:
10616 abort ();
10617 }
10618
10619 if (try_again)
10620 {
10621 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10622 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10623 /* You only get two chances. */
10624 abort ();
10625 }
10626
10627 if (swap_operands)
10628 {
10629 rtx tmp;
10630 tmp = op0;
10631 op0 = op1;
10632 op1 = tmp;
10633 }
10634 }
10635
10636 emit_insn (gen_rtx_fmt_ee (SET,
10637 VOIDmode,
10638 mask,
10639 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10640 gen_rtvec (2, op0, op1),
10641 vec_cmp_insn)));
10642 if (dmode != dest_mode)
10643 {
10644 rtx temp = gen_reg_rtx (dest_mode);
10645 convert_move (temp, mask, 0);
10646 return temp;
10647 }
10648 return mask;
10649}
10650
10651/* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
10652 valid insn doesn exist for given mode. */
10653
10654static int
10655get_vsel_insn (enum machine_mode mode)
10656{
10657 switch (mode)
10658 {
10659 case V4SImode:
10660 return UNSPEC_VSEL4SI;
10661 break;
10662 case V4SFmode:
10663 return UNSPEC_VSEL4SF;
10664 break;
10665 case V8HImode:
10666 return UNSPEC_VSEL8HI;
10667 break;
10668 case V16QImode:
10669 return UNSPEC_VSEL16QI;
10670 break;
10671 default:
10672 return INSN_NOT_AVAILABLE;
10673 break;
10674 }
10675 return INSN_NOT_AVAILABLE;
10676}
10677
10678/* Emit vector select insn where DEST is destination using
10679 operands OP1, OP2 and MASK. */
10680
10681static void
10682rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
10683{
10684 rtx t, temp;
10685 enum machine_mode dest_mode = GET_MODE (dest);
10686 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
10687
10688 temp = gen_reg_rtx (dest_mode);
94ff898d 10689
21213b4c
DP		 10690 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
10691 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10692 gen_rtvec (3, op1, op2, mask),
10693 vsel_insn_index));
10694 emit_insn (t);
10695 emit_move_insn (dest, temp);
10696 return;
10697}
10698
94ff898d 10699/* Emit vector conditional expression.
21213b4c
DP		 10700 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
10701 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
10702
10703int
10704rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
10705 rtx cond, rtx cc_op0, rtx cc_op1)
10706{
10707 enum machine_mode dest_mode = GET_MODE (dest);
10708 enum rtx_code rcode = GET_CODE (cond);
10709 rtx mask;
10710
10711 if (!TARGET_ALTIVEC)
10712 return 0;
10713
10714 /* Get the vector mask for the given relational operations. */
10715 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
10716
10717 rs6000_emit_vector_select (dest, op1, op2, mask);
10718
10719 return 1;
10720}
10721
50a0b056
GK		 10722/* Emit a conditional move: move TRUE_COND to DEST if OP of the
10723 operands of the last comparison is nonzero/true, FALSE_COND if it
10724 is zero/false. Return 0 if the hardware has no such operation. */
a4f6c312 10725
50a0b056 10726int
a2369ed3 10727rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
50a0b056
GK		 10728{
10729 enum rtx_code code = GET_CODE (op);
10730 rtx op0 = rs6000_compare_op0;
10731 rtx op1 = rs6000_compare_op1;
10732 REAL_VALUE_TYPE c1;
3148ad6d
DJ		 10733 enum machine_mode compare_mode = GET_MODE (op0);
10734 enum machine_mode result_mode = GET_MODE (dest);
50a0b056 10735 rtx temp;
add2402e 10736 bool is_against_zero;
50a0b056 10737
a3c9585f 10738 /* These modes should always match. */
a3170dc6
AH		 10739 if (GET_MODE (op1) != compare_mode
10740 /* In the isel case however, we can use a compare immediate, so
10741 op1 may be a small constant. */
10742 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
3148ad6d 10743 return 0;
178c3eff 10744 if (GET_MODE (true_cond) != result_mode)
3148ad6d 10745 return 0;
178c3eff 10746 if (GET_MODE (false_cond) != result_mode)
3148ad6d
DJ		 10747 return 0;
10748
50a0b056 10749 /* First, work out if the hardware can do this at all, or
a3c9585f 10750 if it's too slow.... */
50a0b056 10751 if (! rs6000_compare_fp_p)
a3170dc6
AH		 10752 {
10753 if (TARGET_ISEL)
10754 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
10755 return 0;
10756 }
fef98bf2
AH		 10757 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
10758 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
10759 return 0;
50a0b056 10760
add2402e 10761 is_against_zero = op1 == CONST0_RTX (compare_mode);
94ff898d 10762
add2402e
GK		 10763 /* A floating-point subtract might overflow, underflow, or produce
10764 an inexact result, thus changing the floating-point flags, so it
10765 can't be generated if we care about that. It's safe if one side
10766 of the construct is zero, since then no subtract will be
10767 generated. */
10768 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
10769 && flag_trapping_math && ! is_against_zero)
10770 return 0;
10771
50a0b056
GK		 10772 /* Eliminate half of the comparisons by switching operands, this
10773 makes the remaining code simpler. */
10774 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
bc9ec0e0 10775 || code == LTGT || code == LT || code == UNLE)
50a0b056
GK		 10776 {
10777 code = reverse_condition_maybe_unordered (code);
10778 temp = true_cond;
10779 true_cond = false_cond;
10780 false_cond = temp;
10781 }
10782
10783 /* UNEQ and LTGT take four instructions for a comparison with zero,
10784 it'll probably be faster to use a branch here too. */
bc9ec0e0 10785 if (code == UNEQ && HONOR_NANS (compare_mode))
50a0b056 10786 return 0;
f676971a 10787
50a0b056
GK		 10788 if (GET_CODE (op1) == CONST_DOUBLE)
10789 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
f676971a 10790
b6d08ca1 10791 /* We're going to try to implement comparisons by performing
50a0b056
GK		 10792 a subtract, then comparing against zero. Unfortunately,
10793 Inf - Inf is NaN which is not zero, and so if we don't
27d30956 10794 know that the operand is finite and the comparison
50a0b056 10795 would treat EQ different to UNORDERED, we can't do it. */
bc9ec0e0 10796 if (HONOR_INFINITIES (compare_mode)
50a0b056 10797 && code != GT && code != UNGE
045572c7 10798 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
50a0b056
GK		 10799 /* Constructs of the form (a OP b ? a : b) are safe. */
10800 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
f676971a 10801 || (! rtx_equal_p (op0, true_cond)
50a0b056
GK		 10802 && ! rtx_equal_p (op1, true_cond))))
10803 return 0;
add2402e 10804
50a0b056
GK		 10805 /* At this point we know we can use fsel. */
10806
10807 /* Reduce the comparison to a comparison against zero. */
add2402e
GK		 10808 if (! is_against_zero)
10809 {
10810 temp = gen_reg_rtx (compare_mode);
10811 emit_insn (gen_rtx_SET (VOIDmode, temp,
10812 gen_rtx_MINUS (compare_mode, op0, op1)));
10813 op0 = temp;
10814 op1 = CONST0_RTX (compare_mode);
10815 }
50a0b056
GK		 10816
10817 /* If we don't care about NaNs we can reduce some of the comparisons
10818 down to faster ones. */
bc9ec0e0 10819 if (! HONOR_NANS (compare_mode))
50a0b056
GK		 10820 switch (code)
10821 {
10822 case GT:
10823 code = LE;
10824 temp = true_cond;
10825 true_cond = false_cond;
10826 false_cond = temp;
10827 break;
10828 case UNGE:
10829 code = GE;
10830 break;
10831 case UNEQ:
10832 code = EQ;
10833 break;
10834 default:
10835 break;
10836 }
10837
10838 /* Now, reduce everything down to a GE. */
10839 switch (code)
10840 {
10841 case GE:
10842 break;
10843
10844 case LE:
3148ad6d
DJ		 10845 temp = gen_reg_rtx (compare_mode);
10846 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 10847 op0 = temp;
10848 break;
10849
10850 case ORDERED:
3148ad6d
DJ		 10851 temp = gen_reg_rtx (compare_mode);
10852 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
50a0b056
GK		 10853 op0 = temp;
10854 break;
10855
10856 case EQ:
3148ad6d 10857 temp = gen_reg_rtx (compare_mode);
f676971a 10858 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d
DJ		 10859 gen_rtx_NEG (compare_mode,
10860 gen_rtx_ABS (compare_mode, op0))));
50a0b056
GK		 10861 op0 = temp;
10862 break;
10863
10864 case UNGE:
bc9ec0e0 10865 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
3148ad6d 10866 temp = gen_reg_rtx (result_mode);
50a0b056 10867 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d 10868 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 10869 gen_rtx_GE (VOIDmode,
10870 op0, op1),
10871 true_cond, false_cond)));
bc9ec0e0
GK		 10872 false_cond = true_cond;
10873 true_cond = temp;
50a0b056 10874
3148ad6d
DJ		 10875 temp = gen_reg_rtx (compare_mode);
10876 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 10877 op0 = temp;
10878 break;
10879
10880 case GT:
bc9ec0e0 10881 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
3148ad6d 10882 temp = gen_reg_rtx (result_mode);
50a0b056 10883 emit_insn (gen_rtx_SET (VOIDmode, temp,
f676971a 10884 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 10885 gen_rtx_GE (VOIDmode,
10886 op0, op1),
10887 true_cond, false_cond)));
bc9ec0e0
GK		 10888 true_cond = false_cond;
10889 false_cond = temp;
50a0b056 10890
3148ad6d
DJ		 10891 temp = gen_reg_rtx (compare_mode);
10892 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 10893 op0 = temp;
10894 break;
10895
10896 default:
10897 abort ();
10898 }
10899
10900 emit_insn (gen_rtx_SET (VOIDmode, dest,
3148ad6d 10901 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 10902 gen_rtx_GE (VOIDmode,
10903 op0, op1),
10904 true_cond, false_cond)));
10905 return 1;
10906}
10907
a3170dc6
AH		 10908/* Same as above, but for ints (isel). */
10909
10910static int
a2369ed3 10911rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
a3170dc6
AH		 10912{
10913 rtx condition_rtx, cr;
10914
10915 /* All isel implementations thus far are 32-bits. */
10916 if (GET_MODE (rs6000_compare_op0) != SImode)
10917 return 0;
10918
10919 /* We still have to do the compare, because isel doesn't do a
10920 compare, it just looks at the CRx bits set by a previous compare
10921 instruction. */
10922 condition_rtx = rs6000_generate_compare (GET_CODE (op));
10923 cr = XEXP (condition_rtx, 0);
10924
10925 if (GET_MODE (cr) == CCmode)
10926 emit_insn (gen_isel_signed (dest, condition_rtx,
10927 true_cond, false_cond, cr));
10928 else
10929 emit_insn (gen_isel_unsigned (dest, condition_rtx,
10930 true_cond, false_cond, cr));
10931
10932 return 1;
10933}
10934
10935const char *
a2369ed3 10936output_isel (rtx *operands)
a3170dc6
AH		 10937{
10938 enum rtx_code code;
10939
10940 code = GET_CODE (operands[1]);
10941 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10942 {
10943 PUT_CODE (operands[1], reverse_condition (code));
10944 return "isel %0,%3,%2,%j1";
10945 }
10946 else
10947 return "isel %0,%2,%3,%j1";
10948}
10949
50a0b056 10950void
a2369ed3 10951rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
50a0b056
GK		 10952{
10953 enum machine_mode mode = GET_MODE (op0);
5dc8d536 10954 enum rtx_code c;
50a0b056 10955 rtx target;
5dc8d536
AH		 10956
10957 if (code == SMAX || code == SMIN)
10958 c = GE;
10959 else
10960 c = GEU;
10961
50a0b056 10962 if (code == SMAX || code == UMAX)
f676971a 10963 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056
GK		 10964 op0, op1, mode, 0);
10965 else
f676971a 10966 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056
GK		 10967 op1, op0, mode, 0);
10968 if (target == NULL_RTX)
10969 abort ();
10970 if (target != dest)
10971 emit_move_insn (dest, target);
10972}
46c07df8 10973
a9baceb1
GK		 10974/* Emit instructions to move SRC to DST. Called by splitters for
10975 multi-register moves. It will emit at most one instruction for
10976 each register that is accessed; that is, it won't emit li/lis pairs
10977 (or equivalent for 64-bit code). One of SRC or DST must be a hard
10978 register. */
46c07df8 10979
46c07df8 10980void
a9baceb1 10981rs6000_split_multireg_move (rtx dst, rtx src)
46c07df8 10982{
a9baceb1
GK		 10983 /* The register number of the first register being moved. */
10984 int reg;
10985 /* The mode that is to be moved. */
10986 enum machine_mode mode;
10987 /* The mode that the move is being done in, and its size. */
10988 enum machine_mode reg_mode;
10989 int reg_mode_size;
10990 /* The number of registers that will be moved. */
10991 int nregs;
10992
10993 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10994 mode = GET_MODE (dst);
10995 nregs = HARD_REGNO_NREGS (reg, mode);
10996 if (FP_REGNO_P (reg))
10997 reg_mode = DFmode;
10998 else if (ALTIVEC_REGNO_P (reg))
10999 reg_mode = V16QImode;
11000 else
11001 reg_mode = word_mode;
11002 reg_mode_size = GET_MODE_SIZE (reg_mode);
f676971a 11003
a9baceb1
GK		 11004 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
11005 abort ();
f676971a 11006
a9baceb1
GK		 11007 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11008 {
11009 /* Move register range backwards, if we might have destructive
11010 overlap. */
11011 int i;
11012 for (i = nregs - 1; i >= 0; i--)
f676971a 11013 emit_insn (gen_rtx_SET (VOIDmode,
a9baceb1
GK		 11014 simplify_gen_subreg (reg_mode, dst, mode,
11015 i * reg_mode_size),
11016 simplify_gen_subreg (reg_mode, src, mode,
11017 i * reg_mode_size)));
11018 }
46c07df8
HP		 11019 else
11020 {
a9baceb1
GK		 11021 int i;
11022 int j = -1;
11023 bool used_update = false;
46c07df8 11024
c1e55850 11025 if (MEM_P (src) && INT_REGNO_P (reg))
c4ad648e
AM		 11026 {
11027 rtx breg;
3a1f863f 11028
a9baceb1
GK		 11029 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11030 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
3a1f863f
DE		 11031 {
11032 rtx delta_rtx;
a9baceb1 11033 breg = XEXP (XEXP (src, 0), 0);
c4ad648e
AM		 11034 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11035 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11036 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
a9baceb1
GK		 11037 emit_insn (TARGET_32BIT
11038 ? gen_addsi3 (breg, breg, delta_rtx)
11039 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11040 src = gen_rtx_MEM (mode, breg);
11041 }
c1e55850
GK		 11042 else if (! offsettable_memref_p (src))
11043 {
11044 rtx newsrc, basereg;
11045 basereg = gen_rtx_REG (Pmode, reg);
11046 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11047 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11048 MEM_COPY_ATTRIBUTES (newsrc, src);
11049 src = newsrc;
11050 }
3a1f863f 11051
0423421f
AM		 11052 breg = XEXP (src, 0);
11053 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11054 breg = XEXP (breg, 0);
11055
11056 /* If the base register we are using to address memory is
11057 also a destination reg, then change that register last. */
11058 if (REG_P (breg)
11059 && REGNO (breg) >= REGNO (dst)
3a1f863f
DE		 11060 && REGNO (breg) < REGNO (dst) + nregs)
11061 j = REGNO (breg) - REGNO (dst);
c4ad648e 11062 }
46c07df8 11063
a9baceb1 11064 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
3a1f863f
DE		 11065 {
11066 rtx breg;
11067
a9baceb1
GK		 11068 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11069 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
3a1f863f
DE		 11070 {
11071 rtx delta_rtx;
a9baceb1 11072 breg = XEXP (XEXP (dst, 0), 0);
c4ad648e
AM		 11073 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11074 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11075 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
3a1f863f
DE		 11076
11077 /* We have to update the breg before doing the store.
11078 Use store with update, if available. */
11079
11080 if (TARGET_UPDATE)
11081 {
a9baceb1 11082 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
c4ad648e
AM		 11083 emit_insn (TARGET_32BIT
11084 ? (TARGET_POWERPC64
11085 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11086 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11087 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
a9baceb1 11088 used_update = true;
3a1f863f
DE		 11089 }
11090 else
a9baceb1
GK		 11091 emit_insn (TARGET_32BIT
11092 ? gen_addsi3 (breg, breg, delta_rtx)
11093 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11094 dst = gen_rtx_MEM (mode, breg);
11095 }
c1e55850 11096 else if (! offsettable_memref_p (dst))
112ccb83 11097 abort ();
3a1f863f
DE		 11098 }
11099
46c07df8 11100 for (i = 0; i < nregs; i++)
f676971a 11101 {
3a1f863f
DE		 11102 /* Calculate index to next subword. */
11103 ++j;
f676971a 11104 if (j == nregs)
3a1f863f 11105 j = 0;
46c07df8 11106
112cdef5 11107 /* If compiler already emitted move of first word by
a9baceb1 11108 store with update, no need to do anything. */
3a1f863f 11109 if (j == 0 && used_update)
a9baceb1 11110 continue;
f676971a 11111
a9baceb1
GK		 11112 emit_insn (gen_rtx_SET (VOIDmode,
11113 simplify_gen_subreg (reg_mode, dst, mode,
11114 j * reg_mode_size),
11115 simplify_gen_subreg (reg_mode, src, mode,
11116 j * reg_mode_size)));
3a1f863f 11117 }
46c07df8
HP		 11118 }
11119}
11120
12a4e8c5 11121\f
a4f6c312
SS		 11122/* This page contains routines that are used to determine what the
11123 function prologue and epilogue code will do and write them out. */
9878760c 11124
a4f6c312
SS		 11125/* Return the first fixed-point register that is required to be
11126 saved. 32 if none. */
9878760c
RK		 11127
11128int
863d938c 11129first_reg_to_save (void)
9878760c
RK		 11130{
11131 int first_reg;
11132
11133 /* Find lowest numbered live register. */
11134 for (first_reg = 13; first_reg <= 31; first_reg++)
f676971a 11135 if (regs_ever_live[first_reg]
a38d360d 11136 && (! call_used_regs[first_reg]
1db02437 11137 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 11138 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
b4db40bf
JJ		 11139 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11140 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
9878760c
RK		 11141 break;
11142
ee890fe2 11143#if TARGET_MACHO
93638d7a
AM		 11144 if (flag_pic
11145 && current_function_uses_pic_offset_table
11146 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
1db02437 11147 return RS6000_PIC_OFFSET_TABLE_REGNUM;
ee890fe2
SS		 11148#endif
11149
9878760c
RK		 11150 return first_reg;
11151}
11152
11153/* Similar, for FP regs. */
11154
11155int
863d938c 11156first_fp_reg_to_save (void)
9878760c
RK		 11157{
11158 int first_reg;
11159
11160 /* Find lowest numbered live register. */
11161 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11162 if (regs_ever_live[first_reg])
11163 break;
11164
11165 return first_reg;
11166}
00b960c7
AH		 11167
11168/* Similar, for AltiVec regs. */
11169
11170static int
863d938c 11171first_altivec_reg_to_save (void)
00b960c7
AH		 11172{
11173 int i;
11174
11175 /* Stack frame remains as is unless we are in AltiVec ABI. */
11176 if (! TARGET_ALTIVEC_ABI)
11177 return LAST_ALTIVEC_REGNO + 1;
11178
11179 /* Find lowest numbered live register. */
11180 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11181 if (regs_ever_live[i])
11182 break;
11183
11184 return i;
11185}
11186
11187/* Return a 32-bit mask of the AltiVec registers we need to set in
11188 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11189 the 32-bit word is 0. */
11190
11191static unsigned int
863d938c 11192compute_vrsave_mask (void)
00b960c7
AH		 11193{
11194 unsigned int i, mask = 0;
11195
11196 /* First, find out if we use _any_ altivec registers. */
11197 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11198 if (regs_ever_live[i])
11199 mask |= ALTIVEC_REG_BIT (i);
11200
11201 if (mask == 0)
11202 return mask;
11203
00b960c7
AH		 11204 /* Next, remove the argument registers from the set. These must
11205 be in the VRSAVE mask set by the caller, so we don't need to add
11206 them in again. More importantly, the mask we compute here is
11207 used to generate CLOBBERs in the set_vrsave insn, and we do not
11208 wish the argument registers to die. */
a6cf80f2 11209 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
00b960c7
AH		 11210 mask &= ~ALTIVEC_REG_BIT (i);
11211
11212 /* Similarly, remove the return value from the set. */
11213 {
11214 bool yes = false;
11215 diddle_return_value (is_altivec_return_reg, &yes);
11216 if (yes)
11217 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11218 }
11219
11220 return mask;
11221}
11222
d62294f5 11223/* For a very restricted set of circumstances, we can cut down the
f57fe068
AM		 11224 size of prologues/epilogues by calling our own save/restore-the-world
11225 routines. */
d62294f5
FJ		 11226
11227static void
f57fe068
AM		 11228compute_save_world_info (rs6000_stack_t *info_ptr)
11229{
11230 info_ptr->world_save_p = 1;
11231 info_ptr->world_save_p
11232 = (WORLD_SAVE_P (info_ptr)
11233 && DEFAULT_ABI == ABI_DARWIN
11234 && ! (current_function_calls_setjmp && flag_exceptions)
11235 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11236 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11237 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11238 && info_ptr->cr_save_p);
f676971a 11239
d62294f5
FJ		 11240 /* This will not work in conjunction with sibcalls. Make sure there
11241 are none. (This check is expensive, but seldom executed.) */
f57fe068 11242 if (WORLD_SAVE_P (info_ptr))
f676971a 11243 {
d62294f5
FJ		 11244 rtx insn;
11245 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
c4ad648e
AM		 11246 if ( GET_CODE (insn) == CALL_INSN
11247 && SIBLING_CALL_P (insn))
11248 {
11249 info_ptr->world_save_p = 0;
11250 break;
11251 }
d62294f5 11252 }
f676971a 11253
f57fe068 11254 if (WORLD_SAVE_P (info_ptr))
d62294f5
FJ		 11255 {
11256 /* Even if we're not touching VRsave, make sure there's room on the
11257 stack for it, if it looks like we're calling SAVE_WORLD, which
c4ad648e 11258 will attempt to save it. */
d62294f5
FJ		 11259 info_ptr->vrsave_size = 4;
11260
11261 /* "Save" the VRsave register too if we're saving the world. */
11262 if (info_ptr->vrsave_mask == 0)
c4ad648e 11263 info_ptr->vrsave_mask = compute_vrsave_mask ();
d62294f5
FJ		 11264
11265 /* Because the Darwin register save/restore routines only handle
c4ad648e
AM		 11266 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11267 check and abort if there's something worng. */
f676971a 11268 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
c4ad648e
AM		 11269 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
11270 abort ();
d62294f5 11271 }
f676971a 11272 return;
d62294f5
FJ		 11273}
11274
11275
00b960c7 11276static void
a2369ed3 11277is_altivec_return_reg (rtx reg, void *xyes)
00b960c7
AH		 11278{
11279 bool *yes = (bool *) xyes;
11280 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11281 *yes = true;
11282}
11283
4697a36c
MM		 11284\f
11285/* Calculate the stack information for the current function. This is
11286 complicated by having two separate calling sequences, the AIX calling
11287 sequence and the V.4 calling sequence.
11288
592696dd 11289 AIX (and Darwin/Mac OS X) stack frames look like:
a260abc9 11290 32-bit 64-bit
4697a36c 11291 SP----> +---------------------------------------+
a260abc9 11292 | back chain to caller | 0 0
4697a36c 11293 +---------------------------------------+
a260abc9 11294 | saved CR | 4 8 (8-11)
4697a36c 11295 +---------------------------------------+
a260abc9 11296 | saved LR | 8 16
4697a36c 11297 +---------------------------------------+
a260abc9 11298 | reserved for compilers | 12 24
4697a36c 11299 +---------------------------------------+
a260abc9 11300 | reserved for binders | 16 32
4697a36c 11301 +---------------------------------------+
a260abc9 11302 | saved TOC pointer | 20 40
4697a36c 11303 +---------------------------------------+
a260abc9 11304 | Parameter save area (P) | 24 48
4697a36c 11305 +---------------------------------------+
a260abc9 11306 | Alloca space (A) | 24+P etc.
802a0058 11307 +---------------------------------------+
a7df97e6 11308 | Local variable space (L) | 24+P+A
4697a36c 11309 +---------------------------------------+
a7df97e6 11310 | Float/int conversion temporary (X) | 24+P+A+L
4697a36c 11311 +---------------------------------------+
00b960c7
AH		 11312 | Save area for AltiVec registers (W) | 24+P+A+L+X
11313 +---------------------------------------+
11314 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11315 +---------------------------------------+
11316 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
4697a36c 11317 +---------------------------------------+
00b960c7
AH		 11318 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11319 +---------------------------------------+
11320 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
4697a36c
MM		 11321 +---------------------------------------+
11322 old SP->| back chain to caller's caller |
11323 +---------------------------------------+
11324
5376a30c
KR		 11325 The required alignment for AIX configurations is two words (i.e., 8
11326 or 16 bytes).
11327
11328
4697a36c
MM		 11329 V.4 stack frames look like:
11330
11331 SP----> +---------------------------------------+
11332 | back chain to caller | 0
11333 +---------------------------------------+
5eb387b8 11334 | caller's saved LR | 4
4697a36c
MM		 11335 +---------------------------------------+
11336 | Parameter save area (P) | 8
11337 +---------------------------------------+
a7df97e6 11338 | Alloca space (A) | 8+P
f676971a 11339 +---------------------------------------+
a7df97e6 11340 | Varargs save area (V) | 8+P+A
f676971a 11341 +---------------------------------------+
a7df97e6 11342 | Local variable space (L) | 8+P+A+V
f676971a 11343 +---------------------------------------+
a7df97e6 11344 | Float/int conversion temporary (X) | 8+P+A+V+L
4697a36c 11345 +---------------------------------------+
00b960c7
AH		 11346 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11347 +---------------------------------------+
11348 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11349 +---------------------------------------+
11350 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11351 +---------------------------------------+
c4ad648e
AM		 11352 | SPE: area for 64-bit GP registers |
11353 +---------------------------------------+
11354 | SPE alignment padding |
11355 +---------------------------------------+
00b960c7 11356 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
f676971a 11357 +---------------------------------------+
00b960c7 11358 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
f676971a 11359 +---------------------------------------+
00b960c7 11360 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
4697a36c
MM		 11361 +---------------------------------------+
11362 old SP->| back chain to caller's caller |
11363 +---------------------------------------+
b6c9286a 11364
5376a30c
KR		 11365 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11366 given. (But note below and in sysv4.h that we require only 8 and
11367 may round up the size of our stack frame anyways. The historical
11368 reason is early versions of powerpc-linux which didn't properly
11369 align the stack at program startup. A happy side-effect is that
11370 -mno-eabi libraries can be used with -meabi programs.)
11371
50d440bc 11372 The EABI configuration defaults to the V.4 layout. However,
5376a30c
KR		 11373 the stack alignment requirements may differ. If -mno-eabi is not
11374 given, the required stack alignment is 8 bytes; if -mno-eabi is
11375 given, the required alignment is 16 bytes. (But see V.4 comment
11376 above.) */
4697a36c 11377
61b2fbe7
MM		 11378#ifndef ABI_STACK_BOUNDARY
11379#define ABI_STACK_BOUNDARY STACK_BOUNDARY
11380#endif
11381
d1d0c603 11382static rs6000_stack_t *
863d938c 11383rs6000_stack_info (void)
4697a36c
MM		 11384{
11385 static rs6000_stack_t info, zero_info;
11386 rs6000_stack_t *info_ptr = &info;
327e5343 11387 int reg_size = TARGET_32BIT ? 4 : 8;
83720594 11388 int ehrd_size;
64045029 11389 int save_align;
44688022 11390 HOST_WIDE_INT non_fixed_size;
4697a36c 11391
a4f6c312 11392 /* Zero all fields portably. */
4697a36c
MM		 11393 info = zero_info;
11394
c19de7aa
AH		 11395 if (TARGET_SPE)
11396 {
11397 /* Cache value so we don't rescan instruction chain over and over. */
9b7b447f 11398 if (cfun->machine->insn_chain_scanned_p == 0)
b5a5beb9
AH		 11399 cfun->machine->insn_chain_scanned_p
11400 = spe_func_has_64bit_regs_p () + 1;
11401 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
c19de7aa
AH		 11402 }
11403
a4f6c312 11404 /* Select which calling sequence. */
178274da 11405 info_ptr->abi = DEFAULT_ABI;
9878760c 11406
a4f6c312 11407 /* Calculate which registers need to be saved & save area size. */
4697a36c 11408 info_ptr->first_gp_reg_save = first_reg_to_save ();
f676971a 11409 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
906fb125 11410 even if it currently looks like we won't. */
2bfcf297 11411 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
178274da
AM		 11412 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
11413 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
1db02437
FS		 11414 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
11415 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
906fb125
GK		 11416 else
11417 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
4697a36c 11418
a3170dc6
AH		 11419 /* For the SPE, we have an additional upper 32-bits on each GPR.
11420 Ideally we should save the entire 64-bits only when the upper
11421 half is used in SIMD instructions. Since we only record
11422 registers live (not the size they are used in), this proves
11423 difficult because we'd have to traverse the instruction chain at
11424 the right time, taking reload into account. This is a real pain,
c19de7aa
AH		 11425 so we opt to save the GPRs in 64-bits always if but one register
11426 gets used in 64-bits. Otherwise, all the registers in the frame
11427 get saved in 32-bits.
a3170dc6 11428
c19de7aa 11429 So... since when we save all GPRs (except the SP) in 64-bits, the
a3170dc6 11430 traditional GP save area will be empty. */
c19de7aa 11431 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 11432 info_ptr->gp_size = 0;
11433
4697a36c
MM		 11434 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
11435 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
11436
00b960c7
AH		 11437 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
11438 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
11439 - info_ptr->first_altivec_reg_save);
11440
592696dd 11441 /* Does this function call anything? */
71f123ca
FS		 11442 info_ptr->calls_p = (! current_function_is_leaf
11443 || cfun->machine->ra_needs_full_frame);
b6c9286a 11444
a4f6c312 11445 /* Determine if we need to save the link register. */
71f123ca 11446 if (rs6000_ra_ever_killed ()
ffcfcb5f
AM		 11447 || (DEFAULT_ABI == ABI_AIX
11448 && current_function_profile
11449 && !TARGET_PROFILE_KERNEL)
4697a36c
MM		 11450#ifdef TARGET_RELOCATABLE
11451 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
11452#endif
11453 || (info_ptr->first_fp_reg_save != 64
11454 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
00b960c7 11455 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
178274da 11456 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
a4f6c312
SS		 11457 || (DEFAULT_ABI == ABI_DARWIN
11458 && flag_pic
11459 && current_function_uses_pic_offset_table)
4697a36c
MM		 11460 || info_ptr->calls_p)
11461 {
11462 info_ptr->lr_save_p = 1;
9ebbca7d 11463 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
4697a36c
MM		 11464 }
11465
9ebbca7d 11466 /* Determine if we need to save the condition code registers. */
f676971a 11467 if (regs_ever_live[CR2_REGNO]
9ebbca7d
GK		 11468 || regs_ever_live[CR3_REGNO]
11469 || regs_ever_live[CR4_REGNO])
4697a36c
MM		 11470 {
11471 info_ptr->cr_save_p = 1;
178274da 11472 if (DEFAULT_ABI == ABI_V4)
4697a36c
MM		 11473 info_ptr->cr_size = reg_size;
11474 }
11475
83720594
RH		 11476 /* If the current function calls __builtin_eh_return, then we need
11477 to allocate stack space for registers that will hold data for
11478 the exception handler. */
11479 if (current_function_calls_eh_return)
11480 {
11481 unsigned int i;
11482 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
11483 continue;
a3170dc6
AH		 11484
11485 /* SPE saves EH registers in 64-bits. */
c19de7aa
AH		 11486 ehrd_size = i * (TARGET_SPE_ABI
11487 && info_ptr->spe_64bit_regs_used != 0
11488 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
83720594
RH		 11489 }
11490 else
11491 ehrd_size = 0;
11492
592696dd 11493 /* Determine various sizes. */
4697a36c
MM		 11494 info_ptr->reg_size = reg_size;
11495 info_ptr->fixed_size = RS6000_SAVE_AREA;
11496 info_ptr->varargs_size = RS6000_VARARGS_AREA;
189e03e3 11497 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
a4f6c312 11498 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
03e007d7 11499 TARGET_ALTIVEC ? 16 : 8);
00b960c7 11500
c19de7aa 11501 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 11502 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
11503 else
11504 info_ptr->spe_gp_size = 0;
11505
4d774ff8
HP		 11506 if (TARGET_ALTIVEC_ABI)
11507 info_ptr->vrsave_mask = compute_vrsave_mask ();
00b960c7 11508 else
4d774ff8
HP		 11509 info_ptr->vrsave_mask = 0;
11510
11511 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
11512 info_ptr->vrsave_size = 4;
11513 else
11514 info_ptr->vrsave_size = 0;
b6c9286a 11515
d62294f5
FJ		 11516 compute_save_world_info (info_ptr);
11517
592696dd 11518 /* Calculate the offsets. */
178274da 11519 switch (DEFAULT_ABI)
4697a36c 11520 {
b6c9286a 11521 case ABI_NONE:
24d304eb 11522 default:
b6c9286a
MM		 11523 abort ();
11524
11525 case ABI_AIX:
ee890fe2 11526 case ABI_DARWIN:
b6c9286a
MM		 11527 info_ptr->fp_save_offset = - info_ptr->fp_size;
11528 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
00b960c7
AH		 11529
11530 if (TARGET_ALTIVEC_ABI)
11531 {
11532 info_ptr->vrsave_save_offset
11533 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
11534
11535 /* Align stack so vector save area is on a quadword boundary. */
11536 if (info_ptr->altivec_size != 0)
11537 info_ptr->altivec_padding_size
11538 = 16 - (-info_ptr->vrsave_save_offset % 16);
11539 else
11540 info_ptr->altivec_padding_size = 0;
11541
11542 info_ptr->altivec_save_offset
11543 = info_ptr->vrsave_save_offset
11544 - info_ptr->altivec_padding_size
11545 - info_ptr->altivec_size;
11546
11547 /* Adjust for AltiVec case. */
11548 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
11549 }
11550 else
11551 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
a260abc9
DE		 11552 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
11553 info_ptr->lr_save_offset = 2*reg_size;
24d304eb
RK		 11554 break;
11555
11556 case ABI_V4:
b6c9286a
MM		 11557 info_ptr->fp_save_offset = - info_ptr->fp_size;
11558 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
a7df97e6 11559 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
00b960c7 11560
c19de7aa 11561 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
c4ad648e
AM		 11562 {
11563 /* Align stack so SPE GPR save area is aligned on a
11564 double-word boundary. */
11565 if (info_ptr->spe_gp_size != 0)
11566 info_ptr->spe_padding_size
11567 = 8 - (-info_ptr->cr_save_offset % 8);
11568 else
11569 info_ptr->spe_padding_size = 0;
11570
11571 info_ptr->spe_gp_save_offset
11572 = info_ptr->cr_save_offset
11573 - info_ptr->spe_padding_size
11574 - info_ptr->spe_gp_size;
11575
11576 /* Adjust for SPE case. */
11577 info_ptr->toc_save_offset
11578 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
11579 }
a3170dc6 11580 else if (TARGET_ALTIVEC_ABI)
00b960c7
AH		 11581 {
11582 info_ptr->vrsave_save_offset
11583 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
11584
11585 /* Align stack so vector save area is on a quadword boundary. */
11586 if (info_ptr->altivec_size != 0)
11587 info_ptr->altivec_padding_size
11588 = 16 - (-info_ptr->vrsave_save_offset % 16);
11589 else
11590 info_ptr->altivec_padding_size = 0;
11591
11592 info_ptr->altivec_save_offset
11593 = info_ptr->vrsave_save_offset
11594 - info_ptr->altivec_padding_size
11595 - info_ptr->altivec_size;
11596
11597 /* Adjust for AltiVec case. */
11598 info_ptr->toc_save_offset
11599 = info_ptr->altivec_save_offset - info_ptr->toc_size;
11600 }
11601 else
11602 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
83720594 11603 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
b6c9286a
MM		 11604 info_ptr->lr_save_offset = reg_size;
11605 break;
4697a36c
MM		 11606 }
11607
64045029 11608 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
00b960c7
AH		 11609 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
11610 + info_ptr->gp_size
11611 + info_ptr->altivec_size
11612 + info_ptr->altivec_padding_size
a3170dc6
AH		 11613 + info_ptr->spe_gp_size
11614 + info_ptr->spe_padding_size
00b960c7
AH		 11615 + ehrd_size
11616 + info_ptr->cr_size
11617 + info_ptr->lr_size
11618 + info_ptr->vrsave_size
11619 + info_ptr->toc_size,
64045029 11620 save_align);
00b960c7 11621
44688022 11622 non_fixed_size = (info_ptr->vars_size
ff381587 11623 + info_ptr->parm_size
ff381587 11624 + info_ptr->save_size
44688022 11625 + info_ptr->varargs_size);
ff381587 11626
44688022
AM		 11627 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
11628 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
ff381587
MM		 11629
11630 /* Determine if we need to allocate any stack frame:
11631
a4f6c312
SS		 11632 For AIX we need to push the stack if a frame pointer is needed
11633 (because the stack might be dynamically adjusted), if we are
11634 debugging, if we make calls, or if the sum of fp_save, gp_save,
11635 and local variables are more than the space needed to save all
11636 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11637 + 18*8 = 288 (GPR13 reserved).
ff381587 11638
a4f6c312
SS		 11639 For V.4 we don't have the stack cushion that AIX uses, but assume
11640 that the debugger can handle stackless frames. */
ff381587
MM		 11641
11642 if (info_ptr->calls_p)
11643 info_ptr->push_p = 1;
11644
178274da 11645 else if (DEFAULT_ABI == ABI_V4)
44688022 11646 info_ptr->push_p = non_fixed_size != 0;
ff381587 11647
178274da
AM		 11648 else if (frame_pointer_needed)
11649 info_ptr->push_p = 1;
11650
11651 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11652 info_ptr->push_p = 1;
11653
ff381587 11654 else
44688022 11655 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
ff381587 11656
a4f6c312 11657 /* Zero offsets if we're not saving those registers. */
8dda1a21 11658 if (info_ptr->fp_size == 0)
4697a36c
MM		 11659 info_ptr->fp_save_offset = 0;
11660
8dda1a21 11661 if (info_ptr->gp_size == 0)
4697a36c
MM		 11662 info_ptr->gp_save_offset = 0;
11663
00b960c7
AH		 11664 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11665 info_ptr->altivec_save_offset = 0;
11666
11667 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11668 info_ptr->vrsave_save_offset = 0;
11669
c19de7aa
AH		 11670 if (! TARGET_SPE_ABI
11671 || info_ptr->spe_64bit_regs_used == 0
11672 || info_ptr->spe_gp_size == 0)
a3170dc6
AH		 11673 info_ptr->spe_gp_save_offset = 0;
11674
c81fc13e 11675 if (! info_ptr->lr_save_p)
4697a36c
MM		 11676 info_ptr->lr_save_offset = 0;
11677
c81fc13e 11678 if (! info_ptr->cr_save_p)
4697a36c
MM		 11679 info_ptr->cr_save_offset = 0;
11680
c81fc13e 11681 if (! info_ptr->toc_save_p)
b6c9286a
MM		 11682 info_ptr->toc_save_offset = 0;
11683
4697a36c
MM		 11684 return info_ptr;
11685}
11686
c19de7aa
AH		 11687/* Return true if the current function uses any GPRs in 64-bit SIMD
11688 mode. */
11689
11690static bool
863d938c 11691spe_func_has_64bit_regs_p (void)
c19de7aa
AH		 11692{
11693 rtx insns, insn;
11694
11695 /* Functions that save and restore all the call-saved registers will
11696 need to save/restore the registers in 64-bits. */
11697 if (current_function_calls_eh_return
11698 || current_function_calls_setjmp
11699 || current_function_has_nonlocal_goto)
11700 return true;
11701
11702 insns = get_insns ();
11703
11704 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
11705 {
11706 if (INSN_P (insn))
11707 {
11708 rtx i;
11709
b5a5beb9
AH		 11710 /* FIXME: This should be implemented with attributes...
11711
11712 (set_attr "spe64" "true")....then,
11713 if (get_spe64(insn)) return true;
11714
11715 It's the only reliable way to do the stuff below. */
11716
c19de7aa 11717 i = PATTERN (insn);
f82f556d
AH		 11718 if (GET_CODE (i) == SET)
11719 {
11720 enum machine_mode mode = GET_MODE (SET_SRC (i));
11721
11722 if (SPE_VECTOR_MODE (mode))
11723 return true;
11724 if (TARGET_E500_DOUBLE && mode == DFmode)
11725 return true;
11726 }
c19de7aa
AH		 11727 }
11728 }
11729
11730 return false;
11731}
11732
d1d0c603 11733static void
a2369ed3 11734debug_stack_info (rs6000_stack_t *info)
9878760c 11735{
d330fd93 11736 const char *abi_string;
24d304eb 11737
c81fc13e 11738 if (! info)
4697a36c
MM		 11739 info = rs6000_stack_info ();
11740
11741 fprintf (stderr, "\nStack information for function %s:\n",
11742 ((current_function_decl && DECL_NAME (current_function_decl))
11743 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
11744 : "<unknown>"));
11745
24d304eb
RK		 11746 switch (info->abi)
11747 {
b6c9286a
MM		 11748 default: abi_string = "Unknown"; break;
11749 case ABI_NONE: abi_string = "NONE"; break;
50d440bc 11750 case ABI_AIX: abi_string = "AIX"; break;
ee890fe2 11751 case ABI_DARWIN: abi_string = "Darwin"; break;
b6c9286a 11752 case ABI_V4: abi_string = "V.4"; break;
24d304eb
RK		 11753 }
11754
11755 fprintf (stderr, "\tABI = %5s\n", abi_string);
11756
00b960c7
AH		 11757 if (TARGET_ALTIVEC_ABI)
11758 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
11759
a3170dc6
AH		 11760 if (TARGET_SPE_ABI)
11761 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
11762
4697a36c
MM		 11763 if (info->first_gp_reg_save != 32)
11764 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
11765
11766 if (info->first_fp_reg_save != 64)
11767 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
9878760c 11768
00b960c7
AH		 11769 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
11770 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
11771 info->first_altivec_reg_save);
11772
4697a36c
MM		 11773 if (info->lr_save_p)
11774 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
9878760c 11775
4697a36c
MM		 11776 if (info->cr_save_p)
11777 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
11778
b6c9286a
MM		 11779 if (info->toc_save_p)
11780 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
11781
00b960c7
AH		 11782 if (info->vrsave_mask)
11783 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
11784
4697a36c
MM		 11785 if (info->push_p)
11786 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
11787
11788 if (info->calls_p)
11789 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
11790
4697a36c
MM		 11791 if (info->gp_save_offset)
11792 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
11793
11794 if (info->fp_save_offset)
11795 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
11796
00b960c7
AH		 11797 if (info->altivec_save_offset)
11798 fprintf (stderr, "\taltivec_save_offset = %5d\n",
11799 info->altivec_save_offset);
11800
a3170dc6
AH		 11801 if (info->spe_gp_save_offset)
11802 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
11803 info->spe_gp_save_offset);
11804
00b960c7
AH		 11805 if (info->vrsave_save_offset)
11806 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
11807 info->vrsave_save_offset);
11808
4697a36c
MM		 11809 if (info->lr_save_offset)
11810 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
11811
11812 if (info->cr_save_offset)
11813 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
11814
b6c9286a
MM		 11815 if (info->toc_save_offset)
11816 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
11817
4697a36c
MM		 11818 if (info->varargs_save_offset)
11819 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
11820
11821 if (info->total_size)
d1d0c603
JJ		 11822 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11823 info->total_size);
4697a36c
MM		 11824
11825 if (info->varargs_size)
11826 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
11827
11828 if (info->vars_size)
d1d0c603
JJ		 11829 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11830 info->vars_size);
4697a36c
MM		 11831
11832 if (info->parm_size)
11833 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
11834
11835 if (info->fixed_size)
11836 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
11837
11838 if (info->gp_size)
11839 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
11840
a3170dc6
AH		 11841 if (info->spe_gp_size)
11842 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
11843
4697a36c
MM		 11844 if (info->fp_size)
11845 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
11846
00b960c7
AH		 11847 if (info->altivec_size)
11848 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
11849
11850 if (info->vrsave_size)
11851 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
11852
11853 if (info->altivec_padding_size)
11854 fprintf (stderr, "\taltivec_padding_size= %5d\n",
11855 info->altivec_padding_size);
11856
a3170dc6
AH		 11857 if (info->spe_padding_size)
11858 fprintf (stderr, "\tspe_padding_size = %5d\n",
11859 info->spe_padding_size);
11860
a4f6c312 11861 if (info->lr_size)
ed947a96 11862 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
b6c9286a 11863
4697a36c
MM		 11864 if (info->cr_size)
11865 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
11866
a4f6c312 11867 if (info->toc_size)
b6c9286a
MM		 11868 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
11869
4697a36c
MM		 11870 if (info->save_size)
11871 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
11872
11873 if (info->reg_size != 4)
11874 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
11875
11876 fprintf (stderr, "\n");
9878760c 11877}
71f123ca
FS		 11878
11879rtx
a2369ed3 11880rs6000_return_addr (int count, rtx frame)
71f123ca 11881{
a4f6c312
SS		 11882 /* Currently we don't optimize very well between prolog and body
11883 code and for PIC code the code can be actually quite bad, so
11884 don't try to be too clever here. */
f1384257 11885 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
71f123ca
FS		 11886 {
11887 cfun->machine->ra_needs_full_frame = 1;
8ac61af7
RK		 11888
11889 return
11890 gen_rtx_MEM
11891 (Pmode,
11892 memory_address
11893 (Pmode,
11894 plus_constant (copy_to_reg
11895 (gen_rtx_MEM (Pmode,
11896 memory_address (Pmode, frame))),
11897 RETURN_ADDRESS_OFFSET)));
71f123ca
FS		 11898 }
11899
8c29550d 11900 cfun->machine->ra_need_lr = 1;
9e2f7ec7 11901 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
71f123ca
FS		 11902}
11903
5e1bf043
DJ		 11904/* Say whether a function is a candidate for sibcall handling or not.
11905 We do not allow indirect calls to be optimized into sibling calls.
11906 Also, we can't do it if there are any vector parameters; there's
11907 nowhere to put the VRsave code so it works; note that functions with
11908 vector parameters are required to have a prototype, so the argument
11909 type info must be available here. (The tail recursion case can work
11910 with vector parameters, but there's no way to distinguish here.) */
4977bab6 11911static bool
a2369ed3 11912rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5e1bf043
DJ		 11913{
11914 tree type;
4977bab6 11915 if (decl)
5e1bf043
DJ		 11916 {
11917 if (TARGET_ALTIVEC_VRSAVE)
c4ad648e 11918 {
4977bab6 11919 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
5e1bf043
DJ		 11920 type; type = TREE_CHAIN (type))
11921 {
c15b529f 11922 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
4977bab6 11923 return false;
5e1bf043 11924 }
c4ad648e 11925 }
5e1bf043 11926 if (DEFAULT_ABI == ABI_DARWIN
4977bab6 11927 || (*targetm.binds_local_p) (decl))
2bcc50d0 11928 {
4977bab6 11929 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
2bcc50d0
AM		 11930
11931 if (!lookup_attribute ("longcall", attr_list)
11932 || lookup_attribute ("shortcall", attr_list))
4977bab6 11933 return true;
2bcc50d0 11934 }
5e1bf043 11935 }
4977bab6 11936 return false;
5e1bf043
DJ		 11937}
11938
71f123ca 11939static int
863d938c 11940rs6000_ra_ever_killed (void)
71f123ca
FS		 11941{
11942 rtx top;
5e1bf043
DJ		 11943 rtx reg;
11944 rtx insn;
71f123ca 11945
dd292d0a 11946 if (current_function_is_thunk)
71f123ca 11947 return 0;
eb0424da 11948
36f7e964
AH		 11949 /* regs_ever_live has LR marked as used if any sibcalls are present,
11950 but this should not force saving and restoring in the
11951 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
a3c9585f 11952 clobbers LR, so that is inappropriate. */
36f7e964 11953
5e1bf043
DJ		 11954 /* Also, the prologue can generate a store into LR that
11955 doesn't really count, like this:
36f7e964 11956
5e1bf043
DJ		 11957 move LR->R0
11958 bcl to set PIC register
11959 move LR->R31
11960 move R0->LR
36f7e964
AH		 11961
11962 When we're called from the epilogue, we need to avoid counting
11963 this as a store. */
f676971a 11964
71f123ca
FS		 11965 push_topmost_sequence ();
11966 top = get_insns ();
11967 pop_topmost_sequence ();
5e1bf043 11968 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
71f123ca 11969
5e1bf043
DJ		 11970 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
11971 {
11972 if (INSN_P (insn))
11973 {
11974 if (FIND_REG_INC_NOTE (insn, reg))
11975 return 1;
f676971a 11976 else if (GET_CODE (insn) == CALL_INSN
c15b529f 11977 && !SIBLING_CALL_P (insn))
5e1bf043 11978 return 1;
36f7e964
AH		 11979 else if (set_of (reg, insn) != NULL_RTX
11980 && !prologue_epilogue_contains (insn))
5e1bf043
DJ		 11981 return 1;
11982 }
11983 }
11984 return 0;
71f123ca 11985}
4697a36c 11986\f
8cd8f856
GK		 11987/* Add a REG_MAYBE_DEAD note to the insn. */
11988static void
a2369ed3 11989rs6000_maybe_dead (rtx insn)
8cd8f856
GK		 11990{
11991 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
11992 const0_rtx,
11993 REG_NOTES (insn));
11994}
11995
9ebbca7d 11996/* Emit instructions needed to load the TOC register.
c7ca610e 11997 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
9ebbca7d 11998 a constant pool; or for SVR4 -fpic. */
c7ca610e
RK		 11999
12000void
a2369ed3 12001rs6000_emit_load_toc_table (int fromprolog)
c7ca610e 12002{
027fbf43 12003 rtx dest, insn;
1db02437 12004 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
c7ca610e 12005
20b71b17
AM		 12006 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12007 {
12008 rtx temp = (fromprolog
12009 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12010 : gen_reg_rtx (Pmode));
027fbf43
JJ		 12011 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
12012 if (fromprolog)
12013 rs6000_maybe_dead (insn);
12014 insn = emit_move_insn (dest, temp);
12015 if (fromprolog)
12016 rs6000_maybe_dead (insn);
20b71b17
AM		 12017 }
12018 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12019 {
12020 char buf[30];
12021 rtx tempLR = (fromprolog
12022 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12023 : gen_reg_rtx (Pmode));
12024 rtx temp0 = (fromprolog
12025 ? gen_rtx_REG (Pmode, 0)
12026 : gen_reg_rtx (Pmode));
12027 rtx symF;
12028
20b71b17
AM		 12029 if (fromprolog)
12030 {
12031 rtx symL;
38c1f2d7 12032
20b71b17
AM		 12033 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12034 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d 12035
20b71b17
AM		 12036 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12037 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12038
12039 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12040 symF)));
12041 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12042 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12043 symL,
12044 symF)));
9ebbca7d
GK		 12045 }
12046 else
20b71b17
AM		 12047 {
12048 rtx tocsym;
12049 static int reload_toc_labelno = 0;
12050
12051 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12052
12053 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
12054 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12055
027fbf43
JJ		 12056 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
12057 emit_move_insn (dest, tempLR);
12058 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
20b71b17 12059 }
027fbf43
JJ		 12060 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12061 if (fromprolog)
12062 rs6000_maybe_dead (insn);
9ebbca7d 12063 }
20b71b17
AM		 12064 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12065 {
12066 /* This is for AIX code running in non-PIC ELF32. */
12067 char buf[30];
12068 rtx realsym;
12069 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12070 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12071
027fbf43
JJ		 12072 insn = emit_insn (gen_elf_high (dest, realsym));
12073 if (fromprolog)
12074 rs6000_maybe_dead (insn);
12075 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12076 if (fromprolog)
12077 rs6000_maybe_dead (insn);
20b71b17
AM		 12078 }
12079 else if (DEFAULT_ABI == ABI_AIX)
9ebbca7d
GK		 12080 {
12081 if (TARGET_32BIT)
027fbf43 12082 insn = emit_insn (gen_load_toc_aix_si (dest));
9ebbca7d 12083 else
027fbf43
JJ		 12084 insn = emit_insn (gen_load_toc_aix_di (dest));
12085 if (fromprolog)
12086 rs6000_maybe_dead (insn);
9ebbca7d 12087 }
20b71b17
AM		 12088 else
12089 abort ();
9ebbca7d
GK		 12090}
12091
d1d0c603
JJ		 12092/* Emit instructions to restore the link register after determining where
12093 its value has been stored. */
12094
12095void
12096rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12097{
12098 rs6000_stack_t *info = rs6000_stack_info ();
12099 rtx operands[2];
12100
12101 operands[0] = source;
12102 operands[1] = scratch;
12103
12104 if (info->lr_save_p)
12105 {
12106 rtx frame_rtx = stack_pointer_rtx;
12107 HOST_WIDE_INT sp_offset = 0;
12108 rtx tmp;
12109
12110 if (frame_pointer_needed
12111 || current_function_calls_alloca
12112 || info->total_size > 32767)
12113 {
12114 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12115 frame_rtx = operands[1];
12116 }
12117 else if (info->push_p)
12118 sp_offset = info->total_size;
12119
12120 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12121 tmp = gen_rtx_MEM (Pmode, tmp);
12122 emit_move_insn (tmp, operands[0]);
12123 }
12124 else
12125 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12126}
12127
f103e34d
GK		 12128static GTY(()) int set = -1;
12129
f676971a 12130int
863d938c 12131get_TOC_alias_set (void)
9ebbca7d 12132{
f103e34d
GK		 12133 if (set == -1)
12134 set = new_alias_set ();
12135 return set;
f676971a 12136}
9ebbca7d 12137
c1207243 12138/* This returns nonzero if the current function uses the TOC. This is
3c9eb5f4
AM		 12139 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12140 is generated by the ABI_V4 load_toc_* patterns. */
c954844a 12141#if TARGET_ELF
3c9eb5f4 12142static int
f676971a 12143uses_TOC (void)
9ebbca7d 12144{
c4501e62 12145 rtx insn;
38c1f2d7 12146
c4501e62
JJ		 12147 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12148 if (INSN_P (insn))
12149 {
12150 rtx pat = PATTERN (insn);
12151 int i;
9ebbca7d 12152
f676971a 12153 if (GET_CODE (pat) == PARALLEL)
c4501e62
JJ		 12154 for (i = 0; i < XVECLEN (pat, 0); i++)
12155 {
12156 rtx sub = XVECEXP (pat, 0, i);
12157 if (GET_CODE (sub) == USE)
12158 {
12159 sub = XEXP (sub, 0);
12160 if (GET_CODE (sub) == UNSPEC
12161 && XINT (sub, 1) == UNSPEC_TOC)
12162 return 1;
12163 }
12164 }
12165 }
12166 return 0;
9ebbca7d 12167}
c954844a 12168#endif
38c1f2d7 12169
9ebbca7d 12170rtx
f676971a 12171create_TOC_reference (rtx symbol)
9ebbca7d 12172{
f676971a 12173 return gen_rtx_PLUS (Pmode,
a8a05998 12174 gen_rtx_REG (Pmode, TOC_REGISTER),
f676971a
EC		 12175 gen_rtx_CONST (Pmode,
12176 gen_rtx_MINUS (Pmode, symbol,
b999aaeb 12177 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
9ebbca7d 12178}
38c1f2d7 12179
fc4767bb
JJ		 12180/* If _Unwind_* has been called from within the same module,
12181 toc register is not guaranteed to be saved to 40(1) on function
12182 entry. Save it there in that case. */
c7ca610e 12183
9ebbca7d 12184void
863d938c 12185rs6000_aix_emit_builtin_unwind_init (void)
9ebbca7d
GK		 12186{
12187 rtx mem;
12188 rtx stack_top = gen_reg_rtx (Pmode);
12189 rtx opcode_addr = gen_reg_rtx (Pmode);
fc4767bb
JJ		 12190 rtx opcode = gen_reg_rtx (SImode);
12191 rtx tocompare = gen_reg_rtx (SImode);
12192 rtx no_toc_save_needed = gen_label_rtx ();
9ebbca7d
GK		 12193
12194 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12195 emit_move_insn (stack_top, mem);
12196
fc4767bb
JJ		 12197 mem = gen_rtx_MEM (Pmode,
12198 gen_rtx_PLUS (Pmode, stack_top,
9ebbca7d
GK		 12199 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12200 emit_move_insn (opcode_addr, mem);
fc4767bb
JJ		 12201 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12202 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
2496c7bd 12203 : 0xE8410028, SImode));
9ebbca7d 12204
fc4767bb 12205 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
06f4e019 12206 SImode, NULL_RTX, NULL_RTX,
fc4767bb 12207 no_toc_save_needed);
9ebbca7d 12208
fc4767bb
JJ		 12209 mem = gen_rtx_MEM (Pmode,
12210 gen_rtx_PLUS (Pmode, stack_top,
12211 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12212 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12213 emit_label (no_toc_save_needed);
9ebbca7d 12214}
38c1f2d7 12215\f
ba4828e0
RK		 12216/* This ties together stack memory (MEM with an alias set of
12217 rs6000_sr_alias_set) and the change to the stack pointer. */
12218
9ebbca7d 12219static void
863d938c 12220rs6000_emit_stack_tie (void)
9ebbca7d 12221{
ba4828e0
RK		 12222 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12223
12224 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 12225 emit_insn (gen_stack_tie (mem));
12226}
38c1f2d7 12227
9ebbca7d
GK		 12228/* Emit the correct code for allocating stack space, as insns.
12229 If COPY_R12, make sure a copy of the old frame is left in r12.
12230 The generated code may use hard register 0 as a temporary. */
12231
12232static void
a2369ed3 12233rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
38c1f2d7 12234{
9ebbca7d
GK		 12235 rtx insn;
12236 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12237 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
61168ff1
RS		 12238 rtx todec = gen_int_mode (-size, Pmode);
12239
12240 if (INTVAL (todec) != -size)
12241 {
9390387d 12242 warning ("stack frame too large");
61168ff1
RS		 12243 emit_insn (gen_trap ());
12244 return;
12245 }
a157febd
GK		 12246
12247 if (current_function_limit_stack)
12248 {
12249 if (REG_P (stack_limit_rtx)
f676971a 12250 && REGNO (stack_limit_rtx) > 1
a157febd
GK		 12251 && REGNO (stack_limit_rtx) <= 31)
12252 {
5b71a4e7 12253 emit_insn (TARGET_32BIT
9ebbca7d
GK		 12254 ? gen_addsi3 (tmp_reg,
12255 stack_limit_rtx,
12256 GEN_INT (size))
12257 : gen_adddi3 (tmp_reg,
12258 stack_limit_rtx,
12259 GEN_INT (size)));
5b71a4e7 12260
9ebbca7d
GK		 12261 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12262 const0_rtx));
a157febd
GK		 12263 }
12264 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
9ebbca7d 12265 && TARGET_32BIT
f607bc57 12266 && DEFAULT_ABI == ABI_V4)
a157febd 12267 {
9ebbca7d 12268 rtx toload = gen_rtx_CONST (VOIDmode,
f676971a
EC		 12269 gen_rtx_PLUS (Pmode,
12270 stack_limit_rtx,
9ebbca7d 12271 GEN_INT (size)));
5b71a4e7 12272
9ebbca7d
GK		 12273 emit_insn (gen_elf_high (tmp_reg, toload));
12274 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12275 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12276 const0_rtx));
a157febd
GK		 12277 }
12278 else
12279 warning ("stack limit expression is not supported");
12280 }
12281
9ebbca7d
GK		 12282 if (copy_r12 || ! TARGET_UPDATE)
12283 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12284
38c1f2d7
MM		 12285 if (TARGET_UPDATE)
12286 {
9ebbca7d 12287 if (size > 32767)
38c1f2d7 12288 {
9ebbca7d 12289 /* Need a note here so that try_split doesn't get confused. */
9390387d 12290 if (get_last_insn () == NULL_RTX)
2e040219 12291 emit_note (NOTE_INSN_DELETED);
9ebbca7d
GK		 12292 insn = emit_move_insn (tmp_reg, todec);
12293 try_split (PATTERN (insn), insn, 0);
12294 todec = tmp_reg;
38c1f2d7 12295 }
5b71a4e7
DE		 12296
12297 insn = emit_insn (TARGET_32BIT
12298 ? gen_movsi_update (stack_reg, stack_reg,
12299 todec, stack_reg)
c4ad648e 12300 : gen_movdi_di_update (stack_reg, stack_reg,
9ebbca7d 12301 todec, stack_reg));
38c1f2d7
MM		 12302 }
12303 else
12304 {
5b71a4e7
DE		 12305 insn = emit_insn (TARGET_32BIT
12306 ? gen_addsi3 (stack_reg, stack_reg, todec)
12307 : gen_adddi3 (stack_reg, stack_reg, todec));
9ebbca7d
GK		 12308 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12309 gen_rtx_REG (Pmode, 12));
12310 }
f676971a 12311
9ebbca7d 12312 RTX_FRAME_RELATED_P (insn) = 1;
f676971a 12313 REG_NOTES (insn) =
9ebbca7d 12314 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
f676971a 12315 gen_rtx_SET (VOIDmode, stack_reg,
9ebbca7d
GK		 12316 gen_rtx_PLUS (Pmode, stack_reg,
12317 GEN_INT (-size))),
12318 REG_NOTES (insn));
12319}
12320
a4f6c312
SS		 12321/* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12322 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12323 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12324 deduce these equivalences by itself so it wasn't necessary to hold
12325 its hand so much. */
9ebbca7d
GK		 12326
12327static void
f676971a 12328rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
a2369ed3 12329 rtx reg2, rtx rreg)
9ebbca7d
GK		 12330{
12331 rtx real, temp;
12332
e56c4463
JL		 12333 /* copy_rtx will not make unique copies of registers, so we need to
12334 ensure we don't have unwanted sharing here. */
12335 if (reg == reg2)
12336 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12337
12338 if (reg == rreg)
12339 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12340
9ebbca7d
GK		 12341 real = copy_rtx (PATTERN (insn));
12342
89e7058f
AH		 12343 if (reg2 != NULL_RTX)
12344 real = replace_rtx (real, reg2, rreg);
f676971a
EC		 12345
12346 real = replace_rtx (real, reg,
9ebbca7d
GK		 12347 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12348 STACK_POINTER_REGNUM),
12349 GEN_INT (val)));
f676971a 12350
9ebbca7d
GK		 12351 /* We expect that 'real' is either a SET or a PARALLEL containing
12352 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12353 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12354
12355 if (GET_CODE (real) == SET)
12356 {
12357 rtx set = real;
f676971a 12358
9ebbca7d
GK		 12359 temp = simplify_rtx (SET_SRC (set));
12360 if (temp)
12361 SET_SRC (set) = temp;
12362 temp = simplify_rtx (SET_DEST (set));
12363 if (temp)
12364 SET_DEST (set) = temp;
12365 if (GET_CODE (SET_DEST (set)) == MEM)
38c1f2d7 12366 {
9ebbca7d
GK		 12367 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12368 if (temp)
12369 XEXP (SET_DEST (set), 0) = temp;
38c1f2d7 12370 }
38c1f2d7 12371 }
9ebbca7d
GK		 12372 else if (GET_CODE (real) == PARALLEL)
12373 {
12374 int i;
12375 for (i = 0; i < XVECLEN (real, 0); i++)
12376 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
12377 {
12378 rtx set = XVECEXP (real, 0, i);
f676971a 12379
9ebbca7d
GK		 12380 temp = simplify_rtx (SET_SRC (set));
12381 if (temp)
12382 SET_SRC (set) = temp;
12383 temp = simplify_rtx (SET_DEST (set));
12384 if (temp)
12385 SET_DEST (set) = temp;
12386 if (GET_CODE (SET_DEST (set)) == MEM)
12387 {
12388 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12389 if (temp)
12390 XEXP (SET_DEST (set), 0) = temp;
12391 }
12392 RTX_FRAME_RELATED_P (set) = 1;
12393 }
12394 }
12395 else
a4f6c312 12396 abort ();
c19de7aa
AH		 12397
12398 if (TARGET_SPE)
12399 real = spe_synthesize_frame_save (real);
12400
9ebbca7d
GK		 12401 RTX_FRAME_RELATED_P (insn) = 1;
12402 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12403 real,
12404 REG_NOTES (insn));
38c1f2d7
MM		 12405}
12406
c19de7aa
AH		 12407/* Given an SPE frame note, return a PARALLEL of SETs with the
12408 original note, plus a synthetic register save. */
12409
12410static rtx
a2369ed3 12411spe_synthesize_frame_save (rtx real)
c19de7aa
AH		 12412{
12413 rtx synth, offset, reg, real2;
12414
12415 if (GET_CODE (real) != SET
12416 || GET_MODE (SET_SRC (real)) != V2SImode)
12417 return real;
12418
12419 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12420 frame related note. The parallel contains a set of the register
41f3a930 12421 being saved, and another set to a synthetic register (n+1200).
c19de7aa
AH		 12422 This is so we can differentiate between 64-bit and 32-bit saves.
12423 Words cannot describe this nastiness. */
12424
12425 if (GET_CODE (SET_DEST (real)) != MEM
12426 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
12427 || GET_CODE (SET_SRC (real)) != REG)
12428 abort ();
12429
12430 /* Transform:
12431 (set (mem (plus (reg x) (const y)))
12432 (reg z))
12433 into:
12434 (set (mem (plus (reg x) (const y+4)))
41f3a930 12435 (reg z+1200))
c19de7aa
AH		 12436 */
12437
12438 real2 = copy_rtx (real);
12439 PUT_MODE (SET_DEST (real2), SImode);
12440 reg = SET_SRC (real2);
12441 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
12442 synth = copy_rtx (real2);
12443
12444 if (BYTES_BIG_ENDIAN)
12445 {
12446 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
12447 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
12448 }
12449
12450 reg = SET_SRC (synth);
41f3a930 12451
c19de7aa 12452 synth = replace_rtx (synth, reg,
41f3a930 12453 gen_rtx_REG (SImode, REGNO (reg) + 1200));
c19de7aa
AH		 12454
12455 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
12456 synth = replace_rtx (synth, offset,
12457 GEN_INT (INTVAL (offset)
12458 + (BYTES_BIG_ENDIAN ? 0 : 4)));
12459
12460 RTX_FRAME_RELATED_P (synth) = 1;
12461 RTX_FRAME_RELATED_P (real2) = 1;
12462 if (BYTES_BIG_ENDIAN)
12463 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
12464 else
12465 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
12466
12467 return real;
12468}
12469
00b960c7
AH		 12470/* Returns an insn that has a vrsave set operation with the
12471 appropriate CLOBBERs. */
12472
12473static rtx
a2369ed3 12474generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
00b960c7
AH		 12475{
12476 int nclobs, i;
12477 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
a004eb82 12478 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
00b960c7 12479
a004eb82
AH		 12480 clobs[0]
12481 = gen_rtx_SET (VOIDmode,
12482 vrsave,
12483 gen_rtx_UNSPEC_VOLATILE (SImode,
12484 gen_rtvec (2, reg, vrsave),
12485 30));
00b960c7
AH		 12486
12487 nclobs = 1;
12488
9aa86737
AH		 12489 /* We need to clobber the registers in the mask so the scheduler
12490 does not move sets to VRSAVE before sets of AltiVec registers.
12491
12492 However, if the function receives nonlocal gotos, reload will set
12493 all call saved registers live. We will end up with:
12494
12495 (set (reg 999) (mem))
12496 (parallel [ (set (reg vrsave) (unspec blah))
12497 (clobber (reg 999))])
12498
12499 The clobber will cause the store into reg 999 to be dead, and
12500 flow will attempt to delete an epilogue insn. In this case, we
12501 need an unspec use/set of the register. */
00b960c7
AH		 12502
12503 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
44688022 12504 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
9aa86737
AH		 12505 {
12506 if (!epiloguep || call_used_regs [i])
12507 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
12508 gen_rtx_REG (V4SImode, i));
12509 else
12510 {
12511 rtx reg = gen_rtx_REG (V4SImode, i);
9aa86737
AH		 12512
12513 clobs[nclobs++]
a004eb82
AH		 12514 = gen_rtx_SET (VOIDmode,
12515 reg,
12516 gen_rtx_UNSPEC (V4SImode,
12517 gen_rtvec (1, reg), 27));
9aa86737
AH		 12518 }
12519 }
00b960c7
AH		 12520
12521 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
12522
12523 for (i = 0; i < nclobs; ++i)
12524 XVECEXP (insn, 0, i) = clobs[i];
12525
12526 return insn;
12527}
12528
89e7058f
AH		 12529/* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12530 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12531
12532static void
f676971a 12533emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
d1d0c603 12534 unsigned int regno, int offset, HOST_WIDE_INT total_size)
89e7058f
AH		 12535{
12536 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
12537 rtx replacea, replaceb;
12538
12539 int_rtx = GEN_INT (offset);
12540
12541 /* Some cases that need register indexed addressing. */
12542 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4d4cbc0e 12543 || (TARGET_E500_DOUBLE && mode == DFmode)
a3170dc6
AH		 12544 || (TARGET_SPE_ABI
12545 && SPE_VECTOR_MODE (mode)
12546 && !SPE_CONST_OFFSET_OK (offset)))
89e7058f
AH		 12547 {
12548 /* Whomever calls us must make sure r11 is available in the
c4ad648e 12549 flow path of instructions in the prologue. */
89e7058f
AH		 12550 offset_rtx = gen_rtx_REG (Pmode, 11);
12551 emit_move_insn (offset_rtx, int_rtx);
12552
12553 replacea = offset_rtx;
12554 replaceb = int_rtx;
12555 }
12556 else
12557 {
12558 offset_rtx = int_rtx;
12559 replacea = NULL_RTX;
12560 replaceb = NULL_RTX;
12561 }
12562
12563 reg = gen_rtx_REG (mode, regno);
12564 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
12565 mem = gen_rtx_MEM (mode, addr);
12566 set_mem_alias_set (mem, rs6000_sr_alias_set);
12567
12568 insn = emit_move_insn (mem, reg);
12569
12570 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
12571}
12572
a3170dc6
AH		 12573/* Emit an offset memory reference suitable for a frame store, while
12574 converting to a valid addressing mode. */
12575
12576static rtx
a2369ed3 12577gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
a3170dc6
AH		 12578{
12579 rtx int_rtx, offset_rtx;
12580
12581 int_rtx = GEN_INT (offset);
12582
4d4cbc0e
AH		 12583 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
12584 || (TARGET_E500_DOUBLE && mode == DFmode))
a3170dc6
AH		 12585 {
12586 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12587 emit_move_insn (offset_rtx, int_rtx);
12588 }
12589 else
12590 offset_rtx = int_rtx;
12591
12592 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
12593}
12594
699c914a
MS		 12595#ifndef TARGET_FIX_AND_CONTINUE
12596#define TARGET_FIX_AND_CONTINUE 0
12597#endif
12598
9ebbca7d
GK		 12599/* Emit function prologue as insns. */
12600
9878760c 12601void
863d938c 12602rs6000_emit_prologue (void)
9878760c 12603{
4697a36c 12604 rs6000_stack_t *info = rs6000_stack_info ();
0e67400a 12605 enum machine_mode reg_mode = Pmode;
327e5343 12606 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 12607 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12608 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
12609 rtx frame_reg_rtx = sp_reg_rtx;
b78d48dd 12610 rtx cr_save_rtx = NULL_RTX;
9ebbca7d
GK		 12611 rtx insn;
12612 int saving_FPRs_inline;
12613 int using_store_multiple;
12614 HOST_WIDE_INT sp_offset = 0;
f676971a 12615
699c914a
MS		 12616 if (TARGET_FIX_AND_CONTINUE)
12617 {
12618 /* gdb on darwin arranges to forward a function from the old
12619 address by modifying the first 4 instructions of the function
12620 to branch to the overriding function. This is necessary to
12621 permit function pointers that point to the old function to
12622 actually forward to the new function. */
12623 emit_insn (gen_nop ());
12624 emit_insn (gen_nop ());
12625 emit_insn (gen_nop ());
12626 emit_insn (gen_nop ());
12627 }
12628
12629 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12630 {
12631 reg_mode = V2SImode;
12632 reg_size = 8;
12633 }
a3170dc6 12634
9ebbca7d 12635 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 12636 && (!TARGET_SPE_ABI
12637 || info->spe_64bit_regs_used == 0)
9ebbca7d
GK		 12638 && info->first_gp_reg_save < 31);
12639 saving_FPRs_inline = (info->first_fp_reg_save == 64
8c29550d 12640 || FP_SAVE_INLINE (info->first_fp_reg_save)
acd0b319 12641 || current_function_calls_eh_return
8c29550d 12642 || cfun->machine->ra_need_lr);
9ebbca7d
GK		 12643
12644 /* For V.4, update stack before we do any saving and set back pointer. */
fc4767bb 12645 if (info->push_p
acd0b319
AM		 12646 && (DEFAULT_ABI == ABI_V4
12647 || current_function_calls_eh_return))
9ebbca7d
GK		 12648 {
12649 if (info->total_size < 32767)
12650 sp_offset = info->total_size;
12651 else
12652 frame_reg_rtx = frame_ptr_rtx;
f676971a 12653 rs6000_emit_allocate_stack (info->total_size,
9ebbca7d
GK		 12654 (frame_reg_rtx != sp_reg_rtx
12655 && (info->cr_save_p
12656 || info->lr_save_p
12657 || info->first_fp_reg_save < 64
12658 || info->first_gp_reg_save < 32
12659 )));
12660 if (frame_reg_rtx != sp_reg_rtx)
12661 rs6000_emit_stack_tie ();
12662 }
12663
d62294f5 12664 /* Handle world saves specially here. */
f57fe068 12665 if (WORLD_SAVE_P (info))
d62294f5
FJ		 12666 {
12667 int i, j, sz;
12668 rtx treg;
12669 rtvec p;
12670
12671 /* save_world expects lr in r0. */
12672 if (info->lr_save_p)
c4ad648e
AM		 12673 {
12674 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12675 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12676 RTX_FRAME_RELATED_P (insn) = 1;
12677 }
d62294f5
FJ		 12678
12679 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
c4ad648e
AM		 12680 assumptions about the offsets of various bits of the stack
12681 frame. Abort if things aren't what they should be. */
d62294f5 12682 if (info->gp_save_offset != -220
c4ad648e
AM		 12683 || info->fp_save_offset != -144
12684 || info->lr_save_offset != 8
12685 || info->cr_save_offset != 4
12686 || !info->push_p
12687 || !info->lr_save_p
12688 || (current_function_calls_eh_return && info->ehrd_offset != -432)
12689 || (info->vrsave_save_offset != -224
12690 || info->altivec_save_offset != (-224 -16 -192)))
12691 abort ();
d62294f5
FJ		 12692
12693 treg = gen_rtx_REG (SImode, 11);
12694 emit_move_insn (treg, GEN_INT (-info->total_size));
12695
12696 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
c4ad648e 12697 in R11. It also clobbers R12, so beware! */
d62294f5
FJ		 12698
12699 /* Preserve CR2 for save_world prologues */
12700 sz = 6;
12701 sz += 32 - info->first_gp_reg_save;
12702 sz += 64 - info->first_fp_reg_save;
12703 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
12704 p = rtvec_alloc (sz);
12705 j = 0;
12706 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
c4ad648e
AM		 12707 gen_rtx_REG (Pmode,
12708 LINK_REGISTER_REGNUM));
d62294f5 12709 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 12710 gen_rtx_SYMBOL_REF (Pmode,
12711 "*save_world"));
d62294f5 12712 /* We do floats first so that the instruction pattern matches
c4ad648e
AM		 12713 properly. */
12714 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12715 {
12716 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12717 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12718 GEN_INT (info->fp_save_offset
12719 + sp_offset + 8 * i));
12720 rtx mem = gen_rtx_MEM (DFmode, addr);
12721 set_mem_alias_set (mem, rs6000_sr_alias_set);
12722
12723 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12724 }
d62294f5 12725 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 12726 {
12727 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
12728 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12729 GEN_INT (info->altivec_save_offset
12730 + sp_offset + 16 * i));
12731 rtx mem = gen_rtx_MEM (V4SImode, addr);
12732 set_mem_alias_set (mem, rs6000_sr_alias_set);
12733
12734 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12735 }
d62294f5 12736 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 12737 {
12738 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12739 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12740 GEN_INT (info->gp_save_offset
12741 + sp_offset + reg_size * i));
12742 rtx mem = gen_rtx_MEM (reg_mode, addr);
12743 set_mem_alias_set (mem, rs6000_sr_alias_set);
12744
12745 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12746 }
12747
12748 {
12749 /* CR register traditionally saved as CR2. */
12750 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
12751 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12752 GEN_INT (info->cr_save_offset
12753 + sp_offset));
12754 rtx mem = gen_rtx_MEM (reg_mode, addr);
12755 set_mem_alias_set (mem, rs6000_sr_alias_set);
12756
12757 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12758 }
d62294f5
FJ		 12759 /* Prevent any attempt to delete the setting of r0 and treg! */
12760 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
12761 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
12762 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
12763
12764 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12765 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
c4ad648e 12766 NULL_RTX, NULL_RTX);
d62294f5
FJ		 12767
12768 if (current_function_calls_eh_return)
c4ad648e
AM		 12769 {
12770 unsigned int i;
12771 for (i = 0; ; ++i)
12772 {
12773 unsigned int regno = EH_RETURN_DATA_REGNO (i);
12774 if (regno == INVALID_REGNUM)
12775 break;
12776 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12777 info->ehrd_offset + sp_offset
12778 + reg_size * (int) i,
12779 info->total_size);
12780 }
12781 }
d62294f5
FJ		 12782 }
12783
9aa86737 12784 /* Save AltiVec registers if needed. */
f57fe068 12785 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
9aa86737
AH		 12786 {
12787 int i;
12788
12789 /* There should be a non inline version of this, for when we
12790 are saving lots of vector registers. */
12791 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12792 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12793 {
12794 rtx areg, savereg, mem;
12795 int offset;
12796
12797 offset = info->altivec_save_offset + sp_offset
12798 + 16 * (i - info->first_altivec_reg_save);
12799
12800 savereg = gen_rtx_REG (V4SImode, i);
12801
12802 areg = gen_rtx_REG (Pmode, 0);
12803 emit_move_insn (areg, GEN_INT (offset));
12804
12805 /* AltiVec addressing mode is [reg+reg]. */
12806 mem = gen_rtx_MEM (V4SImode,
12807 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
f676971a 12808
9aa86737
AH		 12809 set_mem_alias_set (mem, rs6000_sr_alias_set);
12810
12811 insn = emit_move_insn (mem, savereg);
12812
5c242421
SB		 12813 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12814 areg, GEN_INT (offset));
9aa86737
AH		 12815 }
12816 }
12817
12818 /* VRSAVE is a bit vector representing which AltiVec registers
12819 are used. The OS uses this to determine which vector
12820 registers to save on a context switch. We need to save
12821 VRSAVE on the stack frame, add whatever AltiVec registers we
12822 used in this function, and do the corresponding magic in the
12823 epilogue. */
12824
4d774ff8 12825 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
f57fe068 12826 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
9aa86737 12827 {
a004eb82 12828 rtx reg, mem, vrsave;
9aa86737
AH		 12829 int offset;
12830
eab97e44
AM		 12831 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
12832 as frame_reg_rtx and r11 as the static chain pointer for
12833 nested functions. */
12834 reg = gen_rtx_REG (SImode, 0);
a004eb82 12835 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
b188f760
AH		 12836 if (TARGET_MACHO)
12837 emit_insn (gen_get_vrsave_internal (reg));
12838 else
12839 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
9aa86737
AH		 12840
12841 /* Save VRSAVE. */
12842 offset = info->vrsave_save_offset + sp_offset;
12843 mem
12844 = gen_rtx_MEM (SImode,
12845 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
12846 set_mem_alias_set (mem, rs6000_sr_alias_set);
12847 insn = emit_move_insn (mem, reg);
12848
12849 /* Include the registers in the mask. */
12850 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
12851
12852 insn = emit_insn (generate_set_vrsave (reg, info, 0));
12853 }
12854
9ebbca7d 12855 /* If we use the link register, get it into r0. */
f57fe068 12856 if (!WORLD_SAVE_P (info) && info->lr_save_p)
f8a57be8
GK		 12857 {
12858 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12859 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12860 RTX_FRAME_RELATED_P (insn) = 1;
12861 }
9ebbca7d
GK		 12862
12863 /* If we need to save CR, put it into r12. */
f57fe068 12864 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
9ebbca7d 12865 {
f8a57be8 12866 rtx set;
f676971a 12867
9ebbca7d 12868 cr_save_rtx = gen_rtx_REG (SImode, 12);
f8a57be8
GK		 12869 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
12870 RTX_FRAME_RELATED_P (insn) = 1;
12871 /* Now, there's no way that dwarf2out_frame_debug_expr is going
12872 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
12873 But that's OK. All we have to do is specify that _one_ condition
12874 code register is saved in this stack slot. The thrower's epilogue
12875 will then restore all the call-saved registers.
12876 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
12877 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
12878 gen_rtx_REG (SImode, CR2_REGNO));
12879 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12880 set,
12881 REG_NOTES (insn));
9ebbca7d
GK		 12882 }
12883
a4f6c312
SS		 12884 /* Do any required saving of fpr's. If only one or two to save, do
12885 it ourselves. Otherwise, call function. */
f57fe068 12886 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
9ebbca7d
GK		 12887 {
12888 int i;
12889 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 12890 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d 12891 && ! call_used_regs[info->first_fp_reg_save+i]))
89e7058f
AH		 12892 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
12893 info->first_fp_reg_save + i,
12894 info->fp_save_offset + sp_offset + 8 * i,
12895 info->total_size);
9ebbca7d 12896 }
f57fe068 12897 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
9ebbca7d
GK		 12898 {
12899 int i;
12900 char rname[30];
520a57c8 12901 const char *alloc_rname;
9ebbca7d
GK		 12902 rtvec p;
12903 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
f676971a
EC		 12904
12905 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
12906 gen_rtx_REG (Pmode,
9ebbca7d
GK		 12907 LINK_REGISTER_REGNUM));
12908 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
12909 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
a8a05998 12910 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 12911 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12912 gen_rtx_SYMBOL_REF (Pmode,
12913 alloc_rname));
12914 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12915 {
12916 rtx addr, reg, mem;
12917 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12918 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a 12919 GEN_INT (info->fp_save_offset
9ebbca7d
GK		 12920 + sp_offset + 8*i));
12921 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 12922 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 12923
12924 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
12925 }
12926 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 12927 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d
GK		 12928 NULL_RTX, NULL_RTX);
12929 }
b6c9286a 12930
9ebbca7d
GK		 12931 /* Save GPRs. This is done as a PARALLEL if we are using
12932 the store-multiple instructions. */
f57fe068 12933 if (!WORLD_SAVE_P (info) && using_store_multiple)
b6c9286a 12934 {
308c142a 12935 rtvec p;
9ebbca7d
GK		 12936 int i;
12937 p = rtvec_alloc (32 - info->first_gp_reg_save);
9ebbca7d
GK		 12938 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12939 {
12940 rtx addr, reg, mem;
12941 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
f676971a
EC		 12942 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12943 GEN_INT (info->gp_save_offset
12944 + sp_offset
9ebbca7d
GK		 12945 + reg_size * i));
12946 mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 12947 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 12948
12949 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
12950 }
12951 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 12952 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d 12953 NULL_RTX, NULL_RTX);
b6c9286a 12954 }
f57fe068 12955 else if (!WORLD_SAVE_P (info))
b6c9286a 12956 {
9ebbca7d
GK		 12957 int i;
12958 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
f676971a 12959 if ((regs_ever_live[info->first_gp_reg_save+i]
b4db40bf
JJ		 12960 && (! call_used_regs[info->first_gp_reg_save+i]
12961 || (i+info->first_gp_reg_save
12962 == RS6000_PIC_OFFSET_TABLE_REGNUM
12963 && TARGET_TOC && TARGET_MINIMAL_TOC)))
1db02437 12964 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 12965 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 12966 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
a3170dc6
AH		 12967 {
12968 rtx addr, reg, mem;
12969 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12970
c19de7aa 12971 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 12972 {
12973 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12974 rtx b;
12975
12976 if (!SPE_CONST_OFFSET_OK (offset))
12977 {
12978 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12979 emit_move_insn (b, GEN_INT (offset));
12980 }
12981 else
12982 b = GEN_INT (offset);
12983
12984 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12985 mem = gen_rtx_MEM (V2SImode, addr);
12986 set_mem_alias_set (mem, rs6000_sr_alias_set);
12987 insn = emit_move_insn (mem, reg);
12988
12989 if (GET_CODE (b) == CONST_INT)
12990 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12991 NULL_RTX, NULL_RTX);
12992 else
12993 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12994 b, GEN_INT (offset));
12995 }
12996 else
12997 {
f676971a
EC		 12998 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12999 GEN_INT (info->gp_save_offset
13000 + sp_offset
a3170dc6
AH		 13001 + reg_size * i));
13002 mem = gen_rtx_MEM (reg_mode, addr);
13003 set_mem_alias_set (mem, rs6000_sr_alias_set);
13004
13005 insn = emit_move_insn (mem, reg);
f676971a 13006 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
a3170dc6
AH		 13007 NULL_RTX, NULL_RTX);
13008 }
13009 }
9ebbca7d
GK		 13010 }
13011
83720594
RH		 13012 /* ??? There's no need to emit actual instructions here, but it's the
13013 easiest way to get the frame unwind information emitted. */
f57fe068 13014 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
83720594 13015 {
78e1b90d
DE		 13016 unsigned int i, regno;
13017
fc4767bb
JJ		 13018 /* In AIX ABI we need to pretend we save r2 here. */
13019 if (TARGET_AIX)
13020 {
13021 rtx addr, reg, mem;
13022
13023 reg = gen_rtx_REG (reg_mode, 2);
13024 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13025 GEN_INT (sp_offset + 5 * reg_size));
13026 mem = gen_rtx_MEM (reg_mode, addr);
13027 set_mem_alias_set (mem, rs6000_sr_alias_set);
13028
13029 insn = emit_move_insn (mem, reg);
f676971a 13030 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
fc4767bb
JJ		 13031 NULL_RTX, NULL_RTX);
13032 PATTERN (insn) = gen_blockage ();
13033 }
13034
83720594
RH		 13035 for (i = 0; ; ++i)
13036 {
83720594
RH		 13037 regno = EH_RETURN_DATA_REGNO (i);
13038 if (regno == INVALID_REGNUM)
13039 break;
13040
89e7058f
AH		 13041 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13042 info->ehrd_offset + sp_offset
13043 + reg_size * (int) i,
13044 info->total_size);
83720594
RH		 13045 }
13046 }
13047
9ebbca7d 13048 /* Save lr if we used it. */
f57fe068 13049 if (!WORLD_SAVE_P (info) && info->lr_save_p)
9ebbca7d
GK		 13050 {
13051 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13052 GEN_INT (info->lr_save_offset + sp_offset));
13053 rtx reg = gen_rtx_REG (Pmode, 0);
13054 rtx mem = gen_rtx_MEM (Pmode, addr);
13055 /* This should not be of rs6000_sr_alias_set, because of
13056 __builtin_return_address. */
f676971a 13057
9ebbca7d 13058 insn = emit_move_insn (mem, reg);
f676971a 13059 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13060 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13061 }
13062
13063 /* Save CR if we use any that must be preserved. */
f57fe068 13064 if (!WORLD_SAVE_P (info) && info->cr_save_p)
9ebbca7d
GK		 13065 {
13066 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13067 GEN_INT (info->cr_save_offset + sp_offset));
13068 rtx mem = gen_rtx_MEM (SImode, addr);
f8a57be8
GK		 13069 /* See the large comment above about why CR2_REGNO is used. */
13070 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
ba4828e0
RK		 13071
13072 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13073
13074 /* If r12 was used to hold the original sp, copy cr into r0 now
13075 that it's free. */
13076 if (REGNO (frame_reg_rtx) == 12)
13077 {
f8a57be8
GK		 13078 rtx set;
13079
9ebbca7d 13080 cr_save_rtx = gen_rtx_REG (SImode, 0);
f8a57be8
GK		 13081 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13082 RTX_FRAME_RELATED_P (insn) = 1;
13083 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13084 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13085 set,
13086 REG_NOTES (insn));
f676971a 13087
9ebbca7d
GK		 13088 }
13089 insn = emit_move_insn (mem, cr_save_rtx);
13090
f676971a 13091 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13092 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13093 }
13094
f676971a 13095 /* Update stack and set back pointer unless this is V.4,
9ebbca7d 13096 for which it was done previously. */
f57fe068 13097 if (!WORLD_SAVE_P (info) && info->push_p
fc4767bb 13098 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
9ebbca7d
GK		 13099 rs6000_emit_allocate_stack (info->total_size, FALSE);
13100
13101 /* Set frame pointer, if needed. */
13102 if (frame_pointer_needed)
13103 {
f676971a 13104 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
9ebbca7d
GK		 13105 sp_reg_rtx);
13106 RTX_FRAME_RELATED_P (insn) = 1;
b6c9286a 13107 }
9878760c 13108
1db02437 13109 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
9ebbca7d 13110 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
f607bc57 13111 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
1db02437 13112 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
c4ad648e
AM		 13113 {
13114 /* If emit_load_toc_table will use the link register, we need to save
13115 it. We use R12 for this purpose because emit_load_toc_table
13116 can use register 0. This allows us to use a plain 'blr' to return
13117 from the procedure more often. */
13118 int save_LR_around_toc_setup = (TARGET_ELF
13119 && DEFAULT_ABI != ABI_AIX
13120 && flag_pic
13121 && ! info->lr_save_p
13122 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13123 if (save_LR_around_toc_setup)
13124 {
13125 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
f8a57be8 13126
c4ad648e
AM		 13127 insn = emit_move_insn (frame_ptr_rtx, lr);
13128 rs6000_maybe_dead (insn);
13129 RTX_FRAME_RELATED_P (insn) = 1;
f8a57be8 13130
c4ad648e 13131 rs6000_emit_load_toc_table (TRUE);
f8a57be8 13132
c4ad648e
AM		 13133 insn = emit_move_insn (lr, frame_ptr_rtx);
13134 rs6000_maybe_dead (insn);
13135 RTX_FRAME_RELATED_P (insn) = 1;
13136 }
13137 else
13138 rs6000_emit_load_toc_table (TRUE);
13139 }
ee890fe2 13140
fcce224d 13141#if TARGET_MACHO
ee890fe2
SS		 13142 if (DEFAULT_ABI == ABI_DARWIN
13143 && flag_pic && current_function_uses_pic_offset_table)
13144 {
f8a57be8 13145 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11abc112 13146 rtx src = machopic_function_base_sym ();
ee890fe2 13147
f8a57be8 13148 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
ee890fe2 13149
f676971a 13150 insn = emit_move_insn (gen_rtx_REG (Pmode,
f8a57be8
GK		 13151 RS6000_PIC_OFFSET_TABLE_REGNUM),
13152 lr);
13153 rs6000_maybe_dead (insn);
ee890fe2 13154 }
fcce224d 13155#endif
9ebbca7d
GK		 13156}
13157
9ebbca7d 13158/* Write function prologue. */
a4f6c312 13159
08c148a8 13160static void
f676971a 13161rs6000_output_function_prologue (FILE *file,
a2369ed3 13162 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9ebbca7d
GK		 13163{
13164 rs6000_stack_t *info = rs6000_stack_info ();
13165
4697a36c
MM		 13166 if (TARGET_DEBUG_STACK)
13167 debug_stack_info (info);
9878760c 13168
a4f6c312
SS		 13169 /* Write .extern for any function we will call to save and restore
13170 fp values. */
13171 if (info->first_fp_reg_save < 64
13172 && !FP_SAVE_INLINE (info->first_fp_reg_save))
4d30c363 13173 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
4697a36c 13174 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
a4f6c312
SS		 13175 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13176 RESTORE_FP_SUFFIX);
9878760c 13177
c764f757
RK		 13178 /* Write .extern for AIX common mode routines, if needed. */
13179 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13180 {
f6709c70
JW		 13181 fputs ("\t.extern __mulh\n", file);
13182 fputs ("\t.extern __mull\n", file);
13183 fputs ("\t.extern __divss\n", file);
13184 fputs ("\t.extern __divus\n", file);
13185 fputs ("\t.extern __quoss\n", file);
13186 fputs ("\t.extern __quous\n", file);
c764f757
RK		 13187 common_mode_defined = 1;
13188 }
9878760c 13189
9ebbca7d 13190 if (! HAVE_prologue)
979721f8 13191 {
9ebbca7d 13192 start_sequence ();
9dda4cc8 13193
a4f6c312
SS		 13194 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13195 the "toplevel" insn chain. */
2e040219 13196 emit_note (NOTE_INSN_DELETED);
9ebbca7d 13197 rs6000_emit_prologue ();
2e040219 13198 emit_note (NOTE_INSN_DELETED);
178c3eff 13199
a3c9585f 13200 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 13201 {
13202 rtx insn;
13203 unsigned addr = 0;
13204 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13205 {
13206 INSN_ADDRESSES_NEW (insn, addr);
13207 addr += 4;
13208 }
13209 }
9dda4cc8 13210
9ebbca7d 13211 if (TARGET_DEBUG_STACK)
a4f6c312
SS		 13212 debug_rtx_list (get_insns (), 100);
13213 final (get_insns (), file, FALSE, FALSE);
9ebbca7d 13214 end_sequence ();
979721f8
MM		 13215 }
13216
9ebbca7d
GK		 13217 rs6000_pic_labelno++;
13218}
f676971a 13219
9ebbca7d 13220/* Emit function epilogue as insns.
9878760c 13221
9ebbca7d
GK		 13222 At present, dwarf2out_frame_debug_expr doesn't understand
13223 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13224 anywhere in the epilogue. Most of the insns below would in any case
13225 need special notes to explain where r11 is in relation to the stack. */
9878760c 13226
9ebbca7d 13227void
a2369ed3 13228rs6000_emit_epilogue (int sibcall)
9ebbca7d
GK		 13229{
13230 rs6000_stack_t *info;
13231 int restoring_FPRs_inline;
13232 int using_load_multiple;
13233 int using_mfcr_multiple;
13234 int use_backchain_to_restore_sp;
13235 int sp_offset = 0;
13236 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13237 rtx frame_reg_rtx = sp_reg_rtx;
0e67400a 13238 enum machine_mode reg_mode = Pmode;
327e5343 13239 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 13240 int i;
13241
c19de7aa
AH		 13242 info = rs6000_stack_info ();
13243
13244 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13245 {
13246 reg_mode = V2SImode;
13247 reg_size = 8;
13248 }
13249
9ebbca7d 13250 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 13251 && (!TARGET_SPE_ABI
13252 || info->spe_64bit_regs_used == 0)
9ebbca7d
GK		 13253 && info->first_gp_reg_save < 31);
13254 restoring_FPRs_inline = (sibcall
83720594 13255 || current_function_calls_eh_return
9ebbca7d
GK		 13256 || info->first_fp_reg_save == 64
13257 || FP_SAVE_INLINE (info->first_fp_reg_save));
f676971a 13258 use_backchain_to_restore_sp = (frame_pointer_needed
9ebbca7d
GK		 13259 || current_function_calls_alloca
13260 || info->total_size > 32767);
13261 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13262 || rs6000_cpu == PROCESSOR_PPC603
13263 || rs6000_cpu == PROCESSOR_PPC750
13264 || optimize_size);
13265
f57fe068 13266 if (WORLD_SAVE_P (info))
d62294f5
FJ		 13267 {
13268 int i, j;
13269 char rname[30];
13270 const char *alloc_rname;
13271 rtvec p;
13272
13273 /* eh_rest_world_r10 will return to the location saved in the LR
c4ad648e
AM		 13274 stack slot (which is not likely to be our caller.)
13275 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13276 rest_world is similar, except any R10 parameter is ignored.
13277 The exception-handling stuff that was here in 2.95 is no
13278 longer necessary. */
d62294f5
FJ		 13279
13280 p = rtvec_alloc (9
13281 + 1
f676971a 13282 + 32 - info->first_gp_reg_save
c4ad648e
AM		 13283 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13284 + 63 + 1 - info->first_fp_reg_save);
d62294f5 13285
c4ad648e
AM		 13286 strcpy (rname, ((current_function_calls_eh_return) ?
13287 "*eh_rest_world_r10" : "*rest_world"));
d62294f5
FJ		 13288 alloc_rname = ggc_strdup (rname);
13289
13290 j = 0;
13291 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13292 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 13293 gen_rtx_REG (Pmode,
13294 LINK_REGISTER_REGNUM));
d62294f5 13295 RTVEC_ELT (p, j++)
c4ad648e 13296 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
d62294f5 13297 /* The instruction pattern requires a clobber here;
c4ad648e 13298 it is shared with the restVEC helper. */
d62294f5 13299 RTVEC_ELT (p, j++)
c4ad648e 13300 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
d62294f5
FJ		 13301
13302 {
c4ad648e
AM		 13303 /* CR register traditionally saved as CR2. */
13304 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13305 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13306 GEN_INT (info->cr_save_offset));
13307 rtx mem = gen_rtx_MEM (reg_mode, addr);
13308 set_mem_alias_set (mem, rs6000_sr_alias_set);
13309
13310 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
d62294f5
FJ		 13311 }
13312
13313 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 13314 {
13315 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13316 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13317 GEN_INT (info->gp_save_offset
13318 + reg_size * i));
13319 rtx mem = gen_rtx_MEM (reg_mode, addr);
13320 set_mem_alias_set (mem, rs6000_sr_alias_set);
13321
13322 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13323 }
d62294f5 13324 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 13325 {
13326 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13327 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13328 GEN_INT (info->altivec_save_offset
13329 + 16 * i));
13330 rtx mem = gen_rtx_MEM (V4SImode, addr);
13331 set_mem_alias_set (mem, rs6000_sr_alias_set);
13332
13333 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13334 }
d62294f5 13335 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
c4ad648e
AM		 13336 {
13337 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13338 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13339 GEN_INT (info->fp_save_offset
13340 + 8 * i));
13341 rtx mem = gen_rtx_MEM (DFmode, addr);
13342 set_mem_alias_set (mem, rs6000_sr_alias_set);
13343
13344 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13345 }
d62294f5 13346 RTVEC_ELT (p, j++)
c4ad648e 13347 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
d62294f5 13348 RTVEC_ELT (p, j++)
c4ad648e 13349 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
d62294f5 13350 RTVEC_ELT (p, j++)
c4ad648e 13351 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
d62294f5 13352 RTVEC_ELT (p, j++)
c4ad648e 13353 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
d62294f5 13354 RTVEC_ELT (p, j++)
c4ad648e 13355 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
d62294f5
FJ		 13356 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13357
13358 return;
13359 }
13360
9ebbca7d
GK		 13361 /* If we have a frame pointer, a call to alloca, or a large stack
13362 frame, restore the old stack pointer using the backchain. Otherwise,
13363 we know what size to update it with. */
13364 if (use_backchain_to_restore_sp)
bacbde18 13365 {
9ebbca7d
GK		 13366 /* Under V.4, don't reset the stack pointer until after we're done
13367 loading the saved registers. */
f607bc57 13368 if (DEFAULT_ABI == ABI_V4)
9ebbca7d 13369 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
4697a36c 13370
9ebbca7d
GK		 13371 emit_move_insn (frame_reg_rtx,
13372 gen_rtx_MEM (Pmode, sp_reg_rtx));
f676971a 13373
bacbde18 13374 }
9ebbca7d 13375 else if (info->push_p)
85638c0d 13376 {
fc4767bb
JJ		 13377 if (DEFAULT_ABI == ABI_V4
13378 || current_function_calls_eh_return)
9ebbca7d
GK		 13379 sp_offset = info->total_size;
13380 else
13381 {
13382 emit_insn (TARGET_32BIT
13383 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13384 GEN_INT (info->total_size))
13385 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13386 GEN_INT (info->total_size)));
13387 }
85638c0d 13388 }
f676971a 13389
9aa86737
AH		 13390 /* Restore AltiVec registers if needed. */
13391 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13392 {
13393 int i;
13394
13395 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13396 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13397 {
13398 rtx addr, areg, mem;
13399
13400 areg = gen_rtx_REG (Pmode, 0);
13401 emit_move_insn
13402 (areg, GEN_INT (info->altivec_save_offset
13403 + sp_offset
13404 + 16 * (i - info->first_altivec_reg_save)));
13405
13406 /* AltiVec addressing mode is [reg+reg]. */
13407 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
13408 mem = gen_rtx_MEM (V4SImode, addr);
13409 set_mem_alias_set (mem, rs6000_sr_alias_set);
13410
13411 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
13412 }
13413 }
13414
13415 /* Restore VRSAVE if needed. */
44688022 13416 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
4d774ff8 13417 && info->vrsave_mask != 0)
9aa86737
AH		 13418 {
13419 rtx addr, mem, reg;
13420
13421 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13422 GEN_INT (info->vrsave_save_offset + sp_offset));
13423 mem = gen_rtx_MEM (SImode, addr);
13424 set_mem_alias_set (mem, rs6000_sr_alias_set);
13425 reg = gen_rtx_REG (SImode, 12);
13426 emit_move_insn (reg, mem);
13427
13428 emit_insn (generate_set_vrsave (reg, info, 1));
13429 }
13430
9ebbca7d
GK		 13431 /* Get the old lr if we saved it. */
13432 if (info->lr_save_p)
b6c9286a 13433 {
a3170dc6
AH		 13434 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
13435 info->lr_save_offset + sp_offset);
ba4828e0
RK		 13436
13437 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 13438
9ebbca7d 13439 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
b6c9286a 13440 }
f676971a 13441
9ebbca7d
GK		 13442 /* Get the old cr if we saved it. */
13443 if (info->cr_save_p)
13444 {
13445 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13446 GEN_INT (info->cr_save_offset + sp_offset));
13447 rtx mem = gen_rtx_MEM (SImode, addr);
ba4828e0
RK		 13448
13449 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 13450
9ebbca7d
GK		 13451 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
13452 }
f676971a 13453
9ebbca7d 13454 /* Set LR here to try to overlap restores below. */
4697a36c 13455 if (info->lr_save_p)
9ebbca7d
GK		 13456 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
13457 gen_rtx_REG (Pmode, 0));
f676971a 13458
83720594
RH		 13459 /* Load exception handler data registers, if needed. */
13460 if (current_function_calls_eh_return)
13461 {
78e1b90d
DE		 13462 unsigned int i, regno;
13463
fc4767bb
JJ		 13464 if (TARGET_AIX)
13465 {
13466 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13467 GEN_INT (sp_offset + 5 * reg_size));
13468 rtx mem = gen_rtx_MEM (reg_mode, addr);
13469
13470 set_mem_alias_set (mem, rs6000_sr_alias_set);
13471
13472 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
13473 }
13474
83720594
RH		 13475 for (i = 0; ; ++i)
13476 {
a3170dc6 13477 rtx mem;
83720594
RH		 13478
13479 regno = EH_RETURN_DATA_REGNO (i);
13480 if (regno == INVALID_REGNUM)
13481 break;
13482
a3170dc6
AH		 13483 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
13484 info->ehrd_offset + sp_offset
13485 + reg_size * (int) i);
ba4828e0 13486 set_mem_alias_set (mem, rs6000_sr_alias_set);
83720594
RH		 13487
13488 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
13489 }
13490 }
f676971a 13491
9ebbca7d
GK		 13492 /* Restore GPRs. This is done as a PARALLEL if we are using
13493 the load-multiple instructions. */
13494 if (using_load_multiple)
979721f8 13495 {
9ebbca7d
GK		 13496 rtvec p;
13497 p = rtvec_alloc (32 - info->first_gp_reg_save);
13498 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
979721f8 13499 {
f676971a
EC		 13500 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13501 GEN_INT (info->gp_save_offset
13502 + sp_offset
9ebbca7d
GK		 13503 + reg_size * i));
13504 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0
RK		 13505
13506 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13507
f676971a 13508 RTVEC_ELT (p, i) =
9ebbca7d
GK		 13509 gen_rtx_SET (VOIDmode,
13510 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
13511 mem);
979721f8 13512 }
9ebbca7d 13513 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
979721f8 13514 }
9ebbca7d
GK		 13515 else
13516 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
f676971a 13517 if ((regs_ever_live[info->first_gp_reg_save+i]
b4db40bf
JJ		 13518 && (! call_used_regs[info->first_gp_reg_save+i]
13519 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13520 && TARGET_TOC && TARGET_MINIMAL_TOC)))
1db02437 13521 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 13522 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 13523 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
9ebbca7d 13524 {
f676971a
EC		 13525 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13526 GEN_INT (info->gp_save_offset
13527 + sp_offset
9ebbca7d
GK		 13528 + reg_size * i));
13529 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 13530
a3170dc6 13531 /* Restore 64-bit quantities for SPE. */
c19de7aa 13532 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13533 {
13534 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13535 rtx b;
13536
13537 if (!SPE_CONST_OFFSET_OK (offset))
13538 {
13539 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13540 emit_move_insn (b, GEN_INT (offset));
13541 }
13542 else
13543 b = GEN_INT (offset);
13544
13545 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13546 mem = gen_rtx_MEM (V2SImode, addr);
13547 }
13548
ba4828e0 13549 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13550
f676971a 13551 emit_move_insn (gen_rtx_REG (reg_mode,
a3170dc6 13552 info->first_gp_reg_save + i), mem);
9ebbca7d 13553 }
9878760c 13554
9ebbca7d
GK		 13555 /* Restore fpr's if we need to do it without calling a function. */
13556 if (restoring_FPRs_inline)
13557 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 13558 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d
GK		 13559 && ! call_used_regs[info->first_fp_reg_save+i]))
13560 {
13561 rtx addr, mem;
13562 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a
EC		 13563 GEN_INT (info->fp_save_offset
13564 + sp_offset
a4f6c312 13565 + 8 * i));
9ebbca7d 13566 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 13567 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13568
f676971a 13569 emit_move_insn (gen_rtx_REG (DFmode,
9ebbca7d
GK		 13570 info->first_fp_reg_save + i),
13571 mem);
13572 }
8d30c4ee 13573
9ebbca7d
GK		 13574 /* If we saved cr, restore it here. Just those that were used. */
13575 if (info->cr_save_p)
979721f8 13576 {
9ebbca7d 13577 rtx r12_rtx = gen_rtx_REG (SImode, 12);
e35b9579 13578 int count = 0;
f676971a 13579
9ebbca7d 13580 if (using_mfcr_multiple)
979721f8 13581 {
9ebbca7d
GK		 13582 for (i = 0; i < 8; i++)
13583 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
e35b9579 13584 count++;
9ebbca7d 13585 if (count == 0)
e35b9579
GK		 13586 abort ();
13587 }
13588
13589 if (using_mfcr_multiple && count > 1)
13590 {
13591 rtvec p;
13592 int ndx;
f676971a 13593
e35b9579 13594 p = rtvec_alloc (count);
9ebbca7d 13595
e35b9579 13596 ndx = 0;
9ebbca7d
GK		 13597 for (i = 0; i < 8; i++)
13598 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13599 {
13600 rtvec r = rtvec_alloc (2);
13601 RTVEC_ELT (r, 0) = r12_rtx;
13602 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
e35b9579 13603 RTVEC_ELT (p, ndx) =
f676971a 13604 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
615158e2 13605 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
e35b9579 13606 ndx++;
9ebbca7d
GK		 13607 }
13608 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
e35b9579
GK		 13609 if (ndx != count)
13610 abort ();
979721f8
MM		 13611 }
13612 else
9ebbca7d
GK		 13613 for (i = 0; i < 8; i++)
13614 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
979721f8 13615 {
f676971a 13616 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
9ebbca7d
GK		 13617 CR0_REGNO+i),
13618 r12_rtx));
979721f8 13619 }
979721f8
MM		 13620 }
13621
9ebbca7d
GK		 13622 /* If this is V.4, unwind the stack pointer after all of the loads
13623 have been done. We need to emit a block here so that sched
13624 doesn't decide to move the sp change before the register restores
13625 (which may not have any obvious dependency on the stack). This
13626 doesn't hurt performance, because there is no scheduling that can
13627 be done after this point. */
fc4767bb
JJ		 13628 if (DEFAULT_ABI == ABI_V4
13629 || current_function_calls_eh_return)
b6c9286a 13630 {
9ebbca7d 13631 if (frame_reg_rtx != sp_reg_rtx)
c4ad648e 13632 rs6000_emit_stack_tie ();
b6c9286a 13633
9ebbca7d 13634 if (use_backchain_to_restore_sp)
b6c9286a 13635 {
9ebbca7d 13636 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
b6c9286a 13637 }
9ebbca7d 13638 else if (sp_offset != 0)
13f1623b 13639 {
5b71a4e7 13640 emit_insn (TARGET_32BIT
9ebbca7d
GK		 13641 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13642 GEN_INT (sp_offset))
13643 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13644 GEN_INT (sp_offset)));
13f1623b 13645 }
9ebbca7d 13646 }
b6c9286a 13647
83720594
RH		 13648 if (current_function_calls_eh_return)
13649 {
13650 rtx sa = EH_RETURN_STACKADJ_RTX;
5b71a4e7 13651 emit_insn (TARGET_32BIT
83720594
RH		 13652 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
13653 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
13654 }
13655
9ebbca7d
GK		 13656 if (!sibcall)
13657 {
13658 rtvec p;
13659 if (! restoring_FPRs_inline)
13660 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
13661 else
13662 p = rtvec_alloc (2);
b6c9286a 13663
e35b9579 13664 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
f676971a
EC		 13665 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13666 gen_rtx_REG (Pmode,
9ebbca7d 13667 LINK_REGISTER_REGNUM));
9ebbca7d
GK		 13668
13669 /* If we have to restore more than two FP registers, branch to the
13670 restore function. It will return to our caller. */
13671 if (! restoring_FPRs_inline)
13672 {
13673 int i;
13674 char rname[30];
520a57c8 13675 const char *alloc_rname;
979721f8 13676
f676971a 13677 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
9ebbca7d 13678 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
a8a05998 13679 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 13680 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
13681 gen_rtx_SYMBOL_REF (Pmode,
13682 alloc_rname));
b6c9286a 13683
9ebbca7d
GK		 13684 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13685 {
13686 rtx addr, mem;
13687 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
13688 GEN_INT (info->fp_save_offset + 8*i));
13689 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 13690 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13691
f676971a 13692 RTVEC_ELT (p, i+3) =
9ebbca7d
GK		 13693 gen_rtx_SET (VOIDmode,
13694 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
13695 mem);
b6c9286a
MM		 13696 }
13697 }
f676971a 13698
9ebbca7d 13699 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
3daf36a4 13700 }
9878760c
RK		 13701}
13702
13703/* Write function epilogue. */
13704
08c148a8 13705static void
f676971a 13706rs6000_output_function_epilogue (FILE *file,
a2369ed3 13707 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9878760c 13708{
4697a36c 13709 rs6000_stack_t *info = rs6000_stack_info ();
9878760c 13710
9ebbca7d 13711 if (! HAVE_epilogue)
9878760c 13712 {
9ebbca7d
GK		 13713 rtx insn = get_last_insn ();
13714 /* If the last insn was a BARRIER, we don't have to write anything except
13715 the trace table. */
13716 if (GET_CODE (insn) == NOTE)
13717 insn = prev_nonnote_insn (insn);
13718 if (insn == 0 || GET_CODE (insn) != BARRIER)
4697a36c 13719 {
9ebbca7d
GK		 13720 /* This is slightly ugly, but at least we don't have two
13721 copies of the epilogue-emitting code. */
13722 start_sequence ();
13723
13724 /* A NOTE_INSN_DELETED is supposed to be at the start
13725 and end of the "toplevel" insn chain. */
2e040219 13726 emit_note (NOTE_INSN_DELETED);
9ebbca7d 13727 rs6000_emit_epilogue (FALSE);
2e040219 13728 emit_note (NOTE_INSN_DELETED);
9ebbca7d 13729
a3c9585f 13730 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 13731 {
13732 rtx insn;
13733 unsigned addr = 0;
13734 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13735 {
13736 INSN_ADDRESSES_NEW (insn, addr);
13737 addr += 4;
13738 }
13739 }
13740
9ebbca7d 13741 if (TARGET_DEBUG_STACK)
a4f6c312
SS		 13742 debug_rtx_list (get_insns (), 100);
13743 final (get_insns (), file, FALSE, FALSE);
9ebbca7d 13744 end_sequence ();
4697a36c 13745 }
9878760c 13746 }
b4ac57ab 13747
efdba735
SH		 13748#if TARGET_MACHO
13749 macho_branch_islands ();
0e5da0be
GK		 13750 /* Mach-O doesn't support labels at the end of objects, so if
13751 it looks like we might want one, insert a NOP. */
13752 {
13753 rtx insn = get_last_insn ();
13754 while (insn
13755 && NOTE_P (insn)
13756 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
13757 insn = PREV_INSN (insn);
f676971a
EC		 13758 if (insn
13759 && (LABEL_P (insn)
0e5da0be
GK		 13760 || (NOTE_P (insn)
13761 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
13762 fputs ("\tnop\n", file);
13763 }
13764#endif
13765
9b30bae2 13766 /* Output a traceback table here. See /usr/include/sys/debug.h for info
314fc5a9
ILT		 13767 on its format.
13768
13769 We don't output a traceback table if -finhibit-size-directive was
13770 used. The documentation for -finhibit-size-directive reads
13771 ``don't output a @code{.size} assembler directive, or anything
13772 else that would cause trouble if the function is split in the
13773 middle, and the two halves are placed at locations far apart in
13774 memory.'' The traceback table has this property, since it
13775 includes the offset from the start of the function to the
4d30c363
MM		 13776 traceback table itself.
13777
13778 System V.4 Powerpc's (and the embedded ABI derived from it) use a
b6c9286a 13779 different traceback table. */
57ac7be9
AM		 13780 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
13781 && rs6000_traceback != traceback_none)
9b30bae2 13782 {
69c75916 13783 const char *fname = NULL;
3ac88239 13784 const char *language_string = lang_hooks.name;
6041bf2f 13785 int fixed_parms = 0, float_parms = 0, parm_info = 0;
314fc5a9 13786 int i;
57ac7be9
AM		 13787 int optional_tbtab;
13788
13789 if (rs6000_traceback == traceback_full)
13790 optional_tbtab = 1;
13791 else if (rs6000_traceback == traceback_part)
13792 optional_tbtab = 0;
13793 else
13794 optional_tbtab = !optimize_size && !TARGET_ELF;
314fc5a9 13795
69c75916
AM		 13796 if (optional_tbtab)
13797 {
13798 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13799 while (*fname == '.') /* V.4 encodes . in the name */
13800 fname++;
13801
13802 /* Need label immediately before tbtab, so we can compute
13803 its offset from the function start. */
13804 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13805 ASM_OUTPUT_LABEL (file, fname);
13806 }
314fc5a9
ILT		 13807
13808 /* The .tbtab pseudo-op can only be used for the first eight
13809 expressions, since it can't handle the possibly variable
13810 length fields that follow. However, if you omit the optional
13811 fields, the assembler outputs zeros for all optional fields
13812 anyways, giving each variable length field is minimum length
13813 (as defined in sys/debug.h). Thus we can not use the .tbtab
13814 pseudo-op at all. */
13815
13816 /* An all-zero word flags the start of the tbtab, for debuggers
13817 that have to find it by searching forward from the entry
13818 point or from the current pc. */
19d2d16f 13819 fputs ("\t.long 0\n", file);
314fc5a9
ILT		 13820
13821 /* Tbtab format type. Use format type 0. */
19d2d16f 13822 fputs ("\t.byte 0,", file);
314fc5a9 13823
5fc921c1
DE		 13824 /* Language type. Unfortunately, there does not seem to be any
13825 official way to discover the language being compiled, so we
13826 use language_string.
13827 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
13828 Java is 13. Objective-C is 14. */
13829 if (! strcmp (language_string, "GNU C"))
314fc5a9 13830 i = 0;
6de9cd9a
DN		 13831 else if (! strcmp (language_string, "GNU F77")
13832 || ! strcmp (language_string, "GNU F95"))
314fc5a9 13833 i = 1;
8b83775b 13834 else if (! strcmp (language_string, "GNU Pascal"))
314fc5a9 13835 i = 2;
5fc921c1
DE		 13836 else if (! strcmp (language_string, "GNU Ada"))
13837 i = 3;
314fc5a9
ILT		 13838 else if (! strcmp (language_string, "GNU C++"))
13839 i = 9;
9517ead8
AG		 13840 else if (! strcmp (language_string, "GNU Java"))
13841 i = 13;
5fc921c1
DE		 13842 else if (! strcmp (language_string, "GNU Objective-C"))
13843 i = 14;
314fc5a9
ILT		 13844 else
13845 abort ();
13846 fprintf (file, "%d,", i);
13847
13848 /* 8 single bit fields: global linkage (not set for C extern linkage,
13849 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
13850 from start of procedure stored in tbtab, internal function, function
13851 has controlled storage, function has no toc, function uses fp,
13852 function logs/aborts fp operations. */
13853 /* Assume that fp operations are used if any fp reg must be saved. */
6041bf2f
DE		 13854 fprintf (file, "%d,",
13855 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
314fc5a9
ILT		 13856
13857 /* 6 bitfields: function is interrupt handler, name present in
13858 proc table, function calls alloca, on condition directives
13859 (controls stack walks, 3 bits), saves condition reg, saves
13860 link reg. */
13861 /* The `function calls alloca' bit seems to be set whenever reg 31 is
13862 set up as a frame pointer, even when there is no alloca call. */
13863 fprintf (file, "%d,",
6041bf2f
DE		 13864 ((optional_tbtab << 6)
13865 | ((optional_tbtab & frame_pointer_needed) << 5)
13866 | (info->cr_save_p << 1)
13867 | (info->lr_save_p)));
314fc5a9 13868
6041bf2f 13869 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
314fc5a9
ILT		 13870 (6 bits). */
13871 fprintf (file, "%d,",
4697a36c 13872 (info->push_p << 7) | (64 - info->first_fp_reg_save));
314fc5a9
ILT		 13873
13874 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
13875 fprintf (file, "%d,", (32 - first_reg_to_save ()));
13876
6041bf2f
DE		 13877 if (optional_tbtab)
13878 {
13879 /* Compute the parameter info from the function decl argument
13880 list. */
13881 tree decl;
13882 int next_parm_info_bit = 31;
314fc5a9 13883
6041bf2f
DE		 13884 for (decl = DECL_ARGUMENTS (current_function_decl);
13885 decl; decl = TREE_CHAIN (decl))
13886 {
13887 rtx parameter = DECL_INCOMING_RTL (decl);
13888 enum machine_mode mode = GET_MODE (parameter);
314fc5a9 13889
6041bf2f
DE		 13890 if (GET_CODE (parameter) == REG)
13891 {
13892 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
13893 {
13894 int bits;
13895
13896 float_parms++;
13897
13898 if (mode == SFmode)
13899 bits = 0x2;
fcce224d 13900 else if (mode == DFmode || mode == TFmode)
6041bf2f
DE		 13901 bits = 0x3;
13902 else
13903 abort ();
13904
13905 /* If only one bit will fit, don't or in this entry. */
13906 if (next_parm_info_bit > 0)
13907 parm_info |= (bits << (next_parm_info_bit - 1));
13908 next_parm_info_bit -= 2;
13909 }
13910 else
13911 {
13912 fixed_parms += ((GET_MODE_SIZE (mode)
13913 + (UNITS_PER_WORD - 1))
13914 / UNITS_PER_WORD);
13915 next_parm_info_bit -= 1;
13916 }
13917 }
13918 }
13919 }
314fc5a9
ILT		 13920
13921 /* Number of fixed point parameters. */
13922 /* This is actually the number of words of fixed point parameters; thus
13923 an 8 byte struct counts as 2; and thus the maximum value is 8. */
13924 fprintf (file, "%d,", fixed_parms);
13925
13926 /* 2 bitfields: number of floating point parameters (7 bits), parameters
13927 all on stack. */
13928 /* This is actually the number of fp registers that hold parameters;
13929 and thus the maximum value is 13. */
13930 /* Set parameters on stack bit if parameters are not in their original
13931 registers, regardless of whether they are on the stack? Xlc
13932 seems to set the bit when not optimizing. */
13933 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
13934
6041bf2f
DE		 13935 if (! optional_tbtab)
13936 return;
13937
314fc5a9
ILT		 13938 /* Optional fields follow. Some are variable length. */
13939
13940 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
13941 11 double float. */
13942 /* There is an entry for each parameter in a register, in the order that
13943 they occur in the parameter list. Any intervening arguments on the
13944 stack are ignored. If the list overflows a long (max possible length
13945 34 bits) then completely leave off all elements that don't fit. */
13946 /* Only emit this long if there was at least one parameter. */
13947 if (fixed_parms || float_parms)
13948 fprintf (file, "\t.long %d\n", parm_info);
13949
13950 /* Offset from start of code to tb table. */
19d2d16f 13951 fputs ("\t.long ", file);
314fc5a9 13952 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
85b776df
AM		 13953 if (TARGET_AIX)
13954 RS6000_OUTPUT_BASENAME (file, fname);
13955 else
13956 assemble_name (file, fname);
13957 putc ('-', file);
13958 rs6000_output_function_entry (file, fname);
19d2d16f 13959 putc ('\n', file);
314fc5a9
ILT		 13960
13961 /* Interrupt handler mask. */
13962 /* Omit this long, since we never set the interrupt handler bit
13963 above. */
13964
13965 /* Number of CTL (controlled storage) anchors. */
13966 /* Omit this long, since the has_ctl bit is never set above. */
13967
13968 /* Displacement into stack of each CTL anchor. */
13969 /* Omit this list of longs, because there are no CTL anchors. */
13970
13971 /* Length of function name. */
69c75916
AM		 13972 if (*fname == '*')
13973 ++fname;
296b8152 13974 fprintf (file, "\t.short %d\n", (int) strlen (fname));
314fc5a9
ILT		 13975
13976 /* Function name. */
13977 assemble_string (fname, strlen (fname));
13978
13979 /* Register for alloca automatic storage; this is always reg 31.
13980 Only emit this if the alloca bit was set above. */
13981 if (frame_pointer_needed)
19d2d16f 13982 fputs ("\t.byte 31\n", file);
b1765bde
DE		 13983
13984 fputs ("\t.align 2\n", file);
9b30bae2 13985 }
9878760c 13986}
17167fd8 13987\f
a4f6c312
SS		 13988/* A C compound statement that outputs the assembler code for a thunk
13989 function, used to implement C++ virtual function calls with
13990 multiple inheritance. The thunk acts as a wrapper around a virtual
13991 function, adjusting the implicit object parameter before handing
13992 control off to the real function.
13993
13994 First, emit code to add the integer DELTA to the location that
13995 contains the incoming first argument. Assume that this argument
13996 contains a pointer, and is the one used to pass the `this' pointer
13997 in C++. This is the incoming argument *before* the function
13998 prologue, e.g. `%o0' on a sparc. The addition must preserve the
13999 values of all other incoming arguments.
17167fd8
MM		 14000
14001 After the addition, emit code to jump to FUNCTION, which is a
a4f6c312
SS		 14002 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14003 not touch the return address. Hence returning from FUNCTION will
14004 return to whoever called the current `thunk'.
17167fd8 14005
a4f6c312
SS		 14006 The effect must be as if FUNCTION had been called directly with the
14007 adjusted first argument. This macro is responsible for emitting
14008 all of the code for a thunk function; output_function_prologue()
14009 and output_function_epilogue() are not invoked.
17167fd8 14010
a4f6c312
SS		 14011 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14012 been extracted from it.) It might possibly be useful on some
14013 targets, but probably not.
17167fd8 14014
a4f6c312
SS		 14015 If you do not define this macro, the target-independent code in the
14016 C++ frontend will generate a less efficient heavyweight thunk that
14017 calls FUNCTION instead of jumping to it. The generic approach does
14018 not support varargs. */
17167fd8 14019
3961e8fe 14020static void
f676971a
EC		 14021rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14022 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
a2369ed3 14023 tree function)
17167fd8 14024{
5b71a4e7 14025 rtx this, insn, funexp;
17167fd8 14026
5b71a4e7 14027 reload_completed = 1;
fe3ad572 14028 epilogue_completed = 1;
5b71a4e7 14029 no_new_pseudos = 1;
6429e3be 14030 reset_block_changes ();
56a7189a 14031
5b71a4e7 14032 /* Mark the end of the (empty) prologue. */
2e040219 14033 emit_note (NOTE_INSN_PROLOGUE_END);
17167fd8 14034
5b71a4e7
DE		 14035 /* Find the "this" pointer. If the function returns a structure,
14036 the structure return pointer is in r3. */
61f71b34 14037 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
5b71a4e7 14038 this = gen_rtx_REG (Pmode, 4);
56a7189a 14039 else
5b71a4e7 14040 this = gen_rtx_REG (Pmode, 3);
17167fd8 14041
5b71a4e7
DE		 14042 /* Apply the constant offset, if required. */
14043 if (delta)
14044 {
14045 rtx delta_rtx = GEN_INT (delta);
14046 emit_insn (TARGET_32BIT
14047 ? gen_addsi3 (this, this, delta_rtx)
14048 : gen_adddi3 (this, this, delta_rtx));
17167fd8
MM		 14049 }
14050
5b71a4e7
DE		 14051 /* Apply the offset from the vtable, if required. */
14052 if (vcall_offset)
17167fd8 14053 {
5b71a4e7
DE		 14054 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14055 rtx tmp = gen_rtx_REG (Pmode, 12);
17167fd8 14056
5b71a4e7 14057 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
eeff9307
JJ		 14058 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14059 {
14060 emit_insn (TARGET_32BIT
14061 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14062 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14063 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14064 }
14065 else
14066 {
14067 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14068
14069 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14070 }
5b71a4e7
DE		 14071 emit_insn (TARGET_32BIT
14072 ? gen_addsi3 (this, this, tmp)
14073 : gen_adddi3 (this, this, tmp));
17167fd8
MM		 14074 }
14075
5b71a4e7
DE		 14076 /* Generate a tail call to the target function. */
14077 if (!TREE_USED (function))
14078 {
14079 assemble_external (function);
14080 TREE_USED (function) = 1;
14081 }
14082 funexp = XEXP (DECL_RTL (function), 0);
5b71a4e7 14083 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
ee890fe2
SS		 14084
14085#if TARGET_MACHO
ab82a49f 14086 if (MACHOPIC_INDIRECT)
5b71a4e7 14087 funexp = machopic_indirect_call_target (funexp);
ee890fe2 14088#endif
5b71a4e7
DE		 14089
14090 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14091 generate sibcall RTL explicitly to avoid constraint abort. */
14092 insn = emit_call_insn (
14093 gen_rtx_PARALLEL (VOIDmode,
14094 gen_rtvec (4,
14095 gen_rtx_CALL (VOIDmode,
14096 funexp, const0_rtx),
14097 gen_rtx_USE (VOIDmode, const0_rtx),
14098 gen_rtx_USE (VOIDmode,
14099 gen_rtx_REG (SImode,
14100 LINK_REGISTER_REGNUM)),
14101 gen_rtx_RETURN (VOIDmode))));
14102 SIBLING_CALL_P (insn) = 1;
14103 emit_barrier ();
14104
14105 /* Run just enough of rest_of_compilation to get the insns emitted.
14106 There's not really enough bulk here to make other passes such as
14107 instruction scheduling worth while. Note that use_thunk calls
14108 assemble_start_function and assemble_end_function. */
14109 insn = get_insns ();
a2855205 14110 insn_locators_initialize ();
5b71a4e7
DE		 14111 shorten_branches (insn);
14112 final_start_function (insn, file, 1);
14113 final (insn, file, 1, 0);
14114 final_end_function ();
14115
14116 reload_completed = 0;
fe3ad572 14117 epilogue_completed = 0;
5b71a4e7 14118 no_new_pseudos = 0;
9ebbca7d 14119}
9ebbca7d
GK		 14120\f
14121/* A quick summary of the various types of 'constant-pool tables'
14122 under PowerPC:
14123
f676971a 14124 Target Flags Name One table per
9ebbca7d
GK		 14125 AIX (none) AIX TOC object file
14126 AIX -mfull-toc AIX TOC object file
14127 AIX -mminimal-toc AIX minimal TOC translation unit
14128 SVR4/EABI (none) SVR4 SDATA object file
14129 SVR4/EABI -fpic SVR4 pic object file
14130 SVR4/EABI -fPIC SVR4 PIC translation unit
14131 SVR4/EABI -mrelocatable EABI TOC function
14132 SVR4/EABI -maix AIX TOC object file
f676971a 14133 SVR4/EABI -maix -mminimal-toc
9ebbca7d
GK		 14134 AIX minimal TOC translation unit
14135
14136 Name Reg. Set by entries contains:
14137 made by addrs? fp? sum?
14138
14139 AIX TOC 2 crt0 as Y option option
14140 AIX minimal TOC 30 prolog gcc Y Y option
14141 SVR4 SDATA 13 crt0 gcc N Y N
14142 SVR4 pic 30 prolog ld Y not yet N
14143 SVR4 PIC 30 prolog gcc Y option option
14144 EABI TOC 30 prolog gcc Y option option
14145
14146*/
14147
9ebbca7d
GK		 14148/* Hash functions for the hash table. */
14149
14150static unsigned
a2369ed3 14151rs6000_hash_constant (rtx k)
9ebbca7d 14152{
46b33600
RH		 14153 enum rtx_code code = GET_CODE (k);
14154 enum machine_mode mode = GET_MODE (k);
14155 unsigned result = (code << 3) ^ mode;
14156 const char *format;
14157 int flen, fidx;
f676971a 14158
46b33600
RH		 14159 format = GET_RTX_FORMAT (code);
14160 flen = strlen (format);
14161 fidx = 0;
9ebbca7d 14162
46b33600
RH		 14163 switch (code)
14164 {
14165 case LABEL_REF:
14166 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14167
14168 case CONST_DOUBLE:
14169 if (mode != VOIDmode)
14170 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14171 flen = 2;
14172 break;
14173
14174 case CODE_LABEL:
14175 fidx = 3;
14176 break;
14177
14178 default:
14179 break;
14180 }
9ebbca7d
GK		 14181
14182 for (; fidx < flen; fidx++)
14183 switch (format[fidx])
14184 {
14185 case 's':
14186 {
14187 unsigned i, len;
14188 const char *str = XSTR (k, fidx);
14189 len = strlen (str);
14190 result = result * 613 + len;
14191 for (i = 0; i < len; i++)
14192 result = result * 613 + (unsigned) str[i];
17167fd8
MM		 14193 break;
14194 }
9ebbca7d
GK		 14195 case 'u':
14196 case 'e':
14197 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14198 break;
14199 case 'i':
14200 case 'n':
14201 result = result * 613 + (unsigned) XINT (k, fidx);
14202 break;
14203 case 'w':
14204 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14205 result = result * 613 + (unsigned) XWINT (k, fidx);
14206 else
14207 {
14208 size_t i;
9390387d 14209 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
9ebbca7d
GK		 14210 result = result * 613 + (unsigned) (XWINT (k, fidx)
14211 >> CHAR_BIT * i);
14212 }
14213 break;
09501938
DE		 14214 case '0':
14215 break;
9ebbca7d 14216 default:
a4f6c312 14217 abort ();
9ebbca7d 14218 }
46b33600 14219
9ebbca7d
GK		 14220 return result;
14221}
14222
14223static unsigned
a2369ed3 14224toc_hash_function (const void *hash_entry)
9ebbca7d 14225{
f676971a 14226 const struct toc_hash_struct *thc =
a9098fd0
GK		 14227 (const struct toc_hash_struct *) hash_entry;
14228 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
9ebbca7d
GK		 14229}
14230
14231/* Compare H1 and H2 for equivalence. */
14232
14233static int
a2369ed3 14234toc_hash_eq (const void *h1, const void *h2)
9ebbca7d
GK		 14235{
14236 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14237 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14238
a9098fd0
GK		 14239 if (((const struct toc_hash_struct *) h1)->key_mode
14240 != ((const struct toc_hash_struct *) h2)->key_mode)
14241 return 0;
14242
5692c7bc 14243 return rtx_equal_p (r1, r2);
9ebbca7d
GK		 14244}
14245
28e510bd
MM		 14246/* These are the names given by the C++ front-end to vtables, and
14247 vtable-like objects. Ideally, this logic should not be here;
14248 instead, there should be some programmatic way of inquiring as
14249 to whether or not an object is a vtable. */
14250
14251#define VTABLE_NAME_P(NAME) \
9390387d 14252 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
28e510bd
MM		 14253 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14254 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
26be75db 14255 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
f676971a 14256 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
28e510bd
MM		 14257
14258void
a2369ed3 14259rs6000_output_symbol_ref (FILE *file, rtx x)
28e510bd
MM		 14260{
14261 /* Currently C++ toc references to vtables can be emitted before it
14262 is decided whether the vtable is public or private. If this is
14263 the case, then the linker will eventually complain that there is
f676971a 14264 a reference to an unknown section. Thus, for vtables only,
28e510bd
MM		 14265 we emit the TOC reference to reference the symbol and not the
14266 section. */
14267 const char *name = XSTR (x, 0);
54ee9799 14268
f676971a 14269 if (VTABLE_NAME_P (name))
54ee9799
DE		 14270 {
14271 RS6000_OUTPUT_BASENAME (file, name);
14272 }
14273 else
14274 assemble_name (file, name);
28e510bd
MM		 14275}
14276
a4f6c312
SS		 14277/* Output a TOC entry. We derive the entry name from what is being
14278 written. */
9878760c
RK		 14279
14280void
a2369ed3 14281output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
9878760c
RK		 14282{
14283 char buf[256];
3cce094d 14284 const char *name = buf;
ec940faa 14285 const char *real_name;
9878760c
RK		 14286 rtx base = x;
14287 int offset = 0;
14288
4697a36c
MM		 14289 if (TARGET_NO_TOC)
14290 abort ();
14291
9ebbca7d
GK		 14292 /* When the linker won't eliminate them, don't output duplicate
14293 TOC entries (this happens on AIX if there is any kind of TOC,
17211ab5
GK		 14294 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14295 CODE_LABELs. */
14296 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
9ebbca7d
GK		 14297 {
14298 struct toc_hash_struct *h;
14299 void * * found;
f676971a 14300
17211ab5 14301 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
c4ad648e 14302 time because GGC is not initialized at that point. */
17211ab5 14303 if (toc_hash_table == NULL)
f676971a 14304 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
17211ab5
GK		 14305 toc_hash_eq, NULL);
14306
9ebbca7d
GK		 14307 h = ggc_alloc (sizeof (*h));
14308 h->key = x;
a9098fd0 14309 h->key_mode = mode;
9ebbca7d 14310 h->labelno = labelno;
f676971a 14311
9ebbca7d
GK		 14312 found = htab_find_slot (toc_hash_table, h, 1);
14313 if (*found == NULL)
14314 *found = h;
f676971a 14315 else /* This is indeed a duplicate.
9ebbca7d
GK		 14316 Set this label equal to that label. */
14317 {
14318 fputs ("\t.set ", file);
14319 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14320 fprintf (file, "%d,", labelno);
14321 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
f676971a 14322 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
9ebbca7d
GK		 14323 found)->labelno));
14324 return;
14325 }
14326 }
14327
14328 /* If we're going to put a double constant in the TOC, make sure it's
14329 aligned properly when strict alignment is on. */
ff1720ed
RK		 14330 if (GET_CODE (x) == CONST_DOUBLE
14331 && STRICT_ALIGNMENT
a9098fd0 14332 && GET_MODE_BITSIZE (mode) >= 64
ff1720ed
RK		 14333 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
14334 ASM_OUTPUT_ALIGN (file, 3);
14335 }
14336
4977bab6 14337 (*targetm.asm_out.internal_label) (file, "LC", labelno);
9878760c 14338
37c37a57
RK		 14339 /* Handle FP constants specially. Note that if we have a minimal
14340 TOC, things we put here aren't actually in the TOC, so we can allow
14341 FP constants. */
fcce224d
DE		 14342 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
14343 {
14344 REAL_VALUE_TYPE rv;
14345 long k[4];
14346
14347 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14348 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
14349
14350 if (TARGET_64BIT)
14351 {
14352 if (TARGET_MINIMAL_TOC)
14353 fputs (DOUBLE_INT_ASM_OP, file);
14354 else
14355 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14356 k[0] & 0xffffffff, k[1] & 0xffffffff,
14357 k[2] & 0xffffffff, k[3] & 0xffffffff);
14358 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
14359 k[0] & 0xffffffff, k[1] & 0xffffffff,
14360 k[2] & 0xffffffff, k[3] & 0xffffffff);
14361 return;
14362 }
14363 else
14364 {
14365 if (TARGET_MINIMAL_TOC)
14366 fputs ("\t.long ", file);
14367 else
14368 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14369 k[0] & 0xffffffff, k[1] & 0xffffffff,
14370 k[2] & 0xffffffff, k[3] & 0xffffffff);
14371 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14372 k[0] & 0xffffffff, k[1] & 0xffffffff,
14373 k[2] & 0xffffffff, k[3] & 0xffffffff);
14374 return;
14375 }
14376 }
14377 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9878760c 14378 {
042259f2
DE		 14379 REAL_VALUE_TYPE rv;
14380 long k[2];
0adc764e 14381
042259f2
DE		 14382 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14383 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
31bfaa0b 14384
13ded975
DE		 14385 if (TARGET_64BIT)
14386 {
14387 if (TARGET_MINIMAL_TOC)
2bfcf297 14388 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 14389 else
2f0552b6
AM		 14390 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14391 k[0] & 0xffffffff, k[1] & 0xffffffff);
14392 fprintf (file, "0x%lx%08lx\n",
14393 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 14394 return;
14395 }
1875cc88 14396 else
13ded975
DE		 14397 {
14398 if (TARGET_MINIMAL_TOC)
2bfcf297 14399 fputs ("\t.long ", file);
13ded975 14400 else
2f0552b6
AM		 14401 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14402 k[0] & 0xffffffff, k[1] & 0xffffffff);
14403 fprintf (file, "0x%lx,0x%lx\n",
14404 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 14405 return;
14406 }
9878760c 14407 }
a9098fd0 14408 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9878760c 14409 {
042259f2
DE		 14410 REAL_VALUE_TYPE rv;
14411 long l;
9878760c 14412
042259f2
DE		 14413 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14414 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
14415
31bfaa0b
DE		 14416 if (TARGET_64BIT)
14417 {
14418 if (TARGET_MINIMAL_TOC)
2bfcf297 14419 fputs (DOUBLE_INT_ASM_OP, file);
31bfaa0b 14420 else
2f0552b6
AM		 14421 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14422 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
31bfaa0b
DE		 14423 return;
14424 }
042259f2 14425 else
31bfaa0b
DE		 14426 {
14427 if (TARGET_MINIMAL_TOC)
2bfcf297 14428 fputs ("\t.long ", file);
31bfaa0b 14429 else
2f0552b6
AM		 14430 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14431 fprintf (file, "0x%lx\n", l & 0xffffffff);
31bfaa0b
DE		 14432 return;
14433 }
042259f2 14434 }
f176e826 14435 else if (GET_MODE (x) == VOIDmode
a9098fd0 14436 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
042259f2 14437 {
e2c953b6 14438 unsigned HOST_WIDE_INT low;
042259f2
DE		 14439 HOST_WIDE_INT high;
14440
14441 if (GET_CODE (x) == CONST_DOUBLE)
14442 {
14443 low = CONST_DOUBLE_LOW (x);
14444 high = CONST_DOUBLE_HIGH (x);
14445 }
14446 else
14447#if HOST_BITS_PER_WIDE_INT == 32
14448 {
14449 low = INTVAL (x);
0858c623 14450 high = (low & 0x80000000) ? ~0 : 0;
042259f2
DE		 14451 }
14452#else
14453 {
c4ad648e
AM		 14454 low = INTVAL (x) & 0xffffffff;
14455 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
042259f2
DE		 14456 }
14457#endif
9878760c 14458
a9098fd0
GK		 14459 /* TOC entries are always Pmode-sized, but since this
14460 is a bigendian machine then if we're putting smaller
14461 integer constants in the TOC we have to pad them.
14462 (This is still a win over putting the constants in
14463 a separate constant pool, because then we'd have
02a4ec28
FS		 14464 to have both a TOC entry _and_ the actual constant.)
14465
14466 For a 32-bit target, CONST_INT values are loaded and shifted
14467 entirely within `low' and can be stored in one TOC entry. */
14468
14469 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
a9098fd0 14470 abort ();/* It would be easy to make this work, but it doesn't now. */
02a4ec28
FS		 14471
14472 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
fb52d8de
AM		 14473 {
14474#if HOST_BITS_PER_WIDE_INT == 32
14475 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
14476 POINTER_SIZE, &low, &high, 0);
14477#else
14478 low |= high << 32;
14479 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
14480 high = (HOST_WIDE_INT) low >> 32;
14481 low &= 0xffffffff;
14482#endif
14483 }
a9098fd0 14484
13ded975
DE		 14485 if (TARGET_64BIT)
14486 {
14487 if (TARGET_MINIMAL_TOC)
2bfcf297 14488 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 14489 else
2f0552b6
AM		 14490 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14491 (long) high & 0xffffffff, (long) low & 0xffffffff);
14492 fprintf (file, "0x%lx%08lx\n",
14493 (long) high & 0xffffffff, (long) low & 0xffffffff);
13ded975
DE		 14494 return;
14495 }
1875cc88 14496 else
13ded975 14497 {
02a4ec28
FS		 14498 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
14499 {
14500 if (TARGET_MINIMAL_TOC)
2bfcf297 14501 fputs ("\t.long ", file);
02a4ec28 14502 else
2bfcf297 14503 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
2f0552b6
AM		 14504 (long) high & 0xffffffff, (long) low & 0xffffffff);
14505 fprintf (file, "0x%lx,0x%lx\n",
14506 (long) high & 0xffffffff, (long) low & 0xffffffff);
02a4ec28 14507 }
13ded975 14508 else
02a4ec28
FS		 14509 {
14510 if (TARGET_MINIMAL_TOC)
2bfcf297 14511 fputs ("\t.long ", file);
02a4ec28 14512 else
2f0552b6
AM		 14513 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
14514 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
02a4ec28 14515 }
13ded975
DE		 14516 return;
14517 }
9878760c
RK		 14518 }
14519
14520 if (GET_CODE (x) == CONST)
14521 {
2bfcf297
DB		 14522 if (GET_CODE (XEXP (x, 0)) != PLUS)
14523 abort ();
14524
9878760c
RK		 14525 base = XEXP (XEXP (x, 0), 0);
14526 offset = INTVAL (XEXP (XEXP (x, 0), 1));
14527 }
f676971a 14528
9878760c
RK		 14529 if (GET_CODE (base) == SYMBOL_REF)
14530 name = XSTR (base, 0);
14531 else if (GET_CODE (base) == LABEL_REF)
14532 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
14533 else if (GET_CODE (base) == CODE_LABEL)
14534 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
14535 else
14536 abort ();
14537
772c5265 14538 real_name = (*targetm.strip_name_encoding) (name);
1875cc88 14539 if (TARGET_MINIMAL_TOC)
2bfcf297 14540 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
1875cc88
JW		 14541 else
14542 {
b6c9286a 14543 fprintf (file, "\t.tc %s", real_name);
9878760c 14544
1875cc88
JW		 14545 if (offset < 0)
14546 fprintf (file, ".N%d", - offset);
14547 else if (offset)
14548 fprintf (file, ".P%d", offset);
9878760c 14549
19d2d16f 14550 fputs ("[TC],", file);
1875cc88 14551 }
581bc4de
MM		 14552
14553 /* Currently C++ toc references to vtables can be emitted before it
14554 is decided whether the vtable is public or private. If this is
14555 the case, then the linker will eventually complain that there is
14556 a TOC reference to an unknown section. Thus, for vtables only,
14557 we emit the TOC reference to reference the symbol and not the
14558 section. */
28e510bd 14559 if (VTABLE_NAME_P (name))
581bc4de 14560 {
54ee9799 14561 RS6000_OUTPUT_BASENAME (file, name);
581bc4de
MM		 14562 if (offset < 0)
14563 fprintf (file, "%d", offset);
14564 else if (offset > 0)
14565 fprintf (file, "+%d", offset);
14566 }
14567 else
14568 output_addr_const (file, x);
19d2d16f 14569 putc ('\n', file);
9878760c
RK		 14570}
14571\f
14572/* Output an assembler pseudo-op to write an ASCII string of N characters
14573 starting at P to FILE.
14574
14575 On the RS/6000, we have to do this using the .byte operation and
14576 write out special characters outside the quoted string.
14577 Also, the assembler is broken; very long strings are truncated,
a4f6c312 14578 so we must artificially break them up early. */
9878760c
RK		 14579
14580void
a2369ed3 14581output_ascii (FILE *file, const char *p, int n)
9878760c
RK		 14582{
14583 char c;
14584 int i, count_string;
d330fd93
KG		 14585 const char *for_string = "\t.byte \"";
14586 const char *for_decimal = "\t.byte ";
14587 const char *to_close = NULL;
9878760c
RK		 14588
14589 count_string = 0;
14590 for (i = 0; i < n; i++)
14591 {
14592 c = *p++;
14593 if (c >= ' ' && c < 0177)
14594 {
14595 if (for_string)
14596 fputs (for_string, file);
14597 putc (c, file);
14598
14599 /* Write two quotes to get one. */
14600 if (c == '"')
14601 {
14602 putc (c, file);
14603 ++count_string;
14604 }
14605
14606 for_string = NULL;
14607 for_decimal = "\"\n\t.byte ";
14608 to_close = "\"\n";
14609 ++count_string;
14610
14611 if (count_string >= 512)
14612 {
14613 fputs (to_close, file);
14614
14615 for_string = "\t.byte \"";
14616 for_decimal = "\t.byte ";
14617 to_close = NULL;
14618 count_string = 0;
14619 }
14620 }
14621 else
14622 {
14623 if (for_decimal)
14624 fputs (for_decimal, file);
14625 fprintf (file, "%d", c);
14626
14627 for_string = "\n\t.byte \"";
14628 for_decimal = ", ";
14629 to_close = "\n";
14630 count_string = 0;
14631 }
14632 }
14633
14634 /* Now close the string if we have written one. Then end the line. */
14635 if (to_close)
9ebbca7d 14636 fputs (to_close, file);
9878760c
RK		 14637}
14638\f
14639/* Generate a unique section name for FILENAME for a section type
14640 represented by SECTION_DESC. Output goes into BUF.
14641
14642 SECTION_DESC can be any string, as long as it is different for each
14643 possible section type.
14644
14645 We name the section in the same manner as xlc. The name begins with an
14646 underscore followed by the filename (after stripping any leading directory
11e5fe42
RK		 14647 names) with the last period replaced by the string SECTION_DESC. If
14648 FILENAME does not contain a period, SECTION_DESC is appended to the end of
14649 the name. */
9878760c
RK		 14650
14651void
f676971a 14652rs6000_gen_section_name (char **buf, const char *filename,
c4ad648e 14653 const char *section_desc)
9878760c 14654{
9ebbca7d 14655 const char *q, *after_last_slash, *last_period = 0;
9878760c
RK		 14656 char *p;
14657 int len;
9878760c
RK		 14658
14659 after_last_slash = filename;
14660 for (q = filename; *q; q++)
11e5fe42
RK		 14661 {
14662 if (*q == '/')
14663 after_last_slash = q + 1;
14664 else if (*q == '.')
14665 last_period = q;
14666 }
9878760c 14667
11e5fe42 14668 len = strlen (after_last_slash) + strlen (section_desc) + 2;
6d9f628e 14669 *buf = (char *) xmalloc (len);
9878760c
RK		 14670
14671 p = *buf;
14672 *p++ = '_';
14673
14674 for (q = after_last_slash; *q; q++)
14675 {
11e5fe42 14676 if (q == last_period)
c4ad648e 14677 {
9878760c
RK		 14678 strcpy (p, section_desc);
14679 p += strlen (section_desc);
e3981aab 14680 break;
c4ad648e 14681 }
9878760c 14682
e9a780ec 14683 else if (ISALNUM (*q))
c4ad648e 14684 *p++ = *q;
9878760c
RK		 14685 }
14686
11e5fe42 14687 if (last_period == 0)
9878760c
RK		 14688 strcpy (p, section_desc);
14689 else
14690 *p = '\0';
14691}
e165f3f0 14692\f
a4f6c312 14693/* Emit profile function. */
411707f4 14694
411707f4 14695void
a2369ed3 14696output_profile_hook (int labelno ATTRIBUTE_UNUSED)
411707f4 14697{
ffcfcb5f
AM		 14698 if (TARGET_PROFILE_KERNEL)
14699 return;
14700
8480e480
CC		 14701 if (DEFAULT_ABI == ABI_AIX)
14702 {
9739c90c
JJ		 14703#ifndef NO_PROFILE_COUNTERS
14704# define NO_PROFILE_COUNTERS 0
14705#endif
f676971a 14706 if (NO_PROFILE_COUNTERS)
9739c90c
JJ		 14707 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
14708 else
14709 {
14710 char buf[30];
14711 const char *label_name;
14712 rtx fun;
411707f4 14713
9739c90c
JJ		 14714 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14715 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
14716 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
411707f4 14717
9739c90c
JJ		 14718 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
14719 fun, Pmode);
14720 }
8480e480 14721 }
ee890fe2
SS		 14722 else if (DEFAULT_ABI == ABI_DARWIN)
14723 {
d5fa86ba 14724 const char *mcount_name = RS6000_MCOUNT;
ee890fe2
SS		 14725 int caller_addr_regno = LINK_REGISTER_REGNUM;
14726
14727 /* Be conservative and always set this, at least for now. */
14728 current_function_uses_pic_offset_table = 1;
14729
14730#if TARGET_MACHO
14731 /* For PIC code, set up a stub and collect the caller's address
14732 from r0, which is where the prologue puts it. */
11abc112
MM		 14733 if (MACHOPIC_INDIRECT
14734 && current_function_uses_pic_offset_table)
14735 caller_addr_regno = 0;
ee890fe2
SS		 14736#endif
14737 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
14738 0, VOIDmode, 1,
14739 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
14740 }
411707f4
CC		 14741}
14742
a4f6c312 14743/* Write function profiler code. */
e165f3f0
RK		 14744
14745void
a2369ed3 14746output_function_profiler (FILE *file, int labelno)
e165f3f0 14747{
3daf36a4 14748 char buf[100];
09eeeacb 14749 int save_lr = 8;
e165f3f0 14750
38c1f2d7 14751 switch (DEFAULT_ABI)
3daf36a4 14752 {
38c1f2d7
MM		 14753 default:
14754 abort ();
14755
14756 case ABI_V4:
09eeeacb 14757 save_lr = 4;
09eeeacb
AM		 14758 if (!TARGET_32BIT)
14759 {
14760 warning ("no profiling of 64-bit code for this ABI");
14761 return;
14762 }
ffcfcb5f 14763 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
38c1f2d7
MM		 14764 fprintf (file, "\tmflr %s\n", reg_names[0]);
14765 if (flag_pic == 1)
14766 {
dfdfa60f 14767 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
09eeeacb
AM		 14768 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14769 reg_names[0], save_lr, reg_names[1]);
17167fd8 14770 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
dfdfa60f 14771 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
38c1f2d7 14772 assemble_name (file, buf);
17167fd8 14773 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
38c1f2d7 14774 }
9ebbca7d 14775 else if (flag_pic > 1)
38c1f2d7 14776 {
09eeeacb
AM		 14777 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14778 reg_names[0], save_lr, reg_names[1]);
9ebbca7d
GK		 14779 /* Now, we need to get the address of the label. */
14780 fputs ("\tbl 1f\n\t.long ", file);
034e84c4 14781 assemble_name (file, buf);
9ebbca7d
GK		 14782 fputs ("-.\n1:", file);
14783 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
f676971a 14784 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
9ebbca7d
GK		 14785 reg_names[0], reg_names[11]);
14786 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
14787 reg_names[0], reg_names[0], reg_names[11]);
38c1f2d7 14788 }
38c1f2d7
MM		 14789 else
14790 {
17167fd8 14791 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
38c1f2d7 14792 assemble_name (file, buf);
dfdfa60f 14793 fputs ("@ha\n", file);
09eeeacb
AM		 14794 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14795 reg_names[0], save_lr, reg_names[1]);
a260abc9 14796 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
38c1f2d7 14797 assemble_name (file, buf);
17167fd8 14798 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
38c1f2d7
MM		 14799 }
14800
50d440bc 14801 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
3b6ce0af
DE		 14802 fprintf (file, "\tbl %s%s\n",
14803 RS6000_MCOUNT, flag_pic ? "@plt" : "");
38c1f2d7
MM		 14804 break;
14805
14806 case ABI_AIX:
ee890fe2 14807 case ABI_DARWIN:
ffcfcb5f
AM		 14808 if (!TARGET_PROFILE_KERNEL)
14809 {
a3c9585f 14810 /* Don't do anything, done in output_profile_hook (). */
ffcfcb5f
AM		 14811 }
14812 else
14813 {
14814 if (TARGET_32BIT)
14815 abort ();
14816
14817 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
14818 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
14819
6de9cd9a 14820 if (cfun->static_chain_decl != NULL)
ffcfcb5f
AM		 14821 {
14822 asm_fprintf (file, "\tstd %s,24(%s)\n",
14823 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14824 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14825 asm_fprintf (file, "\tld %s,24(%s)\n",
14826 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14827 }
14828 else
14829 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14830 }
38c1f2d7
MM		 14831 break;
14832 }
e165f3f0 14833}
a251ffd0 14834
b54cf83a 14835\f
b54cf83a
DE		 14836/* Power4 load update and store update instructions are cracked into a
14837 load or store and an integer insn which are executed in the same cycle.
14838 Branches have their own dispatch slot which does not count against the
14839 GCC issue rate, but it changes the program flow so there are no other
14840 instructions to issue in this cycle. */
14841
14842static int
f676971a
EC		 14843rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
14844 int verbose ATTRIBUTE_UNUSED,
a2369ed3 14845 rtx insn, int more)
b54cf83a
DE		 14846{
14847 if (GET_CODE (PATTERN (insn)) == USE
14848 || GET_CODE (PATTERN (insn)) == CLOBBER)
14849 return more;
14850
ec507f2d 14851 if (rs6000_sched_groups)
b54cf83a 14852 {
cbe26ab8 14853 if (is_microcoded_insn (insn))
c4ad648e 14854 return 0;
cbe26ab8 14855 else if (is_cracked_insn (insn))
c4ad648e 14856 return more > 2 ? more - 2 : 0;
b54cf83a 14857 }
165b263e
DE		 14858
14859 return more - 1;
b54cf83a
DE		 14860}
14861
a251ffd0
TG		 14862/* Adjust the cost of a scheduling dependency. Return the new cost of
14863 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
14864
c237e94a 14865static int
0a4f0294 14866rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
a251ffd0
TG		 14867{
14868 if (! recog_memoized (insn))
14869 return 0;
14870
14871 if (REG_NOTE_KIND (link) != 0)
14872 return 0;
14873
14874 if (REG_NOTE_KIND (link) == 0)
14875 {
ed947a96
DJ		 14876 /* Data dependency; DEP_INSN writes a register that INSN reads
14877 some cycles later. */
c9dbf840
DE		 14878
14879 /* Separate a load from a narrower, dependent store. */
14880 if (rs6000_sched_groups
14881 && GET_CODE (PATTERN (insn)) == SET
14882 && GET_CODE (PATTERN (dep_insn)) == SET
14883 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
14884 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
14885 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
14886 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
14887 return cost + 14;
14888
ed947a96
DJ		 14889 switch (get_attr_type (insn))
14890 {
14891 case TYPE_JMPREG:
309323c2 14892 /* Tell the first scheduling pass about the latency between
ed947a96
DJ		 14893 a mtctr and bctr (and mtlr and br/blr). The first
14894 scheduling pass will not know about this latency since
14895 the mtctr instruction, which has the latency associated
14896 to it, will be generated by reload. */
309323c2 14897 return TARGET_POWER ? 5 : 4;
ed947a96
DJ		 14898 case TYPE_BRANCH:
14899 /* Leave some extra cycles between a compare and its
14900 dependent branch, to inhibit expensive mispredicts. */
309323c2
DE		 14901 if ((rs6000_cpu_attr == CPU_PPC603
14902 || rs6000_cpu_attr == CPU_PPC604
14903 || rs6000_cpu_attr == CPU_PPC604E
14904 || rs6000_cpu_attr == CPU_PPC620
14905 || rs6000_cpu_attr == CPU_PPC630
14906 || rs6000_cpu_attr == CPU_PPC750
14907 || rs6000_cpu_attr == CPU_PPC7400
14908 || rs6000_cpu_attr == CPU_PPC7450
ec507f2d
DE		 14909 || rs6000_cpu_attr == CPU_POWER4
14910 || rs6000_cpu_attr == CPU_POWER5)
ed947a96
DJ		 14911 && recog_memoized (dep_insn)
14912 && (INSN_CODE (dep_insn) >= 0)
b54cf83a
DE		 14913 && (get_attr_type (dep_insn) == TYPE_CMP
14914 || get_attr_type (dep_insn) == TYPE_COMPARE
ed947a96 14915 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
9259f3b0
DE		 14916 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
14917 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
ed947a96 14918 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
b54cf83a
DE		 14919 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
14920 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
ed947a96
DJ		 14921 return cost + 2;
14922 default:
14923 break;
14924 }
a251ffd0
TG		 14925 /* Fall out to return default cost. */
14926 }
14927
14928 return cost;
14929}
b6c9286a 14930
cbe26ab8 14931/* The function returns a true if INSN is microcoded.
839a4992 14932 Return false otherwise. */
cbe26ab8
DN		 14933
14934static bool
14935is_microcoded_insn (rtx insn)
14936{
14937 if (!insn || !INSN_P (insn)
14938 || GET_CODE (PATTERN (insn)) == USE
14939 || GET_CODE (PATTERN (insn)) == CLOBBER)
14940 return false;
14941
ec507f2d 14942 if (rs6000_sched_groups)
cbe26ab8
DN		 14943 {
14944 enum attr_type type = get_attr_type (insn);
14945 if (type == TYPE_LOAD_EXT_U
14946 || type == TYPE_LOAD_EXT_UX
14947 || type == TYPE_LOAD_UX
14948 || type == TYPE_STORE_UX
14949 || type == TYPE_MFCR)
c4ad648e 14950 return true;
cbe26ab8
DN		 14951 }
14952
14953 return false;
14954}
14955
5c425df5 14956/* The function returns a nonzero value if INSN can be scheduled only
cbe26ab8
DN		 14957 as the first insn in a dispatch group ("dispatch-slot restricted").
14958 In this case, the returned value indicates how many dispatch slots
14959 the insn occupies (at the beginning of the group).
79ae11c4
DN		 14960 Return 0 otherwise. */
14961
cbe26ab8 14962static int
79ae11c4
DN		 14963is_dispatch_slot_restricted (rtx insn)
14964{
14965 enum attr_type type;
14966
ec507f2d 14967 if (!rs6000_sched_groups)
79ae11c4
DN		 14968 return 0;
14969
14970 if (!insn
14971 || insn == NULL_RTX
14972 || GET_CODE (insn) == NOTE
14973 || GET_CODE (PATTERN (insn)) == USE
14974 || GET_CODE (PATTERN (insn)) == CLOBBER)
14975 return 0;
14976
14977 type = get_attr_type (insn);
14978
ec507f2d
DE		 14979 switch (type)
14980 {
14981 case TYPE_MFCR:
14982 case TYPE_MFCRF:
14983 case TYPE_MTCR:
14984 case TYPE_DELAYED_CR:
14985 case TYPE_CR_LOGICAL:
14986 case TYPE_MTJMPR:
14987 case TYPE_MFJMPR:
14988 return 1;
14989 case TYPE_IDIV:
14990 case TYPE_LDIV:
14991 return 2;
14992 default:
14993 if (rs6000_cpu == PROCESSOR_POWER5
14994 && is_cracked_insn (insn))
14995 return 2;
14996 return 0;
14997 }
79ae11c4
DN		 14998}
14999
cbe26ab8
DN		 15000/* The function returns true if INSN is cracked into 2 instructions
15001 by the processor (and therefore occupies 2 issue slots). */
15002
15003static bool
15004is_cracked_insn (rtx insn)
15005{
15006 if (!insn || !INSN_P (insn)
15007 || GET_CODE (PATTERN (insn)) == USE
15008 || GET_CODE (PATTERN (insn)) == CLOBBER)
15009 return false;
15010
ec507f2d 15011 if (rs6000_sched_groups)
cbe26ab8
DN		 15012 {
15013 enum attr_type type = get_attr_type (insn);
15014 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
c4ad648e
AM		 15015 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15016 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15017 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15018 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15019 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15020 || type == TYPE_IDIV || type == TYPE_LDIV
15021 || type == TYPE_INSERT_WORD)
15022 return true;
cbe26ab8
DN		 15023 }
15024
15025 return false;
15026}
15027
15028/* The function returns true if INSN can be issued only from
a3c9585f 15029 the branch slot. */
cbe26ab8
DN		 15030
15031static bool
15032is_branch_slot_insn (rtx insn)
15033{
15034 if (!insn || !INSN_P (insn)
15035 || GET_CODE (PATTERN (insn)) == USE
15036 || GET_CODE (PATTERN (insn)) == CLOBBER)
15037 return false;
15038
ec507f2d 15039 if (rs6000_sched_groups)
cbe26ab8
DN		 15040 {
15041 enum attr_type type = get_attr_type (insn);
15042 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
f676971a 15043 return true;
cbe26ab8
DN		 15044 return false;
15045 }
15046
15047 return false;
15048}
79ae11c4 15049
a4f6c312 15050/* A C statement (sans semicolon) to update the integer scheduling
79ae11c4
DN		 15051 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15052 INSN earlier, reduce the priority to execute INSN later. Do not
a4f6c312
SS		 15053 define this macro if you do not need to adjust the scheduling
15054 priorities of insns. */
bef84347 15055
c237e94a 15056static int
a2369ed3 15057rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
bef84347 15058{
a4f6c312
SS		 15059 /* On machines (like the 750) which have asymmetric integer units,
15060 where one integer unit can do multiply and divides and the other
15061 can't, reduce the priority of multiply/divide so it is scheduled
15062 before other integer operations. */
bef84347
VM		 15063
15064#if 0
2c3c49de 15065 if (! INSN_P (insn))
bef84347
VM		 15066 return priority;
15067
15068 if (GET_CODE (PATTERN (insn)) == USE)
15069 return priority;
15070
15071 switch (rs6000_cpu_attr) {
15072 case CPU_PPC750:
15073 switch (get_attr_type (insn))
15074 {
15075 default:
15076 break;
15077
15078 case TYPE_IMUL:
15079 case TYPE_IDIV:
3cb999d8
DE		 15080 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15081 priority, priority);
bef84347
VM		 15082 if (priority >= 0 && priority < 0x01000000)
15083 priority >>= 3;
15084 break;
15085 }
15086 }
15087#endif
15088
79ae11c4
DN		 15089 if (is_dispatch_slot_restricted (insn)
15090 && reload_completed
f676971a 15091 && current_sched_info->sched_max_insns_priority
79ae11c4
DN		 15092 && rs6000_sched_restricted_insns_priority)
15093 {
15094
c4ad648e
AM		 15095 /* Prioritize insns that can be dispatched only in the first
15096 dispatch slot. */
79ae11c4 15097 if (rs6000_sched_restricted_insns_priority == 1)
f676971a
EC		 15098 /* Attach highest priority to insn. This means that in
15099 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
79ae11c4 15100 precede 'priority' (critical path) considerations. */
f676971a 15101 return current_sched_info->sched_max_insns_priority;
79ae11c4 15102 else if (rs6000_sched_restricted_insns_priority == 2)
f676971a 15103 /* Increase priority of insn by a minimal amount. This means that in
c4ad648e
AM		 15104 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15105 considerations precede dispatch-slot restriction considerations. */
f676971a
EC		 15106 return (priority + 1);
15107 }
79ae11c4 15108
bef84347
VM		 15109 return priority;
15110}
15111
a4f6c312
SS		 15112/* Return how many instructions the machine can issue per cycle. */
15113
c237e94a 15114static int
863d938c 15115rs6000_issue_rate (void)
b6c9286a 15116{
3317bab1
DE		 15117 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15118 if (!reload_completed)
15119 return 1;
15120
b6c9286a 15121 switch (rs6000_cpu_attr) {
3cb999d8
DE		 15122 case CPU_RIOS1: /* ? */
15123 case CPU_RS64A:
15124 case CPU_PPC601: /* ? */
ed947a96 15125 case CPU_PPC7450:
3cb999d8 15126 return 3;
b54cf83a 15127 case CPU_PPC440:
b6c9286a 15128 case CPU_PPC603:
bef84347 15129 case CPU_PPC750:
ed947a96 15130 case CPU_PPC7400:
be12c2b0 15131 case CPU_PPC8540:
f676971a 15132 return 2;
3cb999d8 15133 case CPU_RIOS2:
b6c9286a 15134 case CPU_PPC604:
19684119 15135 case CPU_PPC604E:
b6c9286a 15136 case CPU_PPC620:
3cb999d8 15137 case CPU_PPC630:
b6c9286a 15138 return 4;
cbe26ab8 15139 case CPU_POWER4:
ec507f2d 15140 case CPU_POWER5:
cbe26ab8 15141 return 5;
b6c9286a
MM		 15142 default:
15143 return 1;
15144 }
15145}
15146
be12c2b0
VM		 15147/* Return how many instructions to look ahead for better insn
15148 scheduling. */
15149
15150static int
863d938c 15151rs6000_use_sched_lookahead (void)
be12c2b0
VM		 15152{
15153 if (rs6000_cpu_attr == CPU_PPC8540)
15154 return 4;
15155 return 0;
15156}
15157
569fa502
DN		 15158/* Determine is PAT refers to memory. */
15159
15160static bool
15161is_mem_ref (rtx pat)
15162{
15163 const char * fmt;
15164 int i, j;
15165 bool ret = false;
15166
15167 if (GET_CODE (pat) == MEM)
15168 return true;
15169
15170 /* Recursively process the pattern. */
15171 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15172
15173 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15174 {
15175 if (fmt[i] == 'e')
15176 ret |= is_mem_ref (XEXP (pat, i));
15177 else if (fmt[i] == 'E')
15178 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15179 ret |= is_mem_ref (XVECEXP (pat, i, j));
15180 }
15181
15182 return ret;
15183}
15184
15185/* Determine if PAT is a PATTERN of a load insn. */
f676971a 15186
569fa502
DN		 15187static bool
15188is_load_insn1 (rtx pat)
15189{
15190 if (!pat || pat == NULL_RTX)
15191 return false;
15192
15193 if (GET_CODE (pat) == SET)
15194 return is_mem_ref (SET_SRC (pat));
15195
15196 if (GET_CODE (pat) == PARALLEL)
15197 {
15198 int i;
15199
15200 for (i = 0; i < XVECLEN (pat, 0); i++)
15201 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15202 return true;
15203 }
15204
15205 return false;
15206}
15207
15208/* Determine if INSN loads from memory. */
15209
15210static bool
15211is_load_insn (rtx insn)
15212{
15213 if (!insn || !INSN_P (insn))
15214 return false;
15215
15216 if (GET_CODE (insn) == CALL_INSN)
15217 return false;
15218
15219 return is_load_insn1 (PATTERN (insn));
15220}
15221
15222/* Determine if PAT is a PATTERN of a store insn. */
15223
15224static bool
15225is_store_insn1 (rtx pat)
15226{
15227 if (!pat || pat == NULL_RTX)
15228 return false;
15229
15230 if (GET_CODE (pat) == SET)
15231 return is_mem_ref (SET_DEST (pat));
15232
15233 if (GET_CODE (pat) == PARALLEL)
15234 {
15235 int i;
15236
15237 for (i = 0; i < XVECLEN (pat, 0); i++)
15238 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15239 return true;
15240 }
15241
15242 return false;
15243}
15244
15245/* Determine if INSN stores to memory. */
15246
15247static bool
15248is_store_insn (rtx insn)
15249{
15250 if (!insn || !INSN_P (insn))
15251 return false;
15252
15253 return is_store_insn1 (PATTERN (insn));
15254}
15255
15256/* Returns whether the dependence between INSN and NEXT is considered
15257 costly by the given target. */
15258
15259static bool
c4ad648e
AM		 15260rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15261 int distance)
f676971a 15262{
569fa502 15263 /* If the flag is not enbled - no dependence is considered costly;
f676971a 15264 allow all dependent insns in the same group.
569fa502
DN		 15265 This is the most aggressive option. */
15266 if (rs6000_sched_costly_dep == no_dep_costly)
15267 return false;
15268
f676971a 15269 /* If the flag is set to 1 - a dependence is always considered costly;
569fa502
DN		 15270 do not allow dependent instructions in the same group.
15271 This is the most conservative option. */
15272 if (rs6000_sched_costly_dep == all_deps_costly)
f676971a 15273 return true;
569fa502 15274
f676971a
EC		 15275 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15276 && is_load_insn (next)
569fa502
DN		 15277 && is_store_insn (insn))
15278 /* Prevent load after store in the same group. */
15279 return true;
15280
15281 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
f676971a 15282 && is_load_insn (next)
569fa502
DN		 15283 && is_store_insn (insn)
15284 && (!link || (int) REG_NOTE_KIND (link) == 0))
c4ad648e
AM		 15285 /* Prevent load after store in the same group if it is a true
15286 dependence. */
569fa502 15287 return true;
f676971a
EC		 15288
15289 /* The flag is set to X; dependences with latency >= X are considered costly,
569fa502
DN		 15290 and will not be scheduled in the same group. */
15291 if (rs6000_sched_costly_dep <= max_dep_latency
15292 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
15293 return true;
15294
15295 return false;
15296}
15297
f676971a 15298/* Return the next insn after INSN that is found before TAIL is reached,
cbe26ab8
DN		 15299 skipping any "non-active" insns - insns that will not actually occupy
15300 an issue slot. Return NULL_RTX if such an insn is not found. */
15301
15302static rtx
15303get_next_active_insn (rtx insn, rtx tail)
15304{
15305 rtx next_insn;
15306
15307 if (!insn || insn == tail)
15308 return NULL_RTX;
15309
15310 next_insn = NEXT_INSN (insn);
15311
15312 while (next_insn
15313 && next_insn != tail
9390387d 15314 && (GET_CODE (next_insn) == NOTE
cbe26ab8
DN		 15315 || GET_CODE (PATTERN (next_insn)) == USE
15316 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
15317 {
15318 next_insn = NEXT_INSN (next_insn);
15319 }
15320
15321 if (!next_insn || next_insn == tail)
15322 return NULL_RTX;
15323
15324 return next_insn;
15325}
15326
839a4992 15327/* Return whether the presence of INSN causes a dispatch group termination
cbe26ab8
DN		 15328 of group WHICH_GROUP.
15329
15330 If WHICH_GROUP == current_group, this function will return true if INSN
15331 causes the termination of the current group (i.e, the dispatch group to
15332 which INSN belongs). This means that INSN will be the last insn in the
15333 group it belongs to.
15334
15335 If WHICH_GROUP == previous_group, this function will return true if INSN
15336 causes the termination of the previous group (i.e, the dispatch group that
15337 precedes the group to which INSN belongs). This means that INSN will be
15338 the first insn in the group it belongs to). */
15339
15340static bool
15341insn_terminates_group_p (rtx insn, enum group_termination which_group)
15342{
15343 enum attr_type type;
15344
15345 if (! insn)
15346 return false;
569fa502 15347
cbe26ab8
DN		 15348 type = get_attr_type (insn);
15349
15350 if (is_microcoded_insn (insn))
15351 return true;
15352
15353 if (which_group == current_group)
15354 {
15355 if (is_branch_slot_insn (insn))
c4ad648e 15356 return true;
cbe26ab8
DN		 15357 return false;
15358 }
15359 else if (which_group == previous_group)
15360 {
15361 if (is_dispatch_slot_restricted (insn))
c4ad648e 15362 return true;
cbe26ab8
DN		 15363 return false;
15364 }
15365
15366 return false;
15367}
15368
839a4992 15369/* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
cbe26ab8
DN		 15370 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15371
15372static bool
15373is_costly_group (rtx *group_insns, rtx next_insn)
15374{
15375 int i;
15376 rtx link;
15377 int cost;
15378 int issue_rate = rs6000_issue_rate ();
15379
15380 for (i = 0; i < issue_rate; i++)
15381 {
15382 rtx insn = group_insns[i];
15383 if (!insn)
c4ad648e 15384 continue;
cbe26ab8 15385 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
c4ad648e
AM		 15386 {
15387 rtx next = XEXP (link, 0);
15388 if (next == next_insn)
15389 {
15390 cost = insn_cost (insn, link, next_insn);
15391 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
15392 return true;
15393 }
15394 }
cbe26ab8
DN		 15395 }
15396
15397 return false;
15398}
15399
f676971a 15400/* Utility of the function redefine_groups.
cbe26ab8
DN		 15401 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15402 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15403 to keep it "far" (in a separate group) from GROUP_INSNS, following
15404 one of the following schemes, depending on the value of the flag
15405 -minsert_sched_nops = X:
15406 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
839a4992 15407 in order to force NEXT_INSN into a separate group.
f676971a
EC		 15408 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15409 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
cbe26ab8
DN		 15410 insertion (has a group just ended, how many vacant issue slots remain in the
15411 last group, and how many dispatch groups were encountered so far). */
15412
f676971a 15413static int
c4ad648e
AM		 15414force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
15415 rtx next_insn, bool *group_end, int can_issue_more,
15416 int *group_count)
cbe26ab8
DN		 15417{
15418 rtx nop;
15419 bool force;
15420 int issue_rate = rs6000_issue_rate ();
15421 bool end = *group_end;
15422 int i;
15423
15424 if (next_insn == NULL_RTX)
15425 return can_issue_more;
15426
15427 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
15428 return can_issue_more;
15429
15430 force = is_costly_group (group_insns, next_insn);
15431 if (!force)
15432 return can_issue_more;
15433
15434 if (sched_verbose > 6)
15435 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
c4ad648e 15436 *group_count ,can_issue_more);
cbe26ab8
DN		 15437
15438 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
15439 {
15440 if (*group_end)
c4ad648e 15441 can_issue_more = 0;
cbe26ab8
DN		 15442
15443 /* Since only a branch can be issued in the last issue_slot, it is
15444 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15445 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
c4ad648e
AM		 15446 in this case the last nop will start a new group and the branch
15447 will be forced to the new group. */
cbe26ab8 15448 if (can_issue_more && !is_branch_slot_insn (next_insn))
c4ad648e 15449 can_issue_more--;
cbe26ab8
DN		 15450
15451 while (can_issue_more > 0)
c4ad648e 15452 {
9390387d 15453 nop = gen_nop ();
c4ad648e
AM		 15454 emit_insn_before (nop, next_insn);
15455 can_issue_more--;
15456 }
cbe26ab8
DN		 15457
15458 *group_end = true;
15459 return 0;
f676971a 15460 }
cbe26ab8
DN		 15461
15462 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
15463 {
15464 int n_nops = rs6000_sched_insert_nops;
15465
f676971a 15466 /* Nops can't be issued from the branch slot, so the effective
c4ad648e 15467 issue_rate for nops is 'issue_rate - 1'. */
cbe26ab8 15468 if (can_issue_more == 0)
c4ad648e 15469 can_issue_more = issue_rate;
cbe26ab8
DN		 15470 can_issue_more--;
15471 if (can_issue_more == 0)
c4ad648e
AM		 15472 {
15473 can_issue_more = issue_rate - 1;
15474 (*group_count)++;
15475 end = true;
15476 for (i = 0; i < issue_rate; i++)
15477 {
15478 group_insns[i] = 0;
15479 }
15480 }
cbe26ab8
DN		 15481
15482 while (n_nops > 0)
c4ad648e
AM		 15483 {
15484 nop = gen_nop ();
15485 emit_insn_before (nop, next_insn);
15486 if (can_issue_more == issue_rate - 1) /* new group begins */
15487 end = false;
15488 can_issue_more--;
15489 if (can_issue_more == 0)
15490 {
15491 can_issue_more = issue_rate - 1;
15492 (*group_count)++;
15493 end = true;
15494 for (i = 0; i < issue_rate; i++)
15495 {
15496 group_insns[i] = 0;
15497 }
15498 }
15499 n_nops--;
15500 }
cbe26ab8
DN		 15501
15502 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
f676971a 15503 can_issue_more++;
cbe26ab8 15504
c4ad648e
AM		 15505 /* Is next_insn going to start a new group? */
15506 *group_end
15507 = (end
cbe26ab8
DN		 15508 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15509 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15510 || (can_issue_more < issue_rate &&
c4ad648e 15511 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 15512 if (*group_end && end)
c4ad648e 15513 (*group_count)--;
cbe26ab8
DN		 15514
15515 if (sched_verbose > 6)
c4ad648e
AM		 15516 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
15517 *group_count, can_issue_more);
f676971a
EC		 15518 return can_issue_more;
15519 }
cbe26ab8
DN		 15520
15521 return can_issue_more;
15522}
15523
15524/* This function tries to synch the dispatch groups that the compiler "sees"
f676971a 15525 with the dispatch groups that the processor dispatcher is expected to
cbe26ab8
DN		 15526 form in practice. It tries to achieve this synchronization by forcing the
15527 estimated processor grouping on the compiler (as opposed to the function
15528 'pad_goups' which tries to force the scheduler's grouping on the processor).
15529
15530 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15531 examines the (estimated) dispatch groups that will be formed by the processor
15532 dispatcher. It marks these group boundaries to reflect the estimated
15533 processor grouping, overriding the grouping that the scheduler had marked.
15534 Depending on the value of the flag '-minsert-sched-nops' this function can
15535 force certain insns into separate groups or force a certain distance between
15536 them by inserting nops, for example, if there exists a "costly dependence"
15537 between the insns.
15538
15539 The function estimates the group boundaries that the processor will form as
15540 folllows: It keeps track of how many vacant issue slots are available after
15541 each insn. A subsequent insn will start a new group if one of the following
15542 4 cases applies:
15543 - no more vacant issue slots remain in the current dispatch group.
15544 - only the last issue slot, which is the branch slot, is vacant, but the next
15545 insn is not a branch.
15546 - only the last 2 or less issue slots, including the branch slot, are vacant,
15547 which means that a cracked insn (which occupies two issue slots) can't be
15548 issued in this group.
f676971a 15549 - less than 'issue_rate' slots are vacant, and the next insn always needs to
cbe26ab8
DN		 15550 start a new group. */
15551
15552static int
15553redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15554{
15555 rtx insn, next_insn;
15556 int issue_rate;
15557 int can_issue_more;
15558 int slot, i;
15559 bool group_end;
15560 int group_count = 0;
15561 rtx *group_insns;
15562
15563 /* Initialize. */
15564 issue_rate = rs6000_issue_rate ();
15565 group_insns = alloca (issue_rate * sizeof (rtx));
f676971a 15566 for (i = 0; i < issue_rate; i++)
cbe26ab8
DN		 15567 {
15568 group_insns[i] = 0;
15569 }
15570 can_issue_more = issue_rate;
15571 slot = 0;
15572 insn = get_next_active_insn (prev_head_insn, tail);
15573 group_end = false;
15574
15575 while (insn != NULL_RTX)
15576 {
15577 slot = (issue_rate - can_issue_more);
15578 group_insns[slot] = insn;
15579 can_issue_more =
c4ad648e 15580 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
cbe26ab8 15581 if (insn_terminates_group_p (insn, current_group))
c4ad648e 15582 can_issue_more = 0;
cbe26ab8
DN		 15583
15584 next_insn = get_next_active_insn (insn, tail);
15585 if (next_insn == NULL_RTX)
c4ad648e 15586 return group_count + 1;
cbe26ab8 15587
c4ad648e
AM		 15588 /* Is next_insn going to start a new group? */
15589 group_end
15590 = (can_issue_more == 0
15591 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15592 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15593 || (can_issue_more < issue_rate &&
15594 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 15595
f676971a 15596 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
c4ad648e
AM		 15597 next_insn, &group_end, can_issue_more,
15598 &group_count);
cbe26ab8
DN		 15599
15600 if (group_end)
c4ad648e
AM		 15601 {
15602 group_count++;
15603 can_issue_more = 0;
15604 for (i = 0; i < issue_rate; i++)
15605 {
15606 group_insns[i] = 0;
15607 }
15608 }
cbe26ab8
DN		 15609
15610 if (GET_MODE (next_insn) == TImode && can_issue_more)
9390387d 15611 PUT_MODE (next_insn, VOIDmode);
cbe26ab8 15612 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
c4ad648e 15613 PUT_MODE (next_insn, TImode);
cbe26ab8
DN		 15614
15615 insn = next_insn;
15616 if (can_issue_more == 0)
c4ad648e
AM		 15617 can_issue_more = issue_rate;
15618 } /* while */
cbe26ab8
DN		 15619
15620 return group_count;
15621}
15622
15623/* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
15624 dispatch group boundaries that the scheduler had marked. Pad with nops
15625 any dispatch groups which have vacant issue slots, in order to force the
15626 scheduler's grouping on the processor dispatcher. The function
15627 returns the number of dispatch groups found. */
15628
15629static int
15630pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15631{
15632 rtx insn, next_insn;
15633 rtx nop;
15634 int issue_rate;
15635 int can_issue_more;
15636 int group_end;
15637 int group_count = 0;
15638
15639 /* Initialize issue_rate. */
15640 issue_rate = rs6000_issue_rate ();
15641 can_issue_more = issue_rate;
15642
15643 insn = get_next_active_insn (prev_head_insn, tail);
15644 next_insn = get_next_active_insn (insn, tail);
15645
15646 while (insn != NULL_RTX)
15647 {
15648 can_issue_more =
15649 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15650
15651 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
15652
15653 if (next_insn == NULL_RTX)
c4ad648e 15654 break;
cbe26ab8
DN		 15655
15656 if (group_end)
c4ad648e
AM		 15657 {
15658 /* If the scheduler had marked group termination at this location
15659 (between insn and next_indn), and neither insn nor next_insn will
15660 force group termination, pad the group with nops to force group
15661 termination. */
15662 if (can_issue_more
15663 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
15664 && !insn_terminates_group_p (insn, current_group)
15665 && !insn_terminates_group_p (next_insn, previous_group))
15666 {
9390387d 15667 if (!is_branch_slot_insn (next_insn))
c4ad648e
AM		 15668 can_issue_more--;
15669
15670 while (can_issue_more)
15671 {
15672 nop = gen_nop ();
15673 emit_insn_before (nop, next_insn);
15674 can_issue_more--;
15675 }
15676 }
15677
15678 can_issue_more = issue_rate;
15679 group_count++;
15680 }
cbe26ab8
DN		 15681
15682 insn = next_insn;
15683 next_insn = get_next_active_insn (insn, tail);
15684 }
15685
15686 return group_count;
15687}
15688
15689/* The following function is called at the end of scheduling BB.
15690 After reload, it inserts nops at insn group bundling. */
15691
15692static void
38f391a5 15693rs6000_sched_finish (FILE *dump, int sched_verbose)
cbe26ab8
DN		 15694{
15695 int n_groups;
15696
15697 if (sched_verbose)
15698 fprintf (dump, "=== Finishing schedule.\n");
15699
ec507f2d 15700 if (reload_completed && rs6000_sched_groups)
cbe26ab8
DN		 15701 {
15702 if (rs6000_sched_insert_nops == sched_finish_none)
c4ad648e 15703 return;
cbe26ab8
DN		 15704
15705 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
c4ad648e
AM		 15706 n_groups = pad_groups (dump, sched_verbose,
15707 current_sched_info->prev_head,
15708 current_sched_info->next_tail);
cbe26ab8 15709 else
c4ad648e
AM		 15710 n_groups = redefine_groups (dump, sched_verbose,
15711 current_sched_info->prev_head,
15712 current_sched_info->next_tail);
cbe26ab8
DN		 15713
15714 if (sched_verbose >= 6)
15715 {
15716 fprintf (dump, "ngroups = %d\n", n_groups);
15717 print_rtl (dump, current_sched_info->prev_head);
15718 fprintf (dump, "Done finish_sched\n");
15719 }
15720 }
15721}
b6c9286a 15722\f
b6c9286a
MM		 15723/* Length in units of the trampoline for entering a nested function. */
15724
15725int
863d938c 15726rs6000_trampoline_size (void)
b6c9286a
MM		 15727{
15728 int ret = 0;
15729
15730 switch (DEFAULT_ABI)
15731 {
15732 default:
15733 abort ();
15734
15735 case ABI_AIX:
8f802bfb 15736 ret = (TARGET_32BIT) ? 12 : 24;
b6c9286a
MM		 15737 break;
15738
4dabc42d 15739 case ABI_DARWIN:
b6c9286a 15740 case ABI_V4:
03a7e1a5 15741 ret = (TARGET_32BIT) ? 40 : 48;
b6c9286a 15742 break;
b6c9286a
MM		 15743 }
15744
15745 return ret;
15746}
15747
15748/* Emit RTL insns to initialize the variable parts of a trampoline.
15749 FNADDR is an RTX for the address of the function's pure code.
15750 CXT is an RTX for the static chain value for the function. */
15751
15752void
a2369ed3 15753rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
b6c9286a 15754{
ac2a93a1 15755 enum machine_mode pmode = Pmode;
8bd04c56
MM		 15756 int regsize = (TARGET_32BIT) ? 4 : 8;
15757 rtx ctx_reg = force_reg (pmode, cxt);
b6c9286a
MM		 15758
15759 switch (DEFAULT_ABI)
15760 {
15761 default:
15762 abort ();
15763
8bd04c56 15764/* Macros to shorten the code expansions below. */
39403d82 15765#define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
c5c76735
JL		 15766#define MEM_PLUS(addr,offset) \
15767 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
7c59dc5d 15768
b6c9286a
MM		 15769 /* Under AIX, just build the 3 word function descriptor */
15770 case ABI_AIX:
8bd04c56
MM		 15771 {
15772 rtx fn_reg = gen_reg_rtx (pmode);
15773 rtx toc_reg = gen_reg_rtx (pmode);
15774 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
1cb18e3c 15775 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
8bd04c56
MM		 15776 emit_move_insn (MEM_DEREF (addr), fn_reg);
15777 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
15778 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
15779 }
b6c9286a
MM		 15780 break;
15781
4dabc42d
TC		 15782 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
15783 case ABI_DARWIN:
b6c9286a 15784 case ABI_V4:
39403d82 15785 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
eaf1bcf1
MM		 15786 FALSE, VOIDmode, 4,
15787 addr, pmode,
15788 GEN_INT (rs6000_trampoline_size ()), SImode,
15789 fnaddr, pmode,
15790 ctx_reg, pmode);
b6c9286a 15791 break;
b6c9286a
MM		 15792 }
15793
15794 return;
15795}
7509c759
MM		 15796
15797\f
91d231cb 15798/* Table of valid machine attributes. */
a4f6c312 15799
91d231cb 15800const struct attribute_spec rs6000_attribute_table[] =
7509c759 15801{
91d231cb 15802 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8bb418a3 15803 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
a5c76ee6
ZW		 15804 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15805 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
005c1a13
GK		 15806#ifdef SUBTARGET_ATTRIBUTE_TABLE
15807 SUBTARGET_ATTRIBUTE_TABLE,
15808#endif
a5c76ee6 15809 { NULL, 0, 0, false, false, false, NULL }
91d231cb 15810};
7509c759 15811
8bb418a3
ZL		 15812/* Handle the "altivec" attribute. The attribute may have
15813 arguments as follows:
f676971a 15814
8bb418a3
ZL		 15815 __attribute__((altivec(vector__)))
15816 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
15817 __attribute__((altivec(bool__))) (always followed by 'unsigned')
15818
15819 and may appear more than once (e.g., 'vector bool char') in a
15820 given declaration. */
15821
15822static tree
f90ac3f0
UP		 15823rs6000_handle_altivec_attribute (tree *node,
15824 tree name ATTRIBUTE_UNUSED,
15825 tree args,
8bb418a3
ZL		 15826 int flags ATTRIBUTE_UNUSED,
15827 bool *no_add_attrs)
15828{
15829 tree type = *node, result = NULL_TREE;
15830 enum machine_mode mode;
15831 int unsigned_p;
15832 char altivec_type
15833 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
15834 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
15835 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
f676971a 15836 : '?');
8bb418a3
ZL		 15837
15838 while (POINTER_TYPE_P (type)
15839 || TREE_CODE (type) == FUNCTION_TYPE
15840 || TREE_CODE (type) == METHOD_TYPE
15841 || TREE_CODE (type) == ARRAY_TYPE)
15842 type = TREE_TYPE (type);
15843
15844 mode = TYPE_MODE (type);
15845
f90ac3f0
UP		 15846 /* Check for invalid AltiVec type qualifiers. */
15847 if (type == long_unsigned_type_node || type == long_integer_type_node)
15848 {
15849 if (TARGET_64BIT)
15850 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
15851 else if (rs6000_warn_altivec_long)
15852 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
15853 }
15854 else if (type == long_long_unsigned_type_node
15855 || type == long_long_integer_type_node)
15856 error ("use of %<long long%> in AltiVec types is invalid");
15857 else if (type == double_type_node)
15858 error ("use of %<double%> in AltiVec types is invalid");
15859 else if (type == long_double_type_node)
15860 error ("use of %<long double%> in AltiVec types is invalid");
15861 else if (type == boolean_type_node)
15862 error ("use of boolean types in AltiVec types is invalid");
15863 else if (TREE_CODE (type) == COMPLEX_TYPE)
15864 error ("use of %<complex%> in AltiVec types is invalid");
8bb418a3
ZL		 15865
15866 switch (altivec_type)
15867 {
15868 case 'v':
8df83eae 15869 unsigned_p = TYPE_UNSIGNED (type);
8bb418a3
ZL		 15870 switch (mode)
15871 {
c4ad648e
AM		 15872 case SImode:
15873 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
15874 break;
15875 case HImode:
15876 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
15877 break;
15878 case QImode:
15879 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
15880 break;
15881 case SFmode: result = V4SF_type_node; break;
15882 /* If the user says 'vector int bool', we may be handed the 'bool'
15883 attribute _before_ the 'vector' attribute, and so select the
15884 proper type in the 'b' case below. */
15885 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
15886 result = type;
15887 default: break;
8bb418a3
ZL		 15888 }
15889 break;
15890 case 'b':
15891 switch (mode)
15892 {
c4ad648e
AM		 15893 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
15894 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
15895 case QImode: case V16QImode: result = bool_V16QI_type_node;
15896 default: break;
8bb418a3
ZL		 15897 }
15898 break;
15899 case 'p':
15900 switch (mode)
15901 {
c4ad648e
AM		 15902 case V8HImode: result = pixel_V8HI_type_node;
15903 default: break;
8bb418a3
ZL		 15904 }
15905 default: break;
15906 }
15907
7958a2a6
FJ		 15908 if (result && result != type && TYPE_READONLY (type))
15909 result = build_qualified_type (result, TYPE_QUAL_CONST);
15910
8bb418a3
ZL		 15911 *no_add_attrs = true; /* No need to hang on to the attribute. */
15912
f90ac3f0 15913 if (result)
8bb418a3
ZL		 15914 *node = reconstruct_complex_type (*node, result);
15915
15916 return NULL_TREE;
15917}
15918
f18eca82
ZL		 15919/* AltiVec defines four built-in scalar types that serve as vector
15920 elements; we must teach the compiler how to mangle them. */
15921
15922static const char *
15923rs6000_mangle_fundamental_type (tree type)
15924{
15925 if (type == bool_char_type_node) return "U6__boolc";
15926 if (type == bool_short_type_node) return "U6__bools";
15927 if (type == pixel_type_node) return "u7__pixel";
15928 if (type == bool_int_type_node) return "U6__booli";
15929
15930 /* For all other types, use normal C++ mangling. */
15931 return NULL;
15932}
15933
a5c76ee6
ZW		 15934/* Handle a "longcall" or "shortcall" attribute; arguments as in
15935 struct attribute_spec.handler. */
a4f6c312 15936
91d231cb 15937static tree
f676971a
EC		 15938rs6000_handle_longcall_attribute (tree *node, tree name,
15939 tree args ATTRIBUTE_UNUSED,
15940 int flags ATTRIBUTE_UNUSED,
a2369ed3 15941 bool *no_add_attrs)
91d231cb
JM		 15942{
15943 if (TREE_CODE (*node) != FUNCTION_TYPE
15944 && TREE_CODE (*node) != FIELD_DECL
15945 && TREE_CODE (*node) != TYPE_DECL)
15946 {
9e637a26 15947 warning ("%qs attribute only applies to functions",
91d231cb
JM		 15948 IDENTIFIER_POINTER (name));
15949 *no_add_attrs = true;
15950 }
6a4cee5f 15951
91d231cb 15952 return NULL_TREE;
7509c759
MM		 15953}
15954
a5c76ee6
ZW		 15955/* Set longcall attributes on all functions declared when
15956 rs6000_default_long_calls is true. */
15957static void
a2369ed3 15958rs6000_set_default_type_attributes (tree type)
a5c76ee6
ZW		 15959{
15960 if (rs6000_default_long_calls
15961 && (TREE_CODE (type) == FUNCTION_TYPE
15962 || TREE_CODE (type) == METHOD_TYPE))
15963 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
15964 NULL_TREE,
15965 TYPE_ATTRIBUTES (type));
15966}
15967
3cb999d8
DE		 15968/* Return a reference suitable for calling a function with the
15969 longcall attribute. */
a4f6c312 15970
9390387d 15971rtx
a2369ed3 15972rs6000_longcall_ref (rtx call_ref)
6a4cee5f 15973{
d330fd93 15974 const char *call_name;
6a4cee5f
MM		 15975 tree node;
15976
15977 if (GET_CODE (call_ref) != SYMBOL_REF)
15978 return call_ref;
15979
15980 /* System V adds '.' to the internal name, so skip them. */
15981 call_name = XSTR (call_ref, 0);
15982 if (*call_name == '.')
15983 {
15984 while (*call_name == '.')
15985 call_name++;
15986
15987 node = get_identifier (call_name);
39403d82 15988 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
6a4cee5f
MM		 15989 }
15990
15991 return force_reg (Pmode, call_ref);
15992}
7509c759 15993\f
b64a1b53
RH		 15994#ifdef USING_ELFOS_H
15995
7509c759
MM		 15996/* A C statement or statements to switch to the appropriate section
15997 for output of RTX in mode MODE. You can assume that RTX is some
15998 kind of constant in RTL. The argument MODE is redundant except in
15999 the case of a `const_int' rtx. Select the section by calling
16000 `text_section' or one of the alternatives for other sections.
16001
16002 Do not define this macro if you put all constants in the read-only
16003 data section. */
16004
b64a1b53 16005static void
f676971a 16006rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
a2369ed3 16007 unsigned HOST_WIDE_INT align)
7509c759 16008{
a9098fd0 16009 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
7509c759 16010 toc_section ();
7509c759 16011 else
b64a1b53 16012 default_elf_select_rtx_section (mode, x, align);
7509c759
MM		 16013}
16014
16015/* A C statement or statements to switch to the appropriate
16016 section for output of DECL. DECL is either a `VAR_DECL' node
16017 or a constant of some sort. RELOC indicates whether forming
16018 the initial value of DECL requires link-time relocations. */
16019
ae46c4e0 16020static void
f676971a 16021rs6000_elf_select_section (tree decl, int reloc,
a2369ed3 16022 unsigned HOST_WIDE_INT align)
7509c759 16023{
f1384257
AM		 16024 /* Pretend that we're always building for a shared library when
16025 ABI_AIX, because otherwise we end up with dynamic relocations
16026 in read-only sections. This happens for function pointers,
16027 references to vtables in typeinfo, and probably other cases. */
0e5dbd9b
DE		 16028 default_elf_select_section_1 (decl, reloc, align,
16029 flag_pic || DEFAULT_ABI == ABI_AIX);
63019373
GK		 16030}
16031
16032/* A C statement to build up a unique section name, expressed as a
16033 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16034 RELOC indicates whether the initial value of EXP requires
16035 link-time relocations. If you do not define this macro, GCC will use
16036 the symbol name prefixed by `.' as the section name. Note - this
f5143c46 16037 macro can now be called for uninitialized data items as well as
4912a07c 16038 initialized data and functions. */
63019373 16039
ae46c4e0 16040static void
a2369ed3 16041rs6000_elf_unique_section (tree decl, int reloc)
63019373 16042{
f1384257
AM		 16043 /* As above, pretend that we're always building for a shared library
16044 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
0e5dbd9b
DE		 16045 default_unique_section_1 (decl, reloc,
16046 flag_pic || DEFAULT_ABI == ABI_AIX);
7509c759 16047}
d9407988 16048\f
d1908feb
JJ		 16049/* For a SYMBOL_REF, set generic flags and then perform some
16050 target-specific processing.
16051
d1908feb
JJ		 16052 When the AIX ABI is requested on a non-AIX system, replace the
16053 function name with the real name (with a leading .) rather than the
16054 function descriptor name. This saves a lot of overriding code to
16055 read the prefixes. */
d9407988 16056
fb49053f 16057static void
a2369ed3 16058rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
d9407988 16059{
d1908feb 16060 default_encode_section_info (decl, rtl, first);
b2003250 16061
d1908feb
JJ		 16062 if (first
16063 && TREE_CODE (decl) == FUNCTION_DECL
16064 && !TARGET_AIX
16065 && DEFAULT_ABI == ABI_AIX)
d9407988 16066 {
c6a2438a 16067 rtx sym_ref = XEXP (rtl, 0);
d1908feb
JJ		 16068 size_t len = strlen (XSTR (sym_ref, 0));
16069 char *str = alloca (len + 2);
16070 str[0] = '.';
16071 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16072 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
d9407988 16073 }
d9407988
MM		 16074}
16075
0e5dbd9b 16076static bool
a2369ed3 16077rs6000_elf_in_small_data_p (tree decl)
0e5dbd9b
DE		 16078{
16079 if (rs6000_sdata == SDATA_NONE)
16080 return false;
16081
7482ad25
AF		 16082 /* We want to merge strings, so we never consider them small data. */
16083 if (TREE_CODE (decl) == STRING_CST)
16084 return false;
16085
16086 /* Functions are never in the small data area. */
16087 if (TREE_CODE (decl) == FUNCTION_DECL)
16088 return false;
16089
0e5dbd9b
DE		 16090 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16091 {
16092 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16093 if (strcmp (section, ".sdata") == 0
16094 || strcmp (section, ".sdata2") == 0
20bfcd69
GK		 16095 || strcmp (section, ".sbss") == 0
16096 || strcmp (section, ".sbss2") == 0
16097 || strcmp (section, ".PPC.EMB.sdata0") == 0
16098 || strcmp (section, ".PPC.EMB.sbss0") == 0)
0e5dbd9b
DE		 16099 return true;
16100 }
16101 else
16102 {
16103 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16104
16105 if (size > 0
307b599c 16106 && (unsigned HOST_WIDE_INT) size <= g_switch_value
20bfcd69
GK		 16107 /* If it's not public, and we're not going to reference it there,
16108 there's no need to put it in the small data section. */
0e5dbd9b
DE		 16109 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16110 return true;
16111 }
16112
16113 return false;
16114}
16115
b91da81f 16116#endif /* USING_ELFOS_H */
000034eb 16117
a6c2a102 16118\f
000034eb 16119/* Return a REG that occurs in ADDR with coefficient 1.
02441cd6
JL		 16120 ADDR can be effectively incremented by incrementing REG.
16121
16122 r0 is special and we must not select it as an address
16123 register by this routine since our caller will try to
16124 increment the returned register via an "la" instruction. */
000034eb 16125
9390387d 16126rtx
a2369ed3 16127find_addr_reg (rtx addr)
000034eb
DE		 16128{
16129 while (GET_CODE (addr) == PLUS)
16130 {
02441cd6
JL		 16131 if (GET_CODE (XEXP (addr, 0)) == REG
16132 && REGNO (XEXP (addr, 0)) != 0)
000034eb 16133 addr = XEXP (addr, 0);
02441cd6
JL		 16134 else if (GET_CODE (XEXP (addr, 1)) == REG
16135 && REGNO (XEXP (addr, 1)) != 0)
000034eb
DE		 16136 addr = XEXP (addr, 1);
16137 else if (CONSTANT_P (XEXP (addr, 0)))
16138 addr = XEXP (addr, 1);
16139 else if (CONSTANT_P (XEXP (addr, 1)))
16140 addr = XEXP (addr, 0);
16141 else
16142 abort ();
16143 }
02441cd6 16144 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
000034eb
DE		 16145 return addr;
16146 abort ();
16147}
16148
a6c2a102 16149void
a2369ed3 16150rs6000_fatal_bad_address (rtx op)
a6c2a102
DE		 16151{
16152 fatal_insn ("bad address", op);
16153}
c8023011 16154
ee890fe2
SS		 16155#if TARGET_MACHO
16156
efdba735 16157static tree branch_island_list = 0;
ee890fe2 16158
efdba735
SH		 16159/* Remember to generate a branch island for far calls to the given
16160 function. */
ee890fe2 16161
f676971a 16162static void
c4ad648e
AM		 16163add_compiler_branch_island (tree label_name, tree function_name,
16164 int line_number)
ee890fe2 16165{
efdba735 16166 tree branch_island = build_tree_list (function_name, label_name);
7d60be94 16167 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
efdba735
SH		 16168 TREE_CHAIN (branch_island) = branch_island_list;
16169 branch_island_list = branch_island;
ee890fe2
SS		 16170}
16171
efdba735
SH		 16172#define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16173#define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16174#define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16175 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
ee890fe2 16176
efdba735
SH		 16177/* Generate far-jump branch islands for everything on the
16178 branch_island_list. Invoked immediately after the last instruction
16179 of the epilogue has been emitted; the branch-islands must be
16180 appended to, and contiguous with, the function body. Mach-O stubs
16181 are generated in machopic_output_stub(). */
ee890fe2 16182
efdba735
SH		 16183static void
16184macho_branch_islands (void)
16185{
16186 char tmp_buf[512];
16187 tree branch_island;
16188
16189 for (branch_island = branch_island_list;
16190 branch_island;
16191 branch_island = TREE_CHAIN (branch_island))
16192 {
16193 const char *label =
16194 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16195 const char *name =
11abc112 16196 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
efdba735
SH		 16197 char name_buf[512];
16198 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16199 if (name[0] == '*' || name[0] == '&')
16200 strcpy (name_buf, name+1);
16201 else
16202 {
16203 name_buf[0] = '_';
16204 strcpy (name_buf+1, name);
16205 }
16206 strcpy (tmp_buf, "\n");
16207 strcat (tmp_buf, label);
ee890fe2 16208#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16209 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16210 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16211#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735
SH		 16212 if (flag_pic)
16213 {
16214 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16215 strcat (tmp_buf, label);
16216 strcat (tmp_buf, "_pic\n");
16217 strcat (tmp_buf, label);
16218 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
f676971a 16219
efdba735
SH		 16220 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16221 strcat (tmp_buf, name_buf);
16222 strcat (tmp_buf, " - ");
16223 strcat (tmp_buf, label);
16224 strcat (tmp_buf, "_pic)\n");
f676971a 16225
efdba735 16226 strcat (tmp_buf, "\tmtlr r0\n");
f676971a 16227
efdba735
SH		 16228 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16229 strcat (tmp_buf, name_buf);
16230 strcat (tmp_buf, " - ");
16231 strcat (tmp_buf, label);
16232 strcat (tmp_buf, "_pic)\n");
f676971a 16233
efdba735
SH		 16234 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16235 }
16236 else
16237 {
16238 strcat (tmp_buf, ":\nlis r12,hi16(");
16239 strcat (tmp_buf, name_buf);
16240 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16241 strcat (tmp_buf, name_buf);
16242 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16243 }
16244 output_asm_insn (tmp_buf, 0);
ee890fe2 16245#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16246 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16247 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16248#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735 16249 }
ee890fe2 16250
efdba735 16251 branch_island_list = 0;
ee890fe2
SS		 16252}
16253
16254/* NO_PREVIOUS_DEF checks in the link list whether the function name is
16255 already there or not. */
16256
efdba735 16257static int
a2369ed3 16258no_previous_def (tree function_name)
ee890fe2 16259{
efdba735
SH		 16260 tree branch_island;
16261 for (branch_island = branch_island_list;
16262 branch_island;
16263 branch_island = TREE_CHAIN (branch_island))
16264 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
ee890fe2
SS		 16265 return 0;
16266 return 1;
16267}
16268
16269/* GET_PREV_LABEL gets the label name from the previous definition of
16270 the function. */
16271
efdba735 16272static tree
a2369ed3 16273get_prev_label (tree function_name)
ee890fe2 16274{
efdba735
SH		 16275 tree branch_island;
16276 for (branch_island = branch_island_list;
16277 branch_island;
16278 branch_island = TREE_CHAIN (branch_island))
16279 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16280 return BRANCH_ISLAND_LABEL_NAME (branch_island);
ee890fe2
SS		 16281 return 0;
16282}
16283
16284/* INSN is either a function call or a millicode call. It may have an
f676971a 16285 unconditional jump in its delay slot.
ee890fe2
SS		 16286
16287 CALL_DEST is the routine we are calling. */
16288
16289char *
c4ad648e
AM		 16290output_call (rtx insn, rtx *operands, int dest_operand_number,
16291 int cookie_operand_number)
ee890fe2
SS		 16292{
16293 static char buf[256];
efdba735
SH		 16294 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
16295 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
ee890fe2
SS		 16296 {
16297 tree labelname;
efdba735 16298 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
f676971a 16299
ee890fe2
SS		 16300 if (no_previous_def (funname))
16301 {
308c142a 16302 int line_number = 0;
ee890fe2
SS		 16303 rtx label_rtx = gen_label_rtx ();
16304 char *label_buf, temp_buf[256];
16305 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
16306 CODE_LABEL_NUMBER (label_rtx));
16307 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
16308 labelname = get_identifier (label_buf);
16309 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
16310 if (insn)
16311 line_number = NOTE_LINE_NUMBER (insn);
efdba735 16312 add_compiler_branch_island (labelname, funname, line_number);
ee890fe2
SS		 16313 }
16314 else
16315 labelname = get_prev_label (funname);
16316
efdba735
SH		 16317 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16318 instruction will reach 'foo', otherwise link as 'bl L42'".
16319 "L42" should be a 'branch island', that will do a far jump to
16320 'foo'. Branch islands are generated in
16321 macho_branch_islands(). */
ee890fe2 16322 sprintf (buf, "jbsr %%z%d,%.246s",
efdba735 16323 dest_operand_number, IDENTIFIER_POINTER (labelname));
ee890fe2
SS		 16324 }
16325 else
efdba735
SH		 16326 sprintf (buf, "bl %%z%d", dest_operand_number);
16327 return buf;
ee890fe2
SS		 16328}
16329
ee890fe2
SS		 16330/* Generate PIC and indirect symbol stubs. */
16331
16332void
a2369ed3 16333machopic_output_stub (FILE *file, const char *symb, const char *stub)
ee890fe2
SS		 16334{
16335 unsigned int length;
a4f6c312
SS		 16336 char *symbol_name, *lazy_ptr_name;
16337 char *local_label_0;
ee890fe2
SS		 16338 static int label = 0;
16339
df56a27f 16340 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
772c5265 16341 symb = (*targetm.strip_name_encoding) (symb);
df56a27f 16342
ee890fe2 16343
ee890fe2
SS		 16344 length = strlen (symb);
16345 symbol_name = alloca (length + 32);
16346 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16347
16348 lazy_ptr_name = alloca (length + 32);
16349 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
16350
ee890fe2 16351 if (flag_pic == 2)
d3c300d2 16352 machopic_picsymbol_stub1_section ();
ee890fe2 16353 else
d3c300d2 16354 machopic_symbol_stub1_section ();
ee890fe2
SS		 16355
16356 if (flag_pic == 2)
16357 {
d974312d
DJ		 16358 fprintf (file, "\t.align 5\n");
16359
16360 fprintf (file, "%s:\n", stub);
16361 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16362
876455fa 16363 label++;
9390387d 16364 local_label_0 = alloca (sizeof ("\"L0000000000$spb\""));
876455fa 16365 sprintf (local_label_0, "\"L%011d$spb\"", label);
f676971a 16366
ee890fe2
SS		 16367 fprintf (file, "\tmflr r0\n");
16368 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
16369 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
16370 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
16371 lazy_ptr_name, local_label_0);
16372 fprintf (file, "\tmtlr r0\n");
3d0e2d58
SS		 16373 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
16374 (TARGET_64BIT ? "ldu" : "lwzu"),
ee890fe2
SS		 16375 lazy_ptr_name, local_label_0);
16376 fprintf (file, "\tmtctr r12\n");
ee890fe2
SS		 16377 fprintf (file, "\tbctr\n");
16378 }
16379 else
d974312d
DJ		 16380 {
16381 fprintf (file, "\t.align 4\n");
16382
16383 fprintf (file, "%s:\n", stub);
16384 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16385
16386 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
d9e4e4f5
SS		 16387 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
16388 (TARGET_64BIT ? "ldu" : "lwzu"),
16389 lazy_ptr_name);
d974312d
DJ		 16390 fprintf (file, "\tmtctr r12\n");
16391 fprintf (file, "\tbctr\n");
16392 }
f676971a 16393
ee890fe2
SS		 16394 machopic_lazy_symbol_ptr_section ();
16395 fprintf (file, "%s:\n", lazy_ptr_name);
16396 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
49bd1d27
SS		 16397 fprintf (file, "%sdyld_stub_binding_helper\n",
16398 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
ee890fe2
SS		 16399}
16400
16401/* Legitimize PIC addresses. If the address is already
16402 position-independent, we return ORIG. Newly generated
16403 position-independent addresses go into a reg. This is REG if non
16404 zero, otherwise we allocate register(s) as necessary. */
16405
9390387d 16406#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
ee890fe2
SS		 16407
16408rtx
f676971a 16409rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
a2369ed3 16410 rtx reg)
ee890fe2
SS		 16411{
16412 rtx base, offset;
16413
16414 if (reg == NULL && ! reload_in_progress && ! reload_completed)
16415 reg = gen_reg_rtx (Pmode);
16416
16417 if (GET_CODE (orig) == CONST)
16418 {
16419 if (GET_CODE (XEXP (orig, 0)) == PLUS
16420 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
16421 return orig;
16422
16423 if (GET_CODE (XEXP (orig, 0)) == PLUS)
16424 {
2cf520bf 16425 /* Use a different reg for the intermediate value, as
a3c9585f 16426 it will be marked UNCHANGING. */
2cf520bf
GK		 16427 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
16428
a4f6c312
SS		 16429 base =
16430 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
2cf520bf 16431 Pmode, reg_temp);
a4f6c312
SS		 16432 offset =
16433 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
16434 Pmode, reg);
ee890fe2
SS		 16435 }
16436 else
16437 abort ();
16438
16439 if (GET_CODE (offset) == CONST_INT)
16440 {
16441 if (SMALL_INT (offset))
ed8908e7 16442 return plus_constant (base, INTVAL (offset));
ee890fe2
SS		 16443 else if (! reload_in_progress && ! reload_completed)
16444 offset = force_reg (Pmode, offset);
16445 else
c859cda6
DJ		 16446 {
16447 rtx mem = force_const_mem (Pmode, orig);
16448 return machopic_legitimize_pic_address (mem, Pmode, reg);
16449 }
ee890fe2 16450 }
f1c25d3b 16451 return gen_rtx_PLUS (Pmode, base, offset);
ee890fe2
SS		 16452 }
16453
16454 /* Fall back on generic machopic code. */
16455 return machopic_legitimize_pic_address (orig, mode, reg);
16456}
16457
16458/* This is just a placeholder to make linking work without having to
16459 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16460 ever needed for Darwin (not too likely!) this would have to get a
16461 real definition. */
16462
16463void
863d938c 16464toc_section (void)
ee890fe2
SS		 16465{
16466}
16467
c4e18b1c
GK		 16468/* Output a .machine directive for the Darwin assembler, and call
16469 the generic start_file routine. */
16470
16471static void
16472rs6000_darwin_file_start (void)
16473{
94ff898d 16474 static const struct
c4e18b1c
GK		 16475 {
16476 const char *arg;
16477 const char *name;
16478 int if_set;
16479 } mapping[] = {
55dbfb48 16480 { "ppc64", "ppc64", MASK_64BIT },
c4e18b1c
GK		 16481 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
16482 { "power4", "ppc970", 0 },
16483 { "G5", "ppc970", 0 },
16484 { "7450", "ppc7450", 0 },
16485 { "7400", "ppc7400", MASK_ALTIVEC },
16486 { "G4", "ppc7400", 0 },
16487 { "750", "ppc750", 0 },
16488 { "740", "ppc750", 0 },
16489 { "G3", "ppc750", 0 },
16490 { "604e", "ppc604e", 0 },
16491 { "604", "ppc604", 0 },
16492 { "603e", "ppc603", 0 },
16493 { "603", "ppc603", 0 },
16494 { "601", "ppc601", 0 },
16495 { NULL, "ppc", 0 } };
16496 const char *cpu_id = "";
16497 size_t i;
94ff898d 16498
9390387d 16499 rs6000_file_start ();
c4e18b1c
GK		 16500
16501 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
16502 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
16503 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
16504 && rs6000_select[i].string[0] != '\0')
16505 cpu_id = rs6000_select[i].string;
16506
16507 /* Look through the mapping array. Pick the first name that either
16508 matches the argument, has a bit set in IF_SET that is also set
16509 in the target flags, or has a NULL name. */
16510
16511 i = 0;
16512 while (mapping[i].arg != NULL
16513 && strcmp (mapping[i].arg, cpu_id) != 0
16514 && (mapping[i].if_set & target_flags) == 0)
16515 i++;
16516
16517 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
16518}
16519
ee890fe2 16520#endif /* TARGET_MACHO */
7c262518
RH		 16521
16522#if TARGET_ELF
16523static unsigned int
a2369ed3 16524rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
7c262518 16525{
1ff8f81a
AM		 16526 return default_section_type_flags_1 (decl, name, reloc,
16527 flag_pic || DEFAULT_ABI == ABI_AIX);
7c262518 16528}
d9f6800d
RH		 16529
16530/* Record an element in the table of global constructors. SYMBOL is
16531 a SYMBOL_REF of the function to be called; PRIORITY is a number
16532 between 0 and MAX_INIT_PRIORITY.
16533
16534 This differs from default_named_section_asm_out_constructor in
16535 that we have special handling for -mrelocatable. */
16536
16537static void
a2369ed3 16538rs6000_elf_asm_out_constructor (rtx symbol, int priority)
d9f6800d
RH		 16539{
16540 const char *section = ".ctors";
16541 char buf[16];
16542
16543 if (priority != DEFAULT_INIT_PRIORITY)
16544 {
16545 sprintf (buf, ".ctors.%.5u",
c4ad648e
AM		 16546 /* Invert the numbering so the linker puts us in the proper
16547 order; constructors are run from right to left, and the
16548 linker sorts in increasing order. */
16549 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 16550 section = buf;
16551 }
16552
715bdd29
RH		 16553 named_section_flags (section, SECTION_WRITE);
16554 assemble_align (POINTER_SIZE);
d9f6800d
RH		 16555
16556 if (TARGET_RELOCATABLE)
16557 {
16558 fputs ("\t.long (", asm_out_file);
16559 output_addr_const (asm_out_file, symbol);
16560 fputs (")@fixup\n", asm_out_file);
16561 }
16562 else
c8af3574 16563 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d
RH		 16564}
16565
16566static void
a2369ed3 16567rs6000_elf_asm_out_destructor (rtx symbol, int priority)
d9f6800d
RH		 16568{
16569 const char *section = ".dtors";
16570 char buf[16];
16571
16572 if (priority != DEFAULT_INIT_PRIORITY)
16573 {
16574 sprintf (buf, ".dtors.%.5u",
c4ad648e
AM		 16575 /* Invert the numbering so the linker puts us in the proper
16576 order; constructors are run from right to left, and the
16577 linker sorts in increasing order. */
16578 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 16579 section = buf;
16580 }
16581
715bdd29
RH		 16582 named_section_flags (section, SECTION_WRITE);
16583 assemble_align (POINTER_SIZE);
d9f6800d
RH		 16584
16585 if (TARGET_RELOCATABLE)
16586 {
16587 fputs ("\t.long (", asm_out_file);
16588 output_addr_const (asm_out_file, symbol);
16589 fputs (")@fixup\n", asm_out_file);
16590 }
16591 else
c8af3574 16592 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d 16593}
9739c90c
JJ		 16594
16595void
a2369ed3 16596rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
9739c90c
JJ		 16597{
16598 if (TARGET_64BIT)
16599 {
16600 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
16601 ASM_OUTPUT_LABEL (file, name);
16602 fputs (DOUBLE_INT_ASM_OP, file);
85b776df
AM		 16603 rs6000_output_function_entry (file, name);
16604 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
16605 if (DOT_SYMBOLS)
9739c90c 16606 {
85b776df 16607 fputs ("\t.size\t", file);
9739c90c 16608 assemble_name (file, name);
85b776df
AM		 16609 fputs (",24\n\t.type\t.", file);
16610 assemble_name (file, name);
16611 fputs (",@function\n", file);
16612 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
16613 {
16614 fputs ("\t.globl\t.", file);
16615 assemble_name (file, name);
16616 putc ('\n', file);
16617 }
9739c90c 16618 }
85b776df
AM		 16619 else
16620 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
9739c90c 16621 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
85b776df
AM		 16622 rs6000_output_function_entry (file, name);
16623 fputs (":\n", file);
9739c90c
JJ		 16624 return;
16625 }
16626
16627 if (TARGET_RELOCATABLE
16628 && (get_pool_size () != 0 || current_function_profile)
3c9eb5f4 16629 && uses_TOC ())
9739c90c
JJ		 16630 {
16631 char buf[256];
16632
16633 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
16634
16635 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
16636 fprintf (file, "\t.long ");
16637 assemble_name (file, buf);
16638 putc ('-', file);
16639 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
16640 assemble_name (file, buf);
16641 putc ('\n', file);
16642 }
16643
16644 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16645 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16646
16647 if (DEFAULT_ABI == ABI_AIX)
16648 {
16649 const char *desc_name, *orig_name;
16650
16651 orig_name = (*targetm.strip_name_encoding) (name);
16652 desc_name = orig_name;
16653 while (*desc_name == '.')
16654 desc_name++;
16655
16656 if (TREE_PUBLIC (decl))
16657 fprintf (file, "\t.globl %s\n", desc_name);
16658
16659 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
16660 fprintf (file, "%s:\n", desc_name);
16661 fprintf (file, "\t.long %s\n", orig_name);
16662 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
16663 if (DEFAULT_ABI == ABI_AIX)
16664 fputs ("\t.long 0\n", file);
16665 fprintf (file, "\t.previous\n");
16666 }
16667 ASM_OUTPUT_LABEL (file, name);
16668}
7c262518
RH		 16669#endif
16670
cbaaba19 16671#if TARGET_XCOFF
7c262518 16672static void
a2369ed3 16673rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
b275d088
DE		 16674{
16675 fputs (GLOBAL_ASM_OP, stream);
16676 RS6000_OUTPUT_BASENAME (stream, name);
16677 putc ('\n', stream);
16678}
16679
16680static void
c18a5b6c
MM		 16681rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
16682 tree decl ATTRIBUTE_UNUSED)
7c262518 16683{
0e5dbd9b
DE		 16684 int smclass;
16685 static const char * const suffix[3] = { "PR", "RO", "RW" };
16686
16687 if (flags & SECTION_CODE)
16688 smclass = 0;
16689 else if (flags & SECTION_WRITE)
16690 smclass = 2;
16691 else
16692 smclass = 1;
16693
5b5198f7 16694 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
0e5dbd9b 16695 (flags & SECTION_CODE) ? "." : "",
5b5198f7 16696 name, suffix[smclass], flags & SECTION_ENTSIZE);
7c262518 16697}
ae46c4e0
RH		 16698
16699static void
f676971a 16700rs6000_xcoff_select_section (tree decl, int reloc,
c4ad648e 16701 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
ae46c4e0 16702{
5add3202 16703 if (decl_readonly_section_1 (decl, reloc, 1))
ae46c4e0 16704 {
0e5dbd9b 16705 if (TREE_PUBLIC (decl))
c4ad648e 16706 read_only_data_section ();
ae46c4e0 16707 else
c4ad648e 16708 read_only_private_data_section ();
ae46c4e0
RH		 16709 }
16710 else
16711 {
0e5dbd9b 16712 if (TREE_PUBLIC (decl))
c4ad648e 16713 data_section ();
ae46c4e0 16714 else
c4ad648e 16715 private_data_section ();
ae46c4e0
RH		 16716 }
16717}
16718
16719static void
a2369ed3 16720rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
ae46c4e0
RH		 16721{
16722 const char *name;
ae46c4e0 16723
5b5198f7
DE		 16724 /* Use select_section for private and uninitialized data. */
16725 if (!TREE_PUBLIC (decl)
16726 || DECL_COMMON (decl)
0e5dbd9b
DE		 16727 || DECL_INITIAL (decl) == NULL_TREE
16728 || DECL_INITIAL (decl) == error_mark_node
16729 || (flag_zero_initialized_in_bss
16730 && initializer_zerop (DECL_INITIAL (decl))))
16731 return;
16732
16733 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
16734 name = (*targetm.strip_name_encoding) (name);
16735 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
ae46c4e0 16736}
b64a1b53 16737
fb49053f
RH		 16738/* Select section for constant in constant pool.
16739
16740 On RS/6000, all constants are in the private read-only data area.
16741 However, if this is being placed in the TOC it must be output as a
16742 toc entry. */
16743
b64a1b53 16744static void
f676971a 16745rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
c4ad648e 16746 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
b64a1b53
RH		 16747{
16748 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16749 toc_section ();
16750 else
16751 read_only_private_data_section ();
16752}
772c5265
RH		 16753
16754/* Remove any trailing [DS] or the like from the symbol name. */
16755
16756static const char *
a2369ed3 16757rs6000_xcoff_strip_name_encoding (const char *name)
772c5265
RH		 16758{
16759 size_t len;
16760 if (*name == '*')
16761 name++;
16762 len = strlen (name);
16763 if (name[len - 1] == ']')
16764 return ggc_alloc_string (name, len - 4);
16765 else
16766 return name;
16767}
16768
5add3202
DE		 16769/* Section attributes. AIX is always PIC. */
16770
16771static unsigned int
a2369ed3 16772rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
5add3202 16773{
5b5198f7
DE		 16774 unsigned int align;
16775 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
16776
16777 /* Align to at least UNIT size. */
16778 if (flags & SECTION_CODE)
16779 align = MIN_UNITS_PER_WORD;
16780 else
16781 /* Increase alignment of large objects if not already stricter. */
16782 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
16783 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
16784 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
16785
16786 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
5add3202 16787}
a5fe455b 16788
1bc7c5b6
ZW		 16789/* Output at beginning of assembler file.
16790
16791 Initialize the section names for the RS/6000 at this point.
16792
16793 Specify filename, including full path, to assembler.
16794
16795 We want to go into the TOC section so at least one .toc will be emitted.
16796 Also, in order to output proper .bs/.es pairs, we need at least one static
16797 [RW] section emitted.
16798
16799 Finally, declare mcount when profiling to make the assembler happy. */
16800
16801static void
863d938c 16802rs6000_xcoff_file_start (void)
1bc7c5b6
ZW		 16803{
16804 rs6000_gen_section_name (&xcoff_bss_section_name,
16805 main_input_filename, ".bss_");
16806 rs6000_gen_section_name (&xcoff_private_data_section_name,
16807 main_input_filename, ".rw_");
16808 rs6000_gen_section_name (&xcoff_read_only_section_name,
16809 main_input_filename, ".ro_");
16810
16811 fputs ("\t.file\t", asm_out_file);
16812 output_quoted_string (asm_out_file, main_input_filename);
16813 fputc ('\n', asm_out_file);
1bc7c5b6
ZW		 16814 if (write_symbols != NO_DEBUG)
16815 private_data_section ();
16816 text_section ();
16817 if (profile_flag)
16818 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
16819 rs6000_file_start ();
16820}
16821
a5fe455b
ZW		 16822/* Output at end of assembler file.
16823 On the RS/6000, referencing data should automatically pull in text. */
16824
16825static void
863d938c 16826rs6000_xcoff_file_end (void)
a5fe455b
ZW		 16827{
16828 text_section ();
16829 fputs ("_section_.text:\n", asm_out_file);
16830 data_section ();
16831 fputs (TARGET_32BIT
16832 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
16833 asm_out_file);
16834}
f1384257 16835#endif /* TARGET_XCOFF */
0e5dbd9b 16836
f1384257
AM		 16837#if TARGET_MACHO
16838/* Cross-module name binding. Darwin does not support overriding
7f3d8013 16839 functions at dynamic-link time. */
0e5dbd9b 16840
2bcc50d0 16841static bool
a2369ed3 16842rs6000_binds_local_p (tree decl)
0e5dbd9b 16843{
f1384257 16844 return default_binds_local_p_1 (decl, 0);
0e5dbd9b 16845}
f1384257 16846#endif
34bb030a 16847
3c50106f
RH		 16848/* Compute a (partial) cost for rtx X. Return true if the complete
16849 cost has been computed, and false if subexpressions should be
16850 scanned. In either case, *TOTAL contains the cost result. */
16851
16852static bool
1494c534 16853rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
3c50106f 16854{
f0517163
RS		 16855 enum machine_mode mode = GET_MODE (x);
16856
3c50106f
RH		 16857 switch (code)
16858 {
30a555d9 16859 /* On the RS/6000, if it is valid in the insn, it is free. */
3c50106f 16860 case CONST_INT:
066cd967
DE		 16861 if (((outer_code == SET
16862 || outer_code == PLUS
16863 || outer_code == MINUS)
16864 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16865 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
066cd967
DE		 16866 || (outer_code == AND
16867 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
22e54023
DE		 16868 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16869 mode == SImode ? 'L' : 'J'))
d5861a7a 16870 || mask_operand (x, VOIDmode)))
22e54023
DE		 16871 || ((outer_code == IOR || outer_code == XOR)
16872 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16873 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16874 mode == SImode ? 'L' : 'J'))))
066cd967
DE		 16875 || outer_code == ASHIFT
16876 || outer_code == ASHIFTRT
16877 || outer_code == LSHIFTRT
16878 || outer_code == ROTATE
16879 || outer_code == ROTATERT
d5861a7a 16880 || outer_code == ZERO_EXTRACT
066cd967
DE		 16881 || (outer_code == MULT
16882 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
22e54023
DE		 16883 || ((outer_code == DIV || outer_code == UDIV
16884 || outer_code == MOD || outer_code == UMOD)
16885 && exact_log2 (INTVAL (x)) >= 0)
066cd967
DE		 16886 || (outer_code == COMPARE
16887 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
22e54023
DE		 16888 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
16889 || (outer_code == EQ
16890 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16891 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16892 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16893 mode == SImode ? 'L' : 'J'))))
16894 || (outer_code == GTU
16895 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16896 || (outer_code == LTU
16897 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
066cd967
DE		 16898 {
16899 *total = 0;
16900 return true;
16901 }
16902 else if ((outer_code == PLUS
16903 && reg_or_add_cint64_operand (x, VOIDmode))
16904 || (outer_code == MINUS
16905 && reg_or_sub_cint64_operand (x, VOIDmode))
16906 || ((outer_code == SET
16907 || outer_code == IOR
16908 || outer_code == XOR)
16909 && (INTVAL (x)
16910 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
16911 {
16912 *total = COSTS_N_INSNS (1);
16913 return true;
16914 }
16915 /* FALLTHRU */
16916
16917 case CONST_DOUBLE:
16918 if (mode == DImode
16919 && ((outer_code == AND
16920 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16921 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
d5861a7a 16922 || mask64_operand (x, DImode)))
066cd967
DE		 16923 || ((outer_code == IOR || outer_code == XOR)
16924 && CONST_DOUBLE_HIGH (x) == 0
16925 && (CONST_DOUBLE_LOW (x)
16926 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
16927 {
16928 *total = 0;
16929 return true;
16930 }
16931 else if (mode == DImode
16932 && (outer_code == SET
16933 || outer_code == IOR
16934 || outer_code == XOR)
16935 && CONST_DOUBLE_HIGH (x) == 0)
16936 {
16937 *total = COSTS_N_INSNS (1);
16938 return true;
16939 }
16940 /* FALLTHRU */
16941
3c50106f 16942 case CONST:
066cd967 16943 case HIGH:
3c50106f 16944 case SYMBOL_REF:
066cd967
DE		 16945 case MEM:
16946 /* When optimizing for size, MEM should be slightly more expensive
16947 than generating address, e.g., (plus (reg) (const)).
c112cf2b 16948 L1 cache latency is about two instructions. */
066cd967 16949 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
3c50106f
RH		 16950 return true;
16951
30a555d9
DE		 16952 case LABEL_REF:
16953 *total = 0;
16954 return true;
16955
3c50106f 16956 case PLUS:
f0517163 16957 if (mode == DFmode)
066cd967
DE		 16958 {
16959 if (GET_CODE (XEXP (x, 0)) == MULT)
16960 {
16961 /* FNMA accounted in outer NEG. */
16962 if (outer_code == NEG)
16963 *total = rs6000_cost->dmul - rs6000_cost->fp;
16964 else
16965 *total = rs6000_cost->dmul;
16966 }
16967 else
16968 *total = rs6000_cost->fp;
16969 }
f0517163 16970 else if (mode == SFmode)
066cd967
DE		 16971 {
16972 /* FNMA accounted in outer NEG. */
16973 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16974 *total = 0;
16975 else
16976 *total = rs6000_cost->fp;
16977 }
938bf747
RS		 16978 else if (GET_CODE (XEXP (x, 0)) == MULT)
16979 {
16980 /* The rs6000 doesn't have shift-and-add instructions. */
16981 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
16982 *total += COSTS_N_INSNS (1);
16983 }
f0517163 16984 else
066cd967
DE		 16985 *total = COSTS_N_INSNS (1);
16986 return false;
3c50106f 16987
52190329 16988 case MINUS:
f0517163 16989 if (mode == DFmode)
066cd967
DE		 16990 {
16991 if (GET_CODE (XEXP (x, 0)) == MULT)
16992 {
16993 /* FNMA accounted in outer NEG. */
16994 if (outer_code == NEG)
16995 *total = 0;
16996 else
16997 *total = rs6000_cost->dmul;
16998 }
16999 else
17000 *total = rs6000_cost->fp;
17001 }
f0517163 17002 else if (mode == SFmode)
066cd967
DE		 17003 {
17004 /* FNMA accounted in outer NEG. */
17005 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17006 *total = 0;
17007 else
17008 *total = rs6000_cost->fp;
17009 }
938bf747
RS		 17010 else if (GET_CODE (XEXP (x, 0)) == MULT)
17011 {
17012 /* The rs6000 doesn't have shift-and-sub instructions. */
17013 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17014 *total += COSTS_N_INSNS (1);
17015 }
f0517163 17016 else
c4ad648e 17017 *total = COSTS_N_INSNS (1);
066cd967 17018 return false;
3c50106f
RH		 17019
17020 case MULT:
c9dbf840
DE		 17021 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17022 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
3c50106f 17023 {
8b897cfa
RS		 17024 if (INTVAL (XEXP (x, 1)) >= -256
17025 && INTVAL (XEXP (x, 1)) <= 255)
06a67bdd 17026 *total = rs6000_cost->mulsi_const9;
8b897cfa 17027 else
06a67bdd 17028 *total = rs6000_cost->mulsi_const;
3c50106f 17029 }
066cd967
DE		 17030 /* FMA accounted in outer PLUS/MINUS. */
17031 else if ((mode == DFmode || mode == SFmode)
17032 && (outer_code == PLUS || outer_code == MINUS))
17033 *total = 0;
f0517163 17034 else if (mode == DFmode)
06a67bdd 17035 *total = rs6000_cost->dmul;
f0517163 17036 else if (mode == SFmode)
06a67bdd 17037 *total = rs6000_cost->fp;
f0517163 17038 else if (mode == DImode)
06a67bdd 17039 *total = rs6000_cost->muldi;
8b897cfa 17040 else
06a67bdd 17041 *total = rs6000_cost->mulsi;
066cd967 17042 return false;
3c50106f
RH		 17043
17044 case DIV:
17045 case MOD:
f0517163
RS		 17046 if (FLOAT_MODE_P (mode))
17047 {
06a67bdd
RS		 17048 *total = mode == DFmode ? rs6000_cost->ddiv
17049 : rs6000_cost->sdiv;
066cd967 17050 return false;
f0517163 17051 }
5efb1046 17052 /* FALLTHRU */
3c50106f
RH		 17053
17054 case UDIV:
17055 case UMOD:
627b6fe2
DJ		 17056 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17057 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17058 {
17059 if (code == DIV || code == MOD)
17060 /* Shift, addze */
17061 *total = COSTS_N_INSNS (2);
17062 else
17063 /* Shift */
17064 *total = COSTS_N_INSNS (1);
17065 }
c4ad648e 17066 else
627b6fe2
DJ		 17067 {
17068 if (GET_MODE (XEXP (x, 1)) == DImode)
17069 *total = rs6000_cost->divdi;
17070 else
17071 *total = rs6000_cost->divsi;
17072 }
17073 /* Add in shift and subtract for MOD. */
17074 if (code == MOD || code == UMOD)
17075 *total += COSTS_N_INSNS (2);
066cd967 17076 return false;
3c50106f
RH		 17077
17078 case FFS:
17079 *total = COSTS_N_INSNS (4);
066cd967 17080 return false;
3c50106f 17081
06a67bdd 17082 case NOT:
066cd967
DE		 17083 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17084 {
17085 *total = 0;
17086 return false;
17087 }
17088 /* FALLTHRU */
17089
17090 case AND:
17091 case IOR:
17092 case XOR:
d5861a7a
DE		 17093 case ZERO_EXTRACT:
17094 *total = COSTS_N_INSNS (1);
17095 return false;
17096
066cd967
DE		 17097 case ASHIFT:
17098 case ASHIFTRT:
17099 case LSHIFTRT:
17100 case ROTATE:
17101 case ROTATERT:
d5861a7a 17102 /* Handle mul_highpart. */
066cd967
DE		 17103 if (outer_code == TRUNCATE
17104 && GET_CODE (XEXP (x, 0)) == MULT)
17105 {
17106 if (mode == DImode)
17107 *total = rs6000_cost->muldi;
17108 else
17109 *total = rs6000_cost->mulsi;
17110 return true;
17111 }
d5861a7a
DE		 17112 else if (outer_code == AND)
17113 *total = 0;
17114 else
17115 *total = COSTS_N_INSNS (1);
17116 return false;
17117
17118 case SIGN_EXTEND:
17119 case ZERO_EXTEND:
17120 if (GET_CODE (XEXP (x, 0)) == MEM)
17121 *total = 0;
17122 else
17123 *total = COSTS_N_INSNS (1);
066cd967 17124 return false;
06a67bdd 17125
066cd967
DE		 17126 case COMPARE:
17127 case NEG:
17128 case ABS:
17129 if (!FLOAT_MODE_P (mode))
17130 {
17131 *total = COSTS_N_INSNS (1);
17132 return false;
17133 }
17134 /* FALLTHRU */
17135
17136 case FLOAT:
17137 case UNSIGNED_FLOAT:
17138 case FIX:
17139 case UNSIGNED_FIX:
17140 case FLOAT_EXTEND:
06a67bdd
RS		 17141 case FLOAT_TRUNCATE:
17142 *total = rs6000_cost->fp;
066cd967 17143 return false;
06a67bdd
RS		 17144
17145 case UNSPEC:
17146 switch (XINT (x, 1))
17147 {
17148 case UNSPEC_FRSP:
17149 *total = rs6000_cost->fp;
17150 return true;
17151
17152 default:
17153 break;
17154 }
17155 break;
17156
17157 case CALL:
17158 case IF_THEN_ELSE:
17159 if (optimize_size)
17160 {
17161 *total = COSTS_N_INSNS (1);
17162 return true;
17163 }
066cd967
DE		 17164 else if (FLOAT_MODE_P (mode)
17165 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17166 {
17167 *total = rs6000_cost->fp;
17168 return false;
17169 }
06a67bdd
RS		 17170 break;
17171
c0600ecd
DE		 17172 case EQ:
17173 case GTU:
17174 case LTU:
22e54023
DE		 17175 /* Carry bit requires mode == Pmode.
17176 NEG or PLUS already counted so only add one. */
17177 if (mode == Pmode
17178 && (outer_code == NEG || outer_code == PLUS))
c0600ecd 17179 {
22e54023
DE		 17180 *total = COSTS_N_INSNS (1);
17181 return true;
17182 }
17183 if (outer_code == SET)
17184 {
17185 if (XEXP (x, 1) == const0_rtx)
c0600ecd 17186 {
22e54023 17187 *total = COSTS_N_INSNS (2);
c0600ecd 17188 return true;
c0600ecd 17189 }
22e54023
DE		 17190 else if (mode == Pmode)
17191 {
17192 *total = COSTS_N_INSNS (3);
17193 return false;
17194 }
17195 }
17196 /* FALLTHRU */
17197
17198 case GT:
17199 case LT:
17200 case UNORDERED:
17201 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17202 {
17203 *total = COSTS_N_INSNS (2);
17204 return true;
c0600ecd 17205 }
22e54023
DE		 17206 /* CC COMPARE. */
17207 if (outer_code == COMPARE)
17208 {
17209 *total = 0;
17210 return true;
17211 }
17212 break;
c0600ecd 17213
3c50106f 17214 default:
06a67bdd 17215 break;
3c50106f 17216 }
06a67bdd
RS		 17217
17218 return false;
3c50106f
RH		 17219}
17220
34bb030a
DE		 17221/* A C expression returning the cost of moving data from a register of class
17222 CLASS1 to one of CLASS2. */
17223
17224int
f676971a 17225rs6000_register_move_cost (enum machine_mode mode,
a2369ed3 17226 enum reg_class from, enum reg_class to)
34bb030a
DE		 17227{
17228 /* Moves from/to GENERAL_REGS. */
17229 if (reg_classes_intersect_p (to, GENERAL_REGS)
17230 || reg_classes_intersect_p (from, GENERAL_REGS))
17231 {
17232 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17233 from = to;
17234
17235 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17236 return (rs6000_memory_move_cost (mode, from, 0)
17237 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17238
c4ad648e
AM		 17239 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17240 shift. */
34bb030a
DE		 17241 else if (from == CR_REGS)
17242 return 4;
17243
17244 else
c4ad648e 17245 /* A move will cost one instruction per GPR moved. */
34bb030a
DE		 17246 return 2 * HARD_REGNO_NREGS (0, mode);
17247 }
17248
c4ad648e 17249 /* Moving between two similar registers is just one instruction. */
34bb030a
DE		 17250 else if (reg_classes_intersect_p (to, from))
17251 return mode == TFmode ? 4 : 2;
17252
c4ad648e 17253 /* Everything else has to go through GENERAL_REGS. */
34bb030a 17254 else
f676971a 17255 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34bb030a
DE		 17256 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17257}
17258
17259/* A C expressions returning the cost of moving data of MODE from a register to
17260 or from memory. */
17261
17262int
f676971a 17263rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
a2369ed3 17264 int in ATTRIBUTE_UNUSED)
34bb030a
DE		 17265{
17266 if (reg_classes_intersect_p (class, GENERAL_REGS))
17267 return 4 * HARD_REGNO_NREGS (0, mode);
17268 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17269 return 4 * HARD_REGNO_NREGS (32, mode);
17270 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17271 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
17272 else
17273 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17274}
17275
ded9bf77
AH		 17276/* Return an RTX representing where to find the function value of a
17277 function returning MODE. */
17278static rtx
17279rs6000_complex_function_value (enum machine_mode mode)
17280{
17281 unsigned int regno;
17282 rtx r1, r2;
17283 enum machine_mode inner = GET_MODE_INNER (mode);
fb7e4164 17284 unsigned int inner_bytes = GET_MODE_SIZE (inner);
ded9bf77 17285
18f63bfa
AH		 17286 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
17287 regno = FP_ARG_RETURN;
354ed18f
AH		 17288 else
17289 {
18f63bfa 17290 regno = GP_ARG_RETURN;
ded9bf77 17291
18f63bfa
AH		 17292 /* 32-bit is OK since it'll go in r3/r4. */
17293 if (TARGET_32BIT && inner_bytes >= 4)
ded9bf77
AH		 17294 return gen_rtx_REG (mode, regno);
17295 }
17296
18f63bfa
AH		 17297 if (inner_bytes >= 8)
17298 return gen_rtx_REG (mode, regno);
17299
ded9bf77
AH		 17300 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
17301 const0_rtx);
17302 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
fb7e4164 17303 GEN_INT (inner_bytes));
ded9bf77
AH		 17304 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
17305}
17306
a6ebc39a
AH		 17307/* Define how to find the value returned by a function.
17308 VALTYPE is the data type of the value (as a tree).
17309 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17310 otherwise, FUNC is 0.
17311
17312 On the SPE, both FPs and vectors are returned in r3.
17313
17314 On RS/6000 an integer value is in r3 and a floating-point value is in
17315 fp1, unless -msoft-float. */
17316
17317rtx
17318rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
17319{
17320 enum machine_mode mode;
2a8fa26c 17321 unsigned int regno;
a6ebc39a 17322
594a51fe
SS		 17323 /* Special handling for structs in darwin64. */
17324 if (rs6000_darwin64_abi
17325 && TYPE_MODE (valtype) == BLKmode
0b5383eb
DJ		 17326 && TREE_CODE (valtype) == RECORD_TYPE
17327 && int_size_in_bytes (valtype) > 0)
594a51fe
SS		 17328 {
17329 CUMULATIVE_ARGS valcum;
17330 rtx valret;
17331
0b5383eb 17332 valcum.words = 0;
594a51fe
SS		 17333 valcum.fregno = FP_ARG_MIN_REG;
17334 valcum.vregno = ALTIVEC_ARG_MIN_REG;
0b5383eb
DJ		 17335 /* Do a trial code generation as if this were going to be passed as
17336 an argument; if any part goes in memory, we return NULL. */
17337 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
594a51fe
SS		 17338 if (valret)
17339 return valret;
17340 /* Otherwise fall through to standard ABI rules. */
17341 }
17342
0e67400a
FJ		 17343 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
17344 {
17345 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17346 return gen_rtx_PARALLEL (DImode,
17347 gen_rtvec (2,
17348 gen_rtx_EXPR_LIST (VOIDmode,
17349 gen_rtx_REG (SImode, GP_ARG_RETURN),
17350 const0_rtx),
17351 gen_rtx_EXPR_LIST (VOIDmode,
17352 gen_rtx_REG (SImode,
17353 GP_ARG_RETURN + 1),
17354 GEN_INT (4))));
17355 }
17356
a6ebc39a
AH		 17357 if ((INTEGRAL_TYPE_P (valtype)
17358 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
17359 || POINTER_TYPE_P (valtype))
b78d48dd 17360 mode = TARGET_32BIT ? SImode : DImode;
a6ebc39a
AH		 17361 else
17362 mode = TYPE_MODE (valtype);
17363
4ed78545 17364 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
2a8fa26c 17365 regno = FP_ARG_RETURN;
ded9bf77 17366 else if (TREE_CODE (valtype) == COMPLEX_TYPE
42ba5130 17367 && targetm.calls.split_complex_arg)
ded9bf77 17368 return rs6000_complex_function_value (mode);
44688022 17369 else if (TREE_CODE (valtype) == VECTOR_TYPE
d0b2079e 17370 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
23ba09f0 17371 && ALTIVEC_VECTOR_MODE (mode))
a6ebc39a 17372 regno = ALTIVEC_ARG_RETURN;
18f63bfa
AH		 17373 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17374 && (mode == DFmode || mode == DCmode))
17375 return spe_build_register_parallel (mode, GP_ARG_RETURN);
a6ebc39a
AH		 17376 else
17377 regno = GP_ARG_RETURN;
17378
17379 return gen_rtx_REG (mode, regno);
17380}
17381
ded9bf77
AH		 17382/* Define how to find the value returned by a library function
17383 assuming the value has mode MODE. */
17384rtx
17385rs6000_libcall_value (enum machine_mode mode)
17386{
17387 unsigned int regno;
17388
2e6c9641
FJ		 17389 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
17390 {
17391 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17392 return gen_rtx_PARALLEL (DImode,
17393 gen_rtvec (2,
17394 gen_rtx_EXPR_LIST (VOIDmode,
17395 gen_rtx_REG (SImode, GP_ARG_RETURN),
17396 const0_rtx),
17397 gen_rtx_EXPR_LIST (VOIDmode,
17398 gen_rtx_REG (SImode,
17399 GP_ARG_RETURN + 1),
17400 GEN_INT (4))));
17401 }
17402
ded9bf77
AH		 17403 if (GET_MODE_CLASS (mode) == MODE_FLOAT
17404 && TARGET_HARD_FLOAT && TARGET_FPRS)
17405 regno = FP_ARG_RETURN;
44688022
AM		 17406 else if (ALTIVEC_VECTOR_MODE (mode)
17407 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
ded9bf77 17408 regno = ALTIVEC_ARG_RETURN;
42ba5130 17409 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
ded9bf77 17410 return rs6000_complex_function_value (mode);
18f63bfa
AH		 17411 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17412 && (mode == DFmode || mode == DCmode))
17413 return spe_build_register_parallel (mode, GP_ARG_RETURN);
ded9bf77
AH		 17414 else
17415 regno = GP_ARG_RETURN;
17416
17417 return gen_rtx_REG (mode, regno);
17418}
17419
d1d0c603
JJ		 17420/* Define the offset between two registers, FROM to be eliminated and its
17421 replacement TO, at the start of a routine. */
17422HOST_WIDE_INT
17423rs6000_initial_elimination_offset (int from, int to)
17424{
17425 rs6000_stack_t *info = rs6000_stack_info ();
17426 HOST_WIDE_INT offset;
17427
17428 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17429 offset = info->push_p ? 0 : -info->total_size;
17430 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
17431 offset = info->total_size;
17432 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17433 offset = info->push_p ? info->total_size : 0;
17434 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
17435 offset = 0;
17436 else
17437 abort ();
17438
17439 return offset;
17440}
17441
62e1dfcf
NC		 17442/* Return true if TYPE is of type __ev64_opaque__. */
17443
c8e4f0e9 17444static bool
a2369ed3 17445is_ev64_opaque_type (tree type)
62e1dfcf 17446{
c8e4f0e9 17447 return (TARGET_SPE
2abe3e28
AH		 17448 && (type == opaque_V2SI_type_node
17449 || type == opaque_V2SF_type_node
36252949 17450 || type == opaque_p_V2SI_type_node));
62e1dfcf
NC		 17451}
17452
96714395 17453static rtx
a2369ed3 17454rs6000_dwarf_register_span (rtx reg)
96714395
AH		 17455{
17456 unsigned regno;
17457
4d4cbc0e
AH		 17458 if (TARGET_SPE
17459 && (SPE_VECTOR_MODE (GET_MODE (reg))
17460 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
17461 ;
17462 else
96714395
AH		 17463 return NULL_RTX;
17464
17465 regno = REGNO (reg);
17466
17467 /* The duality of the SPE register size wreaks all kinds of havoc.
17468 This is a way of distinguishing r0 in 32-bits from r0 in
17469 64-bits. */
17470 return
17471 gen_rtx_PARALLEL (VOIDmode,
3bd104d1
AH		 17472 BYTES_BIG_ENDIAN
17473 ? gen_rtvec (2,
17474 gen_rtx_REG (SImode, regno + 1200),
17475 gen_rtx_REG (SImode, regno))
17476 : gen_rtvec (2,
17477 gen_rtx_REG (SImode, regno),
17478 gen_rtx_REG (SImode, regno + 1200)));
96714395
AH		 17479}
17480
93c9d1ba
AM		 17481/* Map internal gcc register numbers to DWARF2 register numbers. */
17482
17483unsigned int
17484rs6000_dbx_register_number (unsigned int regno)
17485{
17486 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
17487 return regno;
17488 if (regno == MQ_REGNO)
17489 return 100;
17490 if (regno == LINK_REGISTER_REGNUM)
17491 return 108;
17492 if (regno == COUNT_REGISTER_REGNUM)
17493 return 109;
17494 if (CR_REGNO_P (regno))
17495 return regno - CR0_REGNO + 86;
17496 if (regno == XER_REGNO)
17497 return 101;
17498 if (ALTIVEC_REGNO_P (regno))
17499 return regno - FIRST_ALTIVEC_REGNO + 1124;
17500 if (regno == VRSAVE_REGNO)
17501 return 356;
17502 if (regno == VSCR_REGNO)
17503 return 67;
17504 if (regno == SPE_ACC_REGNO)
17505 return 99;
17506 if (regno == SPEFSCR_REGNO)
17507 return 612;
17508 /* SPE high reg number. We get these values of regno from
17509 rs6000_dwarf_register_span. */
17510 if (regno >= 1200 && regno < 1232)
17511 return regno;
17512
17513 abort ();
17514}
17515
93f90be6 17516/* target hook eh_return_filter_mode */
f676971a 17517static enum machine_mode
93f90be6
FJ		 17518rs6000_eh_return_filter_mode (void)
17519{
17520 return TARGET_32BIT ? SImode : word_mode;
17521}
17522
f676971a
EC		 17523/* Target hook for vector_mode_supported_p. */
17524static bool
17525rs6000_vector_mode_supported_p (enum machine_mode mode)
17526{
17527
17528 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
17529 return true;
17530
17531 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
17532 return true;
17533
17534 else
17535 return false;
17536}
17537
4d3e6fae
FJ		 17538/* Target hook for invalid_arg_for_unprototyped_fn. */
17539static const char *
17540invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
17541{
17542 return (!rs6000_darwin64_abi
17543 && typelist == 0
17544 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
17545 && (funcdecl == NULL_TREE
17546 || (TREE_CODE (funcdecl) == FUNCTION_DECL
17547 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
17548 ? N_("AltiVec argument passed to unprototyped function")
17549 : NULL;
17550}
17551
17211ab5 17552#include "gt-rs6000.h"
Mirror of https://gcc.gnu.org/git/gcc.git