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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
95385cbb | 3 | 2000, 2001, 2002 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
9878760c RK |
31 | #include "insn-attr.h" |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
9878760c | 34 | #include "obstack.h" |
9b30bae2 | 35 | #include "tree.h" |
dfafc897 | 36 | #include "expr.h" |
2fc1c679 | 37 | #include "optabs.h" |
2a430ec1 | 38 | #include "except.h" |
a7df97e6 | 39 | #include "function.h" |
296b8152 | 40 | #include "output.h" |
d5fa86ba | 41 | #include "basic-block.h" |
d0101753 | 42 | #include "integrate.h" |
296b8152 | 43 | #include "toplev.h" |
c8023011 | 44 | #include "ggc.h" |
9ebbca7d GK |
45 | #include "hashtab.h" |
46 | #include "tm_p.h" | |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
3ac88239 | 49 | #include "langhooks.h" |
24ea750e | 50 | #include "reload.h" |
9b30bae2 | 51 | |
7509c759 MM |
52 | #ifndef TARGET_NO_PROTOTYPE |
53 | #define TARGET_NO_PROTOTYPE 0 | |
54 | #endif | |
55 | ||
9878760c RK |
56 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
57 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
58 | ||
5248c961 RK |
59 | /* Target cpu type */ |
60 | ||
61 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
62 | struct rs6000_cpu_select rs6000_select[3] = |
63 | { | |
815cdc52 MM |
64 | /* switch name, tune arch */ |
65 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
66 | { (const char *)0, "-mcpu=", 1, 1 }, | |
67 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 68 | }; |
5248c961 | 69 | |
6fa3f289 ZW |
70 | /* Size of long double */ |
71 | const char *rs6000_long_double_size_string; | |
72 | int rs6000_long_double_type_size; | |
73 | ||
74 | /* Whether -mabi=altivec has appeared */ | |
75 | int rs6000_altivec_abi; | |
76 | ||
c764f757 RK |
77 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
78 | static int common_mode_defined; | |
c81bebd7 | 79 | |
9878760c RK |
80 | /* Save information from a "cmpxx" operation until the branch or scc is |
81 | emitted. */ | |
9878760c RK |
82 | rtx rs6000_compare_op0, rs6000_compare_op1; |
83 | int rs6000_compare_fp_p; | |
874a0744 | 84 | |
874a0744 MM |
85 | /* Label number of label created for -mrelocatable, to call to so we can |
86 | get the address of the GOT section */ | |
87 | int rs6000_pic_labelno; | |
c81bebd7 | 88 | |
b91da81f | 89 | #ifdef USING_ELFOS_H |
c81bebd7 | 90 | /* Which abi to adhere to */ |
815cdc52 | 91 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
92 | |
93 | /* Semantics of the small data area */ | |
94 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
95 | ||
96 | /* Which small data model to use */ | |
815cdc52 | 97 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
98 | |
99 | /* Counter for labels which are to be placed in .fixup. */ | |
100 | int fixuplabelno = 0; | |
874a0744 | 101 | #endif |
4697a36c | 102 | |
b6c9286a MM |
103 | /* ABI enumeration available for subtarget to use. */ |
104 | enum rs6000_abi rs6000_current_abi; | |
105 | ||
0ac081f6 AH |
106 | /* ABI string from -mabi= option. */ |
107 | const char *rs6000_abi_string; | |
108 | ||
38c1f2d7 | 109 | /* Debug flags */ |
815cdc52 | 110 | const char *rs6000_debug_name; |
38c1f2d7 MM |
111 | int rs6000_debug_stack; /* debug stack applications */ |
112 | int rs6000_debug_arg; /* debug argument handling */ | |
113 | ||
114 | /* Flag to say the TOC is initialized */ | |
115 | int toc_initialized; | |
9ebbca7d | 116 | char toc_label_name[10]; |
38c1f2d7 | 117 | |
9ebbca7d GK |
118 | /* Alias set for saves and restores from the rs6000 stack. */ |
119 | static int rs6000_sr_alias_set; | |
c8023011 | 120 | |
9ebbca7d GK |
121 | static void rs6000_add_gc_roots PARAMS ((void)); |
122 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
123 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
124 | static void validate_condition_mode |
125 | PARAMS ((enum rtx_code, enum machine_mode)); | |
126 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 127 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
128 | static void rs6000_emit_stack_tie PARAMS ((void)); |
129 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
130 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
131 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
132 | static unsigned toc_hash_function PARAMS ((const void *)); | |
133 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 134 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
135 | static void toc_hash_mark_table PARAMS ((void *)); |
136 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
6fee9e99 NC |
137 | static void rs6000_free_machine_status PARAMS ((struct function *)); |
138 | static void rs6000_init_machine_status PARAMS ((struct function *)); | |
301d03af | 139 | static bool rs6000_assemble_integer PARAMS ((rtx, unsigned int, int)); |
71f123ca | 140 | static int rs6000_ra_ever_killed PARAMS ((void)); |
91d231cb JM |
141 | static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *)); |
142 | const struct attribute_spec rs6000_attribute_table[]; | |
08c148a8 NB |
143 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
144 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
2bfcf297 DB |
145 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
146 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
7c262518 RH |
147 | #if TARGET_ELF |
148 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
149 | int)); | |
d9f6800d RH |
150 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
151 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
7c262518 RH |
152 | #endif |
153 | #ifdef OBJECT_FORMAT_COFF | |
715bdd29 | 154 | static void xcoff_asm_named_section PARAMS ((const char *, unsigned int)); |
7c262518 | 155 | #endif |
c237e94a ZW |
156 | static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
157 | static int rs6000_adjust_priority PARAMS ((rtx, int)); | |
158 | static int rs6000_issue_rate PARAMS ((void)); | |
159 | ||
6fa3f289 | 160 | static void rs6000_init_builtins PARAMS ((void)); |
0ac081f6 AH |
161 | static void altivec_init_builtins PARAMS ((void)); |
162 | static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int)); | |
00b960c7 | 163 | static rtx altivec_expand_builtin PARAMS ((tree, rtx)); |
2212663f | 164 | static rtx altivec_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx)); |
0ac081f6 | 165 | static rtx altivec_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); |
100c4561 | 166 | static rtx altivec_expand_abs_builtin PARAMS ((enum insn_code, tree, rtx)); |
ae4b4a02 | 167 | static rtx altivec_expand_predicate_builtin PARAMS ((enum insn_code, const char *, tree, rtx)); |
2212663f | 168 | static rtx altivec_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx)); |
6525c0e7 | 169 | static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree)); |
0ac081f6 | 170 | static void rs6000_parse_abi_options PARAMS ((void)); |
00b960c7 AH |
171 | static int first_altivec_reg_to_save PARAMS ((void)); |
172 | static unsigned int compute_vrsave_mask PARAMS ((void)); | |
173 | static void is_altivec_return_reg PARAMS ((rtx, void *)); | |
174 | int vrsave_operation PARAMS ((rtx, enum machine_mode)); | |
9aa86737 AH |
175 | static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *, int)); |
176 | static void altivec_frame_fixup PARAMS ((rtx, rtx, HOST_WIDE_INT)); | |
69ef87e2 | 177 | static int easy_vector_constant PARAMS ((rtx)); |
c81bebd7 MM |
178 | \f |
179 | /* Default register names. */ | |
180 | char rs6000_reg_names[][8] = | |
181 | { | |
802a0058 MM |
182 | "0", "1", "2", "3", "4", "5", "6", "7", |
183 | "8", "9", "10", "11", "12", "13", "14", "15", | |
184 | "16", "17", "18", "19", "20", "21", "22", "23", | |
185 | "24", "25", "26", "27", "28", "29", "30", "31", | |
186 | "0", "1", "2", "3", "4", "5", "6", "7", | |
187 | "8", "9", "10", "11", "12", "13", "14", "15", | |
188 | "16", "17", "18", "19", "20", "21", "22", "23", | |
189 | "24", "25", "26", "27", "28", "29", "30", "31", | |
190 | "mq", "lr", "ctr","ap", | |
191 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
192 | "xer", |
193 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
194 | "0", "1", "2", "3", "4", "5", "6", "7", |
195 | "8", "9", "10", "11", "12", "13", "14", "15", | |
196 | "16", "17", "18", "19", "20", "21", "22", "23", | |
197 | "24", "25", "26", "27", "28", "29", "30", "31", | |
0ac081f6 | 198 | "vrsave" |
c81bebd7 MM |
199 | }; |
200 | ||
201 | #ifdef TARGET_REGNAMES | |
8b60264b | 202 | static const char alt_reg_names[][8] = |
c81bebd7 | 203 | { |
802a0058 MM |
204 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
205 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
206 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
207 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
208 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
209 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
210 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
211 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
212 | "mq", "lr", "ctr", "ap", | |
213 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 AH |
214 | "xer", |
215 | /* AltiVec registers. */ | |
216 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", | |
217 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", | |
218 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
219 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
76a773f3 | 220 | "vrsave" |
c81bebd7 MM |
221 | }; |
222 | #endif | |
9878760c | 223 | \f |
daf11973 MM |
224 | #ifndef MASK_STRICT_ALIGN |
225 | #define MASK_STRICT_ALIGN 0 | |
226 | #endif | |
672a6f42 NB |
227 | \f |
228 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
229 | #undef TARGET_ATTRIBUTE_TABLE |
230 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
daf11973 | 231 | |
301d03af RS |
232 | #undef TARGET_ASM_ALIGNED_DI_OP |
233 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
234 | ||
235 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
236 | for non-ELF systems. */ | |
237 | #ifndef OBJECT_FORMAT_ELF | |
238 | #ifdef OBJECT_FORMAT_COFF | |
ae6c1efd | 239 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
240 | 64-bit targets. */ |
241 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
242 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
243 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
244 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
245 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
246 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
247 | #else | |
248 | /* For Darwin. */ | |
249 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
250 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
251 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
252 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
253 | #endif | |
254 | #endif | |
255 | ||
256 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
257 | in 64-bit code. */ | |
258 | #undef TARGET_ASM_INTEGER | |
259 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
260 | ||
08c148a8 NB |
261 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
262 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
263 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
264 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
265 | ||
7c262518 RH |
266 | #if TARGET_ELF |
267 | #undef TARGET_SECTION_TYPE_FLAGS | |
268 | #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags | |
269 | #endif | |
270 | ||
c237e94a ZW |
271 | #undef TARGET_SCHED_ISSUE_RATE |
272 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
273 | #undef TARGET_SCHED_ADJUST_COST | |
274 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
275 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
276 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
277 | ||
0ac081f6 AH |
278 | #undef TARGET_INIT_BUILTINS |
279 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
280 | ||
281 | #undef TARGET_EXPAND_BUILTIN | |
282 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
283 | ||
00b960c7 AH |
284 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ |
285 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
286 | ||
f6897b10 | 287 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 288 | \f |
5248c961 RK |
289 | /* Override command line options. Mostly we process the processor |
290 | type and sometimes adjust other TARGET_ options. */ | |
291 | ||
292 | void | |
8e3f41e7 | 293 | rs6000_override_options (default_cpu) |
d330fd93 | 294 | const char *default_cpu; |
5248c961 | 295 | { |
c4d38ccb | 296 | size_t i, j; |
8e3f41e7 | 297 | struct rs6000_cpu_select *ptr; |
5248c961 | 298 | |
85638c0d RK |
299 | /* Simplify the entries below by making a mask for any POWER |
300 | variant and any PowerPC variant. */ | |
301 | ||
938937d8 | 302 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
303 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
304 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
305 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 306 | |
5248c961 RK |
307 | static struct ptt |
308 | { | |
8b60264b KG |
309 | const char *const name; /* Canonical processor name. */ |
310 | const enum processor_type processor; /* Processor type enum value. */ | |
311 | const int target_enable; /* Target flags to enable. */ | |
312 | const int target_disable; /* Target flags to disable. */ | |
313 | } const processor_target_table[] | |
cf27b467 MM |
314 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
315 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 316 | {"power", PROCESSOR_POWER, |
938937d8 | 317 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 318 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
319 | {"power2", PROCESSOR_POWER, |
320 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
321 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
322 | {"power3", PROCESSOR_PPC630, |
323 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
324 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
325 | {"powerpc", PROCESSOR_POWERPC, |
326 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 327 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
328 | {"powerpc64", PROCESSOR_POWERPC64, |
329 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
330 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 331 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 332 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
333 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
334 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 335 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
336 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
337 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 338 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
339 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
340 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 341 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
342 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
343 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 344 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 345 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
346 | {"rs64a", PROCESSOR_RS64A, |
347 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
348 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
349 | {"401", PROCESSOR_PPC403, |
350 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
351 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 352 | {"403", PROCESSOR_PPC403, |
daf11973 | 353 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 354 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
d7a5e253 DE |
355 | {"405", PROCESSOR_PPC405, |
356 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
357 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
358 | {"505", PROCESSOR_MPCCORE, |
359 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
360 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 361 | {"601", PROCESSOR_PPC601, |
938937d8 | 362 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 363 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 364 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
365 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
366 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 367 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
368 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
369 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
370 | {"603e", PROCESSOR_PPC603, |
371 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
372 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 373 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
374 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
375 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 376 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
377 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
378 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 379 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
380 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
381 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 382 | {"620", PROCESSOR_PPC620, |
68c49ffa | 383 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 384 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
385 | {"630", PROCESSOR_PPC630, |
386 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
387 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
388 | {"740", PROCESSOR_PPC750, |
389 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
390 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
391 | {"750", PROCESSOR_PPC750, | |
392 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
393 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a4f6c312 SS |
394 | {"7400", PROCESSOR_PPC7400, |
395 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
396 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
397 | {"7450", PROCESSOR_PPC7450, | |
398 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
399 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
400 | {"801", PROCESSOR_MPCCORE, |
401 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
402 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
403 | {"821", PROCESSOR_MPCCORE, |
404 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
405 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
406 | {"823", PROCESSOR_MPCCORE, |
407 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
408 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
409 | {"860", PROCESSOR_MPCCORE, |
410 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
411 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 412 | |
ca7558fc | 413 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 414 | |
a4f6c312 SS |
415 | /* Save current -mmultiple/-mno-multiple status. */ |
416 | int multiple = TARGET_MULTIPLE; | |
417 | /* Save current -mstring/-mno-string status. */ | |
418 | int string = TARGET_STRING; | |
8a61d227 | 419 | |
a4f6c312 | 420 | /* Identify the processor type. */ |
8e3f41e7 | 421 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 422 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 423 | |
b6a1cbae | 424 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 425 | { |
8e3f41e7 MM |
426 | ptr = &rs6000_select[i]; |
427 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 428 | { |
8e3f41e7 MM |
429 | for (j = 0; j < ptt_size; j++) |
430 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
431 | { | |
432 | if (ptr->set_tune_p) | |
433 | rs6000_cpu = processor_target_table[j].processor; | |
434 | ||
435 | if (ptr->set_arch_p) | |
436 | { | |
437 | target_flags |= processor_target_table[j].target_enable; | |
438 | target_flags &= ~processor_target_table[j].target_disable; | |
439 | } | |
440 | break; | |
441 | } | |
442 | ||
4406229e | 443 | if (j == ptt_size) |
8e3f41e7 | 444 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
445 | } |
446 | } | |
8a61d227 | 447 | |
a4f6c312 SS |
448 | /* If we are optimizing big endian systems for space, use the store |
449 | multiple instructions. */ | |
ef792183 MM |
450 | if (BYTES_BIG_ENDIAN && optimize_size) |
451 | target_flags |= MASK_MULTIPLE; | |
452 | ||
8a61d227 MM |
453 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
454 | override with the processor default */ | |
455 | if (TARGET_MULTIPLE_SET) | |
456 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 457 | |
a4f6c312 SS |
458 | /* If -mstring or -mno-string was explicitly used, don't override |
459 | with the processor default. */ | |
938937d8 | 460 | if (TARGET_STRING_SET) |
1f5515bf | 461 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 462 | |
a4f6c312 SS |
463 | /* Don't allow -mmultiple or -mstring on little endian systems |
464 | unless the cpu is a 750, because the hardware doesn't support the | |
465 | instructions used in little endian mode, and causes an alignment | |
466 | trap. The 750 does not cause an alignment trap (except when the | |
467 | target is unaligned). */ | |
bef84347 | 468 | |
bfc79d3b | 469 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
470 | { |
471 | if (TARGET_MULTIPLE) | |
472 | { | |
473 | target_flags &= ~MASK_MULTIPLE; | |
474 | if (TARGET_MULTIPLE_SET) | |
475 | warning ("-mmultiple is not supported on little endian systems"); | |
476 | } | |
477 | ||
478 | if (TARGET_STRING) | |
479 | { | |
480 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
481 | if (TARGET_STRING_SET) |
482 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
483 | } |
484 | } | |
3933e0e1 | 485 | |
2bfcf297 | 486 | if (flag_pic && DEFAULT_ABI == ABI_AIX) |
a260abc9 | 487 | { |
2bfcf297 | 488 | warning ("-f%s ignored (all code is position independent)", |
a260abc9 DE |
489 | (flag_pic > 1) ? "PIC" : "pic"); |
490 | flag_pic = 0; | |
491 | } | |
492 | ||
2bfcf297 | 493 | #ifdef XCOFF_DEBUGGING_INFO |
9861b0c9 | 494 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
2bfcf297 | 495 | && DEFAULT_ABI == ABI_AIX) |
9861b0c9 DE |
496 | { |
497 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
498 | flag_function_sections = 0; | |
499 | } | |
500 | ||
501 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
502 | { | |
503 | warning ("-fdata-sections not supported on AIX"); | |
504 | flag_data_sections = 0; | |
505 | } | |
2bfcf297 | 506 | #endif |
9861b0c9 | 507 | |
38c1f2d7 MM |
508 | /* Set debug flags */ |
509 | if (rs6000_debug_name) | |
510 | { | |
bfc79d3b | 511 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 512 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 513 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 514 | rs6000_debug_stack = 1; |
bfc79d3b | 515 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
516 | rs6000_debug_arg = 1; |
517 | else | |
c725bd79 | 518 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
519 | } |
520 | ||
6fa3f289 ZW |
521 | /* Set size of long double */ |
522 | rs6000_long_double_type_size = 64; | |
523 | if (rs6000_long_double_size_string) | |
524 | { | |
525 | char *tail; | |
526 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
527 | if (*tail != '\0' || (size != 64 && size != 128)) | |
528 | error ("Unknown switch -mlong-double-%s", | |
529 | rs6000_long_double_size_string); | |
530 | else | |
531 | rs6000_long_double_type_size = size; | |
532 | } | |
533 | ||
0ac081f6 AH |
534 | /* Handle -mabi= options. */ |
535 | rs6000_parse_abi_options (); | |
536 | ||
c81bebd7 | 537 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
538 | /* If the user desires alternate register names, copy in the |
539 | alternate names now. */ | |
c81bebd7 | 540 | if (TARGET_REGNAMES) |
4e135bdd | 541 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
542 | #endif |
543 | ||
3933e0e1 MM |
544 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
545 | SUBTARGET_OVERRIDE_OPTIONS; | |
546 | #endif | |
10baca6b AH |
547 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS |
548 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
549 | #endif | |
c8023011 | 550 | |
6fa3f289 ZW |
551 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
552 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
553 | used, don't override with the ABI default. */ | |
554 | if (!(target_flags & MASK_AIX_STRUCT_RET_SET)) | |
555 | { | |
556 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
557 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
558 | else | |
559 | target_flags |= MASK_AIX_STRUCT_RET; | |
560 | } | |
561 | ||
c8023011 MM |
562 | /* Register global variables with the garbage collector. */ |
563 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
564 | |
565 | /* Allocate an alias set for register saves & restores from stack. */ | |
566 | rs6000_sr_alias_set = new_alias_set (); | |
567 | ||
568 | if (TARGET_TOC) | |
569 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca | 570 | |
301d03af RS |
571 | /* We can only guarantee the availability of DI pseudo-ops when |
572 | assembling for 64-bit targets. */ | |
ae6c1efd | 573 | if (!TARGET_64BIT) |
301d03af RS |
574 | { |
575 | targetm.asm_out.aligned_op.di = NULL; | |
576 | targetm.asm_out.unaligned_op.di = NULL; | |
577 | } | |
578 | ||
71f123ca FS |
579 | /* Arrange to save and restore machine status around nested functions. */ |
580 | init_machine_status = rs6000_init_machine_status; | |
71f123ca | 581 | free_machine_status = rs6000_free_machine_status; |
5248c961 | 582 | } |
5accd822 | 583 | |
0ac081f6 | 584 | /* Handle -mabi= options. */ |
00b960c7 AH |
585 | static void |
586 | rs6000_parse_abi_options () | |
0ac081f6 AH |
587 | { |
588 | if (rs6000_abi_string == 0) | |
589 | return; | |
590 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
6fa3f289 | 591 | rs6000_altivec_abi = 1; |
76a773f3 AH |
592 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
593 | rs6000_altivec_abi = 0; | |
0ac081f6 | 594 | else |
c725bd79 | 595 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
596 | } |
597 | ||
5accd822 DE |
598 | void |
599 | optimization_options (level, size) | |
e2c953b6 | 600 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
601 | int size ATTRIBUTE_UNUSED; |
602 | { | |
5accd822 | 603 | } |
3cfa4909 MM |
604 | \f |
605 | /* Do anything needed at the start of the asm file. */ | |
606 | ||
607 | void | |
608 | rs6000_file_start (file, default_cpu) | |
609 | FILE *file; | |
d330fd93 | 610 | const char *default_cpu; |
3cfa4909 | 611 | { |
c4d38ccb | 612 | size_t i; |
3cfa4909 | 613 | char buffer[80]; |
d330fd93 | 614 | const char *start = buffer; |
3cfa4909 MM |
615 | struct rs6000_cpu_select *ptr; |
616 | ||
617 | if (flag_verbose_asm) | |
618 | { | |
619 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
620 | rs6000_select[0].string = default_cpu; | |
621 | ||
b6a1cbae | 622 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
623 | { |
624 | ptr = &rs6000_select[i]; | |
625 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
626 | { | |
627 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
628 | start = ""; | |
629 | } | |
630 | } | |
631 | ||
b91da81f | 632 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
633 | switch (rs6000_sdata) |
634 | { | |
635 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
636 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
637 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
638 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
639 | } | |
640 | ||
641 | if (rs6000_sdata && g_switch_value) | |
642 | { | |
643 | fprintf (file, "%s -G %d", start, g_switch_value); | |
644 | start = ""; | |
645 | } | |
646 | #endif | |
647 | ||
648 | if (*start == '\0') | |
949ea356 | 649 | putc ('\n', file); |
3cfa4909 MM |
650 | } |
651 | } | |
652 | ||
24d304eb RK |
653 | \f |
654 | /* Create a CONST_DOUBLE from a string. */ | |
655 | ||
656 | struct rtx_def * | |
657 | rs6000_float_const (string, mode) | |
d330fd93 | 658 | const char *string; |
24d304eb RK |
659 | enum machine_mode mode; |
660 | { | |
ca5adc63 GK |
661 | REAL_VALUE_TYPE value; |
662 | value = REAL_VALUE_ATOF (string, mode); | |
24d304eb RK |
663 | return immed_real_const_1 (value, mode); |
664 | } | |
5248c961 | 665 | \f |
9878760c RK |
666 | /* Return non-zero if this function is known to have a null epilogue. */ |
667 | ||
668 | int | |
669 | direct_return () | |
670 | { | |
4697a36c MM |
671 | if (reload_completed) |
672 | { | |
673 | rs6000_stack_t *info = rs6000_stack_info (); | |
674 | ||
675 | if (info->first_gp_reg_save == 32 | |
676 | && info->first_fp_reg_save == 64 | |
00b960c7 | 677 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
678 | && ! info->lr_save_p |
679 | && ! info->cr_save_p | |
00b960c7 | 680 | && info->vrsave_mask == 0 |
c81fc13e | 681 | && ! info->push_p) |
4697a36c MM |
682 | return 1; |
683 | } | |
684 | ||
685 | return 0; | |
9878760c RK |
686 | } |
687 | ||
688 | /* Returns 1 always. */ | |
689 | ||
690 | int | |
691 | any_operand (op, mode) | |
592696dd | 692 | rtx op ATTRIBUTE_UNUSED; |
296b8152 | 693 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
694 | { |
695 | return 1; | |
696 | } | |
697 | ||
a4f6c312 | 698 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 699 | int |
a4f6c312 | 700 | count_register_operand (op, mode) |
592696dd | 701 | rtx op; |
296b8152 | 702 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
703 | { |
704 | if (GET_CODE (op) != REG) | |
705 | return 0; | |
706 | ||
707 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
708 | return 1; | |
709 | ||
710 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
711 | return 1; | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
0ec4e2a8 AH |
716 | /* Returns 1 if op is an altivec register. */ |
717 | int | |
718 | altivec_register_operand (op, mode) | |
719 | rtx op; | |
720 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
721 | { | |
722 | ||
723 | return (register_operand (op, mode) | |
724 | && (GET_CODE (op) != REG | |
725 | || REGNO (op) > FIRST_PSEUDO_REGISTER | |
726 | || ALTIVEC_REGNO_P (REGNO (op)))); | |
727 | } | |
728 | ||
38c1f2d7 | 729 | int |
a4f6c312 | 730 | xer_operand (op, mode) |
592696dd | 731 | rtx op; |
296b8152 | 732 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
733 | { |
734 | if (GET_CODE (op) != REG) | |
735 | return 0; | |
736 | ||
9ebbca7d | 737 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
738 | return 1; |
739 | ||
802a0058 MM |
740 | return 0; |
741 | } | |
742 | ||
c859cda6 | 743 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 744 | by such constants completes more quickly. */ |
c859cda6 DJ |
745 | |
746 | int | |
747 | s8bit_cint_operand (op, mode) | |
748 | rtx op; | |
749 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
750 | { | |
751 | return ( GET_CODE (op) == CONST_INT | |
752 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); | |
753 | } | |
754 | ||
9878760c RK |
755 | /* Return 1 if OP is a constant that can fit in a D field. */ |
756 | ||
757 | int | |
758 | short_cint_operand (op, mode) | |
592696dd | 759 | rtx op; |
296b8152 | 760 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 761 | { |
5f59ecb7 DE |
762 | return (GET_CODE (op) == CONST_INT |
763 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
764 | } |
765 | ||
5519a4f9 | 766 | /* Similar for an unsigned D field. */ |
9878760c RK |
767 | |
768 | int | |
769 | u_short_cint_operand (op, mode) | |
592696dd | 770 | rtx op; |
296b8152 | 771 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 772 | { |
19684119 | 773 | return (GET_CODE (op) == CONST_INT |
c1f11548 | 774 | && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K')); |
9878760c RK |
775 | } |
776 | ||
dcfedcd0 RK |
777 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
778 | ||
779 | int | |
780 | non_short_cint_operand (op, mode) | |
592696dd | 781 | rtx op; |
296b8152 | 782 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
783 | { |
784 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 785 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
786 | } |
787 | ||
2bfcf297 DB |
788 | /* Returns 1 if OP is a CONST_INT that is a positive value |
789 | and an exact power of 2. */ | |
790 | ||
791 | int | |
792 | exact_log2_cint_operand (op, mode) | |
592696dd | 793 | rtx op; |
2bfcf297 DB |
794 | enum machine_mode mode ATTRIBUTE_UNUSED; |
795 | { | |
796 | return (GET_CODE (op) == CONST_INT | |
797 | && INTVAL (op) > 0 | |
798 | && exact_log2 (INTVAL (op)) >= 0); | |
799 | } | |
800 | ||
9878760c RK |
801 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
802 | ctr, or lr). */ | |
803 | ||
804 | int | |
cd2b37d9 | 805 | gpc_reg_operand (op, mode) |
592696dd | 806 | rtx op; |
9878760c RK |
807 | enum machine_mode mode; |
808 | { | |
809 | return (register_operand (op, mode) | |
802a0058 | 810 | && (GET_CODE (op) != REG |
9ebbca7d GK |
811 | || (REGNO (op) >= ARG_POINTER_REGNUM |
812 | && !XER_REGNO_P (REGNO (op))) | |
813 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
814 | } |
815 | ||
816 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
817 | CR field. */ | |
818 | ||
819 | int | |
820 | cc_reg_operand (op, mode) | |
592696dd | 821 | rtx op; |
9878760c RK |
822 | enum machine_mode mode; |
823 | { | |
824 | return (register_operand (op, mode) | |
825 | && (GET_CODE (op) != REG | |
826 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
827 | || CR_REGNO_P (REGNO (op)))); | |
828 | } | |
829 | ||
815cdc52 MM |
830 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
831 | CR field that isn't CR0. */ | |
832 | ||
833 | int | |
834 | cc_reg_not_cr0_operand (op, mode) | |
592696dd | 835 | rtx op; |
815cdc52 MM |
836 | enum machine_mode mode; |
837 | { | |
838 | return (register_operand (op, mode) | |
839 | && (GET_CODE (op) != REG | |
840 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
841 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
842 | } | |
843 | ||
a4f6c312 SS |
844 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
845 | a non-special register. If a register, it must be in the proper | |
846 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
847 | |
848 | int | |
849 | reg_or_short_operand (op, mode) | |
592696dd | 850 | rtx op; |
9878760c RK |
851 | enum machine_mode mode; |
852 | { | |
f5a28898 | 853 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
854 | } |
855 | ||
a4f6c312 SS |
856 | /* Similar, except check if the negation of the constant would be |
857 | valid for a D-field. */ | |
9878760c RK |
858 | |
859 | int | |
860 | reg_or_neg_short_operand (op, mode) | |
592696dd | 861 | rtx op; |
9878760c RK |
862 | enum machine_mode mode; |
863 | { | |
864 | if (GET_CODE (op) == CONST_INT) | |
865 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
866 | ||
cd2b37d9 | 867 | return gpc_reg_operand (op, mode); |
9878760c RK |
868 | } |
869 | ||
768070a0 TR |
870 | /* Returns 1 if OP is either a constant integer valid for a DS-field or |
871 | a non-special register. If a register, it must be in the proper | |
872 | mode unless MODE is VOIDmode. */ | |
873 | ||
874 | int | |
875 | reg_or_aligned_short_operand (op, mode) | |
876 | rtx op; | |
877 | enum machine_mode mode; | |
878 | { | |
879 | if (gpc_reg_operand (op, mode)) | |
880 | return 1; | |
881 | else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3)) | |
882 | return 1; | |
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
887 | ||
a4f6c312 SS |
888 | /* Return 1 if the operand is either a register or an integer whose |
889 | high-order 16 bits are zero. */ | |
9878760c RK |
890 | |
891 | int | |
892 | reg_or_u_short_operand (op, mode) | |
592696dd | 893 | rtx op; |
9878760c RK |
894 | enum machine_mode mode; |
895 | { | |
e675f625 | 896 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
897 | } |
898 | ||
899 | /* Return 1 is the operand is either a non-special register or ANY | |
900 | constant integer. */ | |
901 | ||
902 | int | |
903 | reg_or_cint_operand (op, mode) | |
592696dd | 904 | rtx op; |
9878760c RK |
905 | enum machine_mode mode; |
906 | { | |
a4f6c312 | 907 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
908 | } |
909 | ||
910 | /* Return 1 is the operand is either a non-special register or ANY | |
911 | 32-bit signed constant integer. */ | |
912 | ||
913 | int | |
914 | reg_or_arith_cint_operand (op, mode) | |
592696dd | 915 | rtx op; |
f6bf7de2 DE |
916 | enum machine_mode mode; |
917 | { | |
a4f6c312 SS |
918 | return (gpc_reg_operand (op, mode) |
919 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 920 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
921 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
922 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 923 | #endif |
a4f6c312 | 924 | )); |
9878760c RK |
925 | } |
926 | ||
2bfcf297 DB |
927 | /* Return 1 is the operand is either a non-special register or a 32-bit |
928 | signed constant integer valid for 64-bit addition. */ | |
929 | ||
930 | int | |
931 | reg_or_add_cint64_operand (op, mode) | |
592696dd | 932 | rtx op; |
2bfcf297 DB |
933 | enum machine_mode mode; |
934 | { | |
a4f6c312 SS |
935 | return (gpc_reg_operand (op, mode) |
936 | || (GET_CODE (op) == CONST_INT | |
937 | && INTVAL (op) < 0x7fff8000 | |
2bfcf297 | 938 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
939 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
940 | < 0x100000000ll) | |
2bfcf297 | 941 | #endif |
a4f6c312 | 942 | )); |
2bfcf297 DB |
943 | } |
944 | ||
945 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
946 | signed constant integer valid for 64-bit subtraction. */ | |
947 | ||
948 | int | |
949 | reg_or_sub_cint64_operand (op, mode) | |
592696dd | 950 | rtx op; |
2bfcf297 DB |
951 | enum machine_mode mode; |
952 | { | |
a4f6c312 SS |
953 | return (gpc_reg_operand (op, mode) |
954 | || (GET_CODE (op) == CONST_INT | |
955 | && (- INTVAL (op)) < 0x7fff8000 | |
2bfcf297 | 956 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
957 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
958 | < 0x100000000ll) | |
2bfcf297 | 959 | #endif |
a4f6c312 | 960 | )); |
2bfcf297 DB |
961 | } |
962 | ||
9ebbca7d GK |
963 | /* Return 1 is the operand is either a non-special register or ANY |
964 | 32-bit unsigned constant integer. */ | |
965 | ||
966 | int | |
1d328b19 | 967 | reg_or_logical_cint_operand (op, mode) |
592696dd | 968 | rtx op; |
9ebbca7d GK |
969 | enum machine_mode mode; |
970 | { | |
1d328b19 GK |
971 | if (GET_CODE (op) == CONST_INT) |
972 | { | |
973 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
974 | { | |
975 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 976 | abort (); |
1d328b19 GK |
977 | |
978 | if (INTVAL (op) < 0) | |
979 | return 0; | |
980 | } | |
981 | ||
982 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 983 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
984 | } |
985 | else if (GET_CODE (op) == CONST_DOUBLE) | |
986 | { | |
987 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
988 | || mode != DImode) | |
a4f6c312 | 989 | abort (); |
1d328b19 GK |
990 | |
991 | return CONST_DOUBLE_HIGH (op) == 0; | |
992 | } | |
993 | else | |
994 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
995 | } |
996 | ||
51d3e7d6 | 997 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
998 | |
999 | int | |
1000 | got_operand (op, mode) | |
592696dd | 1001 | rtx op; |
296b8152 | 1002 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
1003 | { |
1004 | return (GET_CODE (op) == SYMBOL_REF | |
1005 | || GET_CODE (op) == CONST | |
1006 | || GET_CODE (op) == LABEL_REF); | |
1007 | } | |
1008 | ||
38c1f2d7 MM |
1009 | /* Return 1 if the operand is a simple references that can be loaded via |
1010 | the GOT (labels involving addition aren't allowed). */ | |
1011 | ||
1012 | int | |
1013 | got_no_const_operand (op, mode) | |
592696dd | 1014 | rtx op; |
296b8152 | 1015 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
1016 | { |
1017 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
1018 | } | |
1019 | ||
4e74d8ec MM |
1020 | /* Return the number of instructions it takes to form a constant in an |
1021 | integer register. */ | |
1022 | ||
1023 | static int | |
1024 | num_insns_constant_wide (value) | |
1025 | HOST_WIDE_INT value; | |
1026 | { | |
1027 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1028 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1029 | return 1; |
1030 | ||
4e74d8ec | 1031 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1032 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1033 | return 1; |
1034 | ||
5f59ecb7 | 1035 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1036 | else if (TARGET_POWERPC64) |
4e74d8ec | 1037 | { |
0d30d435 | 1038 | HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
1039 | HOST_WIDE_INT high = value >> 32; |
1040 | ||
0d30d435 DE |
1041 | low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ |
1042 | ||
0858c623 | 1043 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
1044 | return 2; |
1045 | ||
0858c623 | 1046 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
1047 | return 2; |
1048 | ||
c81fc13e | 1049 | else if (! low) |
4e74d8ec MM |
1050 | return num_insns_constant_wide (high) + 1; |
1051 | ||
1052 | else | |
1053 | return (num_insns_constant_wide (high) | |
e396202a | 1054 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1055 | } |
1056 | #endif | |
1057 | ||
1058 | else | |
1059 | return 2; | |
1060 | } | |
1061 | ||
1062 | int | |
1063 | num_insns_constant (op, mode) | |
1064 | rtx op; | |
1065 | enum machine_mode mode; | |
1066 | { | |
4e74d8ec | 1067 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
1068 | { |
1069 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
1070 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1071 | && mask64_operand (op, mode)) | |
0d30d435 DE |
1072 | return 2; |
1073 | else | |
1074 | #endif | |
1075 | return num_insns_constant_wide (INTVAL (op)); | |
1076 | } | |
4e74d8ec | 1077 | |
6fc48950 MM |
1078 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
1079 | { | |
1080 | long l; | |
1081 | REAL_VALUE_TYPE rv; | |
1082 | ||
1083 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1084 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
e72247f4 | 1085 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
6fc48950 MM |
1086 | } |
1087 | ||
47ad8c61 | 1088 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 1089 | { |
47ad8c61 MM |
1090 | HOST_WIDE_INT low; |
1091 | HOST_WIDE_INT high; | |
1092 | long l[2]; | |
1093 | REAL_VALUE_TYPE rv; | |
1094 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 1095 | |
47ad8c61 MM |
1096 | if (mode == VOIDmode || mode == DImode) |
1097 | { | |
1098 | high = CONST_DOUBLE_HIGH (op); | |
1099 | low = CONST_DOUBLE_LOW (op); | |
1100 | } | |
1101 | else | |
1102 | { | |
1103 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1104 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1105 | high = l[endian]; | |
1106 | low = l[1 - endian]; | |
1107 | } | |
4e74d8ec | 1108 | |
47ad8c61 MM |
1109 | if (TARGET_32BIT) |
1110 | return (num_insns_constant_wide (low) | |
1111 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
1112 | |
1113 | else | |
47ad8c61 | 1114 | { |
e72247f4 | 1115 | if (high == 0 && low >= 0) |
47ad8c61 MM |
1116 | return num_insns_constant_wide (low); |
1117 | ||
e72247f4 | 1118 | else if (high == -1 && low < 0) |
47ad8c61 MM |
1119 | return num_insns_constant_wide (low); |
1120 | ||
a260abc9 DE |
1121 | else if (mask64_operand (op, mode)) |
1122 | return 2; | |
1123 | ||
47ad8c61 MM |
1124 | else if (low == 0) |
1125 | return num_insns_constant_wide (high) + 1; | |
1126 | ||
1127 | else | |
1128 | return (num_insns_constant_wide (high) | |
1129 | + num_insns_constant_wide (low) + 1); | |
1130 | } | |
4e74d8ec MM |
1131 | } |
1132 | ||
1133 | else | |
1134 | abort (); | |
1135 | } | |
1136 | ||
a4f6c312 SS |
1137 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
1138 | register with one instruction per word. We only do this if we can | |
1139 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
1140 | |
1141 | int | |
1142 | easy_fp_constant (op, mode) | |
592696dd SS |
1143 | rtx op; |
1144 | enum machine_mode mode; | |
9878760c | 1145 | { |
9878760c RK |
1146 | if (GET_CODE (op) != CONST_DOUBLE |
1147 | || GET_MODE (op) != mode | |
4e74d8ec | 1148 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
1149 | return 0; |
1150 | ||
a4f6c312 | 1151 | /* Consider all constants with -msoft-float to be easy. */ |
4e74d8ec | 1152 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
1153 | return 1; |
1154 | ||
a4f6c312 | 1155 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 1156 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
1157 | return 0; |
1158 | ||
5ae4759c | 1159 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
1160 | /* Similarly if we are using -mrelocatable, consider all constants |
1161 | to be hard. */ | |
5ae4759c MM |
1162 | if (TARGET_RELOCATABLE) |
1163 | return 0; | |
1164 | #endif | |
1165 | ||
042259f2 DE |
1166 | if (mode == DFmode) |
1167 | { | |
1168 | long k[2]; | |
1169 | REAL_VALUE_TYPE rv; | |
1170 | ||
1171 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1172 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 1173 | |
4e74d8ec MM |
1174 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
1175 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 1176 | } |
4e74d8ec MM |
1177 | |
1178 | else if (mode == SFmode) | |
042259f2 DE |
1179 | { |
1180 | long l; | |
1181 | REAL_VALUE_TYPE rv; | |
1182 | ||
1183 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1184 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 1185 | |
4e74d8ec | 1186 | return num_insns_constant_wide (l) == 1; |
042259f2 | 1187 | } |
4e74d8ec | 1188 | |
a260abc9 | 1189 | else if (mode == DImode) |
c81fc13e | 1190 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1191 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1192 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1193 | |
a9098fd0 GK |
1194 | else if (mode == SImode) |
1195 | return 1; | |
4e74d8ec MM |
1196 | else |
1197 | abort (); | |
9878760c | 1198 | } |
8f75773e | 1199 | |
69ef87e2 AH |
1200 | /* Return 1 if the operand is a CONST_INT and can be put into a |
1201 | register with one instruction. */ | |
1202 | ||
1203 | static int | |
1204 | easy_vector_constant (op) | |
1205 | rtx op; | |
1206 | { | |
1207 | rtx elt; | |
1208 | int units, i; | |
1209 | ||
1210 | if (GET_CODE (op) != CONST_VECTOR) | |
1211 | return 0; | |
1212 | ||
1213 | units = CONST_VECTOR_NUNITS (op); | |
1214 | ||
1215 | /* We can generate 0 easily. Look for that. */ | |
1216 | for (i = 0; i < units; ++i) | |
1217 | { | |
1218 | elt = CONST_VECTOR_ELT (op, i); | |
1219 | ||
1220 | /* We could probably simplify this by just checking for equality | |
1221 | with CONST0_RTX for the current mode, but let's be safe | |
1222 | instead. */ | |
1223 | ||
1224 | if (GET_CODE (elt) == CONST_INT && INTVAL (elt) != 0) | |
1225 | return 0; | |
1226 | ||
1227 | if (GET_CODE (elt) == CONST_DOUBLE | |
1228 | && (CONST_DOUBLE_LOW (elt) != 0 | |
1229 | || CONST_DOUBLE_HIGH (elt) != 0)) | |
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | /* We could probably generate a few other constants trivially, but | |
1234 | gcc doesn't generate them yet. FIXME later. */ | |
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | /* Return 1 if the operand is the constant 0. This works for scalars | |
1239 | as well as vectors. */ | |
1240 | int | |
1241 | zero_constant (op, mode) | |
1242 | rtx op; | |
1243 | enum machine_mode mode; | |
1244 | { | |
1245 | return op == CONST0_RTX (mode); | |
1246 | } | |
1247 | ||
50a0b056 GK |
1248 | /* Return 1 if the operand is 0.0. */ |
1249 | int | |
1250 | zero_fp_constant (op, mode) | |
592696dd SS |
1251 | rtx op; |
1252 | enum machine_mode mode; | |
50a0b056 GK |
1253 | { |
1254 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1255 | } | |
1256 | ||
a4f6c312 SS |
1257 | /* Return 1 if the operand is in volatile memory. Note that during |
1258 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
1259 | volatile memory references. So this function allows us to |
1260 | recognize volatile references where its safe. */ | |
1261 | ||
1262 | int | |
1263 | volatile_mem_operand (op, mode) | |
592696dd | 1264 | rtx op; |
b6c9286a MM |
1265 | enum machine_mode mode; |
1266 | { | |
1267 | if (GET_CODE (op) != MEM) | |
1268 | return 0; | |
1269 | ||
1270 | if (!MEM_VOLATILE_P (op)) | |
1271 | return 0; | |
1272 | ||
1273 | if (mode != GET_MODE (op)) | |
1274 | return 0; | |
1275 | ||
1276 | if (reload_completed) | |
1277 | return memory_operand (op, mode); | |
1278 | ||
1279 | if (reload_in_progress) | |
1280 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1281 | ||
1282 | return memory_address_p (mode, XEXP (op, 0)); | |
1283 | } | |
1284 | ||
97f6e72f | 1285 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1286 | |
1287 | int | |
97f6e72f | 1288 | offsettable_mem_operand (op, mode) |
592696dd | 1289 | rtx op; |
914c2e77 RK |
1290 | enum machine_mode mode; |
1291 | { | |
97f6e72f | 1292 | return ((GET_CODE (op) == MEM) |
677a9668 | 1293 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1294 | mode, XEXP (op, 0))); |
914c2e77 RK |
1295 | } |
1296 | ||
9878760c RK |
1297 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1298 | memory. */ | |
1299 | ||
1300 | int | |
1301 | mem_or_easy_const_operand (op, mode) | |
592696dd | 1302 | rtx op; |
9878760c RK |
1303 | enum machine_mode mode; |
1304 | { | |
1305 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1306 | } | |
1307 | ||
1308 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1309 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1310 | |
1311 | int | |
1312 | add_operand (op, mode) | |
592696dd | 1313 | rtx op; |
9878760c RK |
1314 | enum machine_mode mode; |
1315 | { | |
2bfcf297 | 1316 | if (GET_CODE (op) == CONST_INT) |
e72247f4 DE |
1317 | return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
1318 | || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
2bfcf297 DB |
1319 | |
1320 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1321 | } |
1322 | ||
dcfedcd0 RK |
1323 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1324 | ||
1325 | int | |
1326 | non_add_cint_operand (op, mode) | |
592696dd | 1327 | rtx op; |
296b8152 | 1328 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1329 | { |
1330 | return (GET_CODE (op) == CONST_INT | |
e72247f4 DE |
1331 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
1332 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
dcfedcd0 RK |
1333 | } |
1334 | ||
9878760c RK |
1335 | /* Return 1 if the operand is a non-special register or a constant that |
1336 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1337 | ||
1338 | int | |
1339 | logical_operand (op, mode) | |
592696dd | 1340 | rtx op; |
9878760c RK |
1341 | enum machine_mode mode; |
1342 | { | |
40501e5f | 1343 | HOST_WIDE_INT opl, oph; |
1d328b19 | 1344 | |
dfbdccdb GK |
1345 | if (gpc_reg_operand (op, mode)) |
1346 | return 1; | |
1d328b19 | 1347 | |
dfbdccdb | 1348 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
1349 | { |
1350 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
1351 | ||
1352 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
1353 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
1354 | return 0; | |
1355 | #endif | |
1356 | } | |
dfbdccdb GK |
1357 | else if (GET_CODE (op) == CONST_DOUBLE) |
1358 | { | |
1d328b19 | 1359 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 1360 | abort (); |
1d328b19 GK |
1361 | |
1362 | opl = CONST_DOUBLE_LOW (op); | |
1363 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 1364 | if (oph != 0) |
38886f37 | 1365 | return 0; |
dfbdccdb GK |
1366 | } |
1367 | else | |
1368 | return 0; | |
1d328b19 | 1369 | |
40501e5f AM |
1370 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
1371 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
1372 | } |
1373 | ||
dcfedcd0 | 1374 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1375 | above), but could be split into one. */ |
dcfedcd0 RK |
1376 | |
1377 | int | |
1378 | non_logical_cint_operand (op, mode) | |
592696dd | 1379 | rtx op; |
5f59ecb7 | 1380 | enum machine_mode mode; |
dcfedcd0 | 1381 | { |
dfbdccdb | 1382 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1383 | && ! logical_operand (op, mode) |
1384 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1385 | } |
1386 | ||
19ba8161 | 1387 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1388 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1389 | Reject all ones and all zeros, since these should have been optimized | |
1390 | away and confuse the making of MB and ME. */ | |
1391 | ||
1392 | int | |
19ba8161 | 1393 | mask_operand (op, mode) |
592696dd | 1394 | rtx op; |
19ba8161 | 1395 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1396 | { |
02071907 | 1397 | HOST_WIDE_INT c, lsb; |
9878760c | 1398 | |
19ba8161 DE |
1399 | if (GET_CODE (op) != CONST_INT) |
1400 | return 0; | |
1401 | ||
1402 | c = INTVAL (op); | |
1403 | ||
57deb3a1 AM |
1404 | /* Fail in 64-bit mode if the mask wraps around because the upper |
1405 | 32-bits of the mask will all be 1s, contrary to GCC's internal view. */ | |
1406 | if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001) | |
1407 | return 0; | |
1408 | ||
c5059423 AM |
1409 | /* We don't change the number of transitions by inverting, |
1410 | so make sure we start with the LS bit zero. */ | |
1411 | if (c & 1) | |
1412 | c = ~c; | |
1413 | ||
1414 | /* Reject all zeros or all ones. */ | |
1415 | if (c == 0) | |
9878760c RK |
1416 | return 0; |
1417 | ||
c5059423 AM |
1418 | /* Find the first transition. */ |
1419 | lsb = c & -c; | |
1420 | ||
1421 | /* Invert to look for a second transition. */ | |
1422 | c = ~c; | |
9878760c | 1423 | |
c5059423 AM |
1424 | /* Erase first transition. */ |
1425 | c &= -lsb; | |
9878760c | 1426 | |
c5059423 AM |
1427 | /* Find the second transition (if any). */ |
1428 | lsb = c & -c; | |
1429 | ||
1430 | /* Match if all the bits above are 1's (or c is zero). */ | |
1431 | return c == -lsb; | |
9878760c RK |
1432 | } |
1433 | ||
a260abc9 DE |
1434 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1435 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1436 | Reject all ones and all zeros, since these should have been optimized | |
1437 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1438 | |
1439 | int | |
a260abc9 | 1440 | mask64_operand (op, mode) |
592696dd | 1441 | rtx op; |
a260abc9 DE |
1442 | enum machine_mode mode; |
1443 | { | |
1444 | if (GET_CODE (op) == CONST_INT) | |
1445 | { | |
02071907 | 1446 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1447 | |
c5059423 AM |
1448 | /* We don't change the number of transitions by inverting, |
1449 | so make sure we start with the LS bit zero. */ | |
1450 | c = INTVAL (op); | |
1451 | if (c & 1) | |
1452 | c = ~c; | |
a260abc9 | 1453 | |
c5059423 AM |
1454 | /* Reject all zeros or all ones. */ |
1455 | if (c == 0) | |
e2c953b6 DE |
1456 | return 0; |
1457 | ||
c5059423 AM |
1458 | /* Find the transition, and check that all bits above are 1's. */ |
1459 | lsb = c & -c; | |
1460 | return c == -lsb; | |
e2c953b6 | 1461 | } |
a260abc9 DE |
1462 | else if (GET_CODE (op) == CONST_DOUBLE |
1463 | && (mode == VOIDmode || mode == DImode)) | |
1464 | { | |
02071907 | 1465 | HOST_WIDE_INT low, high, lsb; |
a260abc9 | 1466 | |
c5059423 AM |
1467 | if (HOST_BITS_PER_WIDE_INT < 64) |
1468 | high = CONST_DOUBLE_HIGH (op); | |
a260abc9 | 1469 | |
c5059423 AM |
1470 | low = CONST_DOUBLE_LOW (op); |
1471 | if (low & 1) | |
1472 | { | |
1473 | if (HOST_BITS_PER_WIDE_INT < 64) | |
1474 | high = ~high; | |
1475 | low = ~low; | |
1476 | } | |
a260abc9 | 1477 | |
c5059423 AM |
1478 | if (low == 0) |
1479 | { | |
1480 | if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0) | |
1481 | return 0; | |
a260abc9 | 1482 | |
c5059423 AM |
1483 | lsb = high & -high; |
1484 | return high == -lsb; | |
1485 | } | |
a260abc9 | 1486 | |
c5059423 AM |
1487 | lsb = low & -low; |
1488 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
a260abc9 DE |
1489 | } |
1490 | else | |
1491 | return 0; | |
1492 | } | |
1493 | ||
1494 | /* Return 1 if the operand is either a non-special register or a constant | |
1495 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1496 | ||
1497 | int | |
1498 | and64_operand (op, mode) | |
592696dd | 1499 | rtx op; |
9878760c RK |
1500 | enum machine_mode mode; |
1501 | { | |
a4f6c312 | 1502 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1503 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1504 | ||
1505 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1506 | } |
1507 | ||
a260abc9 DE |
1508 | /* Return 1 if the operand is either a non-special register or a |
1509 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1510 | |
1511 | int | |
a260abc9 | 1512 | and_operand (op, mode) |
592696dd | 1513 | rtx op; |
a260abc9 | 1514 | enum machine_mode mode; |
dcfedcd0 | 1515 | { |
a4f6c312 | 1516 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1517 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1518 | ||
1519 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1520 | } |
1521 | ||
9878760c RK |
1522 | /* Return 1 if the operand is a general register or memory operand. */ |
1523 | ||
1524 | int | |
1525 | reg_or_mem_operand (op, mode) | |
592696dd SS |
1526 | rtx op; |
1527 | enum machine_mode mode; | |
9878760c | 1528 | { |
b6c9286a MM |
1529 | return (gpc_reg_operand (op, mode) |
1530 | || memory_operand (op, mode) | |
1531 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1532 | } |
1533 | ||
a7a813f7 | 1534 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1535 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1536 | instruction. */ |
1537 | ||
1538 | int | |
1539 | lwa_operand (op, mode) | |
592696dd SS |
1540 | rtx op; |
1541 | enum machine_mode mode; | |
a7a813f7 RK |
1542 | { |
1543 | rtx inner = op; | |
1544 | ||
1545 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1546 | inner = SUBREG_REG (inner); | |
1547 | ||
1548 | return gpc_reg_operand (inner, mode) | |
1549 | || (memory_operand (inner, mode) | |
1550 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
1551 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
1552 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
1553 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
1554 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
1555 | } |
1556 | ||
9878760c RK |
1557 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1558 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1559 | forced to lr. */ | |
1560 | ||
1561 | int | |
1562 | call_operand (op, mode) | |
592696dd | 1563 | rtx op; |
9878760c RK |
1564 | enum machine_mode mode; |
1565 | { | |
1566 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1567 | return 0; | |
1568 | ||
1569 | return (GET_CODE (op) == SYMBOL_REF | |
1570 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1571 | } | |
1572 | ||
2af3d377 | 1573 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
a4f6c312 | 1574 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1575 | |
1576 | int | |
1577 | current_file_function_operand (op, mode) | |
592696dd | 1578 | rtx op; |
296b8152 | 1579 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1580 | { |
1581 | return (GET_CODE (op) == SYMBOL_REF | |
1582 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1583 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1584 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1585 | } |
1586 | ||
9878760c RK |
1587 | /* Return 1 if this operand is a valid input for a move insn. */ |
1588 | ||
1589 | int | |
1590 | input_operand (op, mode) | |
592696dd | 1591 | rtx op; |
9878760c RK |
1592 | enum machine_mode mode; |
1593 | { | |
eb4e8003 | 1594 | /* Memory is always valid. */ |
9878760c RK |
1595 | if (memory_operand (op, mode)) |
1596 | return 1; | |
1597 | ||
34792e82 | 1598 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1599 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1600 | return 1; |
1601 | ||
eb4e8003 RK |
1602 | /* For floating-point, easy constants are valid. */ |
1603 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1604 | && CONSTANT_P (op) | |
1605 | && easy_fp_constant (op, mode)) | |
1606 | return 1; | |
1607 | ||
4e74d8ec MM |
1608 | /* Allow any integer constant. */ |
1609 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1610 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1611 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1612 | return 1; |
1613 | ||
eb4e8003 RK |
1614 | /* For floating-point or multi-word mode, the only remaining valid type |
1615 | is a register. */ | |
9878760c RK |
1616 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1617 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1618 | return register_operand (op, mode); |
9878760c | 1619 | |
88fe15a1 RK |
1620 | /* The only cases left are integral modes one word or smaller (we |
1621 | do not get called for MODE_CC values). These can be in any | |
1622 | register. */ | |
1623 | if (register_operand (op, mode)) | |
a8b3aeda | 1624 | return 1; |
88fe15a1 | 1625 | |
84cf9dda | 1626 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1627 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1628 | return 1; |
1629 | ||
9ebbca7d GK |
1630 | /* A constant pool expression (relative to the TOC) is valid */ |
1631 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1632 | return 1; |
1633 | ||
88228c4b MM |
1634 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1635 | to be valid. */ | |
f607bc57 | 1636 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
1637 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1638 | && small_data_operand (op, Pmode)) | |
1639 | return 1; | |
1640 | ||
042259f2 | 1641 | return 0; |
9878760c | 1642 | } |
7509c759 | 1643 | |
a4f6c312 | 1644 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
1645 | |
1646 | int | |
1647 | small_data_operand (op, mode) | |
296b8152 KG |
1648 | rtx op ATTRIBUTE_UNUSED; |
1649 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1650 | { |
38c1f2d7 | 1651 | #if TARGET_ELF |
5f59ecb7 | 1652 | rtx sym_ref; |
7509c759 | 1653 | |
d9407988 | 1654 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1655 | return 0; |
a54d04b7 | 1656 | |
f607bc57 | 1657 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
1658 | return 0; |
1659 | ||
88228c4b MM |
1660 | if (GET_CODE (op) == SYMBOL_REF) |
1661 | sym_ref = op; | |
1662 | ||
1663 | else if (GET_CODE (op) != CONST | |
1664 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1665 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1666 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1667 | return 0; |
1668 | ||
88228c4b | 1669 | else |
dbf55e53 MM |
1670 | { |
1671 | rtx sum = XEXP (op, 0); | |
1672 | HOST_WIDE_INT summand; | |
1673 | ||
1674 | /* We have to be careful here, because it is the referenced address | |
1675 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1676 | summand = INTVAL (XEXP (sum, 1)); | |
1677 | if (summand < 0 || summand > g_switch_value) | |
1678 | return 0; | |
1679 | ||
1680 | sym_ref = XEXP (sum, 0); | |
1681 | } | |
88228c4b MM |
1682 | |
1683 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1684 | return 0; |
1685 | ||
1686 | return 1; | |
d9407988 MM |
1687 | |
1688 | #else | |
1689 | return 0; | |
1690 | #endif | |
7509c759 | 1691 | } |
9ebbca7d GK |
1692 | \f |
1693 | static int | |
1694 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1695 | rtx op; | |
1696 | int *have_sym; | |
1697 | int *have_toc; | |
1698 | { | |
1699 | switch (GET_CODE(op)) | |
1700 | { | |
1701 | case SYMBOL_REF: | |
a4f6c312 SS |
1702 | if (CONSTANT_POOL_ADDRESS_P (op)) |
1703 | { | |
1704 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
1705 | { | |
1706 | *have_sym = 1; | |
1707 | return 1; | |
1708 | } | |
1709 | else | |
1710 | return 0; | |
1711 | } | |
1712 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1713 | { | |
1714 | *have_toc = 1; | |
1715 | return 1; | |
1716 | } | |
1717 | else | |
1718 | return 0; | |
9ebbca7d GK |
1719 | case PLUS: |
1720 | case MINUS: | |
c1f11548 DE |
1721 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
1722 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 1723 | case CONST: |
a4f6c312 | 1724 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 1725 | case CONST_INT: |
a4f6c312 | 1726 | return 1; |
9ebbca7d | 1727 | default: |
a4f6c312 | 1728 | return 0; |
9ebbca7d GK |
1729 | } |
1730 | } | |
1731 | ||
1732 | int | |
1733 | constant_pool_expr_p (op) | |
1734 | rtx op; | |
1735 | { | |
1736 | int have_sym = 0; | |
1737 | int have_toc = 0; | |
1738 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1739 | } | |
1740 | ||
1741 | int | |
1742 | toc_relative_expr_p (op) | |
1743 | rtx op; | |
1744 | { | |
1745 | int have_sym = 0; | |
1746 | int have_toc = 0; | |
1747 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1748 | } | |
1749 | ||
1750 | /* Try machine-dependent ways of modifying an illegitimate address | |
1751 | to be legitimate. If we find one, return the new, valid address. | |
1752 | This is used from only one place: `memory_address' in explow.c. | |
1753 | ||
a4f6c312 SS |
1754 | OLDX is the address as it was before break_out_memory_refs was |
1755 | called. In some cases it is useful to look at this to decide what | |
1756 | needs to be done. | |
9ebbca7d | 1757 | |
a4f6c312 | 1758 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 1759 | |
a4f6c312 SS |
1760 | It is always safe for this function to do nothing. It exists to |
1761 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
1762 | |
1763 | On RS/6000, first check for the sum of a register with a constant | |
1764 | integer that is out of range. If so, generate code to add the | |
1765 | constant with the low-order 16 bits masked to the register and force | |
1766 | this result into another register (this can be done with `cau'). | |
1767 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1768 | possibility of bit 16 being a one. | |
1769 | ||
1770 | Then check for the sum of a register and something not constant, try to | |
1771 | load the other things into a register and return the sum. */ | |
1772 | rtx | |
1773 | rs6000_legitimize_address (x, oldx, mode) | |
1774 | rtx x; | |
1775 | rtx oldx ATTRIBUTE_UNUSED; | |
1776 | enum machine_mode mode; | |
0ac081f6 | 1777 | { |
9ebbca7d GK |
1778 | if (GET_CODE (x) == PLUS |
1779 | && GET_CODE (XEXP (x, 0)) == REG | |
1780 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1781 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1782 | { | |
1783 | HOST_WIDE_INT high_int, low_int; | |
1784 | rtx sum; | |
1785 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1786 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1787 | if (low_int & 0x8000) | |
1788 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1789 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1790 | GEN_INT (high_int)), 0); | |
1791 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1792 | } | |
1793 | else if (GET_CODE (x) == PLUS | |
1794 | && GET_CODE (XEXP (x, 0)) == REG | |
1795 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 1796 | && GET_MODE_NUNITS (mode) == 1 |
9ebbca7d GK |
1797 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) |
1798 | && (TARGET_POWERPC64 || mode != DImode) | |
1799 | && mode != TImode) | |
1800 | { | |
1801 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1802 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1803 | } | |
0ac081f6 AH |
1804 | else if (ALTIVEC_VECTOR_MODE (mode)) |
1805 | { | |
1806 | rtx reg; | |
1807 | ||
1808 | /* Make sure both operands are registers. */ | |
1809 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 1810 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
1811 | force_reg (Pmode, XEXP (x, 1))); |
1812 | ||
1813 | reg = force_reg (Pmode, x); | |
1814 | return reg; | |
1815 | } | |
9ebbca7d GK |
1816 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic |
1817 | && GET_CODE (x) != CONST_INT | |
1818 | && GET_CODE (x) != CONST_DOUBLE | |
1819 | && CONSTANT_P (x) | |
6ac7bf2c GK |
1820 | && GET_MODE_NUNITS (mode) == 1 |
1821 | && (GET_MODE_BITSIZE (mode) <= 32 | |
c3bb62b9 | 1822 | || (TARGET_HARD_FLOAT && mode == DFmode))) |
9ebbca7d GK |
1823 | { |
1824 | rtx reg = gen_reg_rtx (Pmode); | |
1825 | emit_insn (gen_elf_high (reg, (x))); | |
1826 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1827 | } | |
ee890fe2 SS |
1828 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
1829 | && ! flag_pic | |
1830 | && GET_CODE (x) != CONST_INT | |
1831 | && GET_CODE (x) != CONST_DOUBLE | |
1832 | && CONSTANT_P (x) | |
1833 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1834 | && mode != DImode | |
1835 | && mode != TImode) | |
1836 | { | |
1837 | rtx reg = gen_reg_rtx (Pmode); | |
1838 | emit_insn (gen_macho_high (reg, (x))); | |
1839 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1840 | } | |
9ebbca7d GK |
1841 | else if (TARGET_TOC |
1842 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1843 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1844 | { |
1845 | return create_TOC_reference (x); | |
1846 | } | |
1847 | else | |
1848 | return NULL_RTX; | |
1849 | } | |
258bfae2 | 1850 | |
24ea750e DJ |
1851 | /* The convention appears to be to define this wherever it is used. |
1852 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
1853 | is now used here. */ | |
1854 | #ifndef REG_MODE_OK_FOR_BASE_P | |
1855 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
1856 | #endif | |
1857 | ||
1858 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
1859 | replace the input X, or the original X if no replacement is called for. | |
1860 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
1861 | 0 if it should not. | |
1862 | ||
1863 | For RS/6000, we wish to handle large displacements off a base | |
1864 | register by splitting the addend across an addiu/addis and the mem insn. | |
1865 | This cuts number of extra insns needed from 3 to 1. | |
1866 | ||
1867 | On Darwin, we use this to generate code for floating point constants. | |
1868 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
1869 | The Darwin code is inside #if TARGET_MACHO because only then is | |
1870 | machopic_function_base_name() defined. */ | |
1871 | rtx | |
1872 | rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win) | |
1873 | rtx x; | |
1874 | enum machine_mode mode; | |
1875 | int opnum; | |
1876 | int type; | |
1877 | int ind_levels ATTRIBUTE_UNUSED; | |
1878 | int *win; | |
1879 | { | |
1880 | /* We must recognize output that we have already generated ourselves. */ | |
1881 | if (GET_CODE (x) == PLUS | |
1882 | && GET_CODE (XEXP (x, 0)) == PLUS | |
1883 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1884 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1885 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1886 | { | |
1887 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1888 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
1889 | opnum, (enum reload_type)type); | |
1890 | *win = 1; | |
1891 | return x; | |
1892 | } | |
3deb2758 | 1893 | |
24ea750e DJ |
1894 | #if TARGET_MACHO |
1895 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
1896 | && GET_CODE (x) == LO_SUM | |
1897 | && GET_CODE (XEXP (x, 0)) == PLUS | |
1898 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
1899 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
1900 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
1901 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
1902 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
1903 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
1904 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
1905 | { | |
1906 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 1907 | floating point constant. */ |
24ea750e DJ |
1908 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
1909 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
1910 | opnum, (enum reload_type)type); | |
1911 | *win = 1; | |
1912 | return x; | |
1913 | } | |
1914 | #endif | |
1915 | if (GET_CODE (x) == PLUS | |
1916 | && GET_CODE (XEXP (x, 0)) == REG | |
1917 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
1918 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 AH |
1919 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
1920 | && !ALTIVEC_VECTOR_MODE (mode)) | |
24ea750e DJ |
1921 | { |
1922 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
1923 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
1924 | HOST_WIDE_INT high | |
1925 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1926 | ||
1927 | /* Check for 32-bit overflow. */ | |
1928 | if (high + low != val) | |
1929 | { | |
1930 | *win = 0; | |
1931 | return x; | |
1932 | } | |
1933 | ||
1934 | /* Reload the high part into a base reg; leave the low part | |
1935 | in the mem directly. */ | |
1936 | ||
1937 | x = gen_rtx_PLUS (GET_MODE (x), | |
1938 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
1939 | GEN_INT (high)), | |
1940 | GEN_INT (low)); | |
1941 | ||
1942 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1943 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
1944 | opnum, (enum reload_type)type); | |
1945 | *win = 1; | |
1946 | return x; | |
1947 | } | |
1948 | #if TARGET_MACHO | |
1949 | if (GET_CODE (x) == SYMBOL_REF | |
1950 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 1951 | && !ALTIVEC_VECTOR_MODE (mode) |
24ea750e DJ |
1952 | && flag_pic) |
1953 | { | |
1954 | /* Darwin load of floating point constant. */ | |
1955 | rtx offset = gen_rtx (CONST, Pmode, | |
1956 | gen_rtx (MINUS, Pmode, x, | |
1957 | gen_rtx (SYMBOL_REF, Pmode, | |
1958 | machopic_function_base_name ()))); | |
1959 | x = gen_rtx (LO_SUM, GET_MODE (x), | |
1960 | gen_rtx (PLUS, Pmode, pic_offset_table_rtx, | |
1961 | gen_rtx (HIGH, Pmode, offset)), offset); | |
1962 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1963 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
1964 | opnum, (enum reload_type)type); | |
1965 | *win = 1; | |
1966 | return x; | |
1967 | } | |
1968 | #endif | |
1969 | if (TARGET_TOC | |
c1f11548 DE |
1970 | && CONSTANT_POOL_EXPR_P (x) |
1971 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) | |
24ea750e DJ |
1972 | { |
1973 | (x) = create_TOC_reference (x); | |
1974 | *win = 1; | |
1975 | return x; | |
1976 | } | |
1977 | *win = 0; | |
1978 | return x; | |
1979 | } | |
1980 | ||
258bfae2 FS |
1981 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
1982 | that is a valid memory address for an instruction. | |
1983 | The MODE argument is the machine mode for the MEM expression | |
1984 | that wants to use this address. | |
1985 | ||
1986 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1987 | refers to a constant pool entry of an address (or the sum of it | |
1988 | plus a constant), a short (16-bit signed) constant plus a register, | |
1989 | the sum of two registers, or a register indirect, possibly with an | |
1990 | auto-increment. For DFmode and DImode with an constant plus register, | |
1991 | we must ensure that both words are addressable or PowerPC64 with offset | |
1992 | word aligned. | |
1993 | ||
1994 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1995 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1996 | adjacent memory cells are accessed by adding word-sized offsets | |
1997 | during assembly output. */ | |
1998 | int | |
1999 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
2000 | enum machine_mode mode; | |
2001 | rtx x; | |
2002 | int reg_ok_strict; | |
2003 | { | |
2004 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
2005 | return 1; | |
2006 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
2007 | && TARGET_UPDATE | |
2008 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
2009 | return 1; | |
2010 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
2011 | return 1; | |
2012 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
2013 | return 1; | |
2014 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
2015 | if (! reg_ok_strict | |
2016 | && GET_CODE (x) == PLUS | |
2017 | && GET_CODE (XEXP (x, 0)) == REG | |
2018 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
2019 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2020 | return 1; | |
2021 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
2022 | return 1; | |
2023 | if (mode != TImode | |
2024 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
2025 | && (TARGET_POWERPC64 || mode != DImode) | |
2026 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
2027 | return 1; | |
2028 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
2029 | return 1; | |
2030 | return 0; | |
2031 | } | |
fb4d4348 | 2032 | \f |
a4f6c312 SS |
2033 | /* Try to output insns to set TARGET equal to the constant C if it can |
2034 | be done in less than N insns. Do all computations in MODE. | |
2035 | Returns the place where the output has been placed if it can be | |
2036 | done and the insns have been emitted. If it would take more than N | |
2037 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
2038 | |
2039 | rtx | |
2040 | rs6000_emit_set_const (dest, mode, source, n) | |
2041 | rtx dest, source; | |
2042 | enum machine_mode mode; | |
2043 | int n ATTRIBUTE_UNUSED; | |
2044 | { | |
2045 | HOST_WIDE_INT c0, c1; | |
2046 | ||
2047 | if (mode == QImode || mode == HImode || mode == SImode) | |
2048 | { | |
2049 | if (dest == NULL) | |
2050 | dest = gen_reg_rtx (mode); | |
2051 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
2052 | return dest; | |
2053 | } | |
2054 | ||
2055 | if (GET_CODE (source) == CONST_INT) | |
2056 | { | |
2057 | c0 = INTVAL (source); | |
2058 | c1 = -(c0 < 0); | |
2059 | } | |
2060 | else if (GET_CODE (source) == CONST_DOUBLE) | |
2061 | { | |
2062 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2063 | c0 = CONST_DOUBLE_LOW (source); | |
2064 | c1 = -(c0 < 0); | |
2065 | #else | |
2066 | c0 = CONST_DOUBLE_LOW (source); | |
2067 | c1 = CONST_DOUBLE_HIGH (source); | |
2068 | #endif | |
2069 | } | |
2070 | else | |
a4f6c312 | 2071 | abort (); |
2bfcf297 DB |
2072 | |
2073 | return rs6000_emit_set_long_const (dest, c0, c1); | |
2074 | } | |
2075 | ||
2076 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
2077 | fall back to a straight forward decomposition. We do this to avoid | |
2078 | exponential run times encountered when looking for longer sequences | |
2079 | with rs6000_emit_set_const. */ | |
2080 | static rtx | |
2081 | rs6000_emit_set_long_const (dest, c1, c2) | |
2082 | rtx dest; | |
2083 | HOST_WIDE_INT c1, c2; | |
2084 | { | |
2085 | if (!TARGET_POWERPC64) | |
2086 | { | |
2087 | rtx operand1, operand2; | |
2088 | ||
2089 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
2090 | DImode); | |
2091 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
2092 | DImode); | |
2093 | emit_move_insn (operand1, GEN_INT (c1)); | |
2094 | emit_move_insn (operand2, GEN_INT (c2)); | |
2095 | } | |
2096 | else | |
2097 | { | |
bc06712d | 2098 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 2099 | |
bc06712d TR |
2100 | ud1 = c1 & 0xffff; |
2101 | ud2 = (c1 & 0xffff0000) >> 16; | |
2bfcf297 | 2102 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 2103 | c2 = c1 >> 32; |
2bfcf297 | 2104 | #endif |
bc06712d TR |
2105 | ud3 = c2 & 0xffff; |
2106 | ud4 = (c2 & 0xffff0000) >> 16; | |
2bfcf297 | 2107 | |
bc06712d TR |
2108 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
2109 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) | |
2bfcf297 | 2110 | { |
bc06712d TR |
2111 | if (ud1 & 0x8000) |
2112 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); | |
2113 | else | |
2114 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 2115 | } |
2bfcf297 | 2116 | |
bc06712d TR |
2117 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
2118 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) | |
252b88f7 | 2119 | { |
bc06712d TR |
2120 | if (ud2 & 0x8000) |
2121 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) | |
2122 | - 0x80000000)); | |
252b88f7 | 2123 | else |
bc06712d TR |
2124 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
2125 | if (ud1 != 0) | |
2126 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 2127 | } |
bc06712d TR |
2128 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
2129 | || (ud4 == 0 && ! (ud3 & 0x8000))) | |
2130 | { | |
2131 | if (ud3 & 0x8000) | |
2132 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) | |
2133 | - 0x80000000)); | |
2134 | else | |
2135 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
2136 | ||
2137 | if (ud2 != 0) | |
2138 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
2139 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
2140 | if (ud1 != 0) | |
2141 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
2142 | } | |
2143 | else | |
2144 | { | |
2145 | if (ud4 & 0x8000) | |
2146 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) | |
2147 | - 0x80000000)); | |
2148 | else | |
2149 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
2150 | ||
2151 | if (ud3 != 0) | |
2152 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 2153 | |
bc06712d TR |
2154 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
2155 | if (ud2 != 0) | |
2156 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, | |
2157 | GEN_INT (ud2 << 16))); | |
2158 | if (ud1 != 0) | |
2159 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
2160 | } | |
2161 | } | |
2bfcf297 DB |
2162 | return dest; |
2163 | } | |
2164 | ||
fb4d4348 GK |
2165 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
2166 | void | |
2167 | rs6000_emit_move (dest, source, mode) | |
2168 | rtx dest; | |
2169 | rtx source; | |
2170 | enum machine_mode mode; | |
2171 | { | |
2172 | rtx operands[2]; | |
2173 | operands[0] = dest; | |
2174 | operands[1] = source; | |
2175 | ||
2176 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
2177 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
2178 | && ! FLOAT_MODE_P (mode) | |
2179 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
2180 | { | |
2181 | /* FIXME. This should never happen. */ | |
2182 | /* Since it seems that it does, do the safe thing and convert | |
2183 | to a CONST_INT. */ | |
2184 | operands[1] = | |
2185 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
2186 | } | |
2187 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
2188 | && ! FLOAT_MODE_P (mode) | |
2189 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
2190 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
2191 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
2192 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
2193 | abort (); | |
c9e8cb32 DD |
2194 | |
2195 | /* Check if GCC is setting up a block move that will end up using FP | |
2196 | registers as temporaries. We must make sure this is acceptable. */ | |
2197 | if (GET_CODE (operands[0]) == MEM | |
2198 | && GET_CODE (operands[1]) == MEM | |
2199 | && mode == DImode | |
41543739 GK |
2200 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
2201 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
2202 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
2203 | ? 32 : MEM_ALIGN (operands[0]))) | |
2204 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
2205 | ? 32 | |
2206 | : MEM_ALIGN (operands[1])))) | |
2207 | && ! MEM_VOLATILE_P (operands [0]) | |
2208 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 2209 | { |
41543739 GK |
2210 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
2211 | adjust_address (operands[1], SImode, 0)); | |
2212 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
2213 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
2214 | return; |
2215 | } | |
fb4d4348 GK |
2216 | |
2217 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
2218 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 2219 | |
ffc14f31 GK |
2220 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
2221 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 2222 | { |
ffc14f31 GK |
2223 | int regnum; |
2224 | ||
2225 | if (reload_in_progress || reload_completed) | |
2226 | regnum = true_regnum (operands[1]); | |
2227 | else if (GET_CODE (operands[1]) == REG) | |
2228 | regnum = REGNO (operands[1]); | |
2229 | else | |
2230 | regnum = -1; | |
fb4d4348 GK |
2231 | |
2232 | /* If operands[1] is a register, on POWER it may have | |
2233 | double-precision data in it, so truncate it to single | |
2234 | precision. */ | |
2235 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
2236 | { | |
2237 | rtx newreg; | |
2238 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
2239 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
2240 | operands[1] = newreg; | |
2241 | } | |
2242 | } | |
2243 | ||
a9098fd0 GK |
2244 | /* Handle the case where reload calls us with an invalid address; |
2245 | and the case of CONSTANT_P_RTX. */ | |
69ef87e2 AH |
2246 | if (!VECTOR_MODE_P (mode) |
2247 | && (! general_operand (operands[1], mode) | |
2248 | || ! nonimmediate_operand (operands[0], mode) | |
2249 | || GET_CODE (operands[1]) == CONSTANT_P_RTX)) | |
fb4d4348 GK |
2250 | { |
2251 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2252 | return; | |
2253 | } | |
a9098fd0 | 2254 | |
fb4d4348 GK |
2255 | /* FIXME: In the long term, this switch statement should go away |
2256 | and be replaced by a sequence of tests based on things like | |
2257 | mode == Pmode. */ | |
2258 | switch (mode) | |
2259 | { | |
2260 | case HImode: | |
2261 | case QImode: | |
2262 | if (CONSTANT_P (operands[1]) | |
2263 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 2264 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2265 | break; |
2266 | ||
06f4e019 | 2267 | case TFmode: |
fb4d4348 GK |
2268 | case DFmode: |
2269 | case SFmode: | |
2270 | if (CONSTANT_P (operands[1]) | |
2271 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 2272 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2273 | break; |
2274 | ||
0ac081f6 AH |
2275 | case V16QImode: |
2276 | case V8HImode: | |
2277 | case V4SFmode: | |
2278 | case V4SImode: | |
69ef87e2 AH |
2279 | if (CONSTANT_P (operands[1]) |
2280 | && !easy_vector_constant (operands[1])) | |
0ac081f6 AH |
2281 | operands[1] = force_const_mem (mode, operands[1]); |
2282 | break; | |
2283 | ||
fb4d4348 | 2284 | case SImode: |
a9098fd0 | 2285 | case DImode: |
fb4d4348 GK |
2286 | /* Use default pattern for address of ELF small data */ |
2287 | if (TARGET_ELF | |
a9098fd0 | 2288 | && mode == Pmode |
f607bc57 | 2289 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
2290 | && (GET_CODE (operands[1]) == SYMBOL_REF |
2291 | || GET_CODE (operands[1]) == CONST) | |
2292 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
2293 | { |
2294 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2295 | return; | |
2296 | } | |
2297 | ||
f607bc57 | 2298 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
2299 | && mode == Pmode && mode == SImode |
2300 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
2301 | { |
2302 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
2303 | return; | |
2304 | } | |
2305 | ||
ee890fe2 SS |
2306 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
2307 | && TARGET_NO_TOC && ! flag_pic | |
a9098fd0 | 2308 | && mode == Pmode |
fb4d4348 GK |
2309 | && CONSTANT_P (operands[1]) |
2310 | && GET_CODE (operands[1]) != HIGH | |
2311 | && GET_CODE (operands[1]) != CONST_INT) | |
2312 | { | |
a9098fd0 | 2313 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
2314 | |
2315 | /* If this is a function address on -mcall-aixdesc, | |
2316 | convert it to the address of the descriptor. */ | |
2317 | if (DEFAULT_ABI == ABI_AIX | |
2318 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2319 | && XSTR (operands[1], 0)[0] == '.') | |
2320 | { | |
2321 | const char *name = XSTR (operands[1], 0); | |
2322 | rtx new_ref; | |
2323 | while (*name == '.') | |
2324 | name++; | |
2325 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
2326 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
2327 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
2328 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
2329 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
2330 | operands[1] = new_ref; | |
2331 | } | |
7509c759 | 2332 | |
ee890fe2 SS |
2333 | if (DEFAULT_ABI == ABI_DARWIN) |
2334 | { | |
2335 | emit_insn (gen_macho_high (target, operands[1])); | |
2336 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
2337 | return; | |
2338 | } | |
2339 | ||
fb4d4348 GK |
2340 | emit_insn (gen_elf_high (target, operands[1])); |
2341 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
2342 | return; | |
2343 | } | |
2344 | ||
a9098fd0 GK |
2345 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
2346 | and we have put it in the TOC, we just need to make a TOC-relative | |
2347 | reference to it. */ | |
2348 | if (TARGET_TOC | |
2349 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2350 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
2351 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
2352 | get_pool_mode (operands[1]))) | |
fb4d4348 | 2353 | { |
a9098fd0 | 2354 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 2355 | } |
a9098fd0 GK |
2356 | else if (mode == Pmode |
2357 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
2358 | && ((GET_CODE (operands[1]) != CONST_INT |
2359 | && ! easy_fp_constant (operands[1], mode)) | |
2360 | || (GET_CODE (operands[1]) == CONST_INT | |
2361 | && num_insns_constant (operands[1], mode) > 2) | |
2362 | || (GET_CODE (operands[0]) == REG | |
2363 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
2364 | && GET_CODE (operands[1]) != HIGH |
2365 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2366 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
2367 | { |
2368 | /* Emit a USE operation so that the constant isn't deleted if | |
2369 | expensive optimizations are turned on because nobody | |
2370 | references it. This should only be done for operands that | |
2371 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
2372 | This should not be done for operands that contain LABEL_REFs. | |
2373 | For now, we just handle the obvious case. */ | |
2374 | if (GET_CODE (operands[1]) != LABEL_REF) | |
2375 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
2376 | ||
c859cda6 | 2377 | #if TARGET_MACHO |
ee890fe2 SS |
2378 | /* Darwin uses a special PIC legitimizer. */ |
2379 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
2380 | { | |
ee890fe2 SS |
2381 | operands[1] = |
2382 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
2383 | operands[0]); |
2384 | if (operands[0] != operands[1]) | |
2385 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
2386 | return; |
2387 | } | |
c859cda6 | 2388 | #endif |
ee890fe2 | 2389 | |
fb4d4348 GK |
2390 | /* If we are to limit the number of things we put in the TOC and |
2391 | this is a symbol plus a constant we can add in one insn, | |
2392 | just put the symbol in the TOC and add the constant. Don't do | |
2393 | this if reload is in progress. */ | |
2394 | if (GET_CODE (operands[1]) == CONST | |
2395 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
2396 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 2397 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
2398 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
2399 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
2400 | && ! side_effects_p (operands[0])) | |
2401 | { | |
a4f6c312 SS |
2402 | rtx sym = |
2403 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
2404 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
2405 | ||
a9098fd0 GK |
2406 | sym = force_reg (mode, sym); |
2407 | if (mode == SImode) | |
2408 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
2409 | else | |
2410 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
2411 | return; |
2412 | } | |
2413 | ||
a9098fd0 | 2414 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2415 | |
2416 | if (TARGET_TOC | |
d34c5b80 DE |
2417 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
2418 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
2419 | get_pool_constant (XEXP (operands[1], 0)), | |
2420 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 2421 | { |
ba4828e0 RK |
2422 | operands[1] |
2423 | = gen_rtx_MEM (mode, | |
2424 | create_TOC_reference (XEXP (operands[1], 0))); | |
2425 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 2426 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 2427 | } |
fb4d4348 GK |
2428 | } |
2429 | break; | |
a9098fd0 | 2430 | |
fb4d4348 GK |
2431 | case TImode: |
2432 | if (GET_CODE (operands[0]) == MEM | |
2433 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
2434 | && ! reload_in_progress) | |
792760b9 RK |
2435 | operands[0] |
2436 | = replace_equiv_address (operands[0], | |
2437 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
2438 | |
2439 | if (GET_CODE (operands[1]) == MEM | |
2440 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
2441 | && ! reload_in_progress) | |
792760b9 RK |
2442 | operands[1] |
2443 | = replace_equiv_address (operands[1], | |
2444 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
fb4d4348 GK |
2445 | break; |
2446 | ||
2447 | default: | |
2448 | abort (); | |
2449 | } | |
2450 | ||
a9098fd0 GK |
2451 | /* Above, we may have called force_const_mem which may have returned |
2452 | an invalid address. If we can, fix this up; otherwise, reload will | |
2453 | have to deal with it. */ | |
2454 | if (GET_CODE (operands[1]) == MEM | |
2455 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
2456 | && ! reload_in_progress) | |
f4ef873c | 2457 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 2458 | |
fb4d4348 | 2459 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 2460 | return; |
fb4d4348 | 2461 | } |
4697a36c MM |
2462 | \f |
2463 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2464 | for a call to a function whose data type is FNTYPE. | |
2465 | For a library call, FNTYPE is 0. | |
2466 | ||
2467 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 2468 | so we never return a PARALLEL. */ |
4697a36c MM |
2469 | |
2470 | void | |
2471 | init_cumulative_args (cum, fntype, libname, incoming) | |
2472 | CUMULATIVE_ARGS *cum; | |
2473 | tree fntype; | |
296b8152 | 2474 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
2475 | int incoming; |
2476 | { | |
2477 | static CUMULATIVE_ARGS zero_cumulative; | |
2478 | ||
2479 | *cum = zero_cumulative; | |
2480 | cum->words = 0; | |
2481 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 2482 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 2483 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
7509c759 | 2484 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 2485 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
2486 | |
2487 | if (incoming) | |
bd227acc | 2488 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
2489 | |
2490 | else if (cum->prototype) | |
2491 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
2492 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
2493 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
2494 | ||
2495 | else | |
2496 | cum->nargs_prototype = 0; | |
2497 | ||
2498 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 2499 | |
9ebbca7d GK |
2500 | /* Check for longcall's */ |
2501 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
2502 | cum->call_cookie = CALL_LONG; |
2503 | ||
4697a36c MM |
2504 | if (TARGET_DEBUG_ARG) |
2505 | { | |
2506 | fprintf (stderr, "\ninit_cumulative_args:"); | |
2507 | if (fntype) | |
2508 | { | |
2509 | tree ret_type = TREE_TYPE (fntype); | |
2510 | fprintf (stderr, " ret code = %s,", | |
2511 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
2512 | } | |
2513 | ||
6a4cee5f MM |
2514 | if (cum->call_cookie & CALL_LONG) |
2515 | fprintf (stderr, " longcall,"); | |
2516 | ||
4697a36c MM |
2517 | fprintf (stderr, " proto = %d, nargs = %d\n", |
2518 | cum->prototype, cum->nargs_prototype); | |
2519 | } | |
2520 | } | |
2521 | \f | |
c229cba9 DE |
2522 | /* If defined, a C expression which determines whether, and in which |
2523 | direction, to pad out an argument with extra space. The value | |
2524 | should be of type `enum direction': either `upward' to pad above | |
2525 | the argument, `downward' to pad below, or `none' to inhibit | |
2526 | padding. | |
2527 | ||
2528 | For the AIX ABI structs are always stored left shifted in their | |
2529 | argument slot. */ | |
2530 | ||
9ebbca7d | 2531 | enum direction |
c229cba9 DE |
2532 | function_arg_padding (mode, type) |
2533 | enum machine_mode mode; | |
2534 | tree type; | |
2535 | { | |
c85f7c16 | 2536 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 2537 | return upward; |
c229cba9 DE |
2538 | |
2539 | /* This is the default definition. */ | |
2540 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 2541 | ? upward |
c229cba9 DE |
2542 | : ((mode == BLKmode |
2543 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
2544 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
2545 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 2546 | ? downward : upward)); |
c229cba9 DE |
2547 | } |
2548 | ||
b6c9286a MM |
2549 | /* If defined, a C expression that gives the alignment boundary, in bits, |
2550 | of an argument with the specified mode and type. If it is not defined, | |
2551 | PARM_BOUNDARY is used for all arguments. | |
2552 | ||
2310f99a | 2553 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
2554 | |
2555 | int | |
2556 | function_arg_boundary (mode, type) | |
2557 | enum machine_mode mode; | |
9ebbca7d | 2558 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 2559 | { |
f607bc57 | 2560 | if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode)) |
e1f83b4d | 2561 | return 64; |
0ac081f6 AH |
2562 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2563 | return 128; | |
9ebbca7d | 2564 | else |
b6c9286a | 2565 | return PARM_BOUNDARY; |
b6c9286a MM |
2566 | } |
2567 | \f | |
4697a36c MM |
2568 | /* Update the data in CUM to advance over an argument |
2569 | of mode MODE and data type TYPE. | |
2570 | (TYPE is null for libcalls where that information may not be available.) */ | |
2571 | ||
2572 | void | |
2573 | function_arg_advance (cum, mode, type, named) | |
2574 | CUMULATIVE_ARGS *cum; | |
2575 | enum machine_mode mode; | |
2576 | tree type; | |
2577 | int named; | |
2578 | { | |
2579 | cum->nargs_prototype--; | |
2580 | ||
0ac081f6 AH |
2581 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2582 | { | |
2583 | if (cum->vregno <= ALTIVEC_ARG_MAX_REG && cum->nargs_prototype >= 0) | |
2584 | cum->vregno++; | |
2585 | else | |
2586 | cum->words += RS6000_ARG_SIZE (mode, type); | |
2587 | } | |
f607bc57 | 2588 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2589 | { |
4cc833b7 RH |
2590 | if (TARGET_HARD_FLOAT |
2591 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 2592 | { |
4cc833b7 RH |
2593 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
2594 | cum->fregno++; | |
2595 | else | |
2596 | { | |
2597 | if (mode == DFmode) | |
2598 | cum->words += cum->words & 1; | |
d34c5b80 | 2599 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 2600 | } |
4697a36c | 2601 | } |
4cc833b7 RH |
2602 | else |
2603 | { | |
2604 | int n_words; | |
2605 | int gregno = cum->sysv_gregno; | |
2606 | ||
2607 | /* Aggregates and IEEE quad get passed by reference. */ | |
2608 | if ((type && AGGREGATE_TYPE_P (type)) | |
2609 | || mode == TFmode) | |
2610 | n_words = 1; | |
2611 | else | |
d34c5b80 | 2612 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2613 | |
2614 | /* Long long is put in odd registers. */ | |
2615 | if (n_words == 2 && (gregno & 1) == 0) | |
2616 | gregno += 1; | |
2617 | ||
2618 | /* Long long is not split between registers and stack. */ | |
2619 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
2620 | { | |
2621 | /* Long long is aligned on the stack. */ | |
2622 | if (n_words == 2) | |
2623 | cum->words += cum->words & 1; | |
2624 | cum->words += n_words; | |
2625 | } | |
4697a36c | 2626 | |
4cc833b7 RH |
2627 | /* Note: continuing to accumulate gregno past when we've started |
2628 | spilling to the stack indicates the fact that we've started | |
2629 | spilling to the stack to expand_builtin_saveregs. */ | |
2630 | cum->sysv_gregno = gregno + n_words; | |
2631 | } | |
4697a36c | 2632 | |
4cc833b7 RH |
2633 | if (TARGET_DEBUG_ARG) |
2634 | { | |
2635 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2636 | cum->words, cum->fregno); | |
2637 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
2638 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
2639 | fprintf (stderr, "mode = %4s, named = %d\n", | |
2640 | GET_MODE_NAME (mode), named); | |
2641 | } | |
4697a36c MM |
2642 | } |
2643 | else | |
4cc833b7 RH |
2644 | { |
2645 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2646 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
a4f6c312 | 2647 | |
d34c5b80 | 2648 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 2649 | |
d34c5b80 DE |
2650 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) |
2651 | cum->fregno++; | |
4cc833b7 RH |
2652 | |
2653 | if (TARGET_DEBUG_ARG) | |
2654 | { | |
2655 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2656 | cum->words, cum->fregno); | |
2657 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
2658 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
2659 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
2660 | } | |
2661 | } | |
4697a36c MM |
2662 | } |
2663 | \f | |
2664 | /* Determine where to put an argument to a function. | |
2665 | Value is zero to push the argument on the stack, | |
2666 | or a hard register in which to store the argument. | |
2667 | ||
2668 | MODE is the argument's machine mode. | |
2669 | TYPE is the data type of the argument (as a tree). | |
2670 | This is null for libcalls where that information may | |
2671 | not be available. | |
2672 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2673 | the preceding args and about the function being called. | |
2674 | NAMED is nonzero if this argument is a named parameter | |
2675 | (otherwise it is an extra parameter matching an ellipsis). | |
2676 | ||
2677 | On RS/6000 the first eight words of non-FP are normally in registers | |
2678 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2679 | Under V.4, the first 8 FP args are in registers. | |
2680 | ||
2681 | If this is floating-point and no prototype is specified, we use | |
2682 | both an FP and integer register (or possibly FP reg and stack). Library | |
2683 | functions (when TYPE is zero) always have the proper types for args, | |
2684 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2685 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2686 | |
2687 | struct rtx_def * | |
2688 | function_arg (cum, mode, type, named) | |
2689 | CUMULATIVE_ARGS *cum; | |
2690 | enum machine_mode mode; | |
2691 | tree type; | |
20c29ebe | 2692 | int named; |
4697a36c | 2693 | { |
4cc833b7 | 2694 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2695 | |
a4f6c312 SS |
2696 | /* Return a marker to indicate whether CR1 needs to set or clear the |
2697 | bit that V.4 uses to say fp args were passed in registers. | |
2698 | Assume that we don't need the marker for software floating point, | |
2699 | or compiler generated library calls. */ | |
4697a36c MM |
2700 | if (mode == VOIDmode) |
2701 | { | |
f607bc57 | 2702 | if (abi == ABI_V4 |
7509c759 MM |
2703 | && TARGET_HARD_FLOAT |
2704 | && cum->nargs_prototype < 0 | |
4697a36c | 2705 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2706 | { |
6a4cee5f MM |
2707 | return GEN_INT (cum->call_cookie |
2708 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2709 | ? CALL_V4_SET_FP_ARGS | |
2710 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2711 | } |
4697a36c | 2712 | |
7509c759 | 2713 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2714 | } |
2715 | ||
0ac081f6 AH |
2716 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2717 | { | |
20c29ebe | 2718 | if (named && cum->vregno <= ALTIVEC_ARG_MAX_REG) |
0ac081f6 AH |
2719 | return gen_rtx_REG (mode, cum->vregno); |
2720 | else | |
2721 | return NULL; | |
2722 | } | |
f607bc57 | 2723 | else if (abi == ABI_V4) |
4697a36c | 2724 | { |
4cc833b7 RH |
2725 | if (TARGET_HARD_FLOAT |
2726 | && (mode == SFmode || mode == DFmode)) | |
2727 | { | |
2728 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2729 | return gen_rtx_REG (mode, cum->fregno); | |
2730 | else | |
2731 | return NULL; | |
2732 | } | |
2733 | else | |
2734 | { | |
2735 | int n_words; | |
2736 | int gregno = cum->sysv_gregno; | |
2737 | ||
2738 | /* Aggregates and IEEE quad get passed by reference. */ | |
2739 | if ((type && AGGREGATE_TYPE_P (type)) | |
2740 | || mode == TFmode) | |
2741 | n_words = 1; | |
2742 | else | |
d34c5b80 | 2743 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2744 | |
2745 | /* Long long is put in odd registers. */ | |
2746 | if (n_words == 2 && (gregno & 1) == 0) | |
2747 | gregno += 1; | |
2748 | ||
2749 | /* Long long is not split between registers and stack. */ | |
2750 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2751 | return gen_rtx_REG (mode, gregno); | |
2752 | else | |
2753 | return NULL; | |
2754 | } | |
4697a36c | 2755 | } |
4cc833b7 RH |
2756 | else |
2757 | { | |
2758 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2759 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2760 | int align_words = cum->words + align; | |
4697a36c | 2761 | |
4cc833b7 RH |
2762 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2763 | return NULL_RTX; | |
2764 | ||
2765 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2766 | { | |
2767 | if (! type | |
2768 | || ((cum->nargs_prototype > 0) | |
2769 | /* IBM AIX extended its linkage convention definition always | |
2770 | to require FP args after register save area hole on the | |
2771 | stack. */ | |
2772 | && (DEFAULT_ABI != ABI_AIX | |
2773 | || ! TARGET_XL_CALL | |
2774 | || (align_words < GP_ARG_NUM_REG)))) | |
2775 | return gen_rtx_REG (mode, cum->fregno); | |
2776 | ||
2777 | return gen_rtx_PARALLEL (mode, | |
2778 | gen_rtvec (2, | |
39403d82 | 2779 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2780 | ((align_words >= GP_ARG_NUM_REG) |
2781 | ? NULL_RTX | |
2782 | : (align_words | |
d34c5b80 | 2783 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
2784 | > GP_ARG_NUM_REG |
2785 | /* If this is partially on the stack, then | |
2786 | we only include the portion actually | |
2787 | in registers here. */ | |
39403d82 | 2788 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2789 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2790 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2791 | GP_ARG_MIN_REG + align_words))), |
2792 | const0_rtx), | |
39403d82 DE |
2793 | gen_rtx_EXPR_LIST (VOIDmode, |
2794 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2795 | const0_rtx))); |
4cc833b7 RH |
2796 | } |
2797 | else if (align_words < GP_ARG_NUM_REG) | |
2798 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2799 | else | |
2800 | return NULL_RTX; | |
4697a36c | 2801 | } |
4697a36c MM |
2802 | } |
2803 | \f | |
2804 | /* For an arg passed partly in registers and partly in memory, | |
2805 | this is the number of registers used. | |
2806 | For args passed entirely in registers or entirely in memory, zero. */ | |
2807 | ||
2808 | int | |
2809 | function_arg_partial_nregs (cum, mode, type, named) | |
2810 | CUMULATIVE_ARGS *cum; | |
2811 | enum machine_mode mode; | |
2812 | tree type; | |
d34c5b80 | 2813 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2814 | { |
f607bc57 | 2815 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2816 | return 0; |
4697a36c | 2817 | |
0ac081f6 AH |
2818 | if (USE_FP_FOR_ARG_P (*cum, mode, type) |
2819 | || USE_ALTIVEC_FOR_ARG_P (*cum, mode, type)) | |
4697a36c MM |
2820 | { |
2821 | if (cum->nargs_prototype >= 0) | |
2822 | return 0; | |
2823 | } | |
2824 | ||
2825 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 2826 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
2827 | { |
2828 | int ret = GP_ARG_NUM_REG - cum->words; | |
2829 | if (ret && TARGET_DEBUG_ARG) | |
2830 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2831 | ||
2832 | return ret; | |
2833 | } | |
2834 | ||
2835 | return 0; | |
2836 | } | |
2837 | \f | |
2838 | /* A C expression that indicates when an argument must be passed by | |
2839 | reference. If nonzero for an argument, a copy of that argument is | |
2840 | made in memory and a pointer to the argument is passed instead of | |
2841 | the argument itself. The pointer is passed in whatever way is | |
2842 | appropriate for passing a pointer to that type. | |
2843 | ||
2844 | Under V.4, structures and unions are passed by reference. */ | |
2845 | ||
2846 | int | |
2847 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2848 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2849 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2850 | tree type; |
296b8152 | 2851 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2852 | { |
f607bc57 | 2853 | if (DEFAULT_ABI == ABI_V4 |
4cc833b7 RH |
2854 | && ((type && AGGREGATE_TYPE_P (type)) |
2855 | || mode == TFmode)) | |
4697a36c MM |
2856 | { |
2857 | if (TARGET_DEBUG_ARG) | |
2858 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2859 | ||
2860 | return 1; | |
2861 | } | |
4697a36c MM |
2862 | |
2863 | return 0; | |
2864 | } | |
4697a36c MM |
2865 | \f |
2866 | /* Perform any needed actions needed for a function that is receiving a | |
2867 | variable number of arguments. | |
2868 | ||
2869 | CUM is as above. | |
2870 | ||
2871 | MODE and TYPE are the mode and type of the current parameter. | |
2872 | ||
2873 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2874 | that must be pushed by the prolog to pretend that our caller pushed | |
2875 | it. | |
2876 | ||
2877 | Normally, this macro will push all remaining incoming registers on the | |
2878 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2879 | ||
2880 | void | |
2881 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2882 | CUMULATIVE_ARGS *cum; | |
2883 | enum machine_mode mode; | |
2884 | tree type; | |
2885 | int *pretend_size; | |
2886 | int no_rtl; | |
2887 | ||
2888 | { | |
4cc833b7 RH |
2889 | CUMULATIVE_ARGS next_cum; |
2890 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 2891 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 2892 | int first_reg_offset, set; |
d34c5b80 DE |
2893 | tree fntype; |
2894 | int stdarg_p; | |
4697a36c | 2895 | |
d34c5b80 DE |
2896 | fntype = TREE_TYPE (current_function_decl); |
2897 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2898 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2899 | != void_type_node)); | |
4cc833b7 | 2900 | |
d34c5b80 DE |
2901 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
2902 | For stdargs, we do want to skip the last named argument. */ | |
2903 | next_cum = *cum; | |
2904 | if (stdarg_p) | |
2905 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 2906 | |
f607bc57 | 2907 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 2908 | { |
4cc833b7 RH |
2909 | /* Indicate to allocate space on the stack for varargs save area. */ |
2910 | /* ??? Does this really have to be located at a magic spot on the | |
2911 | stack, or can we allocate this with assign_stack_local instead. */ | |
00dba523 | 2912 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 2913 | if (! no_rtl) |
2c4974b7 | 2914 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2915 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2916 | |
2917 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2918 | } |
60e2d0ca | 2919 | else |
4697a36c | 2920 | { |
d34c5b80 | 2921 | first_reg_offset = next_cum.words; |
4cc833b7 | 2922 | save_area = virtual_incoming_args_rtx; |
00dba523 | 2923 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
2924 | |
2925 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 2926 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 2927 | } |
4697a36c | 2928 | |
dfafc897 | 2929 | set = get_varargs_alias_set (); |
c81fc13e | 2930 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2931 | { |
dfafc897 FS |
2932 | mem = gen_rtx_MEM (BLKmode, |
2933 | plus_constant (save_area, | |
2934 | first_reg_offset * reg_size)), | |
ba4828e0 | 2935 | set_mem_alias_set (mem, set); |
8ac61af7 | 2936 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 2937 | |
4cc833b7 | 2938 | move_block_from_reg |
dfafc897 | 2939 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2940 | GP_ARG_NUM_REG - first_reg_offset, |
2941 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2942 | ||
2943 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2944 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2945 | } | |
2946 | ||
4697a36c | 2947 | /* Save FP registers if needed. */ |
f607bc57 | 2948 | if (DEFAULT_ABI == ABI_V4 |
c81fc13e | 2949 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2950 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2951 | { |
4cc833b7 | 2952 | int fregno = next_cum.fregno; |
9ebbca7d | 2953 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2954 | rtx lab = gen_label_rtx (); |
2955 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2956 | |
4cc833b7 | 2957 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2958 | pc_rtx, |
39403d82 | 2959 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2960 | gen_rtx_NE (VOIDmode, cr1, |
2961 | const0_rtx), | |
39403d82 | 2962 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2963 | pc_rtx))); |
2964 | ||
4cc833b7 RH |
2965 | while (fregno <= FP_ARG_V4_MAX_REG) |
2966 | { | |
dfafc897 | 2967 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 2968 | set_mem_alias_set (mem, set); |
dfafc897 | 2969 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
2970 | fregno++; |
2971 | off += 8; | |
4697a36c | 2972 | } |
4cc833b7 RH |
2973 | |
2974 | emit_label (lab); | |
4697a36c | 2975 | } |
4697a36c | 2976 | } |
4697a36c | 2977 | |
dfafc897 | 2978 | /* Create the va_list data type. */ |
2c4974b7 | 2979 | |
dfafc897 FS |
2980 | tree |
2981 | rs6000_build_va_list () | |
2982 | { | |
bab45a51 | 2983 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2984 | |
9ebbca7d GK |
2985 | /* For AIX, prefer 'char *' because that's what the system |
2986 | header files like. */ | |
f607bc57 | 2987 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 2988 | return build_pointer_type (char_type_node); |
dfafc897 | 2989 | |
0f4fd75d | 2990 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2991 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2992 | |
9ebbca7d GK |
2993 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2994 | unsigned_char_type_node); | |
2995 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2996 | unsigned_char_type_node); | |
dfafc897 FS |
2997 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2998 | ptr_type_node); | |
2999 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
3000 | ptr_type_node); | |
3001 | ||
3002 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
3003 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
3004 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
3005 | DECL_FIELD_CONTEXT (f_sav) = record; | |
3006 | ||
bab45a51 FS |
3007 | TREE_CHAIN (record) = type_decl; |
3008 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
3009 | TYPE_FIELDS (record) = f_gpr; |
3010 | TREE_CHAIN (f_gpr) = f_fpr; | |
3011 | TREE_CHAIN (f_fpr) = f_ovf; | |
3012 | TREE_CHAIN (f_ovf) = f_sav; | |
3013 | ||
3014 | layout_type (record); | |
3015 | ||
3016 | /* The correct type is an array type of one element. */ | |
3017 | return build_array_type (record, build_index_type (size_zero_node)); | |
3018 | } | |
3019 | ||
3020 | /* Implement va_start. */ | |
3021 | ||
3022 | void | |
3023 | rs6000_va_start (stdarg_p, valist, nextarg) | |
3024 | int stdarg_p; | |
3025 | tree valist; | |
3026 | rtx nextarg; | |
4697a36c | 3027 | { |
dfafc897 FS |
3028 | HOST_WIDE_INT words, n_gpr, n_fpr; |
3029 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
3030 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 3031 | |
dfafc897 | 3032 | /* Only SVR4 needs something special. */ |
f607bc57 | 3033 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 FS |
3034 | { |
3035 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
3036 | return; | |
3037 | } | |
3038 | ||
973a648b | 3039 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
3040 | f_fpr = TREE_CHAIN (f_gpr); |
3041 | f_ovf = TREE_CHAIN (f_fpr); | |
3042 | f_sav = TREE_CHAIN (f_ovf); | |
3043 | ||
8ebecc3b | 3044 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
3045 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
3046 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
3047 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
3048 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
3049 | ||
3050 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 3051 | words = current_function_args_info.words; |
dfafc897 FS |
3052 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
3053 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
3054 | ||
3055 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
3056 | { |
3057 | fputs ("va_start: words = ", stderr); | |
3058 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
3059 | fputs (", n_gpr = ", stderr); | |
3060 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
3061 | fputs (", n_fpr = ", stderr); | |
3062 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
3063 | putc ('\n', stderr); | |
3064 | } | |
dfafc897 FS |
3065 | |
3066 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
3067 | TREE_SIDE_EFFECTS (t) = 1; | |
3068 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3069 | ||
3070 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
3071 | TREE_SIDE_EFFECTS (t) = 1; | |
3072 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3073 | ||
3074 | /* Find the overflow area. */ | |
3075 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
3076 | if (words != 0) | |
3077 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
3078 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
3079 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
3080 | TREE_SIDE_EFFECTS (t) = 1; | |
3081 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3082 | ||
3083 | /* Find the register save area. */ | |
3084 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
3085 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
3086 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
3087 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
3088 | TREE_SIDE_EFFECTS (t) = 1; | |
3089 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3090 | } | |
3091 | ||
3092 | /* Implement va_arg. */ | |
3093 | ||
3094 | rtx | |
3095 | rs6000_va_arg (valist, type) | |
3096 | tree valist, type; | |
3097 | { | |
3098 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
3099 | tree gpr, fpr, ovf, sav, reg, t, u; | |
3100 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
3101 | rtx lab_false, lab_over, addr_rtx, r; | |
3102 | ||
9ebbca7d GK |
3103 | /* For AIX, the rule is that structures are passed left-aligned in |
3104 | their stack slot. However, GCC does not presently do this: | |
3105 | structures which are the same size as integer types are passed | |
3106 | right-aligned, as if they were in fact integers. This only | |
3107 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
f607bc57 | 3108 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
3109 | { |
3110 | HOST_WIDE_INT align, rounded_size; | |
3111 | enum machine_mode mode; | |
3112 | tree addr_tree; | |
3113 | ||
3114 | /* Compute the rounded size of the type. */ | |
3115 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
3116 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
3117 | * align); | |
3118 | ||
3119 | addr_tree = valist; | |
3120 | ||
3121 | mode = TYPE_MODE (type); | |
3122 | if (mode != BLKmode) | |
3123 | { | |
3124 | HOST_WIDE_INT adj; | |
3125 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
3126 | if (rounded_size > align) | |
3127 | adj = rounded_size; | |
3128 | ||
3129 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
3130 | build_int_2 (rounded_size - adj, 0)); | |
3131 | } | |
3132 | ||
3133 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
3134 | addr_rtx = copy_to_reg (addr_rtx); | |
3135 | ||
3136 | /* Compute new value for AP. */ | |
3137 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
3138 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
3139 | build_int_2 (rounded_size, 0))); | |
3140 | TREE_SIDE_EFFECTS (t) = 1; | |
3141 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3142 | ||
3143 | return addr_rtx; | |
3144 | } | |
dfafc897 | 3145 | |
973a648b | 3146 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
3147 | f_fpr = TREE_CHAIN (f_gpr); |
3148 | f_ovf = TREE_CHAIN (f_fpr); | |
3149 | f_sav = TREE_CHAIN (f_ovf); | |
3150 | ||
8ebecc3b | 3151 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
3152 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
3153 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
3154 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
3155 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
3156 | ||
3157 | size = int_size_in_bytes (type); | |
3158 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 3159 | |
dfafc897 | 3160 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 3161 | { |
dfafc897 FS |
3162 | /* Aggregates and long doubles are passed by reference. */ |
3163 | indirect_p = 1; | |
3164 | reg = gpr; | |
3165 | n_reg = 1; | |
3166 | sav_ofs = 0; | |
3167 | sav_scale = 4; | |
3168 | size = rsize = UNITS_PER_WORD; | |
3169 | } | |
3170 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
3171 | { | |
3172 | /* FP args go in FP registers, if present. */ | |
3173 | indirect_p = 0; | |
3174 | reg = fpr; | |
3175 | n_reg = 1; | |
3176 | sav_ofs = 8*4; | |
3177 | sav_scale = 8; | |
4cc833b7 | 3178 | } |
dfafc897 FS |
3179 | else |
3180 | { | |
3181 | /* Otherwise into GP registers. */ | |
3182 | indirect_p = 0; | |
3183 | reg = gpr; | |
3184 | n_reg = rsize; | |
3185 | sav_ofs = 0; | |
3186 | sav_scale = 4; | |
3187 | } | |
3188 | ||
a4f6c312 | 3189 | /* Pull the value out of the saved registers ... */ |
dfafc897 FS |
3190 | |
3191 | lab_false = gen_label_rtx (); | |
3192 | lab_over = gen_label_rtx (); | |
3193 | addr_rtx = gen_reg_rtx (Pmode); | |
3194 | ||
41daaf0e AH |
3195 | /* Vectors never go in registers. */ |
3196 | if (TREE_CODE (type) != VECTOR_TYPE) | |
2c4974b7 | 3197 | { |
41daaf0e AH |
3198 | TREE_THIS_VOLATILE (reg) = 1; |
3199 | emit_cmp_and_jump_insns | |
3200 | (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
3201 | GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1, | |
3202 | lab_false); | |
dfafc897 | 3203 | |
41daaf0e AH |
3204 | /* Long long is aligned in the registers. */ |
3205 | if (n_reg > 1) | |
3206 | { | |
3207 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
3208 | build_int_2 (n_reg - 1, 0)); | |
3209 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
3210 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
3211 | TREE_SIDE_EFFECTS (u) = 1; | |
3212 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3213 | } | |
2c4974b7 | 3214 | |
41daaf0e AH |
3215 | if (sav_ofs) |
3216 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
3217 | else | |
3218 | t = sav; | |
2c4974b7 | 3219 | |
41daaf0e AH |
3220 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, |
3221 | build_int_2 (n_reg, 0)); | |
3222 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 3223 | |
41daaf0e AH |
3224 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
3225 | TREE_SIDE_EFFECTS (u) = 1; | |
dfafc897 | 3226 | |
41daaf0e AH |
3227 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
3228 | TREE_SIDE_EFFECTS (u) = 1; | |
dfafc897 | 3229 | |
41daaf0e AH |
3230 | t = build (PLUS_EXPR, ptr_type_node, t, u); |
3231 | TREE_SIDE_EFFECTS (t) = 1; | |
3232 | ||
3233 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
3234 | if (r != addr_rtx) | |
3235 | emit_move_insn (addr_rtx, r); | |
3236 | ||
3237 | emit_jump_insn (gen_jump (lab_over)); | |
3238 | emit_barrier (); | |
3239 | } | |
dfafc897 | 3240 | |
dfafc897 FS |
3241 | emit_label (lab_false); |
3242 | ||
a4f6c312 | 3243 | /* ... otherwise out of the overflow area. */ |
dfafc897 | 3244 | |
41daaf0e AH |
3245 | /* Make sure we don't find reg 7 for the next int arg. |
3246 | ||
3247 | All AltiVec vectors go in the overflow area. So in the AltiVec | |
3248 | case we need to get the vectors from the overflow area, but | |
3249 | remember where the GPRs and FPRs are. */ | |
3250 | if (n_reg > 1 && TREE_CODE (type) != VECTOR_TYPE) | |
dfafc897 FS |
3251 | { |
3252 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
3253 | TREE_SIDE_EFFECTS (t) = 1; | |
3254 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3255 | } | |
3256 | ||
3257 | /* Care for on-stack alignment if needed. */ | |
3258 | if (rsize <= 1) | |
3259 | t = ovf; | |
3260 | else | |
3261 | { | |
41daaf0e AH |
3262 | int align; |
3263 | ||
3264 | /* Vectors are 16 byte aligned. */ | |
3265 | if (TREE_CODE (type) == VECTOR_TYPE) | |
3266 | align = 15; | |
3267 | else | |
3268 | align = 7; | |
3269 | ||
3270 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0)); | |
3271 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1)); | |
dfafc897 FS |
3272 | } |
3273 | t = save_expr (t); | |
3274 | ||
3275 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
3276 | if (r != addr_rtx) | |
3277 | emit_move_insn (addr_rtx, r); | |
3278 | ||
3279 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
3280 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
3281 | TREE_SIDE_EFFECTS (t) = 1; | |
3282 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3283 | ||
3284 | emit_label (lab_over); | |
3285 | ||
3286 | if (indirect_p) | |
3287 | { | |
3288 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 3289 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
3290 | emit_move_insn (addr_rtx, r); |
3291 | } | |
3292 | ||
3293 | return addr_rtx; | |
4697a36c | 3294 | } |
0ac081f6 AH |
3295 | |
3296 | /* Builtins. */ | |
3297 | ||
3298 | #define def_builtin(MASK, NAME, TYPE, CODE) \ | |
3299 | do { \ | |
3300 | if ((MASK) & target_flags) \ | |
3301 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \ | |
3302 | } while (0) | |
3303 | ||
3304 | struct builtin_description | |
3305 | { | |
3306 | const unsigned int mask; | |
3307 | const enum insn_code icode; | |
3308 | const char *const name; | |
3309 | const enum rs6000_builtins code; | |
3310 | }; | |
24408032 AH |
3311 | |
3312 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ | |
3313 | ||
2212663f | 3314 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
3315 | { |
3316 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
3317 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
3318 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
3319 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
3320 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
3321 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
3322 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
3323 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
3324 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
3325 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
3326 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, | |
3327 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, | |
3328 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
3329 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
3330 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
3331 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
3332 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
3333 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
3334 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
3335 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
3336 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
3337 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
3338 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
3339 | }; | |
2212663f | 3340 | |
95385cbb AH |
3341 | /* DST operations: void foo (void *, const int, const char). */ |
3342 | ||
3343 | static const struct builtin_description bdesc_dst[] = | |
3344 | { | |
3345 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
3346 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
3347 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
3348 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
3349 | }; | |
3350 | ||
2212663f | 3351 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 3352 | |
0ac081f6 AH |
3353 | static const struct builtin_description bdesc_2arg[] = |
3354 | { | |
f18c054f DB |
3355 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
3356 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
3357 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
3358 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
3359 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
3360 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
3361 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
3362 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
3363 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
3364 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
3365 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 3366 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
3367 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
3368 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
3369 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
3370 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
3371 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
3372 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
3373 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
3374 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
3375 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
3376 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
3377 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
3378 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
3379 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
3380 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
3381 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
3382 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
3383 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
3384 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
3385 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
3386 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
3387 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
3388 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
3389 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
3390 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
3391 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
3392 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
3393 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, | |
3394 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
3395 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
3396 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
3397 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
3398 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
3399 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
3400 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
3401 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
3402 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
3403 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
3404 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
3405 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
3406 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
3407 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
3408 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
3409 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
3410 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
3411 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
3412 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
3413 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
3414 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
3415 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
3416 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
3417 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
3418 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
3419 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 3420 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
3421 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
3422 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
3423 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
3424 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
3425 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
3426 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
3427 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
3428 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
3429 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
3430 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
3431 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
3432 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
3433 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
3434 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
3435 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
3436 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
3437 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
3438 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
3439 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
3440 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
3441 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
3442 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 3443 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
3444 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
3445 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
3446 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
3447 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
3448 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
3449 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
3450 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
3451 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
3452 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
3453 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
3454 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
3455 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
3456 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
3457 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
3458 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
3459 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
3460 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
3461 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
3462 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
3463 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
3464 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
3465 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
3466 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 3467 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
ae4b4a02 AH |
3468 | }; |
3469 | ||
3470 | /* AltiVec predicates. */ | |
3471 | ||
3472 | struct builtin_description_predicates | |
3473 | { | |
3474 | const unsigned int mask; | |
3475 | const enum insn_code icode; | |
3476 | const char *opcode; | |
3477 | const char *const name; | |
3478 | const enum rs6000_builtins code; | |
3479 | }; | |
3480 | ||
3481 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
3482 | { | |
3483 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
3484 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
3485 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
3486 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
3487 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
3488 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
3489 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
3490 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
3491 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
3492 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
3493 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
3494 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
3495 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 3496 | }; |
24408032 | 3497 | |
100c4561 AH |
3498 | /* ABS* opreations. */ |
3499 | ||
3500 | static const struct builtin_description bdesc_abs[] = | |
3501 | { | |
3502 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
3503 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
3504 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
3505 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
3506 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
3507 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
3508 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
3509 | }; | |
3510 | ||
617e0e1d DB |
3511 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
3512 | foo (VECa). */ | |
24408032 | 3513 | |
2212663f DB |
3514 | static const struct builtin_description bdesc_1arg[] = |
3515 | { | |
617e0e1d DB |
3516 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
3517 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
3518 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
3519 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
3520 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
3521 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
3522 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
3523 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
3524 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
3525 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
3526 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
3527 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
3528 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
3529 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
3530 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
3531 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
3532 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
2212663f DB |
3533 | }; |
3534 | ||
3535 | static rtx | |
3536 | altivec_expand_unop_builtin (icode, arglist, target) | |
3537 | enum insn_code icode; | |
3538 | tree arglist; | |
3539 | rtx target; | |
3540 | { | |
3541 | rtx pat; | |
3542 | tree arg0 = TREE_VALUE (arglist); | |
3543 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3544 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3545 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3546 | ||
20e26713 AH |
3547 | /* If we got invalid arguments bail out before generating bad rtl. */ |
3548 | if (arg0 == error_mark_node) | |
95385cbb | 3549 | return NULL_RTX; |
20e26713 | 3550 | |
c62f2db5 | 3551 | if (target == 0 |
2212663f DB |
3552 | || GET_MODE (target) != tmode |
3553 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3554 | target = gen_reg_rtx (tmode); | |
3555 | ||
3556 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3557 | op0 = copy_to_mode_reg (mode0, op0); | |
3558 | ||
3559 | pat = GEN_FCN (icode) (target, op0); | |
3560 | if (! pat) | |
3561 | return 0; | |
3562 | emit_insn (pat); | |
0ac081f6 | 3563 | |
2212663f DB |
3564 | return target; |
3565 | } | |
ae4b4a02 | 3566 | |
100c4561 AH |
3567 | static rtx |
3568 | altivec_expand_abs_builtin (icode, arglist, target) | |
3569 | enum insn_code icode; | |
3570 | tree arglist; | |
3571 | rtx target; | |
3572 | { | |
3573 | rtx pat, scratch1, scratch2; | |
3574 | tree arg0 = TREE_VALUE (arglist); | |
3575 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3576 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3577 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3578 | ||
3579 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
3580 | if (arg0 == error_mark_node) | |
3581 | return NULL_RTX; | |
3582 | ||
3583 | if (target == 0 | |
3584 | || GET_MODE (target) != tmode | |
3585 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3586 | target = gen_reg_rtx (tmode); | |
3587 | ||
3588 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3589 | op0 = copy_to_mode_reg (mode0, op0); | |
3590 | ||
3591 | scratch1 = gen_reg_rtx (mode0); | |
3592 | scratch2 = gen_reg_rtx (mode0); | |
3593 | ||
3594 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
3595 | if (! pat) | |
3596 | return 0; | |
3597 | emit_insn (pat); | |
3598 | ||
3599 | return target; | |
3600 | } | |
3601 | ||
0ac081f6 AH |
3602 | static rtx |
3603 | altivec_expand_binop_builtin (icode, arglist, target) | |
3604 | enum insn_code icode; | |
3605 | tree arglist; | |
3606 | rtx target; | |
3607 | { | |
3608 | rtx pat; | |
3609 | tree arg0 = TREE_VALUE (arglist); | |
3610 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3611 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3612 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3613 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3614 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3615 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3616 | ||
20e26713 AH |
3617 | /* If we got invalid arguments bail out before generating bad rtl. */ |
3618 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
95385cbb | 3619 | return NULL_RTX; |
20e26713 | 3620 | |
c62f2db5 | 3621 | if (target == 0 |
0ac081f6 AH |
3622 | || GET_MODE (target) != tmode |
3623 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3624 | target = gen_reg_rtx (tmode); | |
3625 | ||
3626 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3627 | op0 = copy_to_mode_reg (mode0, op0); | |
3628 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3629 | op1 = copy_to_mode_reg (mode1, op1); | |
3630 | ||
3631 | pat = GEN_FCN (icode) (target, op0, op1); | |
3632 | if (! pat) | |
3633 | return 0; | |
3634 | emit_insn (pat); | |
3635 | ||
3636 | return target; | |
3637 | } | |
6525c0e7 | 3638 | |
ae4b4a02 AH |
3639 | static rtx |
3640 | altivec_expand_predicate_builtin (icode, opcode, arglist, target) | |
3641 | enum insn_code icode; | |
3642 | const char *opcode; | |
3643 | tree arglist; | |
3644 | rtx target; | |
3645 | { | |
3646 | rtx pat, scratch; | |
3647 | tree cr6_form = TREE_VALUE (arglist); | |
3648 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3649 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
3650 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3651 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3652 | enum machine_mode tmode = SImode; | |
3653 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3654 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3655 | int cr6_form_int; | |
3656 | ||
3657 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
3658 | { | |
3659 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
3660 | return NULL_RTX; | |
3661 | } | |
3662 | else | |
3663 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
3664 | ||
3665 | if (mode0 != mode1) | |
3666 | abort (); | |
3667 | ||
3668 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
3669 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
3670 | return NULL_RTX; | |
3671 | ||
3672 | if (target == 0 | |
3673 | || GET_MODE (target) != tmode | |
3674 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3675 | target = gen_reg_rtx (tmode); | |
3676 | ||
3677 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3678 | op0 = copy_to_mode_reg (mode0, op0); | |
3679 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3680 | op1 = copy_to_mode_reg (mode1, op1); | |
3681 | ||
3682 | scratch = gen_reg_rtx (mode0); | |
3683 | ||
3684 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
3685 | gen_rtx (SYMBOL_REF, Pmode, opcode)); | |
3686 | if (! pat) | |
3687 | return 0; | |
3688 | emit_insn (pat); | |
3689 | ||
3690 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
3691 | different operations, but the bits in CR6 will be different | |
3692 | depending on what information we want. So we have to play tricks | |
3693 | with CR6 to get the right bits out. | |
3694 | ||
3695 | If you think this is disgusting, look at the specs for the | |
3696 | AltiVec predicates. */ | |
3697 | ||
3698 | switch (cr6_form_int) | |
3699 | { | |
3700 | case 0: | |
3701 | emit_insn (gen_cr6_test_for_zero (target)); | |
3702 | break; | |
3703 | case 1: | |
3704 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
3705 | break; | |
3706 | case 2: | |
3707 | emit_insn (gen_cr6_test_for_lt (target)); | |
3708 | break; | |
3709 | case 3: | |
3710 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
3711 | break; | |
3712 | default: | |
3713 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
3714 | break; | |
3715 | } | |
3716 | ||
3717 | return target; | |
3718 | } | |
3719 | ||
6525c0e7 AH |
3720 | static rtx |
3721 | altivec_expand_stv_builtin (icode, arglist) | |
3722 | enum insn_code icode; | |
3723 | tree arglist; | |
3724 | { | |
3725 | tree arg0 = TREE_VALUE (arglist); | |
3726 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3727 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
3728 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3729 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3730 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
3731 | rtx pat; | |
3732 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
3733 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
3734 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
3735 | ||
3736 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
3737 | if (arg0 == error_mark_node | |
3738 | || arg1 == error_mark_node | |
3739 | || arg2 == error_mark_node) | |
3740 | return NULL_RTX; | |
3741 | ||
3742 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
3743 | op0 = copy_to_mode_reg (mode2, op0); | |
3744 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
3745 | op1 = copy_to_mode_reg (mode0, op1); | |
3746 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
3747 | op2 = copy_to_mode_reg (mode1, op2); | |
3748 | ||
3749 | pat = GEN_FCN (icode) (op1, op2, op0); | |
3750 | if (pat) | |
3751 | emit_insn (pat); | |
3752 | return NULL_RTX; | |
3753 | } | |
3754 | ||
2212663f DB |
3755 | static rtx |
3756 | altivec_expand_ternop_builtin (icode, arglist, target) | |
3757 | enum insn_code icode; | |
3758 | tree arglist; | |
3759 | rtx target; | |
3760 | { | |
3761 | rtx pat; | |
3762 | tree arg0 = TREE_VALUE (arglist); | |
3763 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3764 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
3765 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3766 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3767 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
3768 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3769 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3770 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3771 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 3772 | |
20e26713 AH |
3773 | /* If we got invalid arguments bail out before generating bad rtl. */ |
3774 | if (arg0 == error_mark_node | |
3775 | || arg1 == error_mark_node | |
3776 | || arg2 == error_mark_node) | |
95385cbb | 3777 | return NULL_RTX; |
20e26713 | 3778 | |
c62f2db5 | 3779 | if (target == 0 |
2212663f DB |
3780 | || GET_MODE (target) != tmode |
3781 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3782 | target = gen_reg_rtx (tmode); | |
3783 | ||
3784 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3785 | op0 = copy_to_mode_reg (mode0, op0); | |
3786 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3787 | op1 = copy_to_mode_reg (mode1, op1); | |
3788 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
3789 | op2 = copy_to_mode_reg (mode2, op2); | |
3790 | ||
3791 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
3792 | if (! pat) | |
3793 | return 0; | |
3794 | emit_insn (pat); | |
3795 | ||
3796 | return target; | |
3797 | } | |
0ac081f6 | 3798 | static rtx |
00b960c7 | 3799 | altivec_expand_builtin (exp, target) |
0ac081f6 AH |
3800 | tree exp; |
3801 | rtx target; | |
0ac081f6 AH |
3802 | { |
3803 | struct builtin_description *d; | |
ae4b4a02 | 3804 | struct builtin_description_predicates *dp; |
0ac081f6 AH |
3805 | size_t i; |
3806 | enum insn_code icode; | |
3807 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
3808 | tree arglist = TREE_OPERAND (exp, 1); | |
95385cbb AH |
3809 | tree arg0, arg1, arg2; |
3810 | rtx op0, op1, op2, pat; | |
3811 | enum machine_mode tmode, mode0, mode1, mode2; | |
0ac081f6 AH |
3812 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3813 | ||
3814 | switch (fcode) | |
3815 | { | |
f18c054f DB |
3816 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
3817 | icode = CODE_FOR_altivec_lvx_16qi; | |
0ac081f6 AH |
3818 | arg0 = TREE_VALUE (arglist); |
3819 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3820 | tmode = insn_data[icode].operand[0].mode; | |
3821 | mode0 = insn_data[icode].operand[1].mode; | |
3822 | ||
c62f2db5 | 3823 | if (target == 0 |
0ac081f6 AH |
3824 | || GET_MODE (target) != tmode |
3825 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3826 | target = gen_reg_rtx (tmode); | |
3827 | ||
3828 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3829 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3830 | ||
3831 | pat = GEN_FCN (icode) (target, op0); | |
3832 | if (! pat) | |
3833 | return 0; | |
3834 | emit_insn (pat); | |
3835 | return target; | |
24408032 | 3836 | |
f18c054f DB |
3837 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
3838 | icode = CODE_FOR_altivec_lvx_8hi; | |
3839 | arg0 = TREE_VALUE (arglist); | |
3840 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3841 | tmode = insn_data[icode].operand[0].mode; | |
3842 | mode0 = insn_data[icode].operand[1].mode; | |
0ac081f6 | 3843 | |
c62f2db5 | 3844 | if (target == 0 |
f18c054f DB |
3845 | || GET_MODE (target) != tmode |
3846 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3847 | target = gen_reg_rtx (tmode); | |
3848 | ||
3849 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3850 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3851 | ||
3852 | pat = GEN_FCN (icode) (target, op0); | |
3853 | if (! pat) | |
3854 | return 0; | |
3855 | emit_insn (pat); | |
3856 | return target; | |
24408032 | 3857 | |
f18c054f DB |
3858 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: |
3859 | icode = CODE_FOR_altivec_lvx_4si; | |
3860 | arg0 = TREE_VALUE (arglist); | |
3861 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3862 | tmode = insn_data[icode].operand[0].mode; | |
3863 | mode0 = insn_data[icode].operand[1].mode; | |
3864 | ||
c62f2db5 | 3865 | if (target == 0 |
f18c054f DB |
3866 | || GET_MODE (target) != tmode |
3867 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3868 | target = gen_reg_rtx (tmode); | |
3869 | ||
3870 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3871 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3872 | ||
3873 | pat = GEN_FCN (icode) (target, op0); | |
3874 | if (! pat) | |
3875 | return 0; | |
3876 | emit_insn (pat); | |
3877 | return target; | |
24408032 | 3878 | |
f18c054f DB |
3879 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: |
3880 | icode = CODE_FOR_altivec_lvx_4sf; | |
3881 | arg0 = TREE_VALUE (arglist); | |
3882 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3883 | tmode = insn_data[icode].operand[0].mode; | |
3884 | mode0 = insn_data[icode].operand[1].mode; | |
3885 | ||
c62f2db5 | 3886 | if (target == 0 |
f18c054f DB |
3887 | || GET_MODE (target) != tmode |
3888 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3889 | target = gen_reg_rtx (tmode); | |
3890 | ||
3891 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3892 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3893 | ||
3894 | pat = GEN_FCN (icode) (target, op0); | |
3895 | if (! pat) | |
3896 | return 0; | |
3897 | emit_insn (pat); | |
3898 | return target; | |
3899 | ||
3900 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
3901 | icode = CODE_FOR_altivec_stvx_16qi; | |
3902 | arg0 = TREE_VALUE (arglist); | |
3903 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3904 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3905 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3906 | mode0 = insn_data[icode].operand[0].mode; | |
3907 | mode1 = insn_data[icode].operand[1].mode; | |
3908 | ||
3909 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3910 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3911 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3912 | op1 = copy_to_mode_reg (mode1, op1); | |
3913 | ||
3914 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3915 | if (pat) |
3916 | emit_insn (pat); | |
f18c054f | 3917 | return NULL_RTX; |
24408032 | 3918 | |
f18c054f DB |
3919 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: |
3920 | icode = CODE_FOR_altivec_stvx_8hi; | |
3921 | arg0 = TREE_VALUE (arglist); | |
3922 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3923 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3924 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3925 | mode0 = insn_data[icode].operand[0].mode; | |
3926 | mode1 = insn_data[icode].operand[1].mode; | |
3927 | ||
3928 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3929 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3930 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3931 | op1 = copy_to_mode_reg (mode1, op1); | |
3932 | ||
3933 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3934 | if (pat) |
3935 | emit_insn (pat); | |
f18c054f | 3936 | return NULL_RTX; |
24408032 | 3937 | |
f18c054f DB |
3938 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: |
3939 | icode = CODE_FOR_altivec_stvx_4si; | |
3940 | arg0 = TREE_VALUE (arglist); | |
3941 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3942 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3943 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3944 | mode0 = insn_data[icode].operand[0].mode; | |
3945 | mode1 = insn_data[icode].operand[1].mode; | |
3946 | ||
3947 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3948 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3949 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3950 | op1 = copy_to_mode_reg (mode1, op1); | |
3951 | ||
3952 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3953 | if (pat) |
3954 | emit_insn (pat); | |
f18c054f | 3955 | return NULL_RTX; |
24408032 | 3956 | |
f18c054f DB |
3957 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: |
3958 | icode = CODE_FOR_altivec_stvx_4sf; | |
0ac081f6 AH |
3959 | arg0 = TREE_VALUE (arglist); |
3960 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3961 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3962 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3963 | mode0 = insn_data[icode].operand[0].mode; | |
3964 | mode1 = insn_data[icode].operand[1].mode; | |
3965 | ||
3966 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3967 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3968 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3969 | op1 = copy_to_mode_reg (mode1, op1); | |
3970 | ||
3971 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3972 | if (pat) |
3973 | emit_insn (pat); | |
3974 | return NULL_RTX; | |
3975 | ||
6525c0e7 AH |
3976 | case ALTIVEC_BUILTIN_STVX: |
3977 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
3978 | case ALTIVEC_BUILTIN_STVEBX: | |
3979 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
3980 | case ALTIVEC_BUILTIN_STVEHX: | |
3981 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
3982 | case ALTIVEC_BUILTIN_STVEWX: | |
3983 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
3984 | case ALTIVEC_BUILTIN_STVXL: | |
3985 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3986 | ||
95385cbb AH |
3987 | case ALTIVEC_BUILTIN_MFVSCR: |
3988 | icode = CODE_FOR_altivec_mfvscr; | |
3989 | tmode = insn_data[icode].operand[0].mode; | |
3990 | ||
3991 | if (target == 0 | |
3992 | || GET_MODE (target) != tmode | |
3993 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3994 | target = gen_reg_rtx (tmode); | |
3995 | ||
3996 | pat = GEN_FCN (icode) (target); | |
0ac081f6 AH |
3997 | if (! pat) |
3998 | return 0; | |
3999 | emit_insn (pat); | |
95385cbb AH |
4000 | return target; |
4001 | ||
4002 | case ALTIVEC_BUILTIN_MTVSCR: | |
4003 | icode = CODE_FOR_altivec_mtvscr; | |
4004 | arg0 = TREE_VALUE (arglist); | |
4005 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4006 | mode0 = insn_data[icode].operand[0].mode; | |
4007 | ||
4008 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
4009 | if (arg0 == error_mark_node) | |
4010 | return NULL_RTX; | |
4011 | ||
4012 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
4013 | op0 = copy_to_mode_reg (mode0, op0); | |
4014 | ||
4015 | pat = GEN_FCN (icode) (op0); | |
4016 | if (pat) | |
4017 | emit_insn (pat); | |
4018 | return NULL_RTX; | |
4019 | ||
4020 | case ALTIVEC_BUILTIN_DSSALL: | |
4021 | emit_insn (gen_altivec_dssall ()); | |
4022 | return NULL_RTX; | |
4023 | ||
4024 | case ALTIVEC_BUILTIN_DSS: | |
4025 | icode = CODE_FOR_altivec_dss; | |
4026 | arg0 = TREE_VALUE (arglist); | |
4027 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4028 | mode0 = insn_data[icode].operand[0].mode; | |
4029 | ||
4030 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
4031 | if (arg0 == error_mark_node) | |
4032 | return NULL_RTX; | |
4033 | ||
4034 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
4035 | op0 = copy_to_mode_reg (mode0, op0); | |
4036 | ||
4037 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 AH |
4038 | return NULL_RTX; |
4039 | } | |
24408032 | 4040 | |
95385cbb AH |
4041 | /* Handle DST variants. */ |
4042 | d = (struct builtin_description *) bdesc_dst; | |
ca7558fc | 4043 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) |
95385cbb AH |
4044 | if (d->code == fcode) |
4045 | { | |
4046 | arg0 = TREE_VALUE (arglist); | |
4047 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
4048 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
4049 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4050 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
4051 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
4052 | mode0 = insn_data[d->icode].operand[0].mode; | |
4053 | mode1 = insn_data[d->icode].operand[1].mode; | |
4054 | mode2 = insn_data[d->icode].operand[2].mode; | |
4055 | ||
4056 | /* Invalid arguments, bail out before generating bad rtl. */ | |
4057 | if (arg0 == error_mark_node | |
4058 | || arg1 == error_mark_node | |
4059 | || arg2 == error_mark_node) | |
4060 | return NULL_RTX; | |
4061 | ||
4062 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) | |
4063 | op0 = copy_to_mode_reg (mode0, op0); | |
4064 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) | |
4065 | op1 = copy_to_mode_reg (mode1, op1); | |
4066 | ||
4067 | if (GET_CODE (op2) != CONST_INT || INTVAL (op2) > 3) | |
4068 | { | |
4069 | error ("argument 3 of `%s' must be a 2-bit literal", d->name); | |
4070 | return NULL_RTX; | |
4071 | } | |
4072 | ||
4073 | pat = GEN_FCN (d->icode) (op0, op1, op2); | |
4074 | if (pat != 0) | |
4075 | emit_insn (pat); | |
4076 | ||
4077 | return NULL_RTX; | |
4078 | } | |
4079 | ||
100c4561 AH |
4080 | /* Expand abs* operations. */ |
4081 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 4082 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
4083 | if (d->code == fcode) |
4084 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
4085 | ||
2212663f DB |
4086 | /* Handle simple unary operations. */ |
4087 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 4088 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
4089 | if (d->code == fcode) |
4090 | return altivec_expand_unop_builtin (d->icode, arglist, target); | |
0ac081f6 AH |
4091 | |
4092 | /* Handle simple binary operations. */ | |
00b960c7 | 4093 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 4094 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
4095 | if (d->code == fcode) |
4096 | return altivec_expand_binop_builtin (d->icode, arglist, target); | |
4097 | ||
ae4b4a02 AH |
4098 | /* Expand the AltiVec predicates. */ |
4099 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 4100 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 AH |
4101 | if (dp->code == fcode) |
4102 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target); | |
4103 | ||
6525c0e7 AH |
4104 | /* LV* are funky. We initialized them differently. */ |
4105 | switch (fcode) | |
4106 | { | |
4107 | case ALTIVEC_BUILTIN_LVSL: | |
4108 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsl, | |
4109 | arglist, target); | |
4110 | case ALTIVEC_BUILTIN_LVSR: | |
4111 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsr, | |
4112 | arglist, target); | |
4113 | case ALTIVEC_BUILTIN_LVEBX: | |
4114 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvebx, | |
4115 | arglist, target); | |
4116 | case ALTIVEC_BUILTIN_LVEHX: | |
4117 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvehx, | |
4118 | arglist, target); | |
4119 | case ALTIVEC_BUILTIN_LVEWX: | |
4120 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvewx, | |
4121 | arglist, target); | |
4122 | case ALTIVEC_BUILTIN_LVXL: | |
4123 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvxl, | |
4124 | arglist, target); | |
4125 | case ALTIVEC_BUILTIN_LVX: | |
4126 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvx, | |
4127 | arglist, target); | |
4128 | default: | |
4129 | break; | |
4130 | /* Fall through. */ | |
4131 | } | |
95385cbb | 4132 | |
2212663f DB |
4133 | /* Handle simple ternary operations. */ |
4134 | d = (struct builtin_description *) bdesc_3arg; | |
ca7558fc | 4135 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f DB |
4136 | if (d->code == fcode) |
4137 | return altivec_expand_ternop_builtin (d->icode, arglist, target); | |
4138 | ||
0ac081f6 AH |
4139 | abort (); |
4140 | return NULL_RTX; | |
4141 | } | |
4142 | ||
4143 | /* Expand an expression EXP that calls a built-in function, | |
4144 | with result going to TARGET if that's convenient | |
4145 | (and in mode MODE if that's convenient). | |
4146 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
4147 | IGNORE is nonzero if the value is to be ignored. */ | |
4148 | ||
4149 | static rtx | |
4150 | rs6000_expand_builtin (exp, target, subtarget, mode, ignore) | |
4151 | tree exp; | |
4152 | rtx target; | |
00b960c7 AH |
4153 | rtx subtarget ATTRIBUTE_UNUSED; |
4154 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4155 | int ignore ATTRIBUTE_UNUSED; | |
0ac081f6 AH |
4156 | { |
4157 | if (TARGET_ALTIVEC) | |
00b960c7 | 4158 | return altivec_expand_builtin (exp, target); |
0ac081f6 AH |
4159 | |
4160 | abort (); | |
4161 | } | |
4162 | ||
4163 | static void | |
6fa3f289 | 4164 | rs6000_init_builtins () |
0ac081f6 AH |
4165 | { |
4166 | if (TARGET_ALTIVEC) | |
4167 | altivec_init_builtins (); | |
4168 | } | |
4169 | ||
4170 | static void | |
4171 | altivec_init_builtins (void) | |
4172 | { | |
ae4b4a02 AH |
4173 | struct builtin_description *d; |
4174 | struct builtin_description_predicates *dp; | |
0ac081f6 AH |
4175 | size_t i; |
4176 | ||
4177 | tree endlink = void_list_node; | |
4178 | ||
4179 | tree pint_type_node = build_pointer_type (integer_type_node); | |
95385cbb | 4180 | tree pvoid_type_node = build_pointer_type (void_type_node); |
f18c054f DB |
4181 | tree pshort_type_node = build_pointer_type (short_integer_type_node); |
4182 | tree pchar_type_node = build_pointer_type (char_type_node); | |
4183 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
20e26713 | 4184 | |
2212663f DB |
4185 | tree v4sf_ftype_v4sf_v4sf_v16qi |
4186 | = build_function_type (V4SF_type_node, | |
4187 | tree_cons (NULL_TREE, V4SF_type_node, | |
4188 | tree_cons (NULL_TREE, V4SF_type_node, | |
4189 | tree_cons (NULL_TREE, | |
4190 | V16QI_type_node, | |
4191 | endlink)))); | |
4192 | tree v4si_ftype_v4si_v4si_v16qi | |
4193 | = build_function_type (V4SI_type_node, | |
4194 | tree_cons (NULL_TREE, V4SI_type_node, | |
4195 | tree_cons (NULL_TREE, V4SI_type_node, | |
4196 | tree_cons (NULL_TREE, | |
4197 | V16QI_type_node, | |
4198 | endlink)))); | |
4199 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
4200 | = build_function_type (V8HI_type_node, | |
4201 | tree_cons (NULL_TREE, V8HI_type_node, | |
4202 | tree_cons (NULL_TREE, V8HI_type_node, | |
4203 | tree_cons (NULL_TREE, | |
4204 | V16QI_type_node, | |
4205 | endlink)))); | |
4206 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
4207 | = build_function_type (V16QI_type_node, | |
4208 | tree_cons (NULL_TREE, V16QI_type_node, | |
4209 | tree_cons (NULL_TREE, V16QI_type_node, | |
4210 | tree_cons (NULL_TREE, | |
4211 | V16QI_type_node, | |
4212 | endlink)))); | |
4213 | ||
24408032 | 4214 | /* V4SI foo (char). */ |
2212663f DB |
4215 | tree v4si_ftype_char |
4216 | = build_function_type (V4SI_type_node, | |
4217 | tree_cons (NULL_TREE, char_type_node, endlink)); | |
4218 | ||
24408032 | 4219 | /* V8HI foo (char). */ |
2212663f DB |
4220 | tree v8hi_ftype_char |
4221 | = build_function_type (V8HI_type_node, | |
4222 | tree_cons (NULL_TREE, char_type_node, endlink)); | |
4223 | ||
24408032 | 4224 | /* V16QI foo (char). */ |
2212663f DB |
4225 | tree v16qi_ftype_char |
4226 | = build_function_type (V16QI_type_node, | |
4227 | tree_cons (NULL_TREE, char_type_node, endlink)); | |
24408032 | 4228 | /* V4SF foo (V4SF). */ |
617e0e1d DB |
4229 | tree v4sf_ftype_v4sf |
4230 | = build_function_type (V4SF_type_node, | |
4231 | tree_cons (NULL_TREE, V4SF_type_node, endlink)); | |
0ac081f6 AH |
4232 | |
4233 | /* V4SI foo (int *). */ | |
4234 | tree v4si_ftype_pint | |
4235 | = build_function_type (V4SI_type_node, | |
4236 | tree_cons (NULL_TREE, pint_type_node, endlink)); | |
f18c054f DB |
4237 | /* V8HI foo (short *). */ |
4238 | tree v8hi_ftype_pshort | |
4239 | = build_function_type (V8HI_type_node, | |
4240 | tree_cons (NULL_TREE, pshort_type_node, endlink)); | |
4241 | /* V16QI foo (char *). */ | |
4242 | tree v16qi_ftype_pchar | |
4243 | = build_function_type (V16QI_type_node, | |
4244 | tree_cons (NULL_TREE, pchar_type_node, endlink)); | |
4245 | /* V4SF foo (float *). */ | |
4246 | tree v4sf_ftype_pfloat | |
4247 | = build_function_type (V4SF_type_node, | |
4248 | tree_cons (NULL_TREE, pfloat_type_node, endlink)); | |
0ac081f6 | 4249 | |
20e26713 AH |
4250 | /* V8HI foo (V16QI). */ |
4251 | tree v8hi_ftype_v16qi | |
4252 | = build_function_type (V8HI_type_node, | |
4253 | tree_cons (NULL_TREE, V16QI_type_node, endlink)); | |
4254 | ||
95385cbb AH |
4255 | /* void foo (void *, int, char/literal). */ |
4256 | tree void_ftype_pvoid_int_char | |
4257 | = build_function_type (void_type_node, | |
4258 | tree_cons (NULL_TREE, pvoid_type_node, | |
4259 | tree_cons (NULL_TREE, integer_type_node, | |
4260 | tree_cons (NULL_TREE, | |
4261 | char_type_node, | |
4262 | endlink)))); | |
4263 | ||
0ac081f6 AH |
4264 | /* void foo (int *, V4SI). */ |
4265 | tree void_ftype_pint_v4si | |
4266 | = build_function_type (void_type_node, | |
4267 | tree_cons (NULL_TREE, pint_type_node, | |
4268 | tree_cons (NULL_TREE, V4SI_type_node, | |
4269 | endlink))); | |
f18c054f DB |
4270 | /* void foo (short *, V8HI). */ |
4271 | tree void_ftype_pshort_v8hi | |
4272 | = build_function_type (void_type_node, | |
4273 | tree_cons (NULL_TREE, pshort_type_node, | |
4274 | tree_cons (NULL_TREE, V8HI_type_node, | |
4275 | endlink))); | |
4276 | /* void foo (char *, V16QI). */ | |
4277 | tree void_ftype_pchar_v16qi | |
4278 | = build_function_type (void_type_node, | |
4279 | tree_cons (NULL_TREE, pchar_type_node, | |
4280 | tree_cons (NULL_TREE, V16QI_type_node, | |
4281 | endlink))); | |
4282 | /* void foo (float *, V4SF). */ | |
4283 | tree void_ftype_pfloat_v4sf | |
4284 | = build_function_type (void_type_node, | |
4285 | tree_cons (NULL_TREE, pfloat_type_node, | |
4286 | tree_cons (NULL_TREE, V4SF_type_node, | |
4287 | endlink))); | |
0ac081f6 | 4288 | |
95385cbb AH |
4289 | /* void foo (V4SI). */ |
4290 | tree void_ftype_v4si | |
4291 | = build_function_type (void_type_node, | |
4292 | tree_cons (NULL_TREE, V4SI_type_node, | |
4293 | endlink)); | |
4294 | ||
6525c0e7 AH |
4295 | /* void foo (vint, int, void *). */ |
4296 | tree void_ftype_v4si_int_pvoid | |
4297 | = build_function_type (void_type_node, | |
4298 | tree_cons (NULL_TREE, V4SI_type_node, | |
4299 | tree_cons (NULL_TREE, integer_type_node, | |
4300 | tree_cons (NULL_TREE, | |
4301 | pvoid_type_node, | |
4302 | endlink)))); | |
4303 | ||
4304 | /* void foo (vchar, int, void *). */ | |
4305 | tree void_ftype_v16qi_int_pvoid | |
4306 | = build_function_type (void_type_node, | |
4307 | tree_cons (NULL_TREE, V16QI_type_node, | |
4308 | tree_cons (NULL_TREE, integer_type_node, | |
4309 | tree_cons (NULL_TREE, | |
4310 | pvoid_type_node, | |
4311 | endlink)))); | |
4312 | ||
4313 | /* void foo (vshort, int, void *). */ | |
4314 | tree void_ftype_v8hi_int_pvoid | |
4315 | = build_function_type (void_type_node, | |
4316 | tree_cons (NULL_TREE, V8HI_type_node, | |
4317 | tree_cons (NULL_TREE, integer_type_node, | |
4318 | tree_cons (NULL_TREE, | |
4319 | pvoid_type_node, | |
4320 | endlink)))); | |
4321 | ||
95385cbb AH |
4322 | /* void foo (char). */ |
4323 | tree void_ftype_qi | |
4324 | = build_function_type (void_type_node, | |
4325 | tree_cons (NULL_TREE, char_type_node, | |
4326 | endlink)); | |
4327 | ||
4328 | /* void foo (void). */ | |
4329 | tree void_ftype_void | |
3deb2758 | 4330 | = build_function_type (void_type_node, void_list_node); |
95385cbb AH |
4331 | |
4332 | /* vshort foo (void). */ | |
4333 | tree v8hi_ftype_void | |
3deb2758 | 4334 | = build_function_type (V8HI_type_node, void_list_node); |
95385cbb | 4335 | |
0ac081f6 AH |
4336 | tree v4si_ftype_v4si_v4si |
4337 | = build_function_type (V4SI_type_node, | |
4338 | tree_cons (NULL_TREE, V4SI_type_node, | |
4339 | tree_cons (NULL_TREE, V4SI_type_node, | |
4340 | endlink))); | |
24408032 AH |
4341 | |
4342 | /* These are for the unsigned 5 bit literals. */ | |
4343 | ||
617e0e1d DB |
4344 | tree v4sf_ftype_v4si_char |
4345 | = build_function_type (V4SF_type_node, | |
4346 | tree_cons (NULL_TREE, V4SI_type_node, | |
4347 | tree_cons (NULL_TREE, char_type_node, | |
4348 | endlink))); | |
4349 | tree v4si_ftype_v4sf_char | |
4350 | = build_function_type (V4SI_type_node, | |
4351 | tree_cons (NULL_TREE, V4SF_type_node, | |
4352 | tree_cons (NULL_TREE, char_type_node, | |
4353 | endlink))); | |
2212663f DB |
4354 | tree v4si_ftype_v4si_char |
4355 | = build_function_type (V4SI_type_node, | |
4356 | tree_cons (NULL_TREE, V4SI_type_node, | |
4357 | tree_cons (NULL_TREE, char_type_node, | |
4358 | endlink))); | |
4359 | tree v8hi_ftype_v8hi_char | |
4360 | = build_function_type (V8HI_type_node, | |
4361 | tree_cons (NULL_TREE, V8HI_type_node, | |
4362 | tree_cons (NULL_TREE, char_type_node, | |
4363 | endlink))); | |
4364 | tree v16qi_ftype_v16qi_char | |
4365 | = build_function_type (V16QI_type_node, | |
4366 | tree_cons (NULL_TREE, V16QI_type_node, | |
4367 | tree_cons (NULL_TREE, char_type_node, | |
4368 | endlink))); | |
0ac081f6 | 4369 | |
24408032 AH |
4370 | /* These are for the unsigned 4 bit literals. */ |
4371 | ||
4372 | tree v16qi_ftype_v16qi_v16qi_char | |
4373 | = build_function_type (V16QI_type_node, | |
4374 | tree_cons (NULL_TREE, V16QI_type_node, | |
4375 | tree_cons (NULL_TREE, V16QI_type_node, | |
4376 | tree_cons (NULL_TREE, | |
4377 | char_type_node, | |
4378 | endlink)))); | |
4379 | ||
4380 | tree v8hi_ftype_v8hi_v8hi_char | |
4381 | = build_function_type (V8HI_type_node, | |
4382 | tree_cons (NULL_TREE, V8HI_type_node, | |
4383 | tree_cons (NULL_TREE, V8HI_type_node, | |
4384 | tree_cons (NULL_TREE, | |
4385 | char_type_node, | |
4386 | endlink)))); | |
4387 | ||
4388 | tree v4si_ftype_v4si_v4si_char | |
4389 | = build_function_type (V4SI_type_node, | |
4390 | tree_cons (NULL_TREE, V4SI_type_node, | |
4391 | tree_cons (NULL_TREE, V4SI_type_node, | |
4392 | tree_cons (NULL_TREE, | |
4393 | char_type_node, | |
4394 | endlink)))); | |
4395 | ||
4396 | tree v4sf_ftype_v4sf_v4sf_char | |
4397 | = build_function_type (V4SF_type_node, | |
4398 | tree_cons (NULL_TREE, V4SF_type_node, | |
4399 | tree_cons (NULL_TREE, V4SF_type_node, | |
4400 | tree_cons (NULL_TREE, | |
4401 | char_type_node, | |
4402 | endlink)))); | |
4403 | ||
4404 | /* End of 4 bit literals. */ | |
4405 | ||
0ac081f6 AH |
4406 | tree v4sf_ftype_v4sf_v4sf |
4407 | = build_function_type (V4SF_type_node, | |
4408 | tree_cons (NULL_TREE, V4SF_type_node, | |
4409 | tree_cons (NULL_TREE, V4SF_type_node, | |
4410 | endlink))); | |
617e0e1d DB |
4411 | tree v4sf_ftype_v4sf_v4sf_v4si |
4412 | = build_function_type (V4SF_type_node, | |
4413 | tree_cons (NULL_TREE, V4SF_type_node, | |
4414 | tree_cons (NULL_TREE, V4SF_type_node, | |
4415 | tree_cons (NULL_TREE, | |
4416 | V4SI_type_node, | |
4417 | endlink)))); | |
2212663f DB |
4418 | tree v4sf_ftype_v4sf_v4sf_v4sf |
4419 | = build_function_type (V4SF_type_node, | |
4420 | tree_cons (NULL_TREE, V4SF_type_node, | |
4421 | tree_cons (NULL_TREE, V4SF_type_node, | |
4422 | tree_cons (NULL_TREE, | |
4423 | V4SF_type_node, | |
4424 | endlink)))); | |
617e0e1d DB |
4425 | tree v4si_ftype_v4si_v4si_v4si |
4426 | = build_function_type (V4SI_type_node, | |
4427 | tree_cons (NULL_TREE, V4SI_type_node, | |
4428 | tree_cons (NULL_TREE, V4SI_type_node, | |
4429 | tree_cons (NULL_TREE, | |
4430 | V4SI_type_node, | |
4431 | endlink)))); | |
2212663f | 4432 | |
0ac081f6 AH |
4433 | tree v8hi_ftype_v8hi_v8hi |
4434 | = build_function_type (V8HI_type_node, | |
4435 | tree_cons (NULL_TREE, V8HI_type_node, | |
4436 | tree_cons (NULL_TREE, V8HI_type_node, | |
4437 | endlink))); | |
2212663f DB |
4438 | tree v8hi_ftype_v8hi_v8hi_v8hi |
4439 | = build_function_type (V8HI_type_node, | |
4440 | tree_cons (NULL_TREE, V8HI_type_node, | |
4441 | tree_cons (NULL_TREE, V8HI_type_node, | |
4442 | tree_cons (NULL_TREE, | |
4443 | V8HI_type_node, | |
4444 | endlink)))); | |
4445 | tree v4si_ftype_v8hi_v8hi_v4si | |
4446 | = build_function_type (V4SI_type_node, | |
4447 | tree_cons (NULL_TREE, V8HI_type_node, | |
4448 | tree_cons (NULL_TREE, V8HI_type_node, | |
4449 | tree_cons (NULL_TREE, | |
4450 | V4SI_type_node, | |
4451 | endlink)))); | |
4452 | tree v4si_ftype_v16qi_v16qi_v4si | |
4453 | = build_function_type (V4SI_type_node, | |
4454 | tree_cons (NULL_TREE, V16QI_type_node, | |
4455 | tree_cons (NULL_TREE, V16QI_type_node, | |
4456 | tree_cons (NULL_TREE, | |
4457 | V4SI_type_node, | |
4458 | endlink)))); | |
4459 | ||
0ac081f6 AH |
4460 | tree v16qi_ftype_v16qi_v16qi |
4461 | = build_function_type (V16QI_type_node, | |
4462 | tree_cons (NULL_TREE, V16QI_type_node, | |
4463 | tree_cons (NULL_TREE, V16QI_type_node, | |
4464 | endlink))); | |
2212663f | 4465 | |
0ac081f6 AH |
4466 | tree v4si_ftype_v4sf_v4sf |
4467 | = build_function_type (V4SI_type_node, | |
4468 | tree_cons (NULL_TREE, V4SF_type_node, | |
4469 | tree_cons (NULL_TREE, V4SF_type_node, | |
4470 | endlink))); | |
4471 | ||
100c4561 AH |
4472 | tree v4si_ftype_v4si |
4473 | = build_function_type (V4SI_type_node, | |
4474 | tree_cons (NULL_TREE, V4SI_type_node, endlink)); | |
4475 | ||
4476 | tree v8hi_ftype_v8hi | |
4477 | = build_function_type (V8HI_type_node, | |
4478 | tree_cons (NULL_TREE, V8HI_type_node, endlink)); | |
4479 | ||
4480 | tree v16qi_ftype_v16qi | |
4481 | = build_function_type (V16QI_type_node, | |
4482 | tree_cons (NULL_TREE, V16QI_type_node, endlink)); | |
4483 | ||
0ac081f6 AH |
4484 | tree v8hi_ftype_v16qi_v16qi |
4485 | = build_function_type (V8HI_type_node, | |
4486 | tree_cons (NULL_TREE, V16QI_type_node, | |
4487 | tree_cons (NULL_TREE, V16QI_type_node, | |
4488 | endlink))); | |
4489 | ||
4490 | tree v4si_ftype_v8hi_v8hi | |
4491 | = build_function_type (V4SI_type_node, | |
4492 | tree_cons (NULL_TREE, V8HI_type_node, | |
4493 | tree_cons (NULL_TREE, V8HI_type_node, | |
4494 | endlink))); | |
4495 | ||
4496 | tree v8hi_ftype_v4si_v4si | |
4497 | = build_function_type (V8HI_type_node, | |
4498 | tree_cons (NULL_TREE, V4SI_type_node, | |
4499 | tree_cons (NULL_TREE, V4SI_type_node, | |
4500 | endlink))); | |
4501 | ||
4502 | tree v16qi_ftype_v8hi_v8hi | |
4503 | = build_function_type (V16QI_type_node, | |
4504 | tree_cons (NULL_TREE, V8HI_type_node, | |
4505 | tree_cons (NULL_TREE, V8HI_type_node, | |
4506 | endlink))); | |
4507 | ||
4508 | tree v4si_ftype_v16qi_v4si | |
4509 | = build_function_type (V4SI_type_node, | |
4510 | tree_cons (NULL_TREE, V16QI_type_node, | |
4511 | tree_cons (NULL_TREE, V4SI_type_node, | |
4512 | endlink))); | |
4513 | ||
fa066a23 AH |
4514 | tree v4si_ftype_v16qi_v16qi |
4515 | = build_function_type (V4SI_type_node, | |
4516 | tree_cons (NULL_TREE, V16QI_type_node, | |
4517 | tree_cons (NULL_TREE, V16QI_type_node, | |
4518 | endlink))); | |
4519 | ||
0ac081f6 AH |
4520 | tree v4si_ftype_v8hi_v4si |
4521 | = build_function_type (V4SI_type_node, | |
4522 | tree_cons (NULL_TREE, V8HI_type_node, | |
4523 | tree_cons (NULL_TREE, V4SI_type_node, | |
4524 | endlink))); | |
4525 | ||
20e26713 AH |
4526 | tree v4si_ftype_v8hi |
4527 | = build_function_type (V4SI_type_node, | |
4528 | tree_cons (NULL_TREE, V8HI_type_node, endlink)); | |
4529 | ||
0ac081f6 AH |
4530 | tree int_ftype_v4si_v4si |
4531 | = build_function_type (integer_type_node, | |
4532 | tree_cons (NULL_TREE, V4SI_type_node, | |
4533 | tree_cons (NULL_TREE, V4SI_type_node, | |
4534 | endlink))); | |
4535 | ||
4536 | tree int_ftype_v4sf_v4sf | |
4537 | = build_function_type (integer_type_node, | |
4538 | tree_cons (NULL_TREE, V4SF_type_node, | |
4539 | tree_cons (NULL_TREE, V4SF_type_node, | |
4540 | endlink))); | |
4541 | ||
4542 | tree int_ftype_v16qi_v16qi | |
4543 | = build_function_type (integer_type_node, | |
4544 | tree_cons (NULL_TREE, V16QI_type_node, | |
4545 | tree_cons (NULL_TREE, V16QI_type_node, | |
4546 | endlink))); | |
4547 | ||
ae4b4a02 AH |
4548 | tree int_ftype_int_v4si_v4si |
4549 | = build_function_type | |
4550 | (integer_type_node, | |
4551 | tree_cons (NULL_TREE, integer_type_node, | |
4552 | tree_cons (NULL_TREE, V4SI_type_node, | |
4553 | tree_cons (NULL_TREE, V4SI_type_node, | |
4554 | endlink)))); | |
4555 | ||
4556 | tree int_ftype_int_v4sf_v4sf | |
4557 | = build_function_type | |
4558 | (integer_type_node, | |
4559 | tree_cons (NULL_TREE, integer_type_node, | |
4560 | tree_cons (NULL_TREE, V4SF_type_node, | |
4561 | tree_cons (NULL_TREE, V4SF_type_node, | |
4562 | endlink)))); | |
4563 | ||
4564 | tree int_ftype_int_v8hi_v8hi | |
4565 | = build_function_type | |
4566 | (integer_type_node, | |
4567 | tree_cons (NULL_TREE, integer_type_node, | |
4568 | tree_cons (NULL_TREE, V8HI_type_node, | |
4569 | tree_cons (NULL_TREE, V8HI_type_node, | |
4570 | endlink)))); | |
4571 | ||
4572 | tree int_ftype_int_v16qi_v16qi | |
4573 | = build_function_type | |
4574 | (integer_type_node, | |
4575 | tree_cons (NULL_TREE, integer_type_node, | |
4576 | tree_cons (NULL_TREE, V16QI_type_node, | |
4577 | tree_cons (NULL_TREE, V16QI_type_node, | |
4578 | endlink)))); | |
4579 | ||
95385cbb AH |
4580 | tree v16qi_ftype_int_pvoid |
4581 | = build_function_type (V16QI_type_node, | |
4582 | tree_cons (NULL_TREE, integer_type_node, | |
4583 | tree_cons (NULL_TREE, pvoid_type_node, | |
4584 | endlink))); | |
4585 | ||
6525c0e7 AH |
4586 | tree v4si_ftype_int_pvoid |
4587 | = build_function_type (V4SI_type_node, | |
4588 | tree_cons (NULL_TREE, integer_type_node, | |
4589 | tree_cons (NULL_TREE, pvoid_type_node, | |
4590 | endlink))); | |
4591 | ||
4592 | tree v8hi_ftype_int_pvoid | |
4593 | = build_function_type (V8HI_type_node, | |
4594 | tree_cons (NULL_TREE, integer_type_node, | |
4595 | tree_cons (NULL_TREE, pvoid_type_node, | |
4596 | endlink))); | |
4597 | ||
0ac081f6 AH |
4598 | tree int_ftype_v8hi_v8hi |
4599 | = build_function_type (integer_type_node, | |
4600 | tree_cons (NULL_TREE, V8HI_type_node, | |
4601 | tree_cons (NULL_TREE, V8HI_type_node, | |
4602 | endlink))); | |
4603 | ||
f18c054f DB |
4604 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pfloat, ALTIVEC_BUILTIN_LD_INTERNAL_4sf); |
4605 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
4606 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pint, ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
4607 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
4608 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pshort, ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
4609 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
4610 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pchar, ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
4611 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
95385cbb AH |
4612 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
4613 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
4614 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
4615 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); | |
4616 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSL); | |
4617 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSR); | |
6525c0e7 AH |
4618 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEBX); |
4619 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEHX); | |
4620 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEWX); | |
4621 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVXL); | |
4622 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVX); | |
4623 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVX); | |
4624 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_int_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
4625 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_int_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
4626 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
4627 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVXL); | |
100c4561 | 4628 | |
6f317ef3 | 4629 | /* Add the simple ternary operators. */ |
2212663f | 4630 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 4631 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f DB |
4632 | { |
4633 | ||
4634 | enum machine_mode mode0, mode1, mode2, mode3; | |
4635 | tree type; | |
4636 | ||
4637 | if (d->name == 0) | |
4638 | continue; | |
4639 | ||
4640 | mode0 = insn_data[d->icode].operand[0].mode; | |
4641 | mode1 = insn_data[d->icode].operand[1].mode; | |
4642 | mode2 = insn_data[d->icode].operand[2].mode; | |
4643 | mode3 = insn_data[d->icode].operand[3].mode; | |
4644 | ||
4645 | /* When all four are of the same mode. */ | |
4646 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
4647 | { | |
4648 | switch (mode0) | |
4649 | { | |
617e0e1d DB |
4650 | case V4SImode: |
4651 | type = v4si_ftype_v4si_v4si_v4si; | |
4652 | break; | |
2212663f DB |
4653 | case V4SFmode: |
4654 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
4655 | break; | |
4656 | case V8HImode: | |
4657 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
4658 | break; | |
4659 | case V16QImode: | |
4660 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
4661 | break; | |
4662 | default: | |
4663 | abort(); | |
4664 | } | |
4665 | } | |
4666 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
4667 | { | |
4668 | switch (mode0) | |
4669 | { | |
4670 | case V4SImode: | |
4671 | type = v4si_ftype_v4si_v4si_v16qi; | |
4672 | break; | |
4673 | case V4SFmode: | |
4674 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
4675 | break; | |
4676 | case V8HImode: | |
4677 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
4678 | break; | |
4679 | case V16QImode: | |
4680 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
4681 | break; | |
4682 | default: | |
4683 | abort(); | |
4684 | } | |
4685 | } | |
4686 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode | |
4687 | && mode3 == V4SImode) | |
24408032 | 4688 | type = v4si_ftype_v16qi_v16qi_v4si; |
2212663f DB |
4689 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
4690 | && mode3 == V4SImode) | |
24408032 | 4691 | type = v4si_ftype_v8hi_v8hi_v4si; |
617e0e1d DB |
4692 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
4693 | && mode3 == V4SImode) | |
24408032 AH |
4694 | type = v4sf_ftype_v4sf_v4sf_v4si; |
4695 | ||
4696 | /* vchar, vchar, vchar, 4 bit literal. */ | |
4697 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
4698 | && mode3 == QImode) | |
4699 | type = v16qi_ftype_v16qi_v16qi_char; | |
4700 | ||
4701 | /* vshort, vshort, vshort, 4 bit literal. */ | |
4702 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
4703 | && mode3 == QImode) | |
4704 | type = v8hi_ftype_v8hi_v8hi_char; | |
4705 | ||
4706 | /* vint, vint, vint, 4 bit literal. */ | |
4707 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
4708 | && mode3 == QImode) | |
4709 | type = v4si_ftype_v4si_v4si_char; | |
4710 | ||
4711 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
4712 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
4713 | && mode3 == QImode) | |
4714 | type = v4sf_ftype_v4sf_v4sf_char; | |
4715 | ||
2212663f DB |
4716 | else |
4717 | abort (); | |
4718 | ||
4719 | def_builtin (d->mask, d->name, type, d->code); | |
4720 | } | |
4721 | ||
95385cbb AH |
4722 | /* Add the DST variants. */ |
4723 | d = (struct builtin_description *) bdesc_dst; | |
ca7558fc | 4724 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) |
95385cbb AH |
4725 | def_builtin (d->mask, d->name, void_ftype_pvoid_int_char, d->code); |
4726 | ||
ae4b4a02 AH |
4727 | /* Initialize the predicates. */ |
4728 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 4729 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 AH |
4730 | { |
4731 | enum machine_mode mode1; | |
4732 | tree type; | |
4733 | ||
4734 | mode1 = insn_data[dp->icode].operand[1].mode; | |
4735 | ||
4736 | switch (mode1) | |
4737 | { | |
4738 | case V4SImode: | |
4739 | type = int_ftype_int_v4si_v4si; | |
4740 | break; | |
4741 | case V8HImode: | |
4742 | type = int_ftype_int_v8hi_v8hi; | |
4743 | break; | |
4744 | case V16QImode: | |
4745 | type = int_ftype_int_v16qi_v16qi; | |
4746 | break; | |
4747 | case V4SFmode: | |
4748 | type = int_ftype_int_v4sf_v4sf; | |
4749 | break; | |
4750 | default: | |
4751 | abort (); | |
4752 | } | |
4753 | ||
4754 | def_builtin (dp->mask, dp->name, type, dp->code); | |
4755 | } | |
4756 | ||
0ac081f6 | 4757 | /* Add the simple binary operators. */ |
00b960c7 | 4758 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 4759 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
4760 | { |
4761 | enum machine_mode mode0, mode1, mode2; | |
4762 | tree type; | |
4763 | ||
4764 | if (d->name == 0) | |
4765 | continue; | |
4766 | ||
4767 | mode0 = insn_data[d->icode].operand[0].mode; | |
4768 | mode1 = insn_data[d->icode].operand[1].mode; | |
4769 | mode2 = insn_data[d->icode].operand[2].mode; | |
4770 | ||
4771 | /* When all three operands are of the same mode. */ | |
4772 | if (mode0 == mode1 && mode1 == mode2) | |
4773 | { | |
4774 | switch (mode0) | |
4775 | { | |
4776 | case V4SFmode: | |
4777 | type = v4sf_ftype_v4sf_v4sf; | |
4778 | break; | |
4779 | case V4SImode: | |
4780 | type = v4si_ftype_v4si_v4si; | |
4781 | break; | |
4782 | case V16QImode: | |
4783 | type = v16qi_ftype_v16qi_v16qi; | |
4784 | break; | |
4785 | case V8HImode: | |
4786 | type = v8hi_ftype_v8hi_v8hi; | |
4787 | break; | |
4788 | default: | |
4789 | abort (); | |
4790 | } | |
4791 | } | |
4792 | ||
4793 | /* A few other combos we really don't want to do manually. */ | |
4794 | ||
4795 | /* vint, vfloat, vfloat. */ | |
4796 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
4797 | type = v4si_ftype_v4sf_v4sf; | |
4798 | ||
4799 | /* vshort, vchar, vchar. */ | |
4800 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
4801 | type = v8hi_ftype_v16qi_v16qi; | |
4802 | ||
4803 | /* vint, vshort, vshort. */ | |
4804 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
4805 | type = v4si_ftype_v8hi_v8hi; | |
4806 | ||
4807 | /* vshort, vint, vint. */ | |
4808 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
4809 | type = v8hi_ftype_v4si_v4si; | |
4810 | ||
4811 | /* vchar, vshort, vshort. */ | |
4812 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
4813 | type = v16qi_ftype_v8hi_v8hi; | |
4814 | ||
4815 | /* vint, vchar, vint. */ | |
4816 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
4817 | type = v4si_ftype_v16qi_v4si; | |
4818 | ||
fa066a23 AH |
4819 | /* vint, vchar, vchar. */ |
4820 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
4821 | type = v4si_ftype_v16qi_v16qi; | |
4822 | ||
0ac081f6 AH |
4823 | /* vint, vshort, vint. */ |
4824 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
4825 | type = v4si_ftype_v8hi_v4si; | |
2212663f DB |
4826 | |
4827 | /* vint, vint, 5 bit literal. */ | |
4828 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
4829 | type = v4si_ftype_v4si_char; | |
4830 | ||
4831 | /* vshort, vshort, 5 bit literal. */ | |
4832 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
4833 | type = v8hi_ftype_v8hi_char; | |
4834 | ||
4835 | /* vchar, vchar, 5 bit literal. */ | |
4836 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
4837 | type = v16qi_ftype_v16qi_char; | |
0ac081f6 | 4838 | |
617e0e1d DB |
4839 | /* vfloat, vint, 5 bit literal. */ |
4840 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
4841 | type = v4sf_ftype_v4si_char; | |
4842 | ||
4843 | /* vint, vfloat, 5 bit literal. */ | |
4844 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
4845 | type = v4si_ftype_v4sf_char; | |
4846 | ||
0ac081f6 AH |
4847 | /* int, x, x. */ |
4848 | else if (mode0 == SImode) | |
4849 | { | |
4850 | switch (mode1) | |
4851 | { | |
4852 | case V4SImode: | |
4853 | type = int_ftype_v4si_v4si; | |
4854 | break; | |
4855 | case V4SFmode: | |
4856 | type = int_ftype_v4sf_v4sf; | |
4857 | break; | |
4858 | case V16QImode: | |
4859 | type = int_ftype_v16qi_v16qi; | |
4860 | break; | |
4861 | case V8HImode: | |
4862 | type = int_ftype_v8hi_v8hi; | |
4863 | break; | |
4864 | default: | |
4865 | abort (); | |
4866 | } | |
4867 | } | |
4868 | ||
4869 | else | |
4870 | abort (); | |
4871 | ||
2212663f DB |
4872 | def_builtin (d->mask, d->name, type, d->code); |
4873 | } | |
24408032 | 4874 | |
100c4561 AH |
4875 | /* Initialize the abs* operators. */ |
4876 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 4877 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
4878 | { |
4879 | enum machine_mode mode0; | |
4880 | tree type; | |
4881 | ||
4882 | mode0 = insn_data[d->icode].operand[0].mode; | |
4883 | ||
4884 | switch (mode0) | |
4885 | { | |
4886 | case V4SImode: | |
4887 | type = v4si_ftype_v4si; | |
4888 | break; | |
4889 | case V8HImode: | |
4890 | type = v8hi_ftype_v8hi; | |
4891 | break; | |
4892 | case V16QImode: | |
4893 | type = v16qi_ftype_v16qi; | |
4894 | break; | |
4895 | case V4SFmode: | |
4896 | type = v4sf_ftype_v4sf; | |
4897 | break; | |
4898 | default: | |
4899 | abort (); | |
4900 | } | |
4901 | ||
4902 | def_builtin (d->mask, d->name, type, d->code); | |
4903 | } | |
4904 | ||
2212663f DB |
4905 | /* Add the simple unary operators. */ |
4906 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 4907 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
4908 | { |
4909 | enum machine_mode mode0, mode1; | |
4910 | tree type; | |
4911 | ||
4912 | if (d->name == 0) | |
4913 | continue; | |
4914 | ||
4915 | mode0 = insn_data[d->icode].operand[0].mode; | |
4916 | mode1 = insn_data[d->icode].operand[1].mode; | |
4917 | ||
4918 | if (mode0 == V4SImode && mode1 == QImode) | |
4919 | type = v4si_ftype_char; | |
4920 | else if (mode0 == V8HImode && mode1 == QImode) | |
4921 | type = v8hi_ftype_char; | |
4922 | else if (mode0 == V16QImode && mode1 == QImode) | |
4923 | type = v16qi_ftype_char; | |
617e0e1d DB |
4924 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
4925 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
4926 | else if (mode0 == V8HImode && mode1 == V16QImode) |
4927 | type = v8hi_ftype_v16qi; | |
4928 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
4929 | type = v4si_ftype_v8hi; | |
2212663f DB |
4930 | else |
4931 | abort (); | |
4932 | ||
0ac081f6 AH |
4933 | def_builtin (d->mask, d->name, type, d->code); |
4934 | } | |
4935 | } | |
4936 | ||
5b5040b9 RK |
4937 | \f |
4938 | /* Generate a memory reference for expand_block_move, copying volatile, | |
4939 | and other bits from an original memory reference. */ | |
4940 | ||
4941 | static rtx | |
4942 | expand_block_move_mem (mode, addr, orig_mem) | |
4943 | enum machine_mode mode; | |
4944 | rtx addr; | |
4945 | rtx orig_mem; | |
4946 | { | |
39403d82 | 4947 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 4948 | |
c6df88cb | 4949 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
5b5040b9 RK |
4950 | return mem; |
4951 | } | |
4952 | ||
7e69e155 MM |
4953 | /* Expand a block move operation, and return 1 if successful. Return 0 |
4954 | if we should let the compiler generate normal code. | |
4955 | ||
4956 | operands[0] is the destination | |
4957 | operands[1] is the source | |
4958 | operands[2] is the length | |
4959 | operands[3] is the alignment */ | |
4960 | ||
3933e0e1 MM |
4961 | #define MAX_MOVE_REG 4 |
4962 | ||
7e69e155 MM |
4963 | int |
4964 | expand_block_move (operands) | |
4965 | rtx operands[]; | |
4966 | { | |
b6c9286a MM |
4967 | rtx orig_dest = operands[0]; |
4968 | rtx orig_src = operands[1]; | |
7e69e155 | 4969 | rtx bytes_rtx = operands[2]; |
7e69e155 | 4970 | rtx align_rtx = operands[3]; |
3933e0e1 | 4971 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 4972 | int align; |
3933e0e1 MM |
4973 | int bytes; |
4974 | int offset; | |
4975 | int num_reg; | |
4976 | int i; | |
7e69e155 MM |
4977 | rtx src_reg; |
4978 | rtx dest_reg; | |
3933e0e1 MM |
4979 | rtx src_addr; |
4980 | rtx dest_addr; | |
7e69e155 | 4981 | rtx tmp_reg; |
3933e0e1 | 4982 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
4983 | int move_bytes; |
4984 | ||
3933e0e1 | 4985 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 4986 | if (! constp) |
3933e0e1 MM |
4987 | return 0; |
4988 | ||
5ee95df6 FS |
4989 | /* If this is not a fixed size alignment, abort */ |
4990 | if (GET_CODE (align_rtx) != CONST_INT) | |
4991 | abort (); | |
4992 | align = INTVAL (align_rtx); | |
4993 | ||
7e69e155 | 4994 | /* Anything to move? */ |
3933e0e1 MM |
4995 | bytes = INTVAL (bytes_rtx); |
4996 | if (bytes <= 0) | |
7e69e155 MM |
4997 | return 1; |
4998 | ||
ea9982a8 | 4999 | /* store_one_arg depends on expand_block_move to handle at least the size of |
6f317ef3 | 5000 | reg_parm_stack_space. */ |
ea9982a8 | 5001 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
5002 | return 0; |
5003 | ||
5004 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
5005 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
5006 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 5007 | |
3933e0e1 | 5008 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 5009 | { |
3933e0e1 | 5010 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 5011 | { |
3933e0e1 | 5012 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
5013 | && ! fixed_regs[5] |
5014 | && ! fixed_regs[6] | |
5015 | && ! fixed_regs[7] | |
5016 | && ! fixed_regs[8] | |
5017 | && ! fixed_regs[9] | |
5018 | && ! fixed_regs[10] | |
5019 | && ! fixed_regs[11] | |
5020 | && ! fixed_regs[12]) | |
3933e0e1 MM |
5021 | { |
5022 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
5023 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
5024 | dest_reg, | |
5025 | orig_dest), | |
5026 | expand_block_move_mem (BLKmode, | |
5027 | src_reg, | |
5028 | orig_src), | |
5029 | GEN_INT ((move_bytes == 32) | |
5030 | ? 0 : move_bytes), | |
4c64a852 | 5031 | align_rtx)); |
3933e0e1 MM |
5032 | } |
5033 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
5034 | && ! fixed_regs[5] |
5035 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
5036 | && ! fixed_regs[7] |
5037 | && ! fixed_regs[8] | |
5038 | && ! fixed_regs[9] | |
f9562f27 | 5039 | && ! fixed_regs[10]) |
3933e0e1 MM |
5040 | { |
5041 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
5042 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
5043 | dest_reg, | |
5044 | orig_dest), | |
5045 | expand_block_move_mem (BLKmode, | |
5046 | src_reg, | |
5047 | orig_src), | |
3933e0e1 | 5048 | GEN_INT (move_bytes), |
4c64a852 | 5049 | align_rtx)); |
3933e0e1 MM |
5050 | } |
5051 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
5052 | && ! fixed_regs[5] |
5053 | && ! fixed_regs[6] | |
5054 | && ! fixed_regs[7] | |
5055 | && ! fixed_regs[8]) | |
3933e0e1 MM |
5056 | { |
5057 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
5058 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
5059 | dest_reg, | |
5060 | orig_dest), | |
5061 | expand_block_move_mem (BLKmode, | |
5062 | src_reg, | |
5063 | orig_src), | |
3933e0e1 | 5064 | GEN_INT (move_bytes), |
4c64a852 | 5065 | align_rtx)); |
3933e0e1 | 5066 | } |
acad7ed3 | 5067 | else if (bytes >= 8 && TARGET_POWERPC64 |
a4f6c312 | 5068 | /* 64-bit loads and stores require word-aligned |
82e41834 | 5069 | displacements. */ |
a4f6c312 | 5070 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
acad7ed3 DE |
5071 | { |
5072 | move_bytes = 8; | |
5073 | tmp_reg = gen_reg_rtx (DImode); | |
5074 | emit_move_insn (tmp_reg, | |
5075 | expand_block_move_mem (DImode, | |
2eba1afa | 5076 | src_reg, orig_src)); |
acad7ed3 | 5077 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 5078 | dest_reg, orig_dest), |
acad7ed3 DE |
5079 | tmp_reg); |
5080 | } | |
09a625f7 | 5081 | else if (bytes > 4 && !TARGET_POWERPC64) |
3933e0e1 MM |
5082 | { /* move up to 8 bytes at a time */ |
5083 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
5084 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
5085 | dest_reg, | |
5086 | orig_dest), | |
5087 | expand_block_move_mem (BLKmode, | |
5088 | src_reg, | |
5089 | orig_src), | |
3933e0e1 | 5090 | GEN_INT (move_bytes), |
4c64a852 | 5091 | align_rtx)); |
3933e0e1 | 5092 | } |
cc0d9ba8 | 5093 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
5094 | { /* move 4 bytes */ |
5095 | move_bytes = 4; | |
5096 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
5097 | emit_move_insn (tmp_reg, |
5098 | expand_block_move_mem (SImode, | |
5099 | src_reg, orig_src)); | |
5100 | emit_move_insn (expand_block_move_mem (SImode, | |
5101 | dest_reg, orig_dest), | |
5102 | tmp_reg); | |
3933e0e1 | 5103 | } |
cc0d9ba8 | 5104 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
5105 | { /* move 2 bytes */ |
5106 | move_bytes = 2; | |
5107 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
5108 | emit_move_insn (tmp_reg, |
5109 | expand_block_move_mem (HImode, | |
5110 | src_reg, orig_src)); | |
5111 | emit_move_insn (expand_block_move_mem (HImode, | |
5112 | dest_reg, orig_dest), | |
5113 | tmp_reg); | |
3933e0e1 MM |
5114 | } |
5115 | else if (bytes == 1) /* move 1 byte */ | |
5116 | { | |
5117 | move_bytes = 1; | |
5118 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
5119 | emit_move_insn (tmp_reg, |
5120 | expand_block_move_mem (QImode, | |
5121 | src_reg, orig_src)); | |
5122 | emit_move_insn (expand_block_move_mem (QImode, | |
5123 | dest_reg, orig_dest), | |
5124 | tmp_reg); | |
3933e0e1 MM |
5125 | } |
5126 | else | |
5127 | { /* move up to 4 bytes at a time */ | |
5128 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
5129 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
5130 | dest_reg, | |
5131 | orig_dest), | |
5132 | expand_block_move_mem (BLKmode, | |
5133 | src_reg, | |
5134 | orig_src), | |
3933e0e1 | 5135 | GEN_INT (move_bytes), |
4c64a852 | 5136 | align_rtx)); |
3933e0e1 | 5137 | } |
4c64a852 | 5138 | |
015892ee RK |
5139 | if (bytes > move_bytes) |
5140 | { | |
cc0d9ba8 DE |
5141 | if (! TARGET_POWERPC64) |
5142 | { | |
5143 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
5144 | GEN_INT (move_bytes))); | |
5145 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
5146 | GEN_INT (move_bytes))); | |
5147 | } | |
5148 | else | |
5149 | { | |
5150 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
5151 | GEN_INT (move_bytes))); | |
5152 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
5153 | GEN_INT (move_bytes))); | |
5154 | } | |
015892ee | 5155 | } |
4c64a852 | 5156 | } |
3933e0e1 MM |
5157 | } |
5158 | ||
5159 | else /* string instructions not available */ | |
5160 | { | |
5161 | num_reg = offset = 0; | |
5162 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 5163 | { |
3933e0e1 MM |
5164 | /* Calculate the correct offset for src/dest */ |
5165 | if (offset == 0) | |
7e69e155 | 5166 | { |
3933e0e1 MM |
5167 | src_addr = src_reg; |
5168 | dest_addr = dest_reg; | |
5169 | } | |
5170 | else | |
5171 | { | |
c5c76735 JL |
5172 | src_addr = plus_constant (src_reg, offset); |
5173 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
5174 | } |
5175 | ||
cc0d9ba8 DE |
5176 | /* Generate the appropriate load and store, saving the stores |
5177 | for later. */ | |
5178 | if (bytes >= 8 && TARGET_POWERPC64 | |
a4f6c312 SS |
5179 | /* 64-bit loads and stores require word-aligned |
5180 | displacements. */ | |
cc0d9ba8 | 5181 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
b6c9286a MM |
5182 | { |
5183 | move_bytes = 8; | |
5184 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
5185 | emit_insn (gen_movdi (tmp_reg, |
5186 | expand_block_move_mem (DImode, | |
5187 | src_addr, | |
5188 | orig_src))); | |
5189 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
5190 | dest_addr, | |
5191 | orig_dest), | |
5192 | tmp_reg); | |
b6c9286a | 5193 | } |
cc0d9ba8 | 5194 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
5195 | { |
5196 | move_bytes = 4; | |
5197 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
5198 | emit_insn (gen_movsi (tmp_reg, |
5199 | expand_block_move_mem (SImode, | |
5200 | src_addr, | |
5201 | orig_src))); | |
5202 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
5203 | dest_addr, | |
5204 | orig_dest), | |
5205 | tmp_reg); | |
3933e0e1 | 5206 | } |
cc0d9ba8 | 5207 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
5208 | { |
5209 | move_bytes = 2; | |
5210 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 5211 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
5212 | expand_block_move_mem (HImode, |
5213 | src_addr, | |
5214 | orig_src))); | |
5215 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
5216 | dest_addr, | |
5217 | orig_dest), | |
5218 | tmp_reg); | |
3933e0e1 MM |
5219 | } |
5220 | else | |
5221 | { | |
5222 | move_bytes = 1; | |
5223 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 5224 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
5225 | expand_block_move_mem (QImode, |
5226 | src_addr, | |
5227 | orig_src))); | |
5228 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
5229 | dest_addr, | |
5230 | orig_dest), | |
a4f6c312 | 5231 | tmp_reg); |
3933e0e1 MM |
5232 | } |
5233 | ||
5234 | if (num_reg >= MAX_MOVE_REG) | |
5235 | { | |
5236 | for (i = 0; i < num_reg; i++) | |
5237 | emit_insn (stores[i]); | |
5238 | num_reg = 0; | |
7e69e155 MM |
5239 | } |
5240 | } | |
3933e0e1 | 5241 | |
b6c9286a MM |
5242 | for (i = 0; i < num_reg; i++) |
5243 | emit_insn (stores[i]); | |
7e69e155 MM |
5244 | } |
5245 | ||
5246 | return 1; | |
5247 | } | |
5248 | ||
9878760c RK |
5249 | \f |
5250 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
5251 | PARALLEL and the first section will be tested. */ | |
5252 | ||
5253 | int | |
5254 | load_multiple_operation (op, mode) | |
5255 | rtx op; | |
296b8152 | 5256 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
5257 | { |
5258 | int count = XVECLEN (op, 0); | |
e2c953b6 | 5259 | unsigned int dest_regno; |
9878760c RK |
5260 | rtx src_addr; |
5261 | int i; | |
5262 | ||
5263 | /* Perform a quick check so we don't blow up below. */ | |
5264 | if (count <= 1 | |
5265 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5266 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
5267 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
5268 | return 0; | |
5269 | ||
5270 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
5271 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
5272 | ||
5273 | for (i = 1; i < count; i++) | |
5274 | { | |
5275 | rtx elt = XVECEXP (op, 0, i); | |
5276 | ||
5277 | if (GET_CODE (elt) != SET | |
5278 | || GET_CODE (SET_DEST (elt)) != REG | |
5279 | || GET_MODE (SET_DEST (elt)) != SImode | |
5280 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
5281 | || GET_CODE (SET_SRC (elt)) != MEM | |
5282 | || GET_MODE (SET_SRC (elt)) != SImode | |
5283 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
5284 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
5285 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
5286 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
5287 | return 0; | |
5288 | } | |
5289 | ||
5290 | return 1; | |
5291 | } | |
5292 | ||
5293 | /* Similar, but tests for store multiple. Here, the second vector element | |
5294 | is a CLOBBER. It will be tested later. */ | |
5295 | ||
5296 | int | |
5297 | store_multiple_operation (op, mode) | |
5298 | rtx op; | |
296b8152 | 5299 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
5300 | { |
5301 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 5302 | unsigned int src_regno; |
9878760c RK |
5303 | rtx dest_addr; |
5304 | int i; | |
5305 | ||
5306 | /* Perform a quick check so we don't blow up below. */ | |
5307 | if (count <= 1 | |
5308 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5309 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
5310 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
5311 | return 0; | |
5312 | ||
5313 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
5314 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
5315 | ||
5316 | for (i = 1; i < count; i++) | |
5317 | { | |
5318 | rtx elt = XVECEXP (op, 0, i + 1); | |
5319 | ||
5320 | if (GET_CODE (elt) != SET | |
5321 | || GET_CODE (SET_SRC (elt)) != REG | |
5322 | || GET_MODE (SET_SRC (elt)) != SImode | |
5323 | || REGNO (SET_SRC (elt)) != src_regno + i | |
5324 | || GET_CODE (SET_DEST (elt)) != MEM | |
5325 | || GET_MODE (SET_DEST (elt)) != SImode | |
5326 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
5327 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
5328 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
5329 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
5330 | return 0; | |
5331 | } | |
5332 | ||
5333 | return 1; | |
5334 | } | |
9ebbca7d | 5335 | |
00b960c7 AH |
5336 | /* Return 1 for a parallel vrsave operation. */ |
5337 | ||
5338 | int | |
5339 | vrsave_operation (op, mode) | |
5340 | rtx op; | |
5341 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5342 | { | |
5343 | int count = XVECLEN (op, 0); | |
5344 | unsigned int dest_regno, src_regno; | |
5345 | int i; | |
5346 | ||
5347 | if (count <= 1 | |
5348 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5349 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 5350 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
5351 | return 0; |
5352 | ||
5353 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
5354 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
5355 | ||
5356 | if (dest_regno != VRSAVE_REGNO | |
5357 | && src_regno != VRSAVE_REGNO) | |
5358 | return 0; | |
5359 | ||
5360 | for (i = 1; i < count; i++) | |
5361 | { | |
5362 | rtx elt = XVECEXP (op, 0, i); | |
5363 | ||
9aa86737 AH |
5364 | if (GET_CODE (elt) != CLOBBER |
5365 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
5366 | return 0; |
5367 | } | |
5368 | ||
5369 | return 1; | |
5370 | } | |
5371 | ||
a4f6c312 | 5372 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
5373 | |
5374 | int | |
5375 | mtcrf_operation (op, mode) | |
5376 | rtx op; | |
5377 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5378 | { | |
5379 | int count = XVECLEN (op, 0); | |
5380 | int i; | |
9ebbca7d GK |
5381 | rtx src_reg; |
5382 | ||
5383 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
5384 | if (count < 1 |
5385 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5386 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
5387 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 5388 | return 0; |
e35b9579 | 5389 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
5390 | |
5391 | if (GET_CODE (src_reg) != REG | |
5392 | || GET_MODE (src_reg) != SImode | |
5393 | || ! INT_REGNO_P (REGNO (src_reg))) | |
5394 | return 0; | |
5395 | ||
e35b9579 | 5396 | for (i = 0; i < count; i++) |
9ebbca7d GK |
5397 | { |
5398 | rtx exp = XVECEXP (op, 0, i); | |
5399 | rtx unspec; | |
5400 | int maskval; | |
5401 | ||
5402 | if (GET_CODE (exp) != SET | |
5403 | || GET_CODE (SET_DEST (exp)) != REG | |
5404 | || GET_MODE (SET_DEST (exp)) != CCmode | |
5405 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
5406 | return 0; | |
5407 | unspec = SET_SRC (exp); | |
5408 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
5409 | |
5410 | if (GET_CODE (unspec) != UNSPEC | |
5411 | || XINT (unspec, 1) != 20 | |
5412 | || XVECLEN (unspec, 0) != 2 | |
5413 | || XVECEXP (unspec, 0, 0) != src_reg | |
5414 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
5415 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
5416 | return 0; | |
5417 | } | |
e35b9579 | 5418 | return 1; |
9ebbca7d GK |
5419 | } |
5420 | ||
a4f6c312 | 5421 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
5422 | |
5423 | int | |
5424 | lmw_operation (op, mode) | |
5425 | rtx op; | |
5426 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5427 | { | |
5428 | int count = XVECLEN (op, 0); | |
e2c953b6 | 5429 | unsigned int dest_regno; |
9ebbca7d | 5430 | rtx src_addr; |
e2c953b6 | 5431 | unsigned int base_regno; |
9ebbca7d GK |
5432 | HOST_WIDE_INT offset; |
5433 | int i; | |
5434 | ||
5435 | /* Perform a quick check so we don't blow up below. */ | |
5436 | if (count <= 1 | |
5437 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5438 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
5439 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
5440 | return 0; | |
5441 | ||
5442 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
5443 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
5444 | ||
5445 | if (dest_regno > 31 | |
e2c953b6 | 5446 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
5447 | return 0; |
5448 | ||
258bfae2 | 5449 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
5450 | { |
5451 | offset = 0; | |
5452 | base_regno = REGNO (src_addr); | |
5453 | if (base_regno == 0) | |
5454 | return 0; | |
5455 | } | |
258bfae2 | 5456 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
5457 | { |
5458 | offset = INTVAL (XEXP (src_addr, 1)); | |
5459 | base_regno = REGNO (XEXP (src_addr, 0)); | |
5460 | } | |
5461 | else | |
5462 | return 0; | |
5463 | ||
5464 | for (i = 0; i < count; i++) | |
5465 | { | |
5466 | rtx elt = XVECEXP (op, 0, i); | |
5467 | rtx newaddr; | |
5468 | rtx addr_reg; | |
5469 | HOST_WIDE_INT newoffset; | |
5470 | ||
5471 | if (GET_CODE (elt) != SET | |
5472 | || GET_CODE (SET_DEST (elt)) != REG | |
5473 | || GET_MODE (SET_DEST (elt)) != SImode | |
5474 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
5475 | || GET_CODE (SET_SRC (elt)) != MEM | |
5476 | || GET_MODE (SET_SRC (elt)) != SImode) | |
5477 | return 0; | |
5478 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 5479 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
5480 | { |
5481 | newoffset = 0; | |
5482 | addr_reg = newaddr; | |
5483 | } | |
258bfae2 | 5484 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
5485 | { |
5486 | addr_reg = XEXP (newaddr, 0); | |
5487 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
5488 | } | |
5489 | else | |
5490 | return 0; | |
5491 | if (REGNO (addr_reg) != base_regno | |
5492 | || newoffset != offset + 4 * i) | |
5493 | return 0; | |
5494 | } | |
5495 | ||
5496 | return 1; | |
5497 | } | |
5498 | ||
a4f6c312 | 5499 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
5500 | |
5501 | int | |
5502 | stmw_operation (op, mode) | |
5503 | rtx op; | |
5504 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5505 | { | |
5506 | int count = XVECLEN (op, 0); | |
e2c953b6 | 5507 | unsigned int src_regno; |
9ebbca7d | 5508 | rtx dest_addr; |
e2c953b6 | 5509 | unsigned int base_regno; |
9ebbca7d GK |
5510 | HOST_WIDE_INT offset; |
5511 | int i; | |
5512 | ||
5513 | /* Perform a quick check so we don't blow up below. */ | |
5514 | if (count <= 1 | |
5515 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5516 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
5517 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
5518 | return 0; | |
5519 | ||
5520 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
5521 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
5522 | ||
5523 | if (src_regno > 31 | |
e2c953b6 | 5524 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
5525 | return 0; |
5526 | ||
258bfae2 | 5527 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
5528 | { |
5529 | offset = 0; | |
5530 | base_regno = REGNO (dest_addr); | |
5531 | if (base_regno == 0) | |
5532 | return 0; | |
5533 | } | |
258bfae2 | 5534 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
5535 | { |
5536 | offset = INTVAL (XEXP (dest_addr, 1)); | |
5537 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
5538 | } | |
5539 | else | |
5540 | return 0; | |
5541 | ||
5542 | for (i = 0; i < count; i++) | |
5543 | { | |
5544 | rtx elt = XVECEXP (op, 0, i); | |
5545 | rtx newaddr; | |
5546 | rtx addr_reg; | |
5547 | HOST_WIDE_INT newoffset; | |
5548 | ||
5549 | if (GET_CODE (elt) != SET | |
5550 | || GET_CODE (SET_SRC (elt)) != REG | |
5551 | || GET_MODE (SET_SRC (elt)) != SImode | |
5552 | || REGNO (SET_SRC (elt)) != src_regno + i | |
5553 | || GET_CODE (SET_DEST (elt)) != MEM | |
5554 | || GET_MODE (SET_DEST (elt)) != SImode) | |
5555 | return 0; | |
5556 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 5557 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
5558 | { |
5559 | newoffset = 0; | |
5560 | addr_reg = newaddr; | |
5561 | } | |
258bfae2 | 5562 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
5563 | { |
5564 | addr_reg = XEXP (newaddr, 0); | |
5565 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
5566 | } | |
5567 | else | |
5568 | return 0; | |
5569 | if (REGNO (addr_reg) != base_regno | |
5570 | || newoffset != offset + 4 * i) | |
5571 | return 0; | |
5572 | } | |
5573 | ||
5574 | return 1; | |
5575 | } | |
9878760c | 5576 | \f |
a4f6c312 SS |
5577 | /* A validation routine: say whether CODE, a condition code, and MODE |
5578 | match. The other alternatives either don't make sense or should | |
5579 | never be generated. */ | |
39a10a29 | 5580 | |
39a10a29 GK |
5581 | static void |
5582 | validate_condition_mode (code, mode) | |
5583 | enum rtx_code code; | |
5584 | enum machine_mode mode; | |
5585 | { | |
5586 | if (GET_RTX_CLASS (code) != '<' | |
5587 | || GET_MODE_CLASS (mode) != MODE_CC) | |
5588 | abort (); | |
5589 | ||
5590 | /* These don't make sense. */ | |
5591 | if ((code == GT || code == LT || code == GE || code == LE) | |
5592 | && mode == CCUNSmode) | |
5593 | abort (); | |
5594 | ||
5595 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
5596 | && mode != CCUNSmode) | |
5597 | abort (); | |
5598 | ||
5599 | if (mode != CCFPmode | |
5600 | && (code == ORDERED || code == UNORDERED | |
5601 | || code == UNEQ || code == LTGT | |
5602 | || code == UNGT || code == UNLT | |
5603 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 5604 | abort (); |
39a10a29 | 5605 | |
de6c5979 BL |
5606 | /* These should never be generated except for |
5607 | flag_unsafe_math_optimizations. */ | |
39a10a29 | 5608 | if (mode == CCFPmode |
de6c5979 | 5609 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
5610 | && (code == LE || code == GE |
5611 | || code == UNEQ || code == LTGT | |
5612 | || code == UNGT || code == UNLT)) | |
5613 | abort (); | |
5614 | ||
5615 | /* These are invalid; the information is not there. */ | |
5616 | if (mode == CCEQmode | |
5617 | && code != EQ && code != NE) | |
5618 | abort (); | |
5619 | } | |
5620 | ||
9878760c RK |
5621 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
5622 | We only check the opcode against the mode of the CC value here. */ | |
5623 | ||
5624 | int | |
5625 | branch_comparison_operator (op, mode) | |
592696dd | 5626 | rtx op; |
296b8152 | 5627 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
5628 | { |
5629 | enum rtx_code code = GET_CODE (op); | |
5630 | enum machine_mode cc_mode; | |
5631 | ||
5632 | if (GET_RTX_CLASS (code) != '<') | |
5633 | return 0; | |
5634 | ||
5635 | cc_mode = GET_MODE (XEXP (op, 0)); | |
5636 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
5637 | return 0; | |
5638 | ||
39a10a29 | 5639 | validate_condition_mode (code, cc_mode); |
9878760c | 5640 | |
39a10a29 GK |
5641 | return 1; |
5642 | } | |
5643 | ||
5644 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
5645 | insn and which is true if the corresponding bit in the CC register | |
5646 | is set. */ | |
5647 | ||
5648 | int | |
5649 | branch_positive_comparison_operator (op, mode) | |
592696dd | 5650 | rtx op; |
39a10a29 GK |
5651 | enum machine_mode mode; |
5652 | { | |
5653 | enum rtx_code code; | |
5654 | ||
5655 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
5656 | return 0; |
5657 | ||
39a10a29 GK |
5658 | code = GET_CODE (op); |
5659 | return (code == EQ || code == LT || code == GT | |
5660 | || code == LTU || code == GTU | |
5661 | || code == UNORDERED); | |
9878760c RK |
5662 | } |
5663 | ||
5664 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
5665 | We check the opcode against the mode of the CC value and disallow EQ or | |
5666 | NE comparisons for integers. */ | |
5667 | ||
5668 | int | |
5669 | scc_comparison_operator (op, mode) | |
592696dd | 5670 | rtx op; |
9878760c RK |
5671 | enum machine_mode mode; |
5672 | { | |
5673 | enum rtx_code code = GET_CODE (op); | |
5674 | enum machine_mode cc_mode; | |
5675 | ||
5676 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
5677 | return 0; | |
5678 | ||
5679 | if (GET_RTX_CLASS (code) != '<') | |
5680 | return 0; | |
5681 | ||
5682 | cc_mode = GET_MODE (XEXP (op, 0)); | |
5683 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
5684 | return 0; | |
5685 | ||
39a10a29 | 5686 | validate_condition_mode (code, cc_mode); |
9878760c | 5687 | |
39a10a29 | 5688 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
5689 | return 0; |
5690 | ||
9878760c RK |
5691 | return 1; |
5692 | } | |
e0cd0770 JC |
5693 | |
5694 | int | |
5695 | trap_comparison_operator (op, mode) | |
5696 | rtx op; | |
5697 | enum machine_mode mode; | |
5698 | { | |
5699 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
5700 | return 0; | |
39a10a29 | 5701 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 5702 | } |
dfbdccdb GK |
5703 | |
5704 | int | |
5705 | boolean_operator (op, mode) | |
5706 | rtx op; | |
5707 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5708 | { | |
5709 | enum rtx_code code = GET_CODE (op); | |
5710 | return (code == AND || code == IOR || code == XOR); | |
5711 | } | |
1d328b19 GK |
5712 | |
5713 | int | |
5714 | boolean_or_operator (op, mode) | |
5715 | rtx op; | |
5716 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5717 | { | |
5718 | enum rtx_code code = GET_CODE (op); | |
5719 | return (code == IOR || code == XOR); | |
5720 | } | |
50a0b056 GK |
5721 | |
5722 | int | |
5723 | min_max_operator (op, mode) | |
5724 | rtx op; | |
5725 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5726 | { | |
5727 | enum rtx_code code = GET_CODE (op); | |
5728 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
5729 | } | |
9878760c RK |
5730 | \f |
5731 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
5732 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 5733 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
5734 | |
5735 | int | |
5736 | includes_lshift_p (shiftop, andop) | |
592696dd SS |
5737 | rtx shiftop; |
5738 | rtx andop; | |
9878760c | 5739 | { |
e2c953b6 DE |
5740 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
5741 | ||
5742 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 5743 | |
b1765bde | 5744 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
5745 | } |
5746 | ||
5747 | /* Similar, but for right shift. */ | |
5748 | ||
5749 | int | |
5750 | includes_rshift_p (shiftop, andop) | |
592696dd SS |
5751 | rtx shiftop; |
5752 | rtx andop; | |
9878760c | 5753 | { |
a7653a2c | 5754 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
5755 | |
5756 | shift_mask >>= INTVAL (shiftop); | |
5757 | ||
b1765bde | 5758 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
5759 | } |
5760 | ||
c5059423 AM |
5761 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
5762 | to perform a left shift. It must have exactly SHIFTOP least | |
5763 | signifigant 0's, then one or more 1's, then zero or more 0's. */ | |
e2c953b6 DE |
5764 | |
5765 | int | |
c5059423 | 5766 | includes_rldic_lshift_p (shiftop, andop) |
592696dd SS |
5767 | rtx shiftop; |
5768 | rtx andop; | |
e2c953b6 | 5769 | { |
c5059423 AM |
5770 | if (GET_CODE (andop) == CONST_INT) |
5771 | { | |
02071907 | 5772 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 5773 | |
c5059423 | 5774 | c = INTVAL (andop); |
02071907 | 5775 | if (c == 0 || c == ~0) |
c5059423 | 5776 | return 0; |
e2c953b6 | 5777 | |
02071907 | 5778 | shift_mask = ~0; |
c5059423 AM |
5779 | shift_mask <<= INTVAL (shiftop); |
5780 | ||
5781 | /* Find the least signifigant one bit. */ | |
5782 | lsb = c & -c; | |
5783 | ||
5784 | /* It must coincide with the LSB of the shift mask. */ | |
5785 | if (-lsb != shift_mask) | |
5786 | return 0; | |
e2c953b6 | 5787 | |
c5059423 AM |
5788 | /* Invert to look for the next transition (if any). */ |
5789 | c = ~c; | |
5790 | ||
5791 | /* Remove the low group of ones (originally low group of zeros). */ | |
5792 | c &= -lsb; | |
5793 | ||
5794 | /* Again find the lsb, and check we have all 1's above. */ | |
5795 | lsb = c & -c; | |
5796 | return c == -lsb; | |
5797 | } | |
5798 | else if (GET_CODE (andop) == CONST_DOUBLE | |
5799 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
5800 | { | |
02071907 AM |
5801 | HOST_WIDE_INT low, high, lsb; |
5802 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
5803 | |
5804 | low = CONST_DOUBLE_LOW (andop); | |
5805 | if (HOST_BITS_PER_WIDE_INT < 64) | |
5806 | high = CONST_DOUBLE_HIGH (andop); | |
5807 | ||
5808 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 5809 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
5810 | return 0; |
5811 | ||
5812 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
5813 | { | |
02071907 | 5814 | shift_mask_high = ~0; |
c5059423 AM |
5815 | if (INTVAL (shiftop) > 32) |
5816 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
5817 | ||
5818 | lsb = high & -high; | |
5819 | ||
5820 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
5821 | return 0; | |
5822 | ||
5823 | high = ~high; | |
5824 | high &= -lsb; | |
5825 | ||
5826 | lsb = high & -high; | |
5827 | return high == -lsb; | |
5828 | } | |
5829 | ||
02071907 | 5830 | shift_mask_low = ~0; |
c5059423 AM |
5831 | shift_mask_low <<= INTVAL (shiftop); |
5832 | ||
5833 | lsb = low & -low; | |
5834 | ||
5835 | if (-lsb != shift_mask_low) | |
5836 | return 0; | |
5837 | ||
5838 | if (HOST_BITS_PER_WIDE_INT < 64) | |
5839 | high = ~high; | |
5840 | low = ~low; | |
5841 | low &= -lsb; | |
5842 | ||
5843 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
5844 | { | |
5845 | lsb = high & -high; | |
5846 | return high == -lsb; | |
5847 | } | |
5848 | ||
5849 | lsb = low & -low; | |
5850 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
5851 | } | |
5852 | else | |
5853 | return 0; | |
5854 | } | |
e2c953b6 | 5855 | |
c5059423 AM |
5856 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
5857 | to perform a left shift. It must have SHIFTOP or more least | |
5858 | signifigant 0's, with the remainder of the word 1's. */ | |
e2c953b6 | 5859 | |
c5059423 AM |
5860 | int |
5861 | includes_rldicr_lshift_p (shiftop, andop) | |
592696dd SS |
5862 | rtx shiftop; |
5863 | rtx andop; | |
c5059423 | 5864 | { |
e2c953b6 | 5865 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 5866 | { |
02071907 | 5867 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 5868 | |
02071907 | 5869 | shift_mask = ~0; |
c5059423 AM |
5870 | shift_mask <<= INTVAL (shiftop); |
5871 | c = INTVAL (andop); | |
5872 | ||
5873 | /* Find the least signifigant one bit. */ | |
5874 | lsb = c & -c; | |
5875 | ||
5876 | /* It must be covered by the shift mask. | |
a4f6c312 | 5877 | This test also rejects c == 0. */ |
c5059423 AM |
5878 | if ((lsb & shift_mask) == 0) |
5879 | return 0; | |
5880 | ||
5881 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
5882 | return c == -lsb && lsb != 1; | |
5883 | } | |
5884 | else if (GET_CODE (andop) == CONST_DOUBLE | |
5885 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
5886 | { | |
02071907 | 5887 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
5888 | |
5889 | low = CONST_DOUBLE_LOW (andop); | |
5890 | ||
5891 | if (HOST_BITS_PER_WIDE_INT < 64) | |
5892 | { | |
02071907 | 5893 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
5894 | |
5895 | high = CONST_DOUBLE_HIGH (andop); | |
5896 | ||
5897 | if (low == 0) | |
5898 | { | |
02071907 | 5899 | shift_mask_high = ~0; |
c5059423 AM |
5900 | if (INTVAL (shiftop) > 32) |
5901 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
5902 | ||
5903 | lsb = high & -high; | |
5904 | ||
5905 | if ((lsb & shift_mask_high) == 0) | |
5906 | return 0; | |
5907 | ||
5908 | return high == -lsb; | |
5909 | } | |
5910 | if (high != ~0) | |
5911 | return 0; | |
5912 | } | |
5913 | ||
02071907 | 5914 | shift_mask_low = ~0; |
c5059423 AM |
5915 | shift_mask_low <<= INTVAL (shiftop); |
5916 | ||
5917 | lsb = low & -low; | |
5918 | ||
5919 | if ((lsb & shift_mask_low) == 0) | |
5920 | return 0; | |
5921 | ||
5922 | return low == -lsb && lsb != 1; | |
5923 | } | |
e2c953b6 | 5924 | else |
c5059423 | 5925 | return 0; |
9878760c | 5926 | } |
35068b43 RK |
5927 | |
5928 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
5929 | for lfq and stfq insns. | |
5930 | ||
5931 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
5932 | abort if we are passed pseudo registers. */ | |
5933 | ||
5934 | int | |
5935 | registers_ok_for_quad_peep (reg1, reg2) | |
5936 | rtx reg1, reg2; | |
5937 | { | |
5938 | /* We might have been passed a SUBREG. */ | |
5939 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
5940 | return 0; | |
5941 | ||
5942 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
5943 | } | |
5944 | ||
a4f6c312 SS |
5945 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
5946 | addr1 and addr2 must be in consecutive memory locations | |
5947 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
5948 | |
5949 | int | |
5950 | addrs_ok_for_quad_peep (addr1, addr2) | |
592696dd SS |
5951 | rtx addr1; |
5952 | rtx addr2; | |
35068b43 | 5953 | { |
e2c953b6 | 5954 | unsigned int reg1; |
35068b43 RK |
5955 | int offset1; |
5956 | ||
5957 | /* Extract an offset (if used) from the first addr. */ | |
5958 | if (GET_CODE (addr1) == PLUS) | |
5959 | { | |
5960 | /* If not a REG, return zero. */ | |
5961 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
5962 | return 0; | |
5963 | else | |
5964 | { | |
5965 | reg1 = REGNO (XEXP (addr1, 0)); | |
5966 | /* The offset must be constant! */ | |
5967 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
5968 | return 0; | |
5969 | offset1 = INTVAL (XEXP (addr1, 1)); | |
5970 | } | |
5971 | } | |
5972 | else if (GET_CODE (addr1) != REG) | |
5973 | return 0; | |
5974 | else | |
5975 | { | |
5976 | reg1 = REGNO (addr1); | |
5977 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
5978 | offset1 = 0; | |
5979 | } | |
5980 | ||
acad7ed3 | 5981 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
5982 | if (GET_CODE (addr2) != PLUS) |
5983 | return 0; | |
5984 | ||
5985 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
5986 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
5987 | return 0; | |
5988 | ||
5989 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
5990 | return 0; | |
5991 | ||
5992 | /* The offset for the second addr must be 8 more than the first addr. */ | |
5993 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
5994 | return 0; | |
5995 | ||
5996 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
5997 | instructions. */ | |
5998 | return 1; | |
5999 | } | |
9878760c RK |
6000 | \f |
6001 | /* Return the register class of a scratch register needed to copy IN into | |
6002 | or out of a register in CLASS in MODE. If it can be done directly, | |
6003 | NO_REGS is returned. */ | |
6004 | ||
6005 | enum reg_class | |
6006 | secondary_reload_class (class, mode, in) | |
6007 | enum reg_class class; | |
296b8152 | 6008 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
6009 | rtx in; |
6010 | { | |
5accd822 | 6011 | int regno; |
9878760c | 6012 | |
46fad5b7 DJ |
6013 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic)) |
6014 | { | |
6015 | /* We cannot copy a symbolic operand directly into anything | |
6016 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
6017 | register from BASE_REGS is needed as an intermediate | |
6018 | register. | |
6019 | ||
6020 | On Darwin, pic addresses require a load from memory, which | |
6021 | needs a base register. */ | |
6022 | if (class != BASE_REGS | |
6023 | && (GET_CODE (in) == SYMBOL_REF | |
6024 | || GET_CODE (in) == HIGH | |
6025 | || GET_CODE (in) == LABEL_REF | |
6026 | || GET_CODE (in) == CONST)) | |
6027 | return BASE_REGS; | |
6028 | } | |
e7b7998a | 6029 | |
5accd822 DE |
6030 | if (GET_CODE (in) == REG) |
6031 | { | |
6032 | regno = REGNO (in); | |
6033 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6034 | { | |
6035 | regno = true_regnum (in); | |
6036 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6037 | regno = -1; | |
6038 | } | |
6039 | } | |
6040 | else if (GET_CODE (in) == SUBREG) | |
6041 | { | |
6042 | regno = true_regnum (in); | |
6043 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6044 | regno = -1; | |
6045 | } | |
6046 | else | |
6047 | regno = -1; | |
6048 | ||
9878760c RK |
6049 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
6050 | into anything. */ | |
6051 | if (class == GENERAL_REGS || class == BASE_REGS | |
6052 | || (regno >= 0 && INT_REGNO_P (regno))) | |
6053 | return NO_REGS; | |
6054 | ||
6055 | /* Constants, memory, and FP registers can go into FP registers. */ | |
6056 | if ((regno == -1 || FP_REGNO_P (regno)) | |
6057 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
6058 | return NO_REGS; | |
6059 | ||
0ac081f6 AH |
6060 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
6061 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
6062 | && class == ALTIVEC_REGS) | |
6063 | return NO_REGS; | |
6064 | ||
9878760c RK |
6065 | /* We can copy among the CR registers. */ |
6066 | if ((class == CR_REGS || class == CR0_REGS) | |
6067 | && regno >= 0 && CR_REGNO_P (regno)) | |
6068 | return NO_REGS; | |
6069 | ||
6070 | /* Otherwise, we need GENERAL_REGS. */ | |
6071 | return GENERAL_REGS; | |
6072 | } | |
6073 | \f | |
6074 | /* Given a comparison operation, return the bit number in CCR to test. We | |
6075 | know this is a valid comparison. | |
6076 | ||
6077 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
6078 | used instead of %C, so the bits will be in different places. | |
6079 | ||
b4ac57ab | 6080 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
6081 | |
6082 | int | |
6083 | ccr_bit (op, scc_p) | |
592696dd | 6084 | rtx op; |
9878760c RK |
6085 | int scc_p; |
6086 | { | |
6087 | enum rtx_code code = GET_CODE (op); | |
6088 | enum machine_mode cc_mode; | |
6089 | int cc_regnum; | |
6090 | int base_bit; | |
9ebbca7d | 6091 | rtx reg; |
9878760c RK |
6092 | |
6093 | if (GET_RTX_CLASS (code) != '<') | |
6094 | return -1; | |
6095 | ||
9ebbca7d GK |
6096 | reg = XEXP (op, 0); |
6097 | ||
6098 | if (GET_CODE (reg) != REG | |
6099 | || ! CR_REGNO_P (REGNO (reg))) | |
6100 | abort (); | |
6101 | ||
6102 | cc_mode = GET_MODE (reg); | |
6103 | cc_regnum = REGNO (reg); | |
6104 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 6105 | |
39a10a29 | 6106 | validate_condition_mode (code, cc_mode); |
c5defebb | 6107 | |
9878760c RK |
6108 | switch (code) |
6109 | { | |
6110 | case NE: | |
6111 | return scc_p ? base_bit + 3 : base_bit + 2; | |
6112 | case EQ: | |
6113 | return base_bit + 2; | |
1c882ea4 | 6114 | case GT: case GTU: case UNLE: |
9878760c | 6115 | return base_bit + 1; |
1c882ea4 | 6116 | case LT: case LTU: case UNGE: |
9878760c | 6117 | return base_bit; |
1c882ea4 GK |
6118 | case ORDERED: case UNORDERED: |
6119 | return base_bit + 3; | |
9878760c RK |
6120 | |
6121 | case GE: case GEU: | |
39a10a29 | 6122 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
6123 | unordered position. So test that bit. For integer, this is ! LT |
6124 | unless this is an scc insn. */ | |
39a10a29 | 6125 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
6126 | |
6127 | case LE: case LEU: | |
39a10a29 | 6128 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 6129 | |
9878760c RK |
6130 | default: |
6131 | abort (); | |
6132 | } | |
6133 | } | |
1ff7789b | 6134 | \f |
8d30c4ee | 6135 | /* Return the GOT register. */ |
1ff7789b MM |
6136 | |
6137 | struct rtx_def * | |
6138 | rs6000_got_register (value) | |
5f59ecb7 | 6139 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 6140 | { |
a4f6c312 SS |
6141 | /* The second flow pass currently (June 1999) can't update |
6142 | regs_ever_live without disturbing other parts of the compiler, so | |
6143 | update it here to make the prolog/epilogue code happy. */ | |
3cb999d8 | 6144 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 6145 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 6146 | |
8d30c4ee | 6147 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 6148 | |
1ff7789b MM |
6149 | return pic_offset_table_rtx; |
6150 | } | |
a7df97e6 | 6151 | \f |
71f123ca | 6152 | /* Functions to init, mark and free struct machine_function. |
a7df97e6 MM |
6153 | These will be called, via pointer variables, |
6154 | from push_function_context and pop_function_context. */ | |
6155 | ||
00dba523 NC |
6156 | static void |
6157 | rs6000_init_machine_status (p) | |
a7df97e6 MM |
6158 | struct function *p; |
6159 | { | |
71f123ca FS |
6160 | p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); |
6161 | } | |
a7df97e6 | 6162 | |
00dba523 NC |
6163 | static void |
6164 | rs6000_free_machine_status (p) | |
a7df97e6 MM |
6165 | struct function *p; |
6166 | { | |
00dba523 NC |
6167 | if (p->machine == NULL) |
6168 | return; | |
a7df97e6 | 6169 | |
00dba523 NC |
6170 | free (p->machine); |
6171 | p->machine = NULL; | |
a7df97e6 MM |
6172 | } |
6173 | ||
9878760c RK |
6174 | \f |
6175 | /* Print an operand. Recognize special options, documented below. */ | |
6176 | ||
38c1f2d7 | 6177 | #if TARGET_ELF |
d9407988 | 6178 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 6179 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
6180 | #else |
6181 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 6182 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
6183 | #endif |
6184 | ||
9878760c RK |
6185 | void |
6186 | print_operand (file, x, code) | |
6187 | FILE *file; | |
6188 | rtx x; | |
9ebbca7d | 6189 | int code; |
9878760c RK |
6190 | { |
6191 | int i; | |
a260abc9 | 6192 | HOST_WIDE_INT val; |
9878760c RK |
6193 | |
6194 | /* These macros test for integers and extract the low-order bits. */ | |
6195 | #define INT_P(X) \ | |
6196 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
6197 | && GET_MODE (X) == VOIDmode) | |
6198 | ||
6199 | #define INT_LOWPART(X) \ | |
6200 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
6201 | ||
6202 | switch (code) | |
6203 | { | |
a8b3aeda | 6204 | case '.': |
a85d226b RK |
6205 | /* Write out an instruction after the call which may be replaced |
6206 | with glue code by the loader. This depends on the AIX version. */ | |
6207 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
6208 | return; |
6209 | ||
81eace42 GK |
6210 | /* %a is output_address. */ |
6211 | ||
9854d9ed RK |
6212 | case 'A': |
6213 | /* If X is a constant integer whose low-order 5 bits are zero, | |
6214 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 6215 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 6216 | writes a trash instruction. */ |
9854d9ed | 6217 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 6218 | putc ('l', file); |
9854d9ed | 6219 | else |
76229ac8 | 6220 | putc ('r', file); |
9854d9ed RK |
6221 | return; |
6222 | ||
6223 | case 'b': | |
e2c953b6 DE |
6224 | /* If constant, low-order 16 bits of constant, unsigned. |
6225 | Otherwise, write normally. */ | |
6226 | if (INT_P (x)) | |
6227 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
6228 | else | |
6229 | print_operand (file, x, 0); | |
cad12a8d RK |
6230 | return; |
6231 | ||
a260abc9 DE |
6232 | case 'B': |
6233 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
6234 | for 64-bit mask direction. */ | |
296b8152 | 6235 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 6236 | return; |
a260abc9 | 6237 | |
81eace42 GK |
6238 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
6239 | output_operand. */ | |
6240 | ||
9854d9ed | 6241 | case 'D': |
39a10a29 GK |
6242 | /* There used to be a comment for 'C' reading "This is an |
6243 | optional cror needed for certain floating-point | |
6244 | comparisons. Otherwise write nothing." */ | |
6245 | ||
9854d9ed RK |
6246 | /* Similar, except that this is for an scc, so we must be able to |
6247 | encode the test in a single bit that is one. We do the above | |
6248 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
6249 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
6250 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
6251 | { | |
9ebbca7d | 6252 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
6253 | |
6254 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
6255 | base_bit + 2, | |
6256 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
6257 | } | |
6258 | ||
6259 | else if (GET_CODE (x) == NE) | |
6260 | { | |
9ebbca7d | 6261 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
6262 | |
6263 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
6264 | base_bit + 2, base_bit + 2); | |
6265 | } | |
6266 | return; | |
6267 | ||
6268 | case 'E': | |
39a10a29 | 6269 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
6270 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
6271 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 6272 | else |
39a10a29 | 6273 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 6274 | return; |
9854d9ed RK |
6275 | |
6276 | case 'f': | |
6277 | /* X is a CR register. Print the shift count needed to move it | |
6278 | to the high-order four bits. */ | |
6279 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
6280 | output_operand_lossage ("invalid %%f value"); | |
6281 | else | |
9ebbca7d | 6282 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
6283 | return; |
6284 | ||
6285 | case 'F': | |
6286 | /* Similar, but print the count for the rotate in the opposite | |
6287 | direction. */ | |
6288 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
6289 | output_operand_lossage ("invalid %%F value"); | |
6290 | else | |
9ebbca7d | 6291 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
6292 | return; |
6293 | ||
6294 | case 'G': | |
6295 | /* X is a constant integer. If it is negative, print "m", | |
6296 | otherwise print "z". This is to make a aze or ame insn. */ | |
6297 | if (GET_CODE (x) != CONST_INT) | |
6298 | output_operand_lossage ("invalid %%G value"); | |
6299 | else if (INTVAL (x) >= 0) | |
76229ac8 | 6300 | putc ('z', file); |
9854d9ed | 6301 | else |
76229ac8 | 6302 | putc ('m', file); |
9854d9ed | 6303 | return; |
e2c953b6 | 6304 | |
9878760c | 6305 | case 'h': |
a4f6c312 SS |
6306 | /* If constant, output low-order five bits. Otherwise, write |
6307 | normally. */ | |
9878760c | 6308 | if (INT_P (x)) |
5f59ecb7 | 6309 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
6310 | else |
6311 | print_operand (file, x, 0); | |
6312 | return; | |
6313 | ||
64305719 | 6314 | case 'H': |
a4f6c312 SS |
6315 | /* If constant, output low-order six bits. Otherwise, write |
6316 | normally. */ | |
64305719 | 6317 | if (INT_P (x)) |
5f59ecb7 | 6318 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
6319 | else |
6320 | print_operand (file, x, 0); | |
6321 | return; | |
6322 | ||
9854d9ed RK |
6323 | case 'I': |
6324 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 6325 | if (INT_P (x)) |
76229ac8 | 6326 | putc ('i', file); |
9878760c RK |
6327 | return; |
6328 | ||
9854d9ed RK |
6329 | case 'j': |
6330 | /* Write the bit number in CCR for jump. */ | |
6331 | i = ccr_bit (x, 0); | |
6332 | if (i == -1) | |
6333 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 6334 | else |
9854d9ed | 6335 | fprintf (file, "%d", i); |
9878760c RK |
6336 | return; |
6337 | ||
9854d9ed RK |
6338 | case 'J': |
6339 | /* Similar, but add one for shift count in rlinm for scc and pass | |
6340 | scc flag to `ccr_bit'. */ | |
6341 | i = ccr_bit (x, 1); | |
6342 | if (i == -1) | |
6343 | output_operand_lossage ("invalid %%J code"); | |
6344 | else | |
a0466a68 RK |
6345 | /* If we want bit 31, write a shift count of zero, not 32. */ |
6346 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
6347 | return; |
6348 | ||
9854d9ed RK |
6349 | case 'k': |
6350 | /* X must be a constant. Write the 1's complement of the | |
6351 | constant. */ | |
9878760c | 6352 | if (! INT_P (x)) |
9854d9ed | 6353 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
6354 | else |
6355 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
6356 | return; |
6357 | ||
81eace42 | 6358 | case 'K': |
9ebbca7d GK |
6359 | /* X must be a symbolic constant on ELF. Write an |
6360 | expression suitable for an 'addi' that adds in the low 16 | |
6361 | bits of the MEM. */ | |
6362 | if (GET_CODE (x) != CONST) | |
6363 | { | |
6364 | print_operand_address (file, x); | |
6365 | fputs ("@l", file); | |
6366 | } | |
6367 | else | |
6368 | { | |
6369 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
6370 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
6371 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
6372 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 6373 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
6374 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
6375 | fputs ("@l", file); | |
6376 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
6377 | } | |
81eace42 GK |
6378 | return; |
6379 | ||
6380 | /* %l is output_asm_label. */ | |
9ebbca7d | 6381 | |
9854d9ed RK |
6382 | case 'L': |
6383 | /* Write second word of DImode or DFmode reference. Works on register | |
6384 | or non-indexed memory only. */ | |
6385 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 6386 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
6387 | else if (GET_CODE (x) == MEM) |
6388 | { | |
6389 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 6390 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
6391 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
6392 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
6393 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
6394 | UNITS_PER_WORD)); | |
9854d9ed | 6395 | else |
d7624dc0 RK |
6396 | output_address (XEXP (adjust_address_nv (x, SImode, |
6397 | UNITS_PER_WORD), | |
6398 | 0)); | |
ed8908e7 | 6399 | |
ba5e43aa | 6400 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6401 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6402 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 6403 | } |
9878760c | 6404 | return; |
9854d9ed | 6405 | |
9878760c RK |
6406 | case 'm': |
6407 | /* MB value for a mask operand. */ | |
b1765bde | 6408 | if (! mask_operand (x, SImode)) |
9878760c RK |
6409 | output_operand_lossage ("invalid %%m value"); |
6410 | ||
6411 | val = INT_LOWPART (x); | |
6412 | ||
6413 | /* If the high bit is set and the low bit is not, the value is zero. | |
6414 | If the high bit is zero, the value is the first 1 bit we find from | |
6415 | the left. */ | |
0858c623 | 6416 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 6417 | { |
19d2d16f | 6418 | putc ('0', file); |
9878760c RK |
6419 | return; |
6420 | } | |
0858c623 | 6421 | else if ((val & 0x80000000) == 0) |
9878760c RK |
6422 | { |
6423 | for (i = 1; i < 32; i++) | |
0858c623 | 6424 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
6425 | break; |
6426 | fprintf (file, "%d", i); | |
6427 | return; | |
6428 | } | |
6429 | ||
6430 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
6431 | number plus 1. We know the low-order bit is one. */ | |
6432 | for (i = 0; i < 32; i++) | |
6433 | if (((val >>= 1) & 1) == 0) | |
6434 | break; | |
6435 | ||
a260abc9 | 6436 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
6437 | we want 31 - i. */ |
6438 | fprintf (file, "%d", 31 - i); | |
6439 | return; | |
6440 | ||
6441 | case 'M': | |
6442 | /* ME value for a mask operand. */ | |
b1765bde | 6443 | if (! mask_operand (x, SImode)) |
a260abc9 | 6444 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
6445 | |
6446 | val = INT_LOWPART (x); | |
6447 | ||
6448 | /* If the low bit is set and the high bit is not, the value is 31. | |
6449 | If the low bit is zero, the value is the first 1 bit we find from | |
6450 | the right. */ | |
0858c623 | 6451 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 6452 | { |
76229ac8 | 6453 | fputs ("31", file); |
9878760c RK |
6454 | return; |
6455 | } | |
6456 | else if ((val & 1) == 0) | |
6457 | { | |
6458 | for (i = 0; i < 32; i++) | |
6459 | if ((val >>= 1) & 1) | |
6460 | break; | |
6461 | ||
a260abc9 | 6462 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
6463 | 30, so we need 30 - i. */ |
6464 | fprintf (file, "%d", 30 - i); | |
6465 | return; | |
6466 | } | |
6467 | ||
6468 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
6469 | number minus 1. We know the high-order bit is one. */ | |
6470 | for (i = 0; i < 32; i++) | |
0858c623 | 6471 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
6472 | break; |
6473 | ||
6474 | fprintf (file, "%d", i); | |
6475 | return; | |
6476 | ||
81eace42 GK |
6477 | /* %n outputs the negative of its operand. */ |
6478 | ||
9878760c RK |
6479 | case 'N': |
6480 | /* Write the number of elements in the vector times 4. */ | |
6481 | if (GET_CODE (x) != PARALLEL) | |
6482 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
6483 | else |
6484 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
6485 | return; |
6486 | ||
6487 | case 'O': | |
6488 | /* Similar, but subtract 1 first. */ | |
6489 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 6490 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
6491 | else |
6492 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
6493 | return; |
6494 | ||
9854d9ed RK |
6495 | case 'p': |
6496 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
6497 | if (! INT_P (x) | |
2bfcf297 | 6498 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
6499 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
6500 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
6501 | else |
6502 | fprintf (file, "%d", i); | |
9854d9ed RK |
6503 | return; |
6504 | ||
9878760c RK |
6505 | case 'P': |
6506 | /* The operand must be an indirect memory reference. The result | |
a4f6c312 | 6507 | is the register number. */ |
9878760c RK |
6508 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
6509 | || REGNO (XEXP (x, 0)) >= 32) | |
6510 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
6511 | else |
6512 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
6513 | return; |
6514 | ||
dfbdccdb GK |
6515 | case 'q': |
6516 | /* This outputs the logical code corresponding to a boolean | |
6517 | expression. The expression may have one or both operands | |
39a10a29 GK |
6518 | negated (if one, only the first one). For condition register |
6519 | logical operations, it will also treat the negated | |
6520 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 6521 | { |
63bc1d05 | 6522 | const char *const *t = 0; |
dfbdccdb GK |
6523 | const char *s; |
6524 | enum rtx_code code = GET_CODE (x); | |
6525 | static const char * const tbl[3][3] = { | |
6526 | { "and", "andc", "nor" }, | |
6527 | { "or", "orc", "nand" }, | |
6528 | { "xor", "eqv", "xor" } }; | |
6529 | ||
6530 | if (code == AND) | |
6531 | t = tbl[0]; | |
6532 | else if (code == IOR) | |
6533 | t = tbl[1]; | |
6534 | else if (code == XOR) | |
6535 | t = tbl[2]; | |
6536 | else | |
6537 | output_operand_lossage ("invalid %%q value"); | |
6538 | ||
6539 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
6540 | s = t[0]; | |
6541 | else | |
6542 | { | |
6543 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
6544 | s = t[2]; | |
6545 | else | |
6546 | s = t[1]; | |
6547 | } | |
6548 | ||
6549 | fputs (s, file); | |
6550 | } | |
6551 | return; | |
6552 | ||
9854d9ed RK |
6553 | case 'R': |
6554 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
6555 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
6556 | output_operand_lossage ("invalid %%R value"); | |
6557 | else | |
9ebbca7d | 6558 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 6559 | return; |
9854d9ed RK |
6560 | |
6561 | case 's': | |
6562 | /* Low 5 bits of 32 - value */ | |
6563 | if (! INT_P (x)) | |
6564 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
6565 | else |
6566 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 6567 | return; |
9854d9ed | 6568 | |
a260abc9 DE |
6569 | case 'S': |
6570 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
6571 | CONST_INT 32-bit mask is considered sign-extended so any | |
6572 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 6573 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
6574 | output_operand_lossage ("invalid %%S value"); |
6575 | ||
6576 | val = INT_LOWPART (x); | |
6577 | ||
6578 | if (val & 1) /* Clear Left */ | |
6579 | { | |
a238cd8b DE |
6580 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
6581 | if (!((val >>= 1) & 1)) | |
6582 | break; | |
a260abc9 | 6583 | |
a238cd8b DE |
6584 | #if HOST_BITS_PER_WIDE_INT == 32 |
6585 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
6586 | { | |
6587 | val = CONST_DOUBLE_HIGH (x); | |
6588 | ||
6589 | if (val == 0) | |
6590 | --i; | |
6591 | else | |
6592 | for (i = 32; i < 64; i++) | |
6593 | if (!((val >>= 1) & 1)) | |
6594 | break; | |
6595 | } | |
a260abc9 | 6596 | #endif |
a238cd8b DE |
6597 | /* i = index of last set bit from right |
6598 | mask begins at 63 - i from left */ | |
6599 | if (i > 63) | |
6600 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 6601 | |
a260abc9 DE |
6602 | fprintf (file, "%d", 63 - i); |
6603 | return; | |
6604 | } | |
6605 | else /* Clear Right */ | |
6606 | { | |
a238cd8b DE |
6607 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
6608 | if ((val >>= 1) & 1) | |
6609 | break; | |
a260abc9 | 6610 | |
a238cd8b | 6611 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
6612 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
6613 | { | |
a238cd8b | 6614 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 6615 | |
a238cd8b | 6616 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 6617 | --i; |
a260abc9 | 6618 | else |
a238cd8b DE |
6619 | for (i = 32; i < 64; i++) |
6620 | if ((val >>= 1) & 1) | |
a260abc9 DE |
6621 | break; |
6622 | } | |
6623 | #endif | |
a238cd8b DE |
6624 | /* i = index of last clear bit from right |
6625 | mask ends at 62 - i from left */ | |
6626 | if (i > 62) | |
6627 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 6628 | |
a238cd8b | 6629 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
6630 | return; |
6631 | } | |
6632 | ||
cccf3bdc DE |
6633 | case 'T': |
6634 | /* Print the symbolic name of a branch target register. */ | |
6635 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
6636 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
6637 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 6638 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
6639 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
6640 | else | |
6641 | fputs ("ctr", file); | |
6642 | return; | |
6643 | ||
9854d9ed | 6644 | case 'u': |
802a0058 | 6645 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
6646 | if (! INT_P (x)) |
6647 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
6648 | else |
6649 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
6650 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
6651 | return; |
6652 | ||
802a0058 MM |
6653 | case 'v': |
6654 | /* High-order 16 bits of constant for use in signed operand. */ | |
6655 | if (! INT_P (x)) | |
6656 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 6657 | else |
134c32f6 DE |
6658 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
6659 | (INT_LOWPART (x) >> 16) & 0xffff); | |
6660 | return; | |
802a0058 | 6661 | |
9854d9ed RK |
6662 | case 'U': |
6663 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
6664 | if (GET_CODE (x) == MEM | |
6665 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
6666 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 6667 | putc ('u', file); |
9854d9ed | 6668 | return; |
9878760c | 6669 | |
e0cd0770 JC |
6670 | case 'V': |
6671 | /* Print the trap code for this operand. */ | |
6672 | switch (GET_CODE (x)) | |
6673 | { | |
6674 | case EQ: | |
6675 | fputs ("eq", file); /* 4 */ | |
6676 | break; | |
6677 | case NE: | |
6678 | fputs ("ne", file); /* 24 */ | |
6679 | break; | |
6680 | case LT: | |
6681 | fputs ("lt", file); /* 16 */ | |
6682 | break; | |
6683 | case LE: | |
6684 | fputs ("le", file); /* 20 */ | |
6685 | break; | |
6686 | case GT: | |
6687 | fputs ("gt", file); /* 8 */ | |
6688 | break; | |
6689 | case GE: | |
6690 | fputs ("ge", file); /* 12 */ | |
6691 | break; | |
6692 | case LTU: | |
6693 | fputs ("llt", file); /* 2 */ | |
6694 | break; | |
6695 | case LEU: | |
6696 | fputs ("lle", file); /* 6 */ | |
6697 | break; | |
6698 | case GTU: | |
6699 | fputs ("lgt", file); /* 1 */ | |
6700 | break; | |
6701 | case GEU: | |
6702 | fputs ("lge", file); /* 5 */ | |
6703 | break; | |
6704 | default: | |
6705 | abort (); | |
6706 | } | |
6707 | break; | |
6708 | ||
9854d9ed RK |
6709 | case 'w': |
6710 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
6711 | normally. */ | |
6712 | if (INT_P (x)) | |
5f59ecb7 DE |
6713 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
6714 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
6715 | else |
6716 | print_operand (file, x, 0); | |
9878760c RK |
6717 | return; |
6718 | ||
9854d9ed | 6719 | case 'W': |
e2c953b6 | 6720 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
6721 | val = (GET_CODE (x) == CONST_INT |
6722 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
6723 | ||
6724 | if (val < 0) | |
6725 | i = -1; | |
9854d9ed | 6726 | else |
e2c953b6 DE |
6727 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
6728 | if ((val <<= 1) < 0) | |
6729 | break; | |
6730 | ||
6731 | #if HOST_BITS_PER_WIDE_INT == 32 | |
6732 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
6733 | i += 32; /* zero-extend high-part was all 0's */ | |
6734 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
6735 | { | |
6736 | val = CONST_DOUBLE_LOW (x); | |
6737 | ||
6738 | if (val == 0) | |
a4f6c312 | 6739 | abort (); |
e2c953b6 DE |
6740 | else if (val < 0) |
6741 | --i; | |
6742 | else | |
6743 | for ( ; i < 64; i++) | |
6744 | if ((val <<= 1) < 0) | |
6745 | break; | |
6746 | } | |
6747 | #endif | |
6748 | ||
6749 | fprintf (file, "%d", i + 1); | |
9854d9ed | 6750 | return; |
9878760c | 6751 | |
9854d9ed RK |
6752 | case 'X': |
6753 | if (GET_CODE (x) == MEM | |
258bfae2 | 6754 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 6755 | putc ('x', file); |
9854d9ed | 6756 | return; |
9878760c | 6757 | |
9854d9ed RK |
6758 | case 'Y': |
6759 | /* Like 'L', for third word of TImode */ | |
6760 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 6761 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 6762 | else if (GET_CODE (x) == MEM) |
9878760c | 6763 | { |
9854d9ed RK |
6764 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
6765 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 6766 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 6767 | else |
d7624dc0 | 6768 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 6769 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6770 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6771 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
6772 | } |
6773 | return; | |
9854d9ed | 6774 | |
9878760c | 6775 | case 'z': |
b4ac57ab RS |
6776 | /* X is a SYMBOL_REF. Write out the name preceded by a |
6777 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
6778 | names. If we are configured for System V (or the embedded ABI) on |
6779 | the PowerPC, do not emit the period, since those systems do not use | |
6780 | TOCs and the like. */ | |
9878760c RK |
6781 | if (GET_CODE (x) != SYMBOL_REF) |
6782 | abort (); | |
6783 | ||
b6c9286a MM |
6784 | if (XSTR (x, 0)[0] != '.') |
6785 | { | |
6786 | switch (DEFAULT_ABI) | |
6787 | { | |
6788 | default: | |
6789 | abort (); | |
6790 | ||
6791 | case ABI_AIX: | |
6792 | putc ('.', file); | |
6793 | break; | |
6794 | ||
6795 | case ABI_V4: | |
6796 | case ABI_AIX_NODESC: | |
ee890fe2 | 6797 | case ABI_DARWIN: |
b6c9286a | 6798 | break; |
b6c9286a MM |
6799 | } |
6800 | } | |
54ee9799 DE |
6801 | #if TARGET_AIX |
6802 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); | |
6803 | #else | |
9ebbca7d | 6804 | assemble_name (file, XSTR (x, 0)); |
54ee9799 | 6805 | #endif |
9878760c RK |
6806 | return; |
6807 | ||
9854d9ed RK |
6808 | case 'Z': |
6809 | /* Like 'L', for last word of TImode. */ | |
6810 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 6811 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
6812 | else if (GET_CODE (x) == MEM) |
6813 | { | |
6814 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
6815 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 6816 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 6817 | else |
d7624dc0 | 6818 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 6819 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6820 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6821 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 6822 | } |
5c23c401 | 6823 | return; |
0ac081f6 AH |
6824 | |
6825 | /* Print AltiVec memory operand. */ | |
6826 | case 'y': | |
6827 | { | |
6828 | rtx tmp; | |
6829 | ||
6830 | if (GET_CODE (x) != MEM) | |
6831 | abort (); | |
6832 | ||
6833 | tmp = XEXP (x, 0); | |
6834 | ||
6835 | if (GET_CODE (tmp) == REG) | |
c62f2db5 | 6836 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
6837 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
6838 | { | |
6839 | if (REGNO (XEXP (tmp, 0)) == 0) | |
6840 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
6841 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
6842 | else | |
6843 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
6844 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
6845 | } | |
6846 | else | |
6847 | abort (); | |
6848 | break; | |
6849 | } | |
9854d9ed | 6850 | |
9878760c RK |
6851 | case 0: |
6852 | if (GET_CODE (x) == REG) | |
6853 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
6854 | else if (GET_CODE (x) == MEM) | |
6855 | { | |
6856 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
6857 | know the width from the mode. */ | |
6858 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
6859 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
6860 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 6861 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
6862 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
6863 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 6864 | else |
a54d04b7 | 6865 | output_address (XEXP (x, 0)); |
9878760c RK |
6866 | } |
6867 | else | |
a54d04b7 | 6868 | output_addr_const (file, x); |
a85d226b | 6869 | return; |
9878760c RK |
6870 | |
6871 | default: | |
6872 | output_operand_lossage ("invalid %%xn code"); | |
6873 | } | |
6874 | } | |
6875 | \f | |
6876 | /* Print the address of an operand. */ | |
6877 | ||
6878 | void | |
6879 | print_operand_address (file, x) | |
6880 | FILE *file; | |
592696dd | 6881 | rtx x; |
9878760c RK |
6882 | { |
6883 | if (GET_CODE (x) == REG) | |
4697a36c | 6884 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
6885 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
6886 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
6887 | { |
6888 | output_addr_const (file, x); | |
ba5e43aa | 6889 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6890 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6891 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 6892 | else if (TARGET_TOC) |
a4f6c312 | 6893 | abort (); |
9878760c RK |
6894 | } |
6895 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
6896 | { | |
6897 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
6898 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
6899 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 6900 | else |
4697a36c MM |
6901 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
6902 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
6903 | } |
6904 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
6905 | { |
6906 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
6907 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
6908 | } | |
3cb999d8 DE |
6909 | #if TARGET_ELF |
6910 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
6911 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
6912 | { |
6913 | output_addr_const (file, XEXP (x, 1)); | |
6914 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
6915 | } | |
c859cda6 DJ |
6916 | #endif |
6917 | #if TARGET_MACHO | |
6918 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
6919 | && CONSTANT_P (XEXP (x, 1))) | |
6920 | { | |
6921 | fprintf (file, "lo16("); | |
6922 | output_addr_const (file, XEXP (x, 1)); | |
6923 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
6924 | } | |
3cb999d8 | 6925 | #endif |
9ebbca7d GK |
6926 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
6927 | { | |
2bfcf297 | 6928 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 6929 | { |
2bfcf297 DB |
6930 | rtx contains_minus = XEXP (x, 1); |
6931 | rtx minus, symref; | |
6932 | const char *name; | |
9ebbca7d GK |
6933 | |
6934 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 6935 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
6936 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
6937 | contains_minus = XEXP (contains_minus, 0); | |
6938 | ||
2bfcf297 DB |
6939 | minus = XEXP (contains_minus, 0); |
6940 | symref = XEXP (minus, 0); | |
6941 | XEXP (contains_minus, 0) = symref; | |
6942 | if (TARGET_ELF) | |
6943 | { | |
6944 | char *newname; | |
6945 | ||
6946 | name = XSTR (symref, 0); | |
6947 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
6948 | strcpy (newname, name); | |
6949 | strcat (newname, "@toc"); | |
6950 | XSTR (symref, 0) = newname; | |
6951 | } | |
6952 | output_addr_const (file, XEXP (x, 1)); | |
6953 | if (TARGET_ELF) | |
6954 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
6955 | XEXP (contains_minus, 0) = minus; |
6956 | } | |
6957 | else | |
6958 | output_addr_const (file, XEXP (x, 1)); | |
6959 | ||
6960 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
6961 | } | |
9878760c RK |
6962 | else |
6963 | abort (); | |
6964 | } | |
6965 | \f | |
301d03af RS |
6966 | /* Target hook for assembling integer objects. The powerpc version has |
6967 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP | |
6968 | is defined. It also needs to handle DI-mode objects on 64-bit | |
6969 | targets. */ | |
6970 | ||
6971 | static bool | |
6972 | rs6000_assemble_integer (x, size, aligned_p) | |
6973 | rtx x; | |
6974 | unsigned int size; | |
6975 | int aligned_p; | |
6976 | { | |
6977 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
6978 | /* Special handling for SI values. */ | |
6979 | if (size == 4 && aligned_p) | |
6980 | { | |
6981 | extern int in_toc_section PARAMS ((void)); | |
6982 | static int recurse = 0; | |
6983 | ||
6984 | /* For -mrelocatable, we mark all addresses that need to be fixed up | |
6985 | in the .fixup section. */ | |
6986 | if (TARGET_RELOCATABLE | |
6987 | && !in_toc_section () | |
6988 | && !in_text_section () | |
6989 | && !recurse | |
6990 | && GET_CODE (x) != CONST_INT | |
6991 | && GET_CODE (x) != CONST_DOUBLE | |
6992 | && CONSTANT_P (x)) | |
6993 | { | |
6994 | char buf[256]; | |
6995 | ||
6996 | recurse = 1; | |
6997 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
6998 | fixuplabelno++; | |
6999 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
7000 | fprintf (asm_out_file, "\t.long\t("); | |
7001 | output_addr_const (asm_out_file, x); | |
7002 | fprintf (asm_out_file, ")@fixup\n"); | |
7003 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
7004 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
7005 | fprintf (asm_out_file, "\t.long\t"); | |
7006 | assemble_name (asm_out_file, buf); | |
7007 | fprintf (asm_out_file, "\n\t.previous\n"); | |
7008 | recurse = 0; | |
7009 | return true; | |
7010 | } | |
7011 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
7012 | address into the address of the descriptor, not the function | |
7013 | itself. */ | |
7014 | else if (GET_CODE (x) == SYMBOL_REF | |
7015 | && XSTR (x, 0)[0] == '.' | |
7016 | && DEFAULT_ABI == ABI_AIX) | |
7017 | { | |
7018 | const char *name = XSTR (x, 0); | |
7019 | while (*name == '.') | |
7020 | name++; | |
7021 | ||
7022 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
7023 | return true; | |
7024 | } | |
7025 | } | |
7026 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
7027 | return default_assemble_integer (x, size, aligned_p); | |
7028 | } | |
7029 | \f | |
39a10a29 GK |
7030 | enum rtx_code |
7031 | rs6000_reverse_condition (mode, code) | |
7032 | enum machine_mode mode; | |
7033 | enum rtx_code code; | |
7034 | { | |
7035 | /* Reversal of FP compares takes care -- an ordered compare | |
7036 | becomes an unordered compare and vice versa. */ | |
7037 | if (mode == CCFPmode) | |
bab6226b | 7038 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 7039 | else |
bab6226b | 7040 | return reverse_condition (code); |
39a10a29 GK |
7041 | } |
7042 | ||
39a10a29 GK |
7043 | /* Generate a compare for CODE. Return a brand-new rtx that |
7044 | represents the result of the compare. */ | |
a4f6c312 | 7045 | |
39a10a29 GK |
7046 | static rtx |
7047 | rs6000_generate_compare (code) | |
7048 | enum rtx_code code; | |
7049 | { | |
7050 | enum machine_mode comp_mode; | |
7051 | rtx compare_result; | |
7052 | ||
7053 | if (rs6000_compare_fp_p) | |
7054 | comp_mode = CCFPmode; | |
7055 | else if (code == GTU || code == LTU | |
7056 | || code == GEU || code == LEU) | |
7057 | comp_mode = CCUNSmode; | |
7058 | else | |
7059 | comp_mode = CCmode; | |
7060 | ||
7061 | /* First, the compare. */ | |
7062 | compare_result = gen_reg_rtx (comp_mode); | |
7063 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
7064 | gen_rtx_COMPARE (comp_mode, | |
7065 | rs6000_compare_op0, | |
7066 | rs6000_compare_op1))); | |
7067 | ||
ca5adc63 | 7068 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 7069 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 7070 | if (rs6000_compare_fp_p |
de6c5979 | 7071 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
7072 | && (code == LE || code == GE |
7073 | || code == UNEQ || code == LTGT | |
7074 | || code == UNGT || code == UNLT)) | |
7075 | { | |
7076 | enum rtx_code or1, or2; | |
7077 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
7078 | rtx or_result = gen_reg_rtx (CCEQmode); | |
7079 | ||
7080 | switch (code) | |
7081 | { | |
7082 | case LE: or1 = LT; or2 = EQ; break; | |
7083 | case GE: or1 = GT; or2 = EQ; break; | |
7084 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
7085 | case LTGT: or1 = LT; or2 = GT; break; | |
7086 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
7087 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
7088 | default: abort (); | |
7089 | } | |
7090 | validate_condition_mode (or1, comp_mode); | |
7091 | validate_condition_mode (or2, comp_mode); | |
7092 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
7093 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
7094 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
7095 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
7096 | const_true_rtx); | |
7097 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
7098 | ||
7099 | compare_result = or_result; | |
7100 | code = EQ; | |
7101 | } | |
7102 | ||
7103 | validate_condition_mode (code, GET_MODE (compare_result)); | |
7104 | ||
7105 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
7106 | } | |
7107 | ||
7108 | ||
7109 | /* Emit the RTL for an sCOND pattern. */ | |
7110 | ||
7111 | void | |
7112 | rs6000_emit_sCOND (code, result) | |
7113 | enum rtx_code code; | |
7114 | rtx result; | |
7115 | { | |
7116 | rtx condition_rtx; | |
7117 | enum machine_mode op_mode; | |
7118 | ||
7119 | condition_rtx = rs6000_generate_compare (code); | |
7120 | ||
7121 | op_mode = GET_MODE (rs6000_compare_op0); | |
7122 | if (op_mode == VOIDmode) | |
7123 | op_mode = GET_MODE (rs6000_compare_op1); | |
7124 | ||
7125 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
7126 | { | |
7127 | PUT_MODE (condition_rtx, DImode); | |
7128 | convert_move (result, condition_rtx, 0); | |
7129 | } | |
7130 | else | |
7131 | { | |
7132 | PUT_MODE (condition_rtx, SImode); | |
7133 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
7134 | } | |
7135 | } | |
7136 | ||
39a10a29 GK |
7137 | /* Emit a branch of kind CODE to location LOC. */ |
7138 | ||
7139 | void | |
7140 | rs6000_emit_cbranch (code, loc) | |
7141 | enum rtx_code code; | |
7142 | rtx loc; | |
7143 | { | |
7144 | rtx condition_rtx, loc_ref; | |
7145 | ||
7146 | condition_rtx = rs6000_generate_compare (code); | |
7147 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
7148 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
7149 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
7150 | loc_ref, pc_rtx))); | |
7151 | } | |
7152 | ||
12a4e8c5 GK |
7153 | /* Return the string to output a conditional branch to LABEL, which is |
7154 | the operand number of the label, or -1 if the branch is really a | |
7155 | conditional return. | |
7156 | ||
7157 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
7158 | condition code register and its mode specifies what kind of | |
7159 | comparison we made. | |
7160 | ||
7161 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
7162 | ||
7163 | INSN is the insn. */ | |
7164 | ||
7165 | char * | |
7166 | output_cbranch (op, label, reversed, insn) | |
7167 | rtx op; | |
7168 | const char * label; | |
7169 | int reversed; | |
7170 | rtx insn; | |
7171 | { | |
7172 | static char string[64]; | |
7173 | enum rtx_code code = GET_CODE (op); | |
7174 | rtx cc_reg = XEXP (op, 0); | |
7175 | enum machine_mode mode = GET_MODE (cc_reg); | |
7176 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 7177 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
7178 | int really_reversed = reversed ^ need_longbranch; |
7179 | char *s = string; | |
7180 | const char *ccode; | |
7181 | const char *pred; | |
7182 | rtx note; | |
7183 | ||
39a10a29 GK |
7184 | validate_condition_mode (code, mode); |
7185 | ||
7186 | /* Work out which way this really branches. We could use | |
7187 | reverse_condition_maybe_unordered here always but this | |
7188 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 7189 | if (really_reversed) |
39a10a29 | 7190 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 7191 | |
39a10a29 | 7192 | switch (code) |
12a4e8c5 GK |
7193 | { |
7194 | /* Not all of these are actually distinct opcodes, but | |
7195 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
7196 | case NE: case LTGT: |
7197 | ccode = "ne"; break; | |
7198 | case EQ: case UNEQ: | |
7199 | ccode = "eq"; break; | |
7200 | case GE: case GEU: | |
7201 | ccode = "ge"; break; | |
7202 | case GT: case GTU: case UNGT: | |
7203 | ccode = "gt"; break; | |
7204 | case LE: case LEU: | |
7205 | ccode = "le"; break; | |
7206 | case LT: case LTU: case UNLT: | |
7207 | ccode = "lt"; break; | |
12a4e8c5 GK |
7208 | case UNORDERED: ccode = "un"; break; |
7209 | case ORDERED: ccode = "nu"; break; | |
7210 | case UNGE: ccode = "nl"; break; | |
7211 | case UNLE: ccode = "ng"; break; | |
7212 | default: | |
a4f6c312 | 7213 | abort (); |
12a4e8c5 GK |
7214 | } |
7215 | ||
94a54f47 GK |
7216 | /* Maybe we have a guess as to how likely the branch is. |
7217 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
7218 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
7219 | if (note != NULL_RTX) | |
7220 | { | |
7221 | /* PROB is the difference from 50%. */ | |
7222 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
7223 | ||
7224 | /* For branches that are very close to 50%, assume not-taken. */ | |
7225 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
7226 | && ((prob > 0) ^ need_longbranch)) | |
7227 | pred = "+"; | |
7228 | else | |
7229 | pred = "-"; | |
7230 | } | |
7231 | else | |
7232 | pred = ""; | |
7233 | ||
7234 | if (label == NULL) | |
94a54f47 | 7235 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 7236 | else |
94a54f47 | 7237 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 7238 | |
37c67319 GK |
7239 | /* We need to escape any '%' characters in the reg_names string. |
7240 | Assume they'd only be the first character... */ | |
7241 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
7242 | *s++ = '%'; | |
94a54f47 | 7243 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
7244 | |
7245 | if (label != NULL) | |
7246 | { | |
7247 | /* If the branch distance was too far, we may have to use an | |
7248 | unconditional branch to go the distance. */ | |
7249 | if (need_longbranch) | |
44518ddd | 7250 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
7251 | else |
7252 | s += sprintf (s, ",%s", label); | |
7253 | } | |
7254 | ||
7255 | return string; | |
7256 | } | |
50a0b056 GK |
7257 | |
7258 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
7259 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
7260 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 7261 | |
50a0b056 GK |
7262 | int |
7263 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
7264 | rtx dest; | |
7265 | rtx op; | |
7266 | rtx true_cond; | |
7267 | rtx false_cond; | |
7268 | { | |
7269 | enum rtx_code code = GET_CODE (op); | |
7270 | rtx op0 = rs6000_compare_op0; | |
7271 | rtx op1 = rs6000_compare_op1; | |
7272 | REAL_VALUE_TYPE c1; | |
7273 | enum machine_mode mode = GET_MODE (op0); | |
7274 | rtx temp; | |
7275 | ||
7276 | /* First, work out if the hardware can do this at all, or | |
7277 | if it's too slow... */ | |
7278 | /* If the comparison is an integer one, since we only have fsel | |
7279 | it'll be cheaper to use a branch. */ | |
7280 | if (! rs6000_compare_fp_p) | |
7281 | return 0; | |
7282 | ||
7283 | /* Eliminate half of the comparisons by switching operands, this | |
7284 | makes the remaining code simpler. */ | |
7285 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
7286 | || code == LTGT || code == LT) | |
7287 | { | |
7288 | code = reverse_condition_maybe_unordered (code); | |
7289 | temp = true_cond; | |
7290 | true_cond = false_cond; | |
7291 | false_cond = temp; | |
7292 | } | |
7293 | ||
7294 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
7295 | it'll probably be faster to use a branch here too. */ | |
7296 | if (code == UNEQ) | |
7297 | return 0; | |
7298 | ||
7299 | if (GET_CODE (op1) == CONST_DOUBLE) | |
7300 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
7301 | ||
7302 | /* We're going to try to implement comparions by performing | |
7303 | a subtract, then comparing against zero. Unfortunately, | |
7304 | Inf - Inf is NaN which is not zero, and so if we don't | |
7305 | know that the the operand is finite and the comparison | |
7306 | would treat EQ different to UNORDERED, we can't do it. */ | |
7307 | if (! flag_unsafe_math_optimizations | |
7308 | && code != GT && code != UNGE | |
7309 | && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) | |
7310 | /* Constructs of the form (a OP b ? a : b) are safe. */ | |
7311 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
7312 | || (! rtx_equal_p (op0, true_cond) | |
7313 | && ! rtx_equal_p (op1, true_cond)))) | |
7314 | return 0; | |
7315 | /* At this point we know we can use fsel. */ | |
7316 | ||
7317 | /* Reduce the comparison to a comparison against zero. */ | |
7318 | temp = gen_reg_rtx (mode); | |
7319 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
7320 | gen_rtx_MINUS (mode, op0, op1))); | |
7321 | op0 = temp; | |
7322 | op1 = CONST0_RTX (mode); | |
7323 | ||
7324 | /* If we don't care about NaNs we can reduce some of the comparisons | |
7325 | down to faster ones. */ | |
7326 | if (flag_unsafe_math_optimizations) | |
7327 | switch (code) | |
7328 | { | |
7329 | case GT: | |
7330 | code = LE; | |
7331 | temp = true_cond; | |
7332 | true_cond = false_cond; | |
7333 | false_cond = temp; | |
7334 | break; | |
7335 | case UNGE: | |
7336 | code = GE; | |
7337 | break; | |
7338 | case UNEQ: | |
7339 | code = EQ; | |
7340 | break; | |
7341 | default: | |
7342 | break; | |
7343 | } | |
7344 | ||
7345 | /* Now, reduce everything down to a GE. */ | |
7346 | switch (code) | |
7347 | { | |
7348 | case GE: | |
7349 | break; | |
7350 | ||
7351 | case LE: | |
7352 | temp = gen_reg_rtx (mode); | |
7353 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
7354 | op0 = temp; | |
7355 | break; | |
7356 | ||
7357 | case ORDERED: | |
7358 | temp = gen_reg_rtx (mode); | |
7359 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0))); | |
7360 | op0 = temp; | |
7361 | break; | |
7362 | ||
7363 | case EQ: | |
7364 | temp = gen_reg_rtx (mode); | |
7365 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
7366 | gen_rtx_NEG (mode, | |
7367 | gen_rtx_ABS (mode, op0)))); | |
7368 | op0 = temp; | |
7369 | break; | |
7370 | ||
7371 | case UNGE: | |
7372 | temp = gen_reg_rtx (mode); | |
7373 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
7374 | gen_rtx_IF_THEN_ELSE (mode, | |
7375 | gen_rtx_GE (VOIDmode, | |
7376 | op0, op1), | |
7377 | true_cond, false_cond))); | |
7378 | false_cond = temp; | |
7379 | true_cond = false_cond; | |
7380 | ||
7381 | temp = gen_reg_rtx (mode); | |
7382 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
7383 | op0 = temp; | |
7384 | break; | |
7385 | ||
7386 | case GT: | |
7387 | temp = gen_reg_rtx (mode); | |
7388 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
7389 | gen_rtx_IF_THEN_ELSE (mode, | |
7390 | gen_rtx_GE (VOIDmode, | |
7391 | op0, op1), | |
7392 | true_cond, false_cond))); | |
7393 | true_cond = temp; | |
7394 | false_cond = true_cond; | |
7395 | ||
7396 | temp = gen_reg_rtx (mode); | |
7397 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
7398 | op0 = temp; | |
7399 | break; | |
7400 | ||
7401 | default: | |
7402 | abort (); | |
7403 | } | |
7404 | ||
7405 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
9f1a9740 | 7406 | gen_rtx_IF_THEN_ELSE (GET_MODE (dest), |
50a0b056 GK |
7407 | gen_rtx_GE (VOIDmode, |
7408 | op0, op1), | |
7409 | true_cond, false_cond))); | |
7410 | return 1; | |
7411 | } | |
7412 | ||
7413 | void | |
7414 | rs6000_emit_minmax (dest, code, op0, op1) | |
7415 | rtx dest; | |
7416 | enum rtx_code code; | |
7417 | rtx op0; | |
7418 | rtx op1; | |
7419 | { | |
7420 | enum machine_mode mode = GET_MODE (op0); | |
7421 | rtx target; | |
7422 | if (code == SMAX || code == UMAX) | |
7423 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
7424 | op0, op1, mode, 0); | |
7425 | else | |
7426 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
7427 | op1, op0, mode, 0); | |
7428 | if (target == NULL_RTX) | |
7429 | abort (); | |
7430 | if (target != dest) | |
7431 | emit_move_insn (dest, target); | |
7432 | } | |
12a4e8c5 | 7433 | \f |
a4f6c312 SS |
7434 | /* This page contains routines that are used to determine what the |
7435 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 7436 | |
a4f6c312 SS |
7437 | /* Return the first fixed-point register that is required to be |
7438 | saved. 32 if none. */ | |
9878760c RK |
7439 | |
7440 | int | |
7441 | first_reg_to_save () | |
7442 | { | |
7443 | int first_reg; | |
7444 | ||
7445 | /* Find lowest numbered live register. */ | |
7446 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
7447 | if (regs_ever_live[first_reg] |
7448 | && (! call_used_regs[first_reg] | |
7449 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
7450 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
7451 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) | |
9878760c RK |
7452 | break; |
7453 | ||
70f4f91c | 7454 | if (current_function_profile) |
b5253831 DE |
7455 | { |
7456 | /* AIX must save/restore every register that contains a parameter | |
7457 | before/after the .__mcount call plus an additional register | |
7458 | for the static chain, if needed; use registers from 30 down to 22 | |
7459 | to do this. */ | |
ee890fe2 | 7460 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
b5253831 DE |
7461 | { |
7462 | int last_parm_reg, profile_first_reg; | |
7463 | ||
7464 | /* Figure out last used parameter register. The proper thing | |
7465 | to do is to walk incoming args of the function. A function | |
7466 | might have live parameter registers even if it has no | |
7467 | incoming args. */ | |
7468 | for (last_parm_reg = 10; | |
7469 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
7470 | last_parm_reg--) | |
7471 | ; | |
7472 | ||
7473 | /* Calculate first reg for saving parameter registers | |
7474 | and static chain. | |
7475 | Skip reg 31 which may contain the frame pointer. */ | |
7476 | profile_first_reg = (33 - last_parm_reg | |
7477 | - (current_function_needs_context ? 1 : 0)); | |
ee890fe2 SS |
7478 | #if TARGET_MACHO |
7479 | /* Need to skip another reg to account for R31 being PICBASE | |
7480 | (when flag_pic is set) or R30 being used as the frame | |
7481 | pointer (when flag_pic is not set). */ | |
7482 | --profile_first_reg; | |
7483 | #endif | |
b5253831 DE |
7484 | /* Do not save frame pointer if no parameters needs to be saved. */ |
7485 | if (profile_first_reg == 31) | |
7486 | profile_first_reg = 32; | |
7487 | ||
7488 | if (first_reg > profile_first_reg) | |
7489 | first_reg = profile_first_reg; | |
7490 | } | |
e165f3f0 | 7491 | |
b5253831 DE |
7492 | /* SVR4 may need one register to preserve the static chain. */ |
7493 | else if (current_function_needs_context) | |
7494 | { | |
7495 | /* Skip reg 31 which may contain the frame pointer. */ | |
7496 | if (first_reg > 30) | |
7497 | first_reg = 30; | |
7498 | } | |
7499 | } | |
e165f3f0 | 7500 | |
ee890fe2 SS |
7501 | #if TARGET_MACHO |
7502 | if (flag_pic && current_function_uses_pic_offset_table && | |
7503 | (first_reg > PIC_OFFSET_TABLE_REGNUM)) | |
7504 | return PIC_OFFSET_TABLE_REGNUM; | |
7505 | #endif | |
7506 | ||
9878760c RK |
7507 | return first_reg; |
7508 | } | |
7509 | ||
7510 | /* Similar, for FP regs. */ | |
7511 | ||
7512 | int | |
7513 | first_fp_reg_to_save () | |
7514 | { | |
7515 | int first_reg; | |
7516 | ||
7517 | /* Find lowest numbered live register. */ | |
7518 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
7519 | if (regs_ever_live[first_reg]) | |
7520 | break; | |
7521 | ||
7522 | return first_reg; | |
7523 | } | |
00b960c7 AH |
7524 | |
7525 | /* Similar, for AltiVec regs. */ | |
7526 | ||
7527 | static int | |
7528 | first_altivec_reg_to_save () | |
7529 | { | |
7530 | int i; | |
7531 | ||
7532 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
7533 | if (! TARGET_ALTIVEC_ABI) | |
7534 | return LAST_ALTIVEC_REGNO + 1; | |
7535 | ||
7536 | /* Find lowest numbered live register. */ | |
7537 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
7538 | if (regs_ever_live[i]) | |
7539 | break; | |
7540 | ||
7541 | return i; | |
7542 | } | |
7543 | ||
7544 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
7545 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
7546 | the 32-bit word is 0. */ | |
7547 | ||
7548 | static unsigned int | |
7549 | compute_vrsave_mask () | |
7550 | { | |
7551 | unsigned int i, mask = 0; | |
7552 | ||
7553 | /* First, find out if we use _any_ altivec registers. */ | |
7554 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
7555 | if (regs_ever_live[i]) | |
7556 | mask |= ALTIVEC_REG_BIT (i); | |
7557 | ||
7558 | if (mask == 0) | |
7559 | return mask; | |
7560 | ||
7561 | /* Next, add all registers that are call-clobbered. We do this | |
7562 | because post-reload register optimizers such as regrename_optimize | |
7563 | may choose to use them. They never change the register class | |
7564 | chosen by reload, so cannot create new uses of altivec registers | |
7565 | if there were none before, so the early exit above is safe. */ | |
7566 | /* ??? Alternately, we could define HARD_REGNO_RENAME_OK to disallow | |
7567 | altivec registers not saved in the mask, which might well make the | |
7568 | adjustments below more effective in eliding the save/restore of | |
7569 | VRSAVE in small functions. */ | |
7570 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
7571 | if (call_used_regs[i]) | |
7572 | mask |= ALTIVEC_REG_BIT (i); | |
7573 | ||
7574 | /* Next, remove the argument registers from the set. These must | |
7575 | be in the VRSAVE mask set by the caller, so we don't need to add | |
7576 | them in again. More importantly, the mask we compute here is | |
7577 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
7578 | wish the argument registers to die. */ | |
7579 | for (i = cfun->args_info.vregno; i >= ALTIVEC_ARG_MIN_REG; --i) | |
7580 | mask &= ~ALTIVEC_REG_BIT (i); | |
7581 | ||
7582 | /* Similarly, remove the return value from the set. */ | |
7583 | { | |
7584 | bool yes = false; | |
7585 | diddle_return_value (is_altivec_return_reg, &yes); | |
7586 | if (yes) | |
7587 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
7588 | } | |
7589 | ||
7590 | return mask; | |
7591 | } | |
7592 | ||
7593 | static void | |
7594 | is_altivec_return_reg (reg, xyes) | |
7595 | rtx reg; | |
7596 | void *xyes; | |
7597 | { | |
7598 | bool *yes = (bool *) xyes; | |
7599 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
7600 | *yes = true; | |
7601 | } | |
7602 | ||
4697a36c MM |
7603 | \f |
7604 | /* Calculate the stack information for the current function. This is | |
7605 | complicated by having two separate calling sequences, the AIX calling | |
7606 | sequence and the V.4 calling sequence. | |
7607 | ||
592696dd | 7608 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 7609 | 32-bit 64-bit |
4697a36c | 7610 | SP----> +---------------------------------------+ |
a260abc9 | 7611 | | back chain to caller | 0 0 |
4697a36c | 7612 | +---------------------------------------+ |
a260abc9 | 7613 | | saved CR | 4 8 (8-11) |
4697a36c | 7614 | +---------------------------------------+ |
a260abc9 | 7615 | | saved LR | 8 16 |
4697a36c | 7616 | +---------------------------------------+ |
a260abc9 | 7617 | | reserved for compilers | 12 24 |
4697a36c | 7618 | +---------------------------------------+ |
a260abc9 | 7619 | | reserved for binders | 16 32 |
4697a36c | 7620 | +---------------------------------------+ |
a260abc9 | 7621 | | saved TOC pointer | 20 40 |
4697a36c | 7622 | +---------------------------------------+ |
a260abc9 | 7623 | | Parameter save area (P) | 24 48 |
4697a36c | 7624 | +---------------------------------------+ |
a260abc9 | 7625 | | Alloca space (A) | 24+P etc. |
802a0058 | 7626 | +---------------------------------------+ |
a7df97e6 | 7627 | | Local variable space (L) | 24+P+A |
4697a36c | 7628 | +---------------------------------------+ |
a7df97e6 | 7629 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 7630 | +---------------------------------------+ |
00b960c7 AH |
7631 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
7632 | +---------------------------------------+ | |
7633 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
7634 | +---------------------------------------+ | |
7635 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 7636 | +---------------------------------------+ |
00b960c7 AH |
7637 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
7638 | +---------------------------------------+ | |
7639 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
7640 | +---------------------------------------+ |
7641 | old SP->| back chain to caller's caller | | |
7642 | +---------------------------------------+ | |
7643 | ||
5376a30c KR |
7644 | The required alignment for AIX configurations is two words (i.e., 8 |
7645 | or 16 bytes). | |
7646 | ||
7647 | ||
4697a36c MM |
7648 | V.4 stack frames look like: |
7649 | ||
7650 | SP----> +---------------------------------------+ | |
7651 | | back chain to caller | 0 | |
7652 | +---------------------------------------+ | |
5eb387b8 | 7653 | | caller's saved LR | 4 |
4697a36c MM |
7654 | +---------------------------------------+ |
7655 | | Parameter save area (P) | 8 | |
7656 | +---------------------------------------+ | |
a7df97e6 MM |
7657 | | Alloca space (A) | 8+P |
7658 | +---------------------------------------+ | |
7659 | | Varargs save area (V) | 8+P+A | |
7660 | +---------------------------------------+ | |
7661 | | Local variable space (L) | 8+P+A+V | |
7662 | +---------------------------------------+ | |
7663 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 7664 | +---------------------------------------+ |
00b960c7 AH |
7665 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
7666 | +---------------------------------------+ | |
7667 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
7668 | +---------------------------------------+ | |
7669 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
7670 | +---------------------------------------+ | |
7671 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z | |
a7df97e6 | 7672 | +---------------------------------------+ |
00b960c7 | 7673 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 7674 | +---------------------------------------+ |
00b960c7 | 7675 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
7676 | +---------------------------------------+ |
7677 | old SP->| back chain to caller's caller | | |
7678 | +---------------------------------------+ | |
b6c9286a | 7679 | |
5376a30c KR |
7680 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
7681 | given. (But note below and in sysv4.h that we require only 8 and | |
7682 | may round up the size of our stack frame anyways. The historical | |
7683 | reason is early versions of powerpc-linux which didn't properly | |
7684 | align the stack at program startup. A happy side-effect is that | |
7685 | -mno-eabi libraries can be used with -meabi programs.) | |
7686 | ||
5376a30c KR |
7687 | The EABI configuration defaults to the V.4 layout, unless |
7688 | -mcall-aix is used, in which case the AIX layout is used. However, | |
7689 | the stack alignment requirements may differ. If -mno-eabi is not | |
7690 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
7691 | given, the required alignment is 16 bytes. (But see V.4 comment | |
7692 | above.) */ | |
4697a36c | 7693 | |
61b2fbe7 MM |
7694 | #ifndef ABI_STACK_BOUNDARY |
7695 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
7696 | #endif | |
7697 | ||
4697a36c MM |
7698 | rs6000_stack_t * |
7699 | rs6000_stack_info () | |
7700 | { | |
7701 | static rs6000_stack_t info, zero_info; | |
7702 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 7703 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 7704 | enum rs6000_abi abi; |
83720594 | 7705 | int ehrd_size; |
b6c9286a | 7706 | int total_raw_size; |
4697a36c | 7707 | |
a4f6c312 | 7708 | /* Zero all fields portably. */ |
4697a36c MM |
7709 | info = zero_info; |
7710 | ||
a4f6c312 | 7711 | /* Select which calling sequence. */ |
b6c9286a | 7712 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 7713 | |
a4f6c312 | 7714 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 7715 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
906fb125 GK |
7716 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
7717 | even if it currently looks like we won't. */ | |
2bfcf297 | 7718 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
f607bc57 ZW |
7719 | || (flag_pic == 1 && abi == ABI_V4) |
7720 | || (flag_pic && abi == ABI_DARWIN)) | |
906fb125 GK |
7721 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) |
7722 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
7723 | else | |
7724 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
7725 | |
7726 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
7727 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
7728 | ||
00b960c7 AH |
7729 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
7730 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
7731 | - info_ptr->first_altivec_reg_save); | |
7732 | ||
592696dd | 7733 | /* Does this function call anything? */ |
71f123ca FS |
7734 | info_ptr->calls_p = (! current_function_is_leaf |
7735 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 7736 | |
a4f6c312 | 7737 | /* Determine if we need to save the link register. */ |
71f123ca | 7738 | if (rs6000_ra_ever_killed () |
70f4f91c | 7739 | || (DEFAULT_ABI == ABI_AIX && current_function_profile) |
4697a36c MM |
7740 | #ifdef TARGET_RELOCATABLE |
7741 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
7742 | #endif | |
7743 | || (info_ptr->first_fp_reg_save != 64 | |
7744 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 7745 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
24d304eb | 7746 | || (abi == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
7747 | || (DEFAULT_ABI == ABI_DARWIN |
7748 | && flag_pic | |
7749 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
7750 | || info_ptr->calls_p) |
7751 | { | |
7752 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 7753 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
7754 | } |
7755 | ||
9ebbca7d GK |
7756 | /* Determine if we need to save the condition code registers. */ |
7757 | if (regs_ever_live[CR2_REGNO] | |
7758 | || regs_ever_live[CR3_REGNO] | |
7759 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
7760 | { |
7761 | info_ptr->cr_save_p = 1; | |
f607bc57 | 7762 | if (abi == ABI_V4) |
4697a36c MM |
7763 | info_ptr->cr_size = reg_size; |
7764 | } | |
7765 | ||
83720594 RH |
7766 | /* If the current function calls __builtin_eh_return, then we need |
7767 | to allocate stack space for registers that will hold data for | |
7768 | the exception handler. */ | |
7769 | if (current_function_calls_eh_return) | |
7770 | { | |
7771 | unsigned int i; | |
7772 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
7773 | continue; | |
7774 | ehrd_size = i * UNITS_PER_WORD; | |
7775 | } | |
7776 | else | |
7777 | ehrd_size = 0; | |
7778 | ||
592696dd | 7779 | /* Determine various sizes. */ |
4697a36c MM |
7780 | info_ptr->reg_size = reg_size; |
7781 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
7782 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 7783 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 SS |
7784 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
7785 | 8); | |
00b960c7 AH |
7786 | |
7787 | if (TARGET_ALTIVEC_ABI) | |
7788 | { | |
7789 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
7790 | info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0; | |
7791 | } | |
7792 | else | |
7793 | { | |
7794 | info_ptr->vrsave_mask = 0; | |
7795 | info_ptr->vrsave_size = 0; | |
7796 | } | |
b6c9286a | 7797 | |
592696dd | 7798 | /* Calculate the offsets. */ |
24d304eb | 7799 | switch (abi) |
4697a36c | 7800 | { |
b6c9286a | 7801 | case ABI_NONE: |
24d304eb | 7802 | default: |
b6c9286a MM |
7803 | abort (); |
7804 | ||
7805 | case ABI_AIX: | |
7806 | case ABI_AIX_NODESC: | |
ee890fe2 | 7807 | case ABI_DARWIN: |
b6c9286a MM |
7808 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
7809 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
7810 | |
7811 | if (TARGET_ALTIVEC_ABI) | |
7812 | { | |
7813 | info_ptr->vrsave_save_offset | |
7814 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
7815 | ||
7816 | /* Align stack so vector save area is on a quadword boundary. */ | |
7817 | if (info_ptr->altivec_size != 0) | |
7818 | info_ptr->altivec_padding_size | |
7819 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
7820 | else | |
7821 | info_ptr->altivec_padding_size = 0; | |
7822 | ||
7823 | info_ptr->altivec_save_offset | |
7824 | = info_ptr->vrsave_save_offset | |
7825 | - info_ptr->altivec_padding_size | |
7826 | - info_ptr->altivec_size; | |
7827 | ||
7828 | /* Adjust for AltiVec case. */ | |
7829 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
7830 | } | |
7831 | else | |
7832 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
7833 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
7834 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
7835 | break; |
7836 | ||
7837 | case ABI_V4: | |
b6c9286a MM |
7838 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
7839 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 7840 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 AH |
7841 | |
7842 | if (TARGET_ALTIVEC_ABI) | |
7843 | { | |
7844 | info_ptr->vrsave_save_offset | |
7845 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
7846 | ||
7847 | /* Align stack so vector save area is on a quadword boundary. */ | |
7848 | if (info_ptr->altivec_size != 0) | |
7849 | info_ptr->altivec_padding_size | |
7850 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
7851 | else | |
7852 | info_ptr->altivec_padding_size = 0; | |
7853 | ||
7854 | info_ptr->altivec_save_offset | |
7855 | = info_ptr->vrsave_save_offset | |
7856 | - info_ptr->altivec_padding_size | |
7857 | - info_ptr->altivec_size; | |
7858 | ||
7859 | /* Adjust for AltiVec case. */ | |
7860 | info_ptr->toc_save_offset | |
7861 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
7862 | } | |
7863 | else | |
7864 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 7865 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
7866 | info_ptr->lr_save_offset = reg_size; |
7867 | break; | |
4697a36c MM |
7868 | } |
7869 | ||
00b960c7 AH |
7870 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
7871 | + info_ptr->gp_size | |
7872 | + info_ptr->altivec_size | |
7873 | + info_ptr->altivec_padding_size | |
7874 | + info_ptr->vrsave_size | |
7875 | + ehrd_size | |
7876 | + info_ptr->cr_size | |
7877 | + info_ptr->lr_size | |
7878 | + info_ptr->vrsave_size | |
7879 | + info_ptr->toc_size, | |
7880 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
7881 | ? 16 : 8); | |
7882 | ||
ff381587 MM |
7883 | total_raw_size = (info_ptr->vars_size |
7884 | + info_ptr->parm_size | |
ff381587 MM |
7885 | + info_ptr->save_size |
7886 | + info_ptr->varargs_size | |
7887 | + info_ptr->fixed_size); | |
7888 | ||
a4f6c312 SS |
7889 | info_ptr->total_size = |
7890 | RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
7891 | |
7892 | /* Determine if we need to allocate any stack frame: | |
7893 | ||
a4f6c312 SS |
7894 | For AIX we need to push the stack if a frame pointer is needed |
7895 | (because the stack might be dynamically adjusted), if we are | |
7896 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
7897 | and local variables are more than the space needed to save all | |
7898 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
7899 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 7900 | |
a4f6c312 SS |
7901 | For V.4 we don't have the stack cushion that AIX uses, but assume |
7902 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
7903 | |
7904 | if (info_ptr->calls_p) | |
7905 | info_ptr->push_p = 1; | |
7906 | ||
f607bc57 | 7907 | else if (abi == ABI_V4) |
e72247f4 | 7908 | info_ptr->push_p = total_raw_size > info_ptr->fixed_size; |
ff381587 MM |
7909 | |
7910 | else | |
7911 | info_ptr->push_p = (frame_pointer_needed | |
ee890fe2 | 7912 | || (abi != ABI_DARWIN && write_symbols != NO_DEBUG) |
ff381587 | 7913 | || ((total_raw_size - info_ptr->fixed_size) |
bfc79d3b | 7914 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 7915 | |
a4f6c312 | 7916 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 7917 | if (info_ptr->fp_size == 0) |
4697a36c MM |
7918 | info_ptr->fp_save_offset = 0; |
7919 | ||
8dda1a21 | 7920 | if (info_ptr->gp_size == 0) |
4697a36c MM |
7921 | info_ptr->gp_save_offset = 0; |
7922 | ||
00b960c7 AH |
7923 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
7924 | info_ptr->altivec_save_offset = 0; | |
7925 | ||
7926 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
7927 | info_ptr->vrsave_save_offset = 0; | |
7928 | ||
c81fc13e | 7929 | if (! info_ptr->lr_save_p) |
4697a36c MM |
7930 | info_ptr->lr_save_offset = 0; |
7931 | ||
c81fc13e | 7932 | if (! info_ptr->cr_save_p) |
4697a36c MM |
7933 | info_ptr->cr_save_offset = 0; |
7934 | ||
c81fc13e | 7935 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
7936 | info_ptr->toc_save_offset = 0; |
7937 | ||
4697a36c MM |
7938 | return info_ptr; |
7939 | } | |
7940 | ||
7941 | void | |
7942 | debug_stack_info (info) | |
7943 | rs6000_stack_t *info; | |
9878760c | 7944 | { |
d330fd93 | 7945 | const char *abi_string; |
24d304eb | 7946 | |
c81fc13e | 7947 | if (! info) |
4697a36c MM |
7948 | info = rs6000_stack_info (); |
7949 | ||
7950 | fprintf (stderr, "\nStack information for function %s:\n", | |
7951 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
7952 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
7953 | : "<unknown>")); | |
7954 | ||
24d304eb RK |
7955 | switch (info->abi) |
7956 | { | |
b6c9286a MM |
7957 | default: abi_string = "Unknown"; break; |
7958 | case ABI_NONE: abi_string = "NONE"; break; | |
f607bc57 | 7959 | case ABI_AIX: |
b6c9286a | 7960 | case ABI_AIX_NODESC: abi_string = "AIX"; break; |
ee890fe2 | 7961 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 7962 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
7963 | } |
7964 | ||
7965 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
7966 | ||
00b960c7 AH |
7967 | if (TARGET_ALTIVEC_ABI) |
7968 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
7969 | ||
4697a36c MM |
7970 | if (info->first_gp_reg_save != 32) |
7971 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
7972 | ||
7973 | if (info->first_fp_reg_save != 64) | |
7974 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 7975 | |
00b960c7 AH |
7976 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
7977 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
7978 | info->first_altivec_reg_save); | |
7979 | ||
4697a36c MM |
7980 | if (info->lr_save_p) |
7981 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 7982 | |
4697a36c MM |
7983 | if (info->cr_save_p) |
7984 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
7985 | ||
b6c9286a MM |
7986 | if (info->toc_save_p) |
7987 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
7988 | ||
00b960c7 AH |
7989 | if (info->vrsave_mask) |
7990 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
7991 | ||
4697a36c MM |
7992 | if (info->push_p) |
7993 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
7994 | ||
7995 | if (info->calls_p) | |
7996 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
7997 | ||
4697a36c MM |
7998 | if (info->gp_save_offset) |
7999 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
8000 | ||
8001 | if (info->fp_save_offset) | |
8002 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
8003 | ||
00b960c7 AH |
8004 | if (info->altivec_save_offset) |
8005 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
8006 | info->altivec_save_offset); | |
8007 | ||
8008 | if (info->vrsave_save_offset) | |
8009 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
8010 | info->vrsave_save_offset); | |
8011 | ||
4697a36c MM |
8012 | if (info->lr_save_offset) |
8013 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
8014 | ||
8015 | if (info->cr_save_offset) | |
8016 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
8017 | ||
b6c9286a MM |
8018 | if (info->toc_save_offset) |
8019 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
8020 | ||
4697a36c MM |
8021 | if (info->varargs_save_offset) |
8022 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
8023 | ||
8024 | if (info->total_size) | |
8025 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
8026 | ||
8027 | if (info->varargs_size) | |
8028 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
8029 | ||
8030 | if (info->vars_size) | |
8031 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
8032 | ||
8033 | if (info->parm_size) | |
8034 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
8035 | ||
8036 | if (info->fixed_size) | |
8037 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
8038 | ||
8039 | if (info->gp_size) | |
8040 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
8041 | ||
8042 | if (info->fp_size) | |
8043 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
8044 | ||
00b960c7 AH |
8045 | if (info->altivec_size) |
8046 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
8047 | ||
8048 | if (info->vrsave_size) | |
8049 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
8050 | ||
8051 | if (info->altivec_padding_size) | |
8052 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
8053 | info->altivec_padding_size); | |
8054 | ||
a4f6c312 | 8055 | if (info->lr_size) |
ed947a96 | 8056 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 8057 | |
4697a36c MM |
8058 | if (info->cr_size) |
8059 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
8060 | ||
a4f6c312 | 8061 | if (info->toc_size) |
b6c9286a MM |
8062 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
8063 | ||
4697a36c MM |
8064 | if (info->save_size) |
8065 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
8066 | ||
8067 | if (info->reg_size != 4) | |
8068 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
8069 | ||
8070 | fprintf (stderr, "\n"); | |
9878760c | 8071 | } |
71f123ca FS |
8072 | |
8073 | rtx | |
8074 | rs6000_return_addr (count, frame) | |
8075 | int count; | |
8076 | rtx frame; | |
8077 | { | |
a4f6c312 SS |
8078 | /* Currently we don't optimize very well between prolog and body |
8079 | code and for PIC code the code can be actually quite bad, so | |
8080 | don't try to be too clever here. */ | |
f585a356 | 8081 | if (count != 0 || flag_pic != 0) |
71f123ca FS |
8082 | { |
8083 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
8084 | |
8085 | return | |
8086 | gen_rtx_MEM | |
8087 | (Pmode, | |
8088 | memory_address | |
8089 | (Pmode, | |
8090 | plus_constant (copy_to_reg | |
8091 | (gen_rtx_MEM (Pmode, | |
8092 | memory_address (Pmode, frame))), | |
8093 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
8094 | } |
8095 | ||
9e2f7ec7 | 8096 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
8097 | } |
8098 | ||
8099 | static int | |
8100 | rs6000_ra_ever_killed () | |
8101 | { | |
8102 | rtx top; | |
8103 | ||
8104 | #ifdef ASM_OUTPUT_MI_THUNK | |
8105 | if (current_function_is_thunk) | |
8106 | return 0; | |
8107 | #endif | |
9e2f7ec7 DD |
8108 | if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) |
8109 | || cfun->machine->ra_needs_full_frame) | |
71f123ca FS |
8110 | return regs_ever_live[LINK_REGISTER_REGNUM]; |
8111 | ||
8112 | push_topmost_sequence (); | |
8113 | top = get_insns (); | |
8114 | pop_topmost_sequence (); | |
8115 | ||
8116 | return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
8117 | top, NULL_RTX); | |
8118 | } | |
4697a36c | 8119 | \f |
8cd8f856 GK |
8120 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
8121 | static void | |
8122 | rs6000_maybe_dead (insn) | |
8123 | rtx insn; | |
8124 | { | |
8125 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
8126 | const0_rtx, | |
8127 | REG_NOTES (insn)); | |
8128 | } | |
8129 | ||
9ebbca7d | 8130 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 8131 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 8132 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
8133 | |
8134 | void | |
9ebbca7d GK |
8135 | rs6000_emit_load_toc_table (fromprolog) |
8136 | int fromprolog; | |
c7ca610e | 8137 | { |
9ebbca7d GK |
8138 | rtx dest; |
8139 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 8140 | |
2bfcf297 | 8141 | if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) |
c7ca610e | 8142 | { |
f607bc57 | 8143 | if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
38c1f2d7 | 8144 | { |
9ebbca7d GK |
8145 | rtx temp = (fromprolog |
8146 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
8147 | : gen_reg_rtx (Pmode)); | |
2bfcf297 | 8148 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
8cd8f856 | 8149 | rs6000_maybe_dead (emit_move_insn (dest, temp)); |
38c1f2d7 | 8150 | } |
9ebbca7d GK |
8151 | else if (flag_pic == 2) |
8152 | { | |
8153 | char buf[30]; | |
8154 | rtx tempLR = (fromprolog | |
8155 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
8156 | : gen_reg_rtx (Pmode)); | |
8157 | rtx temp0 = (fromprolog | |
8158 | ? gen_rtx_REG (Pmode, 0) | |
8159 | : gen_reg_rtx (Pmode)); | |
8160 | rtx symF; | |
8161 | ||
8162 | /* possibly create the toc section */ | |
8163 | if (! toc_initialized) | |
8164 | { | |
8165 | toc_section (); | |
8166 | function_section (current_function_decl); | |
8167 | } | |
8168 | ||
8169 | if (fromprolog) | |
8170 | { | |
8171 | rtx symL; | |
8172 | ||
8173 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
a8a05998 | 8174 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 8175 | |
9ebbca7d | 8176 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
a8a05998 | 8177 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 8178 | |
8cd8f856 GK |
8179 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
8180 | symF))); | |
8181 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
8182 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
8183 | symL, | |
8184 | symF))); | |
9ebbca7d GK |
8185 | } |
8186 | else | |
8187 | { | |
8188 | rtx tocsym; | |
8189 | static int reload_toc_labelno = 0; | |
8190 | ||
b999aaeb | 8191 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); |
38c1f2d7 | 8192 | |
9ebbca7d | 8193 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
a8a05998 | 8194 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 8195 | |
8cd8f856 GK |
8196 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
8197 | symF, | |
8198 | tocsym))); | |
8199 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
8200 | rs6000_maybe_dead (emit_move_insn (temp0, | |
8201 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 8202 | } |
8cd8f856 | 8203 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
8204 | } |
8205 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
8206 | { | |
8207 | /* This is for AIX code running in non-PIC ELF. */ | |
8208 | char buf[30]; | |
8209 | rtx realsym; | |
38c1f2d7 | 8210 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
a8a05998 | 8211 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 8212 | |
8cd8f856 GK |
8213 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
8214 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
8215 | } |
8216 | else | |
a4f6c312 | 8217 | abort (); |
9ebbca7d GK |
8218 | } |
8219 | else | |
8220 | { | |
8221 | if (TARGET_32BIT) | |
8cd8f856 | 8222 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 8223 | else |
8cd8f856 | 8224 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
8225 | } |
8226 | } | |
8227 | ||
8228 | int | |
8229 | get_TOC_alias_set () | |
8230 | { | |
8231 | static int set = -1; | |
8232 | if (set == -1) | |
8233 | set = new_alias_set (); | |
8234 | return set; | |
8235 | } | |
8236 | ||
8237 | /* This retuns nonzero if the current function uses the TOC. This is | |
8238 | determined by the presence of (unspec ... 7), which is generated by | |
8239 | the various load_toc_* patterns. */ | |
a4f6c312 | 8240 | |
9ebbca7d GK |
8241 | int |
8242 | uses_TOC () | |
8243 | { | |
8244 | rtx insn; | |
38c1f2d7 | 8245 | |
9ebbca7d | 8246 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 8247 | if (INSN_P (insn)) |
9ebbca7d GK |
8248 | { |
8249 | rtx pat = PATTERN (insn); | |
8250 | int i; | |
8251 | ||
8cd8f856 | 8252 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
8253 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
8254 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
8255 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
8256 | return 1; | |
38c1f2d7 | 8257 | } |
9ebbca7d GK |
8258 | return 0; |
8259 | } | |
38c1f2d7 | 8260 | |
9ebbca7d | 8261 | rtx |
a4f6c312 | 8262 | create_TOC_reference (symbol) |
9ebbca7d GK |
8263 | rtx symbol; |
8264 | { | |
a8a05998 ZW |
8265 | return gen_rtx_PLUS (Pmode, |
8266 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
8267 | gen_rtx_CONST (Pmode, | |
8268 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 8269 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 8270 | } |
38c1f2d7 | 8271 | |
9ebbca7d GK |
8272 | #if TARGET_AIX |
8273 | /* __throw will restore its own return address to be the same as the | |
8274 | return address of the function that the throw is being made to. | |
8275 | This is unfortunate, because we want to check the original | |
8276 | return address to see if we need to restore the TOC. | |
8277 | So we have to squirrel it away here. | |
8278 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 8279 | |
9ebbca7d GK |
8280 | Most of this code should be removed by CSE. */ |
8281 | static rtx insn_after_throw; | |
c7ca610e | 8282 | |
a4f6c312 | 8283 | /* This does the saving... */ |
9ebbca7d GK |
8284 | void |
8285 | rs6000_aix_emit_builtin_unwind_init () | |
8286 | { | |
8287 | rtx mem; | |
8288 | rtx stack_top = gen_reg_rtx (Pmode); | |
8289 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
8290 | ||
8291 | insn_after_throw = gen_reg_rtx (SImode); | |
8292 | ||
8293 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
8294 | emit_move_insn (stack_top, mem); | |
8295 | ||
8296 | mem = gen_rtx_MEM (Pmode, | |
8297 | gen_rtx_PLUS (Pmode, stack_top, | |
8298 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
8299 | emit_move_insn (opcode_addr, mem); | |
8300 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
8301 | } |
8302 | ||
a4f6c312 SS |
8303 | /* Emit insns to _restore_ the TOC register, at runtime (specifically |
8304 | in _eh.o). Only used on AIX. | |
9ebbca7d GK |
8305 | |
8306 | The idea is that on AIX, function calls look like this: | |
8307 | bl somefunction-trampoline | |
8308 | lwz r2,20(sp) | |
8309 | ||
a4f6c312 | 8310 | and later, |
9ebbca7d GK |
8311 | somefunction-trampoline: |
8312 | stw r2,20(sp) | |
8313 | ... load function address in the count register ... | |
8314 | bctr | |
8315 | or like this, if the linker determines that this is not a cross-module call | |
8316 | and so the TOC need not be restored: | |
8317 | bl somefunction | |
8318 | nop | |
8319 | or like this, if the compiler could determine that this is not a | |
8320 | cross-module call: | |
8321 | bl somefunction | |
8322 | now, the tricky bit here is that register 2 is saved and restored | |
8323 | by the _linker_, so we can't readily generate debugging information | |
8324 | for it. So we need to go back up the call chain looking at the | |
8325 | insns at return addresses to see which calls saved the TOC register | |
8326 | and so see where it gets restored from. | |
8327 | ||
8328 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
8329 | just before the actual epilogue. | |
8330 | ||
8331 | On the bright side, this incurs no space or time overhead unless an | |
8332 | exception is thrown, except for the extra code in libgcc.a. | |
8333 | ||
8334 | The parameter STACKSIZE is a register containing (at runtime) | |
8335 | the amount to be popped off the stack in addition to the stack frame | |
8336 | of this routine (which will be __throw or __rethrow, and so is | |
8337 | guaranteed to have a stack frame). */ | |
a4f6c312 | 8338 | |
9ebbca7d GK |
8339 | void |
8340 | rs6000_emit_eh_toc_restore (stacksize) | |
8341 | rtx stacksize; | |
8342 | { | |
8343 | rtx top_of_stack; | |
8344 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
8345 | rtx tocompare = gen_reg_rtx (SImode); | |
8346 | rtx opcode = gen_reg_rtx (SImode); | |
8347 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
8348 | rtx mem; | |
8349 | rtx loop_start = gen_label_rtx (); | |
8350 | rtx no_toc_restore_needed = gen_label_rtx (); | |
8351 | rtx loop_exit = gen_label_rtx (); | |
8352 | ||
8353 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 8354 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8355 | emit_move_insn (bottom_of_stack, mem); |
8356 | ||
8357 | top_of_stack = expand_binop (Pmode, add_optab, | |
8358 | bottom_of_stack, stacksize, | |
8359 | NULL_RTX, 1, OPTAB_WIDEN); | |
8360 | ||
8361 | emit_move_insn (tocompare, | |
8362 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
8363 | ? 0x80410014 | |
8364 | : 0xE8410028, SImode))); | |
8365 | ||
8366 | if (insn_after_throw == NULL_RTX) | |
a4f6c312 | 8367 | abort (); |
9ebbca7d GK |
8368 | emit_move_insn (opcode, insn_after_throw); |
8369 | ||
6496a589 | 8370 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
8371 | emit_label (loop_start); |
8372 | ||
8373 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
06f4e019 | 8374 | SImode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
8375 | no_toc_restore_needed); |
8376 | ||
8377 | mem = gen_rtx_MEM (Pmode, | |
8378 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
8379 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
8380 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
8381 | ||
8382 | emit_label (no_toc_restore_needed); | |
8383 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
06f4e019 | 8384 | Pmode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
8385 | loop_exit); |
8386 | ||
8387 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 8388 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8389 | emit_move_insn (bottom_of_stack, mem); |
8390 | ||
8391 | mem = gen_rtx_MEM (Pmode, | |
8392 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
8393 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
8394 | emit_move_insn (opcode_addr, mem); | |
8395 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
8396 | ||
6496a589 | 8397 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 8398 | emit_jump (loop_start); |
6496a589 | 8399 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
8400 | emit_label (loop_exit); |
8401 | } | |
8402 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 8403 | \f |
ba4828e0 RK |
8404 | /* This ties together stack memory (MEM with an alias set of |
8405 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
8406 | ||
9ebbca7d GK |
8407 | static void |
8408 | rs6000_emit_stack_tie () | |
8409 | { | |
ba4828e0 RK |
8410 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
8411 | ||
8412 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
8413 | emit_insn (gen_stack_tie (mem)); |
8414 | } | |
38c1f2d7 | 8415 | |
9ebbca7d GK |
8416 | /* Emit the correct code for allocating stack space, as insns. |
8417 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
8418 | The generated code may use hard register 0 as a temporary. */ | |
8419 | ||
8420 | static void | |
8421 | rs6000_emit_allocate_stack (size, copy_r12) | |
8422 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
8423 | int copy_r12; |
8424 | { | |
9ebbca7d GK |
8425 | rtx insn; |
8426 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
8427 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
8428 | rtx todec = GEN_INT (-size); | |
a157febd GK |
8429 | |
8430 | if (current_function_limit_stack) | |
8431 | { | |
8432 | if (REG_P (stack_limit_rtx) | |
8433 | && REGNO (stack_limit_rtx) > 1 | |
8434 | && REGNO (stack_limit_rtx) <= 31) | |
8435 | { | |
9ebbca7d GK |
8436 | emit_insn (Pmode == SImode |
8437 | ? gen_addsi3 (tmp_reg, | |
8438 | stack_limit_rtx, | |
8439 | GEN_INT (size)) | |
8440 | : gen_adddi3 (tmp_reg, | |
8441 | stack_limit_rtx, | |
8442 | GEN_INT (size))); | |
8443 | ||
8444 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
8445 | const0_rtx)); | |
a157febd GK |
8446 | } |
8447 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 8448 | && TARGET_32BIT |
f607bc57 | 8449 | && DEFAULT_ABI == ABI_V4) |
a157febd | 8450 | { |
9ebbca7d GK |
8451 | rtx toload = gen_rtx_CONST (VOIDmode, |
8452 | gen_rtx_PLUS (Pmode, | |
8453 | stack_limit_rtx, | |
8454 | GEN_INT (size))); | |
8455 | ||
8456 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
8457 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
8458 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
8459 | const0_rtx)); | |
a157febd GK |
8460 | } |
8461 | else | |
8462 | warning ("stack limit expression is not supported"); | |
8463 | } | |
8464 | ||
9ebbca7d GK |
8465 | if (copy_r12 || ! TARGET_UPDATE) |
8466 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
8467 | ||
38c1f2d7 MM |
8468 | if (TARGET_UPDATE) |
8469 | { | |
9ebbca7d | 8470 | if (size > 32767) |
38c1f2d7 | 8471 | { |
9ebbca7d GK |
8472 | /* Need a note here so that try_split doesn't get confused. */ |
8473 | if (get_last_insn() == NULL_RTX) | |
8474 | emit_note (0, NOTE_INSN_DELETED); | |
8475 | insn = emit_move_insn (tmp_reg, todec); | |
8476 | try_split (PATTERN (insn), insn, 0); | |
8477 | todec = tmp_reg; | |
38c1f2d7 | 8478 | } |
9ebbca7d GK |
8479 | |
8480 | if (Pmode == SImode) | |
8481 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
8482 | todec, stack_reg)); | |
8483 | else | |
8484 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
8485 | todec, stack_reg)); | |
38c1f2d7 MM |
8486 | } |
8487 | else | |
8488 | { | |
9ebbca7d GK |
8489 | if (Pmode == SImode) |
8490 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 8491 | else |
9ebbca7d GK |
8492 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
8493 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
8494 | gen_rtx_REG (Pmode, 12)); | |
8495 | } | |
8496 | ||
8497 | RTX_FRAME_RELATED_P (insn) = 1; | |
8498 | REG_NOTES (insn) = | |
8499 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8500 | gen_rtx_SET (VOIDmode, stack_reg, | |
8501 | gen_rtx_PLUS (Pmode, stack_reg, | |
8502 | GEN_INT (-size))), | |
8503 | REG_NOTES (insn)); | |
8504 | } | |
8505 | ||
9aa86737 AH |
8506 | /* Add a RTX_FRAME_RELATED note so that dwarf2out_frame_debug_expr |
8507 | knows that: | |
8508 | ||
8509 | (mem (plus (blah) (regXX))) | |
8510 | ||
8511 | is really: | |
8512 | ||
8513 | (mem (plus (blah) (const VALUE_OF_REGXX))). */ | |
8514 | ||
8515 | static void | |
8516 | altivec_frame_fixup (insn, reg, val) | |
8517 | rtx insn, reg; | |
8518 | HOST_WIDE_INT val; | |
8519 | { | |
8520 | rtx real; | |
8521 | ||
8522 | real = copy_rtx (PATTERN (insn)); | |
8523 | ||
8524 | real = replace_rtx (real, reg, GEN_INT (val)); | |
8525 | ||
8526 | RTX_FRAME_RELATED_P (insn) = 1; | |
8527 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8528 | real, | |
8529 | REG_NOTES (insn)); | |
8530 | } | |
8531 | ||
a4f6c312 SS |
8532 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
8533 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
8534 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
8535 | deduce these equivalences by itself so it wasn't necessary to hold | |
8536 | its hand so much. */ | |
9ebbca7d GK |
8537 | |
8538 | static void | |
8539 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
8540 | rtx insn; | |
8541 | rtx reg; | |
8542 | HOST_WIDE_INT val; | |
8543 | rtx reg2; | |
8544 | rtx rreg; | |
8545 | { | |
8546 | rtx real, temp; | |
8547 | ||
8548 | real = copy_rtx (PATTERN (insn)); | |
8549 | ||
8550 | real = replace_rtx (real, reg, | |
8551 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
8552 | STACK_POINTER_REGNUM), | |
8553 | GEN_INT (val))); | |
8554 | ||
8555 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
8556 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
8557 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
8558 | ||
8559 | if (GET_CODE (real) == SET) | |
8560 | { | |
8561 | rtx set = real; | |
8562 | ||
8563 | temp = simplify_rtx (SET_SRC (set)); | |
8564 | if (temp) | |
8565 | SET_SRC (set) = temp; | |
8566 | temp = simplify_rtx (SET_DEST (set)); | |
8567 | if (temp) | |
8568 | SET_DEST (set) = temp; | |
8569 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 8570 | { |
9ebbca7d GK |
8571 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
8572 | if (temp) | |
8573 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 8574 | } |
38c1f2d7 | 8575 | } |
9ebbca7d GK |
8576 | else if (GET_CODE (real) == PARALLEL) |
8577 | { | |
8578 | int i; | |
8579 | for (i = 0; i < XVECLEN (real, 0); i++) | |
8580 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
8581 | { | |
8582 | rtx set = XVECEXP (real, 0, i); | |
8583 | ||
8584 | temp = simplify_rtx (SET_SRC (set)); | |
8585 | if (temp) | |
8586 | SET_SRC (set) = temp; | |
8587 | temp = simplify_rtx (SET_DEST (set)); | |
8588 | if (temp) | |
8589 | SET_DEST (set) = temp; | |
8590 | if (GET_CODE (SET_DEST (set)) == MEM) | |
8591 | { | |
8592 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
8593 | if (temp) | |
8594 | XEXP (SET_DEST (set), 0) = temp; | |
8595 | } | |
8596 | RTX_FRAME_RELATED_P (set) = 1; | |
8597 | } | |
8598 | } | |
8599 | else | |
a4f6c312 | 8600 | abort (); |
9ebbca7d GK |
8601 | |
8602 | if (reg2 != NULL_RTX) | |
8603 | real = replace_rtx (real, reg2, rreg); | |
8604 | ||
8605 | RTX_FRAME_RELATED_P (insn) = 1; | |
8606 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8607 | real, | |
8608 | REG_NOTES (insn)); | |
38c1f2d7 MM |
8609 | } |
8610 | ||
00b960c7 AH |
8611 | /* Returns an insn that has a vrsave set operation with the |
8612 | appropriate CLOBBERs. */ | |
8613 | ||
8614 | static rtx | |
9aa86737 | 8615 | generate_set_vrsave (reg, info, epiloguep) |
00b960c7 AH |
8616 | rtx reg; |
8617 | rs6000_stack_t *info; | |
9aa86737 | 8618 | int epiloguep; |
00b960c7 AH |
8619 | { |
8620 | int nclobs, i; | |
8621 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 8622 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 8623 | |
a004eb82 AH |
8624 | clobs[0] |
8625 | = gen_rtx_SET (VOIDmode, | |
8626 | vrsave, | |
8627 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
8628 | gen_rtvec (2, reg, vrsave), | |
8629 | 30)); | |
00b960c7 AH |
8630 | |
8631 | nclobs = 1; | |
8632 | ||
9aa86737 AH |
8633 | /* We need to clobber the registers in the mask so the scheduler |
8634 | does not move sets to VRSAVE before sets of AltiVec registers. | |
8635 | ||
8636 | However, if the function receives nonlocal gotos, reload will set | |
8637 | all call saved registers live. We will end up with: | |
8638 | ||
8639 | (set (reg 999) (mem)) | |
8640 | (parallel [ (set (reg vrsave) (unspec blah)) | |
8641 | (clobber (reg 999))]) | |
8642 | ||
8643 | The clobber will cause the store into reg 999 to be dead, and | |
8644 | flow will attempt to delete an epilogue insn. In this case, we | |
8645 | need an unspec use/set of the register. */ | |
00b960c7 AH |
8646 | |
8647 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
8648 | if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0) | |
9aa86737 AH |
8649 | { |
8650 | if (!epiloguep || call_used_regs [i]) | |
8651 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
8652 | gen_rtx_REG (V4SImode, i)); | |
8653 | else | |
8654 | { | |
8655 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
8656 | |
8657 | clobs[nclobs++] | |
a004eb82 AH |
8658 | = gen_rtx_SET (VOIDmode, |
8659 | reg, | |
8660 | gen_rtx_UNSPEC (V4SImode, | |
8661 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
8662 | } |
8663 | } | |
00b960c7 AH |
8664 | |
8665 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
8666 | ||
8667 | for (i = 0; i < nclobs; ++i) | |
8668 | XVECEXP (insn, 0, i) = clobs[i]; | |
8669 | ||
8670 | return insn; | |
8671 | } | |
8672 | ||
9ebbca7d GK |
8673 | /* Emit function prologue as insns. */ |
8674 | ||
9878760c | 8675 | void |
83720594 | 8676 | rs6000_emit_prologue () |
9878760c | 8677 | { |
4697a36c | 8678 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
8679 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
8680 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
8681 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
8682 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
8683 | rtx frame_reg_rtx = sp_reg_rtx; | |
8684 | rtx cr_save_rtx = NULL; | |
8685 | rtx insn; | |
8686 | int saving_FPRs_inline; | |
8687 | int using_store_multiple; | |
8688 | HOST_WIDE_INT sp_offset = 0; | |
8689 | ||
8690 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
8691 | && info->first_gp_reg_save < 31); | |
8692 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8693 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
8694 | ||
8695 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
f607bc57 | 8696 | if (info->push_p && DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
8697 | { |
8698 | if (info->total_size < 32767) | |
8699 | sp_offset = info->total_size; | |
8700 | else | |
8701 | frame_reg_rtx = frame_ptr_rtx; | |
8702 | rs6000_emit_allocate_stack (info->total_size, | |
8703 | (frame_reg_rtx != sp_reg_rtx | |
8704 | && (info->cr_save_p | |
8705 | || info->lr_save_p | |
8706 | || info->first_fp_reg_save < 64 | |
8707 | || info->first_gp_reg_save < 32 | |
8708 | ))); | |
8709 | if (frame_reg_rtx != sp_reg_rtx) | |
8710 | rs6000_emit_stack_tie (); | |
8711 | } | |
8712 | ||
9aa86737 AH |
8713 | /* Save AltiVec registers if needed. */ |
8714 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
8715 | { | |
8716 | int i; | |
8717 | ||
8718 | /* There should be a non inline version of this, for when we | |
8719 | are saving lots of vector registers. */ | |
8720 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
8721 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
8722 | { | |
8723 | rtx areg, savereg, mem; | |
8724 | int offset; | |
8725 | ||
8726 | offset = info->altivec_save_offset + sp_offset | |
8727 | + 16 * (i - info->first_altivec_reg_save); | |
8728 | ||
8729 | savereg = gen_rtx_REG (V4SImode, i); | |
8730 | ||
8731 | areg = gen_rtx_REG (Pmode, 0); | |
8732 | emit_move_insn (areg, GEN_INT (offset)); | |
8733 | ||
8734 | /* AltiVec addressing mode is [reg+reg]. */ | |
8735 | mem = gen_rtx_MEM (V4SImode, | |
8736 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
8737 | ||
8738 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
8739 | ||
8740 | insn = emit_move_insn (mem, savereg); | |
8741 | ||
8742 | altivec_frame_fixup (insn, areg, offset); | |
8743 | } | |
8744 | } | |
8745 | ||
8746 | /* VRSAVE is a bit vector representing which AltiVec registers | |
8747 | are used. The OS uses this to determine which vector | |
8748 | registers to save on a context switch. We need to save | |
8749 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
8750 | used in this function, and do the corresponding magic in the | |
8751 | epilogue. */ | |
8752 | ||
8753 | if (TARGET_ALTIVEC && info->vrsave_mask != 0) | |
8754 | { | |
a004eb82 | 8755 | rtx reg, mem, vrsave; |
9aa86737 AH |
8756 | int offset; |
8757 | ||
8758 | /* Get VRSAVE onto a GPR. */ | |
8759 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 | 8760 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
8761 | if (TARGET_MACHO) |
8762 | emit_insn (gen_get_vrsave_internal (reg)); | |
8763 | else | |
8764 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
8765 | |
8766 | /* Save VRSAVE. */ | |
8767 | offset = info->vrsave_save_offset + sp_offset; | |
8768 | mem | |
8769 | = gen_rtx_MEM (SImode, | |
8770 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
8771 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
8772 | insn = emit_move_insn (mem, reg); | |
8773 | ||
8774 | /* Include the registers in the mask. */ | |
8775 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
8776 | ||
8777 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
8778 | } | |
8779 | ||
9ebbca7d GK |
8780 | /* If we use the link register, get it into r0. */ |
8781 | if (info->lr_save_p) | |
71f123ca | 8782 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
8783 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
8784 | ||
8785 | /* If we need to save CR, put it into r12. */ | |
8786 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
8787 | { | |
8788 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
8789 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
8790 | } | |
8791 | ||
a4f6c312 SS |
8792 | /* Do any required saving of fpr's. If only one or two to save, do |
8793 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
8794 | if (saving_FPRs_inline) |
8795 | { | |
8796 | int i; | |
8797 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
8798 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
8799 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
8800 | { | |
8801 | rtx addr, reg, mem; | |
8802 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
8803 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8804 | GEN_INT (info->fp_save_offset | |
8805 | + sp_offset | |
a4f6c312 | 8806 | + 8 * i)); |
9ebbca7d | 8807 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 8808 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8809 | |
8810 | insn = emit_move_insn (mem, reg); | |
8811 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8812 | NULL_RTX, NULL_RTX); | |
8813 | } | |
8814 | } | |
8815 | else if (info->first_fp_reg_save != 64) | |
8816 | { | |
8817 | int i; | |
8818 | char rname[30]; | |
520a57c8 | 8819 | const char *alloc_rname; |
9ebbca7d GK |
8820 | rtvec p; |
8821 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
8822 | ||
8823 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
8824 | gen_rtx_REG (Pmode, | |
8825 | LINK_REGISTER_REGNUM)); | |
8826 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
8827 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 8828 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
8829 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
8830 | gen_rtx_SYMBOL_REF (Pmode, | |
8831 | alloc_rname)); | |
8832 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
8833 | { | |
8834 | rtx addr, reg, mem; | |
8835 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
8836 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8837 | GEN_INT (info->fp_save_offset | |
8838 | + sp_offset + 8*i)); | |
8839 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 8840 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8841 | |
8842 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
8843 | } | |
8844 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
8845 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8846 | NULL_RTX, NULL_RTX); | |
8847 | } | |
b6c9286a | 8848 | |
9ebbca7d GK |
8849 | /* Save GPRs. This is done as a PARALLEL if we are using |
8850 | the store-multiple instructions. */ | |
8851 | if (using_store_multiple) | |
b6c9286a | 8852 | { |
9ebbca7d GK |
8853 | rtvec p, dwarfp; |
8854 | int i; | |
8855 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
8856 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
8857 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
8858 | { | |
8859 | rtx addr, reg, mem; | |
8860 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
8861 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8862 | GEN_INT (info->gp_save_offset | |
8863 | + sp_offset | |
8864 | + reg_size * i)); | |
8865 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 8866 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8867 | |
8868 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
8869 | } | |
8870 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
8871 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8872 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
8873 | } |
8874 | else | |
8875 | { | |
9ebbca7d GK |
8876 | int i; |
8877 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
8878 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
8879 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
8880 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
8881 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
8882 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
8883 | { |
8884 | rtx addr, reg, mem; | |
8885 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
8886 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8887 | GEN_INT (info->gp_save_offset | |
8888 | + sp_offset | |
8889 | + reg_size * i)); | |
8890 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 8891 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8892 | |
8893 | insn = emit_move_insn (mem, reg); | |
8894 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8895 | NULL_RTX, NULL_RTX); | |
8896 | } | |
8897 | } | |
8898 | ||
83720594 RH |
8899 | /* ??? There's no need to emit actual instructions here, but it's the |
8900 | easiest way to get the frame unwind information emitted. */ | |
8901 | if (current_function_calls_eh_return) | |
8902 | { | |
78e1b90d DE |
8903 | unsigned int i, regno; |
8904 | ||
83720594 RH |
8905 | for (i = 0; ; ++i) |
8906 | { | |
8907 | rtx addr, reg, mem; | |
8908 | ||
8909 | regno = EH_RETURN_DATA_REGNO (i); | |
8910 | if (regno == INVALID_REGNUM) | |
8911 | break; | |
8912 | ||
8913 | reg = gen_rtx_REG (reg_mode, regno); | |
8914 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
8915 | info->ehrd_offset + sp_offset |
8916 | + reg_size * (int) i); | |
83720594 | 8917 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 8918 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
8919 | |
8920 | insn = emit_move_insn (mem, reg); | |
8921 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8922 | NULL_RTX, NULL_RTX); | |
8923 | } | |
8924 | } | |
8925 | ||
9ebbca7d GK |
8926 | /* Save lr if we used it. */ |
8927 | if (info->lr_save_p) | |
8928 | { | |
8929 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8930 | GEN_INT (info->lr_save_offset + sp_offset)); | |
8931 | rtx reg = gen_rtx_REG (Pmode, 0); | |
8932 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
8933 | /* This should not be of rs6000_sr_alias_set, because of | |
8934 | __builtin_return_address. */ | |
8935 | ||
8936 | insn = emit_move_insn (mem, reg); | |
8937 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8938 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
8939 | } | |
8940 | ||
8941 | /* Save CR if we use any that must be preserved. */ | |
8942 | if (info->cr_save_p) | |
8943 | { | |
8944 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8945 | GEN_INT (info->cr_save_offset + sp_offset)); | |
8946 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
8947 | |
8948 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
8949 | |
8950 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
8951 | that it's free. */ | |
8952 | if (REGNO (frame_reg_rtx) == 12) | |
8953 | { | |
8954 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
8955 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
8956 | } | |
8957 | insn = emit_move_insn (mem, cr_save_rtx); | |
8958 | ||
8959 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
8960 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
8961 | OK. All we have to do is specify that _one_ condition code | |
8962 | register is saved in this stack slot. The thrower's epilogue | |
a1dc9455 FS |
8963 | will then restore all the call-saved registers. |
8964 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
9ebbca7d | 8965 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a1dc9455 | 8966 | cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO)); |
9ebbca7d GK |
8967 | } |
8968 | ||
8969 | /* Update stack and set back pointer unless this is V.4, | |
8970 | for which it was done previously. */ | |
f607bc57 | 8971 | if (info->push_p && DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
8972 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
8973 | ||
8974 | /* Set frame pointer, if needed. */ | |
8975 | if (frame_pointer_needed) | |
8976 | { | |
8977 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
8978 | sp_reg_rtx); | |
8979 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 8980 | } |
9878760c | 8981 | |
9ebbca7d GK |
8982 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
8983 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
f607bc57 ZW |
8984 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
8985 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
9ebbca7d GK |
8986 | { |
8987 | /* If emit_load_toc_table will use the link register, we need to save | |
8988 | it. We use R11 for this purpose because emit_load_toc_table | |
8989 | can use register 0. This allows us to use a plain 'blr' to return | |
8990 | from the procedure more often. */ | |
d5fa86ba GK |
8991 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 |
8992 | && ! info->lr_save_p | |
8993 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
8994 | if (save_LR_around_toc_setup) |
8995 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
8996 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
8997 | ||
8998 | rs6000_emit_load_toc_table (TRUE); | |
8999 | ||
9000 | if (save_LR_around_toc_setup) | |
9001 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
9002 | gen_rtx_REG (Pmode, 11)); | |
9003 | } | |
ee890fe2 SS |
9004 | |
9005 | if (DEFAULT_ABI == ABI_DARWIN | |
9006 | && flag_pic && current_function_uses_pic_offset_table) | |
9007 | { | |
9008 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
9009 | ||
9010 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); | |
9011 | ||
9012 | rs6000_maybe_dead ( | |
9013 | emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM), | |
9014 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); | |
9015 | } | |
9ebbca7d GK |
9016 | } |
9017 | ||
9ebbca7d | 9018 | /* Write function prologue. */ |
a4f6c312 | 9019 | |
08c148a8 NB |
9020 | static void |
9021 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 9022 | FILE *file; |
08c148a8 | 9023 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
9024 | { |
9025 | rs6000_stack_t *info = rs6000_stack_info (); | |
9026 | ||
4697a36c MM |
9027 | if (TARGET_DEBUG_STACK) |
9028 | debug_stack_info (info); | |
9878760c | 9029 | |
a4f6c312 SS |
9030 | /* Write .extern for any function we will call to save and restore |
9031 | fp values. */ | |
9032 | if (info->first_fp_reg_save < 64 | |
9033 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 9034 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 9035 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
9036 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
9037 | RESTORE_FP_SUFFIX); | |
9878760c | 9038 | |
c764f757 RK |
9039 | /* Write .extern for AIX common mode routines, if needed. */ |
9040 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
9041 | { | |
f6709c70 JW |
9042 | fputs ("\t.extern __mulh\n", file); |
9043 | fputs ("\t.extern __mull\n", file); | |
9044 | fputs ("\t.extern __divss\n", file); | |
9045 | fputs ("\t.extern __divus\n", file); | |
9046 | fputs ("\t.extern __quoss\n", file); | |
9047 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
9048 | common_mode_defined = 1; |
9049 | } | |
9878760c | 9050 | |
9ebbca7d | 9051 | if (! HAVE_prologue) |
979721f8 | 9052 | { |
9ebbca7d GK |
9053 | start_sequence (); |
9054 | ||
a4f6c312 SS |
9055 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
9056 | the "toplevel" insn chain. */ | |
9ebbca7d GK |
9057 | emit_note (0, NOTE_INSN_DELETED); |
9058 | rs6000_emit_prologue (); | |
9059 | emit_note (0, NOTE_INSN_DELETED); | |
9060 | ||
9061 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
9062 | debug_rtx_list (get_insns (), 100); |
9063 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 9064 | end_sequence (); |
979721f8 MM |
9065 | } |
9066 | ||
9ebbca7d GK |
9067 | rs6000_pic_labelno++; |
9068 | } | |
9069 | ||
9070 | /* Emit function epilogue as insns. | |
9878760c | 9071 | |
9ebbca7d GK |
9072 | At present, dwarf2out_frame_debug_expr doesn't understand |
9073 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
9074 | anywhere in the epilogue. Most of the insns below would in any case | |
9075 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 9076 | |
9ebbca7d | 9077 | void |
83720594 | 9078 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
9079 | int sibcall; |
9080 | { | |
9081 | rs6000_stack_t *info; | |
9082 | int restoring_FPRs_inline; | |
9083 | int using_load_multiple; | |
9084 | int using_mfcr_multiple; | |
9085 | int use_backchain_to_restore_sp; | |
9086 | int sp_offset = 0; | |
9087 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
9088 | rtx frame_reg_rtx = sp_reg_rtx; | |
9089 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
9090 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
9091 | int i; | |
9092 | ||
9093 | info = rs6000_stack_info (); | |
9094 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
9095 | && info->first_gp_reg_save < 31); | |
9096 | restoring_FPRs_inline = (sibcall | |
83720594 | 9097 | || current_function_calls_eh_return |
9ebbca7d GK |
9098 | || info->first_fp_reg_save == 64 |
9099 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
9100 | use_backchain_to_restore_sp = (frame_pointer_needed | |
9101 | || current_function_calls_alloca | |
9102 | || info->total_size > 32767); | |
9103 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
9104 | || rs6000_cpu == PROCESSOR_PPC603 | |
9105 | || rs6000_cpu == PROCESSOR_PPC750 | |
9106 | || optimize_size); | |
9107 | ||
9108 | /* If we have a frame pointer, a call to alloca, or a large stack | |
9109 | frame, restore the old stack pointer using the backchain. Otherwise, | |
9110 | we know what size to update it with. */ | |
9111 | if (use_backchain_to_restore_sp) | |
bacbde18 | 9112 | { |
9ebbca7d GK |
9113 | /* Under V.4, don't reset the stack pointer until after we're done |
9114 | loading the saved registers. */ | |
f607bc57 | 9115 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 9116 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 9117 | |
9ebbca7d GK |
9118 | emit_move_insn (frame_reg_rtx, |
9119 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
9120 | ||
bacbde18 | 9121 | } |
9ebbca7d | 9122 | else if (info->push_p) |
85638c0d | 9123 | { |
f607bc57 | 9124 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
9125 | sp_offset = info->total_size; |
9126 | else | |
9127 | { | |
9128 | emit_insn (TARGET_32BIT | |
9129 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
9130 | GEN_INT (info->total_size)) | |
9131 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
9132 | GEN_INT (info->total_size))); | |
9133 | } | |
85638c0d | 9134 | } |
9ebbca7d | 9135 | |
9aa86737 AH |
9136 | /* Restore AltiVec registers if needed. */ |
9137 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
9138 | { | |
9139 | int i; | |
9140 | ||
9141 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
9142 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
9143 | { | |
9144 | rtx addr, areg, mem; | |
9145 | ||
9146 | areg = gen_rtx_REG (Pmode, 0); | |
9147 | emit_move_insn | |
9148 | (areg, GEN_INT (info->altivec_save_offset | |
9149 | + sp_offset | |
9150 | + 16 * (i - info->first_altivec_reg_save))); | |
9151 | ||
9152 | /* AltiVec addressing mode is [reg+reg]. */ | |
9153 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
9154 | mem = gen_rtx_MEM (V4SImode, addr); | |
9155 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9156 | ||
9157 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
9158 | } | |
9159 | } | |
9160 | ||
9161 | /* Restore VRSAVE if needed. */ | |
9162 | if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0) | |
9163 | { | |
9164 | rtx addr, mem, reg; | |
9165 | ||
9166 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
9167 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
9168 | mem = gen_rtx_MEM (SImode, addr); | |
9169 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9170 | reg = gen_rtx_REG (SImode, 12); | |
9171 | emit_move_insn (reg, mem); | |
9172 | ||
9173 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
9174 | } | |
9175 | ||
9ebbca7d GK |
9176 | /* Get the old lr if we saved it. */ |
9177 | if (info->lr_save_p) | |
b6c9286a | 9178 | { |
9ebbca7d GK |
9179 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
9180 | GEN_INT (info->lr_save_offset + sp_offset)); | |
9181 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
ba4828e0 RK |
9182 | |
9183 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 9184 | |
9ebbca7d | 9185 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 9186 | } |
9ebbca7d GK |
9187 | |
9188 | /* Get the old cr if we saved it. */ | |
9189 | if (info->cr_save_p) | |
9190 | { | |
9191 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
9192 | GEN_INT (info->cr_save_offset + sp_offset)); | |
9193 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
9194 | |
9195 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 9196 | |
9ebbca7d GK |
9197 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
9198 | } | |
9199 | ||
9200 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 9201 | if (info->lr_save_p) |
9ebbca7d GK |
9202 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
9203 | gen_rtx_REG (Pmode, 0)); | |
9204 | ||
83720594 RH |
9205 | /* Load exception handler data registers, if needed. */ |
9206 | if (current_function_calls_eh_return) | |
9207 | { | |
78e1b90d DE |
9208 | unsigned int i, regno; |
9209 | ||
83720594 RH |
9210 | for (i = 0; ; ++i) |
9211 | { | |
9212 | rtx addr, mem; | |
9213 | ||
9214 | regno = EH_RETURN_DATA_REGNO (i); | |
9215 | if (regno == INVALID_REGNUM) | |
9216 | break; | |
9217 | ||
9218 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
9219 | info->ehrd_offset + sp_offset |
9220 | + reg_size * (int) i); | |
83720594 | 9221 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 9222 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
9223 | |
9224 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
9225 | } | |
9226 | } | |
9ebbca7d GK |
9227 | |
9228 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
9229 | the load-multiple instructions. */ | |
9230 | if (using_load_multiple) | |
979721f8 | 9231 | { |
9ebbca7d GK |
9232 | rtvec p; |
9233 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9234 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 9235 | { |
9ebbca7d GK |
9236 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
9237 | GEN_INT (info->gp_save_offset | |
9238 | + sp_offset | |
9239 | + reg_size * i)); | |
9240 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
9241 | |
9242 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
9243 | |
9244 | RTVEC_ELT (p, i) = | |
9245 | gen_rtx_SET (VOIDmode, | |
9246 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
9247 | mem); | |
979721f8 | 9248 | } |
9ebbca7d | 9249 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 9250 | } |
9ebbca7d GK |
9251 | else |
9252 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
9253 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
9254 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
9255 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
9256 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
9257 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
9258 | { |
9259 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
9260 | GEN_INT (info->gp_save_offset | |
9261 | + sp_offset | |
9262 | + reg_size * i)); | |
9263 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
9264 | |
9265 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
9266 | |
9267 | emit_move_insn (gen_rtx_REG (reg_mode, | |
9268 | info->first_gp_reg_save + i), | |
9269 | mem); | |
9270 | } | |
9878760c | 9271 | |
9ebbca7d GK |
9272 | /* Restore fpr's if we need to do it without calling a function. */ |
9273 | if (restoring_FPRs_inline) | |
9274 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
9275 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
9276 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
9277 | { | |
9278 | rtx addr, mem; | |
9279 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
9280 | GEN_INT (info->fp_save_offset | |
9281 | + sp_offset | |
a4f6c312 | 9282 | + 8 * i)); |
9ebbca7d | 9283 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 9284 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
9285 | |
9286 | emit_move_insn (gen_rtx_REG (DFmode, | |
9287 | info->first_fp_reg_save + i), | |
9288 | mem); | |
9289 | } | |
8d30c4ee | 9290 | |
9ebbca7d GK |
9291 | /* If we saved cr, restore it here. Just those that were used. */ |
9292 | if (info->cr_save_p) | |
979721f8 | 9293 | { |
9ebbca7d | 9294 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 9295 | int count = 0; |
9ebbca7d GK |
9296 | |
9297 | if (using_mfcr_multiple) | |
979721f8 | 9298 | { |
9ebbca7d GK |
9299 | for (i = 0; i < 8; i++) |
9300 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 9301 | count++; |
9ebbca7d | 9302 | if (count == 0) |
e35b9579 GK |
9303 | abort (); |
9304 | } | |
9305 | ||
9306 | if (using_mfcr_multiple && count > 1) | |
9307 | { | |
9308 | rtvec p; | |
9309 | int ndx; | |
9ebbca7d | 9310 | |
e35b9579 | 9311 | p = rtvec_alloc (count); |
9ebbca7d | 9312 | |
e35b9579 | 9313 | ndx = 0; |
9ebbca7d GK |
9314 | for (i = 0; i < 8; i++) |
9315 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
9316 | { | |
9317 | rtvec r = rtvec_alloc (2); | |
9318 | RTVEC_ELT (r, 0) = r12_rtx; | |
9319 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 9320 | RTVEC_ELT (p, ndx) = |
9ebbca7d GK |
9321 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
9322 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
e35b9579 | 9323 | ndx++; |
9ebbca7d GK |
9324 | } |
9325 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
9326 | if (ndx != count) |
9327 | abort (); | |
979721f8 MM |
9328 | } |
9329 | else | |
9ebbca7d GK |
9330 | for (i = 0; i < 8; i++) |
9331 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 9332 | { |
9ebbca7d GK |
9333 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
9334 | CR0_REGNO+i), | |
9335 | r12_rtx)); | |
979721f8 | 9336 | } |
979721f8 MM |
9337 | } |
9338 | ||
9ebbca7d GK |
9339 | /* If this is V.4, unwind the stack pointer after all of the loads |
9340 | have been done. We need to emit a block here so that sched | |
9341 | doesn't decide to move the sp change before the register restores | |
9342 | (which may not have any obvious dependency on the stack). This | |
9343 | doesn't hurt performance, because there is no scheduling that can | |
9344 | be done after this point. */ | |
f607bc57 | 9345 | if (DEFAULT_ABI == ABI_V4) |
b6c9286a | 9346 | { |
9ebbca7d GK |
9347 | if (frame_reg_rtx != sp_reg_rtx) |
9348 | rs6000_emit_stack_tie (); | |
b6c9286a | 9349 | |
9ebbca7d | 9350 | if (use_backchain_to_restore_sp) |
b6c9286a | 9351 | { |
9ebbca7d | 9352 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 9353 | } |
9ebbca7d | 9354 | else if (sp_offset != 0) |
13f1623b | 9355 | { |
9ebbca7d GK |
9356 | emit_insn (Pmode == SImode |
9357 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
9358 | GEN_INT (sp_offset)) | |
9359 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
9360 | GEN_INT (sp_offset))); | |
13f1623b | 9361 | } |
9ebbca7d | 9362 | } |
b6c9286a | 9363 | |
83720594 RH |
9364 | if (current_function_calls_eh_return) |
9365 | { | |
9366 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
9367 | emit_insn (Pmode == SImode | |
9368 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) | |
9369 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
9370 | } | |
9371 | ||
9ebbca7d GK |
9372 | if (!sibcall) |
9373 | { | |
9374 | rtvec p; | |
9375 | if (! restoring_FPRs_inline) | |
9376 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
9377 | else | |
9378 | p = rtvec_alloc (2); | |
b6c9286a | 9379 | |
e35b9579 GK |
9380 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
9381 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
9382 | gen_rtx_REG (Pmode, |
9383 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
9384 | |
9385 | /* If we have to restore more than two FP registers, branch to the | |
9386 | restore function. It will return to our caller. */ | |
9387 | if (! restoring_FPRs_inline) | |
9388 | { | |
9389 | int i; | |
9390 | char rname[30]; | |
520a57c8 | 9391 | const char *alloc_rname; |
979721f8 | 9392 | |
9ebbca7d GK |
9393 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
9394 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 9395 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
9396 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
9397 | gen_rtx_SYMBOL_REF (Pmode, | |
9398 | alloc_rname)); | |
b6c9286a | 9399 | |
9ebbca7d GK |
9400 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
9401 | { | |
9402 | rtx addr, mem; | |
9403 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
9404 | GEN_INT (info->fp_save_offset + 8*i)); | |
9405 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 9406 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
9407 | |
9408 | RTVEC_ELT (p, i+3) = | |
9409 | gen_rtx_SET (VOIDmode, | |
9410 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
9411 | mem); | |
b6c9286a MM |
9412 | } |
9413 | } | |
9ebbca7d GK |
9414 | |
9415 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 9416 | } |
9878760c RK |
9417 | } |
9418 | ||
9419 | /* Write function epilogue. */ | |
9420 | ||
08c148a8 NB |
9421 | static void |
9422 | rs6000_output_function_epilogue (file, size) | |
9878760c | 9423 | FILE *file; |
08c148a8 | 9424 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 9425 | { |
4697a36c | 9426 | rs6000_stack_t *info = rs6000_stack_info (); |
6041bf2f | 9427 | int optional_tbtab = (optimize_size || TARGET_ELF) ? 0 : 1; |
9878760c | 9428 | |
9ebbca7d | 9429 | if (! HAVE_epilogue) |
9878760c | 9430 | { |
9ebbca7d GK |
9431 | rtx insn = get_last_insn (); |
9432 | /* If the last insn was a BARRIER, we don't have to write anything except | |
9433 | the trace table. */ | |
9434 | if (GET_CODE (insn) == NOTE) | |
9435 | insn = prev_nonnote_insn (insn); | |
9436 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 9437 | { |
9ebbca7d GK |
9438 | /* This is slightly ugly, but at least we don't have two |
9439 | copies of the epilogue-emitting code. */ | |
9440 | start_sequence (); | |
9441 | ||
9442 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
9443 | and end of the "toplevel" insn chain. */ | |
9444 | emit_note (0, NOTE_INSN_DELETED); | |
9445 | rs6000_emit_epilogue (FALSE); | |
9446 | emit_note (0, NOTE_INSN_DELETED); | |
9447 | ||
9448 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
9449 | debug_rtx_list (get_insns (), 100); |
9450 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 9451 | end_sequence (); |
4697a36c | 9452 | } |
9878760c | 9453 | } |
b4ac57ab | 9454 | |
9b30bae2 | 9455 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
9456 | on its format. |
9457 | ||
9458 | We don't output a traceback table if -finhibit-size-directive was | |
9459 | used. The documentation for -finhibit-size-directive reads | |
9460 | ``don't output a @code{.size} assembler directive, or anything | |
9461 | else that would cause trouble if the function is split in the | |
9462 | middle, and the two halves are placed at locations far apart in | |
9463 | memory.'' The traceback table has this property, since it | |
9464 | includes the offset from the start of the function to the | |
4d30c363 MM |
9465 | traceback table itself. |
9466 | ||
9467 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
9468 | different traceback table. */ |
9469 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 9470 | { |
3cce094d | 9471 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
3ac88239 | 9472 | const char *language_string = lang_hooks.name; |
6041bf2f | 9473 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 ILT |
9474 | int i; |
9475 | ||
b6c9286a MM |
9476 | while (*fname == '.') /* V.4 encodes . in the name */ |
9477 | fname++; | |
9478 | ||
314fc5a9 ILT |
9479 | /* Need label immediately before tbtab, so we can compute its offset |
9480 | from the function start. */ | |
9481 | if (*fname == '*') | |
9482 | ++fname; | |
9483 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
9484 | ASM_OUTPUT_LABEL (file, fname); | |
9485 | ||
9486 | /* The .tbtab pseudo-op can only be used for the first eight | |
9487 | expressions, since it can't handle the possibly variable | |
9488 | length fields that follow. However, if you omit the optional | |
9489 | fields, the assembler outputs zeros for all optional fields | |
9490 | anyways, giving each variable length field is minimum length | |
9491 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
9492 | pseudo-op at all. */ | |
9493 | ||
9494 | /* An all-zero word flags the start of the tbtab, for debuggers | |
9495 | that have to find it by searching forward from the entry | |
9496 | point or from the current pc. */ | |
19d2d16f | 9497 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
9498 | |
9499 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 9500 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
9501 | |
9502 | /* Language type. Unfortunately, there doesn't seem to be any | |
9503 | official way to get this info, so we use language_string. C | |
9504 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 9505 | value for C for now. There is no official value for Java, |
6f573ff9 | 9506 | although IBM appears to be using 13. There is no official value |
f710504c | 9507 | for Chill, so we've chosen 44 pseudo-randomly. */ |
314fc5a9 | 9508 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 9509 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
9510 | i = 0; |
9511 | else if (! strcmp (language_string, "GNU F77")) | |
9512 | i = 1; | |
9513 | else if (! strcmp (language_string, "GNU Ada")) | |
9514 | i = 3; | |
8b83775b | 9515 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
9516 | i = 2; |
9517 | else if (! strcmp (language_string, "GNU C++")) | |
9518 | i = 9; | |
9517ead8 AG |
9519 | else if (! strcmp (language_string, "GNU Java")) |
9520 | i = 13; | |
6f573ff9 JL |
9521 | else if (! strcmp (language_string, "GNU CHILL")) |
9522 | i = 44; | |
314fc5a9 ILT |
9523 | else |
9524 | abort (); | |
9525 | fprintf (file, "%d,", i); | |
9526 | ||
9527 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
9528 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
9529 | from start of procedure stored in tbtab, internal function, function | |
9530 | has controlled storage, function has no toc, function uses fp, | |
9531 | function logs/aborts fp operations. */ | |
9532 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
9533 | fprintf (file, "%d,", |
9534 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
9535 | |
9536 | /* 6 bitfields: function is interrupt handler, name present in | |
9537 | proc table, function calls alloca, on condition directives | |
9538 | (controls stack walks, 3 bits), saves condition reg, saves | |
9539 | link reg. */ | |
9540 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
9541 | set up as a frame pointer, even when there is no alloca call. */ | |
9542 | fprintf (file, "%d,", | |
6041bf2f DE |
9543 | ((optional_tbtab << 6) |
9544 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
9545 | | (info->cr_save_p << 1) | |
9546 | | (info->lr_save_p))); | |
314fc5a9 | 9547 | |
6041bf2f | 9548 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
9549 | (6 bits). */ |
9550 | fprintf (file, "%d,", | |
4697a36c | 9551 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
9552 | |
9553 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
9554 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
9555 | ||
6041bf2f DE |
9556 | if (optional_tbtab) |
9557 | { | |
9558 | /* Compute the parameter info from the function decl argument | |
9559 | list. */ | |
9560 | tree decl; | |
9561 | int next_parm_info_bit = 31; | |
314fc5a9 | 9562 | |
6041bf2f DE |
9563 | for (decl = DECL_ARGUMENTS (current_function_decl); |
9564 | decl; decl = TREE_CHAIN (decl)) | |
9565 | { | |
9566 | rtx parameter = DECL_INCOMING_RTL (decl); | |
9567 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 9568 | |
6041bf2f DE |
9569 | if (GET_CODE (parameter) == REG) |
9570 | { | |
9571 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
9572 | { | |
9573 | int bits; | |
9574 | ||
9575 | float_parms++; | |
9576 | ||
9577 | if (mode == SFmode) | |
9578 | bits = 0x2; | |
9579 | else if (mode == DFmode) | |
9580 | bits = 0x3; | |
9581 | else | |
9582 | abort (); | |
9583 | ||
9584 | /* If only one bit will fit, don't or in this entry. */ | |
9585 | if (next_parm_info_bit > 0) | |
9586 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
9587 | next_parm_info_bit -= 2; | |
9588 | } | |
9589 | else | |
9590 | { | |
9591 | fixed_parms += ((GET_MODE_SIZE (mode) | |
9592 | + (UNITS_PER_WORD - 1)) | |
9593 | / UNITS_PER_WORD); | |
9594 | next_parm_info_bit -= 1; | |
9595 | } | |
9596 | } | |
9597 | } | |
9598 | } | |
314fc5a9 ILT |
9599 | |
9600 | /* Number of fixed point parameters. */ | |
9601 | /* This is actually the number of words of fixed point parameters; thus | |
9602 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
9603 | fprintf (file, "%d,", fixed_parms); | |
9604 | ||
9605 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
9606 | all on stack. */ | |
9607 | /* This is actually the number of fp registers that hold parameters; | |
9608 | and thus the maximum value is 13. */ | |
9609 | /* Set parameters on stack bit if parameters are not in their original | |
9610 | registers, regardless of whether they are on the stack? Xlc | |
9611 | seems to set the bit when not optimizing. */ | |
9612 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
9613 | ||
6041bf2f DE |
9614 | if (! optional_tbtab) |
9615 | return; | |
9616 | ||
314fc5a9 ILT |
9617 | /* Optional fields follow. Some are variable length. */ |
9618 | ||
9619 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
9620 | 11 double float. */ | |
9621 | /* There is an entry for each parameter in a register, in the order that | |
9622 | they occur in the parameter list. Any intervening arguments on the | |
9623 | stack are ignored. If the list overflows a long (max possible length | |
9624 | 34 bits) then completely leave off all elements that don't fit. */ | |
9625 | /* Only emit this long if there was at least one parameter. */ | |
9626 | if (fixed_parms || float_parms) | |
9627 | fprintf (file, "\t.long %d\n", parm_info); | |
9628 | ||
9629 | /* Offset from start of code to tb table. */ | |
19d2d16f | 9630 | fputs ("\t.long ", file); |
314fc5a9 | 9631 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
9632 | #if TARGET_AIX |
9633 | RS6000_OUTPUT_BASENAME (file, fname); | |
9634 | #else | |
9ebbca7d | 9635 | assemble_name (file, fname); |
54ee9799 | 9636 | #endif |
19d2d16f | 9637 | fputs ("-.", file); |
54ee9799 DE |
9638 | #if TARGET_AIX |
9639 | RS6000_OUTPUT_BASENAME (file, fname); | |
9640 | #else | |
9ebbca7d | 9641 | assemble_name (file, fname); |
54ee9799 | 9642 | #endif |
19d2d16f | 9643 | putc ('\n', file); |
314fc5a9 ILT |
9644 | |
9645 | /* Interrupt handler mask. */ | |
9646 | /* Omit this long, since we never set the interrupt handler bit | |
9647 | above. */ | |
9648 | ||
9649 | /* Number of CTL (controlled storage) anchors. */ | |
9650 | /* Omit this long, since the has_ctl bit is never set above. */ | |
9651 | ||
9652 | /* Displacement into stack of each CTL anchor. */ | |
9653 | /* Omit this list of longs, because there are no CTL anchors. */ | |
9654 | ||
9655 | /* Length of function name. */ | |
296b8152 | 9656 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
9657 | |
9658 | /* Function name. */ | |
9659 | assemble_string (fname, strlen (fname)); | |
9660 | ||
9661 | /* Register for alloca automatic storage; this is always reg 31. | |
9662 | Only emit this if the alloca bit was set above. */ | |
9663 | if (frame_pointer_needed) | |
19d2d16f | 9664 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
9665 | |
9666 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 9667 | } |
6041bf2f | 9668 | return; |
9878760c | 9669 | } |
17167fd8 | 9670 | \f |
a4f6c312 SS |
9671 | /* A C compound statement that outputs the assembler code for a thunk |
9672 | function, used to implement C++ virtual function calls with | |
9673 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
9674 | function, adjusting the implicit object parameter before handing | |
9675 | control off to the real function. | |
9676 | ||
9677 | First, emit code to add the integer DELTA to the location that | |
9678 | contains the incoming first argument. Assume that this argument | |
9679 | contains a pointer, and is the one used to pass the `this' pointer | |
9680 | in C++. This is the incoming argument *before* the function | |
9681 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
9682 | values of all other incoming arguments. | |
17167fd8 MM |
9683 | |
9684 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
9685 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
9686 | not touch the return address. Hence returning from FUNCTION will | |
9687 | return to whoever called the current `thunk'. | |
17167fd8 | 9688 | |
a4f6c312 SS |
9689 | The effect must be as if FUNCTION had been called directly with the |
9690 | adjusted first argument. This macro is responsible for emitting | |
9691 | all of the code for a thunk function; output_function_prologue() | |
9692 | and output_function_epilogue() are not invoked. | |
17167fd8 | 9693 | |
a4f6c312 SS |
9694 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
9695 | been extracted from it.) It might possibly be useful on some | |
9696 | targets, but probably not. | |
17167fd8 | 9697 | |
a4f6c312 SS |
9698 | If you do not define this macro, the target-independent code in the |
9699 | C++ frontend will generate a less efficient heavyweight thunk that | |
9700 | calls FUNCTION instead of jumping to it. The generic approach does | |
9701 | not support varargs. */ | |
17167fd8 MM |
9702 | |
9703 | void | |
9704 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
9705 | FILE *file; | |
d330fd93 | 9706 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
9707 | int delta; |
9708 | tree function; | |
9709 | { | |
a4f6c312 SS |
9710 | const char *this_reg = |
9711 | reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; | |
d330fd93 | 9712 | const char *prefix; |
3cce094d | 9713 | const char *fname; |
d330fd93 | 9714 | const char *r0 = reg_names[0]; |
d330fd93 KG |
9715 | const char *toc = reg_names[2]; |
9716 | const char *schain = reg_names[11]; | |
9717 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
9718 | char buf[512]; |
9719 | static int labelno = 0; | |
9720 | ||
a4f6c312 | 9721 | /* Small constants that can be done by one add instruction. */ |
17167fd8 MM |
9722 | if (delta >= -32768 && delta <= 32767) |
9723 | { | |
22b4a3b0 | 9724 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
9725 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
9726 | else | |
9727 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
9728 | } | |
9729 | ||
a4f6c312 | 9730 | /* Large constants that can be done by one addis instruction. */ |
17167fd8 MM |
9731 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) |
9732 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
9733 | delta >> 16); | |
9734 | ||
9735 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
9736 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
9737 | { | |
a4f6c312 SS |
9738 | /* Break into two pieces, propagating the sign bit from the low |
9739 | word to the upper word. */ | |
17167fd8 MM |
9740 | int delta_high = delta >> 16; |
9741 | int delta_low = delta & 0xffff; | |
9742 | if ((delta_low & 0x8000) != 0) | |
9743 | { | |
9744 | delta_high++; | |
9745 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
9746 | } | |
9747 | ||
9748 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
9749 | delta_high); | |
9750 | ||
22b4a3b0 | 9751 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
9752 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
9753 | else | |
9754 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
9755 | } | |
9756 | ||
9757 | /* 64-bit constants, fixme */ | |
9758 | else | |
9759 | abort (); | |
9760 | ||
9761 | /* Get the prefix in front of the names. */ | |
9762 | switch (DEFAULT_ABI) | |
9763 | { | |
9764 | default: | |
9765 | abort (); | |
9766 | ||
9767 | case ABI_AIX: | |
9768 | prefix = "."; | |
9769 | break; | |
9770 | ||
9771 | case ABI_V4: | |
9772 | case ABI_AIX_NODESC: | |
17167fd8 MM |
9773 | prefix = ""; |
9774 | break; | |
17167fd8 MM |
9775 | } |
9776 | ||
9777 | /* If the function is compiled in this module, jump to it directly. | |
9778 | Otherwise, load up its address and jump to it. */ | |
9779 | ||
9780 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 9781 | |
9ebbca7d | 9782 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
9783 | && ! lookup_attribute ("longcall", |
9784 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
9785 | { |
9786 | fprintf (file, "\tb %s", prefix); | |
9787 | assemble_name (file, fname); | |
22b4a3b0 | 9788 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 9789 | putc ('\n', file); |
17167fd8 MM |
9790 | } |
9791 | ||
9792 | else | |
9793 | { | |
9794 | switch (DEFAULT_ABI) | |
9795 | { | |
9796 | default: | |
17167fd8 MM |
9797 | abort (); |
9798 | ||
9799 | case ABI_AIX: | |
9800 | /* Set up a TOC entry for the function. */ | |
9801 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
9802 | toc_section (); | |
9803 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
9804 | labelno++; | |
9805 | ||
fa9b5c6b DE |
9806 | if (TARGET_MINIMAL_TOC) |
9807 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); | |
9808 | else | |
9809 | { | |
9810 | fputs ("\t.tc ", file); | |
9811 | assemble_name (file, fname); | |
9812 | fputs ("[TC],", file); | |
9813 | } | |
9814 | assemble_name (file, fname); | |
17167fd8 MM |
9815 | putc ('\n', file); |
9816 | text_section (); | |
468e8dba DE |
9817 | if (TARGET_MINIMAL_TOC) |
9818 | asm_fprintf (file, (TARGET_32BIT) | |
9819 | ? "\t{l|lwz} %s,%s(%s)\n" : "\tld %s,%s(%s)\n", r12, | |
9820 | TARGET_ELF ? ".LCTOC0@toc" : ".LCTOC..1", toc); | |
d2574c50 | 9821 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s,", r12); |
17167fd8 | 9822 | assemble_name (file, buf); |
468e8dba DE |
9823 | if (TARGET_ELF && TARGET_MINIMAL_TOC) |
9824 | fputs ("-(.LCTOC1)", file); | |
9825 | asm_fprintf (file, "(%s)\n", TARGET_MINIMAL_TOC ? r12 : toc); | |
17167fd8 MM |
9826 | asm_fprintf (file, |
9827 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
9828 | r0, r12); | |
9829 | ||
9830 | asm_fprintf (file, | |
9831 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
9832 | toc, r12); | |
9833 | ||
9834 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
9835 | asm_fprintf (file, | |
9836 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
9837 | schain, r12); | |
9838 | ||
9839 | asm_fprintf (file, "\tbctr\n"); | |
9840 | break; | |
9841 | ||
9ebbca7d | 9842 | case ABI_AIX_NODESC: |
17167fd8 | 9843 | case ABI_V4: |
22b4a3b0 FS |
9844 | fprintf (file, "\tb %s", prefix); |
9845 | assemble_name (file, fname); | |
9846 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 9847 | putc ('\n', file); |
22b4a3b0 | 9848 | break; |
ee890fe2 SS |
9849 | |
9850 | #if TARGET_MACHO | |
9851 | case ABI_DARWIN: | |
9852 | fprintf (file, "\tb %s", prefix); | |
9853 | if (flag_pic && !machopic_name_defined_p (fname)) | |
9854 | assemble_name (file, machopic_stub_name (fname)); | |
9855 | else | |
9856 | assemble_name (file, fname); | |
9857 | putc ('\n', file); | |
9858 | break; | |
9859 | #endif | |
9ebbca7d GK |
9860 | } |
9861 | } | |
9862 | } | |
42820a49 | 9863 | |
9ebbca7d GK |
9864 | \f |
9865 | /* A quick summary of the various types of 'constant-pool tables' | |
9866 | under PowerPC: | |
9867 | ||
9868 | Target Flags Name One table per | |
9869 | AIX (none) AIX TOC object file | |
9870 | AIX -mfull-toc AIX TOC object file | |
9871 | AIX -mminimal-toc AIX minimal TOC translation unit | |
9872 | SVR4/EABI (none) SVR4 SDATA object file | |
9873 | SVR4/EABI -fpic SVR4 pic object file | |
9874 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
9875 | SVR4/EABI -mrelocatable EABI TOC function | |
9876 | SVR4/EABI -maix AIX TOC object file | |
9877 | SVR4/EABI -maix -mminimal-toc | |
9878 | AIX minimal TOC translation unit | |
9879 | ||
9880 | Name Reg. Set by entries contains: | |
9881 | made by addrs? fp? sum? | |
9882 | ||
9883 | AIX TOC 2 crt0 as Y option option | |
9884 | AIX minimal TOC 30 prolog gcc Y Y option | |
9885 | SVR4 SDATA 13 crt0 gcc N Y N | |
9886 | SVR4 pic 30 prolog ld Y not yet N | |
9887 | SVR4 PIC 30 prolog gcc Y option option | |
9888 | EABI TOC 30 prolog gcc Y option option | |
9889 | ||
9890 | */ | |
9891 | ||
9892 | /* Hash table stuff for keeping track of TOC entries. */ | |
9893 | ||
9894 | struct toc_hash_struct | |
9895 | { | |
9896 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
9897 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
9898 | rtx key; | |
a9098fd0 | 9899 | enum machine_mode key_mode; |
9ebbca7d GK |
9900 | int labelno; |
9901 | }; | |
17167fd8 | 9902 | |
9ebbca7d GK |
9903 | static htab_t toc_hash_table; |
9904 | ||
9905 | /* Hash functions for the hash table. */ | |
9906 | ||
9907 | static unsigned | |
9908 | rs6000_hash_constant (k) | |
9909 | rtx k; | |
9910 | { | |
a9098fd0 | 9911 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
9912 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
9913 | int flen = strlen (format); | |
9914 | int fidx; | |
9915 | ||
9916 | if (GET_CODE (k) == LABEL_REF) | |
832ea3b3 | 9917 | return result * 1231 + X0INT (XEXP (k, 0), 3); |
9ebbca7d GK |
9918 | |
9919 | if (GET_CODE (k) == CONST_DOUBLE) | |
592bf28c | 9920 | fidx = 1; |
9ebbca7d GK |
9921 | else if (GET_CODE (k) == CODE_LABEL) |
9922 | fidx = 3; | |
9923 | else | |
9924 | fidx = 0; | |
9925 | ||
9926 | for (; fidx < flen; fidx++) | |
9927 | switch (format[fidx]) | |
9928 | { | |
9929 | case 's': | |
9930 | { | |
9931 | unsigned i, len; | |
9932 | const char *str = XSTR (k, fidx); | |
9933 | len = strlen (str); | |
9934 | result = result * 613 + len; | |
9935 | for (i = 0; i < len; i++) | |
9936 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
9937 | break; |
9938 | } | |
9ebbca7d GK |
9939 | case 'u': |
9940 | case 'e': | |
9941 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
9942 | break; | |
9943 | case 'i': | |
9944 | case 'n': | |
9945 | result = result * 613 + (unsigned) XINT (k, fidx); | |
9946 | break; | |
9947 | case 'w': | |
9948 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
9949 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
9950 | else | |
9951 | { | |
9952 | size_t i; | |
9953 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
9954 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
9955 | >> CHAR_BIT * i); | |
9956 | } | |
9957 | break; | |
9958 | default: | |
a4f6c312 | 9959 | abort (); |
9ebbca7d GK |
9960 | } |
9961 | return result; | |
9962 | } | |
9963 | ||
9964 | static unsigned | |
9965 | toc_hash_function (hash_entry) | |
9966 | const void * hash_entry; | |
9967 | { | |
a9098fd0 GK |
9968 | const struct toc_hash_struct *thc = |
9969 | (const struct toc_hash_struct *) hash_entry; | |
9970 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
9971 | } |
9972 | ||
9973 | /* Compare H1 and H2 for equivalence. */ | |
9974 | ||
9975 | static int | |
9976 | toc_hash_eq (h1, h2) | |
9977 | const void * h1; | |
9978 | const void * h2; | |
9979 | { | |
9980 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
9981 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
9982 | ||
a9098fd0 GK |
9983 | if (((const struct toc_hash_struct *) h1)->key_mode |
9984 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
9985 | return 0; | |
9986 | ||
9ebbca7d GK |
9987 | /* Gotcha: One of these const_doubles will be in memory. |
9988 | The other may be on the constant-pool chain. | |
a4f6c312 | 9989 | So rtx_equal_p will think they are different... */ |
9ebbca7d GK |
9990 | if (r1 == r2) |
9991 | return 1; | |
9992 | if (GET_CODE (r1) != GET_CODE (r2) | |
9993 | || GET_MODE (r1) != GET_MODE (r2)) | |
9994 | return 0; | |
9995 | if (GET_CODE (r1) == CONST_DOUBLE) | |
9996 | { | |
9997 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
9998 | int i; | |
592bf28c | 9999 | for (i = 1; i < format_len; i++) |
9ebbca7d GK |
10000 | if (XWINT (r1, i) != XWINT (r2, i)) |
10001 | return 0; | |
10002 | ||
10003 | return 1; | |
17167fd8 | 10004 | } |
9ebbca7d | 10005 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
10006 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
10007 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
10008 | else |
10009 | return rtx_equal_p (r1, r2); | |
10010 | } | |
10011 | ||
10012 | /* Mark the hash table-entry HASH_ENTRY. */ | |
10013 | ||
10014 | static int | |
10015 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 10016 | void ** hash_slot; |
9ebbca7d GK |
10017 | void * unused ATTRIBUTE_UNUSED; |
10018 | { | |
10019 | const struct toc_hash_struct * hash_entry = | |
10020 | *(const struct toc_hash_struct **) hash_slot; | |
10021 | rtx r = hash_entry->key; | |
10022 | ggc_set_mark (hash_entry); | |
a4f6c312 | 10023 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ |
9ebbca7d GK |
10024 | if (GET_CODE (r) == LABEL_REF) |
10025 | { | |
10026 | ggc_set_mark (r); | |
10027 | ggc_set_mark (XEXP (r, 0)); | |
10028 | } | |
10029 | else | |
10030 | ggc_mark_rtx (r); | |
10031 | return 1; | |
10032 | } | |
10033 | ||
10034 | /* Mark all the elements of the TOC hash-table *HT. */ | |
10035 | ||
10036 | static void | |
10037 | toc_hash_mark_table (vht) | |
10038 | void *vht; | |
10039 | { | |
10040 | htab_t *ht = vht; | |
10041 | ||
10042 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
10043 | } |
10044 | ||
28e510bd MM |
10045 | /* These are the names given by the C++ front-end to vtables, and |
10046 | vtable-like objects. Ideally, this logic should not be here; | |
10047 | instead, there should be some programmatic way of inquiring as | |
10048 | to whether or not an object is a vtable. */ | |
10049 | ||
10050 | #define VTABLE_NAME_P(NAME) \ | |
10051 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
10052 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
10053 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
10054 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
10055 | ||
10056 | void | |
10057 | rs6000_output_symbol_ref (file, x) | |
10058 | FILE *file; | |
10059 | rtx x; | |
10060 | { | |
10061 | /* Currently C++ toc references to vtables can be emitted before it | |
10062 | is decided whether the vtable is public or private. If this is | |
10063 | the case, then the linker will eventually complain that there is | |
10064 | a reference to an unknown section. Thus, for vtables only, | |
10065 | we emit the TOC reference to reference the symbol and not the | |
10066 | section. */ | |
10067 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
10068 | |
10069 | if (VTABLE_NAME_P (name)) | |
10070 | { | |
10071 | RS6000_OUTPUT_BASENAME (file, name); | |
10072 | } | |
10073 | else | |
10074 | assemble_name (file, name); | |
28e510bd MM |
10075 | } |
10076 | ||
a4f6c312 SS |
10077 | /* Output a TOC entry. We derive the entry name from what is being |
10078 | written. */ | |
9878760c RK |
10079 | |
10080 | void | |
a9098fd0 | 10081 | output_toc (file, x, labelno, mode) |
9878760c RK |
10082 | FILE *file; |
10083 | rtx x; | |
10084 | int labelno; | |
a9098fd0 | 10085 | enum machine_mode mode; |
9878760c RK |
10086 | { |
10087 | char buf[256]; | |
3cce094d | 10088 | const char *name = buf; |
ec940faa | 10089 | const char *real_name; |
9878760c RK |
10090 | rtx base = x; |
10091 | int offset = 0; | |
10092 | ||
4697a36c MM |
10093 | if (TARGET_NO_TOC) |
10094 | abort (); | |
10095 | ||
9ebbca7d GK |
10096 | /* When the linker won't eliminate them, don't output duplicate |
10097 | TOC entries (this happens on AIX if there is any kind of TOC, | |
1f8f4a0b MM |
10098 | and on SVR4 under -fPIC or -mrelocatable). */ |
10099 | if (TARGET_TOC) | |
9ebbca7d GK |
10100 | { |
10101 | struct toc_hash_struct *h; | |
10102 | void * * found; | |
10103 | ||
10104 | h = ggc_alloc (sizeof (*h)); | |
10105 | h->key = x; | |
a9098fd0 | 10106 | h->key_mode = mode; |
9ebbca7d GK |
10107 | h->labelno = labelno; |
10108 | ||
10109 | found = htab_find_slot (toc_hash_table, h, 1); | |
10110 | if (*found == NULL) | |
10111 | *found = h; | |
10112 | else /* This is indeed a duplicate. | |
10113 | Set this label equal to that label. */ | |
10114 | { | |
10115 | fputs ("\t.set ", file); | |
10116 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
10117 | fprintf (file, "%d,", labelno); | |
10118 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
10119 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
10120 | found)->labelno)); | |
10121 | return; | |
10122 | } | |
10123 | } | |
10124 | ||
10125 | /* If we're going to put a double constant in the TOC, make sure it's | |
10126 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
10127 | if (GET_CODE (x) == CONST_DOUBLE |
10128 | && STRICT_ALIGNMENT | |
a9098fd0 | 10129 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
10130 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
10131 | ASM_OUTPUT_ALIGN (file, 3); | |
10132 | } | |
10133 | ||
9ebbca7d | 10134 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 10135 | |
37c37a57 RK |
10136 | /* Handle FP constants specially. Note that if we have a minimal |
10137 | TOC, things we put here aren't actually in the TOC, so we can allow | |
10138 | FP constants. */ | |
a9098fd0 | 10139 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 10140 | { |
042259f2 DE |
10141 | REAL_VALUE_TYPE rv; |
10142 | long k[2]; | |
0adc764e | 10143 | |
042259f2 DE |
10144 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
10145 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 10146 | |
13ded975 DE |
10147 | if (TARGET_64BIT) |
10148 | { | |
10149 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10150 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 10151 | else |
2bfcf297 DB |
10152 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
10153 | fprintf (file, "0x%lx%08lx\n", k[0], k[1]); | |
13ded975 DE |
10154 | return; |
10155 | } | |
1875cc88 | 10156 | else |
13ded975 DE |
10157 | { |
10158 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10159 | fputs ("\t.long ", file); |
13ded975 | 10160 | else |
2bfcf297 DB |
10161 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
10162 | fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]); | |
13ded975 DE |
10163 | return; |
10164 | } | |
9878760c | 10165 | } |
a9098fd0 | 10166 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 10167 | { |
042259f2 DE |
10168 | REAL_VALUE_TYPE rv; |
10169 | long l; | |
9878760c | 10170 | |
042259f2 DE |
10171 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
10172 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
10173 | ||
31bfaa0b DE |
10174 | if (TARGET_64BIT) |
10175 | { | |
10176 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10177 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 10178 | else |
2bfcf297 DB |
10179 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
10180 | fprintf (file, "0x%lx00000000\n", l); | |
31bfaa0b DE |
10181 | return; |
10182 | } | |
042259f2 | 10183 | else |
31bfaa0b DE |
10184 | { |
10185 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10186 | fputs ("\t.long ", file); |
31bfaa0b | 10187 | else |
2bfcf297 DB |
10188 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
10189 | fprintf (file, "0x%lx\n", l); | |
31bfaa0b DE |
10190 | return; |
10191 | } | |
042259f2 | 10192 | } |
f176e826 | 10193 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 10194 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 10195 | { |
e2c953b6 | 10196 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
10197 | HOST_WIDE_INT high; |
10198 | ||
10199 | if (GET_CODE (x) == CONST_DOUBLE) | |
10200 | { | |
10201 | low = CONST_DOUBLE_LOW (x); | |
10202 | high = CONST_DOUBLE_HIGH (x); | |
10203 | } | |
10204 | else | |
10205 | #if HOST_BITS_PER_WIDE_INT == 32 | |
10206 | { | |
10207 | low = INTVAL (x); | |
0858c623 | 10208 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
10209 | } |
10210 | #else | |
10211 | { | |
0858c623 | 10212 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
10213 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
10214 | } | |
10215 | #endif | |
9878760c | 10216 | |
a9098fd0 GK |
10217 | /* TOC entries are always Pmode-sized, but since this |
10218 | is a bigendian machine then if we're putting smaller | |
10219 | integer constants in the TOC we have to pad them. | |
10220 | (This is still a win over putting the constants in | |
10221 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
10222 | to have both a TOC entry _and_ the actual constant.) |
10223 | ||
10224 | For a 32-bit target, CONST_INT values are loaded and shifted | |
10225 | entirely within `low' and can be stored in one TOC entry. */ | |
10226 | ||
10227 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 10228 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
10229 | |
10230 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
a9098fd0 GK |
10231 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), |
10232 | POINTER_SIZE, &low, &high, 0); | |
10233 | ||
13ded975 DE |
10234 | if (TARGET_64BIT) |
10235 | { | |
10236 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10237 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 10238 | else |
e72247f4 | 10239 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long) high, (long) low); |
2bfcf297 | 10240 | fprintf (file, "0x%lx%08lx\n", (long) high, (long) low); |
13ded975 DE |
10241 | return; |
10242 | } | |
1875cc88 | 10243 | else |
13ded975 | 10244 | { |
02a4ec28 FS |
10245 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
10246 | { | |
10247 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10248 | fputs ("\t.long ", file); |
02a4ec28 | 10249 | else |
2bfcf297 | 10250 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
e72247f4 | 10251 | (long) high, (long) low); |
2bfcf297 | 10252 | fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low); |
02a4ec28 | 10253 | } |
13ded975 | 10254 | else |
02a4ec28 FS |
10255 | { |
10256 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10257 | fputs ("\t.long ", file); |
02a4ec28 | 10258 | else |
2bfcf297 DB |
10259 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low); |
10260 | fprintf (file, "0x%lx\n", (long) low); | |
02a4ec28 | 10261 | } |
13ded975 DE |
10262 | return; |
10263 | } | |
9878760c RK |
10264 | } |
10265 | ||
10266 | if (GET_CODE (x) == CONST) | |
10267 | { | |
2bfcf297 DB |
10268 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
10269 | abort (); | |
10270 | ||
9878760c RK |
10271 | base = XEXP (XEXP (x, 0), 0); |
10272 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
10273 | } | |
10274 | ||
10275 | if (GET_CODE (base) == SYMBOL_REF) | |
10276 | name = XSTR (base, 0); | |
10277 | else if (GET_CODE (base) == LABEL_REF) | |
10278 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
10279 | else if (GET_CODE (base) == CODE_LABEL) | |
10280 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
10281 | else | |
10282 | abort (); | |
10283 | ||
2e4eb9b0 | 10284 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 10285 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 10286 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
10287 | else |
10288 | { | |
b6c9286a | 10289 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 10290 | |
1875cc88 JW |
10291 | if (offset < 0) |
10292 | fprintf (file, ".N%d", - offset); | |
10293 | else if (offset) | |
10294 | fprintf (file, ".P%d", offset); | |
9878760c | 10295 | |
19d2d16f | 10296 | fputs ("[TC],", file); |
1875cc88 | 10297 | } |
581bc4de MM |
10298 | |
10299 | /* Currently C++ toc references to vtables can be emitted before it | |
10300 | is decided whether the vtable is public or private. If this is | |
10301 | the case, then the linker will eventually complain that there is | |
10302 | a TOC reference to an unknown section. Thus, for vtables only, | |
10303 | we emit the TOC reference to reference the symbol and not the | |
10304 | section. */ | |
28e510bd | 10305 | if (VTABLE_NAME_P (name)) |
581bc4de | 10306 | { |
54ee9799 | 10307 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
10308 | if (offset < 0) |
10309 | fprintf (file, "%d", offset); | |
10310 | else if (offset > 0) | |
10311 | fprintf (file, "+%d", offset); | |
10312 | } | |
10313 | else | |
10314 | output_addr_const (file, x); | |
19d2d16f | 10315 | putc ('\n', file); |
9878760c RK |
10316 | } |
10317 | \f | |
10318 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
10319 | starting at P to FILE. | |
10320 | ||
10321 | On the RS/6000, we have to do this using the .byte operation and | |
10322 | write out special characters outside the quoted string. | |
10323 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 10324 | so we must artificially break them up early. */ |
9878760c RK |
10325 | |
10326 | void | |
10327 | output_ascii (file, p, n) | |
10328 | FILE *file; | |
d330fd93 | 10329 | const char *p; |
9878760c RK |
10330 | int n; |
10331 | { | |
10332 | char c; | |
10333 | int i, count_string; | |
d330fd93 KG |
10334 | const char *for_string = "\t.byte \""; |
10335 | const char *for_decimal = "\t.byte "; | |
10336 | const char *to_close = NULL; | |
9878760c RK |
10337 | |
10338 | count_string = 0; | |
10339 | for (i = 0; i < n; i++) | |
10340 | { | |
10341 | c = *p++; | |
10342 | if (c >= ' ' && c < 0177) | |
10343 | { | |
10344 | if (for_string) | |
10345 | fputs (for_string, file); | |
10346 | putc (c, file); | |
10347 | ||
10348 | /* Write two quotes to get one. */ | |
10349 | if (c == '"') | |
10350 | { | |
10351 | putc (c, file); | |
10352 | ++count_string; | |
10353 | } | |
10354 | ||
10355 | for_string = NULL; | |
10356 | for_decimal = "\"\n\t.byte "; | |
10357 | to_close = "\"\n"; | |
10358 | ++count_string; | |
10359 | ||
10360 | if (count_string >= 512) | |
10361 | { | |
10362 | fputs (to_close, file); | |
10363 | ||
10364 | for_string = "\t.byte \""; | |
10365 | for_decimal = "\t.byte "; | |
10366 | to_close = NULL; | |
10367 | count_string = 0; | |
10368 | } | |
10369 | } | |
10370 | else | |
10371 | { | |
10372 | if (for_decimal) | |
10373 | fputs (for_decimal, file); | |
10374 | fprintf (file, "%d", c); | |
10375 | ||
10376 | for_string = "\n\t.byte \""; | |
10377 | for_decimal = ", "; | |
10378 | to_close = "\n"; | |
10379 | count_string = 0; | |
10380 | } | |
10381 | } | |
10382 | ||
10383 | /* Now close the string if we have written one. Then end the line. */ | |
10384 | if (to_close) | |
9ebbca7d | 10385 | fputs (to_close, file); |
9878760c RK |
10386 | } |
10387 | \f | |
10388 | /* Generate a unique section name for FILENAME for a section type | |
10389 | represented by SECTION_DESC. Output goes into BUF. | |
10390 | ||
10391 | SECTION_DESC can be any string, as long as it is different for each | |
10392 | possible section type. | |
10393 | ||
10394 | We name the section in the same manner as xlc. The name begins with an | |
10395 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
10396 | names) with the last period replaced by the string SECTION_DESC. If |
10397 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
10398 | the name. */ | |
9878760c RK |
10399 | |
10400 | void | |
10401 | rs6000_gen_section_name (buf, filename, section_desc) | |
10402 | char **buf; | |
9ebbca7d GK |
10403 | const char *filename; |
10404 | const char *section_desc; | |
9878760c | 10405 | { |
9ebbca7d | 10406 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
10407 | char *p; |
10408 | int len; | |
9878760c RK |
10409 | |
10410 | after_last_slash = filename; | |
10411 | for (q = filename; *q; q++) | |
11e5fe42 RK |
10412 | { |
10413 | if (*q == '/') | |
10414 | after_last_slash = q + 1; | |
10415 | else if (*q == '.') | |
10416 | last_period = q; | |
10417 | } | |
9878760c | 10418 | |
11e5fe42 | 10419 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
10420 | *buf = (char *) permalloc (len); |
10421 | ||
10422 | p = *buf; | |
10423 | *p++ = '_'; | |
10424 | ||
10425 | for (q = after_last_slash; *q; q++) | |
10426 | { | |
11e5fe42 | 10427 | if (q == last_period) |
9878760c RK |
10428 | { |
10429 | strcpy (p, section_desc); | |
10430 | p += strlen (section_desc); | |
9878760c RK |
10431 | } |
10432 | ||
e9a780ec | 10433 | else if (ISALNUM (*q)) |
9878760c RK |
10434 | *p++ = *q; |
10435 | } | |
10436 | ||
11e5fe42 | 10437 | if (last_period == 0) |
9878760c RK |
10438 | strcpy (p, section_desc); |
10439 | else | |
10440 | *p = '\0'; | |
10441 | } | |
e165f3f0 | 10442 | \f |
a4f6c312 | 10443 | /* Emit profile function. */ |
411707f4 | 10444 | |
411707f4 CC |
10445 | void |
10446 | output_profile_hook (labelno) | |
10447 | int labelno; | |
10448 | { | |
8480e480 CC |
10449 | if (DEFAULT_ABI == ABI_AIX) |
10450 | { | |
10451 | char buf[30]; | |
40501e5f | 10452 | const char *label_name; |
8480e480 | 10453 | rtx fun; |
411707f4 | 10454 | |
8480e480 | 10455 | labelno += 1; |
411707f4 | 10456 | |
8480e480 CC |
10457 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
10458 | STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); | |
10459 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 10460 | |
8480e480 CC |
10461 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
10462 | fun, Pmode); | |
10463 | } | |
ee890fe2 SS |
10464 | else if (DEFAULT_ABI == ABI_DARWIN) |
10465 | { | |
d5fa86ba | 10466 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
10467 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
10468 | ||
10469 | /* Be conservative and always set this, at least for now. */ | |
10470 | current_function_uses_pic_offset_table = 1; | |
10471 | ||
10472 | #if TARGET_MACHO | |
10473 | /* For PIC code, set up a stub and collect the caller's address | |
10474 | from r0, which is where the prologue puts it. */ | |
10475 | if (flag_pic) | |
10476 | { | |
10477 | mcount_name = machopic_stub_name (mcount_name); | |
10478 | if (current_function_uses_pic_offset_table) | |
10479 | caller_addr_regno = 0; | |
10480 | } | |
10481 | #endif | |
10482 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
10483 | 0, VOIDmode, 1, | |
10484 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
10485 | } | |
411707f4 CC |
10486 | } |
10487 | ||
a4f6c312 | 10488 | /* Write function profiler code. */ |
e165f3f0 RK |
10489 | |
10490 | void | |
10491 | output_function_profiler (file, labelno) | |
10492 | FILE *file; | |
10493 | int labelno; | |
10494 | { | |
3daf36a4 | 10495 | char buf[100]; |
e165f3f0 | 10496 | |
3daf36a4 | 10497 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 10498 | switch (DEFAULT_ABI) |
3daf36a4 | 10499 | { |
38c1f2d7 MM |
10500 | default: |
10501 | abort (); | |
10502 | ||
10503 | case ABI_V4: | |
38c1f2d7 MM |
10504 | case ABI_AIX_NODESC: |
10505 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
10506 | if (flag_pic == 1) | |
10507 | { | |
dfdfa60f DE |
10508 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
10509 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
10510 | reg_names[0], reg_names[1]); | |
17167fd8 | 10511 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 10512 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 10513 | assemble_name (file, buf); |
17167fd8 | 10514 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 10515 | } |
9ebbca7d | 10516 | else if (flag_pic > 1) |
38c1f2d7 | 10517 | { |
dfdfa60f DE |
10518 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
10519 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
10520 | /* Now, we need to get the address of the label. */ |
10521 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 10522 | assemble_name (file, buf); |
9ebbca7d GK |
10523 | fputs ("-.\n1:", file); |
10524 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
10525 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
10526 | reg_names[0], reg_names[11]); | |
10527 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
10528 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 10529 | } |
38c1f2d7 MM |
10530 | else |
10531 | { | |
17167fd8 | 10532 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 10533 | assemble_name (file, buf); |
dfdfa60f | 10534 | fputs ("@ha\n", file); |
b5253831 DE |
10535 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
10536 | reg_names[0], reg_names[1]); | |
a260abc9 | 10537 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 10538 | assemble_name (file, buf); |
17167fd8 | 10539 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
10540 | } |
10541 | ||
b5253831 DE |
10542 | if (current_function_needs_context) |
10543 | asm_fprintf (file, "\tmr %s,%s\n", | |
10544 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 10545 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
10546 | if (current_function_needs_context) |
10547 | asm_fprintf (file, "\tmr %s,%s\n", | |
10548 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
10549 | break; |
10550 | ||
10551 | case ABI_AIX: | |
ee890fe2 | 10552 | case ABI_DARWIN: |
a4f6c312 | 10553 | /* Don't do anything, done in output_profile_hook (). */ |
38c1f2d7 | 10554 | break; |
411707f4 | 10555 | |
38c1f2d7 | 10556 | } |
e165f3f0 | 10557 | } |
a251ffd0 TG |
10558 | |
10559 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
10560 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
10561 | ||
c237e94a | 10562 | static int |
a06faf84 | 10563 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
10564 | rtx insn; |
10565 | rtx link; | |
296b8152 | 10566 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
10567 | int cost; |
10568 | { | |
10569 | if (! recog_memoized (insn)) | |
10570 | return 0; | |
10571 | ||
10572 | if (REG_NOTE_KIND (link) != 0) | |
10573 | return 0; | |
10574 | ||
10575 | if (REG_NOTE_KIND (link) == 0) | |
10576 | { | |
ed947a96 DJ |
10577 | /* Data dependency; DEP_INSN writes a register that INSN reads |
10578 | some cycles later. */ | |
10579 | switch (get_attr_type (insn)) | |
10580 | { | |
10581 | case TYPE_JMPREG: | |
10582 | /* Tell the first scheduling pass about the latency between | |
10583 | a mtctr and bctr (and mtlr and br/blr). The first | |
10584 | scheduling pass will not know about this latency since | |
10585 | the mtctr instruction, which has the latency associated | |
10586 | to it, will be generated by reload. */ | |
10587 | return TARGET_POWER ? 5 : 4; | |
10588 | case TYPE_BRANCH: | |
10589 | /* Leave some extra cycles between a compare and its | |
10590 | dependent branch, to inhibit expensive mispredicts. */ | |
10591 | if ((rs6000_cpu_attr == CPU_PPC750 | |
10592 | || rs6000_cpu_attr == CPU_PPC7400 | |
10593 | || rs6000_cpu_attr == CPU_PPC7450) | |
10594 | && recog_memoized (dep_insn) | |
10595 | && (INSN_CODE (dep_insn) >= 0) | |
10596 | && (get_attr_type (dep_insn) == TYPE_COMPARE | |
10597 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE | |
10598 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE | |
10599 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL)) | |
10600 | return cost + 2; | |
10601 | default: | |
10602 | break; | |
10603 | } | |
a251ffd0 TG |
10604 | /* Fall out to return default cost. */ |
10605 | } | |
10606 | ||
10607 | return cost; | |
10608 | } | |
b6c9286a | 10609 | |
a4f6c312 SS |
10610 | /* A C statement (sans semicolon) to update the integer scheduling |
10611 | priority INSN_PRIORITY (INSN). Reduce the priority to execute the | |
10612 | INSN earlier, increase the priority to execute INSN later. Do not | |
10613 | define this macro if you do not need to adjust the scheduling | |
10614 | priorities of insns. */ | |
bef84347 | 10615 | |
c237e94a | 10616 | static int |
bef84347 | 10617 | rs6000_adjust_priority (insn, priority) |
d330fd93 | 10618 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
10619 | int priority; |
10620 | { | |
a4f6c312 SS |
10621 | /* On machines (like the 750) which have asymmetric integer units, |
10622 | where one integer unit can do multiply and divides and the other | |
10623 | can't, reduce the priority of multiply/divide so it is scheduled | |
10624 | before other integer operations. */ | |
bef84347 VM |
10625 | |
10626 | #if 0 | |
2c3c49de | 10627 | if (! INSN_P (insn)) |
bef84347 VM |
10628 | return priority; |
10629 | ||
10630 | if (GET_CODE (PATTERN (insn)) == USE) | |
10631 | return priority; | |
10632 | ||
10633 | switch (rs6000_cpu_attr) { | |
10634 | case CPU_PPC750: | |
10635 | switch (get_attr_type (insn)) | |
10636 | { | |
10637 | default: | |
10638 | break; | |
10639 | ||
10640 | case TYPE_IMUL: | |
10641 | case TYPE_IDIV: | |
3cb999d8 DE |
10642 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
10643 | priority, priority); | |
bef84347 VM |
10644 | if (priority >= 0 && priority < 0x01000000) |
10645 | priority >>= 3; | |
10646 | break; | |
10647 | } | |
10648 | } | |
10649 | #endif | |
10650 | ||
10651 | return priority; | |
10652 | } | |
10653 | ||
a4f6c312 SS |
10654 | /* Return how many instructions the machine can issue per cycle. */ |
10655 | ||
c237e94a ZW |
10656 | static int |
10657 | rs6000_issue_rate () | |
b6c9286a MM |
10658 | { |
10659 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
10660 | case CPU_RIOS1: /* ? */ |
10661 | case CPU_RS64A: | |
10662 | case CPU_PPC601: /* ? */ | |
ed947a96 | 10663 | case CPU_PPC7450: |
3cb999d8 | 10664 | return 3; |
b6c9286a | 10665 | case CPU_PPC603: |
bef84347 | 10666 | case CPU_PPC750: |
ed947a96 | 10667 | case CPU_PPC7400: |
bef84347 | 10668 | return 2; |
3cb999d8 | 10669 | case CPU_RIOS2: |
b6c9286a | 10670 | case CPU_PPC604: |
19684119 | 10671 | case CPU_PPC604E: |
b6c9286a | 10672 | case CPU_PPC620: |
3cb999d8 | 10673 | case CPU_PPC630: |
b6c9286a MM |
10674 | return 4; |
10675 | default: | |
10676 | return 1; | |
10677 | } | |
10678 | } | |
10679 | ||
b6c9286a | 10680 | \f |
b6c9286a MM |
10681 | /* Length in units of the trampoline for entering a nested function. */ |
10682 | ||
10683 | int | |
10684 | rs6000_trampoline_size () | |
10685 | { | |
10686 | int ret = 0; | |
10687 | ||
10688 | switch (DEFAULT_ABI) | |
10689 | { | |
10690 | default: | |
10691 | abort (); | |
10692 | ||
10693 | case ABI_AIX: | |
8f802bfb | 10694 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
10695 | break; |
10696 | ||
4dabc42d | 10697 | case ABI_DARWIN: |
b6c9286a MM |
10698 | case ABI_V4: |
10699 | case ABI_AIX_NODESC: | |
03a7e1a5 | 10700 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 10701 | break; |
b6c9286a MM |
10702 | } |
10703 | ||
10704 | return ret; | |
10705 | } | |
10706 | ||
10707 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
10708 | FNADDR is an RTX for the address of the function's pure code. | |
10709 | CXT is an RTX for the static chain value for the function. */ | |
10710 | ||
10711 | void | |
10712 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
10713 | rtx addr; | |
10714 | rtx fnaddr; | |
10715 | rtx cxt; | |
10716 | { | |
ac2a93a1 | 10717 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
10718 | int regsize = (TARGET_32BIT) ? 4 : 8; |
10719 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
10720 | |
10721 | switch (DEFAULT_ABI) | |
10722 | { | |
10723 | default: | |
10724 | abort (); | |
10725 | ||
8bd04c56 | 10726 | /* Macros to shorten the code expansions below. */ |
39403d82 | 10727 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
10728 | #define MEM_PLUS(addr,offset) \ |
10729 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 10730 | |
b6c9286a MM |
10731 | /* Under AIX, just build the 3 word function descriptor */ |
10732 | case ABI_AIX: | |
8bd04c56 MM |
10733 | { |
10734 | rtx fn_reg = gen_reg_rtx (pmode); | |
10735 | rtx toc_reg = gen_reg_rtx (pmode); | |
10736 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 10737 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
10738 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
10739 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
10740 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
10741 | } | |
b6c9286a MM |
10742 | break; |
10743 | ||
4dabc42d TC |
10744 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
10745 | case ABI_DARWIN: | |
b6c9286a MM |
10746 | case ABI_V4: |
10747 | case ABI_AIX_NODESC: | |
39403d82 | 10748 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
10749 | FALSE, VOIDmode, 4, |
10750 | addr, pmode, | |
10751 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
10752 | fnaddr, pmode, | |
10753 | ctx_reg, pmode); | |
b6c9286a | 10754 | break; |
b6c9286a MM |
10755 | } |
10756 | ||
10757 | return; | |
10758 | } | |
7509c759 MM |
10759 | |
10760 | \f | |
91d231cb | 10761 | /* Table of valid machine attributes. */ |
a4f6c312 | 10762 | |
91d231cb | 10763 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 10764 | { |
91d231cb JM |
10765 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
10766 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
10767 | { NULL, 0, 0, false, false, false, NULL } | |
10768 | }; | |
7509c759 | 10769 | |
a4f6c312 SS |
10770 | /* Handle a "longcall" attribute; arguments as in struct |
10771 | attribute_spec.handler. */ | |
10772 | ||
91d231cb JM |
10773 | static tree |
10774 | rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) | |
10775 | tree *node; | |
10776 | tree name; | |
10777 | tree args ATTRIBUTE_UNUSED; | |
10778 | int flags ATTRIBUTE_UNUSED; | |
10779 | bool *no_add_attrs; | |
10780 | { | |
10781 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
10782 | && TREE_CODE (*node) != FIELD_DECL | |
10783 | && TREE_CODE (*node) != TYPE_DECL) | |
10784 | { | |
10785 | warning ("`%s' attribute only applies to functions", | |
10786 | IDENTIFIER_POINTER (name)); | |
10787 | *no_add_attrs = true; | |
10788 | } | |
6a4cee5f | 10789 | |
91d231cb | 10790 | return NULL_TREE; |
7509c759 MM |
10791 | } |
10792 | ||
3cb999d8 DE |
10793 | /* Return a reference suitable for calling a function with the |
10794 | longcall attribute. */ | |
a4f6c312 | 10795 | |
6a4cee5f MM |
10796 | struct rtx_def * |
10797 | rs6000_longcall_ref (call_ref) | |
10798 | rtx call_ref; | |
10799 | { | |
d330fd93 | 10800 | const char *call_name; |
6a4cee5f MM |
10801 | tree node; |
10802 | ||
10803 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
10804 | return call_ref; | |
10805 | ||
10806 | /* System V adds '.' to the internal name, so skip them. */ | |
10807 | call_name = XSTR (call_ref, 0); | |
10808 | if (*call_name == '.') | |
10809 | { | |
10810 | while (*call_name == '.') | |
10811 | call_name++; | |
10812 | ||
10813 | node = get_identifier (call_name); | |
39403d82 | 10814 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
10815 | } |
10816 | ||
10817 | return force_reg (Pmode, call_ref); | |
10818 | } | |
10819 | ||
7509c759 MM |
10820 | \f |
10821 | /* A C statement or statements to switch to the appropriate section | |
10822 | for output of RTX in mode MODE. You can assume that RTX is some | |
10823 | kind of constant in RTL. The argument MODE is redundant except in | |
10824 | the case of a `const_int' rtx. Select the section by calling | |
10825 | `text_section' or one of the alternatives for other sections. | |
10826 | ||
10827 | Do not define this macro if you put all constants in the read-only | |
10828 | data section. */ | |
10829 | ||
b91da81f | 10830 | #ifdef USING_ELFOS_H |
7509c759 MM |
10831 | |
10832 | void | |
10833 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 10834 | enum machine_mode mode; |
7509c759 MM |
10835 | rtx x; |
10836 | { | |
a9098fd0 | 10837 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 10838 | toc_section (); |
7509c759 MM |
10839 | else |
10840 | const_section (); | |
10841 | } | |
10842 | ||
10843 | /* A C statement or statements to switch to the appropriate | |
10844 | section for output of DECL. DECL is either a `VAR_DECL' node | |
10845 | or a constant of some sort. RELOC indicates whether forming | |
10846 | the initial value of DECL requires link-time relocations. */ | |
10847 | ||
10848 | void | |
10849 | rs6000_select_section (decl, reloc) | |
10850 | tree decl; | |
10851 | int reloc; | |
10852 | { | |
10853 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
10854 | int needs_sdata; |
10855 | int readonly; | |
10856 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
10857 | &const_section, | |
10858 | &sdata2_section, | |
10859 | &data_section, | |
10860 | &sdata_section | |
10861 | }; | |
10862 | ||
10863 | needs_sdata = (size > 0 | |
10864 | && size <= g_switch_value | |
10865 | && rs6000_sdata != SDATA_NONE | |
10866 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
10867 | |
10868 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 10869 | readonly = ! flag_writable_strings; |
a9098fd0 | 10870 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
10871 | readonly = (! (flag_pic && reloc) |
10872 | && TREE_READONLY (decl) | |
10873 | && ! TREE_SIDE_EFFECTS (decl) | |
10874 | && DECL_INITIAL (decl) | |
10875 | && DECL_INITIAL (decl) != error_mark_node | |
10876 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
ac4f7ad9 GK |
10877 | else if (TREE_CODE (decl) == CONSTRUCTOR) |
10878 | readonly = (! (flag_pic && reloc) | |
ac4f7ad9 | 10879 | && ! TREE_SIDE_EFFECTS (decl) |
f3afc192 | 10880 | && TREE_CONSTANT (decl)); |
7509c759 | 10881 | else |
63019373 GK |
10882 | readonly = 1; |
10883 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
10884 | readonly = 0; | |
10885 | ||
10886 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
10887 | } | |
10888 | ||
10889 | /* A C statement to build up a unique section name, expressed as a | |
10890 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
10891 | RELOC indicates whether the initial value of EXP requires | |
10892 | link-time relocations. If you do not define this macro, GCC will use | |
10893 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 10894 | macro can now be called for uninitialized data items as well as |
63019373 GK |
10895 | initialised data and functions. */ |
10896 | ||
10897 | void | |
10898 | rs6000_unique_section (decl, reloc) | |
10899 | tree decl; | |
10900 | int reloc; | |
10901 | { | |
63019373 GK |
10902 | int len; |
10903 | int sec; | |
10904 | const char *name; | |
10905 | char *string; | |
10906 | const char *prefix; | |
10907 | ||
10908 | static const char *const prefixes[7][2] = | |
10909 | { | |
63019373 GK |
10910 | { ".rodata.", ".gnu.linkonce.r." }, |
10911 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
10912 | { ".data.", ".gnu.linkonce.d." }, | |
10913 | { ".sdata.", ".gnu.linkonce.s." }, | |
10914 | { ".bss.", ".gnu.linkonce.b." }, | |
5b8c2356 AM |
10915 | { ".sbss.", ".gnu.linkonce.sb." }, |
10916 | { ".text.", ".gnu.linkonce.t." } | |
63019373 | 10917 | }; |
63019373 | 10918 | |
5b8c2356 AM |
10919 | if (TREE_CODE (decl) == FUNCTION_DECL) |
10920 | sec = 6; | |
63019373 | 10921 | else |
5b8c2356 AM |
10922 | { |
10923 | int readonly; | |
10924 | int needs_sdata; | |
10925 | int size; | |
10926 | ||
10927 | readonly = 1; | |
10928 | if (TREE_CODE (decl) == STRING_CST) | |
10929 | readonly = ! flag_writable_strings; | |
10930 | else if (TREE_CODE (decl) == VAR_DECL) | |
10931 | readonly = (! (flag_pic && reloc) | |
10932 | && TREE_READONLY (decl) | |
10933 | && ! TREE_SIDE_EFFECTS (decl) | |
10934 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
10935 | ||
10936 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
10937 | needs_sdata = (size > 0 | |
10938 | && size <= g_switch_value | |
10939 | && rs6000_sdata != SDATA_NONE | |
10940 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
10941 | ||
10942 | if (DECL_INITIAL (decl) == 0 | |
10943 | || DECL_INITIAL (decl) == error_mark_node) | |
10944 | sec = 4; | |
10945 | else if (! readonly) | |
10946 | sec = 2; | |
10947 | else | |
10948 | sec = 0; | |
63019373 | 10949 | |
5b8c2356 AM |
10950 | if (needs_sdata) |
10951 | { | |
10952 | /* .sdata2 is only for EABI. */ | |
10953 | if (sec == 0 && rs6000_sdata != SDATA_EABI) | |
10954 | sec = 2; | |
10955 | sec += 1; | |
10956 | } | |
10957 | } | |
63019373 | 10958 | |
e6978109 | 10959 | STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); |
63019373 GK |
10960 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; |
10961 | len = strlen (name) + strlen (prefix); | |
10962 | string = alloca (len + 1); | |
10963 | ||
10964 | sprintf (string, "%s%s", prefix, name); | |
10965 | ||
10966 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 10967 | } |
d9407988 MM |
10968 | |
10969 | \f | |
d9407988 MM |
10970 | /* If we are referencing a function that is static or is known to be |
10971 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
10972 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 10973 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
10974 | function name with the real name (1 or 2 leading .'s), rather than |
10975 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 10976 | to read the prefixes. */ |
d9407988 MM |
10977 | |
10978 | void | |
b2003250 | 10979 | rs6000_encode_section_info (decl, first) |
d9407988 | 10980 | tree decl; |
b2003250 | 10981 | int first; |
d9407988 | 10982 | { |
b2003250 RH |
10983 | if (!first) |
10984 | return; | |
10985 | ||
d9407988 MM |
10986 | if (TREE_CODE (decl) == FUNCTION_DECL) |
10987 | { | |
10988 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 10989 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 10990 | && ! DECL_WEAK (decl)) |
d9407988 MM |
10991 | SYMBOL_REF_FLAG (sym_ref) = 1; |
10992 | ||
9ebbca7d | 10993 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 10994 | { |
ff669a6c RH |
10995 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
10996 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 10997 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
10998 | str[0] = '.'; |
10999 | str[1] = '.'; | |
11000 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
11001 | ||
520a57c8 | 11002 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
11003 | } |
11004 | } | |
11005 | else if (rs6000_sdata != SDATA_NONE | |
f607bc57 | 11006 | && DEFAULT_ABI == ABI_V4 |
d9407988 MM |
11007 | && TREE_CODE (decl) == VAR_DECL) |
11008 | { | |
11009 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
11010 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 11011 | const char *name = (char *)0; |
d9407988 MM |
11012 | int len = 0; |
11013 | ||
11014 | if (section_name) | |
11015 | { | |
11016 | if (TREE_CODE (section_name) == STRING_CST) | |
11017 | { | |
11018 | name = TREE_STRING_POINTER (section_name); | |
11019 | len = TREE_STRING_LENGTH (section_name); | |
11020 | } | |
11021 | else | |
11022 | abort (); | |
11023 | } | |
11024 | ||
11025 | if ((size > 0 && size <= g_switch_value) | |
11026 | || (name | |
5f59ecb7 | 11027 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 11028 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 11029 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 11030 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 11031 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 11032 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 11033 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 11034 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 11035 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 11036 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 11037 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 11038 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
11039 | { |
11040 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c | 11041 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 11042 | char *str = alloca (len + 2); |
ff669a6c | 11043 | |
ff669a6c RH |
11044 | str[0] = '@'; |
11045 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 11046 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
11047 | } |
11048 | } | |
11049 | } | |
11050 | ||
b91da81f | 11051 | #endif /* USING_ELFOS_H */ |
000034eb | 11052 | |
a6c2a102 | 11053 | \f |
000034eb | 11054 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
11055 | ADDR can be effectively incremented by incrementing REG. |
11056 | ||
11057 | r0 is special and we must not select it as an address | |
11058 | register by this routine since our caller will try to | |
11059 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
11060 | |
11061 | struct rtx_def * | |
11062 | find_addr_reg (addr) | |
11063 | rtx addr; | |
11064 | { | |
11065 | while (GET_CODE (addr) == PLUS) | |
11066 | { | |
02441cd6 JL |
11067 | if (GET_CODE (XEXP (addr, 0)) == REG |
11068 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 11069 | addr = XEXP (addr, 0); |
02441cd6 JL |
11070 | else if (GET_CODE (XEXP (addr, 1)) == REG |
11071 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
11072 | addr = XEXP (addr, 1); |
11073 | else if (CONSTANT_P (XEXP (addr, 0))) | |
11074 | addr = XEXP (addr, 1); | |
11075 | else if (CONSTANT_P (XEXP (addr, 1))) | |
11076 | addr = XEXP (addr, 0); | |
11077 | else | |
11078 | abort (); | |
11079 | } | |
02441cd6 | 11080 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
11081 | return addr; |
11082 | abort (); | |
11083 | } | |
11084 | ||
a6c2a102 DE |
11085 | void |
11086 | rs6000_fatal_bad_address (op) | |
11087 | rtx op; | |
11088 | { | |
11089 | fatal_insn ("bad address", op); | |
11090 | } | |
c8023011 MM |
11091 | |
11092 | /* Called to register all of our global variables with the garbage | |
11093 | collector. */ | |
11094 | ||
11095 | static void | |
11096 | rs6000_add_gc_roots () | |
11097 | { | |
11098 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
11099 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
11100 | |
11101 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
11102 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
11103 | toc_hash_mark_table); | |
ee890fe2 SS |
11104 | |
11105 | #if TARGET_MACHO | |
11106 | machopic_add_gc_roots (); | |
11107 | #endif | |
11108 | } | |
11109 | ||
11110 | #if TARGET_MACHO | |
11111 | ||
11112 | #if 0 | |
11113 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
11114 | reference and a constant. */ | |
11115 | ||
11116 | int | |
11117 | symbolic_operand (op) | |
592696dd | 11118 | rtx op; |
ee890fe2 SS |
11119 | { |
11120 | switch (GET_CODE (op)) | |
11121 | { | |
11122 | case SYMBOL_REF: | |
11123 | case LABEL_REF: | |
11124 | return 1; | |
11125 | case CONST: | |
11126 | op = XEXP (op, 0); | |
11127 | return (GET_CODE (op) == SYMBOL_REF || | |
11128 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
11129 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
11130 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
11131 | default: | |
11132 | return 0; | |
11133 | } | |
c8023011 | 11134 | } |
ee890fe2 SS |
11135 | #endif |
11136 | ||
11137 | #ifdef RS6000_LONG_BRANCH | |
11138 | ||
11139 | static tree stub_list = 0; | |
11140 | ||
11141 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
11142 | procedure calls to the linked list. */ | |
11143 | ||
11144 | void | |
11145 | add_compiler_stub (label_name, function_name, line_number) | |
11146 | tree label_name; | |
11147 | tree function_name; | |
11148 | int line_number; | |
11149 | { | |
11150 | tree stub = build_tree_list (function_name, label_name); | |
11151 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
11152 | TREE_CHAIN (stub) = stub_list; | |
11153 | stub_list = stub; | |
11154 | } | |
11155 | ||
11156 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
11157 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
11158 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
11159 | ||
a4f6c312 SS |
11160 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for |
11161 | handling procedure calls from the linked list and initializes the | |
11162 | linked list. */ | |
ee890fe2 | 11163 | |
a4f6c312 SS |
11164 | void |
11165 | output_compiler_stub () | |
ee890fe2 SS |
11166 | { |
11167 | char tmp_buf[256]; | |
11168 | char label_buf[256]; | |
11169 | char *label; | |
11170 | tree tmp_stub, stub; | |
11171 | ||
11172 | if (!flag_pic) | |
11173 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
11174 | { | |
11175 | fprintf (asm_out_file, | |
11176 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
11177 | ||
11178 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
11179 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
11180 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
11181 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
11182 | ||
11183 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
11184 | strcpy (label_buf, | |
11185 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
11186 | else | |
11187 | { | |
11188 | label_buf[0] = '_'; | |
11189 | strcpy (label_buf+1, | |
11190 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
11191 | } | |
11192 | ||
11193 | strcpy (tmp_buf, "lis r12,hi16("); | |
11194 | strcat (tmp_buf, label_buf); | |
11195 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
11196 | strcat (tmp_buf, label_buf); | |
11197 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
11198 | output_asm_insn (tmp_buf, 0); | |
11199 | ||
11200 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
11201 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
11202 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
11203 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
11204 | } | |
11205 | ||
11206 | stub_list = 0; | |
11207 | } | |
11208 | ||
11209 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
11210 | already there or not. */ | |
11211 | ||
a4f6c312 SS |
11212 | int |
11213 | no_previous_def (function_name) | |
ee890fe2 SS |
11214 | tree function_name; |
11215 | { | |
11216 | tree stub; | |
11217 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
11218 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
11219 | return 0; | |
11220 | return 1; | |
11221 | } | |
11222 | ||
11223 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
11224 | the function. */ | |
11225 | ||
a4f6c312 SS |
11226 | tree |
11227 | get_prev_label (function_name) | |
ee890fe2 SS |
11228 | tree function_name; |
11229 | { | |
11230 | tree stub; | |
11231 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
11232 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
11233 | return STUB_LABEL_NAME (stub); | |
11234 | return 0; | |
11235 | } | |
11236 | ||
11237 | /* INSN is either a function call or a millicode call. It may have an | |
11238 | unconditional jump in its delay slot. | |
11239 | ||
11240 | CALL_DEST is the routine we are calling. */ | |
11241 | ||
11242 | char * | |
11243 | output_call (insn, call_dest, operand_number) | |
11244 | rtx insn; | |
11245 | rtx call_dest; | |
11246 | int operand_number; | |
11247 | { | |
11248 | static char buf[256]; | |
11249 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
11250 | { | |
11251 | tree labelname; | |
11252 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
11253 | ||
11254 | if (no_previous_def (funname)) | |
11255 | { | |
11256 | int line_number; | |
11257 | rtx label_rtx = gen_label_rtx (); | |
11258 | char *label_buf, temp_buf[256]; | |
11259 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
11260 | CODE_LABEL_NUMBER (label_rtx)); | |
11261 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
11262 | labelname = get_identifier (label_buf); | |
11263 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
11264 | if (insn) | |
11265 | line_number = NOTE_LINE_NUMBER (insn); | |
11266 | add_compiler_stub (labelname, funname, line_number); | |
11267 | } | |
11268 | else | |
11269 | labelname = get_prev_label (funname); | |
11270 | ||
11271 | sprintf (buf, "jbsr %%z%d,%.246s", | |
11272 | operand_number, IDENTIFIER_POINTER (labelname)); | |
11273 | return buf; | |
11274 | } | |
11275 | else | |
11276 | { | |
11277 | sprintf (buf, "bl %%z%d", operand_number); | |
11278 | return buf; | |
11279 | } | |
11280 | } | |
11281 | ||
11282 | #endif /* RS6000_LONG_BRANCH */ | |
11283 | ||
11284 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
11285 | do { \ | |
83182544 | 11286 | const char *const symbol_ = (SYMBOL); \ |
ee890fe2 SS |
11287 | char *buffer_ = (BUF); \ |
11288 | if (symbol_[0] == '"') \ | |
11289 | { \ | |
11290 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
11291 | } \ | |
11292 | else if (name_needs_quotes(symbol_)) \ | |
11293 | { \ | |
11294 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
11295 | } \ | |
11296 | else \ | |
11297 | { \ | |
11298 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
11299 | } \ | |
11300 | } while (0) | |
11301 | ||
11302 | ||
11303 | /* Generate PIC and indirect symbol stubs. */ | |
11304 | ||
11305 | void | |
11306 | machopic_output_stub (file, symb, stub) | |
11307 | FILE *file; | |
11308 | const char *symb, *stub; | |
11309 | { | |
11310 | unsigned int length; | |
a4f6c312 SS |
11311 | char *symbol_name, *lazy_ptr_name; |
11312 | char *local_label_0; | |
ee890fe2 SS |
11313 | static int label = 0; |
11314 | ||
df56a27f SS |
11315 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
11316 | STRIP_NAME_ENCODING (symb, symb); | |
11317 | ||
ee890fe2 SS |
11318 | label += 1; |
11319 | ||
ee890fe2 SS |
11320 | length = strlen (symb); |
11321 | symbol_name = alloca (length + 32); | |
11322 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
11323 | ||
11324 | lazy_ptr_name = alloca (length + 32); | |
11325 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
11326 | ||
11327 | local_label_0 = alloca (length + 32); | |
11328 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
11329 | ||
ee890fe2 SS |
11330 | if (flag_pic == 2) |
11331 | machopic_picsymbol_stub_section (); | |
11332 | else | |
11333 | machopic_symbol_stub_section (); | |
11334 | ||
11335 | fprintf (file, "%s:\n", stub); | |
11336 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
11337 | ||
11338 | if (flag_pic == 2) | |
11339 | { | |
11340 | fprintf (file, "\tmflr r0\n"); | |
11341 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
11342 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
11343 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
11344 | lazy_ptr_name, local_label_0); | |
11345 | fprintf (file, "\tmtlr r0\n"); | |
11346 | fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n", | |
11347 | lazy_ptr_name, local_label_0); | |
11348 | fprintf (file, "\tmtctr r12\n"); | |
11349 | fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n", | |
11350 | lazy_ptr_name, local_label_0); | |
11351 | fprintf (file, "\tbctr\n"); | |
11352 | } | |
11353 | else | |
11354 | fprintf (file, "non-pure not supported\n"); | |
11355 | ||
11356 | machopic_lazy_symbol_ptr_section (); | |
11357 | fprintf (file, "%s:\n", lazy_ptr_name); | |
11358 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
11359 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
11360 | } | |
11361 | ||
11362 | /* Legitimize PIC addresses. If the address is already | |
11363 | position-independent, we return ORIG. Newly generated | |
11364 | position-independent addresses go into a reg. This is REG if non | |
11365 | zero, otherwise we allocate register(s) as necessary. */ | |
11366 | ||
c859cda6 | 11367 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
11368 | |
11369 | rtx | |
11370 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
11371 | rtx orig; | |
11372 | enum machine_mode mode; | |
11373 | rtx reg; | |
11374 | { | |
11375 | rtx base, offset; | |
11376 | ||
11377 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
11378 | reg = gen_reg_rtx (Pmode); | |
11379 | ||
11380 | if (GET_CODE (orig) == CONST) | |
11381 | { | |
11382 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
11383 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
11384 | return orig; | |
11385 | ||
11386 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
11387 | { | |
a4f6c312 SS |
11388 | base = |
11389 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
11390 | Pmode, reg); | |
11391 | offset = | |
11392 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
11393 | Pmode, reg); | |
ee890fe2 SS |
11394 | } |
11395 | else | |
11396 | abort (); | |
11397 | ||
11398 | if (GET_CODE (offset) == CONST_INT) | |
11399 | { | |
11400 | if (SMALL_INT (offset)) | |
ed8908e7 | 11401 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
11402 | else if (! reload_in_progress && ! reload_completed) |
11403 | offset = force_reg (Pmode, offset); | |
11404 | else | |
c859cda6 DJ |
11405 | { |
11406 | rtx mem = force_const_mem (Pmode, orig); | |
11407 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
11408 | } | |
ee890fe2 SS |
11409 | } |
11410 | return gen_rtx (PLUS, Pmode, base, offset); | |
11411 | } | |
11412 | ||
11413 | /* Fall back on generic machopic code. */ | |
11414 | return machopic_legitimize_pic_address (orig, mode, reg); | |
11415 | } | |
11416 | ||
11417 | /* This is just a placeholder to make linking work without having to | |
11418 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
11419 | ever needed for Darwin (not too likely!) this would have to get a | |
11420 | real definition. */ | |
11421 | ||
11422 | void | |
11423 | toc_section () | |
11424 | { | |
11425 | } | |
11426 | ||
11427 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
11428 | |
11429 | #if TARGET_ELF | |
11430 | static unsigned int | |
11431 | rs6000_elf_section_type_flags (decl, name, reloc) | |
11432 | tree decl; | |
11433 | const char *name; | |
11434 | int reloc; | |
11435 | { | |
11436 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
11437 | ||
270fc29b RH |
11438 | if (TARGET_RELOCATABLE) |
11439 | flags |= SECTION_WRITE; | |
7c262518 | 11440 | |
d0101753 | 11441 | return flags; |
7c262518 | 11442 | } |
d9f6800d RH |
11443 | |
11444 | /* Record an element in the table of global constructors. SYMBOL is | |
11445 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
11446 | between 0 and MAX_INIT_PRIORITY. | |
11447 | ||
11448 | This differs from default_named_section_asm_out_constructor in | |
11449 | that we have special handling for -mrelocatable. */ | |
11450 | ||
11451 | static void | |
11452 | rs6000_elf_asm_out_constructor (symbol, priority) | |
11453 | rtx symbol; | |
11454 | int priority; | |
11455 | { | |
11456 | const char *section = ".ctors"; | |
11457 | char buf[16]; | |
11458 | ||
11459 | if (priority != DEFAULT_INIT_PRIORITY) | |
11460 | { | |
11461 | sprintf (buf, ".ctors.%.5u", | |
11462 | /* Invert the numbering so the linker puts us in the proper | |
11463 | order; constructors are run from right to left, and the | |
11464 | linker sorts in increasing order. */ | |
11465 | MAX_INIT_PRIORITY - priority); | |
11466 | section = buf; | |
11467 | } | |
11468 | ||
715bdd29 RH |
11469 | named_section_flags (section, SECTION_WRITE); |
11470 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
11471 | |
11472 | if (TARGET_RELOCATABLE) | |
11473 | { | |
11474 | fputs ("\t.long (", asm_out_file); | |
11475 | output_addr_const (asm_out_file, symbol); | |
11476 | fputs (")@fixup\n", asm_out_file); | |
11477 | } | |
11478 | else | |
c8af3574 | 11479 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
11480 | } |
11481 | ||
11482 | static void | |
11483 | rs6000_elf_asm_out_destructor (symbol, priority) | |
11484 | rtx symbol; | |
11485 | int priority; | |
11486 | { | |
11487 | const char *section = ".dtors"; | |
11488 | char buf[16]; | |
11489 | ||
11490 | if (priority != DEFAULT_INIT_PRIORITY) | |
11491 | { | |
11492 | sprintf (buf, ".dtors.%.5u", | |
11493 | /* Invert the numbering so the linker puts us in the proper | |
11494 | order; constructors are run from right to left, and the | |
11495 | linker sorts in increasing order. */ | |
11496 | MAX_INIT_PRIORITY - priority); | |
11497 | section = buf; | |
11498 | } | |
11499 | ||
715bdd29 RH |
11500 | named_section_flags (section, SECTION_WRITE); |
11501 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
11502 | |
11503 | if (TARGET_RELOCATABLE) | |
11504 | { | |
11505 | fputs ("\t.long (", asm_out_file); | |
11506 | output_addr_const (asm_out_file, symbol); | |
11507 | fputs (")@fixup\n", asm_out_file); | |
11508 | } | |
11509 | else | |
c8af3574 | 11510 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 11511 | } |
7c262518 RH |
11512 | #endif |
11513 | ||
11514 | #ifdef OBJECT_FORMAT_COFF | |
11515 | static void | |
715bdd29 | 11516 | xcoff_asm_named_section (name, flags) |
7c262518 RH |
11517 | const char *name; |
11518 | unsigned int flags ATTRIBUTE_UNUSED; | |
7c262518 RH |
11519 | { |
11520 | fprintf (asm_out_file, "\t.csect %s\n", name); | |
11521 | } | |
11522 | #endif |