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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
95385cbb | 3 | 2000, 2001, 2002 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
9878760c RK |
31 | #include "insn-attr.h" |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
9878760c | 34 | #include "obstack.h" |
9b30bae2 | 35 | #include "tree.h" |
dfafc897 | 36 | #include "expr.h" |
2fc1c679 | 37 | #include "optabs.h" |
2a430ec1 | 38 | #include "except.h" |
a7df97e6 | 39 | #include "function.h" |
296b8152 | 40 | #include "output.h" |
d5fa86ba | 41 | #include "basic-block.h" |
d0101753 | 42 | #include "integrate.h" |
296b8152 | 43 | #include "toplev.h" |
c8023011 | 44 | #include "ggc.h" |
9ebbca7d GK |
45 | #include "hashtab.h" |
46 | #include "tm_p.h" | |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
3ac88239 | 49 | #include "langhooks.h" |
24ea750e | 50 | #include "reload.h" |
9b30bae2 | 51 | |
7509c759 MM |
52 | #ifndef TARGET_NO_PROTOTYPE |
53 | #define TARGET_NO_PROTOTYPE 0 | |
54 | #endif | |
55 | ||
9878760c RK |
56 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
57 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
58 | ||
5248c961 RK |
59 | /* Target cpu type */ |
60 | ||
61 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
62 | struct rs6000_cpu_select rs6000_select[3] = |
63 | { | |
815cdc52 MM |
64 | /* switch name, tune arch */ |
65 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
66 | { (const char *)0, "-mcpu=", 1, 1 }, | |
67 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 68 | }; |
5248c961 | 69 | |
6fa3f289 ZW |
70 | /* Size of long double */ |
71 | const char *rs6000_long_double_size_string; | |
72 | int rs6000_long_double_type_size; | |
73 | ||
74 | /* Whether -mabi=altivec has appeared */ | |
75 | int rs6000_altivec_abi; | |
76 | ||
c764f757 RK |
77 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
78 | static int common_mode_defined; | |
c81bebd7 | 79 | |
9878760c RK |
80 | /* Save information from a "cmpxx" operation until the branch or scc is |
81 | emitted. */ | |
9878760c RK |
82 | rtx rs6000_compare_op0, rs6000_compare_op1; |
83 | int rs6000_compare_fp_p; | |
874a0744 | 84 | |
874a0744 MM |
85 | /* Label number of label created for -mrelocatable, to call to so we can |
86 | get the address of the GOT section */ | |
87 | int rs6000_pic_labelno; | |
c81bebd7 | 88 | |
b91da81f | 89 | #ifdef USING_ELFOS_H |
c81bebd7 | 90 | /* Which abi to adhere to */ |
815cdc52 | 91 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
92 | |
93 | /* Semantics of the small data area */ | |
94 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
95 | ||
96 | /* Which small data model to use */ | |
815cdc52 | 97 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
98 | |
99 | /* Counter for labels which are to be placed in .fixup. */ | |
100 | int fixuplabelno = 0; | |
874a0744 | 101 | #endif |
4697a36c | 102 | |
b6c9286a MM |
103 | /* ABI enumeration available for subtarget to use. */ |
104 | enum rs6000_abi rs6000_current_abi; | |
105 | ||
0ac081f6 AH |
106 | /* ABI string from -mabi= option. */ |
107 | const char *rs6000_abi_string; | |
108 | ||
38c1f2d7 | 109 | /* Debug flags */ |
815cdc52 | 110 | const char *rs6000_debug_name; |
38c1f2d7 MM |
111 | int rs6000_debug_stack; /* debug stack applications */ |
112 | int rs6000_debug_arg; /* debug argument handling */ | |
113 | ||
114 | /* Flag to say the TOC is initialized */ | |
115 | int toc_initialized; | |
9ebbca7d | 116 | char toc_label_name[10]; |
38c1f2d7 | 117 | |
9ebbca7d GK |
118 | /* Alias set for saves and restores from the rs6000 stack. */ |
119 | static int rs6000_sr_alias_set; | |
c8023011 | 120 | |
9ebbca7d GK |
121 | static void rs6000_add_gc_roots PARAMS ((void)); |
122 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
123 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
124 | static void validate_condition_mode |
125 | PARAMS ((enum rtx_code, enum machine_mode)); | |
126 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 127 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
128 | static void rs6000_emit_stack_tie PARAMS ((void)); |
129 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
130 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
131 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
132 | static unsigned toc_hash_function PARAMS ((const void *)); | |
133 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 134 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
135 | static void toc_hash_mark_table PARAMS ((void *)); |
136 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
6fee9e99 NC |
137 | static void rs6000_free_machine_status PARAMS ((struct function *)); |
138 | static void rs6000_init_machine_status PARAMS ((struct function *)); | |
301d03af | 139 | static bool rs6000_assemble_integer PARAMS ((rtx, unsigned int, int)); |
71f123ca | 140 | static int rs6000_ra_ever_killed PARAMS ((void)); |
91d231cb JM |
141 | static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *)); |
142 | const struct attribute_spec rs6000_attribute_table[]; | |
08c148a8 NB |
143 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
144 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
2bfcf297 DB |
145 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
146 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
7c262518 RH |
147 | #if TARGET_ELF |
148 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
149 | int)); | |
d9f6800d RH |
150 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
151 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
7c262518 RH |
152 | #endif |
153 | #ifdef OBJECT_FORMAT_COFF | |
715bdd29 | 154 | static void xcoff_asm_named_section PARAMS ((const char *, unsigned int)); |
7c262518 | 155 | #endif |
c237e94a ZW |
156 | static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
157 | static int rs6000_adjust_priority PARAMS ((rtx, int)); | |
158 | static int rs6000_issue_rate PARAMS ((void)); | |
159 | ||
6fa3f289 | 160 | static void rs6000_init_builtins PARAMS ((void)); |
0ac081f6 AH |
161 | static void altivec_init_builtins PARAMS ((void)); |
162 | static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int)); | |
00b960c7 | 163 | static rtx altivec_expand_builtin PARAMS ((tree, rtx)); |
2212663f | 164 | static rtx altivec_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx)); |
0ac081f6 | 165 | static rtx altivec_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); |
100c4561 | 166 | static rtx altivec_expand_abs_builtin PARAMS ((enum insn_code, tree, rtx)); |
ae4b4a02 | 167 | static rtx altivec_expand_predicate_builtin PARAMS ((enum insn_code, const char *, tree, rtx)); |
2212663f | 168 | static rtx altivec_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx)); |
6525c0e7 | 169 | static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree)); |
0ac081f6 | 170 | static void rs6000_parse_abi_options PARAMS ((void)); |
00b960c7 AH |
171 | static int first_altivec_reg_to_save PARAMS ((void)); |
172 | static unsigned int compute_vrsave_mask PARAMS ((void)); | |
173 | static void is_altivec_return_reg PARAMS ((rtx, void *)); | |
174 | int vrsave_operation PARAMS ((rtx, enum machine_mode)); | |
9aa86737 AH |
175 | static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *, int)); |
176 | static void altivec_frame_fixup PARAMS ((rtx, rtx, HOST_WIDE_INT)); | |
c81bebd7 MM |
177 | \f |
178 | /* Default register names. */ | |
179 | char rs6000_reg_names[][8] = | |
180 | { | |
802a0058 MM |
181 | "0", "1", "2", "3", "4", "5", "6", "7", |
182 | "8", "9", "10", "11", "12", "13", "14", "15", | |
183 | "16", "17", "18", "19", "20", "21", "22", "23", | |
184 | "24", "25", "26", "27", "28", "29", "30", "31", | |
185 | "0", "1", "2", "3", "4", "5", "6", "7", | |
186 | "8", "9", "10", "11", "12", "13", "14", "15", | |
187 | "16", "17", "18", "19", "20", "21", "22", "23", | |
188 | "24", "25", "26", "27", "28", "29", "30", "31", | |
189 | "mq", "lr", "ctr","ap", | |
190 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
191 | "xer", |
192 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
193 | "0", "1", "2", "3", "4", "5", "6", "7", |
194 | "8", "9", "10", "11", "12", "13", "14", "15", | |
195 | "16", "17", "18", "19", "20", "21", "22", "23", | |
196 | "24", "25", "26", "27", "28", "29", "30", "31", | |
0ac081f6 | 197 | "vrsave" |
c81bebd7 MM |
198 | }; |
199 | ||
200 | #ifdef TARGET_REGNAMES | |
8b60264b | 201 | static const char alt_reg_names[][8] = |
c81bebd7 | 202 | { |
802a0058 MM |
203 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
204 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
205 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
206 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
207 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
208 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
209 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
210 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
211 | "mq", "lr", "ctr", "ap", | |
212 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 AH |
213 | "xer", |
214 | /* AltiVec registers. */ | |
215 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", | |
216 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", | |
217 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
218 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
219 | "%vrsave" | |
c81bebd7 MM |
220 | }; |
221 | #endif | |
9878760c | 222 | \f |
daf11973 MM |
223 | #ifndef MASK_STRICT_ALIGN |
224 | #define MASK_STRICT_ALIGN 0 | |
225 | #endif | |
672a6f42 NB |
226 | \f |
227 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
228 | #undef TARGET_ATTRIBUTE_TABLE |
229 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
daf11973 | 230 | |
301d03af RS |
231 | #undef TARGET_ASM_ALIGNED_DI_OP |
232 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
233 | ||
234 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
235 | for non-ELF systems. */ | |
236 | #ifndef OBJECT_FORMAT_ELF | |
237 | #ifdef OBJECT_FORMAT_COFF | |
ae6c1efd | 238 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
239 | 64-bit targets. */ |
240 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
241 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
242 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
243 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
244 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
245 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
246 | #else | |
247 | /* For Darwin. */ | |
248 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
249 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
250 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
251 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
252 | #endif | |
253 | #endif | |
254 | ||
255 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
256 | in 64-bit code. */ | |
257 | #undef TARGET_ASM_INTEGER | |
258 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
259 | ||
08c148a8 NB |
260 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
261 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
262 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
263 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
264 | ||
7c262518 RH |
265 | #if TARGET_ELF |
266 | #undef TARGET_SECTION_TYPE_FLAGS | |
267 | #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags | |
268 | #endif | |
269 | ||
c237e94a ZW |
270 | #undef TARGET_SCHED_ISSUE_RATE |
271 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
272 | #undef TARGET_SCHED_ADJUST_COST | |
273 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
274 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
275 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
276 | ||
0ac081f6 AH |
277 | #undef TARGET_INIT_BUILTINS |
278 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
279 | ||
280 | #undef TARGET_EXPAND_BUILTIN | |
281 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
282 | ||
00b960c7 AH |
283 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ |
284 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
285 | ||
f6897b10 | 286 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 287 | \f |
5248c961 RK |
288 | /* Override command line options. Mostly we process the processor |
289 | type and sometimes adjust other TARGET_ options. */ | |
290 | ||
291 | void | |
8e3f41e7 | 292 | rs6000_override_options (default_cpu) |
d330fd93 | 293 | const char *default_cpu; |
5248c961 | 294 | { |
c4d38ccb | 295 | size_t i, j; |
8e3f41e7 | 296 | struct rs6000_cpu_select *ptr; |
5248c961 | 297 | |
85638c0d RK |
298 | /* Simplify the entries below by making a mask for any POWER |
299 | variant and any PowerPC variant. */ | |
300 | ||
938937d8 | 301 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
302 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
303 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
304 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 305 | |
5248c961 RK |
306 | static struct ptt |
307 | { | |
8b60264b KG |
308 | const char *const name; /* Canonical processor name. */ |
309 | const enum processor_type processor; /* Processor type enum value. */ | |
310 | const int target_enable; /* Target flags to enable. */ | |
311 | const int target_disable; /* Target flags to disable. */ | |
312 | } const processor_target_table[] | |
cf27b467 MM |
313 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
314 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 315 | {"power", PROCESSOR_POWER, |
938937d8 | 316 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 317 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
318 | {"power2", PROCESSOR_POWER, |
319 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
320 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
321 | {"power3", PROCESSOR_PPC630, |
322 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
323 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
324 | {"powerpc", PROCESSOR_POWERPC, |
325 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 326 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
327 | {"powerpc64", PROCESSOR_POWERPC64, |
328 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
329 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 330 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 331 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
332 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
333 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 334 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
335 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
336 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 337 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
338 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
339 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 340 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
341 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
342 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 343 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 344 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
345 | {"rs64a", PROCESSOR_RS64A, |
346 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
347 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
348 | {"401", PROCESSOR_PPC403, |
349 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
350 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 351 | {"403", PROCESSOR_PPC403, |
daf11973 | 352 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 353 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
d7a5e253 DE |
354 | {"405", PROCESSOR_PPC405, |
355 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
356 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
357 | {"505", PROCESSOR_MPCCORE, |
358 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
359 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 360 | {"601", PROCESSOR_PPC601, |
938937d8 | 361 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 362 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 363 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
364 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
365 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 366 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
367 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
368 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
369 | {"603e", PROCESSOR_PPC603, |
370 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
371 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 372 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
373 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
374 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 375 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
376 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
377 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 378 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
379 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
380 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 381 | {"620", PROCESSOR_PPC620, |
68c49ffa | 382 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 383 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
384 | {"630", PROCESSOR_PPC630, |
385 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
386 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
387 | {"740", PROCESSOR_PPC750, |
388 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
389 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
390 | {"750", PROCESSOR_PPC750, | |
391 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
392 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a4f6c312 SS |
393 | {"7400", PROCESSOR_PPC7400, |
394 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
395 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
396 | {"7450", PROCESSOR_PPC7450, | |
397 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
398 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
399 | {"801", PROCESSOR_MPCCORE, |
400 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
401 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
402 | {"821", PROCESSOR_MPCCORE, |
403 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
404 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
405 | {"823", PROCESSOR_MPCCORE, |
406 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
407 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
408 | {"860", PROCESSOR_MPCCORE, |
409 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
410 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 411 | |
c4d38ccb | 412 | size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); |
5248c961 | 413 | |
a4f6c312 SS |
414 | /* Save current -mmultiple/-mno-multiple status. */ |
415 | int multiple = TARGET_MULTIPLE; | |
416 | /* Save current -mstring/-mno-string status. */ | |
417 | int string = TARGET_STRING; | |
8a61d227 | 418 | |
a4f6c312 | 419 | /* Identify the processor type. */ |
8e3f41e7 | 420 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 421 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 422 | |
b6a1cbae | 423 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 424 | { |
8e3f41e7 MM |
425 | ptr = &rs6000_select[i]; |
426 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 427 | { |
8e3f41e7 MM |
428 | for (j = 0; j < ptt_size; j++) |
429 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
430 | { | |
431 | if (ptr->set_tune_p) | |
432 | rs6000_cpu = processor_target_table[j].processor; | |
433 | ||
434 | if (ptr->set_arch_p) | |
435 | { | |
436 | target_flags |= processor_target_table[j].target_enable; | |
437 | target_flags &= ~processor_target_table[j].target_disable; | |
438 | } | |
439 | break; | |
440 | } | |
441 | ||
4406229e | 442 | if (j == ptt_size) |
8e3f41e7 | 443 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
444 | } |
445 | } | |
8a61d227 | 446 | |
a4f6c312 SS |
447 | /* If we are optimizing big endian systems for space, use the store |
448 | multiple instructions. */ | |
ef792183 MM |
449 | if (BYTES_BIG_ENDIAN && optimize_size) |
450 | target_flags |= MASK_MULTIPLE; | |
451 | ||
8a61d227 MM |
452 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
453 | override with the processor default */ | |
454 | if (TARGET_MULTIPLE_SET) | |
455 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 456 | |
a4f6c312 SS |
457 | /* If -mstring or -mno-string was explicitly used, don't override |
458 | with the processor default. */ | |
938937d8 | 459 | if (TARGET_STRING_SET) |
1f5515bf | 460 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 461 | |
a4f6c312 SS |
462 | /* Don't allow -mmultiple or -mstring on little endian systems |
463 | unless the cpu is a 750, because the hardware doesn't support the | |
464 | instructions used in little endian mode, and causes an alignment | |
465 | trap. The 750 does not cause an alignment trap (except when the | |
466 | target is unaligned). */ | |
bef84347 | 467 | |
bfc79d3b | 468 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
469 | { |
470 | if (TARGET_MULTIPLE) | |
471 | { | |
472 | target_flags &= ~MASK_MULTIPLE; | |
473 | if (TARGET_MULTIPLE_SET) | |
474 | warning ("-mmultiple is not supported on little endian systems"); | |
475 | } | |
476 | ||
477 | if (TARGET_STRING) | |
478 | { | |
479 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
480 | if (TARGET_STRING_SET) |
481 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
482 | } |
483 | } | |
3933e0e1 | 484 | |
2bfcf297 | 485 | if (flag_pic && DEFAULT_ABI == ABI_AIX) |
a260abc9 | 486 | { |
2bfcf297 | 487 | warning ("-f%s ignored (all code is position independent)", |
a260abc9 DE |
488 | (flag_pic > 1) ? "PIC" : "pic"); |
489 | flag_pic = 0; | |
490 | } | |
491 | ||
2bfcf297 | 492 | #ifdef XCOFF_DEBUGGING_INFO |
9861b0c9 | 493 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
2bfcf297 | 494 | && DEFAULT_ABI == ABI_AIX) |
9861b0c9 DE |
495 | { |
496 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
497 | flag_function_sections = 0; | |
498 | } | |
499 | ||
500 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
501 | { | |
502 | warning ("-fdata-sections not supported on AIX"); | |
503 | flag_data_sections = 0; | |
504 | } | |
2bfcf297 | 505 | #endif |
9861b0c9 | 506 | |
38c1f2d7 MM |
507 | /* Set debug flags */ |
508 | if (rs6000_debug_name) | |
509 | { | |
bfc79d3b | 510 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 511 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 512 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 513 | rs6000_debug_stack = 1; |
bfc79d3b | 514 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
515 | rs6000_debug_arg = 1; |
516 | else | |
c725bd79 | 517 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
518 | } |
519 | ||
6fa3f289 ZW |
520 | /* Set size of long double */ |
521 | rs6000_long_double_type_size = 64; | |
522 | if (rs6000_long_double_size_string) | |
523 | { | |
524 | char *tail; | |
525 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
526 | if (*tail != '\0' || (size != 64 && size != 128)) | |
527 | error ("Unknown switch -mlong-double-%s", | |
528 | rs6000_long_double_size_string); | |
529 | else | |
530 | rs6000_long_double_type_size = size; | |
531 | } | |
532 | ||
0ac081f6 AH |
533 | /* Handle -mabi= options. */ |
534 | rs6000_parse_abi_options (); | |
535 | ||
c81bebd7 | 536 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
537 | /* If the user desires alternate register names, copy in the |
538 | alternate names now. */ | |
c81bebd7 | 539 | if (TARGET_REGNAMES) |
4e135bdd | 540 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
541 | #endif |
542 | ||
3933e0e1 MM |
543 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
544 | SUBTARGET_OVERRIDE_OPTIONS; | |
545 | #endif | |
10baca6b AH |
546 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS |
547 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
548 | #endif | |
c8023011 | 549 | |
6fa3f289 ZW |
550 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
551 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
552 | used, don't override with the ABI default. */ | |
553 | if (!(target_flags & MASK_AIX_STRUCT_RET_SET)) | |
554 | { | |
555 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
556 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
557 | else | |
558 | target_flags |= MASK_AIX_STRUCT_RET; | |
559 | } | |
560 | ||
c8023011 MM |
561 | /* Register global variables with the garbage collector. */ |
562 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
563 | |
564 | /* Allocate an alias set for register saves & restores from stack. */ | |
565 | rs6000_sr_alias_set = new_alias_set (); | |
566 | ||
567 | if (TARGET_TOC) | |
568 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca | 569 | |
301d03af RS |
570 | /* We can only guarantee the availability of DI pseudo-ops when |
571 | assembling for 64-bit targets. */ | |
ae6c1efd | 572 | if (!TARGET_64BIT) |
301d03af RS |
573 | { |
574 | targetm.asm_out.aligned_op.di = NULL; | |
575 | targetm.asm_out.unaligned_op.di = NULL; | |
576 | } | |
577 | ||
71f123ca FS |
578 | /* Arrange to save and restore machine status around nested functions. */ |
579 | init_machine_status = rs6000_init_machine_status; | |
71f123ca | 580 | free_machine_status = rs6000_free_machine_status; |
5248c961 | 581 | } |
5accd822 | 582 | |
0ac081f6 | 583 | /* Handle -mabi= options. */ |
00b960c7 AH |
584 | static void |
585 | rs6000_parse_abi_options () | |
0ac081f6 AH |
586 | { |
587 | if (rs6000_abi_string == 0) | |
588 | return; | |
589 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
6fa3f289 | 590 | rs6000_altivec_abi = 1; |
0ac081f6 | 591 | else |
c725bd79 | 592 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
593 | } |
594 | ||
5accd822 DE |
595 | void |
596 | optimization_options (level, size) | |
e2c953b6 | 597 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
598 | int size ATTRIBUTE_UNUSED; |
599 | { | |
5accd822 | 600 | } |
3cfa4909 MM |
601 | \f |
602 | /* Do anything needed at the start of the asm file. */ | |
603 | ||
604 | void | |
605 | rs6000_file_start (file, default_cpu) | |
606 | FILE *file; | |
d330fd93 | 607 | const char *default_cpu; |
3cfa4909 | 608 | { |
c4d38ccb | 609 | size_t i; |
3cfa4909 | 610 | char buffer[80]; |
d330fd93 | 611 | const char *start = buffer; |
3cfa4909 MM |
612 | struct rs6000_cpu_select *ptr; |
613 | ||
614 | if (flag_verbose_asm) | |
615 | { | |
616 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
617 | rs6000_select[0].string = default_cpu; | |
618 | ||
b6a1cbae | 619 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
620 | { |
621 | ptr = &rs6000_select[i]; | |
622 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
623 | { | |
624 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
625 | start = ""; | |
626 | } | |
627 | } | |
628 | ||
b91da81f | 629 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
630 | switch (rs6000_sdata) |
631 | { | |
632 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
633 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
634 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
635 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
636 | } | |
637 | ||
638 | if (rs6000_sdata && g_switch_value) | |
639 | { | |
640 | fprintf (file, "%s -G %d", start, g_switch_value); | |
641 | start = ""; | |
642 | } | |
643 | #endif | |
644 | ||
645 | if (*start == '\0') | |
949ea356 | 646 | putc ('\n', file); |
3cfa4909 MM |
647 | } |
648 | } | |
649 | ||
24d304eb RK |
650 | \f |
651 | /* Create a CONST_DOUBLE from a string. */ | |
652 | ||
653 | struct rtx_def * | |
654 | rs6000_float_const (string, mode) | |
d330fd93 | 655 | const char *string; |
24d304eb RK |
656 | enum machine_mode mode; |
657 | { | |
ca5adc63 GK |
658 | REAL_VALUE_TYPE value; |
659 | value = REAL_VALUE_ATOF (string, mode); | |
24d304eb RK |
660 | return immed_real_const_1 (value, mode); |
661 | } | |
5248c961 | 662 | \f |
9878760c RK |
663 | /* Return non-zero if this function is known to have a null epilogue. */ |
664 | ||
665 | int | |
666 | direct_return () | |
667 | { | |
4697a36c MM |
668 | if (reload_completed) |
669 | { | |
670 | rs6000_stack_t *info = rs6000_stack_info (); | |
671 | ||
672 | if (info->first_gp_reg_save == 32 | |
673 | && info->first_fp_reg_save == 64 | |
00b960c7 | 674 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
675 | && ! info->lr_save_p |
676 | && ! info->cr_save_p | |
00b960c7 | 677 | && info->vrsave_mask == 0 |
c81fc13e | 678 | && ! info->push_p) |
4697a36c MM |
679 | return 1; |
680 | } | |
681 | ||
682 | return 0; | |
9878760c RK |
683 | } |
684 | ||
685 | /* Returns 1 always. */ | |
686 | ||
687 | int | |
688 | any_operand (op, mode) | |
592696dd | 689 | rtx op ATTRIBUTE_UNUSED; |
296b8152 | 690 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
691 | { |
692 | return 1; | |
693 | } | |
694 | ||
a4f6c312 | 695 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 696 | int |
a4f6c312 | 697 | count_register_operand (op, mode) |
592696dd | 698 | rtx op; |
296b8152 | 699 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
700 | { |
701 | if (GET_CODE (op) != REG) | |
702 | return 0; | |
703 | ||
704 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
705 | return 1; | |
706 | ||
707 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
708 | return 1; | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
0ec4e2a8 AH |
713 | /* Returns 1 if op is an altivec register. */ |
714 | int | |
715 | altivec_register_operand (op, mode) | |
716 | rtx op; | |
717 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
718 | { | |
719 | ||
720 | return (register_operand (op, mode) | |
721 | && (GET_CODE (op) != REG | |
722 | || REGNO (op) > FIRST_PSEUDO_REGISTER | |
723 | || ALTIVEC_REGNO_P (REGNO (op)))); | |
724 | } | |
725 | ||
38c1f2d7 | 726 | int |
a4f6c312 | 727 | xer_operand (op, mode) |
592696dd | 728 | rtx op; |
296b8152 | 729 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
730 | { |
731 | if (GET_CODE (op) != REG) | |
732 | return 0; | |
733 | ||
9ebbca7d | 734 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
735 | return 1; |
736 | ||
802a0058 MM |
737 | return 0; |
738 | } | |
739 | ||
c859cda6 | 740 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 741 | by such constants completes more quickly. */ |
c859cda6 DJ |
742 | |
743 | int | |
744 | s8bit_cint_operand (op, mode) | |
745 | rtx op; | |
746 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
747 | { | |
748 | return ( GET_CODE (op) == CONST_INT | |
749 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); | |
750 | } | |
751 | ||
9878760c RK |
752 | /* Return 1 if OP is a constant that can fit in a D field. */ |
753 | ||
754 | int | |
755 | short_cint_operand (op, mode) | |
592696dd | 756 | rtx op; |
296b8152 | 757 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 758 | { |
5f59ecb7 DE |
759 | return (GET_CODE (op) == CONST_INT |
760 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
761 | } |
762 | ||
5519a4f9 | 763 | /* Similar for an unsigned D field. */ |
9878760c RK |
764 | |
765 | int | |
766 | u_short_cint_operand (op, mode) | |
592696dd | 767 | rtx op; |
296b8152 | 768 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 769 | { |
19684119 | 770 | return (GET_CODE (op) == CONST_INT |
5f59ecb7 | 771 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')); |
9878760c RK |
772 | } |
773 | ||
dcfedcd0 RK |
774 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
775 | ||
776 | int | |
777 | non_short_cint_operand (op, mode) | |
592696dd | 778 | rtx op; |
296b8152 | 779 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
780 | { |
781 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 782 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
783 | } |
784 | ||
2bfcf297 DB |
785 | /* Returns 1 if OP is a CONST_INT that is a positive value |
786 | and an exact power of 2. */ | |
787 | ||
788 | int | |
789 | exact_log2_cint_operand (op, mode) | |
592696dd | 790 | rtx op; |
2bfcf297 DB |
791 | enum machine_mode mode ATTRIBUTE_UNUSED; |
792 | { | |
793 | return (GET_CODE (op) == CONST_INT | |
794 | && INTVAL (op) > 0 | |
795 | && exact_log2 (INTVAL (op)) >= 0); | |
796 | } | |
797 | ||
9878760c RK |
798 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
799 | ctr, or lr). */ | |
800 | ||
801 | int | |
cd2b37d9 | 802 | gpc_reg_operand (op, mode) |
592696dd | 803 | rtx op; |
9878760c RK |
804 | enum machine_mode mode; |
805 | { | |
806 | return (register_operand (op, mode) | |
802a0058 | 807 | && (GET_CODE (op) != REG |
9ebbca7d GK |
808 | || (REGNO (op) >= ARG_POINTER_REGNUM |
809 | && !XER_REGNO_P (REGNO (op))) | |
810 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
811 | } |
812 | ||
813 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
814 | CR field. */ | |
815 | ||
816 | int | |
817 | cc_reg_operand (op, mode) | |
592696dd | 818 | rtx op; |
9878760c RK |
819 | enum machine_mode mode; |
820 | { | |
821 | return (register_operand (op, mode) | |
822 | && (GET_CODE (op) != REG | |
823 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
824 | || CR_REGNO_P (REGNO (op)))); | |
825 | } | |
826 | ||
815cdc52 MM |
827 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
828 | CR field that isn't CR0. */ | |
829 | ||
830 | int | |
831 | cc_reg_not_cr0_operand (op, mode) | |
592696dd | 832 | rtx op; |
815cdc52 MM |
833 | enum machine_mode mode; |
834 | { | |
835 | return (register_operand (op, mode) | |
836 | && (GET_CODE (op) != REG | |
837 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
838 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
839 | } | |
840 | ||
a4f6c312 SS |
841 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
842 | a non-special register. If a register, it must be in the proper | |
843 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
844 | |
845 | int | |
846 | reg_or_short_operand (op, mode) | |
592696dd | 847 | rtx op; |
9878760c RK |
848 | enum machine_mode mode; |
849 | { | |
f5a28898 | 850 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
851 | } |
852 | ||
a4f6c312 SS |
853 | /* Similar, except check if the negation of the constant would be |
854 | valid for a D-field. */ | |
9878760c RK |
855 | |
856 | int | |
857 | reg_or_neg_short_operand (op, mode) | |
592696dd | 858 | rtx op; |
9878760c RK |
859 | enum machine_mode mode; |
860 | { | |
861 | if (GET_CODE (op) == CONST_INT) | |
862 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
863 | ||
cd2b37d9 | 864 | return gpc_reg_operand (op, mode); |
9878760c RK |
865 | } |
866 | ||
768070a0 TR |
867 | /* Returns 1 if OP is either a constant integer valid for a DS-field or |
868 | a non-special register. If a register, it must be in the proper | |
869 | mode unless MODE is VOIDmode. */ | |
870 | ||
871 | int | |
872 | reg_or_aligned_short_operand (op, mode) | |
873 | rtx op; | |
874 | enum machine_mode mode; | |
875 | { | |
876 | if (gpc_reg_operand (op, mode)) | |
877 | return 1; | |
878 | else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3)) | |
879 | return 1; | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | ||
a4f6c312 SS |
885 | /* Return 1 if the operand is either a register or an integer whose |
886 | high-order 16 bits are zero. */ | |
9878760c RK |
887 | |
888 | int | |
889 | reg_or_u_short_operand (op, mode) | |
592696dd | 890 | rtx op; |
9878760c RK |
891 | enum machine_mode mode; |
892 | { | |
e675f625 | 893 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
894 | } |
895 | ||
896 | /* Return 1 is the operand is either a non-special register or ANY | |
897 | constant integer. */ | |
898 | ||
899 | int | |
900 | reg_or_cint_operand (op, mode) | |
592696dd | 901 | rtx op; |
9878760c RK |
902 | enum machine_mode mode; |
903 | { | |
a4f6c312 | 904 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
905 | } |
906 | ||
907 | /* Return 1 is the operand is either a non-special register or ANY | |
908 | 32-bit signed constant integer. */ | |
909 | ||
910 | int | |
911 | reg_or_arith_cint_operand (op, mode) | |
592696dd | 912 | rtx op; |
f6bf7de2 DE |
913 | enum machine_mode mode; |
914 | { | |
a4f6c312 SS |
915 | return (gpc_reg_operand (op, mode) |
916 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 917 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
918 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
919 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 920 | #endif |
a4f6c312 | 921 | )); |
9878760c RK |
922 | } |
923 | ||
2bfcf297 DB |
924 | /* Return 1 is the operand is either a non-special register or a 32-bit |
925 | signed constant integer valid for 64-bit addition. */ | |
926 | ||
927 | int | |
928 | reg_or_add_cint64_operand (op, mode) | |
592696dd | 929 | rtx op; |
2bfcf297 DB |
930 | enum machine_mode mode; |
931 | { | |
a4f6c312 SS |
932 | return (gpc_reg_operand (op, mode) |
933 | || (GET_CODE (op) == CONST_INT | |
934 | && INTVAL (op) < 0x7fff8000 | |
2bfcf297 | 935 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
936 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
937 | < 0x100000000ll) | |
2bfcf297 | 938 | #endif |
a4f6c312 | 939 | )); |
2bfcf297 DB |
940 | } |
941 | ||
942 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
943 | signed constant integer valid for 64-bit subtraction. */ | |
944 | ||
945 | int | |
946 | reg_or_sub_cint64_operand (op, mode) | |
592696dd | 947 | rtx op; |
2bfcf297 DB |
948 | enum machine_mode mode; |
949 | { | |
a4f6c312 SS |
950 | return (gpc_reg_operand (op, mode) |
951 | || (GET_CODE (op) == CONST_INT | |
952 | && (- INTVAL (op)) < 0x7fff8000 | |
2bfcf297 | 953 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
954 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
955 | < 0x100000000ll) | |
2bfcf297 | 956 | #endif |
a4f6c312 | 957 | )); |
2bfcf297 DB |
958 | } |
959 | ||
9ebbca7d GK |
960 | /* Return 1 is the operand is either a non-special register or ANY |
961 | 32-bit unsigned constant integer. */ | |
962 | ||
963 | int | |
1d328b19 | 964 | reg_or_logical_cint_operand (op, mode) |
592696dd | 965 | rtx op; |
9ebbca7d GK |
966 | enum machine_mode mode; |
967 | { | |
1d328b19 GK |
968 | if (GET_CODE (op) == CONST_INT) |
969 | { | |
970 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
971 | { | |
972 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 973 | abort (); |
1d328b19 GK |
974 | |
975 | if (INTVAL (op) < 0) | |
976 | return 0; | |
977 | } | |
978 | ||
979 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 980 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
981 | } |
982 | else if (GET_CODE (op) == CONST_DOUBLE) | |
983 | { | |
984 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
985 | || mode != DImode) | |
a4f6c312 | 986 | abort (); |
1d328b19 GK |
987 | |
988 | return CONST_DOUBLE_HIGH (op) == 0; | |
989 | } | |
990 | else | |
991 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
992 | } |
993 | ||
51d3e7d6 | 994 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
995 | |
996 | int | |
997 | got_operand (op, mode) | |
592696dd | 998 | rtx op; |
296b8152 | 999 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
1000 | { |
1001 | return (GET_CODE (op) == SYMBOL_REF | |
1002 | || GET_CODE (op) == CONST | |
1003 | || GET_CODE (op) == LABEL_REF); | |
1004 | } | |
1005 | ||
38c1f2d7 MM |
1006 | /* Return 1 if the operand is a simple references that can be loaded via |
1007 | the GOT (labels involving addition aren't allowed). */ | |
1008 | ||
1009 | int | |
1010 | got_no_const_operand (op, mode) | |
592696dd | 1011 | rtx op; |
296b8152 | 1012 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
1013 | { |
1014 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
1015 | } | |
1016 | ||
4e74d8ec MM |
1017 | /* Return the number of instructions it takes to form a constant in an |
1018 | integer register. */ | |
1019 | ||
1020 | static int | |
1021 | num_insns_constant_wide (value) | |
1022 | HOST_WIDE_INT value; | |
1023 | { | |
1024 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1025 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1026 | return 1; |
1027 | ||
4e74d8ec | 1028 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1029 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1030 | return 1; |
1031 | ||
5f59ecb7 | 1032 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1033 | else if (TARGET_POWERPC64) |
4e74d8ec | 1034 | { |
0d30d435 | 1035 | HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
1036 | HOST_WIDE_INT high = value >> 32; |
1037 | ||
0d30d435 DE |
1038 | low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ |
1039 | ||
0858c623 | 1040 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
1041 | return 2; |
1042 | ||
0858c623 | 1043 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
1044 | return 2; |
1045 | ||
c81fc13e | 1046 | else if (! low) |
4e74d8ec MM |
1047 | return num_insns_constant_wide (high) + 1; |
1048 | ||
1049 | else | |
1050 | return (num_insns_constant_wide (high) | |
e396202a | 1051 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1052 | } |
1053 | #endif | |
1054 | ||
1055 | else | |
1056 | return 2; | |
1057 | } | |
1058 | ||
1059 | int | |
1060 | num_insns_constant (op, mode) | |
1061 | rtx op; | |
1062 | enum machine_mode mode; | |
1063 | { | |
4e74d8ec | 1064 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
1065 | { |
1066 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
1067 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1068 | && mask64_operand (op, mode)) | |
0d30d435 DE |
1069 | return 2; |
1070 | else | |
1071 | #endif | |
1072 | return num_insns_constant_wide (INTVAL (op)); | |
1073 | } | |
4e74d8ec | 1074 | |
6fc48950 MM |
1075 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
1076 | { | |
1077 | long l; | |
1078 | REAL_VALUE_TYPE rv; | |
1079 | ||
1080 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1081 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
1082 | return num_insns_constant_wide ((HOST_WIDE_INT)l); | |
1083 | } | |
1084 | ||
47ad8c61 | 1085 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 1086 | { |
47ad8c61 MM |
1087 | HOST_WIDE_INT low; |
1088 | HOST_WIDE_INT high; | |
1089 | long l[2]; | |
1090 | REAL_VALUE_TYPE rv; | |
1091 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 1092 | |
47ad8c61 MM |
1093 | if (mode == VOIDmode || mode == DImode) |
1094 | { | |
1095 | high = CONST_DOUBLE_HIGH (op); | |
1096 | low = CONST_DOUBLE_LOW (op); | |
1097 | } | |
1098 | else | |
1099 | { | |
1100 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1101 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1102 | high = l[endian]; | |
1103 | low = l[1 - endian]; | |
1104 | } | |
4e74d8ec | 1105 | |
47ad8c61 MM |
1106 | if (TARGET_32BIT) |
1107 | return (num_insns_constant_wide (low) | |
1108 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
1109 | |
1110 | else | |
47ad8c61 | 1111 | { |
0858c623 | 1112 | if (high == 0 && (low & 0x80000000) == 0) |
47ad8c61 MM |
1113 | return num_insns_constant_wide (low); |
1114 | ||
0858c623 | 1115 | else if (high == -1 && (low & 0x80000000) != 0) |
47ad8c61 MM |
1116 | return num_insns_constant_wide (low); |
1117 | ||
a260abc9 DE |
1118 | else if (mask64_operand (op, mode)) |
1119 | return 2; | |
1120 | ||
47ad8c61 MM |
1121 | else if (low == 0) |
1122 | return num_insns_constant_wide (high) + 1; | |
1123 | ||
1124 | else | |
1125 | return (num_insns_constant_wide (high) | |
1126 | + num_insns_constant_wide (low) + 1); | |
1127 | } | |
4e74d8ec MM |
1128 | } |
1129 | ||
1130 | else | |
1131 | abort (); | |
1132 | } | |
1133 | ||
a4f6c312 SS |
1134 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
1135 | register with one instruction per word. We only do this if we can | |
1136 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
1137 | |
1138 | int | |
1139 | easy_fp_constant (op, mode) | |
592696dd SS |
1140 | rtx op; |
1141 | enum machine_mode mode; | |
9878760c | 1142 | { |
9878760c RK |
1143 | if (GET_CODE (op) != CONST_DOUBLE |
1144 | || GET_MODE (op) != mode | |
4e74d8ec | 1145 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
1146 | return 0; |
1147 | ||
a4f6c312 | 1148 | /* Consider all constants with -msoft-float to be easy. */ |
4e74d8ec | 1149 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
1150 | return 1; |
1151 | ||
a4f6c312 | 1152 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 1153 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
1154 | return 0; |
1155 | ||
5ae4759c | 1156 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
1157 | /* Similarly if we are using -mrelocatable, consider all constants |
1158 | to be hard. */ | |
5ae4759c MM |
1159 | if (TARGET_RELOCATABLE) |
1160 | return 0; | |
1161 | #endif | |
1162 | ||
042259f2 DE |
1163 | if (mode == DFmode) |
1164 | { | |
1165 | long k[2]; | |
1166 | REAL_VALUE_TYPE rv; | |
1167 | ||
1168 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1169 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 1170 | |
4e74d8ec MM |
1171 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
1172 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 1173 | } |
4e74d8ec MM |
1174 | |
1175 | else if (mode == SFmode) | |
042259f2 DE |
1176 | { |
1177 | long l; | |
1178 | REAL_VALUE_TYPE rv; | |
1179 | ||
1180 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1181 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 1182 | |
4e74d8ec | 1183 | return num_insns_constant_wide (l) == 1; |
042259f2 | 1184 | } |
4e74d8ec | 1185 | |
a260abc9 | 1186 | else if (mode == DImode) |
c81fc13e | 1187 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1188 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1189 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1190 | |
a9098fd0 GK |
1191 | else if (mode == SImode) |
1192 | return 1; | |
4e74d8ec MM |
1193 | else |
1194 | abort (); | |
9878760c | 1195 | } |
8f75773e | 1196 | |
50a0b056 GK |
1197 | /* Return 1 if the operand is 0.0. */ |
1198 | int | |
1199 | zero_fp_constant (op, mode) | |
592696dd SS |
1200 | rtx op; |
1201 | enum machine_mode mode; | |
50a0b056 GK |
1202 | { |
1203 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1204 | } | |
1205 | ||
a4f6c312 SS |
1206 | /* Return 1 if the operand is in volatile memory. Note that during |
1207 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
1208 | volatile memory references. So this function allows us to |
1209 | recognize volatile references where its safe. */ | |
1210 | ||
1211 | int | |
1212 | volatile_mem_operand (op, mode) | |
592696dd | 1213 | rtx op; |
b6c9286a MM |
1214 | enum machine_mode mode; |
1215 | { | |
1216 | if (GET_CODE (op) != MEM) | |
1217 | return 0; | |
1218 | ||
1219 | if (!MEM_VOLATILE_P (op)) | |
1220 | return 0; | |
1221 | ||
1222 | if (mode != GET_MODE (op)) | |
1223 | return 0; | |
1224 | ||
1225 | if (reload_completed) | |
1226 | return memory_operand (op, mode); | |
1227 | ||
1228 | if (reload_in_progress) | |
1229 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1230 | ||
1231 | return memory_address_p (mode, XEXP (op, 0)); | |
1232 | } | |
1233 | ||
97f6e72f | 1234 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1235 | |
1236 | int | |
97f6e72f | 1237 | offsettable_mem_operand (op, mode) |
592696dd | 1238 | rtx op; |
914c2e77 RK |
1239 | enum machine_mode mode; |
1240 | { | |
97f6e72f | 1241 | return ((GET_CODE (op) == MEM) |
677a9668 | 1242 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1243 | mode, XEXP (op, 0))); |
914c2e77 RK |
1244 | } |
1245 | ||
9878760c RK |
1246 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1247 | memory. */ | |
1248 | ||
1249 | int | |
1250 | mem_or_easy_const_operand (op, mode) | |
592696dd | 1251 | rtx op; |
9878760c RK |
1252 | enum machine_mode mode; |
1253 | { | |
1254 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1255 | } | |
1256 | ||
1257 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1258 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1259 | |
1260 | int | |
1261 | add_operand (op, mode) | |
592696dd | 1262 | rtx op; |
9878760c RK |
1263 | enum machine_mode mode; |
1264 | { | |
2bfcf297 DB |
1265 | if (GET_CODE (op) == CONST_INT) |
1266 | return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I') | |
1267 | || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')); | |
1268 | ||
1269 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1270 | } |
1271 | ||
dcfedcd0 RK |
1272 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1273 | ||
1274 | int | |
1275 | non_add_cint_operand (op, mode) | |
592696dd | 1276 | rtx op; |
296b8152 | 1277 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1278 | { |
1279 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1280 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000 |
38886f37 | 1281 | && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); |
dcfedcd0 RK |
1282 | } |
1283 | ||
9878760c RK |
1284 | /* Return 1 if the operand is a non-special register or a constant that |
1285 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1286 | ||
1287 | int | |
1288 | logical_operand (op, mode) | |
592696dd | 1289 | rtx op; |
9878760c RK |
1290 | enum machine_mode mode; |
1291 | { | |
40501e5f | 1292 | HOST_WIDE_INT opl, oph; |
1d328b19 | 1293 | |
dfbdccdb GK |
1294 | if (gpc_reg_operand (op, mode)) |
1295 | return 1; | |
1d328b19 | 1296 | |
dfbdccdb | 1297 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
1298 | { |
1299 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
1300 | ||
1301 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
1302 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
1303 | return 0; | |
1304 | #endif | |
1305 | } | |
dfbdccdb GK |
1306 | else if (GET_CODE (op) == CONST_DOUBLE) |
1307 | { | |
1d328b19 | 1308 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 1309 | abort (); |
1d328b19 GK |
1310 | |
1311 | opl = CONST_DOUBLE_LOW (op); | |
1312 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 1313 | if (oph != 0) |
38886f37 | 1314 | return 0; |
dfbdccdb GK |
1315 | } |
1316 | else | |
1317 | return 0; | |
1d328b19 | 1318 | |
40501e5f AM |
1319 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
1320 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
1321 | } |
1322 | ||
dcfedcd0 | 1323 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1324 | above), but could be split into one. */ |
dcfedcd0 RK |
1325 | |
1326 | int | |
1327 | non_logical_cint_operand (op, mode) | |
592696dd | 1328 | rtx op; |
5f59ecb7 | 1329 | enum machine_mode mode; |
dcfedcd0 | 1330 | { |
dfbdccdb | 1331 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1332 | && ! logical_operand (op, mode) |
1333 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1334 | } |
1335 | ||
19ba8161 | 1336 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1337 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1338 | Reject all ones and all zeros, since these should have been optimized | |
1339 | away and confuse the making of MB and ME. */ | |
1340 | ||
1341 | int | |
19ba8161 | 1342 | mask_operand (op, mode) |
592696dd | 1343 | rtx op; |
19ba8161 | 1344 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1345 | { |
02071907 | 1346 | HOST_WIDE_INT c, lsb; |
9878760c | 1347 | |
19ba8161 DE |
1348 | if (GET_CODE (op) != CONST_INT) |
1349 | return 0; | |
1350 | ||
1351 | c = INTVAL (op); | |
1352 | ||
c5059423 AM |
1353 | /* We don't change the number of transitions by inverting, |
1354 | so make sure we start with the LS bit zero. */ | |
1355 | if (c & 1) | |
1356 | c = ~c; | |
1357 | ||
1358 | /* Reject all zeros or all ones. */ | |
1359 | if (c == 0) | |
9878760c RK |
1360 | return 0; |
1361 | ||
c5059423 AM |
1362 | /* Find the first transition. */ |
1363 | lsb = c & -c; | |
1364 | ||
1365 | /* Invert to look for a second transition. */ | |
1366 | c = ~c; | |
9878760c | 1367 | |
c5059423 AM |
1368 | /* Erase first transition. */ |
1369 | c &= -lsb; | |
9878760c | 1370 | |
c5059423 AM |
1371 | /* Find the second transition (if any). */ |
1372 | lsb = c & -c; | |
1373 | ||
1374 | /* Match if all the bits above are 1's (or c is zero). */ | |
1375 | return c == -lsb; | |
9878760c RK |
1376 | } |
1377 | ||
a260abc9 DE |
1378 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1379 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1380 | Reject all ones and all zeros, since these should have been optimized | |
1381 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1382 | |
1383 | int | |
a260abc9 | 1384 | mask64_operand (op, mode) |
592696dd | 1385 | rtx op; |
a260abc9 DE |
1386 | enum machine_mode mode; |
1387 | { | |
1388 | if (GET_CODE (op) == CONST_INT) | |
1389 | { | |
02071907 | 1390 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1391 | |
c5059423 AM |
1392 | /* We don't change the number of transitions by inverting, |
1393 | so make sure we start with the LS bit zero. */ | |
1394 | c = INTVAL (op); | |
1395 | if (c & 1) | |
1396 | c = ~c; | |
a260abc9 | 1397 | |
c5059423 AM |
1398 | /* Reject all zeros or all ones. */ |
1399 | if (c == 0) | |
e2c953b6 DE |
1400 | return 0; |
1401 | ||
c5059423 AM |
1402 | /* Find the transition, and check that all bits above are 1's. */ |
1403 | lsb = c & -c; | |
1404 | return c == -lsb; | |
e2c953b6 | 1405 | } |
a260abc9 DE |
1406 | else if (GET_CODE (op) == CONST_DOUBLE |
1407 | && (mode == VOIDmode || mode == DImode)) | |
1408 | { | |
02071907 | 1409 | HOST_WIDE_INT low, high, lsb; |
a260abc9 | 1410 | |
c5059423 AM |
1411 | if (HOST_BITS_PER_WIDE_INT < 64) |
1412 | high = CONST_DOUBLE_HIGH (op); | |
a260abc9 | 1413 | |
c5059423 AM |
1414 | low = CONST_DOUBLE_LOW (op); |
1415 | if (low & 1) | |
1416 | { | |
1417 | if (HOST_BITS_PER_WIDE_INT < 64) | |
1418 | high = ~high; | |
1419 | low = ~low; | |
1420 | } | |
a260abc9 | 1421 | |
c5059423 AM |
1422 | if (low == 0) |
1423 | { | |
1424 | if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0) | |
1425 | return 0; | |
a260abc9 | 1426 | |
c5059423 AM |
1427 | lsb = high & -high; |
1428 | return high == -lsb; | |
1429 | } | |
a260abc9 | 1430 | |
c5059423 AM |
1431 | lsb = low & -low; |
1432 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
a260abc9 DE |
1433 | } |
1434 | else | |
1435 | return 0; | |
1436 | } | |
1437 | ||
1438 | /* Return 1 if the operand is either a non-special register or a constant | |
1439 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1440 | ||
1441 | int | |
1442 | and64_operand (op, mode) | |
592696dd | 1443 | rtx op; |
9878760c RK |
1444 | enum machine_mode mode; |
1445 | { | |
a4f6c312 | 1446 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1447 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1448 | ||
1449 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1450 | } |
1451 | ||
a260abc9 DE |
1452 | /* Return 1 if the operand is either a non-special register or a |
1453 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1454 | |
1455 | int | |
a260abc9 | 1456 | and_operand (op, mode) |
592696dd | 1457 | rtx op; |
a260abc9 | 1458 | enum machine_mode mode; |
dcfedcd0 | 1459 | { |
a4f6c312 | 1460 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1461 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1462 | ||
1463 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1464 | } |
1465 | ||
9878760c RK |
1466 | /* Return 1 if the operand is a general register or memory operand. */ |
1467 | ||
1468 | int | |
1469 | reg_or_mem_operand (op, mode) | |
592696dd SS |
1470 | rtx op; |
1471 | enum machine_mode mode; | |
9878760c | 1472 | { |
b6c9286a MM |
1473 | return (gpc_reg_operand (op, mode) |
1474 | || memory_operand (op, mode) | |
1475 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1476 | } |
1477 | ||
a7a813f7 | 1478 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1479 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1480 | instruction. */ |
1481 | ||
1482 | int | |
1483 | lwa_operand (op, mode) | |
592696dd SS |
1484 | rtx op; |
1485 | enum machine_mode mode; | |
a7a813f7 RK |
1486 | { |
1487 | rtx inner = op; | |
1488 | ||
1489 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1490 | inner = SUBREG_REG (inner); | |
1491 | ||
1492 | return gpc_reg_operand (inner, mode) | |
1493 | || (memory_operand (inner, mode) | |
1494 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
1495 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
1496 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
1497 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
1498 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
1499 | } |
1500 | ||
9878760c RK |
1501 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1502 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1503 | forced to lr. */ | |
1504 | ||
1505 | int | |
1506 | call_operand (op, mode) | |
592696dd | 1507 | rtx op; |
9878760c RK |
1508 | enum machine_mode mode; |
1509 | { | |
1510 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1511 | return 0; | |
1512 | ||
1513 | return (GET_CODE (op) == SYMBOL_REF | |
1514 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1515 | } | |
1516 | ||
2af3d377 | 1517 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
a4f6c312 | 1518 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1519 | |
1520 | int | |
1521 | current_file_function_operand (op, mode) | |
592696dd | 1522 | rtx op; |
296b8152 | 1523 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1524 | { |
1525 | return (GET_CODE (op) == SYMBOL_REF | |
1526 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1527 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1528 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1529 | } |
1530 | ||
9878760c RK |
1531 | /* Return 1 if this operand is a valid input for a move insn. */ |
1532 | ||
1533 | int | |
1534 | input_operand (op, mode) | |
592696dd | 1535 | rtx op; |
9878760c RK |
1536 | enum machine_mode mode; |
1537 | { | |
eb4e8003 | 1538 | /* Memory is always valid. */ |
9878760c RK |
1539 | if (memory_operand (op, mode)) |
1540 | return 1; | |
1541 | ||
34792e82 | 1542 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1543 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1544 | return 1; |
1545 | ||
eb4e8003 RK |
1546 | /* For floating-point, easy constants are valid. */ |
1547 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1548 | && CONSTANT_P (op) | |
1549 | && easy_fp_constant (op, mode)) | |
1550 | return 1; | |
1551 | ||
4e74d8ec MM |
1552 | /* Allow any integer constant. */ |
1553 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1554 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1555 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1556 | return 1; |
1557 | ||
eb4e8003 RK |
1558 | /* For floating-point or multi-word mode, the only remaining valid type |
1559 | is a register. */ | |
9878760c RK |
1560 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1561 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1562 | return register_operand (op, mode); |
9878760c | 1563 | |
88fe15a1 RK |
1564 | /* The only cases left are integral modes one word or smaller (we |
1565 | do not get called for MODE_CC values). These can be in any | |
1566 | register. */ | |
1567 | if (register_operand (op, mode)) | |
a8b3aeda | 1568 | return 1; |
88fe15a1 | 1569 | |
84cf9dda | 1570 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1571 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1572 | return 1; |
1573 | ||
9ebbca7d GK |
1574 | /* A constant pool expression (relative to the TOC) is valid */ |
1575 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1576 | return 1; |
1577 | ||
88228c4b MM |
1578 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1579 | to be valid. */ | |
f607bc57 | 1580 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
1581 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1582 | && small_data_operand (op, Pmode)) | |
1583 | return 1; | |
1584 | ||
042259f2 | 1585 | return 0; |
9878760c | 1586 | } |
7509c759 | 1587 | |
a4f6c312 | 1588 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
1589 | |
1590 | int | |
1591 | small_data_operand (op, mode) | |
296b8152 KG |
1592 | rtx op ATTRIBUTE_UNUSED; |
1593 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1594 | { |
38c1f2d7 | 1595 | #if TARGET_ELF |
5f59ecb7 | 1596 | rtx sym_ref; |
7509c759 | 1597 | |
d9407988 | 1598 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1599 | return 0; |
a54d04b7 | 1600 | |
f607bc57 | 1601 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
1602 | return 0; |
1603 | ||
88228c4b MM |
1604 | if (GET_CODE (op) == SYMBOL_REF) |
1605 | sym_ref = op; | |
1606 | ||
1607 | else if (GET_CODE (op) != CONST | |
1608 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1609 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1610 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1611 | return 0; |
1612 | ||
88228c4b | 1613 | else |
dbf55e53 MM |
1614 | { |
1615 | rtx sum = XEXP (op, 0); | |
1616 | HOST_WIDE_INT summand; | |
1617 | ||
1618 | /* We have to be careful here, because it is the referenced address | |
1619 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1620 | summand = INTVAL (XEXP (sum, 1)); | |
1621 | if (summand < 0 || summand > g_switch_value) | |
1622 | return 0; | |
1623 | ||
1624 | sym_ref = XEXP (sum, 0); | |
1625 | } | |
88228c4b MM |
1626 | |
1627 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1628 | return 0; |
1629 | ||
1630 | return 1; | |
d9407988 MM |
1631 | |
1632 | #else | |
1633 | return 0; | |
1634 | #endif | |
7509c759 | 1635 | } |
9ebbca7d GK |
1636 | \f |
1637 | static int | |
1638 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1639 | rtx op; | |
1640 | int *have_sym; | |
1641 | int *have_toc; | |
1642 | { | |
1643 | switch (GET_CODE(op)) | |
1644 | { | |
1645 | case SYMBOL_REF: | |
a4f6c312 SS |
1646 | if (CONSTANT_POOL_ADDRESS_P (op)) |
1647 | { | |
1648 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
1649 | { | |
1650 | *have_sym = 1; | |
1651 | return 1; | |
1652 | } | |
1653 | else | |
1654 | return 0; | |
1655 | } | |
1656 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1657 | { | |
1658 | *have_toc = 1; | |
1659 | return 1; | |
1660 | } | |
1661 | else | |
1662 | return 0; | |
9ebbca7d GK |
1663 | case PLUS: |
1664 | case MINUS: | |
a4f6c312 SS |
1665 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) && |
1666 | constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc); | |
9ebbca7d | 1667 | case CONST: |
a4f6c312 | 1668 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 1669 | case CONST_INT: |
a4f6c312 | 1670 | return 1; |
9ebbca7d | 1671 | default: |
a4f6c312 | 1672 | return 0; |
9ebbca7d GK |
1673 | } |
1674 | } | |
1675 | ||
1676 | int | |
1677 | constant_pool_expr_p (op) | |
1678 | rtx op; | |
1679 | { | |
1680 | int have_sym = 0; | |
1681 | int have_toc = 0; | |
1682 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1683 | } | |
1684 | ||
1685 | int | |
1686 | toc_relative_expr_p (op) | |
1687 | rtx op; | |
1688 | { | |
1689 | int have_sym = 0; | |
1690 | int have_toc = 0; | |
1691 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1692 | } | |
1693 | ||
1694 | /* Try machine-dependent ways of modifying an illegitimate address | |
1695 | to be legitimate. If we find one, return the new, valid address. | |
1696 | This is used from only one place: `memory_address' in explow.c. | |
1697 | ||
a4f6c312 SS |
1698 | OLDX is the address as it was before break_out_memory_refs was |
1699 | called. In some cases it is useful to look at this to decide what | |
1700 | needs to be done. | |
9ebbca7d | 1701 | |
a4f6c312 | 1702 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 1703 | |
a4f6c312 SS |
1704 | It is always safe for this function to do nothing. It exists to |
1705 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
1706 | |
1707 | On RS/6000, first check for the sum of a register with a constant | |
1708 | integer that is out of range. If so, generate code to add the | |
1709 | constant with the low-order 16 bits masked to the register and force | |
1710 | this result into another register (this can be done with `cau'). | |
1711 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1712 | possibility of bit 16 being a one. | |
1713 | ||
1714 | Then check for the sum of a register and something not constant, try to | |
1715 | load the other things into a register and return the sum. */ | |
1716 | rtx | |
1717 | rs6000_legitimize_address (x, oldx, mode) | |
1718 | rtx x; | |
1719 | rtx oldx ATTRIBUTE_UNUSED; | |
1720 | enum machine_mode mode; | |
0ac081f6 | 1721 | { |
9ebbca7d GK |
1722 | if (GET_CODE (x) == PLUS |
1723 | && GET_CODE (XEXP (x, 0)) == REG | |
1724 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1725 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1726 | { | |
1727 | HOST_WIDE_INT high_int, low_int; | |
1728 | rtx sum; | |
1729 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1730 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1731 | if (low_int & 0x8000) | |
1732 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1733 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1734 | GEN_INT (high_int)), 0); | |
1735 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1736 | } | |
1737 | else if (GET_CODE (x) == PLUS | |
1738 | && GET_CODE (XEXP (x, 0)) == REG | |
1739 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 1740 | && GET_MODE_NUNITS (mode) == 1 |
9ebbca7d GK |
1741 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) |
1742 | && (TARGET_POWERPC64 || mode != DImode) | |
1743 | && mode != TImode) | |
1744 | { | |
1745 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1746 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1747 | } | |
0ac081f6 AH |
1748 | else if (ALTIVEC_VECTOR_MODE (mode)) |
1749 | { | |
1750 | rtx reg; | |
1751 | ||
1752 | /* Make sure both operands are registers. */ | |
1753 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 1754 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
1755 | force_reg (Pmode, XEXP (x, 1))); |
1756 | ||
1757 | reg = force_reg (Pmode, x); | |
1758 | return reg; | |
1759 | } | |
9ebbca7d GK |
1760 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic |
1761 | && GET_CODE (x) != CONST_INT | |
1762 | && GET_CODE (x) != CONST_DOUBLE | |
1763 | && CONSTANT_P (x) | |
6ac7bf2c GK |
1764 | && GET_MODE_NUNITS (mode) == 1 |
1765 | && (GET_MODE_BITSIZE (mode) <= 32 | |
c3bb62b9 | 1766 | || (TARGET_HARD_FLOAT && mode == DFmode))) |
9ebbca7d GK |
1767 | { |
1768 | rtx reg = gen_reg_rtx (Pmode); | |
1769 | emit_insn (gen_elf_high (reg, (x))); | |
1770 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1771 | } | |
ee890fe2 SS |
1772 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
1773 | && ! flag_pic | |
1774 | && GET_CODE (x) != CONST_INT | |
1775 | && GET_CODE (x) != CONST_DOUBLE | |
1776 | && CONSTANT_P (x) | |
1777 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1778 | && mode != DImode | |
1779 | && mode != TImode) | |
1780 | { | |
1781 | rtx reg = gen_reg_rtx (Pmode); | |
1782 | emit_insn (gen_macho_high (reg, (x))); | |
1783 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1784 | } | |
9ebbca7d GK |
1785 | else if (TARGET_TOC |
1786 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1787 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1788 | { |
1789 | return create_TOC_reference (x); | |
1790 | } | |
1791 | else | |
1792 | return NULL_RTX; | |
1793 | } | |
258bfae2 | 1794 | |
24ea750e DJ |
1795 | /* The convention appears to be to define this wherever it is used. |
1796 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
1797 | is now used here. */ | |
1798 | #ifndef REG_MODE_OK_FOR_BASE_P | |
1799 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
1800 | #endif | |
1801 | ||
1802 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
1803 | replace the input X, or the original X if no replacement is called for. | |
1804 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
1805 | 0 if it should not. | |
1806 | ||
1807 | For RS/6000, we wish to handle large displacements off a base | |
1808 | register by splitting the addend across an addiu/addis and the mem insn. | |
1809 | This cuts number of extra insns needed from 3 to 1. | |
1810 | ||
1811 | On Darwin, we use this to generate code for floating point constants. | |
1812 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
1813 | The Darwin code is inside #if TARGET_MACHO because only then is | |
1814 | machopic_function_base_name() defined. */ | |
1815 | rtx | |
1816 | rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win) | |
1817 | rtx x; | |
1818 | enum machine_mode mode; | |
1819 | int opnum; | |
1820 | int type; | |
1821 | int ind_levels ATTRIBUTE_UNUSED; | |
1822 | int *win; | |
1823 | { | |
1824 | /* We must recognize output that we have already generated ourselves. */ | |
1825 | if (GET_CODE (x) == PLUS | |
1826 | && GET_CODE (XEXP (x, 0)) == PLUS | |
1827 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1828 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1829 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1830 | { | |
1831 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1832 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
1833 | opnum, (enum reload_type)type); | |
1834 | *win = 1; | |
1835 | return x; | |
1836 | } | |
3deb2758 | 1837 | |
24ea750e DJ |
1838 | #if TARGET_MACHO |
1839 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
1840 | && GET_CODE (x) == LO_SUM | |
1841 | && GET_CODE (XEXP (x, 0)) == PLUS | |
1842 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
1843 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
1844 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
1845 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
1846 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
1847 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
1848 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
1849 | { | |
1850 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 1851 | floating point constant. */ |
24ea750e DJ |
1852 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
1853 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
1854 | opnum, (enum reload_type)type); | |
1855 | *win = 1; | |
1856 | return x; | |
1857 | } | |
1858 | #endif | |
1859 | if (GET_CODE (x) == PLUS | |
1860 | && GET_CODE (XEXP (x, 0)) == REG | |
1861 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
1862 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 AH |
1863 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
1864 | && !ALTIVEC_VECTOR_MODE (mode)) | |
24ea750e DJ |
1865 | { |
1866 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
1867 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
1868 | HOST_WIDE_INT high | |
1869 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1870 | ||
1871 | /* Check for 32-bit overflow. */ | |
1872 | if (high + low != val) | |
1873 | { | |
1874 | *win = 0; | |
1875 | return x; | |
1876 | } | |
1877 | ||
1878 | /* Reload the high part into a base reg; leave the low part | |
1879 | in the mem directly. */ | |
1880 | ||
1881 | x = gen_rtx_PLUS (GET_MODE (x), | |
1882 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
1883 | GEN_INT (high)), | |
1884 | GEN_INT (low)); | |
1885 | ||
1886 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1887 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
1888 | opnum, (enum reload_type)type); | |
1889 | *win = 1; | |
1890 | return x; | |
1891 | } | |
1892 | #if TARGET_MACHO | |
1893 | if (GET_CODE (x) == SYMBOL_REF | |
1894 | && DEFAULT_ABI == ABI_DARWIN | |
1895 | && flag_pic) | |
1896 | { | |
1897 | /* Darwin load of floating point constant. */ | |
1898 | rtx offset = gen_rtx (CONST, Pmode, | |
1899 | gen_rtx (MINUS, Pmode, x, | |
1900 | gen_rtx (SYMBOL_REF, Pmode, | |
1901 | machopic_function_base_name ()))); | |
1902 | x = gen_rtx (LO_SUM, GET_MODE (x), | |
1903 | gen_rtx (PLUS, Pmode, pic_offset_table_rtx, | |
1904 | gen_rtx (HIGH, Pmode, offset)), offset); | |
1905 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1906 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
1907 | opnum, (enum reload_type)type); | |
1908 | *win = 1; | |
1909 | return x; | |
1910 | } | |
1911 | #endif | |
1912 | if (TARGET_TOC | |
1913 | && CONSTANT_POOL_EXPR_P (x) | |
1914 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) | |
1915 | { | |
1916 | (x) = create_TOC_reference (x); | |
1917 | *win = 1; | |
1918 | return x; | |
1919 | } | |
1920 | *win = 0; | |
1921 | return x; | |
1922 | } | |
1923 | ||
258bfae2 FS |
1924 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
1925 | that is a valid memory address for an instruction. | |
1926 | The MODE argument is the machine mode for the MEM expression | |
1927 | that wants to use this address. | |
1928 | ||
1929 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1930 | refers to a constant pool entry of an address (or the sum of it | |
1931 | plus a constant), a short (16-bit signed) constant plus a register, | |
1932 | the sum of two registers, or a register indirect, possibly with an | |
1933 | auto-increment. For DFmode and DImode with an constant plus register, | |
1934 | we must ensure that both words are addressable or PowerPC64 with offset | |
1935 | word aligned. | |
1936 | ||
1937 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1938 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1939 | adjacent memory cells are accessed by adding word-sized offsets | |
1940 | during assembly output. */ | |
1941 | int | |
1942 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
1943 | enum machine_mode mode; | |
1944 | rtx x; | |
1945 | int reg_ok_strict; | |
1946 | { | |
1947 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
1948 | return 1; | |
1949 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
1950 | && TARGET_UPDATE | |
1951 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
1952 | return 1; | |
1953 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
1954 | return 1; | |
1955 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
1956 | return 1; | |
1957 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
1958 | if (! reg_ok_strict | |
1959 | && GET_CODE (x) == PLUS | |
1960 | && GET_CODE (XEXP (x, 0)) == REG | |
1961 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
1962 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1963 | return 1; | |
1964 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
1965 | return 1; | |
1966 | if (mode != TImode | |
1967 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1968 | && (TARGET_POWERPC64 || mode != DImode) | |
1969 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
1970 | return 1; | |
1971 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
1972 | return 1; | |
1973 | return 0; | |
1974 | } | |
fb4d4348 | 1975 | \f |
a4f6c312 SS |
1976 | /* Try to output insns to set TARGET equal to the constant C if it can |
1977 | be done in less than N insns. Do all computations in MODE. | |
1978 | Returns the place where the output has been placed if it can be | |
1979 | done and the insns have been emitted. If it would take more than N | |
1980 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
1981 | |
1982 | rtx | |
1983 | rs6000_emit_set_const (dest, mode, source, n) | |
1984 | rtx dest, source; | |
1985 | enum machine_mode mode; | |
1986 | int n ATTRIBUTE_UNUSED; | |
1987 | { | |
1988 | HOST_WIDE_INT c0, c1; | |
1989 | ||
1990 | if (mode == QImode || mode == HImode || mode == SImode) | |
1991 | { | |
1992 | if (dest == NULL) | |
1993 | dest = gen_reg_rtx (mode); | |
1994 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
1995 | return dest; | |
1996 | } | |
1997 | ||
1998 | if (GET_CODE (source) == CONST_INT) | |
1999 | { | |
2000 | c0 = INTVAL (source); | |
2001 | c1 = -(c0 < 0); | |
2002 | } | |
2003 | else if (GET_CODE (source) == CONST_DOUBLE) | |
2004 | { | |
2005 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2006 | c0 = CONST_DOUBLE_LOW (source); | |
2007 | c1 = -(c0 < 0); | |
2008 | #else | |
2009 | c0 = CONST_DOUBLE_LOW (source); | |
2010 | c1 = CONST_DOUBLE_HIGH (source); | |
2011 | #endif | |
2012 | } | |
2013 | else | |
a4f6c312 | 2014 | abort (); |
2bfcf297 DB |
2015 | |
2016 | return rs6000_emit_set_long_const (dest, c0, c1); | |
2017 | } | |
2018 | ||
2019 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
2020 | fall back to a straight forward decomposition. We do this to avoid | |
2021 | exponential run times encountered when looking for longer sequences | |
2022 | with rs6000_emit_set_const. */ | |
2023 | static rtx | |
2024 | rs6000_emit_set_long_const (dest, c1, c2) | |
2025 | rtx dest; | |
2026 | HOST_WIDE_INT c1, c2; | |
2027 | { | |
2028 | if (!TARGET_POWERPC64) | |
2029 | { | |
2030 | rtx operand1, operand2; | |
2031 | ||
2032 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
2033 | DImode); | |
2034 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
2035 | DImode); | |
2036 | emit_move_insn (operand1, GEN_INT (c1)); | |
2037 | emit_move_insn (operand2, GEN_INT (c2)); | |
2038 | } | |
2039 | else | |
2040 | { | |
bc06712d | 2041 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 2042 | |
bc06712d TR |
2043 | ud1 = c1 & 0xffff; |
2044 | ud2 = (c1 & 0xffff0000) >> 16; | |
2bfcf297 | 2045 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 2046 | c2 = c1 >> 32; |
2bfcf297 | 2047 | #endif |
bc06712d TR |
2048 | ud3 = c2 & 0xffff; |
2049 | ud4 = (c2 & 0xffff0000) >> 16; | |
2bfcf297 | 2050 | |
bc06712d TR |
2051 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
2052 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) | |
2bfcf297 | 2053 | { |
bc06712d TR |
2054 | if (ud1 & 0x8000) |
2055 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); | |
2056 | else | |
2057 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 2058 | } |
2bfcf297 | 2059 | |
bc06712d TR |
2060 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
2061 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) | |
252b88f7 | 2062 | { |
bc06712d TR |
2063 | if (ud2 & 0x8000) |
2064 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) | |
2065 | - 0x80000000)); | |
252b88f7 | 2066 | else |
bc06712d TR |
2067 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
2068 | if (ud1 != 0) | |
2069 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 2070 | } |
bc06712d TR |
2071 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
2072 | || (ud4 == 0 && ! (ud3 & 0x8000))) | |
2073 | { | |
2074 | if (ud3 & 0x8000) | |
2075 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) | |
2076 | - 0x80000000)); | |
2077 | else | |
2078 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
2079 | ||
2080 | if (ud2 != 0) | |
2081 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
2082 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
2083 | if (ud1 != 0) | |
2084 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
2085 | } | |
2086 | else | |
2087 | { | |
2088 | if (ud4 & 0x8000) | |
2089 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) | |
2090 | - 0x80000000)); | |
2091 | else | |
2092 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
2093 | ||
2094 | if (ud3 != 0) | |
2095 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 2096 | |
bc06712d TR |
2097 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
2098 | if (ud2 != 0) | |
2099 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, | |
2100 | GEN_INT (ud2 << 16))); | |
2101 | if (ud1 != 0) | |
2102 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
2103 | } | |
2104 | } | |
2bfcf297 DB |
2105 | return dest; |
2106 | } | |
2107 | ||
fb4d4348 GK |
2108 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
2109 | void | |
2110 | rs6000_emit_move (dest, source, mode) | |
2111 | rtx dest; | |
2112 | rtx source; | |
2113 | enum machine_mode mode; | |
2114 | { | |
2115 | rtx operands[2]; | |
2116 | operands[0] = dest; | |
2117 | operands[1] = source; | |
2118 | ||
2119 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
2120 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
2121 | && ! FLOAT_MODE_P (mode) | |
2122 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
2123 | { | |
2124 | /* FIXME. This should never happen. */ | |
2125 | /* Since it seems that it does, do the safe thing and convert | |
2126 | to a CONST_INT. */ | |
2127 | operands[1] = | |
2128 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
2129 | } | |
2130 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
2131 | && ! FLOAT_MODE_P (mode) | |
2132 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
2133 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
2134 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
2135 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
2136 | abort (); | |
c9e8cb32 DD |
2137 | |
2138 | /* Check if GCC is setting up a block move that will end up using FP | |
2139 | registers as temporaries. We must make sure this is acceptable. */ | |
2140 | if (GET_CODE (operands[0]) == MEM | |
2141 | && GET_CODE (operands[1]) == MEM | |
2142 | && mode == DImode | |
41543739 GK |
2143 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
2144 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
2145 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
2146 | ? 32 : MEM_ALIGN (operands[0]))) | |
2147 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
2148 | ? 32 | |
2149 | : MEM_ALIGN (operands[1])))) | |
2150 | && ! MEM_VOLATILE_P (operands [0]) | |
2151 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 2152 | { |
41543739 GK |
2153 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
2154 | adjust_address (operands[1], SImode, 0)); | |
2155 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
2156 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
2157 | return; |
2158 | } | |
fb4d4348 GK |
2159 | |
2160 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
2161 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 2162 | |
ffc14f31 GK |
2163 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
2164 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 2165 | { |
ffc14f31 GK |
2166 | int regnum; |
2167 | ||
2168 | if (reload_in_progress || reload_completed) | |
2169 | regnum = true_regnum (operands[1]); | |
2170 | else if (GET_CODE (operands[1]) == REG) | |
2171 | regnum = REGNO (operands[1]); | |
2172 | else | |
2173 | regnum = -1; | |
fb4d4348 GK |
2174 | |
2175 | /* If operands[1] is a register, on POWER it may have | |
2176 | double-precision data in it, so truncate it to single | |
2177 | precision. */ | |
2178 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
2179 | { | |
2180 | rtx newreg; | |
2181 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
2182 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
2183 | operands[1] = newreg; | |
2184 | } | |
2185 | } | |
2186 | ||
a9098fd0 GK |
2187 | /* Handle the case where reload calls us with an invalid address; |
2188 | and the case of CONSTANT_P_RTX. */ | |
2189 | if (! general_operand (operands[1], mode) | |
2190 | || ! nonimmediate_operand (operands[0], mode) | |
2191 | || GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
fb4d4348 GK |
2192 | { |
2193 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2194 | return; | |
2195 | } | |
a9098fd0 | 2196 | |
fb4d4348 GK |
2197 | /* FIXME: In the long term, this switch statement should go away |
2198 | and be replaced by a sequence of tests based on things like | |
2199 | mode == Pmode. */ | |
2200 | switch (mode) | |
2201 | { | |
2202 | case HImode: | |
2203 | case QImode: | |
2204 | if (CONSTANT_P (operands[1]) | |
2205 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 2206 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2207 | break; |
2208 | ||
06f4e019 | 2209 | case TFmode: |
fb4d4348 GK |
2210 | case DFmode: |
2211 | case SFmode: | |
2212 | if (CONSTANT_P (operands[1]) | |
2213 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 2214 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2215 | break; |
2216 | ||
0ac081f6 AH |
2217 | case V16QImode: |
2218 | case V8HImode: | |
2219 | case V4SFmode: | |
2220 | case V4SImode: | |
2221 | /* fixme: aldyh -- allow vector constants when they are implemented. */ | |
2222 | if (CONSTANT_P (operands[1])) | |
2223 | operands[1] = force_const_mem (mode, operands[1]); | |
2224 | break; | |
2225 | ||
fb4d4348 | 2226 | case SImode: |
a9098fd0 | 2227 | case DImode: |
fb4d4348 GK |
2228 | /* Use default pattern for address of ELF small data */ |
2229 | if (TARGET_ELF | |
a9098fd0 | 2230 | && mode == Pmode |
f607bc57 | 2231 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
2232 | && (GET_CODE (operands[1]) == SYMBOL_REF |
2233 | || GET_CODE (operands[1]) == CONST) | |
2234 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
2235 | { |
2236 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2237 | return; | |
2238 | } | |
2239 | ||
f607bc57 | 2240 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
2241 | && mode == Pmode && mode == SImode |
2242 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
2243 | { |
2244 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
2245 | return; | |
2246 | } | |
2247 | ||
ee890fe2 SS |
2248 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
2249 | && TARGET_NO_TOC && ! flag_pic | |
a9098fd0 | 2250 | && mode == Pmode |
fb4d4348 GK |
2251 | && CONSTANT_P (operands[1]) |
2252 | && GET_CODE (operands[1]) != HIGH | |
2253 | && GET_CODE (operands[1]) != CONST_INT) | |
2254 | { | |
a9098fd0 | 2255 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
2256 | |
2257 | /* If this is a function address on -mcall-aixdesc, | |
2258 | convert it to the address of the descriptor. */ | |
2259 | if (DEFAULT_ABI == ABI_AIX | |
2260 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2261 | && XSTR (operands[1], 0)[0] == '.') | |
2262 | { | |
2263 | const char *name = XSTR (operands[1], 0); | |
2264 | rtx new_ref; | |
2265 | while (*name == '.') | |
2266 | name++; | |
2267 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
2268 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
2269 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
2270 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
2271 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
2272 | operands[1] = new_ref; | |
2273 | } | |
7509c759 | 2274 | |
ee890fe2 SS |
2275 | if (DEFAULT_ABI == ABI_DARWIN) |
2276 | { | |
2277 | emit_insn (gen_macho_high (target, operands[1])); | |
2278 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
2279 | return; | |
2280 | } | |
2281 | ||
fb4d4348 GK |
2282 | emit_insn (gen_elf_high (target, operands[1])); |
2283 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
2284 | return; | |
2285 | } | |
2286 | ||
a9098fd0 GK |
2287 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
2288 | and we have put it in the TOC, we just need to make a TOC-relative | |
2289 | reference to it. */ | |
2290 | if (TARGET_TOC | |
2291 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2292 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
2293 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
2294 | get_pool_mode (operands[1]))) | |
fb4d4348 | 2295 | { |
a9098fd0 | 2296 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 2297 | } |
a9098fd0 GK |
2298 | else if (mode == Pmode |
2299 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
2300 | && ((GET_CODE (operands[1]) != CONST_INT |
2301 | && ! easy_fp_constant (operands[1], mode)) | |
2302 | || (GET_CODE (operands[1]) == CONST_INT | |
2303 | && num_insns_constant (operands[1], mode) > 2) | |
2304 | || (GET_CODE (operands[0]) == REG | |
2305 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
2306 | && GET_CODE (operands[1]) != HIGH |
2307 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2308 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
2309 | { |
2310 | /* Emit a USE operation so that the constant isn't deleted if | |
2311 | expensive optimizations are turned on because nobody | |
2312 | references it. This should only be done for operands that | |
2313 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
2314 | This should not be done for operands that contain LABEL_REFs. | |
2315 | For now, we just handle the obvious case. */ | |
2316 | if (GET_CODE (operands[1]) != LABEL_REF) | |
2317 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
2318 | ||
c859cda6 | 2319 | #if TARGET_MACHO |
ee890fe2 SS |
2320 | /* Darwin uses a special PIC legitimizer. */ |
2321 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
2322 | { | |
ee890fe2 SS |
2323 | operands[1] = |
2324 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
2325 | operands[0]); |
2326 | if (operands[0] != operands[1]) | |
2327 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
2328 | return; |
2329 | } | |
c859cda6 | 2330 | #endif |
ee890fe2 | 2331 | |
fb4d4348 GK |
2332 | /* If we are to limit the number of things we put in the TOC and |
2333 | this is a symbol plus a constant we can add in one insn, | |
2334 | just put the symbol in the TOC and add the constant. Don't do | |
2335 | this if reload is in progress. */ | |
2336 | if (GET_CODE (operands[1]) == CONST | |
2337 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
2338 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 2339 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
2340 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
2341 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
2342 | && ! side_effects_p (operands[0])) | |
2343 | { | |
a4f6c312 SS |
2344 | rtx sym = |
2345 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
2346 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
2347 | ||
a9098fd0 GK |
2348 | sym = force_reg (mode, sym); |
2349 | if (mode == SImode) | |
2350 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
2351 | else | |
2352 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
2353 | return; |
2354 | } | |
2355 | ||
a9098fd0 | 2356 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2357 | |
2358 | if (TARGET_TOC | |
d34c5b80 DE |
2359 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
2360 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
2361 | get_pool_constant (XEXP (operands[1], 0)), | |
2362 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 2363 | { |
ba4828e0 RK |
2364 | operands[1] |
2365 | = gen_rtx_MEM (mode, | |
2366 | create_TOC_reference (XEXP (operands[1], 0))); | |
2367 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 2368 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 2369 | } |
fb4d4348 GK |
2370 | } |
2371 | break; | |
a9098fd0 | 2372 | |
fb4d4348 GK |
2373 | case TImode: |
2374 | if (GET_CODE (operands[0]) == MEM | |
2375 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
2376 | && ! reload_in_progress) | |
792760b9 RK |
2377 | operands[0] |
2378 | = replace_equiv_address (operands[0], | |
2379 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
2380 | |
2381 | if (GET_CODE (operands[1]) == MEM | |
2382 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
2383 | && ! reload_in_progress) | |
792760b9 RK |
2384 | operands[1] |
2385 | = replace_equiv_address (operands[1], | |
2386 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
fb4d4348 GK |
2387 | break; |
2388 | ||
2389 | default: | |
2390 | abort (); | |
2391 | } | |
2392 | ||
a9098fd0 GK |
2393 | /* Above, we may have called force_const_mem which may have returned |
2394 | an invalid address. If we can, fix this up; otherwise, reload will | |
2395 | have to deal with it. */ | |
2396 | if (GET_CODE (operands[1]) == MEM | |
2397 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
2398 | && ! reload_in_progress) | |
f4ef873c | 2399 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 2400 | |
fb4d4348 | 2401 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 2402 | return; |
fb4d4348 | 2403 | } |
4697a36c MM |
2404 | \f |
2405 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2406 | for a call to a function whose data type is FNTYPE. | |
2407 | For a library call, FNTYPE is 0. | |
2408 | ||
2409 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 2410 | so we never return a PARALLEL. */ |
4697a36c MM |
2411 | |
2412 | void | |
2413 | init_cumulative_args (cum, fntype, libname, incoming) | |
2414 | CUMULATIVE_ARGS *cum; | |
2415 | tree fntype; | |
296b8152 | 2416 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
2417 | int incoming; |
2418 | { | |
2419 | static CUMULATIVE_ARGS zero_cumulative; | |
2420 | ||
2421 | *cum = zero_cumulative; | |
2422 | cum->words = 0; | |
2423 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 2424 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 2425 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
7509c759 | 2426 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 2427 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
2428 | |
2429 | if (incoming) | |
bd227acc | 2430 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
2431 | |
2432 | else if (cum->prototype) | |
2433 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
2434 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
2435 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
2436 | ||
2437 | else | |
2438 | cum->nargs_prototype = 0; | |
2439 | ||
2440 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 2441 | |
9ebbca7d GK |
2442 | /* Check for longcall's */ |
2443 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
2444 | cum->call_cookie = CALL_LONG; |
2445 | ||
4697a36c MM |
2446 | if (TARGET_DEBUG_ARG) |
2447 | { | |
2448 | fprintf (stderr, "\ninit_cumulative_args:"); | |
2449 | if (fntype) | |
2450 | { | |
2451 | tree ret_type = TREE_TYPE (fntype); | |
2452 | fprintf (stderr, " ret code = %s,", | |
2453 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
2454 | } | |
2455 | ||
6a4cee5f MM |
2456 | if (cum->call_cookie & CALL_LONG) |
2457 | fprintf (stderr, " longcall,"); | |
2458 | ||
4697a36c MM |
2459 | fprintf (stderr, " proto = %d, nargs = %d\n", |
2460 | cum->prototype, cum->nargs_prototype); | |
2461 | } | |
2462 | } | |
2463 | \f | |
c229cba9 DE |
2464 | /* If defined, a C expression which determines whether, and in which |
2465 | direction, to pad out an argument with extra space. The value | |
2466 | should be of type `enum direction': either `upward' to pad above | |
2467 | the argument, `downward' to pad below, or `none' to inhibit | |
2468 | padding. | |
2469 | ||
2470 | For the AIX ABI structs are always stored left shifted in their | |
2471 | argument slot. */ | |
2472 | ||
9ebbca7d | 2473 | enum direction |
c229cba9 DE |
2474 | function_arg_padding (mode, type) |
2475 | enum machine_mode mode; | |
2476 | tree type; | |
2477 | { | |
c85f7c16 | 2478 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 2479 | return upward; |
c229cba9 DE |
2480 | |
2481 | /* This is the default definition. */ | |
2482 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 2483 | ? upward |
c229cba9 DE |
2484 | : ((mode == BLKmode |
2485 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
2486 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
2487 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 2488 | ? downward : upward)); |
c229cba9 DE |
2489 | } |
2490 | ||
b6c9286a MM |
2491 | /* If defined, a C expression that gives the alignment boundary, in bits, |
2492 | of an argument with the specified mode and type. If it is not defined, | |
2493 | PARM_BOUNDARY is used for all arguments. | |
2494 | ||
2310f99a | 2495 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
2496 | |
2497 | int | |
2498 | function_arg_boundary (mode, type) | |
2499 | enum machine_mode mode; | |
9ebbca7d | 2500 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 2501 | { |
f607bc57 | 2502 | if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode)) |
e1f83b4d | 2503 | return 64; |
0ac081f6 AH |
2504 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2505 | return 128; | |
9ebbca7d | 2506 | else |
b6c9286a | 2507 | return PARM_BOUNDARY; |
b6c9286a MM |
2508 | } |
2509 | \f | |
4697a36c MM |
2510 | /* Update the data in CUM to advance over an argument |
2511 | of mode MODE and data type TYPE. | |
2512 | (TYPE is null for libcalls where that information may not be available.) */ | |
2513 | ||
2514 | void | |
2515 | function_arg_advance (cum, mode, type, named) | |
2516 | CUMULATIVE_ARGS *cum; | |
2517 | enum machine_mode mode; | |
2518 | tree type; | |
2519 | int named; | |
2520 | { | |
2521 | cum->nargs_prototype--; | |
2522 | ||
0ac081f6 AH |
2523 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2524 | { | |
2525 | if (cum->vregno <= ALTIVEC_ARG_MAX_REG && cum->nargs_prototype >= 0) | |
2526 | cum->vregno++; | |
2527 | else | |
2528 | cum->words += RS6000_ARG_SIZE (mode, type); | |
2529 | } | |
f607bc57 | 2530 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2531 | { |
4cc833b7 RH |
2532 | if (TARGET_HARD_FLOAT |
2533 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 2534 | { |
4cc833b7 RH |
2535 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
2536 | cum->fregno++; | |
2537 | else | |
2538 | { | |
2539 | if (mode == DFmode) | |
2540 | cum->words += cum->words & 1; | |
d34c5b80 | 2541 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 2542 | } |
4697a36c | 2543 | } |
4cc833b7 RH |
2544 | else |
2545 | { | |
2546 | int n_words; | |
2547 | int gregno = cum->sysv_gregno; | |
2548 | ||
2549 | /* Aggregates and IEEE quad get passed by reference. */ | |
2550 | if ((type && AGGREGATE_TYPE_P (type)) | |
2551 | || mode == TFmode) | |
2552 | n_words = 1; | |
2553 | else | |
d34c5b80 | 2554 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2555 | |
2556 | /* Long long is put in odd registers. */ | |
2557 | if (n_words == 2 && (gregno & 1) == 0) | |
2558 | gregno += 1; | |
2559 | ||
2560 | /* Long long is not split between registers and stack. */ | |
2561 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
2562 | { | |
2563 | /* Long long is aligned on the stack. */ | |
2564 | if (n_words == 2) | |
2565 | cum->words += cum->words & 1; | |
2566 | cum->words += n_words; | |
2567 | } | |
4697a36c | 2568 | |
4cc833b7 RH |
2569 | /* Note: continuing to accumulate gregno past when we've started |
2570 | spilling to the stack indicates the fact that we've started | |
2571 | spilling to the stack to expand_builtin_saveregs. */ | |
2572 | cum->sysv_gregno = gregno + n_words; | |
2573 | } | |
4697a36c | 2574 | |
4cc833b7 RH |
2575 | if (TARGET_DEBUG_ARG) |
2576 | { | |
2577 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2578 | cum->words, cum->fregno); | |
2579 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
2580 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
2581 | fprintf (stderr, "mode = %4s, named = %d\n", | |
2582 | GET_MODE_NAME (mode), named); | |
2583 | } | |
4697a36c MM |
2584 | } |
2585 | else | |
4cc833b7 RH |
2586 | { |
2587 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2588 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
a4f6c312 | 2589 | |
d34c5b80 | 2590 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 2591 | |
d34c5b80 DE |
2592 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) |
2593 | cum->fregno++; | |
4cc833b7 RH |
2594 | |
2595 | if (TARGET_DEBUG_ARG) | |
2596 | { | |
2597 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2598 | cum->words, cum->fregno); | |
2599 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
2600 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
2601 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
2602 | } | |
2603 | } | |
4697a36c MM |
2604 | } |
2605 | \f | |
2606 | /* Determine where to put an argument to a function. | |
2607 | Value is zero to push the argument on the stack, | |
2608 | or a hard register in which to store the argument. | |
2609 | ||
2610 | MODE is the argument's machine mode. | |
2611 | TYPE is the data type of the argument (as a tree). | |
2612 | This is null for libcalls where that information may | |
2613 | not be available. | |
2614 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2615 | the preceding args and about the function being called. | |
2616 | NAMED is nonzero if this argument is a named parameter | |
2617 | (otherwise it is an extra parameter matching an ellipsis). | |
2618 | ||
2619 | On RS/6000 the first eight words of non-FP are normally in registers | |
2620 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2621 | Under V.4, the first 8 FP args are in registers. | |
2622 | ||
2623 | If this is floating-point and no prototype is specified, we use | |
2624 | both an FP and integer register (or possibly FP reg and stack). Library | |
2625 | functions (when TYPE is zero) always have the proper types for args, | |
2626 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2627 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2628 | |
2629 | struct rtx_def * | |
2630 | function_arg (cum, mode, type, named) | |
2631 | CUMULATIVE_ARGS *cum; | |
2632 | enum machine_mode mode; | |
2633 | tree type; | |
20c29ebe | 2634 | int named; |
4697a36c | 2635 | { |
4cc833b7 | 2636 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2637 | |
a4f6c312 SS |
2638 | /* Return a marker to indicate whether CR1 needs to set or clear the |
2639 | bit that V.4 uses to say fp args were passed in registers. | |
2640 | Assume that we don't need the marker for software floating point, | |
2641 | or compiler generated library calls. */ | |
4697a36c MM |
2642 | if (mode == VOIDmode) |
2643 | { | |
f607bc57 | 2644 | if (abi == ABI_V4 |
7509c759 MM |
2645 | && TARGET_HARD_FLOAT |
2646 | && cum->nargs_prototype < 0 | |
4697a36c | 2647 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2648 | { |
6a4cee5f MM |
2649 | return GEN_INT (cum->call_cookie |
2650 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2651 | ? CALL_V4_SET_FP_ARGS | |
2652 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2653 | } |
4697a36c | 2654 | |
7509c759 | 2655 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2656 | } |
2657 | ||
0ac081f6 AH |
2658 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2659 | { | |
20c29ebe | 2660 | if (named && cum->vregno <= ALTIVEC_ARG_MAX_REG) |
0ac081f6 AH |
2661 | return gen_rtx_REG (mode, cum->vregno); |
2662 | else | |
2663 | return NULL; | |
2664 | } | |
f607bc57 | 2665 | else if (abi == ABI_V4) |
4697a36c | 2666 | { |
4cc833b7 RH |
2667 | if (TARGET_HARD_FLOAT |
2668 | && (mode == SFmode || mode == DFmode)) | |
2669 | { | |
2670 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2671 | return gen_rtx_REG (mode, cum->fregno); | |
2672 | else | |
2673 | return NULL; | |
2674 | } | |
2675 | else | |
2676 | { | |
2677 | int n_words; | |
2678 | int gregno = cum->sysv_gregno; | |
2679 | ||
2680 | /* Aggregates and IEEE quad get passed by reference. */ | |
2681 | if ((type && AGGREGATE_TYPE_P (type)) | |
2682 | || mode == TFmode) | |
2683 | n_words = 1; | |
2684 | else | |
d34c5b80 | 2685 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2686 | |
2687 | /* Long long is put in odd registers. */ | |
2688 | if (n_words == 2 && (gregno & 1) == 0) | |
2689 | gregno += 1; | |
2690 | ||
2691 | /* Long long is not split between registers and stack. */ | |
2692 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2693 | return gen_rtx_REG (mode, gregno); | |
2694 | else | |
2695 | return NULL; | |
2696 | } | |
4697a36c | 2697 | } |
4cc833b7 RH |
2698 | else |
2699 | { | |
2700 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2701 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2702 | int align_words = cum->words + align; | |
4697a36c | 2703 | |
4cc833b7 RH |
2704 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2705 | return NULL_RTX; | |
2706 | ||
2707 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2708 | { | |
2709 | if (! type | |
2710 | || ((cum->nargs_prototype > 0) | |
2711 | /* IBM AIX extended its linkage convention definition always | |
2712 | to require FP args after register save area hole on the | |
2713 | stack. */ | |
2714 | && (DEFAULT_ABI != ABI_AIX | |
2715 | || ! TARGET_XL_CALL | |
2716 | || (align_words < GP_ARG_NUM_REG)))) | |
2717 | return gen_rtx_REG (mode, cum->fregno); | |
2718 | ||
2719 | return gen_rtx_PARALLEL (mode, | |
2720 | gen_rtvec (2, | |
39403d82 | 2721 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2722 | ((align_words >= GP_ARG_NUM_REG) |
2723 | ? NULL_RTX | |
2724 | : (align_words | |
d34c5b80 | 2725 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
2726 | > GP_ARG_NUM_REG |
2727 | /* If this is partially on the stack, then | |
2728 | we only include the portion actually | |
2729 | in registers here. */ | |
39403d82 | 2730 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2731 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2732 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2733 | GP_ARG_MIN_REG + align_words))), |
2734 | const0_rtx), | |
39403d82 DE |
2735 | gen_rtx_EXPR_LIST (VOIDmode, |
2736 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2737 | const0_rtx))); |
4cc833b7 RH |
2738 | } |
2739 | else if (align_words < GP_ARG_NUM_REG) | |
2740 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2741 | else | |
2742 | return NULL_RTX; | |
4697a36c | 2743 | } |
4697a36c MM |
2744 | } |
2745 | \f | |
2746 | /* For an arg passed partly in registers and partly in memory, | |
2747 | this is the number of registers used. | |
2748 | For args passed entirely in registers or entirely in memory, zero. */ | |
2749 | ||
2750 | int | |
2751 | function_arg_partial_nregs (cum, mode, type, named) | |
2752 | CUMULATIVE_ARGS *cum; | |
2753 | enum machine_mode mode; | |
2754 | tree type; | |
d34c5b80 | 2755 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2756 | { |
f607bc57 | 2757 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2758 | return 0; |
4697a36c | 2759 | |
0ac081f6 AH |
2760 | if (USE_FP_FOR_ARG_P (*cum, mode, type) |
2761 | || USE_ALTIVEC_FOR_ARG_P (*cum, mode, type)) | |
4697a36c MM |
2762 | { |
2763 | if (cum->nargs_prototype >= 0) | |
2764 | return 0; | |
2765 | } | |
2766 | ||
2767 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 2768 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
2769 | { |
2770 | int ret = GP_ARG_NUM_REG - cum->words; | |
2771 | if (ret && TARGET_DEBUG_ARG) | |
2772 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2773 | ||
2774 | return ret; | |
2775 | } | |
2776 | ||
2777 | return 0; | |
2778 | } | |
2779 | \f | |
2780 | /* A C expression that indicates when an argument must be passed by | |
2781 | reference. If nonzero for an argument, a copy of that argument is | |
2782 | made in memory and a pointer to the argument is passed instead of | |
2783 | the argument itself. The pointer is passed in whatever way is | |
2784 | appropriate for passing a pointer to that type. | |
2785 | ||
2786 | Under V.4, structures and unions are passed by reference. */ | |
2787 | ||
2788 | int | |
2789 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2790 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2791 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2792 | tree type; |
296b8152 | 2793 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2794 | { |
f607bc57 | 2795 | if (DEFAULT_ABI == ABI_V4 |
4cc833b7 RH |
2796 | && ((type && AGGREGATE_TYPE_P (type)) |
2797 | || mode == TFmode)) | |
4697a36c MM |
2798 | { |
2799 | if (TARGET_DEBUG_ARG) | |
2800 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2801 | ||
2802 | return 1; | |
2803 | } | |
4697a36c MM |
2804 | |
2805 | return 0; | |
2806 | } | |
4697a36c MM |
2807 | \f |
2808 | /* Perform any needed actions needed for a function that is receiving a | |
2809 | variable number of arguments. | |
2810 | ||
2811 | CUM is as above. | |
2812 | ||
2813 | MODE and TYPE are the mode and type of the current parameter. | |
2814 | ||
2815 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2816 | that must be pushed by the prolog to pretend that our caller pushed | |
2817 | it. | |
2818 | ||
2819 | Normally, this macro will push all remaining incoming registers on the | |
2820 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2821 | ||
2822 | void | |
2823 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2824 | CUMULATIVE_ARGS *cum; | |
2825 | enum machine_mode mode; | |
2826 | tree type; | |
2827 | int *pretend_size; | |
2828 | int no_rtl; | |
2829 | ||
2830 | { | |
4cc833b7 RH |
2831 | CUMULATIVE_ARGS next_cum; |
2832 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 2833 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 2834 | int first_reg_offset, set; |
d34c5b80 DE |
2835 | tree fntype; |
2836 | int stdarg_p; | |
4697a36c | 2837 | |
d34c5b80 DE |
2838 | fntype = TREE_TYPE (current_function_decl); |
2839 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2840 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2841 | != void_type_node)); | |
4cc833b7 | 2842 | |
d34c5b80 DE |
2843 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
2844 | For stdargs, we do want to skip the last named argument. */ | |
2845 | next_cum = *cum; | |
2846 | if (stdarg_p) | |
2847 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 2848 | |
f607bc57 | 2849 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 2850 | { |
4cc833b7 RH |
2851 | /* Indicate to allocate space on the stack for varargs save area. */ |
2852 | /* ??? Does this really have to be located at a magic spot on the | |
2853 | stack, or can we allocate this with assign_stack_local instead. */ | |
00dba523 | 2854 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 2855 | if (! no_rtl) |
2c4974b7 | 2856 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2857 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2858 | |
2859 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2860 | } |
60e2d0ca | 2861 | else |
4697a36c | 2862 | { |
d34c5b80 | 2863 | first_reg_offset = next_cum.words; |
4cc833b7 | 2864 | save_area = virtual_incoming_args_rtx; |
00dba523 | 2865 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
2866 | |
2867 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 2868 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 2869 | } |
4697a36c | 2870 | |
dfafc897 | 2871 | set = get_varargs_alias_set (); |
c81fc13e | 2872 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2873 | { |
dfafc897 FS |
2874 | mem = gen_rtx_MEM (BLKmode, |
2875 | plus_constant (save_area, | |
2876 | first_reg_offset * reg_size)), | |
ba4828e0 | 2877 | set_mem_alias_set (mem, set); |
8ac61af7 | 2878 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 2879 | |
4cc833b7 | 2880 | move_block_from_reg |
dfafc897 | 2881 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2882 | GP_ARG_NUM_REG - first_reg_offset, |
2883 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2884 | ||
2885 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2886 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2887 | } | |
2888 | ||
4697a36c | 2889 | /* Save FP registers if needed. */ |
f607bc57 | 2890 | if (DEFAULT_ABI == ABI_V4 |
c81fc13e | 2891 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2892 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2893 | { |
4cc833b7 | 2894 | int fregno = next_cum.fregno; |
9ebbca7d | 2895 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2896 | rtx lab = gen_label_rtx (); |
2897 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2898 | |
4cc833b7 | 2899 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2900 | pc_rtx, |
39403d82 | 2901 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2902 | gen_rtx_NE (VOIDmode, cr1, |
2903 | const0_rtx), | |
39403d82 | 2904 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2905 | pc_rtx))); |
2906 | ||
4cc833b7 RH |
2907 | while (fregno <= FP_ARG_V4_MAX_REG) |
2908 | { | |
dfafc897 | 2909 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 2910 | set_mem_alias_set (mem, set); |
dfafc897 | 2911 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
2912 | fregno++; |
2913 | off += 8; | |
4697a36c | 2914 | } |
4cc833b7 RH |
2915 | |
2916 | emit_label (lab); | |
4697a36c | 2917 | } |
4697a36c | 2918 | } |
4697a36c | 2919 | |
dfafc897 | 2920 | /* Create the va_list data type. */ |
2c4974b7 | 2921 | |
dfafc897 FS |
2922 | tree |
2923 | rs6000_build_va_list () | |
2924 | { | |
bab45a51 | 2925 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2926 | |
9ebbca7d GK |
2927 | /* For AIX, prefer 'char *' because that's what the system |
2928 | header files like. */ | |
f607bc57 | 2929 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 2930 | return build_pointer_type (char_type_node); |
dfafc897 | 2931 | |
0f4fd75d | 2932 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2933 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2934 | |
9ebbca7d GK |
2935 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2936 | unsigned_char_type_node); | |
2937 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2938 | unsigned_char_type_node); | |
dfafc897 FS |
2939 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2940 | ptr_type_node); | |
2941 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
2942 | ptr_type_node); | |
2943 | ||
2944 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
2945 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
2946 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
2947 | DECL_FIELD_CONTEXT (f_sav) = record; | |
2948 | ||
bab45a51 FS |
2949 | TREE_CHAIN (record) = type_decl; |
2950 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
2951 | TYPE_FIELDS (record) = f_gpr; |
2952 | TREE_CHAIN (f_gpr) = f_fpr; | |
2953 | TREE_CHAIN (f_fpr) = f_ovf; | |
2954 | TREE_CHAIN (f_ovf) = f_sav; | |
2955 | ||
2956 | layout_type (record); | |
2957 | ||
2958 | /* The correct type is an array type of one element. */ | |
2959 | return build_array_type (record, build_index_type (size_zero_node)); | |
2960 | } | |
2961 | ||
2962 | /* Implement va_start. */ | |
2963 | ||
2964 | void | |
2965 | rs6000_va_start (stdarg_p, valist, nextarg) | |
2966 | int stdarg_p; | |
2967 | tree valist; | |
2968 | rtx nextarg; | |
4697a36c | 2969 | { |
dfafc897 FS |
2970 | HOST_WIDE_INT words, n_gpr, n_fpr; |
2971 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2972 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 2973 | |
dfafc897 | 2974 | /* Only SVR4 needs something special. */ |
f607bc57 | 2975 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 FS |
2976 | { |
2977 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
2978 | return; | |
2979 | } | |
2980 | ||
973a648b | 2981 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2982 | f_fpr = TREE_CHAIN (f_gpr); |
2983 | f_ovf = TREE_CHAIN (f_fpr); | |
2984 | f_sav = TREE_CHAIN (f_ovf); | |
2985 | ||
8ebecc3b | 2986 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2987 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2988 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2989 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2990 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2991 | ||
2992 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 2993 | words = current_function_args_info.words; |
dfafc897 FS |
2994 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
2995 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
2996 | ||
2997 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
2998 | { |
2999 | fputs ("va_start: words = ", stderr); | |
3000 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
3001 | fputs (", n_gpr = ", stderr); | |
3002 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
3003 | fputs (", n_fpr = ", stderr); | |
3004 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
3005 | putc ('\n', stderr); | |
3006 | } | |
dfafc897 FS |
3007 | |
3008 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
3009 | TREE_SIDE_EFFECTS (t) = 1; | |
3010 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3011 | ||
3012 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
3013 | TREE_SIDE_EFFECTS (t) = 1; | |
3014 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3015 | ||
3016 | /* Find the overflow area. */ | |
3017 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
3018 | if (words != 0) | |
3019 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
3020 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
3021 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
3022 | TREE_SIDE_EFFECTS (t) = 1; | |
3023 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3024 | ||
3025 | /* Find the register save area. */ | |
3026 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
3027 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
3028 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
3029 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
3030 | TREE_SIDE_EFFECTS (t) = 1; | |
3031 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3032 | } | |
3033 | ||
3034 | /* Implement va_arg. */ | |
3035 | ||
3036 | rtx | |
3037 | rs6000_va_arg (valist, type) | |
3038 | tree valist, type; | |
3039 | { | |
3040 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
3041 | tree gpr, fpr, ovf, sav, reg, t, u; | |
3042 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
3043 | rtx lab_false, lab_over, addr_rtx, r; | |
3044 | ||
9ebbca7d GK |
3045 | /* For AIX, the rule is that structures are passed left-aligned in |
3046 | their stack slot. However, GCC does not presently do this: | |
3047 | structures which are the same size as integer types are passed | |
3048 | right-aligned, as if they were in fact integers. This only | |
3049 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
f607bc57 | 3050 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
3051 | { |
3052 | HOST_WIDE_INT align, rounded_size; | |
3053 | enum machine_mode mode; | |
3054 | tree addr_tree; | |
3055 | ||
3056 | /* Compute the rounded size of the type. */ | |
3057 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
3058 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
3059 | * align); | |
3060 | ||
3061 | addr_tree = valist; | |
3062 | ||
3063 | mode = TYPE_MODE (type); | |
3064 | if (mode != BLKmode) | |
3065 | { | |
3066 | HOST_WIDE_INT adj; | |
3067 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
3068 | if (rounded_size > align) | |
3069 | adj = rounded_size; | |
3070 | ||
3071 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
3072 | build_int_2 (rounded_size - adj, 0)); | |
3073 | } | |
3074 | ||
3075 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
3076 | addr_rtx = copy_to_reg (addr_rtx); | |
3077 | ||
3078 | /* Compute new value for AP. */ | |
3079 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
3080 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
3081 | build_int_2 (rounded_size, 0))); | |
3082 | TREE_SIDE_EFFECTS (t) = 1; | |
3083 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3084 | ||
3085 | return addr_rtx; | |
3086 | } | |
dfafc897 | 3087 | |
973a648b | 3088 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
3089 | f_fpr = TREE_CHAIN (f_gpr); |
3090 | f_ovf = TREE_CHAIN (f_fpr); | |
3091 | f_sav = TREE_CHAIN (f_ovf); | |
3092 | ||
8ebecc3b | 3093 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
3094 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
3095 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
3096 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
3097 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
3098 | ||
3099 | size = int_size_in_bytes (type); | |
3100 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 3101 | |
dfafc897 | 3102 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 3103 | { |
dfafc897 FS |
3104 | /* Aggregates and long doubles are passed by reference. */ |
3105 | indirect_p = 1; | |
3106 | reg = gpr; | |
3107 | n_reg = 1; | |
3108 | sav_ofs = 0; | |
3109 | sav_scale = 4; | |
3110 | size = rsize = UNITS_PER_WORD; | |
3111 | } | |
3112 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
3113 | { | |
3114 | /* FP args go in FP registers, if present. */ | |
3115 | indirect_p = 0; | |
3116 | reg = fpr; | |
3117 | n_reg = 1; | |
3118 | sav_ofs = 8*4; | |
3119 | sav_scale = 8; | |
4cc833b7 | 3120 | } |
dfafc897 FS |
3121 | else |
3122 | { | |
3123 | /* Otherwise into GP registers. */ | |
3124 | indirect_p = 0; | |
3125 | reg = gpr; | |
3126 | n_reg = rsize; | |
3127 | sav_ofs = 0; | |
3128 | sav_scale = 4; | |
3129 | } | |
3130 | ||
a4f6c312 | 3131 | /* Pull the value out of the saved registers ... */ |
dfafc897 FS |
3132 | |
3133 | lab_false = gen_label_rtx (); | |
3134 | lab_over = gen_label_rtx (); | |
3135 | addr_rtx = gen_reg_rtx (Pmode); | |
3136 | ||
3137 | emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
a06ef755 RK |
3138 | GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1, |
3139 | lab_false); | |
2c4974b7 | 3140 | |
dfafc897 FS |
3141 | /* Long long is aligned in the registers. */ |
3142 | if (n_reg > 1) | |
2c4974b7 | 3143 | { |
dfafc897 FS |
3144 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, |
3145 | build_int_2 (n_reg - 1, 0)); | |
3146 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
3147 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
3148 | TREE_SIDE_EFFECTS (u) = 1; | |
3149 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2c4974b7 | 3150 | } |
dfafc897 FS |
3151 | |
3152 | if (sav_ofs) | |
3153 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
2c4974b7 | 3154 | else |
dfafc897 | 3155 | t = sav; |
2c4974b7 | 3156 | |
dfafc897 FS |
3157 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0)); |
3158 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 3159 | |
dfafc897 FS |
3160 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
3161 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 3162 | |
dfafc897 FS |
3163 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
3164 | TREE_SIDE_EFFECTS (u) = 1; | |
3165 | ||
3166 | t = build (PLUS_EXPR, ptr_type_node, t, u); | |
3167 | TREE_SIDE_EFFECTS (t) = 1; | |
3168 | ||
3169 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
3170 | if (r != addr_rtx) | |
3171 | emit_move_insn (addr_rtx, r); | |
3172 | ||
3173 | emit_jump_insn (gen_jump (lab_over)); | |
3174 | emit_barrier (); | |
3175 | emit_label (lab_false); | |
3176 | ||
a4f6c312 | 3177 | /* ... otherwise out of the overflow area. */ |
dfafc897 FS |
3178 | |
3179 | /* Make sure we don't find reg 7 for the next int arg. */ | |
3180 | if (n_reg > 1) | |
3181 | { | |
3182 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
3183 | TREE_SIDE_EFFECTS (t) = 1; | |
3184 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3185 | } | |
3186 | ||
3187 | /* Care for on-stack alignment if needed. */ | |
3188 | if (rsize <= 1) | |
3189 | t = ovf; | |
3190 | else | |
3191 | { | |
3192 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0)); | |
3193 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1)); | |
3194 | } | |
3195 | t = save_expr (t); | |
3196 | ||
3197 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
3198 | if (r != addr_rtx) | |
3199 | emit_move_insn (addr_rtx, r); | |
3200 | ||
3201 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
3202 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
3203 | TREE_SIDE_EFFECTS (t) = 1; | |
3204 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3205 | ||
3206 | emit_label (lab_over); | |
3207 | ||
3208 | if (indirect_p) | |
3209 | { | |
3210 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 3211 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
3212 | emit_move_insn (addr_rtx, r); |
3213 | } | |
3214 | ||
3215 | return addr_rtx; | |
4697a36c | 3216 | } |
0ac081f6 AH |
3217 | |
3218 | /* Builtins. */ | |
3219 | ||
3220 | #define def_builtin(MASK, NAME, TYPE, CODE) \ | |
3221 | do { \ | |
3222 | if ((MASK) & target_flags) \ | |
3223 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \ | |
3224 | } while (0) | |
3225 | ||
3226 | struct builtin_description | |
3227 | { | |
3228 | const unsigned int mask; | |
3229 | const enum insn_code icode; | |
3230 | const char *const name; | |
3231 | const enum rs6000_builtins code; | |
3232 | }; | |
24408032 AH |
3233 | |
3234 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ | |
3235 | ||
2212663f | 3236 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
3237 | { |
3238 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
3239 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
3240 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
3241 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
3242 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
3243 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
3244 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
3245 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
3246 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
3247 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
3248 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, | |
3249 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, | |
3250 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
3251 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
3252 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
3253 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
3254 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
3255 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
3256 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
3257 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
3258 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
3259 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
3260 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
3261 | }; | |
2212663f | 3262 | |
95385cbb AH |
3263 | /* DST operations: void foo (void *, const int, const char). */ |
3264 | ||
3265 | static const struct builtin_description bdesc_dst[] = | |
3266 | { | |
3267 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
3268 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
3269 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
3270 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
3271 | }; | |
3272 | ||
2212663f | 3273 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 3274 | |
0ac081f6 AH |
3275 | static const struct builtin_description bdesc_2arg[] = |
3276 | { | |
f18c054f DB |
3277 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
3278 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
3279 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
3280 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
3281 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
3282 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
3283 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
3284 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
3285 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
3286 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
3287 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 3288 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
3289 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
3290 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
3291 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
3292 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
3293 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
3294 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
3295 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
3296 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
3297 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
3298 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
3299 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
3300 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
3301 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
3302 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
3303 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
3304 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
3305 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
3306 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
3307 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
3308 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
3309 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
3310 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
3311 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
3312 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
3313 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
3314 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
3315 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, | |
3316 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
3317 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
3318 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
3319 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
3320 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
3321 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
3322 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
3323 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
3324 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
3325 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
3326 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
3327 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
3328 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
3329 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
3330 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
3331 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
3332 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
3333 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
3334 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
3335 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
3336 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
3337 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
3338 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
3339 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
3340 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
3341 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 3342 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
3343 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
3344 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
3345 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
3346 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
3347 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
3348 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
3349 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
3350 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
3351 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
3352 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
3353 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
3354 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
3355 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
3356 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
3357 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
3358 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
3359 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
3360 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
3361 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
3362 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
3363 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
3364 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 3365 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
3366 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
3367 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
3368 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
3369 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
3370 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
3371 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
3372 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
3373 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
3374 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
3375 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
3376 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
3377 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
3378 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
3379 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
3380 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
3381 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
3382 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
3383 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
3384 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
3385 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
3386 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
3387 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
3388 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 3389 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
ae4b4a02 AH |
3390 | }; |
3391 | ||
3392 | /* AltiVec predicates. */ | |
3393 | ||
3394 | struct builtin_description_predicates | |
3395 | { | |
3396 | const unsigned int mask; | |
3397 | const enum insn_code icode; | |
3398 | const char *opcode; | |
3399 | const char *const name; | |
3400 | const enum rs6000_builtins code; | |
3401 | }; | |
3402 | ||
3403 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
3404 | { | |
3405 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
3406 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
3407 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
3408 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
3409 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
3410 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
3411 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
3412 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
3413 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
3414 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
3415 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
3416 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
3417 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 3418 | }; |
24408032 | 3419 | |
100c4561 AH |
3420 | /* ABS* opreations. */ |
3421 | ||
3422 | static const struct builtin_description bdesc_abs[] = | |
3423 | { | |
3424 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
3425 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
3426 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
3427 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
3428 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
3429 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
3430 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
3431 | }; | |
3432 | ||
617e0e1d DB |
3433 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
3434 | foo (VECa). */ | |
24408032 | 3435 | |
2212663f DB |
3436 | static const struct builtin_description bdesc_1arg[] = |
3437 | { | |
617e0e1d DB |
3438 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
3439 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
3440 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
3441 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
3442 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
3443 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
3444 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
3445 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
3446 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
3447 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
3448 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
3449 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
3450 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
3451 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
3452 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
3453 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
3454 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
2212663f DB |
3455 | }; |
3456 | ||
3457 | static rtx | |
3458 | altivec_expand_unop_builtin (icode, arglist, target) | |
3459 | enum insn_code icode; | |
3460 | tree arglist; | |
3461 | rtx target; | |
3462 | { | |
3463 | rtx pat; | |
3464 | tree arg0 = TREE_VALUE (arglist); | |
3465 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3466 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3467 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3468 | ||
20e26713 AH |
3469 | /* If we got invalid arguments bail out before generating bad rtl. */ |
3470 | if (arg0 == error_mark_node) | |
95385cbb | 3471 | return NULL_RTX; |
20e26713 | 3472 | |
c62f2db5 | 3473 | if (target == 0 |
2212663f DB |
3474 | || GET_MODE (target) != tmode |
3475 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3476 | target = gen_reg_rtx (tmode); | |
3477 | ||
3478 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3479 | op0 = copy_to_mode_reg (mode0, op0); | |
3480 | ||
3481 | pat = GEN_FCN (icode) (target, op0); | |
3482 | if (! pat) | |
3483 | return 0; | |
3484 | emit_insn (pat); | |
0ac081f6 | 3485 | |
2212663f DB |
3486 | return target; |
3487 | } | |
ae4b4a02 | 3488 | |
100c4561 AH |
3489 | static rtx |
3490 | altivec_expand_abs_builtin (icode, arglist, target) | |
3491 | enum insn_code icode; | |
3492 | tree arglist; | |
3493 | rtx target; | |
3494 | { | |
3495 | rtx pat, scratch1, scratch2; | |
3496 | tree arg0 = TREE_VALUE (arglist); | |
3497 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3498 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3499 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3500 | ||
3501 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
3502 | if (arg0 == error_mark_node) | |
3503 | return NULL_RTX; | |
3504 | ||
3505 | if (target == 0 | |
3506 | || GET_MODE (target) != tmode | |
3507 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3508 | target = gen_reg_rtx (tmode); | |
3509 | ||
3510 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3511 | op0 = copy_to_mode_reg (mode0, op0); | |
3512 | ||
3513 | scratch1 = gen_reg_rtx (mode0); | |
3514 | scratch2 = gen_reg_rtx (mode0); | |
3515 | ||
3516 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
3517 | if (! pat) | |
3518 | return 0; | |
3519 | emit_insn (pat); | |
3520 | ||
3521 | return target; | |
3522 | } | |
3523 | ||
0ac081f6 AH |
3524 | static rtx |
3525 | altivec_expand_binop_builtin (icode, arglist, target) | |
3526 | enum insn_code icode; | |
3527 | tree arglist; | |
3528 | rtx target; | |
3529 | { | |
3530 | rtx pat; | |
3531 | tree arg0 = TREE_VALUE (arglist); | |
3532 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3533 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3534 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3535 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3536 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3537 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3538 | ||
20e26713 AH |
3539 | /* If we got invalid arguments bail out before generating bad rtl. */ |
3540 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
95385cbb | 3541 | return NULL_RTX; |
20e26713 | 3542 | |
c62f2db5 | 3543 | if (target == 0 |
0ac081f6 AH |
3544 | || GET_MODE (target) != tmode |
3545 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3546 | target = gen_reg_rtx (tmode); | |
3547 | ||
3548 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3549 | op0 = copy_to_mode_reg (mode0, op0); | |
3550 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3551 | op1 = copy_to_mode_reg (mode1, op1); | |
3552 | ||
3553 | pat = GEN_FCN (icode) (target, op0, op1); | |
3554 | if (! pat) | |
3555 | return 0; | |
3556 | emit_insn (pat); | |
3557 | ||
3558 | return target; | |
3559 | } | |
6525c0e7 | 3560 | |
ae4b4a02 AH |
3561 | static rtx |
3562 | altivec_expand_predicate_builtin (icode, opcode, arglist, target) | |
3563 | enum insn_code icode; | |
3564 | const char *opcode; | |
3565 | tree arglist; | |
3566 | rtx target; | |
3567 | { | |
3568 | rtx pat, scratch; | |
3569 | tree cr6_form = TREE_VALUE (arglist); | |
3570 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3571 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
3572 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3573 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3574 | enum machine_mode tmode = SImode; | |
3575 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3576 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3577 | int cr6_form_int; | |
3578 | ||
3579 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
3580 | { | |
3581 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
3582 | return NULL_RTX; | |
3583 | } | |
3584 | else | |
3585 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
3586 | ||
3587 | if (mode0 != mode1) | |
3588 | abort (); | |
3589 | ||
3590 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
3591 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
3592 | return NULL_RTX; | |
3593 | ||
3594 | if (target == 0 | |
3595 | || GET_MODE (target) != tmode | |
3596 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3597 | target = gen_reg_rtx (tmode); | |
3598 | ||
3599 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3600 | op0 = copy_to_mode_reg (mode0, op0); | |
3601 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3602 | op1 = copy_to_mode_reg (mode1, op1); | |
3603 | ||
3604 | scratch = gen_reg_rtx (mode0); | |
3605 | ||
3606 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
3607 | gen_rtx (SYMBOL_REF, Pmode, opcode)); | |
3608 | if (! pat) | |
3609 | return 0; | |
3610 | emit_insn (pat); | |
3611 | ||
3612 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
3613 | different operations, but the bits in CR6 will be different | |
3614 | depending on what information we want. So we have to play tricks | |
3615 | with CR6 to get the right bits out. | |
3616 | ||
3617 | If you think this is disgusting, look at the specs for the | |
3618 | AltiVec predicates. */ | |
3619 | ||
3620 | switch (cr6_form_int) | |
3621 | { | |
3622 | case 0: | |
3623 | emit_insn (gen_cr6_test_for_zero (target)); | |
3624 | break; | |
3625 | case 1: | |
3626 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
3627 | break; | |
3628 | case 2: | |
3629 | emit_insn (gen_cr6_test_for_lt (target)); | |
3630 | break; | |
3631 | case 3: | |
3632 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
3633 | break; | |
3634 | default: | |
3635 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
3636 | break; | |
3637 | } | |
3638 | ||
3639 | return target; | |
3640 | } | |
3641 | ||
6525c0e7 AH |
3642 | static rtx |
3643 | altivec_expand_stv_builtin (icode, arglist) | |
3644 | enum insn_code icode; | |
3645 | tree arglist; | |
3646 | { | |
3647 | tree arg0 = TREE_VALUE (arglist); | |
3648 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3649 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
3650 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3651 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3652 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
3653 | rtx pat; | |
3654 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
3655 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
3656 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
3657 | ||
3658 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
3659 | if (arg0 == error_mark_node | |
3660 | || arg1 == error_mark_node | |
3661 | || arg2 == error_mark_node) | |
3662 | return NULL_RTX; | |
3663 | ||
3664 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
3665 | op0 = copy_to_mode_reg (mode2, op0); | |
3666 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
3667 | op1 = copy_to_mode_reg (mode0, op1); | |
3668 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
3669 | op2 = copy_to_mode_reg (mode1, op2); | |
3670 | ||
3671 | pat = GEN_FCN (icode) (op1, op2, op0); | |
3672 | if (pat) | |
3673 | emit_insn (pat); | |
3674 | return NULL_RTX; | |
3675 | } | |
3676 | ||
2212663f DB |
3677 | static rtx |
3678 | altivec_expand_ternop_builtin (icode, arglist, target) | |
3679 | enum insn_code icode; | |
3680 | tree arglist; | |
3681 | rtx target; | |
3682 | { | |
3683 | rtx pat; | |
3684 | tree arg0 = TREE_VALUE (arglist); | |
3685 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3686 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
3687 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3688 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3689 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
3690 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3691 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3692 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3693 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 3694 | |
20e26713 AH |
3695 | /* If we got invalid arguments bail out before generating bad rtl. */ |
3696 | if (arg0 == error_mark_node | |
3697 | || arg1 == error_mark_node | |
3698 | || arg2 == error_mark_node) | |
95385cbb | 3699 | return NULL_RTX; |
20e26713 | 3700 | |
c62f2db5 | 3701 | if (target == 0 |
2212663f DB |
3702 | || GET_MODE (target) != tmode |
3703 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3704 | target = gen_reg_rtx (tmode); | |
3705 | ||
3706 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3707 | op0 = copy_to_mode_reg (mode0, op0); | |
3708 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3709 | op1 = copy_to_mode_reg (mode1, op1); | |
3710 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
3711 | op2 = copy_to_mode_reg (mode2, op2); | |
3712 | ||
3713 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
3714 | if (! pat) | |
3715 | return 0; | |
3716 | emit_insn (pat); | |
3717 | ||
3718 | return target; | |
3719 | } | |
0ac081f6 | 3720 | static rtx |
00b960c7 | 3721 | altivec_expand_builtin (exp, target) |
0ac081f6 AH |
3722 | tree exp; |
3723 | rtx target; | |
0ac081f6 AH |
3724 | { |
3725 | struct builtin_description *d; | |
ae4b4a02 | 3726 | struct builtin_description_predicates *dp; |
0ac081f6 AH |
3727 | size_t i; |
3728 | enum insn_code icode; | |
3729 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
3730 | tree arglist = TREE_OPERAND (exp, 1); | |
95385cbb AH |
3731 | tree arg0, arg1, arg2; |
3732 | rtx op0, op1, op2, pat; | |
3733 | enum machine_mode tmode, mode0, mode1, mode2; | |
0ac081f6 AH |
3734 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3735 | ||
3736 | switch (fcode) | |
3737 | { | |
f18c054f DB |
3738 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
3739 | icode = CODE_FOR_altivec_lvx_16qi; | |
0ac081f6 AH |
3740 | arg0 = TREE_VALUE (arglist); |
3741 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3742 | tmode = insn_data[icode].operand[0].mode; | |
3743 | mode0 = insn_data[icode].operand[1].mode; | |
3744 | ||
c62f2db5 | 3745 | if (target == 0 |
0ac081f6 AH |
3746 | || GET_MODE (target) != tmode |
3747 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3748 | target = gen_reg_rtx (tmode); | |
3749 | ||
3750 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3751 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3752 | ||
3753 | pat = GEN_FCN (icode) (target, op0); | |
3754 | if (! pat) | |
3755 | return 0; | |
3756 | emit_insn (pat); | |
3757 | return target; | |
24408032 | 3758 | |
f18c054f DB |
3759 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
3760 | icode = CODE_FOR_altivec_lvx_8hi; | |
3761 | arg0 = TREE_VALUE (arglist); | |
3762 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3763 | tmode = insn_data[icode].operand[0].mode; | |
3764 | mode0 = insn_data[icode].operand[1].mode; | |
0ac081f6 | 3765 | |
c62f2db5 | 3766 | if (target == 0 |
f18c054f DB |
3767 | || GET_MODE (target) != tmode |
3768 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3769 | target = gen_reg_rtx (tmode); | |
3770 | ||
3771 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3772 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3773 | ||
3774 | pat = GEN_FCN (icode) (target, op0); | |
3775 | if (! pat) | |
3776 | return 0; | |
3777 | emit_insn (pat); | |
3778 | return target; | |
24408032 | 3779 | |
f18c054f DB |
3780 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: |
3781 | icode = CODE_FOR_altivec_lvx_4si; | |
3782 | arg0 = TREE_VALUE (arglist); | |
3783 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3784 | tmode = insn_data[icode].operand[0].mode; | |
3785 | mode0 = insn_data[icode].operand[1].mode; | |
3786 | ||
c62f2db5 | 3787 | if (target == 0 |
f18c054f DB |
3788 | || GET_MODE (target) != tmode |
3789 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3790 | target = gen_reg_rtx (tmode); | |
3791 | ||
3792 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3793 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3794 | ||
3795 | pat = GEN_FCN (icode) (target, op0); | |
3796 | if (! pat) | |
3797 | return 0; | |
3798 | emit_insn (pat); | |
3799 | return target; | |
24408032 | 3800 | |
f18c054f DB |
3801 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: |
3802 | icode = CODE_FOR_altivec_lvx_4sf; | |
3803 | arg0 = TREE_VALUE (arglist); | |
3804 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3805 | tmode = insn_data[icode].operand[0].mode; | |
3806 | mode0 = insn_data[icode].operand[1].mode; | |
3807 | ||
c62f2db5 | 3808 | if (target == 0 |
f18c054f DB |
3809 | || GET_MODE (target) != tmode |
3810 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3811 | target = gen_reg_rtx (tmode); | |
3812 | ||
3813 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3814 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3815 | ||
3816 | pat = GEN_FCN (icode) (target, op0); | |
3817 | if (! pat) | |
3818 | return 0; | |
3819 | emit_insn (pat); | |
3820 | return target; | |
3821 | ||
3822 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
3823 | icode = CODE_FOR_altivec_stvx_16qi; | |
3824 | arg0 = TREE_VALUE (arglist); | |
3825 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3826 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3827 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3828 | mode0 = insn_data[icode].operand[0].mode; | |
3829 | mode1 = insn_data[icode].operand[1].mode; | |
3830 | ||
3831 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3832 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3833 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3834 | op1 = copy_to_mode_reg (mode1, op1); | |
3835 | ||
3836 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3837 | if (pat) |
3838 | emit_insn (pat); | |
f18c054f | 3839 | return NULL_RTX; |
24408032 | 3840 | |
f18c054f DB |
3841 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: |
3842 | icode = CODE_FOR_altivec_stvx_8hi; | |
3843 | arg0 = TREE_VALUE (arglist); | |
3844 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3845 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3846 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3847 | mode0 = insn_data[icode].operand[0].mode; | |
3848 | mode1 = insn_data[icode].operand[1].mode; | |
3849 | ||
3850 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3851 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3852 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3853 | op1 = copy_to_mode_reg (mode1, op1); | |
3854 | ||
3855 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3856 | if (pat) |
3857 | emit_insn (pat); | |
f18c054f | 3858 | return NULL_RTX; |
24408032 | 3859 | |
f18c054f DB |
3860 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: |
3861 | icode = CODE_FOR_altivec_stvx_4si; | |
3862 | arg0 = TREE_VALUE (arglist); | |
3863 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3864 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3865 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3866 | mode0 = insn_data[icode].operand[0].mode; | |
3867 | mode1 = insn_data[icode].operand[1].mode; | |
3868 | ||
3869 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3870 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3871 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3872 | op1 = copy_to_mode_reg (mode1, op1); | |
3873 | ||
3874 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3875 | if (pat) |
3876 | emit_insn (pat); | |
f18c054f | 3877 | return NULL_RTX; |
24408032 | 3878 | |
f18c054f DB |
3879 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: |
3880 | icode = CODE_FOR_altivec_stvx_4sf; | |
0ac081f6 AH |
3881 | arg0 = TREE_VALUE (arglist); |
3882 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3883 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3884 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3885 | mode0 = insn_data[icode].operand[0].mode; | |
3886 | mode1 = insn_data[icode].operand[1].mode; | |
3887 | ||
3888 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3889 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3890 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3891 | op1 = copy_to_mode_reg (mode1, op1); | |
3892 | ||
3893 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3894 | if (pat) |
3895 | emit_insn (pat); | |
3896 | return NULL_RTX; | |
3897 | ||
6525c0e7 AH |
3898 | case ALTIVEC_BUILTIN_STVX: |
3899 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
3900 | case ALTIVEC_BUILTIN_STVEBX: | |
3901 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
3902 | case ALTIVEC_BUILTIN_STVEHX: | |
3903 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
3904 | case ALTIVEC_BUILTIN_STVEWX: | |
3905 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
3906 | case ALTIVEC_BUILTIN_STVXL: | |
3907 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3908 | ||
95385cbb AH |
3909 | case ALTIVEC_BUILTIN_MFVSCR: |
3910 | icode = CODE_FOR_altivec_mfvscr; | |
3911 | tmode = insn_data[icode].operand[0].mode; | |
3912 | ||
3913 | if (target == 0 | |
3914 | || GET_MODE (target) != tmode | |
3915 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3916 | target = gen_reg_rtx (tmode); | |
3917 | ||
3918 | pat = GEN_FCN (icode) (target); | |
0ac081f6 AH |
3919 | if (! pat) |
3920 | return 0; | |
3921 | emit_insn (pat); | |
95385cbb AH |
3922 | return target; |
3923 | ||
3924 | case ALTIVEC_BUILTIN_MTVSCR: | |
3925 | icode = CODE_FOR_altivec_mtvscr; | |
3926 | arg0 = TREE_VALUE (arglist); | |
3927 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3928 | mode0 = insn_data[icode].operand[0].mode; | |
3929 | ||
3930 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
3931 | if (arg0 == error_mark_node) | |
3932 | return NULL_RTX; | |
3933 | ||
3934 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3935 | op0 = copy_to_mode_reg (mode0, op0); | |
3936 | ||
3937 | pat = GEN_FCN (icode) (op0); | |
3938 | if (pat) | |
3939 | emit_insn (pat); | |
3940 | return NULL_RTX; | |
3941 | ||
3942 | case ALTIVEC_BUILTIN_DSSALL: | |
3943 | emit_insn (gen_altivec_dssall ()); | |
3944 | return NULL_RTX; | |
3945 | ||
3946 | case ALTIVEC_BUILTIN_DSS: | |
3947 | icode = CODE_FOR_altivec_dss; | |
3948 | arg0 = TREE_VALUE (arglist); | |
3949 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3950 | mode0 = insn_data[icode].operand[0].mode; | |
3951 | ||
3952 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
3953 | if (arg0 == error_mark_node) | |
3954 | return NULL_RTX; | |
3955 | ||
3956 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3957 | op0 = copy_to_mode_reg (mode0, op0); | |
3958 | ||
3959 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 AH |
3960 | return NULL_RTX; |
3961 | } | |
24408032 | 3962 | |
95385cbb AH |
3963 | /* Handle DST variants. */ |
3964 | d = (struct builtin_description *) bdesc_dst; | |
3965 | for (i = 0; i < sizeof (bdesc_dst) / sizeof *d; i++, d++) | |
3966 | if (d->code == fcode) | |
3967 | { | |
3968 | arg0 = TREE_VALUE (arglist); | |
3969 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3970 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
3971 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3972 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3973 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
3974 | mode0 = insn_data[d->icode].operand[0].mode; | |
3975 | mode1 = insn_data[d->icode].operand[1].mode; | |
3976 | mode2 = insn_data[d->icode].operand[2].mode; | |
3977 | ||
3978 | /* Invalid arguments, bail out before generating bad rtl. */ | |
3979 | if (arg0 == error_mark_node | |
3980 | || arg1 == error_mark_node | |
3981 | || arg2 == error_mark_node) | |
3982 | return NULL_RTX; | |
3983 | ||
3984 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) | |
3985 | op0 = copy_to_mode_reg (mode0, op0); | |
3986 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) | |
3987 | op1 = copy_to_mode_reg (mode1, op1); | |
3988 | ||
3989 | if (GET_CODE (op2) != CONST_INT || INTVAL (op2) > 3) | |
3990 | { | |
3991 | error ("argument 3 of `%s' must be a 2-bit literal", d->name); | |
3992 | return NULL_RTX; | |
3993 | } | |
3994 | ||
3995 | pat = GEN_FCN (d->icode) (op0, op1, op2); | |
3996 | if (pat != 0) | |
3997 | emit_insn (pat); | |
3998 | ||
3999 | return NULL_RTX; | |
4000 | } | |
4001 | ||
100c4561 AH |
4002 | /* Expand abs* operations. */ |
4003 | d = (struct builtin_description *) bdesc_abs; | |
4004 | for (i = 0; i < sizeof (bdesc_abs) / sizeof *d; i++, d++) | |
4005 | if (d->code == fcode) | |
4006 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
4007 | ||
2212663f DB |
4008 | /* Handle simple unary operations. */ |
4009 | d = (struct builtin_description *) bdesc_1arg; | |
4010 | for (i = 0; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++) | |
4011 | if (d->code == fcode) | |
4012 | return altivec_expand_unop_builtin (d->icode, arglist, target); | |
0ac081f6 AH |
4013 | |
4014 | /* Handle simple binary operations. */ | |
00b960c7 AH |
4015 | d = (struct builtin_description *) bdesc_2arg; |
4016 | for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
0ac081f6 AH |
4017 | if (d->code == fcode) |
4018 | return altivec_expand_binop_builtin (d->icode, arglist, target); | |
4019 | ||
ae4b4a02 AH |
4020 | /* Expand the AltiVec predicates. */ |
4021 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
4022 | for (i = 0; i < sizeof (bdesc_altivec_preds) / sizeof *dp; i++, dp++) | |
4023 | if (dp->code == fcode) | |
4024 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target); | |
4025 | ||
6525c0e7 AH |
4026 | /* LV* are funky. We initialized them differently. */ |
4027 | switch (fcode) | |
4028 | { | |
4029 | case ALTIVEC_BUILTIN_LVSL: | |
4030 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsl, | |
4031 | arglist, target); | |
4032 | case ALTIVEC_BUILTIN_LVSR: | |
4033 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsr, | |
4034 | arglist, target); | |
4035 | case ALTIVEC_BUILTIN_LVEBX: | |
4036 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvebx, | |
4037 | arglist, target); | |
4038 | case ALTIVEC_BUILTIN_LVEHX: | |
4039 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvehx, | |
4040 | arglist, target); | |
4041 | case ALTIVEC_BUILTIN_LVEWX: | |
4042 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvewx, | |
4043 | arglist, target); | |
4044 | case ALTIVEC_BUILTIN_LVXL: | |
4045 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvxl, | |
4046 | arglist, target); | |
4047 | case ALTIVEC_BUILTIN_LVX: | |
4048 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvx, | |
4049 | arglist, target); | |
4050 | default: | |
4051 | break; | |
4052 | /* Fall through. */ | |
4053 | } | |
95385cbb | 4054 | |
2212663f DB |
4055 | /* Handle simple ternary operations. */ |
4056 | d = (struct builtin_description *) bdesc_3arg; | |
4057 | for (i = 0; i < sizeof (bdesc_3arg) / sizeof *d; i++, d++) | |
4058 | if (d->code == fcode) | |
4059 | return altivec_expand_ternop_builtin (d->icode, arglist, target); | |
4060 | ||
0ac081f6 AH |
4061 | abort (); |
4062 | return NULL_RTX; | |
4063 | } | |
4064 | ||
4065 | /* Expand an expression EXP that calls a built-in function, | |
4066 | with result going to TARGET if that's convenient | |
4067 | (and in mode MODE if that's convenient). | |
4068 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
4069 | IGNORE is nonzero if the value is to be ignored. */ | |
4070 | ||
4071 | static rtx | |
4072 | rs6000_expand_builtin (exp, target, subtarget, mode, ignore) | |
4073 | tree exp; | |
4074 | rtx target; | |
00b960c7 AH |
4075 | rtx subtarget ATTRIBUTE_UNUSED; |
4076 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4077 | int ignore ATTRIBUTE_UNUSED; | |
0ac081f6 AH |
4078 | { |
4079 | if (TARGET_ALTIVEC) | |
00b960c7 | 4080 | return altivec_expand_builtin (exp, target); |
0ac081f6 AH |
4081 | |
4082 | abort (); | |
4083 | } | |
4084 | ||
4085 | static void | |
6fa3f289 | 4086 | rs6000_init_builtins () |
0ac081f6 AH |
4087 | { |
4088 | if (TARGET_ALTIVEC) | |
4089 | altivec_init_builtins (); | |
4090 | } | |
4091 | ||
4092 | static void | |
4093 | altivec_init_builtins (void) | |
4094 | { | |
ae4b4a02 AH |
4095 | struct builtin_description *d; |
4096 | struct builtin_description_predicates *dp; | |
0ac081f6 AH |
4097 | size_t i; |
4098 | ||
4099 | tree endlink = void_list_node; | |
4100 | ||
4101 | tree pint_type_node = build_pointer_type (integer_type_node); | |
95385cbb | 4102 | tree pvoid_type_node = build_pointer_type (void_type_node); |
f18c054f DB |
4103 | tree pshort_type_node = build_pointer_type (short_integer_type_node); |
4104 | tree pchar_type_node = build_pointer_type (char_type_node); | |
4105 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
20e26713 | 4106 | |
2212663f DB |
4107 | tree v4sf_ftype_v4sf_v4sf_v16qi |
4108 | = build_function_type (V4SF_type_node, | |
4109 | tree_cons (NULL_TREE, V4SF_type_node, | |
4110 | tree_cons (NULL_TREE, V4SF_type_node, | |
4111 | tree_cons (NULL_TREE, | |
4112 | V16QI_type_node, | |
4113 | endlink)))); | |
4114 | tree v4si_ftype_v4si_v4si_v16qi | |
4115 | = build_function_type (V4SI_type_node, | |
4116 | tree_cons (NULL_TREE, V4SI_type_node, | |
4117 | tree_cons (NULL_TREE, V4SI_type_node, | |
4118 | tree_cons (NULL_TREE, | |
4119 | V16QI_type_node, | |
4120 | endlink)))); | |
4121 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
4122 | = build_function_type (V8HI_type_node, | |
4123 | tree_cons (NULL_TREE, V8HI_type_node, | |
4124 | tree_cons (NULL_TREE, V8HI_type_node, | |
4125 | tree_cons (NULL_TREE, | |
4126 | V16QI_type_node, | |
4127 | endlink)))); | |
4128 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
4129 | = build_function_type (V16QI_type_node, | |
4130 | tree_cons (NULL_TREE, V16QI_type_node, | |
4131 | tree_cons (NULL_TREE, V16QI_type_node, | |
4132 | tree_cons (NULL_TREE, | |
4133 | V16QI_type_node, | |
4134 | endlink)))); | |
4135 | ||
24408032 | 4136 | /* V4SI foo (char). */ |
2212663f DB |
4137 | tree v4si_ftype_char |
4138 | = build_function_type (V4SI_type_node, | |
4139 | tree_cons (NULL_TREE, char_type_node, endlink)); | |
4140 | ||
24408032 | 4141 | /* V8HI foo (char). */ |
2212663f DB |
4142 | tree v8hi_ftype_char |
4143 | = build_function_type (V8HI_type_node, | |
4144 | tree_cons (NULL_TREE, char_type_node, endlink)); | |
4145 | ||
24408032 | 4146 | /* V16QI foo (char). */ |
2212663f DB |
4147 | tree v16qi_ftype_char |
4148 | = build_function_type (V16QI_type_node, | |
4149 | tree_cons (NULL_TREE, char_type_node, endlink)); | |
24408032 | 4150 | /* V4SF foo (V4SF). */ |
617e0e1d DB |
4151 | tree v4sf_ftype_v4sf |
4152 | = build_function_type (V4SF_type_node, | |
4153 | tree_cons (NULL_TREE, V4SF_type_node, endlink)); | |
0ac081f6 AH |
4154 | |
4155 | /* V4SI foo (int *). */ | |
4156 | tree v4si_ftype_pint | |
4157 | = build_function_type (V4SI_type_node, | |
4158 | tree_cons (NULL_TREE, pint_type_node, endlink)); | |
f18c054f DB |
4159 | /* V8HI foo (short *). */ |
4160 | tree v8hi_ftype_pshort | |
4161 | = build_function_type (V8HI_type_node, | |
4162 | tree_cons (NULL_TREE, pshort_type_node, endlink)); | |
4163 | /* V16QI foo (char *). */ | |
4164 | tree v16qi_ftype_pchar | |
4165 | = build_function_type (V16QI_type_node, | |
4166 | tree_cons (NULL_TREE, pchar_type_node, endlink)); | |
4167 | /* V4SF foo (float *). */ | |
4168 | tree v4sf_ftype_pfloat | |
4169 | = build_function_type (V4SF_type_node, | |
4170 | tree_cons (NULL_TREE, pfloat_type_node, endlink)); | |
0ac081f6 | 4171 | |
20e26713 AH |
4172 | /* V8HI foo (V16QI). */ |
4173 | tree v8hi_ftype_v16qi | |
4174 | = build_function_type (V8HI_type_node, | |
4175 | tree_cons (NULL_TREE, V16QI_type_node, endlink)); | |
4176 | ||
95385cbb AH |
4177 | /* void foo (void *, int, char/literal). */ |
4178 | tree void_ftype_pvoid_int_char | |
4179 | = build_function_type (void_type_node, | |
4180 | tree_cons (NULL_TREE, pvoid_type_node, | |
4181 | tree_cons (NULL_TREE, integer_type_node, | |
4182 | tree_cons (NULL_TREE, | |
4183 | char_type_node, | |
4184 | endlink)))); | |
4185 | ||
0ac081f6 AH |
4186 | /* void foo (int *, V4SI). */ |
4187 | tree void_ftype_pint_v4si | |
4188 | = build_function_type (void_type_node, | |
4189 | tree_cons (NULL_TREE, pint_type_node, | |
4190 | tree_cons (NULL_TREE, V4SI_type_node, | |
4191 | endlink))); | |
f18c054f DB |
4192 | /* void foo (short *, V8HI). */ |
4193 | tree void_ftype_pshort_v8hi | |
4194 | = build_function_type (void_type_node, | |
4195 | tree_cons (NULL_TREE, pshort_type_node, | |
4196 | tree_cons (NULL_TREE, V8HI_type_node, | |
4197 | endlink))); | |
4198 | /* void foo (char *, V16QI). */ | |
4199 | tree void_ftype_pchar_v16qi | |
4200 | = build_function_type (void_type_node, | |
4201 | tree_cons (NULL_TREE, pchar_type_node, | |
4202 | tree_cons (NULL_TREE, V16QI_type_node, | |
4203 | endlink))); | |
4204 | /* void foo (float *, V4SF). */ | |
4205 | tree void_ftype_pfloat_v4sf | |
4206 | = build_function_type (void_type_node, | |
4207 | tree_cons (NULL_TREE, pfloat_type_node, | |
4208 | tree_cons (NULL_TREE, V4SF_type_node, | |
4209 | endlink))); | |
0ac081f6 | 4210 | |
95385cbb AH |
4211 | /* void foo (V4SI). */ |
4212 | tree void_ftype_v4si | |
4213 | = build_function_type (void_type_node, | |
4214 | tree_cons (NULL_TREE, V4SI_type_node, | |
4215 | endlink)); | |
4216 | ||
6525c0e7 AH |
4217 | /* void foo (vint, int, void *). */ |
4218 | tree void_ftype_v4si_int_pvoid | |
4219 | = build_function_type (void_type_node, | |
4220 | tree_cons (NULL_TREE, V4SI_type_node, | |
4221 | tree_cons (NULL_TREE, integer_type_node, | |
4222 | tree_cons (NULL_TREE, | |
4223 | pvoid_type_node, | |
4224 | endlink)))); | |
4225 | ||
4226 | /* void foo (vchar, int, void *). */ | |
4227 | tree void_ftype_v16qi_int_pvoid | |
4228 | = build_function_type (void_type_node, | |
4229 | tree_cons (NULL_TREE, V16QI_type_node, | |
4230 | tree_cons (NULL_TREE, integer_type_node, | |
4231 | tree_cons (NULL_TREE, | |
4232 | pvoid_type_node, | |
4233 | endlink)))); | |
4234 | ||
4235 | /* void foo (vshort, int, void *). */ | |
4236 | tree void_ftype_v8hi_int_pvoid | |
4237 | = build_function_type (void_type_node, | |
4238 | tree_cons (NULL_TREE, V8HI_type_node, | |
4239 | tree_cons (NULL_TREE, integer_type_node, | |
4240 | tree_cons (NULL_TREE, | |
4241 | pvoid_type_node, | |
4242 | endlink)))); | |
4243 | ||
95385cbb AH |
4244 | /* void foo (char). */ |
4245 | tree void_ftype_qi | |
4246 | = build_function_type (void_type_node, | |
4247 | tree_cons (NULL_TREE, char_type_node, | |
4248 | endlink)); | |
4249 | ||
4250 | /* void foo (void). */ | |
4251 | tree void_ftype_void | |
3deb2758 | 4252 | = build_function_type (void_type_node, void_list_node); |
95385cbb AH |
4253 | |
4254 | /* vshort foo (void). */ | |
4255 | tree v8hi_ftype_void | |
3deb2758 | 4256 | = build_function_type (V8HI_type_node, void_list_node); |
95385cbb | 4257 | |
0ac081f6 AH |
4258 | tree v4si_ftype_v4si_v4si |
4259 | = build_function_type (V4SI_type_node, | |
4260 | tree_cons (NULL_TREE, V4SI_type_node, | |
4261 | tree_cons (NULL_TREE, V4SI_type_node, | |
4262 | endlink))); | |
24408032 AH |
4263 | |
4264 | /* These are for the unsigned 5 bit literals. */ | |
4265 | ||
617e0e1d DB |
4266 | tree v4sf_ftype_v4si_char |
4267 | = build_function_type (V4SF_type_node, | |
4268 | tree_cons (NULL_TREE, V4SI_type_node, | |
4269 | tree_cons (NULL_TREE, char_type_node, | |
4270 | endlink))); | |
4271 | tree v4si_ftype_v4sf_char | |
4272 | = build_function_type (V4SI_type_node, | |
4273 | tree_cons (NULL_TREE, V4SF_type_node, | |
4274 | tree_cons (NULL_TREE, char_type_node, | |
4275 | endlink))); | |
2212663f DB |
4276 | tree v4si_ftype_v4si_char |
4277 | = build_function_type (V4SI_type_node, | |
4278 | tree_cons (NULL_TREE, V4SI_type_node, | |
4279 | tree_cons (NULL_TREE, char_type_node, | |
4280 | endlink))); | |
4281 | tree v8hi_ftype_v8hi_char | |
4282 | = build_function_type (V8HI_type_node, | |
4283 | tree_cons (NULL_TREE, V8HI_type_node, | |
4284 | tree_cons (NULL_TREE, char_type_node, | |
4285 | endlink))); | |
4286 | tree v16qi_ftype_v16qi_char | |
4287 | = build_function_type (V16QI_type_node, | |
4288 | tree_cons (NULL_TREE, V16QI_type_node, | |
4289 | tree_cons (NULL_TREE, char_type_node, | |
4290 | endlink))); | |
0ac081f6 | 4291 | |
24408032 AH |
4292 | /* These are for the unsigned 4 bit literals. */ |
4293 | ||
4294 | tree v16qi_ftype_v16qi_v16qi_char | |
4295 | = build_function_type (V16QI_type_node, | |
4296 | tree_cons (NULL_TREE, V16QI_type_node, | |
4297 | tree_cons (NULL_TREE, V16QI_type_node, | |
4298 | tree_cons (NULL_TREE, | |
4299 | char_type_node, | |
4300 | endlink)))); | |
4301 | ||
4302 | tree v8hi_ftype_v8hi_v8hi_char | |
4303 | = build_function_type (V8HI_type_node, | |
4304 | tree_cons (NULL_TREE, V8HI_type_node, | |
4305 | tree_cons (NULL_TREE, V8HI_type_node, | |
4306 | tree_cons (NULL_TREE, | |
4307 | char_type_node, | |
4308 | endlink)))); | |
4309 | ||
4310 | tree v4si_ftype_v4si_v4si_char | |
4311 | = build_function_type (V4SI_type_node, | |
4312 | tree_cons (NULL_TREE, V4SI_type_node, | |
4313 | tree_cons (NULL_TREE, V4SI_type_node, | |
4314 | tree_cons (NULL_TREE, | |
4315 | char_type_node, | |
4316 | endlink)))); | |
4317 | ||
4318 | tree v4sf_ftype_v4sf_v4sf_char | |
4319 | = build_function_type (V4SF_type_node, | |
4320 | tree_cons (NULL_TREE, V4SF_type_node, | |
4321 | tree_cons (NULL_TREE, V4SF_type_node, | |
4322 | tree_cons (NULL_TREE, | |
4323 | char_type_node, | |
4324 | endlink)))); | |
4325 | ||
4326 | /* End of 4 bit literals. */ | |
4327 | ||
0ac081f6 AH |
4328 | tree v4sf_ftype_v4sf_v4sf |
4329 | = build_function_type (V4SF_type_node, | |
4330 | tree_cons (NULL_TREE, V4SF_type_node, | |
4331 | tree_cons (NULL_TREE, V4SF_type_node, | |
4332 | endlink))); | |
617e0e1d DB |
4333 | tree v4sf_ftype_v4sf_v4sf_v4si |
4334 | = build_function_type (V4SF_type_node, | |
4335 | tree_cons (NULL_TREE, V4SF_type_node, | |
4336 | tree_cons (NULL_TREE, V4SF_type_node, | |
4337 | tree_cons (NULL_TREE, | |
4338 | V4SI_type_node, | |
4339 | endlink)))); | |
2212663f DB |
4340 | tree v4sf_ftype_v4sf_v4sf_v4sf |
4341 | = build_function_type (V4SF_type_node, | |
4342 | tree_cons (NULL_TREE, V4SF_type_node, | |
4343 | tree_cons (NULL_TREE, V4SF_type_node, | |
4344 | tree_cons (NULL_TREE, | |
4345 | V4SF_type_node, | |
4346 | endlink)))); | |
617e0e1d DB |
4347 | tree v4si_ftype_v4si_v4si_v4si |
4348 | = build_function_type (V4SI_type_node, | |
4349 | tree_cons (NULL_TREE, V4SI_type_node, | |
4350 | tree_cons (NULL_TREE, V4SI_type_node, | |
4351 | tree_cons (NULL_TREE, | |
4352 | V4SI_type_node, | |
4353 | endlink)))); | |
2212663f | 4354 | |
0ac081f6 AH |
4355 | tree v8hi_ftype_v8hi_v8hi |
4356 | = build_function_type (V8HI_type_node, | |
4357 | tree_cons (NULL_TREE, V8HI_type_node, | |
4358 | tree_cons (NULL_TREE, V8HI_type_node, | |
4359 | endlink))); | |
2212663f DB |
4360 | tree v8hi_ftype_v8hi_v8hi_v8hi |
4361 | = build_function_type (V8HI_type_node, | |
4362 | tree_cons (NULL_TREE, V8HI_type_node, | |
4363 | tree_cons (NULL_TREE, V8HI_type_node, | |
4364 | tree_cons (NULL_TREE, | |
4365 | V8HI_type_node, | |
4366 | endlink)))); | |
4367 | tree v4si_ftype_v8hi_v8hi_v4si | |
4368 | = build_function_type (V4SI_type_node, | |
4369 | tree_cons (NULL_TREE, V8HI_type_node, | |
4370 | tree_cons (NULL_TREE, V8HI_type_node, | |
4371 | tree_cons (NULL_TREE, | |
4372 | V4SI_type_node, | |
4373 | endlink)))); | |
4374 | tree v4si_ftype_v16qi_v16qi_v4si | |
4375 | = build_function_type (V4SI_type_node, | |
4376 | tree_cons (NULL_TREE, V16QI_type_node, | |
4377 | tree_cons (NULL_TREE, V16QI_type_node, | |
4378 | tree_cons (NULL_TREE, | |
4379 | V4SI_type_node, | |
4380 | endlink)))); | |
4381 | ||
0ac081f6 AH |
4382 | tree v16qi_ftype_v16qi_v16qi |
4383 | = build_function_type (V16QI_type_node, | |
4384 | tree_cons (NULL_TREE, V16QI_type_node, | |
4385 | tree_cons (NULL_TREE, V16QI_type_node, | |
4386 | endlink))); | |
2212663f | 4387 | |
0ac081f6 AH |
4388 | tree v4si_ftype_v4sf_v4sf |
4389 | = build_function_type (V4SI_type_node, | |
4390 | tree_cons (NULL_TREE, V4SF_type_node, | |
4391 | tree_cons (NULL_TREE, V4SF_type_node, | |
4392 | endlink))); | |
4393 | ||
100c4561 AH |
4394 | tree v4si_ftype_v4si |
4395 | = build_function_type (V4SI_type_node, | |
4396 | tree_cons (NULL_TREE, V4SI_type_node, endlink)); | |
4397 | ||
4398 | tree v8hi_ftype_v8hi | |
4399 | = build_function_type (V8HI_type_node, | |
4400 | tree_cons (NULL_TREE, V8HI_type_node, endlink)); | |
4401 | ||
4402 | tree v16qi_ftype_v16qi | |
4403 | = build_function_type (V16QI_type_node, | |
4404 | tree_cons (NULL_TREE, V16QI_type_node, endlink)); | |
4405 | ||
0ac081f6 AH |
4406 | tree v8hi_ftype_v16qi_v16qi |
4407 | = build_function_type (V8HI_type_node, | |
4408 | tree_cons (NULL_TREE, V16QI_type_node, | |
4409 | tree_cons (NULL_TREE, V16QI_type_node, | |
4410 | endlink))); | |
4411 | ||
4412 | tree v4si_ftype_v8hi_v8hi | |
4413 | = build_function_type (V4SI_type_node, | |
4414 | tree_cons (NULL_TREE, V8HI_type_node, | |
4415 | tree_cons (NULL_TREE, V8HI_type_node, | |
4416 | endlink))); | |
4417 | ||
4418 | tree v8hi_ftype_v4si_v4si | |
4419 | = build_function_type (V8HI_type_node, | |
4420 | tree_cons (NULL_TREE, V4SI_type_node, | |
4421 | tree_cons (NULL_TREE, V4SI_type_node, | |
4422 | endlink))); | |
4423 | ||
4424 | tree v16qi_ftype_v8hi_v8hi | |
4425 | = build_function_type (V16QI_type_node, | |
4426 | tree_cons (NULL_TREE, V8HI_type_node, | |
4427 | tree_cons (NULL_TREE, V8HI_type_node, | |
4428 | endlink))); | |
4429 | ||
4430 | tree v4si_ftype_v16qi_v4si | |
4431 | = build_function_type (V4SI_type_node, | |
4432 | tree_cons (NULL_TREE, V16QI_type_node, | |
4433 | tree_cons (NULL_TREE, V4SI_type_node, | |
4434 | endlink))); | |
4435 | ||
fa066a23 AH |
4436 | tree v4si_ftype_v16qi_v16qi |
4437 | = build_function_type (V4SI_type_node, | |
4438 | tree_cons (NULL_TREE, V16QI_type_node, | |
4439 | tree_cons (NULL_TREE, V16QI_type_node, | |
4440 | endlink))); | |
4441 | ||
0ac081f6 AH |
4442 | tree v4si_ftype_v8hi_v4si |
4443 | = build_function_type (V4SI_type_node, | |
4444 | tree_cons (NULL_TREE, V8HI_type_node, | |
4445 | tree_cons (NULL_TREE, V4SI_type_node, | |
4446 | endlink))); | |
4447 | ||
20e26713 AH |
4448 | tree v4si_ftype_v8hi |
4449 | = build_function_type (V4SI_type_node, | |
4450 | tree_cons (NULL_TREE, V8HI_type_node, endlink)); | |
4451 | ||
0ac081f6 AH |
4452 | tree int_ftype_v4si_v4si |
4453 | = build_function_type (integer_type_node, | |
4454 | tree_cons (NULL_TREE, V4SI_type_node, | |
4455 | tree_cons (NULL_TREE, V4SI_type_node, | |
4456 | endlink))); | |
4457 | ||
4458 | tree int_ftype_v4sf_v4sf | |
4459 | = build_function_type (integer_type_node, | |
4460 | tree_cons (NULL_TREE, V4SF_type_node, | |
4461 | tree_cons (NULL_TREE, V4SF_type_node, | |
4462 | endlink))); | |
4463 | ||
4464 | tree int_ftype_v16qi_v16qi | |
4465 | = build_function_type (integer_type_node, | |
4466 | tree_cons (NULL_TREE, V16QI_type_node, | |
4467 | tree_cons (NULL_TREE, V16QI_type_node, | |
4468 | endlink))); | |
4469 | ||
ae4b4a02 AH |
4470 | tree int_ftype_int_v4si_v4si |
4471 | = build_function_type | |
4472 | (integer_type_node, | |
4473 | tree_cons (NULL_TREE, integer_type_node, | |
4474 | tree_cons (NULL_TREE, V4SI_type_node, | |
4475 | tree_cons (NULL_TREE, V4SI_type_node, | |
4476 | endlink)))); | |
4477 | ||
4478 | tree int_ftype_int_v4sf_v4sf | |
4479 | = build_function_type | |
4480 | (integer_type_node, | |
4481 | tree_cons (NULL_TREE, integer_type_node, | |
4482 | tree_cons (NULL_TREE, V4SF_type_node, | |
4483 | tree_cons (NULL_TREE, V4SF_type_node, | |
4484 | endlink)))); | |
4485 | ||
4486 | tree int_ftype_int_v8hi_v8hi | |
4487 | = build_function_type | |
4488 | (integer_type_node, | |
4489 | tree_cons (NULL_TREE, integer_type_node, | |
4490 | tree_cons (NULL_TREE, V8HI_type_node, | |
4491 | tree_cons (NULL_TREE, V8HI_type_node, | |
4492 | endlink)))); | |
4493 | ||
4494 | tree int_ftype_int_v16qi_v16qi | |
4495 | = build_function_type | |
4496 | (integer_type_node, | |
4497 | tree_cons (NULL_TREE, integer_type_node, | |
4498 | tree_cons (NULL_TREE, V16QI_type_node, | |
4499 | tree_cons (NULL_TREE, V16QI_type_node, | |
4500 | endlink)))); | |
4501 | ||
95385cbb AH |
4502 | tree v16qi_ftype_int_pvoid |
4503 | = build_function_type (V16QI_type_node, | |
4504 | tree_cons (NULL_TREE, integer_type_node, | |
4505 | tree_cons (NULL_TREE, pvoid_type_node, | |
4506 | endlink))); | |
4507 | ||
6525c0e7 AH |
4508 | tree v4si_ftype_int_pvoid |
4509 | = build_function_type (V4SI_type_node, | |
4510 | tree_cons (NULL_TREE, integer_type_node, | |
4511 | tree_cons (NULL_TREE, pvoid_type_node, | |
4512 | endlink))); | |
4513 | ||
4514 | tree v8hi_ftype_int_pvoid | |
4515 | = build_function_type (V8HI_type_node, | |
4516 | tree_cons (NULL_TREE, integer_type_node, | |
4517 | tree_cons (NULL_TREE, pvoid_type_node, | |
4518 | endlink))); | |
4519 | ||
0ac081f6 AH |
4520 | tree int_ftype_v8hi_v8hi |
4521 | = build_function_type (integer_type_node, | |
4522 | tree_cons (NULL_TREE, V8HI_type_node, | |
4523 | tree_cons (NULL_TREE, V8HI_type_node, | |
4524 | endlink))); | |
4525 | ||
f18c054f DB |
4526 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pfloat, ALTIVEC_BUILTIN_LD_INTERNAL_4sf); |
4527 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
4528 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pint, ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
4529 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
4530 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pshort, ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
4531 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
4532 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pchar, ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
4533 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
95385cbb AH |
4534 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
4535 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
4536 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
4537 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); | |
4538 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSL); | |
4539 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSR); | |
6525c0e7 AH |
4540 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEBX); |
4541 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEHX); | |
4542 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEWX); | |
4543 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVXL); | |
4544 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVX); | |
4545 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVX); | |
4546 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_int_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
4547 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_int_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
4548 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
4549 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVXL); | |
100c4561 | 4550 | |
6f317ef3 | 4551 | /* Add the simple ternary operators. */ |
2212663f DB |
4552 | d = (struct builtin_description *) bdesc_3arg; |
4553 | for (i = 0; i < sizeof (bdesc_3arg) / sizeof *d; i++, d++) | |
4554 | { | |
4555 | ||
4556 | enum machine_mode mode0, mode1, mode2, mode3; | |
4557 | tree type; | |
4558 | ||
4559 | if (d->name == 0) | |
4560 | continue; | |
4561 | ||
4562 | mode0 = insn_data[d->icode].operand[0].mode; | |
4563 | mode1 = insn_data[d->icode].operand[1].mode; | |
4564 | mode2 = insn_data[d->icode].operand[2].mode; | |
4565 | mode3 = insn_data[d->icode].operand[3].mode; | |
4566 | ||
4567 | /* When all four are of the same mode. */ | |
4568 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
4569 | { | |
4570 | switch (mode0) | |
4571 | { | |
617e0e1d DB |
4572 | case V4SImode: |
4573 | type = v4si_ftype_v4si_v4si_v4si; | |
4574 | break; | |
2212663f DB |
4575 | case V4SFmode: |
4576 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
4577 | break; | |
4578 | case V8HImode: | |
4579 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
4580 | break; | |
4581 | case V16QImode: | |
4582 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
4583 | break; | |
4584 | default: | |
4585 | abort(); | |
4586 | } | |
4587 | } | |
4588 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
4589 | { | |
4590 | switch (mode0) | |
4591 | { | |
4592 | case V4SImode: | |
4593 | type = v4si_ftype_v4si_v4si_v16qi; | |
4594 | break; | |
4595 | case V4SFmode: | |
4596 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
4597 | break; | |
4598 | case V8HImode: | |
4599 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
4600 | break; | |
4601 | case V16QImode: | |
4602 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
4603 | break; | |
4604 | default: | |
4605 | abort(); | |
4606 | } | |
4607 | } | |
4608 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode | |
4609 | && mode3 == V4SImode) | |
24408032 | 4610 | type = v4si_ftype_v16qi_v16qi_v4si; |
2212663f DB |
4611 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
4612 | && mode3 == V4SImode) | |
24408032 | 4613 | type = v4si_ftype_v8hi_v8hi_v4si; |
617e0e1d DB |
4614 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
4615 | && mode3 == V4SImode) | |
24408032 AH |
4616 | type = v4sf_ftype_v4sf_v4sf_v4si; |
4617 | ||
4618 | /* vchar, vchar, vchar, 4 bit literal. */ | |
4619 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
4620 | && mode3 == QImode) | |
4621 | type = v16qi_ftype_v16qi_v16qi_char; | |
4622 | ||
4623 | /* vshort, vshort, vshort, 4 bit literal. */ | |
4624 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
4625 | && mode3 == QImode) | |
4626 | type = v8hi_ftype_v8hi_v8hi_char; | |
4627 | ||
4628 | /* vint, vint, vint, 4 bit literal. */ | |
4629 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
4630 | && mode3 == QImode) | |
4631 | type = v4si_ftype_v4si_v4si_char; | |
4632 | ||
4633 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
4634 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
4635 | && mode3 == QImode) | |
4636 | type = v4sf_ftype_v4sf_v4sf_char; | |
4637 | ||
2212663f DB |
4638 | else |
4639 | abort (); | |
4640 | ||
4641 | def_builtin (d->mask, d->name, type, d->code); | |
4642 | } | |
4643 | ||
95385cbb AH |
4644 | /* Add the DST variants. */ |
4645 | d = (struct builtin_description *) bdesc_dst; | |
4646 | for (i = 0; i < sizeof (bdesc_dst) / sizeof *d; i++, d++) | |
4647 | def_builtin (d->mask, d->name, void_ftype_pvoid_int_char, d->code); | |
4648 | ||
ae4b4a02 AH |
4649 | /* Initialize the predicates. */ |
4650 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
4651 | for (i = 0; i < sizeof (bdesc_altivec_preds) / sizeof *dp; i++, dp++) | |
4652 | { | |
4653 | enum machine_mode mode1; | |
4654 | tree type; | |
4655 | ||
4656 | mode1 = insn_data[dp->icode].operand[1].mode; | |
4657 | ||
4658 | switch (mode1) | |
4659 | { | |
4660 | case V4SImode: | |
4661 | type = int_ftype_int_v4si_v4si; | |
4662 | break; | |
4663 | case V8HImode: | |
4664 | type = int_ftype_int_v8hi_v8hi; | |
4665 | break; | |
4666 | case V16QImode: | |
4667 | type = int_ftype_int_v16qi_v16qi; | |
4668 | break; | |
4669 | case V4SFmode: | |
4670 | type = int_ftype_int_v4sf_v4sf; | |
4671 | break; | |
4672 | default: | |
4673 | abort (); | |
4674 | } | |
4675 | ||
4676 | def_builtin (dp->mask, dp->name, type, dp->code); | |
4677 | } | |
4678 | ||
0ac081f6 | 4679 | /* Add the simple binary operators. */ |
00b960c7 AH |
4680 | d = (struct builtin_description *) bdesc_2arg; |
4681 | for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
0ac081f6 AH |
4682 | { |
4683 | enum machine_mode mode0, mode1, mode2; | |
4684 | tree type; | |
4685 | ||
4686 | if (d->name == 0) | |
4687 | continue; | |
4688 | ||
4689 | mode0 = insn_data[d->icode].operand[0].mode; | |
4690 | mode1 = insn_data[d->icode].operand[1].mode; | |
4691 | mode2 = insn_data[d->icode].operand[2].mode; | |
4692 | ||
4693 | /* When all three operands are of the same mode. */ | |
4694 | if (mode0 == mode1 && mode1 == mode2) | |
4695 | { | |
4696 | switch (mode0) | |
4697 | { | |
4698 | case V4SFmode: | |
4699 | type = v4sf_ftype_v4sf_v4sf; | |
4700 | break; | |
4701 | case V4SImode: | |
4702 | type = v4si_ftype_v4si_v4si; | |
4703 | break; | |
4704 | case V16QImode: | |
4705 | type = v16qi_ftype_v16qi_v16qi; | |
4706 | break; | |
4707 | case V8HImode: | |
4708 | type = v8hi_ftype_v8hi_v8hi; | |
4709 | break; | |
4710 | default: | |
4711 | abort (); | |
4712 | } | |
4713 | } | |
4714 | ||
4715 | /* A few other combos we really don't want to do manually. */ | |
4716 | ||
4717 | /* vint, vfloat, vfloat. */ | |
4718 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
4719 | type = v4si_ftype_v4sf_v4sf; | |
4720 | ||
4721 | /* vshort, vchar, vchar. */ | |
4722 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
4723 | type = v8hi_ftype_v16qi_v16qi; | |
4724 | ||
4725 | /* vint, vshort, vshort. */ | |
4726 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
4727 | type = v4si_ftype_v8hi_v8hi; | |
4728 | ||
4729 | /* vshort, vint, vint. */ | |
4730 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
4731 | type = v8hi_ftype_v4si_v4si; | |
4732 | ||
4733 | /* vchar, vshort, vshort. */ | |
4734 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
4735 | type = v16qi_ftype_v8hi_v8hi; | |
4736 | ||
4737 | /* vint, vchar, vint. */ | |
4738 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
4739 | type = v4si_ftype_v16qi_v4si; | |
4740 | ||
fa066a23 AH |
4741 | /* vint, vchar, vchar. */ |
4742 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
4743 | type = v4si_ftype_v16qi_v16qi; | |
4744 | ||
0ac081f6 AH |
4745 | /* vint, vshort, vint. */ |
4746 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
4747 | type = v4si_ftype_v8hi_v4si; | |
2212663f DB |
4748 | |
4749 | /* vint, vint, 5 bit literal. */ | |
4750 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
4751 | type = v4si_ftype_v4si_char; | |
4752 | ||
4753 | /* vshort, vshort, 5 bit literal. */ | |
4754 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
4755 | type = v8hi_ftype_v8hi_char; | |
4756 | ||
4757 | /* vchar, vchar, 5 bit literal. */ | |
4758 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
4759 | type = v16qi_ftype_v16qi_char; | |
0ac081f6 | 4760 | |
617e0e1d DB |
4761 | /* vfloat, vint, 5 bit literal. */ |
4762 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
4763 | type = v4sf_ftype_v4si_char; | |
4764 | ||
4765 | /* vint, vfloat, 5 bit literal. */ | |
4766 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
4767 | type = v4si_ftype_v4sf_char; | |
4768 | ||
0ac081f6 AH |
4769 | /* int, x, x. */ |
4770 | else if (mode0 == SImode) | |
4771 | { | |
4772 | switch (mode1) | |
4773 | { | |
4774 | case V4SImode: | |
4775 | type = int_ftype_v4si_v4si; | |
4776 | break; | |
4777 | case V4SFmode: | |
4778 | type = int_ftype_v4sf_v4sf; | |
4779 | break; | |
4780 | case V16QImode: | |
4781 | type = int_ftype_v16qi_v16qi; | |
4782 | break; | |
4783 | case V8HImode: | |
4784 | type = int_ftype_v8hi_v8hi; | |
4785 | break; | |
4786 | default: | |
4787 | abort (); | |
4788 | } | |
4789 | } | |
4790 | ||
4791 | else | |
4792 | abort (); | |
4793 | ||
2212663f DB |
4794 | def_builtin (d->mask, d->name, type, d->code); |
4795 | } | |
24408032 | 4796 | |
100c4561 AH |
4797 | /* Initialize the abs* operators. */ |
4798 | d = (struct builtin_description *) bdesc_abs; | |
4799 | for (i = 0; i < sizeof (bdesc_abs) / sizeof *d; i++, d++) | |
4800 | { | |
4801 | enum machine_mode mode0; | |
4802 | tree type; | |
4803 | ||
4804 | mode0 = insn_data[d->icode].operand[0].mode; | |
4805 | ||
4806 | switch (mode0) | |
4807 | { | |
4808 | case V4SImode: | |
4809 | type = v4si_ftype_v4si; | |
4810 | break; | |
4811 | case V8HImode: | |
4812 | type = v8hi_ftype_v8hi; | |
4813 | break; | |
4814 | case V16QImode: | |
4815 | type = v16qi_ftype_v16qi; | |
4816 | break; | |
4817 | case V4SFmode: | |
4818 | type = v4sf_ftype_v4sf; | |
4819 | break; | |
4820 | default: | |
4821 | abort (); | |
4822 | } | |
4823 | ||
4824 | def_builtin (d->mask, d->name, type, d->code); | |
4825 | } | |
4826 | ||
2212663f DB |
4827 | /* Add the simple unary operators. */ |
4828 | d = (struct builtin_description *) bdesc_1arg; | |
4829 | for (i = 0; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++) | |
4830 | { | |
4831 | enum machine_mode mode0, mode1; | |
4832 | tree type; | |
4833 | ||
4834 | if (d->name == 0) | |
4835 | continue; | |
4836 | ||
4837 | mode0 = insn_data[d->icode].operand[0].mode; | |
4838 | mode1 = insn_data[d->icode].operand[1].mode; | |
4839 | ||
4840 | if (mode0 == V4SImode && mode1 == QImode) | |
4841 | type = v4si_ftype_char; | |
4842 | else if (mode0 == V8HImode && mode1 == QImode) | |
4843 | type = v8hi_ftype_char; | |
4844 | else if (mode0 == V16QImode && mode1 == QImode) | |
4845 | type = v16qi_ftype_char; | |
617e0e1d DB |
4846 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
4847 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
4848 | else if (mode0 == V8HImode && mode1 == V16QImode) |
4849 | type = v8hi_ftype_v16qi; | |
4850 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
4851 | type = v4si_ftype_v8hi; | |
2212663f DB |
4852 | else |
4853 | abort (); | |
4854 | ||
0ac081f6 AH |
4855 | def_builtin (d->mask, d->name, type, d->code); |
4856 | } | |
4857 | } | |
4858 | ||
5b5040b9 RK |
4859 | \f |
4860 | /* Generate a memory reference for expand_block_move, copying volatile, | |
4861 | and other bits from an original memory reference. */ | |
4862 | ||
4863 | static rtx | |
4864 | expand_block_move_mem (mode, addr, orig_mem) | |
4865 | enum machine_mode mode; | |
4866 | rtx addr; | |
4867 | rtx orig_mem; | |
4868 | { | |
39403d82 | 4869 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 4870 | |
c6df88cb | 4871 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
5b5040b9 RK |
4872 | return mem; |
4873 | } | |
4874 | ||
7e69e155 MM |
4875 | /* Expand a block move operation, and return 1 if successful. Return 0 |
4876 | if we should let the compiler generate normal code. | |
4877 | ||
4878 | operands[0] is the destination | |
4879 | operands[1] is the source | |
4880 | operands[2] is the length | |
4881 | operands[3] is the alignment */ | |
4882 | ||
3933e0e1 MM |
4883 | #define MAX_MOVE_REG 4 |
4884 | ||
7e69e155 MM |
4885 | int |
4886 | expand_block_move (operands) | |
4887 | rtx operands[]; | |
4888 | { | |
b6c9286a MM |
4889 | rtx orig_dest = operands[0]; |
4890 | rtx orig_src = operands[1]; | |
7e69e155 | 4891 | rtx bytes_rtx = operands[2]; |
7e69e155 | 4892 | rtx align_rtx = operands[3]; |
3933e0e1 | 4893 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 4894 | int align; |
3933e0e1 MM |
4895 | int bytes; |
4896 | int offset; | |
4897 | int num_reg; | |
4898 | int i; | |
7e69e155 MM |
4899 | rtx src_reg; |
4900 | rtx dest_reg; | |
3933e0e1 MM |
4901 | rtx src_addr; |
4902 | rtx dest_addr; | |
7e69e155 | 4903 | rtx tmp_reg; |
3933e0e1 | 4904 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
4905 | int move_bytes; |
4906 | ||
3933e0e1 | 4907 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 4908 | if (! constp) |
3933e0e1 MM |
4909 | return 0; |
4910 | ||
5ee95df6 FS |
4911 | /* If this is not a fixed size alignment, abort */ |
4912 | if (GET_CODE (align_rtx) != CONST_INT) | |
4913 | abort (); | |
4914 | align = INTVAL (align_rtx); | |
4915 | ||
7e69e155 | 4916 | /* Anything to move? */ |
3933e0e1 MM |
4917 | bytes = INTVAL (bytes_rtx); |
4918 | if (bytes <= 0) | |
7e69e155 MM |
4919 | return 1; |
4920 | ||
ea9982a8 | 4921 | /* store_one_arg depends on expand_block_move to handle at least the size of |
6f317ef3 | 4922 | reg_parm_stack_space. */ |
ea9982a8 | 4923 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
4924 | return 0; |
4925 | ||
4926 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
4927 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
4928 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 4929 | |
3933e0e1 | 4930 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 4931 | { |
3933e0e1 | 4932 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 4933 | { |
3933e0e1 | 4934 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
4935 | && ! fixed_regs[5] |
4936 | && ! fixed_regs[6] | |
4937 | && ! fixed_regs[7] | |
4938 | && ! fixed_regs[8] | |
4939 | && ! fixed_regs[9] | |
4940 | && ! fixed_regs[10] | |
4941 | && ! fixed_regs[11] | |
4942 | && ! fixed_regs[12]) | |
3933e0e1 MM |
4943 | { |
4944 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
4945 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
4946 | dest_reg, | |
4947 | orig_dest), | |
4948 | expand_block_move_mem (BLKmode, | |
4949 | src_reg, | |
4950 | orig_src), | |
4951 | GEN_INT ((move_bytes == 32) | |
4952 | ? 0 : move_bytes), | |
4c64a852 | 4953 | align_rtx)); |
3933e0e1 MM |
4954 | } |
4955 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
4956 | && ! fixed_regs[5] |
4957 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
4958 | && ! fixed_regs[7] |
4959 | && ! fixed_regs[8] | |
4960 | && ! fixed_regs[9] | |
f9562f27 | 4961 | && ! fixed_regs[10]) |
3933e0e1 MM |
4962 | { |
4963 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
4964 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
4965 | dest_reg, | |
4966 | orig_dest), | |
4967 | expand_block_move_mem (BLKmode, | |
4968 | src_reg, | |
4969 | orig_src), | |
3933e0e1 | 4970 | GEN_INT (move_bytes), |
4c64a852 | 4971 | align_rtx)); |
3933e0e1 MM |
4972 | } |
4973 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
4974 | && ! fixed_regs[5] |
4975 | && ! fixed_regs[6] | |
4976 | && ! fixed_regs[7] | |
4977 | && ! fixed_regs[8]) | |
3933e0e1 MM |
4978 | { |
4979 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
4980 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
4981 | dest_reg, | |
4982 | orig_dest), | |
4983 | expand_block_move_mem (BLKmode, | |
4984 | src_reg, | |
4985 | orig_src), | |
3933e0e1 | 4986 | GEN_INT (move_bytes), |
4c64a852 | 4987 | align_rtx)); |
3933e0e1 | 4988 | } |
acad7ed3 | 4989 | else if (bytes >= 8 && TARGET_POWERPC64 |
a4f6c312 | 4990 | /* 64-bit loads and stores require word-aligned |
82e41834 | 4991 | displacements. */ |
a4f6c312 | 4992 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
acad7ed3 DE |
4993 | { |
4994 | move_bytes = 8; | |
4995 | tmp_reg = gen_reg_rtx (DImode); | |
4996 | emit_move_insn (tmp_reg, | |
4997 | expand_block_move_mem (DImode, | |
2eba1afa | 4998 | src_reg, orig_src)); |
acad7ed3 | 4999 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 5000 | dest_reg, orig_dest), |
acad7ed3 DE |
5001 | tmp_reg); |
5002 | } | |
09a625f7 | 5003 | else if (bytes > 4 && !TARGET_POWERPC64) |
3933e0e1 MM |
5004 | { /* move up to 8 bytes at a time */ |
5005 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
5006 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
5007 | dest_reg, | |
5008 | orig_dest), | |
5009 | expand_block_move_mem (BLKmode, | |
5010 | src_reg, | |
5011 | orig_src), | |
3933e0e1 | 5012 | GEN_INT (move_bytes), |
4c64a852 | 5013 | align_rtx)); |
3933e0e1 | 5014 | } |
cc0d9ba8 | 5015 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
5016 | { /* move 4 bytes */ |
5017 | move_bytes = 4; | |
5018 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
5019 | emit_move_insn (tmp_reg, |
5020 | expand_block_move_mem (SImode, | |
5021 | src_reg, orig_src)); | |
5022 | emit_move_insn (expand_block_move_mem (SImode, | |
5023 | dest_reg, orig_dest), | |
5024 | tmp_reg); | |
3933e0e1 | 5025 | } |
cc0d9ba8 | 5026 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
5027 | { /* move 2 bytes */ |
5028 | move_bytes = 2; | |
5029 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
5030 | emit_move_insn (tmp_reg, |
5031 | expand_block_move_mem (HImode, | |
5032 | src_reg, orig_src)); | |
5033 | emit_move_insn (expand_block_move_mem (HImode, | |
5034 | dest_reg, orig_dest), | |
5035 | tmp_reg); | |
3933e0e1 MM |
5036 | } |
5037 | else if (bytes == 1) /* move 1 byte */ | |
5038 | { | |
5039 | move_bytes = 1; | |
5040 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
5041 | emit_move_insn (tmp_reg, |
5042 | expand_block_move_mem (QImode, | |
5043 | src_reg, orig_src)); | |
5044 | emit_move_insn (expand_block_move_mem (QImode, | |
5045 | dest_reg, orig_dest), | |
5046 | tmp_reg); | |
3933e0e1 MM |
5047 | } |
5048 | else | |
5049 | { /* move up to 4 bytes at a time */ | |
5050 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
5051 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
5052 | dest_reg, | |
5053 | orig_dest), | |
5054 | expand_block_move_mem (BLKmode, | |
5055 | src_reg, | |
5056 | orig_src), | |
3933e0e1 | 5057 | GEN_INT (move_bytes), |
4c64a852 | 5058 | align_rtx)); |
3933e0e1 | 5059 | } |
4c64a852 | 5060 | |
015892ee RK |
5061 | if (bytes > move_bytes) |
5062 | { | |
cc0d9ba8 DE |
5063 | if (! TARGET_POWERPC64) |
5064 | { | |
5065 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
5066 | GEN_INT (move_bytes))); | |
5067 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
5068 | GEN_INT (move_bytes))); | |
5069 | } | |
5070 | else | |
5071 | { | |
5072 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
5073 | GEN_INT (move_bytes))); | |
5074 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
5075 | GEN_INT (move_bytes))); | |
5076 | } | |
015892ee | 5077 | } |
4c64a852 | 5078 | } |
3933e0e1 MM |
5079 | } |
5080 | ||
5081 | else /* string instructions not available */ | |
5082 | { | |
5083 | num_reg = offset = 0; | |
5084 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 5085 | { |
3933e0e1 MM |
5086 | /* Calculate the correct offset for src/dest */ |
5087 | if (offset == 0) | |
7e69e155 | 5088 | { |
3933e0e1 MM |
5089 | src_addr = src_reg; |
5090 | dest_addr = dest_reg; | |
5091 | } | |
5092 | else | |
5093 | { | |
c5c76735 JL |
5094 | src_addr = plus_constant (src_reg, offset); |
5095 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
5096 | } |
5097 | ||
cc0d9ba8 DE |
5098 | /* Generate the appropriate load and store, saving the stores |
5099 | for later. */ | |
5100 | if (bytes >= 8 && TARGET_POWERPC64 | |
a4f6c312 SS |
5101 | /* 64-bit loads and stores require word-aligned |
5102 | displacements. */ | |
cc0d9ba8 | 5103 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
b6c9286a MM |
5104 | { |
5105 | move_bytes = 8; | |
5106 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
5107 | emit_insn (gen_movdi (tmp_reg, |
5108 | expand_block_move_mem (DImode, | |
5109 | src_addr, | |
5110 | orig_src))); | |
5111 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
5112 | dest_addr, | |
5113 | orig_dest), | |
5114 | tmp_reg); | |
b6c9286a | 5115 | } |
cc0d9ba8 | 5116 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
5117 | { |
5118 | move_bytes = 4; | |
5119 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
5120 | emit_insn (gen_movsi (tmp_reg, |
5121 | expand_block_move_mem (SImode, | |
5122 | src_addr, | |
5123 | orig_src))); | |
5124 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
5125 | dest_addr, | |
5126 | orig_dest), | |
5127 | tmp_reg); | |
3933e0e1 | 5128 | } |
cc0d9ba8 | 5129 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
5130 | { |
5131 | move_bytes = 2; | |
5132 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 5133 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
5134 | expand_block_move_mem (HImode, |
5135 | src_addr, | |
5136 | orig_src))); | |
5137 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
5138 | dest_addr, | |
5139 | orig_dest), | |
5140 | tmp_reg); | |
3933e0e1 MM |
5141 | } |
5142 | else | |
5143 | { | |
5144 | move_bytes = 1; | |
5145 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 5146 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
5147 | expand_block_move_mem (QImode, |
5148 | src_addr, | |
5149 | orig_src))); | |
5150 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
5151 | dest_addr, | |
5152 | orig_dest), | |
a4f6c312 | 5153 | tmp_reg); |
3933e0e1 MM |
5154 | } |
5155 | ||
5156 | if (num_reg >= MAX_MOVE_REG) | |
5157 | { | |
5158 | for (i = 0; i < num_reg; i++) | |
5159 | emit_insn (stores[i]); | |
5160 | num_reg = 0; | |
7e69e155 MM |
5161 | } |
5162 | } | |
3933e0e1 | 5163 | |
b6c9286a MM |
5164 | for (i = 0; i < num_reg; i++) |
5165 | emit_insn (stores[i]); | |
7e69e155 MM |
5166 | } |
5167 | ||
5168 | return 1; | |
5169 | } | |
5170 | ||
9878760c RK |
5171 | \f |
5172 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
5173 | PARALLEL and the first section will be tested. */ | |
5174 | ||
5175 | int | |
5176 | load_multiple_operation (op, mode) | |
5177 | rtx op; | |
296b8152 | 5178 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
5179 | { |
5180 | int count = XVECLEN (op, 0); | |
e2c953b6 | 5181 | unsigned int dest_regno; |
9878760c RK |
5182 | rtx src_addr; |
5183 | int i; | |
5184 | ||
5185 | /* Perform a quick check so we don't blow up below. */ | |
5186 | if (count <= 1 | |
5187 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5188 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
5189 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
5190 | return 0; | |
5191 | ||
5192 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
5193 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
5194 | ||
5195 | for (i = 1; i < count; i++) | |
5196 | { | |
5197 | rtx elt = XVECEXP (op, 0, i); | |
5198 | ||
5199 | if (GET_CODE (elt) != SET | |
5200 | || GET_CODE (SET_DEST (elt)) != REG | |
5201 | || GET_MODE (SET_DEST (elt)) != SImode | |
5202 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
5203 | || GET_CODE (SET_SRC (elt)) != MEM | |
5204 | || GET_MODE (SET_SRC (elt)) != SImode | |
5205 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
5206 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
5207 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
5208 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
5209 | return 0; | |
5210 | } | |
5211 | ||
5212 | return 1; | |
5213 | } | |
5214 | ||
5215 | /* Similar, but tests for store multiple. Here, the second vector element | |
5216 | is a CLOBBER. It will be tested later. */ | |
5217 | ||
5218 | int | |
5219 | store_multiple_operation (op, mode) | |
5220 | rtx op; | |
296b8152 | 5221 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
5222 | { |
5223 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 5224 | unsigned int src_regno; |
9878760c RK |
5225 | rtx dest_addr; |
5226 | int i; | |
5227 | ||
5228 | /* Perform a quick check so we don't blow up below. */ | |
5229 | if (count <= 1 | |
5230 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5231 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
5232 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
5233 | return 0; | |
5234 | ||
5235 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
5236 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
5237 | ||
5238 | for (i = 1; i < count; i++) | |
5239 | { | |
5240 | rtx elt = XVECEXP (op, 0, i + 1); | |
5241 | ||
5242 | if (GET_CODE (elt) != SET | |
5243 | || GET_CODE (SET_SRC (elt)) != REG | |
5244 | || GET_MODE (SET_SRC (elt)) != SImode | |
5245 | || REGNO (SET_SRC (elt)) != src_regno + i | |
5246 | || GET_CODE (SET_DEST (elt)) != MEM | |
5247 | || GET_MODE (SET_DEST (elt)) != SImode | |
5248 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
5249 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
5250 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
5251 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
5252 | return 0; | |
5253 | } | |
5254 | ||
5255 | return 1; | |
5256 | } | |
9ebbca7d | 5257 | |
00b960c7 AH |
5258 | /* Return 1 for a parallel vrsave operation. */ |
5259 | ||
5260 | int | |
5261 | vrsave_operation (op, mode) | |
5262 | rtx op; | |
5263 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5264 | { | |
5265 | int count = XVECLEN (op, 0); | |
5266 | unsigned int dest_regno, src_regno; | |
5267 | int i; | |
5268 | ||
5269 | if (count <= 1 | |
5270 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5271 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 5272 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
5273 | return 0; |
5274 | ||
5275 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
5276 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
5277 | ||
5278 | if (dest_regno != VRSAVE_REGNO | |
5279 | && src_regno != VRSAVE_REGNO) | |
5280 | return 0; | |
5281 | ||
5282 | for (i = 1; i < count; i++) | |
5283 | { | |
5284 | rtx elt = XVECEXP (op, 0, i); | |
5285 | ||
9aa86737 AH |
5286 | if (GET_CODE (elt) != CLOBBER |
5287 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
5288 | return 0; |
5289 | } | |
5290 | ||
5291 | return 1; | |
5292 | } | |
5293 | ||
a4f6c312 | 5294 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
5295 | |
5296 | int | |
5297 | mtcrf_operation (op, mode) | |
5298 | rtx op; | |
5299 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5300 | { | |
5301 | int count = XVECLEN (op, 0); | |
5302 | int i; | |
9ebbca7d GK |
5303 | rtx src_reg; |
5304 | ||
5305 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
5306 | if (count < 1 |
5307 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5308 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
5309 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 5310 | return 0; |
e35b9579 | 5311 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
5312 | |
5313 | if (GET_CODE (src_reg) != REG | |
5314 | || GET_MODE (src_reg) != SImode | |
5315 | || ! INT_REGNO_P (REGNO (src_reg))) | |
5316 | return 0; | |
5317 | ||
e35b9579 | 5318 | for (i = 0; i < count; i++) |
9ebbca7d GK |
5319 | { |
5320 | rtx exp = XVECEXP (op, 0, i); | |
5321 | rtx unspec; | |
5322 | int maskval; | |
5323 | ||
5324 | if (GET_CODE (exp) != SET | |
5325 | || GET_CODE (SET_DEST (exp)) != REG | |
5326 | || GET_MODE (SET_DEST (exp)) != CCmode | |
5327 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
5328 | return 0; | |
5329 | unspec = SET_SRC (exp); | |
5330 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
5331 | |
5332 | if (GET_CODE (unspec) != UNSPEC | |
5333 | || XINT (unspec, 1) != 20 | |
5334 | || XVECLEN (unspec, 0) != 2 | |
5335 | || XVECEXP (unspec, 0, 0) != src_reg | |
5336 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
5337 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
5338 | return 0; | |
5339 | } | |
e35b9579 | 5340 | return 1; |
9ebbca7d GK |
5341 | } |
5342 | ||
a4f6c312 | 5343 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
5344 | |
5345 | int | |
5346 | lmw_operation (op, mode) | |
5347 | rtx op; | |
5348 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5349 | { | |
5350 | int count = XVECLEN (op, 0); | |
e2c953b6 | 5351 | unsigned int dest_regno; |
9ebbca7d | 5352 | rtx src_addr; |
e2c953b6 | 5353 | unsigned int base_regno; |
9ebbca7d GK |
5354 | HOST_WIDE_INT offset; |
5355 | int i; | |
5356 | ||
5357 | /* Perform a quick check so we don't blow up below. */ | |
5358 | if (count <= 1 | |
5359 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5360 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
5361 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
5362 | return 0; | |
5363 | ||
5364 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
5365 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
5366 | ||
5367 | if (dest_regno > 31 | |
e2c953b6 | 5368 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
5369 | return 0; |
5370 | ||
258bfae2 | 5371 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
5372 | { |
5373 | offset = 0; | |
5374 | base_regno = REGNO (src_addr); | |
5375 | if (base_regno == 0) | |
5376 | return 0; | |
5377 | } | |
258bfae2 | 5378 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
5379 | { |
5380 | offset = INTVAL (XEXP (src_addr, 1)); | |
5381 | base_regno = REGNO (XEXP (src_addr, 0)); | |
5382 | } | |
5383 | else | |
5384 | return 0; | |
5385 | ||
5386 | for (i = 0; i < count; i++) | |
5387 | { | |
5388 | rtx elt = XVECEXP (op, 0, i); | |
5389 | rtx newaddr; | |
5390 | rtx addr_reg; | |
5391 | HOST_WIDE_INT newoffset; | |
5392 | ||
5393 | if (GET_CODE (elt) != SET | |
5394 | || GET_CODE (SET_DEST (elt)) != REG | |
5395 | || GET_MODE (SET_DEST (elt)) != SImode | |
5396 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
5397 | || GET_CODE (SET_SRC (elt)) != MEM | |
5398 | || GET_MODE (SET_SRC (elt)) != SImode) | |
5399 | return 0; | |
5400 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 5401 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
5402 | { |
5403 | newoffset = 0; | |
5404 | addr_reg = newaddr; | |
5405 | } | |
258bfae2 | 5406 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
5407 | { |
5408 | addr_reg = XEXP (newaddr, 0); | |
5409 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
5410 | } | |
5411 | else | |
5412 | return 0; | |
5413 | if (REGNO (addr_reg) != base_regno | |
5414 | || newoffset != offset + 4 * i) | |
5415 | return 0; | |
5416 | } | |
5417 | ||
5418 | return 1; | |
5419 | } | |
5420 | ||
a4f6c312 | 5421 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
5422 | |
5423 | int | |
5424 | stmw_operation (op, mode) | |
5425 | rtx op; | |
5426 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5427 | { | |
5428 | int count = XVECLEN (op, 0); | |
e2c953b6 | 5429 | unsigned int src_regno; |
9ebbca7d | 5430 | rtx dest_addr; |
e2c953b6 | 5431 | unsigned int base_regno; |
9ebbca7d GK |
5432 | HOST_WIDE_INT offset; |
5433 | int i; | |
5434 | ||
5435 | /* Perform a quick check so we don't blow up below. */ | |
5436 | if (count <= 1 | |
5437 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5438 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
5439 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
5440 | return 0; | |
5441 | ||
5442 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
5443 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
5444 | ||
5445 | if (src_regno > 31 | |
e2c953b6 | 5446 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
5447 | return 0; |
5448 | ||
258bfae2 | 5449 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
5450 | { |
5451 | offset = 0; | |
5452 | base_regno = REGNO (dest_addr); | |
5453 | if (base_regno == 0) | |
5454 | return 0; | |
5455 | } | |
258bfae2 | 5456 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
5457 | { |
5458 | offset = INTVAL (XEXP (dest_addr, 1)); | |
5459 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
5460 | } | |
5461 | else | |
5462 | return 0; | |
5463 | ||
5464 | for (i = 0; i < count; i++) | |
5465 | { | |
5466 | rtx elt = XVECEXP (op, 0, i); | |
5467 | rtx newaddr; | |
5468 | rtx addr_reg; | |
5469 | HOST_WIDE_INT newoffset; | |
5470 | ||
5471 | if (GET_CODE (elt) != SET | |
5472 | || GET_CODE (SET_SRC (elt)) != REG | |
5473 | || GET_MODE (SET_SRC (elt)) != SImode | |
5474 | || REGNO (SET_SRC (elt)) != src_regno + i | |
5475 | || GET_CODE (SET_DEST (elt)) != MEM | |
5476 | || GET_MODE (SET_DEST (elt)) != SImode) | |
5477 | return 0; | |
5478 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 5479 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
5480 | { |
5481 | newoffset = 0; | |
5482 | addr_reg = newaddr; | |
5483 | } | |
258bfae2 | 5484 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
5485 | { |
5486 | addr_reg = XEXP (newaddr, 0); | |
5487 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
5488 | } | |
5489 | else | |
5490 | return 0; | |
5491 | if (REGNO (addr_reg) != base_regno | |
5492 | || newoffset != offset + 4 * i) | |
5493 | return 0; | |
5494 | } | |
5495 | ||
5496 | return 1; | |
5497 | } | |
9878760c | 5498 | \f |
a4f6c312 SS |
5499 | /* A validation routine: say whether CODE, a condition code, and MODE |
5500 | match. The other alternatives either don't make sense or should | |
5501 | never be generated. */ | |
39a10a29 | 5502 | |
39a10a29 GK |
5503 | static void |
5504 | validate_condition_mode (code, mode) | |
5505 | enum rtx_code code; | |
5506 | enum machine_mode mode; | |
5507 | { | |
5508 | if (GET_RTX_CLASS (code) != '<' | |
5509 | || GET_MODE_CLASS (mode) != MODE_CC) | |
5510 | abort (); | |
5511 | ||
5512 | /* These don't make sense. */ | |
5513 | if ((code == GT || code == LT || code == GE || code == LE) | |
5514 | && mode == CCUNSmode) | |
5515 | abort (); | |
5516 | ||
5517 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
5518 | && mode != CCUNSmode) | |
5519 | abort (); | |
5520 | ||
5521 | if (mode != CCFPmode | |
5522 | && (code == ORDERED || code == UNORDERED | |
5523 | || code == UNEQ || code == LTGT | |
5524 | || code == UNGT || code == UNLT | |
5525 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 5526 | abort (); |
39a10a29 | 5527 | |
de6c5979 BL |
5528 | /* These should never be generated except for |
5529 | flag_unsafe_math_optimizations. */ | |
39a10a29 | 5530 | if (mode == CCFPmode |
de6c5979 | 5531 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
5532 | && (code == LE || code == GE |
5533 | || code == UNEQ || code == LTGT | |
5534 | || code == UNGT || code == UNLT)) | |
5535 | abort (); | |
5536 | ||
5537 | /* These are invalid; the information is not there. */ | |
5538 | if (mode == CCEQmode | |
5539 | && code != EQ && code != NE) | |
5540 | abort (); | |
5541 | } | |
5542 | ||
9878760c RK |
5543 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
5544 | We only check the opcode against the mode of the CC value here. */ | |
5545 | ||
5546 | int | |
5547 | branch_comparison_operator (op, mode) | |
592696dd | 5548 | rtx op; |
296b8152 | 5549 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
5550 | { |
5551 | enum rtx_code code = GET_CODE (op); | |
5552 | enum machine_mode cc_mode; | |
5553 | ||
5554 | if (GET_RTX_CLASS (code) != '<') | |
5555 | return 0; | |
5556 | ||
5557 | cc_mode = GET_MODE (XEXP (op, 0)); | |
5558 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
5559 | return 0; | |
5560 | ||
39a10a29 | 5561 | validate_condition_mode (code, cc_mode); |
9878760c | 5562 | |
39a10a29 GK |
5563 | return 1; |
5564 | } | |
5565 | ||
5566 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
5567 | insn and which is true if the corresponding bit in the CC register | |
5568 | is set. */ | |
5569 | ||
5570 | int | |
5571 | branch_positive_comparison_operator (op, mode) | |
592696dd | 5572 | rtx op; |
39a10a29 GK |
5573 | enum machine_mode mode; |
5574 | { | |
5575 | enum rtx_code code; | |
5576 | ||
5577 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
5578 | return 0; |
5579 | ||
39a10a29 GK |
5580 | code = GET_CODE (op); |
5581 | return (code == EQ || code == LT || code == GT | |
5582 | || code == LTU || code == GTU | |
5583 | || code == UNORDERED); | |
9878760c RK |
5584 | } |
5585 | ||
5586 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
5587 | We check the opcode against the mode of the CC value and disallow EQ or | |
5588 | NE comparisons for integers. */ | |
5589 | ||
5590 | int | |
5591 | scc_comparison_operator (op, mode) | |
592696dd | 5592 | rtx op; |
9878760c RK |
5593 | enum machine_mode mode; |
5594 | { | |
5595 | enum rtx_code code = GET_CODE (op); | |
5596 | enum machine_mode cc_mode; | |
5597 | ||
5598 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
5599 | return 0; | |
5600 | ||
5601 | if (GET_RTX_CLASS (code) != '<') | |
5602 | return 0; | |
5603 | ||
5604 | cc_mode = GET_MODE (XEXP (op, 0)); | |
5605 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
5606 | return 0; | |
5607 | ||
39a10a29 | 5608 | validate_condition_mode (code, cc_mode); |
9878760c | 5609 | |
39a10a29 | 5610 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
5611 | return 0; |
5612 | ||
9878760c RK |
5613 | return 1; |
5614 | } | |
e0cd0770 JC |
5615 | |
5616 | int | |
5617 | trap_comparison_operator (op, mode) | |
5618 | rtx op; | |
5619 | enum machine_mode mode; | |
5620 | { | |
5621 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
5622 | return 0; | |
39a10a29 | 5623 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 5624 | } |
dfbdccdb GK |
5625 | |
5626 | int | |
5627 | boolean_operator (op, mode) | |
5628 | rtx op; | |
5629 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5630 | { | |
5631 | enum rtx_code code = GET_CODE (op); | |
5632 | return (code == AND || code == IOR || code == XOR); | |
5633 | } | |
1d328b19 GK |
5634 | |
5635 | int | |
5636 | boolean_or_operator (op, mode) | |
5637 | rtx op; | |
5638 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5639 | { | |
5640 | enum rtx_code code = GET_CODE (op); | |
5641 | return (code == IOR || code == XOR); | |
5642 | } | |
50a0b056 GK |
5643 | |
5644 | int | |
5645 | min_max_operator (op, mode) | |
5646 | rtx op; | |
5647 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5648 | { | |
5649 | enum rtx_code code = GET_CODE (op); | |
5650 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
5651 | } | |
9878760c RK |
5652 | \f |
5653 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
5654 | mask required to convert the result of a rotate insn into a shift | |
5655 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
5656 | ||
5657 | int | |
5658 | includes_lshift_p (shiftop, andop) | |
592696dd SS |
5659 | rtx shiftop; |
5660 | rtx andop; | |
9878760c | 5661 | { |
e2c953b6 DE |
5662 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
5663 | ||
5664 | shift_mask <<= INTVAL (shiftop); | |
9878760c RK |
5665 | |
5666 | return (INTVAL (andop) & ~shift_mask) == 0; | |
5667 | } | |
5668 | ||
5669 | /* Similar, but for right shift. */ | |
5670 | ||
5671 | int | |
5672 | includes_rshift_p (shiftop, andop) | |
592696dd SS |
5673 | rtx shiftop; |
5674 | rtx andop; | |
9878760c | 5675 | { |
a7653a2c | 5676 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
5677 | |
5678 | shift_mask >>= INTVAL (shiftop); | |
5679 | ||
e2c953b6 DE |
5680 | return (INTVAL (andop) & ~shift_mask) == 0; |
5681 | } | |
5682 | ||
c5059423 AM |
5683 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
5684 | to perform a left shift. It must have exactly SHIFTOP least | |
5685 | signifigant 0's, then one or more 1's, then zero or more 0's. */ | |
e2c953b6 DE |
5686 | |
5687 | int | |
c5059423 | 5688 | includes_rldic_lshift_p (shiftop, andop) |
592696dd SS |
5689 | rtx shiftop; |
5690 | rtx andop; | |
e2c953b6 | 5691 | { |
c5059423 AM |
5692 | if (GET_CODE (andop) == CONST_INT) |
5693 | { | |
02071907 | 5694 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 5695 | |
c5059423 | 5696 | c = INTVAL (andop); |
02071907 | 5697 | if (c == 0 || c == ~0) |
c5059423 | 5698 | return 0; |
e2c953b6 | 5699 | |
02071907 | 5700 | shift_mask = ~0; |
c5059423 AM |
5701 | shift_mask <<= INTVAL (shiftop); |
5702 | ||
5703 | /* Find the least signifigant one bit. */ | |
5704 | lsb = c & -c; | |
5705 | ||
5706 | /* It must coincide with the LSB of the shift mask. */ | |
5707 | if (-lsb != shift_mask) | |
5708 | return 0; | |
e2c953b6 | 5709 | |
c5059423 AM |
5710 | /* Invert to look for the next transition (if any). */ |
5711 | c = ~c; | |
5712 | ||
5713 | /* Remove the low group of ones (originally low group of zeros). */ | |
5714 | c &= -lsb; | |
5715 | ||
5716 | /* Again find the lsb, and check we have all 1's above. */ | |
5717 | lsb = c & -c; | |
5718 | return c == -lsb; | |
5719 | } | |
5720 | else if (GET_CODE (andop) == CONST_DOUBLE | |
5721 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
5722 | { | |
02071907 AM |
5723 | HOST_WIDE_INT low, high, lsb; |
5724 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
5725 | |
5726 | low = CONST_DOUBLE_LOW (andop); | |
5727 | if (HOST_BITS_PER_WIDE_INT < 64) | |
5728 | high = CONST_DOUBLE_HIGH (andop); | |
5729 | ||
5730 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 5731 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
5732 | return 0; |
5733 | ||
5734 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
5735 | { | |
02071907 | 5736 | shift_mask_high = ~0; |
c5059423 AM |
5737 | if (INTVAL (shiftop) > 32) |
5738 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
5739 | ||
5740 | lsb = high & -high; | |
5741 | ||
5742 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
5743 | return 0; | |
5744 | ||
5745 | high = ~high; | |
5746 | high &= -lsb; | |
5747 | ||
5748 | lsb = high & -high; | |
5749 | return high == -lsb; | |
5750 | } | |
5751 | ||
02071907 | 5752 | shift_mask_low = ~0; |
c5059423 AM |
5753 | shift_mask_low <<= INTVAL (shiftop); |
5754 | ||
5755 | lsb = low & -low; | |
5756 | ||
5757 | if (-lsb != shift_mask_low) | |
5758 | return 0; | |
5759 | ||
5760 | if (HOST_BITS_PER_WIDE_INT < 64) | |
5761 | high = ~high; | |
5762 | low = ~low; | |
5763 | low &= -lsb; | |
5764 | ||
5765 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
5766 | { | |
5767 | lsb = high & -high; | |
5768 | return high == -lsb; | |
5769 | } | |
5770 | ||
5771 | lsb = low & -low; | |
5772 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
5773 | } | |
5774 | else | |
5775 | return 0; | |
5776 | } | |
e2c953b6 | 5777 | |
c5059423 AM |
5778 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
5779 | to perform a left shift. It must have SHIFTOP or more least | |
5780 | signifigant 0's, with the remainder of the word 1's. */ | |
e2c953b6 | 5781 | |
c5059423 AM |
5782 | int |
5783 | includes_rldicr_lshift_p (shiftop, andop) | |
592696dd SS |
5784 | rtx shiftop; |
5785 | rtx andop; | |
c5059423 | 5786 | { |
e2c953b6 | 5787 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 5788 | { |
02071907 | 5789 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 5790 | |
02071907 | 5791 | shift_mask = ~0; |
c5059423 AM |
5792 | shift_mask <<= INTVAL (shiftop); |
5793 | c = INTVAL (andop); | |
5794 | ||
5795 | /* Find the least signifigant one bit. */ | |
5796 | lsb = c & -c; | |
5797 | ||
5798 | /* It must be covered by the shift mask. | |
a4f6c312 | 5799 | This test also rejects c == 0. */ |
c5059423 AM |
5800 | if ((lsb & shift_mask) == 0) |
5801 | return 0; | |
5802 | ||
5803 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
5804 | return c == -lsb && lsb != 1; | |
5805 | } | |
5806 | else if (GET_CODE (andop) == CONST_DOUBLE | |
5807 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
5808 | { | |
02071907 | 5809 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
5810 | |
5811 | low = CONST_DOUBLE_LOW (andop); | |
5812 | ||
5813 | if (HOST_BITS_PER_WIDE_INT < 64) | |
5814 | { | |
02071907 | 5815 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
5816 | |
5817 | high = CONST_DOUBLE_HIGH (andop); | |
5818 | ||
5819 | if (low == 0) | |
5820 | { | |
02071907 | 5821 | shift_mask_high = ~0; |
c5059423 AM |
5822 | if (INTVAL (shiftop) > 32) |
5823 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
5824 | ||
5825 | lsb = high & -high; | |
5826 | ||
5827 | if ((lsb & shift_mask_high) == 0) | |
5828 | return 0; | |
5829 | ||
5830 | return high == -lsb; | |
5831 | } | |
5832 | if (high != ~0) | |
5833 | return 0; | |
5834 | } | |
5835 | ||
02071907 | 5836 | shift_mask_low = ~0; |
c5059423 AM |
5837 | shift_mask_low <<= INTVAL (shiftop); |
5838 | ||
5839 | lsb = low & -low; | |
5840 | ||
5841 | if ((lsb & shift_mask_low) == 0) | |
5842 | return 0; | |
5843 | ||
5844 | return low == -lsb && lsb != 1; | |
5845 | } | |
e2c953b6 | 5846 | else |
c5059423 | 5847 | return 0; |
9878760c | 5848 | } |
35068b43 RK |
5849 | |
5850 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
5851 | for lfq and stfq insns. | |
5852 | ||
5853 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
5854 | abort if we are passed pseudo registers. */ | |
5855 | ||
5856 | int | |
5857 | registers_ok_for_quad_peep (reg1, reg2) | |
5858 | rtx reg1, reg2; | |
5859 | { | |
5860 | /* We might have been passed a SUBREG. */ | |
5861 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
5862 | return 0; | |
5863 | ||
5864 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
5865 | } | |
5866 | ||
a4f6c312 SS |
5867 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
5868 | addr1 and addr2 must be in consecutive memory locations | |
5869 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
5870 | |
5871 | int | |
5872 | addrs_ok_for_quad_peep (addr1, addr2) | |
592696dd SS |
5873 | rtx addr1; |
5874 | rtx addr2; | |
35068b43 | 5875 | { |
e2c953b6 | 5876 | unsigned int reg1; |
35068b43 RK |
5877 | int offset1; |
5878 | ||
5879 | /* Extract an offset (if used) from the first addr. */ | |
5880 | if (GET_CODE (addr1) == PLUS) | |
5881 | { | |
5882 | /* If not a REG, return zero. */ | |
5883 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
5884 | return 0; | |
5885 | else | |
5886 | { | |
5887 | reg1 = REGNO (XEXP (addr1, 0)); | |
5888 | /* The offset must be constant! */ | |
5889 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
5890 | return 0; | |
5891 | offset1 = INTVAL (XEXP (addr1, 1)); | |
5892 | } | |
5893 | } | |
5894 | else if (GET_CODE (addr1) != REG) | |
5895 | return 0; | |
5896 | else | |
5897 | { | |
5898 | reg1 = REGNO (addr1); | |
5899 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
5900 | offset1 = 0; | |
5901 | } | |
5902 | ||
acad7ed3 | 5903 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
5904 | if (GET_CODE (addr2) != PLUS) |
5905 | return 0; | |
5906 | ||
5907 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
5908 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
5909 | return 0; | |
5910 | ||
5911 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
5912 | return 0; | |
5913 | ||
5914 | /* The offset for the second addr must be 8 more than the first addr. */ | |
5915 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
5916 | return 0; | |
5917 | ||
5918 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
5919 | instructions. */ | |
5920 | return 1; | |
5921 | } | |
9878760c RK |
5922 | \f |
5923 | /* Return the register class of a scratch register needed to copy IN into | |
5924 | or out of a register in CLASS in MODE. If it can be done directly, | |
5925 | NO_REGS is returned. */ | |
5926 | ||
5927 | enum reg_class | |
5928 | secondary_reload_class (class, mode, in) | |
5929 | enum reg_class class; | |
296b8152 | 5930 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
5931 | rtx in; |
5932 | { | |
5accd822 | 5933 | int regno; |
9878760c | 5934 | |
46fad5b7 DJ |
5935 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic)) |
5936 | { | |
5937 | /* We cannot copy a symbolic operand directly into anything | |
5938 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
5939 | register from BASE_REGS is needed as an intermediate | |
5940 | register. | |
5941 | ||
5942 | On Darwin, pic addresses require a load from memory, which | |
5943 | needs a base register. */ | |
5944 | if (class != BASE_REGS | |
5945 | && (GET_CODE (in) == SYMBOL_REF | |
5946 | || GET_CODE (in) == HIGH | |
5947 | || GET_CODE (in) == LABEL_REF | |
5948 | || GET_CODE (in) == CONST)) | |
5949 | return BASE_REGS; | |
5950 | } | |
e7b7998a | 5951 | |
5accd822 DE |
5952 | if (GET_CODE (in) == REG) |
5953 | { | |
5954 | regno = REGNO (in); | |
5955 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5956 | { | |
5957 | regno = true_regnum (in); | |
5958 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5959 | regno = -1; | |
5960 | } | |
5961 | } | |
5962 | else if (GET_CODE (in) == SUBREG) | |
5963 | { | |
5964 | regno = true_regnum (in); | |
5965 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5966 | regno = -1; | |
5967 | } | |
5968 | else | |
5969 | regno = -1; | |
5970 | ||
9878760c RK |
5971 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
5972 | into anything. */ | |
5973 | if (class == GENERAL_REGS || class == BASE_REGS | |
5974 | || (regno >= 0 && INT_REGNO_P (regno))) | |
5975 | return NO_REGS; | |
5976 | ||
5977 | /* Constants, memory, and FP registers can go into FP registers. */ | |
5978 | if ((regno == -1 || FP_REGNO_P (regno)) | |
5979 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
5980 | return NO_REGS; | |
5981 | ||
0ac081f6 AH |
5982 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
5983 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
5984 | && class == ALTIVEC_REGS) | |
5985 | return NO_REGS; | |
5986 | ||
9878760c RK |
5987 | /* We can copy among the CR registers. */ |
5988 | if ((class == CR_REGS || class == CR0_REGS) | |
5989 | && regno >= 0 && CR_REGNO_P (regno)) | |
5990 | return NO_REGS; | |
5991 | ||
5992 | /* Otherwise, we need GENERAL_REGS. */ | |
5993 | return GENERAL_REGS; | |
5994 | } | |
5995 | \f | |
5996 | /* Given a comparison operation, return the bit number in CCR to test. We | |
5997 | know this is a valid comparison. | |
5998 | ||
5999 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
6000 | used instead of %C, so the bits will be in different places. | |
6001 | ||
b4ac57ab | 6002 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
6003 | |
6004 | int | |
6005 | ccr_bit (op, scc_p) | |
592696dd | 6006 | rtx op; |
9878760c RK |
6007 | int scc_p; |
6008 | { | |
6009 | enum rtx_code code = GET_CODE (op); | |
6010 | enum machine_mode cc_mode; | |
6011 | int cc_regnum; | |
6012 | int base_bit; | |
9ebbca7d | 6013 | rtx reg; |
9878760c RK |
6014 | |
6015 | if (GET_RTX_CLASS (code) != '<') | |
6016 | return -1; | |
6017 | ||
9ebbca7d GK |
6018 | reg = XEXP (op, 0); |
6019 | ||
6020 | if (GET_CODE (reg) != REG | |
6021 | || ! CR_REGNO_P (REGNO (reg))) | |
6022 | abort (); | |
6023 | ||
6024 | cc_mode = GET_MODE (reg); | |
6025 | cc_regnum = REGNO (reg); | |
6026 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 6027 | |
39a10a29 | 6028 | validate_condition_mode (code, cc_mode); |
c5defebb | 6029 | |
9878760c RK |
6030 | switch (code) |
6031 | { | |
6032 | case NE: | |
6033 | return scc_p ? base_bit + 3 : base_bit + 2; | |
6034 | case EQ: | |
6035 | return base_bit + 2; | |
1c882ea4 | 6036 | case GT: case GTU: case UNLE: |
9878760c | 6037 | return base_bit + 1; |
1c882ea4 | 6038 | case LT: case LTU: case UNGE: |
9878760c | 6039 | return base_bit; |
1c882ea4 GK |
6040 | case ORDERED: case UNORDERED: |
6041 | return base_bit + 3; | |
9878760c RK |
6042 | |
6043 | case GE: case GEU: | |
39a10a29 | 6044 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
6045 | unordered position. So test that bit. For integer, this is ! LT |
6046 | unless this is an scc insn. */ | |
39a10a29 | 6047 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
6048 | |
6049 | case LE: case LEU: | |
39a10a29 | 6050 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 6051 | |
9878760c RK |
6052 | default: |
6053 | abort (); | |
6054 | } | |
6055 | } | |
1ff7789b | 6056 | \f |
8d30c4ee | 6057 | /* Return the GOT register. */ |
1ff7789b MM |
6058 | |
6059 | struct rtx_def * | |
6060 | rs6000_got_register (value) | |
5f59ecb7 | 6061 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 6062 | { |
a4f6c312 SS |
6063 | /* The second flow pass currently (June 1999) can't update |
6064 | regs_ever_live without disturbing other parts of the compiler, so | |
6065 | update it here to make the prolog/epilogue code happy. */ | |
3cb999d8 | 6066 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 6067 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 6068 | |
8d30c4ee | 6069 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 6070 | |
1ff7789b MM |
6071 | return pic_offset_table_rtx; |
6072 | } | |
a7df97e6 | 6073 | \f |
71f123ca | 6074 | /* Functions to init, mark and free struct machine_function. |
a7df97e6 MM |
6075 | These will be called, via pointer variables, |
6076 | from push_function_context and pop_function_context. */ | |
6077 | ||
00dba523 NC |
6078 | static void |
6079 | rs6000_init_machine_status (p) | |
a7df97e6 MM |
6080 | struct function *p; |
6081 | { | |
71f123ca FS |
6082 | p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); |
6083 | } | |
a7df97e6 | 6084 | |
00dba523 NC |
6085 | static void |
6086 | rs6000_free_machine_status (p) | |
a7df97e6 MM |
6087 | struct function *p; |
6088 | { | |
00dba523 NC |
6089 | if (p->machine == NULL) |
6090 | return; | |
a7df97e6 | 6091 | |
00dba523 NC |
6092 | free (p->machine); |
6093 | p->machine = NULL; | |
a7df97e6 MM |
6094 | } |
6095 | ||
9878760c RK |
6096 | \f |
6097 | /* Print an operand. Recognize special options, documented below. */ | |
6098 | ||
38c1f2d7 | 6099 | #if TARGET_ELF |
d9407988 | 6100 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 6101 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
6102 | #else |
6103 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 6104 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
6105 | #endif |
6106 | ||
9878760c RK |
6107 | void |
6108 | print_operand (file, x, code) | |
6109 | FILE *file; | |
6110 | rtx x; | |
9ebbca7d | 6111 | int code; |
9878760c RK |
6112 | { |
6113 | int i; | |
a260abc9 | 6114 | HOST_WIDE_INT val; |
9878760c RK |
6115 | |
6116 | /* These macros test for integers and extract the low-order bits. */ | |
6117 | #define INT_P(X) \ | |
6118 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
6119 | && GET_MODE (X) == VOIDmode) | |
6120 | ||
6121 | #define INT_LOWPART(X) \ | |
6122 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
6123 | ||
6124 | switch (code) | |
6125 | { | |
a8b3aeda | 6126 | case '.': |
a85d226b RK |
6127 | /* Write out an instruction after the call which may be replaced |
6128 | with glue code by the loader. This depends on the AIX version. */ | |
6129 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
6130 | return; |
6131 | ||
81eace42 GK |
6132 | /* %a is output_address. */ |
6133 | ||
9854d9ed RK |
6134 | case 'A': |
6135 | /* If X is a constant integer whose low-order 5 bits are zero, | |
6136 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 6137 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 6138 | writes a trash instruction. */ |
9854d9ed | 6139 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 6140 | putc ('l', file); |
9854d9ed | 6141 | else |
76229ac8 | 6142 | putc ('r', file); |
9854d9ed RK |
6143 | return; |
6144 | ||
6145 | case 'b': | |
e2c953b6 DE |
6146 | /* If constant, low-order 16 bits of constant, unsigned. |
6147 | Otherwise, write normally. */ | |
6148 | if (INT_P (x)) | |
6149 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
6150 | else | |
6151 | print_operand (file, x, 0); | |
cad12a8d RK |
6152 | return; |
6153 | ||
a260abc9 DE |
6154 | case 'B': |
6155 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
6156 | for 64-bit mask direction. */ | |
296b8152 | 6157 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 6158 | return; |
a260abc9 | 6159 | |
81eace42 GK |
6160 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
6161 | output_operand. */ | |
6162 | ||
9854d9ed | 6163 | case 'D': |
39a10a29 GK |
6164 | /* There used to be a comment for 'C' reading "This is an |
6165 | optional cror needed for certain floating-point | |
6166 | comparisons. Otherwise write nothing." */ | |
6167 | ||
9854d9ed RK |
6168 | /* Similar, except that this is for an scc, so we must be able to |
6169 | encode the test in a single bit that is one. We do the above | |
6170 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
6171 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
6172 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
6173 | { | |
9ebbca7d | 6174 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
6175 | |
6176 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
6177 | base_bit + 2, | |
6178 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
6179 | } | |
6180 | ||
6181 | else if (GET_CODE (x) == NE) | |
6182 | { | |
9ebbca7d | 6183 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
6184 | |
6185 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
6186 | base_bit + 2, base_bit + 2); | |
6187 | } | |
6188 | return; | |
6189 | ||
6190 | case 'E': | |
39a10a29 | 6191 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
6192 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
6193 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 6194 | else |
39a10a29 | 6195 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 6196 | return; |
9854d9ed RK |
6197 | |
6198 | case 'f': | |
6199 | /* X is a CR register. Print the shift count needed to move it | |
6200 | to the high-order four bits. */ | |
6201 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
6202 | output_operand_lossage ("invalid %%f value"); | |
6203 | else | |
9ebbca7d | 6204 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
6205 | return; |
6206 | ||
6207 | case 'F': | |
6208 | /* Similar, but print the count for the rotate in the opposite | |
6209 | direction. */ | |
6210 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
6211 | output_operand_lossage ("invalid %%F value"); | |
6212 | else | |
9ebbca7d | 6213 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
6214 | return; |
6215 | ||
6216 | case 'G': | |
6217 | /* X is a constant integer. If it is negative, print "m", | |
6218 | otherwise print "z". This is to make a aze or ame insn. */ | |
6219 | if (GET_CODE (x) != CONST_INT) | |
6220 | output_operand_lossage ("invalid %%G value"); | |
6221 | else if (INTVAL (x) >= 0) | |
76229ac8 | 6222 | putc ('z', file); |
9854d9ed | 6223 | else |
76229ac8 | 6224 | putc ('m', file); |
9854d9ed | 6225 | return; |
e2c953b6 | 6226 | |
9878760c | 6227 | case 'h': |
a4f6c312 SS |
6228 | /* If constant, output low-order five bits. Otherwise, write |
6229 | normally. */ | |
9878760c | 6230 | if (INT_P (x)) |
5f59ecb7 | 6231 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
6232 | else |
6233 | print_operand (file, x, 0); | |
6234 | return; | |
6235 | ||
64305719 | 6236 | case 'H': |
a4f6c312 SS |
6237 | /* If constant, output low-order six bits. Otherwise, write |
6238 | normally. */ | |
64305719 | 6239 | if (INT_P (x)) |
5f59ecb7 | 6240 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
6241 | else |
6242 | print_operand (file, x, 0); | |
6243 | return; | |
6244 | ||
9854d9ed RK |
6245 | case 'I': |
6246 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 6247 | if (INT_P (x)) |
76229ac8 | 6248 | putc ('i', file); |
9878760c RK |
6249 | return; |
6250 | ||
9854d9ed RK |
6251 | case 'j': |
6252 | /* Write the bit number in CCR for jump. */ | |
6253 | i = ccr_bit (x, 0); | |
6254 | if (i == -1) | |
6255 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 6256 | else |
9854d9ed | 6257 | fprintf (file, "%d", i); |
9878760c RK |
6258 | return; |
6259 | ||
9854d9ed RK |
6260 | case 'J': |
6261 | /* Similar, but add one for shift count in rlinm for scc and pass | |
6262 | scc flag to `ccr_bit'. */ | |
6263 | i = ccr_bit (x, 1); | |
6264 | if (i == -1) | |
6265 | output_operand_lossage ("invalid %%J code"); | |
6266 | else | |
a0466a68 RK |
6267 | /* If we want bit 31, write a shift count of zero, not 32. */ |
6268 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
6269 | return; |
6270 | ||
9854d9ed RK |
6271 | case 'k': |
6272 | /* X must be a constant. Write the 1's complement of the | |
6273 | constant. */ | |
9878760c | 6274 | if (! INT_P (x)) |
9854d9ed | 6275 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
6276 | else |
6277 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
6278 | return; |
6279 | ||
81eace42 | 6280 | case 'K': |
9ebbca7d GK |
6281 | /* X must be a symbolic constant on ELF. Write an |
6282 | expression suitable for an 'addi' that adds in the low 16 | |
6283 | bits of the MEM. */ | |
6284 | if (GET_CODE (x) != CONST) | |
6285 | { | |
6286 | print_operand_address (file, x); | |
6287 | fputs ("@l", file); | |
6288 | } | |
6289 | else | |
6290 | { | |
6291 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
6292 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
6293 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
6294 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 6295 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
6296 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
6297 | fputs ("@l", file); | |
6298 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
6299 | } | |
81eace42 GK |
6300 | return; |
6301 | ||
6302 | /* %l is output_asm_label. */ | |
9ebbca7d | 6303 | |
9854d9ed RK |
6304 | case 'L': |
6305 | /* Write second word of DImode or DFmode reference. Works on register | |
6306 | or non-indexed memory only. */ | |
6307 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 6308 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
6309 | else if (GET_CODE (x) == MEM) |
6310 | { | |
6311 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 6312 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
6313 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
6314 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
6315 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
6316 | UNITS_PER_WORD)); | |
9854d9ed | 6317 | else |
d7624dc0 RK |
6318 | output_address (XEXP (adjust_address_nv (x, SImode, |
6319 | UNITS_PER_WORD), | |
6320 | 0)); | |
ed8908e7 | 6321 | |
ba5e43aa | 6322 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6323 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6324 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 6325 | } |
9878760c | 6326 | return; |
9854d9ed | 6327 | |
9878760c RK |
6328 | case 'm': |
6329 | /* MB value for a mask operand. */ | |
6330 | if (! mask_operand (x, VOIDmode)) | |
6331 | output_operand_lossage ("invalid %%m value"); | |
6332 | ||
6333 | val = INT_LOWPART (x); | |
6334 | ||
6335 | /* If the high bit is set and the low bit is not, the value is zero. | |
6336 | If the high bit is zero, the value is the first 1 bit we find from | |
6337 | the left. */ | |
0858c623 | 6338 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 6339 | { |
19d2d16f | 6340 | putc ('0', file); |
9878760c RK |
6341 | return; |
6342 | } | |
0858c623 | 6343 | else if ((val & 0x80000000) == 0) |
9878760c RK |
6344 | { |
6345 | for (i = 1; i < 32; i++) | |
0858c623 | 6346 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
6347 | break; |
6348 | fprintf (file, "%d", i); | |
6349 | return; | |
6350 | } | |
6351 | ||
6352 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
6353 | number plus 1. We know the low-order bit is one. */ | |
6354 | for (i = 0; i < 32; i++) | |
6355 | if (((val >>= 1) & 1) == 0) | |
6356 | break; | |
6357 | ||
a260abc9 | 6358 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
6359 | we want 31 - i. */ |
6360 | fprintf (file, "%d", 31 - i); | |
6361 | return; | |
6362 | ||
6363 | case 'M': | |
6364 | /* ME value for a mask operand. */ | |
6365 | if (! mask_operand (x, VOIDmode)) | |
a260abc9 | 6366 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
6367 | |
6368 | val = INT_LOWPART (x); | |
6369 | ||
6370 | /* If the low bit is set and the high bit is not, the value is 31. | |
6371 | If the low bit is zero, the value is the first 1 bit we find from | |
6372 | the right. */ | |
0858c623 | 6373 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 6374 | { |
76229ac8 | 6375 | fputs ("31", file); |
9878760c RK |
6376 | return; |
6377 | } | |
6378 | else if ((val & 1) == 0) | |
6379 | { | |
6380 | for (i = 0; i < 32; i++) | |
6381 | if ((val >>= 1) & 1) | |
6382 | break; | |
6383 | ||
a260abc9 | 6384 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
6385 | 30, so we need 30 - i. */ |
6386 | fprintf (file, "%d", 30 - i); | |
6387 | return; | |
6388 | } | |
6389 | ||
6390 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
6391 | number minus 1. We know the high-order bit is one. */ | |
6392 | for (i = 0; i < 32; i++) | |
0858c623 | 6393 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
6394 | break; |
6395 | ||
6396 | fprintf (file, "%d", i); | |
6397 | return; | |
6398 | ||
81eace42 GK |
6399 | /* %n outputs the negative of its operand. */ |
6400 | ||
9878760c RK |
6401 | case 'N': |
6402 | /* Write the number of elements in the vector times 4. */ | |
6403 | if (GET_CODE (x) != PARALLEL) | |
6404 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
6405 | else |
6406 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
6407 | return; |
6408 | ||
6409 | case 'O': | |
6410 | /* Similar, but subtract 1 first. */ | |
6411 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 6412 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
6413 | else |
6414 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
6415 | return; |
6416 | ||
9854d9ed RK |
6417 | case 'p': |
6418 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
6419 | if (! INT_P (x) | |
2bfcf297 | 6420 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
6421 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
6422 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
6423 | else |
6424 | fprintf (file, "%d", i); | |
9854d9ed RK |
6425 | return; |
6426 | ||
9878760c RK |
6427 | case 'P': |
6428 | /* The operand must be an indirect memory reference. The result | |
a4f6c312 | 6429 | is the register number. */ |
9878760c RK |
6430 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
6431 | || REGNO (XEXP (x, 0)) >= 32) | |
6432 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
6433 | else |
6434 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
6435 | return; |
6436 | ||
dfbdccdb GK |
6437 | case 'q': |
6438 | /* This outputs the logical code corresponding to a boolean | |
6439 | expression. The expression may have one or both operands | |
39a10a29 GK |
6440 | negated (if one, only the first one). For condition register |
6441 | logical operations, it will also treat the negated | |
6442 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 6443 | { |
63bc1d05 | 6444 | const char *const *t = 0; |
dfbdccdb GK |
6445 | const char *s; |
6446 | enum rtx_code code = GET_CODE (x); | |
6447 | static const char * const tbl[3][3] = { | |
6448 | { "and", "andc", "nor" }, | |
6449 | { "or", "orc", "nand" }, | |
6450 | { "xor", "eqv", "xor" } }; | |
6451 | ||
6452 | if (code == AND) | |
6453 | t = tbl[0]; | |
6454 | else if (code == IOR) | |
6455 | t = tbl[1]; | |
6456 | else if (code == XOR) | |
6457 | t = tbl[2]; | |
6458 | else | |
6459 | output_operand_lossage ("invalid %%q value"); | |
6460 | ||
6461 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
6462 | s = t[0]; | |
6463 | else | |
6464 | { | |
6465 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
6466 | s = t[2]; | |
6467 | else | |
6468 | s = t[1]; | |
6469 | } | |
6470 | ||
6471 | fputs (s, file); | |
6472 | } | |
6473 | return; | |
6474 | ||
9854d9ed RK |
6475 | case 'R': |
6476 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
6477 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
6478 | output_operand_lossage ("invalid %%R value"); | |
6479 | else | |
9ebbca7d | 6480 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 6481 | return; |
9854d9ed RK |
6482 | |
6483 | case 's': | |
6484 | /* Low 5 bits of 32 - value */ | |
6485 | if (! INT_P (x)) | |
6486 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
6487 | else |
6488 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 6489 | return; |
9854d9ed | 6490 | |
a260abc9 DE |
6491 | case 'S': |
6492 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
6493 | CONST_INT 32-bit mask is considered sign-extended so any | |
6494 | transition must occur within the CONST_INT, not on the boundary. */ | |
6495 | if (! mask64_operand (x, VOIDmode)) | |
6496 | output_operand_lossage ("invalid %%S value"); | |
6497 | ||
6498 | val = INT_LOWPART (x); | |
6499 | ||
6500 | if (val & 1) /* Clear Left */ | |
6501 | { | |
a238cd8b DE |
6502 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
6503 | if (!((val >>= 1) & 1)) | |
6504 | break; | |
a260abc9 | 6505 | |
a238cd8b DE |
6506 | #if HOST_BITS_PER_WIDE_INT == 32 |
6507 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
6508 | { | |
6509 | val = CONST_DOUBLE_HIGH (x); | |
6510 | ||
6511 | if (val == 0) | |
6512 | --i; | |
6513 | else | |
6514 | for (i = 32; i < 64; i++) | |
6515 | if (!((val >>= 1) & 1)) | |
6516 | break; | |
6517 | } | |
a260abc9 | 6518 | #endif |
a238cd8b DE |
6519 | /* i = index of last set bit from right |
6520 | mask begins at 63 - i from left */ | |
6521 | if (i > 63) | |
6522 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 6523 | |
a260abc9 DE |
6524 | fprintf (file, "%d", 63 - i); |
6525 | return; | |
6526 | } | |
6527 | else /* Clear Right */ | |
6528 | { | |
a238cd8b DE |
6529 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
6530 | if ((val >>= 1) & 1) | |
6531 | break; | |
a260abc9 | 6532 | |
a238cd8b | 6533 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
6534 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
6535 | { | |
a238cd8b | 6536 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 6537 | |
a238cd8b | 6538 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 6539 | --i; |
a260abc9 | 6540 | else |
a238cd8b DE |
6541 | for (i = 32; i < 64; i++) |
6542 | if ((val >>= 1) & 1) | |
a260abc9 DE |
6543 | break; |
6544 | } | |
6545 | #endif | |
a238cd8b DE |
6546 | /* i = index of last clear bit from right |
6547 | mask ends at 62 - i from left */ | |
6548 | if (i > 62) | |
6549 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 6550 | |
a238cd8b | 6551 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
6552 | return; |
6553 | } | |
6554 | ||
cccf3bdc DE |
6555 | case 'T': |
6556 | /* Print the symbolic name of a branch target register. */ | |
6557 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
6558 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
6559 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 6560 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
6561 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
6562 | else | |
6563 | fputs ("ctr", file); | |
6564 | return; | |
6565 | ||
9854d9ed | 6566 | case 'u': |
802a0058 | 6567 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
6568 | if (! INT_P (x)) |
6569 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
6570 | else |
6571 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
6572 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
6573 | return; |
6574 | ||
802a0058 MM |
6575 | case 'v': |
6576 | /* High-order 16 bits of constant for use in signed operand. */ | |
6577 | if (! INT_P (x)) | |
6578 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 6579 | else |
134c32f6 DE |
6580 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
6581 | (INT_LOWPART (x) >> 16) & 0xffff); | |
6582 | return; | |
802a0058 | 6583 | |
9854d9ed RK |
6584 | case 'U': |
6585 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
6586 | if (GET_CODE (x) == MEM | |
6587 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
6588 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 6589 | putc ('u', file); |
9854d9ed | 6590 | return; |
9878760c | 6591 | |
e0cd0770 JC |
6592 | case 'V': |
6593 | /* Print the trap code for this operand. */ | |
6594 | switch (GET_CODE (x)) | |
6595 | { | |
6596 | case EQ: | |
6597 | fputs ("eq", file); /* 4 */ | |
6598 | break; | |
6599 | case NE: | |
6600 | fputs ("ne", file); /* 24 */ | |
6601 | break; | |
6602 | case LT: | |
6603 | fputs ("lt", file); /* 16 */ | |
6604 | break; | |
6605 | case LE: | |
6606 | fputs ("le", file); /* 20 */ | |
6607 | break; | |
6608 | case GT: | |
6609 | fputs ("gt", file); /* 8 */ | |
6610 | break; | |
6611 | case GE: | |
6612 | fputs ("ge", file); /* 12 */ | |
6613 | break; | |
6614 | case LTU: | |
6615 | fputs ("llt", file); /* 2 */ | |
6616 | break; | |
6617 | case LEU: | |
6618 | fputs ("lle", file); /* 6 */ | |
6619 | break; | |
6620 | case GTU: | |
6621 | fputs ("lgt", file); /* 1 */ | |
6622 | break; | |
6623 | case GEU: | |
6624 | fputs ("lge", file); /* 5 */ | |
6625 | break; | |
6626 | default: | |
6627 | abort (); | |
6628 | } | |
6629 | break; | |
6630 | ||
9854d9ed RK |
6631 | case 'w': |
6632 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
6633 | normally. */ | |
6634 | if (INT_P (x)) | |
5f59ecb7 DE |
6635 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
6636 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
6637 | else |
6638 | print_operand (file, x, 0); | |
9878760c RK |
6639 | return; |
6640 | ||
9854d9ed | 6641 | case 'W': |
e2c953b6 | 6642 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
6643 | val = (GET_CODE (x) == CONST_INT |
6644 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
6645 | ||
6646 | if (val < 0) | |
6647 | i = -1; | |
9854d9ed | 6648 | else |
e2c953b6 DE |
6649 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
6650 | if ((val <<= 1) < 0) | |
6651 | break; | |
6652 | ||
6653 | #if HOST_BITS_PER_WIDE_INT == 32 | |
6654 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
6655 | i += 32; /* zero-extend high-part was all 0's */ | |
6656 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
6657 | { | |
6658 | val = CONST_DOUBLE_LOW (x); | |
6659 | ||
6660 | if (val == 0) | |
a4f6c312 | 6661 | abort (); |
e2c953b6 DE |
6662 | else if (val < 0) |
6663 | --i; | |
6664 | else | |
6665 | for ( ; i < 64; i++) | |
6666 | if ((val <<= 1) < 0) | |
6667 | break; | |
6668 | } | |
6669 | #endif | |
6670 | ||
6671 | fprintf (file, "%d", i + 1); | |
9854d9ed | 6672 | return; |
9878760c | 6673 | |
9854d9ed RK |
6674 | case 'X': |
6675 | if (GET_CODE (x) == MEM | |
258bfae2 | 6676 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 6677 | putc ('x', file); |
9854d9ed | 6678 | return; |
9878760c | 6679 | |
9854d9ed RK |
6680 | case 'Y': |
6681 | /* Like 'L', for third word of TImode */ | |
6682 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 6683 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 6684 | else if (GET_CODE (x) == MEM) |
9878760c | 6685 | { |
9854d9ed RK |
6686 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
6687 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 6688 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 6689 | else |
d7624dc0 | 6690 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 6691 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6692 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6693 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
6694 | } |
6695 | return; | |
9854d9ed | 6696 | |
9878760c | 6697 | case 'z': |
b4ac57ab RS |
6698 | /* X is a SYMBOL_REF. Write out the name preceded by a |
6699 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
6700 | names. If we are configured for System V (or the embedded ABI) on |
6701 | the PowerPC, do not emit the period, since those systems do not use | |
6702 | TOCs and the like. */ | |
9878760c RK |
6703 | if (GET_CODE (x) != SYMBOL_REF) |
6704 | abort (); | |
6705 | ||
b6c9286a MM |
6706 | if (XSTR (x, 0)[0] != '.') |
6707 | { | |
6708 | switch (DEFAULT_ABI) | |
6709 | { | |
6710 | default: | |
6711 | abort (); | |
6712 | ||
6713 | case ABI_AIX: | |
6714 | putc ('.', file); | |
6715 | break; | |
6716 | ||
6717 | case ABI_V4: | |
6718 | case ABI_AIX_NODESC: | |
ee890fe2 | 6719 | case ABI_DARWIN: |
b6c9286a | 6720 | break; |
b6c9286a MM |
6721 | } |
6722 | } | |
54ee9799 DE |
6723 | #if TARGET_AIX |
6724 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); | |
6725 | #else | |
9ebbca7d | 6726 | assemble_name (file, XSTR (x, 0)); |
54ee9799 | 6727 | #endif |
9878760c RK |
6728 | return; |
6729 | ||
9854d9ed RK |
6730 | case 'Z': |
6731 | /* Like 'L', for last word of TImode. */ | |
6732 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 6733 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
6734 | else if (GET_CODE (x) == MEM) |
6735 | { | |
6736 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
6737 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 6738 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 6739 | else |
d7624dc0 | 6740 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 6741 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6742 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6743 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 6744 | } |
5c23c401 | 6745 | return; |
0ac081f6 AH |
6746 | |
6747 | /* Print AltiVec memory operand. */ | |
6748 | case 'y': | |
6749 | { | |
6750 | rtx tmp; | |
6751 | ||
6752 | if (GET_CODE (x) != MEM) | |
6753 | abort (); | |
6754 | ||
6755 | tmp = XEXP (x, 0); | |
6756 | ||
6757 | if (GET_CODE (tmp) == REG) | |
c62f2db5 | 6758 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
6759 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
6760 | { | |
6761 | if (REGNO (XEXP (tmp, 0)) == 0) | |
6762 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
6763 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
6764 | else | |
6765 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
6766 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
6767 | } | |
6768 | else | |
6769 | abort (); | |
6770 | break; | |
6771 | } | |
9854d9ed | 6772 | |
9878760c RK |
6773 | case 0: |
6774 | if (GET_CODE (x) == REG) | |
6775 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
6776 | else if (GET_CODE (x) == MEM) | |
6777 | { | |
6778 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
6779 | know the width from the mode. */ | |
6780 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
6781 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
6782 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 6783 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
6784 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
6785 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 6786 | else |
a54d04b7 | 6787 | output_address (XEXP (x, 0)); |
9878760c RK |
6788 | } |
6789 | else | |
a54d04b7 | 6790 | output_addr_const (file, x); |
a85d226b | 6791 | return; |
9878760c RK |
6792 | |
6793 | default: | |
6794 | output_operand_lossage ("invalid %%xn code"); | |
6795 | } | |
6796 | } | |
6797 | \f | |
6798 | /* Print the address of an operand. */ | |
6799 | ||
6800 | void | |
6801 | print_operand_address (file, x) | |
6802 | FILE *file; | |
592696dd | 6803 | rtx x; |
9878760c RK |
6804 | { |
6805 | if (GET_CODE (x) == REG) | |
4697a36c | 6806 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
6807 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
6808 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
6809 | { |
6810 | output_addr_const (file, x); | |
ba5e43aa | 6811 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6812 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6813 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 6814 | else if (TARGET_TOC) |
a4f6c312 | 6815 | abort (); |
9878760c RK |
6816 | } |
6817 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
6818 | { | |
6819 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
6820 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
6821 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 6822 | else |
4697a36c MM |
6823 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
6824 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
6825 | } |
6826 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
6827 | { |
6828 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
6829 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
6830 | } | |
3cb999d8 DE |
6831 | #if TARGET_ELF |
6832 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
6833 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
6834 | { |
6835 | output_addr_const (file, XEXP (x, 1)); | |
6836 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
6837 | } | |
c859cda6 DJ |
6838 | #endif |
6839 | #if TARGET_MACHO | |
6840 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
6841 | && CONSTANT_P (XEXP (x, 1))) | |
6842 | { | |
6843 | fprintf (file, "lo16("); | |
6844 | output_addr_const (file, XEXP (x, 1)); | |
6845 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
6846 | } | |
3cb999d8 | 6847 | #endif |
9ebbca7d GK |
6848 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
6849 | { | |
2bfcf297 | 6850 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 6851 | { |
2bfcf297 DB |
6852 | rtx contains_minus = XEXP (x, 1); |
6853 | rtx minus, symref; | |
6854 | const char *name; | |
9ebbca7d GK |
6855 | |
6856 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 6857 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
6858 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
6859 | contains_minus = XEXP (contains_minus, 0); | |
6860 | ||
2bfcf297 DB |
6861 | minus = XEXP (contains_minus, 0); |
6862 | symref = XEXP (minus, 0); | |
6863 | XEXP (contains_minus, 0) = symref; | |
6864 | if (TARGET_ELF) | |
6865 | { | |
6866 | char *newname; | |
6867 | ||
6868 | name = XSTR (symref, 0); | |
6869 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
6870 | strcpy (newname, name); | |
6871 | strcat (newname, "@toc"); | |
6872 | XSTR (symref, 0) = newname; | |
6873 | } | |
6874 | output_addr_const (file, XEXP (x, 1)); | |
6875 | if (TARGET_ELF) | |
6876 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
6877 | XEXP (contains_minus, 0) = minus; |
6878 | } | |
6879 | else | |
6880 | output_addr_const (file, XEXP (x, 1)); | |
6881 | ||
6882 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
6883 | } | |
9878760c RK |
6884 | else |
6885 | abort (); | |
6886 | } | |
6887 | \f | |
301d03af RS |
6888 | /* Target hook for assembling integer objects. The powerpc version has |
6889 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP | |
6890 | is defined. It also needs to handle DI-mode objects on 64-bit | |
6891 | targets. */ | |
6892 | ||
6893 | static bool | |
6894 | rs6000_assemble_integer (x, size, aligned_p) | |
6895 | rtx x; | |
6896 | unsigned int size; | |
6897 | int aligned_p; | |
6898 | { | |
6899 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
6900 | /* Special handling for SI values. */ | |
6901 | if (size == 4 && aligned_p) | |
6902 | { | |
6903 | extern int in_toc_section PARAMS ((void)); | |
6904 | static int recurse = 0; | |
6905 | ||
6906 | /* For -mrelocatable, we mark all addresses that need to be fixed up | |
6907 | in the .fixup section. */ | |
6908 | if (TARGET_RELOCATABLE | |
6909 | && !in_toc_section () | |
6910 | && !in_text_section () | |
6911 | && !recurse | |
6912 | && GET_CODE (x) != CONST_INT | |
6913 | && GET_CODE (x) != CONST_DOUBLE | |
6914 | && CONSTANT_P (x)) | |
6915 | { | |
6916 | char buf[256]; | |
6917 | ||
6918 | recurse = 1; | |
6919 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
6920 | fixuplabelno++; | |
6921 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
6922 | fprintf (asm_out_file, "\t.long\t("); | |
6923 | output_addr_const (asm_out_file, x); | |
6924 | fprintf (asm_out_file, ")@fixup\n"); | |
6925 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
6926 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
6927 | fprintf (asm_out_file, "\t.long\t"); | |
6928 | assemble_name (asm_out_file, buf); | |
6929 | fprintf (asm_out_file, "\n\t.previous\n"); | |
6930 | recurse = 0; | |
6931 | return true; | |
6932 | } | |
6933 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
6934 | address into the address of the descriptor, not the function | |
6935 | itself. */ | |
6936 | else if (GET_CODE (x) == SYMBOL_REF | |
6937 | && XSTR (x, 0)[0] == '.' | |
6938 | && DEFAULT_ABI == ABI_AIX) | |
6939 | { | |
6940 | const char *name = XSTR (x, 0); | |
6941 | while (*name == '.') | |
6942 | name++; | |
6943 | ||
6944 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
6945 | return true; | |
6946 | } | |
6947 | } | |
6948 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
6949 | return default_assemble_integer (x, size, aligned_p); | |
6950 | } | |
6951 | \f | |
39a10a29 GK |
6952 | enum rtx_code |
6953 | rs6000_reverse_condition (mode, code) | |
6954 | enum machine_mode mode; | |
6955 | enum rtx_code code; | |
6956 | { | |
6957 | /* Reversal of FP compares takes care -- an ordered compare | |
6958 | becomes an unordered compare and vice versa. */ | |
6959 | if (mode == CCFPmode) | |
bab6226b | 6960 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 6961 | else |
bab6226b | 6962 | return reverse_condition (code); |
39a10a29 GK |
6963 | } |
6964 | ||
39a10a29 GK |
6965 | /* Generate a compare for CODE. Return a brand-new rtx that |
6966 | represents the result of the compare. */ | |
a4f6c312 | 6967 | |
39a10a29 GK |
6968 | static rtx |
6969 | rs6000_generate_compare (code) | |
6970 | enum rtx_code code; | |
6971 | { | |
6972 | enum machine_mode comp_mode; | |
6973 | rtx compare_result; | |
6974 | ||
6975 | if (rs6000_compare_fp_p) | |
6976 | comp_mode = CCFPmode; | |
6977 | else if (code == GTU || code == LTU | |
6978 | || code == GEU || code == LEU) | |
6979 | comp_mode = CCUNSmode; | |
6980 | else | |
6981 | comp_mode = CCmode; | |
6982 | ||
6983 | /* First, the compare. */ | |
6984 | compare_result = gen_reg_rtx (comp_mode); | |
6985 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
6986 | gen_rtx_COMPARE (comp_mode, | |
6987 | rs6000_compare_op0, | |
6988 | rs6000_compare_op1))); | |
6989 | ||
ca5adc63 | 6990 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 6991 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 6992 | if (rs6000_compare_fp_p |
de6c5979 | 6993 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
6994 | && (code == LE || code == GE |
6995 | || code == UNEQ || code == LTGT | |
6996 | || code == UNGT || code == UNLT)) | |
6997 | { | |
6998 | enum rtx_code or1, or2; | |
6999 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
7000 | rtx or_result = gen_reg_rtx (CCEQmode); | |
7001 | ||
7002 | switch (code) | |
7003 | { | |
7004 | case LE: or1 = LT; or2 = EQ; break; | |
7005 | case GE: or1 = GT; or2 = EQ; break; | |
7006 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
7007 | case LTGT: or1 = LT; or2 = GT; break; | |
7008 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
7009 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
7010 | default: abort (); | |
7011 | } | |
7012 | validate_condition_mode (or1, comp_mode); | |
7013 | validate_condition_mode (or2, comp_mode); | |
7014 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
7015 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
7016 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
7017 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
7018 | const_true_rtx); | |
7019 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
7020 | ||
7021 | compare_result = or_result; | |
7022 | code = EQ; | |
7023 | } | |
7024 | ||
7025 | validate_condition_mode (code, GET_MODE (compare_result)); | |
7026 | ||
7027 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
7028 | } | |
7029 | ||
7030 | ||
7031 | /* Emit the RTL for an sCOND pattern. */ | |
7032 | ||
7033 | void | |
7034 | rs6000_emit_sCOND (code, result) | |
7035 | enum rtx_code code; | |
7036 | rtx result; | |
7037 | { | |
7038 | rtx condition_rtx; | |
7039 | enum machine_mode op_mode; | |
7040 | ||
7041 | condition_rtx = rs6000_generate_compare (code); | |
7042 | ||
7043 | op_mode = GET_MODE (rs6000_compare_op0); | |
7044 | if (op_mode == VOIDmode) | |
7045 | op_mode = GET_MODE (rs6000_compare_op1); | |
7046 | ||
7047 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
7048 | { | |
7049 | PUT_MODE (condition_rtx, DImode); | |
7050 | convert_move (result, condition_rtx, 0); | |
7051 | } | |
7052 | else | |
7053 | { | |
7054 | PUT_MODE (condition_rtx, SImode); | |
7055 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
7056 | } | |
7057 | } | |
7058 | ||
39a10a29 GK |
7059 | /* Emit a branch of kind CODE to location LOC. */ |
7060 | ||
7061 | void | |
7062 | rs6000_emit_cbranch (code, loc) | |
7063 | enum rtx_code code; | |
7064 | rtx loc; | |
7065 | { | |
7066 | rtx condition_rtx, loc_ref; | |
7067 | ||
7068 | condition_rtx = rs6000_generate_compare (code); | |
7069 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
7070 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
7071 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
7072 | loc_ref, pc_rtx))); | |
7073 | } | |
7074 | ||
12a4e8c5 GK |
7075 | /* Return the string to output a conditional branch to LABEL, which is |
7076 | the operand number of the label, or -1 if the branch is really a | |
7077 | conditional return. | |
7078 | ||
7079 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
7080 | condition code register and its mode specifies what kind of | |
7081 | comparison we made. | |
7082 | ||
7083 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
7084 | ||
7085 | INSN is the insn. */ | |
7086 | ||
7087 | char * | |
7088 | output_cbranch (op, label, reversed, insn) | |
7089 | rtx op; | |
7090 | const char * label; | |
7091 | int reversed; | |
7092 | rtx insn; | |
7093 | { | |
7094 | static char string[64]; | |
7095 | enum rtx_code code = GET_CODE (op); | |
7096 | rtx cc_reg = XEXP (op, 0); | |
7097 | enum machine_mode mode = GET_MODE (cc_reg); | |
7098 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 7099 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
7100 | int really_reversed = reversed ^ need_longbranch; |
7101 | char *s = string; | |
7102 | const char *ccode; | |
7103 | const char *pred; | |
7104 | rtx note; | |
7105 | ||
39a10a29 GK |
7106 | validate_condition_mode (code, mode); |
7107 | ||
7108 | /* Work out which way this really branches. We could use | |
7109 | reverse_condition_maybe_unordered here always but this | |
7110 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 7111 | if (really_reversed) |
39a10a29 | 7112 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 7113 | |
39a10a29 | 7114 | switch (code) |
12a4e8c5 GK |
7115 | { |
7116 | /* Not all of these are actually distinct opcodes, but | |
7117 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
7118 | case NE: case LTGT: |
7119 | ccode = "ne"; break; | |
7120 | case EQ: case UNEQ: | |
7121 | ccode = "eq"; break; | |
7122 | case GE: case GEU: | |
7123 | ccode = "ge"; break; | |
7124 | case GT: case GTU: case UNGT: | |
7125 | ccode = "gt"; break; | |
7126 | case LE: case LEU: | |
7127 | ccode = "le"; break; | |
7128 | case LT: case LTU: case UNLT: | |
7129 | ccode = "lt"; break; | |
12a4e8c5 GK |
7130 | case UNORDERED: ccode = "un"; break; |
7131 | case ORDERED: ccode = "nu"; break; | |
7132 | case UNGE: ccode = "nl"; break; | |
7133 | case UNLE: ccode = "ng"; break; | |
7134 | default: | |
a4f6c312 | 7135 | abort (); |
12a4e8c5 GK |
7136 | } |
7137 | ||
94a54f47 GK |
7138 | /* Maybe we have a guess as to how likely the branch is. |
7139 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
7140 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
7141 | if (note != NULL_RTX) | |
7142 | { | |
7143 | /* PROB is the difference from 50%. */ | |
7144 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
7145 | ||
7146 | /* For branches that are very close to 50%, assume not-taken. */ | |
7147 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
7148 | && ((prob > 0) ^ need_longbranch)) | |
7149 | pred = "+"; | |
7150 | else | |
7151 | pred = "-"; | |
7152 | } | |
7153 | else | |
7154 | pred = ""; | |
7155 | ||
7156 | if (label == NULL) | |
94a54f47 | 7157 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 7158 | else |
94a54f47 | 7159 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 7160 | |
37c67319 GK |
7161 | /* We need to escape any '%' characters in the reg_names string. |
7162 | Assume they'd only be the first character... */ | |
7163 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
7164 | *s++ = '%'; | |
94a54f47 | 7165 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
7166 | |
7167 | if (label != NULL) | |
7168 | { | |
7169 | /* If the branch distance was too far, we may have to use an | |
7170 | unconditional branch to go the distance. */ | |
7171 | if (need_longbranch) | |
44518ddd | 7172 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
7173 | else |
7174 | s += sprintf (s, ",%s", label); | |
7175 | } | |
7176 | ||
7177 | return string; | |
7178 | } | |
50a0b056 GK |
7179 | |
7180 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
7181 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
7182 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 7183 | |
50a0b056 GK |
7184 | int |
7185 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
7186 | rtx dest; | |
7187 | rtx op; | |
7188 | rtx true_cond; | |
7189 | rtx false_cond; | |
7190 | { | |
7191 | enum rtx_code code = GET_CODE (op); | |
7192 | rtx op0 = rs6000_compare_op0; | |
7193 | rtx op1 = rs6000_compare_op1; | |
7194 | REAL_VALUE_TYPE c1; | |
7195 | enum machine_mode mode = GET_MODE (op0); | |
7196 | rtx temp; | |
7197 | ||
7198 | /* First, work out if the hardware can do this at all, or | |
7199 | if it's too slow... */ | |
7200 | /* If the comparison is an integer one, since we only have fsel | |
7201 | it'll be cheaper to use a branch. */ | |
7202 | if (! rs6000_compare_fp_p) | |
7203 | return 0; | |
7204 | ||
7205 | /* Eliminate half of the comparisons by switching operands, this | |
7206 | makes the remaining code simpler. */ | |
7207 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
7208 | || code == LTGT || code == LT) | |
7209 | { | |
7210 | code = reverse_condition_maybe_unordered (code); | |
7211 | temp = true_cond; | |
7212 | true_cond = false_cond; | |
7213 | false_cond = temp; | |
7214 | } | |
7215 | ||
7216 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
7217 | it'll probably be faster to use a branch here too. */ | |
7218 | if (code == UNEQ) | |
7219 | return 0; | |
7220 | ||
7221 | if (GET_CODE (op1) == CONST_DOUBLE) | |
7222 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
7223 | ||
7224 | /* We're going to try to implement comparions by performing | |
7225 | a subtract, then comparing against zero. Unfortunately, | |
7226 | Inf - Inf is NaN which is not zero, and so if we don't | |
7227 | know that the the operand is finite and the comparison | |
7228 | would treat EQ different to UNORDERED, we can't do it. */ | |
7229 | if (! flag_unsafe_math_optimizations | |
7230 | && code != GT && code != UNGE | |
7231 | && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) | |
7232 | /* Constructs of the form (a OP b ? a : b) are safe. */ | |
7233 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
7234 | || (! rtx_equal_p (op0, true_cond) | |
7235 | && ! rtx_equal_p (op1, true_cond)))) | |
7236 | return 0; | |
7237 | /* At this point we know we can use fsel. */ | |
7238 | ||
7239 | /* Reduce the comparison to a comparison against zero. */ | |
7240 | temp = gen_reg_rtx (mode); | |
7241 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
7242 | gen_rtx_MINUS (mode, op0, op1))); | |
7243 | op0 = temp; | |
7244 | op1 = CONST0_RTX (mode); | |
7245 | ||
7246 | /* If we don't care about NaNs we can reduce some of the comparisons | |
7247 | down to faster ones. */ | |
7248 | if (flag_unsafe_math_optimizations) | |
7249 | switch (code) | |
7250 | { | |
7251 | case GT: | |
7252 | code = LE; | |
7253 | temp = true_cond; | |
7254 | true_cond = false_cond; | |
7255 | false_cond = temp; | |
7256 | break; | |
7257 | case UNGE: | |
7258 | code = GE; | |
7259 | break; | |
7260 | case UNEQ: | |
7261 | code = EQ; | |
7262 | break; | |
7263 | default: | |
7264 | break; | |
7265 | } | |
7266 | ||
7267 | /* Now, reduce everything down to a GE. */ | |
7268 | switch (code) | |
7269 | { | |
7270 | case GE: | |
7271 | break; | |
7272 | ||
7273 | case LE: | |
7274 | temp = gen_reg_rtx (mode); | |
7275 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
7276 | op0 = temp; | |
7277 | break; | |
7278 | ||
7279 | case ORDERED: | |
7280 | temp = gen_reg_rtx (mode); | |
7281 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0))); | |
7282 | op0 = temp; | |
7283 | break; | |
7284 | ||
7285 | case EQ: | |
7286 | temp = gen_reg_rtx (mode); | |
7287 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
7288 | gen_rtx_NEG (mode, | |
7289 | gen_rtx_ABS (mode, op0)))); | |
7290 | op0 = temp; | |
7291 | break; | |
7292 | ||
7293 | case UNGE: | |
7294 | temp = gen_reg_rtx (mode); | |
7295 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
7296 | gen_rtx_IF_THEN_ELSE (mode, | |
7297 | gen_rtx_GE (VOIDmode, | |
7298 | op0, op1), | |
7299 | true_cond, false_cond))); | |
7300 | false_cond = temp; | |
7301 | true_cond = false_cond; | |
7302 | ||
7303 | temp = gen_reg_rtx (mode); | |
7304 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
7305 | op0 = temp; | |
7306 | break; | |
7307 | ||
7308 | case GT: | |
7309 | temp = gen_reg_rtx (mode); | |
7310 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
7311 | gen_rtx_IF_THEN_ELSE (mode, | |
7312 | gen_rtx_GE (VOIDmode, | |
7313 | op0, op1), | |
7314 | true_cond, false_cond))); | |
7315 | true_cond = temp; | |
7316 | false_cond = true_cond; | |
7317 | ||
7318 | temp = gen_reg_rtx (mode); | |
7319 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
7320 | op0 = temp; | |
7321 | break; | |
7322 | ||
7323 | default: | |
7324 | abort (); | |
7325 | } | |
7326 | ||
7327 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
9f1a9740 | 7328 | gen_rtx_IF_THEN_ELSE (GET_MODE (dest), |
50a0b056 GK |
7329 | gen_rtx_GE (VOIDmode, |
7330 | op0, op1), | |
7331 | true_cond, false_cond))); | |
7332 | return 1; | |
7333 | } | |
7334 | ||
7335 | void | |
7336 | rs6000_emit_minmax (dest, code, op0, op1) | |
7337 | rtx dest; | |
7338 | enum rtx_code code; | |
7339 | rtx op0; | |
7340 | rtx op1; | |
7341 | { | |
7342 | enum machine_mode mode = GET_MODE (op0); | |
7343 | rtx target; | |
7344 | if (code == SMAX || code == UMAX) | |
7345 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
7346 | op0, op1, mode, 0); | |
7347 | else | |
7348 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
7349 | op1, op0, mode, 0); | |
7350 | if (target == NULL_RTX) | |
7351 | abort (); | |
7352 | if (target != dest) | |
7353 | emit_move_insn (dest, target); | |
7354 | } | |
12a4e8c5 | 7355 | \f |
a4f6c312 SS |
7356 | /* This page contains routines that are used to determine what the |
7357 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 7358 | |
a4f6c312 SS |
7359 | /* Return the first fixed-point register that is required to be |
7360 | saved. 32 if none. */ | |
9878760c RK |
7361 | |
7362 | int | |
7363 | first_reg_to_save () | |
7364 | { | |
7365 | int first_reg; | |
7366 | ||
7367 | /* Find lowest numbered live register. */ | |
7368 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
7369 | if (regs_ever_live[first_reg] |
7370 | && (! call_used_regs[first_reg] | |
7371 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
7372 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
7373 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) | |
9878760c RK |
7374 | break; |
7375 | ||
70f4f91c | 7376 | if (current_function_profile) |
b5253831 DE |
7377 | { |
7378 | /* AIX must save/restore every register that contains a parameter | |
7379 | before/after the .__mcount call plus an additional register | |
7380 | for the static chain, if needed; use registers from 30 down to 22 | |
7381 | to do this. */ | |
ee890fe2 | 7382 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
b5253831 DE |
7383 | { |
7384 | int last_parm_reg, profile_first_reg; | |
7385 | ||
7386 | /* Figure out last used parameter register. The proper thing | |
7387 | to do is to walk incoming args of the function. A function | |
7388 | might have live parameter registers even if it has no | |
7389 | incoming args. */ | |
7390 | for (last_parm_reg = 10; | |
7391 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
7392 | last_parm_reg--) | |
7393 | ; | |
7394 | ||
7395 | /* Calculate first reg for saving parameter registers | |
7396 | and static chain. | |
7397 | Skip reg 31 which may contain the frame pointer. */ | |
7398 | profile_first_reg = (33 - last_parm_reg | |
7399 | - (current_function_needs_context ? 1 : 0)); | |
ee890fe2 SS |
7400 | #if TARGET_MACHO |
7401 | /* Need to skip another reg to account for R31 being PICBASE | |
7402 | (when flag_pic is set) or R30 being used as the frame | |
7403 | pointer (when flag_pic is not set). */ | |
7404 | --profile_first_reg; | |
7405 | #endif | |
b5253831 DE |
7406 | /* Do not save frame pointer if no parameters needs to be saved. */ |
7407 | if (profile_first_reg == 31) | |
7408 | profile_first_reg = 32; | |
7409 | ||
7410 | if (first_reg > profile_first_reg) | |
7411 | first_reg = profile_first_reg; | |
7412 | } | |
e165f3f0 | 7413 | |
b5253831 DE |
7414 | /* SVR4 may need one register to preserve the static chain. */ |
7415 | else if (current_function_needs_context) | |
7416 | { | |
7417 | /* Skip reg 31 which may contain the frame pointer. */ | |
7418 | if (first_reg > 30) | |
7419 | first_reg = 30; | |
7420 | } | |
7421 | } | |
e165f3f0 | 7422 | |
ee890fe2 SS |
7423 | #if TARGET_MACHO |
7424 | if (flag_pic && current_function_uses_pic_offset_table && | |
7425 | (first_reg > PIC_OFFSET_TABLE_REGNUM)) | |
7426 | return PIC_OFFSET_TABLE_REGNUM; | |
7427 | #endif | |
7428 | ||
9878760c RK |
7429 | return first_reg; |
7430 | } | |
7431 | ||
7432 | /* Similar, for FP regs. */ | |
7433 | ||
7434 | int | |
7435 | first_fp_reg_to_save () | |
7436 | { | |
7437 | int first_reg; | |
7438 | ||
7439 | /* Find lowest numbered live register. */ | |
7440 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
7441 | if (regs_ever_live[first_reg]) | |
7442 | break; | |
7443 | ||
7444 | return first_reg; | |
7445 | } | |
00b960c7 AH |
7446 | |
7447 | /* Similar, for AltiVec regs. */ | |
7448 | ||
7449 | static int | |
7450 | first_altivec_reg_to_save () | |
7451 | { | |
7452 | int i; | |
7453 | ||
7454 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
7455 | if (! TARGET_ALTIVEC_ABI) | |
7456 | return LAST_ALTIVEC_REGNO + 1; | |
7457 | ||
7458 | /* Find lowest numbered live register. */ | |
7459 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
7460 | if (regs_ever_live[i]) | |
7461 | break; | |
7462 | ||
7463 | return i; | |
7464 | } | |
7465 | ||
7466 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
7467 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
7468 | the 32-bit word is 0. */ | |
7469 | ||
7470 | static unsigned int | |
7471 | compute_vrsave_mask () | |
7472 | { | |
7473 | unsigned int i, mask = 0; | |
7474 | ||
7475 | /* First, find out if we use _any_ altivec registers. */ | |
7476 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
7477 | if (regs_ever_live[i]) | |
7478 | mask |= ALTIVEC_REG_BIT (i); | |
7479 | ||
7480 | if (mask == 0) | |
7481 | return mask; | |
7482 | ||
7483 | /* Next, add all registers that are call-clobbered. We do this | |
7484 | because post-reload register optimizers such as regrename_optimize | |
7485 | may choose to use them. They never change the register class | |
7486 | chosen by reload, so cannot create new uses of altivec registers | |
7487 | if there were none before, so the early exit above is safe. */ | |
7488 | /* ??? Alternately, we could define HARD_REGNO_RENAME_OK to disallow | |
7489 | altivec registers not saved in the mask, which might well make the | |
7490 | adjustments below more effective in eliding the save/restore of | |
7491 | VRSAVE in small functions. */ | |
7492 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
7493 | if (call_used_regs[i]) | |
7494 | mask |= ALTIVEC_REG_BIT (i); | |
7495 | ||
7496 | /* Next, remove the argument registers from the set. These must | |
7497 | be in the VRSAVE mask set by the caller, so we don't need to add | |
7498 | them in again. More importantly, the mask we compute here is | |
7499 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
7500 | wish the argument registers to die. */ | |
7501 | for (i = cfun->args_info.vregno; i >= ALTIVEC_ARG_MIN_REG; --i) | |
7502 | mask &= ~ALTIVEC_REG_BIT (i); | |
7503 | ||
7504 | /* Similarly, remove the return value from the set. */ | |
7505 | { | |
7506 | bool yes = false; | |
7507 | diddle_return_value (is_altivec_return_reg, &yes); | |
7508 | if (yes) | |
7509 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
7510 | } | |
7511 | ||
7512 | return mask; | |
7513 | } | |
7514 | ||
7515 | static void | |
7516 | is_altivec_return_reg (reg, xyes) | |
7517 | rtx reg; | |
7518 | void *xyes; | |
7519 | { | |
7520 | bool *yes = (bool *) xyes; | |
7521 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
7522 | *yes = true; | |
7523 | } | |
7524 | ||
4697a36c MM |
7525 | \f |
7526 | /* Calculate the stack information for the current function. This is | |
7527 | complicated by having two separate calling sequences, the AIX calling | |
7528 | sequence and the V.4 calling sequence. | |
7529 | ||
592696dd | 7530 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 7531 | 32-bit 64-bit |
4697a36c | 7532 | SP----> +---------------------------------------+ |
a260abc9 | 7533 | | back chain to caller | 0 0 |
4697a36c | 7534 | +---------------------------------------+ |
a260abc9 | 7535 | | saved CR | 4 8 (8-11) |
4697a36c | 7536 | +---------------------------------------+ |
a260abc9 | 7537 | | saved LR | 8 16 |
4697a36c | 7538 | +---------------------------------------+ |
a260abc9 | 7539 | | reserved for compilers | 12 24 |
4697a36c | 7540 | +---------------------------------------+ |
a260abc9 | 7541 | | reserved for binders | 16 32 |
4697a36c | 7542 | +---------------------------------------+ |
a260abc9 | 7543 | | saved TOC pointer | 20 40 |
4697a36c | 7544 | +---------------------------------------+ |
a260abc9 | 7545 | | Parameter save area (P) | 24 48 |
4697a36c | 7546 | +---------------------------------------+ |
a260abc9 | 7547 | | Alloca space (A) | 24+P etc. |
802a0058 | 7548 | +---------------------------------------+ |
a7df97e6 | 7549 | | Local variable space (L) | 24+P+A |
4697a36c | 7550 | +---------------------------------------+ |
a7df97e6 | 7551 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 7552 | +---------------------------------------+ |
00b960c7 AH |
7553 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
7554 | +---------------------------------------+ | |
7555 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
7556 | +---------------------------------------+ | |
7557 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 7558 | +---------------------------------------+ |
00b960c7 AH |
7559 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
7560 | +---------------------------------------+ | |
7561 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
7562 | +---------------------------------------+ |
7563 | old SP->| back chain to caller's caller | | |
7564 | +---------------------------------------+ | |
7565 | ||
5376a30c KR |
7566 | The required alignment for AIX configurations is two words (i.e., 8 |
7567 | or 16 bytes). | |
7568 | ||
7569 | ||
4697a36c MM |
7570 | V.4 stack frames look like: |
7571 | ||
7572 | SP----> +---------------------------------------+ | |
7573 | | back chain to caller | 0 | |
7574 | +---------------------------------------+ | |
5eb387b8 | 7575 | | caller's saved LR | 4 |
4697a36c MM |
7576 | +---------------------------------------+ |
7577 | | Parameter save area (P) | 8 | |
7578 | +---------------------------------------+ | |
a7df97e6 MM |
7579 | | Alloca space (A) | 8+P |
7580 | +---------------------------------------+ | |
7581 | | Varargs save area (V) | 8+P+A | |
7582 | +---------------------------------------+ | |
7583 | | Local variable space (L) | 8+P+A+V | |
7584 | +---------------------------------------+ | |
7585 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 7586 | +---------------------------------------+ |
00b960c7 AH |
7587 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
7588 | +---------------------------------------+ | |
7589 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
7590 | +---------------------------------------+ | |
7591 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
7592 | +---------------------------------------+ | |
7593 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z | |
a7df97e6 | 7594 | +---------------------------------------+ |
00b960c7 | 7595 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 7596 | +---------------------------------------+ |
00b960c7 | 7597 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
7598 | +---------------------------------------+ |
7599 | old SP->| back chain to caller's caller | | |
7600 | +---------------------------------------+ | |
b6c9286a | 7601 | |
5376a30c KR |
7602 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
7603 | given. (But note below and in sysv4.h that we require only 8 and | |
7604 | may round up the size of our stack frame anyways. The historical | |
7605 | reason is early versions of powerpc-linux which didn't properly | |
7606 | align the stack at program startup. A happy side-effect is that | |
7607 | -mno-eabi libraries can be used with -meabi programs.) | |
7608 | ||
5376a30c KR |
7609 | The EABI configuration defaults to the V.4 layout, unless |
7610 | -mcall-aix is used, in which case the AIX layout is used. However, | |
7611 | the stack alignment requirements may differ. If -mno-eabi is not | |
7612 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
7613 | given, the required alignment is 16 bytes. (But see V.4 comment | |
7614 | above.) */ | |
4697a36c | 7615 | |
61b2fbe7 MM |
7616 | #ifndef ABI_STACK_BOUNDARY |
7617 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
7618 | #endif | |
7619 | ||
4697a36c MM |
7620 | rs6000_stack_t * |
7621 | rs6000_stack_info () | |
7622 | { | |
7623 | static rs6000_stack_t info, zero_info; | |
7624 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 7625 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 7626 | enum rs6000_abi abi; |
83720594 | 7627 | int ehrd_size; |
b6c9286a | 7628 | int total_raw_size; |
4697a36c | 7629 | |
a4f6c312 | 7630 | /* Zero all fields portably. */ |
4697a36c MM |
7631 | info = zero_info; |
7632 | ||
a4f6c312 | 7633 | /* Select which calling sequence. */ |
b6c9286a | 7634 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 7635 | |
a4f6c312 | 7636 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 7637 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
906fb125 GK |
7638 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
7639 | even if it currently looks like we won't. */ | |
2bfcf297 | 7640 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
f607bc57 ZW |
7641 | || (flag_pic == 1 && abi == ABI_V4) |
7642 | || (flag_pic && abi == ABI_DARWIN)) | |
906fb125 GK |
7643 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) |
7644 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
7645 | else | |
7646 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
7647 | |
7648 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
7649 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
7650 | ||
00b960c7 AH |
7651 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
7652 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
7653 | - info_ptr->first_altivec_reg_save); | |
7654 | ||
592696dd | 7655 | /* Does this function call anything? */ |
71f123ca FS |
7656 | info_ptr->calls_p = (! current_function_is_leaf |
7657 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 7658 | |
a4f6c312 | 7659 | /* Determine if we need to save the link register. */ |
71f123ca | 7660 | if (rs6000_ra_ever_killed () |
70f4f91c | 7661 | || (DEFAULT_ABI == ABI_AIX && current_function_profile) |
4697a36c MM |
7662 | #ifdef TARGET_RELOCATABLE |
7663 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
7664 | #endif | |
7665 | || (info_ptr->first_fp_reg_save != 64 | |
7666 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 7667 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
24d304eb | 7668 | || (abi == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
7669 | || (DEFAULT_ABI == ABI_DARWIN |
7670 | && flag_pic | |
7671 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
7672 | || info_ptr->calls_p) |
7673 | { | |
7674 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 7675 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
7676 | } |
7677 | ||
9ebbca7d GK |
7678 | /* Determine if we need to save the condition code registers. */ |
7679 | if (regs_ever_live[CR2_REGNO] | |
7680 | || regs_ever_live[CR3_REGNO] | |
7681 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
7682 | { |
7683 | info_ptr->cr_save_p = 1; | |
f607bc57 | 7684 | if (abi == ABI_V4) |
4697a36c MM |
7685 | info_ptr->cr_size = reg_size; |
7686 | } | |
7687 | ||
83720594 RH |
7688 | /* If the current function calls __builtin_eh_return, then we need |
7689 | to allocate stack space for registers that will hold data for | |
7690 | the exception handler. */ | |
7691 | if (current_function_calls_eh_return) | |
7692 | { | |
7693 | unsigned int i; | |
7694 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
7695 | continue; | |
7696 | ehrd_size = i * UNITS_PER_WORD; | |
7697 | } | |
7698 | else | |
7699 | ehrd_size = 0; | |
7700 | ||
592696dd | 7701 | /* Determine various sizes. */ |
4697a36c MM |
7702 | info_ptr->reg_size = reg_size; |
7703 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
7704 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 7705 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 SS |
7706 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
7707 | 8); | |
00b960c7 AH |
7708 | |
7709 | if (TARGET_ALTIVEC_ABI) | |
7710 | { | |
7711 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
7712 | info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0; | |
7713 | } | |
7714 | else | |
7715 | { | |
7716 | info_ptr->vrsave_mask = 0; | |
7717 | info_ptr->vrsave_size = 0; | |
7718 | } | |
b6c9286a | 7719 | |
592696dd | 7720 | /* Calculate the offsets. */ |
24d304eb | 7721 | switch (abi) |
4697a36c | 7722 | { |
b6c9286a | 7723 | case ABI_NONE: |
24d304eb | 7724 | default: |
b6c9286a MM |
7725 | abort (); |
7726 | ||
7727 | case ABI_AIX: | |
7728 | case ABI_AIX_NODESC: | |
ee890fe2 | 7729 | case ABI_DARWIN: |
b6c9286a MM |
7730 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
7731 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
7732 | |
7733 | if (TARGET_ALTIVEC_ABI) | |
7734 | { | |
7735 | info_ptr->vrsave_save_offset | |
7736 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
7737 | ||
7738 | /* Align stack so vector save area is on a quadword boundary. */ | |
7739 | if (info_ptr->altivec_size != 0) | |
7740 | info_ptr->altivec_padding_size | |
7741 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
7742 | else | |
7743 | info_ptr->altivec_padding_size = 0; | |
7744 | ||
7745 | info_ptr->altivec_save_offset | |
7746 | = info_ptr->vrsave_save_offset | |
7747 | - info_ptr->altivec_padding_size | |
7748 | - info_ptr->altivec_size; | |
7749 | ||
7750 | /* Adjust for AltiVec case. */ | |
7751 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
7752 | } | |
7753 | else | |
7754 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
7755 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
7756 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
7757 | break; |
7758 | ||
7759 | case ABI_V4: | |
b6c9286a MM |
7760 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
7761 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 7762 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 AH |
7763 | |
7764 | if (TARGET_ALTIVEC_ABI) | |
7765 | { | |
7766 | info_ptr->vrsave_save_offset | |
7767 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
7768 | ||
7769 | /* Align stack so vector save area is on a quadword boundary. */ | |
7770 | if (info_ptr->altivec_size != 0) | |
7771 | info_ptr->altivec_padding_size | |
7772 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
7773 | else | |
7774 | info_ptr->altivec_padding_size = 0; | |
7775 | ||
7776 | info_ptr->altivec_save_offset | |
7777 | = info_ptr->vrsave_save_offset | |
7778 | - info_ptr->altivec_padding_size | |
7779 | - info_ptr->altivec_size; | |
7780 | ||
7781 | /* Adjust for AltiVec case. */ | |
7782 | info_ptr->toc_save_offset | |
7783 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
7784 | } | |
7785 | else | |
7786 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 7787 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
7788 | info_ptr->lr_save_offset = reg_size; |
7789 | break; | |
4697a36c MM |
7790 | } |
7791 | ||
00b960c7 AH |
7792 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
7793 | + info_ptr->gp_size | |
7794 | + info_ptr->altivec_size | |
7795 | + info_ptr->altivec_padding_size | |
7796 | + info_ptr->vrsave_size | |
7797 | + ehrd_size | |
7798 | + info_ptr->cr_size | |
7799 | + info_ptr->lr_size | |
7800 | + info_ptr->vrsave_size | |
7801 | + info_ptr->toc_size, | |
7802 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
7803 | ? 16 : 8); | |
7804 | ||
ff381587 MM |
7805 | total_raw_size = (info_ptr->vars_size |
7806 | + info_ptr->parm_size | |
ff381587 MM |
7807 | + info_ptr->save_size |
7808 | + info_ptr->varargs_size | |
7809 | + info_ptr->fixed_size); | |
7810 | ||
a4f6c312 SS |
7811 | info_ptr->total_size = |
7812 | RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
7813 | |
7814 | /* Determine if we need to allocate any stack frame: | |
7815 | ||
a4f6c312 SS |
7816 | For AIX we need to push the stack if a frame pointer is needed |
7817 | (because the stack might be dynamically adjusted), if we are | |
7818 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
7819 | and local variables are more than the space needed to save all | |
7820 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
7821 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 7822 | |
a4f6c312 SS |
7823 | For V.4 we don't have the stack cushion that AIX uses, but assume |
7824 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
7825 | |
7826 | if (info_ptr->calls_p) | |
7827 | info_ptr->push_p = 1; | |
7828 | ||
f607bc57 | 7829 | else if (abi == ABI_V4) |
ff381587 | 7830 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
9ebbca7d | 7831 | || info_ptr->calls_p); |
ff381587 MM |
7832 | |
7833 | else | |
7834 | info_ptr->push_p = (frame_pointer_needed | |
ee890fe2 | 7835 | || (abi != ABI_DARWIN && write_symbols != NO_DEBUG) |
ff381587 | 7836 | || ((total_raw_size - info_ptr->fixed_size) |
bfc79d3b | 7837 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 7838 | |
a4f6c312 | 7839 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 7840 | if (info_ptr->fp_size == 0) |
4697a36c MM |
7841 | info_ptr->fp_save_offset = 0; |
7842 | ||
8dda1a21 | 7843 | if (info_ptr->gp_size == 0) |
4697a36c MM |
7844 | info_ptr->gp_save_offset = 0; |
7845 | ||
00b960c7 AH |
7846 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
7847 | info_ptr->altivec_save_offset = 0; | |
7848 | ||
7849 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
7850 | info_ptr->vrsave_save_offset = 0; | |
7851 | ||
c81fc13e | 7852 | if (! info_ptr->lr_save_p) |
4697a36c MM |
7853 | info_ptr->lr_save_offset = 0; |
7854 | ||
c81fc13e | 7855 | if (! info_ptr->cr_save_p) |
4697a36c MM |
7856 | info_ptr->cr_save_offset = 0; |
7857 | ||
c81fc13e | 7858 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
7859 | info_ptr->toc_save_offset = 0; |
7860 | ||
4697a36c MM |
7861 | return info_ptr; |
7862 | } | |
7863 | ||
7864 | void | |
7865 | debug_stack_info (info) | |
7866 | rs6000_stack_t *info; | |
9878760c | 7867 | { |
d330fd93 | 7868 | const char *abi_string; |
24d304eb | 7869 | |
c81fc13e | 7870 | if (! info) |
4697a36c MM |
7871 | info = rs6000_stack_info (); |
7872 | ||
7873 | fprintf (stderr, "\nStack information for function %s:\n", | |
7874 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
7875 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
7876 | : "<unknown>")); | |
7877 | ||
24d304eb RK |
7878 | switch (info->abi) |
7879 | { | |
b6c9286a MM |
7880 | default: abi_string = "Unknown"; break; |
7881 | case ABI_NONE: abi_string = "NONE"; break; | |
f607bc57 | 7882 | case ABI_AIX: |
b6c9286a | 7883 | case ABI_AIX_NODESC: abi_string = "AIX"; break; |
ee890fe2 | 7884 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 7885 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
7886 | } |
7887 | ||
7888 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
7889 | ||
00b960c7 AH |
7890 | if (TARGET_ALTIVEC_ABI) |
7891 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
7892 | ||
4697a36c MM |
7893 | if (info->first_gp_reg_save != 32) |
7894 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
7895 | ||
7896 | if (info->first_fp_reg_save != 64) | |
7897 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 7898 | |
00b960c7 AH |
7899 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
7900 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
7901 | info->first_altivec_reg_save); | |
7902 | ||
4697a36c MM |
7903 | if (info->lr_save_p) |
7904 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 7905 | |
4697a36c MM |
7906 | if (info->cr_save_p) |
7907 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
7908 | ||
b6c9286a MM |
7909 | if (info->toc_save_p) |
7910 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
7911 | ||
00b960c7 AH |
7912 | if (info->vrsave_mask) |
7913 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
7914 | ||
4697a36c MM |
7915 | if (info->push_p) |
7916 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
7917 | ||
7918 | if (info->calls_p) | |
7919 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
7920 | ||
4697a36c MM |
7921 | if (info->gp_save_offset) |
7922 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
7923 | ||
7924 | if (info->fp_save_offset) | |
7925 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
7926 | ||
00b960c7 AH |
7927 | if (info->altivec_save_offset) |
7928 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
7929 | info->altivec_save_offset); | |
7930 | ||
7931 | if (info->vrsave_save_offset) | |
7932 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
7933 | info->vrsave_save_offset); | |
7934 | ||
4697a36c MM |
7935 | if (info->lr_save_offset) |
7936 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
7937 | ||
7938 | if (info->cr_save_offset) | |
7939 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
7940 | ||
b6c9286a MM |
7941 | if (info->toc_save_offset) |
7942 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
7943 | ||
4697a36c MM |
7944 | if (info->varargs_save_offset) |
7945 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
7946 | ||
7947 | if (info->total_size) | |
7948 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
7949 | ||
7950 | if (info->varargs_size) | |
7951 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
7952 | ||
7953 | if (info->vars_size) | |
7954 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
7955 | ||
7956 | if (info->parm_size) | |
7957 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
7958 | ||
7959 | if (info->fixed_size) | |
7960 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
7961 | ||
7962 | if (info->gp_size) | |
7963 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
7964 | ||
7965 | if (info->fp_size) | |
7966 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
7967 | ||
00b960c7 AH |
7968 | if (info->altivec_size) |
7969 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
7970 | ||
7971 | if (info->vrsave_size) | |
7972 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
7973 | ||
7974 | if (info->altivec_padding_size) | |
7975 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
7976 | info->altivec_padding_size); | |
7977 | ||
a4f6c312 | 7978 | if (info->lr_size) |
ed947a96 | 7979 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 7980 | |
4697a36c MM |
7981 | if (info->cr_size) |
7982 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
7983 | ||
a4f6c312 | 7984 | if (info->toc_size) |
b6c9286a MM |
7985 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
7986 | ||
4697a36c MM |
7987 | if (info->save_size) |
7988 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
7989 | ||
7990 | if (info->reg_size != 4) | |
7991 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
7992 | ||
7993 | fprintf (stderr, "\n"); | |
9878760c | 7994 | } |
71f123ca FS |
7995 | |
7996 | rtx | |
7997 | rs6000_return_addr (count, frame) | |
7998 | int count; | |
7999 | rtx frame; | |
8000 | { | |
a4f6c312 SS |
8001 | /* Currently we don't optimize very well between prolog and body |
8002 | code and for PIC code the code can be actually quite bad, so | |
8003 | don't try to be too clever here. */ | |
3418dd3a FS |
8004 | if (count != 0 |
8005 | || flag_pic != 0 | |
8006 | || DEFAULT_ABI == ABI_AIX | |
8007 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
71f123ca FS |
8008 | { |
8009 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
8010 | |
8011 | return | |
8012 | gen_rtx_MEM | |
8013 | (Pmode, | |
8014 | memory_address | |
8015 | (Pmode, | |
8016 | plus_constant (copy_to_reg | |
8017 | (gen_rtx_MEM (Pmode, | |
8018 | memory_address (Pmode, frame))), | |
8019 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
8020 | } |
8021 | ||
9e2f7ec7 | 8022 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
8023 | } |
8024 | ||
8025 | static int | |
8026 | rs6000_ra_ever_killed () | |
8027 | { | |
8028 | rtx top; | |
8029 | ||
8030 | #ifdef ASM_OUTPUT_MI_THUNK | |
8031 | if (current_function_is_thunk) | |
8032 | return 0; | |
8033 | #endif | |
9e2f7ec7 DD |
8034 | if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) |
8035 | || cfun->machine->ra_needs_full_frame) | |
71f123ca FS |
8036 | return regs_ever_live[LINK_REGISTER_REGNUM]; |
8037 | ||
8038 | push_topmost_sequence (); | |
8039 | top = get_insns (); | |
8040 | pop_topmost_sequence (); | |
8041 | ||
8042 | return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
8043 | top, NULL_RTX); | |
8044 | } | |
4697a36c | 8045 | \f |
8cd8f856 GK |
8046 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
8047 | static void | |
8048 | rs6000_maybe_dead (insn) | |
8049 | rtx insn; | |
8050 | { | |
8051 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
8052 | const0_rtx, | |
8053 | REG_NOTES (insn)); | |
8054 | } | |
8055 | ||
9ebbca7d | 8056 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 8057 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 8058 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
8059 | |
8060 | void | |
9ebbca7d GK |
8061 | rs6000_emit_load_toc_table (fromprolog) |
8062 | int fromprolog; | |
c7ca610e | 8063 | { |
9ebbca7d GK |
8064 | rtx dest; |
8065 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 8066 | |
2bfcf297 | 8067 | if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) |
c7ca610e | 8068 | { |
f607bc57 | 8069 | if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
38c1f2d7 | 8070 | { |
9ebbca7d GK |
8071 | rtx temp = (fromprolog |
8072 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
8073 | : gen_reg_rtx (Pmode)); | |
2bfcf297 | 8074 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
8cd8f856 | 8075 | rs6000_maybe_dead (emit_move_insn (dest, temp)); |
38c1f2d7 | 8076 | } |
9ebbca7d GK |
8077 | else if (flag_pic == 2) |
8078 | { | |
8079 | char buf[30]; | |
8080 | rtx tempLR = (fromprolog | |
8081 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
8082 | : gen_reg_rtx (Pmode)); | |
8083 | rtx temp0 = (fromprolog | |
8084 | ? gen_rtx_REG (Pmode, 0) | |
8085 | : gen_reg_rtx (Pmode)); | |
8086 | rtx symF; | |
8087 | ||
8088 | /* possibly create the toc section */ | |
8089 | if (! toc_initialized) | |
8090 | { | |
8091 | toc_section (); | |
8092 | function_section (current_function_decl); | |
8093 | } | |
8094 | ||
8095 | if (fromprolog) | |
8096 | { | |
8097 | rtx symL; | |
8098 | ||
8099 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
a8a05998 | 8100 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 8101 | |
9ebbca7d | 8102 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
a8a05998 | 8103 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 8104 | |
8cd8f856 GK |
8105 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
8106 | symF))); | |
8107 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
8108 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
8109 | symL, | |
8110 | symF))); | |
9ebbca7d GK |
8111 | } |
8112 | else | |
8113 | { | |
8114 | rtx tocsym; | |
8115 | static int reload_toc_labelno = 0; | |
8116 | ||
b999aaeb | 8117 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); |
38c1f2d7 | 8118 | |
9ebbca7d | 8119 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
a8a05998 | 8120 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 8121 | |
8cd8f856 GK |
8122 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
8123 | symF, | |
8124 | tocsym))); | |
8125 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
8126 | rs6000_maybe_dead (emit_move_insn (temp0, | |
8127 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 8128 | } |
8cd8f856 | 8129 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
8130 | } |
8131 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
8132 | { | |
8133 | /* This is for AIX code running in non-PIC ELF. */ | |
8134 | char buf[30]; | |
8135 | rtx realsym; | |
38c1f2d7 | 8136 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
a8a05998 | 8137 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 8138 | |
8cd8f856 GK |
8139 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
8140 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
8141 | } |
8142 | else | |
a4f6c312 | 8143 | abort (); |
9ebbca7d GK |
8144 | } |
8145 | else | |
8146 | { | |
8147 | if (TARGET_32BIT) | |
8cd8f856 | 8148 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 8149 | else |
8cd8f856 | 8150 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
8151 | } |
8152 | } | |
8153 | ||
8154 | int | |
8155 | get_TOC_alias_set () | |
8156 | { | |
8157 | static int set = -1; | |
8158 | if (set == -1) | |
8159 | set = new_alias_set (); | |
8160 | return set; | |
8161 | } | |
8162 | ||
8163 | /* This retuns nonzero if the current function uses the TOC. This is | |
8164 | determined by the presence of (unspec ... 7), which is generated by | |
8165 | the various load_toc_* patterns. */ | |
a4f6c312 | 8166 | |
9ebbca7d GK |
8167 | int |
8168 | uses_TOC () | |
8169 | { | |
8170 | rtx insn; | |
38c1f2d7 | 8171 | |
9ebbca7d | 8172 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 8173 | if (INSN_P (insn)) |
9ebbca7d GK |
8174 | { |
8175 | rtx pat = PATTERN (insn); | |
8176 | int i; | |
8177 | ||
8cd8f856 | 8178 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
8179 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
8180 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
8181 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
8182 | return 1; | |
38c1f2d7 | 8183 | } |
9ebbca7d GK |
8184 | return 0; |
8185 | } | |
38c1f2d7 | 8186 | |
9ebbca7d | 8187 | rtx |
a4f6c312 | 8188 | create_TOC_reference (symbol) |
9ebbca7d GK |
8189 | rtx symbol; |
8190 | { | |
a8a05998 ZW |
8191 | return gen_rtx_PLUS (Pmode, |
8192 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
8193 | gen_rtx_CONST (Pmode, | |
8194 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 8195 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 8196 | } |
38c1f2d7 | 8197 | |
9ebbca7d GK |
8198 | #if TARGET_AIX |
8199 | /* __throw will restore its own return address to be the same as the | |
8200 | return address of the function that the throw is being made to. | |
8201 | This is unfortunate, because we want to check the original | |
8202 | return address to see if we need to restore the TOC. | |
8203 | So we have to squirrel it away here. | |
8204 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 8205 | |
9ebbca7d GK |
8206 | Most of this code should be removed by CSE. */ |
8207 | static rtx insn_after_throw; | |
c7ca610e | 8208 | |
a4f6c312 | 8209 | /* This does the saving... */ |
9ebbca7d GK |
8210 | void |
8211 | rs6000_aix_emit_builtin_unwind_init () | |
8212 | { | |
8213 | rtx mem; | |
8214 | rtx stack_top = gen_reg_rtx (Pmode); | |
8215 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
8216 | ||
8217 | insn_after_throw = gen_reg_rtx (SImode); | |
8218 | ||
8219 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
8220 | emit_move_insn (stack_top, mem); | |
8221 | ||
8222 | mem = gen_rtx_MEM (Pmode, | |
8223 | gen_rtx_PLUS (Pmode, stack_top, | |
8224 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
8225 | emit_move_insn (opcode_addr, mem); | |
8226 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
8227 | } |
8228 | ||
a4f6c312 SS |
8229 | /* Emit insns to _restore_ the TOC register, at runtime (specifically |
8230 | in _eh.o). Only used on AIX. | |
9ebbca7d GK |
8231 | |
8232 | The idea is that on AIX, function calls look like this: | |
8233 | bl somefunction-trampoline | |
8234 | lwz r2,20(sp) | |
8235 | ||
a4f6c312 | 8236 | and later, |
9ebbca7d GK |
8237 | somefunction-trampoline: |
8238 | stw r2,20(sp) | |
8239 | ... load function address in the count register ... | |
8240 | bctr | |
8241 | or like this, if the linker determines that this is not a cross-module call | |
8242 | and so the TOC need not be restored: | |
8243 | bl somefunction | |
8244 | nop | |
8245 | or like this, if the compiler could determine that this is not a | |
8246 | cross-module call: | |
8247 | bl somefunction | |
8248 | now, the tricky bit here is that register 2 is saved and restored | |
8249 | by the _linker_, so we can't readily generate debugging information | |
8250 | for it. So we need to go back up the call chain looking at the | |
8251 | insns at return addresses to see which calls saved the TOC register | |
8252 | and so see where it gets restored from. | |
8253 | ||
8254 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
8255 | just before the actual epilogue. | |
8256 | ||
8257 | On the bright side, this incurs no space or time overhead unless an | |
8258 | exception is thrown, except for the extra code in libgcc.a. | |
8259 | ||
8260 | The parameter STACKSIZE is a register containing (at runtime) | |
8261 | the amount to be popped off the stack in addition to the stack frame | |
8262 | of this routine (which will be __throw or __rethrow, and so is | |
8263 | guaranteed to have a stack frame). */ | |
a4f6c312 | 8264 | |
9ebbca7d GK |
8265 | void |
8266 | rs6000_emit_eh_toc_restore (stacksize) | |
8267 | rtx stacksize; | |
8268 | { | |
8269 | rtx top_of_stack; | |
8270 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
8271 | rtx tocompare = gen_reg_rtx (SImode); | |
8272 | rtx opcode = gen_reg_rtx (SImode); | |
8273 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
8274 | rtx mem; | |
8275 | rtx loop_start = gen_label_rtx (); | |
8276 | rtx no_toc_restore_needed = gen_label_rtx (); | |
8277 | rtx loop_exit = gen_label_rtx (); | |
8278 | ||
8279 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 8280 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8281 | emit_move_insn (bottom_of_stack, mem); |
8282 | ||
8283 | top_of_stack = expand_binop (Pmode, add_optab, | |
8284 | bottom_of_stack, stacksize, | |
8285 | NULL_RTX, 1, OPTAB_WIDEN); | |
8286 | ||
8287 | emit_move_insn (tocompare, | |
8288 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
8289 | ? 0x80410014 | |
8290 | : 0xE8410028, SImode))); | |
8291 | ||
8292 | if (insn_after_throw == NULL_RTX) | |
a4f6c312 | 8293 | abort (); |
9ebbca7d GK |
8294 | emit_move_insn (opcode, insn_after_throw); |
8295 | ||
6496a589 | 8296 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
8297 | emit_label (loop_start); |
8298 | ||
8299 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
06f4e019 | 8300 | SImode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
8301 | no_toc_restore_needed); |
8302 | ||
8303 | mem = gen_rtx_MEM (Pmode, | |
8304 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
8305 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
8306 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
8307 | ||
8308 | emit_label (no_toc_restore_needed); | |
8309 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
06f4e019 | 8310 | Pmode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
8311 | loop_exit); |
8312 | ||
8313 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 8314 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8315 | emit_move_insn (bottom_of_stack, mem); |
8316 | ||
8317 | mem = gen_rtx_MEM (Pmode, | |
8318 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
8319 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
8320 | emit_move_insn (opcode_addr, mem); | |
8321 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
8322 | ||
6496a589 | 8323 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 8324 | emit_jump (loop_start); |
6496a589 | 8325 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
8326 | emit_label (loop_exit); |
8327 | } | |
8328 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 8329 | \f |
ba4828e0 RK |
8330 | /* This ties together stack memory (MEM with an alias set of |
8331 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
8332 | ||
9ebbca7d GK |
8333 | static void |
8334 | rs6000_emit_stack_tie () | |
8335 | { | |
ba4828e0 RK |
8336 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
8337 | ||
8338 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
8339 | emit_insn (gen_stack_tie (mem)); |
8340 | } | |
38c1f2d7 | 8341 | |
9ebbca7d GK |
8342 | /* Emit the correct code for allocating stack space, as insns. |
8343 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
8344 | The generated code may use hard register 0 as a temporary. */ | |
8345 | ||
8346 | static void | |
8347 | rs6000_emit_allocate_stack (size, copy_r12) | |
8348 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
8349 | int copy_r12; |
8350 | { | |
9ebbca7d GK |
8351 | rtx insn; |
8352 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
8353 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
8354 | rtx todec = GEN_INT (-size); | |
a157febd GK |
8355 | |
8356 | if (current_function_limit_stack) | |
8357 | { | |
8358 | if (REG_P (stack_limit_rtx) | |
8359 | && REGNO (stack_limit_rtx) > 1 | |
8360 | && REGNO (stack_limit_rtx) <= 31) | |
8361 | { | |
9ebbca7d GK |
8362 | emit_insn (Pmode == SImode |
8363 | ? gen_addsi3 (tmp_reg, | |
8364 | stack_limit_rtx, | |
8365 | GEN_INT (size)) | |
8366 | : gen_adddi3 (tmp_reg, | |
8367 | stack_limit_rtx, | |
8368 | GEN_INT (size))); | |
8369 | ||
8370 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
8371 | const0_rtx)); | |
a157febd GK |
8372 | } |
8373 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 8374 | && TARGET_32BIT |
f607bc57 | 8375 | && DEFAULT_ABI == ABI_V4) |
a157febd | 8376 | { |
9ebbca7d GK |
8377 | rtx toload = gen_rtx_CONST (VOIDmode, |
8378 | gen_rtx_PLUS (Pmode, | |
8379 | stack_limit_rtx, | |
8380 | GEN_INT (size))); | |
8381 | ||
8382 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
8383 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
8384 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
8385 | const0_rtx)); | |
a157febd GK |
8386 | } |
8387 | else | |
8388 | warning ("stack limit expression is not supported"); | |
8389 | } | |
8390 | ||
9ebbca7d GK |
8391 | if (copy_r12 || ! TARGET_UPDATE) |
8392 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
8393 | ||
38c1f2d7 MM |
8394 | if (TARGET_UPDATE) |
8395 | { | |
9ebbca7d | 8396 | if (size > 32767) |
38c1f2d7 | 8397 | { |
9ebbca7d GK |
8398 | /* Need a note here so that try_split doesn't get confused. */ |
8399 | if (get_last_insn() == NULL_RTX) | |
8400 | emit_note (0, NOTE_INSN_DELETED); | |
8401 | insn = emit_move_insn (tmp_reg, todec); | |
8402 | try_split (PATTERN (insn), insn, 0); | |
8403 | todec = tmp_reg; | |
38c1f2d7 | 8404 | } |
9ebbca7d GK |
8405 | |
8406 | if (Pmode == SImode) | |
8407 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
8408 | todec, stack_reg)); | |
8409 | else | |
8410 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
8411 | todec, stack_reg)); | |
38c1f2d7 MM |
8412 | } |
8413 | else | |
8414 | { | |
9ebbca7d GK |
8415 | if (Pmode == SImode) |
8416 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 8417 | else |
9ebbca7d GK |
8418 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
8419 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
8420 | gen_rtx_REG (Pmode, 12)); | |
8421 | } | |
8422 | ||
8423 | RTX_FRAME_RELATED_P (insn) = 1; | |
8424 | REG_NOTES (insn) = | |
8425 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8426 | gen_rtx_SET (VOIDmode, stack_reg, | |
8427 | gen_rtx_PLUS (Pmode, stack_reg, | |
8428 | GEN_INT (-size))), | |
8429 | REG_NOTES (insn)); | |
8430 | } | |
8431 | ||
9aa86737 AH |
8432 | /* Add a RTX_FRAME_RELATED note so that dwarf2out_frame_debug_expr |
8433 | knows that: | |
8434 | ||
8435 | (mem (plus (blah) (regXX))) | |
8436 | ||
8437 | is really: | |
8438 | ||
8439 | (mem (plus (blah) (const VALUE_OF_REGXX))). */ | |
8440 | ||
8441 | static void | |
8442 | altivec_frame_fixup (insn, reg, val) | |
8443 | rtx insn, reg; | |
8444 | HOST_WIDE_INT val; | |
8445 | { | |
8446 | rtx real; | |
8447 | ||
8448 | real = copy_rtx (PATTERN (insn)); | |
8449 | ||
8450 | real = replace_rtx (real, reg, GEN_INT (val)); | |
8451 | ||
8452 | RTX_FRAME_RELATED_P (insn) = 1; | |
8453 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8454 | real, | |
8455 | REG_NOTES (insn)); | |
8456 | } | |
8457 | ||
a4f6c312 SS |
8458 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
8459 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
8460 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
8461 | deduce these equivalences by itself so it wasn't necessary to hold | |
8462 | its hand so much. */ | |
9ebbca7d GK |
8463 | |
8464 | static void | |
8465 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
8466 | rtx insn; | |
8467 | rtx reg; | |
8468 | HOST_WIDE_INT val; | |
8469 | rtx reg2; | |
8470 | rtx rreg; | |
8471 | { | |
8472 | rtx real, temp; | |
8473 | ||
8474 | real = copy_rtx (PATTERN (insn)); | |
8475 | ||
8476 | real = replace_rtx (real, reg, | |
8477 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
8478 | STACK_POINTER_REGNUM), | |
8479 | GEN_INT (val))); | |
8480 | ||
8481 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
8482 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
8483 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
8484 | ||
8485 | if (GET_CODE (real) == SET) | |
8486 | { | |
8487 | rtx set = real; | |
8488 | ||
8489 | temp = simplify_rtx (SET_SRC (set)); | |
8490 | if (temp) | |
8491 | SET_SRC (set) = temp; | |
8492 | temp = simplify_rtx (SET_DEST (set)); | |
8493 | if (temp) | |
8494 | SET_DEST (set) = temp; | |
8495 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 8496 | { |
9ebbca7d GK |
8497 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
8498 | if (temp) | |
8499 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 8500 | } |
38c1f2d7 | 8501 | } |
9ebbca7d GK |
8502 | else if (GET_CODE (real) == PARALLEL) |
8503 | { | |
8504 | int i; | |
8505 | for (i = 0; i < XVECLEN (real, 0); i++) | |
8506 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
8507 | { | |
8508 | rtx set = XVECEXP (real, 0, i); | |
8509 | ||
8510 | temp = simplify_rtx (SET_SRC (set)); | |
8511 | if (temp) | |
8512 | SET_SRC (set) = temp; | |
8513 | temp = simplify_rtx (SET_DEST (set)); | |
8514 | if (temp) | |
8515 | SET_DEST (set) = temp; | |
8516 | if (GET_CODE (SET_DEST (set)) == MEM) | |
8517 | { | |
8518 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
8519 | if (temp) | |
8520 | XEXP (SET_DEST (set), 0) = temp; | |
8521 | } | |
8522 | RTX_FRAME_RELATED_P (set) = 1; | |
8523 | } | |
8524 | } | |
8525 | else | |
a4f6c312 | 8526 | abort (); |
9ebbca7d GK |
8527 | |
8528 | if (reg2 != NULL_RTX) | |
8529 | real = replace_rtx (real, reg2, rreg); | |
8530 | ||
8531 | RTX_FRAME_RELATED_P (insn) = 1; | |
8532 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8533 | real, | |
8534 | REG_NOTES (insn)); | |
38c1f2d7 MM |
8535 | } |
8536 | ||
00b960c7 AH |
8537 | /* Returns an insn that has a vrsave set operation with the |
8538 | appropriate CLOBBERs. */ | |
8539 | ||
8540 | static rtx | |
9aa86737 | 8541 | generate_set_vrsave (reg, info, epiloguep) |
00b960c7 AH |
8542 | rtx reg; |
8543 | rs6000_stack_t *info; | |
9aa86737 | 8544 | int epiloguep; |
00b960c7 AH |
8545 | { |
8546 | int nclobs, i; | |
8547 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 8548 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 8549 | |
a004eb82 AH |
8550 | clobs[0] |
8551 | = gen_rtx_SET (VOIDmode, | |
8552 | vrsave, | |
8553 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
8554 | gen_rtvec (2, reg, vrsave), | |
8555 | 30)); | |
00b960c7 AH |
8556 | |
8557 | nclobs = 1; | |
8558 | ||
9aa86737 AH |
8559 | /* We need to clobber the registers in the mask so the scheduler |
8560 | does not move sets to VRSAVE before sets of AltiVec registers. | |
8561 | ||
8562 | However, if the function receives nonlocal gotos, reload will set | |
8563 | all call saved registers live. We will end up with: | |
8564 | ||
8565 | (set (reg 999) (mem)) | |
8566 | (parallel [ (set (reg vrsave) (unspec blah)) | |
8567 | (clobber (reg 999))]) | |
8568 | ||
8569 | The clobber will cause the store into reg 999 to be dead, and | |
8570 | flow will attempt to delete an epilogue insn. In this case, we | |
8571 | need an unspec use/set of the register. */ | |
00b960c7 AH |
8572 | |
8573 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
8574 | if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0) | |
9aa86737 AH |
8575 | { |
8576 | if (!epiloguep || call_used_regs [i]) | |
8577 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
8578 | gen_rtx_REG (V4SImode, i)); | |
8579 | else | |
8580 | { | |
8581 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
8582 | |
8583 | clobs[nclobs++] | |
a004eb82 AH |
8584 | = gen_rtx_SET (VOIDmode, |
8585 | reg, | |
8586 | gen_rtx_UNSPEC (V4SImode, | |
8587 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
8588 | } |
8589 | } | |
00b960c7 AH |
8590 | |
8591 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
8592 | ||
8593 | for (i = 0; i < nclobs; ++i) | |
8594 | XVECEXP (insn, 0, i) = clobs[i]; | |
8595 | ||
8596 | return insn; | |
8597 | } | |
8598 | ||
9ebbca7d GK |
8599 | /* Emit function prologue as insns. */ |
8600 | ||
9878760c | 8601 | void |
83720594 | 8602 | rs6000_emit_prologue () |
9878760c | 8603 | { |
4697a36c | 8604 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
8605 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
8606 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
8607 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
8608 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
8609 | rtx frame_reg_rtx = sp_reg_rtx; | |
8610 | rtx cr_save_rtx = NULL; | |
8611 | rtx insn; | |
8612 | int saving_FPRs_inline; | |
8613 | int using_store_multiple; | |
8614 | HOST_WIDE_INT sp_offset = 0; | |
8615 | ||
8616 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
8617 | && info->first_gp_reg_save < 31); | |
8618 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8619 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
8620 | ||
8621 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
f607bc57 | 8622 | if (info->push_p && DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
8623 | { |
8624 | if (info->total_size < 32767) | |
8625 | sp_offset = info->total_size; | |
8626 | else | |
8627 | frame_reg_rtx = frame_ptr_rtx; | |
8628 | rs6000_emit_allocate_stack (info->total_size, | |
8629 | (frame_reg_rtx != sp_reg_rtx | |
8630 | && (info->cr_save_p | |
8631 | || info->lr_save_p | |
8632 | || info->first_fp_reg_save < 64 | |
8633 | || info->first_gp_reg_save < 32 | |
8634 | ))); | |
8635 | if (frame_reg_rtx != sp_reg_rtx) | |
8636 | rs6000_emit_stack_tie (); | |
8637 | } | |
8638 | ||
9aa86737 AH |
8639 | /* Save AltiVec registers if needed. */ |
8640 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
8641 | { | |
8642 | int i; | |
8643 | ||
8644 | /* There should be a non inline version of this, for when we | |
8645 | are saving lots of vector registers. */ | |
8646 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
8647 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
8648 | { | |
8649 | rtx areg, savereg, mem; | |
8650 | int offset; | |
8651 | ||
8652 | offset = info->altivec_save_offset + sp_offset | |
8653 | + 16 * (i - info->first_altivec_reg_save); | |
8654 | ||
8655 | savereg = gen_rtx_REG (V4SImode, i); | |
8656 | ||
8657 | areg = gen_rtx_REG (Pmode, 0); | |
8658 | emit_move_insn (areg, GEN_INT (offset)); | |
8659 | ||
8660 | /* AltiVec addressing mode is [reg+reg]. */ | |
8661 | mem = gen_rtx_MEM (V4SImode, | |
8662 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
8663 | ||
8664 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
8665 | ||
8666 | insn = emit_move_insn (mem, savereg); | |
8667 | ||
8668 | altivec_frame_fixup (insn, areg, offset); | |
8669 | } | |
8670 | } | |
8671 | ||
8672 | /* VRSAVE is a bit vector representing which AltiVec registers | |
8673 | are used. The OS uses this to determine which vector | |
8674 | registers to save on a context switch. We need to save | |
8675 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
8676 | used in this function, and do the corresponding magic in the | |
8677 | epilogue. */ | |
8678 | ||
8679 | if (TARGET_ALTIVEC && info->vrsave_mask != 0) | |
8680 | { | |
a004eb82 | 8681 | rtx reg, mem, vrsave; |
9aa86737 AH |
8682 | int offset; |
8683 | ||
8684 | /* Get VRSAVE onto a GPR. */ | |
8685 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 AH |
8686 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
8687 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
8688 | |
8689 | /* Save VRSAVE. */ | |
8690 | offset = info->vrsave_save_offset + sp_offset; | |
8691 | mem | |
8692 | = gen_rtx_MEM (SImode, | |
8693 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
8694 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
8695 | insn = emit_move_insn (mem, reg); | |
8696 | ||
8697 | /* Include the registers in the mask. */ | |
8698 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
8699 | ||
8700 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
8701 | } | |
8702 | ||
9ebbca7d GK |
8703 | /* If we use the link register, get it into r0. */ |
8704 | if (info->lr_save_p) | |
71f123ca | 8705 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
8706 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
8707 | ||
8708 | /* If we need to save CR, put it into r12. */ | |
8709 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
8710 | { | |
8711 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
8712 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
8713 | } | |
8714 | ||
a4f6c312 SS |
8715 | /* Do any required saving of fpr's. If only one or two to save, do |
8716 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
8717 | if (saving_FPRs_inline) |
8718 | { | |
8719 | int i; | |
8720 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
8721 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
8722 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
8723 | { | |
8724 | rtx addr, reg, mem; | |
8725 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
8726 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8727 | GEN_INT (info->fp_save_offset | |
8728 | + sp_offset | |
a4f6c312 | 8729 | + 8 * i)); |
9ebbca7d | 8730 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 8731 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8732 | |
8733 | insn = emit_move_insn (mem, reg); | |
8734 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8735 | NULL_RTX, NULL_RTX); | |
8736 | } | |
8737 | } | |
8738 | else if (info->first_fp_reg_save != 64) | |
8739 | { | |
8740 | int i; | |
8741 | char rname[30]; | |
520a57c8 | 8742 | const char *alloc_rname; |
9ebbca7d GK |
8743 | rtvec p; |
8744 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
8745 | ||
8746 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
8747 | gen_rtx_REG (Pmode, | |
8748 | LINK_REGISTER_REGNUM)); | |
8749 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
8750 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 8751 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
8752 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
8753 | gen_rtx_SYMBOL_REF (Pmode, | |
8754 | alloc_rname)); | |
8755 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
8756 | { | |
8757 | rtx addr, reg, mem; | |
8758 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
8759 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8760 | GEN_INT (info->fp_save_offset | |
8761 | + sp_offset + 8*i)); | |
8762 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 8763 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8764 | |
8765 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
8766 | } | |
8767 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
8768 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8769 | NULL_RTX, NULL_RTX); | |
8770 | } | |
b6c9286a | 8771 | |
9ebbca7d GK |
8772 | /* Save GPRs. This is done as a PARALLEL if we are using |
8773 | the store-multiple instructions. */ | |
8774 | if (using_store_multiple) | |
b6c9286a | 8775 | { |
9ebbca7d GK |
8776 | rtvec p, dwarfp; |
8777 | int i; | |
8778 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
8779 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
8780 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
8781 | { | |
8782 | rtx addr, reg, mem; | |
8783 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
8784 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8785 | GEN_INT (info->gp_save_offset | |
8786 | + sp_offset | |
8787 | + reg_size * i)); | |
8788 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 8789 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8790 | |
8791 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
8792 | } | |
8793 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
8794 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8795 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
8796 | } |
8797 | else | |
8798 | { | |
9ebbca7d GK |
8799 | int i; |
8800 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
8801 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
8802 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
8803 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
8804 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
8805 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
8806 | { |
8807 | rtx addr, reg, mem; | |
8808 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
8809 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8810 | GEN_INT (info->gp_save_offset | |
8811 | + sp_offset | |
8812 | + reg_size * i)); | |
8813 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 8814 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8815 | |
8816 | insn = emit_move_insn (mem, reg); | |
8817 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8818 | NULL_RTX, NULL_RTX); | |
8819 | } | |
8820 | } | |
8821 | ||
83720594 RH |
8822 | /* ??? There's no need to emit actual instructions here, but it's the |
8823 | easiest way to get the frame unwind information emitted. */ | |
8824 | if (current_function_calls_eh_return) | |
8825 | { | |
78e1b90d DE |
8826 | unsigned int i, regno; |
8827 | ||
83720594 RH |
8828 | for (i = 0; ; ++i) |
8829 | { | |
8830 | rtx addr, reg, mem; | |
8831 | ||
8832 | regno = EH_RETURN_DATA_REGNO (i); | |
8833 | if (regno == INVALID_REGNUM) | |
8834 | break; | |
8835 | ||
8836 | reg = gen_rtx_REG (reg_mode, regno); | |
8837 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
8838 | info->ehrd_offset + sp_offset |
8839 | + reg_size * (int) i); | |
83720594 | 8840 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 8841 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
8842 | |
8843 | insn = emit_move_insn (mem, reg); | |
8844 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8845 | NULL_RTX, NULL_RTX); | |
8846 | } | |
8847 | } | |
8848 | ||
9ebbca7d GK |
8849 | /* Save lr if we used it. */ |
8850 | if (info->lr_save_p) | |
8851 | { | |
8852 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8853 | GEN_INT (info->lr_save_offset + sp_offset)); | |
8854 | rtx reg = gen_rtx_REG (Pmode, 0); | |
8855 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
8856 | /* This should not be of rs6000_sr_alias_set, because of | |
8857 | __builtin_return_address. */ | |
8858 | ||
8859 | insn = emit_move_insn (mem, reg); | |
8860 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8861 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
8862 | } | |
8863 | ||
8864 | /* Save CR if we use any that must be preserved. */ | |
8865 | if (info->cr_save_p) | |
8866 | { | |
8867 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8868 | GEN_INT (info->cr_save_offset + sp_offset)); | |
8869 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
8870 | |
8871 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
8872 | |
8873 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
8874 | that it's free. */ | |
8875 | if (REGNO (frame_reg_rtx) == 12) | |
8876 | { | |
8877 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
8878 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
8879 | } | |
8880 | insn = emit_move_insn (mem, cr_save_rtx); | |
8881 | ||
8882 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
8883 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
8884 | OK. All we have to do is specify that _one_ condition code | |
8885 | register is saved in this stack slot. The thrower's epilogue | |
a1dc9455 FS |
8886 | will then restore all the call-saved registers. |
8887 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
9ebbca7d | 8888 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a1dc9455 | 8889 | cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO)); |
9ebbca7d GK |
8890 | } |
8891 | ||
8892 | /* Update stack and set back pointer unless this is V.4, | |
8893 | for which it was done previously. */ | |
f607bc57 | 8894 | if (info->push_p && DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
8895 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
8896 | ||
8897 | /* Set frame pointer, if needed. */ | |
8898 | if (frame_pointer_needed) | |
8899 | { | |
8900 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
8901 | sp_reg_rtx); | |
8902 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 8903 | } |
9878760c | 8904 | |
9ebbca7d GK |
8905 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
8906 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
f607bc57 ZW |
8907 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
8908 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
9ebbca7d GK |
8909 | { |
8910 | /* If emit_load_toc_table will use the link register, we need to save | |
8911 | it. We use R11 for this purpose because emit_load_toc_table | |
8912 | can use register 0. This allows us to use a plain 'blr' to return | |
8913 | from the procedure more often. */ | |
d5fa86ba GK |
8914 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 |
8915 | && ! info->lr_save_p | |
8916 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
8917 | if (save_LR_around_toc_setup) |
8918 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
8919 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
8920 | ||
8921 | rs6000_emit_load_toc_table (TRUE); | |
8922 | ||
8923 | if (save_LR_around_toc_setup) | |
8924 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
8925 | gen_rtx_REG (Pmode, 11)); | |
8926 | } | |
ee890fe2 SS |
8927 | |
8928 | if (DEFAULT_ABI == ABI_DARWIN | |
8929 | && flag_pic && current_function_uses_pic_offset_table) | |
8930 | { | |
8931 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
8932 | ||
8933 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); | |
8934 | ||
8935 | rs6000_maybe_dead ( | |
8936 | emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM), | |
8937 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); | |
8938 | } | |
9ebbca7d GK |
8939 | } |
8940 | ||
9ebbca7d | 8941 | /* Write function prologue. */ |
a4f6c312 | 8942 | |
08c148a8 NB |
8943 | static void |
8944 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 8945 | FILE *file; |
08c148a8 | 8946 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
8947 | { |
8948 | rs6000_stack_t *info = rs6000_stack_info (); | |
8949 | ||
4697a36c MM |
8950 | if (TARGET_DEBUG_STACK) |
8951 | debug_stack_info (info); | |
9878760c | 8952 | |
a4f6c312 SS |
8953 | /* Write .extern for any function we will call to save and restore |
8954 | fp values. */ | |
8955 | if (info->first_fp_reg_save < 64 | |
8956 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 8957 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 8958 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
8959 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
8960 | RESTORE_FP_SUFFIX); | |
9878760c | 8961 | |
c764f757 RK |
8962 | /* Write .extern for AIX common mode routines, if needed. */ |
8963 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
8964 | { | |
f6709c70 JW |
8965 | fputs ("\t.extern __mulh\n", file); |
8966 | fputs ("\t.extern __mull\n", file); | |
8967 | fputs ("\t.extern __divss\n", file); | |
8968 | fputs ("\t.extern __divus\n", file); | |
8969 | fputs ("\t.extern __quoss\n", file); | |
8970 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
8971 | common_mode_defined = 1; |
8972 | } | |
9878760c | 8973 | |
9ebbca7d | 8974 | if (! HAVE_prologue) |
979721f8 | 8975 | { |
9ebbca7d GK |
8976 | start_sequence (); |
8977 | ||
a4f6c312 SS |
8978 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
8979 | the "toplevel" insn chain. */ | |
9ebbca7d GK |
8980 | emit_note (0, NOTE_INSN_DELETED); |
8981 | rs6000_emit_prologue (); | |
8982 | emit_note (0, NOTE_INSN_DELETED); | |
8983 | ||
8984 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
8985 | debug_rtx_list (get_insns (), 100); |
8986 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 8987 | end_sequence (); |
979721f8 MM |
8988 | } |
8989 | ||
9ebbca7d GK |
8990 | rs6000_pic_labelno++; |
8991 | } | |
8992 | ||
8993 | /* Emit function epilogue as insns. | |
9878760c | 8994 | |
9ebbca7d GK |
8995 | At present, dwarf2out_frame_debug_expr doesn't understand |
8996 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
8997 | anywhere in the epilogue. Most of the insns below would in any case | |
8998 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 8999 | |
9ebbca7d | 9000 | void |
83720594 | 9001 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
9002 | int sibcall; |
9003 | { | |
9004 | rs6000_stack_t *info; | |
9005 | int restoring_FPRs_inline; | |
9006 | int using_load_multiple; | |
9007 | int using_mfcr_multiple; | |
9008 | int use_backchain_to_restore_sp; | |
9009 | int sp_offset = 0; | |
9010 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
9011 | rtx frame_reg_rtx = sp_reg_rtx; | |
9012 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
9013 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
9014 | int i; | |
9015 | ||
9016 | info = rs6000_stack_info (); | |
9017 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
9018 | && info->first_gp_reg_save < 31); | |
9019 | restoring_FPRs_inline = (sibcall | |
83720594 | 9020 | || current_function_calls_eh_return |
9ebbca7d GK |
9021 | || info->first_fp_reg_save == 64 |
9022 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
9023 | use_backchain_to_restore_sp = (frame_pointer_needed | |
9024 | || current_function_calls_alloca | |
9025 | || info->total_size > 32767); | |
9026 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
9027 | || rs6000_cpu == PROCESSOR_PPC603 | |
9028 | || rs6000_cpu == PROCESSOR_PPC750 | |
9029 | || optimize_size); | |
9030 | ||
9031 | /* If we have a frame pointer, a call to alloca, or a large stack | |
9032 | frame, restore the old stack pointer using the backchain. Otherwise, | |
9033 | we know what size to update it with. */ | |
9034 | if (use_backchain_to_restore_sp) | |
bacbde18 | 9035 | { |
9ebbca7d GK |
9036 | /* Under V.4, don't reset the stack pointer until after we're done |
9037 | loading the saved registers. */ | |
f607bc57 | 9038 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 9039 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 9040 | |
9ebbca7d GK |
9041 | emit_move_insn (frame_reg_rtx, |
9042 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
9043 | ||
bacbde18 | 9044 | } |
9ebbca7d | 9045 | else if (info->push_p) |
85638c0d | 9046 | { |
f607bc57 | 9047 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
9048 | sp_offset = info->total_size; |
9049 | else | |
9050 | { | |
9051 | emit_insn (TARGET_32BIT | |
9052 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
9053 | GEN_INT (info->total_size)) | |
9054 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
9055 | GEN_INT (info->total_size))); | |
9056 | } | |
85638c0d | 9057 | } |
9ebbca7d | 9058 | |
9aa86737 AH |
9059 | /* Restore AltiVec registers if needed. */ |
9060 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
9061 | { | |
9062 | int i; | |
9063 | ||
9064 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
9065 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
9066 | { | |
9067 | rtx addr, areg, mem; | |
9068 | ||
9069 | areg = gen_rtx_REG (Pmode, 0); | |
9070 | emit_move_insn | |
9071 | (areg, GEN_INT (info->altivec_save_offset | |
9072 | + sp_offset | |
9073 | + 16 * (i - info->first_altivec_reg_save))); | |
9074 | ||
9075 | /* AltiVec addressing mode is [reg+reg]. */ | |
9076 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
9077 | mem = gen_rtx_MEM (V4SImode, addr); | |
9078 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9079 | ||
9080 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
9081 | } | |
9082 | } | |
9083 | ||
9084 | /* Restore VRSAVE if needed. */ | |
9085 | if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0) | |
9086 | { | |
9087 | rtx addr, mem, reg; | |
9088 | ||
9089 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
9090 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
9091 | mem = gen_rtx_MEM (SImode, addr); | |
9092 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9093 | reg = gen_rtx_REG (SImode, 12); | |
9094 | emit_move_insn (reg, mem); | |
9095 | ||
9096 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
9097 | } | |
9098 | ||
9ebbca7d GK |
9099 | /* Get the old lr if we saved it. */ |
9100 | if (info->lr_save_p) | |
b6c9286a | 9101 | { |
9ebbca7d GK |
9102 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
9103 | GEN_INT (info->lr_save_offset + sp_offset)); | |
9104 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
ba4828e0 RK |
9105 | |
9106 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 9107 | |
9ebbca7d | 9108 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 9109 | } |
9ebbca7d GK |
9110 | |
9111 | /* Get the old cr if we saved it. */ | |
9112 | if (info->cr_save_p) | |
9113 | { | |
9114 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
9115 | GEN_INT (info->cr_save_offset + sp_offset)); | |
9116 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
9117 | |
9118 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 9119 | |
9ebbca7d GK |
9120 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
9121 | } | |
9122 | ||
9123 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 9124 | if (info->lr_save_p) |
9ebbca7d GK |
9125 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
9126 | gen_rtx_REG (Pmode, 0)); | |
9127 | ||
83720594 RH |
9128 | /* Load exception handler data registers, if needed. */ |
9129 | if (current_function_calls_eh_return) | |
9130 | { | |
78e1b90d DE |
9131 | unsigned int i, regno; |
9132 | ||
83720594 RH |
9133 | for (i = 0; ; ++i) |
9134 | { | |
9135 | rtx addr, mem; | |
9136 | ||
9137 | regno = EH_RETURN_DATA_REGNO (i); | |
9138 | if (regno == INVALID_REGNUM) | |
9139 | break; | |
9140 | ||
9141 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
9142 | info->ehrd_offset + sp_offset |
9143 | + reg_size * (int) i); | |
83720594 | 9144 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 9145 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
9146 | |
9147 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
9148 | } | |
9149 | } | |
9ebbca7d GK |
9150 | |
9151 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
9152 | the load-multiple instructions. */ | |
9153 | if (using_load_multiple) | |
979721f8 | 9154 | { |
9ebbca7d GK |
9155 | rtvec p; |
9156 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9157 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 9158 | { |
9ebbca7d GK |
9159 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
9160 | GEN_INT (info->gp_save_offset | |
9161 | + sp_offset | |
9162 | + reg_size * i)); | |
9163 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
9164 | |
9165 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
9166 | |
9167 | RTVEC_ELT (p, i) = | |
9168 | gen_rtx_SET (VOIDmode, | |
9169 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
9170 | mem); | |
979721f8 | 9171 | } |
9ebbca7d | 9172 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 9173 | } |
9ebbca7d GK |
9174 | else |
9175 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
9176 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
9177 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
9178 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
9179 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
9180 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
9181 | { |
9182 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
9183 | GEN_INT (info->gp_save_offset | |
9184 | + sp_offset | |
9185 | + reg_size * i)); | |
9186 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
9187 | |
9188 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
9189 | |
9190 | emit_move_insn (gen_rtx_REG (reg_mode, | |
9191 | info->first_gp_reg_save + i), | |
9192 | mem); | |
9193 | } | |
9878760c | 9194 | |
9ebbca7d GK |
9195 | /* Restore fpr's if we need to do it without calling a function. */ |
9196 | if (restoring_FPRs_inline) | |
9197 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
9198 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
9199 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
9200 | { | |
9201 | rtx addr, mem; | |
9202 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
9203 | GEN_INT (info->fp_save_offset | |
9204 | + sp_offset | |
a4f6c312 | 9205 | + 8 * i)); |
9ebbca7d | 9206 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 9207 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
9208 | |
9209 | emit_move_insn (gen_rtx_REG (DFmode, | |
9210 | info->first_fp_reg_save + i), | |
9211 | mem); | |
9212 | } | |
8d30c4ee | 9213 | |
9ebbca7d GK |
9214 | /* If we saved cr, restore it here. Just those that were used. */ |
9215 | if (info->cr_save_p) | |
979721f8 | 9216 | { |
9ebbca7d | 9217 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 9218 | int count = 0; |
9ebbca7d GK |
9219 | |
9220 | if (using_mfcr_multiple) | |
979721f8 | 9221 | { |
9ebbca7d GK |
9222 | for (i = 0; i < 8; i++) |
9223 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 9224 | count++; |
9ebbca7d | 9225 | if (count == 0) |
e35b9579 GK |
9226 | abort (); |
9227 | } | |
9228 | ||
9229 | if (using_mfcr_multiple && count > 1) | |
9230 | { | |
9231 | rtvec p; | |
9232 | int ndx; | |
9ebbca7d | 9233 | |
e35b9579 | 9234 | p = rtvec_alloc (count); |
9ebbca7d | 9235 | |
e35b9579 | 9236 | ndx = 0; |
9ebbca7d GK |
9237 | for (i = 0; i < 8; i++) |
9238 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
9239 | { | |
9240 | rtvec r = rtvec_alloc (2); | |
9241 | RTVEC_ELT (r, 0) = r12_rtx; | |
9242 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 9243 | RTVEC_ELT (p, ndx) = |
9ebbca7d GK |
9244 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
9245 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
e35b9579 | 9246 | ndx++; |
9ebbca7d GK |
9247 | } |
9248 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
9249 | if (ndx != count) |
9250 | abort (); | |
979721f8 MM |
9251 | } |
9252 | else | |
9ebbca7d GK |
9253 | for (i = 0; i < 8; i++) |
9254 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 9255 | { |
9ebbca7d GK |
9256 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
9257 | CR0_REGNO+i), | |
9258 | r12_rtx)); | |
979721f8 | 9259 | } |
979721f8 MM |
9260 | } |
9261 | ||
9ebbca7d GK |
9262 | /* If this is V.4, unwind the stack pointer after all of the loads |
9263 | have been done. We need to emit a block here so that sched | |
9264 | doesn't decide to move the sp change before the register restores | |
9265 | (which may not have any obvious dependency on the stack). This | |
9266 | doesn't hurt performance, because there is no scheduling that can | |
9267 | be done after this point. */ | |
f607bc57 | 9268 | if (DEFAULT_ABI == ABI_V4) |
b6c9286a | 9269 | { |
9ebbca7d GK |
9270 | if (frame_reg_rtx != sp_reg_rtx) |
9271 | rs6000_emit_stack_tie (); | |
b6c9286a | 9272 | |
9ebbca7d | 9273 | if (use_backchain_to_restore_sp) |
b6c9286a | 9274 | { |
9ebbca7d | 9275 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 9276 | } |
9ebbca7d | 9277 | else if (sp_offset != 0) |
13f1623b | 9278 | { |
9ebbca7d GK |
9279 | emit_insn (Pmode == SImode |
9280 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
9281 | GEN_INT (sp_offset)) | |
9282 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
9283 | GEN_INT (sp_offset))); | |
13f1623b | 9284 | } |
9ebbca7d | 9285 | } |
b6c9286a | 9286 | |
83720594 RH |
9287 | if (current_function_calls_eh_return) |
9288 | { | |
9289 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
9290 | emit_insn (Pmode == SImode | |
9291 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) | |
9292 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
9293 | } | |
9294 | ||
9ebbca7d GK |
9295 | if (!sibcall) |
9296 | { | |
9297 | rtvec p; | |
9298 | if (! restoring_FPRs_inline) | |
9299 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
9300 | else | |
9301 | p = rtvec_alloc (2); | |
b6c9286a | 9302 | |
e35b9579 GK |
9303 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
9304 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
9305 | gen_rtx_REG (Pmode, |
9306 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
9307 | |
9308 | /* If we have to restore more than two FP registers, branch to the | |
9309 | restore function. It will return to our caller. */ | |
9310 | if (! restoring_FPRs_inline) | |
9311 | { | |
9312 | int i; | |
9313 | char rname[30]; | |
520a57c8 | 9314 | const char *alloc_rname; |
979721f8 | 9315 | |
9ebbca7d GK |
9316 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
9317 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 9318 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
9319 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
9320 | gen_rtx_SYMBOL_REF (Pmode, | |
9321 | alloc_rname)); | |
b6c9286a | 9322 | |
9ebbca7d GK |
9323 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
9324 | { | |
9325 | rtx addr, mem; | |
9326 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
9327 | GEN_INT (info->fp_save_offset + 8*i)); | |
9328 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 9329 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
9330 | |
9331 | RTVEC_ELT (p, i+3) = | |
9332 | gen_rtx_SET (VOIDmode, | |
9333 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
9334 | mem); | |
b6c9286a MM |
9335 | } |
9336 | } | |
9ebbca7d GK |
9337 | |
9338 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 9339 | } |
9878760c RK |
9340 | } |
9341 | ||
9342 | /* Write function epilogue. */ | |
9343 | ||
08c148a8 NB |
9344 | static void |
9345 | rs6000_output_function_epilogue (file, size) | |
9878760c | 9346 | FILE *file; |
08c148a8 | 9347 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 9348 | { |
4697a36c | 9349 | rs6000_stack_t *info = rs6000_stack_info (); |
6041bf2f | 9350 | int optional_tbtab = (optimize_size || TARGET_ELF) ? 0 : 1; |
9878760c | 9351 | |
9ebbca7d | 9352 | if (! HAVE_epilogue) |
9878760c | 9353 | { |
9ebbca7d GK |
9354 | rtx insn = get_last_insn (); |
9355 | /* If the last insn was a BARRIER, we don't have to write anything except | |
9356 | the trace table. */ | |
9357 | if (GET_CODE (insn) == NOTE) | |
9358 | insn = prev_nonnote_insn (insn); | |
9359 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 9360 | { |
9ebbca7d GK |
9361 | /* This is slightly ugly, but at least we don't have two |
9362 | copies of the epilogue-emitting code. */ | |
9363 | start_sequence (); | |
9364 | ||
9365 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
9366 | and end of the "toplevel" insn chain. */ | |
9367 | emit_note (0, NOTE_INSN_DELETED); | |
9368 | rs6000_emit_epilogue (FALSE); | |
9369 | emit_note (0, NOTE_INSN_DELETED); | |
9370 | ||
9371 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
9372 | debug_rtx_list (get_insns (), 100); |
9373 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 9374 | end_sequence (); |
4697a36c | 9375 | } |
9878760c | 9376 | } |
b4ac57ab | 9377 | |
9b30bae2 | 9378 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
9379 | on its format. |
9380 | ||
9381 | We don't output a traceback table if -finhibit-size-directive was | |
9382 | used. The documentation for -finhibit-size-directive reads | |
9383 | ``don't output a @code{.size} assembler directive, or anything | |
9384 | else that would cause trouble if the function is split in the | |
9385 | middle, and the two halves are placed at locations far apart in | |
9386 | memory.'' The traceback table has this property, since it | |
9387 | includes the offset from the start of the function to the | |
4d30c363 MM |
9388 | traceback table itself. |
9389 | ||
9390 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
9391 | different traceback table. */ |
9392 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 9393 | { |
3cce094d | 9394 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
3ac88239 | 9395 | const char *language_string = lang_hooks.name; |
6041bf2f | 9396 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 ILT |
9397 | int i; |
9398 | ||
b6c9286a MM |
9399 | while (*fname == '.') /* V.4 encodes . in the name */ |
9400 | fname++; | |
9401 | ||
314fc5a9 ILT |
9402 | /* Need label immediately before tbtab, so we can compute its offset |
9403 | from the function start. */ | |
9404 | if (*fname == '*') | |
9405 | ++fname; | |
9406 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
9407 | ASM_OUTPUT_LABEL (file, fname); | |
9408 | ||
9409 | /* The .tbtab pseudo-op can only be used for the first eight | |
9410 | expressions, since it can't handle the possibly variable | |
9411 | length fields that follow. However, if you omit the optional | |
9412 | fields, the assembler outputs zeros for all optional fields | |
9413 | anyways, giving each variable length field is minimum length | |
9414 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
9415 | pseudo-op at all. */ | |
9416 | ||
9417 | /* An all-zero word flags the start of the tbtab, for debuggers | |
9418 | that have to find it by searching forward from the entry | |
9419 | point or from the current pc. */ | |
19d2d16f | 9420 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
9421 | |
9422 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 9423 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
9424 | |
9425 | /* Language type. Unfortunately, there doesn't seem to be any | |
9426 | official way to get this info, so we use language_string. C | |
9427 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 9428 | value for C for now. There is no official value for Java, |
6f573ff9 | 9429 | although IBM appears to be using 13. There is no official value |
f710504c | 9430 | for Chill, so we've chosen 44 pseudo-randomly. */ |
314fc5a9 | 9431 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 9432 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
9433 | i = 0; |
9434 | else if (! strcmp (language_string, "GNU F77")) | |
9435 | i = 1; | |
9436 | else if (! strcmp (language_string, "GNU Ada")) | |
9437 | i = 3; | |
8b83775b | 9438 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
9439 | i = 2; |
9440 | else if (! strcmp (language_string, "GNU C++")) | |
9441 | i = 9; | |
9517ead8 AG |
9442 | else if (! strcmp (language_string, "GNU Java")) |
9443 | i = 13; | |
6f573ff9 JL |
9444 | else if (! strcmp (language_string, "GNU CHILL")) |
9445 | i = 44; | |
314fc5a9 ILT |
9446 | else |
9447 | abort (); | |
9448 | fprintf (file, "%d,", i); | |
9449 | ||
9450 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
9451 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
9452 | from start of procedure stored in tbtab, internal function, function | |
9453 | has controlled storage, function has no toc, function uses fp, | |
9454 | function logs/aborts fp operations. */ | |
9455 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
9456 | fprintf (file, "%d,", |
9457 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
9458 | |
9459 | /* 6 bitfields: function is interrupt handler, name present in | |
9460 | proc table, function calls alloca, on condition directives | |
9461 | (controls stack walks, 3 bits), saves condition reg, saves | |
9462 | link reg. */ | |
9463 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
9464 | set up as a frame pointer, even when there is no alloca call. */ | |
9465 | fprintf (file, "%d,", | |
6041bf2f DE |
9466 | ((optional_tbtab << 6) |
9467 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
9468 | | (info->cr_save_p << 1) | |
9469 | | (info->lr_save_p))); | |
314fc5a9 | 9470 | |
6041bf2f | 9471 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
9472 | (6 bits). */ |
9473 | fprintf (file, "%d,", | |
4697a36c | 9474 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
9475 | |
9476 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
9477 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
9478 | ||
6041bf2f DE |
9479 | if (optional_tbtab) |
9480 | { | |
9481 | /* Compute the parameter info from the function decl argument | |
9482 | list. */ | |
9483 | tree decl; | |
9484 | int next_parm_info_bit = 31; | |
314fc5a9 | 9485 | |
6041bf2f DE |
9486 | for (decl = DECL_ARGUMENTS (current_function_decl); |
9487 | decl; decl = TREE_CHAIN (decl)) | |
9488 | { | |
9489 | rtx parameter = DECL_INCOMING_RTL (decl); | |
9490 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 9491 | |
6041bf2f DE |
9492 | if (GET_CODE (parameter) == REG) |
9493 | { | |
9494 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
9495 | { | |
9496 | int bits; | |
9497 | ||
9498 | float_parms++; | |
9499 | ||
9500 | if (mode == SFmode) | |
9501 | bits = 0x2; | |
9502 | else if (mode == DFmode) | |
9503 | bits = 0x3; | |
9504 | else | |
9505 | abort (); | |
9506 | ||
9507 | /* If only one bit will fit, don't or in this entry. */ | |
9508 | if (next_parm_info_bit > 0) | |
9509 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
9510 | next_parm_info_bit -= 2; | |
9511 | } | |
9512 | else | |
9513 | { | |
9514 | fixed_parms += ((GET_MODE_SIZE (mode) | |
9515 | + (UNITS_PER_WORD - 1)) | |
9516 | / UNITS_PER_WORD); | |
9517 | next_parm_info_bit -= 1; | |
9518 | } | |
9519 | } | |
9520 | } | |
9521 | } | |
314fc5a9 ILT |
9522 | |
9523 | /* Number of fixed point parameters. */ | |
9524 | /* This is actually the number of words of fixed point parameters; thus | |
9525 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
9526 | fprintf (file, "%d,", fixed_parms); | |
9527 | ||
9528 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
9529 | all on stack. */ | |
9530 | /* This is actually the number of fp registers that hold parameters; | |
9531 | and thus the maximum value is 13. */ | |
9532 | /* Set parameters on stack bit if parameters are not in their original | |
9533 | registers, regardless of whether they are on the stack? Xlc | |
9534 | seems to set the bit when not optimizing. */ | |
9535 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
9536 | ||
6041bf2f DE |
9537 | if (! optional_tbtab) |
9538 | return; | |
9539 | ||
314fc5a9 ILT |
9540 | /* Optional fields follow. Some are variable length. */ |
9541 | ||
9542 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
9543 | 11 double float. */ | |
9544 | /* There is an entry for each parameter in a register, in the order that | |
9545 | they occur in the parameter list. Any intervening arguments on the | |
9546 | stack are ignored. If the list overflows a long (max possible length | |
9547 | 34 bits) then completely leave off all elements that don't fit. */ | |
9548 | /* Only emit this long if there was at least one parameter. */ | |
9549 | if (fixed_parms || float_parms) | |
9550 | fprintf (file, "\t.long %d\n", parm_info); | |
9551 | ||
9552 | /* Offset from start of code to tb table. */ | |
19d2d16f | 9553 | fputs ("\t.long ", file); |
314fc5a9 | 9554 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
9555 | #if TARGET_AIX |
9556 | RS6000_OUTPUT_BASENAME (file, fname); | |
9557 | #else | |
9ebbca7d | 9558 | assemble_name (file, fname); |
54ee9799 | 9559 | #endif |
19d2d16f | 9560 | fputs ("-.", file); |
54ee9799 DE |
9561 | #if TARGET_AIX |
9562 | RS6000_OUTPUT_BASENAME (file, fname); | |
9563 | #else | |
9ebbca7d | 9564 | assemble_name (file, fname); |
54ee9799 | 9565 | #endif |
19d2d16f | 9566 | putc ('\n', file); |
314fc5a9 ILT |
9567 | |
9568 | /* Interrupt handler mask. */ | |
9569 | /* Omit this long, since we never set the interrupt handler bit | |
9570 | above. */ | |
9571 | ||
9572 | /* Number of CTL (controlled storage) anchors. */ | |
9573 | /* Omit this long, since the has_ctl bit is never set above. */ | |
9574 | ||
9575 | /* Displacement into stack of each CTL anchor. */ | |
9576 | /* Omit this list of longs, because there are no CTL anchors. */ | |
9577 | ||
9578 | /* Length of function name. */ | |
296b8152 | 9579 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
9580 | |
9581 | /* Function name. */ | |
9582 | assemble_string (fname, strlen (fname)); | |
9583 | ||
9584 | /* Register for alloca automatic storage; this is always reg 31. | |
9585 | Only emit this if the alloca bit was set above. */ | |
9586 | if (frame_pointer_needed) | |
19d2d16f | 9587 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 9588 | } |
6041bf2f | 9589 | return; |
9878760c | 9590 | } |
17167fd8 | 9591 | \f |
a4f6c312 SS |
9592 | /* A C compound statement that outputs the assembler code for a thunk |
9593 | function, used to implement C++ virtual function calls with | |
9594 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
9595 | function, adjusting the implicit object parameter before handing | |
9596 | control off to the real function. | |
9597 | ||
9598 | First, emit code to add the integer DELTA to the location that | |
9599 | contains the incoming first argument. Assume that this argument | |
9600 | contains a pointer, and is the one used to pass the `this' pointer | |
9601 | in C++. This is the incoming argument *before* the function | |
9602 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
9603 | values of all other incoming arguments. | |
17167fd8 MM |
9604 | |
9605 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
9606 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
9607 | not touch the return address. Hence returning from FUNCTION will | |
9608 | return to whoever called the current `thunk'. | |
17167fd8 | 9609 | |
a4f6c312 SS |
9610 | The effect must be as if FUNCTION had been called directly with the |
9611 | adjusted first argument. This macro is responsible for emitting | |
9612 | all of the code for a thunk function; output_function_prologue() | |
9613 | and output_function_epilogue() are not invoked. | |
17167fd8 | 9614 | |
a4f6c312 SS |
9615 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
9616 | been extracted from it.) It might possibly be useful on some | |
9617 | targets, but probably not. | |
17167fd8 | 9618 | |
a4f6c312 SS |
9619 | If you do not define this macro, the target-independent code in the |
9620 | C++ frontend will generate a less efficient heavyweight thunk that | |
9621 | calls FUNCTION instead of jumping to it. The generic approach does | |
9622 | not support varargs. */ | |
17167fd8 MM |
9623 | |
9624 | void | |
9625 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
9626 | FILE *file; | |
d330fd93 | 9627 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
9628 | int delta; |
9629 | tree function; | |
9630 | { | |
a4f6c312 SS |
9631 | const char *this_reg = |
9632 | reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; | |
d330fd93 | 9633 | const char *prefix; |
3cce094d | 9634 | const char *fname; |
d330fd93 | 9635 | const char *r0 = reg_names[0]; |
d330fd93 KG |
9636 | const char *toc = reg_names[2]; |
9637 | const char *schain = reg_names[11]; | |
9638 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
9639 | char buf[512]; |
9640 | static int labelno = 0; | |
9641 | ||
a4f6c312 | 9642 | /* Small constants that can be done by one add instruction. */ |
17167fd8 MM |
9643 | if (delta >= -32768 && delta <= 32767) |
9644 | { | |
22b4a3b0 | 9645 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
9646 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
9647 | else | |
9648 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
9649 | } | |
9650 | ||
a4f6c312 | 9651 | /* Large constants that can be done by one addis instruction. */ |
17167fd8 MM |
9652 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) |
9653 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
9654 | delta >> 16); | |
9655 | ||
9656 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
9657 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
9658 | { | |
a4f6c312 SS |
9659 | /* Break into two pieces, propagating the sign bit from the low |
9660 | word to the upper word. */ | |
17167fd8 MM |
9661 | int delta_high = delta >> 16; |
9662 | int delta_low = delta & 0xffff; | |
9663 | if ((delta_low & 0x8000) != 0) | |
9664 | { | |
9665 | delta_high++; | |
9666 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
9667 | } | |
9668 | ||
9669 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
9670 | delta_high); | |
9671 | ||
22b4a3b0 | 9672 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
9673 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
9674 | else | |
9675 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
9676 | } | |
9677 | ||
9678 | /* 64-bit constants, fixme */ | |
9679 | else | |
9680 | abort (); | |
9681 | ||
9682 | /* Get the prefix in front of the names. */ | |
9683 | switch (DEFAULT_ABI) | |
9684 | { | |
9685 | default: | |
9686 | abort (); | |
9687 | ||
9688 | case ABI_AIX: | |
9689 | prefix = "."; | |
9690 | break; | |
9691 | ||
9692 | case ABI_V4: | |
9693 | case ABI_AIX_NODESC: | |
17167fd8 MM |
9694 | prefix = ""; |
9695 | break; | |
17167fd8 MM |
9696 | } |
9697 | ||
9698 | /* If the function is compiled in this module, jump to it directly. | |
9699 | Otherwise, load up its address and jump to it. */ | |
9700 | ||
9701 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 9702 | |
9ebbca7d | 9703 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
9704 | && ! lookup_attribute ("longcall", |
9705 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
9706 | { |
9707 | fprintf (file, "\tb %s", prefix); | |
9708 | assemble_name (file, fname); | |
22b4a3b0 | 9709 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 9710 | putc ('\n', file); |
17167fd8 MM |
9711 | } |
9712 | ||
9713 | else | |
9714 | { | |
9715 | switch (DEFAULT_ABI) | |
9716 | { | |
9717 | default: | |
17167fd8 MM |
9718 | abort (); |
9719 | ||
9720 | case ABI_AIX: | |
9721 | /* Set up a TOC entry for the function. */ | |
9722 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
9723 | toc_section (); | |
9724 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
9725 | labelno++; | |
9726 | ||
fa9b5c6b DE |
9727 | if (TARGET_MINIMAL_TOC) |
9728 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); | |
9729 | else | |
9730 | { | |
9731 | fputs ("\t.tc ", file); | |
9732 | assemble_name (file, fname); | |
9733 | fputs ("[TC],", file); | |
9734 | } | |
9735 | assemble_name (file, fname); | |
17167fd8 MM |
9736 | putc ('\n', file); |
9737 | text_section (); | |
468e8dba DE |
9738 | if (TARGET_MINIMAL_TOC) |
9739 | asm_fprintf (file, (TARGET_32BIT) | |
9740 | ? "\t{l|lwz} %s,%s(%s)\n" : "\tld %s,%s(%s)\n", r12, | |
9741 | TARGET_ELF ? ".LCTOC0@toc" : ".LCTOC..1", toc); | |
d2574c50 | 9742 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s,", r12); |
17167fd8 | 9743 | assemble_name (file, buf); |
468e8dba DE |
9744 | if (TARGET_ELF && TARGET_MINIMAL_TOC) |
9745 | fputs ("-(.LCTOC1)", file); | |
9746 | asm_fprintf (file, "(%s)\n", TARGET_MINIMAL_TOC ? r12 : toc); | |
17167fd8 MM |
9747 | asm_fprintf (file, |
9748 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
9749 | r0, r12); | |
9750 | ||
9751 | asm_fprintf (file, | |
9752 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
9753 | toc, r12); | |
9754 | ||
9755 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
9756 | asm_fprintf (file, | |
9757 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
9758 | schain, r12); | |
9759 | ||
9760 | asm_fprintf (file, "\tbctr\n"); | |
9761 | break; | |
9762 | ||
9ebbca7d | 9763 | case ABI_AIX_NODESC: |
17167fd8 | 9764 | case ABI_V4: |
22b4a3b0 FS |
9765 | fprintf (file, "\tb %s", prefix); |
9766 | assemble_name (file, fname); | |
9767 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 9768 | putc ('\n', file); |
22b4a3b0 | 9769 | break; |
ee890fe2 SS |
9770 | |
9771 | #if TARGET_MACHO | |
9772 | case ABI_DARWIN: | |
9773 | fprintf (file, "\tb %s", prefix); | |
9774 | if (flag_pic && !machopic_name_defined_p (fname)) | |
9775 | assemble_name (file, machopic_stub_name (fname)); | |
9776 | else | |
9777 | assemble_name (file, fname); | |
9778 | putc ('\n', file); | |
9779 | break; | |
9780 | #endif | |
9ebbca7d GK |
9781 | } |
9782 | } | |
9783 | } | |
42820a49 | 9784 | |
9ebbca7d GK |
9785 | \f |
9786 | /* A quick summary of the various types of 'constant-pool tables' | |
9787 | under PowerPC: | |
9788 | ||
9789 | Target Flags Name One table per | |
9790 | AIX (none) AIX TOC object file | |
9791 | AIX -mfull-toc AIX TOC object file | |
9792 | AIX -mminimal-toc AIX minimal TOC translation unit | |
9793 | SVR4/EABI (none) SVR4 SDATA object file | |
9794 | SVR4/EABI -fpic SVR4 pic object file | |
9795 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
9796 | SVR4/EABI -mrelocatable EABI TOC function | |
9797 | SVR4/EABI -maix AIX TOC object file | |
9798 | SVR4/EABI -maix -mminimal-toc | |
9799 | AIX minimal TOC translation unit | |
9800 | ||
9801 | Name Reg. Set by entries contains: | |
9802 | made by addrs? fp? sum? | |
9803 | ||
9804 | AIX TOC 2 crt0 as Y option option | |
9805 | AIX minimal TOC 30 prolog gcc Y Y option | |
9806 | SVR4 SDATA 13 crt0 gcc N Y N | |
9807 | SVR4 pic 30 prolog ld Y not yet N | |
9808 | SVR4 PIC 30 prolog gcc Y option option | |
9809 | EABI TOC 30 prolog gcc Y option option | |
9810 | ||
9811 | */ | |
9812 | ||
9813 | /* Hash table stuff for keeping track of TOC entries. */ | |
9814 | ||
9815 | struct toc_hash_struct | |
9816 | { | |
9817 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
9818 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
9819 | rtx key; | |
a9098fd0 | 9820 | enum machine_mode key_mode; |
9ebbca7d GK |
9821 | int labelno; |
9822 | }; | |
17167fd8 | 9823 | |
9ebbca7d GK |
9824 | static htab_t toc_hash_table; |
9825 | ||
9826 | /* Hash functions for the hash table. */ | |
9827 | ||
9828 | static unsigned | |
9829 | rs6000_hash_constant (k) | |
9830 | rtx k; | |
9831 | { | |
a9098fd0 | 9832 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
9833 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
9834 | int flen = strlen (format); | |
9835 | int fidx; | |
9836 | ||
9837 | if (GET_CODE (k) == LABEL_REF) | |
832ea3b3 | 9838 | return result * 1231 + X0INT (XEXP (k, 0), 3); |
9ebbca7d GK |
9839 | |
9840 | if (GET_CODE (k) == CONST_DOUBLE) | |
592bf28c | 9841 | fidx = 1; |
9ebbca7d GK |
9842 | else if (GET_CODE (k) == CODE_LABEL) |
9843 | fidx = 3; | |
9844 | else | |
9845 | fidx = 0; | |
9846 | ||
9847 | for (; fidx < flen; fidx++) | |
9848 | switch (format[fidx]) | |
9849 | { | |
9850 | case 's': | |
9851 | { | |
9852 | unsigned i, len; | |
9853 | const char *str = XSTR (k, fidx); | |
9854 | len = strlen (str); | |
9855 | result = result * 613 + len; | |
9856 | for (i = 0; i < len; i++) | |
9857 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
9858 | break; |
9859 | } | |
9ebbca7d GK |
9860 | case 'u': |
9861 | case 'e': | |
9862 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
9863 | break; | |
9864 | case 'i': | |
9865 | case 'n': | |
9866 | result = result * 613 + (unsigned) XINT (k, fidx); | |
9867 | break; | |
9868 | case 'w': | |
9869 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
9870 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
9871 | else | |
9872 | { | |
9873 | size_t i; | |
9874 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
9875 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
9876 | >> CHAR_BIT * i); | |
9877 | } | |
9878 | break; | |
9879 | default: | |
a4f6c312 | 9880 | abort (); |
9ebbca7d GK |
9881 | } |
9882 | return result; | |
9883 | } | |
9884 | ||
9885 | static unsigned | |
9886 | toc_hash_function (hash_entry) | |
9887 | const void * hash_entry; | |
9888 | { | |
a9098fd0 GK |
9889 | const struct toc_hash_struct *thc = |
9890 | (const struct toc_hash_struct *) hash_entry; | |
9891 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
9892 | } |
9893 | ||
9894 | /* Compare H1 and H2 for equivalence. */ | |
9895 | ||
9896 | static int | |
9897 | toc_hash_eq (h1, h2) | |
9898 | const void * h1; | |
9899 | const void * h2; | |
9900 | { | |
9901 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
9902 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
9903 | ||
a9098fd0 GK |
9904 | if (((const struct toc_hash_struct *) h1)->key_mode |
9905 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
9906 | return 0; | |
9907 | ||
9ebbca7d GK |
9908 | /* Gotcha: One of these const_doubles will be in memory. |
9909 | The other may be on the constant-pool chain. | |
a4f6c312 | 9910 | So rtx_equal_p will think they are different... */ |
9ebbca7d GK |
9911 | if (r1 == r2) |
9912 | return 1; | |
9913 | if (GET_CODE (r1) != GET_CODE (r2) | |
9914 | || GET_MODE (r1) != GET_MODE (r2)) | |
9915 | return 0; | |
9916 | if (GET_CODE (r1) == CONST_DOUBLE) | |
9917 | { | |
9918 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
9919 | int i; | |
592bf28c | 9920 | for (i = 1; i < format_len; i++) |
9ebbca7d GK |
9921 | if (XWINT (r1, i) != XWINT (r2, i)) |
9922 | return 0; | |
9923 | ||
9924 | return 1; | |
17167fd8 | 9925 | } |
9ebbca7d | 9926 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
9927 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
9928 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
9929 | else |
9930 | return rtx_equal_p (r1, r2); | |
9931 | } | |
9932 | ||
9933 | /* Mark the hash table-entry HASH_ENTRY. */ | |
9934 | ||
9935 | static int | |
9936 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 9937 | void ** hash_slot; |
9ebbca7d GK |
9938 | void * unused ATTRIBUTE_UNUSED; |
9939 | { | |
9940 | const struct toc_hash_struct * hash_entry = | |
9941 | *(const struct toc_hash_struct **) hash_slot; | |
9942 | rtx r = hash_entry->key; | |
9943 | ggc_set_mark (hash_entry); | |
a4f6c312 | 9944 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ |
9ebbca7d GK |
9945 | if (GET_CODE (r) == LABEL_REF) |
9946 | { | |
9947 | ggc_set_mark (r); | |
9948 | ggc_set_mark (XEXP (r, 0)); | |
9949 | } | |
9950 | else | |
9951 | ggc_mark_rtx (r); | |
9952 | return 1; | |
9953 | } | |
9954 | ||
9955 | /* Mark all the elements of the TOC hash-table *HT. */ | |
9956 | ||
9957 | static void | |
9958 | toc_hash_mark_table (vht) | |
9959 | void *vht; | |
9960 | { | |
9961 | htab_t *ht = vht; | |
9962 | ||
9963 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
9964 | } |
9965 | ||
28e510bd MM |
9966 | /* These are the names given by the C++ front-end to vtables, and |
9967 | vtable-like objects. Ideally, this logic should not be here; | |
9968 | instead, there should be some programmatic way of inquiring as | |
9969 | to whether or not an object is a vtable. */ | |
9970 | ||
9971 | #define VTABLE_NAME_P(NAME) \ | |
9972 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
9973 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
9974 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
9975 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
9976 | ||
9977 | void | |
9978 | rs6000_output_symbol_ref (file, x) | |
9979 | FILE *file; | |
9980 | rtx x; | |
9981 | { | |
9982 | /* Currently C++ toc references to vtables can be emitted before it | |
9983 | is decided whether the vtable is public or private. If this is | |
9984 | the case, then the linker will eventually complain that there is | |
9985 | a reference to an unknown section. Thus, for vtables only, | |
9986 | we emit the TOC reference to reference the symbol and not the | |
9987 | section. */ | |
9988 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
9989 | |
9990 | if (VTABLE_NAME_P (name)) | |
9991 | { | |
9992 | RS6000_OUTPUT_BASENAME (file, name); | |
9993 | } | |
9994 | else | |
9995 | assemble_name (file, name); | |
28e510bd MM |
9996 | } |
9997 | ||
a4f6c312 SS |
9998 | /* Output a TOC entry. We derive the entry name from what is being |
9999 | written. */ | |
9878760c RK |
10000 | |
10001 | void | |
a9098fd0 | 10002 | output_toc (file, x, labelno, mode) |
9878760c RK |
10003 | FILE *file; |
10004 | rtx x; | |
10005 | int labelno; | |
a9098fd0 | 10006 | enum machine_mode mode; |
9878760c RK |
10007 | { |
10008 | char buf[256]; | |
3cce094d | 10009 | const char *name = buf; |
ec940faa | 10010 | const char *real_name; |
9878760c RK |
10011 | rtx base = x; |
10012 | int offset = 0; | |
10013 | ||
4697a36c MM |
10014 | if (TARGET_NO_TOC) |
10015 | abort (); | |
10016 | ||
9ebbca7d GK |
10017 | /* When the linker won't eliminate them, don't output duplicate |
10018 | TOC entries (this happens on AIX if there is any kind of TOC, | |
1f8f4a0b MM |
10019 | and on SVR4 under -fPIC or -mrelocatable). */ |
10020 | if (TARGET_TOC) | |
9ebbca7d GK |
10021 | { |
10022 | struct toc_hash_struct *h; | |
10023 | void * * found; | |
10024 | ||
10025 | h = ggc_alloc (sizeof (*h)); | |
10026 | h->key = x; | |
a9098fd0 | 10027 | h->key_mode = mode; |
9ebbca7d GK |
10028 | h->labelno = labelno; |
10029 | ||
10030 | found = htab_find_slot (toc_hash_table, h, 1); | |
10031 | if (*found == NULL) | |
10032 | *found = h; | |
10033 | else /* This is indeed a duplicate. | |
10034 | Set this label equal to that label. */ | |
10035 | { | |
10036 | fputs ("\t.set ", file); | |
10037 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
10038 | fprintf (file, "%d,", labelno); | |
10039 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
10040 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
10041 | found)->labelno)); | |
10042 | return; | |
10043 | } | |
10044 | } | |
10045 | ||
10046 | /* If we're going to put a double constant in the TOC, make sure it's | |
10047 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
10048 | if (GET_CODE (x) == CONST_DOUBLE |
10049 | && STRICT_ALIGNMENT | |
a9098fd0 | 10050 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
10051 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
10052 | ASM_OUTPUT_ALIGN (file, 3); | |
10053 | } | |
10054 | ||
9ebbca7d | 10055 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 10056 | |
37c37a57 RK |
10057 | /* Handle FP constants specially. Note that if we have a minimal |
10058 | TOC, things we put here aren't actually in the TOC, so we can allow | |
10059 | FP constants. */ | |
a9098fd0 | 10060 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 10061 | { |
042259f2 DE |
10062 | REAL_VALUE_TYPE rv; |
10063 | long k[2]; | |
0adc764e | 10064 | |
042259f2 DE |
10065 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
10066 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 10067 | |
13ded975 DE |
10068 | if (TARGET_64BIT) |
10069 | { | |
10070 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10071 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 10072 | else |
2bfcf297 DB |
10073 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
10074 | fprintf (file, "0x%lx%08lx\n", k[0], k[1]); | |
13ded975 DE |
10075 | return; |
10076 | } | |
1875cc88 | 10077 | else |
13ded975 DE |
10078 | { |
10079 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10080 | fputs ("\t.long ", file); |
13ded975 | 10081 | else |
2bfcf297 DB |
10082 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
10083 | fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]); | |
13ded975 DE |
10084 | return; |
10085 | } | |
9878760c | 10086 | } |
a9098fd0 | 10087 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 10088 | { |
042259f2 DE |
10089 | REAL_VALUE_TYPE rv; |
10090 | long l; | |
9878760c | 10091 | |
042259f2 DE |
10092 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
10093 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
10094 | ||
31bfaa0b DE |
10095 | if (TARGET_64BIT) |
10096 | { | |
10097 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10098 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 10099 | else |
2bfcf297 DB |
10100 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
10101 | fprintf (file, "0x%lx00000000\n", l); | |
31bfaa0b DE |
10102 | return; |
10103 | } | |
042259f2 | 10104 | else |
31bfaa0b DE |
10105 | { |
10106 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10107 | fputs ("\t.long ", file); |
31bfaa0b | 10108 | else |
2bfcf297 DB |
10109 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
10110 | fprintf (file, "0x%lx\n", l); | |
31bfaa0b DE |
10111 | return; |
10112 | } | |
042259f2 | 10113 | } |
f176e826 | 10114 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 10115 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 10116 | { |
e2c953b6 | 10117 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
10118 | HOST_WIDE_INT high; |
10119 | ||
10120 | if (GET_CODE (x) == CONST_DOUBLE) | |
10121 | { | |
10122 | low = CONST_DOUBLE_LOW (x); | |
10123 | high = CONST_DOUBLE_HIGH (x); | |
10124 | } | |
10125 | else | |
10126 | #if HOST_BITS_PER_WIDE_INT == 32 | |
10127 | { | |
10128 | low = INTVAL (x); | |
0858c623 | 10129 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
10130 | } |
10131 | #else | |
10132 | { | |
0858c623 | 10133 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
10134 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
10135 | } | |
10136 | #endif | |
9878760c | 10137 | |
a9098fd0 GK |
10138 | /* TOC entries are always Pmode-sized, but since this |
10139 | is a bigendian machine then if we're putting smaller | |
10140 | integer constants in the TOC we have to pad them. | |
10141 | (This is still a win over putting the constants in | |
10142 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
10143 | to have both a TOC entry _and_ the actual constant.) |
10144 | ||
10145 | For a 32-bit target, CONST_INT values are loaded and shifted | |
10146 | entirely within `low' and can be stored in one TOC entry. */ | |
10147 | ||
10148 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 10149 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
10150 | |
10151 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
a9098fd0 GK |
10152 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), |
10153 | POINTER_SIZE, &low, &high, 0); | |
10154 | ||
13ded975 DE |
10155 | if (TARGET_64BIT) |
10156 | { | |
10157 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10158 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 10159 | else |
2bfcf297 DB |
10160 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long)high, (long)low); |
10161 | fprintf (file, "0x%lx%08lx\n", (long) high, (long) low); | |
13ded975 DE |
10162 | return; |
10163 | } | |
1875cc88 | 10164 | else |
13ded975 | 10165 | { |
02a4ec28 FS |
10166 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
10167 | { | |
10168 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10169 | fputs ("\t.long ", file); |
02a4ec28 | 10170 | else |
2bfcf297 DB |
10171 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
10172 | (long)high, (long)low); | |
10173 | fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low); | |
02a4ec28 | 10174 | } |
13ded975 | 10175 | else |
02a4ec28 FS |
10176 | { |
10177 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 10178 | fputs ("\t.long ", file); |
02a4ec28 | 10179 | else |
2bfcf297 DB |
10180 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low); |
10181 | fprintf (file, "0x%lx\n", (long) low); | |
02a4ec28 | 10182 | } |
13ded975 DE |
10183 | return; |
10184 | } | |
9878760c RK |
10185 | } |
10186 | ||
10187 | if (GET_CODE (x) == CONST) | |
10188 | { | |
2bfcf297 DB |
10189 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
10190 | abort (); | |
10191 | ||
9878760c RK |
10192 | base = XEXP (XEXP (x, 0), 0); |
10193 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
10194 | } | |
10195 | ||
10196 | if (GET_CODE (base) == SYMBOL_REF) | |
10197 | name = XSTR (base, 0); | |
10198 | else if (GET_CODE (base) == LABEL_REF) | |
10199 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
10200 | else if (GET_CODE (base) == CODE_LABEL) | |
10201 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
10202 | else | |
10203 | abort (); | |
10204 | ||
2e4eb9b0 | 10205 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 10206 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 10207 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
10208 | else |
10209 | { | |
b6c9286a | 10210 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 10211 | |
1875cc88 JW |
10212 | if (offset < 0) |
10213 | fprintf (file, ".N%d", - offset); | |
10214 | else if (offset) | |
10215 | fprintf (file, ".P%d", offset); | |
9878760c | 10216 | |
19d2d16f | 10217 | fputs ("[TC],", file); |
1875cc88 | 10218 | } |
581bc4de MM |
10219 | |
10220 | /* Currently C++ toc references to vtables can be emitted before it | |
10221 | is decided whether the vtable is public or private. If this is | |
10222 | the case, then the linker will eventually complain that there is | |
10223 | a TOC reference to an unknown section. Thus, for vtables only, | |
10224 | we emit the TOC reference to reference the symbol and not the | |
10225 | section. */ | |
28e510bd | 10226 | if (VTABLE_NAME_P (name)) |
581bc4de | 10227 | { |
54ee9799 | 10228 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
10229 | if (offset < 0) |
10230 | fprintf (file, "%d", offset); | |
10231 | else if (offset > 0) | |
10232 | fprintf (file, "+%d", offset); | |
10233 | } | |
10234 | else | |
10235 | output_addr_const (file, x); | |
19d2d16f | 10236 | putc ('\n', file); |
9878760c RK |
10237 | } |
10238 | \f | |
10239 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
10240 | starting at P to FILE. | |
10241 | ||
10242 | On the RS/6000, we have to do this using the .byte operation and | |
10243 | write out special characters outside the quoted string. | |
10244 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 10245 | so we must artificially break them up early. */ |
9878760c RK |
10246 | |
10247 | void | |
10248 | output_ascii (file, p, n) | |
10249 | FILE *file; | |
d330fd93 | 10250 | const char *p; |
9878760c RK |
10251 | int n; |
10252 | { | |
10253 | char c; | |
10254 | int i, count_string; | |
d330fd93 KG |
10255 | const char *for_string = "\t.byte \""; |
10256 | const char *for_decimal = "\t.byte "; | |
10257 | const char *to_close = NULL; | |
9878760c RK |
10258 | |
10259 | count_string = 0; | |
10260 | for (i = 0; i < n; i++) | |
10261 | { | |
10262 | c = *p++; | |
10263 | if (c >= ' ' && c < 0177) | |
10264 | { | |
10265 | if (for_string) | |
10266 | fputs (for_string, file); | |
10267 | putc (c, file); | |
10268 | ||
10269 | /* Write two quotes to get one. */ | |
10270 | if (c == '"') | |
10271 | { | |
10272 | putc (c, file); | |
10273 | ++count_string; | |
10274 | } | |
10275 | ||
10276 | for_string = NULL; | |
10277 | for_decimal = "\"\n\t.byte "; | |
10278 | to_close = "\"\n"; | |
10279 | ++count_string; | |
10280 | ||
10281 | if (count_string >= 512) | |
10282 | { | |
10283 | fputs (to_close, file); | |
10284 | ||
10285 | for_string = "\t.byte \""; | |
10286 | for_decimal = "\t.byte "; | |
10287 | to_close = NULL; | |
10288 | count_string = 0; | |
10289 | } | |
10290 | } | |
10291 | else | |
10292 | { | |
10293 | if (for_decimal) | |
10294 | fputs (for_decimal, file); | |
10295 | fprintf (file, "%d", c); | |
10296 | ||
10297 | for_string = "\n\t.byte \""; | |
10298 | for_decimal = ", "; | |
10299 | to_close = "\n"; | |
10300 | count_string = 0; | |
10301 | } | |
10302 | } | |
10303 | ||
10304 | /* Now close the string if we have written one. Then end the line. */ | |
10305 | if (to_close) | |
9ebbca7d | 10306 | fputs (to_close, file); |
9878760c RK |
10307 | } |
10308 | \f | |
10309 | /* Generate a unique section name for FILENAME for a section type | |
10310 | represented by SECTION_DESC. Output goes into BUF. | |
10311 | ||
10312 | SECTION_DESC can be any string, as long as it is different for each | |
10313 | possible section type. | |
10314 | ||
10315 | We name the section in the same manner as xlc. The name begins with an | |
10316 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
10317 | names) with the last period replaced by the string SECTION_DESC. If |
10318 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
10319 | the name. */ | |
9878760c RK |
10320 | |
10321 | void | |
10322 | rs6000_gen_section_name (buf, filename, section_desc) | |
10323 | char **buf; | |
9ebbca7d GK |
10324 | const char *filename; |
10325 | const char *section_desc; | |
9878760c | 10326 | { |
9ebbca7d | 10327 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
10328 | char *p; |
10329 | int len; | |
9878760c RK |
10330 | |
10331 | after_last_slash = filename; | |
10332 | for (q = filename; *q; q++) | |
11e5fe42 RK |
10333 | { |
10334 | if (*q == '/') | |
10335 | after_last_slash = q + 1; | |
10336 | else if (*q == '.') | |
10337 | last_period = q; | |
10338 | } | |
9878760c | 10339 | |
11e5fe42 | 10340 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
10341 | *buf = (char *) permalloc (len); |
10342 | ||
10343 | p = *buf; | |
10344 | *p++ = '_'; | |
10345 | ||
10346 | for (q = after_last_slash; *q; q++) | |
10347 | { | |
11e5fe42 | 10348 | if (q == last_period) |
9878760c RK |
10349 | { |
10350 | strcpy (p, section_desc); | |
10351 | p += strlen (section_desc); | |
9878760c RK |
10352 | } |
10353 | ||
e9a780ec | 10354 | else if (ISALNUM (*q)) |
9878760c RK |
10355 | *p++ = *q; |
10356 | } | |
10357 | ||
11e5fe42 | 10358 | if (last_period == 0) |
9878760c RK |
10359 | strcpy (p, section_desc); |
10360 | else | |
10361 | *p = '\0'; | |
10362 | } | |
e165f3f0 | 10363 | \f |
a4f6c312 | 10364 | /* Emit profile function. */ |
411707f4 | 10365 | |
411707f4 CC |
10366 | void |
10367 | output_profile_hook (labelno) | |
10368 | int labelno; | |
10369 | { | |
8480e480 CC |
10370 | if (DEFAULT_ABI == ABI_AIX) |
10371 | { | |
10372 | char buf[30]; | |
40501e5f | 10373 | const char *label_name; |
8480e480 | 10374 | rtx fun; |
411707f4 | 10375 | |
8480e480 | 10376 | labelno += 1; |
411707f4 | 10377 | |
8480e480 CC |
10378 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
10379 | STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); | |
10380 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 10381 | |
8480e480 CC |
10382 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
10383 | fun, Pmode); | |
10384 | } | |
ee890fe2 SS |
10385 | else if (DEFAULT_ABI == ABI_DARWIN) |
10386 | { | |
d5fa86ba | 10387 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
10388 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
10389 | ||
10390 | /* Be conservative and always set this, at least for now. */ | |
10391 | current_function_uses_pic_offset_table = 1; | |
10392 | ||
10393 | #if TARGET_MACHO | |
10394 | /* For PIC code, set up a stub and collect the caller's address | |
10395 | from r0, which is where the prologue puts it. */ | |
10396 | if (flag_pic) | |
10397 | { | |
10398 | mcount_name = machopic_stub_name (mcount_name); | |
10399 | if (current_function_uses_pic_offset_table) | |
10400 | caller_addr_regno = 0; | |
10401 | } | |
10402 | #endif | |
10403 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
10404 | 0, VOIDmode, 1, | |
10405 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
10406 | } | |
411707f4 CC |
10407 | } |
10408 | ||
a4f6c312 | 10409 | /* Write function profiler code. */ |
e165f3f0 RK |
10410 | |
10411 | void | |
10412 | output_function_profiler (file, labelno) | |
10413 | FILE *file; | |
10414 | int labelno; | |
10415 | { | |
3daf36a4 | 10416 | char buf[100]; |
e165f3f0 | 10417 | |
3daf36a4 | 10418 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 10419 | switch (DEFAULT_ABI) |
3daf36a4 | 10420 | { |
38c1f2d7 MM |
10421 | default: |
10422 | abort (); | |
10423 | ||
10424 | case ABI_V4: | |
38c1f2d7 MM |
10425 | case ABI_AIX_NODESC: |
10426 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
10427 | if (flag_pic == 1) | |
10428 | { | |
dfdfa60f DE |
10429 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
10430 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
10431 | reg_names[0], reg_names[1]); | |
17167fd8 | 10432 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 10433 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 10434 | assemble_name (file, buf); |
17167fd8 | 10435 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 10436 | } |
9ebbca7d | 10437 | else if (flag_pic > 1) |
38c1f2d7 | 10438 | { |
dfdfa60f DE |
10439 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
10440 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
10441 | /* Now, we need to get the address of the label. */ |
10442 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 10443 | assemble_name (file, buf); |
9ebbca7d GK |
10444 | fputs ("-.\n1:", file); |
10445 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
10446 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
10447 | reg_names[0], reg_names[11]); | |
10448 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
10449 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 10450 | } |
38c1f2d7 MM |
10451 | else |
10452 | { | |
17167fd8 | 10453 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 10454 | assemble_name (file, buf); |
dfdfa60f | 10455 | fputs ("@ha\n", file); |
b5253831 DE |
10456 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
10457 | reg_names[0], reg_names[1]); | |
a260abc9 | 10458 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 10459 | assemble_name (file, buf); |
17167fd8 | 10460 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
10461 | } |
10462 | ||
b5253831 DE |
10463 | if (current_function_needs_context) |
10464 | asm_fprintf (file, "\tmr %s,%s\n", | |
10465 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 10466 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
10467 | if (current_function_needs_context) |
10468 | asm_fprintf (file, "\tmr %s,%s\n", | |
10469 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
10470 | break; |
10471 | ||
10472 | case ABI_AIX: | |
ee890fe2 | 10473 | case ABI_DARWIN: |
a4f6c312 | 10474 | /* Don't do anything, done in output_profile_hook (). */ |
38c1f2d7 | 10475 | break; |
411707f4 | 10476 | |
38c1f2d7 | 10477 | } |
e165f3f0 | 10478 | } |
a251ffd0 TG |
10479 | |
10480 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
10481 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
10482 | ||
c237e94a | 10483 | static int |
a06faf84 | 10484 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
10485 | rtx insn; |
10486 | rtx link; | |
296b8152 | 10487 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
10488 | int cost; |
10489 | { | |
10490 | if (! recog_memoized (insn)) | |
10491 | return 0; | |
10492 | ||
10493 | if (REG_NOTE_KIND (link) != 0) | |
10494 | return 0; | |
10495 | ||
10496 | if (REG_NOTE_KIND (link) == 0) | |
10497 | { | |
ed947a96 DJ |
10498 | /* Data dependency; DEP_INSN writes a register that INSN reads |
10499 | some cycles later. */ | |
10500 | switch (get_attr_type (insn)) | |
10501 | { | |
10502 | case TYPE_JMPREG: | |
10503 | /* Tell the first scheduling pass about the latency between | |
10504 | a mtctr and bctr (and mtlr and br/blr). The first | |
10505 | scheduling pass will not know about this latency since | |
10506 | the mtctr instruction, which has the latency associated | |
10507 | to it, will be generated by reload. */ | |
10508 | return TARGET_POWER ? 5 : 4; | |
10509 | case TYPE_BRANCH: | |
10510 | /* Leave some extra cycles between a compare and its | |
10511 | dependent branch, to inhibit expensive mispredicts. */ | |
10512 | if ((rs6000_cpu_attr == CPU_PPC750 | |
10513 | || rs6000_cpu_attr == CPU_PPC7400 | |
10514 | || rs6000_cpu_attr == CPU_PPC7450) | |
10515 | && recog_memoized (dep_insn) | |
10516 | && (INSN_CODE (dep_insn) >= 0) | |
10517 | && (get_attr_type (dep_insn) == TYPE_COMPARE | |
10518 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE | |
10519 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE | |
10520 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL)) | |
10521 | return cost + 2; | |
10522 | default: | |
10523 | break; | |
10524 | } | |
a251ffd0 TG |
10525 | /* Fall out to return default cost. */ |
10526 | } | |
10527 | ||
10528 | return cost; | |
10529 | } | |
b6c9286a | 10530 | |
a4f6c312 SS |
10531 | /* A C statement (sans semicolon) to update the integer scheduling |
10532 | priority INSN_PRIORITY (INSN). Reduce the priority to execute the | |
10533 | INSN earlier, increase the priority to execute INSN later. Do not | |
10534 | define this macro if you do not need to adjust the scheduling | |
10535 | priorities of insns. */ | |
bef84347 | 10536 | |
c237e94a | 10537 | static int |
bef84347 | 10538 | rs6000_adjust_priority (insn, priority) |
d330fd93 | 10539 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
10540 | int priority; |
10541 | { | |
a4f6c312 SS |
10542 | /* On machines (like the 750) which have asymmetric integer units, |
10543 | where one integer unit can do multiply and divides and the other | |
10544 | can't, reduce the priority of multiply/divide so it is scheduled | |
10545 | before other integer operations. */ | |
bef84347 VM |
10546 | |
10547 | #if 0 | |
2c3c49de | 10548 | if (! INSN_P (insn)) |
bef84347 VM |
10549 | return priority; |
10550 | ||
10551 | if (GET_CODE (PATTERN (insn)) == USE) | |
10552 | return priority; | |
10553 | ||
10554 | switch (rs6000_cpu_attr) { | |
10555 | case CPU_PPC750: | |
10556 | switch (get_attr_type (insn)) | |
10557 | { | |
10558 | default: | |
10559 | break; | |
10560 | ||
10561 | case TYPE_IMUL: | |
10562 | case TYPE_IDIV: | |
3cb999d8 DE |
10563 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
10564 | priority, priority); | |
bef84347 VM |
10565 | if (priority >= 0 && priority < 0x01000000) |
10566 | priority >>= 3; | |
10567 | break; | |
10568 | } | |
10569 | } | |
10570 | #endif | |
10571 | ||
10572 | return priority; | |
10573 | } | |
10574 | ||
a4f6c312 SS |
10575 | /* Return how many instructions the machine can issue per cycle. */ |
10576 | ||
c237e94a ZW |
10577 | static int |
10578 | rs6000_issue_rate () | |
b6c9286a MM |
10579 | { |
10580 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
10581 | case CPU_RIOS1: /* ? */ |
10582 | case CPU_RS64A: | |
10583 | case CPU_PPC601: /* ? */ | |
ed947a96 | 10584 | case CPU_PPC7450: |
3cb999d8 | 10585 | return 3; |
b6c9286a | 10586 | case CPU_PPC603: |
bef84347 | 10587 | case CPU_PPC750: |
ed947a96 | 10588 | case CPU_PPC7400: |
bef84347 | 10589 | return 2; |
3cb999d8 | 10590 | case CPU_RIOS2: |
b6c9286a | 10591 | case CPU_PPC604: |
19684119 | 10592 | case CPU_PPC604E: |
b6c9286a | 10593 | case CPU_PPC620: |
3cb999d8 | 10594 | case CPU_PPC630: |
b6c9286a MM |
10595 | return 4; |
10596 | default: | |
10597 | return 1; | |
10598 | } | |
10599 | } | |
10600 | ||
b6c9286a | 10601 | \f |
b6c9286a MM |
10602 | /* Length in units of the trampoline for entering a nested function. */ |
10603 | ||
10604 | int | |
10605 | rs6000_trampoline_size () | |
10606 | { | |
10607 | int ret = 0; | |
10608 | ||
10609 | switch (DEFAULT_ABI) | |
10610 | { | |
10611 | default: | |
10612 | abort (); | |
10613 | ||
10614 | case ABI_AIX: | |
8f802bfb | 10615 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
10616 | break; |
10617 | ||
4dabc42d | 10618 | case ABI_DARWIN: |
b6c9286a MM |
10619 | case ABI_V4: |
10620 | case ABI_AIX_NODESC: | |
03a7e1a5 | 10621 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 10622 | break; |
b6c9286a MM |
10623 | } |
10624 | ||
10625 | return ret; | |
10626 | } | |
10627 | ||
10628 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
10629 | FNADDR is an RTX for the address of the function's pure code. | |
10630 | CXT is an RTX for the static chain value for the function. */ | |
10631 | ||
10632 | void | |
10633 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
10634 | rtx addr; | |
10635 | rtx fnaddr; | |
10636 | rtx cxt; | |
10637 | { | |
ac2a93a1 | 10638 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
10639 | int regsize = (TARGET_32BIT) ? 4 : 8; |
10640 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
10641 | |
10642 | switch (DEFAULT_ABI) | |
10643 | { | |
10644 | default: | |
10645 | abort (); | |
10646 | ||
8bd04c56 | 10647 | /* Macros to shorten the code expansions below. */ |
39403d82 | 10648 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
10649 | #define MEM_PLUS(addr,offset) \ |
10650 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 10651 | |
b6c9286a MM |
10652 | /* Under AIX, just build the 3 word function descriptor */ |
10653 | case ABI_AIX: | |
8bd04c56 MM |
10654 | { |
10655 | rtx fn_reg = gen_reg_rtx (pmode); | |
10656 | rtx toc_reg = gen_reg_rtx (pmode); | |
10657 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 10658 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
10659 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
10660 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
10661 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
10662 | } | |
b6c9286a MM |
10663 | break; |
10664 | ||
4dabc42d TC |
10665 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
10666 | case ABI_DARWIN: | |
b6c9286a MM |
10667 | case ABI_V4: |
10668 | case ABI_AIX_NODESC: | |
39403d82 | 10669 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
10670 | FALSE, VOIDmode, 4, |
10671 | addr, pmode, | |
10672 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
10673 | fnaddr, pmode, | |
10674 | ctx_reg, pmode); | |
b6c9286a | 10675 | break; |
b6c9286a MM |
10676 | } |
10677 | ||
10678 | return; | |
10679 | } | |
7509c759 MM |
10680 | |
10681 | \f | |
91d231cb | 10682 | /* Table of valid machine attributes. */ |
a4f6c312 | 10683 | |
91d231cb | 10684 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 10685 | { |
91d231cb JM |
10686 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
10687 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
10688 | { NULL, 0, 0, false, false, false, NULL } | |
10689 | }; | |
7509c759 | 10690 | |
a4f6c312 SS |
10691 | /* Handle a "longcall" attribute; arguments as in struct |
10692 | attribute_spec.handler. */ | |
10693 | ||
91d231cb JM |
10694 | static tree |
10695 | rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) | |
10696 | tree *node; | |
10697 | tree name; | |
10698 | tree args ATTRIBUTE_UNUSED; | |
10699 | int flags ATTRIBUTE_UNUSED; | |
10700 | bool *no_add_attrs; | |
10701 | { | |
10702 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
10703 | && TREE_CODE (*node) != FIELD_DECL | |
10704 | && TREE_CODE (*node) != TYPE_DECL) | |
10705 | { | |
10706 | warning ("`%s' attribute only applies to functions", | |
10707 | IDENTIFIER_POINTER (name)); | |
10708 | *no_add_attrs = true; | |
10709 | } | |
6a4cee5f | 10710 | |
91d231cb | 10711 | return NULL_TREE; |
7509c759 MM |
10712 | } |
10713 | ||
3cb999d8 DE |
10714 | /* Return a reference suitable for calling a function with the |
10715 | longcall attribute. */ | |
a4f6c312 | 10716 | |
6a4cee5f MM |
10717 | struct rtx_def * |
10718 | rs6000_longcall_ref (call_ref) | |
10719 | rtx call_ref; | |
10720 | { | |
d330fd93 | 10721 | const char *call_name; |
6a4cee5f MM |
10722 | tree node; |
10723 | ||
10724 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
10725 | return call_ref; | |
10726 | ||
10727 | /* System V adds '.' to the internal name, so skip them. */ | |
10728 | call_name = XSTR (call_ref, 0); | |
10729 | if (*call_name == '.') | |
10730 | { | |
10731 | while (*call_name == '.') | |
10732 | call_name++; | |
10733 | ||
10734 | node = get_identifier (call_name); | |
39403d82 | 10735 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
10736 | } |
10737 | ||
10738 | return force_reg (Pmode, call_ref); | |
10739 | } | |
10740 | ||
7509c759 MM |
10741 | \f |
10742 | /* A C statement or statements to switch to the appropriate section | |
10743 | for output of RTX in mode MODE. You can assume that RTX is some | |
10744 | kind of constant in RTL. The argument MODE is redundant except in | |
10745 | the case of a `const_int' rtx. Select the section by calling | |
10746 | `text_section' or one of the alternatives for other sections. | |
10747 | ||
10748 | Do not define this macro if you put all constants in the read-only | |
10749 | data section. */ | |
10750 | ||
b91da81f | 10751 | #ifdef USING_ELFOS_H |
7509c759 MM |
10752 | |
10753 | void | |
10754 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 10755 | enum machine_mode mode; |
7509c759 MM |
10756 | rtx x; |
10757 | { | |
a9098fd0 | 10758 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 10759 | toc_section (); |
7509c759 MM |
10760 | else |
10761 | const_section (); | |
10762 | } | |
10763 | ||
10764 | /* A C statement or statements to switch to the appropriate | |
10765 | section for output of DECL. DECL is either a `VAR_DECL' node | |
10766 | or a constant of some sort. RELOC indicates whether forming | |
10767 | the initial value of DECL requires link-time relocations. */ | |
10768 | ||
10769 | void | |
10770 | rs6000_select_section (decl, reloc) | |
10771 | tree decl; | |
10772 | int reloc; | |
10773 | { | |
10774 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
10775 | int needs_sdata; |
10776 | int readonly; | |
10777 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
10778 | &const_section, | |
10779 | &sdata2_section, | |
10780 | &data_section, | |
10781 | &sdata_section | |
10782 | }; | |
10783 | ||
10784 | needs_sdata = (size > 0 | |
10785 | && size <= g_switch_value | |
10786 | && rs6000_sdata != SDATA_NONE | |
10787 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
10788 | |
10789 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 10790 | readonly = ! flag_writable_strings; |
a9098fd0 | 10791 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
10792 | readonly = (! (flag_pic && reloc) |
10793 | && TREE_READONLY (decl) | |
10794 | && ! TREE_SIDE_EFFECTS (decl) | |
10795 | && DECL_INITIAL (decl) | |
10796 | && DECL_INITIAL (decl) != error_mark_node | |
10797 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
ac4f7ad9 GK |
10798 | else if (TREE_CODE (decl) == CONSTRUCTOR) |
10799 | readonly = (! (flag_pic && reloc) | |
ac4f7ad9 | 10800 | && ! TREE_SIDE_EFFECTS (decl) |
f3afc192 | 10801 | && TREE_CONSTANT (decl)); |
7509c759 | 10802 | else |
63019373 GK |
10803 | readonly = 1; |
10804 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
10805 | readonly = 0; | |
10806 | ||
10807 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
10808 | } | |
10809 | ||
10810 | /* A C statement to build up a unique section name, expressed as a | |
10811 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
10812 | RELOC indicates whether the initial value of EXP requires | |
10813 | link-time relocations. If you do not define this macro, GCC will use | |
10814 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 10815 | macro can now be called for uninitialized data items as well as |
63019373 GK |
10816 | initialised data and functions. */ |
10817 | ||
10818 | void | |
10819 | rs6000_unique_section (decl, reloc) | |
10820 | tree decl; | |
10821 | int reloc; | |
10822 | { | |
63019373 GK |
10823 | int len; |
10824 | int sec; | |
10825 | const char *name; | |
10826 | char *string; | |
10827 | const char *prefix; | |
10828 | ||
10829 | static const char *const prefixes[7][2] = | |
10830 | { | |
63019373 GK |
10831 | { ".rodata.", ".gnu.linkonce.r." }, |
10832 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
10833 | { ".data.", ".gnu.linkonce.d." }, | |
10834 | { ".sdata.", ".gnu.linkonce.s." }, | |
10835 | { ".bss.", ".gnu.linkonce.b." }, | |
5b8c2356 AM |
10836 | { ".sbss.", ".gnu.linkonce.sb." }, |
10837 | { ".text.", ".gnu.linkonce.t." } | |
63019373 | 10838 | }; |
63019373 | 10839 | |
5b8c2356 AM |
10840 | if (TREE_CODE (decl) == FUNCTION_DECL) |
10841 | sec = 6; | |
63019373 | 10842 | else |
5b8c2356 AM |
10843 | { |
10844 | int readonly; | |
10845 | int needs_sdata; | |
10846 | int size; | |
10847 | ||
10848 | readonly = 1; | |
10849 | if (TREE_CODE (decl) == STRING_CST) | |
10850 | readonly = ! flag_writable_strings; | |
10851 | else if (TREE_CODE (decl) == VAR_DECL) | |
10852 | readonly = (! (flag_pic && reloc) | |
10853 | && TREE_READONLY (decl) | |
10854 | && ! TREE_SIDE_EFFECTS (decl) | |
10855 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
10856 | ||
10857 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
10858 | needs_sdata = (size > 0 | |
10859 | && size <= g_switch_value | |
10860 | && rs6000_sdata != SDATA_NONE | |
10861 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
10862 | ||
10863 | if (DECL_INITIAL (decl) == 0 | |
10864 | || DECL_INITIAL (decl) == error_mark_node) | |
10865 | sec = 4; | |
10866 | else if (! readonly) | |
10867 | sec = 2; | |
10868 | else | |
10869 | sec = 0; | |
63019373 | 10870 | |
5b8c2356 AM |
10871 | if (needs_sdata) |
10872 | { | |
10873 | /* .sdata2 is only for EABI. */ | |
10874 | if (sec == 0 && rs6000_sdata != SDATA_EABI) | |
10875 | sec = 2; | |
10876 | sec += 1; | |
10877 | } | |
10878 | } | |
63019373 | 10879 | |
e6978109 | 10880 | STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); |
63019373 GK |
10881 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; |
10882 | len = strlen (name) + strlen (prefix); | |
10883 | string = alloca (len + 1); | |
10884 | ||
10885 | sprintf (string, "%s%s", prefix, name); | |
10886 | ||
10887 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 10888 | } |
d9407988 MM |
10889 | |
10890 | \f | |
d9407988 MM |
10891 | /* If we are referencing a function that is static or is known to be |
10892 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
10893 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 10894 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
10895 | function name with the real name (1 or 2 leading .'s), rather than |
10896 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 10897 | to read the prefixes. */ |
d9407988 MM |
10898 | |
10899 | void | |
10900 | rs6000_encode_section_info (decl) | |
10901 | tree decl; | |
10902 | { | |
10903 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
10904 | { | |
10905 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 10906 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 10907 | && ! DECL_WEAK (decl)) |
d9407988 MM |
10908 | SYMBOL_REF_FLAG (sym_ref) = 1; |
10909 | ||
9ebbca7d | 10910 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 10911 | { |
ff669a6c RH |
10912 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
10913 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 10914 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
10915 | str[0] = '.'; |
10916 | str[1] = '.'; | |
10917 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
10918 | ||
520a57c8 | 10919 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
10920 | } |
10921 | } | |
10922 | else if (rs6000_sdata != SDATA_NONE | |
f607bc57 | 10923 | && DEFAULT_ABI == ABI_V4 |
d9407988 MM |
10924 | && TREE_CODE (decl) == VAR_DECL) |
10925 | { | |
10926 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
10927 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 10928 | const char *name = (char *)0; |
d9407988 MM |
10929 | int len = 0; |
10930 | ||
10931 | if (section_name) | |
10932 | { | |
10933 | if (TREE_CODE (section_name) == STRING_CST) | |
10934 | { | |
10935 | name = TREE_STRING_POINTER (section_name); | |
10936 | len = TREE_STRING_LENGTH (section_name); | |
10937 | } | |
10938 | else | |
10939 | abort (); | |
10940 | } | |
10941 | ||
10942 | if ((size > 0 && size <= g_switch_value) | |
10943 | || (name | |
5f59ecb7 | 10944 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 10945 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 10946 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 10947 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 10948 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 10949 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 10950 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 10951 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 10952 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 10953 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 10954 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 10955 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
10956 | { |
10957 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c | 10958 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 10959 | char *str = alloca (len + 2); |
ff669a6c | 10960 | |
ff669a6c RH |
10961 | str[0] = '@'; |
10962 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 10963 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
10964 | } |
10965 | } | |
10966 | } | |
10967 | ||
b91da81f | 10968 | #endif /* USING_ELFOS_H */ |
000034eb | 10969 | |
a6c2a102 | 10970 | \f |
000034eb | 10971 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
10972 | ADDR can be effectively incremented by incrementing REG. |
10973 | ||
10974 | r0 is special and we must not select it as an address | |
10975 | register by this routine since our caller will try to | |
10976 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
10977 | |
10978 | struct rtx_def * | |
10979 | find_addr_reg (addr) | |
10980 | rtx addr; | |
10981 | { | |
10982 | while (GET_CODE (addr) == PLUS) | |
10983 | { | |
02441cd6 JL |
10984 | if (GET_CODE (XEXP (addr, 0)) == REG |
10985 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 10986 | addr = XEXP (addr, 0); |
02441cd6 JL |
10987 | else if (GET_CODE (XEXP (addr, 1)) == REG |
10988 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
10989 | addr = XEXP (addr, 1); |
10990 | else if (CONSTANT_P (XEXP (addr, 0))) | |
10991 | addr = XEXP (addr, 1); | |
10992 | else if (CONSTANT_P (XEXP (addr, 1))) | |
10993 | addr = XEXP (addr, 0); | |
10994 | else | |
10995 | abort (); | |
10996 | } | |
02441cd6 | 10997 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
10998 | return addr; |
10999 | abort (); | |
11000 | } | |
11001 | ||
a6c2a102 DE |
11002 | void |
11003 | rs6000_fatal_bad_address (op) | |
11004 | rtx op; | |
11005 | { | |
11006 | fatal_insn ("bad address", op); | |
11007 | } | |
c8023011 MM |
11008 | |
11009 | /* Called to register all of our global variables with the garbage | |
11010 | collector. */ | |
11011 | ||
11012 | static void | |
11013 | rs6000_add_gc_roots () | |
11014 | { | |
11015 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
11016 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
11017 | |
11018 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
11019 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
11020 | toc_hash_mark_table); | |
ee890fe2 SS |
11021 | |
11022 | #if TARGET_MACHO | |
11023 | machopic_add_gc_roots (); | |
11024 | #endif | |
11025 | } | |
11026 | ||
11027 | #if TARGET_MACHO | |
11028 | ||
11029 | #if 0 | |
11030 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
11031 | reference and a constant. */ | |
11032 | ||
11033 | int | |
11034 | symbolic_operand (op) | |
592696dd | 11035 | rtx op; |
ee890fe2 SS |
11036 | { |
11037 | switch (GET_CODE (op)) | |
11038 | { | |
11039 | case SYMBOL_REF: | |
11040 | case LABEL_REF: | |
11041 | return 1; | |
11042 | case CONST: | |
11043 | op = XEXP (op, 0); | |
11044 | return (GET_CODE (op) == SYMBOL_REF || | |
11045 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
11046 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
11047 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
11048 | default: | |
11049 | return 0; | |
11050 | } | |
c8023011 | 11051 | } |
ee890fe2 SS |
11052 | #endif |
11053 | ||
11054 | #ifdef RS6000_LONG_BRANCH | |
11055 | ||
11056 | static tree stub_list = 0; | |
11057 | ||
11058 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
11059 | procedure calls to the linked list. */ | |
11060 | ||
11061 | void | |
11062 | add_compiler_stub (label_name, function_name, line_number) | |
11063 | tree label_name; | |
11064 | tree function_name; | |
11065 | int line_number; | |
11066 | { | |
11067 | tree stub = build_tree_list (function_name, label_name); | |
11068 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
11069 | TREE_CHAIN (stub) = stub_list; | |
11070 | stub_list = stub; | |
11071 | } | |
11072 | ||
11073 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
11074 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
11075 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
11076 | ||
a4f6c312 SS |
11077 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for |
11078 | handling procedure calls from the linked list and initializes the | |
11079 | linked list. */ | |
ee890fe2 | 11080 | |
a4f6c312 SS |
11081 | void |
11082 | output_compiler_stub () | |
ee890fe2 SS |
11083 | { |
11084 | char tmp_buf[256]; | |
11085 | char label_buf[256]; | |
11086 | char *label; | |
11087 | tree tmp_stub, stub; | |
11088 | ||
11089 | if (!flag_pic) | |
11090 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
11091 | { | |
11092 | fprintf (asm_out_file, | |
11093 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
11094 | ||
11095 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
11096 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
11097 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
11098 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
11099 | ||
11100 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
11101 | strcpy (label_buf, | |
11102 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
11103 | else | |
11104 | { | |
11105 | label_buf[0] = '_'; | |
11106 | strcpy (label_buf+1, | |
11107 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
11108 | } | |
11109 | ||
11110 | strcpy (tmp_buf, "lis r12,hi16("); | |
11111 | strcat (tmp_buf, label_buf); | |
11112 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
11113 | strcat (tmp_buf, label_buf); | |
11114 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
11115 | output_asm_insn (tmp_buf, 0); | |
11116 | ||
11117 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
11118 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
11119 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
11120 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
11121 | } | |
11122 | ||
11123 | stub_list = 0; | |
11124 | } | |
11125 | ||
11126 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
11127 | already there or not. */ | |
11128 | ||
a4f6c312 SS |
11129 | int |
11130 | no_previous_def (function_name) | |
ee890fe2 SS |
11131 | tree function_name; |
11132 | { | |
11133 | tree stub; | |
11134 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
11135 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
11136 | return 0; | |
11137 | return 1; | |
11138 | } | |
11139 | ||
11140 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
11141 | the function. */ | |
11142 | ||
a4f6c312 SS |
11143 | tree |
11144 | get_prev_label (function_name) | |
ee890fe2 SS |
11145 | tree function_name; |
11146 | { | |
11147 | tree stub; | |
11148 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
11149 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
11150 | return STUB_LABEL_NAME (stub); | |
11151 | return 0; | |
11152 | } | |
11153 | ||
11154 | /* INSN is either a function call or a millicode call. It may have an | |
11155 | unconditional jump in its delay slot. | |
11156 | ||
11157 | CALL_DEST is the routine we are calling. */ | |
11158 | ||
11159 | char * | |
11160 | output_call (insn, call_dest, operand_number) | |
11161 | rtx insn; | |
11162 | rtx call_dest; | |
11163 | int operand_number; | |
11164 | { | |
11165 | static char buf[256]; | |
11166 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
11167 | { | |
11168 | tree labelname; | |
11169 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
11170 | ||
11171 | if (no_previous_def (funname)) | |
11172 | { | |
11173 | int line_number; | |
11174 | rtx label_rtx = gen_label_rtx (); | |
11175 | char *label_buf, temp_buf[256]; | |
11176 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
11177 | CODE_LABEL_NUMBER (label_rtx)); | |
11178 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
11179 | labelname = get_identifier (label_buf); | |
11180 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
11181 | if (insn) | |
11182 | line_number = NOTE_LINE_NUMBER (insn); | |
11183 | add_compiler_stub (labelname, funname, line_number); | |
11184 | } | |
11185 | else | |
11186 | labelname = get_prev_label (funname); | |
11187 | ||
11188 | sprintf (buf, "jbsr %%z%d,%.246s", | |
11189 | operand_number, IDENTIFIER_POINTER (labelname)); | |
11190 | return buf; | |
11191 | } | |
11192 | else | |
11193 | { | |
11194 | sprintf (buf, "bl %%z%d", operand_number); | |
11195 | return buf; | |
11196 | } | |
11197 | } | |
11198 | ||
11199 | #endif /* RS6000_LONG_BRANCH */ | |
11200 | ||
11201 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
11202 | do { \ | |
83182544 | 11203 | const char *const symbol_ = (SYMBOL); \ |
ee890fe2 SS |
11204 | char *buffer_ = (BUF); \ |
11205 | if (symbol_[0] == '"') \ | |
11206 | { \ | |
11207 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
11208 | } \ | |
11209 | else if (name_needs_quotes(symbol_)) \ | |
11210 | { \ | |
11211 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
11212 | } \ | |
11213 | else \ | |
11214 | { \ | |
11215 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
11216 | } \ | |
11217 | } while (0) | |
11218 | ||
11219 | ||
11220 | /* Generate PIC and indirect symbol stubs. */ | |
11221 | ||
11222 | void | |
11223 | machopic_output_stub (file, symb, stub) | |
11224 | FILE *file; | |
11225 | const char *symb, *stub; | |
11226 | { | |
11227 | unsigned int length; | |
a4f6c312 SS |
11228 | char *symbol_name, *lazy_ptr_name; |
11229 | char *local_label_0; | |
ee890fe2 SS |
11230 | static int label = 0; |
11231 | ||
df56a27f SS |
11232 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
11233 | STRIP_NAME_ENCODING (symb, symb); | |
11234 | ||
ee890fe2 SS |
11235 | label += 1; |
11236 | ||
ee890fe2 SS |
11237 | length = strlen (symb); |
11238 | symbol_name = alloca (length + 32); | |
11239 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
11240 | ||
11241 | lazy_ptr_name = alloca (length + 32); | |
11242 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
11243 | ||
11244 | local_label_0 = alloca (length + 32); | |
11245 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
11246 | ||
ee890fe2 SS |
11247 | if (flag_pic == 2) |
11248 | machopic_picsymbol_stub_section (); | |
11249 | else | |
11250 | machopic_symbol_stub_section (); | |
11251 | ||
11252 | fprintf (file, "%s:\n", stub); | |
11253 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
11254 | ||
11255 | if (flag_pic == 2) | |
11256 | { | |
11257 | fprintf (file, "\tmflr r0\n"); | |
11258 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
11259 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
11260 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
11261 | lazy_ptr_name, local_label_0); | |
11262 | fprintf (file, "\tmtlr r0\n"); | |
11263 | fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n", | |
11264 | lazy_ptr_name, local_label_0); | |
11265 | fprintf (file, "\tmtctr r12\n"); | |
11266 | fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n", | |
11267 | lazy_ptr_name, local_label_0); | |
11268 | fprintf (file, "\tbctr\n"); | |
11269 | } | |
11270 | else | |
11271 | fprintf (file, "non-pure not supported\n"); | |
11272 | ||
11273 | machopic_lazy_symbol_ptr_section (); | |
11274 | fprintf (file, "%s:\n", lazy_ptr_name); | |
11275 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
11276 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
11277 | } | |
11278 | ||
11279 | /* Legitimize PIC addresses. If the address is already | |
11280 | position-independent, we return ORIG. Newly generated | |
11281 | position-independent addresses go into a reg. This is REG if non | |
11282 | zero, otherwise we allocate register(s) as necessary. */ | |
11283 | ||
c859cda6 | 11284 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
11285 | |
11286 | rtx | |
11287 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
11288 | rtx orig; | |
11289 | enum machine_mode mode; | |
11290 | rtx reg; | |
11291 | { | |
11292 | rtx base, offset; | |
11293 | ||
11294 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
11295 | reg = gen_reg_rtx (Pmode); | |
11296 | ||
11297 | if (GET_CODE (orig) == CONST) | |
11298 | { | |
11299 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
11300 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
11301 | return orig; | |
11302 | ||
11303 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
11304 | { | |
a4f6c312 SS |
11305 | base = |
11306 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
11307 | Pmode, reg); | |
11308 | offset = | |
11309 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
11310 | Pmode, reg); | |
ee890fe2 SS |
11311 | } |
11312 | else | |
11313 | abort (); | |
11314 | ||
11315 | if (GET_CODE (offset) == CONST_INT) | |
11316 | { | |
11317 | if (SMALL_INT (offset)) | |
ed8908e7 | 11318 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
11319 | else if (! reload_in_progress && ! reload_completed) |
11320 | offset = force_reg (Pmode, offset); | |
11321 | else | |
c859cda6 DJ |
11322 | { |
11323 | rtx mem = force_const_mem (Pmode, orig); | |
11324 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
11325 | } | |
ee890fe2 SS |
11326 | } |
11327 | return gen_rtx (PLUS, Pmode, base, offset); | |
11328 | } | |
11329 | ||
11330 | /* Fall back on generic machopic code. */ | |
11331 | return machopic_legitimize_pic_address (orig, mode, reg); | |
11332 | } | |
11333 | ||
11334 | /* This is just a placeholder to make linking work without having to | |
11335 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
11336 | ever needed for Darwin (not too likely!) this would have to get a | |
11337 | real definition. */ | |
11338 | ||
11339 | void | |
11340 | toc_section () | |
11341 | { | |
11342 | } | |
11343 | ||
11344 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
11345 | |
11346 | #if TARGET_ELF | |
11347 | static unsigned int | |
11348 | rs6000_elf_section_type_flags (decl, name, reloc) | |
11349 | tree decl; | |
11350 | const char *name; | |
11351 | int reloc; | |
11352 | { | |
11353 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
11354 | ||
270fc29b RH |
11355 | if (TARGET_RELOCATABLE) |
11356 | flags |= SECTION_WRITE; | |
7c262518 | 11357 | |
d0101753 | 11358 | return flags; |
7c262518 | 11359 | } |
d9f6800d RH |
11360 | |
11361 | /* Record an element in the table of global constructors. SYMBOL is | |
11362 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
11363 | between 0 and MAX_INIT_PRIORITY. | |
11364 | ||
11365 | This differs from default_named_section_asm_out_constructor in | |
11366 | that we have special handling for -mrelocatable. */ | |
11367 | ||
11368 | static void | |
11369 | rs6000_elf_asm_out_constructor (symbol, priority) | |
11370 | rtx symbol; | |
11371 | int priority; | |
11372 | { | |
11373 | const char *section = ".ctors"; | |
11374 | char buf[16]; | |
11375 | ||
11376 | if (priority != DEFAULT_INIT_PRIORITY) | |
11377 | { | |
11378 | sprintf (buf, ".ctors.%.5u", | |
11379 | /* Invert the numbering so the linker puts us in the proper | |
11380 | order; constructors are run from right to left, and the | |
11381 | linker sorts in increasing order. */ | |
11382 | MAX_INIT_PRIORITY - priority); | |
11383 | section = buf; | |
11384 | } | |
11385 | ||
715bdd29 RH |
11386 | named_section_flags (section, SECTION_WRITE); |
11387 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
11388 | |
11389 | if (TARGET_RELOCATABLE) | |
11390 | { | |
11391 | fputs ("\t.long (", asm_out_file); | |
11392 | output_addr_const (asm_out_file, symbol); | |
11393 | fputs (")@fixup\n", asm_out_file); | |
11394 | } | |
11395 | else | |
c8af3574 | 11396 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
11397 | } |
11398 | ||
11399 | static void | |
11400 | rs6000_elf_asm_out_destructor (symbol, priority) | |
11401 | rtx symbol; | |
11402 | int priority; | |
11403 | { | |
11404 | const char *section = ".dtors"; | |
11405 | char buf[16]; | |
11406 | ||
11407 | if (priority != DEFAULT_INIT_PRIORITY) | |
11408 | { | |
11409 | sprintf (buf, ".dtors.%.5u", | |
11410 | /* Invert the numbering so the linker puts us in the proper | |
11411 | order; constructors are run from right to left, and the | |
11412 | linker sorts in increasing order. */ | |
11413 | MAX_INIT_PRIORITY - priority); | |
11414 | section = buf; | |
11415 | } | |
11416 | ||
715bdd29 RH |
11417 | named_section_flags (section, SECTION_WRITE); |
11418 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
11419 | |
11420 | if (TARGET_RELOCATABLE) | |
11421 | { | |
11422 | fputs ("\t.long (", asm_out_file); | |
11423 | output_addr_const (asm_out_file, symbol); | |
11424 | fputs (")@fixup\n", asm_out_file); | |
11425 | } | |
11426 | else | |
c8af3574 | 11427 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 11428 | } |
7c262518 RH |
11429 | #endif |
11430 | ||
11431 | #ifdef OBJECT_FORMAT_COFF | |
11432 | static void | |
715bdd29 | 11433 | xcoff_asm_named_section (name, flags) |
7c262518 RH |
11434 | const char *name; |
11435 | unsigned int flags ATTRIBUTE_UNUSED; | |
7c262518 RH |
11436 | { |
11437 | fprintf (asm_out_file, "\t.csect %s\n", name); | |
11438 | } | |
11439 | #endif |