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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
93c9d1ba | 3 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
cd3ce9b4 | 55 | #include "tree-gimple.h" |
1bc7c5b6 ZW |
56 | #if TARGET_XCOFF |
57 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
58 | #endif | |
9b30bae2 | 59 | |
7509c759 MM |
60 | #ifndef TARGET_NO_PROTOTYPE |
61 | #define TARGET_NO_PROTOTYPE 0 | |
62 | #endif | |
63 | ||
452a7d36 HP |
64 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
65 | #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e \ | |
66 | && !((n) & 1)) | |
d744e06e | 67 | |
9878760c RK |
68 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
69 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
70 | ||
d1d0c603 JJ |
71 | /* Structure used to define the rs6000 stack */ |
72 | typedef struct rs6000_stack { | |
73 | int first_gp_reg_save; /* first callee saved GP register used */ | |
74 | int first_fp_reg_save; /* first callee saved FP register used */ | |
75 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
76 | int lr_save_p; /* true if the link reg needs to be saved */ | |
77 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
78 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
79 | int toc_save_p; /* true if the TOC needs to be saved */ | |
80 | int push_p; /* true if we need to allocate stack space */ | |
81 | int calls_p; /* true if the function makes any calls */ | |
82 | enum rs6000_abi abi; /* which ABI to use */ | |
83 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
84 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
85 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
86 | int lr_save_offset; /* offset to save LR from initial SP */ | |
87 | int cr_save_offset; /* offset to save CR from initial SP */ | |
88 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
89 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
90 | int toc_save_offset; /* offset to save the TOC pointer */ | |
91 | int varargs_save_offset; /* offset to save the varargs registers */ | |
92 | int ehrd_offset; /* offset to EH return data */ | |
93 | int reg_size; /* register size (4 or 8) */ | |
94 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
95 | HOST_WIDE_INT vars_size; /* variable save area size */ | |
96 | int parm_size; /* outgoing parameter size */ | |
97 | int save_size; /* save area size */ | |
98 | int fixed_size; /* fixed size of stack frame */ | |
99 | int gp_size; /* size of saved GP registers */ | |
100 | int fp_size; /* size of saved FP registers */ | |
101 | int altivec_size; /* size of saved AltiVec registers */ | |
102 | int cr_size; /* size to hold CR if not in save_size */ | |
103 | int lr_size; /* size to hold LR if not in save_size */ | |
104 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ | |
105 | int altivec_padding_size; /* size of altivec alignment padding if | |
106 | not in save_size */ | |
107 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
108 | int spe_padding_size; | |
109 | int toc_size; /* size to hold TOC if not in save_size */ | |
110 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ | |
111 | int spe_64bit_regs_used; | |
112 | } rs6000_stack_t; | |
113 | ||
5248c961 RK |
114 | /* Target cpu type */ |
115 | ||
116 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
117 | struct rs6000_cpu_select rs6000_select[3] = |
118 | { | |
815cdc52 MM |
119 | /* switch name, tune arch */ |
120 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
121 | { (const char *)0, "-mcpu=", 1, 1 }, | |
122 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 123 | }; |
5248c961 | 124 | |
ec507f2d DE |
125 | /* Always emit branch hint bits. */ |
126 | static GTY(()) bool rs6000_always_hint; | |
127 | ||
128 | /* Schedule instructions for group formation. */ | |
129 | static GTY(()) bool rs6000_sched_groups; | |
130 | ||
79ae11c4 DN |
131 | /* Support adjust_priority scheduler hook |
132 | and -mprioritize-restricted-insns= option. */ | |
133 | const char *rs6000_sched_restricted_insns_priority_str; | |
134 | int rs6000_sched_restricted_insns_priority; | |
135 | ||
569fa502 DN |
136 | /* Support for -msched-costly-dep option. */ |
137 | const char *rs6000_sched_costly_dep_str; | |
138 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
139 | ||
cbe26ab8 DN |
140 | /* Support for -minsert-sched-nops option. */ |
141 | const char *rs6000_sched_insert_nops_str; | |
142 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
143 | ||
6fa3f289 ZW |
144 | /* Size of long double */ |
145 | const char *rs6000_long_double_size_string; | |
146 | int rs6000_long_double_type_size; | |
147 | ||
148 | /* Whether -mabi=altivec has appeared */ | |
149 | int rs6000_altivec_abi; | |
150 | ||
08b57fb3 AH |
151 | /* Whether VRSAVE instructions should be generated. */ |
152 | int rs6000_altivec_vrsave; | |
153 | ||
154 | /* String from -mvrsave= option. */ | |
155 | const char *rs6000_altivec_vrsave_string; | |
156 | ||
a3170dc6 AH |
157 | /* Nonzero if we want SPE ABI extensions. */ |
158 | int rs6000_spe_abi; | |
159 | ||
160 | /* Whether isel instructions should be generated. */ | |
161 | int rs6000_isel; | |
162 | ||
993f19a8 AH |
163 | /* Whether SPE simd instructions should be generated. */ |
164 | int rs6000_spe; | |
165 | ||
5da702b1 AH |
166 | /* Nonzero if floating point operations are done in the GPRs. */ |
167 | int rs6000_float_gprs = 0; | |
168 | ||
169 | /* String from -mfloat-gprs=. */ | |
170 | const char *rs6000_float_gprs_string; | |
a3170dc6 AH |
171 | |
172 | /* String from -misel=. */ | |
173 | const char *rs6000_isel_string; | |
174 | ||
993f19a8 AH |
175 | /* String from -mspe=. */ |
176 | const char *rs6000_spe_string; | |
177 | ||
a0ab749a | 178 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 179 | static GTY(()) int common_mode_defined; |
c81bebd7 | 180 | |
9878760c RK |
181 | /* Save information from a "cmpxx" operation until the branch or scc is |
182 | emitted. */ | |
9878760c RK |
183 | rtx rs6000_compare_op0, rs6000_compare_op1; |
184 | int rs6000_compare_fp_p; | |
874a0744 | 185 | |
874a0744 MM |
186 | /* Label number of label created for -mrelocatable, to call to so we can |
187 | get the address of the GOT section */ | |
188 | int rs6000_pic_labelno; | |
c81bebd7 | 189 | |
b91da81f | 190 | #ifdef USING_ELFOS_H |
c81bebd7 | 191 | /* Which abi to adhere to */ |
9739c90c | 192 | const char *rs6000_abi_name; |
d9407988 MM |
193 | |
194 | /* Semantics of the small data area */ | |
195 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
196 | ||
197 | /* Which small data model to use */ | |
815cdc52 | 198 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
199 | |
200 | /* Counter for labels which are to be placed in .fixup. */ | |
201 | int fixuplabelno = 0; | |
874a0744 | 202 | #endif |
4697a36c | 203 | |
c4501e62 JJ |
204 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
205 | int rs6000_tls_size = 32; | |
206 | const char *rs6000_tls_size_string; | |
207 | ||
b6c9286a MM |
208 | /* ABI enumeration available for subtarget to use. */ |
209 | enum rs6000_abi rs6000_current_abi; | |
210 | ||
0ac081f6 AH |
211 | /* ABI string from -mabi= option. */ |
212 | const char *rs6000_abi_string; | |
213 | ||
38c1f2d7 | 214 | /* Debug flags */ |
815cdc52 | 215 | const char *rs6000_debug_name; |
38c1f2d7 MM |
216 | int rs6000_debug_stack; /* debug stack applications */ |
217 | int rs6000_debug_arg; /* debug argument handling */ | |
218 | ||
0d1fbc8c AH |
219 | /* Value is TRUE if register/mode pair is accepatable. */ |
220 | bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; | |
221 | ||
6035d635 | 222 | /* Opaque types. */ |
2abe3e28 | 223 | static GTY(()) tree opaque_V2SI_type_node; |
2abe3e28 | 224 | static GTY(()) tree opaque_V2SF_type_node; |
6035d635 | 225 | static GTY(()) tree opaque_p_V2SI_type_node; |
4a5eab38 PB |
226 | static GTY(()) tree V16QI_type_node; |
227 | static GTY(()) tree V2SI_type_node; | |
228 | static GTY(()) tree V2SF_type_node; | |
229 | static GTY(()) tree V4HI_type_node; | |
230 | static GTY(()) tree V4SI_type_node; | |
231 | static GTY(()) tree V4SF_type_node; | |
232 | static GTY(()) tree V8HI_type_node; | |
233 | static GTY(()) tree unsigned_V16QI_type_node; | |
234 | static GTY(()) tree unsigned_V8HI_type_node; | |
235 | static GTY(()) tree unsigned_V4SI_type_node; | |
8bb418a3 ZL |
236 | static GTY(()) tree bool_char_type_node; /* __bool char */ |
237 | static GTY(()) tree bool_short_type_node; /* __bool short */ | |
238 | static GTY(()) tree bool_int_type_node; /* __bool int */ | |
239 | static GTY(()) tree pixel_type_node; /* __pixel */ | |
240 | static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */ | |
241 | static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */ | |
242 | static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */ | |
243 | static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */ | |
244 | ||
245 | int rs6000_warn_altivec_long = 1; /* On by default. */ | |
246 | const char *rs6000_warn_altivec_long_switch; | |
247 | ||
57ac7be9 AM |
248 | const char *rs6000_traceback_name; |
249 | static enum { | |
250 | traceback_default = 0, | |
251 | traceback_none, | |
252 | traceback_part, | |
253 | traceback_full | |
254 | } rs6000_traceback; | |
255 | ||
38c1f2d7 MM |
256 | /* Flag to say the TOC is initialized */ |
257 | int toc_initialized; | |
9ebbca7d | 258 | char toc_label_name[10]; |
38c1f2d7 | 259 | |
9ebbca7d | 260 | /* Alias set for saves and restores from the rs6000 stack. */ |
f103e34d | 261 | static GTY(()) int rs6000_sr_alias_set; |
c8023011 | 262 | |
a5c76ee6 ZW |
263 | /* Call distance, overridden by -mlongcall and #pragma longcall(1). |
264 | The only place that looks at this is rs6000_set_default_type_attributes; | |
265 | everywhere else should rely on the presence or absence of a longcall | |
266 | attribute on the function declaration. */ | |
267 | int rs6000_default_long_calls; | |
268 | const char *rs6000_longcall_switch; | |
269 | ||
a3c9585f KH |
270 | /* Control alignment for fields within structures. */ |
271 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
272 | const char *rs6000_alignment_string; |
273 | int rs6000_alignment_flags; | |
274 | ||
a3170dc6 AH |
275 | struct builtin_description |
276 | { | |
277 | /* mask is not const because we're going to alter it below. This | |
278 | nonsense will go away when we rewrite the -march infrastructure | |
279 | to give us more target flag bits. */ | |
280 | unsigned int mask; | |
281 | const enum insn_code icode; | |
282 | const char *const name; | |
283 | const enum rs6000_builtins code; | |
284 | }; | |
8b897cfa RS |
285 | \f |
286 | /* Target cpu costs. */ | |
287 | ||
288 | struct processor_costs { | |
289 | const int mulsi; /* cost of SImode multiplication. */ | |
290 | const int mulsi_const; /* cost of SImode multiplication by constant. */ | |
291 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
292 | const int muldi; /* cost of DImode multiplication. */ | |
293 | const int divsi; /* cost of SImode division. */ | |
294 | const int divdi; /* cost of DImode division. */ | |
295 | }; | |
296 | ||
297 | const struct processor_costs *rs6000_cost; | |
298 | ||
299 | /* Processor costs (relative to an add) */ | |
300 | ||
301 | /* Instruction size costs on 32bit processors. */ | |
302 | static const | |
303 | struct processor_costs size32_cost = { | |
304 | 1, /* mulsi */ | |
305 | 1, /* mulsi_const */ | |
306 | 1, /* mulsi_const9 */ | |
307 | 1, /* muldi */ | |
308 | 1, /* divsi */ | |
309 | 1, /* divdi */ | |
310 | }; | |
311 | ||
312 | /* Instruction size costs on 64bit processors. */ | |
313 | static const | |
314 | struct processor_costs size64_cost = { | |
315 | 1, /* mulsi */ | |
316 | 1, /* mulsi_const */ | |
317 | 1, /* mulsi_const9 */ | |
318 | 1, /* muldi */ | |
319 | 1, /* divsi */ | |
320 | 1, /* divdi */ | |
321 | }; | |
322 | ||
323 | /* Instruction costs on RIOS1 processors. */ | |
324 | static const | |
325 | struct processor_costs rios1_cost = { | |
326 | 5, /* mulsi */ | |
327 | 4, /* mulsi_const */ | |
328 | 3, /* mulsi_const9 */ | |
329 | 5, /* muldi */ | |
330 | 19, /* divsi */ | |
331 | 19, /* divdi */ | |
332 | }; | |
333 | ||
334 | /* Instruction costs on RIOS2 processors. */ | |
335 | static const | |
336 | struct processor_costs rios2_cost = { | |
337 | 2, /* mulsi */ | |
338 | 2, /* mulsi_const */ | |
339 | 2, /* mulsi_const9 */ | |
340 | 2, /* muldi */ | |
341 | 13, /* divsi */ | |
342 | 13, /* divdi */ | |
343 | }; | |
344 | ||
345 | /* Instruction costs on RS64A processors. */ | |
346 | static const | |
347 | struct processor_costs rs64a_cost = { | |
348 | 20, /* mulsi */ | |
349 | 12, /* mulsi_const */ | |
350 | 8, /* mulsi_const9 */ | |
351 | 34, /* muldi */ | |
352 | 65, /* divsi */ | |
353 | 67, /* divdi */ | |
354 | }; | |
355 | ||
356 | /* Instruction costs on MPCCORE processors. */ | |
357 | static const | |
358 | struct processor_costs mpccore_cost = { | |
359 | 2, /* mulsi */ | |
360 | 2, /* mulsi_const */ | |
361 | 2, /* mulsi_const9 */ | |
362 | 2, /* muldi */ | |
363 | 6, /* divsi */ | |
364 | 6, /* divdi */ | |
365 | }; | |
366 | ||
367 | /* Instruction costs on PPC403 processors. */ | |
368 | static const | |
369 | struct processor_costs ppc403_cost = { | |
370 | 4, /* mulsi */ | |
371 | 4, /* mulsi_const */ | |
372 | 4, /* mulsi_const9 */ | |
373 | 4, /* muldi */ | |
374 | 33, /* divsi */ | |
375 | 33, /* divdi */ | |
376 | }; | |
377 | ||
378 | /* Instruction costs on PPC405 processors. */ | |
379 | static const | |
380 | struct processor_costs ppc405_cost = { | |
381 | 5, /* mulsi */ | |
382 | 4, /* mulsi_const */ | |
383 | 3, /* mulsi_const9 */ | |
384 | 5, /* muldi */ | |
385 | 35, /* divsi */ | |
386 | 35, /* divdi */ | |
387 | }; | |
388 | ||
389 | /* Instruction costs on PPC440 processors. */ | |
390 | static const | |
391 | struct processor_costs ppc440_cost = { | |
392 | 3, /* mulsi */ | |
393 | 2, /* mulsi_const */ | |
394 | 2, /* mulsi_const9 */ | |
395 | 3, /* muldi */ | |
396 | 34, /* divsi */ | |
397 | 34, /* divdi */ | |
398 | }; | |
399 | ||
400 | /* Instruction costs on PPC601 processors. */ | |
401 | static const | |
402 | struct processor_costs ppc601_cost = { | |
403 | 5, /* mulsi */ | |
404 | 5, /* mulsi_const */ | |
405 | 5, /* mulsi_const9 */ | |
406 | 5, /* muldi */ | |
407 | 36, /* divsi */ | |
408 | 36, /* divdi */ | |
409 | }; | |
410 | ||
411 | /* Instruction costs on PPC603 processors. */ | |
412 | static const | |
413 | struct processor_costs ppc603_cost = { | |
414 | 5, /* mulsi */ | |
415 | 3, /* mulsi_const */ | |
416 | 2, /* mulsi_const9 */ | |
417 | 5, /* muldi */ | |
418 | 37, /* divsi */ | |
419 | 37, /* divdi */ | |
420 | }; | |
421 | ||
422 | /* Instruction costs on PPC604 processors. */ | |
423 | static const | |
424 | struct processor_costs ppc604_cost = { | |
425 | 4, /* mulsi */ | |
426 | 4, /* mulsi_const */ | |
427 | 4, /* mulsi_const9 */ | |
428 | 4, /* muldi */ | |
429 | 20, /* divsi */ | |
430 | 20, /* divdi */ | |
431 | }; | |
432 | ||
433 | /* Instruction costs on PPC604e processors. */ | |
434 | static const | |
435 | struct processor_costs ppc604e_cost = { | |
436 | 2, /* mulsi */ | |
437 | 2, /* mulsi_const */ | |
438 | 2, /* mulsi_const9 */ | |
439 | 2, /* muldi */ | |
440 | 20, /* divsi */ | |
441 | 20, /* divdi */ | |
442 | }; | |
443 | ||
444 | /* Instruction costs on PPC620 and PPC630 processors. */ | |
445 | static const | |
446 | struct processor_costs ppc620_cost = { | |
447 | 5, /* mulsi */ | |
448 | 4, /* mulsi_const */ | |
449 | 3, /* mulsi_const9 */ | |
450 | 7, /* muldi */ | |
451 | 21, /* divsi */ | |
452 | 37, /* divdi */ | |
453 | }; | |
454 | ||
455 | /* Instruction costs on PPC750 and PPC7400 processors. */ | |
456 | static const | |
457 | struct processor_costs ppc750_cost = { | |
458 | 5, /* mulsi */ | |
459 | 3, /* mulsi_const */ | |
460 | 2, /* mulsi_const9 */ | |
461 | 5, /* muldi */ | |
462 | 17, /* divsi */ | |
463 | 17, /* divdi */ | |
464 | }; | |
465 | ||
466 | /* Instruction costs on PPC7450 processors. */ | |
467 | static const | |
468 | struct processor_costs ppc7450_cost = { | |
469 | 4, /* mulsi */ | |
470 | 3, /* mulsi_const */ | |
471 | 3, /* mulsi_const9 */ | |
472 | 4, /* muldi */ | |
473 | 23, /* divsi */ | |
474 | 23, /* divdi */ | |
475 | }; | |
a3170dc6 | 476 | |
8b897cfa RS |
477 | /* Instruction costs on PPC8540 processors. */ |
478 | static const | |
479 | struct processor_costs ppc8540_cost = { | |
480 | 4, /* mulsi */ | |
481 | 4, /* mulsi_const */ | |
482 | 4, /* mulsi_const9 */ | |
483 | 4, /* muldi */ | |
484 | 19, /* divsi */ | |
485 | 19, /* divdi */ | |
486 | }; | |
487 | ||
488 | /* Instruction costs on POWER4 and POWER5 processors. */ | |
489 | static const | |
490 | struct processor_costs power4_cost = { | |
491 | 3, /* mulsi */ | |
492 | 2, /* mulsi_const */ | |
493 | 2, /* mulsi_const9 */ | |
494 | 4, /* muldi */ | |
495 | 18, /* divsi */ | |
496 | 34, /* divdi */ | |
497 | }; | |
498 | ||
499 | \f | |
a2369ed3 DJ |
500 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
501 | static int num_insns_constant_wide (HOST_WIDE_INT); | |
502 | static void validate_condition_mode (enum rtx_code, enum machine_mode); | |
503 | static rtx rs6000_generate_compare (enum rtx_code); | |
504 | static void rs6000_maybe_dead (rtx); | |
505 | static void rs6000_emit_stack_tie (void); | |
506 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
507 | static rtx spe_synthesize_frame_save (rtx); | |
508 | static bool spe_func_has_64bit_regs_p (void); | |
b20a9cca | 509 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 510 | int, HOST_WIDE_INT); |
a2369ed3 DJ |
511 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
512 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); | |
513 | static unsigned rs6000_hash_constant (rtx); | |
514 | static unsigned toc_hash_function (const void *); | |
515 | static int toc_hash_eq (const void *, const void *); | |
516 | static int constant_pool_expr_1 (rtx, int *, int *); | |
517 | static bool constant_pool_expr_p (rtx); | |
518 | static bool toc_relative_expr_p (rtx); | |
519 | static bool legitimate_small_data_p (enum machine_mode, rtx); | |
a2369ed3 DJ |
520 | static bool legitimate_indexed_address_p (rtx, int); |
521 | static bool legitimate_indirect_address_p (rtx, int); | |
4c81e946 | 522 | static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode); |
a2369ed3 DJ |
523 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
524 | static struct machine_function * rs6000_init_machine_status (void); | |
525 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
5add3202 | 526 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 527 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 528 | #endif |
a2369ed3 DJ |
529 | static int rs6000_ra_ever_killed (void); |
530 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
8bb418a3 | 531 | static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); |
76d2b81d | 532 | static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); |
f18eca82 | 533 | static const char *rs6000_mangle_fundamental_type (tree); |
b86fe7b4 | 534 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 DJ |
535 | static void rs6000_set_default_type_attributes (tree); |
536 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); | |
537 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
538 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
539 | tree); | |
a2369ed3 | 540 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
c6e8c921 | 541 | static bool rs6000_return_in_memory (tree, tree); |
a2369ed3 | 542 | static void rs6000_file_start (void); |
7c262518 | 543 | #if TARGET_ELF |
a2369ed3 DJ |
544 | static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); |
545 | static void rs6000_elf_asm_out_constructor (rtx, int); | |
546 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
547 | static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); | |
548 | static void rs6000_elf_unique_section (tree, int); | |
549 | static void rs6000_elf_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 550 | unsigned HOST_WIDE_INT); |
a56d7372 | 551 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 552 | ATTRIBUTE_UNUSED; |
a2369ed3 | 553 | static bool rs6000_elf_in_small_data_p (tree); |
7c262518 | 554 | #endif |
cbaaba19 | 555 | #if TARGET_XCOFF |
a2369ed3 DJ |
556 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
557 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int); | |
558 | static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT); | |
559 | static void rs6000_xcoff_unique_section (tree, int); | |
560 | static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 561 | unsigned HOST_WIDE_INT); |
a2369ed3 DJ |
562 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
563 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
564 | static void rs6000_xcoff_file_start (void); | |
565 | static void rs6000_xcoff_file_end (void); | |
f1384257 AM |
566 | #endif |
567 | #if TARGET_MACHO | |
a2369ed3 | 568 | static bool rs6000_binds_local_p (tree); |
f1384257 | 569 | #endif |
a2369ed3 DJ |
570 | static int rs6000_variable_issue (FILE *, int, rtx, int); |
571 | static bool rs6000_rtx_costs (rtx, int, int, int *); | |
572 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); | |
cbe26ab8 | 573 | static bool is_microcoded_insn (rtx); |
79ae11c4 | 574 | static int is_dispatch_slot_restricted (rtx); |
cbe26ab8 DN |
575 | static bool is_cracked_insn (rtx); |
576 | static bool is_branch_slot_insn (rtx); | |
a2369ed3 DJ |
577 | static int rs6000_adjust_priority (rtx, int); |
578 | static int rs6000_issue_rate (void); | |
569fa502 | 579 | static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); |
cbe26ab8 DN |
580 | static rtx get_next_active_insn (rtx, rtx); |
581 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
582 | static bool is_costly_group (rtx *, rtx); | |
583 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
584 | static int redefine_groups (FILE *, int, rtx, rtx); | |
585 | static int pad_groups (FILE *, int, rtx, rtx); | |
586 | static void rs6000_sched_finish (FILE *, int); | |
a2369ed3 DJ |
587 | static int rs6000_use_sched_lookahead (void); |
588 | ||
589 | static void rs6000_init_builtins (void); | |
590 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
591 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
592 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
593 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
594 | static void altivec_init_builtins (void); | |
595 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 596 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 597 | |
b20a9cca AM |
598 | static void enable_mask_for_builtins (struct builtin_description *, int, |
599 | enum rs6000_builtins, | |
600 | enum rs6000_builtins); | |
7c62e993 | 601 | static tree build_opaque_vector_type (tree, int); |
a2369ed3 DJ |
602 | static void spe_init_builtins (void); |
603 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
61bea3b0 | 604 | static rtx spe_expand_stv_builtin (enum insn_code, tree); |
a2369ed3 DJ |
605 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); |
606 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
607 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
608 | static rs6000_stack_t *rs6000_stack_info (void); |
609 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
610 | |
611 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
612 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
613 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
614 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
615 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
616 | static rtx altivec_expand_predicate_builtin (enum insn_code, | |
617 | const char *, tree, rtx); | |
b4a62fa0 | 618 | static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); |
a2369ed3 DJ |
619 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
620 | static void rs6000_parse_abi_options (void); | |
621 | static void rs6000_parse_alignment_option (void); | |
622 | static void rs6000_parse_tls_size_option (void); | |
5da702b1 | 623 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
a2369ed3 DJ |
624 | static int first_altivec_reg_to_save (void); |
625 | static unsigned int compute_vrsave_mask (void); | |
626 | static void is_altivec_return_reg (rtx, void *); | |
627 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
628 | int easy_vector_constant (rtx, enum machine_mode); | |
629 | static int easy_vector_same (rtx, enum machine_mode); | |
452a7d36 | 630 | static int easy_vector_splat_const (int, enum machine_mode); |
a2369ed3 DJ |
631 | static bool is_ev64_opaque_type (tree); |
632 | static rtx rs6000_dwarf_register_span (rtx); | |
633 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); | |
634 | static rtx rs6000_tls_get_addr (void); | |
635 | static rtx rs6000_got_sym (void); | |
636 | static inline int rs6000_tls_symbol_ref_1 (rtx *, void *); | |
637 | static const char *rs6000_get_some_local_dynamic_name (void); | |
638 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 639 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 640 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 641 | enum machine_mode, tree); |
ec6376ab | 642 | static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); |
b1917422 | 643 | static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); |
c6e8c921 GK |
644 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
645 | enum machine_mode, tree, | |
646 | int *, int); | |
efdba735 SH |
647 | #if TARGET_MACHO |
648 | static void macho_branch_islands (void); | |
649 | static void add_compiler_branch_island (tree, tree, int); | |
650 | static int no_previous_def (tree function_name); | |
651 | static tree get_prev_label (tree function_name); | |
652 | #endif | |
653 | ||
c35d187f | 654 | static tree rs6000_build_builtin_va_list (void); |
23a60a04 | 655 | static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); |
17211ab5 GK |
656 | |
657 | /* Hash table stuff for keeping track of TOC entries. */ | |
658 | ||
659 | struct toc_hash_struct GTY(()) | |
660 | { | |
661 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
662 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
663 | rtx key; | |
664 | enum machine_mode key_mode; | |
665 | int labelno; | |
666 | }; | |
667 | ||
668 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
669 | \f |
670 | /* Default register names. */ | |
671 | char rs6000_reg_names[][8] = | |
672 | { | |
802a0058 MM |
673 | "0", "1", "2", "3", "4", "5", "6", "7", |
674 | "8", "9", "10", "11", "12", "13", "14", "15", | |
675 | "16", "17", "18", "19", "20", "21", "22", "23", | |
676 | "24", "25", "26", "27", "28", "29", "30", "31", | |
677 | "0", "1", "2", "3", "4", "5", "6", "7", | |
678 | "8", "9", "10", "11", "12", "13", "14", "15", | |
679 | "16", "17", "18", "19", "20", "21", "22", "23", | |
680 | "24", "25", "26", "27", "28", "29", "30", "31", | |
681 | "mq", "lr", "ctr","ap", | |
682 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
683 | "xer", |
684 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
685 | "0", "1", "2", "3", "4", "5", "6", "7", |
686 | "8", "9", "10", "11", "12", "13", "14", "15", | |
687 | "16", "17", "18", "19", "20", "21", "22", "23", | |
688 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
689 | "vrsave", "vscr", |
690 | /* SPE registers. */ | |
691 | "spe_acc", "spefscr" | |
c81bebd7 MM |
692 | }; |
693 | ||
694 | #ifdef TARGET_REGNAMES | |
8b60264b | 695 | static const char alt_reg_names[][8] = |
c81bebd7 | 696 | { |
802a0058 MM |
697 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
698 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
699 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
700 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
701 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
702 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
703 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
704 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
705 | "mq", "lr", "ctr", "ap", | |
706 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 707 | "xer", |
59a4c851 | 708 | /* AltiVec registers. */ |
0ac081f6 | 709 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
710 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
711 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
712 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
713 | "vrsave", "vscr", | |
714 | /* SPE registers. */ | |
715 | "spe_acc", "spefscr" | |
c81bebd7 MM |
716 | }; |
717 | #endif | |
9878760c | 718 | \f |
daf11973 MM |
719 | #ifndef MASK_STRICT_ALIGN |
720 | #define MASK_STRICT_ALIGN 0 | |
721 | #endif | |
ffcfcb5f AM |
722 | #ifndef TARGET_PROFILE_KERNEL |
723 | #define TARGET_PROFILE_KERNEL 0 | |
724 | #endif | |
3961e8fe RH |
725 | |
726 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
727 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
c4501e62 JJ |
728 | |
729 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ | |
730 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
731 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
672a6f42 NB |
732 | \f |
733 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
734 | #undef TARGET_ATTRIBUTE_TABLE |
735 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
736 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
737 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 738 | |
301d03af RS |
739 | #undef TARGET_ASM_ALIGNED_DI_OP |
740 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
741 | ||
742 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
743 | for non-ELF systems. */ | |
744 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 745 | #if TARGET_XCOFF |
ae6c1efd | 746 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
747 | 64-bit targets. */ |
748 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
749 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
750 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
751 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
752 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
753 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
754 | #else | |
755 | /* For Darwin. */ | |
756 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
757 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
758 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
759 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
760 | #endif | |
761 | #endif | |
762 | ||
763 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
764 | in 64-bit code. */ | |
765 | #undef TARGET_ASM_INTEGER | |
766 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
767 | ||
93638d7a AM |
768 | #ifdef HAVE_GAS_HIDDEN |
769 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
770 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
771 | #endif | |
772 | ||
c4501e62 JJ |
773 | #undef TARGET_HAVE_TLS |
774 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
775 | ||
776 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
777 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p | |
778 | ||
08c148a8 NB |
779 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
780 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
781 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
782 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
783 | ||
b54cf83a | 784 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
11ac38b2 | 785 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1 |
b54cf83a DE |
786 | #undef TARGET_SCHED_VARIABLE_ISSUE |
787 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
788 | ||
c237e94a ZW |
789 | #undef TARGET_SCHED_ISSUE_RATE |
790 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
791 | #undef TARGET_SCHED_ADJUST_COST | |
792 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
793 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
794 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
569fa502 DN |
795 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
796 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence | |
cbe26ab8 DN |
797 | #undef TARGET_SCHED_FINISH |
798 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
c237e94a | 799 | |
be12c2b0 VM |
800 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
801 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
802 | ||
0ac081f6 AH |
803 | #undef TARGET_INIT_BUILTINS |
804 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
805 | ||
806 | #undef TARGET_EXPAND_BUILTIN | |
807 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
808 | ||
f18eca82 ZL |
809 | #undef TARGET_MANGLE_FUNDAMENTAL_TYPE |
810 | #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type | |
811 | ||
c15c90bb ZW |
812 | #undef TARGET_INIT_LIBFUNCS |
813 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
814 | ||
f1384257 | 815 | #if TARGET_MACHO |
0e5dbd9b DE |
816 | #undef TARGET_BINDS_LOCAL_P |
817 | #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p | |
f1384257 | 818 | #endif |
0e5dbd9b | 819 | |
3961e8fe RH |
820 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
821 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
822 | ||
3961e8fe | 823 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 824 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 825 | |
4977bab6 ZW |
826 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
827 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
828 | ||
3c50106f RH |
829 | #undef TARGET_RTX_COSTS |
830 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
831 | #undef TARGET_ADDRESS_COST |
832 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 833 | |
c8e4f0e9 AH |
834 | #undef TARGET_VECTOR_OPAQUE_P |
835 | #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type | |
62e1dfcf | 836 | |
96714395 AH |
837 | #undef TARGET_DWARF_REGISTER_SPAN |
838 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
839 | ||
c6e8c921 GK |
840 | /* On rs6000, function arguments are promoted, as are function return |
841 | values. */ | |
842 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
843 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
844 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
845 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
846 | ||
c6e8c921 GK |
847 | #undef TARGET_RETURN_IN_MEMORY |
848 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
849 | ||
850 | #undef TARGET_SETUP_INCOMING_VARARGS | |
851 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
852 | ||
853 | /* Always strict argument naming on rs6000. */ | |
854 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
855 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
856 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
857 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
42ba5130 RH |
858 | #undef TARGET_SPLIT_COMPLEX_ARG |
859 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true | |
c6e8c921 | 860 | |
c35d187f RH |
861 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
862 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
863 | ||
cd3ce9b4 JM |
864 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
865 | #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg | |
866 | ||
f6897b10 | 867 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 868 | \f |
0d1fbc8c AH |
869 | |
870 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
871 | MODE. */ | |
872 | static int | |
873 | rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
874 | { | |
875 | /* The GPRs can hold any mode, but values bigger than one register | |
876 | cannot go past R31. */ | |
877 | if (INT_REGNO_P (regno)) | |
878 | return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); | |
879 | ||
880 | /* The float registers can only hold floating modes and DImode. */ | |
881 | if (FP_REGNO_P (regno)) | |
882 | return | |
883 | (GET_MODE_CLASS (mode) == MODE_FLOAT | |
884 | && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) | |
885 | || (GET_MODE_CLASS (mode) == MODE_INT | |
886 | && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD); | |
887 | ||
888 | /* The CR register can only hold CC modes. */ | |
889 | if (CR_REGNO_P (regno)) | |
890 | return GET_MODE_CLASS (mode) == MODE_CC; | |
891 | ||
892 | if (XER_REGNO_P (regno)) | |
893 | return mode == PSImode; | |
894 | ||
895 | /* AltiVec only in AldyVec registers. */ | |
896 | if (ALTIVEC_REGNO_P (regno)) | |
897 | return ALTIVEC_VECTOR_MODE (mode); | |
898 | ||
899 | /* ...but GPRs can hold SIMD data on the SPE in one register. */ | |
900 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
901 | return 1; | |
902 | ||
903 | /* We cannot put TImode anywhere except general register and it must be | |
904 | able to fit within the register set. */ | |
905 | ||
906 | return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; | |
907 | } | |
908 | ||
909 | /* Initialize rs6000_hard_regno_mode_ok_p table. */ | |
910 | static void | |
911 | rs6000_init_hard_regno_mode_ok (void) | |
912 | { | |
913 | int r, m; | |
914 | ||
915 | for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) | |
916 | for (m = 0; m < NUM_MACHINE_MODES; ++m) | |
917 | if (rs6000_hard_regno_mode_ok (r, m)) | |
918 | rs6000_hard_regno_mode_ok_p[m][r] = true; | |
919 | } | |
920 | ||
5248c961 RK |
921 | /* Override command line options. Mostly we process the processor |
922 | type and sometimes adjust other TARGET_ options. */ | |
923 | ||
924 | void | |
d779d0dc | 925 | rs6000_override_options (const char *default_cpu) |
5248c961 | 926 | { |
c4d38ccb | 927 | size_t i, j; |
8e3f41e7 | 928 | struct rs6000_cpu_select *ptr; |
66188a7e | 929 | int set_masks; |
5248c961 | 930 | |
66188a7e | 931 | /* Simplifications for entries below. */ |
85638c0d | 932 | |
66188a7e GK |
933 | enum { |
934 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
935 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
936 | }; | |
85638c0d | 937 | |
66188a7e GK |
938 | /* This table occasionally claims that a processor does not support |
939 | a particular feature even though it does, but the feature is slower | |
940 | than the alternative. Thus, it shouldn't be relied on as a | |
941 | complete description of the processor's support. | |
942 | ||
943 | Please keep this list in order, and don't forget to update the | |
944 | documentation in invoke.texi when adding a new processor or | |
945 | flag. */ | |
5248c961 RK |
946 | static struct ptt |
947 | { | |
8b60264b KG |
948 | const char *const name; /* Canonical processor name. */ |
949 | const enum processor_type processor; /* Processor type enum value. */ | |
950 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 951 | } const processor_target_table[] |
66188a7e | 952 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 953 | {"403", PROCESSOR_PPC403, |
66188a7e GK |
954 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
955 | {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
956 | {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK}, | |
957 | {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
958 | {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK}, | |
959 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, | |
5248c961 | 960 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
961 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
962 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
963 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
964 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
965 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
966 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
967 | {"620", PROCESSOR_PPC620, |
968 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
969 | {"630", PROCESSOR_PPC630, | |
970 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
971 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
972 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
973 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
974 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
975 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
976 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
977 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
978 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
979 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
7177e720 | 980 | {"970", PROCESSOR_POWER4, |
66188a7e GK |
981 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
982 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, | |
983 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
984 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
985 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 986 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
987 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
988 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
989 | {"power2", PROCESSOR_POWER, | |
990 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
991 | {"power3", PROCESSOR_PPC630, |
992 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
993 | {"power4", PROCESSOR_POWER4, | |
fc091c8e | 994 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
ec507f2d | 995 | {"power5", PROCESSOR_POWER5, |
fc091c8e | 996 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
66188a7e GK |
997 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
998 | {"powerpc64", PROCESSOR_POWERPC64, | |
999 | POWERPC_BASE_MASK | MASK_POWERPC64}, | |
1000 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1001 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1002 | {"rios2", PROCESSOR_RIOS2, | |
1003 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
1004 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1005 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 | 1006 | {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64}, |
66188a7e | 1007 | }; |
5248c961 | 1008 | |
ca7558fc | 1009 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 1010 | |
66188a7e GK |
1011 | /* Some OSs don't support saving the high part of 64-bit registers on |
1012 | context switch. Other OSs don't support saving Altivec registers. | |
1013 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
1014 | settings; if the user wants either, the user must explicitly specify | |
1015 | them and we won't interfere with the user's specification. */ | |
1016 | ||
1017 | enum { | |
1018 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
1019 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | |
1020 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC | |
1021 | | MASK_MFCRF) | |
1022 | }; | |
0d1fbc8c AH |
1023 | |
1024 | rs6000_init_hard_regno_mode_ok (); | |
1025 | ||
66188a7e GK |
1026 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; |
1027 | #ifdef OS_MISSING_POWERPC64 | |
1028 | if (OS_MISSING_POWERPC64) | |
1029 | set_masks &= ~MASK_POWERPC64; | |
1030 | #endif | |
1031 | #ifdef OS_MISSING_ALTIVEC | |
1032 | if (OS_MISSING_ALTIVEC) | |
1033 | set_masks &= ~MASK_ALTIVEC; | |
1034 | #endif | |
1035 | ||
957211c3 AM |
1036 | /* Don't override these by the processor default if given explicitly. */ |
1037 | set_masks &= ~(target_flags_explicit | |
1038 | & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT)); | |
1039 | ||
a4f6c312 | 1040 | /* Identify the processor type. */ |
8e3f41e7 | 1041 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 1042 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 1043 | |
b6a1cbae | 1044 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 1045 | { |
8e3f41e7 MM |
1046 | ptr = &rs6000_select[i]; |
1047 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 1048 | { |
8e3f41e7 MM |
1049 | for (j = 0; j < ptt_size; j++) |
1050 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
1051 | { | |
1052 | if (ptr->set_tune_p) | |
1053 | rs6000_cpu = processor_target_table[j].processor; | |
1054 | ||
1055 | if (ptr->set_arch_p) | |
1056 | { | |
66188a7e GK |
1057 | target_flags &= ~set_masks; |
1058 | target_flags |= (processor_target_table[j].target_enable | |
1059 | & set_masks); | |
8e3f41e7 MM |
1060 | } |
1061 | break; | |
1062 | } | |
1063 | ||
4406229e | 1064 | if (j == ptt_size) |
8e3f41e7 | 1065 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
1066 | } |
1067 | } | |
8a61d227 | 1068 | |
993f19a8 | 1069 | if (TARGET_E500) |
a3170dc6 AH |
1070 | rs6000_isel = 1; |
1071 | ||
dff9f1b6 DE |
1072 | /* If we are optimizing big endian systems for space, use the load/store |
1073 | multiple and string instructions. */ | |
ef792183 | 1074 | if (BYTES_BIG_ENDIAN && optimize_size) |
957211c3 | 1075 | target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); |
938937d8 | 1076 | |
a4f6c312 SS |
1077 | /* Don't allow -mmultiple or -mstring on little endian systems |
1078 | unless the cpu is a 750, because the hardware doesn't support the | |
1079 | instructions used in little endian mode, and causes an alignment | |
1080 | trap. The 750 does not cause an alignment trap (except when the | |
1081 | target is unaligned). */ | |
bef84347 | 1082 | |
b21fb038 | 1083 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
1084 | { |
1085 | if (TARGET_MULTIPLE) | |
1086 | { | |
1087 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 1088 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
7e69e155 MM |
1089 | warning ("-mmultiple is not supported on little endian systems"); |
1090 | } | |
1091 | ||
1092 | if (TARGET_STRING) | |
1093 | { | |
1094 | target_flags &= ~MASK_STRING; | |
b21fb038 | 1095 | if ((target_flags_explicit & MASK_STRING) != 0) |
938937d8 | 1096 | warning ("-mstring is not supported on little endian systems"); |
7e69e155 MM |
1097 | } |
1098 | } | |
3933e0e1 | 1099 | |
38c1f2d7 MM |
1100 | /* Set debug flags */ |
1101 | if (rs6000_debug_name) | |
1102 | { | |
bfc79d3b | 1103 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 1104 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 1105 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 1106 | rs6000_debug_stack = 1; |
bfc79d3b | 1107 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
1108 | rs6000_debug_arg = 1; |
1109 | else | |
c725bd79 | 1110 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
1111 | } |
1112 | ||
57ac7be9 AM |
1113 | if (rs6000_traceback_name) |
1114 | { | |
1115 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
1116 | rs6000_traceback = traceback_full; | |
1117 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
1118 | rs6000_traceback = traceback_part; | |
1119 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
1120 | rs6000_traceback = traceback_none; | |
1121 | else | |
1122 | error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'", | |
1123 | rs6000_traceback_name); | |
1124 | } | |
1125 | ||
6fa3f289 ZW |
1126 | /* Set size of long double */ |
1127 | rs6000_long_double_type_size = 64; | |
1128 | if (rs6000_long_double_size_string) | |
1129 | { | |
1130 | char *tail; | |
1131 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
1132 | if (*tail != '\0' || (size != 64 && size != 128)) | |
1133 | error ("Unknown switch -mlong-double-%s", | |
1134 | rs6000_long_double_size_string); | |
1135 | else | |
1136 | rs6000_long_double_type_size = size; | |
1137 | } | |
1138 | ||
6d0ef01e HP |
1139 | /* Set Altivec ABI as default for powerpc64 linux. */ |
1140 | if (TARGET_ELF && TARGET_64BIT) | |
1141 | { | |
1142 | rs6000_altivec_abi = 1; | |
1143 | rs6000_altivec_vrsave = 1; | |
1144 | } | |
1145 | ||
0ac081f6 AH |
1146 | /* Handle -mabi= options. */ |
1147 | rs6000_parse_abi_options (); | |
1148 | ||
025d9908 KH |
1149 | /* Handle -malign-XXXXX option. */ |
1150 | rs6000_parse_alignment_option (); | |
1151 | ||
5da702b1 AH |
1152 | /* Handle generic -mFOO=YES/NO options. */ |
1153 | rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string, | |
1154 | &rs6000_altivec_vrsave); | |
1155 | rs6000_parse_yes_no_option ("isel", rs6000_isel_string, | |
1156 | &rs6000_isel); | |
1157 | rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe); | |
1158 | rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string, | |
1159 | &rs6000_float_gprs); | |
993f19a8 | 1160 | |
c4501e62 JJ |
1161 | /* Handle -mtls-size option. */ |
1162 | rs6000_parse_tls_size_option (); | |
1163 | ||
a7ae18e2 AH |
1164 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1165 | SUBTARGET_OVERRIDE_OPTIONS; | |
1166 | #endif | |
1167 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
1168 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
1169 | #endif | |
1170 | ||
5da702b1 AH |
1171 | if (TARGET_E500) |
1172 | { | |
e4463bf1 AH |
1173 | if (TARGET_ALTIVEC) |
1174 | error ("AltiVec and E500 instructions cannot coexist"); | |
1175 | ||
5da702b1 AH |
1176 | /* The e500 does not have string instructions, and we set |
1177 | MASK_STRING above when optimizing for size. */ | |
1178 | if ((target_flags & MASK_STRING) != 0) | |
1179 | target_flags = target_flags & ~MASK_STRING; | |
b6e59a3a AH |
1180 | |
1181 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
1182 | if (rs6000_spe_string != 0 | |
1183 | && !strcmp (rs6000_spe_string, "no")) | |
1184 | rs6000_long_double_type_size = 64; | |
5da702b1 AH |
1185 | } |
1186 | else if (rs6000_select[1].string != NULL) | |
1187 | { | |
1188 | /* For the powerpc-eabispe configuration, we set all these by | |
1189 | default, so let's unset them if we manually set another | |
1190 | CPU that is not the E500. */ | |
1191 | if (rs6000_abi_string == 0) | |
1192 | rs6000_spe_abi = 0; | |
1193 | if (rs6000_spe_string == 0) | |
1194 | rs6000_spe = 0; | |
1195 | if (rs6000_float_gprs_string == 0) | |
1196 | rs6000_float_gprs = 0; | |
1197 | if (rs6000_isel_string == 0) | |
1198 | rs6000_isel = 0; | |
b6e59a3a AH |
1199 | if (rs6000_long_double_size_string == 0) |
1200 | rs6000_long_double_type_size = 64; | |
5da702b1 | 1201 | } |
b5044283 | 1202 | |
ec507f2d DE |
1203 | rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 |
1204 | && rs6000_cpu != PROCESSOR_POWER5); | |
1205 | rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 | |
1206 | || rs6000_cpu == PROCESSOR_POWER5); | |
1207 | ||
a5c76ee6 ZW |
1208 | /* Handle -m(no-)longcall option. This is a bit of a cheap hack, |
1209 | using TARGET_OPTIONS to handle a toggle switch, but we're out of | |
1210 | bits in target_flags so TARGET_SWITCHES cannot be used. | |
1211 | Assumption here is that rs6000_longcall_switch points into the | |
1212 | text of the complete option, rather than being a copy, so we can | |
1213 | scan back for the presence or absence of the no- modifier. */ | |
1214 | if (rs6000_longcall_switch) | |
1215 | { | |
1216 | const char *base = rs6000_longcall_switch; | |
1217 | while (base[-1] != 'm') base--; | |
1218 | ||
1219 | if (*rs6000_longcall_switch != '\0') | |
1220 | error ("invalid option `%s'", base); | |
1221 | rs6000_default_long_calls = (base[0] != 'n'); | |
1222 | } | |
1223 | ||
8bb418a3 ZL |
1224 | /* Handle -m(no-)warn-altivec-long similarly. */ |
1225 | if (rs6000_warn_altivec_long_switch) | |
1226 | { | |
1227 | const char *base = rs6000_warn_altivec_long_switch; | |
1228 | while (base[-1] != 'm') base--; | |
1229 | ||
1230 | if (*rs6000_warn_altivec_long_switch != '\0') | |
1231 | error ("invalid option `%s'", base); | |
1232 | rs6000_warn_altivec_long = (base[0] != 'n'); | |
1233 | } | |
1234 | ||
cbe26ab8 | 1235 | /* Handle -mprioritize-restricted-insns option. */ |
ec507f2d DE |
1236 | rs6000_sched_restricted_insns_priority |
1237 | = (rs6000_sched_groups ? 1 : 0); | |
79ae11c4 DN |
1238 | if (rs6000_sched_restricted_insns_priority_str) |
1239 | rs6000_sched_restricted_insns_priority = | |
1240 | atoi (rs6000_sched_restricted_insns_priority_str); | |
1241 | ||
569fa502 | 1242 | /* Handle -msched-costly-dep option. */ |
ec507f2d DE |
1243 | rs6000_sched_costly_dep |
1244 | = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); | |
569fa502 DN |
1245 | if (rs6000_sched_costly_dep_str) |
1246 | { | |
1247 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) | |
1248 | rs6000_sched_costly_dep = no_dep_costly; | |
1249 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) | |
1250 | rs6000_sched_costly_dep = all_deps_costly; | |
1251 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) | |
1252 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; | |
1253 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) | |
1254 | rs6000_sched_costly_dep = store_to_load_dep_costly; | |
cbe26ab8 DN |
1255 | else |
1256 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); | |
1257 | } | |
1258 | ||
1259 | /* Handle -minsert-sched-nops option. */ | |
ec507f2d DE |
1260 | rs6000_sched_insert_nops |
1261 | = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); | |
cbe26ab8 DN |
1262 | if (rs6000_sched_insert_nops_str) |
1263 | { | |
1264 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
1265 | rs6000_sched_insert_nops = sched_finish_none; | |
1266 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) | |
1267 | rs6000_sched_insert_nops = sched_finish_pad_groups; | |
1268 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) | |
1269 | rs6000_sched_insert_nops = sched_finish_regroup_exact; | |
1270 | else | |
1271 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); | |
569fa502 DN |
1272 | } |
1273 | ||
c81bebd7 | 1274 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
1275 | /* If the user desires alternate register names, copy in the |
1276 | alternate names now. */ | |
c81bebd7 | 1277 | if (TARGET_REGNAMES) |
4e135bdd | 1278 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
1279 | #endif |
1280 | ||
6fa3f289 ZW |
1281 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
1282 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
1283 | used, don't override with the ABI default. */ | |
b21fb038 | 1284 | if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0) |
6fa3f289 ZW |
1285 | { |
1286 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
1287 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
1288 | else | |
1289 | target_flags |= MASK_AIX_STRUCT_RET; | |
1290 | } | |
1291 | ||
fcce224d DE |
1292 | if (TARGET_LONG_DOUBLE_128 |
1293 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
70a01792 | 1294 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 1295 | |
9ebbca7d GK |
1296 | /* Allocate an alias set for register saves & restores from stack. */ |
1297 | rs6000_sr_alias_set = new_alias_set (); | |
1298 | ||
1299 | if (TARGET_TOC) | |
1300 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca | 1301 | |
301d03af RS |
1302 | /* We can only guarantee the availability of DI pseudo-ops when |
1303 | assembling for 64-bit targets. */ | |
ae6c1efd | 1304 | if (!TARGET_64BIT) |
301d03af RS |
1305 | { |
1306 | targetm.asm_out.aligned_op.di = NULL; | |
1307 | targetm.asm_out.unaligned_op.di = NULL; | |
1308 | } | |
1309 | ||
2792d578 DE |
1310 | /* Set maximum branch target alignment at two instructions, eight bytes. */ |
1311 | align_jumps_max_skip = 8; | |
1312 | align_loops_max_skip = 8; | |
1313 | ||
71f123ca FS |
1314 | /* Arrange to save and restore machine status around nested functions. */ |
1315 | init_machine_status = rs6000_init_machine_status; | |
42ba5130 RH |
1316 | |
1317 | /* We should always be splitting complex arguments, but we can't break | |
1318 | Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ | |
1319 | if (DEFAULT_ABI != ABI_AIX) | |
1320 | targetm.calls.split_complex_arg = NULL; | |
8b897cfa RS |
1321 | |
1322 | /* Initialize rs6000_cost with the appropriate target costs. */ | |
1323 | if (optimize_size) | |
1324 | rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; | |
1325 | else | |
1326 | switch (rs6000_cpu) | |
1327 | { | |
1328 | case PROCESSOR_RIOS1: | |
1329 | rs6000_cost = &rios1_cost; | |
1330 | break; | |
1331 | ||
1332 | case PROCESSOR_RIOS2: | |
1333 | rs6000_cost = &rios2_cost; | |
1334 | break; | |
1335 | ||
1336 | case PROCESSOR_RS64A: | |
1337 | rs6000_cost = &rs64a_cost; | |
1338 | break; | |
1339 | ||
1340 | case PROCESSOR_MPCCORE: | |
1341 | rs6000_cost = &mpccore_cost; | |
1342 | break; | |
1343 | ||
1344 | case PROCESSOR_PPC403: | |
1345 | rs6000_cost = &ppc403_cost; | |
1346 | break; | |
1347 | ||
1348 | case PROCESSOR_PPC405: | |
1349 | rs6000_cost = &ppc405_cost; | |
1350 | break; | |
1351 | ||
1352 | case PROCESSOR_PPC440: | |
1353 | rs6000_cost = &ppc440_cost; | |
1354 | break; | |
1355 | ||
1356 | case PROCESSOR_PPC601: | |
1357 | rs6000_cost = &ppc601_cost; | |
1358 | break; | |
1359 | ||
1360 | case PROCESSOR_PPC603: | |
1361 | rs6000_cost = &ppc603_cost; | |
1362 | break; | |
1363 | ||
1364 | case PROCESSOR_PPC604: | |
1365 | rs6000_cost = &ppc604_cost; | |
1366 | break; | |
1367 | ||
1368 | case PROCESSOR_PPC604e: | |
1369 | rs6000_cost = &ppc604e_cost; | |
1370 | break; | |
1371 | ||
1372 | case PROCESSOR_PPC620: | |
1373 | case PROCESSOR_PPC630: | |
1374 | rs6000_cost = &ppc620_cost; | |
1375 | break; | |
1376 | ||
1377 | case PROCESSOR_PPC750: | |
1378 | case PROCESSOR_PPC7400: | |
1379 | rs6000_cost = &ppc750_cost; | |
1380 | break; | |
1381 | ||
1382 | case PROCESSOR_PPC7450: | |
1383 | rs6000_cost = &ppc7450_cost; | |
1384 | break; | |
1385 | ||
1386 | case PROCESSOR_PPC8540: | |
1387 | rs6000_cost = &ppc8540_cost; | |
1388 | break; | |
1389 | ||
1390 | case PROCESSOR_POWER4: | |
1391 | case PROCESSOR_POWER5: | |
1392 | rs6000_cost = &power4_cost; | |
1393 | break; | |
1394 | ||
1395 | default: | |
1396 | abort (); | |
1397 | } | |
5248c961 | 1398 | } |
5accd822 | 1399 | |
5da702b1 AH |
1400 | /* Handle generic options of the form -mfoo=yes/no. |
1401 | NAME is the option name. | |
1402 | VALUE is the option value. | |
1403 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
1404 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 1405 | static void |
5da702b1 | 1406 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 1407 | { |
5da702b1 | 1408 | if (value == 0) |
993f19a8 | 1409 | return; |
5da702b1 AH |
1410 | else if (!strcmp (value, "yes")) |
1411 | *flag = 1; | |
1412 | else if (!strcmp (value, "no")) | |
1413 | *flag = 0; | |
08b57fb3 | 1414 | else |
5da702b1 | 1415 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
1416 | } |
1417 | ||
0ac081f6 | 1418 | /* Handle -mabi= options. */ |
00b960c7 | 1419 | static void |
863d938c | 1420 | rs6000_parse_abi_options (void) |
0ac081f6 AH |
1421 | { |
1422 | if (rs6000_abi_string == 0) | |
1423 | return; | |
1424 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
5cc73f91 AH |
1425 | { |
1426 | rs6000_altivec_abi = 1; | |
1427 | rs6000_spe_abi = 0; | |
1428 | } | |
76a773f3 AH |
1429 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
1430 | rs6000_altivec_abi = 0; | |
a3170dc6 | 1431 | else if (! strcmp (rs6000_abi_string, "spe")) |
01f4962d NS |
1432 | { |
1433 | rs6000_spe_abi = 1; | |
5cc73f91 | 1434 | rs6000_altivec_abi = 0; |
01f4962d NS |
1435 | if (!TARGET_SPE_ABI) |
1436 | error ("not configured for ABI: '%s'", rs6000_abi_string); | |
1437 | } | |
1438 | ||
a3170dc6 AH |
1439 | else if (! strcmp (rs6000_abi_string, "no-spe")) |
1440 | rs6000_spe_abi = 0; | |
0ac081f6 | 1441 | else |
c725bd79 | 1442 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
1443 | } |
1444 | ||
025d9908 KH |
1445 | /* Handle -malign-XXXXXX options. */ |
1446 | static void | |
863d938c | 1447 | rs6000_parse_alignment_option (void) |
025d9908 | 1448 | { |
b20a9cca AM |
1449 | if (rs6000_alignment_string == 0) |
1450 | return; | |
1451 | else if (! strcmp (rs6000_alignment_string, "power")) | |
025d9908 KH |
1452 | rs6000_alignment_flags = MASK_ALIGN_POWER; |
1453 | else if (! strcmp (rs6000_alignment_string, "natural")) | |
1454 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
1455 | else | |
1456 | error ("unknown -malign-XXXXX option specified: '%s'", | |
1457 | rs6000_alignment_string); | |
1458 | } | |
1459 | ||
c4501e62 JJ |
1460 | /* Validate and record the size specified with the -mtls-size option. */ |
1461 | ||
1462 | static void | |
863d938c | 1463 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
1464 | { |
1465 | if (rs6000_tls_size_string == 0) | |
1466 | return; | |
1467 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
1468 | rs6000_tls_size = 16; | |
1469 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
1470 | rs6000_tls_size = 32; | |
1471 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
1472 | rs6000_tls_size = 64; | |
1473 | else | |
1474 | error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string); | |
1475 | } | |
1476 | ||
5accd822 | 1477 | void |
a2369ed3 | 1478 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 1479 | { |
5accd822 | 1480 | } |
3cfa4909 MM |
1481 | \f |
1482 | /* Do anything needed at the start of the asm file. */ | |
1483 | ||
1bc7c5b6 | 1484 | static void |
863d938c | 1485 | rs6000_file_start (void) |
3cfa4909 | 1486 | { |
c4d38ccb | 1487 | size_t i; |
3cfa4909 | 1488 | char buffer[80]; |
d330fd93 | 1489 | const char *start = buffer; |
3cfa4909 | 1490 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
1491 | const char *default_cpu = TARGET_CPU_DEFAULT; |
1492 | FILE *file = asm_out_file; | |
1493 | ||
1494 | default_file_start (); | |
1495 | ||
1496 | #ifdef TARGET_BI_ARCH | |
1497 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
1498 | default_cpu = 0; | |
1499 | #endif | |
3cfa4909 MM |
1500 | |
1501 | if (flag_verbose_asm) | |
1502 | { | |
1503 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
1504 | rs6000_select[0].string = default_cpu; | |
1505 | ||
b6a1cbae | 1506 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
1507 | { |
1508 | ptr = &rs6000_select[i]; | |
1509 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
1510 | { | |
1511 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
1512 | start = ""; | |
1513 | } | |
1514 | } | |
1515 | ||
b91da81f | 1516 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
1517 | switch (rs6000_sdata) |
1518 | { | |
1519 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
1520 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
1521 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
1522 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
1523 | } | |
1524 | ||
1525 | if (rs6000_sdata && g_switch_value) | |
1526 | { | |
307b599c MK |
1527 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
1528 | g_switch_value); | |
3cfa4909 MM |
1529 | start = ""; |
1530 | } | |
1531 | #endif | |
1532 | ||
1533 | if (*start == '\0') | |
949ea356 | 1534 | putc ('\n', file); |
3cfa4909 MM |
1535 | } |
1536 | } | |
5248c961 | 1537 | \f |
a0ab749a | 1538 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1539 | |
1540 | int | |
863d938c | 1541 | direct_return (void) |
9878760c | 1542 | { |
4697a36c MM |
1543 | if (reload_completed) |
1544 | { | |
1545 | rs6000_stack_t *info = rs6000_stack_info (); | |
1546 | ||
1547 | if (info->first_gp_reg_save == 32 | |
1548 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1549 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1550 | && ! info->lr_save_p |
1551 | && ! info->cr_save_p | |
00b960c7 | 1552 | && info->vrsave_mask == 0 |
c81fc13e | 1553 | && ! info->push_p) |
4697a36c MM |
1554 | return 1; |
1555 | } | |
1556 | ||
1557 | return 0; | |
9878760c RK |
1558 | } |
1559 | ||
1560 | /* Returns 1 always. */ | |
1561 | ||
1562 | int | |
a2369ed3 DJ |
1563 | any_operand (rtx op ATTRIBUTE_UNUSED, |
1564 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
9878760c RK |
1565 | { |
1566 | return 1; | |
1567 | } | |
1568 | ||
a4f6c312 | 1569 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 1570 | int |
a2369ed3 | 1571 | count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
b6c9286a MM |
1572 | { |
1573 | if (GET_CODE (op) != REG) | |
1574 | return 0; | |
1575 | ||
1576 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
1577 | return 1; | |
1578 | ||
1579 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
1580 | return 1; | |
1581 | ||
1582 | return 0; | |
1583 | } | |
1584 | ||
0ec4e2a8 AH |
1585 | /* Returns 1 if op is an altivec register. */ |
1586 | int | |
a2369ed3 | 1587 | altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ec4e2a8 AH |
1588 | { |
1589 | ||
1590 | return (register_operand (op, mode) | |
1591 | && (GET_CODE (op) != REG | |
1592 | || REGNO (op) > FIRST_PSEUDO_REGISTER | |
1593 | || ALTIVEC_REGNO_P (REGNO (op)))); | |
1594 | } | |
1595 | ||
38c1f2d7 | 1596 | int |
a2369ed3 | 1597 | xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
802a0058 MM |
1598 | { |
1599 | if (GET_CODE (op) != REG) | |
1600 | return 0; | |
1601 | ||
9ebbca7d | 1602 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
1603 | return 1; |
1604 | ||
802a0058 MM |
1605 | return 0; |
1606 | } | |
1607 | ||
c859cda6 | 1608 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 1609 | by such constants completes more quickly. */ |
c859cda6 DJ |
1610 | |
1611 | int | |
a2369ed3 | 1612 | s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c859cda6 DJ |
1613 | { |
1614 | return ( GET_CODE (op) == CONST_INT | |
1615 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); | |
1616 | } | |
1617 | ||
9878760c RK |
1618 | /* Return 1 if OP is a constant that can fit in a D field. */ |
1619 | ||
1620 | int | |
a2369ed3 | 1621 | short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1622 | { |
5f59ecb7 DE |
1623 | return (GET_CODE (op) == CONST_INT |
1624 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
1625 | } |
1626 | ||
5519a4f9 | 1627 | /* Similar for an unsigned D field. */ |
9878760c RK |
1628 | |
1629 | int | |
a2369ed3 | 1630 | u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1631 | { |
19684119 | 1632 | return (GET_CODE (op) == CONST_INT |
c1f11548 | 1633 | && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K')); |
9878760c RK |
1634 | } |
1635 | ||
dcfedcd0 RK |
1636 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
1637 | ||
1638 | int | |
a2369ed3 | 1639 | non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
1640 | { |
1641 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1642 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
1643 | } |
1644 | ||
2bfcf297 DB |
1645 | /* Returns 1 if OP is a CONST_INT that is a positive value |
1646 | and an exact power of 2. */ | |
1647 | ||
1648 | int | |
a2369ed3 | 1649 | exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bfcf297 DB |
1650 | { |
1651 | return (GET_CODE (op) == CONST_INT | |
1652 | && INTVAL (op) > 0 | |
1653 | && exact_log2 (INTVAL (op)) >= 0); | |
1654 | } | |
1655 | ||
9878760c RK |
1656 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
1657 | ctr, or lr). */ | |
1658 | ||
1659 | int | |
a2369ed3 | 1660 | gpc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1661 | { |
1662 | return (register_operand (op, mode) | |
802a0058 | 1663 | && (GET_CODE (op) != REG |
9ebbca7d GK |
1664 | || (REGNO (op) >= ARG_POINTER_REGNUM |
1665 | && !XER_REGNO_P (REGNO (op))) | |
1666 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
1667 | } |
1668 | ||
1669 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
1670 | CR field. */ | |
1671 | ||
1672 | int | |
a2369ed3 | 1673 | cc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1674 | { |
1675 | return (register_operand (op, mode) | |
1676 | && (GET_CODE (op) != REG | |
1677 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1678 | || CR_REGNO_P (REGNO (op)))); | |
1679 | } | |
1680 | ||
815cdc52 MM |
1681 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
1682 | CR field that isn't CR0. */ | |
1683 | ||
1684 | int | |
a2369ed3 | 1685 | cc_reg_not_cr0_operand (rtx op, enum machine_mode mode) |
815cdc52 MM |
1686 | { |
1687 | return (register_operand (op, mode) | |
1688 | && (GET_CODE (op) != REG | |
1689 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1690 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
1691 | } | |
1692 | ||
a4f6c312 SS |
1693 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
1694 | a non-special register. If a register, it must be in the proper | |
1695 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
1696 | |
1697 | int | |
a2369ed3 | 1698 | reg_or_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1699 | { |
f5a28898 | 1700 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1701 | } |
1702 | ||
a4f6c312 | 1703 | /* Similar, except check if the negation of the constant would be |
42f806e5 AM |
1704 | valid for a D-field. Don't allow a constant zero, since all the |
1705 | patterns that call this predicate use "addic r1,r2,-constant" on | |
1706 | a constant value to set a carry when r2 is greater or equal to | |
1707 | "constant". That doesn't work for zero. */ | |
9878760c RK |
1708 | |
1709 | int | |
a2369ed3 | 1710 | reg_or_neg_short_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1711 | { |
1712 | if (GET_CODE (op) == CONST_INT) | |
42f806e5 | 1713 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0; |
9878760c | 1714 | |
cd2b37d9 | 1715 | return gpc_reg_operand (op, mode); |
9878760c RK |
1716 | } |
1717 | ||
768070a0 TR |
1718 | /* Returns 1 if OP is either a constant integer valid for a DS-field or |
1719 | a non-special register. If a register, it must be in the proper | |
1720 | mode unless MODE is VOIDmode. */ | |
1721 | ||
1722 | int | |
a2369ed3 | 1723 | reg_or_aligned_short_operand (rtx op, enum machine_mode mode) |
768070a0 TR |
1724 | { |
1725 | if (gpc_reg_operand (op, mode)) | |
1726 | return 1; | |
1727 | else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3)) | |
1728 | return 1; | |
1729 | ||
1730 | return 0; | |
1731 | } | |
1732 | ||
1733 | ||
a4f6c312 SS |
1734 | /* Return 1 if the operand is either a register or an integer whose |
1735 | high-order 16 bits are zero. */ | |
9878760c RK |
1736 | |
1737 | int | |
a2369ed3 | 1738 | reg_or_u_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1739 | { |
e675f625 | 1740 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1741 | } |
1742 | ||
1743 | /* Return 1 is the operand is either a non-special register or ANY | |
1744 | constant integer. */ | |
1745 | ||
1746 | int | |
a2369ed3 | 1747 | reg_or_cint_operand (rtx op, enum machine_mode mode) |
9878760c | 1748 | { |
a4f6c312 | 1749 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
1750 | } |
1751 | ||
1752 | /* Return 1 is the operand is either a non-special register or ANY | |
1753 | 32-bit signed constant integer. */ | |
1754 | ||
1755 | int | |
a2369ed3 | 1756 | reg_or_arith_cint_operand (rtx op, enum machine_mode mode) |
f6bf7de2 | 1757 | { |
a4f6c312 SS |
1758 | return (gpc_reg_operand (op, mode) |
1759 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 1760 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
1761 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
1762 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 1763 | #endif |
a4f6c312 | 1764 | )); |
9878760c RK |
1765 | } |
1766 | ||
2bfcf297 DB |
1767 | /* Return 1 is the operand is either a non-special register or a 32-bit |
1768 | signed constant integer valid for 64-bit addition. */ | |
1769 | ||
1770 | int | |
a2369ed3 | 1771 | reg_or_add_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 1772 | { |
a4f6c312 SS |
1773 | return (gpc_reg_operand (op, mode) |
1774 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1775 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1776 | && INTVAL (op) < 0x7fff8000 |
a65c591c | 1777 | #else |
a4f6c312 SS |
1778 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
1779 | < 0x100000000ll) | |
2bfcf297 | 1780 | #endif |
a4f6c312 | 1781 | )); |
2bfcf297 DB |
1782 | } |
1783 | ||
1784 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
1785 | signed constant integer valid for 64-bit subtraction. */ | |
1786 | ||
1787 | int | |
a2369ed3 | 1788 | reg_or_sub_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 1789 | { |
a4f6c312 SS |
1790 | return (gpc_reg_operand (op, mode) |
1791 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1792 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1793 | && (- INTVAL (op)) < 0x7fff8000 |
a65c591c | 1794 | #else |
a4f6c312 SS |
1795 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
1796 | < 0x100000000ll) | |
2bfcf297 | 1797 | #endif |
a4f6c312 | 1798 | )); |
2bfcf297 DB |
1799 | } |
1800 | ||
9ebbca7d GK |
1801 | /* Return 1 is the operand is either a non-special register or ANY |
1802 | 32-bit unsigned constant integer. */ | |
1803 | ||
1804 | int | |
a2369ed3 | 1805 | reg_or_logical_cint_operand (rtx op, enum machine_mode mode) |
9ebbca7d | 1806 | { |
1d328b19 GK |
1807 | if (GET_CODE (op) == CONST_INT) |
1808 | { | |
1809 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
1810 | { | |
1811 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 1812 | abort (); |
1d328b19 GK |
1813 | |
1814 | if (INTVAL (op) < 0) | |
1815 | return 0; | |
1816 | } | |
1817 | ||
1818 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 1819 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
1820 | } |
1821 | else if (GET_CODE (op) == CONST_DOUBLE) | |
1822 | { | |
1823 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
1824 | || mode != DImode) | |
a4f6c312 | 1825 | abort (); |
1d328b19 GK |
1826 | |
1827 | return CONST_DOUBLE_HIGH (op) == 0; | |
1828 | } | |
1829 | else | |
1830 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
1831 | } |
1832 | ||
51d3e7d6 | 1833 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
1834 | |
1835 | int | |
a2369ed3 | 1836 | got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
766a866c MM |
1837 | { |
1838 | return (GET_CODE (op) == SYMBOL_REF | |
1839 | || GET_CODE (op) == CONST | |
1840 | || GET_CODE (op) == LABEL_REF); | |
1841 | } | |
1842 | ||
38c1f2d7 MM |
1843 | /* Return 1 if the operand is a simple references that can be loaded via |
1844 | the GOT (labels involving addition aren't allowed). */ | |
1845 | ||
1846 | int | |
a2369ed3 | 1847 | got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
38c1f2d7 MM |
1848 | { |
1849 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
1850 | } | |
1851 | ||
4e74d8ec MM |
1852 | /* Return the number of instructions it takes to form a constant in an |
1853 | integer register. */ | |
1854 | ||
1855 | static int | |
a2369ed3 | 1856 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
1857 | { |
1858 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1859 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1860 | return 1; |
1861 | ||
4e74d8ec | 1862 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1863 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1864 | return 1; |
1865 | ||
5f59ecb7 | 1866 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1867 | else if (TARGET_POWERPC64) |
4e74d8ec | 1868 | { |
a65c591c DE |
1869 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1870 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 1871 | |
a65c591c | 1872 | if (high == 0 || high == -1) |
4e74d8ec MM |
1873 | return 2; |
1874 | ||
a65c591c | 1875 | high >>= 1; |
4e74d8ec | 1876 | |
a65c591c | 1877 | if (low == 0) |
4e74d8ec | 1878 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
1879 | else |
1880 | return (num_insns_constant_wide (high) | |
e396202a | 1881 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1882 | } |
1883 | #endif | |
1884 | ||
1885 | else | |
1886 | return 2; | |
1887 | } | |
1888 | ||
1889 | int | |
a2369ed3 | 1890 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 1891 | { |
4e74d8ec | 1892 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
1893 | { |
1894 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
1895 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1896 | && mask64_operand (op, mode)) | |
0d30d435 DE |
1897 | return 2; |
1898 | else | |
1899 | #endif | |
1900 | return num_insns_constant_wide (INTVAL (op)); | |
1901 | } | |
4e74d8ec | 1902 | |
6fc48950 MM |
1903 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
1904 | { | |
1905 | long l; | |
1906 | REAL_VALUE_TYPE rv; | |
1907 | ||
1908 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1909 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
e72247f4 | 1910 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
6fc48950 MM |
1911 | } |
1912 | ||
47ad8c61 | 1913 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 1914 | { |
47ad8c61 MM |
1915 | HOST_WIDE_INT low; |
1916 | HOST_WIDE_INT high; | |
1917 | long l[2]; | |
1918 | REAL_VALUE_TYPE rv; | |
1919 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 1920 | |
47ad8c61 MM |
1921 | if (mode == VOIDmode || mode == DImode) |
1922 | { | |
1923 | high = CONST_DOUBLE_HIGH (op); | |
1924 | low = CONST_DOUBLE_LOW (op); | |
1925 | } | |
1926 | else | |
1927 | { | |
1928 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1929 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1930 | high = l[endian]; | |
1931 | low = l[1 - endian]; | |
1932 | } | |
4e74d8ec | 1933 | |
47ad8c61 MM |
1934 | if (TARGET_32BIT) |
1935 | return (num_insns_constant_wide (low) | |
1936 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
1937 | |
1938 | else | |
47ad8c61 | 1939 | { |
e72247f4 | 1940 | if (high == 0 && low >= 0) |
47ad8c61 MM |
1941 | return num_insns_constant_wide (low); |
1942 | ||
e72247f4 | 1943 | else if (high == -1 && low < 0) |
47ad8c61 MM |
1944 | return num_insns_constant_wide (low); |
1945 | ||
a260abc9 DE |
1946 | else if (mask64_operand (op, mode)) |
1947 | return 2; | |
1948 | ||
47ad8c61 MM |
1949 | else if (low == 0) |
1950 | return num_insns_constant_wide (high) + 1; | |
1951 | ||
1952 | else | |
1953 | return (num_insns_constant_wide (high) | |
1954 | + num_insns_constant_wide (low) + 1); | |
1955 | } | |
4e74d8ec MM |
1956 | } |
1957 | ||
1958 | else | |
1959 | abort (); | |
1960 | } | |
1961 | ||
a4f6c312 SS |
1962 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
1963 | register with one instruction per word. We only do this if we can | |
1964 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
1965 | |
1966 | int | |
a2369ed3 | 1967 | easy_fp_constant (rtx op, enum machine_mode mode) |
9878760c | 1968 | { |
9878760c RK |
1969 | if (GET_CODE (op) != CONST_DOUBLE |
1970 | || GET_MODE (op) != mode | |
4e74d8ec | 1971 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
1972 | return 0; |
1973 | ||
a4f6c312 | 1974 | /* Consider all constants with -msoft-float to be easy. */ |
a3170dc6 AH |
1975 | if ((TARGET_SOFT_FLOAT || !TARGET_FPRS) |
1976 | && mode != DImode) | |
b6c9286a MM |
1977 | return 1; |
1978 | ||
a4f6c312 | 1979 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 1980 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
1981 | return 0; |
1982 | ||
5ae4759c | 1983 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
1984 | /* Similarly if we are using -mrelocatable, consider all constants |
1985 | to be hard. */ | |
5ae4759c MM |
1986 | if (TARGET_RELOCATABLE) |
1987 | return 0; | |
1988 | #endif | |
1989 | ||
fcce224d DE |
1990 | if (mode == TFmode) |
1991 | { | |
1992 | long k[4]; | |
1993 | REAL_VALUE_TYPE rv; | |
1994 | ||
1995 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1996 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
1997 | ||
1998 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
1999 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
2000 | && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
2001 | && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
2002 | } | |
2003 | ||
2004 | else if (mode == DFmode) | |
042259f2 DE |
2005 | { |
2006 | long k[2]; | |
2007 | REAL_VALUE_TYPE rv; | |
2008 | ||
2009 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2010 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 2011 | |
a65c591c DE |
2012 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 |
2013 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
042259f2 | 2014 | } |
4e74d8ec MM |
2015 | |
2016 | else if (mode == SFmode) | |
042259f2 DE |
2017 | { |
2018 | long l; | |
2019 | REAL_VALUE_TYPE rv; | |
2020 | ||
2021 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2022 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 2023 | |
4e74d8ec | 2024 | return num_insns_constant_wide (l) == 1; |
042259f2 | 2025 | } |
4e74d8ec | 2026 | |
a260abc9 | 2027 | else if (mode == DImode) |
c81fc13e | 2028 | return ((TARGET_POWERPC64 |
a260abc9 DE |
2029 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
2030 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 2031 | |
a9098fd0 GK |
2032 | else if (mode == SImode) |
2033 | return 1; | |
4e74d8ec MM |
2034 | else |
2035 | abort (); | |
9878760c | 2036 | } |
8f75773e | 2037 | |
effa5d5d | 2038 | /* Returns the constant for the splat instruction, if exists. */ |
452a7d36 HP |
2039 | |
2040 | static int | |
2041 | easy_vector_splat_const (int cst, enum machine_mode mode) | |
2042 | { | |
2043 | switch (mode) | |
2044 | { | |
2045 | case V4SImode: | |
2046 | if (EASY_VECTOR_15 (cst) | |
2047 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
2048 | return cst; | |
2049 | if ((cst & 0xffff) != ((cst >> 16) & 0xffff)) | |
2050 | break; | |
2051 | cst = cst >> 16; | |
2052 | case V8HImode: | |
2053 | if (EASY_VECTOR_15 (cst) | |
2054 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
2055 | return cst; | |
2056 | if ((cst & 0xff) != ((cst >> 8) & 0xff)) | |
2057 | break; | |
2058 | cst = cst >> 8; | |
2059 | case V16QImode: | |
2060 | if (EASY_VECTOR_15 (cst) | |
2061 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
2062 | return cst; | |
2063 | default: | |
2064 | break; | |
2065 | } | |
2066 | return 0; | |
2067 | } | |
2068 | ||
2069 | ||
72ac76be | 2070 | /* Return nonzero if all elements of a vector have the same value. */ |
69ef87e2 AH |
2071 | |
2072 | static int | |
a2369ed3 | 2073 | easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d744e06e AH |
2074 | { |
2075 | int units, i, cst; | |
2076 | ||
2077 | units = CONST_VECTOR_NUNITS (op); | |
2078 | ||
2079 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
2080 | for (i = 1; i < units; ++i) | |
2081 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
2082 | break; | |
452a7d36 | 2083 | if (i == units && easy_vector_splat_const (cst, mode)) |
d744e06e AH |
2084 | return 1; |
2085 | return 0; | |
2086 | } | |
2087 | ||
2088 | /* Return 1 if the operand is a CONST_INT and can be put into a | |
2089 | register without using memory. */ | |
2090 | ||
2091 | int | |
a2369ed3 | 2092 | easy_vector_constant (rtx op, enum machine_mode mode) |
69ef87e2 | 2093 | { |
d744e06e | 2094 | int cst, cst2; |
69ef87e2 | 2095 | |
d744e06e AH |
2096 | if (GET_CODE (op) != CONST_VECTOR |
2097 | || (!TARGET_ALTIVEC | |
2098 | && !TARGET_SPE)) | |
69ef87e2 AH |
2099 | return 0; |
2100 | ||
d744e06e AH |
2101 | if (zero_constant (op, mode) |
2102 | && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
2103 | || (TARGET_SPE && SPE_VECTOR_MODE (mode)))) | |
2104 | return 1; | |
69ef87e2 | 2105 | |
d744e06e AH |
2106 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) |
2107 | return 0; | |
2108 | ||
f5119d10 AH |
2109 | if (TARGET_SPE && mode == V1DImode) |
2110 | return 0; | |
2111 | ||
d744e06e AH |
2112 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); |
2113 | cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
2114 | ||
2115 | /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
2116 | li r0, CONSTANT1 | |
2117 | evmergelo r0, r0, r0 | |
2118 | li r0, CONSTANT2 | |
2119 | ||
2120 | I don't know how efficient it would be to allow bigger constants, | |
2121 | considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
2122 | instructions is better than a 64-bit memory load, but I don't | |
2123 | have the e500 timing specs. */ | |
2124 | if (TARGET_SPE && mode == V2SImode | |
2125 | && cst >= -0x7fff && cst <= 0x7fff | |
f5119d10 | 2126 | && cst2 >= -0x7fff && cst2 <= 0x7fff) |
d744e06e AH |
2127 | return 1; |
2128 | ||
452a7d36 HP |
2129 | if (TARGET_ALTIVEC |
2130 | && easy_vector_same (op, mode)) | |
2131 | { | |
2132 | cst = easy_vector_splat_const (cst, mode); | |
2133 | if (EASY_VECTOR_15_ADD_SELF (cst) | |
2134 | || EASY_VECTOR_15 (cst)) | |
2135 | return 1; | |
2136 | } | |
d744e06e AH |
2137 | return 0; |
2138 | } | |
2139 | ||
2140 | /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */ | |
2141 | ||
2142 | int | |
a2369ed3 | 2143 | easy_vector_constant_add_self (rtx op, enum machine_mode mode) |
d744e06e AH |
2144 | { |
2145 | int cst; | |
452a7d36 HP |
2146 | if (TARGET_ALTIVEC |
2147 | && GET_CODE (op) == CONST_VECTOR | |
2148 | && easy_vector_same (op, mode)) | |
2149 | { | |
2150 | cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode); | |
2151 | if (EASY_VECTOR_15_ADD_SELF (cst)) | |
2152 | return 1; | |
2153 | } | |
2154 | return 0; | |
2155 | } | |
d744e06e | 2156 | |
452a7d36 | 2157 | /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */ |
d744e06e | 2158 | |
452a7d36 HP |
2159 | rtx |
2160 | gen_easy_vector_constant_add_self (rtx op) | |
2161 | { | |
2162 | int i, units; | |
2163 | rtvec v; | |
2164 | units = GET_MODE_NUNITS (GET_MODE (op)); | |
2165 | v = rtvec_alloc (units); | |
2166 | ||
2167 | for (i = 0; i < units; i++) | |
2168 | RTVEC_ELT (v, i) = | |
2169 | GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1); | |
2170 | return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v); | |
d744e06e AH |
2171 | } |
2172 | ||
2173 | const char * | |
a2369ed3 | 2174 | output_vec_const_move (rtx *operands) |
d744e06e AH |
2175 | { |
2176 | int cst, cst2; | |
2177 | enum machine_mode mode; | |
2178 | rtx dest, vec; | |
2179 | ||
2180 | dest = operands[0]; | |
2181 | vec = operands[1]; | |
69ef87e2 | 2182 | |
d744e06e AH |
2183 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
2184 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
2185 | mode = GET_MODE (dest); | |
69ef87e2 | 2186 | |
d744e06e AH |
2187 | if (TARGET_ALTIVEC) |
2188 | { | |
2189 | if (zero_constant (vec, mode)) | |
2190 | return "vxor %0,%0,%0"; | |
ce1f50b2 | 2191 | else if (easy_vector_constant (vec, mode)) |
98ef3137 | 2192 | { |
d744e06e AH |
2193 | operands[1] = GEN_INT (cst); |
2194 | switch (mode) | |
2195 | { | |
2196 | case V4SImode: | |
452a7d36 | 2197 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2198 | { |
2199 | operands[1] = GEN_INT (cst); | |
2200 | return "vspltisw %0,%1"; | |
2201 | } | |
452a7d36 HP |
2202 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2203 | return "#"; | |
ce1f50b2 | 2204 | cst = cst >> 16; |
d744e06e | 2205 | case V8HImode: |
452a7d36 | 2206 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2207 | { |
2208 | operands[1] = GEN_INT (cst); | |
2209 | return "vspltish %0,%1"; | |
2210 | } | |
452a7d36 HP |
2211 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2212 | return "#"; | |
ce1f50b2 | 2213 | cst = cst >> 8; |
d744e06e | 2214 | case V16QImode: |
452a7d36 | 2215 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2216 | { |
2217 | operands[1] = GEN_INT (cst); | |
2218 | return "vspltisb %0,%1"; | |
2219 | } | |
452a7d36 HP |
2220 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2221 | return "#"; | |
d744e06e AH |
2222 | default: |
2223 | abort (); | |
2224 | } | |
98ef3137 | 2225 | } |
d744e06e AH |
2226 | else |
2227 | abort (); | |
69ef87e2 AH |
2228 | } |
2229 | ||
d744e06e AH |
2230 | if (TARGET_SPE) |
2231 | { | |
2232 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
2233 | pattern of V1DI, V4HI, and V2SF. | |
2234 | ||
c1207243 | 2235 | FIXME: We should probably return # and add post reload |
d744e06e AH |
2236 | splitters for these, but this way is so easy ;-). |
2237 | */ | |
2238 | operands[1] = GEN_INT (cst); | |
2239 | operands[2] = GEN_INT (cst2); | |
2240 | if (cst == cst2) | |
2241 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
2242 | else | |
2243 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
2244 | } | |
2245 | ||
2246 | abort (); | |
69ef87e2 AH |
2247 | } |
2248 | ||
2249 | /* Return 1 if the operand is the constant 0. This works for scalars | |
2250 | as well as vectors. */ | |
2251 | int | |
a2369ed3 | 2252 | zero_constant (rtx op, enum machine_mode mode) |
69ef87e2 AH |
2253 | { |
2254 | return op == CONST0_RTX (mode); | |
2255 | } | |
2256 | ||
50a0b056 GK |
2257 | /* Return 1 if the operand is 0.0. */ |
2258 | int | |
a2369ed3 | 2259 | zero_fp_constant (rtx op, enum machine_mode mode) |
50a0b056 GK |
2260 | { |
2261 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
2262 | } | |
2263 | ||
a4f6c312 SS |
2264 | /* Return 1 if the operand is in volatile memory. Note that during |
2265 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
2266 | volatile memory references. So this function allows us to |
2267 | recognize volatile references where its safe. */ | |
2268 | ||
2269 | int | |
a2369ed3 | 2270 | volatile_mem_operand (rtx op, enum machine_mode mode) |
b6c9286a MM |
2271 | { |
2272 | if (GET_CODE (op) != MEM) | |
2273 | return 0; | |
2274 | ||
2275 | if (!MEM_VOLATILE_P (op)) | |
2276 | return 0; | |
2277 | ||
2278 | if (mode != GET_MODE (op)) | |
2279 | return 0; | |
2280 | ||
2281 | if (reload_completed) | |
2282 | return memory_operand (op, mode); | |
2283 | ||
2284 | if (reload_in_progress) | |
2285 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
2286 | ||
2287 | return memory_address_p (mode, XEXP (op, 0)); | |
2288 | } | |
2289 | ||
97f6e72f | 2290 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
2291 | |
2292 | int | |
a2369ed3 | 2293 | offsettable_mem_operand (rtx op, enum machine_mode mode) |
914c2e77 | 2294 | { |
97f6e72f | 2295 | return ((GET_CODE (op) == MEM) |
677a9668 | 2296 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 2297 | mode, XEXP (op, 0))); |
914c2e77 RK |
2298 | } |
2299 | ||
9878760c RK |
2300 | /* Return 1 if the operand is either an easy FP constant (see above) or |
2301 | memory. */ | |
2302 | ||
2303 | int | |
a2369ed3 | 2304 | mem_or_easy_const_operand (rtx op, enum machine_mode mode) |
9878760c RK |
2305 | { |
2306 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
2307 | } | |
2308 | ||
2309 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 2310 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
2311 | |
2312 | int | |
a2369ed3 | 2313 | add_operand (rtx op, enum machine_mode mode) |
9878760c | 2314 | { |
2bfcf297 | 2315 | if (GET_CODE (op) == CONST_INT) |
e72247f4 DE |
2316 | return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
2317 | || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
2bfcf297 DB |
2318 | |
2319 | return gpc_reg_operand (op, mode); | |
9878760c RK |
2320 | } |
2321 | ||
dcfedcd0 RK |
2322 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
2323 | ||
2324 | int | |
a2369ed3 | 2325 | non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
2326 | { |
2327 | return (GET_CODE (op) == CONST_INT | |
e72247f4 DE |
2328 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
2329 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
dcfedcd0 RK |
2330 | } |
2331 | ||
9878760c RK |
2332 | /* Return 1 if the operand is a non-special register or a constant that |
2333 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
2334 | ||
2335 | int | |
a2369ed3 | 2336 | logical_operand (rtx op, enum machine_mode mode) |
9878760c | 2337 | { |
40501e5f | 2338 | HOST_WIDE_INT opl, oph; |
1d328b19 | 2339 | |
dfbdccdb GK |
2340 | if (gpc_reg_operand (op, mode)) |
2341 | return 1; | |
1d328b19 | 2342 | |
dfbdccdb | 2343 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
2344 | { |
2345 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
2346 | ||
2347 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
2348 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
2349 | return 0; | |
2350 | #endif | |
2351 | } | |
dfbdccdb GK |
2352 | else if (GET_CODE (op) == CONST_DOUBLE) |
2353 | { | |
1d328b19 | 2354 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 2355 | abort (); |
1d328b19 GK |
2356 | |
2357 | opl = CONST_DOUBLE_LOW (op); | |
2358 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 2359 | if (oph != 0) |
38886f37 | 2360 | return 0; |
dfbdccdb GK |
2361 | } |
2362 | else | |
2363 | return 0; | |
1d328b19 | 2364 | |
40501e5f AM |
2365 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
2366 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
2367 | } |
2368 | ||
dcfedcd0 | 2369 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 2370 | above), but could be split into one. */ |
dcfedcd0 RK |
2371 | |
2372 | int | |
a2369ed3 | 2373 | non_logical_cint_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 2374 | { |
dfbdccdb | 2375 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
2376 | && ! logical_operand (op, mode) |
2377 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
2378 | } |
2379 | ||
19ba8161 | 2380 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
2381 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
2382 | Reject all ones and all zeros, since these should have been optimized | |
2383 | away and confuse the making of MB and ME. */ | |
2384 | ||
2385 | int | |
a2369ed3 | 2386 | mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 2387 | { |
02071907 | 2388 | HOST_WIDE_INT c, lsb; |
9878760c | 2389 | |
19ba8161 DE |
2390 | if (GET_CODE (op) != CONST_INT) |
2391 | return 0; | |
2392 | ||
2393 | c = INTVAL (op); | |
2394 | ||
57deb3a1 AM |
2395 | /* Fail in 64-bit mode if the mask wraps around because the upper |
2396 | 32-bits of the mask will all be 1s, contrary to GCC's internal view. */ | |
2397 | if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001) | |
2398 | return 0; | |
2399 | ||
c5059423 AM |
2400 | /* We don't change the number of transitions by inverting, |
2401 | so make sure we start with the LS bit zero. */ | |
2402 | if (c & 1) | |
2403 | c = ~c; | |
2404 | ||
2405 | /* Reject all zeros or all ones. */ | |
2406 | if (c == 0) | |
9878760c RK |
2407 | return 0; |
2408 | ||
c5059423 AM |
2409 | /* Find the first transition. */ |
2410 | lsb = c & -c; | |
2411 | ||
2412 | /* Invert to look for a second transition. */ | |
2413 | c = ~c; | |
9878760c | 2414 | |
c5059423 AM |
2415 | /* Erase first transition. */ |
2416 | c &= -lsb; | |
9878760c | 2417 | |
c5059423 AM |
2418 | /* Find the second transition (if any). */ |
2419 | lsb = c & -c; | |
2420 | ||
2421 | /* Match if all the bits above are 1's (or c is zero). */ | |
2422 | return c == -lsb; | |
9878760c RK |
2423 | } |
2424 | ||
0ba1b2ff AM |
2425 | /* Return 1 for the PowerPC64 rlwinm corner case. */ |
2426 | ||
2427 | int | |
a2369ed3 | 2428 | mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ba1b2ff AM |
2429 | { |
2430 | HOST_WIDE_INT c, lsb; | |
2431 | ||
2432 | if (GET_CODE (op) != CONST_INT) | |
2433 | return 0; | |
2434 | ||
2435 | c = INTVAL (op); | |
2436 | ||
2437 | if ((c & 0x80000001) != 0x80000001) | |
2438 | return 0; | |
2439 | ||
2440 | c = ~c; | |
2441 | if (c == 0) | |
2442 | return 0; | |
2443 | ||
2444 | lsb = c & -c; | |
2445 | c = ~c; | |
2446 | c &= -lsb; | |
2447 | lsb = c & -c; | |
2448 | return c == -lsb; | |
2449 | } | |
2450 | ||
a260abc9 DE |
2451 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
2452 | It is if there are no more than one 1->0 or 0->1 transitions. | |
0ba1b2ff AM |
2453 | Reject all zeros, since zero should have been optimized away and |
2454 | confuses the making of MB and ME. */ | |
9878760c RK |
2455 | |
2456 | int | |
a2369ed3 | 2457 | mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
a260abc9 DE |
2458 | { |
2459 | if (GET_CODE (op) == CONST_INT) | |
2460 | { | |
02071907 | 2461 | HOST_WIDE_INT c, lsb; |
a260abc9 | 2462 | |
c5059423 | 2463 | c = INTVAL (op); |
a260abc9 | 2464 | |
0ba1b2ff | 2465 | /* Reject all zeros. */ |
c5059423 | 2466 | if (c == 0) |
e2c953b6 DE |
2467 | return 0; |
2468 | ||
0ba1b2ff AM |
2469 | /* We don't change the number of transitions by inverting, |
2470 | so make sure we start with the LS bit zero. */ | |
2471 | if (c & 1) | |
2472 | c = ~c; | |
2473 | ||
c5059423 AM |
2474 | /* Find the transition, and check that all bits above are 1's. */ |
2475 | lsb = c & -c; | |
e3981aab DE |
2476 | |
2477 | /* Match if all the bits above are 1's (or c is zero). */ | |
c5059423 | 2478 | return c == -lsb; |
e2c953b6 | 2479 | } |
0ba1b2ff AM |
2480 | return 0; |
2481 | } | |
2482 | ||
2483 | /* Like mask64_operand, but allow up to three transitions. This | |
2484 | predicate is used by insn patterns that generate two rldicl or | |
2485 | rldicr machine insns. */ | |
2486 | ||
2487 | int | |
a2369ed3 | 2488 | mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ba1b2ff AM |
2489 | { |
2490 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 2491 | { |
0ba1b2ff | 2492 | HOST_WIDE_INT c, lsb; |
a260abc9 | 2493 | |
0ba1b2ff | 2494 | c = INTVAL (op); |
a260abc9 | 2495 | |
0ba1b2ff AM |
2496 | /* Disallow all zeros. */ |
2497 | if (c == 0) | |
2498 | return 0; | |
a260abc9 | 2499 | |
0ba1b2ff AM |
2500 | /* We don't change the number of transitions by inverting, |
2501 | so make sure we start with the LS bit zero. */ | |
2502 | if (c & 1) | |
2503 | c = ~c; | |
a260abc9 | 2504 | |
0ba1b2ff AM |
2505 | /* Find the first transition. */ |
2506 | lsb = c & -c; | |
a260abc9 | 2507 | |
0ba1b2ff AM |
2508 | /* Invert to look for a second transition. */ |
2509 | c = ~c; | |
2510 | ||
2511 | /* Erase first transition. */ | |
2512 | c &= -lsb; | |
2513 | ||
2514 | /* Find the second transition. */ | |
2515 | lsb = c & -c; | |
2516 | ||
2517 | /* Invert to look for a third transition. */ | |
2518 | c = ~c; | |
2519 | ||
2520 | /* Erase second transition. */ | |
2521 | c &= -lsb; | |
2522 | ||
2523 | /* Find the third transition (if any). */ | |
2524 | lsb = c & -c; | |
2525 | ||
2526 | /* Match if all the bits above are 1's (or c is zero). */ | |
2527 | return c == -lsb; | |
2528 | } | |
2529 | return 0; | |
2530 | } | |
2531 | ||
2532 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to | |
2533 | implement ANDing by the mask IN. */ | |
2534 | void | |
a2369ed3 | 2535 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
2536 | { |
2537 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2538 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2539 | int shift; | |
2540 | ||
2541 | if (GET_CODE (in) != CONST_INT) | |
2542 | abort (); | |
2543 | ||
2544 | c = INTVAL (in); | |
2545 | if (c & 1) | |
2546 | { | |
2547 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2548 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2549 | is at the MS end and can be cleared with an rldicl mask. We then | |
2550 | rotate back and clear off the MS ^^ group of zeros with a | |
2551 | second rldicl. */ | |
2552 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2553 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2554 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2555 | c = ~c; /* c == 0x00fff000000fffff */ | |
2556 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2557 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2558 | c = ~c; /* c == 0xff000fffffffffff */ | |
2559 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2560 | shift = 0; | |
2561 | while ((lsb >>= 1) != 0) | |
2562 | shift++; /* shift == 44 on exit from loop */ | |
2563 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2564 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2565 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2566 | } |
2567 | else | |
0ba1b2ff AM |
2568 | { |
2569 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2570 | is to rotate the word so that the ^^^ middle group of zeros | |
2571 | is at the LS end and can be cleared with an rldicr mask. We then | |
2572 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2573 | a second rldicr. */ | |
2574 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2575 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2576 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2577 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2578 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2579 | c = ~c; /* c == 0xff000fffffffffff */ | |
2580 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2581 | shift = 0; | |
2582 | while ((lsb >>= 1) != 0) | |
2583 | shift++; /* shift == 44 on exit from loop */ | |
2584 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2585 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2586 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2587 | } | |
2588 | ||
2589 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2590 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2591 | out[0] = GEN_INT (64 - shift); | |
2592 | out[1] = GEN_INT (m1); | |
2593 | out[2] = GEN_INT (shift); | |
2594 | out[3] = GEN_INT (m2); | |
2595 | #else | |
045572c7 GK |
2596 | (void)in; |
2597 | (void)out; | |
0ba1b2ff AM |
2598 | abort (); |
2599 | #endif | |
a260abc9 DE |
2600 | } |
2601 | ||
2602 | /* Return 1 if the operand is either a non-special register or a constant | |
2603 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
2604 | ||
2605 | int | |
a2369ed3 | 2606 | and64_operand (rtx op, enum machine_mode mode) |
9878760c | 2607 | { |
a4f6c312 | 2608 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2609 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
2610 | ||
2611 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
2612 | } |
2613 | ||
0ba1b2ff AM |
2614 | /* Like the above, but also match constants that can be implemented |
2615 | with two rldicl or rldicr insns. */ | |
2616 | ||
2617 | int | |
a2369ed3 | 2618 | and64_2_operand (rtx op, enum machine_mode mode) |
0ba1b2ff | 2619 | { |
a3c9585f | 2620 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
0ba1b2ff AM |
2621 | return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode); |
2622 | ||
2623 | return logical_operand (op, mode) || mask64_2_operand (op, mode); | |
2624 | } | |
2625 | ||
a260abc9 DE |
2626 | /* Return 1 if the operand is either a non-special register or a |
2627 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
2628 | |
2629 | int | |
a2369ed3 | 2630 | and_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 2631 | { |
a4f6c312 | 2632 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2633 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
2634 | ||
2635 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
2636 | } |
2637 | ||
9878760c RK |
2638 | /* Return 1 if the operand is a general register or memory operand. */ |
2639 | ||
2640 | int | |
a2369ed3 | 2641 | reg_or_mem_operand (rtx op, enum machine_mode mode) |
9878760c | 2642 | { |
b6c9286a MM |
2643 | return (gpc_reg_operand (op, mode) |
2644 | || memory_operand (op, mode) | |
4c81e946 | 2645 | || macho_lo_sum_memory_operand (op, mode) |
b6c9286a | 2646 | || volatile_mem_operand (op, mode)); |
9878760c RK |
2647 | } |
2648 | ||
a7a813f7 | 2649 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 2650 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
2651 | instruction. */ |
2652 | ||
2653 | int | |
a2369ed3 | 2654 | lwa_operand (rtx op, enum machine_mode mode) |
a7a813f7 RK |
2655 | { |
2656 | rtx inner = op; | |
2657 | ||
2658 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
2659 | inner = SUBREG_REG (inner); | |
2660 | ||
2661 | return gpc_reg_operand (inner, mode) | |
2662 | || (memory_operand (inner, mode) | |
2663 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
2664 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
2665 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
2666 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
2667 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
2668 | } |
2669 | ||
cc4d5fec JH |
2670 | /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */ |
2671 | ||
2672 | int | |
a2369ed3 | 2673 | symbol_ref_operand (rtx op, enum machine_mode mode) |
cc4d5fec JH |
2674 | { |
2675 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2676 | return 0; | |
2677 | ||
473f51b6 DE |
2678 | return (GET_CODE (op) == SYMBOL_REF |
2679 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))); | |
cc4d5fec JH |
2680 | } |
2681 | ||
9878760c | 2682 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
cc4d5fec | 2683 | to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */ |
9878760c RK |
2684 | |
2685 | int | |
a2369ed3 | 2686 | call_operand (rtx op, enum machine_mode mode) |
9878760c RK |
2687 | { |
2688 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2689 | return 0; | |
2690 | ||
2691 | return (GET_CODE (op) == SYMBOL_REF | |
cc4d5fec JH |
2692 | || (GET_CODE (op) == REG |
2693 | && (REGNO (op) == LINK_REGISTER_REGNUM | |
2694 | || REGNO (op) == COUNT_REGISTER_REGNUM | |
2695 | || REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
9878760c RK |
2696 | } |
2697 | ||
2af3d377 | 2698 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
d1908feb | 2699 | this file. */ |
2af3d377 RK |
2700 | |
2701 | int | |
a2369ed3 DJ |
2702 | current_file_function_operand (rtx op, |
2703 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
2af3d377 | 2704 | { |
473f51b6 DE |
2705 | return (GET_CODE (op) == SYMBOL_REF |
2706 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
2707 | && (SYMBOL_REF_LOCAL_P (op) | |
2708 | || (op == XEXP (DECL_RTL (current_function_decl), 0)))); | |
2af3d377 RK |
2709 | } |
2710 | ||
9878760c RK |
2711 | /* Return 1 if this operand is a valid input for a move insn. */ |
2712 | ||
2713 | int | |
a2369ed3 | 2714 | input_operand (rtx op, enum machine_mode mode) |
9878760c | 2715 | { |
eb4e8003 | 2716 | /* Memory is always valid. */ |
9878760c RK |
2717 | if (memory_operand (op, mode)) |
2718 | return 1; | |
2719 | ||
eb4e8003 RK |
2720 | /* For floating-point, easy constants are valid. */ |
2721 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2722 | && CONSTANT_P (op) | |
2723 | && easy_fp_constant (op, mode)) | |
2724 | return 1; | |
2725 | ||
4e74d8ec MM |
2726 | /* Allow any integer constant. */ |
2727 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 2728 | && (GET_CODE (op) == CONST_INT |
e675f625 | 2729 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
2730 | return 1; |
2731 | ||
d744e06e AH |
2732 | /* Allow easy vector constants. */ |
2733 | if (GET_CODE (op) == CONST_VECTOR | |
2734 | && easy_vector_constant (op, mode)) | |
2735 | return 1; | |
2736 | ||
eb4e8003 RK |
2737 | /* For floating-point or multi-word mode, the only remaining valid type |
2738 | is a register. */ | |
9878760c RK |
2739 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
2740 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 2741 | return register_operand (op, mode); |
9878760c | 2742 | |
88fe15a1 RK |
2743 | /* The only cases left are integral modes one word or smaller (we |
2744 | do not get called for MODE_CC values). These can be in any | |
2745 | register. */ | |
2746 | if (register_operand (op, mode)) | |
a8b3aeda | 2747 | return 1; |
88fe15a1 | 2748 | |
84cf9dda | 2749 | /* A SYMBOL_REF referring to the TOC is valid. */ |
4d588c14 | 2750 | if (legitimate_constant_pool_address_p (op)) |
84cf9dda RK |
2751 | return 1; |
2752 | ||
9ebbca7d | 2753 | /* A constant pool expression (relative to the TOC) is valid */ |
4d588c14 | 2754 | if (toc_relative_expr_p (op)) |
b6c9286a MM |
2755 | return 1; |
2756 | ||
88228c4b MM |
2757 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
2758 | to be valid. */ | |
f607bc57 | 2759 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
2760 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
2761 | && small_data_operand (op, Pmode)) | |
2762 | return 1; | |
2763 | ||
042259f2 | 2764 | return 0; |
9878760c | 2765 | } |
7509c759 | 2766 | |
95727fb8 AP |
2767 | |
2768 | /* Darwin, AIX increases natural record alignment to doubleword if the first | |
2769 | field is an FP double while the FP fields remain word aligned. */ | |
2770 | ||
19d66194 | 2771 | unsigned int |
95727fb8 AP |
2772 | rs6000_special_round_type_align (tree type, int computed, int specified) |
2773 | { | |
2774 | tree field = TYPE_FIELDS (type); | |
95727fb8 AP |
2775 | |
2776 | /* Skip all the static variables only if ABI is greater than | |
71cc389b | 2777 | 1 or equal to 0. */ |
3ce5437a | 2778 | while (field != NULL && TREE_CODE (field) == VAR_DECL) |
95727fb8 AP |
2779 | field = TREE_CHAIN (field); |
2780 | ||
3ce5437a | 2781 | if (field == NULL || field == type || DECL_MODE (field) != DFmode) |
95727fb8 AP |
2782 | return MAX (computed, specified); |
2783 | ||
2784 | return MAX (MAX (computed, specified), 64); | |
2785 | } | |
2786 | ||
a4f6c312 | 2787 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
2788 | |
2789 | int | |
a2369ed3 DJ |
2790 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
2791 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
7509c759 | 2792 | { |
38c1f2d7 | 2793 | #if TARGET_ELF |
5f59ecb7 | 2794 | rtx sym_ref; |
7509c759 | 2795 | |
d9407988 | 2796 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 2797 | return 0; |
a54d04b7 | 2798 | |
f607bc57 | 2799 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
2800 | return 0; |
2801 | ||
88228c4b MM |
2802 | if (GET_CODE (op) == SYMBOL_REF) |
2803 | sym_ref = op; | |
2804 | ||
2805 | else if (GET_CODE (op) != CONST | |
2806 | || GET_CODE (XEXP (op, 0)) != PLUS | |
2807 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
2808 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
2809 | return 0; |
2810 | ||
88228c4b | 2811 | else |
dbf55e53 MM |
2812 | { |
2813 | rtx sum = XEXP (op, 0); | |
2814 | HOST_WIDE_INT summand; | |
2815 | ||
2816 | /* We have to be careful here, because it is the referenced address | |
2817 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
2818 | summand = INTVAL (XEXP (sum, 1)); | |
307b599c | 2819 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
dbf55e53 MM |
2820 | return 0; |
2821 | ||
2822 | sym_ref = XEXP (sum, 0); | |
2823 | } | |
88228c4b | 2824 | |
20bfcd69 | 2825 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
2826 | #else |
2827 | return 0; | |
2828 | #endif | |
7509c759 | 2829 | } |
46c07df8 | 2830 | |
d2288d5d HP |
2831 | /* Return true, if operand is a memory operand and has a |
2832 | displacement divisible by 4. */ | |
2833 | ||
2834 | int | |
2835 | word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2836 | { | |
2837 | rtx addr; | |
2838 | int off = 0; | |
2839 | ||
2840 | if (!memory_operand (op, mode)) | |
2841 | return 0; | |
2842 | ||
2843 | addr = XEXP (op, 0); | |
2844 | if (GET_CODE (addr) == PLUS | |
2845 | && GET_CODE (XEXP (addr, 0)) == REG | |
2846 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2847 | off = INTVAL (XEXP (addr, 1)); | |
2848 | ||
2849 | return (off % 4) == 0; | |
2850 | } | |
2851 | ||
3a1f863f | 2852 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 2853 | |
3a1f863f DE |
2854 | bool |
2855 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 2856 | { |
3a1f863f DE |
2857 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
2858 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
2859 | } |
2860 | ||
9ebbca7d | 2861 | \f |
4d588c14 RH |
2862 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
2863 | ||
9ebbca7d | 2864 | static int |
a2369ed3 | 2865 | constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) |
9ebbca7d GK |
2866 | { |
2867 | switch (GET_CODE(op)) | |
2868 | { | |
2869 | case SYMBOL_REF: | |
c4501e62 JJ |
2870 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
2871 | return 0; | |
2872 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
2873 | { |
2874 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
2875 | { | |
2876 | *have_sym = 1; | |
2877 | return 1; | |
2878 | } | |
2879 | else | |
2880 | return 0; | |
2881 | } | |
2882 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
2883 | { | |
2884 | *have_toc = 1; | |
2885 | return 1; | |
2886 | } | |
2887 | else | |
2888 | return 0; | |
9ebbca7d GK |
2889 | case PLUS: |
2890 | case MINUS: | |
c1f11548 DE |
2891 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
2892 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 2893 | case CONST: |
a4f6c312 | 2894 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 2895 | case CONST_INT: |
a4f6c312 | 2896 | return 1; |
9ebbca7d | 2897 | default: |
a4f6c312 | 2898 | return 0; |
9ebbca7d GK |
2899 | } |
2900 | } | |
2901 | ||
4d588c14 | 2902 | static bool |
a2369ed3 | 2903 | constant_pool_expr_p (rtx op) |
9ebbca7d GK |
2904 | { |
2905 | int have_sym = 0; | |
2906 | int have_toc = 0; | |
2907 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
2908 | } | |
2909 | ||
4d588c14 | 2910 | static bool |
a2369ed3 | 2911 | toc_relative_expr_p (rtx op) |
9ebbca7d | 2912 | { |
4d588c14 RH |
2913 | int have_sym = 0; |
2914 | int have_toc = 0; | |
2915 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
2916 | } | |
2917 | ||
4d588c14 | 2918 | bool |
a2369ed3 | 2919 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
2920 | { |
2921 | return (TARGET_TOC | |
2922 | && GET_CODE (x) == PLUS | |
2923 | && GET_CODE (XEXP (x, 0)) == REG | |
2924 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
2925 | && constant_pool_expr_p (XEXP (x, 1))); | |
2926 | } | |
2927 | ||
2928 | static bool | |
a2369ed3 | 2929 | legitimate_small_data_p (enum machine_mode mode, rtx x) |
4d588c14 RH |
2930 | { |
2931 | return (DEFAULT_ABI == ABI_V4 | |
2932 | && !flag_pic && !TARGET_TOC | |
2933 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
2934 | && small_data_operand (x, mode)); | |
2935 | } | |
2936 | ||
60cdabab DE |
2937 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
2938 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
2939 | ||
76d2b81d DJ |
2940 | bool |
2941 | rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) | |
4d588c14 RH |
2942 | { |
2943 | unsigned HOST_WIDE_INT offset, extra; | |
2944 | ||
2945 | if (GET_CODE (x) != PLUS) | |
2946 | return false; | |
2947 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2948 | return false; | |
2949 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2950 | return false; | |
60cdabab DE |
2951 | if (legitimate_constant_pool_address_p (x)) |
2952 | return true; | |
4d588c14 RH |
2953 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
2954 | return false; | |
2955 | ||
2956 | offset = INTVAL (XEXP (x, 1)); | |
2957 | extra = 0; | |
2958 | switch (mode) | |
2959 | { | |
2960 | case V16QImode: | |
2961 | case V8HImode: | |
2962 | case V4SFmode: | |
2963 | case V4SImode: | |
2964 | /* AltiVec vector modes. Only reg+reg addressing is valid here, | |
2965 | which leaves the only valid constant offset of zero, which by | |
2966 | canonicalization rules is also invalid. */ | |
2967 | return false; | |
2968 | ||
2969 | case V4HImode: | |
2970 | case V2SImode: | |
2971 | case V1DImode: | |
2972 | case V2SFmode: | |
2973 | /* SPE vector modes. */ | |
2974 | return SPE_CONST_OFFSET_OK (offset); | |
2975 | ||
2976 | case DFmode: | |
2977 | case DImode: | |
3364872d | 2978 | if (mode == DFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2979 | extra = 4; |
2980 | else if (offset & 3) | |
2981 | return false; | |
2982 | break; | |
2983 | ||
2984 | case TFmode: | |
2985 | case TImode: | |
3364872d | 2986 | if (mode == TFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2987 | extra = 12; |
2988 | else if (offset & 3) | |
2989 | return false; | |
2990 | else | |
2991 | extra = 8; | |
2992 | break; | |
2993 | ||
2994 | default: | |
2995 | break; | |
2996 | } | |
2997 | ||
b1917422 AM |
2998 | offset += 0x8000; |
2999 | return (offset < 0x10000) && (offset + extra < 0x10000); | |
4d588c14 RH |
3000 | } |
3001 | ||
3002 | static bool | |
a2369ed3 | 3003 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
3004 | { |
3005 | rtx op0, op1; | |
3006 | ||
3007 | if (GET_CODE (x) != PLUS) | |
3008 | return false; | |
3009 | op0 = XEXP (x, 0); | |
3010 | op1 = XEXP (x, 1); | |
3011 | ||
3012 | if (!REG_P (op0) || !REG_P (op1)) | |
3013 | return false; | |
3014 | ||
3015 | return ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
3016 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
3017 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
3018 | && INT_REG_OK_FOR_INDEX_P (op0, strict))); | |
9ebbca7d GK |
3019 | } |
3020 | ||
4d588c14 | 3021 | static inline bool |
a2369ed3 | 3022 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
3023 | { |
3024 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
3025 | } | |
3026 | ||
4c81e946 FJ |
3027 | static bool |
3028 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) | |
3029 | { | |
3030 | if (!TARGET_MACHO || !flag_pic | |
3031 | || mode != SImode || GET_CODE(x) != MEM) | |
3032 | return false; | |
3033 | x = XEXP (x, 0); | |
3034 | ||
3035 | if (GET_CODE (x) != LO_SUM) | |
3036 | return false; | |
3037 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3038 | return false; | |
3039 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
3040 | return false; | |
3041 | x = XEXP (x, 1); | |
3042 | ||
3043 | return CONSTANT_P (x); | |
3044 | } | |
3045 | ||
4d588c14 | 3046 | static bool |
a2369ed3 | 3047 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
3048 | { |
3049 | if (GET_CODE (x) != LO_SUM) | |
3050 | return false; | |
3051 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3052 | return false; | |
3053 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
3054 | return false; | |
3055 | x = XEXP (x, 1); | |
3056 | ||
8622e235 | 3057 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 3058 | { |
a29077da | 3059 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
3060 | return false; |
3061 | if (TARGET_TOC) | |
3062 | return false; | |
3063 | if (GET_MODE_NUNITS (mode) != 1) | |
3064 | return false; | |
3065 | if (GET_MODE_BITSIZE (mode) > 32 | |
3066 | && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)) | |
3067 | return false; | |
3068 | ||
3069 | return CONSTANT_P (x); | |
3070 | } | |
3071 | ||
3072 | return false; | |
3073 | } | |
3074 | ||
3075 | ||
9ebbca7d GK |
3076 | /* Try machine-dependent ways of modifying an illegitimate address |
3077 | to be legitimate. If we find one, return the new, valid address. | |
3078 | This is used from only one place: `memory_address' in explow.c. | |
3079 | ||
a4f6c312 SS |
3080 | OLDX is the address as it was before break_out_memory_refs was |
3081 | called. In some cases it is useful to look at this to decide what | |
3082 | needs to be done. | |
9ebbca7d | 3083 | |
a4f6c312 | 3084 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 3085 | |
a4f6c312 SS |
3086 | It is always safe for this function to do nothing. It exists to |
3087 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
3088 | |
3089 | On RS/6000, first check for the sum of a register with a constant | |
3090 | integer that is out of range. If so, generate code to add the | |
3091 | constant with the low-order 16 bits masked to the register and force | |
3092 | this result into another register (this can be done with `cau'). | |
3093 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
3094 | possibility of bit 16 being a one. | |
3095 | ||
3096 | Then check for the sum of a register and something not constant, try to | |
3097 | load the other things into a register and return the sum. */ | |
4d588c14 | 3098 | |
9ebbca7d | 3099 | rtx |
a2369ed3 DJ |
3100 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
3101 | enum machine_mode mode) | |
0ac081f6 | 3102 | { |
c4501e62 JJ |
3103 | if (GET_CODE (x) == SYMBOL_REF) |
3104 | { | |
3105 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
3106 | if (model != 0) | |
3107 | return rs6000_legitimize_tls_address (x, model); | |
3108 | } | |
3109 | ||
9ebbca7d GK |
3110 | if (GET_CODE (x) == PLUS |
3111 | && GET_CODE (XEXP (x, 0)) == REG | |
3112 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3113 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
3114 | { | |
3115 | HOST_WIDE_INT high_int, low_int; | |
3116 | rtx sum; | |
a65c591c DE |
3117 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
3118 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
3119 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
3120 | GEN_INT (high_int)), 0); | |
3121 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
3122 | } | |
3123 | else if (GET_CODE (x) == PLUS | |
3124 | && GET_CODE (XEXP (x, 0)) == REG | |
3125 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 3126 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
3127 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3128 | || TARGET_POWERPC64 | |
fcce224d | 3129 | || (mode != DFmode && mode != TFmode)) |
9ebbca7d GK |
3130 | && (TARGET_POWERPC64 || mode != DImode) |
3131 | && mode != TImode) | |
3132 | { | |
3133 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3134 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
3135 | } | |
0ac081f6 AH |
3136 | else if (ALTIVEC_VECTOR_MODE (mode)) |
3137 | { | |
3138 | rtx reg; | |
3139 | ||
3140 | /* Make sure both operands are registers. */ | |
3141 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 3142 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
3143 | force_reg (Pmode, XEXP (x, 1))); |
3144 | ||
3145 | reg = force_reg (Pmode, x); | |
3146 | return reg; | |
3147 | } | |
a3170dc6 AH |
3148 | else if (SPE_VECTOR_MODE (mode)) |
3149 | { | |
3150 | /* We accept [reg + reg] and [reg + OFFSET]. */ | |
3151 | ||
3152 | if (GET_CODE (x) == PLUS) | |
3153 | { | |
3154 | rtx op1 = XEXP (x, 0); | |
3155 | rtx op2 = XEXP (x, 1); | |
3156 | ||
3157 | op1 = force_reg (Pmode, op1); | |
3158 | ||
3159 | if (GET_CODE (op2) != REG | |
3160 | && (GET_CODE (op2) != CONST_INT | |
3161 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
3162 | op2 = force_reg (Pmode, op2); | |
3163 | ||
3164 | return gen_rtx_PLUS (Pmode, op1, op2); | |
3165 | } | |
3166 | ||
3167 | return force_reg (Pmode, x); | |
3168 | } | |
f1384257 AM |
3169 | else if (TARGET_ELF |
3170 | && TARGET_32BIT | |
3171 | && TARGET_NO_TOC | |
3172 | && ! flag_pic | |
9ebbca7d GK |
3173 | && GET_CODE (x) != CONST_INT |
3174 | && GET_CODE (x) != CONST_DOUBLE | |
3175 | && CONSTANT_P (x) | |
6ac7bf2c GK |
3176 | && GET_MODE_NUNITS (mode) == 1 |
3177 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 3178 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
3179 | { |
3180 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3181 | emit_insn (gen_elf_high (reg, x)); |
3182 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 3183 | } |
ee890fe2 SS |
3184 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
3185 | && ! flag_pic | |
ab82a49f AP |
3186 | #if TARGET_MACHO |
3187 | && ! MACHO_DYNAMIC_NO_PIC_P | |
3188 | #endif | |
ee890fe2 SS |
3189 | && GET_CODE (x) != CONST_INT |
3190 | && GET_CODE (x) != CONST_DOUBLE | |
3191 | && CONSTANT_P (x) | |
a3170dc6 | 3192 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
ee890fe2 SS |
3193 | && mode != DImode |
3194 | && mode != TImode) | |
3195 | { | |
3196 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3197 | emit_insn (gen_macho_high (reg, x)); |
3198 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 3199 | } |
9ebbca7d | 3200 | else if (TARGET_TOC |
4d588c14 | 3201 | && constant_pool_expr_p (x) |
a9098fd0 | 3202 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
3203 | { |
3204 | return create_TOC_reference (x); | |
3205 | } | |
3206 | else | |
3207 | return NULL_RTX; | |
3208 | } | |
258bfae2 | 3209 | |
c973d557 JJ |
3210 | /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. |
3211 | We need to emit DTP-relative relocations. */ | |
3212 | ||
3213 | void | |
3214 | rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
3215 | { | |
3216 | switch (size) | |
3217 | { | |
3218 | case 4: | |
3219 | fputs ("\t.long\t", file); | |
3220 | break; | |
3221 | case 8: | |
3222 | fputs (DOUBLE_INT_ASM_OP, file); | |
3223 | break; | |
3224 | default: | |
3225 | abort (); | |
3226 | } | |
3227 | output_addr_const (file, x); | |
3228 | fputs ("@dtprel+0x8000", file); | |
3229 | } | |
3230 | ||
c4501e62 JJ |
3231 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
3232 | ||
3233 | static GTY(()) rtx rs6000_tls_symbol; | |
3234 | static rtx | |
863d938c | 3235 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
3236 | { |
3237 | if (!rs6000_tls_symbol) | |
3238 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
3239 | ||
3240 | return rs6000_tls_symbol; | |
3241 | } | |
3242 | ||
3243 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
3244 | ||
3245 | static GTY(()) rtx rs6000_got_symbol; | |
3246 | static rtx | |
863d938c | 3247 | rs6000_got_sym (void) |
c4501e62 JJ |
3248 | { |
3249 | if (!rs6000_got_symbol) | |
3250 | { | |
3251 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3252 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
3253 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
3254 | } | |
3255 | ||
3256 | return rs6000_got_symbol; | |
3257 | } | |
3258 | ||
3259 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3260 | this (thread-local) address. */ | |
3261 | ||
3262 | static rtx | |
a2369ed3 | 3263 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
3264 | { |
3265 | rtx dest, insn; | |
3266 | ||
3267 | dest = gen_reg_rtx (Pmode); | |
3268 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
3269 | { | |
3270 | rtx tlsreg; | |
3271 | ||
3272 | if (TARGET_64BIT) | |
3273 | { | |
3274 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3275 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
3276 | } | |
3277 | else | |
3278 | { | |
3279 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3280 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
3281 | } | |
3282 | emit_insn (insn); | |
3283 | } | |
3284 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
3285 | { | |
3286 | rtx tlsreg, tmp; | |
3287 | ||
3288 | tmp = gen_reg_rtx (Pmode); | |
3289 | if (TARGET_64BIT) | |
3290 | { | |
3291 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3292 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
3293 | } | |
3294 | else | |
3295 | { | |
3296 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3297 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
3298 | } | |
3299 | emit_insn (insn); | |
3300 | if (TARGET_64BIT) | |
3301 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
3302 | else | |
3303 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
3304 | emit_insn (insn); | |
3305 | } | |
3306 | else | |
3307 | { | |
3308 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
3309 | ||
3310 | if (TARGET_64BIT) | |
3311 | got = gen_rtx_REG (Pmode, TOC_REGISTER); | |
3312 | else | |
3313 | { | |
3314 | if (flag_pic == 1) | |
3315 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
3316 | else | |
3317 | { | |
3318 | rtx gsym = rs6000_got_sym (); | |
3319 | got = gen_reg_rtx (Pmode); | |
3320 | if (flag_pic == 0) | |
3321 | rs6000_emit_move (got, gsym, Pmode); | |
3322 | else | |
3323 | { | |
3324 | char buf[30]; | |
3325 | static int tls_got_labelno = 0; | |
3326 | rtx tempLR, lab, tmp3, mem; | |
3327 | rtx first, last; | |
3328 | ||
3329 | ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++); | |
3330 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
3331 | tempLR = gen_reg_rtx (Pmode); | |
3332 | tmp1 = gen_reg_rtx (Pmode); | |
3333 | tmp2 = gen_reg_rtx (Pmode); | |
3334 | tmp3 = gen_reg_rtx (Pmode); | |
3335 | mem = gen_rtx_MEM (Pmode, tmp1); | |
3336 | RTX_UNCHANGING_P (mem) = 1; | |
3337 | ||
3338 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab, | |
3339 | gsym)); | |
3340 | emit_move_insn (tmp1, tempLR); | |
3341 | emit_move_insn (tmp2, mem); | |
3342 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
3343 | last = emit_move_insn (got, tmp3); | |
3344 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
3345 | REG_NOTES (last)); | |
3346 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
3347 | REG_NOTES (first)); | |
3348 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
3349 | REG_NOTES (last)); | |
3350 | } | |
3351 | } | |
3352 | } | |
3353 | ||
3354 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
3355 | { | |
3356 | r3 = gen_rtx_REG (Pmode, 3); | |
3357 | if (TARGET_64BIT) | |
3358 | insn = gen_tls_gd_64 (r3, got, addr); | |
3359 | else | |
3360 | insn = gen_tls_gd_32 (r3, got, addr); | |
3361 | start_sequence (); | |
3362 | emit_insn (insn); | |
3363 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3364 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3365 | insn = emit_call_insn (insn); | |
3366 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3367 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3368 | insn = get_insns (); | |
3369 | end_sequence (); | |
3370 | emit_libcall_block (insn, dest, r3, addr); | |
3371 | } | |
3372 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
3373 | { | |
3374 | r3 = gen_rtx_REG (Pmode, 3); | |
3375 | if (TARGET_64BIT) | |
3376 | insn = gen_tls_ld_64 (r3, got); | |
3377 | else | |
3378 | insn = gen_tls_ld_32 (r3, got); | |
3379 | start_sequence (); | |
3380 | emit_insn (insn); | |
3381 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3382 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3383 | insn = emit_call_insn (insn); | |
3384 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3385 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3386 | insn = get_insns (); | |
3387 | end_sequence (); | |
3388 | tmp1 = gen_reg_rtx (Pmode); | |
3389 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
3390 | UNSPEC_TLSLD); | |
3391 | emit_libcall_block (insn, tmp1, r3, eqv); | |
3392 | if (rs6000_tls_size == 16) | |
3393 | { | |
3394 | if (TARGET_64BIT) | |
3395 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
3396 | else | |
3397 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
3398 | } | |
3399 | else if (rs6000_tls_size == 32) | |
3400 | { | |
3401 | tmp2 = gen_reg_rtx (Pmode); | |
3402 | if (TARGET_64BIT) | |
3403 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
3404 | else | |
3405 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
3406 | emit_insn (insn); | |
3407 | if (TARGET_64BIT) | |
3408 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
3409 | else | |
3410 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
3411 | } | |
3412 | else | |
3413 | { | |
3414 | tmp2 = gen_reg_rtx (Pmode); | |
3415 | if (TARGET_64BIT) | |
3416 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
3417 | else | |
3418 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
3419 | emit_insn (insn); | |
3420 | insn = gen_rtx_SET (Pmode, dest, | |
3421 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
3422 | } | |
3423 | emit_insn (insn); | |
3424 | } | |
3425 | else | |
3426 | { | |
3427 | /* IE, or 64 bit offset LE. */ | |
3428 | tmp2 = gen_reg_rtx (Pmode); | |
3429 | if (TARGET_64BIT) | |
3430 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
3431 | else | |
3432 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
3433 | emit_insn (insn); | |
3434 | if (TARGET_64BIT) | |
3435 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
3436 | else | |
3437 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
3438 | emit_insn (insn); | |
3439 | } | |
3440 | } | |
3441 | ||
3442 | return dest; | |
3443 | } | |
3444 | ||
3445 | /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in | |
3446 | instruction definitions. */ | |
3447 | ||
3448 | int | |
a2369ed3 | 3449 | rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
c4501e62 JJ |
3450 | { |
3451 | return RS6000_SYMBOL_REF_TLS_P (x); | |
3452 | } | |
3453 | ||
3454 | /* Return 1 if X contains a thread-local symbol. */ | |
3455 | ||
3456 | bool | |
a2369ed3 | 3457 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 3458 | { |
cd413cab AP |
3459 | if (! TARGET_HAVE_TLS) |
3460 | return false; | |
3461 | ||
c4501e62 JJ |
3462 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
3463 | } | |
3464 | ||
3465 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
3466 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
3467 | ||
3468 | static inline int | |
a2369ed3 | 3469 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
3470 | { |
3471 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
3472 | } | |
3473 | ||
24ea750e DJ |
3474 | /* The convention appears to be to define this wherever it is used. |
3475 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
3476 | is now used here. */ | |
3477 | #ifndef REG_MODE_OK_FOR_BASE_P | |
3478 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
3479 | #endif | |
3480 | ||
3481 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
3482 | replace the input X, or the original X if no replacement is called for. | |
3483 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
3484 | 0 if it should not. | |
3485 | ||
3486 | For RS/6000, we wish to handle large displacements off a base | |
3487 | register by splitting the addend across an addiu/addis and the mem insn. | |
3488 | This cuts number of extra insns needed from 3 to 1. | |
3489 | ||
3490 | On Darwin, we use this to generate code for floating point constants. | |
3491 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
3492 | The Darwin code is inside #if TARGET_MACHO because only then is | |
3493 | machopic_function_base_name() defined. */ | |
3494 | rtx | |
a2369ed3 DJ |
3495 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
3496 | int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e DJ |
3497 | { |
3498 | /* We must recognize output that we have already generated ourselves. */ | |
3499 | if (GET_CODE (x) == PLUS | |
3500 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3501 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
3502 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3503 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3504 | { | |
3505 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3506 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
3507 | opnum, (enum reload_type)type); | |
3508 | *win = 1; | |
3509 | return x; | |
3510 | } | |
3deb2758 | 3511 | |
24ea750e DJ |
3512 | #if TARGET_MACHO |
3513 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
3514 | && GET_CODE (x) == LO_SUM | |
3515 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3516 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
3517 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
3518 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
3519 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
3520 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
3521 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
3522 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
3523 | { | |
3524 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 3525 | floating point constant. */ |
24ea750e DJ |
3526 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
3527 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
3528 | opnum, (enum reload_type)type); | |
3529 | *win = 1; | |
3530 | return x; | |
3531 | } | |
3532 | #endif | |
3533 | if (GET_CODE (x) == PLUS | |
3534 | && GET_CODE (XEXP (x, 0)) == REG | |
3535 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
3536 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 3537 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 3538 | && !SPE_VECTOR_MODE (mode) |
78c875e8 | 3539 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
3540 | { |
3541 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
3542 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
3543 | HOST_WIDE_INT high | |
3544 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
3545 | ||
3546 | /* Check for 32-bit overflow. */ | |
3547 | if (high + low != val) | |
3548 | { | |
3549 | *win = 0; | |
3550 | return x; | |
3551 | } | |
3552 | ||
3553 | /* Reload the high part into a base reg; leave the low part | |
3554 | in the mem directly. */ | |
3555 | ||
3556 | x = gen_rtx_PLUS (GET_MODE (x), | |
3557 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
3558 | GEN_INT (high)), | |
3559 | GEN_INT (low)); | |
3560 | ||
3561 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3562 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
3563 | opnum, (enum reload_type)type); | |
3564 | *win = 1; | |
3565 | return x; | |
3566 | } | |
3567 | #if TARGET_MACHO | |
3568 | if (GET_CODE (x) == SYMBOL_REF | |
3569 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 3570 | && !ALTIVEC_VECTOR_MODE (mode) |
a29077da GK |
3571 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
3572 | /* Don't do this for TFmode, since the result isn't offsettable. */ | |
3573 | && mode != TFmode) | |
24ea750e | 3574 | { |
a29077da GK |
3575 | if (flag_pic) |
3576 | { | |
3577 | rtx offset = gen_rtx_CONST (Pmode, | |
3578 | gen_rtx_MINUS (Pmode, x, | |
3579 | gen_rtx_SYMBOL_REF (Pmode, | |
3580 | machopic_function_base_name ()))); | |
3581 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
3582 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
3583 | gen_rtx_HIGH (Pmode, offset)), offset); | |
3584 | } | |
3585 | else | |
3586 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
3587 | gen_rtx_HIGH (Pmode, x), x); | |
3588 | ||
24ea750e | 3589 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
3590 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3591 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3592 | *win = 1; |
3593 | return x; | |
3594 | } | |
3595 | #endif | |
3596 | if (TARGET_TOC | |
4d588c14 | 3597 | && constant_pool_expr_p (x) |
c1f11548 | 3598 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3599 | { |
3600 | (x) = create_TOC_reference (x); | |
3601 | *win = 1; | |
3602 | return x; | |
3603 | } | |
3604 | *win = 0; | |
3605 | return x; | |
3606 | } | |
3607 | ||
258bfae2 FS |
3608 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3609 | that is a valid memory address for an instruction. | |
3610 | The MODE argument is the machine mode for the MEM expression | |
3611 | that wants to use this address. | |
3612 | ||
3613 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3614 | refers to a constant pool entry of an address (or the sum of it | |
3615 | plus a constant), a short (16-bit signed) constant plus a register, | |
3616 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3617 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3618 | we must ensure that both words are addressable or PowerPC64 with offset |
3619 | word aligned. | |
3620 | ||
3621 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
76d2b81d | 3622 | 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because |
258bfae2 FS |
3623 | adjacent memory cells are accessed by adding word-sized offsets |
3624 | during assembly output. */ | |
3625 | int | |
a2369ed3 | 3626 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 3627 | { |
c4501e62 JJ |
3628 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3629 | return 0; | |
4d588c14 | 3630 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3631 | return 1; |
3632 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3633 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3634 | && !SPE_VECTOR_MODE (mode) |
258bfae2 | 3635 | && TARGET_UPDATE |
4d588c14 | 3636 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3637 | return 1; |
4d588c14 | 3638 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 3639 | return 1; |
4d588c14 | 3640 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3641 | return 1; |
3642 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3643 | if (! reg_ok_strict | |
3644 | && GET_CODE (x) == PLUS | |
3645 | && GET_CODE (XEXP (x, 0)) == REG | |
708d2456 HP |
3646 | && (XEXP (x, 0) == virtual_stack_vars_rtx |
3647 | || XEXP (x, 0) == arg_pointer_rtx) | |
258bfae2 FS |
3648 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
3649 | return 1; | |
76d2b81d | 3650 | if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3651 | return 1; |
3652 | if (mode != TImode | |
76d2b81d | 3653 | && mode != TFmode |
a3170dc6 AH |
3654 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3655 | || TARGET_POWERPC64 | |
fcce224d | 3656 | || (mode != DFmode && mode != TFmode)) |
258bfae2 | 3657 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3658 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3659 | return 1; |
4d588c14 | 3660 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3661 | return 1; |
3662 | return 0; | |
3663 | } | |
4d588c14 RH |
3664 | |
3665 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3666 | has an effect that depends on the machine mode it is used for. | |
3667 | ||
3668 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3669 | modes don't allow them) or is a pre-increment or decrement. | |
3670 | ||
3671 | ??? Except that due to conceptual problems in offsettable_address_p | |
3672 | we can't really report the problems of integral offsets. So leave | |
3673 | this assuming that the adjustable offset must be valid for the | |
3674 | sub-words of a TFmode operand, which is what we had before. */ | |
3675 | ||
3676 | bool | |
a2369ed3 | 3677 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
3678 | { |
3679 | switch (GET_CODE (addr)) | |
3680 | { | |
3681 | case PLUS: | |
3682 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3683 | { | |
3684 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3685 | return val + 12 + 0x8000 >= 0x10000; | |
3686 | } | |
3687 | break; | |
3688 | ||
3689 | case LO_SUM: | |
3690 | return true; | |
3691 | ||
3692 | case PRE_INC: | |
3693 | case PRE_DEC: | |
3694 | return TARGET_UPDATE; | |
3695 | ||
3696 | default: | |
3697 | break; | |
3698 | } | |
3699 | ||
3700 | return false; | |
3701 | } | |
d8ecbcdb AH |
3702 | |
3703 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
3704 | to hold something of mode MODE. | |
3705 | This is ordinarily the length in words of a value of mode MODE | |
3706 | but can be less for certain modes in special long registers. | |
3707 | ||
3708 | For the SPE, GPRs are 64 bits but only 32 bits are visible in | |
3709 | scalar instructions. The upper 32 bits are only available to the | |
3710 | SIMD instructions. | |
3711 | ||
3712 | POWER and PowerPC GPRs hold 32 bits worth; | |
3713 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
3714 | ||
3715 | int | |
3716 | rs6000_hard_regno_nregs (int regno, enum machine_mode mode) | |
3717 | { | |
3718 | if (FP_REGNO_P (regno)) | |
3719 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; | |
3720 | ||
3721 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
3722 | return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; | |
3723 | ||
3724 | if (ALTIVEC_REGNO_P (regno)) | |
3725 | return | |
3726 | (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; | |
3727 | ||
3728 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3729 | } | |
2aa4498c AH |
3730 | |
3731 | /* Change register usage conditional on target flags. */ | |
3732 | void | |
3733 | rs6000_conditional_register_usage (void) | |
3734 | { | |
3735 | int i; | |
3736 | ||
3737 | /* Set MQ register fixed (already call_used) if not POWER | |
3738 | architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not | |
3739 | be allocated. */ | |
3740 | if (! TARGET_POWER) | |
3741 | fixed_regs[64] = 1; | |
3742 | ||
3743 | /* 64-bit AIX reserves GPR13 for thread-private data. */ | |
3744 | if (TARGET_64BIT) | |
3745 | fixed_regs[13] = call_used_regs[13] | |
3746 | = call_really_used_regs[13] = 1; | |
3747 | ||
3748 | /* Conditionally disable FPRs. */ | |
3749 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
3750 | for (i = 32; i < 64; i++) | |
3751 | fixed_regs[i] = call_used_regs[i] | |
3752 | = call_really_used_regs[i] = 1; | |
3753 | ||
3754 | if (DEFAULT_ABI == ABI_V4 | |
3755 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3756 | && flag_pic == 2) | |
3757 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3758 | ||
3759 | if (DEFAULT_ABI == ABI_V4 | |
3760 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3761 | && flag_pic == 1) | |
3762 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3763 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3764 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3765 | ||
3766 | if (DEFAULT_ABI == ABI_DARWIN | |
3767 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
3768 | global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3769 | = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3770 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3771 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3772 | ||
b4db40bf JJ |
3773 | if (TARGET_TOC && TARGET_MINIMAL_TOC) |
3774 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3775 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3776 | ||
2aa4498c AH |
3777 | if (TARGET_ALTIVEC) |
3778 | global_regs[VSCR_REGNO] = 1; | |
3779 | ||
3780 | if (TARGET_SPE) | |
3781 | { | |
3782 | global_regs[SPEFSCR_REGNO] = 1; | |
3783 | fixed_regs[FIXED_SCRATCH] | |
3784 | = call_used_regs[FIXED_SCRATCH] | |
3785 | = call_really_used_regs[FIXED_SCRATCH] = 1; | |
3786 | } | |
3787 | ||
3788 | if (! TARGET_ALTIVEC) | |
3789 | { | |
3790 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
3791 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
3792 | call_really_used_regs[VRSAVE_REGNO] = 1; | |
3793 | } | |
3794 | ||
3795 | if (TARGET_ALTIVEC_ABI) | |
3796 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) | |
3797 | call_used_regs[i] = call_really_used_regs[i] = 1; | |
3798 | } | |
fb4d4348 | 3799 | \f |
a4f6c312 SS |
3800 | /* Try to output insns to set TARGET equal to the constant C if it can |
3801 | be done in less than N insns. Do all computations in MODE. | |
3802 | Returns the place where the output has been placed if it can be | |
3803 | done and the insns have been emitted. If it would take more than N | |
3804 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
3805 | |
3806 | rtx | |
a2369ed3 DJ |
3807 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
3808 | rtx source, int n ATTRIBUTE_UNUSED) | |
2bfcf297 | 3809 | { |
af8cb5c5 | 3810 | rtx result, insn, set; |
2bfcf297 DB |
3811 | HOST_WIDE_INT c0, c1; |
3812 | ||
af8cb5c5 | 3813 | if (mode == QImode || mode == HImode) |
2bfcf297 DB |
3814 | { |
3815 | if (dest == NULL) | |
3816 | dest = gen_reg_rtx (mode); | |
3817 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
3818 | return dest; | |
3819 | } | |
af8cb5c5 | 3820 | else if (mode == SImode) |
2bfcf297 | 3821 | { |
af8cb5c5 DE |
3822 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
3823 | ||
3824 | emit_insn (gen_rtx_SET (VOIDmode, result, | |
3825 | GEN_INT (INTVAL (source) | |
3826 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
3827 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3828 | gen_rtx_IOR (SImode, result, | |
3829 | GEN_INT (INTVAL (source) & 0xffff)))); | |
3830 | result = dest; | |
2bfcf297 | 3831 | } |
af8cb5c5 | 3832 | else if (mode == DImode) |
2bfcf297 | 3833 | { |
af8cb5c5 DE |
3834 | if (GET_CODE (source) == CONST_INT) |
3835 | { | |
3836 | c0 = INTVAL (source); | |
3837 | c1 = -(c0 < 0); | |
3838 | } | |
3839 | else if (GET_CODE (source) == CONST_DOUBLE) | |
3840 | { | |
2bfcf297 | 3841 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
3842 | c0 = CONST_DOUBLE_LOW (source); |
3843 | c1 = -(c0 < 0); | |
2bfcf297 | 3844 | #else |
af8cb5c5 DE |
3845 | c0 = CONST_DOUBLE_LOW (source); |
3846 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 3847 | #endif |
af8cb5c5 DE |
3848 | } |
3849 | else | |
3850 | abort (); | |
3851 | ||
3852 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
2bfcf297 DB |
3853 | } |
3854 | else | |
a4f6c312 | 3855 | abort (); |
2bfcf297 | 3856 | |
af8cb5c5 DE |
3857 | insn = get_last_insn (); |
3858 | set = single_set (insn); | |
3859 | if (! CONSTANT_P (SET_SRC (set))) | |
3860 | set_unique_reg_note (insn, REG_EQUAL, source); | |
3861 | ||
3862 | return result; | |
2bfcf297 DB |
3863 | } |
3864 | ||
3865 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
3866 | fall back to a straight forward decomposition. We do this to avoid | |
3867 | exponential run times encountered when looking for longer sequences | |
3868 | with rs6000_emit_set_const. */ | |
3869 | static rtx | |
a2369ed3 | 3870 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
3871 | { |
3872 | if (!TARGET_POWERPC64) | |
3873 | { | |
3874 | rtx operand1, operand2; | |
3875 | ||
3876 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
3877 | DImode); | |
3878 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
3879 | DImode); | |
3880 | emit_move_insn (operand1, GEN_INT (c1)); | |
3881 | emit_move_insn (operand2, GEN_INT (c2)); | |
3882 | } | |
3883 | else | |
3884 | { | |
bc06712d | 3885 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 3886 | |
bc06712d | 3887 | ud1 = c1 & 0xffff; |
f921c9c9 | 3888 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 3889 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 3890 | c2 = c1 >> 32; |
2bfcf297 | 3891 | #endif |
bc06712d | 3892 | ud3 = c2 & 0xffff; |
f921c9c9 | 3893 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 3894 | |
bc06712d TR |
3895 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
3896 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) | |
2bfcf297 | 3897 | { |
bc06712d | 3898 | if (ud1 & 0x8000) |
b78d48dd | 3899 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
3900 | else |
3901 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 3902 | } |
2bfcf297 | 3903 | |
bc06712d TR |
3904 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
3905 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) | |
252b88f7 | 3906 | { |
bc06712d TR |
3907 | if (ud2 & 0x8000) |
3908 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) | |
3909 | - 0x80000000)); | |
252b88f7 | 3910 | else |
bc06712d TR |
3911 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
3912 | if (ud1 != 0) | |
3913 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 3914 | } |
bc06712d TR |
3915 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
3916 | || (ud4 == 0 && ! (ud3 & 0x8000))) | |
3917 | { | |
3918 | if (ud3 & 0x8000) | |
3919 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) | |
3920 | - 0x80000000)); | |
3921 | else | |
3922 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
3923 | ||
3924 | if (ud2 != 0) | |
3925 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
3926 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
3927 | if (ud1 != 0) | |
3928 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3929 | } | |
3930 | else | |
3931 | { | |
3932 | if (ud4 & 0x8000) | |
3933 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) | |
3934 | - 0x80000000)); | |
3935 | else | |
3936 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
3937 | ||
3938 | if (ud3 != 0) | |
3939 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 3940 | |
bc06712d TR |
3941 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
3942 | if (ud2 != 0) | |
3943 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, | |
3944 | GEN_INT (ud2 << 16))); | |
3945 | if (ud1 != 0) | |
3946 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3947 | } | |
3948 | } | |
2bfcf297 DB |
3949 | return dest; |
3950 | } | |
3951 | ||
76d2b81d DJ |
3952 | /* Helper for the following. Get rid of [r+r] memory refs |
3953 | in cases where it won't work (TImode, TFmode). */ | |
3954 | ||
3955 | static void | |
3956 | rs6000_eliminate_indexed_memrefs (rtx operands[2]) | |
3957 | { | |
3958 | if (GET_CODE (operands[0]) == MEM | |
3959 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
3960 | && ! reload_in_progress) | |
3961 | operands[0] | |
3962 | = replace_equiv_address (operands[0], | |
3963 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
3964 | ||
3965 | if (GET_CODE (operands[1]) == MEM | |
3966 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
3967 | && ! reload_in_progress) | |
3968 | operands[1] | |
3969 | = replace_equiv_address (operands[1], | |
3970 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
3971 | } | |
3972 | ||
fb4d4348 GK |
3973 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
3974 | void | |
a2369ed3 | 3975 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
3976 | { |
3977 | rtx operands[2]; | |
3978 | operands[0] = dest; | |
3979 | operands[1] = source; | |
3980 | ||
3981 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
3982 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3983 | && ! FLOAT_MODE_P (mode) | |
3984 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
3985 | { | |
3986 | /* FIXME. This should never happen. */ | |
3987 | /* Since it seems that it does, do the safe thing and convert | |
3988 | to a CONST_INT. */ | |
2496c7bd | 3989 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 GK |
3990 | } |
3991 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3992 | && ! FLOAT_MODE_P (mode) | |
3993 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
3994 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
3995 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
3996 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
3997 | abort (); | |
c9e8cb32 DD |
3998 | |
3999 | /* Check if GCC is setting up a block move that will end up using FP | |
4000 | registers as temporaries. We must make sure this is acceptable. */ | |
4001 | if (GET_CODE (operands[0]) == MEM | |
4002 | && GET_CODE (operands[1]) == MEM | |
4003 | && mode == DImode | |
41543739 GK |
4004 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
4005 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
4006 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
4007 | ? 32 : MEM_ALIGN (operands[0]))) | |
4008 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
4009 | ? 32 | |
4010 | : MEM_ALIGN (operands[1])))) | |
4011 | && ! MEM_VOLATILE_P (operands [0]) | |
4012 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 4013 | { |
41543739 GK |
4014 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
4015 | adjust_address (operands[1], SImode, 0)); | |
4016 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
4017 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
4018 | return; |
4019 | } | |
630d42a0 | 4020 | |
67cef334 DE |
4021 | if (!no_new_pseudos) |
4022 | { | |
4023 | if (GET_CODE (operands[1]) == MEM && optimize > 0 | |
4024 | && (mode == QImode || mode == HImode || mode == SImode) | |
4025 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode)) | |
4026 | { | |
4027 | rtx reg = gen_reg_rtx (word_mode); | |
4028 | ||
4029 | emit_insn (gen_rtx_SET (word_mode, reg, | |
4030 | gen_rtx_ZERO_EXTEND (word_mode, | |
4031 | operands[1]))); | |
4032 | operands[1] = gen_lowpart (mode, reg); | |
4033 | } | |
4034 | if (GET_CODE (operands[0]) != REG) | |
4035 | operands[1] = force_reg (mode, operands[1]); | |
4036 | } | |
a9098fd0 | 4037 | |
a3170dc6 AH |
4038 | if (mode == SFmode && ! TARGET_POWERPC |
4039 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 4040 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 4041 | { |
ffc14f31 GK |
4042 | int regnum; |
4043 | ||
4044 | if (reload_in_progress || reload_completed) | |
4045 | regnum = true_regnum (operands[1]); | |
4046 | else if (GET_CODE (operands[1]) == REG) | |
4047 | regnum = REGNO (operands[1]); | |
4048 | else | |
4049 | regnum = -1; | |
fb4d4348 GK |
4050 | |
4051 | /* If operands[1] is a register, on POWER it may have | |
4052 | double-precision data in it, so truncate it to single | |
4053 | precision. */ | |
4054 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
4055 | { | |
4056 | rtx newreg; | |
4057 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
4058 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
4059 | operands[1] = newreg; | |
4060 | } | |
4061 | } | |
4062 | ||
c4501e62 JJ |
4063 | /* Recognize the case where operand[1] is a reference to thread-local |
4064 | data and load its address to a register. */ | |
4065 | if (GET_CODE (operands[1]) == SYMBOL_REF) | |
4066 | { | |
4067 | enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]); | |
4068 | if (model != 0) | |
4069 | operands[1] = rs6000_legitimize_tls_address (operands[1], model); | |
4070 | } | |
4071 | ||
8f4e6caf RH |
4072 | /* Handle the case where reload calls us with an invalid address. */ |
4073 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 4074 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
4075 | || ! nonimmediate_operand (operands[0], mode))) |
4076 | goto emit_set; | |
4077 | ||
a9baceb1 GK |
4078 | /* 128-bit constant floating-point values on Darwin should really be |
4079 | loaded as two parts. */ | |
4080 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
4081 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
4082 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) | |
4083 | { | |
4084 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
4085 | know how to get a DFmode SUBREG of a TFmode. */ | |
4086 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), | |
4087 | simplify_gen_subreg (DImode, operands[1], mode, 0), | |
4088 | DImode); | |
4089 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, | |
4090 | GET_MODE_SIZE (DImode)), | |
4091 | simplify_gen_subreg (DImode, operands[1], mode, | |
4092 | GET_MODE_SIZE (DImode)), | |
4093 | DImode); | |
4094 | return; | |
4095 | } | |
4096 | ||
fb4d4348 GK |
4097 | /* FIXME: In the long term, this switch statement should go away |
4098 | and be replaced by a sequence of tests based on things like | |
4099 | mode == Pmode. */ | |
4100 | switch (mode) | |
4101 | { | |
4102 | case HImode: | |
4103 | case QImode: | |
4104 | if (CONSTANT_P (operands[1]) | |
4105 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 4106 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
4107 | break; |
4108 | ||
06f4e019 | 4109 | case TFmode: |
76d2b81d DJ |
4110 | rs6000_eliminate_indexed_memrefs (operands); |
4111 | /* fall through */ | |
4112 | ||
fb4d4348 GK |
4113 | case DFmode: |
4114 | case SFmode: | |
4115 | if (CONSTANT_P (operands[1]) | |
4116 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 4117 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
4118 | break; |
4119 | ||
0ac081f6 AH |
4120 | case V16QImode: |
4121 | case V8HImode: | |
4122 | case V4SFmode: | |
4123 | case V4SImode: | |
a3170dc6 AH |
4124 | case V4HImode: |
4125 | case V2SFmode: | |
4126 | case V2SImode: | |
00a892b8 | 4127 | case V1DImode: |
69ef87e2 | 4128 | if (CONSTANT_P (operands[1]) |
d744e06e | 4129 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
4130 | operands[1] = force_const_mem (mode, operands[1]); |
4131 | break; | |
4132 | ||
fb4d4348 | 4133 | case SImode: |
a9098fd0 | 4134 | case DImode: |
fb4d4348 GK |
4135 | /* Use default pattern for address of ELF small data */ |
4136 | if (TARGET_ELF | |
a9098fd0 | 4137 | && mode == Pmode |
f607bc57 | 4138 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
4139 | && (GET_CODE (operands[1]) == SYMBOL_REF |
4140 | || GET_CODE (operands[1]) == CONST) | |
4141 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
4142 | { |
4143 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
4144 | return; | |
4145 | } | |
4146 | ||
f607bc57 | 4147 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
4148 | && mode == Pmode && mode == SImode |
4149 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
4150 | { |
4151 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
4152 | return; | |
4153 | } | |
4154 | ||
ee890fe2 | 4155 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
4156 | && TARGET_NO_TOC |
4157 | && ! flag_pic | |
a9098fd0 | 4158 | && mode == Pmode |
fb4d4348 GK |
4159 | && CONSTANT_P (operands[1]) |
4160 | && GET_CODE (operands[1]) != HIGH | |
4161 | && GET_CODE (operands[1]) != CONST_INT) | |
4162 | { | |
a9098fd0 | 4163 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
4164 | |
4165 | /* If this is a function address on -mcall-aixdesc, | |
4166 | convert it to the address of the descriptor. */ | |
4167 | if (DEFAULT_ABI == ABI_AIX | |
4168 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4169 | && XSTR (operands[1], 0)[0] == '.') | |
4170 | { | |
4171 | const char *name = XSTR (operands[1], 0); | |
4172 | rtx new_ref; | |
4173 | while (*name == '.') | |
4174 | name++; | |
4175 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
4176 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
4177 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 4178 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 4179 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 4180 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
4181 | operands[1] = new_ref; |
4182 | } | |
7509c759 | 4183 | |
ee890fe2 SS |
4184 | if (DEFAULT_ABI == ABI_DARWIN) |
4185 | { | |
ab82a49f AP |
4186 | #if TARGET_MACHO |
4187 | if (MACHO_DYNAMIC_NO_PIC_P) | |
4188 | { | |
4189 | /* Take care of any required data indirection. */ | |
4190 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
4191 | operands[1], mode, operands[0]); | |
4192 | if (operands[0] != operands[1]) | |
4193 | emit_insn (gen_rtx_SET (VOIDmode, | |
4194 | operands[0], operands[1])); | |
4195 | return; | |
4196 | } | |
4197 | #endif | |
ee890fe2 SS |
4198 | emit_insn (gen_macho_high (target, operands[1])); |
4199 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
4200 | return; | |
4201 | } | |
4202 | ||
fb4d4348 GK |
4203 | emit_insn (gen_elf_high (target, operands[1])); |
4204 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
4205 | return; | |
4206 | } | |
4207 | ||
a9098fd0 GK |
4208 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
4209 | and we have put it in the TOC, we just need to make a TOC-relative | |
4210 | reference to it. */ | |
4211 | if (TARGET_TOC | |
4212 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 4213 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
4214 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
4215 | get_pool_mode (operands[1]))) | |
fb4d4348 | 4216 | { |
a9098fd0 | 4217 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 4218 | } |
a9098fd0 GK |
4219 | else if (mode == Pmode |
4220 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
4221 | && ((GET_CODE (operands[1]) != CONST_INT |
4222 | && ! easy_fp_constant (operands[1], mode)) | |
4223 | || (GET_CODE (operands[1]) == CONST_INT | |
4224 | && num_insns_constant (operands[1], mode) > 2) | |
4225 | || (GET_CODE (operands[0]) == REG | |
4226 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 4227 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
4228 | && ! legitimate_constant_pool_address_p (operands[1]) |
4229 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
4230 | { |
4231 | /* Emit a USE operation so that the constant isn't deleted if | |
4232 | expensive optimizations are turned on because nobody | |
4233 | references it. This should only be done for operands that | |
4234 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
4235 | This should not be done for operands that contain LABEL_REFs. | |
4236 | For now, we just handle the obvious case. */ | |
4237 | if (GET_CODE (operands[1]) != LABEL_REF) | |
4238 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
4239 | ||
c859cda6 | 4240 | #if TARGET_MACHO |
ee890fe2 | 4241 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 4242 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 4243 | { |
ee890fe2 SS |
4244 | operands[1] = |
4245 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
4246 | operands[0]); |
4247 | if (operands[0] != operands[1]) | |
4248 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
4249 | return; |
4250 | } | |
c859cda6 | 4251 | #endif |
ee890fe2 | 4252 | |
fb4d4348 GK |
4253 | /* If we are to limit the number of things we put in the TOC and |
4254 | this is a symbol plus a constant we can add in one insn, | |
4255 | just put the symbol in the TOC and add the constant. Don't do | |
4256 | this if reload is in progress. */ | |
4257 | if (GET_CODE (operands[1]) == CONST | |
4258 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
4259 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 4260 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
4261 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
4262 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
4263 | && ! side_effects_p (operands[0])) | |
4264 | { | |
a4f6c312 SS |
4265 | rtx sym = |
4266 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
4267 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
4268 | ||
a9098fd0 GK |
4269 | sym = force_reg (mode, sym); |
4270 | if (mode == SImode) | |
4271 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
4272 | else | |
4273 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
4274 | return; |
4275 | } | |
4276 | ||
a9098fd0 | 4277 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
4278 | |
4279 | if (TARGET_TOC | |
4d588c14 | 4280 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
4281 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
4282 | get_pool_constant (XEXP (operands[1], 0)), | |
4283 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 4284 | { |
ba4828e0 RK |
4285 | operands[1] |
4286 | = gen_rtx_MEM (mode, | |
4287 | create_TOC_reference (XEXP (operands[1], 0))); | |
4288 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 4289 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 4290 | } |
fb4d4348 GK |
4291 | } |
4292 | break; | |
a9098fd0 | 4293 | |
fb4d4348 | 4294 | case TImode: |
76d2b81d DJ |
4295 | rs6000_eliminate_indexed_memrefs (operands); |
4296 | ||
27dc0551 DE |
4297 | if (TARGET_POWER) |
4298 | { | |
4299 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
4300 | gen_rtvec (2, | |
4301 | gen_rtx_SET (VOIDmode, | |
4302 | operands[0], operands[1]), | |
4303 | gen_rtx_CLOBBER (VOIDmode, | |
4304 | gen_rtx_SCRATCH (SImode))))); | |
4305 | return; | |
4306 | } | |
fb4d4348 GK |
4307 | break; |
4308 | ||
4309 | default: | |
4310 | abort (); | |
4311 | } | |
4312 | ||
a9098fd0 GK |
4313 | /* Above, we may have called force_const_mem which may have returned |
4314 | an invalid address. If we can, fix this up; otherwise, reload will | |
4315 | have to deal with it. */ | |
8f4e6caf RH |
4316 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
4317 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 4318 | |
8f4e6caf | 4319 | emit_set: |
fb4d4348 GK |
4320 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
4321 | } | |
4697a36c | 4322 | \f |
2858f73a GK |
4323 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
4324 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
4325 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
4326 | && (CUM)->fregno <= FP_ARG_MAX_REG \ | |
4327 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
4328 | ||
4329 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
4330 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
4331 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
4332 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
4333 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 4334 | && (NAMED)) |
2858f73a | 4335 | |
c6e8c921 GK |
4336 | /* Return a nonzero value to say to return the function value in |
4337 | memory, just as large structures are always returned. TYPE will be | |
4338 | the data type of the value, and FNTYPE will be the type of the | |
4339 | function doing the returning, or @code{NULL} for libcalls. | |
4340 | ||
4341 | The AIX ABI for the RS/6000 specifies that all structures are | |
4342 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
4343 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
4344 | draft put them in memory, and GCC used to implement the draft | |
4345 | instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET | |
4346 | controls this instead of DEFAULT_ABI; V.4 targets needing backward | |
4347 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
4348 | default, and -m switches get the final word. See | |
4349 | rs6000_override_options for more details. | |
4350 | ||
4351 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
4352 | long double support is enabled. These values are returned in memory. | |
4353 | ||
4354 | int_size_in_bytes returns -1 for variable size objects, which go in | |
4355 | memory always. The cast to unsigned makes -1 > 8. */ | |
4356 | ||
4357 | static bool | |
4358 | rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
4359 | { | |
4360 | if (AGGREGATE_TYPE_P (type) | |
4361 | && (TARGET_AIX_STRUCT_RET | |
4362 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) | |
4363 | return true; | |
4364 | if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode) | |
4365 | return true; | |
4366 | return false; | |
4367 | } | |
4368 | ||
4697a36c MM |
4369 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
4370 | for a call to a function whose data type is FNTYPE. | |
4371 | For a library call, FNTYPE is 0. | |
4372 | ||
4373 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 4374 | so we never return a PARALLEL. */ |
4697a36c MM |
4375 | |
4376 | void | |
a2369ed3 | 4377 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
4378 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
4379 | int libcall, int n_named_args) | |
4697a36c MM |
4380 | { |
4381 | static CUMULATIVE_ARGS zero_cumulative; | |
4382 | ||
4383 | *cum = zero_cumulative; | |
4384 | cum->words = 0; | |
4385 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 4386 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 4387 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
4388 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
4389 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 4390 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
4391 | cum->stdarg = fntype |
4392 | && (TYPE_ARG_TYPES (fntype) != 0 | |
4393 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
4394 | != void_type_node)); | |
4697a36c | 4395 | |
0f6937fe AM |
4396 | cum->nargs_prototype = 0; |
4397 | if (incoming || cum->prototype) | |
4398 | cum->nargs_prototype = n_named_args; | |
4697a36c | 4399 | |
a5c76ee6 ZW |
4400 | /* Check for a longcall attribute. */ |
4401 | if (fntype | |
4402 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
4403 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
4404 | cum->call_cookie = CALL_LONG; |
4405 | ||
4697a36c MM |
4406 | if (TARGET_DEBUG_ARG) |
4407 | { | |
4408 | fprintf (stderr, "\ninit_cumulative_args:"); | |
4409 | if (fntype) | |
4410 | { | |
4411 | tree ret_type = TREE_TYPE (fntype); | |
4412 | fprintf (stderr, " ret code = %s,", | |
4413 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
4414 | } | |
4415 | ||
6a4cee5f MM |
4416 | if (cum->call_cookie & CALL_LONG) |
4417 | fprintf (stderr, " longcall,"); | |
4418 | ||
4697a36c MM |
4419 | fprintf (stderr, " proto = %d, nargs = %d\n", |
4420 | cum->prototype, cum->nargs_prototype); | |
4421 | } | |
6d0ef01e HP |
4422 | |
4423 | if (fntype | |
4424 | && !TARGET_ALTIVEC | |
4425 | && TARGET_ALTIVEC_ABI | |
4426 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) | |
4427 | { | |
4428 | error ("Cannot return value in vector register because" | |
4429 | " altivec instructions are disabled, use -maltivec" | |
4430 | " to enable them."); | |
4431 | } | |
4697a36c MM |
4432 | } |
4433 | \f | |
c229cba9 DE |
4434 | /* If defined, a C expression which determines whether, and in which |
4435 | direction, to pad out an argument with extra space. The value | |
4436 | should be of type `enum direction': either `upward' to pad above | |
4437 | the argument, `downward' to pad below, or `none' to inhibit | |
4438 | padding. | |
4439 | ||
4440 | For the AIX ABI structs are always stored left shifted in their | |
4441 | argument slot. */ | |
4442 | ||
9ebbca7d | 4443 | enum direction |
a2369ed3 | 4444 | function_arg_padding (enum machine_mode mode, tree type) |
c229cba9 | 4445 | { |
6e985040 AM |
4446 | #ifndef AGGREGATE_PADDING_FIXED |
4447 | #define AGGREGATE_PADDING_FIXED 0 | |
4448 | #endif | |
4449 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
4450 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
4451 | #endif | |
4452 | ||
4453 | if (!AGGREGATE_PADDING_FIXED) | |
4454 | { | |
4455 | /* GCC used to pass structures of the same size as integer types as | |
4456 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
4457 | ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were | |
4458 | passed padded downward, except that -mstrict-align further | |
4459 | muddied the water in that multi-component structures of 2 and 4 | |
4460 | bytes in size were passed padded upward. | |
4461 | ||
4462 | The following arranges for best compatibility with previous | |
4463 | versions of gcc, but removes the -mstrict-align dependency. */ | |
4464 | if (BYTES_BIG_ENDIAN) | |
4465 | { | |
4466 | HOST_WIDE_INT size = 0; | |
4467 | ||
4468 | if (mode == BLKmode) | |
4469 | { | |
4470 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
4471 | size = int_size_in_bytes (type); | |
4472 | } | |
4473 | else | |
4474 | size = GET_MODE_SIZE (mode); | |
4475 | ||
4476 | if (size == 1 || size == 2 || size == 4) | |
4477 | return downward; | |
4478 | } | |
4479 | return upward; | |
4480 | } | |
4481 | ||
4482 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
4483 | { | |
4484 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
4485 | return upward; | |
4486 | } | |
c229cba9 | 4487 | |
d3704c46 KH |
4488 | /* Fall back to the default. */ |
4489 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
4490 | } |
4491 | ||
b6c9286a MM |
4492 | /* If defined, a C expression that gives the alignment boundary, in bits, |
4493 | of an argument with the specified mode and type. If it is not defined, | |
4494 | PARM_BOUNDARY is used for all arguments. | |
4495 | ||
2310f99a | 4496 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
4497 | |
4498 | int | |
a2369ed3 | 4499 | function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED) |
b6c9286a | 4500 | { |
4ed78545 AM |
4501 | if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8) |
4502 | return 64; | |
4503 | else if (SPE_VECTOR_MODE (mode)) | |
e1f83b4d | 4504 | return 64; |
b2d04ecf | 4505 | else if (ALTIVEC_VECTOR_MODE (mode)) |
0ac081f6 | 4506 | return 128; |
9ebbca7d | 4507 | else |
b6c9286a | 4508 | return PARM_BOUNDARY; |
b6c9286a | 4509 | } |
c53bdcf5 AM |
4510 | |
4511 | /* Compute the size (in words) of a function argument. */ | |
4512 | ||
4513 | static unsigned long | |
4514 | rs6000_arg_size (enum machine_mode mode, tree type) | |
4515 | { | |
4516 | unsigned long size; | |
4517 | ||
4518 | if (mode != BLKmode) | |
4519 | size = GET_MODE_SIZE (mode); | |
4520 | else | |
4521 | size = int_size_in_bytes (type); | |
4522 | ||
4523 | if (TARGET_32BIT) | |
4524 | return (size + 3) >> 2; | |
4525 | else | |
4526 | return (size + 7) >> 3; | |
4527 | } | |
b6c9286a | 4528 | \f |
4697a36c MM |
4529 | /* Update the data in CUM to advance over an argument |
4530 | of mode MODE and data type TYPE. | |
b2d04ecf AM |
4531 | (TYPE is null for libcalls where that information may not be available.) |
4532 | ||
4533 | Note that for args passed by reference, function_arg will be called | |
4534 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4535 | itself. */ | |
4697a36c MM |
4536 | |
4537 | void | |
a2369ed3 DJ |
4538 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4539 | tree type, int named) | |
4697a36c MM |
4540 | { |
4541 | cum->nargs_prototype--; | |
4542 | ||
0ac081f6 AH |
4543 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
4544 | { | |
4ed78545 AM |
4545 | bool stack = false; |
4546 | ||
2858f73a | 4547 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
6d0ef01e HP |
4548 | { |
4549 | cum->vregno++; | |
4550 | if (!TARGET_ALTIVEC) | |
4551 | error ("Cannot pass argument in vector register because" | |
4552 | " altivec instructions are disabled, use -maltivec" | |
4553 | " to enable them."); | |
4ed78545 AM |
4554 | |
4555 | /* PowerPC64 Linux and AIX allocate GPRs for a vector argument | |
4556 | even if it is going to be passed in a vector register. | |
4557 | Darwin does the same for variable-argument functions. */ | |
4558 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4559 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
4560 | stack = true; | |
6d0ef01e | 4561 | } |
4ed78545 AM |
4562 | else |
4563 | stack = true; | |
4564 | ||
4565 | if (stack) | |
c72d6c26 | 4566 | { |
a594a19c GK |
4567 | int align; |
4568 | ||
2858f73a GK |
4569 | /* Vector parameters must be 16-byte aligned. This places |
4570 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
4571 | the parameter save area starts at offset 24 from the | |
4572 | stack. In 64-bit mode, they just have to start on an | |
4573 | even word, since the parameter save area is 16-byte | |
4574 | aligned. Space for GPRs is reserved even if the argument | |
4575 | will be passed in memory. */ | |
4576 | if (TARGET_32BIT) | |
4ed78545 | 4577 | align = (2 - cum->words) & 3; |
2858f73a GK |
4578 | else |
4579 | align = cum->words & 1; | |
c53bdcf5 | 4580 | cum->words += align + rs6000_arg_size (mode, type); |
2858f73a | 4581 | |
a594a19c GK |
4582 | if (TARGET_DEBUG_ARG) |
4583 | { | |
4584 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", | |
4585 | cum->words, align); | |
4586 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
2858f73a GK |
4587 | cum->nargs_prototype, cum->prototype, |
4588 | GET_MODE_NAME (mode)); | |
a594a19c GK |
4589 | } |
4590 | } | |
0ac081f6 | 4591 | } |
a4b0320c | 4592 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
4593 | && !cum->stdarg |
4594 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 4595 | cum->sysv_gregno++; |
f607bc57 | 4596 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4597 | { |
a3170dc6 | 4598 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 4599 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 4600 | { |
4cc833b7 RH |
4601 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
4602 | cum->fregno++; | |
4603 | else | |
4604 | { | |
4605 | if (mode == DFmode) | |
4606 | cum->words += cum->words & 1; | |
c53bdcf5 | 4607 | cum->words += rs6000_arg_size (mode, type); |
4cc833b7 | 4608 | } |
4697a36c | 4609 | } |
4cc833b7 RH |
4610 | else |
4611 | { | |
b2d04ecf | 4612 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4613 | int gregno = cum->sysv_gregno; |
4614 | ||
4ed78545 AM |
4615 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4616 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4617 | as complex int due to a historical mistake. */ | |
4618 | if (n_words == 2) | |
4619 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4620 | |
4ed78545 | 4621 | /* Multi-reg args are not split between registers and stack. */ |
4cc833b7 RH |
4622 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
4623 | { | |
4ed78545 AM |
4624 | /* Long long and SPE vectors are aligned on the stack. |
4625 | So are other 2 word items such as complex int due to | |
4626 | a historical mistake. */ | |
4cc833b7 RH |
4627 | if (n_words == 2) |
4628 | cum->words += cum->words & 1; | |
4629 | cum->words += n_words; | |
4630 | } | |
4697a36c | 4631 | |
4cc833b7 RH |
4632 | /* Note: continuing to accumulate gregno past when we've started |
4633 | spilling to the stack indicates the fact that we've started | |
4634 | spilling to the stack to expand_builtin_saveregs. */ | |
4635 | cum->sysv_gregno = gregno + n_words; | |
4636 | } | |
4697a36c | 4637 | |
4cc833b7 RH |
4638 | if (TARGET_DEBUG_ARG) |
4639 | { | |
4640 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4641 | cum->words, cum->fregno); | |
4642 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
4643 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
4644 | fprintf (stderr, "mode = %4s, named = %d\n", | |
4645 | GET_MODE_NAME (mode), named); | |
4646 | } | |
4697a36c MM |
4647 | } |
4648 | else | |
4cc833b7 | 4649 | { |
b2d04ecf AM |
4650 | int n_words = rs6000_arg_size (mode, type); |
4651 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; | |
a4f6c312 | 4652 | |
b2d04ecf AM |
4653 | /* The simple alignment calculation here works because |
4654 | function_arg_boundary / PARM_BOUNDARY will only be 1 or 2. | |
4655 | If we ever want to handle alignments larger than 8 bytes for | |
4656 | 32-bit or 16 bytes for 64-bit, then we'll need to take into | |
4657 | account the offset to the start of the parm save area. */ | |
4658 | align &= cum->words; | |
4659 | cum->words += align + n_words; | |
4697a36c | 4660 | |
a3170dc6 AH |
4661 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
4662 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
c53bdcf5 | 4663 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; |
4cc833b7 RH |
4664 | |
4665 | if (TARGET_DEBUG_ARG) | |
4666 | { | |
4667 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4668 | cum->words, cum->fregno); | |
4669 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
4670 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
4671 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
4672 | } | |
4673 | } | |
4697a36c | 4674 | } |
a6c9bed4 AH |
4675 | |
4676 | /* Determine where to put a SIMD argument on the SPE. */ | |
b78d48dd | 4677 | |
a6c9bed4 | 4678 | static rtx |
a2369ed3 DJ |
4679 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4680 | tree type) | |
a6c9bed4 AH |
4681 | { |
4682 | if (cum->stdarg) | |
4683 | { | |
4684 | int gregno = cum->sysv_gregno; | |
c53bdcf5 | 4685 | int n_words = rs6000_arg_size (mode, type); |
a6c9bed4 AH |
4686 | |
4687 | /* SPE vectors are put in odd registers. */ | |
4688 | if (n_words == 2 && (gregno & 1) == 0) | |
4689 | gregno += 1; | |
4690 | ||
4691 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
4692 | { | |
4693 | rtx r1, r2; | |
4694 | enum machine_mode m = SImode; | |
4695 | ||
4696 | r1 = gen_rtx_REG (m, gregno); | |
4697 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
4698 | r2 = gen_rtx_REG (m, gregno + 1); | |
4699 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
4700 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
4701 | } | |
4702 | else | |
b78d48dd | 4703 | return NULL_RTX; |
a6c9bed4 AH |
4704 | } |
4705 | else | |
4706 | { | |
4707 | if (cum->sysv_gregno <= GP_ARG_MAX_REG) | |
4708 | return gen_rtx_REG (mode, cum->sysv_gregno); | |
4709 | else | |
b78d48dd | 4710 | return NULL_RTX; |
a6c9bed4 AH |
4711 | } |
4712 | } | |
4713 | ||
b78d48dd FJ |
4714 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
4715 | ||
4716 | static rtx | |
ec6376ab | 4717 | rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) |
b78d48dd | 4718 | { |
ec6376ab AM |
4719 | int n_units; |
4720 | int i, k; | |
4721 | rtx rvec[GP_ARG_NUM_REG + 1]; | |
4722 | ||
4723 | if (align_words >= GP_ARG_NUM_REG) | |
4724 | return NULL_RTX; | |
4725 | ||
4726 | n_units = rs6000_arg_size (mode, type); | |
4727 | ||
4728 | /* Optimize the simple case where the arg fits in one gpr, except in | |
4729 | the case of BLKmode due to assign_parms assuming that registers are | |
4730 | BITS_PER_WORD wide. */ | |
4731 | if (n_units == 0 | |
4732 | || (n_units == 1 && mode != BLKmode)) | |
4733 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4734 | ||
4735 | k = 0; | |
4736 | if (align_words + n_units > GP_ARG_NUM_REG) | |
4737 | /* Not all of the arg fits in gprs. Say that it goes in memory too, | |
4738 | using a magic NULL_RTX component. | |
4739 | FIXME: This is not strictly correct. Only some of the arg | |
4740 | belongs in memory, not all of it. However, there isn't any way | |
4741 | to do this currently, apart from building rtx descriptions for | |
4742 | the pieces of memory we want stored. Due to bugs in the generic | |
4743 | code we can't use the normal function_arg_partial_nregs scheme | |
4744 | with the PARALLEL arg description we emit here. | |
4745 | In any case, the code to store the whole arg to memory is often | |
4746 | more efficient than code to store pieces, and we know that space | |
4747 | is available in the right place for the whole arg. */ | |
4748 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4749 | ||
4750 | i = 0; | |
4751 | do | |
36a454e1 | 4752 | { |
ec6376ab AM |
4753 | rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); |
4754 | rtx off = GEN_INT (i++ * 4); | |
4755 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
36a454e1 | 4756 | } |
ec6376ab AM |
4757 | while (++align_words < GP_ARG_NUM_REG && --n_units != 0); |
4758 | ||
4759 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
b78d48dd FJ |
4760 | } |
4761 | ||
4697a36c MM |
4762 | /* Determine where to put an argument to a function. |
4763 | Value is zero to push the argument on the stack, | |
4764 | or a hard register in which to store the argument. | |
4765 | ||
4766 | MODE is the argument's machine mode. | |
4767 | TYPE is the data type of the argument (as a tree). | |
4768 | This is null for libcalls where that information may | |
4769 | not be available. | |
4770 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4771 | the preceding args and about the function being called. | |
4772 | NAMED is nonzero if this argument is a named parameter | |
4773 | (otherwise it is an extra parameter matching an ellipsis). | |
4774 | ||
4775 | On RS/6000 the first eight words of non-FP are normally in registers | |
4776 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
4777 | Under V.4, the first 8 FP args are in registers. | |
4778 | ||
4779 | If this is floating-point and no prototype is specified, we use | |
4780 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 4781 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 4782 | so we can pass the FP value just in one register. emit_library_function |
b2d04ecf AM |
4783 | doesn't support PARALLEL anyway. |
4784 | ||
4785 | Note that for args passed by reference, function_arg will be called | |
4786 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4787 | itself. */ | |
4697a36c MM |
4788 | |
4789 | struct rtx_def * | |
a2369ed3 DJ |
4790 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4791 | tree type, int named) | |
4697a36c | 4792 | { |
4cc833b7 | 4793 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 4794 | |
a4f6c312 SS |
4795 | /* Return a marker to indicate whether CR1 needs to set or clear the |
4796 | bit that V.4 uses to say fp args were passed in registers. | |
4797 | Assume that we don't need the marker for software floating point, | |
4798 | or compiler generated library calls. */ | |
4697a36c MM |
4799 | if (mode == VOIDmode) |
4800 | { | |
f607bc57 | 4801 | if (abi == ABI_V4 |
7509c759 | 4802 | && cum->nargs_prototype < 0 |
b9599e46 FS |
4803 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
4804 | && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
7509c759 | 4805 | { |
a3170dc6 AH |
4806 | /* For the SPE, we need to crxor CR6 always. */ |
4807 | if (TARGET_SPE_ABI) | |
4808 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
4809 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
4810 | return GEN_INT (cum->call_cookie | |
4811 | | ((cum->fregno == FP_ARG_MIN_REG) | |
4812 | ? CALL_V4_SET_FP_ARGS | |
4813 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 4814 | } |
4697a36c | 4815 | |
7509c759 | 4816 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
4817 | } |
4818 | ||
2858f73a | 4819 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
4820 | if (TARGET_64BIT && ! cum->prototype) |
4821 | { | |
4822 | /* Vector parameters get passed in vector register | |
4823 | and also in GPRs or memory, in absence of prototype. */ | |
4824 | int align_words; | |
4825 | rtx slot; | |
4826 | align_words = (cum->words + 1) & ~1; | |
4827 | ||
4828 | if (align_words >= GP_ARG_NUM_REG) | |
4829 | { | |
4830 | slot = NULL_RTX; | |
4831 | } | |
4832 | else | |
4833 | { | |
4834 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4835 | } | |
4836 | return gen_rtx_PARALLEL (mode, | |
4837 | gen_rtvec (2, | |
4838 | gen_rtx_EXPR_LIST (VOIDmode, | |
4839 | slot, const0_rtx), | |
4840 | gen_rtx_EXPR_LIST (VOIDmode, | |
4841 | gen_rtx_REG (mode, cum->vregno), | |
4842 | const0_rtx))); | |
4843 | } | |
4844 | else | |
4845 | return gen_rtx_REG (mode, cum->vregno); | |
2858f73a | 4846 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
0ac081f6 | 4847 | { |
2858f73a | 4848 | if (named || abi == ABI_V4) |
a594a19c | 4849 | return NULL_RTX; |
0ac081f6 | 4850 | else |
a594a19c GK |
4851 | { |
4852 | /* Vector parameters to varargs functions under AIX or Darwin | |
4853 | get passed in memory and possibly also in GPRs. */ | |
ec6376ab AM |
4854 | int align, align_words, n_words; |
4855 | enum machine_mode part_mode; | |
a594a19c GK |
4856 | |
4857 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
4858 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
4859 | save area starts at offset 24 from the stack. In 64-bit mode, | |
4860 | they just have to start on an even word, since the parameter | |
4861 | save area is 16-byte aligned. */ | |
4862 | if (TARGET_32BIT) | |
4ed78545 | 4863 | align = (2 - cum->words) & 3; |
2858f73a GK |
4864 | else |
4865 | align = cum->words & 1; | |
a594a19c GK |
4866 | align_words = cum->words + align; |
4867 | ||
4868 | /* Out of registers? Memory, then. */ | |
4869 | if (align_words >= GP_ARG_NUM_REG) | |
4870 | return NULL_RTX; | |
ec6376ab AM |
4871 | |
4872 | if (TARGET_32BIT && TARGET_POWERPC64) | |
4873 | return rs6000_mixed_function_arg (mode, type, align_words); | |
4874 | ||
2858f73a GK |
4875 | /* The vector value goes in GPRs. Only the part of the |
4876 | value in GPRs is reported here. */ | |
ec6376ab AM |
4877 | part_mode = mode; |
4878 | n_words = rs6000_arg_size (mode, type); | |
4879 | if (align_words + n_words > GP_ARG_NUM_REG) | |
839a4992 | 4880 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
4881 | is either wholly in GPRs or half in GPRs and half not. */ |
4882 | part_mode = DImode; | |
ec6376ab AM |
4883 | |
4884 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 4885 | } |
0ac081f6 | 4886 | } |
a6c9bed4 AH |
4887 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
4888 | return rs6000_spe_function_arg (cum, mode, type); | |
f607bc57 | 4889 | else if (abi == ABI_V4) |
4697a36c | 4890 | { |
a3170dc6 | 4891 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
4892 | && (mode == SFmode || mode == DFmode)) |
4893 | { | |
4894 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
4895 | return gen_rtx_REG (mode, cum->fregno); | |
4896 | else | |
b78d48dd | 4897 | return NULL_RTX; |
4cc833b7 RH |
4898 | } |
4899 | else | |
4900 | { | |
b2d04ecf | 4901 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4902 | int gregno = cum->sysv_gregno; |
4903 | ||
4ed78545 AM |
4904 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4905 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4906 | as complex int due to a historical mistake. */ | |
4907 | if (n_words == 2) | |
4908 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4909 | |
4ed78545 | 4910 | /* Multi-reg args are not split between registers and stack. */ |
ec6376ab | 4911 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
b78d48dd | 4912 | return NULL_RTX; |
ec6376ab AM |
4913 | |
4914 | if (TARGET_32BIT && TARGET_POWERPC64) | |
4915 | return rs6000_mixed_function_arg (mode, type, | |
4916 | gregno - GP_ARG_MIN_REG); | |
4917 | return gen_rtx_REG (mode, gregno); | |
4cc833b7 | 4918 | } |
4697a36c | 4919 | } |
4cc833b7 RH |
4920 | else |
4921 | { | |
b2d04ecf AM |
4922 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
4923 | int align_words = cum->words + (cum->words & align); | |
b78d48dd | 4924 | |
2858f73a | 4925 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 | 4926 | { |
ec6376ab AM |
4927 | rtx rvec[GP_ARG_NUM_REG + 1]; |
4928 | rtx r; | |
4929 | int k; | |
c53bdcf5 AM |
4930 | bool needs_psave; |
4931 | enum machine_mode fmode = mode; | |
c53bdcf5 AM |
4932 | unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; |
4933 | ||
4934 | if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) | |
4935 | { | |
c53bdcf5 AM |
4936 | /* Currently, we only ever need one reg here because complex |
4937 | doubles are split. */ | |
ec6376ab | 4938 | if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode) |
c53bdcf5 | 4939 | abort (); |
ec6376ab AM |
4940 | |
4941 | /* Long double split over regs and memory. */ | |
4942 | fmode = DFmode; | |
c53bdcf5 | 4943 | } |
c53bdcf5 AM |
4944 | |
4945 | /* Do we also need to pass this arg in the parameter save | |
4946 | area? */ | |
4947 | needs_psave = (type | |
4948 | && (cum->nargs_prototype <= 0 | |
4949 | || (DEFAULT_ABI == ABI_AIX | |
4950 | && TARGET_XL_CALL | |
4951 | && align_words >= GP_ARG_NUM_REG))); | |
4952 | ||
4953 | if (!needs_psave && mode == fmode) | |
ec6376ab | 4954 | return gen_rtx_REG (fmode, cum->fregno); |
c53bdcf5 | 4955 | |
ec6376ab | 4956 | k = 0; |
c53bdcf5 AM |
4957 | if (needs_psave) |
4958 | { | |
ec6376ab | 4959 | /* Describe the part that goes in gprs or the stack. |
c53bdcf5 | 4960 | This piece must come first, before the fprs. */ |
c53bdcf5 AM |
4961 | if (align_words < GP_ARG_NUM_REG) |
4962 | { | |
4963 | unsigned long n_words = rs6000_arg_size (mode, type); | |
ec6376ab AM |
4964 | |
4965 | if (align_words + n_words > GP_ARG_NUM_REG | |
4966 | || (TARGET_32BIT && TARGET_POWERPC64)) | |
4967 | { | |
4968 | /* If this is partially on the stack, then we only | |
4969 | include the portion actually in registers here. */ | |
4970 | enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; | |
4971 | rtx off; | |
4972 | do | |
4973 | { | |
4974 | r = gen_rtx_REG (rmode, | |
4975 | GP_ARG_MIN_REG + align_words); | |
4976 | off = GEN_INT (k * GET_MODE_SIZE (rmode)); | |
4977 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
4978 | } | |
4979 | while (++align_words < GP_ARG_NUM_REG && --n_words != 0); | |
4980 | } | |
4981 | else | |
4982 | { | |
4983 | /* The whole arg fits in gprs. */ | |
4984 | r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4985 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
4986 | } | |
c53bdcf5 | 4987 | } |
ec6376ab AM |
4988 | else |
4989 | /* It's entirely in memory. */ | |
4990 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
c53bdcf5 AM |
4991 | } |
4992 | ||
ec6376ab AM |
4993 | /* Describe where this piece goes in the fprs. */ |
4994 | r = gen_rtx_REG (fmode, cum->fregno); | |
4995 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
4996 | ||
4997 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
4cc833b7 RH |
4998 | } |
4999 | else if (align_words < GP_ARG_NUM_REG) | |
b2d04ecf | 5000 | { |
ec6376ab AM |
5001 | if (TARGET_32BIT && TARGET_POWERPC64) |
5002 | return rs6000_mixed_function_arg (mode, type, align_words); | |
b2d04ecf AM |
5003 | |
5004 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5005 | } | |
4cc833b7 RH |
5006 | else |
5007 | return NULL_RTX; | |
4697a36c | 5008 | } |
4697a36c MM |
5009 | } |
5010 | \f | |
ec6376ab AM |
5011 | /* For an arg passed partly in registers and partly in memory, this is |
5012 | the number of registers used. For args passed entirely in registers | |
5013 | or entirely in memory, zero. When an arg is described by a PARALLEL, | |
5014 | perhaps using more than one register type, this function returns the | |
5015 | number of registers used by the first element of the PARALLEL. */ | |
4697a36c MM |
5016 | |
5017 | int | |
a2369ed3 | 5018 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
2858f73a | 5019 | tree type, int named) |
4697a36c | 5020 | { |
c53bdcf5 | 5021 | int ret = 0; |
ec6376ab AM |
5022 | int align; |
5023 | int parm_offset; | |
5024 | int align_words; | |
c53bdcf5 | 5025 | |
f607bc57 | 5026 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 5027 | return 0; |
4697a36c | 5028 | |
c53bdcf5 AM |
5029 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) |
5030 | && cum->nargs_prototype >= 0) | |
5031 | return 0; | |
5032 | ||
ec6376ab AM |
5033 | align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
5034 | parm_offset = TARGET_32BIT ? 2 : 0; | |
5035 | align_words = cum->words + ((parm_offset - cum->words) & align); | |
5036 | ||
5037 | if (USE_FP_FOR_ARG_P (cum, mode, type) | |
5038 | /* If we are passing this arg in gprs as well, then this function | |
5039 | should return the number of gprs (or memory) partially passed, | |
5040 | *not* the number of fprs. */ | |
5041 | && !(type | |
5042 | && (cum->nargs_prototype <= 0 | |
5043 | || (DEFAULT_ABI == ABI_AIX | |
5044 | && TARGET_XL_CALL | |
5045 | && align_words >= GP_ARG_NUM_REG)))) | |
4697a36c | 5046 | { |
c53bdcf5 | 5047 | if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1) |
ec6376ab | 5048 | ret = FP_ARG_MAX_REG + 1 - cum->fregno; |
c53bdcf5 | 5049 | else if (cum->nargs_prototype >= 0) |
4697a36c MM |
5050 | return 0; |
5051 | } | |
5052 | ||
ec6376ab AM |
5053 | if (align_words < GP_ARG_NUM_REG |
5054 | && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) | |
5055 | ret = GP_ARG_NUM_REG - align_words; | |
4697a36c | 5056 | |
c53bdcf5 AM |
5057 | if (ret != 0 && TARGET_DEBUG_ARG) |
5058 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
4697a36c | 5059 | |
c53bdcf5 | 5060 | return ret; |
4697a36c MM |
5061 | } |
5062 | \f | |
5063 | /* A C expression that indicates when an argument must be passed by | |
5064 | reference. If nonzero for an argument, a copy of that argument is | |
5065 | made in memory and a pointer to the argument is passed instead of | |
5066 | the argument itself. The pointer is passed in whatever way is | |
5067 | appropriate for passing a pointer to that type. | |
5068 | ||
b2d04ecf AM |
5069 | Under V.4, aggregates and long double are passed by reference. |
5070 | ||
5071 | As an extension to all 32-bit ABIs, AltiVec vectors are passed by | |
5072 | reference unless the AltiVec vector extension ABI is in force. | |
c8c99a68 DE |
5073 | |
5074 | As an extension to all ABIs, variable sized types are passed by | |
5075 | reference. */ | |
4697a36c MM |
5076 | |
5077 | int | |
a2369ed3 DJ |
5078 | function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
5079 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
d779d0dc | 5080 | tree type, int named ATTRIBUTE_UNUSED) |
4697a36c | 5081 | { |
b2d04ecf AM |
5082 | if ((DEFAULT_ABI == ABI_V4 |
5083 | && ((type && AGGREGATE_TYPE_P (type)) | |
5084 | || mode == TFmode)) | |
5085 | || (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
5086 | || (type && int_size_in_bytes (type) < 0)) | |
4697a36c MM |
5087 | { |
5088 | if (TARGET_DEBUG_ARG) | |
b2d04ecf | 5089 | fprintf (stderr, "function_arg_pass_by_reference\n"); |
4697a36c MM |
5090 | |
5091 | return 1; | |
5092 | } | |
b2d04ecf | 5093 | return 0; |
4697a36c | 5094 | } |
5985c7a6 FJ |
5095 | |
5096 | static void | |
2d9db8eb | 5097 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
5098 | { |
5099 | int i; | |
5100 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
5101 | ||
5102 | if (nregs == 0) | |
5103 | return; | |
5104 | ||
5105 | for (i = 0; i < nregs; i++) | |
5106 | { | |
5107 | rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode)); | |
5108 | if (reload_completed) | |
5109 | { | |
5110 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
5111 | tem = NULL_RTX; | |
5112 | else | |
5113 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
5114 | i * GET_MODE_SIZE(reg_mode)); | |
5115 | } | |
5116 | else | |
5117 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
5118 | ||
5119 | if (tem == NULL_RTX) | |
5120 | abort (); | |
5121 | ||
5122 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
5123 | } | |
5124 | } | |
5125 | ||
4697a36c MM |
5126 | \f |
5127 | /* Perform any needed actions needed for a function that is receiving a | |
5128 | variable number of arguments. | |
5129 | ||
5130 | CUM is as above. | |
5131 | ||
5132 | MODE and TYPE are the mode and type of the current parameter. | |
5133 | ||
5134 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
5135 | that must be pushed by the prolog to pretend that our caller pushed | |
5136 | it. | |
5137 | ||
5138 | Normally, this macro will push all remaining incoming registers on the | |
5139 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
5140 | ||
c6e8c921 | 5141 | static void |
a2369ed3 DJ |
5142 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
5143 | tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl) | |
4697a36c | 5144 | { |
4cc833b7 RH |
5145 | CUMULATIVE_ARGS next_cum; |
5146 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 5147 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 5148 | int first_reg_offset, set; |
4697a36c | 5149 | |
f31bf321 | 5150 | /* Skip the last named argument. */ |
d34c5b80 | 5151 | next_cum = *cum; |
f31bf321 | 5152 | function_arg_advance (&next_cum, mode, type, 1); |
4cc833b7 | 5153 | |
f607bc57 | 5154 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 5155 | { |
4cc833b7 | 5156 | /* Indicate to allocate space on the stack for varargs save area. */ |
00dba523 | 5157 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 5158 | if (! no_rtl) |
2c4974b7 | 5159 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 5160 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
5161 | |
5162 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 5163 | } |
60e2d0ca | 5164 | else |
4697a36c | 5165 | { |
d34c5b80 | 5166 | first_reg_offset = next_cum.words; |
4cc833b7 | 5167 | save_area = virtual_incoming_args_rtx; |
00dba523 | 5168 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
5169 | |
5170 | if (MUST_PASS_IN_STACK (mode, type)) | |
c53bdcf5 | 5171 | first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); |
4cc833b7 | 5172 | } |
4697a36c | 5173 | |
dfafc897 | 5174 | set = get_varargs_alias_set (); |
c81fc13e | 5175 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 5176 | { |
dfafc897 FS |
5177 | mem = gen_rtx_MEM (BLKmode, |
5178 | plus_constant (save_area, | |
5179 | first_reg_offset * reg_size)), | |
ba4828e0 | 5180 | set_mem_alias_set (mem, set); |
8ac61af7 | 5181 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 5182 | |
5985c7a6 FJ |
5183 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
5184 | GP_ARG_NUM_REG - first_reg_offset); | |
4697a36c MM |
5185 | } |
5186 | ||
4697a36c | 5187 | /* Save FP registers if needed. */ |
f607bc57 | 5188 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
5189 | && TARGET_HARD_FLOAT && TARGET_FPRS |
5190 | && ! no_rtl | |
4cc833b7 | 5191 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 5192 | { |
4cc833b7 | 5193 | int fregno = next_cum.fregno; |
9ebbca7d | 5194 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
5195 | rtx lab = gen_label_rtx (); |
5196 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 5197 | |
4cc833b7 | 5198 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 5199 | pc_rtx, |
39403d82 | 5200 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
5201 | gen_rtx_NE (VOIDmode, cr1, |
5202 | const0_rtx), | |
39403d82 | 5203 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
5204 | pc_rtx))); |
5205 | ||
4cc833b7 RH |
5206 | while (fregno <= FP_ARG_V4_MAX_REG) |
5207 | { | |
dfafc897 | 5208 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 5209 | set_mem_alias_set (mem, set); |
dfafc897 | 5210 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
5211 | fregno++; |
5212 | off += 8; | |
4697a36c | 5213 | } |
4cc833b7 RH |
5214 | |
5215 | emit_label (lab); | |
4697a36c | 5216 | } |
4697a36c | 5217 | } |
4697a36c | 5218 | |
dfafc897 | 5219 | /* Create the va_list data type. */ |
2c4974b7 | 5220 | |
c35d187f RH |
5221 | static tree |
5222 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 5223 | { |
64c2816f | 5224 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 5225 | |
9ebbca7d GK |
5226 | /* For AIX, prefer 'char *' because that's what the system |
5227 | header files like. */ | |
f607bc57 | 5228 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 5229 | return build_pointer_type (char_type_node); |
dfafc897 | 5230 | |
f1e639b1 | 5231 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 5232 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 5233 | |
9ebbca7d GK |
5234 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
5235 | unsigned_char_type_node); | |
5236 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
5237 | unsigned_char_type_node); | |
64c2816f DT |
5238 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
5239 | every user file. */ | |
5240 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
5241 | short_unsigned_type_node); | |
dfafc897 FS |
5242 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
5243 | ptr_type_node); | |
5244 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
5245 | ptr_type_node); | |
5246 | ||
5247 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
5248 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 5249 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
5250 | DECL_FIELD_CONTEXT (f_ovf) = record; |
5251 | DECL_FIELD_CONTEXT (f_sav) = record; | |
5252 | ||
bab45a51 FS |
5253 | TREE_CHAIN (record) = type_decl; |
5254 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
5255 | TYPE_FIELDS (record) = f_gpr; |
5256 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
5257 | TREE_CHAIN (f_fpr) = f_res; |
5258 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
5259 | TREE_CHAIN (f_ovf) = f_sav; |
5260 | ||
5261 | layout_type (record); | |
5262 | ||
5263 | /* The correct type is an array type of one element. */ | |
5264 | return build_array_type (record, build_index_type (size_zero_node)); | |
5265 | } | |
5266 | ||
5267 | /* Implement va_start. */ | |
5268 | ||
5269 | void | |
a2369ed3 | 5270 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 5271 | { |
dfafc897 | 5272 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 5273 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 5274 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 5275 | |
dfafc897 | 5276 | /* Only SVR4 needs something special. */ |
f607bc57 | 5277 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 5278 | { |
e5faf155 | 5279 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
5280 | return; |
5281 | } | |
5282 | ||
973a648b | 5283 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 5284 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
5285 | f_res = TREE_CHAIN (f_fpr); |
5286 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
5287 | f_sav = TREE_CHAIN (f_ovf); |
5288 | ||
8ebecc3b | 5289 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
44de5aeb RK |
5290 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5291 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5292 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5293 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
dfafc897 FS |
5294 | |
5295 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 5296 | words = current_function_args_info.words; |
dfafc897 FS |
5297 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
5298 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
5299 | ||
5300 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
5301 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
5302 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
5303 | words, n_gpr, n_fpr); | |
dfafc897 FS |
5304 | |
5305 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
5306 | TREE_SIDE_EFFECTS (t) = 1; | |
5307 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5308 | ||
5309 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
5310 | TREE_SIDE_EFFECTS (t) = 1; | |
5311 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5312 | ||
5313 | /* Find the overflow area. */ | |
5314 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
5315 | if (words != 0) | |
5316 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
5317 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
5318 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
5319 | TREE_SIDE_EFFECTS (t) = 1; | |
5320 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5321 | ||
5322 | /* Find the register save area. */ | |
5323 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
5324 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
5325 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
5326 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
5327 | TREE_SIDE_EFFECTS (t) = 1; | |
5328 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5329 | } | |
5330 | ||
5331 | /* Implement va_arg. */ | |
5332 | ||
23a60a04 JM |
5333 | tree |
5334 | rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) | |
cd3ce9b4 | 5335 | { |
cd3ce9b4 JM |
5336 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
5337 | tree gpr, fpr, ovf, sav, reg, t, u; | |
5338 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
5339 | tree lab_false, lab_over, addr; | |
5340 | int align; | |
5341 | tree ptrtype = build_pointer_type (type); | |
5342 | ||
5343 | if (DEFAULT_ABI != ABI_V4) | |
5344 | { | |
5345 | /* Variable sized types are passed by reference, as are AltiVec | |
5346 | vectors when 32-bit and not using the AltiVec ABI extension. */ | |
5347 | if (int_size_in_bytes (type) < 0 | |
5348 | || (TARGET_32BIT | |
5349 | && !TARGET_ALTIVEC_ABI | |
5350 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))) | |
5351 | { | |
5352 | /* Args grow upward. */ | |
5353 | t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
5354 | build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0)); | |
5355 | t = build1 (NOP_EXPR, build_pointer_type (ptrtype), t); | |
5356 | t = build_fold_indirect_ref (t); | |
23a60a04 | 5357 | return build_fold_indirect_ref (t); |
cd3ce9b4 JM |
5358 | } |
5359 | if (targetm.calls.split_complex_arg | |
5360 | && TREE_CODE (type) == COMPLEX_TYPE) | |
5361 | { | |
5362 | tree elem_type = TREE_TYPE (type); | |
5363 | enum machine_mode elem_mode = TYPE_MODE (elem_type); | |
5364 | int elem_size = GET_MODE_SIZE (elem_mode); | |
5365 | ||
5366 | if (elem_size < UNITS_PER_WORD) | |
5367 | { | |
23a60a04 | 5368 | tree real_part, imag_part; |
cd3ce9b4 JM |
5369 | tree post = NULL_TREE; |
5370 | ||
23a60a04 JM |
5371 | real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5372 | &post); | |
5373 | /* Copy the value into a temporary, lest the formal temporary | |
5374 | be reused out from under us. */ | |
5375 | real_part = get_initialized_tmp_var (real_part, pre_p, &post); | |
cd3ce9b4 JM |
5376 | append_to_statement_list (post, pre_p); |
5377 | ||
23a60a04 JM |
5378 | imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5379 | post_p); | |
cd3ce9b4 | 5380 | |
23a60a04 | 5381 | return build (COMPLEX_EXPR, type, real_part, imag_part); |
cd3ce9b4 JM |
5382 | } |
5383 | } | |
5384 | ||
23a60a04 | 5385 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 JM |
5386 | } |
5387 | ||
5388 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
5389 | f_fpr = TREE_CHAIN (f_gpr); | |
5390 | f_res = TREE_CHAIN (f_fpr); | |
5391 | f_ovf = TREE_CHAIN (f_res); | |
5392 | f_sav = TREE_CHAIN (f_ovf); | |
5393 | ||
5394 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); | |
44de5aeb RK |
5395 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5396 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5397 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5398 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
cd3ce9b4 JM |
5399 | |
5400 | size = int_size_in_bytes (type); | |
5401 | rsize = (size + 3) / 4; | |
5402 | align = 1; | |
5403 | ||
5404 | if (AGGREGATE_TYPE_P (type) | |
5405 | || TYPE_MODE (type) == TFmode | |
5406 | || (!TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))) | |
5407 | { | |
5408 | /* Aggregates, long doubles, and AltiVec vectors are passed by | |
5409 | reference. */ | |
5410 | indirect_p = 1; | |
5411 | reg = gpr; | |
5412 | n_reg = 1; | |
5413 | sav_ofs = 0; | |
5414 | sav_scale = 4; | |
5415 | size = 4; | |
5416 | rsize = 1; | |
5417 | } | |
5418 | else if (TARGET_HARD_FLOAT && TARGET_FPRS | |
5419 | && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode)) | |
5420 | { | |
5421 | /* FP args go in FP registers, if present. */ | |
5422 | indirect_p = 0; | |
5423 | reg = fpr; | |
5424 | n_reg = 1; | |
5425 | sav_ofs = 8*4; | |
5426 | sav_scale = 8; | |
5427 | if (TYPE_MODE (type) == DFmode) | |
5428 | align = 8; | |
5429 | } | |
5430 | else | |
5431 | { | |
5432 | /* Otherwise into GP registers. */ | |
5433 | indirect_p = 0; | |
5434 | reg = gpr; | |
5435 | n_reg = rsize; | |
5436 | sav_ofs = 0; | |
5437 | sav_scale = 4; | |
5438 | if (n_reg == 2) | |
5439 | align = 8; | |
5440 | } | |
5441 | ||
5442 | /* Pull the value out of the saved registers.... */ | |
5443 | ||
5444 | lab_over = NULL; | |
5445 | addr = create_tmp_var (ptr_type_node, "addr"); | |
5446 | DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); | |
5447 | ||
5448 | /* AltiVec vectors never go in registers when -mabi=altivec. */ | |
5449 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
5450 | align = 16; | |
5451 | else | |
5452 | { | |
5453 | lab_false = create_artificial_label (); | |
5454 | lab_over = create_artificial_label (); | |
5455 | ||
5456 | /* Long long and SPE vectors are aligned in the registers. | |
5457 | As are any other 2 gpr item such as complex int due to a | |
5458 | historical mistake. */ | |
5459 | u = reg; | |
5460 | if (n_reg == 2) | |
5461 | { | |
5462 | u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
5463 | build_int_2 (n_reg - 1, 0)); | |
5464 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u); | |
5465 | } | |
5466 | ||
5467 | t = build_int_2 (8 - n_reg + 1, 0); | |
5468 | TREE_TYPE (t) = TREE_TYPE (reg); | |
5469 | t = build2 (GE_EXPR, boolean_type_node, u, t); | |
5470 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
5471 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
5472 | gimplify_and_add (t, pre_p); | |
5473 | ||
5474 | t = sav; | |
5475 | if (sav_ofs) | |
5476 | t = build2 (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
5477 | ||
5478 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, | |
5479 | build_int_2 (n_reg, 0)); | |
5480 | u = build1 (CONVERT_EXPR, integer_type_node, u); | |
5481 | u = build2 (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); | |
5482 | t = build2 (PLUS_EXPR, ptr_type_node, t, u); | |
5483 | ||
5484 | t = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5485 | gimplify_and_add (t, pre_p); | |
5486 | ||
5487 | t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
5488 | gimplify_and_add (t, pre_p); | |
5489 | ||
5490 | t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
5491 | append_to_statement_list (t, pre_p); | |
5492 | ||
5493 | if (n_reg > 2) | |
5494 | { | |
5495 | /* Ensure that we don't find any more args in regs. | |
5496 | Alignment has taken care of the n_reg == 2 case. */ | |
5497 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
5498 | gimplify_and_add (t, pre_p); | |
5499 | } | |
5500 | } | |
5501 | ||
5502 | /* ... otherwise out of the overflow area. */ | |
5503 | ||
5504 | /* Care for on-stack alignment if needed. */ | |
5505 | t = ovf; | |
5506 | if (align != 1) | |
5507 | { | |
5508 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (align - 1, 0)); | |
5509 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1)); | |
5510 | } | |
5511 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
5512 | ||
5513 | u = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5514 | gimplify_and_add (u, pre_p); | |
5515 | ||
5516 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
5517 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
5518 | gimplify_and_add (t, pre_p); | |
5519 | ||
5520 | if (lab_over) | |
5521 | { | |
5522 | t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
5523 | append_to_statement_list (t, pre_p); | |
5524 | } | |
5525 | ||
5526 | if (indirect_p) | |
5527 | { | |
23a60a04 | 5528 | addr = fold_convert (build_pointer_type (ptrtype), addr); |
cd3ce9b4 JM |
5529 | addr = build_fold_indirect_ref (addr); |
5530 | } | |
5531 | else | |
23a60a04 | 5532 | addr = fold_convert (ptrtype, addr); |
cd3ce9b4 | 5533 | |
23a60a04 | 5534 | return build_fold_indirect_ref (addr); |
cd3ce9b4 JM |
5535 | } |
5536 | ||
0ac081f6 AH |
5537 | /* Builtins. */ |
5538 | ||
6a2dd09a RS |
5539 | #define def_builtin(MASK, NAME, TYPE, CODE) \ |
5540 | do { \ | |
5541 | if ((MASK) & target_flags) \ | |
5542 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ | |
5543 | NULL, NULL_TREE); \ | |
0ac081f6 AH |
5544 | } while (0) |
5545 | ||
24408032 AH |
5546 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
5547 | ||
2212663f | 5548 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
5549 | { |
5550 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
5551 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
5552 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
5553 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
5554 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
5555 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
5556 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
5557 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
5558 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
5559 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
5560 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, | |
5561 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, | |
5562 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
5563 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
5564 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
5565 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
5566 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
5567 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
5568 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
5569 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
5570 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
5571 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
5572 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
5573 | }; | |
2212663f | 5574 | |
95385cbb AH |
5575 | /* DST operations: void foo (void *, const int, const char). */ |
5576 | ||
5577 | static const struct builtin_description bdesc_dst[] = | |
5578 | { | |
5579 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
5580 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
5581 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
5582 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
5583 | }; | |
5584 | ||
2212663f | 5585 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 5586 | |
a3170dc6 | 5587 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 5588 | { |
f18c054f DB |
5589 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
5590 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
5591 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
5592 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
5593 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
5594 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
5595 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
5596 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
5597 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
5598 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
5599 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 5600 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
5601 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
5602 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
5603 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
5604 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
5605 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
5606 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
5607 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
5608 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
5609 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
5610 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
5611 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
5612 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
5613 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
5614 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
5615 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
5616 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
5617 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
5618 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
5619 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
5620 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
5621 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
5622 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
5623 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
5624 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
5625 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
5626 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
5627 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
5628 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
5629 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
5630 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
5631 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
5632 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
5633 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
5634 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
5635 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
5636 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
5637 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
5638 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
5639 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
5640 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
5641 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
5642 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
5643 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
5644 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
5645 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
5646 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
5647 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
5648 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
5649 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
5650 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
5651 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
5652 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
5653 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 5654 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
5655 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
5656 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
5657 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
5658 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
5659 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
5660 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
5661 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
5662 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
5663 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
5664 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
5665 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
5666 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
5667 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
5668 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
5669 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
5670 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
5671 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
5672 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
5673 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
5674 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
5675 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
5676 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 5677 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
5678 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
5679 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
5680 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
5681 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
5682 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
5683 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
5684 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
5685 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
5686 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
5687 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
5688 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
5689 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
5690 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
5691 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
5692 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
5693 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
5694 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
5695 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
5696 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
5697 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
5698 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
5699 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
5700 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 5701 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 AH |
5702 | |
5703 | /* Place holder, leave as first spe builtin. */ | |
5704 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
5705 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
5706 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
5707 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
5708 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
5709 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
5710 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
5711 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
5712 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
5713 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
5714 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
5715 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
5716 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
5717 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
5718 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
5719 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
5720 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
5721 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
5722 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
5723 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
5724 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
5725 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
5726 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
5727 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
5728 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
5729 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
5730 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
5731 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
5732 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
5733 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
5734 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
5735 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
5736 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
5737 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
5738 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
5739 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
5740 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
5741 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
5742 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
5743 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
5744 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
5745 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
5746 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
5747 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
5748 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
5749 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
5750 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
5751 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
5752 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
5753 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
5754 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
5755 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
5756 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
5757 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
5758 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
5759 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
5760 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
5761 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
5762 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
5763 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
5764 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
5765 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
5766 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
5767 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
5768 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
5769 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
5770 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
5771 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
5772 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
5773 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
5774 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
5775 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
5776 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
5777 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
5778 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
5779 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
5780 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
5781 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
5782 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
5783 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
5784 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
5785 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
5786 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
5787 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
5788 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
5789 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
5790 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
5791 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
5792 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
5793 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
5794 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
5795 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
5796 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
5797 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
5798 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
5799 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
5800 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
5801 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
5802 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
5803 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
5804 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
5805 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
5806 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
5807 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
5808 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
5809 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
5810 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
5811 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
5812 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
5813 | ||
5814 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
5815 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
5816 | ||
5817 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
5818 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
5819 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
5820 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
5821 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
5822 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
5823 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
5824 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
5825 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
5826 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
5827 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
5828 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
5829 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
5830 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
5831 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
5832 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
5833 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
5834 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
5835 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
5836 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
5837 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
5838 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
5839 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
5840 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
5841 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
5842 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
5843 | ||
5844 | /* Place-holder. Leave as last binary SPE builtin. */ | |
17edbda5 | 5845 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, |
ae4b4a02 AH |
5846 | }; |
5847 | ||
5848 | /* AltiVec predicates. */ | |
5849 | ||
5850 | struct builtin_description_predicates | |
5851 | { | |
5852 | const unsigned int mask; | |
5853 | const enum insn_code icode; | |
5854 | const char *opcode; | |
5855 | const char *const name; | |
5856 | const enum rs6000_builtins code; | |
5857 | }; | |
5858 | ||
5859 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
5860 | { | |
5861 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
5862 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
5863 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
5864 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
5865 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
5866 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
5867 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
5868 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
5869 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
5870 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
5871 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
5872 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
5873 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 5874 | }; |
24408032 | 5875 | |
a3170dc6 AH |
5876 | /* SPE predicates. */ |
5877 | static struct builtin_description bdesc_spe_predicates[] = | |
5878 | { | |
5879 | /* Place-holder. Leave as first. */ | |
5880 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
5881 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
5882 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
5883 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
5884 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
5885 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
5886 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
5887 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
5888 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
5889 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
5890 | /* Place-holder. Leave as last. */ | |
5891 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
5892 | }; | |
5893 | ||
5894 | /* SPE evsel predicates. */ | |
5895 | static struct builtin_description bdesc_spe_evsel[] = | |
5896 | { | |
5897 | /* Place-holder. Leave as first. */ | |
5898 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
5899 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
5900 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
5901 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
5902 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
5903 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
5904 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
5905 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
5906 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
5907 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
5908 | /* Place-holder. Leave as last. */ | |
5909 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
5910 | }; | |
5911 | ||
b6d08ca1 | 5912 | /* ABS* operations. */ |
100c4561 AH |
5913 | |
5914 | static const struct builtin_description bdesc_abs[] = | |
5915 | { | |
5916 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
5917 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
5918 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
5919 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
5920 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
5921 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
5922 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
5923 | }; | |
5924 | ||
617e0e1d DB |
5925 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
5926 | foo (VECa). */ | |
24408032 | 5927 | |
a3170dc6 | 5928 | static struct builtin_description bdesc_1arg[] = |
2212663f | 5929 | { |
617e0e1d DB |
5930 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
5931 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
5932 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
5933 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
5934 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
5935 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
5936 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
5937 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
5938 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
5939 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
5940 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
5941 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
5942 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
5943 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
5944 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
5945 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
5946 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 AH |
5947 | |
5948 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and | |
5949 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
5950 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
5951 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
5952 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
5953 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
5954 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
5955 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
5956 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
5957 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
5958 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
5959 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
5960 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
5961 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
5962 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
5963 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
5964 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
5965 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
5966 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
5967 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
5968 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
5969 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
5970 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
5971 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
5972 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
6a599451 | 5973 | { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, |
a3170dc6 AH |
5974 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, |
5975 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
5976 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
5977 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
5978 | |
5979 | /* Place-holder. Leave as last unary SPE builtin. */ | |
5980 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, | |
2212663f DB |
5981 | }; |
5982 | ||
5983 | static rtx | |
a2369ed3 | 5984 | rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
5985 | { |
5986 | rtx pat; | |
5987 | tree arg0 = TREE_VALUE (arglist); | |
5988 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5989 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5990 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5991 | ||
0559cc77 DE |
5992 | if (icode == CODE_FOR_nothing) |
5993 | /* Builtin not supported on this processor. */ | |
5994 | return 0; | |
5995 | ||
20e26713 AH |
5996 | /* If we got invalid arguments bail out before generating bad rtl. */ |
5997 | if (arg0 == error_mark_node) | |
9a171fcd | 5998 | return const0_rtx; |
20e26713 | 5999 | |
0559cc77 DE |
6000 | if (icode == CODE_FOR_altivec_vspltisb |
6001 | || icode == CODE_FOR_altivec_vspltish | |
6002 | || icode == CODE_FOR_altivec_vspltisw | |
6003 | || icode == CODE_FOR_spe_evsplatfi | |
6004 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
6005 | { |
6006 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 AH |
6007 | if (GET_CODE (op0) != CONST_INT |
6008 | || INTVAL (op0) > 0x1f | |
6009 | || INTVAL (op0) < -0x1f) | |
6010 | { | |
6011 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 6012 | return const0_rtx; |
b44140e7 | 6013 | } |
b44140e7 AH |
6014 | } |
6015 | ||
c62f2db5 | 6016 | if (target == 0 |
2212663f DB |
6017 | || GET_MODE (target) != tmode |
6018 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6019 | target = gen_reg_rtx (tmode); | |
6020 | ||
6021 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6022 | op0 = copy_to_mode_reg (mode0, op0); | |
6023 | ||
6024 | pat = GEN_FCN (icode) (target, op0); | |
6025 | if (! pat) | |
6026 | return 0; | |
6027 | emit_insn (pat); | |
0ac081f6 | 6028 | |
2212663f DB |
6029 | return target; |
6030 | } | |
ae4b4a02 | 6031 | |
100c4561 | 6032 | static rtx |
a2369ed3 | 6033 | altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) |
100c4561 AH |
6034 | { |
6035 | rtx pat, scratch1, scratch2; | |
6036 | tree arg0 = TREE_VALUE (arglist); | |
6037 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6038 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6039 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6040 | ||
6041 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6042 | if (arg0 == error_mark_node) | |
9a171fcd | 6043 | return const0_rtx; |
100c4561 AH |
6044 | |
6045 | if (target == 0 | |
6046 | || GET_MODE (target) != tmode | |
6047 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6048 | target = gen_reg_rtx (tmode); | |
6049 | ||
6050 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6051 | op0 = copy_to_mode_reg (mode0, op0); | |
6052 | ||
6053 | scratch1 = gen_reg_rtx (mode0); | |
6054 | scratch2 = gen_reg_rtx (mode0); | |
6055 | ||
6056 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
6057 | if (! pat) | |
6058 | return 0; | |
6059 | emit_insn (pat); | |
6060 | ||
6061 | return target; | |
6062 | } | |
6063 | ||
0ac081f6 | 6064 | static rtx |
a2369ed3 | 6065 | rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
0ac081f6 AH |
6066 | { |
6067 | rtx pat; | |
6068 | tree arg0 = TREE_VALUE (arglist); | |
6069 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6070 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6071 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6072 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6073 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6074 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6075 | ||
0559cc77 DE |
6076 | if (icode == CODE_FOR_nothing) |
6077 | /* Builtin not supported on this processor. */ | |
6078 | return 0; | |
6079 | ||
20e26713 AH |
6080 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6081 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6082 | return const0_rtx; |
20e26713 | 6083 | |
0559cc77 DE |
6084 | if (icode == CODE_FOR_altivec_vcfux |
6085 | || icode == CODE_FOR_altivec_vcfsx | |
6086 | || icode == CODE_FOR_altivec_vctsxs | |
6087 | || icode == CODE_FOR_altivec_vctuxs | |
6088 | || icode == CODE_FOR_altivec_vspltb | |
6089 | || icode == CODE_FOR_altivec_vsplth | |
6090 | || icode == CODE_FOR_altivec_vspltw | |
6091 | || icode == CODE_FOR_spe_evaddiw | |
6092 | || icode == CODE_FOR_spe_evldd | |
6093 | || icode == CODE_FOR_spe_evldh | |
6094 | || icode == CODE_FOR_spe_evldw | |
6095 | || icode == CODE_FOR_spe_evlhhesplat | |
6096 | || icode == CODE_FOR_spe_evlhhossplat | |
6097 | || icode == CODE_FOR_spe_evlhhousplat | |
6098 | || icode == CODE_FOR_spe_evlwhe | |
6099 | || icode == CODE_FOR_spe_evlwhos | |
6100 | || icode == CODE_FOR_spe_evlwhou | |
6101 | || icode == CODE_FOR_spe_evlwhsplat | |
6102 | || icode == CODE_FOR_spe_evlwwsplat | |
6103 | || icode == CODE_FOR_spe_evrlwi | |
6104 | || icode == CODE_FOR_spe_evslwi | |
6105 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 6106 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 6107 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
6108 | { |
6109 | /* Only allow 5-bit unsigned literals. */ | |
8bb418a3 | 6110 | STRIP_NOPS (arg1); |
b44140e7 AH |
6111 | if (TREE_CODE (arg1) != INTEGER_CST |
6112 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6113 | { | |
6114 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 6115 | return const0_rtx; |
b44140e7 | 6116 | } |
b44140e7 AH |
6117 | } |
6118 | ||
c62f2db5 | 6119 | if (target == 0 |
0ac081f6 AH |
6120 | || GET_MODE (target) != tmode |
6121 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6122 | target = gen_reg_rtx (tmode); | |
6123 | ||
6124 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6125 | op0 = copy_to_mode_reg (mode0, op0); | |
6126 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6127 | op1 = copy_to_mode_reg (mode1, op1); | |
6128 | ||
6129 | pat = GEN_FCN (icode) (target, op0, op1); | |
6130 | if (! pat) | |
6131 | return 0; | |
6132 | emit_insn (pat); | |
6133 | ||
6134 | return target; | |
6135 | } | |
6525c0e7 | 6136 | |
ae4b4a02 | 6137 | static rtx |
a2369ed3 DJ |
6138 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
6139 | tree arglist, rtx target) | |
ae4b4a02 AH |
6140 | { |
6141 | rtx pat, scratch; | |
6142 | tree cr6_form = TREE_VALUE (arglist); | |
6143 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6144 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6145 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6146 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6147 | enum machine_mode tmode = SImode; | |
6148 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6149 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6150 | int cr6_form_int; | |
6151 | ||
6152 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
6153 | { | |
6154 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 6155 | return const0_rtx; |
ae4b4a02 AH |
6156 | } |
6157 | else | |
6158 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
6159 | ||
6160 | if (mode0 != mode1) | |
6161 | abort (); | |
6162 | ||
6163 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6164 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6165 | return const0_rtx; |
ae4b4a02 AH |
6166 | |
6167 | if (target == 0 | |
6168 | || GET_MODE (target) != tmode | |
6169 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6170 | target = gen_reg_rtx (tmode); | |
6171 | ||
6172 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6173 | op0 = copy_to_mode_reg (mode0, op0); | |
6174 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6175 | op1 = copy_to_mode_reg (mode1, op1); | |
6176 | ||
6177 | scratch = gen_reg_rtx (mode0); | |
6178 | ||
6179 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 6180 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
6181 | if (! pat) |
6182 | return 0; | |
6183 | emit_insn (pat); | |
6184 | ||
6185 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
6186 | different operations, but the bits in CR6 will be different | |
6187 | depending on what information we want. So we have to play tricks | |
6188 | with CR6 to get the right bits out. | |
6189 | ||
6190 | If you think this is disgusting, look at the specs for the | |
6191 | AltiVec predicates. */ | |
6192 | ||
6193 | switch (cr6_form_int) | |
6194 | { | |
6195 | case 0: | |
6196 | emit_insn (gen_cr6_test_for_zero (target)); | |
6197 | break; | |
6198 | case 1: | |
6199 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
6200 | break; | |
6201 | case 2: | |
6202 | emit_insn (gen_cr6_test_for_lt (target)); | |
6203 | break; | |
6204 | case 3: | |
6205 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
6206 | break; | |
6207 | default: | |
6208 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
6209 | break; | |
6210 | } | |
6211 | ||
6212 | return target; | |
6213 | } | |
6214 | ||
b4a62fa0 | 6215 | static rtx |
38f391a5 | 6216 | altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) |
b4a62fa0 SB |
6217 | { |
6218 | rtx pat, addr; | |
6219 | tree arg0 = TREE_VALUE (arglist); | |
6220 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6221 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6222 | enum machine_mode mode0 = Pmode; | |
6223 | enum machine_mode mode1 = Pmode; | |
6224 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6225 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6226 | ||
6227 | if (icode == CODE_FOR_nothing) | |
6228 | /* Builtin not supported on this processor. */ | |
6229 | return 0; | |
6230 | ||
6231 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6232 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6233 | return const0_rtx; | |
6234 | ||
6235 | if (target == 0 | |
6236 | || GET_MODE (target) != tmode | |
6237 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6238 | target = gen_reg_rtx (tmode); | |
6239 | ||
6240 | op1 = copy_to_mode_reg (mode1, op1); | |
6241 | ||
6242 | if (op0 == const0_rtx) | |
6243 | { | |
6244 | addr = gen_rtx_MEM (tmode, op1); | |
6245 | } | |
6246 | else | |
6247 | { | |
6248 | op0 = copy_to_mode_reg (mode0, op0); | |
6249 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
6250 | } | |
6251 | ||
6252 | pat = GEN_FCN (icode) (target, addr); | |
6253 | ||
6254 | if (! pat) | |
6255 | return 0; | |
6256 | emit_insn (pat); | |
6257 | ||
6258 | return target; | |
6259 | } | |
6260 | ||
61bea3b0 AH |
6261 | static rtx |
6262 | spe_expand_stv_builtin (enum insn_code icode, tree arglist) | |
6263 | { | |
6264 | tree arg0 = TREE_VALUE (arglist); | |
6265 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6266 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6267 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6268 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6269 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6270 | rtx pat; | |
6271 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
6272 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
6273 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
6274 | ||
6275 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6276 | if (arg0 == error_mark_node | |
6277 | || arg1 == error_mark_node | |
6278 | || arg2 == error_mark_node) | |
6279 | return const0_rtx; | |
6280 | ||
6281 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
6282 | op0 = copy_to_mode_reg (mode2, op0); | |
6283 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
6284 | op1 = copy_to_mode_reg (mode0, op1); | |
6285 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6286 | op2 = copy_to_mode_reg (mode1, op2); | |
6287 | ||
6288 | pat = GEN_FCN (icode) (op1, op2, op0); | |
6289 | if (pat) | |
6290 | emit_insn (pat); | |
6291 | return NULL_RTX; | |
6292 | } | |
6293 | ||
6525c0e7 | 6294 | static rtx |
a2369ed3 | 6295 | altivec_expand_stv_builtin (enum insn_code icode, tree arglist) |
6525c0e7 AH |
6296 | { |
6297 | tree arg0 = TREE_VALUE (arglist); | |
6298 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6299 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6300 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6301 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6302 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
b4a62fa0 SB |
6303 | rtx pat, addr; |
6304 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6305 | enum machine_mode mode1 = Pmode; | |
6306 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
6307 | |
6308 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6309 | if (arg0 == error_mark_node | |
6310 | || arg1 == error_mark_node | |
6311 | || arg2 == error_mark_node) | |
9a171fcd | 6312 | return const0_rtx; |
6525c0e7 | 6313 | |
b4a62fa0 SB |
6314 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
6315 | op0 = copy_to_mode_reg (tmode, op0); | |
6316 | ||
6317 | op2 = copy_to_mode_reg (mode2, op2); | |
6318 | ||
6319 | if (op1 == const0_rtx) | |
6320 | { | |
6321 | addr = gen_rtx_MEM (tmode, op2); | |
6322 | } | |
6323 | else | |
6324 | { | |
6325 | op1 = copy_to_mode_reg (mode1, op1); | |
6326 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
6327 | } | |
6525c0e7 | 6328 | |
b4a62fa0 | 6329 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
6330 | if (pat) |
6331 | emit_insn (pat); | |
6332 | return NULL_RTX; | |
6333 | } | |
6334 | ||
2212663f | 6335 | static rtx |
a2369ed3 | 6336 | rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6337 | { |
6338 | rtx pat; | |
6339 | tree arg0 = TREE_VALUE (arglist); | |
6340 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6341 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6342 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6343 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6344 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6345 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6346 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6347 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6348 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 6349 | |
774b5662 DE |
6350 | if (icode == CODE_FOR_nothing) |
6351 | /* Builtin not supported on this processor. */ | |
6352 | return 0; | |
6353 | ||
20e26713 AH |
6354 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6355 | if (arg0 == error_mark_node | |
6356 | || arg1 == error_mark_node | |
6357 | || arg2 == error_mark_node) | |
9a171fcd | 6358 | return const0_rtx; |
20e26713 | 6359 | |
774b5662 DE |
6360 | if (icode == CODE_FOR_altivec_vsldoi_4sf |
6361 | || icode == CODE_FOR_altivec_vsldoi_4si | |
6362 | || icode == CODE_FOR_altivec_vsldoi_8hi | |
6363 | || icode == CODE_FOR_altivec_vsldoi_16qi) | |
b44140e7 AH |
6364 | { |
6365 | /* Only allow 4-bit unsigned literals. */ | |
8bb418a3 | 6366 | STRIP_NOPS (arg2); |
b44140e7 AH |
6367 | if (TREE_CODE (arg2) != INTEGER_CST |
6368 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
6369 | { | |
6370 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 6371 | return const0_rtx; |
b44140e7 | 6372 | } |
b44140e7 AH |
6373 | } |
6374 | ||
c62f2db5 | 6375 | if (target == 0 |
2212663f DB |
6376 | || GET_MODE (target) != tmode |
6377 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6378 | target = gen_reg_rtx (tmode); | |
6379 | ||
6380 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6381 | op0 = copy_to_mode_reg (mode0, op0); | |
6382 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6383 | op1 = copy_to_mode_reg (mode1, op1); | |
6384 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
6385 | op2 = copy_to_mode_reg (mode2, op2); | |
6386 | ||
6387 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
6388 | if (! pat) | |
6389 | return 0; | |
6390 | emit_insn (pat); | |
6391 | ||
6392 | return target; | |
6393 | } | |
92898235 | 6394 | |
3a9b8c7e | 6395 | /* Expand the lvx builtins. */ |
0ac081f6 | 6396 | static rtx |
a2369ed3 | 6397 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 6398 | { |
0ac081f6 AH |
6399 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6400 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 6401 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
6402 | tree arg0; |
6403 | enum machine_mode tmode, mode0; | |
7c3abc73 | 6404 | rtx pat, op0; |
3a9b8c7e | 6405 | enum insn_code icode; |
92898235 | 6406 | |
0ac081f6 AH |
6407 | switch (fcode) |
6408 | { | |
f18c054f DB |
6409 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
6410 | icode = CODE_FOR_altivec_lvx_16qi; | |
3a9b8c7e | 6411 | break; |
f18c054f DB |
6412 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
6413 | icode = CODE_FOR_altivec_lvx_8hi; | |
3a9b8c7e AH |
6414 | break; |
6415 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
6416 | icode = CODE_FOR_altivec_lvx_4si; | |
6417 | break; | |
6418 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
6419 | icode = CODE_FOR_altivec_lvx_4sf; | |
6420 | break; | |
6421 | default: | |
6422 | *expandedp = false; | |
6423 | return NULL_RTX; | |
6424 | } | |
0ac081f6 | 6425 | |
3a9b8c7e | 6426 | *expandedp = true; |
f18c054f | 6427 | |
3a9b8c7e AH |
6428 | arg0 = TREE_VALUE (arglist); |
6429 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6430 | tmode = insn_data[icode].operand[0].mode; | |
6431 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 6432 | |
3a9b8c7e AH |
6433 | if (target == 0 |
6434 | || GET_MODE (target) != tmode | |
6435 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6436 | target = gen_reg_rtx (tmode); | |
24408032 | 6437 | |
3a9b8c7e AH |
6438 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
6439 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 6440 | |
3a9b8c7e AH |
6441 | pat = GEN_FCN (icode) (target, op0); |
6442 | if (! pat) | |
6443 | return 0; | |
6444 | emit_insn (pat); | |
6445 | return target; | |
6446 | } | |
f18c054f | 6447 | |
3a9b8c7e AH |
6448 | /* Expand the stvx builtins. */ |
6449 | static rtx | |
a2369ed3 DJ |
6450 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
6451 | bool *expandedp) | |
3a9b8c7e AH |
6452 | { |
6453 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6454 | tree arglist = TREE_OPERAND (exp, 1); | |
6455 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6456 | tree arg0, arg1; | |
6457 | enum machine_mode mode0, mode1; | |
7c3abc73 | 6458 | rtx pat, op0, op1; |
3a9b8c7e | 6459 | enum insn_code icode; |
f18c054f | 6460 | |
3a9b8c7e AH |
6461 | switch (fcode) |
6462 | { | |
6463 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
6464 | icode = CODE_FOR_altivec_stvx_16qi; | |
6465 | break; | |
6466 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
6467 | icode = CODE_FOR_altivec_stvx_8hi; | |
6468 | break; | |
6469 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
6470 | icode = CODE_FOR_altivec_stvx_4si; | |
6471 | break; | |
6472 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
6473 | icode = CODE_FOR_altivec_stvx_4sf; | |
6474 | break; | |
6475 | default: | |
6476 | *expandedp = false; | |
6477 | return NULL_RTX; | |
6478 | } | |
24408032 | 6479 | |
3a9b8c7e AH |
6480 | arg0 = TREE_VALUE (arglist); |
6481 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6482 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6483 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6484 | mode0 = insn_data[icode].operand[0].mode; | |
6485 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 6486 | |
3a9b8c7e AH |
6487 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6488 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
6489 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
6490 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 6491 | |
3a9b8c7e AH |
6492 | pat = GEN_FCN (icode) (op0, op1); |
6493 | if (pat) | |
6494 | emit_insn (pat); | |
f18c054f | 6495 | |
3a9b8c7e AH |
6496 | *expandedp = true; |
6497 | return NULL_RTX; | |
6498 | } | |
f18c054f | 6499 | |
3a9b8c7e AH |
6500 | /* Expand the dst builtins. */ |
6501 | static rtx | |
a2369ed3 DJ |
6502 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
6503 | bool *expandedp) | |
3a9b8c7e AH |
6504 | { |
6505 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6506 | tree arglist = TREE_OPERAND (exp, 1); | |
6507 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6508 | tree arg0, arg1, arg2; | |
6509 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 6510 | rtx pat, op0, op1, op2; |
3a9b8c7e | 6511 | struct builtin_description *d; |
a3170dc6 | 6512 | size_t i; |
f18c054f | 6513 | |
3a9b8c7e | 6514 | *expandedp = false; |
f18c054f | 6515 | |
3a9b8c7e AH |
6516 | /* Handle DST variants. */ |
6517 | d = (struct builtin_description *) bdesc_dst; | |
6518 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
6519 | if (d->code == fcode) | |
6520 | { | |
6521 | arg0 = TREE_VALUE (arglist); | |
6522 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6523 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6524 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6525 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6526 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6527 | mode0 = insn_data[d->icode].operand[0].mode; | |
6528 | mode1 = insn_data[d->icode].operand[1].mode; | |
6529 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 6530 | |
3a9b8c7e AH |
6531 | /* Invalid arguments, bail out before generating bad rtl. */ |
6532 | if (arg0 == error_mark_node | |
6533 | || arg1 == error_mark_node | |
6534 | || arg2 == error_mark_node) | |
6535 | return const0_rtx; | |
f18c054f | 6536 | |
86e7df90 | 6537 | *expandedp = true; |
8bb418a3 | 6538 | STRIP_NOPS (arg2); |
3a9b8c7e AH |
6539 | if (TREE_CODE (arg2) != INTEGER_CST |
6540 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
6541 | { | |
6542 | error ("argument to `%s' must be a 2-bit unsigned literal", d->name); | |
6543 | return const0_rtx; | |
6544 | } | |
f18c054f | 6545 | |
3a9b8c7e | 6546 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
b4a62fa0 | 6547 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); |
3a9b8c7e AH |
6548 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
6549 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 6550 | |
3a9b8c7e AH |
6551 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
6552 | if (pat != 0) | |
6553 | emit_insn (pat); | |
f18c054f | 6554 | |
3a9b8c7e AH |
6555 | return NULL_RTX; |
6556 | } | |
f18c054f | 6557 | |
3a9b8c7e AH |
6558 | return NULL_RTX; |
6559 | } | |
24408032 | 6560 | |
3a9b8c7e AH |
6561 | /* Expand the builtin in EXP and store the result in TARGET. Store |
6562 | true in *EXPANDEDP if we found a builtin to expand. */ | |
6563 | static rtx | |
a2369ed3 | 6564 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e AH |
6565 | { |
6566 | struct builtin_description *d; | |
6567 | struct builtin_description_predicates *dp; | |
6568 | size_t i; | |
6569 | enum insn_code icode; | |
6570 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6571 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
6572 | tree arg0; |
6573 | rtx op0, pat; | |
6574 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 6575 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 6576 | |
3a9b8c7e AH |
6577 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
6578 | if (*expandedp) | |
6579 | return target; | |
0ac081f6 | 6580 | |
3a9b8c7e AH |
6581 | target = altivec_expand_st_builtin (exp, target, expandedp); |
6582 | if (*expandedp) | |
6583 | return target; | |
6584 | ||
6585 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
6586 | if (*expandedp) | |
6587 | return target; | |
6588 | ||
6589 | *expandedp = true; | |
95385cbb | 6590 | |
3a9b8c7e AH |
6591 | switch (fcode) |
6592 | { | |
6525c0e7 AH |
6593 | case ALTIVEC_BUILTIN_STVX: |
6594 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
6595 | case ALTIVEC_BUILTIN_STVEBX: | |
6596 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
6597 | case ALTIVEC_BUILTIN_STVEHX: | |
6598 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
6599 | case ALTIVEC_BUILTIN_STVEWX: | |
6600 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
6601 | case ALTIVEC_BUILTIN_STVXL: | |
6602 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 6603 | |
95385cbb AH |
6604 | case ALTIVEC_BUILTIN_MFVSCR: |
6605 | icode = CODE_FOR_altivec_mfvscr; | |
6606 | tmode = insn_data[icode].operand[0].mode; | |
6607 | ||
6608 | if (target == 0 | |
6609 | || GET_MODE (target) != tmode | |
6610 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6611 | target = gen_reg_rtx (tmode); | |
6612 | ||
6613 | pat = GEN_FCN (icode) (target); | |
0ac081f6 AH |
6614 | if (! pat) |
6615 | return 0; | |
6616 | emit_insn (pat); | |
95385cbb AH |
6617 | return target; |
6618 | ||
6619 | case ALTIVEC_BUILTIN_MTVSCR: | |
6620 | icode = CODE_FOR_altivec_mtvscr; | |
6621 | arg0 = TREE_VALUE (arglist); | |
6622 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6623 | mode0 = insn_data[icode].operand[0].mode; | |
6624 | ||
6625 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6626 | if (arg0 == error_mark_node) | |
9a171fcd | 6627 | return const0_rtx; |
95385cbb AH |
6628 | |
6629 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6630 | op0 = copy_to_mode_reg (mode0, op0); | |
6631 | ||
6632 | pat = GEN_FCN (icode) (op0); | |
6633 | if (pat) | |
6634 | emit_insn (pat); | |
6635 | return NULL_RTX; | |
3a9b8c7e | 6636 | |
95385cbb AH |
6637 | case ALTIVEC_BUILTIN_DSSALL: |
6638 | emit_insn (gen_altivec_dssall ()); | |
6639 | return NULL_RTX; | |
6640 | ||
6641 | case ALTIVEC_BUILTIN_DSS: | |
6642 | icode = CODE_FOR_altivec_dss; | |
6643 | arg0 = TREE_VALUE (arglist); | |
8bb418a3 | 6644 | STRIP_NOPS (arg0); |
95385cbb AH |
6645 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
6646 | mode0 = insn_data[icode].operand[0].mode; | |
6647 | ||
6648 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6649 | if (arg0 == error_mark_node) | |
9a171fcd | 6650 | return const0_rtx; |
95385cbb | 6651 | |
b44140e7 AH |
6652 | if (TREE_CODE (arg0) != INTEGER_CST |
6653 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
6654 | { | |
6655 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 6656 | return const0_rtx; |
b44140e7 AH |
6657 | } |
6658 | ||
95385cbb AH |
6659 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6660 | op0 = copy_to_mode_reg (mode0, op0); | |
6661 | ||
6662 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 | 6663 | return NULL_RTX; |
8bb418a3 ZL |
6664 | |
6665 | case ALTIVEC_BUILTIN_COMPILETIME_ERROR: | |
6666 | arg0 = TREE_VALUE (arglist); | |
6667 | while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR) | |
6668 | arg0 = TREE_OPERAND (arg0, 0); | |
6669 | error ("invalid parameter combination for `%s' AltiVec intrinsic", | |
6670 | TREE_STRING_POINTER (arg0)); | |
6671 | ||
6672 | return const0_rtx; | |
0ac081f6 | 6673 | } |
24408032 | 6674 | |
100c4561 AH |
6675 | /* Expand abs* operations. */ |
6676 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 6677 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
6678 | if (d->code == fcode) |
6679 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
6680 | ||
ae4b4a02 AH |
6681 | /* Expand the AltiVec predicates. */ |
6682 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 6683 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 AH |
6684 | if (dp->code == fcode) |
6685 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target); | |
6686 | ||
6525c0e7 AH |
6687 | /* LV* are funky. We initialized them differently. */ |
6688 | switch (fcode) | |
6689 | { | |
6690 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 6691 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
6525c0e7 AH |
6692 | arglist, target); |
6693 | case ALTIVEC_BUILTIN_LVSR: | |
b4a62fa0 | 6694 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
92898235 | 6695 | arglist, target); |
6525c0e7 | 6696 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 6697 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
92898235 | 6698 | arglist, target); |
6525c0e7 | 6699 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 6700 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
92898235 | 6701 | arglist, target); |
6525c0e7 | 6702 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 6703 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
92898235 | 6704 | arglist, target); |
6525c0e7 | 6705 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 6706 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
92898235 | 6707 | arglist, target); |
6525c0e7 | 6708 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 6709 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
92898235 | 6710 | arglist, target); |
6525c0e7 AH |
6711 | default: |
6712 | break; | |
6713 | /* Fall through. */ | |
6714 | } | |
95385cbb | 6715 | |
92898235 | 6716 | *expandedp = false; |
0ac081f6 AH |
6717 | return NULL_RTX; |
6718 | } | |
6719 | ||
a3170dc6 AH |
6720 | /* Binops that need to be initialized manually, but can be expanded |
6721 | automagically by rs6000_expand_binop_builtin. */ | |
6722 | static struct builtin_description bdesc_2arg_spe[] = | |
6723 | { | |
6724 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
6725 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
6726 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
6727 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
6728 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
6729 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
6730 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
6731 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
6732 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
6733 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
6734 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
6735 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
6736 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
6737 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
6738 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
6739 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
6740 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
6741 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
6742 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
6743 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
6744 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
6745 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
6746 | }; | |
6747 | ||
6748 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
6749 | true in *EXPANDEDP if we found a builtin to expand. | |
6750 | ||
6751 | This expands the SPE builtins that are not simple unary and binary | |
6752 | operations. */ | |
6753 | static rtx | |
a2369ed3 | 6754 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 AH |
6755 | { |
6756 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6757 | tree arglist = TREE_OPERAND (exp, 1); | |
6758 | tree arg1, arg0; | |
6759 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6760 | enum insn_code icode; | |
6761 | enum machine_mode tmode, mode0; | |
6762 | rtx pat, op0; | |
6763 | struct builtin_description *d; | |
6764 | size_t i; | |
6765 | ||
6766 | *expandedp = true; | |
6767 | ||
6768 | /* Syntax check for a 5-bit unsigned immediate. */ | |
6769 | switch (fcode) | |
6770 | { | |
6771 | case SPE_BUILTIN_EVSTDD: | |
6772 | case SPE_BUILTIN_EVSTDH: | |
6773 | case SPE_BUILTIN_EVSTDW: | |
6774 | case SPE_BUILTIN_EVSTWHE: | |
6775 | case SPE_BUILTIN_EVSTWHO: | |
6776 | case SPE_BUILTIN_EVSTWWE: | |
6777 | case SPE_BUILTIN_EVSTWWO: | |
6778 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6779 | if (TREE_CODE (arg1) != INTEGER_CST | |
6780 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6781 | { | |
6782 | error ("argument 2 must be a 5-bit unsigned literal"); | |
6783 | return const0_rtx; | |
6784 | } | |
6785 | break; | |
6786 | default: | |
6787 | break; | |
6788 | } | |
6789 | ||
00332c9f AH |
6790 | /* The evsplat*i instructions are not quite generic. */ |
6791 | switch (fcode) | |
6792 | { | |
6793 | case SPE_BUILTIN_EVSPLATFI: | |
6794 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
6795 | arglist, target); | |
6796 | case SPE_BUILTIN_EVSPLATI: | |
6797 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
6798 | arglist, target); | |
6799 | default: | |
6800 | break; | |
6801 | } | |
6802 | ||
a3170dc6 AH |
6803 | d = (struct builtin_description *) bdesc_2arg_spe; |
6804 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
6805 | if (d->code == fcode) | |
6806 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
6807 | ||
6808 | d = (struct builtin_description *) bdesc_spe_predicates; | |
6809 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
6810 | if (d->code == fcode) | |
6811 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
6812 | ||
6813 | d = (struct builtin_description *) bdesc_spe_evsel; | |
6814 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
6815 | if (d->code == fcode) | |
6816 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
6817 | ||
6818 | switch (fcode) | |
6819 | { | |
6820 | case SPE_BUILTIN_EVSTDDX: | |
61bea3b0 | 6821 | return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); |
a3170dc6 | 6822 | case SPE_BUILTIN_EVSTDHX: |
61bea3b0 | 6823 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); |
a3170dc6 | 6824 | case SPE_BUILTIN_EVSTDWX: |
61bea3b0 | 6825 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); |
a3170dc6 | 6826 | case SPE_BUILTIN_EVSTWHEX: |
61bea3b0 | 6827 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); |
a3170dc6 | 6828 | case SPE_BUILTIN_EVSTWHOX: |
61bea3b0 | 6829 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); |
a3170dc6 | 6830 | case SPE_BUILTIN_EVSTWWEX: |
61bea3b0 | 6831 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); |
a3170dc6 | 6832 | case SPE_BUILTIN_EVSTWWOX: |
61bea3b0 | 6833 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); |
a3170dc6 | 6834 | case SPE_BUILTIN_EVSTDD: |
61bea3b0 | 6835 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); |
a3170dc6 | 6836 | case SPE_BUILTIN_EVSTDH: |
61bea3b0 | 6837 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); |
a3170dc6 | 6838 | case SPE_BUILTIN_EVSTDW: |
61bea3b0 | 6839 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); |
a3170dc6 | 6840 | case SPE_BUILTIN_EVSTWHE: |
61bea3b0 | 6841 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); |
a3170dc6 | 6842 | case SPE_BUILTIN_EVSTWHO: |
61bea3b0 | 6843 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); |
a3170dc6 | 6844 | case SPE_BUILTIN_EVSTWWE: |
61bea3b0 | 6845 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); |
a3170dc6 | 6846 | case SPE_BUILTIN_EVSTWWO: |
61bea3b0 | 6847 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); |
a3170dc6 AH |
6848 | case SPE_BUILTIN_MFSPEFSCR: |
6849 | icode = CODE_FOR_spe_mfspefscr; | |
6850 | tmode = insn_data[icode].operand[0].mode; | |
6851 | ||
6852 | if (target == 0 | |
6853 | || GET_MODE (target) != tmode | |
6854 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6855 | target = gen_reg_rtx (tmode); | |
6856 | ||
6857 | pat = GEN_FCN (icode) (target); | |
6858 | if (! pat) | |
6859 | return 0; | |
6860 | emit_insn (pat); | |
6861 | return target; | |
6862 | case SPE_BUILTIN_MTSPEFSCR: | |
6863 | icode = CODE_FOR_spe_mtspefscr; | |
6864 | arg0 = TREE_VALUE (arglist); | |
6865 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6866 | mode0 = insn_data[icode].operand[0].mode; | |
6867 | ||
6868 | if (arg0 == error_mark_node) | |
6869 | return const0_rtx; | |
6870 | ||
6871 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6872 | op0 = copy_to_mode_reg (mode0, op0); | |
6873 | ||
6874 | pat = GEN_FCN (icode) (op0); | |
6875 | if (pat) | |
6876 | emit_insn (pat); | |
6877 | return NULL_RTX; | |
6878 | default: | |
6879 | break; | |
6880 | } | |
6881 | ||
6882 | *expandedp = false; | |
6883 | return NULL_RTX; | |
6884 | } | |
6885 | ||
6886 | static rtx | |
a2369ed3 | 6887 | spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
6888 | { |
6889 | rtx pat, scratch, tmp; | |
6890 | tree form = TREE_VALUE (arglist); | |
6891 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6892 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6893 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6894 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6895 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6896 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6897 | int form_int; | |
6898 | enum rtx_code code; | |
6899 | ||
6900 | if (TREE_CODE (form) != INTEGER_CST) | |
6901 | { | |
6902 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
6903 | return const0_rtx; | |
6904 | } | |
6905 | else | |
6906 | form_int = TREE_INT_CST_LOW (form); | |
6907 | ||
6908 | if (mode0 != mode1) | |
6909 | abort (); | |
6910 | ||
6911 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6912 | return const0_rtx; | |
6913 | ||
6914 | if (target == 0 | |
6915 | || GET_MODE (target) != SImode | |
6916 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
6917 | target = gen_reg_rtx (SImode); | |
6918 | ||
6919 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6920 | op0 = copy_to_mode_reg (mode0, op0); | |
6921 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6922 | op1 = copy_to_mode_reg (mode1, op1); | |
6923 | ||
6924 | scratch = gen_reg_rtx (CCmode); | |
6925 | ||
6926 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
6927 | if (! pat) | |
6928 | return const0_rtx; | |
6929 | emit_insn (pat); | |
6930 | ||
6931 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
6932 | _lower_. We use one compare, but look in different bits of the | |
6933 | CR for each variant. | |
6934 | ||
6935 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
6936 | bits are set as follows: | |
6937 | ||
6938 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
6939 | U | L | (U | L) | (U & L) | |
6940 | ||
6941 | So, for an "all" relationship, BIT 3 would be set. | |
6942 | For an "any" relationship, BIT 2 would be set. Etc. | |
6943 | ||
6944 | Following traditional nomenclature, these bits map to: | |
6945 | ||
6946 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
6947 | LT | GT | EQ | OV | |
6948 | ||
6949 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
6950 | */ | |
6951 | ||
6952 | switch (form_int) | |
6953 | { | |
6954 | /* All variant. OV bit. */ | |
6955 | case 0: | |
6956 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
6957 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
6958 | that's ugly and will trigger a validate_condition_mode abort. | |
6959 | So let's just use another pattern. */ | |
6960 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
6961 | return target; | |
6962 | /* Any variant. EQ bit. */ | |
6963 | case 1: | |
6964 | code = EQ; | |
6965 | break; | |
6966 | /* Upper variant. LT bit. */ | |
6967 | case 2: | |
6968 | code = LT; | |
6969 | break; | |
6970 | /* Lower variant. GT bit. */ | |
6971 | case 3: | |
6972 | code = GT; | |
6973 | break; | |
6974 | default: | |
6975 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
6976 | return const0_rtx; | |
6977 | } | |
6978 | ||
6979 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
6980 | emit_move_insn (target, tmp); | |
6981 | ||
6982 | return target; | |
6983 | } | |
6984 | ||
6985 | /* The evsel builtins look like this: | |
6986 | ||
6987 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
6988 | ||
6989 | and work like this: | |
6990 | ||
6991 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
6992 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
6993 | */ | |
6994 | ||
6995 | static rtx | |
a2369ed3 | 6996 | spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
6997 | { |
6998 | rtx pat, scratch; | |
6999 | tree arg0 = TREE_VALUE (arglist); | |
7000 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7001 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7002 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
7003 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7004 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7005 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
7006 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
7007 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7008 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7009 | ||
7010 | if (mode0 != mode1) | |
7011 | abort (); | |
7012 | ||
7013 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
7014 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
7015 | return const0_rtx; | |
7016 | ||
7017 | if (target == 0 | |
7018 | || GET_MODE (target) != mode0 | |
7019 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
7020 | target = gen_reg_rtx (mode0); | |
7021 | ||
7022 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7023 | op0 = copy_to_mode_reg (mode0, op0); | |
7024 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
7025 | op1 = copy_to_mode_reg (mode0, op1); | |
7026 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
7027 | op2 = copy_to_mode_reg (mode0, op2); | |
7028 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
7029 | op3 = copy_to_mode_reg (mode0, op3); | |
7030 | ||
7031 | /* Generate the compare. */ | |
7032 | scratch = gen_reg_rtx (CCmode); | |
7033 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7034 | if (! pat) | |
7035 | return const0_rtx; | |
7036 | emit_insn (pat); | |
7037 | ||
7038 | if (mode0 == V2SImode) | |
7039 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
7040 | else | |
7041 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
7042 | ||
7043 | return target; | |
7044 | } | |
7045 | ||
0ac081f6 AH |
7046 | /* Expand an expression EXP that calls a built-in function, |
7047 | with result going to TARGET if that's convenient | |
7048 | (and in mode MODE if that's convenient). | |
7049 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
7050 | IGNORE is nonzero if the value is to be ignored. */ | |
7051 | ||
7052 | static rtx | |
a2369ed3 DJ |
7053 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
7054 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
7055 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 7056 | { |
92898235 AH |
7057 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
7058 | tree arglist = TREE_OPERAND (exp, 1); | |
7059 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7060 | struct builtin_description *d; | |
7061 | size_t i; | |
7062 | rtx ret; | |
7063 | bool success; | |
7064 | ||
0ac081f6 | 7065 | if (TARGET_ALTIVEC) |
92898235 AH |
7066 | { |
7067 | ret = altivec_expand_builtin (exp, target, &success); | |
7068 | ||
a3170dc6 AH |
7069 | if (success) |
7070 | return ret; | |
7071 | } | |
7072 | if (TARGET_SPE) | |
7073 | { | |
7074 | ret = spe_expand_builtin (exp, target, &success); | |
7075 | ||
92898235 AH |
7076 | if (success) |
7077 | return ret; | |
7078 | } | |
7079 | ||
0559cc77 DE |
7080 | if (TARGET_ALTIVEC || TARGET_SPE) |
7081 | { | |
7082 | /* Handle simple unary operations. */ | |
7083 | d = (struct builtin_description *) bdesc_1arg; | |
7084 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
7085 | if (d->code == fcode) | |
7086 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
7087 | ||
7088 | /* Handle simple binary operations. */ | |
7089 | d = (struct builtin_description *) bdesc_2arg; | |
7090 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
7091 | if (d->code == fcode) | |
7092 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
7093 | ||
7094 | /* Handle simple ternary operations. */ | |
7095 | d = (struct builtin_description *) bdesc_3arg; | |
7096 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
7097 | if (d->code == fcode) | |
7098 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
7099 | } | |
0ac081f6 AH |
7100 | |
7101 | abort (); | |
92898235 | 7102 | return NULL_RTX; |
0ac081f6 AH |
7103 | } |
7104 | ||
7c62e993 PB |
7105 | static tree |
7106 | build_opaque_vector_type (tree node, int nunits) | |
7107 | { | |
7108 | node = copy_node (node); | |
7109 | TYPE_MAIN_VARIANT (node) = node; | |
7110 | return build_vector_type (node, nunits); | |
7111 | } | |
7112 | ||
0ac081f6 | 7113 | static void |
863d938c | 7114 | rs6000_init_builtins (void) |
0ac081f6 | 7115 | { |
4a5eab38 PB |
7116 | V2SI_type_node = build_vector_type (intSI_type_node, 2); |
7117 | V2SF_type_node = build_vector_type (float_type_node, 2); | |
7118 | V4HI_type_node = build_vector_type (intHI_type_node, 4); | |
7119 | V4SI_type_node = build_vector_type (intSI_type_node, 4); | |
7120 | V4SF_type_node = build_vector_type (float_type_node, 4); | |
7e463bda | 7121 | V8HI_type_node = build_vector_type (intHI_type_node, 8); |
4a5eab38 PB |
7122 | V16QI_type_node = build_vector_type (intQI_type_node, 16); |
7123 | ||
7124 | unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); | |
7125 | unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); | |
7126 | unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); | |
7127 | ||
7c62e993 PB |
7128 | opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); |
7129 | opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); | |
6035d635 | 7130 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
3fdaa45a | 7131 | |
8bb418a3 ZL |
7132 | /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' |
7133 | types, especially in C++ land. Similarly, 'vector pixel' is distinct from | |
7134 | 'vector unsigned short'. */ | |
7135 | ||
7136 | bool_char_type_node = copy_node (unsigned_intQI_type_node); | |
7137 | TYPE_MAIN_VARIANT (bool_char_type_node) = bool_char_type_node; | |
7138 | bool_short_type_node = copy_node (unsigned_intHI_type_node); | |
7139 | TYPE_MAIN_VARIANT (bool_short_type_node) = bool_short_type_node; | |
7140 | bool_int_type_node = copy_node (unsigned_intSI_type_node); | |
7141 | TYPE_MAIN_VARIANT (bool_int_type_node) = bool_int_type_node; | |
7142 | pixel_type_node = copy_node (unsigned_intHI_type_node); | |
7143 | TYPE_MAIN_VARIANT (pixel_type_node) = pixel_type_node; | |
7144 | ||
7145 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7146 | get_identifier ("__bool char"), | |
7147 | bool_char_type_node)); | |
7148 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7149 | get_identifier ("__bool short"), | |
7150 | bool_short_type_node)); | |
7151 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7152 | get_identifier ("__bool int"), | |
7153 | bool_int_type_node)); | |
7154 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7155 | get_identifier ("__pixel"), | |
7156 | pixel_type_node)); | |
7157 | ||
4a5eab38 PB |
7158 | bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); |
7159 | bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); | |
7160 | bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); | |
7161 | pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); | |
8bb418a3 ZL |
7162 | |
7163 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7164 | get_identifier ("__vector unsigned char"), | |
7165 | unsigned_V16QI_type_node)); | |
7166 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7167 | get_identifier ("__vector signed char"), | |
7168 | V16QI_type_node)); | |
7169 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7170 | get_identifier ("__vector __bool char"), | |
7171 | bool_V16QI_type_node)); | |
7172 | ||
7173 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7174 | get_identifier ("__vector unsigned short"), | |
7175 | unsigned_V8HI_type_node)); | |
7176 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7177 | get_identifier ("__vector signed short"), | |
7178 | V8HI_type_node)); | |
7179 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7180 | get_identifier ("__vector __bool short"), | |
7181 | bool_V8HI_type_node)); | |
7182 | ||
7183 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7184 | get_identifier ("__vector unsigned int"), | |
7185 | unsigned_V4SI_type_node)); | |
7186 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7187 | get_identifier ("__vector signed int"), | |
7188 | V4SI_type_node)); | |
7189 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7190 | get_identifier ("__vector __bool int"), | |
7191 | bool_V4SI_type_node)); | |
7192 | ||
7193 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7194 | get_identifier ("__vector float"), | |
7195 | V4SF_type_node)); | |
7196 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7197 | get_identifier ("__vector __pixel"), | |
7198 | pixel_V8HI_type_node)); | |
7199 | ||
a3170dc6 | 7200 | if (TARGET_SPE) |
3fdaa45a | 7201 | spe_init_builtins (); |
0ac081f6 AH |
7202 | if (TARGET_ALTIVEC) |
7203 | altivec_init_builtins (); | |
0559cc77 DE |
7204 | if (TARGET_ALTIVEC || TARGET_SPE) |
7205 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
7206 | } |
7207 | ||
a3170dc6 AH |
7208 | /* Search through a set of builtins and enable the mask bits. |
7209 | DESC is an array of builtins. | |
b6d08ca1 | 7210 | SIZE is the total number of builtins. |
a3170dc6 AH |
7211 | START is the builtin enum at which to start. |
7212 | END is the builtin enum at which to end. */ | |
0ac081f6 | 7213 | static void |
a2369ed3 DJ |
7214 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
7215 | enum rs6000_builtins start, | |
7216 | enum rs6000_builtins end) | |
a3170dc6 AH |
7217 | { |
7218 | int i; | |
7219 | ||
7220 | for (i = 0; i < size; ++i) | |
7221 | if (desc[i].code == start) | |
7222 | break; | |
7223 | ||
7224 | if (i == size) | |
7225 | return; | |
7226 | ||
7227 | for (; i < size; ++i) | |
7228 | { | |
7229 | /* Flip all the bits on. */ | |
7230 | desc[i].mask = target_flags; | |
7231 | if (desc[i].code == end) | |
7232 | break; | |
7233 | } | |
7234 | } | |
7235 | ||
7236 | static void | |
863d938c | 7237 | spe_init_builtins (void) |
0ac081f6 | 7238 | { |
a3170dc6 AH |
7239 | tree endlink = void_list_node; |
7240 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
7241 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 7242 | struct builtin_description *d; |
0ac081f6 AH |
7243 | size_t i; |
7244 | ||
a3170dc6 AH |
7245 | tree v2si_ftype_4_v2si |
7246 | = build_function_type | |
3fdaa45a AH |
7247 | (opaque_V2SI_type_node, |
7248 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7249 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7250 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7251 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7252 | endlink))))); |
7253 | ||
7254 | tree v2sf_ftype_4_v2sf | |
7255 | = build_function_type | |
3fdaa45a AH |
7256 | (opaque_V2SF_type_node, |
7257 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7258 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7259 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7260 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7261 | endlink))))); |
7262 | ||
7263 | tree int_ftype_int_v2si_v2si | |
7264 | = build_function_type | |
7265 | (integer_type_node, | |
7266 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7267 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
7268 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7269 | endlink)))); |
7270 | ||
7271 | tree int_ftype_int_v2sf_v2sf | |
7272 | = build_function_type | |
7273 | (integer_type_node, | |
7274 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7275 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
7276 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7277 | endlink)))); |
7278 | ||
7279 | tree void_ftype_v2si_puint_int | |
7280 | = build_function_type (void_type_node, | |
3fdaa45a | 7281 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7282 | tree_cons (NULL_TREE, puint_type_node, |
7283 | tree_cons (NULL_TREE, | |
7284 | integer_type_node, | |
7285 | endlink)))); | |
7286 | ||
7287 | tree void_ftype_v2si_puint_char | |
7288 | = build_function_type (void_type_node, | |
3fdaa45a | 7289 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7290 | tree_cons (NULL_TREE, puint_type_node, |
7291 | tree_cons (NULL_TREE, | |
7292 | char_type_node, | |
7293 | endlink)))); | |
7294 | ||
7295 | tree void_ftype_v2si_pv2si_int | |
7296 | = build_function_type (void_type_node, | |
3fdaa45a | 7297 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7298 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7299 | tree_cons (NULL_TREE, |
7300 | integer_type_node, | |
7301 | endlink)))); | |
7302 | ||
7303 | tree void_ftype_v2si_pv2si_char | |
7304 | = build_function_type (void_type_node, | |
3fdaa45a | 7305 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7306 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7307 | tree_cons (NULL_TREE, |
7308 | char_type_node, | |
7309 | endlink)))); | |
7310 | ||
7311 | tree void_ftype_int | |
7312 | = build_function_type (void_type_node, | |
7313 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
7314 | ||
7315 | tree int_ftype_void | |
36e8d515 | 7316 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
7317 | |
7318 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 7319 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 7320 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7321 | tree_cons (NULL_TREE, integer_type_node, |
7322 | endlink))); | |
7323 | ||
7324 | tree v2si_ftype_puint_int | |
3fdaa45a | 7325 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7326 | tree_cons (NULL_TREE, puint_type_node, |
7327 | tree_cons (NULL_TREE, integer_type_node, | |
7328 | endlink))); | |
7329 | ||
7330 | tree v2si_ftype_pushort_int | |
3fdaa45a | 7331 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7332 | tree_cons (NULL_TREE, pushort_type_node, |
7333 | tree_cons (NULL_TREE, integer_type_node, | |
7334 | endlink))); | |
7335 | ||
00332c9f AH |
7336 | tree v2si_ftype_signed_char |
7337 | = build_function_type (opaque_V2SI_type_node, | |
7338 | tree_cons (NULL_TREE, signed_char_type_node, | |
7339 | endlink)); | |
7340 | ||
a3170dc6 AH |
7341 | /* The initialization of the simple binary and unary builtins is |
7342 | done in rs6000_common_init_builtins, but we have to enable the | |
7343 | mask bits here manually because we have run out of `target_flags' | |
7344 | bits. We really need to redesign this mask business. */ | |
7345 | ||
7346 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
7347 | ARRAY_SIZE (bdesc_2arg), | |
7348 | SPE_BUILTIN_EVADDW, | |
7349 | SPE_BUILTIN_EVXOR); | |
7350 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
7351 | ARRAY_SIZE (bdesc_1arg), | |
7352 | SPE_BUILTIN_EVABS, | |
7353 | SPE_BUILTIN_EVSUBFUSIAAW); | |
7354 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
7355 | ARRAY_SIZE (bdesc_spe_predicates), | |
7356 | SPE_BUILTIN_EVCMPEQ, | |
7357 | SPE_BUILTIN_EVFSTSTLT); | |
7358 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
7359 | ARRAY_SIZE (bdesc_spe_evsel), | |
7360 | SPE_BUILTIN_EVSEL_CMPGTS, | |
7361 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
7362 | ||
36252949 AH |
7363 | (*lang_hooks.decls.pushdecl) |
7364 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
7365 | opaque_V2SI_type_node)); | |
7366 | ||
a3170dc6 AH |
7367 | /* Initialize irregular SPE builtins. */ |
7368 | ||
7369 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); | |
7370 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
7371 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
7372 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
7373 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
7374 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
7375 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
7376 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
7377 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
7378 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
7379 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
7380 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
7381 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
7382 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
7383 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
7384 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
7385 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
7386 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
7387 | |
7388 | /* Loads. */ | |
7389 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
7390 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
7391 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
7392 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
7393 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
7394 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
7395 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
7396 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
7397 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
7398 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
7399 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
7400 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
7401 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
7402 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
7403 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
7404 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
7405 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
7406 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
7407 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
7408 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
7409 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
7410 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
7411 | ||
7412 | /* Predicates. */ | |
7413 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7414 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
7415 | { | |
7416 | tree type; | |
7417 | ||
7418 | switch (insn_data[d->icode].operand[1].mode) | |
7419 | { | |
7420 | case V2SImode: | |
7421 | type = int_ftype_int_v2si_v2si; | |
7422 | break; | |
7423 | case V2SFmode: | |
7424 | type = int_ftype_int_v2sf_v2sf; | |
7425 | break; | |
7426 | default: | |
7427 | abort (); | |
7428 | } | |
7429 | ||
7430 | def_builtin (d->mask, d->name, type, d->code); | |
7431 | } | |
7432 | ||
7433 | /* Evsel predicates. */ | |
7434 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7435 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
7436 | { | |
7437 | tree type; | |
7438 | ||
7439 | switch (insn_data[d->icode].operand[1].mode) | |
7440 | { | |
7441 | case V2SImode: | |
7442 | type = v2si_ftype_4_v2si; | |
7443 | break; | |
7444 | case V2SFmode: | |
7445 | type = v2sf_ftype_4_v2sf; | |
7446 | break; | |
7447 | default: | |
7448 | abort (); | |
7449 | } | |
7450 | ||
7451 | def_builtin (d->mask, d->name, type, d->code); | |
7452 | } | |
7453 | } | |
7454 | ||
7455 | static void | |
863d938c | 7456 | altivec_init_builtins (void) |
a3170dc6 AH |
7457 | { |
7458 | struct builtin_description *d; | |
7459 | struct builtin_description_predicates *dp; | |
7460 | size_t i; | |
7461 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
7462 | tree pint_type_node = build_pointer_type (integer_type_node); | |
7463 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
7464 | tree pchar_type_node = build_pointer_type (char_type_node); | |
7465 | ||
7466 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
7467 | ||
0dbc3651 ZW |
7468 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
7469 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
7470 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
7471 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
7472 | ||
7473 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
7474 | ||
a3170dc6 AH |
7475 | tree int_ftype_int_v4si_v4si |
7476 | = build_function_type_list (integer_type_node, | |
7477 | integer_type_node, V4SI_type_node, | |
7478 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7479 | tree v4sf_ftype_pcfloat |
7480 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 7481 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 7482 | = build_function_type_list (void_type_node, |
a3170dc6 | 7483 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
7484 | tree v4si_ftype_pcint |
7485 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
7486 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
7487 | = build_function_type_list (void_type_node, |
7488 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7489 | tree v8hi_ftype_pcshort |
7490 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 7491 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
7492 | = build_function_type_list (void_type_node, |
7493 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7494 | tree v16qi_ftype_pcchar |
7495 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 7496 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
7497 | = build_function_type_list (void_type_node, |
7498 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 7499 | tree void_ftype_v4si |
b4de2f7d | 7500 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
7501 | tree v8hi_ftype_void |
7502 | = build_function_type (V8HI_type_node, void_list_node); | |
7503 | tree void_ftype_void | |
7504 | = build_function_type (void_type_node, void_list_node); | |
7505 | tree void_ftype_qi | |
7506 | = build_function_type_list (void_type_node, char_type_node, NULL_TREE); | |
0dbc3651 | 7507 | |
b4a62fa0 | 7508 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 7509 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
7510 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7511 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 7512 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
7513 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7514 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 7515 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 7516 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 7517 | |
b4a62fa0 | 7518 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 7519 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7520 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 7521 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7522 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 7523 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7524 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 7525 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7526 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 7527 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7528 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 7529 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
7530 | tree int_ftype_int_v8hi_v8hi |
7531 | = build_function_type_list (integer_type_node, | |
7532 | integer_type_node, V8HI_type_node, | |
7533 | V8HI_type_node, NULL_TREE); | |
7534 | tree int_ftype_int_v16qi_v16qi | |
7535 | = build_function_type_list (integer_type_node, | |
7536 | integer_type_node, V16QI_type_node, | |
7537 | V16QI_type_node, NULL_TREE); | |
7538 | tree int_ftype_int_v4sf_v4sf | |
7539 | = build_function_type_list (integer_type_node, | |
7540 | integer_type_node, V4SF_type_node, | |
7541 | V4SF_type_node, NULL_TREE); | |
7542 | tree v4si_ftype_v4si | |
7543 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7544 | tree v8hi_ftype_v8hi | |
7545 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
7546 | tree v16qi_ftype_v16qi | |
7547 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
7548 | tree v4sf_ftype_v4sf | |
7549 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8bb418a3 | 7550 | tree void_ftype_pcvoid_int_int |
a3170dc6 | 7551 | = build_function_type_list (void_type_node, |
0dbc3651 | 7552 | pcvoid_type_node, integer_type_node, |
8bb418a3 ZL |
7553 | integer_type_node, NULL_TREE); |
7554 | tree int_ftype_pcchar | |
7555 | = build_function_type_list (integer_type_node, | |
7556 | pcchar_type_node, NULL_TREE); | |
7557 | ||
0dbc3651 ZW |
7558 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, |
7559 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
7560 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
7561 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
7562 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
7563 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
7564 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
7565 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
7566 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
7567 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
7568 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
7569 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
7570 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
7571 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
7572 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
7573 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
7574 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
7575 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
7576 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
7577 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); | |
b4a62fa0 SB |
7578 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
7579 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
7580 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
7581 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
7582 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
7583 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
7584 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
7585 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
7586 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
7587 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
7588 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
7589 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
a3170dc6 | 7590 | |
8bb418a3 ZL |
7591 | /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */ |
7592 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar, | |
7593 | ALTIVEC_BUILTIN_COMPILETIME_ERROR); | |
7594 | ||
a3170dc6 AH |
7595 | /* Add the DST variants. */ |
7596 | d = (struct builtin_description *) bdesc_dst; | |
7597 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
8bb418a3 | 7598 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); |
a3170dc6 AH |
7599 | |
7600 | /* Initialize the predicates. */ | |
7601 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
7602 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
7603 | { | |
7604 | enum machine_mode mode1; | |
7605 | tree type; | |
7606 | ||
7607 | mode1 = insn_data[dp->icode].operand[1].mode; | |
7608 | ||
7609 | switch (mode1) | |
7610 | { | |
7611 | case V4SImode: | |
7612 | type = int_ftype_int_v4si_v4si; | |
7613 | break; | |
7614 | case V8HImode: | |
7615 | type = int_ftype_int_v8hi_v8hi; | |
7616 | break; | |
7617 | case V16QImode: | |
7618 | type = int_ftype_int_v16qi_v16qi; | |
7619 | break; | |
7620 | case V4SFmode: | |
7621 | type = int_ftype_int_v4sf_v4sf; | |
7622 | break; | |
7623 | default: | |
7624 | abort (); | |
7625 | } | |
7626 | ||
7627 | def_builtin (dp->mask, dp->name, type, dp->code); | |
7628 | } | |
7629 | ||
7630 | /* Initialize the abs* operators. */ | |
7631 | d = (struct builtin_description *) bdesc_abs; | |
7632 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
7633 | { | |
7634 | enum machine_mode mode0; | |
7635 | tree type; | |
7636 | ||
7637 | mode0 = insn_data[d->icode].operand[0].mode; | |
7638 | ||
7639 | switch (mode0) | |
7640 | { | |
7641 | case V4SImode: | |
7642 | type = v4si_ftype_v4si; | |
7643 | break; | |
7644 | case V8HImode: | |
7645 | type = v8hi_ftype_v8hi; | |
7646 | break; | |
7647 | case V16QImode: | |
7648 | type = v16qi_ftype_v16qi; | |
7649 | break; | |
7650 | case V4SFmode: | |
7651 | type = v4sf_ftype_v4sf; | |
7652 | break; | |
7653 | default: | |
7654 | abort (); | |
7655 | } | |
7656 | ||
7657 | def_builtin (d->mask, d->name, type, d->code); | |
7658 | } | |
7659 | } | |
7660 | ||
7661 | static void | |
863d938c | 7662 | rs6000_common_init_builtins (void) |
a3170dc6 AH |
7663 | { |
7664 | struct builtin_description *d; | |
7665 | size_t i; | |
7666 | ||
7667 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
7668 | = build_function_type_list (V4SF_type_node, | |
7669 | V4SF_type_node, V4SF_type_node, | |
7670 | V16QI_type_node, NULL_TREE); | |
7671 | tree v4si_ftype_v4si_v4si_v16qi | |
7672 | = build_function_type_list (V4SI_type_node, | |
7673 | V4SI_type_node, V4SI_type_node, | |
7674 | V16QI_type_node, NULL_TREE); | |
7675 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
7676 | = build_function_type_list (V8HI_type_node, | |
7677 | V8HI_type_node, V8HI_type_node, | |
7678 | V16QI_type_node, NULL_TREE); | |
7679 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
7680 | = build_function_type_list (V16QI_type_node, | |
7681 | V16QI_type_node, V16QI_type_node, | |
7682 | V16QI_type_node, NULL_TREE); | |
b9e4e5d1 ZL |
7683 | tree v4si_ftype_int |
7684 | = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); | |
7685 | tree v8hi_ftype_int | |
7686 | = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); | |
7687 | tree v16qi_ftype_int | |
7688 | = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); | |
a3170dc6 AH |
7689 | tree v8hi_ftype_v16qi |
7690 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
7691 | tree v4sf_ftype_v4sf | |
7692 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7693 | ||
7694 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
7695 | = build_function_type_list (opaque_V2SI_type_node, |
7696 | opaque_V2SI_type_node, | |
7697 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7698 | |
7699 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
7700 | = build_function_type_list (opaque_V2SF_type_node, |
7701 | opaque_V2SF_type_node, | |
7702 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7703 | |
7704 | tree v2si_ftype_int_int | |
2abe3e28 | 7705 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
7706 | integer_type_node, integer_type_node, |
7707 | NULL_TREE); | |
7708 | ||
7709 | tree v2si_ftype_v2si | |
2abe3e28 AH |
7710 | = build_function_type_list (opaque_V2SI_type_node, |
7711 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7712 | |
7713 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
7714 | = build_function_type_list (opaque_V2SF_type_node, |
7715 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7716 | |
7717 | tree v2sf_ftype_v2si | |
2abe3e28 AH |
7718 | = build_function_type_list (opaque_V2SF_type_node, |
7719 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7720 | |
7721 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
7722 | = build_function_type_list (opaque_V2SI_type_node, |
7723 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7724 | |
7725 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
7726 | = build_function_type_list (opaque_V2SI_type_node, |
7727 | opaque_V2SI_type_node, | |
7728 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
7729 | |
7730 | tree v2si_ftype_int_char | |
2abe3e28 | 7731 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
7732 | integer_type_node, char_type_node, NULL_TREE); |
7733 | ||
7734 | tree v2si_ftype_char | |
2abe3e28 AH |
7735 | = build_function_type_list (opaque_V2SI_type_node, |
7736 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
7737 | |
7738 | tree int_ftype_int_int | |
7739 | = build_function_type_list (integer_type_node, | |
7740 | integer_type_node, integer_type_node, | |
7741 | NULL_TREE); | |
95385cbb | 7742 | |
0ac081f6 | 7743 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
7744 | = build_function_type_list (V4SI_type_node, |
7745 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
b9e4e5d1 | 7746 | tree v4sf_ftype_v4si_int |
b4de2f7d | 7747 | = build_function_type_list (V4SF_type_node, |
b9e4e5d1 ZL |
7748 | V4SI_type_node, integer_type_node, NULL_TREE); |
7749 | tree v4si_ftype_v4sf_int | |
b4de2f7d | 7750 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
7751 | V4SF_type_node, integer_type_node, NULL_TREE); |
7752 | tree v4si_ftype_v4si_int | |
b4de2f7d | 7753 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
7754 | V4SI_type_node, integer_type_node, NULL_TREE); |
7755 | tree v8hi_ftype_v8hi_int | |
b4de2f7d | 7756 | = build_function_type_list (V8HI_type_node, |
b9e4e5d1 ZL |
7757 | V8HI_type_node, integer_type_node, NULL_TREE); |
7758 | tree v16qi_ftype_v16qi_int | |
b4de2f7d | 7759 | = build_function_type_list (V16QI_type_node, |
b9e4e5d1 ZL |
7760 | V16QI_type_node, integer_type_node, NULL_TREE); |
7761 | tree v16qi_ftype_v16qi_v16qi_int | |
b4de2f7d AH |
7762 | = build_function_type_list (V16QI_type_node, |
7763 | V16QI_type_node, V16QI_type_node, | |
b9e4e5d1 ZL |
7764 | integer_type_node, NULL_TREE); |
7765 | tree v8hi_ftype_v8hi_v8hi_int | |
b4de2f7d AH |
7766 | = build_function_type_list (V8HI_type_node, |
7767 | V8HI_type_node, V8HI_type_node, | |
b9e4e5d1 ZL |
7768 | integer_type_node, NULL_TREE); |
7769 | tree v4si_ftype_v4si_v4si_int | |
b4de2f7d AH |
7770 | = build_function_type_list (V4SI_type_node, |
7771 | V4SI_type_node, V4SI_type_node, | |
b9e4e5d1 ZL |
7772 | integer_type_node, NULL_TREE); |
7773 | tree v4sf_ftype_v4sf_v4sf_int | |
b4de2f7d AH |
7774 | = build_function_type_list (V4SF_type_node, |
7775 | V4SF_type_node, V4SF_type_node, | |
b9e4e5d1 | 7776 | integer_type_node, NULL_TREE); |
0ac081f6 | 7777 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
7778 | = build_function_type_list (V4SF_type_node, |
7779 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
617e0e1d | 7780 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
7781 | = build_function_type_list (V4SF_type_node, |
7782 | V4SF_type_node, V4SF_type_node, | |
7783 | V4SI_type_node, NULL_TREE); | |
2212663f | 7784 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
7785 | = build_function_type_list (V4SF_type_node, |
7786 | V4SF_type_node, V4SF_type_node, | |
7787 | V4SF_type_node, NULL_TREE); | |
617e0e1d | 7788 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
7789 | = build_function_type_list (V4SI_type_node, |
7790 | V4SI_type_node, V4SI_type_node, | |
7791 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7792 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
7793 | = build_function_type_list (V8HI_type_node, |
7794 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 7795 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
7796 | = build_function_type_list (V8HI_type_node, |
7797 | V8HI_type_node, V8HI_type_node, | |
7798 | V8HI_type_node, NULL_TREE); | |
2212663f | 7799 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
7800 | = build_function_type_list (V4SI_type_node, |
7801 | V8HI_type_node, V8HI_type_node, | |
7802 | V4SI_type_node, NULL_TREE); | |
2212663f | 7803 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
7804 | = build_function_type_list (V4SI_type_node, |
7805 | V16QI_type_node, V16QI_type_node, | |
7806 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7807 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
7808 | = build_function_type_list (V16QI_type_node, |
7809 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7810 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
7811 | = build_function_type_list (V4SI_type_node, |
7812 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 7813 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
7814 | = build_function_type_list (V8HI_type_node, |
7815 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7816 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
7817 | = build_function_type_list (V4SI_type_node, |
7818 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7819 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
7820 | = build_function_type_list (V8HI_type_node, |
7821 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7822 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
7823 | = build_function_type_list (V16QI_type_node, |
7824 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7825 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
7826 | = build_function_type_list (V4SI_type_node, |
7827 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 7828 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
7829 | = build_function_type_list (V4SI_type_node, |
7830 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7831 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
7832 | = build_function_type_list (V4SI_type_node, |
7833 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7834 | tree v4si_ftype_v8hi |
7835 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
7836 | tree int_ftype_v4si_v4si | |
7837 | = build_function_type_list (integer_type_node, | |
7838 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7839 | tree int_ftype_v4sf_v4sf | |
7840 | = build_function_type_list (integer_type_node, | |
7841 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7842 | tree int_ftype_v16qi_v16qi | |
7843 | = build_function_type_list (integer_type_node, | |
7844 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7845 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
7846 | = build_function_type_list (integer_type_node, |
7847 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7848 | |
6f317ef3 | 7849 | /* Add the simple ternary operators. */ |
2212663f | 7850 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 7851 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f DB |
7852 | { |
7853 | ||
7854 | enum machine_mode mode0, mode1, mode2, mode3; | |
7855 | tree type; | |
7856 | ||
0559cc77 | 7857 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
7858 | continue; |
7859 | ||
7860 | mode0 = insn_data[d->icode].operand[0].mode; | |
7861 | mode1 = insn_data[d->icode].operand[1].mode; | |
7862 | mode2 = insn_data[d->icode].operand[2].mode; | |
7863 | mode3 = insn_data[d->icode].operand[3].mode; | |
7864 | ||
7865 | /* When all four are of the same mode. */ | |
7866 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
7867 | { | |
7868 | switch (mode0) | |
7869 | { | |
617e0e1d DB |
7870 | case V4SImode: |
7871 | type = v4si_ftype_v4si_v4si_v4si; | |
7872 | break; | |
2212663f DB |
7873 | case V4SFmode: |
7874 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
7875 | break; | |
7876 | case V8HImode: | |
7877 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
7878 | break; | |
7879 | case V16QImode: | |
7880 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
7881 | break; | |
7882 | default: | |
7883 | abort(); | |
7884 | } | |
7885 | } | |
7886 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
7887 | { | |
7888 | switch (mode0) | |
7889 | { | |
7890 | case V4SImode: | |
7891 | type = v4si_ftype_v4si_v4si_v16qi; | |
7892 | break; | |
7893 | case V4SFmode: | |
7894 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
7895 | break; | |
7896 | case V8HImode: | |
7897 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
7898 | break; | |
7899 | case V16QImode: | |
7900 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
7901 | break; | |
7902 | default: | |
7903 | abort(); | |
7904 | } | |
7905 | } | |
7906 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode | |
7907 | && mode3 == V4SImode) | |
24408032 | 7908 | type = v4si_ftype_v16qi_v16qi_v4si; |
2212663f DB |
7909 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
7910 | && mode3 == V4SImode) | |
24408032 | 7911 | type = v4si_ftype_v8hi_v8hi_v4si; |
617e0e1d DB |
7912 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
7913 | && mode3 == V4SImode) | |
24408032 AH |
7914 | type = v4sf_ftype_v4sf_v4sf_v4si; |
7915 | ||
7916 | /* vchar, vchar, vchar, 4 bit literal. */ | |
7917 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
7918 | && mode3 == QImode) | |
b9e4e5d1 | 7919 | type = v16qi_ftype_v16qi_v16qi_int; |
24408032 AH |
7920 | |
7921 | /* vshort, vshort, vshort, 4 bit literal. */ | |
7922 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
7923 | && mode3 == QImode) | |
b9e4e5d1 | 7924 | type = v8hi_ftype_v8hi_v8hi_int; |
24408032 AH |
7925 | |
7926 | /* vint, vint, vint, 4 bit literal. */ | |
7927 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
7928 | && mode3 == QImode) | |
b9e4e5d1 | 7929 | type = v4si_ftype_v4si_v4si_int; |
24408032 AH |
7930 | |
7931 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
7932 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
7933 | && mode3 == QImode) | |
b9e4e5d1 | 7934 | type = v4sf_ftype_v4sf_v4sf_int; |
24408032 | 7935 | |
2212663f DB |
7936 | else |
7937 | abort (); | |
7938 | ||
7939 | def_builtin (d->mask, d->name, type, d->code); | |
7940 | } | |
7941 | ||
0ac081f6 | 7942 | /* Add the simple binary operators. */ |
00b960c7 | 7943 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 7944 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
7945 | { |
7946 | enum machine_mode mode0, mode1, mode2; | |
7947 | tree type; | |
7948 | ||
0559cc77 | 7949 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
0ac081f6 AH |
7950 | continue; |
7951 | ||
7952 | mode0 = insn_data[d->icode].operand[0].mode; | |
7953 | mode1 = insn_data[d->icode].operand[1].mode; | |
7954 | mode2 = insn_data[d->icode].operand[2].mode; | |
7955 | ||
7956 | /* When all three operands are of the same mode. */ | |
7957 | if (mode0 == mode1 && mode1 == mode2) | |
7958 | { | |
7959 | switch (mode0) | |
7960 | { | |
7961 | case V4SFmode: | |
7962 | type = v4sf_ftype_v4sf_v4sf; | |
7963 | break; | |
7964 | case V4SImode: | |
7965 | type = v4si_ftype_v4si_v4si; | |
7966 | break; | |
7967 | case V16QImode: | |
7968 | type = v16qi_ftype_v16qi_v16qi; | |
7969 | break; | |
7970 | case V8HImode: | |
7971 | type = v8hi_ftype_v8hi_v8hi; | |
7972 | break; | |
a3170dc6 AH |
7973 | case V2SImode: |
7974 | type = v2si_ftype_v2si_v2si; | |
7975 | break; | |
7976 | case V2SFmode: | |
7977 | type = v2sf_ftype_v2sf_v2sf; | |
7978 | break; | |
7979 | case SImode: | |
7980 | type = int_ftype_int_int; | |
7981 | break; | |
0ac081f6 AH |
7982 | default: |
7983 | abort (); | |
7984 | } | |
7985 | } | |
7986 | ||
7987 | /* A few other combos we really don't want to do manually. */ | |
7988 | ||
7989 | /* vint, vfloat, vfloat. */ | |
7990 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
7991 | type = v4si_ftype_v4sf_v4sf; | |
7992 | ||
7993 | /* vshort, vchar, vchar. */ | |
7994 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
7995 | type = v8hi_ftype_v16qi_v16qi; | |
7996 | ||
7997 | /* vint, vshort, vshort. */ | |
7998 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
7999 | type = v4si_ftype_v8hi_v8hi; | |
8000 | ||
8001 | /* vshort, vint, vint. */ | |
8002 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
8003 | type = v8hi_ftype_v4si_v4si; | |
8004 | ||
8005 | /* vchar, vshort, vshort. */ | |
8006 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
8007 | type = v16qi_ftype_v8hi_v8hi; | |
8008 | ||
8009 | /* vint, vchar, vint. */ | |
8010 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
8011 | type = v4si_ftype_v16qi_v4si; | |
8012 | ||
fa066a23 AH |
8013 | /* vint, vchar, vchar. */ |
8014 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
8015 | type = v4si_ftype_v16qi_v16qi; | |
8016 | ||
0ac081f6 AH |
8017 | /* vint, vshort, vint. */ |
8018 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
8019 | type = v4si_ftype_v8hi_v4si; | |
2212663f DB |
8020 | |
8021 | /* vint, vint, 5 bit literal. */ | |
8022 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8023 | type = v4si_ftype_v4si_int; |
2212663f DB |
8024 | |
8025 | /* vshort, vshort, 5 bit literal. */ | |
8026 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
b9e4e5d1 | 8027 | type = v8hi_ftype_v8hi_int; |
2212663f DB |
8028 | |
8029 | /* vchar, vchar, 5 bit literal. */ | |
8030 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
b9e4e5d1 | 8031 | type = v16qi_ftype_v16qi_int; |
0ac081f6 | 8032 | |
617e0e1d DB |
8033 | /* vfloat, vint, 5 bit literal. */ |
8034 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8035 | type = v4sf_ftype_v4si_int; |
617e0e1d DB |
8036 | |
8037 | /* vint, vfloat, 5 bit literal. */ | |
8038 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
b9e4e5d1 | 8039 | type = v4si_ftype_v4sf_int; |
617e0e1d | 8040 | |
a3170dc6 AH |
8041 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
8042 | type = v2si_ftype_int_int; | |
8043 | ||
8044 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
8045 | type = v2si_ftype_v2si_char; | |
8046 | ||
8047 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
8048 | type = v2si_ftype_int_char; | |
8049 | ||
0ac081f6 AH |
8050 | /* int, x, x. */ |
8051 | else if (mode0 == SImode) | |
8052 | { | |
8053 | switch (mode1) | |
8054 | { | |
8055 | case V4SImode: | |
8056 | type = int_ftype_v4si_v4si; | |
8057 | break; | |
8058 | case V4SFmode: | |
8059 | type = int_ftype_v4sf_v4sf; | |
8060 | break; | |
8061 | case V16QImode: | |
8062 | type = int_ftype_v16qi_v16qi; | |
8063 | break; | |
8064 | case V8HImode: | |
8065 | type = int_ftype_v8hi_v8hi; | |
8066 | break; | |
8067 | default: | |
8068 | abort (); | |
8069 | } | |
8070 | } | |
8071 | ||
8072 | else | |
8073 | abort (); | |
8074 | ||
2212663f DB |
8075 | def_builtin (d->mask, d->name, type, d->code); |
8076 | } | |
24408032 | 8077 | |
2212663f DB |
8078 | /* Add the simple unary operators. */ |
8079 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 8080 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
8081 | { |
8082 | enum machine_mode mode0, mode1; | |
8083 | tree type; | |
8084 | ||
0559cc77 | 8085 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
8086 | continue; |
8087 | ||
8088 | mode0 = insn_data[d->icode].operand[0].mode; | |
8089 | mode1 = insn_data[d->icode].operand[1].mode; | |
8090 | ||
8091 | if (mode0 == V4SImode && mode1 == QImode) | |
b9e4e5d1 | 8092 | type = v4si_ftype_int; |
2212663f | 8093 | else if (mode0 == V8HImode && mode1 == QImode) |
b9e4e5d1 | 8094 | type = v8hi_ftype_int; |
2212663f | 8095 | else if (mode0 == V16QImode && mode1 == QImode) |
b9e4e5d1 | 8096 | type = v16qi_ftype_int; |
617e0e1d DB |
8097 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
8098 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
8099 | else if (mode0 == V8HImode && mode1 == V16QImode) |
8100 | type = v8hi_ftype_v16qi; | |
8101 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
8102 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
8103 | else if (mode0 == V2SImode && mode1 == V2SImode) |
8104 | type = v2si_ftype_v2si; | |
8105 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
8106 | type = v2sf_ftype_v2sf; | |
8107 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
8108 | type = v2sf_ftype_v2si; | |
8109 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
8110 | type = v2si_ftype_v2sf; | |
8111 | else if (mode0 == V2SImode && mode1 == QImode) | |
8112 | type = v2si_ftype_char; | |
2212663f DB |
8113 | else |
8114 | abort (); | |
8115 | ||
0ac081f6 AH |
8116 | def_builtin (d->mask, d->name, type, d->code); |
8117 | } | |
8118 | } | |
8119 | ||
c15c90bb ZW |
8120 | static void |
8121 | rs6000_init_libfuncs (void) | |
8122 | { | |
8123 | if (!TARGET_HARD_FLOAT) | |
8124 | return; | |
8125 | ||
c9034561 | 8126 | if (DEFAULT_ABI != ABI_V4) |
c15c90bb | 8127 | { |
c9034561 | 8128 | if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC) |
c15c90bb | 8129 | { |
c9034561 | 8130 | /* AIX library routines for float->int conversion. */ |
85363ca0 ZW |
8131 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); |
8132 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
4274207b DE |
8133 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); |
8134 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
c15c90bb ZW |
8135 | } |
8136 | ||
c9034561 | 8137 | /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8138 | set_optab_libfunc (add_optab, TFmode, "_xlqadd"); |
8139 | set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); | |
8140 | set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); | |
8141 | set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); | |
8142 | } | |
c9034561 | 8143 | else |
c15c90bb | 8144 | { |
c9034561 | 8145 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8146 | |
8147 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
8148 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
8149 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
8150 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
8151 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
8152 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
8153 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
8154 | ||
c9034561 ZW |
8155 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
8156 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
8157 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
8158 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
8159 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
8160 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
8161 | ||
85363ca0 ZW |
8162 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
8163 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
8164 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
8165 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
8166 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
8167 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
8168 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
c15c90bb ZW |
8169 | } |
8170 | } | |
35aff10b | 8171 | \f |
7e69e155 MM |
8172 | /* Expand a block move operation, and return 1 if successful. Return 0 |
8173 | if we should let the compiler generate normal code. | |
8174 | ||
8175 | operands[0] is the destination | |
8176 | operands[1] is the source | |
8177 | operands[2] is the length | |
8178 | operands[3] is the alignment */ | |
8179 | ||
3933e0e1 MM |
8180 | #define MAX_MOVE_REG 4 |
8181 | ||
7e69e155 | 8182 | int |
a2369ed3 | 8183 | expand_block_move (rtx operands[]) |
7e69e155 | 8184 | { |
b6c9286a MM |
8185 | rtx orig_dest = operands[0]; |
8186 | rtx orig_src = operands[1]; | |
7e69e155 | 8187 | rtx bytes_rtx = operands[2]; |
7e69e155 | 8188 | rtx align_rtx = operands[3]; |
3933e0e1 | 8189 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 8190 | int align; |
3933e0e1 MM |
8191 | int bytes; |
8192 | int offset; | |
7e69e155 | 8193 | int move_bytes; |
cabfd258 GK |
8194 | rtx stores[MAX_MOVE_REG]; |
8195 | int num_reg = 0; | |
7e69e155 | 8196 | |
3933e0e1 | 8197 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 8198 | if (! constp) |
3933e0e1 MM |
8199 | return 0; |
8200 | ||
5ee95df6 FS |
8201 | /* If this is not a fixed size alignment, abort */ |
8202 | if (GET_CODE (align_rtx) != CONST_INT) | |
8203 | abort (); | |
8204 | align = INTVAL (align_rtx); | |
8205 | ||
7e69e155 | 8206 | /* Anything to move? */ |
3933e0e1 MM |
8207 | bytes = INTVAL (bytes_rtx); |
8208 | if (bytes <= 0) | |
7e69e155 MM |
8209 | return 1; |
8210 | ||
ea9982a8 | 8211 | /* store_one_arg depends on expand_block_move to handle at least the size of |
6f317ef3 | 8212 | reg_parm_stack_space. */ |
ea9982a8 | 8213 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
8214 | return 0; |
8215 | ||
cabfd258 | 8216 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 8217 | { |
cabfd258 | 8218 | union { |
a2369ed3 DJ |
8219 | rtx (*movstrsi) (rtx, rtx, rtx, rtx); |
8220 | rtx (*mov) (rtx, rtx); | |
cabfd258 GK |
8221 | } gen_func; |
8222 | enum machine_mode mode = BLKmode; | |
8223 | rtx src, dest; | |
8224 | ||
8225 | if (TARGET_STRING | |
8226 | && bytes > 24 /* move up to 32 bytes at a time */ | |
8227 | && ! fixed_regs[5] | |
8228 | && ! fixed_regs[6] | |
8229 | && ! fixed_regs[7] | |
8230 | && ! fixed_regs[8] | |
8231 | && ! fixed_regs[9] | |
8232 | && ! fixed_regs[10] | |
8233 | && ! fixed_regs[11] | |
8234 | && ! fixed_regs[12]) | |
7e69e155 | 8235 | { |
cabfd258 GK |
8236 | move_bytes = (bytes > 32) ? 32 : bytes; |
8237 | gen_func.movstrsi = gen_movstrsi_8reg; | |
8238 | } | |
8239 | else if (TARGET_STRING | |
8240 | && bytes > 16 /* move up to 24 bytes at a time */ | |
8241 | && ! fixed_regs[5] | |
8242 | && ! fixed_regs[6] | |
8243 | && ! fixed_regs[7] | |
8244 | && ! fixed_regs[8] | |
8245 | && ! fixed_regs[9] | |
8246 | && ! fixed_regs[10]) | |
8247 | { | |
8248 | move_bytes = (bytes > 24) ? 24 : bytes; | |
8249 | gen_func.movstrsi = gen_movstrsi_6reg; | |
8250 | } | |
8251 | else if (TARGET_STRING | |
8252 | && bytes > 8 /* move up to 16 bytes at a time */ | |
8253 | && ! fixed_regs[5] | |
8254 | && ! fixed_regs[6] | |
8255 | && ! fixed_regs[7] | |
8256 | && ! fixed_regs[8]) | |
8257 | { | |
8258 | move_bytes = (bytes > 16) ? 16 : bytes; | |
8259 | gen_func.movstrsi = gen_movstrsi_4reg; | |
8260 | } | |
8261 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8262 | /* 64-bit loads and stores require word-aligned | |
8263 | displacements. */ | |
8264 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
8265 | { | |
8266 | move_bytes = 8; | |
8267 | mode = DImode; | |
8268 | gen_func.mov = gen_movdi; | |
8269 | } | |
8270 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
8271 | { /* move up to 8 bytes at a time */ | |
8272 | move_bytes = (bytes > 8) ? 8 : bytes; | |
8273 | gen_func.movstrsi = gen_movstrsi_2reg; | |
8274 | } | |
8275 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) | |
8276 | { /* move 4 bytes */ | |
8277 | move_bytes = 4; | |
8278 | mode = SImode; | |
8279 | gen_func.mov = gen_movsi; | |
8280 | } | |
8281 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) | |
8282 | { /* move 2 bytes */ | |
8283 | move_bytes = 2; | |
8284 | mode = HImode; | |
8285 | gen_func.mov = gen_movhi; | |
8286 | } | |
8287 | else if (TARGET_STRING && bytes > 1) | |
8288 | { /* move up to 4 bytes at a time */ | |
8289 | move_bytes = (bytes > 4) ? 4 : bytes; | |
8290 | gen_func.movstrsi = gen_movstrsi_1reg; | |
8291 | } | |
8292 | else /* move 1 byte at a time */ | |
8293 | { | |
8294 | move_bytes = 1; | |
8295 | mode = QImode; | |
8296 | gen_func.mov = gen_movqi; | |
8297 | } | |
8298 | ||
8299 | src = adjust_address (orig_src, mode, offset); | |
8300 | dest = adjust_address (orig_dest, mode, offset); | |
8301 | ||
8302 | if (mode != BLKmode) | |
8303 | { | |
8304 | rtx tmp_reg = gen_reg_rtx (mode); | |
8305 | ||
8306 | emit_insn ((*gen_func.mov) (tmp_reg, src)); | |
8307 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 8308 | } |
3933e0e1 | 8309 | |
cabfd258 GK |
8310 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
8311 | { | |
8312 | int i; | |
8313 | for (i = 0; i < num_reg; i++) | |
8314 | emit_insn (stores[i]); | |
8315 | num_reg = 0; | |
8316 | } | |
35aff10b | 8317 | |
cabfd258 | 8318 | if (mode == BLKmode) |
7e69e155 | 8319 | { |
cabfd258 GK |
8320 | /* Move the address into scratch registers. The movstrsi |
8321 | patterns require zero offset. */ | |
8322 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 8323 | { |
cabfd258 GK |
8324 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
8325 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 8326 | } |
cabfd258 GK |
8327 | set_mem_size (src, GEN_INT (move_bytes)); |
8328 | ||
8329 | if (!REG_P (XEXP (dest, 0))) | |
3933e0e1 | 8330 | { |
cabfd258 GK |
8331 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
8332 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 8333 | } |
cabfd258 GK |
8334 | set_mem_size (dest, GEN_INT (move_bytes)); |
8335 | ||
8336 | emit_insn ((*gen_func.movstrsi) (dest, src, | |
8337 | GEN_INT (move_bytes & 31), | |
8338 | align_rtx)); | |
7e69e155 | 8339 | } |
7e69e155 MM |
8340 | } |
8341 | ||
8342 | return 1; | |
8343 | } | |
8344 | ||
9878760c RK |
8345 | \f |
8346 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
8347 | PARALLEL and the first section will be tested. */ | |
8348 | ||
8349 | int | |
a2369ed3 | 8350 | load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
8351 | { |
8352 | int count = XVECLEN (op, 0); | |
e2c953b6 | 8353 | unsigned int dest_regno; |
9878760c RK |
8354 | rtx src_addr; |
8355 | int i; | |
8356 | ||
8357 | /* Perform a quick check so we don't blow up below. */ | |
8358 | if (count <= 1 | |
8359 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8360 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
8361 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
8362 | return 0; | |
8363 | ||
8364 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
8365 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
8366 | ||
8367 | for (i = 1; i < count; i++) | |
8368 | { | |
8369 | rtx elt = XVECEXP (op, 0, i); | |
8370 | ||
8371 | if (GET_CODE (elt) != SET | |
8372 | || GET_CODE (SET_DEST (elt)) != REG | |
8373 | || GET_MODE (SET_DEST (elt)) != SImode | |
8374 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
8375 | || GET_CODE (SET_SRC (elt)) != MEM | |
8376 | || GET_MODE (SET_SRC (elt)) != SImode | |
8377 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
8378 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
8379 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
8380 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
8381 | return 0; | |
8382 | } | |
8383 | ||
8384 | return 1; | |
8385 | } | |
8386 | ||
8387 | /* Similar, but tests for store multiple. Here, the second vector element | |
8388 | is a CLOBBER. It will be tested later. */ | |
8389 | ||
8390 | int | |
a2369ed3 | 8391 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
8392 | { |
8393 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 8394 | unsigned int src_regno; |
9878760c RK |
8395 | rtx dest_addr; |
8396 | int i; | |
8397 | ||
8398 | /* Perform a quick check so we don't blow up below. */ | |
8399 | if (count <= 1 | |
8400 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8401 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
8402 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
8403 | return 0; | |
8404 | ||
8405 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
8406 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
8407 | ||
8408 | for (i = 1; i < count; i++) | |
8409 | { | |
8410 | rtx elt = XVECEXP (op, 0, i + 1); | |
8411 | ||
8412 | if (GET_CODE (elt) != SET | |
8413 | || GET_CODE (SET_SRC (elt)) != REG | |
8414 | || GET_MODE (SET_SRC (elt)) != SImode | |
8415 | || REGNO (SET_SRC (elt)) != src_regno + i | |
8416 | || GET_CODE (SET_DEST (elt)) != MEM | |
8417 | || GET_MODE (SET_DEST (elt)) != SImode | |
8418 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
8419 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
8420 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
8421 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
8422 | return 0; | |
8423 | } | |
8424 | ||
8425 | return 1; | |
8426 | } | |
9ebbca7d | 8427 | |
9caa3eb2 DE |
8428 | /* Return a string to perform a load_multiple operation. |
8429 | operands[0] is the vector. | |
8430 | operands[1] is the source address. | |
8431 | operands[2] is the first destination register. */ | |
8432 | ||
8433 | const char * | |
a2369ed3 | 8434 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
8435 | { |
8436 | /* We have to handle the case where the pseudo used to contain the address | |
8437 | is assigned to one of the output registers. */ | |
8438 | int i, j; | |
8439 | int words = XVECLEN (operands[0], 0); | |
8440 | rtx xop[10]; | |
8441 | ||
8442 | if (XVECLEN (operands[0], 0) == 1) | |
8443 | return "{l|lwz} %2,0(%1)"; | |
8444 | ||
8445 | for (i = 0; i < words; i++) | |
8446 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
8447 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
8448 | { | |
8449 | if (i == words-1) | |
8450 | { | |
8451 | xop[0] = GEN_INT (4 * (words-1)); | |
8452 | xop[1] = operands[1]; | |
8453 | xop[2] = operands[2]; | |
8454 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
8455 | return ""; | |
8456 | } | |
8457 | else if (i == 0) | |
8458 | { | |
8459 | xop[0] = GEN_INT (4 * (words-1)); | |
8460 | xop[1] = operands[1]; | |
8461 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8462 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
8463 | return ""; | |
8464 | } | |
8465 | else | |
8466 | { | |
8467 | for (j = 0; j < words; j++) | |
8468 | if (j != i) | |
8469 | { | |
8470 | xop[0] = GEN_INT (j * 4); | |
8471 | xop[1] = operands[1]; | |
8472 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
8473 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
8474 | } | |
8475 | xop[0] = GEN_INT (i * 4); | |
8476 | xop[1] = operands[1]; | |
8477 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
8478 | return ""; | |
8479 | } | |
8480 | } | |
8481 | ||
8482 | return "{lsi|lswi} %2,%1,%N0"; | |
8483 | } | |
8484 | ||
00b960c7 AH |
8485 | /* Return 1 for a parallel vrsave operation. */ |
8486 | ||
8487 | int | |
a2369ed3 | 8488 | vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
00b960c7 AH |
8489 | { |
8490 | int count = XVECLEN (op, 0); | |
8491 | unsigned int dest_regno, src_regno; | |
8492 | int i; | |
8493 | ||
8494 | if (count <= 1 | |
8495 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8496 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 8497 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
8498 | return 0; |
8499 | ||
8500 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
8501 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
8502 | ||
8503 | if (dest_regno != VRSAVE_REGNO | |
8504 | && src_regno != VRSAVE_REGNO) | |
8505 | return 0; | |
8506 | ||
8507 | for (i = 1; i < count; i++) | |
8508 | { | |
8509 | rtx elt = XVECEXP (op, 0, i); | |
8510 | ||
9aa86737 AH |
8511 | if (GET_CODE (elt) != CLOBBER |
8512 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
8513 | return 0; |
8514 | } | |
8515 | ||
8516 | return 1; | |
8517 | } | |
8518 | ||
2c4a9cff DE |
8519 | /* Return 1 for an PARALLEL suitable for mfcr. */ |
8520 | ||
8521 | int | |
a2369ed3 | 8522 | mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2c4a9cff DE |
8523 | { |
8524 | int count = XVECLEN (op, 0); | |
8525 | int i; | |
8526 | ||
8527 | /* Perform a quick check so we don't blow up below. */ | |
8528 | if (count < 1 | |
8529 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8530 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
8531 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
8532 | return 0; | |
8533 | ||
8534 | for (i = 0; i < count; i++) | |
8535 | { | |
8536 | rtx exp = XVECEXP (op, 0, i); | |
8537 | rtx unspec; | |
8538 | int maskval; | |
8539 | rtx src_reg; | |
8540 | ||
8541 | src_reg = XVECEXP (SET_SRC (exp), 0, 0); | |
8542 | ||
8543 | if (GET_CODE (src_reg) != REG | |
8544 | || GET_MODE (src_reg) != CCmode | |
8545 | || ! CR_REGNO_P (REGNO (src_reg))) | |
8546 | return 0; | |
8547 | ||
8548 | if (GET_CODE (exp) != SET | |
8549 | || GET_CODE (SET_DEST (exp)) != REG | |
8550 | || GET_MODE (SET_DEST (exp)) != SImode | |
8551 | || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) | |
8552 | return 0; | |
8553 | unspec = SET_SRC (exp); | |
8554 | maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); | |
8555 | ||
8556 | if (GET_CODE (unspec) != UNSPEC | |
8557 | || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR | |
8558 | || XVECLEN (unspec, 0) != 2 | |
8559 | || XVECEXP (unspec, 0, 0) != src_reg | |
8560 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
8561 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
8562 | return 0; | |
8563 | } | |
8564 | return 1; | |
8565 | } | |
8566 | ||
a4f6c312 | 8567 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
8568 | |
8569 | int | |
a2369ed3 | 8570 | mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
8571 | { |
8572 | int count = XVECLEN (op, 0); | |
8573 | int i; | |
9ebbca7d GK |
8574 | rtx src_reg; |
8575 | ||
8576 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
8577 | if (count < 1 |
8578 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8579 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
8580 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 8581 | return 0; |
e35b9579 | 8582 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
8583 | |
8584 | if (GET_CODE (src_reg) != REG | |
8585 | || GET_MODE (src_reg) != SImode | |
8586 | || ! INT_REGNO_P (REGNO (src_reg))) | |
8587 | return 0; | |
8588 | ||
e35b9579 | 8589 | for (i = 0; i < count; i++) |
9ebbca7d GK |
8590 | { |
8591 | rtx exp = XVECEXP (op, 0, i); | |
8592 | rtx unspec; | |
8593 | int maskval; | |
8594 | ||
8595 | if (GET_CODE (exp) != SET | |
8596 | || GET_CODE (SET_DEST (exp)) != REG | |
8597 | || GET_MODE (SET_DEST (exp)) != CCmode | |
8598 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
8599 | return 0; | |
8600 | unspec = SET_SRC (exp); | |
8601 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
8602 | |
8603 | if (GET_CODE (unspec) != UNSPEC | |
615158e2 | 8604 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR |
9ebbca7d GK |
8605 | || XVECLEN (unspec, 0) != 2 |
8606 | || XVECEXP (unspec, 0, 0) != src_reg | |
8607 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
8608 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
8609 | return 0; | |
8610 | } | |
e35b9579 | 8611 | return 1; |
9ebbca7d GK |
8612 | } |
8613 | ||
a4f6c312 | 8614 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
8615 | |
8616 | int | |
a2369ed3 | 8617 | lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
8618 | { |
8619 | int count = XVECLEN (op, 0); | |
e2c953b6 | 8620 | unsigned int dest_regno; |
9ebbca7d | 8621 | rtx src_addr; |
e2c953b6 | 8622 | unsigned int base_regno; |
9ebbca7d GK |
8623 | HOST_WIDE_INT offset; |
8624 | int i; | |
8625 | ||
8626 | /* Perform a quick check so we don't blow up below. */ | |
8627 | if (count <= 1 | |
8628 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8629 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
8630 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
8631 | return 0; | |
8632 | ||
8633 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
8634 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
8635 | ||
8636 | if (dest_regno > 31 | |
e2c953b6 | 8637 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
8638 | return 0; |
8639 | ||
4d588c14 | 8640 | if (legitimate_indirect_address_p (src_addr, 0)) |
9ebbca7d GK |
8641 | { |
8642 | offset = 0; | |
8643 | base_regno = REGNO (src_addr); | |
8644 | if (base_regno == 0) | |
8645 | return 0; | |
8646 | } | |
76d2b81d | 8647 | else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0)) |
9ebbca7d GK |
8648 | { |
8649 | offset = INTVAL (XEXP (src_addr, 1)); | |
8650 | base_regno = REGNO (XEXP (src_addr, 0)); | |
8651 | } | |
8652 | else | |
8653 | return 0; | |
8654 | ||
8655 | for (i = 0; i < count; i++) | |
8656 | { | |
8657 | rtx elt = XVECEXP (op, 0, i); | |
8658 | rtx newaddr; | |
8659 | rtx addr_reg; | |
8660 | HOST_WIDE_INT newoffset; | |
8661 | ||
8662 | if (GET_CODE (elt) != SET | |
8663 | || GET_CODE (SET_DEST (elt)) != REG | |
8664 | || GET_MODE (SET_DEST (elt)) != SImode | |
8665 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
8666 | || GET_CODE (SET_SRC (elt)) != MEM | |
8667 | || GET_MODE (SET_SRC (elt)) != SImode) | |
8668 | return 0; | |
8669 | newaddr = XEXP (SET_SRC (elt), 0); | |
4d588c14 | 8670 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
8671 | { |
8672 | newoffset = 0; | |
8673 | addr_reg = newaddr; | |
8674 | } | |
76d2b81d | 8675 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
8676 | { |
8677 | addr_reg = XEXP (newaddr, 0); | |
8678 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
8679 | } | |
8680 | else | |
8681 | return 0; | |
8682 | if (REGNO (addr_reg) != base_regno | |
8683 | || newoffset != offset + 4 * i) | |
8684 | return 0; | |
8685 | } | |
8686 | ||
8687 | return 1; | |
8688 | } | |
8689 | ||
a4f6c312 | 8690 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
8691 | |
8692 | int | |
a2369ed3 | 8693 | stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
8694 | { |
8695 | int count = XVECLEN (op, 0); | |
e2c953b6 | 8696 | unsigned int src_regno; |
9ebbca7d | 8697 | rtx dest_addr; |
e2c953b6 | 8698 | unsigned int base_regno; |
9ebbca7d GK |
8699 | HOST_WIDE_INT offset; |
8700 | int i; | |
8701 | ||
8702 | /* Perform a quick check so we don't blow up below. */ | |
8703 | if (count <= 1 | |
8704 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8705 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
8706 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
8707 | return 0; | |
8708 | ||
8709 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
8710 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
8711 | ||
8712 | if (src_regno > 31 | |
e2c953b6 | 8713 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
8714 | return 0; |
8715 | ||
4d588c14 | 8716 | if (legitimate_indirect_address_p (dest_addr, 0)) |
9ebbca7d GK |
8717 | { |
8718 | offset = 0; | |
8719 | base_regno = REGNO (dest_addr); | |
8720 | if (base_regno == 0) | |
8721 | return 0; | |
8722 | } | |
76d2b81d | 8723 | else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0)) |
9ebbca7d GK |
8724 | { |
8725 | offset = INTVAL (XEXP (dest_addr, 1)); | |
8726 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
8727 | } | |
8728 | else | |
8729 | return 0; | |
8730 | ||
8731 | for (i = 0; i < count; i++) | |
8732 | { | |
8733 | rtx elt = XVECEXP (op, 0, i); | |
8734 | rtx newaddr; | |
8735 | rtx addr_reg; | |
8736 | HOST_WIDE_INT newoffset; | |
8737 | ||
8738 | if (GET_CODE (elt) != SET | |
8739 | || GET_CODE (SET_SRC (elt)) != REG | |
8740 | || GET_MODE (SET_SRC (elt)) != SImode | |
8741 | || REGNO (SET_SRC (elt)) != src_regno + i | |
8742 | || GET_CODE (SET_DEST (elt)) != MEM | |
8743 | || GET_MODE (SET_DEST (elt)) != SImode) | |
8744 | return 0; | |
8745 | newaddr = XEXP (SET_DEST (elt), 0); | |
4d588c14 | 8746 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
8747 | { |
8748 | newoffset = 0; | |
8749 | addr_reg = newaddr; | |
8750 | } | |
76d2b81d | 8751 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
8752 | { |
8753 | addr_reg = XEXP (newaddr, 0); | |
8754 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
8755 | } | |
8756 | else | |
8757 | return 0; | |
8758 | if (REGNO (addr_reg) != base_regno | |
8759 | || newoffset != offset + 4 * i) | |
8760 | return 0; | |
8761 | } | |
8762 | ||
8763 | return 1; | |
8764 | } | |
9878760c | 8765 | \f |
a4f6c312 SS |
8766 | /* A validation routine: say whether CODE, a condition code, and MODE |
8767 | match. The other alternatives either don't make sense or should | |
8768 | never be generated. */ | |
39a10a29 | 8769 | |
39a10a29 | 8770 | static void |
a2369ed3 | 8771 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 | 8772 | { |
ec8e098d PB |
8773 | if ((GET_RTX_CLASS (code) != RTX_COMPARE |
8774 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE) | |
39a10a29 GK |
8775 | || GET_MODE_CLASS (mode) != MODE_CC) |
8776 | abort (); | |
8777 | ||
8778 | /* These don't make sense. */ | |
8779 | if ((code == GT || code == LT || code == GE || code == LE) | |
8780 | && mode == CCUNSmode) | |
8781 | abort (); | |
8782 | ||
8783 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
8784 | && mode != CCUNSmode) | |
8785 | abort (); | |
8786 | ||
8787 | if (mode != CCFPmode | |
8788 | && (code == ORDERED || code == UNORDERED | |
8789 | || code == UNEQ || code == LTGT | |
8790 | || code == UNGT || code == UNLT | |
8791 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 8792 | abort (); |
39a10a29 | 8793 | |
de6c5979 | 8794 | /* These should never be generated except for |
bc9ec0e0 | 8795 | flag_finite_math_only. */ |
39a10a29 | 8796 | if (mode == CCFPmode |
ad72b533 | 8797 | && ! flag_finite_math_only |
39a10a29 GK |
8798 | && (code == LE || code == GE |
8799 | || code == UNEQ || code == LTGT | |
8800 | || code == UNGT || code == UNLT)) | |
8801 | abort (); | |
8802 | ||
8803 | /* These are invalid; the information is not there. */ | |
8804 | if (mode == CCEQmode | |
8805 | && code != EQ && code != NE) | |
8806 | abort (); | |
8807 | } | |
8808 | ||
9878760c RK |
8809 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
8810 | We only check the opcode against the mode of the CC value here. */ | |
8811 | ||
8812 | int | |
a2369ed3 | 8813 | branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
8814 | { |
8815 | enum rtx_code code = GET_CODE (op); | |
8816 | enum machine_mode cc_mode; | |
8817 | ||
ec8e098d | 8818 | if (!COMPARISON_P (op)) |
9878760c RK |
8819 | return 0; |
8820 | ||
8821 | cc_mode = GET_MODE (XEXP (op, 0)); | |
8822 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
8823 | return 0; | |
8824 | ||
39a10a29 | 8825 | validate_condition_mode (code, cc_mode); |
9878760c | 8826 | |
39a10a29 GK |
8827 | return 1; |
8828 | } | |
8829 | ||
8830 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
8831 | insn and which is true if the corresponding bit in the CC register | |
8832 | is set. */ | |
8833 | ||
8834 | int | |
a2369ed3 | 8835 | branch_positive_comparison_operator (rtx op, enum machine_mode mode) |
39a10a29 GK |
8836 | { |
8837 | enum rtx_code code; | |
8838 | ||
8daf2e65 | 8839 | if (! branch_comparison_operator (op, mode)) |
9878760c RK |
8840 | return 0; |
8841 | ||
39a10a29 GK |
8842 | code = GET_CODE (op); |
8843 | return (code == EQ || code == LT || code == GT | |
8844 | || code == LTU || code == GTU | |
8845 | || code == UNORDERED); | |
9878760c RK |
8846 | } |
8847 | ||
b7053a3f GK |
8848 | /* Return 1 if OP is a comparison operation that is valid for an scc |
8849 | insn: it must be a positive comparison. */ | |
9878760c RK |
8850 | |
8851 | int | |
a2369ed3 | 8852 | scc_comparison_operator (rtx op, enum machine_mode mode) |
9878760c | 8853 | { |
b7053a3f | 8854 | return branch_positive_comparison_operator (op, mode); |
9878760c | 8855 | } |
e0cd0770 JC |
8856 | |
8857 | int | |
a2369ed3 | 8858 | trap_comparison_operator (rtx op, enum machine_mode mode) |
e0cd0770 JC |
8859 | { |
8860 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
8861 | return 0; | |
ec8e098d | 8862 | return COMPARISON_P (op); |
e0cd0770 | 8863 | } |
dfbdccdb GK |
8864 | |
8865 | int | |
a2369ed3 | 8866 | boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dfbdccdb GK |
8867 | { |
8868 | enum rtx_code code = GET_CODE (op); | |
8869 | return (code == AND || code == IOR || code == XOR); | |
8870 | } | |
1d328b19 GK |
8871 | |
8872 | int | |
a2369ed3 | 8873 | boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
1d328b19 GK |
8874 | { |
8875 | enum rtx_code code = GET_CODE (op); | |
8876 | return (code == IOR || code == XOR); | |
8877 | } | |
50a0b056 GK |
8878 | |
8879 | int | |
a2369ed3 | 8880 | min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
50a0b056 GK |
8881 | { |
8882 | enum rtx_code code = GET_CODE (op); | |
8883 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
8884 | } | |
9878760c RK |
8885 | \f |
8886 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
8887 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 8888 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
8889 | |
8890 | int | |
a2369ed3 | 8891 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 8892 | { |
e2c953b6 DE |
8893 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
8894 | ||
8895 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 8896 | |
b1765bde | 8897 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
8898 | } |
8899 | ||
8900 | /* Similar, but for right shift. */ | |
8901 | ||
8902 | int | |
a2369ed3 | 8903 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 8904 | { |
a7653a2c | 8905 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
8906 | |
8907 | shift_mask >>= INTVAL (shiftop); | |
8908 | ||
b1765bde | 8909 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
8910 | } |
8911 | ||
c5059423 AM |
8912 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
8913 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 8914 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
8915 | |
8916 | int | |
a2369ed3 | 8917 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 8918 | { |
c5059423 AM |
8919 | if (GET_CODE (andop) == CONST_INT) |
8920 | { | |
02071907 | 8921 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 8922 | |
c5059423 | 8923 | c = INTVAL (andop); |
02071907 | 8924 | if (c == 0 || c == ~0) |
c5059423 | 8925 | return 0; |
e2c953b6 | 8926 | |
02071907 | 8927 | shift_mask = ~0; |
c5059423 AM |
8928 | shift_mask <<= INTVAL (shiftop); |
8929 | ||
b6d08ca1 | 8930 | /* Find the least significant one bit. */ |
c5059423 AM |
8931 | lsb = c & -c; |
8932 | ||
8933 | /* It must coincide with the LSB of the shift mask. */ | |
8934 | if (-lsb != shift_mask) | |
8935 | return 0; | |
e2c953b6 | 8936 | |
c5059423 AM |
8937 | /* Invert to look for the next transition (if any). */ |
8938 | c = ~c; | |
8939 | ||
8940 | /* Remove the low group of ones (originally low group of zeros). */ | |
8941 | c &= -lsb; | |
8942 | ||
8943 | /* Again find the lsb, and check we have all 1's above. */ | |
8944 | lsb = c & -c; | |
8945 | return c == -lsb; | |
8946 | } | |
8947 | else if (GET_CODE (andop) == CONST_DOUBLE | |
8948 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
8949 | { | |
02071907 AM |
8950 | HOST_WIDE_INT low, high, lsb; |
8951 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
8952 | |
8953 | low = CONST_DOUBLE_LOW (andop); | |
8954 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8955 | high = CONST_DOUBLE_HIGH (andop); | |
8956 | ||
8957 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 8958 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
8959 | return 0; |
8960 | ||
8961 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
8962 | { | |
02071907 | 8963 | shift_mask_high = ~0; |
c5059423 AM |
8964 | if (INTVAL (shiftop) > 32) |
8965 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
8966 | ||
8967 | lsb = high & -high; | |
8968 | ||
8969 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
8970 | return 0; | |
8971 | ||
8972 | high = ~high; | |
8973 | high &= -lsb; | |
8974 | ||
8975 | lsb = high & -high; | |
8976 | return high == -lsb; | |
8977 | } | |
8978 | ||
02071907 | 8979 | shift_mask_low = ~0; |
c5059423 AM |
8980 | shift_mask_low <<= INTVAL (shiftop); |
8981 | ||
8982 | lsb = low & -low; | |
8983 | ||
8984 | if (-lsb != shift_mask_low) | |
8985 | return 0; | |
8986 | ||
8987 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8988 | high = ~high; | |
8989 | low = ~low; | |
8990 | low &= -lsb; | |
8991 | ||
8992 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
8993 | { | |
8994 | lsb = high & -high; | |
8995 | return high == -lsb; | |
8996 | } | |
8997 | ||
8998 | lsb = low & -low; | |
8999 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
9000 | } | |
9001 | else | |
9002 | return 0; | |
9003 | } | |
e2c953b6 | 9004 | |
c5059423 AM |
9005 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
9006 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 9007 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 9008 | |
c5059423 | 9009 | int |
a2369ed3 | 9010 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 9011 | { |
e2c953b6 | 9012 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 9013 | { |
02071907 | 9014 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 9015 | |
02071907 | 9016 | shift_mask = ~0; |
c5059423 AM |
9017 | shift_mask <<= INTVAL (shiftop); |
9018 | c = INTVAL (andop); | |
9019 | ||
c1207243 | 9020 | /* Find the least significant one bit. */ |
c5059423 AM |
9021 | lsb = c & -c; |
9022 | ||
9023 | /* It must be covered by the shift mask. | |
a4f6c312 | 9024 | This test also rejects c == 0. */ |
c5059423 AM |
9025 | if ((lsb & shift_mask) == 0) |
9026 | return 0; | |
9027 | ||
9028 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
9029 | return c == -lsb && lsb != 1; | |
9030 | } | |
9031 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9032 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9033 | { | |
02071907 | 9034 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
9035 | |
9036 | low = CONST_DOUBLE_LOW (andop); | |
9037 | ||
9038 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9039 | { | |
02071907 | 9040 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
9041 | |
9042 | high = CONST_DOUBLE_HIGH (andop); | |
9043 | ||
9044 | if (low == 0) | |
9045 | { | |
02071907 | 9046 | shift_mask_high = ~0; |
c5059423 AM |
9047 | if (INTVAL (shiftop) > 32) |
9048 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9049 | ||
9050 | lsb = high & -high; | |
9051 | ||
9052 | if ((lsb & shift_mask_high) == 0) | |
9053 | return 0; | |
9054 | ||
9055 | return high == -lsb; | |
9056 | } | |
9057 | if (high != ~0) | |
9058 | return 0; | |
9059 | } | |
9060 | ||
02071907 | 9061 | shift_mask_low = ~0; |
c5059423 AM |
9062 | shift_mask_low <<= INTVAL (shiftop); |
9063 | ||
9064 | lsb = low & -low; | |
9065 | ||
9066 | if ((lsb & shift_mask_low) == 0) | |
9067 | return 0; | |
9068 | ||
9069 | return low == -lsb && lsb != 1; | |
9070 | } | |
e2c953b6 | 9071 | else |
c5059423 | 9072 | return 0; |
9878760c | 9073 | } |
35068b43 | 9074 | |
11ac38b2 DE |
9075 | /* Return 1 if operands will generate a valid arguments to rlwimi |
9076 | instruction for insert with right shift in 64-bit mode. The mask may | |
9077 | not start on the first bit or stop on the last bit because wrap-around | |
9078 | effects of instruction do not correspond to semantics of RTL insn. */ | |
9079 | ||
9080 | int | |
9081 | insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) | |
9082 | { | |
9083 | if (INTVAL (startop) < 64 | |
9084 | && INTVAL (startop) > 32 | |
9085 | && (INTVAL (sizeop) + INTVAL (startop) < 64) | |
9086 | && (INTVAL (sizeop) + INTVAL (startop) > 33) | |
9087 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96) | |
9088 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64) | |
9089 | && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) | |
9090 | return 1; | |
9091 | ||
9092 | return 0; | |
9093 | } | |
9094 | ||
35068b43 | 9095 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates |
90f81f99 | 9096 | for lfq and stfq insns iff the registers are hard registers. */ |
35068b43 RK |
9097 | |
9098 | int | |
a2369ed3 | 9099 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
9100 | { |
9101 | /* We might have been passed a SUBREG. */ | |
9102 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
9103 | return 0; | |
90f81f99 AP |
9104 | |
9105 | /* We might have been passed non floating point registers. */ | |
9106 | if (!FP_REGNO_P (REGNO (reg1)) | |
9107 | || !FP_REGNO_P (REGNO (reg2))) | |
9108 | return 0; | |
35068b43 RK |
9109 | |
9110 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
9111 | } | |
9112 | ||
a4f6c312 SS |
9113 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
9114 | addr1 and addr2 must be in consecutive memory locations | |
9115 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
9116 | |
9117 | int | |
90f81f99 | 9118 | mems_ok_for_quad_peep (rtx mem1, rtx mem2) |
35068b43 | 9119 | { |
90f81f99 | 9120 | rtx addr1, addr2; |
e2c953b6 | 9121 | unsigned int reg1; |
35068b43 RK |
9122 | int offset1; |
9123 | ||
90f81f99 AP |
9124 | /* The mems cannot be volatile. */ |
9125 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
9126 | return 0; | |
9127 | ||
9128 | addr1 = XEXP (mem1, 0); | |
9129 | addr2 = XEXP (mem2, 0); | |
9130 | ||
35068b43 RK |
9131 | /* Extract an offset (if used) from the first addr. */ |
9132 | if (GET_CODE (addr1) == PLUS) | |
9133 | { | |
9134 | /* If not a REG, return zero. */ | |
9135 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
9136 | return 0; | |
9137 | else | |
9138 | { | |
9139 | reg1 = REGNO (XEXP (addr1, 0)); | |
9140 | /* The offset must be constant! */ | |
9141 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
9142 | return 0; | |
9143 | offset1 = INTVAL (XEXP (addr1, 1)); | |
9144 | } | |
9145 | } | |
9146 | else if (GET_CODE (addr1) != REG) | |
9147 | return 0; | |
9148 | else | |
9149 | { | |
9150 | reg1 = REGNO (addr1); | |
9151 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
9152 | offset1 = 0; | |
9153 | } | |
9154 | ||
a2369ed3 | 9155 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
0f6937fe AM |
9156 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same |
9157 | register as addr1. */ | |
984e25ac | 9158 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) |
0f6937fe | 9159 | return 1; |
35068b43 RK |
9160 | if (GET_CODE (addr2) != PLUS) |
9161 | return 0; | |
9162 | ||
9163 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
9164 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
9165 | return 0; | |
9166 | ||
9167 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
9168 | return 0; | |
9169 | ||
9170 | /* The offset for the second addr must be 8 more than the first addr. */ | |
9171 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
9172 | return 0; | |
9173 | ||
9174 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
9175 | instructions. */ | |
9176 | return 1; | |
9177 | } | |
9878760c RK |
9178 | \f |
9179 | /* Return the register class of a scratch register needed to copy IN into | |
9180 | or out of a register in CLASS in MODE. If it can be done directly, | |
9181 | NO_REGS is returned. */ | |
9182 | ||
9183 | enum reg_class | |
a2369ed3 | 9184 | secondary_reload_class (enum reg_class class, |
a9baceb1 GK |
9185 | enum machine_mode mode ATTRIBUTE_UNUSED, |
9186 | rtx in) | |
9878760c | 9187 | { |
5accd822 | 9188 | int regno; |
9878760c | 9189 | |
ab82a49f AP |
9190 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
9191 | #if TARGET_MACHO | |
9192 | && MACHOPIC_INDIRECT | |
9193 | #endif | |
9194 | )) | |
46fad5b7 DJ |
9195 | { |
9196 | /* We cannot copy a symbolic operand directly into anything | |
9197 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
9198 | register from BASE_REGS is needed as an intermediate | |
9199 | register. | |
9200 | ||
9201 | On Darwin, pic addresses require a load from memory, which | |
9202 | needs a base register. */ | |
9203 | if (class != BASE_REGS | |
9204 | && (GET_CODE (in) == SYMBOL_REF | |
9205 | || GET_CODE (in) == HIGH | |
9206 | || GET_CODE (in) == LABEL_REF | |
9207 | || GET_CODE (in) == CONST)) | |
9208 | return BASE_REGS; | |
9209 | } | |
e7b7998a | 9210 | |
5accd822 DE |
9211 | if (GET_CODE (in) == REG) |
9212 | { | |
9213 | regno = REGNO (in); | |
9214 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9215 | { | |
9216 | regno = true_regnum (in); | |
9217 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9218 | regno = -1; | |
9219 | } | |
9220 | } | |
9221 | else if (GET_CODE (in) == SUBREG) | |
9222 | { | |
9223 | regno = true_regnum (in); | |
9224 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9225 | regno = -1; | |
9226 | } | |
9227 | else | |
9228 | regno = -1; | |
9229 | ||
9878760c RK |
9230 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
9231 | into anything. */ | |
9232 | if (class == GENERAL_REGS || class == BASE_REGS | |
9233 | || (regno >= 0 && INT_REGNO_P (regno))) | |
9234 | return NO_REGS; | |
9235 | ||
9236 | /* Constants, memory, and FP registers can go into FP registers. */ | |
9237 | if ((regno == -1 || FP_REGNO_P (regno)) | |
9238 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
9239 | return NO_REGS; | |
9240 | ||
0ac081f6 AH |
9241 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
9242 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
9243 | && class == ALTIVEC_REGS) | |
9244 | return NO_REGS; | |
9245 | ||
9878760c RK |
9246 | /* We can copy among the CR registers. */ |
9247 | if ((class == CR_REGS || class == CR0_REGS) | |
9248 | && regno >= 0 && CR_REGNO_P (regno)) | |
9249 | return NO_REGS; | |
9250 | ||
9251 | /* Otherwise, we need GENERAL_REGS. */ | |
9252 | return GENERAL_REGS; | |
9253 | } | |
9254 | \f | |
9255 | /* Given a comparison operation, return the bit number in CCR to test. We | |
9256 | know this is a valid comparison. | |
9257 | ||
9258 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
9259 | used instead of %C, so the bits will be in different places. | |
9260 | ||
b4ac57ab | 9261 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
9262 | |
9263 | int | |
a2369ed3 | 9264 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
9265 | { |
9266 | enum rtx_code code = GET_CODE (op); | |
9267 | enum machine_mode cc_mode; | |
9268 | int cc_regnum; | |
9269 | int base_bit; | |
9ebbca7d | 9270 | rtx reg; |
9878760c | 9271 | |
ec8e098d | 9272 | if (!COMPARISON_P (op)) |
9878760c RK |
9273 | return -1; |
9274 | ||
9ebbca7d GK |
9275 | reg = XEXP (op, 0); |
9276 | ||
9277 | if (GET_CODE (reg) != REG | |
9278 | || ! CR_REGNO_P (REGNO (reg))) | |
9279 | abort (); | |
9280 | ||
9281 | cc_mode = GET_MODE (reg); | |
9282 | cc_regnum = REGNO (reg); | |
9283 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 9284 | |
39a10a29 | 9285 | validate_condition_mode (code, cc_mode); |
c5defebb | 9286 | |
b7053a3f GK |
9287 | /* When generating a sCOND operation, only positive conditions are |
9288 | allowed. */ | |
9289 | if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED | |
9290 | && code != GTU && code != LTU) | |
9291 | abort (); | |
9292 | ||
9878760c RK |
9293 | switch (code) |
9294 | { | |
9295 | case NE: | |
9296 | return scc_p ? base_bit + 3 : base_bit + 2; | |
9297 | case EQ: | |
9298 | return base_bit + 2; | |
1c882ea4 | 9299 | case GT: case GTU: case UNLE: |
9878760c | 9300 | return base_bit + 1; |
1c882ea4 | 9301 | case LT: case LTU: case UNGE: |
9878760c | 9302 | return base_bit; |
1c882ea4 GK |
9303 | case ORDERED: case UNORDERED: |
9304 | return base_bit + 3; | |
9878760c RK |
9305 | |
9306 | case GE: case GEU: | |
39a10a29 | 9307 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
9308 | unordered position. So test that bit. For integer, this is ! LT |
9309 | unless this is an scc insn. */ | |
39a10a29 | 9310 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
9311 | |
9312 | case LE: case LEU: | |
39a10a29 | 9313 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 9314 | |
9878760c RK |
9315 | default: |
9316 | abort (); | |
9317 | } | |
9318 | } | |
1ff7789b | 9319 | \f |
8d30c4ee | 9320 | /* Return the GOT register. */ |
1ff7789b MM |
9321 | |
9322 | struct rtx_def * | |
a2369ed3 | 9323 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 9324 | { |
a4f6c312 SS |
9325 | /* The second flow pass currently (June 1999) can't update |
9326 | regs_ever_live without disturbing other parts of the compiler, so | |
9327 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
9328 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
9329 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 9330 | |
8d30c4ee | 9331 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 9332 | |
1ff7789b MM |
9333 | return pic_offset_table_rtx; |
9334 | } | |
a7df97e6 | 9335 | \f |
e2500fed GK |
9336 | /* Function to init struct machine_function. |
9337 | This will be called, via a pointer variable, | |
9338 | from push_function_context. */ | |
a7df97e6 | 9339 | |
e2500fed | 9340 | static struct machine_function * |
863d938c | 9341 | rs6000_init_machine_status (void) |
a7df97e6 | 9342 | { |
e2500fed | 9343 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 9344 | } |
9878760c | 9345 | \f |
0ba1b2ff AM |
9346 | /* These macros test for integers and extract the low-order bits. */ |
9347 | #define INT_P(X) \ | |
9348 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
9349 | && GET_MODE (X) == VOIDmode) | |
9350 | ||
9351 | #define INT_LOWPART(X) \ | |
9352 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
9353 | ||
9354 | int | |
a2369ed3 | 9355 | extract_MB (rtx op) |
0ba1b2ff AM |
9356 | { |
9357 | int i; | |
9358 | unsigned long val = INT_LOWPART (op); | |
9359 | ||
9360 | /* If the high bit is zero, the value is the first 1 bit we find | |
9361 | from the left. */ | |
9362 | if ((val & 0x80000000) == 0) | |
9363 | { | |
9364 | if ((val & 0xffffffff) == 0) | |
9365 | abort (); | |
9366 | ||
9367 | i = 1; | |
9368 | while (((val <<= 1) & 0x80000000) == 0) | |
9369 | ++i; | |
9370 | return i; | |
9371 | } | |
9372 | ||
9373 | /* If the high bit is set and the low bit is not, or the mask is all | |
9374 | 1's, the value is zero. */ | |
9375 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9376 | return 0; | |
9377 | ||
9378 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9379 | from the right. */ | |
9380 | i = 31; | |
9381 | while (((val >>= 1) & 1) != 0) | |
9382 | --i; | |
9383 | ||
9384 | return i; | |
9385 | } | |
9386 | ||
9387 | int | |
a2369ed3 | 9388 | extract_ME (rtx op) |
0ba1b2ff AM |
9389 | { |
9390 | int i; | |
9391 | unsigned long val = INT_LOWPART (op); | |
9392 | ||
9393 | /* If the low bit is zero, the value is the first 1 bit we find from | |
9394 | the right. */ | |
9395 | if ((val & 1) == 0) | |
9396 | { | |
9397 | if ((val & 0xffffffff) == 0) | |
9398 | abort (); | |
9399 | ||
9400 | i = 30; | |
9401 | while (((val >>= 1) & 1) == 0) | |
9402 | --i; | |
9403 | ||
9404 | return i; | |
9405 | } | |
9406 | ||
9407 | /* If the low bit is set and the high bit is not, or the mask is all | |
9408 | 1's, the value is 31. */ | |
9409 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9410 | return 31; | |
9411 | ||
9412 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9413 | from the left. */ | |
9414 | i = 0; | |
9415 | while (((val <<= 1) & 0x80000000) != 0) | |
9416 | ++i; | |
9417 | ||
9418 | return i; | |
9419 | } | |
9420 | ||
c4501e62 JJ |
9421 | /* Locate some local-dynamic symbol still in use by this function |
9422 | so that we can print its name in some tls_ld pattern. */ | |
9423 | ||
9424 | static const char * | |
863d938c | 9425 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
9426 | { |
9427 | rtx insn; | |
9428 | ||
9429 | if (cfun->machine->some_ld_name) | |
9430 | return cfun->machine->some_ld_name; | |
9431 | ||
9432 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
9433 | if (INSN_P (insn) | |
9434 | && for_each_rtx (&PATTERN (insn), | |
9435 | rs6000_get_some_local_dynamic_name_1, 0)) | |
9436 | return cfun->machine->some_ld_name; | |
9437 | ||
9438 | abort (); | |
9439 | } | |
9440 | ||
9441 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
9442 | ||
9443 | static int | |
a2369ed3 | 9444 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
9445 | { |
9446 | rtx x = *px; | |
9447 | ||
9448 | if (GET_CODE (x) == SYMBOL_REF) | |
9449 | { | |
9450 | const char *str = XSTR (x, 0); | |
9451 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
9452 | { | |
9453 | cfun->machine->some_ld_name = str; | |
9454 | return 1; | |
9455 | } | |
9456 | } | |
9457 | ||
9458 | return 0; | |
9459 | } | |
9460 | ||
9878760c RK |
9461 | /* Print an operand. Recognize special options, documented below. */ |
9462 | ||
38c1f2d7 | 9463 | #if TARGET_ELF |
d9407988 | 9464 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 9465 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
9466 | #else |
9467 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 9468 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
9469 | #endif |
9470 | ||
9878760c | 9471 | void |
a2369ed3 | 9472 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
9473 | { |
9474 | int i; | |
a260abc9 | 9475 | HOST_WIDE_INT val; |
0ba1b2ff | 9476 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
9477 | |
9478 | switch (code) | |
9479 | { | |
a8b3aeda | 9480 | case '.': |
a85d226b RK |
9481 | /* Write out an instruction after the call which may be replaced |
9482 | with glue code by the loader. This depends on the AIX version. */ | |
9483 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
9484 | return; |
9485 | ||
81eace42 GK |
9486 | /* %a is output_address. */ |
9487 | ||
9854d9ed RK |
9488 | case 'A': |
9489 | /* If X is a constant integer whose low-order 5 bits are zero, | |
9490 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 9491 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 9492 | writes a trash instruction. */ |
9854d9ed | 9493 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 9494 | putc ('l', file); |
9854d9ed | 9495 | else |
76229ac8 | 9496 | putc ('r', file); |
9854d9ed RK |
9497 | return; |
9498 | ||
9499 | case 'b': | |
e2c953b6 DE |
9500 | /* If constant, low-order 16 bits of constant, unsigned. |
9501 | Otherwise, write normally. */ | |
9502 | if (INT_P (x)) | |
9503 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
9504 | else | |
9505 | print_operand (file, x, 0); | |
cad12a8d RK |
9506 | return; |
9507 | ||
a260abc9 DE |
9508 | case 'B': |
9509 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
9510 | for 64-bit mask direction. */ | |
296b8152 | 9511 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 9512 | return; |
a260abc9 | 9513 | |
81eace42 GK |
9514 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
9515 | output_operand. */ | |
9516 | ||
423c1189 AH |
9517 | case 'c': |
9518 | /* X is a CR register. Print the number of the GT bit of the CR. */ | |
9519 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9520 | output_operand_lossage ("invalid %%E value"); | |
9521 | else | |
9522 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); | |
9523 | return; | |
9524 | ||
9525 | case 'D': | |
9526 | /* Like 'J' but get to the GT bit. */ | |
9527 | if (GET_CODE (x) != REG) | |
9528 | abort (); | |
9529 | ||
9530 | /* Bit 1 is GT bit. */ | |
9531 | i = 4 * (REGNO (x) - CR0_REGNO) + 1; | |
9532 | ||
9533 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
9534 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9535 | return; | |
9536 | ||
9854d9ed | 9537 | case 'E': |
39a10a29 | 9538 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
9539 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
9540 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 9541 | else |
39a10a29 | 9542 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 9543 | return; |
9854d9ed RK |
9544 | |
9545 | case 'f': | |
9546 | /* X is a CR register. Print the shift count needed to move it | |
9547 | to the high-order four bits. */ | |
9548 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9549 | output_operand_lossage ("invalid %%f value"); | |
9550 | else | |
9ebbca7d | 9551 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9552 | return; |
9553 | ||
9554 | case 'F': | |
9555 | /* Similar, but print the count for the rotate in the opposite | |
9556 | direction. */ | |
9557 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9558 | output_operand_lossage ("invalid %%F value"); | |
9559 | else | |
9ebbca7d | 9560 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9561 | return; |
9562 | ||
9563 | case 'G': | |
9564 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 9565 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
9566 | if (GET_CODE (x) != CONST_INT) |
9567 | output_operand_lossage ("invalid %%G value"); | |
9568 | else if (INTVAL (x) >= 0) | |
76229ac8 | 9569 | putc ('z', file); |
9854d9ed | 9570 | else |
76229ac8 | 9571 | putc ('m', file); |
9854d9ed | 9572 | return; |
e2c953b6 | 9573 | |
9878760c | 9574 | case 'h': |
a4f6c312 SS |
9575 | /* If constant, output low-order five bits. Otherwise, write |
9576 | normally. */ | |
9878760c | 9577 | if (INT_P (x)) |
5f59ecb7 | 9578 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
9579 | else |
9580 | print_operand (file, x, 0); | |
9581 | return; | |
9582 | ||
64305719 | 9583 | case 'H': |
a4f6c312 SS |
9584 | /* If constant, output low-order six bits. Otherwise, write |
9585 | normally. */ | |
64305719 | 9586 | if (INT_P (x)) |
5f59ecb7 | 9587 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
9588 | else |
9589 | print_operand (file, x, 0); | |
9590 | return; | |
9591 | ||
9854d9ed RK |
9592 | case 'I': |
9593 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 9594 | if (INT_P (x)) |
76229ac8 | 9595 | putc ('i', file); |
9878760c RK |
9596 | return; |
9597 | ||
9854d9ed RK |
9598 | case 'j': |
9599 | /* Write the bit number in CCR for jump. */ | |
9600 | i = ccr_bit (x, 0); | |
9601 | if (i == -1) | |
9602 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 9603 | else |
9854d9ed | 9604 | fprintf (file, "%d", i); |
9878760c RK |
9605 | return; |
9606 | ||
9854d9ed RK |
9607 | case 'J': |
9608 | /* Similar, but add one for shift count in rlinm for scc and pass | |
9609 | scc flag to `ccr_bit'. */ | |
9610 | i = ccr_bit (x, 1); | |
9611 | if (i == -1) | |
9612 | output_operand_lossage ("invalid %%J code"); | |
9613 | else | |
a0466a68 RK |
9614 | /* If we want bit 31, write a shift count of zero, not 32. */ |
9615 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
9616 | return; |
9617 | ||
9854d9ed RK |
9618 | case 'k': |
9619 | /* X must be a constant. Write the 1's complement of the | |
9620 | constant. */ | |
9878760c | 9621 | if (! INT_P (x)) |
9854d9ed | 9622 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
9623 | else |
9624 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
9625 | return; |
9626 | ||
81eace42 | 9627 | case 'K': |
9ebbca7d GK |
9628 | /* X must be a symbolic constant on ELF. Write an |
9629 | expression suitable for an 'addi' that adds in the low 16 | |
9630 | bits of the MEM. */ | |
9631 | if (GET_CODE (x) != CONST) | |
9632 | { | |
9633 | print_operand_address (file, x); | |
9634 | fputs ("@l", file); | |
9635 | } | |
9636 | else | |
9637 | { | |
9638 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
9639 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
9640 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
9641 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 9642 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
9643 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
9644 | fputs ("@l", file); | |
ed8d2920 MM |
9645 | /* For GNU as, there must be a non-alphanumeric character |
9646 | between 'l' and the number. The '-' is added by | |
9647 | print_operand() already. */ | |
9648 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
9649 | fputs ("+", file); | |
9ebbca7d GK |
9650 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
9651 | } | |
81eace42 GK |
9652 | return; |
9653 | ||
9654 | /* %l is output_asm_label. */ | |
9ebbca7d | 9655 | |
9854d9ed RK |
9656 | case 'L': |
9657 | /* Write second word of DImode or DFmode reference. Works on register | |
9658 | or non-indexed memory only. */ | |
9659 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 9660 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
9661 | else if (GET_CODE (x) == MEM) |
9662 | { | |
9663 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 9664 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
9665 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
9666 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
9667 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
9668 | UNITS_PER_WORD)); | |
9854d9ed | 9669 | else |
d7624dc0 RK |
9670 | output_address (XEXP (adjust_address_nv (x, SImode, |
9671 | UNITS_PER_WORD), | |
9672 | 0)); | |
ed8908e7 | 9673 | |
ba5e43aa | 9674 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9675 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9676 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 9677 | } |
9878760c | 9678 | return; |
9854d9ed | 9679 | |
9878760c RK |
9680 | case 'm': |
9681 | /* MB value for a mask operand. */ | |
b1765bde | 9682 | if (! mask_operand (x, SImode)) |
9878760c RK |
9683 | output_operand_lossage ("invalid %%m value"); |
9684 | ||
0ba1b2ff | 9685 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
9686 | return; |
9687 | ||
9688 | case 'M': | |
9689 | /* ME value for a mask operand. */ | |
b1765bde | 9690 | if (! mask_operand (x, SImode)) |
a260abc9 | 9691 | output_operand_lossage ("invalid %%M value"); |
9878760c | 9692 | |
0ba1b2ff | 9693 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
9694 | return; |
9695 | ||
81eace42 GK |
9696 | /* %n outputs the negative of its operand. */ |
9697 | ||
9878760c RK |
9698 | case 'N': |
9699 | /* Write the number of elements in the vector times 4. */ | |
9700 | if (GET_CODE (x) != PARALLEL) | |
9701 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
9702 | else |
9703 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
9704 | return; |
9705 | ||
9706 | case 'O': | |
9707 | /* Similar, but subtract 1 first. */ | |
9708 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 9709 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
9710 | else |
9711 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
9712 | return; |
9713 | ||
9854d9ed RK |
9714 | case 'p': |
9715 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
9716 | if (! INT_P (x) | |
2bfcf297 | 9717 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
9718 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
9719 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
9720 | else |
9721 | fprintf (file, "%d", i); | |
9854d9ed RK |
9722 | return; |
9723 | ||
9878760c RK |
9724 | case 'P': |
9725 | /* The operand must be an indirect memory reference. The result | |
8bb418a3 | 9726 | is the register name. */ |
9878760c RK |
9727 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
9728 | || REGNO (XEXP (x, 0)) >= 32) | |
9729 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 | 9730 | else |
8bb418a3 | 9731 | fprintf (file, "%s", reg_names[REGNO (XEXP (x, 0))]); |
9878760c RK |
9732 | return; |
9733 | ||
dfbdccdb GK |
9734 | case 'q': |
9735 | /* This outputs the logical code corresponding to a boolean | |
9736 | expression. The expression may have one or both operands | |
39a10a29 GK |
9737 | negated (if one, only the first one). For condition register |
9738 | logical operations, it will also treat the negated | |
9739 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 9740 | { |
63bc1d05 | 9741 | const char *const *t = 0; |
dfbdccdb GK |
9742 | const char *s; |
9743 | enum rtx_code code = GET_CODE (x); | |
9744 | static const char * const tbl[3][3] = { | |
9745 | { "and", "andc", "nor" }, | |
9746 | { "or", "orc", "nand" }, | |
9747 | { "xor", "eqv", "xor" } }; | |
9748 | ||
9749 | if (code == AND) | |
9750 | t = tbl[0]; | |
9751 | else if (code == IOR) | |
9752 | t = tbl[1]; | |
9753 | else if (code == XOR) | |
9754 | t = tbl[2]; | |
9755 | else | |
9756 | output_operand_lossage ("invalid %%q value"); | |
9757 | ||
9758 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
9759 | s = t[0]; | |
9760 | else | |
9761 | { | |
9762 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
9763 | s = t[2]; | |
9764 | else | |
9765 | s = t[1]; | |
9766 | } | |
9767 | ||
9768 | fputs (s, file); | |
9769 | } | |
9770 | return; | |
9771 | ||
2c4a9cff DE |
9772 | case 'Q': |
9773 | if (TARGET_MFCRF) | |
3b6ce0af | 9774 | fputc (',', file); |
5efb1046 | 9775 | /* FALLTHRU */ |
2c4a9cff DE |
9776 | else |
9777 | return; | |
9778 | ||
9854d9ed RK |
9779 | case 'R': |
9780 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
9781 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9782 | output_operand_lossage ("invalid %%R value"); | |
9783 | else | |
9ebbca7d | 9784 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 9785 | return; |
9854d9ed RK |
9786 | |
9787 | case 's': | |
9788 | /* Low 5 bits of 32 - value */ | |
9789 | if (! INT_P (x)) | |
9790 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
9791 | else |
9792 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 9793 | return; |
9854d9ed | 9794 | |
a260abc9 | 9795 | case 'S': |
0ba1b2ff | 9796 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
9797 | CONST_INT 32-bit mask is considered sign-extended so any |
9798 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 9799 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
9800 | output_operand_lossage ("invalid %%S value"); |
9801 | ||
0ba1b2ff | 9802 | uval = INT_LOWPART (x); |
a260abc9 | 9803 | |
0ba1b2ff | 9804 | if (uval & 1) /* Clear Left */ |
a260abc9 | 9805 | { |
f099d360 GK |
9806 | #if HOST_BITS_PER_WIDE_INT > 64 |
9807 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9808 | #endif | |
0ba1b2ff | 9809 | i = 64; |
a260abc9 | 9810 | } |
0ba1b2ff | 9811 | else /* Clear Right */ |
a260abc9 | 9812 | { |
0ba1b2ff | 9813 | uval = ~uval; |
f099d360 GK |
9814 | #if HOST_BITS_PER_WIDE_INT > 64 |
9815 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9816 | #endif | |
0ba1b2ff | 9817 | i = 63; |
a260abc9 | 9818 | } |
0ba1b2ff AM |
9819 | while (uval != 0) |
9820 | --i, uval >>= 1; | |
9821 | if (i < 0) | |
9822 | abort (); | |
9823 | fprintf (file, "%d", i); | |
9824 | return; | |
a260abc9 | 9825 | |
a3170dc6 AH |
9826 | case 't': |
9827 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
9828 | if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) | |
9829 | abort (); | |
9830 | ||
9831 | /* Bit 3 is OV bit. */ | |
9832 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
9833 | ||
9834 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
9835 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9836 | return; | |
9837 | ||
cccf3bdc DE |
9838 | case 'T': |
9839 | /* Print the symbolic name of a branch target register. */ | |
9840 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
9841 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
9842 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 9843 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
9844 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
9845 | else | |
9846 | fputs ("ctr", file); | |
9847 | return; | |
9848 | ||
9854d9ed | 9849 | case 'u': |
802a0058 | 9850 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
9851 | if (! INT_P (x)) |
9852 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
9853 | else |
9854 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
9855 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
9856 | return; |
9857 | ||
802a0058 MM |
9858 | case 'v': |
9859 | /* High-order 16 bits of constant for use in signed operand. */ | |
9860 | if (! INT_P (x)) | |
9861 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 9862 | else |
134c32f6 DE |
9863 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
9864 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9865 | return; | |
802a0058 | 9866 | |
9854d9ed RK |
9867 | case 'U': |
9868 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
9869 | if (GET_CODE (x) == MEM | |
9870 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
9871 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 9872 | putc ('u', file); |
9854d9ed | 9873 | return; |
9878760c | 9874 | |
e0cd0770 JC |
9875 | case 'V': |
9876 | /* Print the trap code for this operand. */ | |
9877 | switch (GET_CODE (x)) | |
9878 | { | |
9879 | case EQ: | |
9880 | fputs ("eq", file); /* 4 */ | |
9881 | break; | |
9882 | case NE: | |
9883 | fputs ("ne", file); /* 24 */ | |
9884 | break; | |
9885 | case LT: | |
9886 | fputs ("lt", file); /* 16 */ | |
9887 | break; | |
9888 | case LE: | |
9889 | fputs ("le", file); /* 20 */ | |
9890 | break; | |
9891 | case GT: | |
9892 | fputs ("gt", file); /* 8 */ | |
9893 | break; | |
9894 | case GE: | |
9895 | fputs ("ge", file); /* 12 */ | |
9896 | break; | |
9897 | case LTU: | |
9898 | fputs ("llt", file); /* 2 */ | |
9899 | break; | |
9900 | case LEU: | |
9901 | fputs ("lle", file); /* 6 */ | |
9902 | break; | |
9903 | case GTU: | |
9904 | fputs ("lgt", file); /* 1 */ | |
9905 | break; | |
9906 | case GEU: | |
9907 | fputs ("lge", file); /* 5 */ | |
9908 | break; | |
9909 | default: | |
9910 | abort (); | |
9911 | } | |
9912 | break; | |
9913 | ||
9854d9ed RK |
9914 | case 'w': |
9915 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
9916 | normally. */ | |
9917 | if (INT_P (x)) | |
5f59ecb7 DE |
9918 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
9919 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
9920 | else |
9921 | print_operand (file, x, 0); | |
9878760c RK |
9922 | return; |
9923 | ||
9854d9ed | 9924 | case 'W': |
e2c953b6 | 9925 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
9926 | val = (GET_CODE (x) == CONST_INT |
9927 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
9928 | ||
9929 | if (val < 0) | |
9930 | i = -1; | |
9854d9ed | 9931 | else |
e2c953b6 DE |
9932 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
9933 | if ((val <<= 1) < 0) | |
9934 | break; | |
9935 | ||
9936 | #if HOST_BITS_PER_WIDE_INT == 32 | |
9937 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
9938 | i += 32; /* zero-extend high-part was all 0's */ | |
9939 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
9940 | { | |
9941 | val = CONST_DOUBLE_LOW (x); | |
9942 | ||
9943 | if (val == 0) | |
a4f6c312 | 9944 | abort (); |
e2c953b6 DE |
9945 | else if (val < 0) |
9946 | --i; | |
9947 | else | |
9948 | for ( ; i < 64; i++) | |
9949 | if ((val <<= 1) < 0) | |
9950 | break; | |
9951 | } | |
9952 | #endif | |
9953 | ||
9954 | fprintf (file, "%d", i + 1); | |
9854d9ed | 9955 | return; |
9878760c | 9956 | |
9854d9ed RK |
9957 | case 'X': |
9958 | if (GET_CODE (x) == MEM | |
4d588c14 | 9959 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 9960 | putc ('x', file); |
9854d9ed | 9961 | return; |
9878760c | 9962 | |
9854d9ed RK |
9963 | case 'Y': |
9964 | /* Like 'L', for third word of TImode */ | |
9965 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 9966 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 9967 | else if (GET_CODE (x) == MEM) |
9878760c | 9968 | { |
9854d9ed RK |
9969 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
9970 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 9971 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 9972 | else |
d7624dc0 | 9973 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 9974 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9975 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9976 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
9977 | } |
9978 | return; | |
9854d9ed | 9979 | |
9878760c | 9980 | case 'z': |
b4ac57ab RS |
9981 | /* X is a SYMBOL_REF. Write out the name preceded by a |
9982 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
9983 | names. If we are configured for System V (or the embedded ABI) on |
9984 | the PowerPC, do not emit the period, since those systems do not use | |
9985 | TOCs and the like. */ | |
9878760c RK |
9986 | if (GET_CODE (x) != SYMBOL_REF) |
9987 | abort (); | |
9988 | ||
9bf6462a AP |
9989 | /* Mark the decl as referenced so that cgraph will output the function. */ |
9990 | if (SYMBOL_REF_DECL (x)) | |
9991 | mark_decl_referenced (SYMBOL_REF_DECL (x)); | |
9992 | ||
b6c9286a MM |
9993 | if (XSTR (x, 0)[0] != '.') |
9994 | { | |
9995 | switch (DEFAULT_ABI) | |
9996 | { | |
9997 | default: | |
9998 | abort (); | |
9999 | ||
10000 | case ABI_AIX: | |
10001 | putc ('.', file); | |
10002 | break; | |
10003 | ||
10004 | case ABI_V4: | |
ee890fe2 | 10005 | case ABI_DARWIN: |
b6c9286a | 10006 | break; |
b6c9286a MM |
10007 | } |
10008 | } | |
f9da97f0 AP |
10009 | /* For macho, we need to check it see if we need a stub. */ |
10010 | if (TARGET_MACHO) | |
10011 | { | |
10012 | const char *name = XSTR (x, 0); | |
a031e781 | 10013 | #if TARGET_MACHO |
3b48085e AP |
10014 | if (MACHOPIC_INDIRECT |
10015 | && machopic_classify_name (name) == MACHOPIC_UNDEFINED_FUNCTION) | |
f9da97f0 AP |
10016 | name = machopic_stub_name (name); |
10017 | #endif | |
10018 | assemble_name (file, name); | |
10019 | } | |
10020 | else if (TARGET_AIX) | |
9739c90c JJ |
10021 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
10022 | else | |
10023 | assemble_name (file, XSTR (x, 0)); | |
9878760c RK |
10024 | return; |
10025 | ||
9854d9ed RK |
10026 | case 'Z': |
10027 | /* Like 'L', for last word of TImode. */ | |
10028 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 10029 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
10030 | else if (GET_CODE (x) == MEM) |
10031 | { | |
10032 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
10033 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10034 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 10035 | else |
d7624dc0 | 10036 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 10037 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10038 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10039 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 10040 | } |
5c23c401 | 10041 | return; |
0ac081f6 | 10042 | |
a3170dc6 | 10043 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
10044 | case 'y': |
10045 | { | |
10046 | rtx tmp; | |
10047 | ||
10048 | if (GET_CODE (x) != MEM) | |
10049 | abort (); | |
10050 | ||
10051 | tmp = XEXP (x, 0); | |
10052 | ||
993f19a8 | 10053 | if (TARGET_E500) |
a3170dc6 AH |
10054 | { |
10055 | /* Handle [reg]. */ | |
10056 | if (GET_CODE (tmp) == REG) | |
10057 | { | |
10058 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
10059 | break; | |
10060 | } | |
10061 | /* Handle [reg+UIMM]. */ | |
10062 | else if (GET_CODE (tmp) == PLUS && | |
10063 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
10064 | { | |
10065 | int x; | |
10066 | ||
10067 | if (GET_CODE (XEXP (tmp, 0)) != REG) | |
10068 | abort (); | |
10069 | ||
10070 | x = INTVAL (XEXP (tmp, 1)); | |
10071 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
10072 | break; | |
10073 | } | |
10074 | ||
10075 | /* Fall through. Must be [reg+reg]. */ | |
10076 | } | |
0ac081f6 | 10077 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 10078 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
10079 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
10080 | { | |
10081 | if (REGNO (XEXP (tmp, 0)) == 0) | |
10082 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
10083 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
10084 | else | |
10085 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
10086 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
10087 | } | |
10088 | else | |
10089 | abort (); | |
10090 | break; | |
10091 | } | |
9854d9ed | 10092 | |
9878760c RK |
10093 | case 0: |
10094 | if (GET_CODE (x) == REG) | |
10095 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
10096 | else if (GET_CODE (x) == MEM) | |
10097 | { | |
10098 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
10099 | know the width from the mode. */ | |
10100 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
10101 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
10102 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10103 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
10104 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
10105 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10106 | else |
a54d04b7 | 10107 | output_address (XEXP (x, 0)); |
9878760c RK |
10108 | } |
10109 | else | |
a54d04b7 | 10110 | output_addr_const (file, x); |
a85d226b | 10111 | return; |
9878760c | 10112 | |
c4501e62 JJ |
10113 | case '&': |
10114 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
10115 | return; | |
10116 | ||
9878760c RK |
10117 | default: |
10118 | output_operand_lossage ("invalid %%xn code"); | |
10119 | } | |
10120 | } | |
10121 | \f | |
10122 | /* Print the address of an operand. */ | |
10123 | ||
10124 | void | |
a2369ed3 | 10125 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
10126 | { |
10127 | if (GET_CODE (x) == REG) | |
4697a36c | 10128 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
10129 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
10130 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
10131 | { |
10132 | output_addr_const (file, x); | |
ba5e43aa | 10133 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10134 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10135 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 10136 | else if (TARGET_TOC) |
a4f6c312 | 10137 | abort (); |
9878760c RK |
10138 | } |
10139 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
10140 | { | |
10141 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
10142 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
10143 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 10144 | else |
4697a36c MM |
10145 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
10146 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
10147 | } |
10148 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
10149 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
10150 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
10151 | #if TARGET_ELF |
10152 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
10153 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
10154 | { |
10155 | output_addr_const (file, XEXP (x, 1)); | |
10156 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10157 | } | |
c859cda6 DJ |
10158 | #endif |
10159 | #if TARGET_MACHO | |
10160 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
10161 | && CONSTANT_P (XEXP (x, 1))) | |
10162 | { | |
10163 | fprintf (file, "lo16("); | |
10164 | output_addr_const (file, XEXP (x, 1)); | |
10165 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10166 | } | |
3cb999d8 | 10167 | #endif |
4d588c14 | 10168 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 10169 | { |
2bfcf297 | 10170 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 10171 | { |
2bfcf297 DB |
10172 | rtx contains_minus = XEXP (x, 1); |
10173 | rtx minus, symref; | |
10174 | const char *name; | |
9ebbca7d GK |
10175 | |
10176 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 10177 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
10178 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
10179 | contains_minus = XEXP (contains_minus, 0); | |
10180 | ||
2bfcf297 DB |
10181 | minus = XEXP (contains_minus, 0); |
10182 | symref = XEXP (minus, 0); | |
10183 | XEXP (contains_minus, 0) = symref; | |
10184 | if (TARGET_ELF) | |
10185 | { | |
10186 | char *newname; | |
10187 | ||
10188 | name = XSTR (symref, 0); | |
10189 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
10190 | strcpy (newname, name); | |
10191 | strcat (newname, "@toc"); | |
10192 | XSTR (symref, 0) = newname; | |
10193 | } | |
10194 | output_addr_const (file, XEXP (x, 1)); | |
10195 | if (TARGET_ELF) | |
10196 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
10197 | XEXP (contains_minus, 0) = minus; |
10198 | } | |
10199 | else | |
10200 | output_addr_const (file, XEXP (x, 1)); | |
10201 | ||
10202 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
10203 | } | |
9878760c RK |
10204 | else |
10205 | abort (); | |
10206 | } | |
10207 | \f | |
88cad84b | 10208 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
10209 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
10210 | is defined. It also needs to handle DI-mode objects on 64-bit | |
10211 | targets. */ | |
10212 | ||
10213 | static bool | |
a2369ed3 | 10214 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
10215 | { |
10216 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
10217 | /* Special handling for SI values. */ | |
10218 | if (size == 4 && aligned_p) | |
10219 | { | |
a2369ed3 | 10220 | extern int in_toc_section (void); |
301d03af RS |
10221 | static int recurse = 0; |
10222 | ||
10223 | /* For -mrelocatable, we mark all addresses that need to be fixed up | |
10224 | in the .fixup section. */ | |
10225 | if (TARGET_RELOCATABLE | |
10226 | && !in_toc_section () | |
10227 | && !in_text_section () | |
642af3be | 10228 | && !in_unlikely_text_section () |
301d03af RS |
10229 | && !recurse |
10230 | && GET_CODE (x) != CONST_INT | |
10231 | && GET_CODE (x) != CONST_DOUBLE | |
10232 | && CONSTANT_P (x)) | |
10233 | { | |
10234 | char buf[256]; | |
10235 | ||
10236 | recurse = 1; | |
10237 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
10238 | fixuplabelno++; | |
10239 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
10240 | fprintf (asm_out_file, "\t.long\t("); | |
10241 | output_addr_const (asm_out_file, x); | |
10242 | fprintf (asm_out_file, ")@fixup\n"); | |
10243 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
10244 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
10245 | fprintf (asm_out_file, "\t.long\t"); | |
10246 | assemble_name (asm_out_file, buf); | |
10247 | fprintf (asm_out_file, "\n\t.previous\n"); | |
10248 | recurse = 0; | |
10249 | return true; | |
10250 | } | |
10251 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
10252 | address into the address of the descriptor, not the function | |
10253 | itself. */ | |
10254 | else if (GET_CODE (x) == SYMBOL_REF | |
10255 | && XSTR (x, 0)[0] == '.' | |
10256 | && DEFAULT_ABI == ABI_AIX) | |
10257 | { | |
10258 | const char *name = XSTR (x, 0); | |
10259 | while (*name == '.') | |
10260 | name++; | |
10261 | ||
10262 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
10263 | return true; | |
10264 | } | |
10265 | } | |
10266 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
10267 | return default_assemble_integer (x, size, aligned_p); | |
10268 | } | |
93638d7a AM |
10269 | |
10270 | #ifdef HAVE_GAS_HIDDEN | |
10271 | /* Emit an assembler directive to set symbol visibility for DECL to | |
10272 | VISIBILITY_TYPE. */ | |
10273 | ||
5add3202 | 10274 | static void |
a2369ed3 | 10275 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 10276 | { |
93638d7a AM |
10277 | /* Functions need to have their entry point symbol visibility set as |
10278 | well as their descriptor symbol visibility. */ | |
10279 | if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL) | |
10280 | { | |
25fdb4dc RH |
10281 | static const char * const visibility_types[] = { |
10282 | NULL, "internal", "hidden", "protected" | |
10283 | }; | |
10284 | ||
10285 | const char *name, *type; | |
93638d7a AM |
10286 | |
10287 | name = ((* targetm.strip_name_encoding) | |
10288 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 10289 | type = visibility_types[vis]; |
93638d7a | 10290 | |
25fdb4dc RH |
10291 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
10292 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 10293 | } |
25fdb4dc RH |
10294 | else |
10295 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
10296 | } |
10297 | #endif | |
301d03af | 10298 | \f |
39a10a29 | 10299 | enum rtx_code |
a2369ed3 | 10300 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
10301 | { |
10302 | /* Reversal of FP compares takes care -- an ordered compare | |
10303 | becomes an unordered compare and vice versa. */ | |
bc9ec0e0 GK |
10304 | if (mode == CCFPmode |
10305 | && (!flag_finite_math_only | |
10306 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
10307 | || code == UNEQ || code == LTGT)) | |
bab6226b | 10308 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 10309 | else |
bab6226b | 10310 | return reverse_condition (code); |
39a10a29 GK |
10311 | } |
10312 | ||
39a10a29 GK |
10313 | /* Generate a compare for CODE. Return a brand-new rtx that |
10314 | represents the result of the compare. */ | |
a4f6c312 | 10315 | |
39a10a29 | 10316 | static rtx |
a2369ed3 | 10317 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
10318 | { |
10319 | enum machine_mode comp_mode; | |
10320 | rtx compare_result; | |
10321 | ||
10322 | if (rs6000_compare_fp_p) | |
10323 | comp_mode = CCFPmode; | |
10324 | else if (code == GTU || code == LTU | |
10325 | || code == GEU || code == LEU) | |
10326 | comp_mode = CCUNSmode; | |
10327 | else | |
10328 | comp_mode = CCmode; | |
10329 | ||
10330 | /* First, the compare. */ | |
10331 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
10332 | |
10333 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
10334 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
10335 | && rs6000_compare_fp_p) | |
a3170dc6 AH |
10336 | { |
10337 | rtx cmp, or1, or2, or_result, compare_result2; | |
10338 | ||
423c1189 AH |
10339 | /* Note: The E500 comparison instructions set the GT bit (x + |
10340 | 1), on success. This explains the mess. */ | |
10341 | ||
a3170dc6 AH |
10342 | switch (code) |
10343 | { | |
423c1189 | 10344 | case EQ: case UNEQ: case NE: case LTGT: |
bc9ec0e0 | 10345 | cmp = flag_finite_math_only |
a3170dc6 AH |
10346 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, |
10347 | rs6000_compare_op1) | |
10348 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
10349 | rs6000_compare_op1); | |
10350 | break; | |
423c1189 | 10351 | case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: |
bc9ec0e0 | 10352 | cmp = flag_finite_math_only |
a3170dc6 AH |
10353 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, |
10354 | rs6000_compare_op1) | |
10355 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
10356 | rs6000_compare_op1); | |
10357 | break; | |
423c1189 | 10358 | case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: |
bc9ec0e0 | 10359 | cmp = flag_finite_math_only |
a3170dc6 AH |
10360 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, |
10361 | rs6000_compare_op1) | |
10362 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
10363 | rs6000_compare_op1); | |
10364 | break; | |
10365 | default: | |
10366 | abort (); | |
10367 | } | |
10368 | ||
10369 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
10370 | if (code == LE || code == GE || code == LEU || code == GEU) | |
10371 | { | |
a3170dc6 AH |
10372 | emit_insn (cmp); |
10373 | ||
10374 | switch (code) | |
10375 | { | |
10376 | case LE: code = LT; break; | |
10377 | case GE: code = GT; break; | |
10378 | case LEU: code = LT; break; | |
10379 | case GEU: code = GT; break; | |
10380 | default: abort (); | |
10381 | } | |
10382 | ||
10383 | or1 = gen_reg_rtx (SImode); | |
10384 | or2 = gen_reg_rtx (SImode); | |
10385 | or_result = gen_reg_rtx (CCEQmode); | |
10386 | compare_result2 = gen_reg_rtx (CCFPmode); | |
10387 | ||
10388 | /* Do the EQ. */ | |
bc9ec0e0 | 10389 | cmp = flag_finite_math_only |
a3170dc6 AH |
10390 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, |
10391 | rs6000_compare_op1) | |
10392 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
10393 | rs6000_compare_op1); | |
10394 | emit_insn (cmp); | |
10395 | ||
423c1189 AH |
10396 | or1 = gen_rtx_GT (SImode, compare_result, const0_rtx); |
10397 | or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx); | |
a3170dc6 AH |
10398 | |
10399 | /* OR them together. */ | |
10400 | cmp = gen_rtx_SET (VOIDmode, or_result, | |
10401 | gen_rtx_COMPARE (CCEQmode, | |
10402 | gen_rtx_IOR (SImode, or1, or2), | |
10403 | const_true_rtx)); | |
10404 | compare_result = or_result; | |
10405 | code = EQ; | |
10406 | } | |
10407 | else | |
10408 | { | |
a3170dc6 | 10409 | if (code == NE || code == LTGT) |
a3170dc6 | 10410 | code = NE; |
423c1189 AH |
10411 | else |
10412 | code = EQ; | |
a3170dc6 AH |
10413 | } |
10414 | ||
10415 | emit_insn (cmp); | |
10416 | } | |
10417 | else | |
10418 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
10419 | gen_rtx_COMPARE (comp_mode, | |
10420 | rs6000_compare_op0, | |
10421 | rs6000_compare_op1))); | |
39a10a29 | 10422 | |
ca5adc63 | 10423 | /* Some kinds of FP comparisons need an OR operation; |
bc9ec0e0 | 10424 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 10425 | if (rs6000_compare_fp_p |
bc9ec0e0 | 10426 | && ! flag_finite_math_only |
993f19a8 | 10427 | && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) |
39a10a29 GK |
10428 | && (code == LE || code == GE |
10429 | || code == UNEQ || code == LTGT | |
10430 | || code == UNGT || code == UNLT)) | |
10431 | { | |
10432 | enum rtx_code or1, or2; | |
10433 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
10434 | rtx or_result = gen_reg_rtx (CCEQmode); | |
10435 | ||
10436 | switch (code) | |
10437 | { | |
10438 | case LE: or1 = LT; or2 = EQ; break; | |
10439 | case GE: or1 = GT; or2 = EQ; break; | |
10440 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
10441 | case LTGT: or1 = LT; or2 = GT; break; | |
10442 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
10443 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
10444 | default: abort (); | |
10445 | } | |
10446 | validate_condition_mode (or1, comp_mode); | |
10447 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
10448 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
10449 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
10450 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
10451 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
10452 | const_true_rtx); | |
10453 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
10454 | ||
10455 | compare_result = or_result; | |
10456 | code = EQ; | |
10457 | } | |
10458 | ||
10459 | validate_condition_mode (code, GET_MODE (compare_result)); | |
10460 | ||
1c563bed | 10461 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
10462 | } |
10463 | ||
10464 | ||
10465 | /* Emit the RTL for an sCOND pattern. */ | |
10466 | ||
10467 | void | |
a2369ed3 | 10468 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
10469 | { |
10470 | rtx condition_rtx; | |
10471 | enum machine_mode op_mode; | |
b7053a3f | 10472 | enum rtx_code cond_code; |
39a10a29 GK |
10473 | |
10474 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
10475 | cond_code = GET_CODE (condition_rtx); |
10476 | ||
423c1189 AH |
10477 | if (TARGET_E500 && rs6000_compare_fp_p |
10478 | && !TARGET_FPRS && TARGET_HARD_FLOAT) | |
10479 | { | |
10480 | rtx t; | |
10481 | ||
10482 | PUT_MODE (condition_rtx, SImode); | |
10483 | t = XEXP (condition_rtx, 0); | |
10484 | ||
10485 | if (cond_code != NE && cond_code != EQ) | |
10486 | abort (); | |
10487 | ||
10488 | if (cond_code == NE) | |
10489 | emit_insn (gen_e500_flip_gt_bit (t, t)); | |
10490 | ||
10491 | emit_insn (gen_move_from_CR_gt_bit (result, t)); | |
10492 | return; | |
10493 | } | |
10494 | ||
b7053a3f GK |
10495 | if (cond_code == NE |
10496 | || cond_code == GE || cond_code == LE | |
10497 | || cond_code == GEU || cond_code == LEU | |
10498 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
10499 | { | |
10500 | rtx not_result = gen_reg_rtx (CCEQmode); | |
10501 | rtx not_op, rev_cond_rtx; | |
10502 | enum machine_mode cc_mode; | |
10503 | ||
10504 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); | |
10505 | ||
1c563bed | 10506 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 10507 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
10508 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
10509 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
10510 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
10511 | } | |
39a10a29 GK |
10512 | |
10513 | op_mode = GET_MODE (rs6000_compare_op0); | |
10514 | if (op_mode == VOIDmode) | |
10515 | op_mode = GET_MODE (rs6000_compare_op1); | |
10516 | ||
10517 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10518 | { | |
10519 | PUT_MODE (condition_rtx, DImode); | |
10520 | convert_move (result, condition_rtx, 0); | |
10521 | } | |
10522 | else | |
10523 | { | |
10524 | PUT_MODE (condition_rtx, SImode); | |
10525 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
10526 | } | |
10527 | } | |
10528 | ||
39a10a29 GK |
10529 | /* Emit a branch of kind CODE to location LOC. */ |
10530 | ||
10531 | void | |
a2369ed3 | 10532 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
10533 | { |
10534 | rtx condition_rtx, loc_ref; | |
10535 | ||
10536 | condition_rtx = rs6000_generate_compare (code); | |
10537 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
10538 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
10539 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
10540 | loc_ref, pc_rtx))); | |
10541 | } | |
10542 | ||
12a4e8c5 GK |
10543 | /* Return the string to output a conditional branch to LABEL, which is |
10544 | the operand number of the label, or -1 if the branch is really a | |
10545 | conditional return. | |
10546 | ||
10547 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
10548 | condition code register and its mode specifies what kind of | |
10549 | comparison we made. | |
10550 | ||
a0ab749a | 10551 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
10552 | |
10553 | INSN is the insn. */ | |
10554 | ||
10555 | char * | |
a2369ed3 | 10556 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
10557 | { |
10558 | static char string[64]; | |
10559 | enum rtx_code code = GET_CODE (op); | |
10560 | rtx cc_reg = XEXP (op, 0); | |
10561 | enum machine_mode mode = GET_MODE (cc_reg); | |
10562 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 10563 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
10564 | int really_reversed = reversed ^ need_longbranch; |
10565 | char *s = string; | |
10566 | const char *ccode; | |
10567 | const char *pred; | |
10568 | rtx note; | |
10569 | ||
39a10a29 GK |
10570 | validate_condition_mode (code, mode); |
10571 | ||
10572 | /* Work out which way this really branches. We could use | |
10573 | reverse_condition_maybe_unordered here always but this | |
10574 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 10575 | if (really_reversed) |
de40e1df DJ |
10576 | { |
10577 | /* Reversal of FP compares takes care -- an ordered compare | |
10578 | becomes an unordered compare and vice versa. */ | |
10579 | if (mode == CCFPmode) | |
10580 | code = reverse_condition_maybe_unordered (code); | |
10581 | else | |
10582 | code = reverse_condition (code); | |
10583 | } | |
12a4e8c5 | 10584 | |
993f19a8 | 10585 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
10586 | { |
10587 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
10588 | to the GT bit. */ | |
10589 | if (code == EQ) | |
10590 | /* Opposite of GT. */ | |
a3170dc6 | 10591 | code = GT; |
423c1189 AH |
10592 | else if (code == NE) |
10593 | code = UNLE; | |
a3170dc6 AH |
10594 | else |
10595 | abort (); | |
10596 | } | |
10597 | ||
39a10a29 | 10598 | switch (code) |
12a4e8c5 GK |
10599 | { |
10600 | /* Not all of these are actually distinct opcodes, but | |
10601 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
10602 | case NE: case LTGT: |
10603 | ccode = "ne"; break; | |
10604 | case EQ: case UNEQ: | |
10605 | ccode = "eq"; break; | |
10606 | case GE: case GEU: | |
10607 | ccode = "ge"; break; | |
10608 | case GT: case GTU: case UNGT: | |
10609 | ccode = "gt"; break; | |
10610 | case LE: case LEU: | |
10611 | ccode = "le"; break; | |
10612 | case LT: case LTU: case UNLT: | |
10613 | ccode = "lt"; break; | |
12a4e8c5 GK |
10614 | case UNORDERED: ccode = "un"; break; |
10615 | case ORDERED: ccode = "nu"; break; | |
10616 | case UNGE: ccode = "nl"; break; | |
10617 | case UNLE: ccode = "ng"; break; | |
10618 | default: | |
a4f6c312 | 10619 | abort (); |
12a4e8c5 GK |
10620 | } |
10621 | ||
94a54f47 GK |
10622 | /* Maybe we have a guess as to how likely the branch is. |
10623 | The old mnemonics don't have a way to specify this information. */ | |
f4857b9b | 10624 | pred = ""; |
12a4e8c5 GK |
10625 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
10626 | if (note != NULL_RTX) | |
10627 | { | |
10628 | /* PROB is the difference from 50%. */ | |
10629 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
10630 | |
10631 | /* Only hint for highly probable/improbable branches on newer | |
10632 | cpus as static prediction overrides processor dynamic | |
10633 | prediction. For older cpus we may as well always hint, but | |
10634 | assume not taken for branches that are very close to 50% as a | |
10635 | mispredicted taken branch is more expensive than a | |
10636 | mispredicted not-taken branch. */ | |
ec507f2d | 10637 | if (rs6000_always_hint |
f4857b9b AM |
10638 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) |
10639 | { | |
10640 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
10641 | && ((prob > 0) ^ need_longbranch)) | |
7f3d8013 | 10642 | pred = "+"; |
f4857b9b AM |
10643 | else |
10644 | pred = "-"; | |
10645 | } | |
12a4e8c5 | 10646 | } |
12a4e8c5 GK |
10647 | |
10648 | if (label == NULL) | |
94a54f47 | 10649 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 10650 | else |
94a54f47 | 10651 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 10652 | |
37c67319 | 10653 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 10654 | Assume they'd only be the first character.... */ |
37c67319 GK |
10655 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
10656 | *s++ = '%'; | |
94a54f47 | 10657 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
10658 | |
10659 | if (label != NULL) | |
10660 | { | |
10661 | /* If the branch distance was too far, we may have to use an | |
10662 | unconditional branch to go the distance. */ | |
10663 | if (need_longbranch) | |
44518ddd | 10664 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
10665 | else |
10666 | s += sprintf (s, ",%s", label); | |
10667 | } | |
10668 | ||
10669 | return string; | |
10670 | } | |
50a0b056 | 10671 | |
423c1189 AH |
10672 | /* Return the string to flip the GT bit on a CR. */ |
10673 | char * | |
10674 | output_e500_flip_gt_bit (rtx dst, rtx src) | |
10675 | { | |
10676 | static char string[64]; | |
10677 | int a, b; | |
10678 | ||
10679 | if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst)) | |
10680 | || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src))) | |
10681 | abort (); | |
10682 | ||
10683 | /* GT bit. */ | |
10684 | a = 4 * (REGNO (dst) - CR0_REGNO) + 1; | |
10685 | b = 4 * (REGNO (src) - CR0_REGNO) + 1; | |
10686 | ||
10687 | sprintf (string, "crnot %d,%d", a, b); | |
10688 | return string; | |
10689 | } | |
10690 | ||
50a0b056 GK |
10691 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the |
10692 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
10693 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 10694 | |
50a0b056 | 10695 | int |
a2369ed3 | 10696 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
10697 | { |
10698 | enum rtx_code code = GET_CODE (op); | |
10699 | rtx op0 = rs6000_compare_op0; | |
10700 | rtx op1 = rs6000_compare_op1; | |
10701 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
10702 | enum machine_mode compare_mode = GET_MODE (op0); |
10703 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 GK |
10704 | rtx temp; |
10705 | ||
a3c9585f | 10706 | /* These modes should always match. */ |
a3170dc6 AH |
10707 | if (GET_MODE (op1) != compare_mode |
10708 | /* In the isel case however, we can use a compare immediate, so | |
10709 | op1 may be a small constant. */ | |
10710 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 10711 | return 0; |
178c3eff | 10712 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 10713 | return 0; |
178c3eff | 10714 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
10715 | return 0; |
10716 | ||
50a0b056 | 10717 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 10718 | if it's too slow.... */ |
50a0b056 | 10719 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
10720 | { |
10721 | if (TARGET_ISEL) | |
10722 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
10723 | return 0; | |
10724 | } | |
fef98bf2 AH |
10725 | else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS |
10726 | && GET_MODE_CLASS (compare_mode) == MODE_FLOAT) | |
10727 | return 0; | |
50a0b056 GK |
10728 | |
10729 | /* Eliminate half of the comparisons by switching operands, this | |
10730 | makes the remaining code simpler. */ | |
10731 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 10732 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
10733 | { |
10734 | code = reverse_condition_maybe_unordered (code); | |
10735 | temp = true_cond; | |
10736 | true_cond = false_cond; | |
10737 | false_cond = temp; | |
10738 | } | |
10739 | ||
10740 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
10741 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 10742 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 GK |
10743 | return 0; |
10744 | ||
10745 | if (GET_CODE (op1) == CONST_DOUBLE) | |
10746 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
10747 | ||
b6d08ca1 | 10748 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
10749 | a subtract, then comparing against zero. Unfortunately, |
10750 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 10751 | know that the operand is finite and the comparison |
50a0b056 | 10752 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 10753 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 10754 | && code != GT && code != UNGE |
045572c7 | 10755 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
10756 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
10757 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
10758 | || (! rtx_equal_p (op0, true_cond) | |
10759 | && ! rtx_equal_p (op1, true_cond)))) | |
10760 | return 0; | |
10761 | /* At this point we know we can use fsel. */ | |
10762 | ||
10763 | /* Reduce the comparison to a comparison against zero. */ | |
3148ad6d | 10764 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 10765 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 10766 | gen_rtx_MINUS (compare_mode, op0, op1))); |
50a0b056 | 10767 | op0 = temp; |
3148ad6d | 10768 | op1 = CONST0_RTX (compare_mode); |
50a0b056 GK |
10769 | |
10770 | /* If we don't care about NaNs we can reduce some of the comparisons | |
10771 | down to faster ones. */ | |
bc9ec0e0 | 10772 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
10773 | switch (code) |
10774 | { | |
10775 | case GT: | |
10776 | code = LE; | |
10777 | temp = true_cond; | |
10778 | true_cond = false_cond; | |
10779 | false_cond = temp; | |
10780 | break; | |
10781 | case UNGE: | |
10782 | code = GE; | |
10783 | break; | |
10784 | case UNEQ: | |
10785 | code = EQ; | |
10786 | break; | |
10787 | default: | |
10788 | break; | |
10789 | } | |
10790 | ||
10791 | /* Now, reduce everything down to a GE. */ | |
10792 | switch (code) | |
10793 | { | |
10794 | case GE: | |
10795 | break; | |
10796 | ||
10797 | case LE: | |
3148ad6d DJ |
10798 | temp = gen_reg_rtx (compare_mode); |
10799 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10800 | op0 = temp; |
10801 | break; | |
10802 | ||
10803 | case ORDERED: | |
3148ad6d DJ |
10804 | temp = gen_reg_rtx (compare_mode); |
10805 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
10806 | op0 = temp; |
10807 | break; | |
10808 | ||
10809 | case EQ: | |
3148ad6d | 10810 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 10811 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
10812 | gen_rtx_NEG (compare_mode, |
10813 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
10814 | op0 = temp; |
10815 | break; | |
10816 | ||
10817 | case UNGE: | |
bc9ec0e0 | 10818 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 10819 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 10820 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 10821 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10822 | gen_rtx_GE (VOIDmode, |
10823 | op0, op1), | |
10824 | true_cond, false_cond))); | |
bc9ec0e0 GK |
10825 | false_cond = true_cond; |
10826 | true_cond = temp; | |
50a0b056 | 10827 | |
3148ad6d DJ |
10828 | temp = gen_reg_rtx (compare_mode); |
10829 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10830 | op0 = temp; |
10831 | break; | |
10832 | ||
10833 | case GT: | |
bc9ec0e0 | 10834 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 10835 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 10836 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 10837 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10838 | gen_rtx_GE (VOIDmode, |
10839 | op0, op1), | |
10840 | true_cond, false_cond))); | |
bc9ec0e0 GK |
10841 | true_cond = false_cond; |
10842 | false_cond = temp; | |
50a0b056 | 10843 | |
3148ad6d DJ |
10844 | temp = gen_reg_rtx (compare_mode); |
10845 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10846 | op0 = temp; |
10847 | break; | |
10848 | ||
10849 | default: | |
10850 | abort (); | |
10851 | } | |
10852 | ||
10853 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 10854 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10855 | gen_rtx_GE (VOIDmode, |
10856 | op0, op1), | |
10857 | true_cond, false_cond))); | |
10858 | return 1; | |
10859 | } | |
10860 | ||
a3170dc6 AH |
10861 | /* Same as above, but for ints (isel). */ |
10862 | ||
10863 | static int | |
a2369ed3 | 10864 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
10865 | { |
10866 | rtx condition_rtx, cr; | |
10867 | ||
10868 | /* All isel implementations thus far are 32-bits. */ | |
10869 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
10870 | return 0; | |
10871 | ||
10872 | /* We still have to do the compare, because isel doesn't do a | |
10873 | compare, it just looks at the CRx bits set by a previous compare | |
10874 | instruction. */ | |
10875 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
10876 | cr = XEXP (condition_rtx, 0); | |
10877 | ||
10878 | if (GET_MODE (cr) == CCmode) | |
10879 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
10880 | true_cond, false_cond, cr)); | |
10881 | else | |
10882 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
10883 | true_cond, false_cond, cr)); | |
10884 | ||
10885 | return 1; | |
10886 | } | |
10887 | ||
10888 | const char * | |
a2369ed3 | 10889 | output_isel (rtx *operands) |
a3170dc6 AH |
10890 | { |
10891 | enum rtx_code code; | |
10892 | ||
10893 | code = GET_CODE (operands[1]); | |
10894 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
10895 | { | |
10896 | PUT_CODE (operands[1], reverse_condition (code)); | |
10897 | return "isel %0,%3,%2,%j1"; | |
10898 | } | |
10899 | else | |
10900 | return "isel %0,%2,%3,%j1"; | |
10901 | } | |
10902 | ||
50a0b056 | 10903 | void |
a2369ed3 | 10904 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
10905 | { |
10906 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 10907 | enum rtx_code c; |
50a0b056 | 10908 | rtx target; |
5dc8d536 AH |
10909 | |
10910 | if (code == SMAX || code == SMIN) | |
10911 | c = GE; | |
10912 | else | |
10913 | c = GEU; | |
10914 | ||
50a0b056 | 10915 | if (code == SMAX || code == UMAX) |
5dc8d536 | 10916 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
10917 | op0, op1, mode, 0); |
10918 | else | |
5dc8d536 | 10919 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
10920 | op1, op0, mode, 0); |
10921 | if (target == NULL_RTX) | |
10922 | abort (); | |
10923 | if (target != dest) | |
10924 | emit_move_insn (dest, target); | |
10925 | } | |
46c07df8 | 10926 | |
a9baceb1 GK |
10927 | /* Emit instructions to move SRC to DST. Called by splitters for |
10928 | multi-register moves. It will emit at most one instruction for | |
10929 | each register that is accessed; that is, it won't emit li/lis pairs | |
10930 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
10931 | register. */ | |
46c07df8 | 10932 | |
46c07df8 | 10933 | void |
a9baceb1 | 10934 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 10935 | { |
a9baceb1 GK |
10936 | /* The register number of the first register being moved. */ |
10937 | int reg; | |
10938 | /* The mode that is to be moved. */ | |
10939 | enum machine_mode mode; | |
10940 | /* The mode that the move is being done in, and its size. */ | |
10941 | enum machine_mode reg_mode; | |
10942 | int reg_mode_size; | |
10943 | /* The number of registers that will be moved. */ | |
10944 | int nregs; | |
10945 | ||
10946 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
10947 | mode = GET_MODE (dst); | |
10948 | nregs = HARD_REGNO_NREGS (reg, mode); | |
10949 | if (FP_REGNO_P (reg)) | |
10950 | reg_mode = DFmode; | |
10951 | else if (ALTIVEC_REGNO_P (reg)) | |
10952 | reg_mode = V16QImode; | |
10953 | else | |
10954 | reg_mode = word_mode; | |
10955 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
46c07df8 | 10956 | |
a9baceb1 GK |
10957 | if (reg_mode_size * nregs != GET_MODE_SIZE (mode)) |
10958 | abort (); | |
10959 | ||
10960 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) | |
10961 | { | |
10962 | /* Move register range backwards, if we might have destructive | |
10963 | overlap. */ | |
10964 | int i; | |
10965 | for (i = nregs - 1; i >= 0; i--) | |
10966 | emit_insn (gen_rtx_SET (VOIDmode, | |
10967 | simplify_gen_subreg (reg_mode, dst, mode, | |
10968 | i * reg_mode_size), | |
10969 | simplify_gen_subreg (reg_mode, src, mode, | |
10970 | i * reg_mode_size))); | |
10971 | } | |
46c07df8 HP |
10972 | else |
10973 | { | |
a9baceb1 GK |
10974 | int i; |
10975 | int j = -1; | |
10976 | bool used_update = false; | |
46c07df8 | 10977 | |
a9baceb1 | 10978 | if (GET_CODE (src) == MEM && INT_REGNO_P (reg)) |
46c07df8 HP |
10979 | { |
10980 | rtx breg; | |
3a1f863f | 10981 | |
a9baceb1 GK |
10982 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
10983 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
10984 | { |
10985 | rtx delta_rtx; | |
a9baceb1 GK |
10986 | breg = XEXP (XEXP (src, 0), 0); |
10987 | delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC | |
10988 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
10989 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))); | |
10990 | emit_insn (TARGET_32BIT | |
10991 | ? gen_addsi3 (breg, breg, delta_rtx) | |
10992 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
10993 | src = gen_rtx_MEM (mode, breg); |
10994 | } | |
10995 | ||
10996 | /* We have now address involving an base register only. | |
10997 | If we use one of the registers to address memory, | |
10998 | we have change that register last. */ | |
10999 | ||
11000 | breg = (GET_CODE (XEXP (src, 0)) == PLUS | |
11001 | ? XEXP (XEXP (src, 0), 0) | |
11002 | : XEXP (src, 0)); | |
11003 | ||
11004 | if (!REG_P (breg)) | |
11005 | abort(); | |
11006 | ||
11007 | if (REGNO (breg) >= REGNO (dst) | |
11008 | && REGNO (breg) < REGNO (dst) + nregs) | |
11009 | j = REGNO (breg) - REGNO (dst); | |
46c07df8 HP |
11010 | } |
11011 | ||
a9baceb1 | 11012 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
11013 | { |
11014 | rtx breg; | |
11015 | ||
a9baceb1 GK |
11016 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11017 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
11018 | { |
11019 | rtx delta_rtx; | |
a9baceb1 GK |
11020 | breg = XEXP (XEXP (dst, 0), 0); |
11021 | delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC | |
11022 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
11023 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))); | |
3a1f863f DE |
11024 | |
11025 | /* We have to update the breg before doing the store. | |
11026 | Use store with update, if available. */ | |
11027 | ||
11028 | if (TARGET_UPDATE) | |
11029 | { | |
a9baceb1 GK |
11030 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
11031 | emit_insn (TARGET_32BIT | |
11032 | ? gen_movsi_update (breg, breg, delta_rtx, nsrc) | |
11033 | : gen_movdi_update (breg, breg, delta_rtx, nsrc)); | |
11034 | used_update = true; | |
3a1f863f DE |
11035 | } |
11036 | else | |
a9baceb1 GK |
11037 | emit_insn (TARGET_32BIT |
11038 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11039 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11040 | dst = gen_rtx_MEM (mode, breg); |
11041 | } | |
11042 | } | |
11043 | ||
46c07df8 | 11044 | for (i = 0; i < nregs; i++) |
3a1f863f DE |
11045 | { |
11046 | /* Calculate index to next subword. */ | |
11047 | ++j; | |
11048 | if (j == nregs) | |
11049 | j = 0; | |
46c07df8 | 11050 | |
a9baceb1 GK |
11051 | /* If compiler already emited move of first word by |
11052 | store with update, no need to do anything. */ | |
3a1f863f | 11053 | if (j == 0 && used_update) |
a9baceb1 GK |
11054 | continue; |
11055 | ||
11056 | emit_insn (gen_rtx_SET (VOIDmode, | |
11057 | simplify_gen_subreg (reg_mode, dst, mode, | |
11058 | j * reg_mode_size), | |
11059 | simplify_gen_subreg (reg_mode, src, mode, | |
11060 | j * reg_mode_size))); | |
3a1f863f | 11061 | } |
46c07df8 HP |
11062 | } |
11063 | } | |
11064 | ||
12a4e8c5 | 11065 | \f |
a4f6c312 SS |
11066 | /* This page contains routines that are used to determine what the |
11067 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 11068 | |
a4f6c312 SS |
11069 | /* Return the first fixed-point register that is required to be |
11070 | saved. 32 if none. */ | |
9878760c RK |
11071 | |
11072 | int | |
863d938c | 11073 | first_reg_to_save (void) |
9878760c RK |
11074 | { |
11075 | int first_reg; | |
11076 | ||
11077 | /* Find lowest numbered live register. */ | |
11078 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
11079 | if (regs_ever_live[first_reg] |
11080 | && (! call_used_regs[first_reg] | |
1db02437 | 11081 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11082 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
b4db40bf JJ |
11083 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) |
11084 | || (TARGET_TOC && TARGET_MINIMAL_TOC))))) | |
9878760c RK |
11085 | break; |
11086 | ||
ee890fe2 | 11087 | #if TARGET_MACHO |
93638d7a AM |
11088 | if (flag_pic |
11089 | && current_function_uses_pic_offset_table | |
11090 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 11091 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
11092 | #endif |
11093 | ||
9878760c RK |
11094 | return first_reg; |
11095 | } | |
11096 | ||
11097 | /* Similar, for FP regs. */ | |
11098 | ||
11099 | int | |
863d938c | 11100 | first_fp_reg_to_save (void) |
9878760c RK |
11101 | { |
11102 | int first_reg; | |
11103 | ||
11104 | /* Find lowest numbered live register. */ | |
11105 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
11106 | if (regs_ever_live[first_reg]) | |
11107 | break; | |
11108 | ||
11109 | return first_reg; | |
11110 | } | |
00b960c7 AH |
11111 | |
11112 | /* Similar, for AltiVec regs. */ | |
11113 | ||
11114 | static int | |
863d938c | 11115 | first_altivec_reg_to_save (void) |
00b960c7 AH |
11116 | { |
11117 | int i; | |
11118 | ||
11119 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
11120 | if (! TARGET_ALTIVEC_ABI) | |
11121 | return LAST_ALTIVEC_REGNO + 1; | |
11122 | ||
11123 | /* Find lowest numbered live register. */ | |
11124 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
11125 | if (regs_ever_live[i]) | |
11126 | break; | |
11127 | ||
11128 | return i; | |
11129 | } | |
11130 | ||
11131 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
11132 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
11133 | the 32-bit word is 0. */ | |
11134 | ||
11135 | static unsigned int | |
863d938c | 11136 | compute_vrsave_mask (void) |
00b960c7 AH |
11137 | { |
11138 | unsigned int i, mask = 0; | |
11139 | ||
11140 | /* First, find out if we use _any_ altivec registers. */ | |
11141 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
11142 | if (regs_ever_live[i]) | |
11143 | mask |= ALTIVEC_REG_BIT (i); | |
11144 | ||
11145 | if (mask == 0) | |
11146 | return mask; | |
11147 | ||
00b960c7 AH |
11148 | /* Next, remove the argument registers from the set. These must |
11149 | be in the VRSAVE mask set by the caller, so we don't need to add | |
11150 | them in again. More importantly, the mask we compute here is | |
11151 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
11152 | wish the argument registers to die. */ | |
a6cf80f2 | 11153 | for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
11154 | mask &= ~ALTIVEC_REG_BIT (i); |
11155 | ||
11156 | /* Similarly, remove the return value from the set. */ | |
11157 | { | |
11158 | bool yes = false; | |
11159 | diddle_return_value (is_altivec_return_reg, &yes); | |
11160 | if (yes) | |
11161 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
11162 | } | |
11163 | ||
11164 | return mask; | |
11165 | } | |
11166 | ||
11167 | static void | |
a2369ed3 | 11168 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
11169 | { |
11170 | bool *yes = (bool *) xyes; | |
11171 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
11172 | *yes = true; | |
11173 | } | |
11174 | ||
4697a36c MM |
11175 | \f |
11176 | /* Calculate the stack information for the current function. This is | |
11177 | complicated by having two separate calling sequences, the AIX calling | |
11178 | sequence and the V.4 calling sequence. | |
11179 | ||
592696dd | 11180 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 11181 | 32-bit 64-bit |
4697a36c | 11182 | SP----> +---------------------------------------+ |
a260abc9 | 11183 | | back chain to caller | 0 0 |
4697a36c | 11184 | +---------------------------------------+ |
a260abc9 | 11185 | | saved CR | 4 8 (8-11) |
4697a36c | 11186 | +---------------------------------------+ |
a260abc9 | 11187 | | saved LR | 8 16 |
4697a36c | 11188 | +---------------------------------------+ |
a260abc9 | 11189 | | reserved for compilers | 12 24 |
4697a36c | 11190 | +---------------------------------------+ |
a260abc9 | 11191 | | reserved for binders | 16 32 |
4697a36c | 11192 | +---------------------------------------+ |
a260abc9 | 11193 | | saved TOC pointer | 20 40 |
4697a36c | 11194 | +---------------------------------------+ |
a260abc9 | 11195 | | Parameter save area (P) | 24 48 |
4697a36c | 11196 | +---------------------------------------+ |
a260abc9 | 11197 | | Alloca space (A) | 24+P etc. |
802a0058 | 11198 | +---------------------------------------+ |
a7df97e6 | 11199 | | Local variable space (L) | 24+P+A |
4697a36c | 11200 | +---------------------------------------+ |
a7df97e6 | 11201 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 11202 | +---------------------------------------+ |
00b960c7 AH |
11203 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
11204 | +---------------------------------------+ | |
11205 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
11206 | +---------------------------------------+ | |
11207 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 11208 | +---------------------------------------+ |
00b960c7 AH |
11209 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
11210 | +---------------------------------------+ | |
11211 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
11212 | +---------------------------------------+ |
11213 | old SP->| back chain to caller's caller | | |
11214 | +---------------------------------------+ | |
11215 | ||
5376a30c KR |
11216 | The required alignment for AIX configurations is two words (i.e., 8 |
11217 | or 16 bytes). | |
11218 | ||
11219 | ||
4697a36c MM |
11220 | V.4 stack frames look like: |
11221 | ||
11222 | SP----> +---------------------------------------+ | |
11223 | | back chain to caller | 0 | |
11224 | +---------------------------------------+ | |
5eb387b8 | 11225 | | caller's saved LR | 4 |
4697a36c MM |
11226 | +---------------------------------------+ |
11227 | | Parameter save area (P) | 8 | |
11228 | +---------------------------------------+ | |
a7df97e6 MM |
11229 | | Alloca space (A) | 8+P |
11230 | +---------------------------------------+ | |
11231 | | Varargs save area (V) | 8+P+A | |
11232 | +---------------------------------------+ | |
11233 | | Local variable space (L) | 8+P+A+V | |
11234 | +---------------------------------------+ | |
11235 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 11236 | +---------------------------------------+ |
00b960c7 AH |
11237 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
11238 | +---------------------------------------+ | |
11239 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
11240 | +---------------------------------------+ | |
11241 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
11242 | +---------------------------------------+ | |
a3170dc6 AH |
11243 | | SPE: area for 64-bit GP registers | |
11244 | +---------------------------------------+ | |
11245 | | SPE alignment padding | | |
11246 | +---------------------------------------+ | |
00b960c7 | 11247 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
a7df97e6 | 11248 | +---------------------------------------+ |
00b960c7 | 11249 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 11250 | +---------------------------------------+ |
00b960c7 | 11251 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
11252 | +---------------------------------------+ |
11253 | old SP->| back chain to caller's caller | | |
11254 | +---------------------------------------+ | |
b6c9286a | 11255 | |
5376a30c KR |
11256 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
11257 | given. (But note below and in sysv4.h that we require only 8 and | |
11258 | may round up the size of our stack frame anyways. The historical | |
11259 | reason is early versions of powerpc-linux which didn't properly | |
11260 | align the stack at program startup. A happy side-effect is that | |
11261 | -mno-eabi libraries can be used with -meabi programs.) | |
11262 | ||
50d440bc | 11263 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
11264 | the stack alignment requirements may differ. If -mno-eabi is not |
11265 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
11266 | given, the required alignment is 16 bytes. (But see V.4 comment | |
11267 | above.) */ | |
4697a36c | 11268 | |
61b2fbe7 MM |
11269 | #ifndef ABI_STACK_BOUNDARY |
11270 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
11271 | #endif | |
11272 | ||
d1d0c603 | 11273 | static rs6000_stack_t * |
863d938c | 11274 | rs6000_stack_info (void) |
4697a36c MM |
11275 | { |
11276 | static rs6000_stack_t info, zero_info; | |
11277 | rs6000_stack_t *info_ptr = &info; | |
327e5343 | 11278 | int reg_size = TARGET_32BIT ? 4 : 8; |
83720594 | 11279 | int ehrd_size; |
44688022 | 11280 | HOST_WIDE_INT non_fixed_size; |
4697a36c | 11281 | |
a4f6c312 | 11282 | /* Zero all fields portably. */ |
4697a36c MM |
11283 | info = zero_info; |
11284 | ||
c19de7aa AH |
11285 | if (TARGET_SPE) |
11286 | { | |
11287 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f AH |
11288 | if (cfun->machine->insn_chain_scanned_p == 0) |
11289 | { | |
11290 | cfun->machine->insn_chain_scanned_p = 1; | |
11291 | info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p (); | |
11292 | } | |
c19de7aa AH |
11293 | } |
11294 | ||
a4f6c312 | 11295 | /* Select which calling sequence. */ |
178274da | 11296 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 11297 | |
a4f6c312 | 11298 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 11299 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
1db02437 | 11300 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 11301 | even if it currently looks like we won't. */ |
2bfcf297 | 11302 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
11303 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
11304 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
11305 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
11306 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
11307 | else |
11308 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 11309 | |
a3170dc6 AH |
11310 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
11311 | Ideally we should save the entire 64-bits only when the upper | |
11312 | half is used in SIMD instructions. Since we only record | |
11313 | registers live (not the size they are used in), this proves | |
11314 | difficult because we'd have to traverse the instruction chain at | |
11315 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
11316 | so we opt to save the GPRs in 64-bits always if but one register |
11317 | gets used in 64-bits. Otherwise, all the registers in the frame | |
11318 | get saved in 32-bits. | |
a3170dc6 | 11319 | |
c19de7aa | 11320 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 11321 | traditional GP save area will be empty. */ |
c19de7aa | 11322 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11323 | info_ptr->gp_size = 0; |
11324 | ||
4697a36c MM |
11325 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
11326 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
11327 | ||
00b960c7 AH |
11328 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
11329 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
11330 | - info_ptr->first_altivec_reg_save); | |
11331 | ||
592696dd | 11332 | /* Does this function call anything? */ |
71f123ca FS |
11333 | info_ptr->calls_p = (! current_function_is_leaf |
11334 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 11335 | |
a4f6c312 | 11336 | /* Determine if we need to save the link register. */ |
71f123ca | 11337 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
11338 | || (DEFAULT_ABI == ABI_AIX |
11339 | && current_function_profile | |
11340 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
11341 | #ifdef TARGET_RELOCATABLE |
11342 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
11343 | #endif | |
11344 | || (info_ptr->first_fp_reg_save != 64 | |
11345 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 11346 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 11347 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
11348 | || (DEFAULT_ABI == ABI_DARWIN |
11349 | && flag_pic | |
11350 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
11351 | || info_ptr->calls_p) |
11352 | { | |
11353 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 11354 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
11355 | } |
11356 | ||
9ebbca7d GK |
11357 | /* Determine if we need to save the condition code registers. */ |
11358 | if (regs_ever_live[CR2_REGNO] | |
11359 | || regs_ever_live[CR3_REGNO] | |
11360 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
11361 | { |
11362 | info_ptr->cr_save_p = 1; | |
178274da | 11363 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
11364 | info_ptr->cr_size = reg_size; |
11365 | } | |
11366 | ||
83720594 RH |
11367 | /* If the current function calls __builtin_eh_return, then we need |
11368 | to allocate stack space for registers that will hold data for | |
11369 | the exception handler. */ | |
11370 | if (current_function_calls_eh_return) | |
11371 | { | |
11372 | unsigned int i; | |
11373 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
11374 | continue; | |
a3170dc6 AH |
11375 | |
11376 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
11377 | ehrd_size = i * (TARGET_SPE_ABI |
11378 | && info_ptr->spe_64bit_regs_used != 0 | |
11379 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
11380 | } |
11381 | else | |
11382 | ehrd_size = 0; | |
11383 | ||
592696dd | 11384 | /* Determine various sizes. */ |
4697a36c MM |
11385 | info_ptr->reg_size = reg_size; |
11386 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
11387 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 11388 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 | 11389 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
03e007d7 | 11390 | TARGET_ALTIVEC ? 16 : 8); |
00b960c7 | 11391 | |
c19de7aa | 11392 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11393 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
11394 | else | |
11395 | info_ptr->spe_gp_size = 0; | |
11396 | ||
4d774ff8 HP |
11397 | if (TARGET_ALTIVEC_ABI) |
11398 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 11399 | else |
4d774ff8 HP |
11400 | info_ptr->vrsave_mask = 0; |
11401 | ||
11402 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
11403 | info_ptr->vrsave_size = 4; | |
11404 | else | |
11405 | info_ptr->vrsave_size = 0; | |
b6c9286a | 11406 | |
592696dd | 11407 | /* Calculate the offsets. */ |
178274da | 11408 | switch (DEFAULT_ABI) |
4697a36c | 11409 | { |
b6c9286a | 11410 | case ABI_NONE: |
24d304eb | 11411 | default: |
b6c9286a MM |
11412 | abort (); |
11413 | ||
11414 | case ABI_AIX: | |
ee890fe2 | 11415 | case ABI_DARWIN: |
b6c9286a MM |
11416 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
11417 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
11418 | |
11419 | if (TARGET_ALTIVEC_ABI) | |
11420 | { | |
11421 | info_ptr->vrsave_save_offset | |
11422 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
11423 | ||
11424 | /* Align stack so vector save area is on a quadword boundary. */ | |
11425 | if (info_ptr->altivec_size != 0) | |
11426 | info_ptr->altivec_padding_size | |
11427 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
11428 | else | |
11429 | info_ptr->altivec_padding_size = 0; | |
11430 | ||
11431 | info_ptr->altivec_save_offset | |
11432 | = info_ptr->vrsave_save_offset | |
11433 | - info_ptr->altivec_padding_size | |
11434 | - info_ptr->altivec_size; | |
11435 | ||
11436 | /* Adjust for AltiVec case. */ | |
11437 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
11438 | } | |
11439 | else | |
11440 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
11441 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
11442 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
11443 | break; |
11444 | ||
11445 | case ABI_V4: | |
b6c9286a MM |
11446 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
11447 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 11448 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 11449 | |
c19de7aa | 11450 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11451 | { |
11452 | /* Align stack so SPE GPR save area is aligned on a | |
11453 | double-word boundary. */ | |
11454 | if (info_ptr->spe_gp_size != 0) | |
11455 | info_ptr->spe_padding_size | |
11456 | = 8 - (-info_ptr->cr_save_offset % 8); | |
11457 | else | |
11458 | info_ptr->spe_padding_size = 0; | |
11459 | ||
11460 | info_ptr->spe_gp_save_offset | |
11461 | = info_ptr->cr_save_offset | |
11462 | - info_ptr->spe_padding_size | |
11463 | - info_ptr->spe_gp_size; | |
11464 | ||
11465 | /* Adjust for SPE case. */ | |
11466 | info_ptr->toc_save_offset | |
11467 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
11468 | } | |
11469 | else if (TARGET_ALTIVEC_ABI) | |
00b960c7 AH |
11470 | { |
11471 | info_ptr->vrsave_save_offset | |
11472 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
11473 | ||
11474 | /* Align stack so vector save area is on a quadword boundary. */ | |
11475 | if (info_ptr->altivec_size != 0) | |
11476 | info_ptr->altivec_padding_size | |
11477 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
11478 | else | |
11479 | info_ptr->altivec_padding_size = 0; | |
11480 | ||
11481 | info_ptr->altivec_save_offset | |
11482 | = info_ptr->vrsave_save_offset | |
11483 | - info_ptr->altivec_padding_size | |
11484 | - info_ptr->altivec_size; | |
11485 | ||
11486 | /* Adjust for AltiVec case. */ | |
11487 | info_ptr->toc_save_offset | |
11488 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
11489 | } | |
11490 | else | |
11491 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 11492 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
11493 | info_ptr->lr_save_offset = reg_size; |
11494 | break; | |
4697a36c MM |
11495 | } |
11496 | ||
00b960c7 AH |
11497 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
11498 | + info_ptr->gp_size | |
11499 | + info_ptr->altivec_size | |
11500 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
11501 | + info_ptr->spe_gp_size |
11502 | + info_ptr->spe_padding_size | |
00b960c7 AH |
11503 | + ehrd_size |
11504 | + info_ptr->cr_size | |
11505 | + info_ptr->lr_size | |
11506 | + info_ptr->vrsave_size | |
11507 | + info_ptr->toc_size, | |
11508 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
11509 | ? 16 : 8); | |
11510 | ||
44688022 | 11511 | non_fixed_size = (info_ptr->vars_size |
ff381587 | 11512 | + info_ptr->parm_size |
ff381587 | 11513 | + info_ptr->save_size |
44688022 | 11514 | + info_ptr->varargs_size); |
ff381587 | 11515 | |
44688022 AM |
11516 | info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, |
11517 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
11518 | |
11519 | /* Determine if we need to allocate any stack frame: | |
11520 | ||
a4f6c312 SS |
11521 | For AIX we need to push the stack if a frame pointer is needed |
11522 | (because the stack might be dynamically adjusted), if we are | |
11523 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
11524 | and local variables are more than the space needed to save all | |
11525 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
11526 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 11527 | |
a4f6c312 SS |
11528 | For V.4 we don't have the stack cushion that AIX uses, but assume |
11529 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
11530 | |
11531 | if (info_ptr->calls_p) | |
11532 | info_ptr->push_p = 1; | |
11533 | ||
178274da | 11534 | else if (DEFAULT_ABI == ABI_V4) |
44688022 | 11535 | info_ptr->push_p = non_fixed_size != 0; |
ff381587 | 11536 | |
178274da AM |
11537 | else if (frame_pointer_needed) |
11538 | info_ptr->push_p = 1; | |
11539 | ||
11540 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
11541 | info_ptr->push_p = 1; | |
11542 | ||
ff381587 | 11543 | else |
44688022 | 11544 | info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); |
ff381587 | 11545 | |
a4f6c312 | 11546 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 11547 | if (info_ptr->fp_size == 0) |
4697a36c MM |
11548 | info_ptr->fp_save_offset = 0; |
11549 | ||
8dda1a21 | 11550 | if (info_ptr->gp_size == 0) |
4697a36c MM |
11551 | info_ptr->gp_save_offset = 0; |
11552 | ||
00b960c7 AH |
11553 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
11554 | info_ptr->altivec_save_offset = 0; | |
11555 | ||
11556 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
11557 | info_ptr->vrsave_save_offset = 0; | |
11558 | ||
c19de7aa AH |
11559 | if (! TARGET_SPE_ABI |
11560 | || info_ptr->spe_64bit_regs_used == 0 | |
11561 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
11562 | info_ptr->spe_gp_save_offset = 0; |
11563 | ||
c81fc13e | 11564 | if (! info_ptr->lr_save_p) |
4697a36c MM |
11565 | info_ptr->lr_save_offset = 0; |
11566 | ||
c81fc13e | 11567 | if (! info_ptr->cr_save_p) |
4697a36c MM |
11568 | info_ptr->cr_save_offset = 0; |
11569 | ||
c81fc13e | 11570 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
11571 | info_ptr->toc_save_offset = 0; |
11572 | ||
4697a36c MM |
11573 | return info_ptr; |
11574 | } | |
11575 | ||
c19de7aa AH |
11576 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
11577 | mode. */ | |
11578 | ||
11579 | static bool | |
863d938c | 11580 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
11581 | { |
11582 | rtx insns, insn; | |
11583 | ||
11584 | /* Functions that save and restore all the call-saved registers will | |
11585 | need to save/restore the registers in 64-bits. */ | |
11586 | if (current_function_calls_eh_return | |
11587 | || current_function_calls_setjmp | |
11588 | || current_function_has_nonlocal_goto) | |
11589 | return true; | |
11590 | ||
11591 | insns = get_insns (); | |
11592 | ||
11593 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
11594 | { | |
11595 | if (INSN_P (insn)) | |
11596 | { | |
11597 | rtx i; | |
11598 | ||
11599 | i = PATTERN (insn); | |
11600 | if (GET_CODE (i) == SET | |
11601 | && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i)))) | |
11602 | return true; | |
11603 | } | |
11604 | } | |
11605 | ||
11606 | return false; | |
11607 | } | |
11608 | ||
d1d0c603 | 11609 | static void |
a2369ed3 | 11610 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 11611 | { |
d330fd93 | 11612 | const char *abi_string; |
24d304eb | 11613 | |
c81fc13e | 11614 | if (! info) |
4697a36c MM |
11615 | info = rs6000_stack_info (); |
11616 | ||
11617 | fprintf (stderr, "\nStack information for function %s:\n", | |
11618 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
11619 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
11620 | : "<unknown>")); | |
11621 | ||
24d304eb RK |
11622 | switch (info->abi) |
11623 | { | |
b6c9286a MM |
11624 | default: abi_string = "Unknown"; break; |
11625 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 11626 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 11627 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 11628 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
11629 | } |
11630 | ||
11631 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
11632 | ||
00b960c7 AH |
11633 | if (TARGET_ALTIVEC_ABI) |
11634 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
11635 | ||
a3170dc6 AH |
11636 | if (TARGET_SPE_ABI) |
11637 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
11638 | ||
4697a36c MM |
11639 | if (info->first_gp_reg_save != 32) |
11640 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
11641 | ||
11642 | if (info->first_fp_reg_save != 64) | |
11643 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 11644 | |
00b960c7 AH |
11645 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
11646 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
11647 | info->first_altivec_reg_save); | |
11648 | ||
4697a36c MM |
11649 | if (info->lr_save_p) |
11650 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 11651 | |
4697a36c MM |
11652 | if (info->cr_save_p) |
11653 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
11654 | ||
b6c9286a MM |
11655 | if (info->toc_save_p) |
11656 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
11657 | ||
00b960c7 AH |
11658 | if (info->vrsave_mask) |
11659 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
11660 | ||
4697a36c MM |
11661 | if (info->push_p) |
11662 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
11663 | ||
11664 | if (info->calls_p) | |
11665 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
11666 | ||
4697a36c MM |
11667 | if (info->gp_save_offset) |
11668 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
11669 | ||
11670 | if (info->fp_save_offset) | |
11671 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
11672 | ||
00b960c7 AH |
11673 | if (info->altivec_save_offset) |
11674 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
11675 | info->altivec_save_offset); | |
11676 | ||
a3170dc6 AH |
11677 | if (info->spe_gp_save_offset) |
11678 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
11679 | info->spe_gp_save_offset); | |
11680 | ||
00b960c7 AH |
11681 | if (info->vrsave_save_offset) |
11682 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
11683 | info->vrsave_save_offset); | |
11684 | ||
4697a36c MM |
11685 | if (info->lr_save_offset) |
11686 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
11687 | ||
11688 | if (info->cr_save_offset) | |
11689 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
11690 | ||
b6c9286a MM |
11691 | if (info->toc_save_offset) |
11692 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
11693 | ||
4697a36c MM |
11694 | if (info->varargs_save_offset) |
11695 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
11696 | ||
11697 | if (info->total_size) | |
d1d0c603 JJ |
11698 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
11699 | info->total_size); | |
4697a36c MM |
11700 | |
11701 | if (info->varargs_size) | |
11702 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
11703 | ||
11704 | if (info->vars_size) | |
d1d0c603 JJ |
11705 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
11706 | info->vars_size); | |
4697a36c MM |
11707 | |
11708 | if (info->parm_size) | |
11709 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
11710 | ||
11711 | if (info->fixed_size) | |
11712 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
11713 | ||
11714 | if (info->gp_size) | |
11715 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
11716 | ||
a3170dc6 AH |
11717 | if (info->spe_gp_size) |
11718 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
11719 | ||
4697a36c MM |
11720 | if (info->fp_size) |
11721 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
11722 | ||
00b960c7 AH |
11723 | if (info->altivec_size) |
11724 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
11725 | ||
11726 | if (info->vrsave_size) | |
11727 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
11728 | ||
11729 | if (info->altivec_padding_size) | |
11730 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
11731 | info->altivec_padding_size); | |
11732 | ||
a3170dc6 AH |
11733 | if (info->spe_padding_size) |
11734 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
11735 | info->spe_padding_size); | |
11736 | ||
a4f6c312 | 11737 | if (info->lr_size) |
ed947a96 | 11738 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 11739 | |
4697a36c MM |
11740 | if (info->cr_size) |
11741 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
11742 | ||
a4f6c312 | 11743 | if (info->toc_size) |
b6c9286a MM |
11744 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
11745 | ||
4697a36c MM |
11746 | if (info->save_size) |
11747 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
11748 | ||
11749 | if (info->reg_size != 4) | |
11750 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
11751 | ||
11752 | fprintf (stderr, "\n"); | |
9878760c | 11753 | } |
71f123ca FS |
11754 | |
11755 | rtx | |
a2369ed3 | 11756 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 11757 | { |
a4f6c312 SS |
11758 | /* Currently we don't optimize very well between prolog and body |
11759 | code and for PIC code the code can be actually quite bad, so | |
11760 | don't try to be too clever here. */ | |
f1384257 | 11761 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
11762 | { |
11763 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
11764 | |
11765 | return | |
11766 | gen_rtx_MEM | |
11767 | (Pmode, | |
11768 | memory_address | |
11769 | (Pmode, | |
11770 | plus_constant (copy_to_reg | |
11771 | (gen_rtx_MEM (Pmode, | |
11772 | memory_address (Pmode, frame))), | |
11773 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
11774 | } |
11775 | ||
8c29550d | 11776 | cfun->machine->ra_need_lr = 1; |
9e2f7ec7 | 11777 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
11778 | } |
11779 | ||
5e1bf043 DJ |
11780 | /* Say whether a function is a candidate for sibcall handling or not. |
11781 | We do not allow indirect calls to be optimized into sibling calls. | |
11782 | Also, we can't do it if there are any vector parameters; there's | |
11783 | nowhere to put the VRsave code so it works; note that functions with | |
11784 | vector parameters are required to have a prototype, so the argument | |
11785 | type info must be available here. (The tail recursion case can work | |
11786 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 11787 | static bool |
a2369ed3 | 11788 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
11789 | { |
11790 | tree type; | |
4977bab6 | 11791 | if (decl) |
5e1bf043 DJ |
11792 | { |
11793 | if (TARGET_ALTIVEC_VRSAVE) | |
11794 | { | |
4977bab6 | 11795 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
11796 | type; type = TREE_CHAIN (type)) |
11797 | { | |
c15b529f | 11798 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 11799 | return false; |
5e1bf043 DJ |
11800 | } |
11801 | } | |
11802 | if (DEFAULT_ABI == ABI_DARWIN | |
4977bab6 | 11803 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 11804 | { |
4977bab6 | 11805 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
11806 | |
11807 | if (!lookup_attribute ("longcall", attr_list) | |
11808 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 11809 | return true; |
2bcc50d0 | 11810 | } |
5e1bf043 | 11811 | } |
4977bab6 | 11812 | return false; |
5e1bf043 DJ |
11813 | } |
11814 | ||
71f123ca | 11815 | static int |
863d938c | 11816 | rs6000_ra_ever_killed (void) |
71f123ca FS |
11817 | { |
11818 | rtx top; | |
5e1bf043 DJ |
11819 | rtx reg; |
11820 | rtx insn; | |
71f123ca | 11821 | |
dd292d0a | 11822 | if (current_function_is_thunk) |
71f123ca | 11823 | return 0; |
eb0424da | 11824 | |
36f7e964 AH |
11825 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
11826 | but this should not force saving and restoring in the | |
11827 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 11828 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 11829 | |
5e1bf043 DJ |
11830 | /* Also, the prologue can generate a store into LR that |
11831 | doesn't really count, like this: | |
36f7e964 | 11832 | |
5e1bf043 DJ |
11833 | move LR->R0 |
11834 | bcl to set PIC register | |
11835 | move LR->R31 | |
11836 | move R0->LR | |
36f7e964 AH |
11837 | |
11838 | When we're called from the epilogue, we need to avoid counting | |
11839 | this as a store. */ | |
5e1bf043 | 11840 | |
71f123ca FS |
11841 | push_topmost_sequence (); |
11842 | top = get_insns (); | |
11843 | pop_topmost_sequence (); | |
5e1bf043 | 11844 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 11845 | |
5e1bf043 DJ |
11846 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
11847 | { | |
11848 | if (INSN_P (insn)) | |
11849 | { | |
11850 | if (FIND_REG_INC_NOTE (insn, reg)) | |
11851 | return 1; | |
11852 | else if (GET_CODE (insn) == CALL_INSN | |
c15b529f | 11853 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 11854 | return 1; |
36f7e964 AH |
11855 | else if (set_of (reg, insn) != NULL_RTX |
11856 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
11857 | return 1; |
11858 | } | |
11859 | } | |
11860 | return 0; | |
71f123ca | 11861 | } |
4697a36c | 11862 | \f |
8cd8f856 GK |
11863 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
11864 | static void | |
a2369ed3 | 11865 | rs6000_maybe_dead (rtx insn) |
8cd8f856 GK |
11866 | { |
11867 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
11868 | const0_rtx, | |
11869 | REG_NOTES (insn)); | |
11870 | } | |
11871 | ||
9ebbca7d | 11872 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 11873 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 11874 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
11875 | |
11876 | void | |
a2369ed3 | 11877 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 11878 | { |
027fbf43 | 11879 | rtx dest, insn; |
1db02437 | 11880 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 11881 | |
20b71b17 AM |
11882 | if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
11883 | { | |
11884 | rtx temp = (fromprolog | |
11885 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
11886 | : gen_reg_rtx (Pmode)); | |
027fbf43 JJ |
11887 | insn = emit_insn (gen_load_toc_v4_pic_si (temp)); |
11888 | if (fromprolog) | |
11889 | rs6000_maybe_dead (insn); | |
11890 | insn = emit_move_insn (dest, temp); | |
11891 | if (fromprolog) | |
11892 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
11893 | } |
11894 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
11895 | { | |
11896 | char buf[30]; | |
11897 | rtx tempLR = (fromprolog | |
11898 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
11899 | : gen_reg_rtx (Pmode)); | |
11900 | rtx temp0 = (fromprolog | |
11901 | ? gen_rtx_REG (Pmode, 0) | |
11902 | : gen_reg_rtx (Pmode)); | |
11903 | rtx symF; | |
11904 | ||
11905 | /* possibly create the toc section */ | |
11906 | if (! toc_initialized) | |
38c1f2d7 | 11907 | { |
20b71b17 AM |
11908 | toc_section (); |
11909 | function_section (current_function_decl); | |
38c1f2d7 | 11910 | } |
9ebbca7d | 11911 | |
20b71b17 AM |
11912 | if (fromprolog) |
11913 | { | |
11914 | rtx symL; | |
38c1f2d7 | 11915 | |
20b71b17 AM |
11916 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
11917 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 11918 | |
20b71b17 AM |
11919 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
11920 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
11921 | ||
11922 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
11923 | symF))); | |
11924 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
11925 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
11926 | symL, | |
11927 | symF))); | |
9ebbca7d GK |
11928 | } |
11929 | else | |
20b71b17 AM |
11930 | { |
11931 | rtx tocsym; | |
11932 | static int reload_toc_labelno = 0; | |
11933 | ||
11934 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
11935 | ||
11936 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); | |
11937 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
11938 | ||
027fbf43 JJ |
11939 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym)); |
11940 | emit_move_insn (dest, tempLR); | |
11941 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 11942 | } |
027fbf43 JJ |
11943 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
11944 | if (fromprolog) | |
11945 | rs6000_maybe_dead (insn); | |
9ebbca7d | 11946 | } |
20b71b17 AM |
11947 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
11948 | { | |
11949 | /* This is for AIX code running in non-PIC ELF32. */ | |
11950 | char buf[30]; | |
11951 | rtx realsym; | |
11952 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
11953 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
11954 | ||
027fbf43 JJ |
11955 | insn = emit_insn (gen_elf_high (dest, realsym)); |
11956 | if (fromprolog) | |
11957 | rs6000_maybe_dead (insn); | |
11958 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
11959 | if (fromprolog) | |
11960 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
11961 | } |
11962 | else if (DEFAULT_ABI == ABI_AIX) | |
9ebbca7d GK |
11963 | { |
11964 | if (TARGET_32BIT) | |
027fbf43 | 11965 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 11966 | else |
027fbf43 JJ |
11967 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
11968 | if (fromprolog) | |
11969 | rs6000_maybe_dead (insn); | |
9ebbca7d | 11970 | } |
20b71b17 AM |
11971 | else |
11972 | abort (); | |
9ebbca7d GK |
11973 | } |
11974 | ||
d1d0c603 JJ |
11975 | /* Emit instructions to restore the link register after determining where |
11976 | its value has been stored. */ | |
11977 | ||
11978 | void | |
11979 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
11980 | { | |
11981 | rs6000_stack_t *info = rs6000_stack_info (); | |
11982 | rtx operands[2]; | |
11983 | ||
11984 | operands[0] = source; | |
11985 | operands[1] = scratch; | |
11986 | ||
11987 | if (info->lr_save_p) | |
11988 | { | |
11989 | rtx frame_rtx = stack_pointer_rtx; | |
11990 | HOST_WIDE_INT sp_offset = 0; | |
11991 | rtx tmp; | |
11992 | ||
11993 | if (frame_pointer_needed | |
11994 | || current_function_calls_alloca | |
11995 | || info->total_size > 32767) | |
11996 | { | |
11997 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
11998 | frame_rtx = operands[1]; | |
11999 | } | |
12000 | else if (info->push_p) | |
12001 | sp_offset = info->total_size; | |
12002 | ||
12003 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
12004 | tmp = gen_rtx_MEM (Pmode, tmp); | |
12005 | emit_move_insn (tmp, operands[0]); | |
12006 | } | |
12007 | else | |
12008 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
12009 | } | |
12010 | ||
f103e34d GK |
12011 | static GTY(()) int set = -1; |
12012 | ||
9ebbca7d | 12013 | int |
863d938c | 12014 | get_TOC_alias_set (void) |
9ebbca7d | 12015 | { |
f103e34d GK |
12016 | if (set == -1) |
12017 | set = new_alias_set (); | |
12018 | return set; | |
9ebbca7d GK |
12019 | } |
12020 | ||
c1207243 | 12021 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
12022 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
12023 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 12024 | #if TARGET_ELF |
3c9eb5f4 | 12025 | static int |
38f391a5 | 12026 | uses_TOC (void) |
9ebbca7d | 12027 | { |
c4501e62 | 12028 | rtx insn; |
38c1f2d7 | 12029 | |
c4501e62 JJ |
12030 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
12031 | if (INSN_P (insn)) | |
12032 | { | |
12033 | rtx pat = PATTERN (insn); | |
12034 | int i; | |
9ebbca7d | 12035 | |
c4501e62 JJ |
12036 | if (GET_CODE (pat) == PARALLEL) |
12037 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
12038 | { | |
12039 | rtx sub = XVECEXP (pat, 0, i); | |
12040 | if (GET_CODE (sub) == USE) | |
12041 | { | |
12042 | sub = XEXP (sub, 0); | |
12043 | if (GET_CODE (sub) == UNSPEC | |
12044 | && XINT (sub, 1) == UNSPEC_TOC) | |
12045 | return 1; | |
12046 | } | |
12047 | } | |
12048 | } | |
12049 | return 0; | |
9ebbca7d | 12050 | } |
c954844a | 12051 | #endif |
38c1f2d7 | 12052 | |
9ebbca7d | 12053 | rtx |
a2369ed3 | 12054 | create_TOC_reference (rtx symbol) |
9ebbca7d | 12055 | { |
a8a05998 ZW |
12056 | return gen_rtx_PLUS (Pmode, |
12057 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
12058 | gen_rtx_CONST (Pmode, | |
12059 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 12060 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 12061 | } |
38c1f2d7 | 12062 | |
fc4767bb JJ |
12063 | /* If _Unwind_* has been called from within the same module, |
12064 | toc register is not guaranteed to be saved to 40(1) on function | |
12065 | entry. Save it there in that case. */ | |
c7ca610e | 12066 | |
9ebbca7d | 12067 | void |
863d938c | 12068 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
12069 | { |
12070 | rtx mem; | |
12071 | rtx stack_top = gen_reg_rtx (Pmode); | |
12072 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
12073 | rtx opcode = gen_reg_rtx (SImode); |
12074 | rtx tocompare = gen_reg_rtx (SImode); | |
12075 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d GK |
12076 | |
12077 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
12078 | emit_move_insn (stack_top, mem); | |
12079 | ||
fc4767bb JJ |
12080 | mem = gen_rtx_MEM (Pmode, |
12081 | gen_rtx_PLUS (Pmode, stack_top, | |
9ebbca7d GK |
12082 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); |
12083 | emit_move_insn (opcode_addr, mem); | |
fc4767bb JJ |
12084 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
12085 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 12086 | : 0xE8410028, SImode)); |
9ebbca7d | 12087 | |
fc4767bb | 12088 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 12089 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 12090 | no_toc_save_needed); |
9ebbca7d | 12091 | |
fc4767bb JJ |
12092 | mem = gen_rtx_MEM (Pmode, |
12093 | gen_rtx_PLUS (Pmode, stack_top, | |
12094 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
12095 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); | |
12096 | emit_label (no_toc_save_needed); | |
9ebbca7d | 12097 | } |
38c1f2d7 | 12098 | \f |
ba4828e0 RK |
12099 | /* This ties together stack memory (MEM with an alias set of |
12100 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
12101 | ||
9ebbca7d | 12102 | static void |
863d938c | 12103 | rs6000_emit_stack_tie (void) |
9ebbca7d | 12104 | { |
ba4828e0 RK |
12105 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
12106 | ||
12107 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
12108 | emit_insn (gen_stack_tie (mem)); |
12109 | } | |
38c1f2d7 | 12110 | |
9ebbca7d GK |
12111 | /* Emit the correct code for allocating stack space, as insns. |
12112 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
12113 | The generated code may use hard register 0 as a temporary. */ | |
12114 | ||
12115 | static void | |
a2369ed3 | 12116 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) |
38c1f2d7 | 12117 | { |
9ebbca7d GK |
12118 | rtx insn; |
12119 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
12120 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
12121 | rtx todec = GEN_INT (-size); | |
a157febd GK |
12122 | |
12123 | if (current_function_limit_stack) | |
12124 | { | |
12125 | if (REG_P (stack_limit_rtx) | |
12126 | && REGNO (stack_limit_rtx) > 1 | |
12127 | && REGNO (stack_limit_rtx) <= 31) | |
12128 | { | |
5b71a4e7 | 12129 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
12130 | ? gen_addsi3 (tmp_reg, |
12131 | stack_limit_rtx, | |
12132 | GEN_INT (size)) | |
12133 | : gen_adddi3 (tmp_reg, | |
12134 | stack_limit_rtx, | |
12135 | GEN_INT (size))); | |
5b71a4e7 | 12136 | |
9ebbca7d GK |
12137 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
12138 | const0_rtx)); | |
a157febd GK |
12139 | } |
12140 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 12141 | && TARGET_32BIT |
f607bc57 | 12142 | && DEFAULT_ABI == ABI_V4) |
a157febd | 12143 | { |
9ebbca7d GK |
12144 | rtx toload = gen_rtx_CONST (VOIDmode, |
12145 | gen_rtx_PLUS (Pmode, | |
12146 | stack_limit_rtx, | |
12147 | GEN_INT (size))); | |
5b71a4e7 | 12148 | |
9ebbca7d GK |
12149 | emit_insn (gen_elf_high (tmp_reg, toload)); |
12150 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
12151 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
12152 | const0_rtx)); | |
a157febd GK |
12153 | } |
12154 | else | |
12155 | warning ("stack limit expression is not supported"); | |
12156 | } | |
12157 | ||
9ebbca7d GK |
12158 | if (copy_r12 || ! TARGET_UPDATE) |
12159 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
12160 | ||
38c1f2d7 MM |
12161 | if (TARGET_UPDATE) |
12162 | { | |
9ebbca7d | 12163 | if (size > 32767) |
38c1f2d7 | 12164 | { |
9ebbca7d GK |
12165 | /* Need a note here so that try_split doesn't get confused. */ |
12166 | if (get_last_insn() == NULL_RTX) | |
2e040219 | 12167 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d GK |
12168 | insn = emit_move_insn (tmp_reg, todec); |
12169 | try_split (PATTERN (insn), insn, 0); | |
12170 | todec = tmp_reg; | |
38c1f2d7 | 12171 | } |
5b71a4e7 DE |
12172 | |
12173 | insn = emit_insn (TARGET_32BIT | |
12174 | ? gen_movsi_update (stack_reg, stack_reg, | |
12175 | todec, stack_reg) | |
12176 | : gen_movdi_update (stack_reg, stack_reg, | |
9ebbca7d | 12177 | todec, stack_reg)); |
38c1f2d7 MM |
12178 | } |
12179 | else | |
12180 | { | |
5b71a4e7 DE |
12181 | insn = emit_insn (TARGET_32BIT |
12182 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
12183 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
12184 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
12185 | gen_rtx_REG (Pmode, 12)); | |
12186 | } | |
5b71a4e7 | 12187 | |
9ebbca7d GK |
12188 | RTX_FRAME_RELATED_P (insn) = 1; |
12189 | REG_NOTES (insn) = | |
12190 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12191 | gen_rtx_SET (VOIDmode, stack_reg, | |
12192 | gen_rtx_PLUS (Pmode, stack_reg, | |
12193 | GEN_INT (-size))), | |
12194 | REG_NOTES (insn)); | |
12195 | } | |
12196 | ||
a4f6c312 SS |
12197 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
12198 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
12199 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
12200 | deduce these equivalences by itself so it wasn't necessary to hold | |
12201 | its hand so much. */ | |
9ebbca7d GK |
12202 | |
12203 | static void | |
a2369ed3 DJ |
12204 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
12205 | rtx reg2, rtx rreg) | |
9ebbca7d GK |
12206 | { |
12207 | rtx real, temp; | |
12208 | ||
e56c4463 JL |
12209 | /* copy_rtx will not make unique copies of registers, so we need to |
12210 | ensure we don't have unwanted sharing here. */ | |
12211 | if (reg == reg2) | |
12212 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12213 | ||
12214 | if (reg == rreg) | |
12215 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12216 | ||
9ebbca7d GK |
12217 | real = copy_rtx (PATTERN (insn)); |
12218 | ||
89e7058f AH |
12219 | if (reg2 != NULL_RTX) |
12220 | real = replace_rtx (real, reg2, rreg); | |
12221 | ||
9ebbca7d GK |
12222 | real = replace_rtx (real, reg, |
12223 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
12224 | STACK_POINTER_REGNUM), | |
12225 | GEN_INT (val))); | |
12226 | ||
12227 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
12228 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
12229 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
12230 | ||
12231 | if (GET_CODE (real) == SET) | |
12232 | { | |
12233 | rtx set = real; | |
12234 | ||
12235 | temp = simplify_rtx (SET_SRC (set)); | |
12236 | if (temp) | |
12237 | SET_SRC (set) = temp; | |
12238 | temp = simplify_rtx (SET_DEST (set)); | |
12239 | if (temp) | |
12240 | SET_DEST (set) = temp; | |
12241 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 12242 | { |
9ebbca7d GK |
12243 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
12244 | if (temp) | |
12245 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 12246 | } |
38c1f2d7 | 12247 | } |
9ebbca7d GK |
12248 | else if (GET_CODE (real) == PARALLEL) |
12249 | { | |
12250 | int i; | |
12251 | for (i = 0; i < XVECLEN (real, 0); i++) | |
12252 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
12253 | { | |
12254 | rtx set = XVECEXP (real, 0, i); | |
12255 | ||
12256 | temp = simplify_rtx (SET_SRC (set)); | |
12257 | if (temp) | |
12258 | SET_SRC (set) = temp; | |
12259 | temp = simplify_rtx (SET_DEST (set)); | |
12260 | if (temp) | |
12261 | SET_DEST (set) = temp; | |
12262 | if (GET_CODE (SET_DEST (set)) == MEM) | |
12263 | { | |
12264 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
12265 | if (temp) | |
12266 | XEXP (SET_DEST (set), 0) = temp; | |
12267 | } | |
12268 | RTX_FRAME_RELATED_P (set) = 1; | |
12269 | } | |
12270 | } | |
12271 | else | |
a4f6c312 | 12272 | abort (); |
c19de7aa AH |
12273 | |
12274 | if (TARGET_SPE) | |
12275 | real = spe_synthesize_frame_save (real); | |
12276 | ||
9ebbca7d GK |
12277 | RTX_FRAME_RELATED_P (insn) = 1; |
12278 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12279 | real, | |
12280 | REG_NOTES (insn)); | |
38c1f2d7 MM |
12281 | } |
12282 | ||
c19de7aa AH |
12283 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
12284 | original note, plus a synthetic register save. */ | |
12285 | ||
12286 | static rtx | |
a2369ed3 | 12287 | spe_synthesize_frame_save (rtx real) |
c19de7aa AH |
12288 | { |
12289 | rtx synth, offset, reg, real2; | |
12290 | ||
12291 | if (GET_CODE (real) != SET | |
12292 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
12293 | return real; | |
12294 | ||
12295 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
12296 | frame related note. The parallel contains a set of the register | |
41f3a930 | 12297 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
12298 | This is so we can differentiate between 64-bit and 32-bit saves. |
12299 | Words cannot describe this nastiness. */ | |
12300 | ||
12301 | if (GET_CODE (SET_DEST (real)) != MEM | |
12302 | || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS | |
12303 | || GET_CODE (SET_SRC (real)) != REG) | |
12304 | abort (); | |
12305 | ||
12306 | /* Transform: | |
12307 | (set (mem (plus (reg x) (const y))) | |
12308 | (reg z)) | |
12309 | into: | |
12310 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 12311 | (reg z+1200)) |
c19de7aa AH |
12312 | */ |
12313 | ||
12314 | real2 = copy_rtx (real); | |
12315 | PUT_MODE (SET_DEST (real2), SImode); | |
12316 | reg = SET_SRC (real2); | |
12317 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
12318 | synth = copy_rtx (real2); | |
12319 | ||
12320 | if (BYTES_BIG_ENDIAN) | |
12321 | { | |
12322 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
12323 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
12324 | } | |
12325 | ||
12326 | reg = SET_SRC (synth); | |
41f3a930 | 12327 | |
c19de7aa | 12328 | synth = replace_rtx (synth, reg, |
41f3a930 | 12329 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
12330 | |
12331 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
12332 | synth = replace_rtx (synth, offset, | |
12333 | GEN_INT (INTVAL (offset) | |
12334 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
12335 | ||
12336 | RTX_FRAME_RELATED_P (synth) = 1; | |
12337 | RTX_FRAME_RELATED_P (real2) = 1; | |
12338 | if (BYTES_BIG_ENDIAN) | |
12339 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
12340 | else | |
12341 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
12342 | ||
12343 | return real; | |
12344 | } | |
12345 | ||
00b960c7 AH |
12346 | /* Returns an insn that has a vrsave set operation with the |
12347 | appropriate CLOBBERs. */ | |
12348 | ||
12349 | static rtx | |
a2369ed3 | 12350 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
12351 | { |
12352 | int nclobs, i; | |
12353 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 12354 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 12355 | |
a004eb82 AH |
12356 | clobs[0] |
12357 | = gen_rtx_SET (VOIDmode, | |
12358 | vrsave, | |
12359 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
12360 | gen_rtvec (2, reg, vrsave), | |
12361 | 30)); | |
00b960c7 AH |
12362 | |
12363 | nclobs = 1; | |
12364 | ||
9aa86737 AH |
12365 | /* We need to clobber the registers in the mask so the scheduler |
12366 | does not move sets to VRSAVE before sets of AltiVec registers. | |
12367 | ||
12368 | However, if the function receives nonlocal gotos, reload will set | |
12369 | all call saved registers live. We will end up with: | |
12370 | ||
12371 | (set (reg 999) (mem)) | |
12372 | (parallel [ (set (reg vrsave) (unspec blah)) | |
12373 | (clobber (reg 999))]) | |
12374 | ||
12375 | The clobber will cause the store into reg 999 to be dead, and | |
12376 | flow will attempt to delete an epilogue insn. In this case, we | |
12377 | need an unspec use/set of the register. */ | |
00b960c7 AH |
12378 | |
12379 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
44688022 | 12380 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) |
9aa86737 AH |
12381 | { |
12382 | if (!epiloguep || call_used_regs [i]) | |
12383 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
12384 | gen_rtx_REG (V4SImode, i)); | |
12385 | else | |
12386 | { | |
12387 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
12388 | |
12389 | clobs[nclobs++] | |
a004eb82 AH |
12390 | = gen_rtx_SET (VOIDmode, |
12391 | reg, | |
12392 | gen_rtx_UNSPEC (V4SImode, | |
12393 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
12394 | } |
12395 | } | |
00b960c7 AH |
12396 | |
12397 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
12398 | ||
12399 | for (i = 0; i < nclobs; ++i) | |
12400 | XVECEXP (insn, 0, i) = clobs[i]; | |
12401 | ||
12402 | return insn; | |
12403 | } | |
12404 | ||
89e7058f AH |
12405 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
12406 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
12407 | ||
12408 | static void | |
a2369ed3 | 12409 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 12410 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
12411 | { |
12412 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
12413 | rtx replacea, replaceb; | |
12414 | ||
12415 | int_rtx = GEN_INT (offset); | |
12416 | ||
12417 | /* Some cases that need register indexed addressing. */ | |
12418 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
a3170dc6 AH |
12419 | || (TARGET_SPE_ABI |
12420 | && SPE_VECTOR_MODE (mode) | |
12421 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
12422 | { |
12423 | /* Whomever calls us must make sure r11 is available in the | |
12424 | flow path of instructions in the prologue. */ | |
12425 | offset_rtx = gen_rtx_REG (Pmode, 11); | |
12426 | emit_move_insn (offset_rtx, int_rtx); | |
12427 | ||
12428 | replacea = offset_rtx; | |
12429 | replaceb = int_rtx; | |
12430 | } | |
12431 | else | |
12432 | { | |
12433 | offset_rtx = int_rtx; | |
12434 | replacea = NULL_RTX; | |
12435 | replaceb = NULL_RTX; | |
12436 | } | |
12437 | ||
12438 | reg = gen_rtx_REG (mode, regno); | |
12439 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
12440 | mem = gen_rtx_MEM (mode, addr); | |
12441 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12442 | ||
12443 | insn = emit_move_insn (mem, reg); | |
12444 | ||
12445 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
12446 | } | |
12447 | ||
a3170dc6 AH |
12448 | /* Emit an offset memory reference suitable for a frame store, while |
12449 | converting to a valid addressing mode. */ | |
12450 | ||
12451 | static rtx | |
a2369ed3 | 12452 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
12453 | { |
12454 | rtx int_rtx, offset_rtx; | |
12455 | ||
12456 | int_rtx = GEN_INT (offset); | |
12457 | ||
12458 | if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) | |
12459 | { | |
12460 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
12461 | emit_move_insn (offset_rtx, int_rtx); | |
12462 | } | |
12463 | else | |
12464 | offset_rtx = int_rtx; | |
12465 | ||
12466 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
12467 | } | |
12468 | ||
9ebbca7d GK |
12469 | /* Emit function prologue as insns. */ |
12470 | ||
9878760c | 12471 | void |
863d938c | 12472 | rs6000_emit_prologue (void) |
9878760c | 12473 | { |
4697a36c | 12474 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a | 12475 | enum machine_mode reg_mode = Pmode; |
327e5343 | 12476 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
12477 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
12478 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
12479 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 12480 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d GK |
12481 | rtx insn; |
12482 | int saving_FPRs_inline; | |
12483 | int using_store_multiple; | |
12484 | HOST_WIDE_INT sp_offset = 0; | |
12485 | ||
c19de7aa | 12486 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12487 | { |
12488 | reg_mode = V2SImode; | |
12489 | reg_size = 8; | |
12490 | } | |
12491 | ||
9ebbca7d | 12492 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
12493 | && (!TARGET_SPE_ABI |
12494 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
12495 | && info->first_gp_reg_save < 31); |
12496 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8c29550d | 12497 | || FP_SAVE_INLINE (info->first_fp_reg_save) |
acd0b319 | 12498 | || current_function_calls_eh_return |
8c29550d | 12499 | || cfun->machine->ra_need_lr); |
9ebbca7d GK |
12500 | |
12501 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
fc4767bb | 12502 | if (info->push_p |
acd0b319 AM |
12503 | && (DEFAULT_ABI == ABI_V4 |
12504 | || current_function_calls_eh_return)) | |
9ebbca7d GK |
12505 | { |
12506 | if (info->total_size < 32767) | |
12507 | sp_offset = info->total_size; | |
12508 | else | |
12509 | frame_reg_rtx = frame_ptr_rtx; | |
12510 | rs6000_emit_allocate_stack (info->total_size, | |
12511 | (frame_reg_rtx != sp_reg_rtx | |
12512 | && (info->cr_save_p | |
12513 | || info->lr_save_p | |
12514 | || info->first_fp_reg_save < 64 | |
12515 | || info->first_gp_reg_save < 32 | |
12516 | ))); | |
12517 | if (frame_reg_rtx != sp_reg_rtx) | |
12518 | rs6000_emit_stack_tie (); | |
12519 | } | |
12520 | ||
9aa86737 AH |
12521 | /* Save AltiVec registers if needed. */ |
12522 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
12523 | { | |
12524 | int i; | |
12525 | ||
12526 | /* There should be a non inline version of this, for when we | |
12527 | are saving lots of vector registers. */ | |
12528 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
12529 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
12530 | { | |
12531 | rtx areg, savereg, mem; | |
12532 | int offset; | |
12533 | ||
12534 | offset = info->altivec_save_offset + sp_offset | |
12535 | + 16 * (i - info->first_altivec_reg_save); | |
12536 | ||
12537 | savereg = gen_rtx_REG (V4SImode, i); | |
12538 | ||
12539 | areg = gen_rtx_REG (Pmode, 0); | |
12540 | emit_move_insn (areg, GEN_INT (offset)); | |
12541 | ||
12542 | /* AltiVec addressing mode is [reg+reg]. */ | |
12543 | mem = gen_rtx_MEM (V4SImode, | |
12544 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
12545 | ||
12546 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12547 | ||
12548 | insn = emit_move_insn (mem, savereg); | |
12549 | ||
5c242421 SB |
12550 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
12551 | areg, GEN_INT (offset)); | |
9aa86737 AH |
12552 | } |
12553 | } | |
12554 | ||
12555 | /* VRSAVE is a bit vector representing which AltiVec registers | |
12556 | are used. The OS uses this to determine which vector | |
12557 | registers to save on a context switch. We need to save | |
12558 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
12559 | used in this function, and do the corresponding magic in the | |
12560 | epilogue. */ | |
12561 | ||
4d774ff8 HP |
12562 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
12563 | && info->vrsave_mask != 0) | |
9aa86737 | 12564 | { |
a004eb82 | 12565 | rtx reg, mem, vrsave; |
9aa86737 AH |
12566 | int offset; |
12567 | ||
12568 | /* Get VRSAVE onto a GPR. */ | |
12569 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 | 12570 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
12571 | if (TARGET_MACHO) |
12572 | emit_insn (gen_get_vrsave_internal (reg)); | |
12573 | else | |
12574 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
12575 | |
12576 | /* Save VRSAVE. */ | |
12577 | offset = info->vrsave_save_offset + sp_offset; | |
12578 | mem | |
12579 | = gen_rtx_MEM (SImode, | |
12580 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
12581 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12582 | insn = emit_move_insn (mem, reg); | |
12583 | ||
12584 | /* Include the registers in the mask. */ | |
12585 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
12586 | ||
12587 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
12588 | } | |
12589 | ||
9ebbca7d GK |
12590 | /* If we use the link register, get it into r0. */ |
12591 | if (info->lr_save_p) | |
f8a57be8 GK |
12592 | { |
12593 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
12594 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
12595 | RTX_FRAME_RELATED_P (insn) = 1; | |
12596 | } | |
9ebbca7d GK |
12597 | |
12598 | /* If we need to save CR, put it into r12. */ | |
12599 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
12600 | { | |
f8a57be8 GK |
12601 | rtx set; |
12602 | ||
9ebbca7d | 12603 | cr_save_rtx = gen_rtx_REG (SImode, 12); |
f8a57be8 GK |
12604 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
12605 | RTX_FRAME_RELATED_P (insn) = 1; | |
12606 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
12607 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. | |
12608 | But that's OK. All we have to do is specify that _one_ condition | |
12609 | code register is saved in this stack slot. The thrower's epilogue | |
12610 | will then restore all the call-saved registers. | |
12611 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
12612 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, | |
12613 | gen_rtx_REG (SImode, CR2_REGNO)); | |
12614 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12615 | set, | |
12616 | REG_NOTES (insn)); | |
9ebbca7d GK |
12617 | } |
12618 | ||
a4f6c312 SS |
12619 | /* Do any required saving of fpr's. If only one or two to save, do |
12620 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
12621 | if (saving_FPRs_inline) |
12622 | { | |
12623 | int i; | |
12624 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
12625 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
12626 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
89e7058f AH |
12627 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
12628 | info->first_fp_reg_save + i, | |
12629 | info->fp_save_offset + sp_offset + 8 * i, | |
12630 | info->total_size); | |
9ebbca7d GK |
12631 | } |
12632 | else if (info->first_fp_reg_save != 64) | |
12633 | { | |
12634 | int i; | |
12635 | char rname[30]; | |
520a57c8 | 12636 | const char *alloc_rname; |
9ebbca7d GK |
12637 | rtvec p; |
12638 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
12639 | ||
12640 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
12641 | gen_rtx_REG (Pmode, | |
12642 | LINK_REGISTER_REGNUM)); | |
12643 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
12644 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 12645 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
12646 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
12647 | gen_rtx_SYMBOL_REF (Pmode, | |
12648 | alloc_rname)); | |
12649 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
12650 | { | |
12651 | rtx addr, reg, mem; | |
12652 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
12653 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12654 | GEN_INT (info->fp_save_offset | |
12655 | + sp_offset + 8*i)); | |
12656 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 12657 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
12658 | |
12659 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
12660 | } | |
12661 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
12662 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12663 | NULL_RTX, NULL_RTX); | |
12664 | } | |
b6c9286a | 12665 | |
9ebbca7d GK |
12666 | /* Save GPRs. This is done as a PARALLEL if we are using |
12667 | the store-multiple instructions. */ | |
12668 | if (using_store_multiple) | |
b6c9286a | 12669 | { |
308c142a | 12670 | rtvec p; |
9ebbca7d GK |
12671 | int i; |
12672 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
12673 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
12674 | { | |
12675 | rtx addr, reg, mem; | |
12676 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
12677 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12678 | GEN_INT (info->gp_save_offset | |
12679 | + sp_offset | |
12680 | + reg_size * i)); | |
12681 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 12682 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
12683 | |
12684 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
12685 | } | |
12686 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
12687 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12688 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
12689 | } |
12690 | else | |
12691 | { | |
9ebbca7d GK |
12692 | int i; |
12693 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
12694 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
b4db40bf JJ |
12695 | && (! call_used_regs[info->first_gp_reg_save+i] |
12696 | || (i+info->first_gp_reg_save | |
12697 | == RS6000_PIC_OFFSET_TABLE_REGNUM | |
12698 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 12699 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 12700 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 12701 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
12702 | { |
12703 | rtx addr, reg, mem; | |
12704 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
12705 | ||
c19de7aa | 12706 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12707 | { |
12708 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
12709 | rtx b; | |
12710 | ||
12711 | if (!SPE_CONST_OFFSET_OK (offset)) | |
12712 | { | |
12713 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
12714 | emit_move_insn (b, GEN_INT (offset)); | |
12715 | } | |
12716 | else | |
12717 | b = GEN_INT (offset); | |
12718 | ||
12719 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
12720 | mem = gen_rtx_MEM (V2SImode, addr); | |
12721 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12722 | insn = emit_move_insn (mem, reg); | |
12723 | ||
12724 | if (GET_CODE (b) == CONST_INT) | |
12725 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12726 | NULL_RTX, NULL_RTX); | |
12727 | else | |
12728 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12729 | b, GEN_INT (offset)); | |
12730 | } | |
12731 | else | |
12732 | { | |
12733 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12734 | GEN_INT (info->gp_save_offset | |
12735 | + sp_offset | |
12736 | + reg_size * i)); | |
12737 | mem = gen_rtx_MEM (reg_mode, addr); | |
12738 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12739 | ||
12740 | insn = emit_move_insn (mem, reg); | |
12741 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12742 | NULL_RTX, NULL_RTX); | |
12743 | } | |
12744 | } | |
9ebbca7d GK |
12745 | } |
12746 | ||
83720594 RH |
12747 | /* ??? There's no need to emit actual instructions here, but it's the |
12748 | easiest way to get the frame unwind information emitted. */ | |
12749 | if (current_function_calls_eh_return) | |
12750 | { | |
78e1b90d DE |
12751 | unsigned int i, regno; |
12752 | ||
fc4767bb JJ |
12753 | /* In AIX ABI we need to pretend we save r2 here. */ |
12754 | if (TARGET_AIX) | |
12755 | { | |
12756 | rtx addr, reg, mem; | |
12757 | ||
12758 | reg = gen_rtx_REG (reg_mode, 2); | |
12759 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12760 | GEN_INT (sp_offset + 5 * reg_size)); | |
12761 | mem = gen_rtx_MEM (reg_mode, addr); | |
12762 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12763 | ||
12764 | insn = emit_move_insn (mem, reg); | |
12765 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12766 | NULL_RTX, NULL_RTX); | |
12767 | PATTERN (insn) = gen_blockage (); | |
12768 | } | |
12769 | ||
83720594 RH |
12770 | for (i = 0; ; ++i) |
12771 | { | |
83720594 RH |
12772 | regno = EH_RETURN_DATA_REGNO (i); |
12773 | if (regno == INVALID_REGNUM) | |
12774 | break; | |
12775 | ||
89e7058f AH |
12776 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
12777 | info->ehrd_offset + sp_offset | |
12778 | + reg_size * (int) i, | |
12779 | info->total_size); | |
83720594 RH |
12780 | } |
12781 | } | |
12782 | ||
9ebbca7d GK |
12783 | /* Save lr if we used it. */ |
12784 | if (info->lr_save_p) | |
12785 | { | |
12786 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12787 | GEN_INT (info->lr_save_offset + sp_offset)); | |
12788 | rtx reg = gen_rtx_REG (Pmode, 0); | |
12789 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
12790 | /* This should not be of rs6000_sr_alias_set, because of | |
12791 | __builtin_return_address. */ | |
12792 | ||
12793 | insn = emit_move_insn (mem, reg); | |
12794 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
f8a57be8 | 12795 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
12796 | } |
12797 | ||
12798 | /* Save CR if we use any that must be preserved. */ | |
12799 | if (info->cr_save_p) | |
12800 | { | |
12801 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12802 | GEN_INT (info->cr_save_offset + sp_offset)); | |
12803 | rtx mem = gen_rtx_MEM (SImode, addr); | |
f8a57be8 GK |
12804 | /* See the large comment above about why CR2_REGNO is used. */ |
12805 | rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); | |
ba4828e0 RK |
12806 | |
12807 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
12808 | |
12809 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
12810 | that it's free. */ | |
12811 | if (REGNO (frame_reg_rtx) == 12) | |
12812 | { | |
f8a57be8 GK |
12813 | rtx set; |
12814 | ||
9ebbca7d | 12815 | cr_save_rtx = gen_rtx_REG (SImode, 0); |
f8a57be8 GK |
12816 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
12817 | RTX_FRAME_RELATED_P (insn) = 1; | |
12818 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); | |
12819 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12820 | set, | |
12821 | REG_NOTES (insn)); | |
12822 | ||
9ebbca7d GK |
12823 | } |
12824 | insn = emit_move_insn (mem, cr_save_rtx); | |
12825 | ||
9ebbca7d | 12826 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 12827 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
12828 | } |
12829 | ||
12830 | /* Update stack and set back pointer unless this is V.4, | |
12831 | for which it was done previously. */ | |
fc4767bb JJ |
12832 | if (info->push_p |
12833 | && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) | |
9ebbca7d GK |
12834 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
12835 | ||
12836 | /* Set frame pointer, if needed. */ | |
12837 | if (frame_pointer_needed) | |
12838 | { | |
a3170dc6 | 12839 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
12840 | sp_reg_rtx); |
12841 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 12842 | } |
9878760c | 12843 | |
1db02437 | 12844 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 12845 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
f607bc57 | 12846 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
1db02437 | 12847 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
9ebbca7d GK |
12848 | { |
12849 | /* If emit_load_toc_table will use the link register, we need to save | |
c4501e62 | 12850 | it. We use R12 for this purpose because emit_load_toc_table |
9ebbca7d GK |
12851 | can use register 0. This allows us to use a plain 'blr' to return |
12852 | from the procedure more often. */ | |
f1384257 AM |
12853 | int save_LR_around_toc_setup = (TARGET_ELF |
12854 | && DEFAULT_ABI != ABI_AIX | |
12855 | && flag_pic | |
d5fa86ba GK |
12856 | && ! info->lr_save_p |
12857 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d | 12858 | if (save_LR_around_toc_setup) |
c4501e62 JJ |
12859 | { |
12860 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f8a57be8 GK |
12861 | |
12862 | insn = emit_move_insn (frame_ptr_rtx, lr); | |
12863 | rs6000_maybe_dead (insn); | |
12864 | RTX_FRAME_RELATED_P (insn) = 1; | |
12865 | ||
c4501e62 | 12866 | rs6000_emit_load_toc_table (TRUE); |
f8a57be8 GK |
12867 | |
12868 | insn = emit_move_insn (lr, frame_ptr_rtx); | |
12869 | rs6000_maybe_dead (insn); | |
12870 | RTX_FRAME_RELATED_P (insn) = 1; | |
c4501e62 JJ |
12871 | } |
12872 | else | |
12873 | rs6000_emit_load_toc_table (TRUE); | |
9ebbca7d | 12874 | } |
ee890fe2 | 12875 | |
fcce224d | 12876 | #if TARGET_MACHO |
ee890fe2 SS |
12877 | if (DEFAULT_ABI == ABI_DARWIN |
12878 | && flag_pic && current_function_uses_pic_offset_table) | |
12879 | { | |
f8a57be8 | 12880 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
f099d360 | 12881 | const char *picbase = machopic_function_base_name (); |
6788f5ca | 12882 | rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase); |
ee890fe2 | 12883 | |
f8a57be8 | 12884 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); |
ee890fe2 | 12885 | |
f8a57be8 GK |
12886 | insn = emit_move_insn (gen_rtx_REG (Pmode, |
12887 | RS6000_PIC_OFFSET_TABLE_REGNUM), | |
12888 | lr); | |
12889 | rs6000_maybe_dead (insn); | |
ee890fe2 | 12890 | } |
fcce224d | 12891 | #endif |
9ebbca7d GK |
12892 | } |
12893 | ||
9ebbca7d | 12894 | /* Write function prologue. */ |
a4f6c312 | 12895 | |
08c148a8 | 12896 | static void |
a2369ed3 DJ |
12897 | rs6000_output_function_prologue (FILE *file, |
12898 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
9ebbca7d GK |
12899 | { |
12900 | rs6000_stack_t *info = rs6000_stack_info (); | |
12901 | ||
4697a36c MM |
12902 | if (TARGET_DEBUG_STACK) |
12903 | debug_stack_info (info); | |
9878760c | 12904 | |
a4f6c312 SS |
12905 | /* Write .extern for any function we will call to save and restore |
12906 | fp values. */ | |
12907 | if (info->first_fp_reg_save < 64 | |
12908 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 12909 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 12910 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
12911 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
12912 | RESTORE_FP_SUFFIX); | |
9878760c | 12913 | |
c764f757 RK |
12914 | /* Write .extern for AIX common mode routines, if needed. */ |
12915 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
12916 | { | |
f6709c70 JW |
12917 | fputs ("\t.extern __mulh\n", file); |
12918 | fputs ("\t.extern __mull\n", file); | |
12919 | fputs ("\t.extern __divss\n", file); | |
12920 | fputs ("\t.extern __divus\n", file); | |
12921 | fputs ("\t.extern __quoss\n", file); | |
12922 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
12923 | common_mode_defined = 1; |
12924 | } | |
9878760c | 12925 | |
9ebbca7d | 12926 | if (! HAVE_prologue) |
979721f8 | 12927 | { |
9ebbca7d | 12928 | start_sequence (); |
9dda4cc8 | 12929 | |
a4f6c312 SS |
12930 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
12931 | the "toplevel" insn chain. */ | |
2e040219 | 12932 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 12933 | rs6000_emit_prologue (); |
2e040219 | 12934 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 12935 | |
a3c9585f | 12936 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
12937 | { |
12938 | rtx insn; | |
12939 | unsigned addr = 0; | |
12940 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
12941 | { | |
12942 | INSN_ADDRESSES_NEW (insn, addr); | |
12943 | addr += 4; | |
12944 | } | |
12945 | } | |
9dda4cc8 | 12946 | |
9ebbca7d | 12947 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
12948 | debug_rtx_list (get_insns (), 100); |
12949 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 12950 | end_sequence (); |
979721f8 MM |
12951 | } |
12952 | ||
9ebbca7d GK |
12953 | rs6000_pic_labelno++; |
12954 | } | |
12955 | ||
12956 | /* Emit function epilogue as insns. | |
9878760c | 12957 | |
9ebbca7d GK |
12958 | At present, dwarf2out_frame_debug_expr doesn't understand |
12959 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
12960 | anywhere in the epilogue. Most of the insns below would in any case | |
12961 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 12962 | |
9ebbca7d | 12963 | void |
a2369ed3 | 12964 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
12965 | { |
12966 | rs6000_stack_t *info; | |
12967 | int restoring_FPRs_inline; | |
12968 | int using_load_multiple; | |
12969 | int using_mfcr_multiple; | |
12970 | int use_backchain_to_restore_sp; | |
12971 | int sp_offset = 0; | |
12972 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
12973 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a | 12974 | enum machine_mode reg_mode = Pmode; |
327e5343 | 12975 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
12976 | int i; |
12977 | ||
c19de7aa AH |
12978 | info = rs6000_stack_info (); |
12979 | ||
12980 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
12981 | { |
12982 | reg_mode = V2SImode; | |
12983 | reg_size = 8; | |
12984 | } | |
12985 | ||
9ebbca7d | 12986 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
12987 | && (!TARGET_SPE_ABI |
12988 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
12989 | && info->first_gp_reg_save < 31); |
12990 | restoring_FPRs_inline = (sibcall | |
83720594 | 12991 | || current_function_calls_eh_return |
9ebbca7d GK |
12992 | || info->first_fp_reg_save == 64 |
12993 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
12994 | use_backchain_to_restore_sp = (frame_pointer_needed | |
12995 | || current_function_calls_alloca | |
12996 | || info->total_size > 32767); | |
12997 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
12998 | || rs6000_cpu == PROCESSOR_PPC603 | |
12999 | || rs6000_cpu == PROCESSOR_PPC750 | |
13000 | || optimize_size); | |
13001 | ||
13002 | /* If we have a frame pointer, a call to alloca, or a large stack | |
13003 | frame, restore the old stack pointer using the backchain. Otherwise, | |
13004 | we know what size to update it with. */ | |
13005 | if (use_backchain_to_restore_sp) | |
bacbde18 | 13006 | { |
9ebbca7d GK |
13007 | /* Under V.4, don't reset the stack pointer until after we're done |
13008 | loading the saved registers. */ | |
f607bc57 | 13009 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 13010 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 13011 | |
9ebbca7d GK |
13012 | emit_move_insn (frame_reg_rtx, |
13013 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
13014 | ||
bacbde18 | 13015 | } |
9ebbca7d | 13016 | else if (info->push_p) |
85638c0d | 13017 | { |
fc4767bb JJ |
13018 | if (DEFAULT_ABI == ABI_V4 |
13019 | || current_function_calls_eh_return) | |
9ebbca7d GK |
13020 | sp_offset = info->total_size; |
13021 | else | |
13022 | { | |
13023 | emit_insn (TARGET_32BIT | |
13024 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
13025 | GEN_INT (info->total_size)) | |
13026 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
13027 | GEN_INT (info->total_size))); | |
13028 | } | |
85638c0d | 13029 | } |
9ebbca7d | 13030 | |
9aa86737 AH |
13031 | /* Restore AltiVec registers if needed. */ |
13032 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
13033 | { | |
13034 | int i; | |
13035 | ||
13036 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
13037 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
13038 | { | |
13039 | rtx addr, areg, mem; | |
13040 | ||
13041 | areg = gen_rtx_REG (Pmode, 0); | |
13042 | emit_move_insn | |
13043 | (areg, GEN_INT (info->altivec_save_offset | |
13044 | + sp_offset | |
13045 | + 16 * (i - info->first_altivec_reg_save))); | |
13046 | ||
13047 | /* AltiVec addressing mode is [reg+reg]. */ | |
13048 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
13049 | mem = gen_rtx_MEM (V4SImode, addr); | |
13050 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13051 | ||
13052 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
13053 | } | |
13054 | } | |
13055 | ||
13056 | /* Restore VRSAVE if needed. */ | |
44688022 | 13057 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
4d774ff8 | 13058 | && info->vrsave_mask != 0) |
9aa86737 AH |
13059 | { |
13060 | rtx addr, mem, reg; | |
13061 | ||
13062 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13063 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
13064 | mem = gen_rtx_MEM (SImode, addr); | |
13065 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13066 | reg = gen_rtx_REG (SImode, 12); | |
13067 | emit_move_insn (reg, mem); | |
13068 | ||
13069 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
13070 | } | |
13071 | ||
9ebbca7d GK |
13072 | /* Get the old lr if we saved it. */ |
13073 | if (info->lr_save_p) | |
b6c9286a | 13074 | { |
a3170dc6 AH |
13075 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
13076 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
13077 | |
13078 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 13079 | |
9ebbca7d | 13080 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 13081 | } |
9ebbca7d GK |
13082 | |
13083 | /* Get the old cr if we saved it. */ | |
13084 | if (info->cr_save_p) | |
13085 | { | |
13086 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13087 | GEN_INT (info->cr_save_offset + sp_offset)); | |
13088 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
13089 | |
13090 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 13091 | |
9ebbca7d GK |
13092 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
13093 | } | |
13094 | ||
13095 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 13096 | if (info->lr_save_p) |
9ebbca7d GK |
13097 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
13098 | gen_rtx_REG (Pmode, 0)); | |
13099 | ||
83720594 RH |
13100 | /* Load exception handler data registers, if needed. */ |
13101 | if (current_function_calls_eh_return) | |
13102 | { | |
78e1b90d DE |
13103 | unsigned int i, regno; |
13104 | ||
fc4767bb JJ |
13105 | if (TARGET_AIX) |
13106 | { | |
13107 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13108 | GEN_INT (sp_offset + 5 * reg_size)); | |
13109 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13110 | ||
13111 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13112 | ||
13113 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
13114 | } | |
13115 | ||
83720594 RH |
13116 | for (i = 0; ; ++i) |
13117 | { | |
a3170dc6 | 13118 | rtx mem; |
83720594 RH |
13119 | |
13120 | regno = EH_RETURN_DATA_REGNO (i); | |
13121 | if (regno == INVALID_REGNUM) | |
13122 | break; | |
13123 | ||
a3170dc6 AH |
13124 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
13125 | info->ehrd_offset + sp_offset | |
13126 | + reg_size * (int) i); | |
ba4828e0 | 13127 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
13128 | |
13129 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
13130 | } | |
13131 | } | |
9ebbca7d GK |
13132 | |
13133 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
13134 | the load-multiple instructions. */ | |
13135 | if (using_load_multiple) | |
979721f8 | 13136 | { |
9ebbca7d GK |
13137 | rtvec p; |
13138 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
13139 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 13140 | { |
9ebbca7d GK |
13141 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13142 | GEN_INT (info->gp_save_offset | |
13143 | + sp_offset | |
13144 | + reg_size * i)); | |
13145 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
13146 | |
13147 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
13148 | |
13149 | RTVEC_ELT (p, i) = | |
13150 | gen_rtx_SET (VOIDmode, | |
13151 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
13152 | mem); | |
979721f8 | 13153 | } |
9ebbca7d | 13154 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 13155 | } |
9ebbca7d GK |
13156 | else |
13157 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
13158 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
b4db40bf JJ |
13159 | && (! call_used_regs[info->first_gp_reg_save+i] |
13160 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM | |
13161 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 13162 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 13163 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 13164 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d GK |
13165 | { |
13166 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13167 | GEN_INT (info->gp_save_offset | |
13168 | + sp_offset | |
13169 | + reg_size * i)); | |
13170 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 13171 | |
a3170dc6 | 13172 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 13173 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
13174 | { |
13175 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
13176 | rtx b; | |
13177 | ||
13178 | if (!SPE_CONST_OFFSET_OK (offset)) | |
13179 | { | |
13180 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13181 | emit_move_insn (b, GEN_INT (offset)); | |
13182 | } | |
13183 | else | |
13184 | b = GEN_INT (offset); | |
13185 | ||
13186 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
13187 | mem = gen_rtx_MEM (V2SImode, addr); | |
13188 | } | |
13189 | ||
ba4828e0 | 13190 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13191 | |
13192 | emit_move_insn (gen_rtx_REG (reg_mode, | |
a3170dc6 | 13193 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 13194 | } |
9878760c | 13195 | |
9ebbca7d GK |
13196 | /* Restore fpr's if we need to do it without calling a function. */ |
13197 | if (restoring_FPRs_inline) | |
13198 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
13199 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
13200 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
13201 | { | |
13202 | rtx addr, mem; | |
13203 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13204 | GEN_INT (info->fp_save_offset | |
13205 | + sp_offset | |
a4f6c312 | 13206 | + 8 * i)); |
9ebbca7d | 13207 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 13208 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13209 | |
13210 | emit_move_insn (gen_rtx_REG (DFmode, | |
13211 | info->first_fp_reg_save + i), | |
13212 | mem); | |
13213 | } | |
8d30c4ee | 13214 | |
9ebbca7d GK |
13215 | /* If we saved cr, restore it here. Just those that were used. */ |
13216 | if (info->cr_save_p) | |
979721f8 | 13217 | { |
9ebbca7d | 13218 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 13219 | int count = 0; |
9ebbca7d GK |
13220 | |
13221 | if (using_mfcr_multiple) | |
979721f8 | 13222 | { |
9ebbca7d GK |
13223 | for (i = 0; i < 8; i++) |
13224 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 13225 | count++; |
9ebbca7d | 13226 | if (count == 0) |
e35b9579 GK |
13227 | abort (); |
13228 | } | |
13229 | ||
13230 | if (using_mfcr_multiple && count > 1) | |
13231 | { | |
13232 | rtvec p; | |
13233 | int ndx; | |
9ebbca7d | 13234 | |
e35b9579 | 13235 | p = rtvec_alloc (count); |
9ebbca7d | 13236 | |
e35b9579 | 13237 | ndx = 0; |
9ebbca7d GK |
13238 | for (i = 0; i < 8; i++) |
13239 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
13240 | { | |
13241 | rtvec r = rtvec_alloc (2); | |
13242 | RTVEC_ELT (r, 0) = r12_rtx; | |
13243 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 13244 | RTVEC_ELT (p, ndx) = |
9ebbca7d | 13245 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 13246 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 13247 | ndx++; |
9ebbca7d GK |
13248 | } |
13249 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
13250 | if (ndx != count) |
13251 | abort (); | |
979721f8 MM |
13252 | } |
13253 | else | |
9ebbca7d GK |
13254 | for (i = 0; i < 8; i++) |
13255 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 13256 | { |
9ebbca7d GK |
13257 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
13258 | CR0_REGNO+i), | |
13259 | r12_rtx)); | |
979721f8 | 13260 | } |
979721f8 MM |
13261 | } |
13262 | ||
9ebbca7d GK |
13263 | /* If this is V.4, unwind the stack pointer after all of the loads |
13264 | have been done. We need to emit a block here so that sched | |
13265 | doesn't decide to move the sp change before the register restores | |
13266 | (which may not have any obvious dependency on the stack). This | |
13267 | doesn't hurt performance, because there is no scheduling that can | |
13268 | be done after this point. */ | |
fc4767bb JJ |
13269 | if (DEFAULT_ABI == ABI_V4 |
13270 | || current_function_calls_eh_return) | |
b6c9286a | 13271 | { |
9ebbca7d GK |
13272 | if (frame_reg_rtx != sp_reg_rtx) |
13273 | rs6000_emit_stack_tie (); | |
b6c9286a | 13274 | |
9ebbca7d | 13275 | if (use_backchain_to_restore_sp) |
b6c9286a | 13276 | { |
9ebbca7d | 13277 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 13278 | } |
9ebbca7d | 13279 | else if (sp_offset != 0) |
13f1623b | 13280 | { |
5b71a4e7 | 13281 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
13282 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
13283 | GEN_INT (sp_offset)) | |
13284 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
13285 | GEN_INT (sp_offset))); | |
13f1623b | 13286 | } |
9ebbca7d | 13287 | } |
b6c9286a | 13288 | |
83720594 RH |
13289 | if (current_function_calls_eh_return) |
13290 | { | |
13291 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 13292 | emit_insn (TARGET_32BIT |
83720594 RH |
13293 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
13294 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
13295 | } | |
13296 | ||
9ebbca7d GK |
13297 | if (!sibcall) |
13298 | { | |
13299 | rtvec p; | |
13300 | if (! restoring_FPRs_inline) | |
13301 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
13302 | else | |
13303 | p = rtvec_alloc (2); | |
b6c9286a | 13304 | |
e35b9579 GK |
13305 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
13306 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
13307 | gen_rtx_REG (Pmode, |
13308 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
13309 | |
13310 | /* If we have to restore more than two FP registers, branch to the | |
13311 | restore function. It will return to our caller. */ | |
13312 | if (! restoring_FPRs_inline) | |
13313 | { | |
13314 | int i; | |
13315 | char rname[30]; | |
520a57c8 | 13316 | const char *alloc_rname; |
979721f8 | 13317 | |
9ebbca7d GK |
13318 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
13319 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 13320 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
13321 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
13322 | gen_rtx_SYMBOL_REF (Pmode, | |
13323 | alloc_rname)); | |
b6c9286a | 13324 | |
9ebbca7d GK |
13325 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
13326 | { | |
13327 | rtx addr, mem; | |
13328 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
13329 | GEN_INT (info->fp_save_offset + 8*i)); | |
13330 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 13331 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13332 | |
13333 | RTVEC_ELT (p, i+3) = | |
13334 | gen_rtx_SET (VOIDmode, | |
13335 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
13336 | mem); | |
b6c9286a MM |
13337 | } |
13338 | } | |
9ebbca7d GK |
13339 | |
13340 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 13341 | } |
9878760c RK |
13342 | } |
13343 | ||
13344 | /* Write function epilogue. */ | |
13345 | ||
08c148a8 | 13346 | static void |
a2369ed3 DJ |
13347 | rs6000_output_function_epilogue (FILE *file, |
13348 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
9878760c | 13349 | { |
4697a36c | 13350 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 13351 | |
9ebbca7d | 13352 | if (! HAVE_epilogue) |
9878760c | 13353 | { |
9ebbca7d GK |
13354 | rtx insn = get_last_insn (); |
13355 | /* If the last insn was a BARRIER, we don't have to write anything except | |
13356 | the trace table. */ | |
13357 | if (GET_CODE (insn) == NOTE) | |
13358 | insn = prev_nonnote_insn (insn); | |
13359 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 13360 | { |
9ebbca7d GK |
13361 | /* This is slightly ugly, but at least we don't have two |
13362 | copies of the epilogue-emitting code. */ | |
13363 | start_sequence (); | |
13364 | ||
13365 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
13366 | and end of the "toplevel" insn chain. */ | |
2e040219 | 13367 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13368 | rs6000_emit_epilogue (FALSE); |
2e040219 | 13369 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13370 | |
a3c9585f | 13371 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
13372 | { |
13373 | rtx insn; | |
13374 | unsigned addr = 0; | |
13375 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
13376 | { | |
13377 | INSN_ADDRESSES_NEW (insn, addr); | |
13378 | addr += 4; | |
13379 | } | |
13380 | } | |
13381 | ||
9ebbca7d | 13382 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
13383 | debug_rtx_list (get_insns (), 100); |
13384 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 13385 | end_sequence (); |
4697a36c | 13386 | } |
9878760c | 13387 | } |
b4ac57ab | 13388 | |
efdba735 SH |
13389 | #if TARGET_MACHO |
13390 | macho_branch_islands (); | |
0e5da0be GK |
13391 | /* Mach-O doesn't support labels at the end of objects, so if |
13392 | it looks like we might want one, insert a NOP. */ | |
13393 | { | |
13394 | rtx insn = get_last_insn (); | |
13395 | while (insn | |
13396 | && NOTE_P (insn) | |
13397 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) | |
13398 | insn = PREV_INSN (insn); | |
13399 | if (insn | |
13400 | && (LABEL_P (insn) | |
13401 | || (NOTE_P (insn) | |
13402 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) | |
13403 | fputs ("\tnop\n", file); | |
13404 | } | |
13405 | #endif | |
13406 | ||
9b30bae2 | 13407 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
13408 | on its format. |
13409 | ||
13410 | We don't output a traceback table if -finhibit-size-directive was | |
13411 | used. The documentation for -finhibit-size-directive reads | |
13412 | ``don't output a @code{.size} assembler directive, or anything | |
13413 | else that would cause trouble if the function is split in the | |
13414 | middle, and the two halves are placed at locations far apart in | |
13415 | memory.'' The traceback table has this property, since it | |
13416 | includes the offset from the start of the function to the | |
4d30c363 MM |
13417 | traceback table itself. |
13418 | ||
13419 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 13420 | different traceback table. */ |
57ac7be9 AM |
13421 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
13422 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 13423 | { |
69c75916 | 13424 | const char *fname = NULL; |
3ac88239 | 13425 | const char *language_string = lang_hooks.name; |
6041bf2f | 13426 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 13427 | int i; |
57ac7be9 AM |
13428 | int optional_tbtab; |
13429 | ||
13430 | if (rs6000_traceback == traceback_full) | |
13431 | optional_tbtab = 1; | |
13432 | else if (rs6000_traceback == traceback_part) | |
13433 | optional_tbtab = 0; | |
13434 | else | |
13435 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 13436 | |
69c75916 AM |
13437 | if (optional_tbtab) |
13438 | { | |
13439 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
13440 | while (*fname == '.') /* V.4 encodes . in the name */ | |
13441 | fname++; | |
13442 | ||
13443 | /* Need label immediately before tbtab, so we can compute | |
13444 | its offset from the function start. */ | |
13445 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
13446 | ASM_OUTPUT_LABEL (file, fname); | |
13447 | } | |
314fc5a9 ILT |
13448 | |
13449 | /* The .tbtab pseudo-op can only be used for the first eight | |
13450 | expressions, since it can't handle the possibly variable | |
13451 | length fields that follow. However, if you omit the optional | |
13452 | fields, the assembler outputs zeros for all optional fields | |
13453 | anyways, giving each variable length field is minimum length | |
13454 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
13455 | pseudo-op at all. */ | |
13456 | ||
13457 | /* An all-zero word flags the start of the tbtab, for debuggers | |
13458 | that have to find it by searching forward from the entry | |
13459 | point or from the current pc. */ | |
19d2d16f | 13460 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
13461 | |
13462 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 13463 | fputs ("\t.byte 0,", file); |
314fc5a9 | 13464 | |
5fc921c1 DE |
13465 | /* Language type. Unfortunately, there does not seem to be any |
13466 | official way to discover the language being compiled, so we | |
13467 | use language_string. | |
13468 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
13469 | Java is 13. Objective-C is 14. */ | |
13470 | if (! strcmp (language_string, "GNU C")) | |
314fc5a9 | 13471 | i = 0; |
6de9cd9a DN |
13472 | else if (! strcmp (language_string, "GNU F77") |
13473 | || ! strcmp (language_string, "GNU F95")) | |
314fc5a9 | 13474 | i = 1; |
8b83775b | 13475 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 13476 | i = 2; |
5fc921c1 DE |
13477 | else if (! strcmp (language_string, "GNU Ada")) |
13478 | i = 3; | |
314fc5a9 ILT |
13479 | else if (! strcmp (language_string, "GNU C++")) |
13480 | i = 9; | |
9517ead8 AG |
13481 | else if (! strcmp (language_string, "GNU Java")) |
13482 | i = 13; | |
5fc921c1 DE |
13483 | else if (! strcmp (language_string, "GNU Objective-C")) |
13484 | i = 14; | |
314fc5a9 ILT |
13485 | else |
13486 | abort (); | |
13487 | fprintf (file, "%d,", i); | |
13488 | ||
13489 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
13490 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
13491 | from start of procedure stored in tbtab, internal function, function | |
13492 | has controlled storage, function has no toc, function uses fp, | |
13493 | function logs/aborts fp operations. */ | |
13494 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
13495 | fprintf (file, "%d,", |
13496 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
13497 | |
13498 | /* 6 bitfields: function is interrupt handler, name present in | |
13499 | proc table, function calls alloca, on condition directives | |
13500 | (controls stack walks, 3 bits), saves condition reg, saves | |
13501 | link reg. */ | |
13502 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
13503 | set up as a frame pointer, even when there is no alloca call. */ | |
13504 | fprintf (file, "%d,", | |
6041bf2f DE |
13505 | ((optional_tbtab << 6) |
13506 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
13507 | | (info->cr_save_p << 1) | |
13508 | | (info->lr_save_p))); | |
314fc5a9 | 13509 | |
6041bf2f | 13510 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
13511 | (6 bits). */ |
13512 | fprintf (file, "%d,", | |
4697a36c | 13513 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
13514 | |
13515 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
13516 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
13517 | ||
6041bf2f DE |
13518 | if (optional_tbtab) |
13519 | { | |
13520 | /* Compute the parameter info from the function decl argument | |
13521 | list. */ | |
13522 | tree decl; | |
13523 | int next_parm_info_bit = 31; | |
314fc5a9 | 13524 | |
6041bf2f DE |
13525 | for (decl = DECL_ARGUMENTS (current_function_decl); |
13526 | decl; decl = TREE_CHAIN (decl)) | |
13527 | { | |
13528 | rtx parameter = DECL_INCOMING_RTL (decl); | |
13529 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 13530 | |
6041bf2f DE |
13531 | if (GET_CODE (parameter) == REG) |
13532 | { | |
13533 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
13534 | { | |
13535 | int bits; | |
13536 | ||
13537 | float_parms++; | |
13538 | ||
13539 | if (mode == SFmode) | |
13540 | bits = 0x2; | |
fcce224d | 13541 | else if (mode == DFmode || mode == TFmode) |
6041bf2f DE |
13542 | bits = 0x3; |
13543 | else | |
13544 | abort (); | |
13545 | ||
13546 | /* If only one bit will fit, don't or in this entry. */ | |
13547 | if (next_parm_info_bit > 0) | |
13548 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
13549 | next_parm_info_bit -= 2; | |
13550 | } | |
13551 | else | |
13552 | { | |
13553 | fixed_parms += ((GET_MODE_SIZE (mode) | |
13554 | + (UNITS_PER_WORD - 1)) | |
13555 | / UNITS_PER_WORD); | |
13556 | next_parm_info_bit -= 1; | |
13557 | } | |
13558 | } | |
13559 | } | |
13560 | } | |
314fc5a9 ILT |
13561 | |
13562 | /* Number of fixed point parameters. */ | |
13563 | /* This is actually the number of words of fixed point parameters; thus | |
13564 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
13565 | fprintf (file, "%d,", fixed_parms); | |
13566 | ||
13567 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
13568 | all on stack. */ | |
13569 | /* This is actually the number of fp registers that hold parameters; | |
13570 | and thus the maximum value is 13. */ | |
13571 | /* Set parameters on stack bit if parameters are not in their original | |
13572 | registers, regardless of whether they are on the stack? Xlc | |
13573 | seems to set the bit when not optimizing. */ | |
13574 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
13575 | ||
6041bf2f DE |
13576 | if (! optional_tbtab) |
13577 | return; | |
13578 | ||
314fc5a9 ILT |
13579 | /* Optional fields follow. Some are variable length. */ |
13580 | ||
13581 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
13582 | 11 double float. */ | |
13583 | /* There is an entry for each parameter in a register, in the order that | |
13584 | they occur in the parameter list. Any intervening arguments on the | |
13585 | stack are ignored. If the list overflows a long (max possible length | |
13586 | 34 bits) then completely leave off all elements that don't fit. */ | |
13587 | /* Only emit this long if there was at least one parameter. */ | |
13588 | if (fixed_parms || float_parms) | |
13589 | fprintf (file, "\t.long %d\n", parm_info); | |
13590 | ||
13591 | /* Offset from start of code to tb table. */ | |
19d2d16f | 13592 | fputs ("\t.long ", file); |
314fc5a9 | 13593 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
13594 | #if TARGET_AIX |
13595 | RS6000_OUTPUT_BASENAME (file, fname); | |
13596 | #else | |
9ebbca7d | 13597 | assemble_name (file, fname); |
54ee9799 | 13598 | #endif |
19d2d16f | 13599 | fputs ("-.", file); |
54ee9799 DE |
13600 | #if TARGET_AIX |
13601 | RS6000_OUTPUT_BASENAME (file, fname); | |
13602 | #else | |
9ebbca7d | 13603 | assemble_name (file, fname); |
54ee9799 | 13604 | #endif |
19d2d16f | 13605 | putc ('\n', file); |
314fc5a9 ILT |
13606 | |
13607 | /* Interrupt handler mask. */ | |
13608 | /* Omit this long, since we never set the interrupt handler bit | |
13609 | above. */ | |
13610 | ||
13611 | /* Number of CTL (controlled storage) anchors. */ | |
13612 | /* Omit this long, since the has_ctl bit is never set above. */ | |
13613 | ||
13614 | /* Displacement into stack of each CTL anchor. */ | |
13615 | /* Omit this list of longs, because there are no CTL anchors. */ | |
13616 | ||
13617 | /* Length of function name. */ | |
69c75916 AM |
13618 | if (*fname == '*') |
13619 | ++fname; | |
296b8152 | 13620 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
13621 | |
13622 | /* Function name. */ | |
13623 | assemble_string (fname, strlen (fname)); | |
13624 | ||
13625 | /* Register for alloca automatic storage; this is always reg 31. | |
13626 | Only emit this if the alloca bit was set above. */ | |
13627 | if (frame_pointer_needed) | |
19d2d16f | 13628 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
13629 | |
13630 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 13631 | } |
9878760c | 13632 | } |
17167fd8 | 13633 | \f |
a4f6c312 SS |
13634 | /* A C compound statement that outputs the assembler code for a thunk |
13635 | function, used to implement C++ virtual function calls with | |
13636 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
13637 | function, adjusting the implicit object parameter before handing | |
13638 | control off to the real function. | |
13639 | ||
13640 | First, emit code to add the integer DELTA to the location that | |
13641 | contains the incoming first argument. Assume that this argument | |
13642 | contains a pointer, and is the one used to pass the `this' pointer | |
13643 | in C++. This is the incoming argument *before* the function | |
13644 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
13645 | values of all other incoming arguments. | |
17167fd8 MM |
13646 | |
13647 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
13648 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
13649 | not touch the return address. Hence returning from FUNCTION will | |
13650 | return to whoever called the current `thunk'. | |
17167fd8 | 13651 | |
a4f6c312 SS |
13652 | The effect must be as if FUNCTION had been called directly with the |
13653 | adjusted first argument. This macro is responsible for emitting | |
13654 | all of the code for a thunk function; output_function_prologue() | |
13655 | and output_function_epilogue() are not invoked. | |
17167fd8 | 13656 | |
a4f6c312 SS |
13657 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
13658 | been extracted from it.) It might possibly be useful on some | |
13659 | targets, but probably not. | |
17167fd8 | 13660 | |
a4f6c312 SS |
13661 | If you do not define this macro, the target-independent code in the |
13662 | C++ frontend will generate a less efficient heavyweight thunk that | |
13663 | calls FUNCTION instead of jumping to it. The generic approach does | |
13664 | not support varargs. */ | |
17167fd8 | 13665 | |
3961e8fe | 13666 | static void |
a2369ed3 DJ |
13667 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
13668 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
13669 | tree function) | |
17167fd8 | 13670 | { |
5b71a4e7 | 13671 | rtx this, insn, funexp; |
17167fd8 | 13672 | |
5b71a4e7 | 13673 | reload_completed = 1; |
fe3ad572 | 13674 | epilogue_completed = 1; |
5b71a4e7 | 13675 | no_new_pseudos = 1; |
6429e3be | 13676 | reset_block_changes (); |
56a7189a | 13677 | |
5b71a4e7 | 13678 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 13679 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 13680 | |
5b71a4e7 DE |
13681 | /* Find the "this" pointer. If the function returns a structure, |
13682 | the structure return pointer is in r3. */ | |
61f71b34 | 13683 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
5b71a4e7 | 13684 | this = gen_rtx_REG (Pmode, 4); |
56a7189a | 13685 | else |
5b71a4e7 | 13686 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 13687 | |
5b71a4e7 DE |
13688 | /* Apply the constant offset, if required. */ |
13689 | if (delta) | |
13690 | { | |
13691 | rtx delta_rtx = GEN_INT (delta); | |
13692 | emit_insn (TARGET_32BIT | |
13693 | ? gen_addsi3 (this, this, delta_rtx) | |
13694 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
13695 | } |
13696 | ||
5b71a4e7 DE |
13697 | /* Apply the offset from the vtable, if required. */ |
13698 | if (vcall_offset) | |
17167fd8 | 13699 | { |
5b71a4e7 DE |
13700 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
13701 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 13702 | |
5b71a4e7 | 13703 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
eeff9307 JJ |
13704 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
13705 | { | |
13706 | emit_insn (TARGET_32BIT | |
13707 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
13708 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
13709 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
13710 | } | |
13711 | else | |
13712 | { | |
13713 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
13714 | ||
13715 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
13716 | } | |
5b71a4e7 DE |
13717 | emit_insn (TARGET_32BIT |
13718 | ? gen_addsi3 (this, this, tmp) | |
13719 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
13720 | } |
13721 | ||
5b71a4e7 DE |
13722 | /* Generate a tail call to the target function. */ |
13723 | if (!TREE_USED (function)) | |
13724 | { | |
13725 | assemble_external (function); | |
13726 | TREE_USED (function) = 1; | |
13727 | } | |
13728 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 13729 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
13730 | |
13731 | #if TARGET_MACHO | |
ab82a49f | 13732 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 13733 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 13734 | #endif |
5b71a4e7 DE |
13735 | |
13736 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
13737 | generate sibcall RTL explicitly to avoid constraint abort. */ | |
13738 | insn = emit_call_insn ( | |
13739 | gen_rtx_PARALLEL (VOIDmode, | |
13740 | gen_rtvec (4, | |
13741 | gen_rtx_CALL (VOIDmode, | |
13742 | funexp, const0_rtx), | |
13743 | gen_rtx_USE (VOIDmode, const0_rtx), | |
13744 | gen_rtx_USE (VOIDmode, | |
13745 | gen_rtx_REG (SImode, | |
13746 | LINK_REGISTER_REGNUM)), | |
13747 | gen_rtx_RETURN (VOIDmode)))); | |
13748 | SIBLING_CALL_P (insn) = 1; | |
13749 | emit_barrier (); | |
13750 | ||
13751 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
13752 | There's not really enough bulk here to make other passes such as | |
13753 | instruction scheduling worth while. Note that use_thunk calls | |
13754 | assemble_start_function and assemble_end_function. */ | |
13755 | insn = get_insns (); | |
a2855205 | 13756 | insn_locators_initialize (); |
5b71a4e7 DE |
13757 | shorten_branches (insn); |
13758 | final_start_function (insn, file, 1); | |
13759 | final (insn, file, 1, 0); | |
13760 | final_end_function (); | |
13761 | ||
13762 | reload_completed = 0; | |
fe3ad572 | 13763 | epilogue_completed = 0; |
5b71a4e7 | 13764 | no_new_pseudos = 0; |
9ebbca7d | 13765 | } |
9ebbca7d GK |
13766 | \f |
13767 | /* A quick summary of the various types of 'constant-pool tables' | |
13768 | under PowerPC: | |
13769 | ||
13770 | Target Flags Name One table per | |
13771 | AIX (none) AIX TOC object file | |
13772 | AIX -mfull-toc AIX TOC object file | |
13773 | AIX -mminimal-toc AIX minimal TOC translation unit | |
13774 | SVR4/EABI (none) SVR4 SDATA object file | |
13775 | SVR4/EABI -fpic SVR4 pic object file | |
13776 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
13777 | SVR4/EABI -mrelocatable EABI TOC function | |
13778 | SVR4/EABI -maix AIX TOC object file | |
13779 | SVR4/EABI -maix -mminimal-toc | |
13780 | AIX minimal TOC translation unit | |
13781 | ||
13782 | Name Reg. Set by entries contains: | |
13783 | made by addrs? fp? sum? | |
13784 | ||
13785 | AIX TOC 2 crt0 as Y option option | |
13786 | AIX minimal TOC 30 prolog gcc Y Y option | |
13787 | SVR4 SDATA 13 crt0 gcc N Y N | |
13788 | SVR4 pic 30 prolog ld Y not yet N | |
13789 | SVR4 PIC 30 prolog gcc Y option option | |
13790 | EABI TOC 30 prolog gcc Y option option | |
13791 | ||
13792 | */ | |
13793 | ||
9ebbca7d GK |
13794 | /* Hash functions for the hash table. */ |
13795 | ||
13796 | static unsigned | |
a2369ed3 | 13797 | rs6000_hash_constant (rtx k) |
9ebbca7d | 13798 | { |
46b33600 RH |
13799 | enum rtx_code code = GET_CODE (k); |
13800 | enum machine_mode mode = GET_MODE (k); | |
13801 | unsigned result = (code << 3) ^ mode; | |
13802 | const char *format; | |
13803 | int flen, fidx; | |
9ebbca7d | 13804 | |
46b33600 RH |
13805 | format = GET_RTX_FORMAT (code); |
13806 | flen = strlen (format); | |
13807 | fidx = 0; | |
9ebbca7d | 13808 | |
46b33600 RH |
13809 | switch (code) |
13810 | { | |
13811 | case LABEL_REF: | |
13812 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
13813 | ||
13814 | case CONST_DOUBLE: | |
13815 | if (mode != VOIDmode) | |
13816 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
13817 | flen = 2; | |
13818 | break; | |
13819 | ||
13820 | case CODE_LABEL: | |
13821 | fidx = 3; | |
13822 | break; | |
13823 | ||
13824 | default: | |
13825 | break; | |
13826 | } | |
9ebbca7d GK |
13827 | |
13828 | for (; fidx < flen; fidx++) | |
13829 | switch (format[fidx]) | |
13830 | { | |
13831 | case 's': | |
13832 | { | |
13833 | unsigned i, len; | |
13834 | const char *str = XSTR (k, fidx); | |
13835 | len = strlen (str); | |
13836 | result = result * 613 + len; | |
13837 | for (i = 0; i < len; i++) | |
13838 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
13839 | break; |
13840 | } | |
9ebbca7d GK |
13841 | case 'u': |
13842 | case 'e': | |
13843 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
13844 | break; | |
13845 | case 'i': | |
13846 | case 'n': | |
13847 | result = result * 613 + (unsigned) XINT (k, fidx); | |
13848 | break; | |
13849 | case 'w': | |
13850 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
13851 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
13852 | else | |
13853 | { | |
13854 | size_t i; | |
13855 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
13856 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
13857 | >> CHAR_BIT * i); | |
13858 | } | |
13859 | break; | |
09501938 DE |
13860 | case '0': |
13861 | break; | |
9ebbca7d | 13862 | default: |
a4f6c312 | 13863 | abort (); |
9ebbca7d | 13864 | } |
46b33600 | 13865 | |
9ebbca7d GK |
13866 | return result; |
13867 | } | |
13868 | ||
13869 | static unsigned | |
a2369ed3 | 13870 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 13871 | { |
a9098fd0 GK |
13872 | const struct toc_hash_struct *thc = |
13873 | (const struct toc_hash_struct *) hash_entry; | |
13874 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
13875 | } |
13876 | ||
13877 | /* Compare H1 and H2 for equivalence. */ | |
13878 | ||
13879 | static int | |
a2369ed3 | 13880 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
13881 | { |
13882 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
13883 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
13884 | ||
a9098fd0 GK |
13885 | if (((const struct toc_hash_struct *) h1)->key_mode |
13886 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
13887 | return 0; | |
13888 | ||
5692c7bc | 13889 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
13890 | } |
13891 | ||
28e510bd MM |
13892 | /* These are the names given by the C++ front-end to vtables, and |
13893 | vtable-like objects. Ideally, this logic should not be here; | |
13894 | instead, there should be some programmatic way of inquiring as | |
13895 | to whether or not an object is a vtable. */ | |
13896 | ||
13897 | #define VTABLE_NAME_P(NAME) \ | |
13898 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
13899 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
13900 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
26be75db | 13901 | || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ |
28e510bd MM |
13902 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) |
13903 | ||
13904 | void | |
a2369ed3 | 13905 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
13906 | { |
13907 | /* Currently C++ toc references to vtables can be emitted before it | |
13908 | is decided whether the vtable is public or private. If this is | |
13909 | the case, then the linker will eventually complain that there is | |
13910 | a reference to an unknown section. Thus, for vtables only, | |
13911 | we emit the TOC reference to reference the symbol and not the | |
13912 | section. */ | |
13913 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
13914 | |
13915 | if (VTABLE_NAME_P (name)) | |
13916 | { | |
13917 | RS6000_OUTPUT_BASENAME (file, name); | |
13918 | } | |
13919 | else | |
13920 | assemble_name (file, name); | |
28e510bd MM |
13921 | } |
13922 | ||
a4f6c312 SS |
13923 | /* Output a TOC entry. We derive the entry name from what is being |
13924 | written. */ | |
9878760c RK |
13925 | |
13926 | void | |
a2369ed3 | 13927 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
13928 | { |
13929 | char buf[256]; | |
3cce094d | 13930 | const char *name = buf; |
ec940faa | 13931 | const char *real_name; |
9878760c RK |
13932 | rtx base = x; |
13933 | int offset = 0; | |
13934 | ||
4697a36c MM |
13935 | if (TARGET_NO_TOC) |
13936 | abort (); | |
13937 | ||
9ebbca7d GK |
13938 | /* When the linker won't eliminate them, don't output duplicate |
13939 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
13940 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
13941 | CODE_LABELs. */ | |
13942 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
13943 | { |
13944 | struct toc_hash_struct *h; | |
13945 | void * * found; | |
13946 | ||
17211ab5 | 13947 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
39e3f58c | 13948 | time because GGC is not initialized at that point. */ |
17211ab5 GK |
13949 | if (toc_hash_table == NULL) |
13950 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, | |
13951 | toc_hash_eq, NULL); | |
13952 | ||
9ebbca7d GK |
13953 | h = ggc_alloc (sizeof (*h)); |
13954 | h->key = x; | |
a9098fd0 | 13955 | h->key_mode = mode; |
9ebbca7d GK |
13956 | h->labelno = labelno; |
13957 | ||
13958 | found = htab_find_slot (toc_hash_table, h, 1); | |
13959 | if (*found == NULL) | |
13960 | *found = h; | |
13961 | else /* This is indeed a duplicate. | |
13962 | Set this label equal to that label. */ | |
13963 | { | |
13964 | fputs ("\t.set ", file); | |
13965 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
13966 | fprintf (file, "%d,", labelno); | |
13967 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
13968 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
13969 | found)->labelno)); | |
13970 | return; | |
13971 | } | |
13972 | } | |
13973 | ||
13974 | /* If we're going to put a double constant in the TOC, make sure it's | |
13975 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
13976 | if (GET_CODE (x) == CONST_DOUBLE |
13977 | && STRICT_ALIGNMENT | |
a9098fd0 | 13978 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
13979 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
13980 | ASM_OUTPUT_ALIGN (file, 3); | |
13981 | } | |
13982 | ||
4977bab6 | 13983 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 13984 | |
37c37a57 RK |
13985 | /* Handle FP constants specially. Note that if we have a minimal |
13986 | TOC, things we put here aren't actually in the TOC, so we can allow | |
13987 | FP constants. */ | |
fcce224d DE |
13988 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
13989 | { | |
13990 | REAL_VALUE_TYPE rv; | |
13991 | long k[4]; | |
13992 | ||
13993 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
13994 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
13995 | ||
13996 | if (TARGET_64BIT) | |
13997 | { | |
13998 | if (TARGET_MINIMAL_TOC) | |
13999 | fputs (DOUBLE_INT_ASM_OP, file); | |
14000 | else | |
14001 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
14002 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14003 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14004 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
14005 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14006 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14007 | return; | |
14008 | } | |
14009 | else | |
14010 | { | |
14011 | if (TARGET_MINIMAL_TOC) | |
14012 | fputs ("\t.long ", file); | |
14013 | else | |
14014 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
14015 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14016 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14017 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
14018 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14019 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14020 | return; | |
14021 | } | |
14022 | } | |
14023 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 14024 | { |
042259f2 DE |
14025 | REAL_VALUE_TYPE rv; |
14026 | long k[2]; | |
0adc764e | 14027 | |
042259f2 DE |
14028 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
14029 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 14030 | |
13ded975 DE |
14031 | if (TARGET_64BIT) |
14032 | { | |
14033 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14034 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 14035 | else |
2f0552b6 AM |
14036 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
14037 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
14038 | fprintf (file, "0x%lx%08lx\n", | |
14039 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
14040 | return; |
14041 | } | |
1875cc88 | 14042 | else |
13ded975 DE |
14043 | { |
14044 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14045 | fputs ("\t.long ", file); |
13ded975 | 14046 | else |
2f0552b6 AM |
14047 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
14048 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
14049 | fprintf (file, "0x%lx,0x%lx\n", | |
14050 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
14051 | return; |
14052 | } | |
9878760c | 14053 | } |
a9098fd0 | 14054 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 14055 | { |
042259f2 DE |
14056 | REAL_VALUE_TYPE rv; |
14057 | long l; | |
9878760c | 14058 | |
042259f2 DE |
14059 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
14060 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
14061 | ||
31bfaa0b DE |
14062 | if (TARGET_64BIT) |
14063 | { | |
14064 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14065 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 14066 | else |
2f0552b6 AM |
14067 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
14068 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
14069 | return; |
14070 | } | |
042259f2 | 14071 | else |
31bfaa0b DE |
14072 | { |
14073 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14074 | fputs ("\t.long ", file); |
31bfaa0b | 14075 | else |
2f0552b6 AM |
14076 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
14077 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
14078 | return; |
14079 | } | |
042259f2 | 14080 | } |
f176e826 | 14081 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 14082 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 14083 | { |
e2c953b6 | 14084 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
14085 | HOST_WIDE_INT high; |
14086 | ||
14087 | if (GET_CODE (x) == CONST_DOUBLE) | |
14088 | { | |
14089 | low = CONST_DOUBLE_LOW (x); | |
14090 | high = CONST_DOUBLE_HIGH (x); | |
14091 | } | |
14092 | else | |
14093 | #if HOST_BITS_PER_WIDE_INT == 32 | |
14094 | { | |
14095 | low = INTVAL (x); | |
0858c623 | 14096 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
14097 | } |
14098 | #else | |
14099 | { | |
0858c623 | 14100 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
14101 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
14102 | } | |
14103 | #endif | |
9878760c | 14104 | |
a9098fd0 GK |
14105 | /* TOC entries are always Pmode-sized, but since this |
14106 | is a bigendian machine then if we're putting smaller | |
14107 | integer constants in the TOC we have to pad them. | |
14108 | (This is still a win over putting the constants in | |
14109 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
14110 | to have both a TOC entry _and_ the actual constant.) |
14111 | ||
14112 | For a 32-bit target, CONST_INT values are loaded and shifted | |
14113 | entirely within `low' and can be stored in one TOC entry. */ | |
14114 | ||
14115 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 14116 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
14117 | |
14118 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
14119 | { |
14120 | #if HOST_BITS_PER_WIDE_INT == 32 | |
14121 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
14122 | POINTER_SIZE, &low, &high, 0); | |
14123 | #else | |
14124 | low |= high << 32; | |
14125 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
14126 | high = (HOST_WIDE_INT) low >> 32; | |
14127 | low &= 0xffffffff; | |
14128 | #endif | |
14129 | } | |
a9098fd0 | 14130 | |
13ded975 DE |
14131 | if (TARGET_64BIT) |
14132 | { | |
14133 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14134 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 14135 | else |
2f0552b6 AM |
14136 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
14137 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
14138 | fprintf (file, "0x%lx%08lx\n", | |
14139 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
14140 | return; |
14141 | } | |
1875cc88 | 14142 | else |
13ded975 | 14143 | { |
02a4ec28 FS |
14144 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
14145 | { | |
14146 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14147 | fputs ("\t.long ", file); |
02a4ec28 | 14148 | else |
2bfcf297 | 14149 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
14150 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
14151 | fprintf (file, "0x%lx,0x%lx\n", | |
14152 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 14153 | } |
13ded975 | 14154 | else |
02a4ec28 FS |
14155 | { |
14156 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14157 | fputs ("\t.long ", file); |
02a4ec28 | 14158 | else |
2f0552b6 AM |
14159 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
14160 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 14161 | } |
13ded975 DE |
14162 | return; |
14163 | } | |
9878760c RK |
14164 | } |
14165 | ||
14166 | if (GET_CODE (x) == CONST) | |
14167 | { | |
2bfcf297 DB |
14168 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
14169 | abort (); | |
14170 | ||
9878760c RK |
14171 | base = XEXP (XEXP (x, 0), 0); |
14172 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
14173 | } | |
14174 | ||
14175 | if (GET_CODE (base) == SYMBOL_REF) | |
14176 | name = XSTR (base, 0); | |
14177 | else if (GET_CODE (base) == LABEL_REF) | |
14178 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
14179 | else if (GET_CODE (base) == CODE_LABEL) | |
14180 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
14181 | else | |
14182 | abort (); | |
14183 | ||
772c5265 | 14184 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 14185 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 14186 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
14187 | else |
14188 | { | |
b6c9286a | 14189 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 14190 | |
1875cc88 JW |
14191 | if (offset < 0) |
14192 | fprintf (file, ".N%d", - offset); | |
14193 | else if (offset) | |
14194 | fprintf (file, ".P%d", offset); | |
9878760c | 14195 | |
19d2d16f | 14196 | fputs ("[TC],", file); |
1875cc88 | 14197 | } |
581bc4de MM |
14198 | |
14199 | /* Currently C++ toc references to vtables can be emitted before it | |
14200 | is decided whether the vtable is public or private. If this is | |
14201 | the case, then the linker will eventually complain that there is | |
14202 | a TOC reference to an unknown section. Thus, for vtables only, | |
14203 | we emit the TOC reference to reference the symbol and not the | |
14204 | section. */ | |
28e510bd | 14205 | if (VTABLE_NAME_P (name)) |
581bc4de | 14206 | { |
54ee9799 | 14207 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
14208 | if (offset < 0) |
14209 | fprintf (file, "%d", offset); | |
14210 | else if (offset > 0) | |
14211 | fprintf (file, "+%d", offset); | |
14212 | } | |
14213 | else | |
14214 | output_addr_const (file, x); | |
19d2d16f | 14215 | putc ('\n', file); |
9878760c RK |
14216 | } |
14217 | \f | |
14218 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
14219 | starting at P to FILE. | |
14220 | ||
14221 | On the RS/6000, we have to do this using the .byte operation and | |
14222 | write out special characters outside the quoted string. | |
14223 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 14224 | so we must artificially break them up early. */ |
9878760c RK |
14225 | |
14226 | void | |
a2369ed3 | 14227 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
14228 | { |
14229 | char c; | |
14230 | int i, count_string; | |
d330fd93 KG |
14231 | const char *for_string = "\t.byte \""; |
14232 | const char *for_decimal = "\t.byte "; | |
14233 | const char *to_close = NULL; | |
9878760c RK |
14234 | |
14235 | count_string = 0; | |
14236 | for (i = 0; i < n; i++) | |
14237 | { | |
14238 | c = *p++; | |
14239 | if (c >= ' ' && c < 0177) | |
14240 | { | |
14241 | if (for_string) | |
14242 | fputs (for_string, file); | |
14243 | putc (c, file); | |
14244 | ||
14245 | /* Write two quotes to get one. */ | |
14246 | if (c == '"') | |
14247 | { | |
14248 | putc (c, file); | |
14249 | ++count_string; | |
14250 | } | |
14251 | ||
14252 | for_string = NULL; | |
14253 | for_decimal = "\"\n\t.byte "; | |
14254 | to_close = "\"\n"; | |
14255 | ++count_string; | |
14256 | ||
14257 | if (count_string >= 512) | |
14258 | { | |
14259 | fputs (to_close, file); | |
14260 | ||
14261 | for_string = "\t.byte \""; | |
14262 | for_decimal = "\t.byte "; | |
14263 | to_close = NULL; | |
14264 | count_string = 0; | |
14265 | } | |
14266 | } | |
14267 | else | |
14268 | { | |
14269 | if (for_decimal) | |
14270 | fputs (for_decimal, file); | |
14271 | fprintf (file, "%d", c); | |
14272 | ||
14273 | for_string = "\n\t.byte \""; | |
14274 | for_decimal = ", "; | |
14275 | to_close = "\n"; | |
14276 | count_string = 0; | |
14277 | } | |
14278 | } | |
14279 | ||
14280 | /* Now close the string if we have written one. Then end the line. */ | |
14281 | if (to_close) | |
9ebbca7d | 14282 | fputs (to_close, file); |
9878760c RK |
14283 | } |
14284 | \f | |
14285 | /* Generate a unique section name for FILENAME for a section type | |
14286 | represented by SECTION_DESC. Output goes into BUF. | |
14287 | ||
14288 | SECTION_DESC can be any string, as long as it is different for each | |
14289 | possible section type. | |
14290 | ||
14291 | We name the section in the same manner as xlc. The name begins with an | |
14292 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
14293 | names) with the last period replaced by the string SECTION_DESC. If |
14294 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
14295 | the name. */ | |
9878760c RK |
14296 | |
14297 | void | |
a2369ed3 DJ |
14298 | rs6000_gen_section_name (char **buf, const char *filename, |
14299 | const char *section_desc) | |
9878760c | 14300 | { |
9ebbca7d | 14301 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
14302 | char *p; |
14303 | int len; | |
9878760c RK |
14304 | |
14305 | after_last_slash = filename; | |
14306 | for (q = filename; *q; q++) | |
11e5fe42 RK |
14307 | { |
14308 | if (*q == '/') | |
14309 | after_last_slash = q + 1; | |
14310 | else if (*q == '.') | |
14311 | last_period = q; | |
14312 | } | |
9878760c | 14313 | |
11e5fe42 | 14314 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 14315 | *buf = (char *) xmalloc (len); |
9878760c RK |
14316 | |
14317 | p = *buf; | |
14318 | *p++ = '_'; | |
14319 | ||
14320 | for (q = after_last_slash; *q; q++) | |
14321 | { | |
11e5fe42 | 14322 | if (q == last_period) |
9878760c RK |
14323 | { |
14324 | strcpy (p, section_desc); | |
14325 | p += strlen (section_desc); | |
e3981aab | 14326 | break; |
9878760c RK |
14327 | } |
14328 | ||
e9a780ec | 14329 | else if (ISALNUM (*q)) |
9878760c RK |
14330 | *p++ = *q; |
14331 | } | |
14332 | ||
11e5fe42 | 14333 | if (last_period == 0) |
9878760c RK |
14334 | strcpy (p, section_desc); |
14335 | else | |
14336 | *p = '\0'; | |
14337 | } | |
e165f3f0 | 14338 | \f |
a4f6c312 | 14339 | /* Emit profile function. */ |
411707f4 | 14340 | |
411707f4 | 14341 | void |
a2369ed3 | 14342 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 14343 | { |
ffcfcb5f AM |
14344 | if (TARGET_PROFILE_KERNEL) |
14345 | return; | |
14346 | ||
8480e480 CC |
14347 | if (DEFAULT_ABI == ABI_AIX) |
14348 | { | |
9739c90c JJ |
14349 | #ifndef NO_PROFILE_COUNTERS |
14350 | # define NO_PROFILE_COUNTERS 0 | |
14351 | #endif | |
14352 | if (NO_PROFILE_COUNTERS) | |
14353 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); | |
14354 | else | |
14355 | { | |
14356 | char buf[30]; | |
14357 | const char *label_name; | |
14358 | rtx fun; | |
411707f4 | 14359 | |
9739c90c JJ |
14360 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
14361 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
14362 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 14363 | |
9739c90c JJ |
14364 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
14365 | fun, Pmode); | |
14366 | } | |
8480e480 | 14367 | } |
ee890fe2 SS |
14368 | else if (DEFAULT_ABI == ABI_DARWIN) |
14369 | { | |
d5fa86ba | 14370 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
14371 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
14372 | ||
14373 | /* Be conservative and always set this, at least for now. */ | |
14374 | current_function_uses_pic_offset_table = 1; | |
14375 | ||
14376 | #if TARGET_MACHO | |
14377 | /* For PIC code, set up a stub and collect the caller's address | |
14378 | from r0, which is where the prologue puts it. */ | |
ab82a49f | 14379 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
14380 | { |
14381 | mcount_name = machopic_stub_name (mcount_name); | |
14382 | if (current_function_uses_pic_offset_table) | |
14383 | caller_addr_regno = 0; | |
14384 | } | |
14385 | #endif | |
14386 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
14387 | 0, VOIDmode, 1, | |
14388 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
14389 | } | |
411707f4 CC |
14390 | } |
14391 | ||
a4f6c312 | 14392 | /* Write function profiler code. */ |
e165f3f0 RK |
14393 | |
14394 | void | |
a2369ed3 | 14395 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 14396 | { |
3daf36a4 | 14397 | char buf[100]; |
09eeeacb | 14398 | int save_lr = 8; |
e165f3f0 | 14399 | |
38c1f2d7 | 14400 | switch (DEFAULT_ABI) |
3daf36a4 | 14401 | { |
38c1f2d7 MM |
14402 | default: |
14403 | abort (); | |
14404 | ||
14405 | case ABI_V4: | |
09eeeacb | 14406 | save_lr = 4; |
09eeeacb AM |
14407 | if (!TARGET_32BIT) |
14408 | { | |
14409 | warning ("no profiling of 64-bit code for this ABI"); | |
14410 | return; | |
14411 | } | |
ffcfcb5f | 14412 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 MM |
14413 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
14414 | if (flag_pic == 1) | |
14415 | { | |
dfdfa60f | 14416 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
09eeeacb AM |
14417 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14418 | reg_names[0], save_lr, reg_names[1]); | |
17167fd8 | 14419 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 14420 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 14421 | assemble_name (file, buf); |
17167fd8 | 14422 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 14423 | } |
9ebbca7d | 14424 | else if (flag_pic > 1) |
38c1f2d7 | 14425 | { |
09eeeacb AM |
14426 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14427 | reg_names[0], save_lr, reg_names[1]); | |
9ebbca7d GK |
14428 | /* Now, we need to get the address of the label. */ |
14429 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 14430 | assemble_name (file, buf); |
9ebbca7d GK |
14431 | fputs ("-.\n1:", file); |
14432 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
14433 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
14434 | reg_names[0], reg_names[11]); | |
14435 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
14436 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 14437 | } |
38c1f2d7 MM |
14438 | else |
14439 | { | |
17167fd8 | 14440 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 14441 | assemble_name (file, buf); |
dfdfa60f | 14442 | fputs ("@ha\n", file); |
09eeeacb AM |
14443 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14444 | reg_names[0], save_lr, reg_names[1]); | |
a260abc9 | 14445 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 14446 | assemble_name (file, buf); |
17167fd8 | 14447 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
14448 | } |
14449 | ||
50d440bc | 14450 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
3b6ce0af DE |
14451 | fprintf (file, "\tbl %s%s\n", |
14452 | RS6000_MCOUNT, flag_pic ? "@plt" : ""); | |
38c1f2d7 MM |
14453 | break; |
14454 | ||
14455 | case ABI_AIX: | |
ee890fe2 | 14456 | case ABI_DARWIN: |
ffcfcb5f AM |
14457 | if (!TARGET_PROFILE_KERNEL) |
14458 | { | |
a3c9585f | 14459 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
14460 | } |
14461 | else | |
14462 | { | |
14463 | if (TARGET_32BIT) | |
14464 | abort (); | |
14465 | ||
14466 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
14467 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
14468 | ||
6de9cd9a | 14469 | if (cfun->static_chain_decl != NULL) |
ffcfcb5f AM |
14470 | { |
14471 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
14472 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
14473 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
14474 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
14475 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
14476 | } | |
14477 | else | |
14478 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
14479 | } | |
38c1f2d7 MM |
14480 | break; |
14481 | } | |
e165f3f0 | 14482 | } |
a251ffd0 | 14483 | |
b54cf83a | 14484 | \f |
b54cf83a DE |
14485 | /* Power4 load update and store update instructions are cracked into a |
14486 | load or store and an integer insn which are executed in the same cycle. | |
14487 | Branches have their own dispatch slot which does not count against the | |
14488 | GCC issue rate, but it changes the program flow so there are no other | |
14489 | instructions to issue in this cycle. */ | |
14490 | ||
14491 | static int | |
a2369ed3 DJ |
14492 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
14493 | int verbose ATTRIBUTE_UNUSED, | |
14494 | rtx insn, int more) | |
b54cf83a DE |
14495 | { |
14496 | if (GET_CODE (PATTERN (insn)) == USE | |
14497 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14498 | return more; | |
14499 | ||
ec507f2d | 14500 | if (rs6000_sched_groups) |
b54cf83a | 14501 | { |
cbe26ab8 DN |
14502 | if (is_microcoded_insn (insn)) |
14503 | return 0; | |
14504 | else if (is_cracked_insn (insn)) | |
14505 | return more > 2 ? more - 2 : 0; | |
b54cf83a | 14506 | } |
165b263e DE |
14507 | |
14508 | return more - 1; | |
b54cf83a DE |
14509 | } |
14510 | ||
a251ffd0 TG |
14511 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
14512 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
14513 | ||
c237e94a | 14514 | static int |
a2369ed3 DJ |
14515 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED, |
14516 | int cost) | |
a251ffd0 TG |
14517 | { |
14518 | if (! recog_memoized (insn)) | |
14519 | return 0; | |
14520 | ||
14521 | if (REG_NOTE_KIND (link) != 0) | |
14522 | return 0; | |
14523 | ||
14524 | if (REG_NOTE_KIND (link) == 0) | |
14525 | { | |
ed947a96 DJ |
14526 | /* Data dependency; DEP_INSN writes a register that INSN reads |
14527 | some cycles later. */ | |
14528 | switch (get_attr_type (insn)) | |
14529 | { | |
14530 | case TYPE_JMPREG: | |
309323c2 | 14531 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
14532 | a mtctr and bctr (and mtlr and br/blr). The first |
14533 | scheduling pass will not know about this latency since | |
14534 | the mtctr instruction, which has the latency associated | |
14535 | to it, will be generated by reload. */ | |
309323c2 | 14536 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
14537 | case TYPE_BRANCH: |
14538 | /* Leave some extra cycles between a compare and its | |
14539 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
14540 | if ((rs6000_cpu_attr == CPU_PPC603 |
14541 | || rs6000_cpu_attr == CPU_PPC604 | |
14542 | || rs6000_cpu_attr == CPU_PPC604E | |
14543 | || rs6000_cpu_attr == CPU_PPC620 | |
14544 | || rs6000_cpu_attr == CPU_PPC630 | |
14545 | || rs6000_cpu_attr == CPU_PPC750 | |
14546 | || rs6000_cpu_attr == CPU_PPC7400 | |
14547 | || rs6000_cpu_attr == CPU_PPC7450 | |
ec507f2d DE |
14548 | || rs6000_cpu_attr == CPU_POWER4 |
14549 | || rs6000_cpu_attr == CPU_POWER5) | |
ed947a96 DJ |
14550 | && recog_memoized (dep_insn) |
14551 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
14552 | && (get_attr_type (dep_insn) == TYPE_CMP |
14553 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 14554 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
14555 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
14556 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 14557 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
14558 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
14559 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
14560 | return cost + 2; |
14561 | default: | |
14562 | break; | |
14563 | } | |
a251ffd0 TG |
14564 | /* Fall out to return default cost. */ |
14565 | } | |
14566 | ||
14567 | return cost; | |
14568 | } | |
b6c9286a | 14569 | |
cbe26ab8 | 14570 | /* The function returns a true if INSN is microcoded. |
839a4992 | 14571 | Return false otherwise. */ |
cbe26ab8 DN |
14572 | |
14573 | static bool | |
14574 | is_microcoded_insn (rtx insn) | |
14575 | { | |
14576 | if (!insn || !INSN_P (insn) | |
14577 | || GET_CODE (PATTERN (insn)) == USE | |
14578 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14579 | return false; | |
14580 | ||
ec507f2d | 14581 | if (rs6000_sched_groups) |
cbe26ab8 DN |
14582 | { |
14583 | enum attr_type type = get_attr_type (insn); | |
14584 | if (type == TYPE_LOAD_EXT_U | |
14585 | || type == TYPE_LOAD_EXT_UX | |
14586 | || type == TYPE_LOAD_UX | |
14587 | || type == TYPE_STORE_UX | |
14588 | || type == TYPE_MFCR) | |
14589 | return true; | |
14590 | } | |
14591 | ||
14592 | return false; | |
14593 | } | |
14594 | ||
5c425df5 | 14595 | /* The function returns a nonzero value if INSN can be scheduled only |
cbe26ab8 DN |
14596 | as the first insn in a dispatch group ("dispatch-slot restricted"). |
14597 | In this case, the returned value indicates how many dispatch slots | |
14598 | the insn occupies (at the beginning of the group). | |
79ae11c4 DN |
14599 | Return 0 otherwise. */ |
14600 | ||
cbe26ab8 | 14601 | static int |
79ae11c4 DN |
14602 | is_dispatch_slot_restricted (rtx insn) |
14603 | { | |
14604 | enum attr_type type; | |
14605 | ||
ec507f2d | 14606 | if (!rs6000_sched_groups) |
79ae11c4 DN |
14607 | return 0; |
14608 | ||
14609 | if (!insn | |
14610 | || insn == NULL_RTX | |
14611 | || GET_CODE (insn) == NOTE | |
14612 | || GET_CODE (PATTERN (insn)) == USE | |
14613 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14614 | return 0; | |
14615 | ||
14616 | type = get_attr_type (insn); | |
14617 | ||
ec507f2d DE |
14618 | switch (type) |
14619 | { | |
14620 | case TYPE_MFCR: | |
14621 | case TYPE_MFCRF: | |
14622 | case TYPE_MTCR: | |
14623 | case TYPE_DELAYED_CR: | |
14624 | case TYPE_CR_LOGICAL: | |
14625 | case TYPE_MTJMPR: | |
14626 | case TYPE_MFJMPR: | |
14627 | return 1; | |
14628 | case TYPE_IDIV: | |
14629 | case TYPE_LDIV: | |
14630 | return 2; | |
14631 | default: | |
14632 | if (rs6000_cpu == PROCESSOR_POWER5 | |
14633 | && is_cracked_insn (insn)) | |
14634 | return 2; | |
14635 | return 0; | |
14636 | } | |
79ae11c4 DN |
14637 | } |
14638 | ||
cbe26ab8 DN |
14639 | /* The function returns true if INSN is cracked into 2 instructions |
14640 | by the processor (and therefore occupies 2 issue slots). */ | |
14641 | ||
14642 | static bool | |
14643 | is_cracked_insn (rtx insn) | |
14644 | { | |
14645 | if (!insn || !INSN_P (insn) | |
14646 | || GET_CODE (PATTERN (insn)) == USE | |
14647 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14648 | return false; | |
14649 | ||
ec507f2d | 14650 | if (rs6000_sched_groups) |
cbe26ab8 DN |
14651 | { |
14652 | enum attr_type type = get_attr_type (insn); | |
14653 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
14654 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U | |
14655 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
14656 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
14657 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
14658 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
14659 | || type == TYPE_IDIV || type == TYPE_LDIV | |
14660 | || type == TYPE_INSERT_WORD) | |
14661 | return true; | |
14662 | } | |
14663 | ||
14664 | return false; | |
14665 | } | |
14666 | ||
14667 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 14668 | the branch slot. */ |
cbe26ab8 DN |
14669 | |
14670 | static bool | |
14671 | is_branch_slot_insn (rtx insn) | |
14672 | { | |
14673 | if (!insn || !INSN_P (insn) | |
14674 | || GET_CODE (PATTERN (insn)) == USE | |
14675 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14676 | return false; | |
14677 | ||
ec507f2d | 14678 | if (rs6000_sched_groups) |
cbe26ab8 DN |
14679 | { |
14680 | enum attr_type type = get_attr_type (insn); | |
14681 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
14682 | return true; | |
14683 | return false; | |
14684 | } | |
14685 | ||
14686 | return false; | |
14687 | } | |
79ae11c4 | 14688 | |
a4f6c312 | 14689 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
14690 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
14691 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
14692 | define this macro if you do not need to adjust the scheduling |
14693 | priorities of insns. */ | |
bef84347 | 14694 | |
c237e94a | 14695 | static int |
a2369ed3 | 14696 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 14697 | { |
a4f6c312 SS |
14698 | /* On machines (like the 750) which have asymmetric integer units, |
14699 | where one integer unit can do multiply and divides and the other | |
14700 | can't, reduce the priority of multiply/divide so it is scheduled | |
14701 | before other integer operations. */ | |
bef84347 VM |
14702 | |
14703 | #if 0 | |
2c3c49de | 14704 | if (! INSN_P (insn)) |
bef84347 VM |
14705 | return priority; |
14706 | ||
14707 | if (GET_CODE (PATTERN (insn)) == USE) | |
14708 | return priority; | |
14709 | ||
14710 | switch (rs6000_cpu_attr) { | |
14711 | case CPU_PPC750: | |
14712 | switch (get_attr_type (insn)) | |
14713 | { | |
14714 | default: | |
14715 | break; | |
14716 | ||
14717 | case TYPE_IMUL: | |
14718 | case TYPE_IDIV: | |
3cb999d8 DE |
14719 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
14720 | priority, priority); | |
bef84347 VM |
14721 | if (priority >= 0 && priority < 0x01000000) |
14722 | priority >>= 3; | |
14723 | break; | |
14724 | } | |
14725 | } | |
14726 | #endif | |
14727 | ||
79ae11c4 DN |
14728 | if (is_dispatch_slot_restricted (insn) |
14729 | && reload_completed | |
14730 | && current_sched_info->sched_max_insns_priority | |
14731 | && rs6000_sched_restricted_insns_priority) | |
14732 | { | |
14733 | ||
14734 | /* Prioritize insns that can be dispatched only in the first dispatch slot. */ | |
14735 | if (rs6000_sched_restricted_insns_priority == 1) | |
14736 | /* Attach highest priority to insn. This means that in | |
14737 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
14738 | precede 'priority' (critical path) considerations. */ | |
14739 | return current_sched_info->sched_max_insns_priority; | |
14740 | else if (rs6000_sched_restricted_insns_priority == 2) | |
14741 | /* Increase priority of insn by a minimal amount. This means that in | |
14742 | haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations | |
14743 | precede dispatch-slot restriction considerations. */ | |
14744 | return (priority + 1); | |
14745 | } | |
14746 | ||
bef84347 VM |
14747 | return priority; |
14748 | } | |
14749 | ||
a4f6c312 SS |
14750 | /* Return how many instructions the machine can issue per cycle. */ |
14751 | ||
c237e94a | 14752 | static int |
863d938c | 14753 | rs6000_issue_rate (void) |
b6c9286a | 14754 | { |
3317bab1 DE |
14755 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
14756 | if (!reload_completed) | |
14757 | return 1; | |
14758 | ||
b6c9286a | 14759 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
14760 | case CPU_RIOS1: /* ? */ |
14761 | case CPU_RS64A: | |
14762 | case CPU_PPC601: /* ? */ | |
ed947a96 | 14763 | case CPU_PPC7450: |
3cb999d8 | 14764 | return 3; |
b54cf83a | 14765 | case CPU_PPC440: |
b6c9286a | 14766 | case CPU_PPC603: |
bef84347 | 14767 | case CPU_PPC750: |
ed947a96 | 14768 | case CPU_PPC7400: |
be12c2b0 | 14769 | case CPU_PPC8540: |
bef84347 | 14770 | return 2; |
3cb999d8 | 14771 | case CPU_RIOS2: |
b6c9286a | 14772 | case CPU_PPC604: |
19684119 | 14773 | case CPU_PPC604E: |
b6c9286a | 14774 | case CPU_PPC620: |
3cb999d8 | 14775 | case CPU_PPC630: |
b6c9286a | 14776 | return 4; |
cbe26ab8 | 14777 | case CPU_POWER4: |
ec507f2d | 14778 | case CPU_POWER5: |
cbe26ab8 | 14779 | return 5; |
b6c9286a MM |
14780 | default: |
14781 | return 1; | |
14782 | } | |
14783 | } | |
14784 | ||
be12c2b0 VM |
14785 | /* Return how many instructions to look ahead for better insn |
14786 | scheduling. */ | |
14787 | ||
14788 | static int | |
863d938c | 14789 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
14790 | { |
14791 | if (rs6000_cpu_attr == CPU_PPC8540) | |
14792 | return 4; | |
14793 | return 0; | |
14794 | } | |
14795 | ||
569fa502 DN |
14796 | /* Determine is PAT refers to memory. */ |
14797 | ||
14798 | static bool | |
14799 | is_mem_ref (rtx pat) | |
14800 | { | |
14801 | const char * fmt; | |
14802 | int i, j; | |
14803 | bool ret = false; | |
14804 | ||
14805 | if (GET_CODE (pat) == MEM) | |
14806 | return true; | |
14807 | ||
14808 | /* Recursively process the pattern. */ | |
14809 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
14810 | ||
14811 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
14812 | { | |
14813 | if (fmt[i] == 'e') | |
14814 | ret |= is_mem_ref (XEXP (pat, i)); | |
14815 | else if (fmt[i] == 'E') | |
14816 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
14817 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
14818 | } | |
14819 | ||
14820 | return ret; | |
14821 | } | |
14822 | ||
14823 | /* Determine if PAT is a PATTERN of a load insn. */ | |
14824 | ||
14825 | static bool | |
14826 | is_load_insn1 (rtx pat) | |
14827 | { | |
14828 | if (!pat || pat == NULL_RTX) | |
14829 | return false; | |
14830 | ||
14831 | if (GET_CODE (pat) == SET) | |
14832 | return is_mem_ref (SET_SRC (pat)); | |
14833 | ||
14834 | if (GET_CODE (pat) == PARALLEL) | |
14835 | { | |
14836 | int i; | |
14837 | ||
14838 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
14839 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
14840 | return true; | |
14841 | } | |
14842 | ||
14843 | return false; | |
14844 | } | |
14845 | ||
14846 | /* Determine if INSN loads from memory. */ | |
14847 | ||
14848 | static bool | |
14849 | is_load_insn (rtx insn) | |
14850 | { | |
14851 | if (!insn || !INSN_P (insn)) | |
14852 | return false; | |
14853 | ||
14854 | if (GET_CODE (insn) == CALL_INSN) | |
14855 | return false; | |
14856 | ||
14857 | return is_load_insn1 (PATTERN (insn)); | |
14858 | } | |
14859 | ||
14860 | /* Determine if PAT is a PATTERN of a store insn. */ | |
14861 | ||
14862 | static bool | |
14863 | is_store_insn1 (rtx pat) | |
14864 | { | |
14865 | if (!pat || pat == NULL_RTX) | |
14866 | return false; | |
14867 | ||
14868 | if (GET_CODE (pat) == SET) | |
14869 | return is_mem_ref (SET_DEST (pat)); | |
14870 | ||
14871 | if (GET_CODE (pat) == PARALLEL) | |
14872 | { | |
14873 | int i; | |
14874 | ||
14875 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
14876 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
14877 | return true; | |
14878 | } | |
14879 | ||
14880 | return false; | |
14881 | } | |
14882 | ||
14883 | /* Determine if INSN stores to memory. */ | |
14884 | ||
14885 | static bool | |
14886 | is_store_insn (rtx insn) | |
14887 | { | |
14888 | if (!insn || !INSN_P (insn)) | |
14889 | return false; | |
14890 | ||
14891 | return is_store_insn1 (PATTERN (insn)); | |
14892 | } | |
14893 | ||
14894 | /* Returns whether the dependence between INSN and NEXT is considered | |
14895 | costly by the given target. */ | |
14896 | ||
14897 | static bool | |
14898 | rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance) | |
14899 | { | |
14900 | /* If the flag is not enbled - no dependence is considered costly; | |
14901 | allow all dependent insns in the same group. | |
14902 | This is the most aggressive option. */ | |
14903 | if (rs6000_sched_costly_dep == no_dep_costly) | |
14904 | return false; | |
14905 | ||
14906 | /* If the flag is set to 1 - a dependence is always considered costly; | |
14907 | do not allow dependent instructions in the same group. | |
14908 | This is the most conservative option. */ | |
14909 | if (rs6000_sched_costly_dep == all_deps_costly) | |
14910 | return true; | |
14911 | ||
14912 | if (rs6000_sched_costly_dep == store_to_load_dep_costly | |
14913 | && is_load_insn (next) | |
14914 | && is_store_insn (insn)) | |
14915 | /* Prevent load after store in the same group. */ | |
14916 | return true; | |
14917 | ||
14918 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
14919 | && is_load_insn (next) | |
14920 | && is_store_insn (insn) | |
14921 | && (!link || (int) REG_NOTE_KIND (link) == 0)) | |
14922 | /* Prevent load after store in the same group if it is a true dependence. */ | |
14923 | return true; | |
14924 | ||
14925 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
14926 | and will not be scheduled in the same group. */ | |
14927 | if (rs6000_sched_costly_dep <= max_dep_latency | |
14928 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
14929 | return true; | |
14930 | ||
14931 | return false; | |
14932 | } | |
14933 | ||
cbe26ab8 DN |
14934 | /* Return the next insn after INSN that is found before TAIL is reached, |
14935 | skipping any "non-active" insns - insns that will not actually occupy | |
14936 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
14937 | ||
14938 | static rtx | |
14939 | get_next_active_insn (rtx insn, rtx tail) | |
14940 | { | |
14941 | rtx next_insn; | |
14942 | ||
14943 | if (!insn || insn == tail) | |
14944 | return NULL_RTX; | |
14945 | ||
14946 | next_insn = NEXT_INSN (insn); | |
14947 | ||
14948 | while (next_insn | |
14949 | && next_insn != tail | |
14950 | && (GET_CODE(next_insn) == NOTE | |
14951 | || GET_CODE (PATTERN (next_insn)) == USE | |
14952 | || GET_CODE (PATTERN (next_insn)) == CLOBBER)) | |
14953 | { | |
14954 | next_insn = NEXT_INSN (next_insn); | |
14955 | } | |
14956 | ||
14957 | if (!next_insn || next_insn == tail) | |
14958 | return NULL_RTX; | |
14959 | ||
14960 | return next_insn; | |
14961 | } | |
14962 | ||
839a4992 | 14963 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
14964 | of group WHICH_GROUP. |
14965 | ||
14966 | If WHICH_GROUP == current_group, this function will return true if INSN | |
14967 | causes the termination of the current group (i.e, the dispatch group to | |
14968 | which INSN belongs). This means that INSN will be the last insn in the | |
14969 | group it belongs to. | |
14970 | ||
14971 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
14972 | causes the termination of the previous group (i.e, the dispatch group that | |
14973 | precedes the group to which INSN belongs). This means that INSN will be | |
14974 | the first insn in the group it belongs to). */ | |
14975 | ||
14976 | static bool | |
14977 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
14978 | { | |
14979 | enum attr_type type; | |
14980 | ||
14981 | if (! insn) | |
14982 | return false; | |
569fa502 | 14983 | |
cbe26ab8 DN |
14984 | type = get_attr_type (insn); |
14985 | ||
14986 | if (is_microcoded_insn (insn)) | |
14987 | return true; | |
14988 | ||
14989 | if (which_group == current_group) | |
14990 | { | |
14991 | if (is_branch_slot_insn (insn)) | |
14992 | return true; | |
14993 | return false; | |
14994 | } | |
14995 | else if (which_group == previous_group) | |
14996 | { | |
14997 | if (is_dispatch_slot_restricted (insn)) | |
14998 | return true; | |
14999 | return false; | |
15000 | } | |
15001 | ||
15002 | return false; | |
15003 | } | |
15004 | ||
839a4992 | 15005 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
15006 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
15007 | ||
15008 | static bool | |
15009 | is_costly_group (rtx *group_insns, rtx next_insn) | |
15010 | { | |
15011 | int i; | |
15012 | rtx link; | |
15013 | int cost; | |
15014 | int issue_rate = rs6000_issue_rate (); | |
15015 | ||
15016 | for (i = 0; i < issue_rate; i++) | |
15017 | { | |
15018 | rtx insn = group_insns[i]; | |
15019 | if (!insn) | |
15020 | continue; | |
15021 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) | |
15022 | { | |
15023 | rtx next = XEXP (link, 0); | |
15024 | if (next == next_insn) | |
15025 | { | |
15026 | cost = insn_cost (insn, link, next_insn); | |
15027 | if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) | |
15028 | return true; | |
15029 | } | |
15030 | } | |
15031 | } | |
15032 | ||
15033 | return false; | |
15034 | } | |
15035 | ||
15036 | /* Utility of the function redefine_groups. | |
15037 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS | |
15038 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
15039 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
15040 | one of the following schemes, depending on the value of the flag | |
15041 | -minsert_sched_nops = X: | |
15042 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 15043 | in order to force NEXT_INSN into a separate group. |
cbe26ab8 DN |
15044 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
15045 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
15046 | insertion (has a group just ended, how many vacant issue slots remain in the | |
15047 | last group, and how many dispatch groups were encountered so far). */ | |
15048 | ||
15049 | static int | |
15050 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn, | |
15051 | bool *group_end, int can_issue_more, int *group_count) | |
15052 | { | |
15053 | rtx nop; | |
15054 | bool force; | |
15055 | int issue_rate = rs6000_issue_rate (); | |
15056 | bool end = *group_end; | |
15057 | int i; | |
15058 | ||
15059 | if (next_insn == NULL_RTX) | |
15060 | return can_issue_more; | |
15061 | ||
15062 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
15063 | return can_issue_more; | |
15064 | ||
15065 | force = is_costly_group (group_insns, next_insn); | |
15066 | if (!force) | |
15067 | return can_issue_more; | |
15068 | ||
15069 | if (sched_verbose > 6) | |
15070 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
15071 | *group_count ,can_issue_more); | |
15072 | ||
15073 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
15074 | { | |
15075 | if (*group_end) | |
15076 | can_issue_more = 0; | |
15077 | ||
15078 | /* Since only a branch can be issued in the last issue_slot, it is | |
15079 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
15080 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
15081 | in this case the last nop will start a new group and the branch will be | |
15082 | forced to the new group. */ | |
15083 | if (can_issue_more && !is_branch_slot_insn (next_insn)) | |
15084 | can_issue_more--; | |
15085 | ||
15086 | while (can_issue_more > 0) | |
15087 | { | |
15088 | nop = gen_nop(); | |
15089 | emit_insn_before (nop, next_insn); | |
15090 | can_issue_more--; | |
15091 | } | |
15092 | ||
15093 | *group_end = true; | |
15094 | return 0; | |
15095 | } | |
15096 | ||
15097 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
15098 | { | |
15099 | int n_nops = rs6000_sched_insert_nops; | |
15100 | ||
15101 | /* Nops can't be issued from the branch slot, so the effective | |
15102 | issue_rate for nops is 'issue_rate - 1'. */ | |
15103 | if (can_issue_more == 0) | |
15104 | can_issue_more = issue_rate; | |
15105 | can_issue_more--; | |
15106 | if (can_issue_more == 0) | |
15107 | { | |
15108 | can_issue_more = issue_rate - 1; | |
15109 | (*group_count)++; | |
15110 | end = true; | |
15111 | for (i = 0; i < issue_rate; i++) | |
15112 | { | |
15113 | group_insns[i] = 0; | |
15114 | } | |
15115 | } | |
15116 | ||
15117 | while (n_nops > 0) | |
15118 | { | |
15119 | nop = gen_nop (); | |
15120 | emit_insn_before (nop, next_insn); | |
15121 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
15122 | end = false; | |
15123 | can_issue_more--; | |
15124 | if (can_issue_more == 0) | |
15125 | { | |
15126 | can_issue_more = issue_rate - 1; | |
15127 | (*group_count)++; | |
15128 | end = true; | |
15129 | for (i = 0; i < issue_rate; i++) | |
15130 | { | |
15131 | group_insns[i] = 0; | |
15132 | } | |
15133 | } | |
15134 | n_nops--; | |
15135 | } | |
15136 | ||
15137 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
15138 | can_issue_more++; | |
15139 | ||
15140 | *group_end = /* Is next_insn going to start a new group? */ | |
15141 | (end | |
15142 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
15143 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
15144 | || (can_issue_more < issue_rate && | |
15145 | insn_terminates_group_p (next_insn, previous_group))); | |
15146 | if (*group_end && end) | |
15147 | (*group_count)--; | |
15148 | ||
15149 | if (sched_verbose > 6) | |
15150 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", | |
15151 | *group_count, can_issue_more); | |
15152 | return can_issue_more; | |
15153 | } | |
15154 | ||
15155 | return can_issue_more; | |
15156 | } | |
15157 | ||
15158 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
15159 | with the dispatch groups that the processor dispatcher is expected to | |
15160 | form in practice. It tries to achieve this synchronization by forcing the | |
15161 | estimated processor grouping on the compiler (as opposed to the function | |
15162 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
15163 | ||
15164 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
15165 | examines the (estimated) dispatch groups that will be formed by the processor | |
15166 | dispatcher. It marks these group boundaries to reflect the estimated | |
15167 | processor grouping, overriding the grouping that the scheduler had marked. | |
15168 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
15169 | force certain insns into separate groups or force a certain distance between | |
15170 | them by inserting nops, for example, if there exists a "costly dependence" | |
15171 | between the insns. | |
15172 | ||
15173 | The function estimates the group boundaries that the processor will form as | |
15174 | folllows: It keeps track of how many vacant issue slots are available after | |
15175 | each insn. A subsequent insn will start a new group if one of the following | |
15176 | 4 cases applies: | |
15177 | - no more vacant issue slots remain in the current dispatch group. | |
15178 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
15179 | insn is not a branch. | |
15180 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
15181 | which means that a cracked insn (which occupies two issue slots) can't be | |
15182 | issued in this group. | |
15183 | - less than 'issue_rate' slots are vacant, and the next insn always needs to | |
15184 | start a new group. */ | |
15185 | ||
15186 | static int | |
15187 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
15188 | { | |
15189 | rtx insn, next_insn; | |
15190 | int issue_rate; | |
15191 | int can_issue_more; | |
15192 | int slot, i; | |
15193 | bool group_end; | |
15194 | int group_count = 0; | |
15195 | rtx *group_insns; | |
15196 | ||
15197 | /* Initialize. */ | |
15198 | issue_rate = rs6000_issue_rate (); | |
15199 | group_insns = alloca (issue_rate * sizeof (rtx)); | |
15200 | for (i = 0; i < issue_rate; i++) | |
15201 | { | |
15202 | group_insns[i] = 0; | |
15203 | } | |
15204 | can_issue_more = issue_rate; | |
15205 | slot = 0; | |
15206 | insn = get_next_active_insn (prev_head_insn, tail); | |
15207 | group_end = false; | |
15208 | ||
15209 | while (insn != NULL_RTX) | |
15210 | { | |
15211 | slot = (issue_rate - can_issue_more); | |
15212 | group_insns[slot] = insn; | |
15213 | can_issue_more = | |
15214 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
15215 | if (insn_terminates_group_p (insn, current_group)) | |
15216 | can_issue_more = 0; | |
15217 | ||
15218 | next_insn = get_next_active_insn (insn, tail); | |
15219 | if (next_insn == NULL_RTX) | |
15220 | return group_count + 1; | |
15221 | ||
15222 | group_end = /* Is next_insn going to start a new group? */ | |
15223 | (can_issue_more == 0 | |
15224 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
15225 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
15226 | || (can_issue_more < issue_rate && | |
15227 | insn_terminates_group_p (next_insn, previous_group))); | |
15228 | ||
15229 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, | |
15230 | next_insn, &group_end, can_issue_more, &group_count); | |
15231 | ||
15232 | if (group_end) | |
15233 | { | |
15234 | group_count++; | |
15235 | can_issue_more = 0; | |
15236 | for (i = 0; i < issue_rate; i++) | |
15237 | { | |
15238 | group_insns[i] = 0; | |
15239 | } | |
15240 | } | |
15241 | ||
15242 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
15243 | PUT_MODE(next_insn, VOIDmode); | |
15244 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) | |
15245 | PUT_MODE (next_insn, TImode); | |
15246 | ||
15247 | insn = next_insn; | |
15248 | if (can_issue_more == 0) | |
15249 | can_issue_more = issue_rate; | |
15250 | } /* while */ | |
15251 | ||
15252 | return group_count; | |
15253 | } | |
15254 | ||
15255 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
15256 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
15257 | any dispatch groups which have vacant issue slots, in order to force the | |
15258 | scheduler's grouping on the processor dispatcher. The function | |
15259 | returns the number of dispatch groups found. */ | |
15260 | ||
15261 | static int | |
15262 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
15263 | { | |
15264 | rtx insn, next_insn; | |
15265 | rtx nop; | |
15266 | int issue_rate; | |
15267 | int can_issue_more; | |
15268 | int group_end; | |
15269 | int group_count = 0; | |
15270 | ||
15271 | /* Initialize issue_rate. */ | |
15272 | issue_rate = rs6000_issue_rate (); | |
15273 | can_issue_more = issue_rate; | |
15274 | ||
15275 | insn = get_next_active_insn (prev_head_insn, tail); | |
15276 | next_insn = get_next_active_insn (insn, tail); | |
15277 | ||
15278 | while (insn != NULL_RTX) | |
15279 | { | |
15280 | can_issue_more = | |
15281 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
15282 | ||
15283 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
15284 | ||
15285 | if (next_insn == NULL_RTX) | |
15286 | break; | |
15287 | ||
15288 | if (group_end) | |
15289 | { | |
15290 | /* If the scheduler had marked group termination at this location | |
15291 | (between insn and next_indn), and neither insn nor next_insn will | |
15292 | force group termination, pad the group with nops to force group | |
15293 | termination. */ | |
15294 | if (can_issue_more | |
15295 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
15296 | && !insn_terminates_group_p (insn, current_group) | |
15297 | && !insn_terminates_group_p (next_insn, previous_group)) | |
15298 | { | |
15299 | if (!is_branch_slot_insn(next_insn)) | |
15300 | can_issue_more--; | |
15301 | ||
15302 | while (can_issue_more) | |
15303 | { | |
15304 | nop = gen_nop (); | |
15305 | emit_insn_before (nop, next_insn); | |
15306 | can_issue_more--; | |
15307 | } | |
15308 | } | |
15309 | ||
15310 | can_issue_more = issue_rate; | |
15311 | group_count++; | |
15312 | } | |
15313 | ||
15314 | insn = next_insn; | |
15315 | next_insn = get_next_active_insn (insn, tail); | |
15316 | } | |
15317 | ||
15318 | return group_count; | |
15319 | } | |
15320 | ||
15321 | /* The following function is called at the end of scheduling BB. | |
15322 | After reload, it inserts nops at insn group bundling. */ | |
15323 | ||
15324 | static void | |
38f391a5 | 15325 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
15326 | { |
15327 | int n_groups; | |
15328 | ||
15329 | if (sched_verbose) | |
15330 | fprintf (dump, "=== Finishing schedule.\n"); | |
15331 | ||
ec507f2d | 15332 | if (reload_completed && rs6000_sched_groups) |
cbe26ab8 DN |
15333 | { |
15334 | if (rs6000_sched_insert_nops == sched_finish_none) | |
15335 | return; | |
15336 | ||
15337 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
15338 | n_groups = pad_groups (dump, sched_verbose, | |
15339 | current_sched_info->prev_head, | |
15340 | current_sched_info->next_tail); | |
15341 | else | |
15342 | n_groups = redefine_groups (dump, sched_verbose, | |
15343 | current_sched_info->prev_head, | |
15344 | current_sched_info->next_tail); | |
15345 | ||
15346 | if (sched_verbose >= 6) | |
15347 | { | |
15348 | fprintf (dump, "ngroups = %d\n", n_groups); | |
15349 | print_rtl (dump, current_sched_info->prev_head); | |
15350 | fprintf (dump, "Done finish_sched\n"); | |
15351 | } | |
15352 | } | |
15353 | } | |
b6c9286a | 15354 | \f |
b6c9286a MM |
15355 | /* Length in units of the trampoline for entering a nested function. */ |
15356 | ||
15357 | int | |
863d938c | 15358 | rs6000_trampoline_size (void) |
b6c9286a MM |
15359 | { |
15360 | int ret = 0; | |
15361 | ||
15362 | switch (DEFAULT_ABI) | |
15363 | { | |
15364 | default: | |
15365 | abort (); | |
15366 | ||
15367 | case ABI_AIX: | |
8f802bfb | 15368 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
15369 | break; |
15370 | ||
4dabc42d | 15371 | case ABI_DARWIN: |
b6c9286a | 15372 | case ABI_V4: |
03a7e1a5 | 15373 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 15374 | break; |
b6c9286a MM |
15375 | } |
15376 | ||
15377 | return ret; | |
15378 | } | |
15379 | ||
15380 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
15381 | FNADDR is an RTX for the address of the function's pure code. | |
15382 | CXT is an RTX for the static chain value for the function. */ | |
15383 | ||
15384 | void | |
a2369ed3 | 15385 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 15386 | { |
ac2a93a1 | 15387 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
15388 | int regsize = (TARGET_32BIT) ? 4 : 8; |
15389 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
15390 | |
15391 | switch (DEFAULT_ABI) | |
15392 | { | |
15393 | default: | |
15394 | abort (); | |
15395 | ||
8bd04c56 | 15396 | /* Macros to shorten the code expansions below. */ |
39403d82 | 15397 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
15398 | #define MEM_PLUS(addr,offset) \ |
15399 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 15400 | |
b6c9286a MM |
15401 | /* Under AIX, just build the 3 word function descriptor */ |
15402 | case ABI_AIX: | |
8bd04c56 MM |
15403 | { |
15404 | rtx fn_reg = gen_reg_rtx (pmode); | |
15405 | rtx toc_reg = gen_reg_rtx (pmode); | |
15406 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 15407 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
15408 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
15409 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
15410 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
15411 | } | |
b6c9286a MM |
15412 | break; |
15413 | ||
4dabc42d TC |
15414 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
15415 | case ABI_DARWIN: | |
b6c9286a | 15416 | case ABI_V4: |
39403d82 | 15417 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
15418 | FALSE, VOIDmode, 4, |
15419 | addr, pmode, | |
15420 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
15421 | fnaddr, pmode, | |
15422 | ctx_reg, pmode); | |
b6c9286a | 15423 | break; |
b6c9286a MM |
15424 | } |
15425 | ||
15426 | return; | |
15427 | } | |
7509c759 MM |
15428 | |
15429 | \f | |
91d231cb | 15430 | /* Table of valid machine attributes. */ |
a4f6c312 | 15431 | |
91d231cb | 15432 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 15433 | { |
91d231cb | 15434 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8bb418a3 | 15435 | { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, |
a5c76ee6 ZW |
15436 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
15437 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
15438 | { NULL, 0, 0, false, false, false, NULL } | |
91d231cb | 15439 | }; |
7509c759 | 15440 | |
8bb418a3 ZL |
15441 | /* Handle the "altivec" attribute. The attribute may have |
15442 | arguments as follows: | |
15443 | ||
15444 | __attribute__((altivec(vector__))) | |
15445 | __attribute__((altivec(pixel__))) (always followed by 'unsigned short') | |
15446 | __attribute__((altivec(bool__))) (always followed by 'unsigned') | |
15447 | ||
15448 | and may appear more than once (e.g., 'vector bool char') in a | |
15449 | given declaration. */ | |
15450 | ||
15451 | static tree | |
15452 | rs6000_handle_altivec_attribute (tree *node, tree name, tree args, | |
15453 | int flags ATTRIBUTE_UNUSED, | |
15454 | bool *no_add_attrs) | |
15455 | { | |
15456 | tree type = *node, result = NULL_TREE; | |
15457 | enum machine_mode mode; | |
15458 | int unsigned_p; | |
15459 | char altivec_type | |
15460 | = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) | |
15461 | && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) | |
15462 | ? *IDENTIFIER_POINTER (TREE_VALUE (args)) | |
15463 | : '?'); | |
15464 | ||
15465 | while (POINTER_TYPE_P (type) | |
15466 | || TREE_CODE (type) == FUNCTION_TYPE | |
15467 | || TREE_CODE (type) == METHOD_TYPE | |
15468 | || TREE_CODE (type) == ARRAY_TYPE) | |
15469 | type = TREE_TYPE (type); | |
15470 | ||
15471 | mode = TYPE_MODE (type); | |
15472 | ||
15473 | if (rs6000_warn_altivec_long | |
15474 | && (type == long_unsigned_type_node || type == long_integer_type_node)) | |
15475 | warning ("use of 'long' in AltiVec types is deprecated; use 'int'"); | |
15476 | ||
15477 | switch (altivec_type) | |
15478 | { | |
15479 | case 'v': | |
8df83eae | 15480 | unsigned_p = TYPE_UNSIGNED (type); |
8bb418a3 ZL |
15481 | switch (mode) |
15482 | { | |
15483 | case SImode: | |
15484 | result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); | |
15485 | break; | |
15486 | case HImode: | |
15487 | result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); | |
15488 | break; | |
15489 | case QImode: | |
15490 | result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); | |
15491 | break; | |
15492 | case SFmode: result = V4SF_type_node; break; | |
15493 | /* If the user says 'vector int bool', we may be handed the 'bool' | |
15494 | attribute _before_ the 'vector' attribute, and so select the proper | |
15495 | type in the 'b' case below. */ | |
15496 | case V4SImode: case V8HImode: case V16QImode: result = type; | |
15497 | default: break; | |
15498 | } | |
15499 | break; | |
15500 | case 'b': | |
15501 | switch (mode) | |
15502 | { | |
15503 | case SImode: case V4SImode: result = bool_V4SI_type_node; break; | |
15504 | case HImode: case V8HImode: result = bool_V8HI_type_node; break; | |
15505 | case QImode: case V16QImode: result = bool_V16QI_type_node; | |
15506 | default: break; | |
15507 | } | |
15508 | break; | |
15509 | case 'p': | |
15510 | switch (mode) | |
15511 | { | |
15512 | case V8HImode: result = pixel_V8HI_type_node; | |
15513 | default: break; | |
15514 | } | |
15515 | default: break; | |
15516 | } | |
15517 | ||
7958a2a6 FJ |
15518 | if (result && result != type && TYPE_READONLY (type)) |
15519 | result = build_qualified_type (result, TYPE_QUAL_CONST); | |
15520 | ||
8bb418a3 ZL |
15521 | *no_add_attrs = true; /* No need to hang on to the attribute. */ |
15522 | ||
15523 | if (!result) | |
15524 | warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); | |
15525 | else | |
15526 | *node = reconstruct_complex_type (*node, result); | |
15527 | ||
15528 | return NULL_TREE; | |
15529 | } | |
15530 | ||
f18eca82 ZL |
15531 | /* AltiVec defines four built-in scalar types that serve as vector |
15532 | elements; we must teach the compiler how to mangle them. */ | |
15533 | ||
15534 | static const char * | |
15535 | rs6000_mangle_fundamental_type (tree type) | |
15536 | { | |
15537 | if (type == bool_char_type_node) return "U6__boolc"; | |
15538 | if (type == bool_short_type_node) return "U6__bools"; | |
15539 | if (type == pixel_type_node) return "u7__pixel"; | |
15540 | if (type == bool_int_type_node) return "U6__booli"; | |
15541 | ||
15542 | /* For all other types, use normal C++ mangling. */ | |
15543 | return NULL; | |
15544 | } | |
15545 | ||
a5c76ee6 ZW |
15546 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
15547 | struct attribute_spec.handler. */ | |
a4f6c312 | 15548 | |
91d231cb | 15549 | static tree |
a2369ed3 DJ |
15550 | rs6000_handle_longcall_attribute (tree *node, tree name, |
15551 | tree args ATTRIBUTE_UNUSED, | |
15552 | int flags ATTRIBUTE_UNUSED, | |
15553 | bool *no_add_attrs) | |
91d231cb JM |
15554 | { |
15555 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
15556 | && TREE_CODE (*node) != FIELD_DECL | |
15557 | && TREE_CODE (*node) != TYPE_DECL) | |
15558 | { | |
15559 | warning ("`%s' attribute only applies to functions", | |
15560 | IDENTIFIER_POINTER (name)); | |
15561 | *no_add_attrs = true; | |
15562 | } | |
6a4cee5f | 15563 | |
91d231cb | 15564 | return NULL_TREE; |
7509c759 MM |
15565 | } |
15566 | ||
a5c76ee6 ZW |
15567 | /* Set longcall attributes on all functions declared when |
15568 | rs6000_default_long_calls is true. */ | |
15569 | static void | |
a2369ed3 | 15570 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
15571 | { |
15572 | if (rs6000_default_long_calls | |
15573 | && (TREE_CODE (type) == FUNCTION_TYPE | |
15574 | || TREE_CODE (type) == METHOD_TYPE)) | |
15575 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
15576 | NULL_TREE, | |
15577 | TYPE_ATTRIBUTES (type)); | |
15578 | } | |
15579 | ||
3cb999d8 DE |
15580 | /* Return a reference suitable for calling a function with the |
15581 | longcall attribute. */ | |
a4f6c312 | 15582 | |
6a4cee5f | 15583 | struct rtx_def * |
a2369ed3 | 15584 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 15585 | { |
d330fd93 | 15586 | const char *call_name; |
6a4cee5f MM |
15587 | tree node; |
15588 | ||
15589 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
15590 | return call_ref; | |
15591 | ||
15592 | /* System V adds '.' to the internal name, so skip them. */ | |
15593 | call_name = XSTR (call_ref, 0); | |
15594 | if (*call_name == '.') | |
15595 | { | |
15596 | while (*call_name == '.') | |
15597 | call_name++; | |
15598 | ||
15599 | node = get_identifier (call_name); | |
39403d82 | 15600 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
15601 | } |
15602 | ||
15603 | return force_reg (Pmode, call_ref); | |
15604 | } | |
7509c759 | 15605 | \f |
b64a1b53 RH |
15606 | #ifdef USING_ELFOS_H |
15607 | ||
7509c759 MM |
15608 | /* A C statement or statements to switch to the appropriate section |
15609 | for output of RTX in mode MODE. You can assume that RTX is some | |
15610 | kind of constant in RTL. The argument MODE is redundant except in | |
15611 | the case of a `const_int' rtx. Select the section by calling | |
15612 | `text_section' or one of the alternatives for other sections. | |
15613 | ||
15614 | Do not define this macro if you put all constants in the read-only | |
15615 | data section. */ | |
15616 | ||
b64a1b53 | 15617 | static void |
a2369ed3 DJ |
15618 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
15619 | unsigned HOST_WIDE_INT align) | |
7509c759 | 15620 | { |
a9098fd0 | 15621 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 15622 | toc_section (); |
7509c759 | 15623 | else |
b64a1b53 | 15624 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
15625 | } |
15626 | ||
15627 | /* A C statement or statements to switch to the appropriate | |
15628 | section for output of DECL. DECL is either a `VAR_DECL' node | |
15629 | or a constant of some sort. RELOC indicates whether forming | |
15630 | the initial value of DECL requires link-time relocations. */ | |
15631 | ||
ae46c4e0 | 15632 | static void |
a2369ed3 DJ |
15633 | rs6000_elf_select_section (tree decl, int reloc, |
15634 | unsigned HOST_WIDE_INT align) | |
7509c759 | 15635 | { |
f1384257 AM |
15636 | /* Pretend that we're always building for a shared library when |
15637 | ABI_AIX, because otherwise we end up with dynamic relocations | |
15638 | in read-only sections. This happens for function pointers, | |
15639 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
15640 | default_elf_select_section_1 (decl, reloc, align, |
15641 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
15642 | } |
15643 | ||
15644 | /* A C statement to build up a unique section name, expressed as a | |
15645 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
15646 | RELOC indicates whether the initial value of EXP requires | |
15647 | link-time relocations. If you do not define this macro, GCC will use | |
15648 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 15649 | macro can now be called for uninitialized data items as well as |
4912a07c | 15650 | initialized data and functions. */ |
63019373 | 15651 | |
ae46c4e0 | 15652 | static void |
a2369ed3 | 15653 | rs6000_elf_unique_section (tree decl, int reloc) |
63019373 | 15654 | { |
f1384257 AM |
15655 | /* As above, pretend that we're always building for a shared library |
15656 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
15657 | default_unique_section_1 (decl, reloc, |
15658 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 15659 | } |
d9407988 | 15660 | \f |
d1908feb JJ |
15661 | /* For a SYMBOL_REF, set generic flags and then perform some |
15662 | target-specific processing. | |
15663 | ||
d1908feb JJ |
15664 | When the AIX ABI is requested on a non-AIX system, replace the |
15665 | function name with the real name (with a leading .) rather than the | |
15666 | function descriptor name. This saves a lot of overriding code to | |
15667 | read the prefixes. */ | |
d9407988 | 15668 | |
fb49053f | 15669 | static void |
a2369ed3 | 15670 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 15671 | { |
d1908feb | 15672 | default_encode_section_info (decl, rtl, first); |
b2003250 | 15673 | |
d1908feb JJ |
15674 | if (first |
15675 | && TREE_CODE (decl) == FUNCTION_DECL | |
15676 | && !TARGET_AIX | |
15677 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 15678 | { |
c6a2438a | 15679 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
15680 | size_t len = strlen (XSTR (sym_ref, 0)); |
15681 | char *str = alloca (len + 2); | |
15682 | str[0] = '.'; | |
15683 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
15684 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 15685 | } |
d9407988 MM |
15686 | } |
15687 | ||
0e5dbd9b | 15688 | static bool |
a2369ed3 | 15689 | rs6000_elf_in_small_data_p (tree decl) |
0e5dbd9b DE |
15690 | { |
15691 | if (rs6000_sdata == SDATA_NONE) | |
15692 | return false; | |
15693 | ||
15694 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) | |
15695 | { | |
15696 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
15697 | if (strcmp (section, ".sdata") == 0 | |
15698 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
15699 | || strcmp (section, ".sbss") == 0 |
15700 | || strcmp (section, ".sbss2") == 0 | |
15701 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
15702 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
15703 | return true; |
15704 | } | |
15705 | else | |
15706 | { | |
15707 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
15708 | ||
15709 | if (size > 0 | |
307b599c | 15710 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
15711 | /* If it's not public, and we're not going to reference it there, |
15712 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
15713 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
15714 | return true; | |
15715 | } | |
15716 | ||
15717 | return false; | |
15718 | } | |
15719 | ||
b91da81f | 15720 | #endif /* USING_ELFOS_H */ |
000034eb | 15721 | |
a6c2a102 | 15722 | \f |
000034eb | 15723 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
15724 | ADDR can be effectively incremented by incrementing REG. |
15725 | ||
15726 | r0 is special and we must not select it as an address | |
15727 | register by this routine since our caller will try to | |
15728 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
15729 | |
15730 | struct rtx_def * | |
a2369ed3 | 15731 | find_addr_reg (rtx addr) |
000034eb DE |
15732 | { |
15733 | while (GET_CODE (addr) == PLUS) | |
15734 | { | |
02441cd6 JL |
15735 | if (GET_CODE (XEXP (addr, 0)) == REG |
15736 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 15737 | addr = XEXP (addr, 0); |
02441cd6 JL |
15738 | else if (GET_CODE (XEXP (addr, 1)) == REG |
15739 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
15740 | addr = XEXP (addr, 1); |
15741 | else if (CONSTANT_P (XEXP (addr, 0))) | |
15742 | addr = XEXP (addr, 1); | |
15743 | else if (CONSTANT_P (XEXP (addr, 1))) | |
15744 | addr = XEXP (addr, 0); | |
15745 | else | |
15746 | abort (); | |
15747 | } | |
02441cd6 | 15748 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
15749 | return addr; |
15750 | abort (); | |
15751 | } | |
15752 | ||
a6c2a102 | 15753 | void |
a2369ed3 | 15754 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
15755 | { |
15756 | fatal_insn ("bad address", op); | |
15757 | } | |
c8023011 | 15758 | |
ee890fe2 SS |
15759 | #if TARGET_MACHO |
15760 | ||
15761 | #if 0 | |
15762 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
15763 | reference and a constant. */ | |
15764 | ||
15765 | int | |
a2369ed3 | 15766 | symbolic_operand (rtx op) |
ee890fe2 SS |
15767 | { |
15768 | switch (GET_CODE (op)) | |
15769 | { | |
15770 | case SYMBOL_REF: | |
15771 | case LABEL_REF: | |
15772 | return 1; | |
15773 | case CONST: | |
15774 | op = XEXP (op, 0); | |
15775 | return (GET_CODE (op) == SYMBOL_REF || | |
15776 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
15777 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
15778 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
15779 | default: | |
15780 | return 0; | |
15781 | } | |
c8023011 | 15782 | } |
ee890fe2 SS |
15783 | #endif |
15784 | ||
efdba735 | 15785 | #if TARGET_MACHO |
ee890fe2 | 15786 | |
efdba735 | 15787 | static tree branch_island_list = 0; |
ee890fe2 | 15788 | |
efdba735 SH |
15789 | /* Remember to generate a branch island for far calls to the given |
15790 | function. */ | |
ee890fe2 | 15791 | |
efdba735 SH |
15792 | static void |
15793 | add_compiler_branch_island (tree label_name, tree function_name, int line_number) | |
ee890fe2 | 15794 | { |
efdba735 SH |
15795 | tree branch_island = build_tree_list (function_name, label_name); |
15796 | TREE_TYPE (branch_island) = build_int_2 (line_number, 0); | |
15797 | TREE_CHAIN (branch_island) = branch_island_list; | |
15798 | branch_island_list = branch_island; | |
ee890fe2 SS |
15799 | } |
15800 | ||
efdba735 SH |
15801 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
15802 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
15803 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
15804 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 15805 | |
efdba735 SH |
15806 | /* Generate far-jump branch islands for everything on the |
15807 | branch_island_list. Invoked immediately after the last instruction | |
15808 | of the epilogue has been emitted; the branch-islands must be | |
15809 | appended to, and contiguous with, the function body. Mach-O stubs | |
15810 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 15811 | |
efdba735 SH |
15812 | static void |
15813 | macho_branch_islands (void) | |
15814 | { | |
15815 | char tmp_buf[512]; | |
15816 | tree branch_island; | |
15817 | ||
15818 | for (branch_island = branch_island_list; | |
15819 | branch_island; | |
15820 | branch_island = TREE_CHAIN (branch_island)) | |
15821 | { | |
15822 | const char *label = | |
15823 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
15824 | const char *name = | |
15825 | darwin_strip_name_encoding ( | |
15826 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island))); | |
15827 | char name_buf[512]; | |
15828 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
15829 | if (name[0] == '*' || name[0] == '&') | |
15830 | strcpy (name_buf, name+1); | |
15831 | else | |
15832 | { | |
15833 | name_buf[0] = '_'; | |
15834 | strcpy (name_buf+1, name); | |
15835 | } | |
15836 | strcpy (tmp_buf, "\n"); | |
15837 | strcat (tmp_buf, label); | |
ee890fe2 | 15838 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 15839 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
f7efd730 | 15840 | fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n", |
efdba735 | 15841 | BRANCH_ISLAND_LINE_NUMBER(branch_island)); |
ee890fe2 | 15842 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
15843 | if (flag_pic) |
15844 | { | |
15845 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
15846 | strcat (tmp_buf, label); | |
15847 | strcat (tmp_buf, "_pic\n"); | |
15848 | strcat (tmp_buf, label); | |
15849 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
15850 | ||
15851 | strcat (tmp_buf, "\taddis r11,r11,ha16("); | |
15852 | strcat (tmp_buf, name_buf); | |
15853 | strcat (tmp_buf, " - "); | |
15854 | strcat (tmp_buf, label); | |
15855 | strcat (tmp_buf, "_pic)\n"); | |
15856 | ||
15857 | strcat (tmp_buf, "\tmtlr r0\n"); | |
15858 | ||
15859 | strcat (tmp_buf, "\taddi r12,r11,lo16("); | |
15860 | strcat (tmp_buf, name_buf); | |
15861 | strcat (tmp_buf, " - "); | |
15862 | strcat (tmp_buf, label); | |
15863 | strcat (tmp_buf, "_pic)\n"); | |
15864 | ||
15865 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); | |
15866 | } | |
15867 | else | |
15868 | { | |
15869 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
15870 | strcat (tmp_buf, name_buf); | |
15871 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
15872 | strcat (tmp_buf, name_buf); | |
15873 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
15874 | } | |
15875 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 15876 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 15877 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
f7efd730 | 15878 | fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n", |
efdba735 | 15879 | BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 15880 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 15881 | } |
ee890fe2 | 15882 | |
efdba735 | 15883 | branch_island_list = 0; |
ee890fe2 SS |
15884 | } |
15885 | ||
15886 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
15887 | already there or not. */ | |
15888 | ||
efdba735 | 15889 | static int |
a2369ed3 | 15890 | no_previous_def (tree function_name) |
ee890fe2 | 15891 | { |
efdba735 SH |
15892 | tree branch_island; |
15893 | for (branch_island = branch_island_list; | |
15894 | branch_island; | |
15895 | branch_island = TREE_CHAIN (branch_island)) | |
15896 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
15897 | return 0; |
15898 | return 1; | |
15899 | } | |
15900 | ||
15901 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
15902 | the function. */ | |
15903 | ||
efdba735 | 15904 | static tree |
a2369ed3 | 15905 | get_prev_label (tree function_name) |
ee890fe2 | 15906 | { |
efdba735 SH |
15907 | tree branch_island; |
15908 | for (branch_island = branch_island_list; | |
15909 | branch_island; | |
15910 | branch_island = TREE_CHAIN (branch_island)) | |
15911 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
15912 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
15913 | return 0; |
15914 | } | |
15915 | ||
15916 | /* INSN is either a function call or a millicode call. It may have an | |
15917 | unconditional jump in its delay slot. | |
15918 | ||
15919 | CALL_DEST is the routine we are calling. */ | |
15920 | ||
15921 | char * | |
efdba735 | 15922 | output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number) |
ee890fe2 SS |
15923 | { |
15924 | static char buf[256]; | |
efdba735 SH |
15925 | if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF |
15926 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) | |
ee890fe2 SS |
15927 | { |
15928 | tree labelname; | |
efdba735 | 15929 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
ee890fe2 SS |
15930 | |
15931 | if (no_previous_def (funname)) | |
15932 | { | |
308c142a | 15933 | int line_number = 0; |
ee890fe2 SS |
15934 | rtx label_rtx = gen_label_rtx (); |
15935 | char *label_buf, temp_buf[256]; | |
15936 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
15937 | CODE_LABEL_NUMBER (label_rtx)); | |
15938 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
15939 | labelname = get_identifier (label_buf); | |
15940 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
15941 | if (insn) | |
15942 | line_number = NOTE_LINE_NUMBER (insn); | |
efdba735 | 15943 | add_compiler_branch_island (labelname, funname, line_number); |
ee890fe2 SS |
15944 | } |
15945 | else | |
15946 | labelname = get_prev_label (funname); | |
15947 | ||
efdba735 SH |
15948 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
15949 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
15950 | "L42" should be a 'branch island', that will do a far jump to | |
15951 | 'foo'. Branch islands are generated in | |
15952 | macho_branch_islands(). */ | |
ee890fe2 | 15953 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 15954 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
15955 | } |
15956 | else | |
efdba735 SH |
15957 | sprintf (buf, "bl %%z%d", dest_operand_number); |
15958 | return buf; | |
ee890fe2 SS |
15959 | } |
15960 | ||
efdba735 | 15961 | #endif /* TARGET_MACHO */ |
ee890fe2 | 15962 | |
ee890fe2 SS |
15963 | /* Generate PIC and indirect symbol stubs. */ |
15964 | ||
15965 | void | |
a2369ed3 | 15966 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
15967 | { |
15968 | unsigned int length; | |
a4f6c312 SS |
15969 | char *symbol_name, *lazy_ptr_name; |
15970 | char *local_label_0; | |
ee890fe2 SS |
15971 | static int label = 0; |
15972 | ||
df56a27f | 15973 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 15974 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 15975 | |
ee890fe2 | 15976 | |
ee890fe2 SS |
15977 | length = strlen (symb); |
15978 | symbol_name = alloca (length + 32); | |
15979 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
15980 | ||
15981 | lazy_ptr_name = alloca (length + 32); | |
15982 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
15983 | ||
ee890fe2 | 15984 | if (flag_pic == 2) |
d3c300d2 | 15985 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 15986 | else |
d3c300d2 DJ |
15987 | machopic_symbol_stub1_section (); |
15988 | fprintf (file, "\t.align 2\n"); | |
ee890fe2 SS |
15989 | |
15990 | fprintf (file, "%s:\n", stub); | |
15991 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
15992 | ||
15993 | if (flag_pic == 2) | |
15994 | { | |
876455fa AP |
15995 | label++; |
15996 | local_label_0 = alloca (sizeof("\"L0000000000$spb\"")); | |
15997 | sprintf (local_label_0, "\"L%011d$spb\"", label); | |
15998 | ||
ee890fe2 SS |
15999 | fprintf (file, "\tmflr r0\n"); |
16000 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
16001 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
16002 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
16003 | lazy_ptr_name, local_label_0); | |
16004 | fprintf (file, "\tmtlr r0\n"); | |
d3c300d2 | 16005 | fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n", |
ee890fe2 SS |
16006 | lazy_ptr_name, local_label_0); |
16007 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
16008 | fprintf (file, "\tbctr\n"); |
16009 | } | |
16010 | else | |
ab82a49f AP |
16011 | { |
16012 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
16013 | fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name); | |
16014 | fprintf (file, "\tmtctr r12\n"); | |
16015 | fprintf (file, "\tbctr\n"); | |
16016 | } | |
ee890fe2 SS |
16017 | |
16018 | machopic_lazy_symbol_ptr_section (); | |
16019 | fprintf (file, "%s:\n", lazy_ptr_name); | |
16020 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
16021 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
16022 | } | |
16023 | ||
16024 | /* Legitimize PIC addresses. If the address is already | |
16025 | position-independent, we return ORIG. Newly generated | |
16026 | position-independent addresses go into a reg. This is REG if non | |
16027 | zero, otherwise we allocate register(s) as necessary. */ | |
16028 | ||
c859cda6 | 16029 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
16030 | |
16031 | rtx | |
a2369ed3 DJ |
16032 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
16033 | rtx reg) | |
ee890fe2 SS |
16034 | { |
16035 | rtx base, offset; | |
16036 | ||
16037 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
16038 | reg = gen_reg_rtx (Pmode); | |
16039 | ||
16040 | if (GET_CODE (orig) == CONST) | |
16041 | { | |
16042 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
16043 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
16044 | return orig; | |
16045 | ||
16046 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
16047 | { | |
2cf520bf | 16048 | /* Use a different reg for the intermediate value, as |
a3c9585f | 16049 | it will be marked UNCHANGING. */ |
2cf520bf GK |
16050 | rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); |
16051 | ||
a4f6c312 SS |
16052 | base = |
16053 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
2cf520bf | 16054 | Pmode, reg_temp); |
a4f6c312 SS |
16055 | offset = |
16056 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
16057 | Pmode, reg); | |
ee890fe2 SS |
16058 | } |
16059 | else | |
16060 | abort (); | |
16061 | ||
16062 | if (GET_CODE (offset) == CONST_INT) | |
16063 | { | |
16064 | if (SMALL_INT (offset)) | |
ed8908e7 | 16065 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
16066 | else if (! reload_in_progress && ! reload_completed) |
16067 | offset = force_reg (Pmode, offset); | |
16068 | else | |
c859cda6 DJ |
16069 | { |
16070 | rtx mem = force_const_mem (Pmode, orig); | |
16071 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
16072 | } | |
ee890fe2 | 16073 | } |
f1c25d3b | 16074 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
16075 | } |
16076 | ||
16077 | /* Fall back on generic machopic code. */ | |
16078 | return machopic_legitimize_pic_address (orig, mode, reg); | |
16079 | } | |
16080 | ||
16081 | /* This is just a placeholder to make linking work without having to | |
16082 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
16083 | ever needed for Darwin (not too likely!) this would have to get a | |
16084 | real definition. */ | |
16085 | ||
16086 | void | |
863d938c | 16087 | toc_section (void) |
ee890fe2 SS |
16088 | { |
16089 | } | |
16090 | ||
16091 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
16092 | |
16093 | #if TARGET_ELF | |
16094 | static unsigned int | |
a2369ed3 | 16095 | rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) |
7c262518 | 16096 | { |
1ff8f81a AM |
16097 | return default_section_type_flags_1 (decl, name, reloc, |
16098 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 16099 | } |
d9f6800d RH |
16100 | |
16101 | /* Record an element in the table of global constructors. SYMBOL is | |
16102 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
16103 | between 0 and MAX_INIT_PRIORITY. | |
16104 | ||
16105 | This differs from default_named_section_asm_out_constructor in | |
16106 | that we have special handling for -mrelocatable. */ | |
16107 | ||
16108 | static void | |
a2369ed3 | 16109 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
16110 | { |
16111 | const char *section = ".ctors"; | |
16112 | char buf[16]; | |
16113 | ||
16114 | if (priority != DEFAULT_INIT_PRIORITY) | |
16115 | { | |
16116 | sprintf (buf, ".ctors.%.5u", | |
16117 | /* Invert the numbering so the linker puts us in the proper | |
16118 | order; constructors are run from right to left, and the | |
16119 | linker sorts in increasing order. */ | |
16120 | MAX_INIT_PRIORITY - priority); | |
16121 | section = buf; | |
16122 | } | |
16123 | ||
715bdd29 RH |
16124 | named_section_flags (section, SECTION_WRITE); |
16125 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
16126 | |
16127 | if (TARGET_RELOCATABLE) | |
16128 | { | |
16129 | fputs ("\t.long (", asm_out_file); | |
16130 | output_addr_const (asm_out_file, symbol); | |
16131 | fputs (")@fixup\n", asm_out_file); | |
16132 | } | |
16133 | else | |
c8af3574 | 16134 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
16135 | } |
16136 | ||
16137 | static void | |
a2369ed3 | 16138 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
16139 | { |
16140 | const char *section = ".dtors"; | |
16141 | char buf[16]; | |
16142 | ||
16143 | if (priority != DEFAULT_INIT_PRIORITY) | |
16144 | { | |
16145 | sprintf (buf, ".dtors.%.5u", | |
16146 | /* Invert the numbering so the linker puts us in the proper | |
16147 | order; constructors are run from right to left, and the | |
16148 | linker sorts in increasing order. */ | |
16149 | MAX_INIT_PRIORITY - priority); | |
16150 | section = buf; | |
16151 | } | |
16152 | ||
715bdd29 RH |
16153 | named_section_flags (section, SECTION_WRITE); |
16154 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
16155 | |
16156 | if (TARGET_RELOCATABLE) | |
16157 | { | |
16158 | fputs ("\t.long (", asm_out_file); | |
16159 | output_addr_const (asm_out_file, symbol); | |
16160 | fputs (")@fixup\n", asm_out_file); | |
16161 | } | |
16162 | else | |
c8af3574 | 16163 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 16164 | } |
9739c90c JJ |
16165 | |
16166 | void | |
a2369ed3 | 16167 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
16168 | { |
16169 | if (TARGET_64BIT) | |
16170 | { | |
16171 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
16172 | ASM_OUTPUT_LABEL (file, name); | |
16173 | fputs (DOUBLE_INT_ASM_OP, file); | |
16174 | putc ('.', file); | |
16175 | assemble_name (file, name); | |
16176 | fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file); | |
16177 | assemble_name (file, name); | |
16178 | fputs (",24\n\t.type\t.", file); | |
16179 | assemble_name (file, name); | |
16180 | fputs (",@function\n", file); | |
16181 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
16182 | { | |
16183 | fputs ("\t.globl\t.", file); | |
16184 | assemble_name (file, name); | |
16185 | putc ('\n', file); | |
16186 | } | |
16187 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
16188 | putc ('.', file); | |
16189 | ASM_OUTPUT_LABEL (file, name); | |
16190 | return; | |
16191 | } | |
16192 | ||
16193 | if (TARGET_RELOCATABLE | |
16194 | && (get_pool_size () != 0 || current_function_profile) | |
3c9eb5f4 | 16195 | && uses_TOC ()) |
9739c90c JJ |
16196 | { |
16197 | char buf[256]; | |
16198 | ||
16199 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
16200 | ||
16201 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
16202 | fprintf (file, "\t.long "); | |
16203 | assemble_name (file, buf); | |
16204 | putc ('-', file); | |
16205 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
16206 | assemble_name (file, buf); | |
16207 | putc ('\n', file); | |
16208 | } | |
16209 | ||
16210 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
16211 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
16212 | ||
16213 | if (DEFAULT_ABI == ABI_AIX) | |
16214 | { | |
16215 | const char *desc_name, *orig_name; | |
16216 | ||
16217 | orig_name = (*targetm.strip_name_encoding) (name); | |
16218 | desc_name = orig_name; | |
16219 | while (*desc_name == '.') | |
16220 | desc_name++; | |
16221 | ||
16222 | if (TREE_PUBLIC (decl)) | |
16223 | fprintf (file, "\t.globl %s\n", desc_name); | |
16224 | ||
16225 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
16226 | fprintf (file, "%s:\n", desc_name); | |
16227 | fprintf (file, "\t.long %s\n", orig_name); | |
16228 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
16229 | if (DEFAULT_ABI == ABI_AIX) | |
16230 | fputs ("\t.long 0\n", file); | |
16231 | fprintf (file, "\t.previous\n"); | |
16232 | } | |
16233 | ASM_OUTPUT_LABEL (file, name); | |
16234 | } | |
7c262518 RH |
16235 | #endif |
16236 | ||
cbaaba19 | 16237 | #if TARGET_XCOFF |
7c262518 | 16238 | static void |
a2369ed3 | 16239 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
16240 | { |
16241 | fputs (GLOBAL_ASM_OP, stream); | |
16242 | RS6000_OUTPUT_BASENAME (stream, name); | |
16243 | putc ('\n', stream); | |
16244 | } | |
16245 | ||
16246 | static void | |
a2369ed3 | 16247 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags) |
7c262518 | 16248 | { |
0e5dbd9b DE |
16249 | int smclass; |
16250 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
16251 | ||
16252 | if (flags & SECTION_CODE) | |
16253 | smclass = 0; | |
16254 | else if (flags & SECTION_WRITE) | |
16255 | smclass = 2; | |
16256 | else | |
16257 | smclass = 1; | |
16258 | ||
5b5198f7 | 16259 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 16260 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 16261 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 16262 | } |
ae46c4e0 RH |
16263 | |
16264 | static void | |
a2369ed3 DJ |
16265 | rs6000_xcoff_select_section (tree decl, int reloc, |
16266 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
ae46c4e0 | 16267 | { |
5add3202 | 16268 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 16269 | { |
0e5dbd9b | 16270 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
16271 | read_only_data_section (); |
16272 | else | |
16273 | read_only_private_data_section (); | |
16274 | } | |
16275 | else | |
16276 | { | |
0e5dbd9b | 16277 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
16278 | data_section (); |
16279 | else | |
16280 | private_data_section (); | |
16281 | } | |
16282 | } | |
16283 | ||
16284 | static void | |
a2369ed3 | 16285 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
16286 | { |
16287 | const char *name; | |
ae46c4e0 | 16288 | |
5b5198f7 DE |
16289 | /* Use select_section for private and uninitialized data. */ |
16290 | if (!TREE_PUBLIC (decl) | |
16291 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
16292 | || DECL_INITIAL (decl) == NULL_TREE |
16293 | || DECL_INITIAL (decl) == error_mark_node | |
16294 | || (flag_zero_initialized_in_bss | |
16295 | && initializer_zerop (DECL_INITIAL (decl)))) | |
16296 | return; | |
16297 | ||
16298 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
16299 | name = (*targetm.strip_name_encoding) (name); | |
16300 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 16301 | } |
b64a1b53 | 16302 | |
fb49053f RH |
16303 | /* Select section for constant in constant pool. |
16304 | ||
16305 | On RS/6000, all constants are in the private read-only data area. | |
16306 | However, if this is being placed in the TOC it must be output as a | |
16307 | toc entry. */ | |
16308 | ||
b64a1b53 | 16309 | static void |
a2369ed3 DJ |
16310 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
16311 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
b64a1b53 RH |
16312 | { |
16313 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
16314 | toc_section (); | |
16315 | else | |
16316 | read_only_private_data_section (); | |
16317 | } | |
772c5265 RH |
16318 | |
16319 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
16320 | ||
16321 | static const char * | |
a2369ed3 | 16322 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
16323 | { |
16324 | size_t len; | |
16325 | if (*name == '*') | |
16326 | name++; | |
16327 | len = strlen (name); | |
16328 | if (name[len - 1] == ']') | |
16329 | return ggc_alloc_string (name, len - 4); | |
16330 | else | |
16331 | return name; | |
16332 | } | |
16333 | ||
5add3202 DE |
16334 | /* Section attributes. AIX is always PIC. */ |
16335 | ||
16336 | static unsigned int | |
a2369ed3 | 16337 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 16338 | { |
5b5198f7 DE |
16339 | unsigned int align; |
16340 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
16341 | ||
16342 | /* Align to at least UNIT size. */ | |
16343 | if (flags & SECTION_CODE) | |
16344 | align = MIN_UNITS_PER_WORD; | |
16345 | else | |
16346 | /* Increase alignment of large objects if not already stricter. */ | |
16347 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
16348 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
16349 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
16350 | ||
16351 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 16352 | } |
a5fe455b | 16353 | |
1bc7c5b6 ZW |
16354 | /* Output at beginning of assembler file. |
16355 | ||
16356 | Initialize the section names for the RS/6000 at this point. | |
16357 | ||
16358 | Specify filename, including full path, to assembler. | |
16359 | ||
16360 | We want to go into the TOC section so at least one .toc will be emitted. | |
16361 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
16362 | [RW] section emitted. | |
16363 | ||
16364 | Finally, declare mcount when profiling to make the assembler happy. */ | |
16365 | ||
16366 | static void | |
863d938c | 16367 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
16368 | { |
16369 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
16370 | main_input_filename, ".bss_"); | |
16371 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
16372 | main_input_filename, ".rw_"); | |
16373 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
16374 | main_input_filename, ".ro_"); | |
16375 | ||
16376 | fputs ("\t.file\t", asm_out_file); | |
16377 | output_quoted_string (asm_out_file, main_input_filename); | |
16378 | fputc ('\n', asm_out_file); | |
16379 | toc_section (); | |
16380 | if (write_symbols != NO_DEBUG) | |
16381 | private_data_section (); | |
16382 | text_section (); | |
16383 | if (profile_flag) | |
16384 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
16385 | rs6000_file_start (); | |
16386 | } | |
16387 | ||
a5fe455b ZW |
16388 | /* Output at end of assembler file. |
16389 | On the RS/6000, referencing data should automatically pull in text. */ | |
16390 | ||
16391 | static void | |
863d938c | 16392 | rs6000_xcoff_file_end (void) |
a5fe455b ZW |
16393 | { |
16394 | text_section (); | |
16395 | fputs ("_section_.text:\n", asm_out_file); | |
16396 | data_section (); | |
16397 | fputs (TARGET_32BIT | |
16398 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
16399 | asm_out_file); | |
16400 | } | |
f1384257 | 16401 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 16402 | |
f1384257 AM |
16403 | #if TARGET_MACHO |
16404 | /* Cross-module name binding. Darwin does not support overriding | |
7f3d8013 | 16405 | functions at dynamic-link time. */ |
0e5dbd9b | 16406 | |
2bcc50d0 | 16407 | static bool |
a2369ed3 | 16408 | rs6000_binds_local_p (tree decl) |
0e5dbd9b | 16409 | { |
f1384257 | 16410 | return default_binds_local_p_1 (decl, 0); |
0e5dbd9b | 16411 | } |
f1384257 | 16412 | #endif |
34bb030a | 16413 | |
3c50106f RH |
16414 | /* Compute a (partial) cost for rtx X. Return true if the complete |
16415 | cost has been computed, and false if subexpressions should be | |
16416 | scanned. In either case, *TOTAL contains the cost result. */ | |
16417 | ||
16418 | static bool | |
a2369ed3 DJ |
16419 | rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, |
16420 | int *total) | |
3c50106f RH |
16421 | { |
16422 | switch (code) | |
16423 | { | |
16424 | /* On the RS/6000, if it is valid in the insn, it is free. | |
16425 | So this always returns 0. */ | |
16426 | case CONST_INT: | |
16427 | case CONST: | |
16428 | case LABEL_REF: | |
16429 | case SYMBOL_REF: | |
16430 | case CONST_DOUBLE: | |
16431 | case HIGH: | |
16432 | *total = 0; | |
16433 | return true; | |
16434 | ||
16435 | case PLUS: | |
16436 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
16437 | && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) | |
16438 | + 0x8000) >= 0x10000) | |
16439 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
16440 | ? COSTS_N_INSNS (2) | |
16441 | : COSTS_N_INSNS (1)); | |
16442 | return true; | |
16443 | ||
52190329 RS |
16444 | case MINUS: |
16445 | *total = COSTS_N_INSNS (1); | |
16446 | return true; | |
16447 | ||
3c50106f RH |
16448 | case AND: |
16449 | case IOR: | |
16450 | case XOR: | |
16451 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
16452 | && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 | |
16453 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
16454 | ? COSTS_N_INSNS (2) | |
16455 | : COSTS_N_INSNS (1)); | |
16456 | return true; | |
16457 | ||
16458 | case MULT: | |
8b897cfa | 16459 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
3c50106f | 16460 | { |
8b897cfa RS |
16461 | if (INTVAL (XEXP (x, 1)) >= -256 |
16462 | && INTVAL (XEXP (x, 1)) <= 255) | |
16463 | *total = COSTS_N_INSNS (rs6000_cost->mulsi_const9); | |
16464 | else | |
16465 | *total = COSTS_N_INSNS (rs6000_cost->mulsi_const); | |
3c50106f | 16466 | } |
8b897cfa RS |
16467 | else if (GET_MODE (XEXP (x, 1)) == DImode) |
16468 | *total = COSTS_N_INSNS (rs6000_cost->muldi); | |
16469 | else | |
16470 | *total = COSTS_N_INSNS (rs6000_cost->mulsi); | |
16471 | return true; | |
3c50106f RH |
16472 | |
16473 | case DIV: | |
16474 | case MOD: | |
16475 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
16476 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
16477 | { | |
16478 | *total = COSTS_N_INSNS (2); | |
16479 | return true; | |
16480 | } | |
5efb1046 | 16481 | /* FALLTHRU */ |
3c50106f RH |
16482 | |
16483 | case UDIV: | |
16484 | case UMOD: | |
8b897cfa RS |
16485 | if (GET_MODE (XEXP (x, 1)) == DImode) |
16486 | *total = COSTS_N_INSNS (rs6000_cost->divdi); | |
16487 | else | |
16488 | *total = COSTS_N_INSNS (rs6000_cost->divsi); | |
16489 | return true; | |
3c50106f RH |
16490 | |
16491 | case FFS: | |
16492 | *total = COSTS_N_INSNS (4); | |
16493 | return true; | |
16494 | ||
16495 | case MEM: | |
a3c9585f | 16496 | /* MEM should be slightly more expensive than (plus (reg) (const)). */ |
3c50106f RH |
16497 | *total = 5; |
16498 | return true; | |
16499 | ||
16500 | default: | |
16501 | return false; | |
16502 | } | |
16503 | } | |
16504 | ||
34bb030a DE |
16505 | /* A C expression returning the cost of moving data from a register of class |
16506 | CLASS1 to one of CLASS2. */ | |
16507 | ||
16508 | int | |
a2369ed3 DJ |
16509 | rs6000_register_move_cost (enum machine_mode mode, |
16510 | enum reg_class from, enum reg_class to) | |
34bb030a DE |
16511 | { |
16512 | /* Moves from/to GENERAL_REGS. */ | |
16513 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
16514 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
16515 | { | |
16516 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
16517 | from = to; | |
16518 | ||
16519 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
16520 | return (rs6000_memory_move_cost (mode, from, 0) | |
16521 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
16522 | ||
a3c9585f | 16523 | /* It's more expensive to move CR_REGS than CR0_REGS because of the shift.... */ |
34bb030a DE |
16524 | else if (from == CR_REGS) |
16525 | return 4; | |
16526 | ||
16527 | else | |
16528 | /* A move will cost one instruction per GPR moved. */ | |
16529 | return 2 * HARD_REGNO_NREGS (0, mode); | |
16530 | } | |
16531 | ||
16532 | /* Moving between two similar registers is just one instruction. */ | |
16533 | else if (reg_classes_intersect_p (to, from)) | |
16534 | return mode == TFmode ? 4 : 2; | |
16535 | ||
16536 | /* Everything else has to go through GENERAL_REGS. */ | |
16537 | else | |
16538 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) | |
16539 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); | |
16540 | } | |
16541 | ||
16542 | /* A C expressions returning the cost of moving data of MODE from a register to | |
16543 | or from memory. */ | |
16544 | ||
16545 | int | |
a2369ed3 DJ |
16546 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, |
16547 | int in ATTRIBUTE_UNUSED) | |
34bb030a DE |
16548 | { |
16549 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
16550 | return 4 * HARD_REGNO_NREGS (0, mode); | |
16551 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) | |
16552 | return 4 * HARD_REGNO_NREGS (32, mode); | |
16553 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) | |
16554 | return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); | |
16555 | else | |
16556 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
16557 | } | |
16558 | ||
ded9bf77 AH |
16559 | /* Return an RTX representing where to find the function value of a |
16560 | function returning MODE. */ | |
16561 | static rtx | |
16562 | rs6000_complex_function_value (enum machine_mode mode) | |
16563 | { | |
16564 | unsigned int regno; | |
16565 | rtx r1, r2; | |
16566 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 16567 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 | 16568 | |
4ed78545 | 16569 | if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
ded9bf77 AH |
16570 | regno = FP_ARG_RETURN; |
16571 | else | |
16572 | { | |
16573 | regno = GP_ARG_RETURN; | |
16574 | ||
16575 | /* 32-bit is OK since it'll go in r3/r4. */ | |
fb7e4164 | 16576 | if (TARGET_32BIT && inner_bytes >= 4) |
ded9bf77 AH |
16577 | return gen_rtx_REG (mode, regno); |
16578 | } | |
16579 | ||
fb7e4164 AM |
16580 | if (inner_bytes >= 8) |
16581 | return gen_rtx_REG (mode, regno); | |
16582 | ||
ded9bf77 AH |
16583 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
16584 | const0_rtx); | |
16585 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 16586 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
16587 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
16588 | } | |
16589 | ||
a6ebc39a AH |
16590 | /* Define how to find the value returned by a function. |
16591 | VALTYPE is the data type of the value (as a tree). | |
16592 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
16593 | otherwise, FUNC is 0. | |
16594 | ||
16595 | On the SPE, both FPs and vectors are returned in r3. | |
16596 | ||
16597 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
16598 | fp1, unless -msoft-float. */ | |
16599 | ||
16600 | rtx | |
16601 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
16602 | { | |
16603 | enum machine_mode mode; | |
2a8fa26c | 16604 | unsigned int regno; |
a6ebc39a | 16605 | |
0e67400a FJ |
16606 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
16607 | { | |
16608 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
16609 | return gen_rtx_PARALLEL (DImode, | |
16610 | gen_rtvec (2, | |
16611 | gen_rtx_EXPR_LIST (VOIDmode, | |
16612 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
16613 | const0_rtx), | |
16614 | gen_rtx_EXPR_LIST (VOIDmode, | |
16615 | gen_rtx_REG (SImode, | |
16616 | GP_ARG_RETURN + 1), | |
16617 | GEN_INT (4)))); | |
16618 | } | |
16619 | ||
a6ebc39a AH |
16620 | if ((INTEGRAL_TYPE_P (valtype) |
16621 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
16622 | || POINTER_TYPE_P (valtype)) | |
b78d48dd | 16623 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a AH |
16624 | else |
16625 | mode = TYPE_MODE (valtype); | |
16626 | ||
4ed78545 | 16627 | if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) |
2a8fa26c | 16628 | regno = FP_ARG_RETURN; |
ded9bf77 | 16629 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
42ba5130 | 16630 | && targetm.calls.split_complex_arg) |
ded9bf77 | 16631 | return rs6000_complex_function_value (mode); |
44688022 AM |
16632 | else if (TREE_CODE (valtype) == VECTOR_TYPE |
16633 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
a6ebc39a AH |
16634 | regno = ALTIVEC_ARG_RETURN; |
16635 | else | |
16636 | regno = GP_ARG_RETURN; | |
16637 | ||
16638 | return gen_rtx_REG (mode, regno); | |
16639 | } | |
16640 | ||
ded9bf77 AH |
16641 | /* Define how to find the value returned by a library function |
16642 | assuming the value has mode MODE. */ | |
16643 | rtx | |
16644 | rs6000_libcall_value (enum machine_mode mode) | |
16645 | { | |
16646 | unsigned int regno; | |
16647 | ||
16648 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
16649 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
16650 | regno = FP_ARG_RETURN; | |
44688022 AM |
16651 | else if (ALTIVEC_VECTOR_MODE (mode) |
16652 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
ded9bf77 | 16653 | regno = ALTIVEC_ARG_RETURN; |
42ba5130 | 16654 | else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) |
ded9bf77 AH |
16655 | return rs6000_complex_function_value (mode); |
16656 | else | |
16657 | regno = GP_ARG_RETURN; | |
16658 | ||
16659 | return gen_rtx_REG (mode, regno); | |
16660 | } | |
16661 | ||
d1d0c603 JJ |
16662 | /* Define the offset between two registers, FROM to be eliminated and its |
16663 | replacement TO, at the start of a routine. */ | |
16664 | HOST_WIDE_INT | |
16665 | rs6000_initial_elimination_offset (int from, int to) | |
16666 | { | |
16667 | rs6000_stack_t *info = rs6000_stack_info (); | |
16668 | HOST_WIDE_INT offset; | |
16669 | ||
16670 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
16671 | offset = info->push_p ? 0 : -info->total_size; | |
16672 | else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
16673 | offset = info->total_size; | |
16674 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
16675 | offset = info->push_p ? info->total_size : 0; | |
16676 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
16677 | offset = 0; | |
16678 | else | |
16679 | abort (); | |
16680 | ||
16681 | return offset; | |
16682 | } | |
16683 | ||
62e1dfcf NC |
16684 | /* Return true if TYPE is of type __ev64_opaque__. */ |
16685 | ||
c8e4f0e9 | 16686 | static bool |
a2369ed3 | 16687 | is_ev64_opaque_type (tree type) |
62e1dfcf | 16688 | { |
c8e4f0e9 | 16689 | return (TARGET_SPE |
2abe3e28 AH |
16690 | && (type == opaque_V2SI_type_node |
16691 | || type == opaque_V2SF_type_node | |
36252949 | 16692 | || type == opaque_p_V2SI_type_node)); |
62e1dfcf NC |
16693 | } |
16694 | ||
96714395 | 16695 | static rtx |
a2369ed3 | 16696 | rs6000_dwarf_register_span (rtx reg) |
96714395 AH |
16697 | { |
16698 | unsigned regno; | |
16699 | ||
16700 | if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg))) | |
16701 | return NULL_RTX; | |
16702 | ||
16703 | regno = REGNO (reg); | |
16704 | ||
16705 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
16706 | This is a way of distinguishing r0 in 32-bits from r0 in | |
16707 | 64-bits. */ | |
16708 | return | |
16709 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
16710 | BYTES_BIG_ENDIAN |
16711 | ? gen_rtvec (2, | |
16712 | gen_rtx_REG (SImode, regno + 1200), | |
16713 | gen_rtx_REG (SImode, regno)) | |
16714 | : gen_rtvec (2, | |
16715 | gen_rtx_REG (SImode, regno), | |
16716 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
16717 | } |
16718 | ||
93c9d1ba AM |
16719 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
16720 | ||
16721 | unsigned int | |
16722 | rs6000_dbx_register_number (unsigned int regno) | |
16723 | { | |
16724 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
16725 | return regno; | |
16726 | if (regno == MQ_REGNO) | |
16727 | return 100; | |
16728 | if (regno == LINK_REGISTER_REGNUM) | |
16729 | return 108; | |
16730 | if (regno == COUNT_REGISTER_REGNUM) | |
16731 | return 109; | |
16732 | if (CR_REGNO_P (regno)) | |
16733 | return regno - CR0_REGNO + 86; | |
16734 | if (regno == XER_REGNO) | |
16735 | return 101; | |
16736 | if (ALTIVEC_REGNO_P (regno)) | |
16737 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
16738 | if (regno == VRSAVE_REGNO) | |
16739 | return 356; | |
16740 | if (regno == VSCR_REGNO) | |
16741 | return 67; | |
16742 | if (regno == SPE_ACC_REGNO) | |
16743 | return 99; | |
16744 | if (regno == SPEFSCR_REGNO) | |
16745 | return 612; | |
16746 | /* SPE high reg number. We get these values of regno from | |
16747 | rs6000_dwarf_register_span. */ | |
16748 | if (regno >= 1200 && regno < 1232) | |
16749 | return regno; | |
16750 | ||
16751 | abort (); | |
16752 | } | |
16753 | ||
17211ab5 | 16754 | #include "gt-rs6000.h" |