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Commit | Line | Data |
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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
f676971a | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
5b86a469 | 3 | 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
39d14dda KC |
20 | Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
cd3ce9b4 | 55 | #include "tree-gimple.h" |
4d3e6fae | 56 | #include "intl.h" |
1bc7c5b6 ZW |
57 | #if TARGET_XCOFF |
58 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
59 | #endif | |
93a27b7b ZW |
60 | #if TARGET_MACHO |
61 | #include "gstab.h" /* for N_SLINE */ | |
62 | #endif | |
9b30bae2 | 63 | |
7509c759 MM |
64 | #ifndef TARGET_NO_PROTOTYPE |
65 | #define TARGET_NO_PROTOTYPE 0 | |
66 | #endif | |
67 | ||
9878760c RK |
68 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
69 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
70 | ||
d1d0c603 JJ |
71 | /* Structure used to define the rs6000 stack */ |
72 | typedef struct rs6000_stack { | |
73 | int first_gp_reg_save; /* first callee saved GP register used */ | |
74 | int first_fp_reg_save; /* first callee saved FP register used */ | |
75 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
76 | int lr_save_p; /* true if the link reg needs to be saved */ | |
77 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
78 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
79 | int toc_save_p; /* true if the TOC needs to be saved */ | |
80 | int push_p; /* true if we need to allocate stack space */ | |
81 | int calls_p; /* true if the function makes any calls */ | |
c4ad648e | 82 | int world_save_p; /* true if we're saving *everything*: |
d62294f5 | 83 | r13-r31, cr, f14-f31, vrsave, v20-v31 */ |
d1d0c603 JJ |
84 | enum rs6000_abi abi; /* which ABI to use */ |
85 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
86 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
87 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
88 | int lr_save_offset; /* offset to save LR from initial SP */ | |
89 | int cr_save_offset; /* offset to save CR from initial SP */ | |
90 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
91 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
92 | int toc_save_offset; /* offset to save the TOC pointer */ | |
93 | int varargs_save_offset; /* offset to save the varargs registers */ | |
94 | int ehrd_offset; /* offset to EH return data */ | |
95 | int reg_size; /* register size (4 or 8) */ | |
96 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
97 | HOST_WIDE_INT vars_size; /* variable save area size */ | |
98 | int parm_size; /* outgoing parameter size */ | |
99 | int save_size; /* save area size */ | |
100 | int fixed_size; /* fixed size of stack frame */ | |
101 | int gp_size; /* size of saved GP registers */ | |
102 | int fp_size; /* size of saved FP registers */ | |
103 | int altivec_size; /* size of saved AltiVec registers */ | |
104 | int cr_size; /* size to hold CR if not in save_size */ | |
105 | int lr_size; /* size to hold LR if not in save_size */ | |
106 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ | |
107 | int altivec_padding_size; /* size of altivec alignment padding if | |
108 | not in save_size */ | |
109 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
110 | int spe_padding_size; | |
111 | int toc_size; /* size to hold TOC if not in save_size */ | |
112 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ | |
113 | int spe_64bit_regs_used; | |
114 | } rs6000_stack_t; | |
115 | ||
5248c961 RK |
116 | /* Target cpu type */ |
117 | ||
118 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
119 | struct rs6000_cpu_select rs6000_select[3] = |
120 | { | |
815cdc52 MM |
121 | /* switch name, tune arch */ |
122 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
123 | { (const char *)0, "-mcpu=", 1, 1 }, | |
124 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 125 | }; |
5248c961 | 126 | |
ec507f2d DE |
127 | /* Always emit branch hint bits. */ |
128 | static GTY(()) bool rs6000_always_hint; | |
129 | ||
130 | /* Schedule instructions for group formation. */ | |
131 | static GTY(()) bool rs6000_sched_groups; | |
132 | ||
569fa502 DN |
133 | /* Support for -msched-costly-dep option. */ |
134 | const char *rs6000_sched_costly_dep_str; | |
135 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
136 | ||
cbe26ab8 DN |
137 | /* Support for -minsert-sched-nops option. */ |
138 | const char *rs6000_sched_insert_nops_str; | |
139 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
140 | ||
7ccf35ed | 141 | /* Support targetm.vectorize.builtin_mask_for_load. */ |
13c62176 | 142 | static GTY(()) tree altivec_builtin_mask_for_load; |
7ccf35ed | 143 | |
6fa3f289 | 144 | /* Size of long double */ |
6fa3f289 ZW |
145 | int rs6000_long_double_type_size; |
146 | ||
147 | /* Whether -mabi=altivec has appeared */ | |
148 | int rs6000_altivec_abi; | |
149 | ||
a3170dc6 AH |
150 | /* Nonzero if we want SPE ABI extensions. */ |
151 | int rs6000_spe_abi; | |
152 | ||
5da702b1 AH |
153 | /* Nonzero if floating point operations are done in the GPRs. */ |
154 | int rs6000_float_gprs = 0; | |
155 | ||
594a51fe SS |
156 | /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */ |
157 | int rs6000_darwin64_abi; | |
158 | ||
a0ab749a | 159 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 160 | static GTY(()) int common_mode_defined; |
c81bebd7 | 161 | |
9878760c RK |
162 | /* Save information from a "cmpxx" operation until the branch or scc is |
163 | emitted. */ | |
9878760c RK |
164 | rtx rs6000_compare_op0, rs6000_compare_op1; |
165 | int rs6000_compare_fp_p; | |
874a0744 | 166 | |
874a0744 MM |
167 | /* Label number of label created for -mrelocatable, to call to so we can |
168 | get the address of the GOT section */ | |
169 | int rs6000_pic_labelno; | |
c81bebd7 | 170 | |
b91da81f | 171 | #ifdef USING_ELFOS_H |
c81bebd7 | 172 | /* Which abi to adhere to */ |
9739c90c | 173 | const char *rs6000_abi_name; |
d9407988 MM |
174 | |
175 | /* Semantics of the small data area */ | |
176 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
177 | ||
178 | /* Which small data model to use */ | |
815cdc52 | 179 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
180 | |
181 | /* Counter for labels which are to be placed in .fixup. */ | |
182 | int fixuplabelno = 0; | |
874a0744 | 183 | #endif |
4697a36c | 184 | |
c4501e62 JJ |
185 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
186 | int rs6000_tls_size = 32; | |
187 | const char *rs6000_tls_size_string; | |
188 | ||
b6c9286a MM |
189 | /* ABI enumeration available for subtarget to use. */ |
190 | enum rs6000_abi rs6000_current_abi; | |
191 | ||
85b776df AM |
192 | /* Whether to use variant of AIX ABI for PowerPC64 Linux. */ |
193 | int dot_symbols; | |
194 | ||
38c1f2d7 | 195 | /* Debug flags */ |
815cdc52 | 196 | const char *rs6000_debug_name; |
38c1f2d7 MM |
197 | int rs6000_debug_stack; /* debug stack applications */ |
198 | int rs6000_debug_arg; /* debug argument handling */ | |
199 | ||
aabcd309 | 200 | /* Value is TRUE if register/mode pair is acceptable. */ |
0d1fbc8c AH |
201 | bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
202 | ||
58646b77 PB |
203 | /* Built in types. */ |
204 | ||
205 | tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
206 | tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
8bb418a3 | 207 | |
57ac7be9 AM |
208 | const char *rs6000_traceback_name; |
209 | static enum { | |
210 | traceback_default = 0, | |
211 | traceback_none, | |
212 | traceback_part, | |
213 | traceback_full | |
214 | } rs6000_traceback; | |
215 | ||
38c1f2d7 MM |
216 | /* Flag to say the TOC is initialized */ |
217 | int toc_initialized; | |
9ebbca7d | 218 | char toc_label_name[10]; |
38c1f2d7 | 219 | |
9ebbca7d | 220 | /* Alias set for saves and restores from the rs6000 stack. */ |
f103e34d | 221 | static GTY(()) int rs6000_sr_alias_set; |
c8023011 | 222 | |
a3c9585f KH |
223 | /* Control alignment for fields within structures. */ |
224 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
225 | int rs6000_alignment_flags; |
226 | ||
78f5898b AH |
227 | /* True for any options that were explicitly set. */ |
228 | struct { | |
df01da37 | 229 | bool aix_struct_ret; /* True if -maix-struct-ret was used. */ |
78f5898b AH |
230 | bool alignment; /* True if -malign- was used. */ |
231 | bool abi; /* True if -mabi= was used. */ | |
232 | bool spe; /* True if -mspe= was used. */ | |
233 | bool float_gprs; /* True if -mfloat-gprs= was used. */ | |
234 | bool isel; /* True if -misel was used. */ | |
235 | bool long_double; /* True if -mlong-double- was used. */ | |
236 | } rs6000_explicit_options; | |
237 | ||
a3170dc6 AH |
238 | struct builtin_description |
239 | { | |
240 | /* mask is not const because we're going to alter it below. This | |
241 | nonsense will go away when we rewrite the -march infrastructure | |
242 | to give us more target flag bits. */ | |
243 | unsigned int mask; | |
244 | const enum insn_code icode; | |
245 | const char *const name; | |
246 | const enum rs6000_builtins code; | |
247 | }; | |
8b897cfa RS |
248 | \f |
249 | /* Target cpu costs. */ | |
250 | ||
251 | struct processor_costs { | |
c4ad648e | 252 | const int mulsi; /* cost of SImode multiplication. */ |
8b897cfa RS |
253 | const int mulsi_const; /* cost of SImode multiplication by constant. */ |
254 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
c4ad648e AM |
255 | const int muldi; /* cost of DImode multiplication. */ |
256 | const int divsi; /* cost of SImode division. */ | |
257 | const int divdi; /* cost of DImode division. */ | |
258 | const int fp; /* cost of simple SFmode and DFmode insns. */ | |
259 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
260 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
261 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
8b897cfa RS |
262 | }; |
263 | ||
264 | const struct processor_costs *rs6000_cost; | |
265 | ||
266 | /* Processor costs (relative to an add) */ | |
267 | ||
268 | /* Instruction size costs on 32bit processors. */ | |
269 | static const | |
270 | struct processor_costs size32_cost = { | |
06a67bdd RS |
271 | COSTS_N_INSNS (1), /* mulsi */ |
272 | COSTS_N_INSNS (1), /* mulsi_const */ | |
273 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
274 | COSTS_N_INSNS (1), /* muldi */ | |
275 | COSTS_N_INSNS (1), /* divsi */ | |
276 | COSTS_N_INSNS (1), /* divdi */ | |
277 | COSTS_N_INSNS (1), /* fp */ | |
278 | COSTS_N_INSNS (1), /* dmul */ | |
279 | COSTS_N_INSNS (1), /* sdiv */ | |
280 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
281 | }; |
282 | ||
283 | /* Instruction size costs on 64bit processors. */ | |
284 | static const | |
285 | struct processor_costs size64_cost = { | |
06a67bdd RS |
286 | COSTS_N_INSNS (1), /* mulsi */ |
287 | COSTS_N_INSNS (1), /* mulsi_const */ | |
288 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
289 | COSTS_N_INSNS (1), /* muldi */ | |
290 | COSTS_N_INSNS (1), /* divsi */ | |
291 | COSTS_N_INSNS (1), /* divdi */ | |
292 | COSTS_N_INSNS (1), /* fp */ | |
293 | COSTS_N_INSNS (1), /* dmul */ | |
294 | COSTS_N_INSNS (1), /* sdiv */ | |
295 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
296 | }; |
297 | ||
298 | /* Instruction costs on RIOS1 processors. */ | |
299 | static const | |
300 | struct processor_costs rios1_cost = { | |
06a67bdd RS |
301 | COSTS_N_INSNS (5), /* mulsi */ |
302 | COSTS_N_INSNS (4), /* mulsi_const */ | |
303 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
304 | COSTS_N_INSNS (5), /* muldi */ | |
305 | COSTS_N_INSNS (19), /* divsi */ | |
306 | COSTS_N_INSNS (19), /* divdi */ | |
307 | COSTS_N_INSNS (2), /* fp */ | |
308 | COSTS_N_INSNS (2), /* dmul */ | |
309 | COSTS_N_INSNS (19), /* sdiv */ | |
310 | COSTS_N_INSNS (19), /* ddiv */ | |
8b897cfa RS |
311 | }; |
312 | ||
313 | /* Instruction costs on RIOS2 processors. */ | |
314 | static const | |
315 | struct processor_costs rios2_cost = { | |
06a67bdd RS |
316 | COSTS_N_INSNS (2), /* mulsi */ |
317 | COSTS_N_INSNS (2), /* mulsi_const */ | |
318 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
319 | COSTS_N_INSNS (2), /* muldi */ | |
320 | COSTS_N_INSNS (13), /* divsi */ | |
321 | COSTS_N_INSNS (13), /* divdi */ | |
322 | COSTS_N_INSNS (2), /* fp */ | |
323 | COSTS_N_INSNS (2), /* dmul */ | |
324 | COSTS_N_INSNS (17), /* sdiv */ | |
325 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
326 | }; |
327 | ||
328 | /* Instruction costs on RS64A processors. */ | |
329 | static const | |
330 | struct processor_costs rs64a_cost = { | |
06a67bdd RS |
331 | COSTS_N_INSNS (20), /* mulsi */ |
332 | COSTS_N_INSNS (12), /* mulsi_const */ | |
333 | COSTS_N_INSNS (8), /* mulsi_const9 */ | |
334 | COSTS_N_INSNS (34), /* muldi */ | |
335 | COSTS_N_INSNS (65), /* divsi */ | |
336 | COSTS_N_INSNS (67), /* divdi */ | |
337 | COSTS_N_INSNS (4), /* fp */ | |
338 | COSTS_N_INSNS (4), /* dmul */ | |
339 | COSTS_N_INSNS (31), /* sdiv */ | |
340 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
341 | }; |
342 | ||
343 | /* Instruction costs on MPCCORE processors. */ | |
344 | static const | |
345 | struct processor_costs mpccore_cost = { | |
06a67bdd RS |
346 | COSTS_N_INSNS (2), /* mulsi */ |
347 | COSTS_N_INSNS (2), /* mulsi_const */ | |
348 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
349 | COSTS_N_INSNS (2), /* muldi */ | |
350 | COSTS_N_INSNS (6), /* divsi */ | |
351 | COSTS_N_INSNS (6), /* divdi */ | |
352 | COSTS_N_INSNS (4), /* fp */ | |
353 | COSTS_N_INSNS (5), /* dmul */ | |
354 | COSTS_N_INSNS (10), /* sdiv */ | |
355 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
356 | }; |
357 | ||
358 | /* Instruction costs on PPC403 processors. */ | |
359 | static const | |
360 | struct processor_costs ppc403_cost = { | |
06a67bdd RS |
361 | COSTS_N_INSNS (4), /* mulsi */ |
362 | COSTS_N_INSNS (4), /* mulsi_const */ | |
363 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
364 | COSTS_N_INSNS (4), /* muldi */ | |
365 | COSTS_N_INSNS (33), /* divsi */ | |
366 | COSTS_N_INSNS (33), /* divdi */ | |
367 | COSTS_N_INSNS (11), /* fp */ | |
368 | COSTS_N_INSNS (11), /* dmul */ | |
369 | COSTS_N_INSNS (11), /* sdiv */ | |
370 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
371 | }; |
372 | ||
373 | /* Instruction costs on PPC405 processors. */ | |
374 | static const | |
375 | struct processor_costs ppc405_cost = { | |
06a67bdd RS |
376 | COSTS_N_INSNS (5), /* mulsi */ |
377 | COSTS_N_INSNS (4), /* mulsi_const */ | |
378 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
379 | COSTS_N_INSNS (5), /* muldi */ | |
380 | COSTS_N_INSNS (35), /* divsi */ | |
381 | COSTS_N_INSNS (35), /* divdi */ | |
382 | COSTS_N_INSNS (11), /* fp */ | |
383 | COSTS_N_INSNS (11), /* dmul */ | |
384 | COSTS_N_INSNS (11), /* sdiv */ | |
385 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
386 | }; |
387 | ||
388 | /* Instruction costs on PPC440 processors. */ | |
389 | static const | |
390 | struct processor_costs ppc440_cost = { | |
06a67bdd RS |
391 | COSTS_N_INSNS (3), /* mulsi */ |
392 | COSTS_N_INSNS (2), /* mulsi_const */ | |
393 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
394 | COSTS_N_INSNS (3), /* muldi */ | |
395 | COSTS_N_INSNS (34), /* divsi */ | |
396 | COSTS_N_INSNS (34), /* divdi */ | |
397 | COSTS_N_INSNS (5), /* fp */ | |
398 | COSTS_N_INSNS (5), /* dmul */ | |
399 | COSTS_N_INSNS (19), /* sdiv */ | |
400 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
401 | }; |
402 | ||
403 | /* Instruction costs on PPC601 processors. */ | |
404 | static const | |
405 | struct processor_costs ppc601_cost = { | |
06a67bdd RS |
406 | COSTS_N_INSNS (5), /* mulsi */ |
407 | COSTS_N_INSNS (5), /* mulsi_const */ | |
408 | COSTS_N_INSNS (5), /* mulsi_const9 */ | |
409 | COSTS_N_INSNS (5), /* muldi */ | |
410 | COSTS_N_INSNS (36), /* divsi */ | |
411 | COSTS_N_INSNS (36), /* divdi */ | |
412 | COSTS_N_INSNS (4), /* fp */ | |
413 | COSTS_N_INSNS (5), /* dmul */ | |
414 | COSTS_N_INSNS (17), /* sdiv */ | |
415 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
416 | }; |
417 | ||
418 | /* Instruction costs on PPC603 processors. */ | |
419 | static const | |
420 | struct processor_costs ppc603_cost = { | |
06a67bdd RS |
421 | COSTS_N_INSNS (5), /* mulsi */ |
422 | COSTS_N_INSNS (3), /* mulsi_const */ | |
423 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
424 | COSTS_N_INSNS (5), /* muldi */ | |
425 | COSTS_N_INSNS (37), /* divsi */ | |
426 | COSTS_N_INSNS (37), /* divdi */ | |
427 | COSTS_N_INSNS (3), /* fp */ | |
428 | COSTS_N_INSNS (4), /* dmul */ | |
429 | COSTS_N_INSNS (18), /* sdiv */ | |
430 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
431 | }; |
432 | ||
433 | /* Instruction costs on PPC604 processors. */ | |
434 | static const | |
435 | struct processor_costs ppc604_cost = { | |
06a67bdd RS |
436 | COSTS_N_INSNS (4), /* mulsi */ |
437 | COSTS_N_INSNS (4), /* mulsi_const */ | |
438 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
439 | COSTS_N_INSNS (4), /* muldi */ | |
440 | COSTS_N_INSNS (20), /* divsi */ | |
441 | COSTS_N_INSNS (20), /* divdi */ | |
442 | COSTS_N_INSNS (3), /* fp */ | |
443 | COSTS_N_INSNS (3), /* dmul */ | |
444 | COSTS_N_INSNS (18), /* sdiv */ | |
445 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
446 | }; |
447 | ||
448 | /* Instruction costs on PPC604e processors. */ | |
449 | static const | |
450 | struct processor_costs ppc604e_cost = { | |
06a67bdd RS |
451 | COSTS_N_INSNS (2), /* mulsi */ |
452 | COSTS_N_INSNS (2), /* mulsi_const */ | |
453 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
454 | COSTS_N_INSNS (2), /* muldi */ | |
455 | COSTS_N_INSNS (20), /* divsi */ | |
456 | COSTS_N_INSNS (20), /* divdi */ | |
457 | COSTS_N_INSNS (3), /* fp */ | |
458 | COSTS_N_INSNS (3), /* dmul */ | |
459 | COSTS_N_INSNS (18), /* sdiv */ | |
460 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
461 | }; |
462 | ||
f0517163 | 463 | /* Instruction costs on PPC620 processors. */ |
8b897cfa RS |
464 | static const |
465 | struct processor_costs ppc620_cost = { | |
06a67bdd RS |
466 | COSTS_N_INSNS (5), /* mulsi */ |
467 | COSTS_N_INSNS (4), /* mulsi_const */ | |
468 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
469 | COSTS_N_INSNS (7), /* muldi */ | |
470 | COSTS_N_INSNS (21), /* divsi */ | |
471 | COSTS_N_INSNS (37), /* divdi */ | |
472 | COSTS_N_INSNS (3), /* fp */ | |
473 | COSTS_N_INSNS (3), /* dmul */ | |
474 | COSTS_N_INSNS (18), /* sdiv */ | |
475 | COSTS_N_INSNS (32), /* ddiv */ | |
f0517163 RS |
476 | }; |
477 | ||
478 | /* Instruction costs on PPC630 processors. */ | |
479 | static const | |
480 | struct processor_costs ppc630_cost = { | |
06a67bdd RS |
481 | COSTS_N_INSNS (5), /* mulsi */ |
482 | COSTS_N_INSNS (4), /* mulsi_const */ | |
483 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
484 | COSTS_N_INSNS (7), /* muldi */ | |
485 | COSTS_N_INSNS (21), /* divsi */ | |
486 | COSTS_N_INSNS (37), /* divdi */ | |
487 | COSTS_N_INSNS (3), /* fp */ | |
488 | COSTS_N_INSNS (3), /* dmul */ | |
489 | COSTS_N_INSNS (17), /* sdiv */ | |
490 | COSTS_N_INSNS (21), /* ddiv */ | |
8b897cfa RS |
491 | }; |
492 | ||
493 | /* Instruction costs on PPC750 and PPC7400 processors. */ | |
494 | static const | |
495 | struct processor_costs ppc750_cost = { | |
06a67bdd RS |
496 | COSTS_N_INSNS (5), /* mulsi */ |
497 | COSTS_N_INSNS (3), /* mulsi_const */ | |
498 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
499 | COSTS_N_INSNS (5), /* muldi */ | |
500 | COSTS_N_INSNS (17), /* divsi */ | |
501 | COSTS_N_INSNS (17), /* divdi */ | |
502 | COSTS_N_INSNS (3), /* fp */ | |
503 | COSTS_N_INSNS (3), /* dmul */ | |
504 | COSTS_N_INSNS (17), /* sdiv */ | |
505 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
506 | }; |
507 | ||
508 | /* Instruction costs on PPC7450 processors. */ | |
509 | static const | |
510 | struct processor_costs ppc7450_cost = { | |
06a67bdd RS |
511 | COSTS_N_INSNS (4), /* mulsi */ |
512 | COSTS_N_INSNS (3), /* mulsi_const */ | |
513 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
514 | COSTS_N_INSNS (4), /* muldi */ | |
515 | COSTS_N_INSNS (23), /* divsi */ | |
516 | COSTS_N_INSNS (23), /* divdi */ | |
517 | COSTS_N_INSNS (5), /* fp */ | |
518 | COSTS_N_INSNS (5), /* dmul */ | |
519 | COSTS_N_INSNS (21), /* sdiv */ | |
520 | COSTS_N_INSNS (35), /* ddiv */ | |
8b897cfa | 521 | }; |
a3170dc6 | 522 | |
8b897cfa RS |
523 | /* Instruction costs on PPC8540 processors. */ |
524 | static const | |
525 | struct processor_costs ppc8540_cost = { | |
06a67bdd RS |
526 | COSTS_N_INSNS (4), /* mulsi */ |
527 | COSTS_N_INSNS (4), /* mulsi_const */ | |
528 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
529 | COSTS_N_INSNS (4), /* muldi */ | |
530 | COSTS_N_INSNS (19), /* divsi */ | |
531 | COSTS_N_INSNS (19), /* divdi */ | |
532 | COSTS_N_INSNS (4), /* fp */ | |
533 | COSTS_N_INSNS (4), /* dmul */ | |
534 | COSTS_N_INSNS (29), /* sdiv */ | |
535 | COSTS_N_INSNS (29), /* ddiv */ | |
8b897cfa RS |
536 | }; |
537 | ||
538 | /* Instruction costs on POWER4 and POWER5 processors. */ | |
539 | static const | |
540 | struct processor_costs power4_cost = { | |
06a67bdd RS |
541 | COSTS_N_INSNS (3), /* mulsi */ |
542 | COSTS_N_INSNS (2), /* mulsi_const */ | |
543 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
544 | COSTS_N_INSNS (4), /* muldi */ | |
545 | COSTS_N_INSNS (18), /* divsi */ | |
546 | COSTS_N_INSNS (34), /* divdi */ | |
547 | COSTS_N_INSNS (3), /* fp */ | |
548 | COSTS_N_INSNS (3), /* dmul */ | |
549 | COSTS_N_INSNS (17), /* sdiv */ | |
550 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
551 | }; |
552 | ||
553 | \f | |
a2369ed3 | 554 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
2ffa9a0c | 555 | static const char *rs6000_invalid_within_doloop (rtx); |
a2369ed3 DJ |
556 | static rtx rs6000_generate_compare (enum rtx_code); |
557 | static void rs6000_maybe_dead (rtx); | |
558 | static void rs6000_emit_stack_tie (void); | |
559 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
560 | static rtx spe_synthesize_frame_save (rtx); | |
561 | static bool spe_func_has_64bit_regs_p (void); | |
b20a9cca | 562 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 563 | int, HOST_WIDE_INT); |
a2369ed3 DJ |
564 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
565 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); | |
566 | static unsigned rs6000_hash_constant (rtx); | |
567 | static unsigned toc_hash_function (const void *); | |
568 | static int toc_hash_eq (const void *, const void *); | |
569 | static int constant_pool_expr_1 (rtx, int *, int *); | |
570 | static bool constant_pool_expr_p (rtx); | |
a2369ed3 | 571 | static bool legitimate_small_data_p (enum machine_mode, rtx); |
a2369ed3 | 572 | static bool legitimate_indexed_address_p (rtx, int); |
a2369ed3 DJ |
573 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
574 | static struct machine_function * rs6000_init_machine_status (void); | |
575 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
6d0a8091 | 576 | static bool no_global_regs_above (int); |
5add3202 | 577 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 578 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 579 | #endif |
a2369ed3 DJ |
580 | static int rs6000_ra_ever_killed (void); |
581 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
8bb418a3 | 582 | static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); |
76d2b81d | 583 | static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); |
f18eca82 | 584 | static const char *rs6000_mangle_fundamental_type (tree); |
b86fe7b4 | 585 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 DJ |
586 | static void rs6000_set_default_type_attributes (tree); |
587 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); | |
588 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
589 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
590 | tree); | |
a2369ed3 | 591 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
c6e8c921 | 592 | static bool rs6000_return_in_memory (tree, tree); |
a2369ed3 | 593 | static void rs6000_file_start (void); |
7c262518 | 594 | #if TARGET_ELF |
a2369ed3 DJ |
595 | static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); |
596 | static void rs6000_elf_asm_out_constructor (rtx, int); | |
597 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
1334b570 | 598 | static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED; |
a2369ed3 DJ |
599 | static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); |
600 | static void rs6000_elf_unique_section (tree, int); | |
601 | static void rs6000_elf_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 602 | unsigned HOST_WIDE_INT); |
a56d7372 | 603 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 604 | ATTRIBUTE_UNUSED; |
a2369ed3 | 605 | static bool rs6000_elf_in_small_data_p (tree); |
7c262518 | 606 | #endif |
cbaaba19 | 607 | #if TARGET_XCOFF |
a2369ed3 | 608 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
8210e4c4 | 609 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree); |
a2369ed3 DJ |
610 | static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT); |
611 | static void rs6000_xcoff_unique_section (tree, int); | |
612 | static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 613 | unsigned HOST_WIDE_INT); |
a2369ed3 DJ |
614 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
615 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
616 | static void rs6000_xcoff_file_start (void); | |
617 | static void rs6000_xcoff_file_end (void); | |
f1384257 | 618 | #endif |
a2369ed3 DJ |
619 | static int rs6000_variable_issue (FILE *, int, rtx, int); |
620 | static bool rs6000_rtx_costs (rtx, int, int, int *); | |
621 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); | |
cbe26ab8 | 622 | static bool is_microcoded_insn (rtx); |
79ae11c4 | 623 | static int is_dispatch_slot_restricted (rtx); |
cbe26ab8 DN |
624 | static bool is_cracked_insn (rtx); |
625 | static bool is_branch_slot_insn (rtx); | |
a2369ed3 DJ |
626 | static int rs6000_adjust_priority (rtx, int); |
627 | static int rs6000_issue_rate (void); | |
569fa502 | 628 | static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); |
cbe26ab8 DN |
629 | static rtx get_next_active_insn (rtx, rtx); |
630 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
631 | static bool is_costly_group (rtx *, rtx); | |
632 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
633 | static int redefine_groups (FILE *, int, rtx, rtx); | |
634 | static int pad_groups (FILE *, int, rtx, rtx); | |
635 | static void rs6000_sched_finish (FILE *, int); | |
a2369ed3 | 636 | static int rs6000_use_sched_lookahead (void); |
7ccf35ed | 637 | static tree rs6000_builtin_mask_for_load (void); |
a2369ed3 | 638 | |
58646b77 | 639 | static void def_builtin (int, const char *, tree, int); |
a2369ed3 DJ |
640 | static void rs6000_init_builtins (void); |
641 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
642 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
643 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
644 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
645 | static void altivec_init_builtins (void); | |
646 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 647 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 648 | |
b20a9cca AM |
649 | static void enable_mask_for_builtins (struct builtin_description *, int, |
650 | enum rs6000_builtins, | |
651 | enum rs6000_builtins); | |
7c62e993 | 652 | static tree build_opaque_vector_type (tree, int); |
a2369ed3 DJ |
653 | static void spe_init_builtins (void); |
654 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
61bea3b0 | 655 | static rtx spe_expand_stv_builtin (enum insn_code, tree); |
a2369ed3 DJ |
656 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); |
657 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
658 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
659 | static rs6000_stack_t *rs6000_stack_info (void); |
660 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
661 | |
662 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
663 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
664 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
665 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
666 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
f676971a | 667 | static rtx altivec_expand_predicate_builtin (enum insn_code, |
c4ad648e | 668 | const char *, tree, rtx); |
b4a62fa0 | 669 | static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); |
a2369ed3 | 670 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
78f5898b | 671 | static bool rs6000_handle_option (size_t, const char *, int); |
a2369ed3 | 672 | static void rs6000_parse_tls_size_option (void); |
5da702b1 | 673 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
a2369ed3 DJ |
674 | static int first_altivec_reg_to_save (void); |
675 | static unsigned int compute_vrsave_mask (void); | |
9390387d | 676 | static void compute_save_world_info (rs6000_stack_t *info_ptr); |
a2369ed3 DJ |
677 | static void is_altivec_return_reg (rtx, void *); |
678 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
679 | int easy_vector_constant (rtx, enum machine_mode); | |
58646b77 | 680 | static bool rs6000_is_opaque_type (tree); |
a2369ed3 DJ |
681 | static rtx rs6000_dwarf_register_span (rtx); |
682 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); | |
fdbe66f2 | 683 | static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
a2369ed3 DJ |
684 | static rtx rs6000_tls_get_addr (void); |
685 | static rtx rs6000_got_sym (void); | |
9390387d | 686 | static int rs6000_tls_symbol_ref_1 (rtx *, void *); |
a2369ed3 DJ |
687 | static const char *rs6000_get_some_local_dynamic_name (void); |
688 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 689 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 690 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 691 | enum machine_mode, tree); |
0b5383eb DJ |
692 | static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *, |
693 | HOST_WIDE_INT); | |
694 | static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *, | |
695 | tree, HOST_WIDE_INT); | |
696 | static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *, | |
697 | HOST_WIDE_INT, | |
698 | rtx[], int *); | |
699 | static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *, | |
700 | tree, HOST_WIDE_INT, | |
701 | rtx[], int *); | |
702 | static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool); | |
ec6376ab | 703 | static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); |
b1917422 | 704 | static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); |
c6e8c921 GK |
705 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
706 | enum machine_mode, tree, | |
707 | int *, int); | |
8cd5a4e0 RH |
708 | static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
709 | tree, bool); | |
78a52f11 RH |
710 | static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
711 | tree, bool); | |
4d3e6fae | 712 | static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree); |
efdba735 SH |
713 | #if TARGET_MACHO |
714 | static void macho_branch_islands (void); | |
715 | static void add_compiler_branch_island (tree, tree, int); | |
716 | static int no_previous_def (tree function_name); | |
717 | static tree get_prev_label (tree function_name); | |
c4e18b1c | 718 | static void rs6000_darwin_file_start (void); |
efdba735 SH |
719 | #endif |
720 | ||
c35d187f | 721 | static tree rs6000_build_builtin_va_list (void); |
23a60a04 | 722 | static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); |
fe984136 | 723 | static bool rs6000_must_pass_in_stack (enum machine_mode, tree); |
f676971a | 724 | static bool rs6000_vector_mode_supported_p (enum machine_mode); |
94ff898d | 725 | static int get_vec_cmp_insn (enum rtx_code, enum machine_mode, |
21213b4c | 726 | enum machine_mode); |
94ff898d | 727 | static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx, |
21213b4c DP |
728 | enum machine_mode); |
729 | static int get_vsel_insn (enum machine_mode); | |
730 | static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx); | |
17211ab5 | 731 | |
21213b4c DP |
732 | |
733 | const int INSN_NOT_AVAILABLE = -1; | |
93f90be6 FJ |
734 | static enum machine_mode rs6000_eh_return_filter_mode (void); |
735 | ||
17211ab5 GK |
736 | /* Hash table stuff for keeping track of TOC entries. */ |
737 | ||
738 | struct toc_hash_struct GTY(()) | |
739 | { | |
740 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
741 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
742 | rtx key; | |
743 | enum machine_mode key_mode; | |
744 | int labelno; | |
745 | }; | |
746 | ||
747 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
748 | \f |
749 | /* Default register names. */ | |
750 | char rs6000_reg_names[][8] = | |
751 | { | |
802a0058 MM |
752 | "0", "1", "2", "3", "4", "5", "6", "7", |
753 | "8", "9", "10", "11", "12", "13", "14", "15", | |
754 | "16", "17", "18", "19", "20", "21", "22", "23", | |
755 | "24", "25", "26", "27", "28", "29", "30", "31", | |
756 | "0", "1", "2", "3", "4", "5", "6", "7", | |
757 | "8", "9", "10", "11", "12", "13", "14", "15", | |
758 | "16", "17", "18", "19", "20", "21", "22", "23", | |
759 | "24", "25", "26", "27", "28", "29", "30", "31", | |
760 | "mq", "lr", "ctr","ap", | |
761 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
762 | "xer", |
763 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
764 | "0", "1", "2", "3", "4", "5", "6", "7", |
765 | "8", "9", "10", "11", "12", "13", "14", "15", | |
766 | "16", "17", "18", "19", "20", "21", "22", "23", | |
767 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
768 | "vrsave", "vscr", |
769 | /* SPE registers. */ | |
770 | "spe_acc", "spefscr" | |
c81bebd7 MM |
771 | }; |
772 | ||
773 | #ifdef TARGET_REGNAMES | |
8b60264b | 774 | static const char alt_reg_names[][8] = |
c81bebd7 | 775 | { |
802a0058 MM |
776 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
777 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
778 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
779 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
780 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
781 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
782 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
783 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
784 | "mq", "lr", "ctr", "ap", | |
785 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 786 | "xer", |
59a4c851 | 787 | /* AltiVec registers. */ |
0ac081f6 | 788 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
789 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
790 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
791 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
792 | "vrsave", "vscr", | |
793 | /* SPE registers. */ | |
794 | "spe_acc", "spefscr" | |
c81bebd7 MM |
795 | }; |
796 | #endif | |
9878760c | 797 | \f |
daf11973 MM |
798 | #ifndef MASK_STRICT_ALIGN |
799 | #define MASK_STRICT_ALIGN 0 | |
800 | #endif | |
ffcfcb5f AM |
801 | #ifndef TARGET_PROFILE_KERNEL |
802 | #define TARGET_PROFILE_KERNEL 0 | |
803 | #endif | |
3961e8fe RH |
804 | |
805 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
806 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
672a6f42 NB |
807 | \f |
808 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
809 | #undef TARGET_ATTRIBUTE_TABLE |
810 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
811 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
812 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 813 | |
301d03af RS |
814 | #undef TARGET_ASM_ALIGNED_DI_OP |
815 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
816 | ||
817 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
818 | for non-ELF systems. */ | |
819 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 820 | #if TARGET_XCOFF |
ae6c1efd | 821 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
822 | 64-bit targets. */ |
823 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
824 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
825 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
826 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
827 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
828 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
829 | #else | |
830 | /* For Darwin. */ | |
831 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
832 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
833 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
834 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
49bd1d27 SS |
835 | #undef TARGET_ASM_UNALIGNED_DI_OP |
836 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t" | |
837 | #undef TARGET_ASM_ALIGNED_DI_OP | |
838 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
301d03af RS |
839 | #endif |
840 | #endif | |
841 | ||
842 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
843 | in 64-bit code. */ | |
844 | #undef TARGET_ASM_INTEGER | |
845 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
846 | ||
93638d7a AM |
847 | #ifdef HAVE_GAS_HIDDEN |
848 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
849 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
850 | #endif | |
851 | ||
c4501e62 JJ |
852 | #undef TARGET_HAVE_TLS |
853 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
854 | ||
855 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
856 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p | |
857 | ||
08c148a8 NB |
858 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
859 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
860 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
861 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
862 | ||
b54cf83a DE |
863 | #undef TARGET_SCHED_VARIABLE_ISSUE |
864 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
865 | ||
c237e94a ZW |
866 | #undef TARGET_SCHED_ISSUE_RATE |
867 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
868 | #undef TARGET_SCHED_ADJUST_COST | |
869 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
870 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
871 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
f676971a | 872 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
569fa502 | 873 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence |
cbe26ab8 DN |
874 | #undef TARGET_SCHED_FINISH |
875 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
c237e94a | 876 | |
be12c2b0 VM |
877 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
878 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
879 | ||
7ccf35ed DN |
880 | #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD |
881 | #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load | |
882 | ||
0ac081f6 AH |
883 | #undef TARGET_INIT_BUILTINS |
884 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
885 | ||
886 | #undef TARGET_EXPAND_BUILTIN | |
887 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
888 | ||
f18eca82 ZL |
889 | #undef TARGET_MANGLE_FUNDAMENTAL_TYPE |
890 | #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type | |
891 | ||
c15c90bb ZW |
892 | #undef TARGET_INIT_LIBFUNCS |
893 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
894 | ||
f1384257 | 895 | #if TARGET_MACHO |
0e5dbd9b | 896 | #undef TARGET_BINDS_LOCAL_P |
31920d83 | 897 | #define TARGET_BINDS_LOCAL_P darwin_binds_local_p |
f1384257 | 898 | #endif |
0e5dbd9b | 899 | |
3961e8fe RH |
900 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
901 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
902 | ||
3961e8fe | 903 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 904 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 905 | |
4977bab6 ZW |
906 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
907 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
908 | ||
2e3f0db6 DJ |
909 | #undef TARGET_INVALID_WITHIN_DOLOOP |
910 | #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop | |
9419649c | 911 | |
3c50106f RH |
912 | #undef TARGET_RTX_COSTS |
913 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
914 | #undef TARGET_ADDRESS_COST |
915 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 916 | |
c8e4f0e9 | 917 | #undef TARGET_VECTOR_OPAQUE_P |
58646b77 | 918 | #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type |
62e1dfcf | 919 | |
96714395 AH |
920 | #undef TARGET_DWARF_REGISTER_SPAN |
921 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
922 | ||
c6e8c921 GK |
923 | /* On rs6000, function arguments are promoted, as are function return |
924 | values. */ | |
925 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
926 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
927 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
928 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
929 | ||
c6e8c921 GK |
930 | #undef TARGET_RETURN_IN_MEMORY |
931 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
932 | ||
933 | #undef TARGET_SETUP_INCOMING_VARARGS | |
934 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
935 | ||
936 | /* Always strict argument naming on rs6000. */ | |
937 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
938 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
939 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
940 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
42ba5130 RH |
941 | #undef TARGET_SPLIT_COMPLEX_ARG |
942 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true | |
fe984136 RH |
943 | #undef TARGET_MUST_PASS_IN_STACK |
944 | #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack | |
8cd5a4e0 RH |
945 | #undef TARGET_PASS_BY_REFERENCE |
946 | #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference | |
78a52f11 RH |
947 | #undef TARGET_ARG_PARTIAL_BYTES |
948 | #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes | |
c6e8c921 | 949 | |
c35d187f RH |
950 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
951 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
952 | ||
cd3ce9b4 JM |
953 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
954 | #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg | |
955 | ||
93f90be6 FJ |
956 | #undef TARGET_EH_RETURN_FILTER_MODE |
957 | #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode | |
958 | ||
f676971a EC |
959 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
960 | #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p | |
961 | ||
4d3e6fae FJ |
962 | #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN |
963 | #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn | |
964 | ||
78f5898b AH |
965 | #undef TARGET_HANDLE_OPTION |
966 | #define TARGET_HANDLE_OPTION rs6000_handle_option | |
967 | ||
968 | #undef TARGET_DEFAULT_TARGET_FLAGS | |
969 | #define TARGET_DEFAULT_TARGET_FLAGS \ | |
970 | (TARGET_DEFAULT | MASK_SCHED_PROLOG) | |
971 | ||
445cf5eb JM |
972 | /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors |
973 | The PowerPC architecture requires only weak consistency among | |
974 | processors--that is, memory accesses between processors need not be | |
975 | sequentially consistent and memory accesses among processors can occur | |
976 | in any order. The ability to order memory accesses weakly provides | |
977 | opportunities for more efficient use of the system bus. Unless a | |
978 | dependency exists, the 604e allows read operations to precede store | |
979 | operations. */ | |
980 | #undef TARGET_RELAXED_ORDERING | |
981 | #define TARGET_RELAXED_ORDERING true | |
982 | ||
fdbe66f2 EB |
983 | #ifdef HAVE_AS_TLS |
984 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
985 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel | |
986 | #endif | |
987 | ||
f6897b10 | 988 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 989 | \f |
0d1fbc8c AH |
990 | |
991 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
992 | MODE. */ | |
993 | static int | |
994 | rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
995 | { | |
996 | /* The GPRs can hold any mode, but values bigger than one register | |
997 | cannot go past R31. */ | |
998 | if (INT_REGNO_P (regno)) | |
999 | return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); | |
1000 | ||
1001 | /* The float registers can only hold floating modes and DImode. */ | |
1002 | if (FP_REGNO_P (regno)) | |
1003 | return | |
1004 | (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1005 | && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) | |
1006 | || (GET_MODE_CLASS (mode) == MODE_INT | |
1007 | && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD); | |
1008 | ||
1009 | /* The CR register can only hold CC modes. */ | |
1010 | if (CR_REGNO_P (regno)) | |
1011 | return GET_MODE_CLASS (mode) == MODE_CC; | |
1012 | ||
1013 | if (XER_REGNO_P (regno)) | |
1014 | return mode == PSImode; | |
1015 | ||
1016 | /* AltiVec only in AldyVec registers. */ | |
1017 | if (ALTIVEC_REGNO_P (regno)) | |
1018 | return ALTIVEC_VECTOR_MODE (mode); | |
1019 | ||
1020 | /* ...but GPRs can hold SIMD data on the SPE in one register. */ | |
1021 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
1022 | return 1; | |
1023 | ||
1024 | /* We cannot put TImode anywhere except general register and it must be | |
1025 | able to fit within the register set. */ | |
1026 | ||
1027 | return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; | |
1028 | } | |
1029 | ||
1030 | /* Initialize rs6000_hard_regno_mode_ok_p table. */ | |
1031 | static void | |
1032 | rs6000_init_hard_regno_mode_ok (void) | |
1033 | { | |
1034 | int r, m; | |
1035 | ||
1036 | for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) | |
1037 | for (m = 0; m < NUM_MACHINE_MODES; ++m) | |
1038 | if (rs6000_hard_regno_mode_ok (r, m)) | |
1039 | rs6000_hard_regno_mode_ok_p[m][r] = true; | |
1040 | } | |
1041 | ||
c1e55850 GK |
1042 | /* If not otherwise specified by a target, make 'long double' equivalent to |
1043 | 'double'. */ | |
1044 | ||
1045 | #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE | |
1046 | #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 | |
1047 | #endif | |
1048 | ||
5248c961 RK |
1049 | /* Override command line options. Mostly we process the processor |
1050 | type and sometimes adjust other TARGET_ options. */ | |
1051 | ||
1052 | void | |
d779d0dc | 1053 | rs6000_override_options (const char *default_cpu) |
5248c961 | 1054 | { |
c4d38ccb | 1055 | size_t i, j; |
8e3f41e7 | 1056 | struct rs6000_cpu_select *ptr; |
66188a7e | 1057 | int set_masks; |
5248c961 | 1058 | |
66188a7e | 1059 | /* Simplifications for entries below. */ |
85638c0d | 1060 | |
66188a7e GK |
1061 | enum { |
1062 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
1063 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
1064 | }; | |
85638c0d | 1065 | |
66188a7e GK |
1066 | /* This table occasionally claims that a processor does not support |
1067 | a particular feature even though it does, but the feature is slower | |
1068 | than the alternative. Thus, it shouldn't be relied on as a | |
f676971a | 1069 | complete description of the processor's support. |
66188a7e GK |
1070 | |
1071 | Please keep this list in order, and don't forget to update the | |
1072 | documentation in invoke.texi when adding a new processor or | |
1073 | flag. */ | |
5248c961 RK |
1074 | static struct ptt |
1075 | { | |
8b60264b KG |
1076 | const char *const name; /* Canonical processor name. */ |
1077 | const enum processor_type processor; /* Processor type enum value. */ | |
1078 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 1079 | } const processor_target_table[] |
66188a7e | 1080 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 1081 | {"403", PROCESSOR_PPC403, |
66188a7e GK |
1082 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
1083 | {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1084 | {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK}, | |
1085 | {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1086 | {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK}, | |
1087 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, | |
5248c961 | 1088 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
1089 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
1090 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1091 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1092 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1093 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1094 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
1095 | {"620", PROCESSOR_PPC620, |
1096 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1097 | {"630", PROCESSOR_PPC630, | |
1098 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
1099 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
1100 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
1101 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
1102 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1103 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1104 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1105 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1106 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
4d4cbc0e AH |
1107 | /* 8548 has a dummy entry for now. */ |
1108 | {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
66188a7e | 1109 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
7177e720 | 1110 | {"970", PROCESSOR_POWER4, |
66188a7e GK |
1111 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1112 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, | |
1113 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1114 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1115 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 1116 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
1117 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1118 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1119 | {"power2", PROCESSOR_POWER, | |
1120 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
1121 | {"power3", PROCESSOR_PPC630, |
1122 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1123 | {"power4", PROCESSOR_POWER4, | |
fc091c8e | 1124 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
ec507f2d | 1125 | {"power5", PROCESSOR_POWER5, |
432218ba DE |
1126 | POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT |
1127 | | MASK_MFCRF | MASK_POPCNTB}, | |
66188a7e GK |
1128 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
1129 | {"powerpc64", PROCESSOR_POWERPC64, | |
98c41d98 | 1130 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, |
66188a7e GK |
1131 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, |
1132 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1133 | {"rios2", PROCESSOR_RIOS2, | |
1134 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
1135 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1136 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
98c41d98 DE |
1137 | {"rs64", PROCESSOR_RS64A, |
1138 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64} | |
66188a7e | 1139 | }; |
5248c961 | 1140 | |
ca7558fc | 1141 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 1142 | |
66188a7e GK |
1143 | /* Some OSs don't support saving the high part of 64-bit registers on |
1144 | context switch. Other OSs don't support saving Altivec registers. | |
1145 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
1146 | settings; if the user wants either, the user must explicitly specify | |
1147 | them and we won't interfere with the user's specification. */ | |
1148 | ||
1149 | enum { | |
1150 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
f676971a | 1151 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT |
66188a7e GK |
1152 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC |
1153 | | MASK_MFCRF) | |
1154 | }; | |
0d1fbc8c AH |
1155 | |
1156 | rs6000_init_hard_regno_mode_ok (); | |
1157 | ||
c4ad648e | 1158 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; |
66188a7e GK |
1159 | #ifdef OS_MISSING_POWERPC64 |
1160 | if (OS_MISSING_POWERPC64) | |
1161 | set_masks &= ~MASK_POWERPC64; | |
1162 | #endif | |
1163 | #ifdef OS_MISSING_ALTIVEC | |
1164 | if (OS_MISSING_ALTIVEC) | |
1165 | set_masks &= ~MASK_ALTIVEC; | |
1166 | #endif | |
1167 | ||
768875a8 AM |
1168 | /* Don't override by the processor default if given explicitly. */ |
1169 | set_masks &= ~target_flags_explicit; | |
957211c3 | 1170 | |
a4f6c312 | 1171 | /* Identify the processor type. */ |
8e3f41e7 | 1172 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 1173 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 1174 | |
b6a1cbae | 1175 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 1176 | { |
8e3f41e7 MM |
1177 | ptr = &rs6000_select[i]; |
1178 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 1179 | { |
8e3f41e7 MM |
1180 | for (j = 0; j < ptt_size; j++) |
1181 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
1182 | { | |
1183 | if (ptr->set_tune_p) | |
1184 | rs6000_cpu = processor_target_table[j].processor; | |
1185 | ||
1186 | if (ptr->set_arch_p) | |
1187 | { | |
66188a7e GK |
1188 | target_flags &= ~set_masks; |
1189 | target_flags |= (processor_target_table[j].target_enable | |
1190 | & set_masks); | |
8e3f41e7 MM |
1191 | } |
1192 | break; | |
1193 | } | |
1194 | ||
4406229e | 1195 | if (j == ptt_size) |
8e3f41e7 | 1196 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
1197 | } |
1198 | } | |
8a61d227 | 1199 | |
993f19a8 | 1200 | if (TARGET_E500) |
a3170dc6 AH |
1201 | rs6000_isel = 1; |
1202 | ||
dff9f1b6 DE |
1203 | /* If we are optimizing big endian systems for space, use the load/store |
1204 | multiple and string instructions. */ | |
ef792183 | 1205 | if (BYTES_BIG_ENDIAN && optimize_size) |
957211c3 | 1206 | target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); |
938937d8 | 1207 | |
a4f6c312 SS |
1208 | /* Don't allow -mmultiple or -mstring on little endian systems |
1209 | unless the cpu is a 750, because the hardware doesn't support the | |
1210 | instructions used in little endian mode, and causes an alignment | |
1211 | trap. The 750 does not cause an alignment trap (except when the | |
1212 | target is unaligned). */ | |
bef84347 | 1213 | |
b21fb038 | 1214 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
1215 | { |
1216 | if (TARGET_MULTIPLE) | |
1217 | { | |
1218 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 1219 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
d4ee4d25 | 1220 | warning (0, "-mmultiple is not supported on little endian systems"); |
7e69e155 MM |
1221 | } |
1222 | ||
1223 | if (TARGET_STRING) | |
1224 | { | |
1225 | target_flags &= ~MASK_STRING; | |
b21fb038 | 1226 | if ((target_flags_explicit & MASK_STRING) != 0) |
d4ee4d25 | 1227 | warning (0, "-mstring is not supported on little endian systems"); |
7e69e155 MM |
1228 | } |
1229 | } | |
3933e0e1 | 1230 | |
38c1f2d7 MM |
1231 | /* Set debug flags */ |
1232 | if (rs6000_debug_name) | |
1233 | { | |
bfc79d3b | 1234 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 1235 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 1236 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 1237 | rs6000_debug_stack = 1; |
bfc79d3b | 1238 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
1239 | rs6000_debug_arg = 1; |
1240 | else | |
c725bd79 | 1241 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
1242 | } |
1243 | ||
57ac7be9 AM |
1244 | if (rs6000_traceback_name) |
1245 | { | |
1246 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
1247 | rs6000_traceback = traceback_full; | |
1248 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
1249 | rs6000_traceback = traceback_part; | |
1250 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
1251 | rs6000_traceback = traceback_none; | |
1252 | else | |
9e637a26 | 1253 | error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>", |
57ac7be9 AM |
1254 | rs6000_traceback_name); |
1255 | } | |
1256 | ||
78f5898b AH |
1257 | if (!rs6000_explicit_options.long_double) |
1258 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; | |
6fa3f289 | 1259 | |
6d0ef01e HP |
1260 | /* Set Altivec ABI as default for powerpc64 linux. */ |
1261 | if (TARGET_ELF && TARGET_64BIT) | |
1262 | { | |
1263 | rs6000_altivec_abi = 1; | |
78f5898b | 1264 | TARGET_ALTIVEC_VRSAVE = 1; |
6d0ef01e HP |
1265 | } |
1266 | ||
594a51fe SS |
1267 | /* Set the Darwin64 ABI as default for 64-bit Darwin. */ |
1268 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
1269 | { | |
1270 | rs6000_darwin64_abi = 1; | |
9c7956fd | 1271 | #if TARGET_MACHO |
6ac49599 | 1272 | darwin_one_byte_bool = 1; |
9c7956fd | 1273 | #endif |
d9168963 SS |
1274 | /* Default to natural alignment, for better performance. */ |
1275 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
594a51fe SS |
1276 | } |
1277 | ||
c4501e62 JJ |
1278 | /* Handle -mtls-size option. */ |
1279 | rs6000_parse_tls_size_option (); | |
1280 | ||
a7ae18e2 AH |
1281 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1282 | SUBTARGET_OVERRIDE_OPTIONS; | |
1283 | #endif | |
1284 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
1285 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
1286 | #endif | |
4d4cbc0e AH |
1287 | #ifdef SUB3TARGET_OVERRIDE_OPTIONS |
1288 | SUB3TARGET_OVERRIDE_OPTIONS; | |
1289 | #endif | |
a7ae18e2 | 1290 | |
5da702b1 AH |
1291 | if (TARGET_E500) |
1292 | { | |
e4463bf1 AH |
1293 | if (TARGET_ALTIVEC) |
1294 | error ("AltiVec and E500 instructions cannot coexist"); | |
1295 | ||
5da702b1 AH |
1296 | /* The e500 does not have string instructions, and we set |
1297 | MASK_STRING above when optimizing for size. */ | |
1298 | if ((target_flags & MASK_STRING) != 0) | |
1299 | target_flags = target_flags & ~MASK_STRING; | |
1300 | } | |
1301 | else if (rs6000_select[1].string != NULL) | |
1302 | { | |
1303 | /* For the powerpc-eabispe configuration, we set all these by | |
1304 | default, so let's unset them if we manually set another | |
1305 | CPU that is not the E500. */ | |
78f5898b | 1306 | if (!rs6000_explicit_options.abi) |
5da702b1 | 1307 | rs6000_spe_abi = 0; |
78f5898b | 1308 | if (!rs6000_explicit_options.spe) |
5da702b1 | 1309 | rs6000_spe = 0; |
78f5898b | 1310 | if (!rs6000_explicit_options.float_gprs) |
5da702b1 | 1311 | rs6000_float_gprs = 0; |
78f5898b | 1312 | if (!rs6000_explicit_options.isel) |
5da702b1 | 1313 | rs6000_isel = 0; |
78f5898b | 1314 | if (!rs6000_explicit_options.long_double) |
c1e55850 | 1315 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
5da702b1 | 1316 | } |
b5044283 | 1317 | |
ec507f2d DE |
1318 | rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 |
1319 | && rs6000_cpu != PROCESSOR_POWER5); | |
1320 | rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 | |
1321 | || rs6000_cpu == PROCESSOR_POWER5); | |
1322 | ||
ec507f2d DE |
1323 | rs6000_sched_restricted_insns_priority |
1324 | = (rs6000_sched_groups ? 1 : 0); | |
79ae11c4 | 1325 | |
569fa502 | 1326 | /* Handle -msched-costly-dep option. */ |
ec507f2d DE |
1327 | rs6000_sched_costly_dep |
1328 | = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); | |
432218ba | 1329 | |
569fa502 DN |
1330 | if (rs6000_sched_costly_dep_str) |
1331 | { | |
f676971a | 1332 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) |
c4ad648e | 1333 | rs6000_sched_costly_dep = no_dep_costly; |
569fa502 | 1334 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) |
c4ad648e | 1335 | rs6000_sched_costly_dep = all_deps_costly; |
569fa502 | 1336 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) |
c4ad648e | 1337 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; |
569fa502 | 1338 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) |
c4ad648e | 1339 | rs6000_sched_costly_dep = store_to_load_dep_costly; |
f676971a | 1340 | else |
c4ad648e | 1341 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); |
cbe26ab8 DN |
1342 | } |
1343 | ||
1344 | /* Handle -minsert-sched-nops option. */ | |
ec507f2d DE |
1345 | rs6000_sched_insert_nops |
1346 | = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); | |
432218ba | 1347 | |
cbe26ab8 DN |
1348 | if (rs6000_sched_insert_nops_str) |
1349 | { | |
1350 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
c4ad648e | 1351 | rs6000_sched_insert_nops = sched_finish_none; |
cbe26ab8 | 1352 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) |
c4ad648e | 1353 | rs6000_sched_insert_nops = sched_finish_pad_groups; |
cbe26ab8 | 1354 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) |
c4ad648e | 1355 | rs6000_sched_insert_nops = sched_finish_regroup_exact; |
cbe26ab8 | 1356 | else |
c4ad648e | 1357 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); |
569fa502 DN |
1358 | } |
1359 | ||
c81bebd7 | 1360 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
1361 | /* If the user desires alternate register names, copy in the |
1362 | alternate names now. */ | |
c81bebd7 | 1363 | if (TARGET_REGNAMES) |
4e135bdd | 1364 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
1365 | #endif |
1366 | ||
df01da37 | 1367 | /* Set aix_struct_return last, after the ABI is determined. |
6fa3f289 ZW |
1368 | If -maix-struct-return or -msvr4-struct-return was explicitly |
1369 | used, don't override with the ABI default. */ | |
df01da37 DE |
1370 | if (!rs6000_explicit_options.aix_struct_ret) |
1371 | aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET); | |
6fa3f289 | 1372 | |
fcce224d DE |
1373 | if (TARGET_LONG_DOUBLE_128 |
1374 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
70a01792 | 1375 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 1376 | |
9ebbca7d GK |
1377 | /* Allocate an alias set for register saves & restores from stack. */ |
1378 | rs6000_sr_alias_set = new_alias_set (); | |
1379 | ||
f676971a | 1380 | if (TARGET_TOC) |
9ebbca7d | 1381 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); |
71f123ca | 1382 | |
301d03af RS |
1383 | /* We can only guarantee the availability of DI pseudo-ops when |
1384 | assembling for 64-bit targets. */ | |
ae6c1efd | 1385 | if (!TARGET_64BIT) |
301d03af RS |
1386 | { |
1387 | targetm.asm_out.aligned_op.di = NULL; | |
1388 | targetm.asm_out.unaligned_op.di = NULL; | |
1389 | } | |
1390 | ||
1494c534 DE |
1391 | /* Set branch target alignment, if not optimizing for size. */ |
1392 | if (!optimize_size) | |
1393 | { | |
1394 | if (rs6000_sched_groups) | |
1395 | { | |
1396 | if (align_functions <= 0) | |
1397 | align_functions = 16; | |
1398 | if (align_jumps <= 0) | |
1399 | align_jumps = 16; | |
1400 | if (align_loops <= 0) | |
1401 | align_loops = 16; | |
1402 | } | |
1403 | if (align_jumps_max_skip <= 0) | |
1404 | align_jumps_max_skip = 15; | |
1405 | if (align_loops_max_skip <= 0) | |
1406 | align_loops_max_skip = 15; | |
1407 | } | |
2792d578 | 1408 | |
71f123ca FS |
1409 | /* Arrange to save and restore machine status around nested functions. */ |
1410 | init_machine_status = rs6000_init_machine_status; | |
42ba5130 RH |
1411 | |
1412 | /* We should always be splitting complex arguments, but we can't break | |
1413 | Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ | |
18f63bfa | 1414 | if (DEFAULT_ABI != ABI_AIX) |
42ba5130 | 1415 | targetm.calls.split_complex_arg = NULL; |
8b897cfa RS |
1416 | |
1417 | /* Initialize rs6000_cost with the appropriate target costs. */ | |
1418 | if (optimize_size) | |
1419 | rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; | |
1420 | else | |
1421 | switch (rs6000_cpu) | |
1422 | { | |
1423 | case PROCESSOR_RIOS1: | |
1424 | rs6000_cost = &rios1_cost; | |
1425 | break; | |
1426 | ||
1427 | case PROCESSOR_RIOS2: | |
1428 | rs6000_cost = &rios2_cost; | |
1429 | break; | |
1430 | ||
1431 | case PROCESSOR_RS64A: | |
1432 | rs6000_cost = &rs64a_cost; | |
1433 | break; | |
1434 | ||
1435 | case PROCESSOR_MPCCORE: | |
1436 | rs6000_cost = &mpccore_cost; | |
1437 | break; | |
1438 | ||
1439 | case PROCESSOR_PPC403: | |
1440 | rs6000_cost = &ppc403_cost; | |
1441 | break; | |
1442 | ||
1443 | case PROCESSOR_PPC405: | |
1444 | rs6000_cost = &ppc405_cost; | |
1445 | break; | |
1446 | ||
1447 | case PROCESSOR_PPC440: | |
1448 | rs6000_cost = &ppc440_cost; | |
1449 | break; | |
1450 | ||
1451 | case PROCESSOR_PPC601: | |
1452 | rs6000_cost = &ppc601_cost; | |
1453 | break; | |
1454 | ||
1455 | case PROCESSOR_PPC603: | |
1456 | rs6000_cost = &ppc603_cost; | |
1457 | break; | |
1458 | ||
1459 | case PROCESSOR_PPC604: | |
1460 | rs6000_cost = &ppc604_cost; | |
1461 | break; | |
1462 | ||
1463 | case PROCESSOR_PPC604e: | |
1464 | rs6000_cost = &ppc604e_cost; | |
1465 | break; | |
1466 | ||
1467 | case PROCESSOR_PPC620: | |
8b897cfa RS |
1468 | rs6000_cost = &ppc620_cost; |
1469 | break; | |
1470 | ||
f0517163 RS |
1471 | case PROCESSOR_PPC630: |
1472 | rs6000_cost = &ppc630_cost; | |
1473 | break; | |
1474 | ||
8b897cfa RS |
1475 | case PROCESSOR_PPC750: |
1476 | case PROCESSOR_PPC7400: | |
1477 | rs6000_cost = &ppc750_cost; | |
1478 | break; | |
1479 | ||
1480 | case PROCESSOR_PPC7450: | |
1481 | rs6000_cost = &ppc7450_cost; | |
1482 | break; | |
1483 | ||
1484 | case PROCESSOR_PPC8540: | |
1485 | rs6000_cost = &ppc8540_cost; | |
1486 | break; | |
1487 | ||
1488 | case PROCESSOR_POWER4: | |
1489 | case PROCESSOR_POWER5: | |
1490 | rs6000_cost = &power4_cost; | |
1491 | break; | |
1492 | ||
1493 | default: | |
37409796 | 1494 | gcc_unreachable (); |
8b897cfa | 1495 | } |
5248c961 | 1496 | } |
5accd822 | 1497 | |
7ccf35ed DN |
1498 | /* Implement targetm.vectorize.builtin_mask_for_load. */ |
1499 | static tree | |
1500 | rs6000_builtin_mask_for_load (void) | |
1501 | { | |
1502 | if (TARGET_ALTIVEC) | |
1503 | return altivec_builtin_mask_for_load; | |
1504 | else | |
1505 | return 0; | |
1506 | } | |
1507 | ||
5da702b1 AH |
1508 | /* Handle generic options of the form -mfoo=yes/no. |
1509 | NAME is the option name. | |
1510 | VALUE is the option value. | |
1511 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
1512 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 1513 | static void |
5da702b1 | 1514 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 1515 | { |
5da702b1 | 1516 | if (value == 0) |
993f19a8 | 1517 | return; |
5da702b1 AH |
1518 | else if (!strcmp (value, "yes")) |
1519 | *flag = 1; | |
1520 | else if (!strcmp (value, "no")) | |
1521 | *flag = 0; | |
08b57fb3 | 1522 | else |
5da702b1 | 1523 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
1524 | } |
1525 | ||
c4501e62 JJ |
1526 | /* Validate and record the size specified with the -mtls-size option. */ |
1527 | ||
1528 | static void | |
863d938c | 1529 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
1530 | { |
1531 | if (rs6000_tls_size_string == 0) | |
1532 | return; | |
1533 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
1534 | rs6000_tls_size = 16; | |
1535 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
1536 | rs6000_tls_size = 32; | |
1537 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
1538 | rs6000_tls_size = 64; | |
1539 | else | |
9e637a26 | 1540 | error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string); |
c4501e62 JJ |
1541 | } |
1542 | ||
5accd822 | 1543 | void |
a2369ed3 | 1544 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 1545 | { |
2e3f0db6 DJ |
1546 | if (DEFAULT_ABI == ABI_DARWIN) |
1547 | /* The Darwin libraries never set errno, so we might as well | |
1548 | avoid calling them when that's the only reason we would. */ | |
1549 | flag_errno_math = 0; | |
5accd822 | 1550 | } |
78f5898b AH |
1551 | |
1552 | /* Implement TARGET_HANDLE_OPTION. */ | |
1553 | ||
1554 | static bool | |
1555 | rs6000_handle_option (size_t code, const char *arg, int value) | |
1556 | { | |
1557 | switch (code) | |
1558 | { | |
1559 | case OPT_mno_power: | |
1560 | target_flags &= ~(MASK_POWER | MASK_POWER2 | |
1561 | | MASK_MULTIPLE | MASK_STRING); | |
c2dba4ab AH |
1562 | target_flags_explicit |= (MASK_POWER | MASK_POWER2 |
1563 | | MASK_MULTIPLE | MASK_STRING); | |
78f5898b AH |
1564 | break; |
1565 | case OPT_mno_powerpc: | |
1566 | target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT | |
1567 | | MASK_PPC_GFXOPT | MASK_POWERPC64); | |
c2dba4ab AH |
1568 | target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT |
1569 | | MASK_PPC_GFXOPT | MASK_POWERPC64); | |
78f5898b AH |
1570 | break; |
1571 | case OPT_mfull_toc: | |
1572 | target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC | |
1573 | | MASK_NO_SUM_IN_TOC); | |
c2dba4ab AH |
1574 | target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC |
1575 | | MASK_NO_SUM_IN_TOC); | |
78f5898b AH |
1576 | #ifdef TARGET_USES_SYSV4_OPT |
1577 | /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be | |
1578 | just the same as -mminimal-toc. */ | |
1579 | target_flags |= MASK_MINIMAL_TOC; | |
c2dba4ab | 1580 | target_flags_explicit |= MASK_MINIMAL_TOC; |
78f5898b AH |
1581 | #endif |
1582 | break; | |
1583 | ||
1584 | #ifdef TARGET_USES_SYSV4_OPT | |
1585 | case OPT_mtoc: | |
1586 | /* Make -mtoc behave like -mminimal-toc. */ | |
1587 | target_flags |= MASK_MINIMAL_TOC; | |
c2dba4ab | 1588 | target_flags_explicit |= MASK_MINIMAL_TOC; |
78f5898b AH |
1589 | break; |
1590 | #endif | |
1591 | ||
1592 | #ifdef TARGET_USES_AIX64_OPT | |
1593 | case OPT_maix64: | |
1594 | #else | |
1595 | case OPT_m64: | |
1596 | #endif | |
1597 | target_flags |= MASK_POWERPC64 | MASK_POWERPC | MASK_PPC_GFXOPT; | |
c2dba4ab AH |
1598 | target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC |
1599 | | MASK_PPC_GFXOPT; | |
78f5898b AH |
1600 | break; |
1601 | ||
1602 | #ifdef TARGET_USES_AIX64_OPT | |
1603 | case OPT_maix32: | |
1604 | #else | |
1605 | case OPT_m32: | |
1606 | #endif | |
1607 | target_flags &= ~MASK_POWERPC64; | |
c2dba4ab | 1608 | target_flags_explicit |= MASK_POWERPC64; |
78f5898b AH |
1609 | break; |
1610 | ||
1611 | case OPT_minsert_sched_nops_: | |
1612 | rs6000_sched_insert_nops_str = arg; | |
1613 | break; | |
1614 | ||
1615 | case OPT_mminimal_toc: | |
1616 | if (value == 1) | |
1617 | { | |
c2dba4ab AH |
1618 | target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC); |
1619 | target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC); | |
78f5898b AH |
1620 | } |
1621 | break; | |
1622 | ||
1623 | case OPT_mpower: | |
1624 | if (value == 1) | |
c2dba4ab AH |
1625 | { |
1626 | target_flags |= (MASK_MULTIPLE | MASK_STRING); | |
1627 | target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING); | |
1628 | } | |
78f5898b AH |
1629 | break; |
1630 | ||
1631 | case OPT_mpower2: | |
1632 | if (value == 1) | |
c2dba4ab AH |
1633 | { |
1634 | target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING); | |
1635 | target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING); | |
1636 | } | |
78f5898b AH |
1637 | break; |
1638 | ||
1639 | case OPT_mpowerpc_gpopt: | |
1640 | case OPT_mpowerpc_gfxopt: | |
1641 | if (value == 1) | |
c2dba4ab AH |
1642 | { |
1643 | target_flags |= MASK_POWERPC; | |
1644 | target_flags_explicit |= MASK_POWERPC; | |
1645 | } | |
78f5898b AH |
1646 | break; |
1647 | ||
df01da37 DE |
1648 | case OPT_maix_struct_return: |
1649 | case OPT_msvr4_struct_return: | |
1650 | rs6000_explicit_options.aix_struct_ret = true; | |
1651 | break; | |
1652 | ||
78f5898b AH |
1653 | case OPT_mvrsave_: |
1654 | rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE)); | |
1655 | break; | |
78f5898b AH |
1656 | |
1657 | case OPT_misel_: | |
1658 | rs6000_explicit_options.isel = true; | |
1659 | rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel)); | |
1660 | break; | |
1661 | ||
1662 | case OPT_mspe_: | |
1663 | rs6000_explicit_options.spe = true; | |
1664 | rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe)); | |
1665 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
1666 | if (!rs6000_spe) | |
1667 | rs6000_long_double_type_size = 64; | |
1668 | break; | |
1669 | ||
1670 | case OPT_mdebug_: | |
1671 | rs6000_debug_name = arg; | |
1672 | break; | |
1673 | ||
1674 | #ifdef TARGET_USES_SYSV4_OPT | |
1675 | case OPT_mcall_: | |
1676 | rs6000_abi_name = arg; | |
1677 | break; | |
1678 | ||
1679 | case OPT_msdata_: | |
1680 | rs6000_sdata_name = arg; | |
1681 | break; | |
1682 | ||
1683 | case OPT_mtls_size_: | |
1684 | rs6000_tls_size_string = arg; | |
1685 | break; | |
1686 | ||
1687 | case OPT_mrelocatable: | |
1688 | if (value == 1) | |
c2dba4ab AH |
1689 | { |
1690 | target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC; | |
1691 | target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC; | |
1692 | } | |
78f5898b AH |
1693 | break; |
1694 | ||
1695 | case OPT_mrelocatable_lib: | |
1696 | if (value == 1) | |
c2dba4ab AH |
1697 | { |
1698 | target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC | |
1699 | | MASK_NO_FP_IN_TOC; | |
1700 | target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC | |
1701 | | MASK_NO_FP_IN_TOC; | |
1702 | } | |
78f5898b | 1703 | else |
c2dba4ab AH |
1704 | { |
1705 | target_flags &= ~MASK_RELOCATABLE; | |
1706 | target_flags_explicit |= MASK_RELOCATABLE; | |
1707 | } | |
78f5898b AH |
1708 | break; |
1709 | #endif | |
1710 | ||
1711 | case OPT_mabi_: | |
1712 | rs6000_explicit_options.abi = true; | |
1713 | if (!strcmp (arg, "altivec")) | |
1714 | { | |
1715 | rs6000_altivec_abi = 1; | |
1716 | rs6000_spe_abi = 0; | |
1717 | } | |
1718 | else if (! strcmp (arg, "no-altivec")) | |
1719 | rs6000_altivec_abi = 0; | |
1720 | else if (! strcmp (arg, "spe")) | |
1721 | { | |
1722 | rs6000_spe_abi = 1; | |
1723 | rs6000_altivec_abi = 0; | |
1724 | if (!TARGET_SPE_ABI) | |
1725 | error ("not configured for ABI: '%s'", arg); | |
1726 | } | |
1727 | else if (! strcmp (arg, "no-spe")) | |
1728 | rs6000_spe_abi = 0; | |
1729 | ||
1730 | /* These are here for testing during development only, do not | |
1731 | document in the manual please. */ | |
1732 | else if (! strcmp (arg, "d64")) | |
1733 | { | |
1734 | rs6000_darwin64_abi = 1; | |
1735 | warning (0, "Using darwin64 ABI"); | |
1736 | } | |
1737 | else if (! strcmp (arg, "d32")) | |
1738 | { | |
1739 | rs6000_darwin64_abi = 0; | |
1740 | warning (0, "Using old darwin ABI"); | |
1741 | } | |
1742 | ||
1743 | else | |
1744 | { | |
1745 | error ("unknown ABI specified: '%s'", arg); | |
1746 | return false; | |
1747 | } | |
1748 | break; | |
1749 | ||
1750 | case OPT_mcpu_: | |
1751 | rs6000_select[1].string = arg; | |
1752 | break; | |
1753 | ||
1754 | case OPT_mtune_: | |
1755 | rs6000_select[2].string = arg; | |
1756 | break; | |
1757 | ||
1758 | case OPT_mtraceback_: | |
1759 | rs6000_traceback_name = arg; | |
1760 | break; | |
1761 | ||
1762 | case OPT_mfloat_gprs_: | |
1763 | rs6000_explicit_options.float_gprs = true; | |
1764 | if (! strcmp (arg, "yes") || ! strcmp (arg, "single")) | |
1765 | rs6000_float_gprs = 1; | |
1766 | else if (! strcmp (arg, "double")) | |
1767 | rs6000_float_gprs = 2; | |
1768 | else if (! strcmp (arg, "no")) | |
1769 | rs6000_float_gprs = 0; | |
1770 | else | |
1771 | { | |
1772 | error ("invalid option for -mfloat-gprs: '%s'", arg); | |
1773 | return false; | |
1774 | } | |
1775 | break; | |
1776 | ||
1777 | case OPT_mlong_double_: | |
1778 | rs6000_explicit_options.long_double = true; | |
1779 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; | |
1780 | if (value != 64 && value != 128) | |
1781 | { | |
1782 | error ("Unknown switch -mlong-double-%s", arg); | |
1783 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; | |
1784 | return false; | |
1785 | } | |
1786 | else | |
1787 | rs6000_long_double_type_size = value; | |
1788 | break; | |
1789 | ||
1790 | case OPT_msched_costly_dep_: | |
1791 | rs6000_sched_costly_dep_str = arg; | |
1792 | break; | |
1793 | ||
1794 | case OPT_malign_: | |
1795 | rs6000_explicit_options.alignment = true; | |
1796 | if (! strcmp (arg, "power")) | |
1797 | { | |
1798 | /* On 64-bit Darwin, power alignment is ABI-incompatible with | |
1799 | some C library functions, so warn about it. The flag may be | |
1800 | useful for performance studies from time to time though, so | |
1801 | don't disable it entirely. */ | |
1802 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
1803 | warning (0, "-malign-power is not supported for 64-bit Darwin;" | |
1804 | " it is incompatible with the installed C and C++ libraries"); | |
1805 | rs6000_alignment_flags = MASK_ALIGN_POWER; | |
1806 | } | |
1807 | else if (! strcmp (arg, "natural")) | |
1808 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
1809 | else | |
1810 | { | |
1811 | error ("unknown -malign-XXXXX option specified: '%s'", arg); | |
1812 | return false; | |
1813 | } | |
1814 | break; | |
1815 | } | |
1816 | return true; | |
1817 | } | |
3cfa4909 MM |
1818 | \f |
1819 | /* Do anything needed at the start of the asm file. */ | |
1820 | ||
1bc7c5b6 | 1821 | static void |
863d938c | 1822 | rs6000_file_start (void) |
3cfa4909 | 1823 | { |
c4d38ccb | 1824 | size_t i; |
3cfa4909 | 1825 | char buffer[80]; |
d330fd93 | 1826 | const char *start = buffer; |
3cfa4909 | 1827 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
1828 | const char *default_cpu = TARGET_CPU_DEFAULT; |
1829 | FILE *file = asm_out_file; | |
1830 | ||
1831 | default_file_start (); | |
1832 | ||
1833 | #ifdef TARGET_BI_ARCH | |
1834 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
1835 | default_cpu = 0; | |
1836 | #endif | |
3cfa4909 MM |
1837 | |
1838 | if (flag_verbose_asm) | |
1839 | { | |
1840 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
1841 | rs6000_select[0].string = default_cpu; | |
1842 | ||
b6a1cbae | 1843 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
1844 | { |
1845 | ptr = &rs6000_select[i]; | |
1846 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
1847 | { | |
1848 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
1849 | start = ""; | |
1850 | } | |
1851 | } | |
1852 | ||
9c6b4ed9 | 1853 | if (PPC405_ERRATUM77) |
b0bfee6e | 1854 | { |
9c6b4ed9 | 1855 | fprintf (file, "%s PPC405CR_ERRATUM77", start); |
b0bfee6e DE |
1856 | start = ""; |
1857 | } | |
b0bfee6e | 1858 | |
b91da81f | 1859 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
1860 | switch (rs6000_sdata) |
1861 | { | |
1862 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
1863 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
1864 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
1865 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
1866 | } | |
1867 | ||
1868 | if (rs6000_sdata && g_switch_value) | |
1869 | { | |
307b599c MK |
1870 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
1871 | g_switch_value); | |
3cfa4909 MM |
1872 | start = ""; |
1873 | } | |
1874 | #endif | |
1875 | ||
1876 | if (*start == '\0') | |
949ea356 | 1877 | putc ('\n', file); |
3cfa4909 | 1878 | } |
b723e82f JJ |
1879 | |
1880 | if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2)) | |
1881 | { | |
1882 | toc_section (); | |
1883 | text_section (); | |
1884 | } | |
3cfa4909 | 1885 | } |
c4e18b1c | 1886 | |
5248c961 | 1887 | \f |
a0ab749a | 1888 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1889 | |
1890 | int | |
863d938c | 1891 | direct_return (void) |
9878760c | 1892 | { |
4697a36c MM |
1893 | if (reload_completed) |
1894 | { | |
1895 | rs6000_stack_t *info = rs6000_stack_info (); | |
1896 | ||
1897 | if (info->first_gp_reg_save == 32 | |
1898 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1899 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1900 | && ! info->lr_save_p |
1901 | && ! info->cr_save_p | |
00b960c7 | 1902 | && info->vrsave_mask == 0 |
c81fc13e | 1903 | && ! info->push_p) |
4697a36c MM |
1904 | return 1; |
1905 | } | |
1906 | ||
1907 | return 0; | |
9878760c RK |
1908 | } |
1909 | ||
4e74d8ec MM |
1910 | /* Return the number of instructions it takes to form a constant in an |
1911 | integer register. */ | |
1912 | ||
48d72335 | 1913 | int |
a2369ed3 | 1914 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
1915 | { |
1916 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1917 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1918 | return 1; |
1919 | ||
4e74d8ec | 1920 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1921 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1922 | return 1; |
1923 | ||
5f59ecb7 | 1924 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1925 | else if (TARGET_POWERPC64) |
4e74d8ec | 1926 | { |
a65c591c DE |
1927 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1928 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 1929 | |
a65c591c | 1930 | if (high == 0 || high == -1) |
4e74d8ec MM |
1931 | return 2; |
1932 | ||
a65c591c | 1933 | high >>= 1; |
4e74d8ec | 1934 | |
a65c591c | 1935 | if (low == 0) |
4e74d8ec | 1936 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
1937 | else |
1938 | return (num_insns_constant_wide (high) | |
e396202a | 1939 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1940 | } |
1941 | #endif | |
1942 | ||
1943 | else | |
1944 | return 2; | |
1945 | } | |
1946 | ||
1947 | int | |
a2369ed3 | 1948 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 1949 | { |
37409796 NS |
1950 | HOST_WIDE_INT low, high; |
1951 | ||
1952 | switch (GET_CODE (op)) | |
0d30d435 | 1953 | { |
37409796 | 1954 | case CONST_INT: |
0d30d435 | 1955 | #if HOST_BITS_PER_WIDE_INT == 64 |
4e2c1c44 | 1956 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
4ae234b0 | 1957 | && mask_operand (op, mode)) |
c4ad648e | 1958 | return 2; |
0d30d435 DE |
1959 | else |
1960 | #endif | |
1961 | return num_insns_constant_wide (INTVAL (op)); | |
4e74d8ec | 1962 | |
37409796 NS |
1963 | case CONST_DOUBLE: |
1964 | if (mode == SFmode) | |
1965 | { | |
1966 | long l; | |
1967 | REAL_VALUE_TYPE rv; | |
1968 | ||
1969 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1970 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
1971 | return num_insns_constant_wide ((HOST_WIDE_INT) l); | |
1972 | } | |
a260abc9 | 1973 | |
37409796 NS |
1974 | if (mode == VOIDmode || mode == DImode) |
1975 | { | |
1976 | high = CONST_DOUBLE_HIGH (op); | |
1977 | low = CONST_DOUBLE_LOW (op); | |
1978 | } | |
1979 | else | |
1980 | { | |
1981 | long l[2]; | |
1982 | REAL_VALUE_TYPE rv; | |
1983 | ||
1984 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1985 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1986 | high = l[WORDS_BIG_ENDIAN == 0]; | |
1987 | low = l[WORDS_BIG_ENDIAN != 0]; | |
1988 | } | |
47ad8c61 | 1989 | |
37409796 NS |
1990 | if (TARGET_32BIT) |
1991 | return (num_insns_constant_wide (low) | |
1992 | + num_insns_constant_wide (high)); | |
1993 | else | |
1994 | { | |
1995 | if ((high == 0 && low >= 0) | |
1996 | || (high == -1 && low < 0)) | |
1997 | return num_insns_constant_wide (low); | |
1998 | ||
4ae234b0 | 1999 | else if (mask_operand (op, mode)) |
37409796 NS |
2000 | return 2; |
2001 | ||
2002 | else if (low == 0) | |
2003 | return num_insns_constant_wide (high) + 1; | |
2004 | ||
2005 | else | |
2006 | return (num_insns_constant_wide (high) | |
2007 | + num_insns_constant_wide (low) + 1); | |
2008 | } | |
2009 | ||
2010 | default: | |
2011 | gcc_unreachable (); | |
4e74d8ec | 2012 | } |
4e74d8ec MM |
2013 | } |
2014 | ||
effa5d5d | 2015 | /* Returns the constant for the splat instruction, if exists. */ |
452a7d36 | 2016 | |
48d72335 | 2017 | int |
452a7d36 HP |
2018 | easy_vector_splat_const (int cst, enum machine_mode mode) |
2019 | { | |
f676971a | 2020 | switch (mode) |
452a7d36 HP |
2021 | { |
2022 | case V4SImode: | |
f676971a EC |
2023 | if (EASY_VECTOR_15 (cst) |
2024 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
2025 | return cst; |
2026 | if ((cst & 0xffff) != ((cst >> 16) & 0xffff)) | |
2027 | break; | |
2028 | cst = cst >> 16; | |
c4ad648e AM |
2029 | /* Fall thru */ |
2030 | ||
452a7d36 | 2031 | case V8HImode: |
f676971a EC |
2032 | if (EASY_VECTOR_15 (cst) |
2033 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
2034 | return cst; |
2035 | if ((cst & 0xff) != ((cst >> 8) & 0xff)) | |
2036 | break; | |
2037 | cst = cst >> 8; | |
c4ad648e AM |
2038 | /* Fall thru */ |
2039 | ||
452a7d36 | 2040 | case V16QImode: |
c4ad648e AM |
2041 | if (EASY_VECTOR_15 (cst) |
2042 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
2043 | return cst; | |
f676971a | 2044 | default: |
452a7d36 HP |
2045 | break; |
2046 | } | |
2047 | return 0; | |
2048 | } | |
2049 | ||
72ac76be | 2050 | /* Return nonzero if all elements of a vector have the same value. */ |
69ef87e2 | 2051 | |
48d72335 | 2052 | int |
a2369ed3 | 2053 | easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d744e06e AH |
2054 | { |
2055 | int units, i, cst; | |
2056 | ||
2057 | units = CONST_VECTOR_NUNITS (op); | |
2058 | ||
2059 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
2060 | for (i = 1; i < units; ++i) | |
2061 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
2062 | break; | |
452a7d36 | 2063 | if (i == units && easy_vector_splat_const (cst, mode)) |
d744e06e AH |
2064 | return 1; |
2065 | return 0; | |
2066 | } | |
2067 | ||
452a7d36 | 2068 | /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */ |
d744e06e | 2069 | |
f676971a | 2070 | rtx |
452a7d36 HP |
2071 | gen_easy_vector_constant_add_self (rtx op) |
2072 | { | |
2073 | int i, units; | |
2074 | rtvec v; | |
2075 | units = GET_MODE_NUNITS (GET_MODE (op)); | |
2076 | v = rtvec_alloc (units); | |
2077 | ||
2078 | for (i = 0; i < units; i++) | |
f676971a | 2079 | RTVEC_ELT (v, i) = |
452a7d36 HP |
2080 | GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1); |
2081 | return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v); | |
d744e06e AH |
2082 | } |
2083 | ||
2084 | const char * | |
a2369ed3 | 2085 | output_vec_const_move (rtx *operands) |
d744e06e AH |
2086 | { |
2087 | int cst, cst2; | |
2088 | enum machine_mode mode; | |
2089 | rtx dest, vec; | |
2090 | ||
2091 | dest = operands[0]; | |
2092 | vec = operands[1]; | |
69ef87e2 | 2093 | |
d744e06e AH |
2094 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
2095 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
2096 | mode = GET_MODE (dest); | |
69ef87e2 | 2097 | |
d744e06e AH |
2098 | if (TARGET_ALTIVEC) |
2099 | { | |
2100 | if (zero_constant (vec, mode)) | |
2101 | return "vxor %0,%0,%0"; | |
37409796 NS |
2102 | |
2103 | gcc_assert (easy_vector_constant (vec, mode)); | |
2104 | ||
2105 | operands[1] = GEN_INT (cst); | |
2106 | switch (mode) | |
98ef3137 | 2107 | { |
37409796 NS |
2108 | case V4SImode: |
2109 | if (EASY_VECTOR_15 (cst)) | |
d744e06e | 2110 | { |
37409796 NS |
2111 | operands[1] = GEN_INT (cst); |
2112 | return "vspltisw %0,%1"; | |
2113 | } | |
2114 | else if (EASY_VECTOR_15_ADD_SELF (cst)) | |
2115 | return "#"; | |
2116 | cst = cst >> 16; | |
2117 | /* Fall thru */ | |
c4ad648e | 2118 | |
37409796 NS |
2119 | case V8HImode: |
2120 | if (EASY_VECTOR_15 (cst)) | |
2121 | { | |
2122 | operands[1] = GEN_INT (cst); | |
2123 | return "vspltish %0,%1"; | |
2124 | } | |
2125 | else if (EASY_VECTOR_15_ADD_SELF (cst)) | |
2126 | return "#"; | |
2127 | cst = cst >> 8; | |
2128 | /* Fall thru */ | |
c4ad648e | 2129 | |
37409796 NS |
2130 | case V16QImode: |
2131 | if (EASY_VECTOR_15 (cst)) | |
2132 | { | |
2133 | operands[1] = GEN_INT (cst); | |
2134 | return "vspltisb %0,%1"; | |
d744e06e | 2135 | } |
37409796 NS |
2136 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2137 | return "#"; | |
2138 | ||
2139 | default: | |
2140 | gcc_unreachable (); | |
98ef3137 | 2141 | } |
69ef87e2 AH |
2142 | } |
2143 | ||
37409796 NS |
2144 | gcc_assert (TARGET_SPE); |
2145 | ||
2146 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
2147 | pattern of V1DI, V4HI, and V2SF. | |
2148 | ||
2149 | FIXME: We should probably return # and add post reload | |
2150 | splitters for these, but this way is so easy ;-). */ | |
2151 | operands[1] = GEN_INT (cst); | |
2152 | operands[2] = GEN_INT (cst2); | |
2153 | if (cst == cst2) | |
2154 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
2155 | else | |
2156 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
69ef87e2 AH |
2157 | } |
2158 | ||
914c2e77 | 2159 | int |
e1e2e653 NS |
2160 | mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED, |
2161 | bool allow_one) | |
0ba1b2ff AM |
2162 | { |
2163 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 2164 | { |
0ba1b2ff | 2165 | HOST_WIDE_INT c, lsb; |
e1e2e653 NS |
2166 | bool one_ok; |
2167 | ||
0ba1b2ff | 2168 | c = INTVAL (op); |
a260abc9 | 2169 | |
0ba1b2ff AM |
2170 | /* Disallow all zeros. */ |
2171 | if (c == 0) | |
2172 | return 0; | |
a260abc9 | 2173 | |
e1e2e653 NS |
2174 | /* We can use a single rlwinm insn if no upper bits of C are set |
2175 | AND there are zero, one or two transitions in the _whole_ of | |
2176 | C. */ | |
2177 | one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff); | |
2178 | ||
0ba1b2ff AM |
2179 | /* We don't change the number of transitions by inverting, |
2180 | so make sure we start with the LS bit zero. */ | |
2181 | if (c & 1) | |
2182 | c = ~c; | |
a260abc9 | 2183 | |
0ba1b2ff AM |
2184 | /* Find the first transition. */ |
2185 | lsb = c & -c; | |
a260abc9 | 2186 | |
0ba1b2ff AM |
2187 | /* Invert to look for a second transition. */ |
2188 | c = ~c; | |
2189 | ||
2190 | /* Erase first transition. */ | |
2191 | c &= -lsb; | |
2192 | ||
2193 | /* Find the second transition. */ | |
2194 | lsb = c & -c; | |
2195 | ||
2196 | /* Invert to look for a third transition. */ | |
2197 | c = ~c; | |
2198 | ||
2199 | /* Erase second transition. */ | |
2200 | c &= -lsb; | |
2201 | ||
e1e2e653 NS |
2202 | if (one_ok && !(allow_one || c)) |
2203 | return 0; | |
2204 | ||
0ba1b2ff AM |
2205 | /* Find the third transition (if any). */ |
2206 | lsb = c & -c; | |
2207 | ||
2208 | /* Match if all the bits above are 1's (or c is zero). */ | |
2209 | return c == -lsb; | |
2210 | } | |
2211 | return 0; | |
2212 | } | |
2213 | ||
2214 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to | |
2215 | implement ANDing by the mask IN. */ | |
2216 | void | |
a2369ed3 | 2217 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
2218 | { |
2219 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2220 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2221 | int shift; | |
2222 | ||
37409796 | 2223 | gcc_assert (GET_CODE (in) == CONST_INT); |
0ba1b2ff AM |
2224 | |
2225 | c = INTVAL (in); | |
2226 | if (c & 1) | |
2227 | { | |
2228 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2229 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2230 | is at the MS end and can be cleared with an rldicl mask. We then | |
2231 | rotate back and clear off the MS ^^ group of zeros with a | |
2232 | second rldicl. */ | |
2233 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2234 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2235 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2236 | c = ~c; /* c == 0x00fff000000fffff */ | |
2237 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2238 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2239 | c = ~c; /* c == 0xff000fffffffffff */ | |
2240 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2241 | shift = 0; | |
2242 | while ((lsb >>= 1) != 0) | |
2243 | shift++; /* shift == 44 on exit from loop */ | |
2244 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2245 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2246 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2247 | } |
2248 | else | |
0ba1b2ff AM |
2249 | { |
2250 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2251 | is to rotate the word so that the ^^^ middle group of zeros | |
2252 | is at the LS end and can be cleared with an rldicr mask. We then | |
2253 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2254 | a second rldicr. */ | |
2255 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2256 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2257 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2258 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2259 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2260 | c = ~c; /* c == 0xff000fffffffffff */ | |
2261 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2262 | shift = 0; | |
2263 | while ((lsb >>= 1) != 0) | |
2264 | shift++; /* shift == 44 on exit from loop */ | |
2265 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2266 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2267 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2268 | } | |
2269 | ||
2270 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2271 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2272 | out[0] = GEN_INT (64 - shift); | |
2273 | out[1] = GEN_INT (m1); | |
2274 | out[2] = GEN_INT (shift); | |
2275 | out[3] = GEN_INT (m2); | |
2276 | #else | |
045572c7 GK |
2277 | (void)in; |
2278 | (void)out; | |
37409796 | 2279 | gcc_unreachable (); |
0ba1b2ff | 2280 | #endif |
a260abc9 DE |
2281 | } |
2282 | ||
54b695e7 | 2283 | /* Return TRUE if OP is an invalid SUBREG operation on the e500. */ |
48d72335 DE |
2284 | |
2285 | bool | |
54b695e7 AH |
2286 | invalid_e500_subreg (rtx op, enum machine_mode mode) |
2287 | { | |
2288 | /* Reject (subreg:SI (reg:DF)). */ | |
2289 | if (GET_CODE (op) == SUBREG | |
2290 | && mode == SImode | |
2291 | && REG_P (SUBREG_REG (op)) | |
2292 | && GET_MODE (SUBREG_REG (op)) == DFmode) | |
2293 | return true; | |
2294 | ||
2295 | /* Reject (subreg:DF (reg:DI)). */ | |
2296 | if (GET_CODE (op) == SUBREG | |
2297 | && mode == DFmode | |
2298 | && REG_P (SUBREG_REG (op)) | |
2299 | && GET_MODE (SUBREG_REG (op)) == DImode) | |
2300 | return true; | |
2301 | ||
2302 | return false; | |
2303 | } | |
2304 | ||
95727fb8 AP |
2305 | /* Darwin, AIX increases natural record alignment to doubleword if the first |
2306 | field is an FP double while the FP fields remain word aligned. */ | |
2307 | ||
19d66194 | 2308 | unsigned int |
95727fb8 AP |
2309 | rs6000_special_round_type_align (tree type, int computed, int specified) |
2310 | { | |
2311 | tree field = TYPE_FIELDS (type); | |
95727fb8 | 2312 | |
85962ac8 AP |
2313 | /* Skip all non field decls */ |
2314 | while (field != NULL && TREE_CODE (field) != FIELD_DECL) | |
95727fb8 AP |
2315 | field = TREE_CHAIN (field); |
2316 | ||
3ce5437a | 2317 | if (field == NULL || field == type || DECL_MODE (field) != DFmode) |
95727fb8 AP |
2318 | return MAX (computed, specified); |
2319 | ||
2320 | return MAX (MAX (computed, specified), 64); | |
2321 | } | |
2322 | ||
a4f6c312 | 2323 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
2324 | |
2325 | int | |
f676971a | 2326 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
a2369ed3 | 2327 | enum machine_mode mode ATTRIBUTE_UNUSED) |
7509c759 | 2328 | { |
38c1f2d7 | 2329 | #if TARGET_ELF |
5f59ecb7 | 2330 | rtx sym_ref; |
7509c759 | 2331 | |
d9407988 | 2332 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 2333 | return 0; |
a54d04b7 | 2334 | |
f607bc57 | 2335 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
2336 | return 0; |
2337 | ||
88228c4b MM |
2338 | if (GET_CODE (op) == SYMBOL_REF) |
2339 | sym_ref = op; | |
2340 | ||
2341 | else if (GET_CODE (op) != CONST | |
2342 | || GET_CODE (XEXP (op, 0)) != PLUS | |
2343 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
2344 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
2345 | return 0; |
2346 | ||
88228c4b | 2347 | else |
dbf55e53 MM |
2348 | { |
2349 | rtx sum = XEXP (op, 0); | |
2350 | HOST_WIDE_INT summand; | |
2351 | ||
2352 | /* We have to be careful here, because it is the referenced address | |
c4ad648e | 2353 | that must be 32k from _SDA_BASE_, not just the symbol. */ |
dbf55e53 | 2354 | summand = INTVAL (XEXP (sum, 1)); |
307b599c | 2355 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
9390387d | 2356 | return 0; |
dbf55e53 MM |
2357 | |
2358 | sym_ref = XEXP (sum, 0); | |
2359 | } | |
88228c4b | 2360 | |
20bfcd69 | 2361 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
2362 | #else |
2363 | return 0; | |
2364 | #endif | |
7509c759 | 2365 | } |
46c07df8 | 2366 | |
3a1f863f | 2367 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 2368 | |
3a1f863f DE |
2369 | bool |
2370 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 2371 | { |
3a1f863f DE |
2372 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
2373 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
2374 | } |
2375 | ||
9ebbca7d | 2376 | \f |
4d588c14 RH |
2377 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
2378 | ||
f676971a EC |
2379 | static int |
2380 | constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) | |
9ebbca7d | 2381 | { |
9390387d | 2382 | switch (GET_CODE (op)) |
9ebbca7d GK |
2383 | { |
2384 | case SYMBOL_REF: | |
c4501e62 JJ |
2385 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
2386 | return 0; | |
2387 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
2388 | { |
2389 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
2390 | { | |
2391 | *have_sym = 1; | |
2392 | return 1; | |
2393 | } | |
2394 | else | |
2395 | return 0; | |
2396 | } | |
2397 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
2398 | { | |
2399 | *have_toc = 1; | |
2400 | return 1; | |
2401 | } | |
2402 | else | |
2403 | return 0; | |
9ebbca7d GK |
2404 | case PLUS: |
2405 | case MINUS: | |
c1f11548 DE |
2406 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
2407 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 2408 | case CONST: |
a4f6c312 | 2409 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 2410 | case CONST_INT: |
a4f6c312 | 2411 | return 1; |
9ebbca7d | 2412 | default: |
a4f6c312 | 2413 | return 0; |
9ebbca7d GK |
2414 | } |
2415 | } | |
2416 | ||
4d588c14 | 2417 | static bool |
a2369ed3 | 2418 | constant_pool_expr_p (rtx op) |
9ebbca7d GK |
2419 | { |
2420 | int have_sym = 0; | |
2421 | int have_toc = 0; | |
2422 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
2423 | } | |
2424 | ||
48d72335 | 2425 | bool |
a2369ed3 | 2426 | toc_relative_expr_p (rtx op) |
9ebbca7d | 2427 | { |
4d588c14 RH |
2428 | int have_sym = 0; |
2429 | int have_toc = 0; | |
2430 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
2431 | } | |
2432 | ||
4d588c14 | 2433 | bool |
a2369ed3 | 2434 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
2435 | { |
2436 | return (TARGET_TOC | |
2437 | && GET_CODE (x) == PLUS | |
2438 | && GET_CODE (XEXP (x, 0)) == REG | |
2439 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
2440 | && constant_pool_expr_p (XEXP (x, 1))); | |
2441 | } | |
2442 | ||
2443 | static bool | |
a2369ed3 | 2444 | legitimate_small_data_p (enum machine_mode mode, rtx x) |
4d588c14 RH |
2445 | { |
2446 | return (DEFAULT_ABI == ABI_V4 | |
2447 | && !flag_pic && !TARGET_TOC | |
2448 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
2449 | && small_data_operand (x, mode)); | |
2450 | } | |
2451 | ||
60cdabab DE |
2452 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
2453 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
2454 | ||
76d2b81d DJ |
2455 | bool |
2456 | rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) | |
4d588c14 RH |
2457 | { |
2458 | unsigned HOST_WIDE_INT offset, extra; | |
2459 | ||
2460 | if (GET_CODE (x) != PLUS) | |
2461 | return false; | |
2462 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2463 | return false; | |
2464 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2465 | return false; | |
60cdabab DE |
2466 | if (legitimate_constant_pool_address_p (x)) |
2467 | return true; | |
4d588c14 RH |
2468 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
2469 | return false; | |
2470 | ||
2471 | offset = INTVAL (XEXP (x, 1)); | |
2472 | extra = 0; | |
2473 | switch (mode) | |
2474 | { | |
2475 | case V16QImode: | |
2476 | case V8HImode: | |
2477 | case V4SFmode: | |
2478 | case V4SImode: | |
2479 | /* AltiVec vector modes. Only reg+reg addressing is valid here, | |
2480 | which leaves the only valid constant offset of zero, which by | |
2481 | canonicalization rules is also invalid. */ | |
2482 | return false; | |
2483 | ||
2484 | case V4HImode: | |
2485 | case V2SImode: | |
2486 | case V1DImode: | |
2487 | case V2SFmode: | |
2488 | /* SPE vector modes. */ | |
2489 | return SPE_CONST_OFFSET_OK (offset); | |
2490 | ||
2491 | case DFmode: | |
4d4cbc0e AH |
2492 | if (TARGET_E500_DOUBLE) |
2493 | return SPE_CONST_OFFSET_OK (offset); | |
2494 | ||
4d588c14 | 2495 | case DImode: |
54b695e7 AH |
2496 | /* On e500v2, we may have: |
2497 | ||
2498 | (subreg:DF (mem:DI (plus (reg) (const_int))) 0). | |
2499 | ||
2500 | Which gets addressed with evldd instructions. */ | |
2501 | if (TARGET_E500_DOUBLE) | |
2502 | return SPE_CONST_OFFSET_OK (offset); | |
2503 | ||
3364872d | 2504 | if (mode == DFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2505 | extra = 4; |
2506 | else if (offset & 3) | |
2507 | return false; | |
2508 | break; | |
2509 | ||
2510 | case TFmode: | |
2511 | case TImode: | |
3364872d | 2512 | if (mode == TFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2513 | extra = 12; |
2514 | else if (offset & 3) | |
2515 | return false; | |
2516 | else | |
2517 | extra = 8; | |
2518 | break; | |
2519 | ||
2520 | default: | |
2521 | break; | |
2522 | } | |
2523 | ||
b1917422 AM |
2524 | offset += 0x8000; |
2525 | return (offset < 0x10000) && (offset + extra < 0x10000); | |
4d588c14 RH |
2526 | } |
2527 | ||
2528 | static bool | |
a2369ed3 | 2529 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
2530 | { |
2531 | rtx op0, op1; | |
2532 | ||
2533 | if (GET_CODE (x) != PLUS) | |
2534 | return false; | |
850e8d3d | 2535 | |
4d588c14 RH |
2536 | op0 = XEXP (x, 0); |
2537 | op1 = XEXP (x, 1); | |
2538 | ||
2539 | if (!REG_P (op0) || !REG_P (op1)) | |
2540 | return false; | |
2541 | ||
2542 | return ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
2543 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
2544 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
2545 | && INT_REG_OK_FOR_INDEX_P (op0, strict))); | |
9ebbca7d GK |
2546 | } |
2547 | ||
48d72335 | 2548 | inline bool |
a2369ed3 | 2549 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
2550 | { |
2551 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
2552 | } | |
2553 | ||
48d72335 | 2554 | bool |
4c81e946 FJ |
2555 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) |
2556 | { | |
c4ad648e | 2557 | if (!TARGET_MACHO || !flag_pic |
9390387d | 2558 | || mode != SImode || GET_CODE (x) != MEM) |
c4ad648e AM |
2559 | return false; |
2560 | x = XEXP (x, 0); | |
4c81e946 FJ |
2561 | |
2562 | if (GET_CODE (x) != LO_SUM) | |
2563 | return false; | |
2564 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2565 | return false; | |
2566 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
2567 | return false; | |
2568 | x = XEXP (x, 1); | |
2569 | ||
2570 | return CONSTANT_P (x); | |
2571 | } | |
2572 | ||
4d588c14 | 2573 | static bool |
a2369ed3 | 2574 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
2575 | { |
2576 | if (GET_CODE (x) != LO_SUM) | |
2577 | return false; | |
2578 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2579 | return false; | |
2580 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2581 | return false; | |
54b695e7 AH |
2582 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
2583 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) | |
f82f556d | 2584 | return false; |
4d588c14 RH |
2585 | x = XEXP (x, 1); |
2586 | ||
8622e235 | 2587 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 2588 | { |
a29077da | 2589 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
2590 | return false; |
2591 | if (TARGET_TOC) | |
2592 | return false; | |
2593 | if (GET_MODE_NUNITS (mode) != 1) | |
2594 | return false; | |
5e5f01b9 | 2595 | if (GET_MODE_BITSIZE (mode) > 64 |
3c028f65 AM |
2596 | || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64 |
2597 | && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))) | |
4d588c14 RH |
2598 | return false; |
2599 | ||
2600 | return CONSTANT_P (x); | |
2601 | } | |
2602 | ||
2603 | return false; | |
2604 | } | |
2605 | ||
2606 | ||
9ebbca7d GK |
2607 | /* Try machine-dependent ways of modifying an illegitimate address |
2608 | to be legitimate. If we find one, return the new, valid address. | |
2609 | This is used from only one place: `memory_address' in explow.c. | |
2610 | ||
a4f6c312 SS |
2611 | OLDX is the address as it was before break_out_memory_refs was |
2612 | called. In some cases it is useful to look at this to decide what | |
2613 | needs to be done. | |
9ebbca7d | 2614 | |
a4f6c312 | 2615 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 2616 | |
a4f6c312 SS |
2617 | It is always safe for this function to do nothing. It exists to |
2618 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
2619 | |
2620 | On RS/6000, first check for the sum of a register with a constant | |
2621 | integer that is out of range. If so, generate code to add the | |
2622 | constant with the low-order 16 bits masked to the register and force | |
2623 | this result into another register (this can be done with `cau'). | |
2624 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
2625 | possibility of bit 16 being a one. | |
2626 | ||
2627 | Then check for the sum of a register and something not constant, try to | |
2628 | load the other things into a register and return the sum. */ | |
4d588c14 | 2629 | |
9ebbca7d | 2630 | rtx |
a2369ed3 DJ |
2631 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
2632 | enum machine_mode mode) | |
0ac081f6 | 2633 | { |
c4501e62 JJ |
2634 | if (GET_CODE (x) == SYMBOL_REF) |
2635 | { | |
2636 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
2637 | if (model != 0) | |
2638 | return rs6000_legitimize_tls_address (x, model); | |
2639 | } | |
2640 | ||
f676971a | 2641 | if (GET_CODE (x) == PLUS |
9ebbca7d GK |
2642 | && GET_CODE (XEXP (x, 0)) == REG |
2643 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2644 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
f676971a | 2645 | { |
9ebbca7d GK |
2646 | HOST_WIDE_INT high_int, low_int; |
2647 | rtx sum; | |
a65c591c DE |
2648 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
2649 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
2650 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
2651 | GEN_INT (high_int)), 0); | |
2652 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
2653 | } | |
f676971a | 2654 | else if (GET_CODE (x) == PLUS |
9ebbca7d GK |
2655 | && GET_CODE (XEXP (x, 0)) == REG |
2656 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 2657 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
2658 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
2659 | || TARGET_POWERPC64 | |
54b695e7 AH |
2660 | || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE) |
2661 | && mode != TFmode)) | |
9ebbca7d GK |
2662 | && (TARGET_POWERPC64 || mode != DImode) |
2663 | && mode != TImode) | |
2664 | { | |
2665 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
2666 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
2667 | } | |
0ac081f6 AH |
2668 | else if (ALTIVEC_VECTOR_MODE (mode)) |
2669 | { | |
2670 | rtx reg; | |
2671 | ||
2672 | /* Make sure both operands are registers. */ | |
2673 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 2674 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
2675 | force_reg (Pmode, XEXP (x, 1))); |
2676 | ||
2677 | reg = force_reg (Pmode, x); | |
2678 | return reg; | |
2679 | } | |
4d4cbc0e | 2680 | else if (SPE_VECTOR_MODE (mode) |
54b695e7 AH |
2681 | || (TARGET_E500_DOUBLE && (mode == DFmode |
2682 | || mode == DImode))) | |
a3170dc6 | 2683 | { |
54b695e7 AH |
2684 | if (mode == DImode) |
2685 | return NULL_RTX; | |
a3170dc6 AH |
2686 | /* We accept [reg + reg] and [reg + OFFSET]. */ |
2687 | ||
2688 | if (GET_CODE (x) == PLUS) | |
c4ad648e AM |
2689 | { |
2690 | rtx op1 = XEXP (x, 0); | |
2691 | rtx op2 = XEXP (x, 1); | |
a3170dc6 | 2692 | |
c4ad648e | 2693 | op1 = force_reg (Pmode, op1); |
a3170dc6 | 2694 | |
c4ad648e AM |
2695 | if (GET_CODE (op2) != REG |
2696 | && (GET_CODE (op2) != CONST_INT | |
2697 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
2698 | op2 = force_reg (Pmode, op2); | |
a3170dc6 | 2699 | |
c4ad648e AM |
2700 | return gen_rtx_PLUS (Pmode, op1, op2); |
2701 | } | |
a3170dc6 AH |
2702 | |
2703 | return force_reg (Pmode, x); | |
2704 | } | |
f1384257 AM |
2705 | else if (TARGET_ELF |
2706 | && TARGET_32BIT | |
2707 | && TARGET_NO_TOC | |
2708 | && ! flag_pic | |
9ebbca7d | 2709 | && GET_CODE (x) != CONST_INT |
f676971a | 2710 | && GET_CODE (x) != CONST_DOUBLE |
9ebbca7d | 2711 | && CONSTANT_P (x) |
6ac7bf2c GK |
2712 | && GET_MODE_NUNITS (mode) == 1 |
2713 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 2714 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
2715 | { |
2716 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2717 | emit_insn (gen_elf_high (reg, x)); |
2718 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 2719 | } |
ee890fe2 SS |
2720 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
2721 | && ! flag_pic | |
ab82a49f AP |
2722 | #if TARGET_MACHO |
2723 | && ! MACHO_DYNAMIC_NO_PIC_P | |
2724 | #endif | |
ee890fe2 | 2725 | && GET_CODE (x) != CONST_INT |
f676971a | 2726 | && GET_CODE (x) != CONST_DOUBLE |
ee890fe2 | 2727 | && CONSTANT_P (x) |
f82f556d | 2728 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
f676971a | 2729 | && mode != DImode |
ee890fe2 SS |
2730 | && mode != TImode) |
2731 | { | |
2732 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2733 | emit_insn (gen_macho_high (reg, x)); |
2734 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 2735 | } |
f676971a | 2736 | else if (TARGET_TOC |
4d588c14 | 2737 | && constant_pool_expr_p (x) |
a9098fd0 | 2738 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
2739 | { |
2740 | return create_TOC_reference (x); | |
2741 | } | |
2742 | else | |
2743 | return NULL_RTX; | |
2744 | } | |
258bfae2 | 2745 | |
fdbe66f2 | 2746 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
c973d557 JJ |
2747 | We need to emit DTP-relative relocations. */ |
2748 | ||
fdbe66f2 | 2749 | static void |
c973d557 JJ |
2750 | rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) |
2751 | { | |
2752 | switch (size) | |
2753 | { | |
2754 | case 4: | |
2755 | fputs ("\t.long\t", file); | |
2756 | break; | |
2757 | case 8: | |
2758 | fputs (DOUBLE_INT_ASM_OP, file); | |
2759 | break; | |
2760 | default: | |
37409796 | 2761 | gcc_unreachable (); |
c973d557 JJ |
2762 | } |
2763 | output_addr_const (file, x); | |
2764 | fputs ("@dtprel+0x8000", file); | |
2765 | } | |
2766 | ||
c4501e62 JJ |
2767 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
2768 | ||
2769 | static GTY(()) rtx rs6000_tls_symbol; | |
2770 | static rtx | |
863d938c | 2771 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
2772 | { |
2773 | if (!rs6000_tls_symbol) | |
2774 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
2775 | ||
2776 | return rs6000_tls_symbol; | |
2777 | } | |
2778 | ||
2779 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
2780 | ||
2781 | static GTY(()) rtx rs6000_got_symbol; | |
2782 | static rtx | |
863d938c | 2783 | rs6000_got_sym (void) |
c4501e62 JJ |
2784 | { |
2785 | if (!rs6000_got_symbol) | |
2786 | { | |
2787 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2788 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
2789 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
f676971a | 2790 | } |
c4501e62 JJ |
2791 | |
2792 | return rs6000_got_symbol; | |
2793 | } | |
2794 | ||
2795 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
2796 | this (thread-local) address. */ | |
2797 | ||
2798 | static rtx | |
a2369ed3 | 2799 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
2800 | { |
2801 | rtx dest, insn; | |
2802 | ||
2803 | dest = gen_reg_rtx (Pmode); | |
2804 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
2805 | { | |
2806 | rtx tlsreg; | |
2807 | ||
2808 | if (TARGET_64BIT) | |
2809 | { | |
2810 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2811 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
2812 | } | |
2813 | else | |
2814 | { | |
2815 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2816 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
2817 | } | |
2818 | emit_insn (insn); | |
2819 | } | |
2820 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
2821 | { | |
2822 | rtx tlsreg, tmp; | |
2823 | ||
2824 | tmp = gen_reg_rtx (Pmode); | |
2825 | if (TARGET_64BIT) | |
2826 | { | |
2827 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2828 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
2829 | } | |
2830 | else | |
2831 | { | |
2832 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2833 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
2834 | } | |
2835 | emit_insn (insn); | |
2836 | if (TARGET_64BIT) | |
2837 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
2838 | else | |
2839 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
2840 | emit_insn (insn); | |
2841 | } | |
2842 | else | |
2843 | { | |
2844 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
2845 | ||
2846 | if (TARGET_64BIT) | |
2847 | got = gen_rtx_REG (Pmode, TOC_REGISTER); | |
2848 | else | |
2849 | { | |
2850 | if (flag_pic == 1) | |
2851 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
2852 | else | |
2853 | { | |
2854 | rtx gsym = rs6000_got_sym (); | |
2855 | got = gen_reg_rtx (Pmode); | |
2856 | if (flag_pic == 0) | |
2857 | rs6000_emit_move (got, gsym, Pmode); | |
2858 | else | |
2859 | { | |
ccbca5e4 | 2860 | rtx tempLR, tmp3, mem; |
c4501e62 JJ |
2861 | rtx first, last; |
2862 | ||
c4501e62 JJ |
2863 | tempLR = gen_reg_rtx (Pmode); |
2864 | tmp1 = gen_reg_rtx (Pmode); | |
2865 | tmp2 = gen_reg_rtx (Pmode); | |
2866 | tmp3 = gen_reg_rtx (Pmode); | |
542a8afa | 2867 | mem = gen_const_mem (Pmode, tmp1); |
c4501e62 | 2868 | |
ccbca5e4 | 2869 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym)); |
c4501e62 JJ |
2870 | emit_move_insn (tmp1, tempLR); |
2871 | emit_move_insn (tmp2, mem); | |
2872 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
2873 | last = emit_move_insn (got, tmp3); | |
2874 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
2875 | REG_NOTES (last)); | |
2876 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
2877 | REG_NOTES (first)); | |
2878 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
2879 | REG_NOTES (last)); | |
2880 | } | |
2881 | } | |
2882 | } | |
2883 | ||
2884 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
2885 | { | |
2886 | r3 = gen_rtx_REG (Pmode, 3); | |
2887 | if (TARGET_64BIT) | |
2888 | insn = gen_tls_gd_64 (r3, got, addr); | |
2889 | else | |
2890 | insn = gen_tls_gd_32 (r3, got, addr); | |
2891 | start_sequence (); | |
2892 | emit_insn (insn); | |
2893 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2894 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2895 | insn = emit_call_insn (insn); | |
2896 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2897 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2898 | insn = get_insns (); | |
2899 | end_sequence (); | |
2900 | emit_libcall_block (insn, dest, r3, addr); | |
2901 | } | |
2902 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
2903 | { | |
2904 | r3 = gen_rtx_REG (Pmode, 3); | |
2905 | if (TARGET_64BIT) | |
2906 | insn = gen_tls_ld_64 (r3, got); | |
2907 | else | |
2908 | insn = gen_tls_ld_32 (r3, got); | |
2909 | start_sequence (); | |
2910 | emit_insn (insn); | |
2911 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2912 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2913 | insn = emit_call_insn (insn); | |
2914 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2915 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2916 | insn = get_insns (); | |
2917 | end_sequence (); | |
2918 | tmp1 = gen_reg_rtx (Pmode); | |
2919 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2920 | UNSPEC_TLSLD); | |
2921 | emit_libcall_block (insn, tmp1, r3, eqv); | |
2922 | if (rs6000_tls_size == 16) | |
2923 | { | |
2924 | if (TARGET_64BIT) | |
2925 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
2926 | else | |
2927 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
2928 | } | |
2929 | else if (rs6000_tls_size == 32) | |
2930 | { | |
2931 | tmp2 = gen_reg_rtx (Pmode); | |
2932 | if (TARGET_64BIT) | |
2933 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
2934 | else | |
2935 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
2936 | emit_insn (insn); | |
2937 | if (TARGET_64BIT) | |
2938 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
2939 | else | |
2940 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
2941 | } | |
2942 | else | |
2943 | { | |
2944 | tmp2 = gen_reg_rtx (Pmode); | |
2945 | if (TARGET_64BIT) | |
2946 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
2947 | else | |
2948 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
2949 | emit_insn (insn); | |
2950 | insn = gen_rtx_SET (Pmode, dest, | |
2951 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
2952 | } | |
2953 | emit_insn (insn); | |
2954 | } | |
2955 | else | |
2956 | { | |
2957 | /* IE, or 64 bit offset LE. */ | |
2958 | tmp2 = gen_reg_rtx (Pmode); | |
2959 | if (TARGET_64BIT) | |
2960 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
2961 | else | |
2962 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
2963 | emit_insn (insn); | |
2964 | if (TARGET_64BIT) | |
2965 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
2966 | else | |
2967 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
2968 | emit_insn (insn); | |
2969 | } | |
2970 | } | |
2971 | ||
2972 | return dest; | |
2973 | } | |
2974 | ||
c4501e62 JJ |
2975 | /* Return 1 if X contains a thread-local symbol. */ |
2976 | ||
2977 | bool | |
a2369ed3 | 2978 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 2979 | { |
cd413cab AP |
2980 | if (! TARGET_HAVE_TLS) |
2981 | return false; | |
2982 | ||
c4501e62 JJ |
2983 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
2984 | } | |
2985 | ||
2986 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
2987 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
2988 | ||
9390387d | 2989 | static int |
a2369ed3 | 2990 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
2991 | { |
2992 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
2993 | } | |
2994 | ||
24ea750e DJ |
2995 | /* The convention appears to be to define this wherever it is used. |
2996 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
2997 | is now used here. */ | |
2998 | #ifndef REG_MODE_OK_FOR_BASE_P | |
2999 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
3000 | #endif | |
3001 | ||
3002 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
3003 | replace the input X, or the original X if no replacement is called for. | |
3004 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
3005 | 0 if it should not. | |
3006 | ||
3007 | For RS/6000, we wish to handle large displacements off a base | |
3008 | register by splitting the addend across an addiu/addis and the mem insn. | |
3009 | This cuts number of extra insns needed from 3 to 1. | |
3010 | ||
3011 | On Darwin, we use this to generate code for floating point constants. | |
3012 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
3013 | The Darwin code is inside #if TARGET_MACHO because only then is | |
3014 | machopic_function_base_name() defined. */ | |
3015 | rtx | |
f676971a | 3016 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
c4ad648e AM |
3017 | int opnum, int type, |
3018 | int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e | 3019 | { |
f676971a | 3020 | /* We must recognize output that we have already generated ourselves. */ |
24ea750e DJ |
3021 | if (GET_CODE (x) == PLUS |
3022 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3023 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
3024 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3025 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3026 | { | |
3027 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3028 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3029 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3030 | *win = 1; |
3031 | return x; | |
3032 | } | |
3deb2758 | 3033 | |
24ea750e DJ |
3034 | #if TARGET_MACHO |
3035 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
3036 | && GET_CODE (x) == LO_SUM | |
3037 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3038 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
3039 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
3040 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
3041 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
3042 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
3043 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
3044 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
3045 | { | |
3046 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 3047 | floating point constant. */ |
24ea750e | 3048 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
c4ad648e AM |
3049 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3050 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3051 | *win = 1; |
3052 | return x; | |
3053 | } | |
3054 | #endif | |
4937d02d DE |
3055 | |
3056 | /* Force ld/std non-word aligned offset into base register by wrapping | |
3057 | in offset 0. */ | |
3058 | if (GET_CODE (x) == PLUS | |
3059 | && GET_CODE (XEXP (x, 0)) == REG | |
3060 | && REGNO (XEXP (x, 0)) < 32 | |
3061 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
3062 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3063 | && (INTVAL (XEXP (x, 1)) & 3) != 0 | |
78796ad5 | 3064 | && !ALTIVEC_VECTOR_MODE (mode) |
4937d02d DE |
3065 | && GET_MODE_SIZE (mode) >= UNITS_PER_WORD |
3066 | && TARGET_POWERPC64) | |
3067 | { | |
3068 | x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0)); | |
3069 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3070 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
3071 | opnum, (enum reload_type) type); | |
3072 | *win = 1; | |
3073 | return x; | |
3074 | } | |
3075 | ||
24ea750e DJ |
3076 | if (GET_CODE (x) == PLUS |
3077 | && GET_CODE (XEXP (x, 0)) == REG | |
3078 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
3079 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 3080 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 3081 | && !SPE_VECTOR_MODE (mode) |
54b695e7 AH |
3082 | && !(TARGET_E500_DOUBLE && (mode == DFmode |
3083 | || mode == DImode)) | |
78c875e8 | 3084 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
3085 | { |
3086 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
3087 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
3088 | HOST_WIDE_INT high | |
c4ad648e | 3089 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; |
24ea750e DJ |
3090 | |
3091 | /* Check for 32-bit overflow. */ | |
3092 | if (high + low != val) | |
c4ad648e | 3093 | { |
24ea750e DJ |
3094 | *win = 0; |
3095 | return x; | |
3096 | } | |
3097 | ||
3098 | /* Reload the high part into a base reg; leave the low part | |
c4ad648e | 3099 | in the mem directly. */ |
24ea750e DJ |
3100 | |
3101 | x = gen_rtx_PLUS (GET_MODE (x), | |
c4ad648e AM |
3102 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), |
3103 | GEN_INT (high)), | |
3104 | GEN_INT (low)); | |
24ea750e DJ |
3105 | |
3106 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3107 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3108 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3109 | *win = 1; |
3110 | return x; | |
3111 | } | |
4937d02d | 3112 | |
24ea750e DJ |
3113 | #if TARGET_MACHO |
3114 | if (GET_CODE (x) == SYMBOL_REF | |
3115 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 3116 | && !ALTIVEC_VECTOR_MODE (mode) |
a29077da | 3117 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
0d8c1c97 AM |
3118 | /* Don't do this for TFmode, since the result isn't offsettable. |
3119 | The same goes for DImode without 64-bit gprs. */ | |
3120 | && mode != TFmode | |
3121 | && (mode != DImode || TARGET_POWERPC64)) | |
24ea750e | 3122 | { |
a29077da GK |
3123 | if (flag_pic) |
3124 | { | |
3125 | rtx offset = gen_rtx_CONST (Pmode, | |
3126 | gen_rtx_MINUS (Pmode, x, | |
11abc112 | 3127 | machopic_function_base_sym ())); |
a29077da GK |
3128 | x = gen_rtx_LO_SUM (GET_MODE (x), |
3129 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
3130 | gen_rtx_HIGH (Pmode, offset)), offset); | |
3131 | } | |
3132 | else | |
3133 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
c4ad648e | 3134 | gen_rtx_HIGH (Pmode, x), x); |
a29077da | 3135 | |
24ea750e | 3136 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
3137 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3138 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3139 | *win = 1; |
3140 | return x; | |
3141 | } | |
3142 | #endif | |
4937d02d | 3143 | |
24ea750e | 3144 | if (TARGET_TOC |
4d588c14 | 3145 | && constant_pool_expr_p (x) |
c1f11548 | 3146 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3147 | { |
3148 | (x) = create_TOC_reference (x); | |
3149 | *win = 1; | |
3150 | return x; | |
3151 | } | |
3152 | *win = 0; | |
3153 | return x; | |
f676971a | 3154 | } |
24ea750e | 3155 | |
258bfae2 FS |
3156 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3157 | that is a valid memory address for an instruction. | |
3158 | The MODE argument is the machine mode for the MEM expression | |
3159 | that wants to use this address. | |
3160 | ||
3161 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3162 | refers to a constant pool entry of an address (or the sum of it | |
3163 | plus a constant), a short (16-bit signed) constant plus a register, | |
3164 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3165 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3166 | we must ensure that both words are addressable or PowerPC64 with offset |
3167 | word aligned. | |
3168 | ||
3169 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
76d2b81d | 3170 | 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because |
258bfae2 FS |
3171 | adjacent memory cells are accessed by adding word-sized offsets |
3172 | during assembly output. */ | |
3173 | int | |
a2369ed3 | 3174 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 3175 | { |
850e8d3d DN |
3176 | /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ |
3177 | if (TARGET_ALTIVEC | |
3178 | && ALTIVEC_VECTOR_MODE (mode) | |
3179 | && GET_CODE (x) == AND | |
3180 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3181 | && INTVAL (XEXP (x, 1)) == -16) | |
3182 | x = XEXP (x, 0); | |
3183 | ||
c4501e62 JJ |
3184 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3185 | return 0; | |
4d588c14 | 3186 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3187 | return 1; |
3188 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3189 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3190 | && !SPE_VECTOR_MODE (mode) |
54b695e7 AH |
3191 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
3192 | && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) | |
258bfae2 | 3193 | && TARGET_UPDATE |
4d588c14 | 3194 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3195 | return 1; |
4d588c14 | 3196 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 3197 | return 1; |
4d588c14 | 3198 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3199 | return 1; |
3200 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3201 | if (! reg_ok_strict | |
3202 | && GET_CODE (x) == PLUS | |
3203 | && GET_CODE (XEXP (x, 0)) == REG | |
708d2456 | 3204 | && (XEXP (x, 0) == virtual_stack_vars_rtx |
c4ad648e | 3205 | || XEXP (x, 0) == arg_pointer_rtx) |
258bfae2 FS |
3206 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
3207 | return 1; | |
76d2b81d | 3208 | if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3209 | return 1; |
3210 | if (mode != TImode | |
76d2b81d | 3211 | && mode != TFmode |
a3170dc6 AH |
3212 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3213 | || TARGET_POWERPC64 | |
4d4cbc0e | 3214 | || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode)) |
258bfae2 | 3215 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3216 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3217 | return 1; |
4d588c14 | 3218 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3219 | return 1; |
3220 | return 0; | |
3221 | } | |
4d588c14 RH |
3222 | |
3223 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3224 | has an effect that depends on the machine mode it is used for. | |
3225 | ||
3226 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3227 | modes don't allow them) or is a pre-increment or decrement. | |
3228 | ||
3229 | ??? Except that due to conceptual problems in offsettable_address_p | |
3230 | we can't really report the problems of integral offsets. So leave | |
f676971a | 3231 | this assuming that the adjustable offset must be valid for the |
4d588c14 RH |
3232 | sub-words of a TFmode operand, which is what we had before. */ |
3233 | ||
3234 | bool | |
a2369ed3 | 3235 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
3236 | { |
3237 | switch (GET_CODE (addr)) | |
3238 | { | |
3239 | case PLUS: | |
3240 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3241 | { | |
3242 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3243 | return val + 12 + 0x8000 >= 0x10000; | |
3244 | } | |
3245 | break; | |
3246 | ||
3247 | case LO_SUM: | |
3248 | return true; | |
3249 | ||
3250 | case PRE_INC: | |
3251 | case PRE_DEC: | |
3252 | return TARGET_UPDATE; | |
3253 | ||
3254 | default: | |
3255 | break; | |
3256 | } | |
3257 | ||
3258 | return false; | |
3259 | } | |
d8ecbcdb AH |
3260 | |
3261 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
3262 | to hold something of mode MODE. | |
3263 | This is ordinarily the length in words of a value of mode MODE | |
3264 | but can be less for certain modes in special long registers. | |
3265 | ||
3266 | For the SPE, GPRs are 64 bits but only 32 bits are visible in | |
3267 | scalar instructions. The upper 32 bits are only available to the | |
3268 | SIMD instructions. | |
3269 | ||
3270 | POWER and PowerPC GPRs hold 32 bits worth; | |
3271 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
3272 | ||
3273 | int | |
3274 | rs6000_hard_regno_nregs (int regno, enum machine_mode mode) | |
3275 | { | |
3276 | if (FP_REGNO_P (regno)) | |
3277 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; | |
3278 | ||
4d4cbc0e AH |
3279 | if (TARGET_E500_DOUBLE && mode == DFmode) |
3280 | return 1; | |
3281 | ||
d8ecbcdb AH |
3282 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
3283 | return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; | |
3284 | ||
3285 | if (ALTIVEC_REGNO_P (regno)) | |
3286 | return | |
3287 | (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; | |
3288 | ||
3289 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3290 | } | |
2aa4498c AH |
3291 | |
3292 | /* Change register usage conditional on target flags. */ | |
3293 | void | |
3294 | rs6000_conditional_register_usage (void) | |
3295 | { | |
3296 | int i; | |
3297 | ||
3298 | /* Set MQ register fixed (already call_used) if not POWER | |
3299 | architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not | |
3300 | be allocated. */ | |
3301 | if (! TARGET_POWER) | |
3302 | fixed_regs[64] = 1; | |
3303 | ||
7c9ac5c0 | 3304 | /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */ |
2aa4498c AH |
3305 | if (TARGET_64BIT) |
3306 | fixed_regs[13] = call_used_regs[13] | |
3307 | = call_really_used_regs[13] = 1; | |
3308 | ||
3309 | /* Conditionally disable FPRs. */ | |
3310 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
3311 | for (i = 32; i < 64; i++) | |
3312 | fixed_regs[i] = call_used_regs[i] | |
c4ad648e | 3313 | = call_really_used_regs[i] = 1; |
2aa4498c | 3314 | |
7c9ac5c0 PH |
3315 | /* The TOC register is not killed across calls in a way that is |
3316 | visible to the compiler. */ | |
3317 | if (DEFAULT_ABI == ABI_AIX) | |
3318 | call_really_used_regs[2] = 0; | |
3319 | ||
2aa4498c AH |
3320 | if (DEFAULT_ABI == ABI_V4 |
3321 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3322 | && flag_pic == 2) | |
3323 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3324 | ||
3325 | if (DEFAULT_ABI == ABI_V4 | |
3326 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3327 | && flag_pic == 1) | |
3328 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3329 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3330 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3331 | ||
3332 | if (DEFAULT_ABI == ABI_DARWIN | |
3333 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
6d0a8091 | 3334 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] |
2aa4498c AH |
3335 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] |
3336 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3337 | ||
b4db40bf JJ |
3338 | if (TARGET_TOC && TARGET_MINIMAL_TOC) |
3339 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3340 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3341 | ||
2aa4498c AH |
3342 | if (TARGET_ALTIVEC) |
3343 | global_regs[VSCR_REGNO] = 1; | |
3344 | ||
3345 | if (TARGET_SPE) | |
3346 | { | |
3347 | global_regs[SPEFSCR_REGNO] = 1; | |
3348 | fixed_regs[FIXED_SCRATCH] | |
c4ad648e | 3349 | = call_used_regs[FIXED_SCRATCH] |
2aa4498c AH |
3350 | = call_really_used_regs[FIXED_SCRATCH] = 1; |
3351 | } | |
3352 | ||
3353 | if (! TARGET_ALTIVEC) | |
3354 | { | |
3355 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
3356 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
3357 | call_really_used_regs[VRSAVE_REGNO] = 1; | |
3358 | } | |
3359 | ||
3360 | if (TARGET_ALTIVEC_ABI) | |
3361 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) | |
3362 | call_used_regs[i] = call_really_used_regs[i] = 1; | |
3363 | } | |
fb4d4348 | 3364 | \f |
a4f6c312 SS |
3365 | /* Try to output insns to set TARGET equal to the constant C if it can |
3366 | be done in less than N insns. Do all computations in MODE. | |
3367 | Returns the place where the output has been placed if it can be | |
3368 | done and the insns have been emitted. If it would take more than N | |
3369 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
3370 | |
3371 | rtx | |
f676971a | 3372 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
a2369ed3 | 3373 | rtx source, int n ATTRIBUTE_UNUSED) |
2bfcf297 | 3374 | { |
af8cb5c5 | 3375 | rtx result, insn, set; |
2bfcf297 DB |
3376 | HOST_WIDE_INT c0, c1; |
3377 | ||
37409796 | 3378 | switch (mode) |
2bfcf297 | 3379 | { |
37409796 NS |
3380 | case QImode: |
3381 | case HImode: | |
2bfcf297 | 3382 | if (dest == NULL) |
c4ad648e | 3383 | dest = gen_reg_rtx (mode); |
2bfcf297 DB |
3384 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); |
3385 | return dest; | |
37409796 NS |
3386 | |
3387 | case SImode: | |
af8cb5c5 | 3388 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
37409796 | 3389 | |
af8cb5c5 DE |
3390 | emit_insn (gen_rtx_SET (VOIDmode, result, |
3391 | GEN_INT (INTVAL (source) | |
3392 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
3393 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3394 | gen_rtx_IOR (SImode, result, | |
3395 | GEN_INT (INTVAL (source) & 0xffff)))); | |
3396 | result = dest; | |
37409796 NS |
3397 | break; |
3398 | ||
3399 | case DImode: | |
3400 | switch (GET_CODE (source)) | |
af8cb5c5 | 3401 | { |
37409796 | 3402 | case CONST_INT: |
af8cb5c5 DE |
3403 | c0 = INTVAL (source); |
3404 | c1 = -(c0 < 0); | |
37409796 NS |
3405 | break; |
3406 | ||
3407 | case CONST_DOUBLE: | |
2bfcf297 | 3408 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
3409 | c0 = CONST_DOUBLE_LOW (source); |
3410 | c1 = -(c0 < 0); | |
2bfcf297 | 3411 | #else |
af8cb5c5 DE |
3412 | c0 = CONST_DOUBLE_LOW (source); |
3413 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 3414 | #endif |
37409796 NS |
3415 | break; |
3416 | ||
3417 | default: | |
3418 | gcc_unreachable (); | |
af8cb5c5 | 3419 | } |
af8cb5c5 DE |
3420 | |
3421 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
37409796 NS |
3422 | break; |
3423 | ||
3424 | default: | |
3425 | gcc_unreachable (); | |
2bfcf297 | 3426 | } |
2bfcf297 | 3427 | |
af8cb5c5 DE |
3428 | insn = get_last_insn (); |
3429 | set = single_set (insn); | |
3430 | if (! CONSTANT_P (SET_SRC (set))) | |
3431 | set_unique_reg_note (insn, REG_EQUAL, source); | |
3432 | ||
3433 | return result; | |
2bfcf297 DB |
3434 | } |
3435 | ||
3436 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
3437 | fall back to a straight forward decomposition. We do this to avoid | |
3438 | exponential run times encountered when looking for longer sequences | |
3439 | with rs6000_emit_set_const. */ | |
3440 | static rtx | |
a2369ed3 | 3441 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
3442 | { |
3443 | if (!TARGET_POWERPC64) | |
3444 | { | |
3445 | rtx operand1, operand2; | |
3446 | ||
3447 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
3448 | DImode); | |
3449 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
3450 | DImode); | |
3451 | emit_move_insn (operand1, GEN_INT (c1)); | |
3452 | emit_move_insn (operand2, GEN_INT (c2)); | |
3453 | } | |
3454 | else | |
3455 | { | |
bc06712d | 3456 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 3457 | |
bc06712d | 3458 | ud1 = c1 & 0xffff; |
f921c9c9 | 3459 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 3460 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 3461 | c2 = c1 >> 32; |
2bfcf297 | 3462 | #endif |
bc06712d | 3463 | ud3 = c2 & 0xffff; |
f921c9c9 | 3464 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 3465 | |
f676971a | 3466 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
bc06712d | 3467 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) |
2bfcf297 | 3468 | { |
bc06712d | 3469 | if (ud1 & 0x8000) |
b78d48dd | 3470 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
3471 | else |
3472 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 3473 | } |
2bfcf297 | 3474 | |
f676971a | 3475 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
bc06712d | 3476 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) |
252b88f7 | 3477 | { |
bc06712d | 3478 | if (ud2 & 0x8000) |
f676971a | 3479 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) |
bc06712d | 3480 | - 0x80000000)); |
252b88f7 | 3481 | else |
bc06712d TR |
3482 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
3483 | if (ud1 != 0) | |
3484 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 3485 | } |
f676971a | 3486 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
bc06712d TR |
3487 | || (ud4 == 0 && ! (ud3 & 0x8000))) |
3488 | { | |
3489 | if (ud3 & 0x8000) | |
f676971a | 3490 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) |
bc06712d TR |
3491 | - 0x80000000)); |
3492 | else | |
3493 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
3494 | ||
3495 | if (ud2 != 0) | |
3496 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
3497 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
3498 | if (ud1 != 0) | |
3499 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3500 | } | |
f676971a | 3501 | else |
bc06712d TR |
3502 | { |
3503 | if (ud4 & 0x8000) | |
f676971a | 3504 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) |
bc06712d TR |
3505 | - 0x80000000)); |
3506 | else | |
3507 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
3508 | ||
3509 | if (ud3 != 0) | |
3510 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 3511 | |
bc06712d TR |
3512 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
3513 | if (ud2 != 0) | |
f676971a EC |
3514 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, |
3515 | GEN_INT (ud2 << 16))); | |
bc06712d TR |
3516 | if (ud1 != 0) |
3517 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3518 | } | |
3519 | } | |
2bfcf297 DB |
3520 | return dest; |
3521 | } | |
3522 | ||
76d2b81d DJ |
3523 | /* Helper for the following. Get rid of [r+r] memory refs |
3524 | in cases where it won't work (TImode, TFmode). */ | |
3525 | ||
3526 | static void | |
3527 | rs6000_eliminate_indexed_memrefs (rtx operands[2]) | |
3528 | { | |
3529 | if (GET_CODE (operands[0]) == MEM | |
3530 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
55aa0757 | 3531 | && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0)) |
76d2b81d DJ |
3532 | && ! reload_in_progress) |
3533 | operands[0] | |
3534 | = replace_equiv_address (operands[0], | |
3535 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
3536 | ||
3537 | if (GET_CODE (operands[1]) == MEM | |
3538 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
55aa0757 | 3539 | && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0)) |
76d2b81d DJ |
3540 | && ! reload_in_progress) |
3541 | operands[1] | |
3542 | = replace_equiv_address (operands[1], | |
3543 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
3544 | } | |
3545 | ||
fb4d4348 GK |
3546 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
3547 | void | |
a2369ed3 | 3548 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
3549 | { |
3550 | rtx operands[2]; | |
3551 | operands[0] = dest; | |
3552 | operands[1] = source; | |
f676971a | 3553 | |
fb4d4348 GK |
3554 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ |
3555 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3556 | && ! FLOAT_MODE_P (mode) | |
3557 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
3558 | { | |
3559 | /* FIXME. This should never happen. */ | |
3560 | /* Since it seems that it does, do the safe thing and convert | |
3561 | to a CONST_INT. */ | |
2496c7bd | 3562 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 | 3563 | } |
37409796 NS |
3564 | gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE |
3565 | || FLOAT_MODE_P (mode) | |
3566 | || ((CONST_DOUBLE_HIGH (operands[1]) != 0 | |
3567 | || CONST_DOUBLE_LOW (operands[1]) < 0) | |
3568 | && (CONST_DOUBLE_HIGH (operands[1]) != -1 | |
3569 | || CONST_DOUBLE_LOW (operands[1]) >= 0))); | |
3570 | ||
c9e8cb32 DD |
3571 | /* Check if GCC is setting up a block move that will end up using FP |
3572 | registers as temporaries. We must make sure this is acceptable. */ | |
3573 | if (GET_CODE (operands[0]) == MEM | |
3574 | && GET_CODE (operands[1]) == MEM | |
3575 | && mode == DImode | |
41543739 GK |
3576 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
3577 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
3578 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
3579 | ? 32 : MEM_ALIGN (operands[0]))) | |
3580 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
f676971a | 3581 | ? 32 |
41543739 GK |
3582 | : MEM_ALIGN (operands[1])))) |
3583 | && ! MEM_VOLATILE_P (operands [0]) | |
3584 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 3585 | { |
41543739 GK |
3586 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
3587 | adjust_address (operands[1], SImode, 0)); | |
3588 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
3589 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
3590 | return; |
3591 | } | |
630d42a0 | 3592 | |
55aa0757 | 3593 | if (!no_new_pseudos && GET_CODE (operands[0]) == MEM |
c9dbf840 | 3594 | && !gpc_reg_operand (operands[1], mode)) |
f6219a5e | 3595 | operands[1] = force_reg (mode, operands[1]); |
a9098fd0 | 3596 | |
a3170dc6 AH |
3597 | if (mode == SFmode && ! TARGET_POWERPC |
3598 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 3599 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 3600 | { |
ffc14f31 GK |
3601 | int regnum; |
3602 | ||
3603 | if (reload_in_progress || reload_completed) | |
3604 | regnum = true_regnum (operands[1]); | |
3605 | else if (GET_CODE (operands[1]) == REG) | |
3606 | regnum = REGNO (operands[1]); | |
3607 | else | |
3608 | regnum = -1; | |
f676971a | 3609 | |
fb4d4348 GK |
3610 | /* If operands[1] is a register, on POWER it may have |
3611 | double-precision data in it, so truncate it to single | |
3612 | precision. */ | |
3613 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
3614 | { | |
3615 | rtx newreg; | |
3616 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
3617 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
3618 | operands[1] = newreg; | |
3619 | } | |
3620 | } | |
3621 | ||
c4501e62 JJ |
3622 | /* Recognize the case where operand[1] is a reference to thread-local |
3623 | data and load its address to a register. */ | |
84f52ebd | 3624 | if (rs6000_tls_referenced_p (operands[1])) |
c4501e62 | 3625 | { |
84f52ebd RH |
3626 | enum tls_model model; |
3627 | rtx tmp = operands[1]; | |
3628 | rtx addend = NULL; | |
3629 | ||
3630 | if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) | |
3631 | { | |
3632 | addend = XEXP (XEXP (tmp, 0), 1); | |
3633 | tmp = XEXP (XEXP (tmp, 0), 0); | |
3634 | } | |
3635 | ||
3636 | gcc_assert (GET_CODE (tmp) == SYMBOL_REF); | |
3637 | model = SYMBOL_REF_TLS_MODEL (tmp); | |
3638 | gcc_assert (model != 0); | |
3639 | ||
3640 | tmp = rs6000_legitimize_tls_address (tmp, model); | |
3641 | if (addend) | |
3642 | { | |
3643 | tmp = gen_rtx_PLUS (mode, tmp, addend); | |
3644 | tmp = force_operand (tmp, operands[0]); | |
3645 | } | |
3646 | operands[1] = tmp; | |
c4501e62 JJ |
3647 | } |
3648 | ||
8f4e6caf RH |
3649 | /* Handle the case where reload calls us with an invalid address. */ |
3650 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 3651 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
3652 | || ! nonimmediate_operand (operands[0], mode))) |
3653 | goto emit_set; | |
3654 | ||
a9baceb1 GK |
3655 | /* 128-bit constant floating-point values on Darwin should really be |
3656 | loaded as two parts. */ | |
3657 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
3658 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
3659 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) | |
3660 | { | |
3661 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
3662 | know how to get a DFmode SUBREG of a TFmode. */ | |
3663 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), | |
3664 | simplify_gen_subreg (DImode, operands[1], mode, 0), | |
3665 | DImode); | |
3666 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, | |
3667 | GET_MODE_SIZE (DImode)), | |
3668 | simplify_gen_subreg (DImode, operands[1], mode, | |
3669 | GET_MODE_SIZE (DImode)), | |
3670 | DImode); | |
3671 | return; | |
3672 | } | |
3673 | ||
fb4d4348 GK |
3674 | /* FIXME: In the long term, this switch statement should go away |
3675 | and be replaced by a sequence of tests based on things like | |
3676 | mode == Pmode. */ | |
3677 | switch (mode) | |
3678 | { | |
3679 | case HImode: | |
3680 | case QImode: | |
3681 | if (CONSTANT_P (operands[1]) | |
3682 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 3683 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3684 | break; |
3685 | ||
06f4e019 | 3686 | case TFmode: |
76d2b81d DJ |
3687 | rs6000_eliminate_indexed_memrefs (operands); |
3688 | /* fall through */ | |
3689 | ||
fb4d4348 GK |
3690 | case DFmode: |
3691 | case SFmode: | |
f676971a | 3692 | if (CONSTANT_P (operands[1]) |
fb4d4348 | 3693 | && ! easy_fp_constant (operands[1], mode)) |
a9098fd0 | 3694 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 3695 | break; |
f676971a | 3696 | |
0ac081f6 AH |
3697 | case V16QImode: |
3698 | case V8HImode: | |
3699 | case V4SFmode: | |
3700 | case V4SImode: | |
a3170dc6 AH |
3701 | case V4HImode: |
3702 | case V2SFmode: | |
3703 | case V2SImode: | |
00a892b8 | 3704 | case V1DImode: |
69ef87e2 | 3705 | if (CONSTANT_P (operands[1]) |
d744e06e | 3706 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
3707 | operands[1] = force_const_mem (mode, operands[1]); |
3708 | break; | |
f676971a | 3709 | |
fb4d4348 | 3710 | case SImode: |
a9098fd0 | 3711 | case DImode: |
fb4d4348 GK |
3712 | /* Use default pattern for address of ELF small data */ |
3713 | if (TARGET_ELF | |
a9098fd0 | 3714 | && mode == Pmode |
f607bc57 | 3715 | && DEFAULT_ABI == ABI_V4 |
f676971a | 3716 | && (GET_CODE (operands[1]) == SYMBOL_REF |
a9098fd0 GK |
3717 | || GET_CODE (operands[1]) == CONST) |
3718 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
3719 | { |
3720 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
3721 | return; | |
3722 | } | |
3723 | ||
f607bc57 | 3724 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
3725 | && mode == Pmode && mode == SImode |
3726 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
3727 | { |
3728 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
3729 | return; | |
3730 | } | |
3731 | ||
ee890fe2 | 3732 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
3733 | && TARGET_NO_TOC |
3734 | && ! flag_pic | |
a9098fd0 | 3735 | && mode == Pmode |
fb4d4348 GK |
3736 | && CONSTANT_P (operands[1]) |
3737 | && GET_CODE (operands[1]) != HIGH | |
3738 | && GET_CODE (operands[1]) != CONST_INT) | |
3739 | { | |
a9098fd0 | 3740 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
3741 | |
3742 | /* If this is a function address on -mcall-aixdesc, | |
3743 | convert it to the address of the descriptor. */ | |
3744 | if (DEFAULT_ABI == ABI_AIX | |
3745 | && GET_CODE (operands[1]) == SYMBOL_REF | |
3746 | && XSTR (operands[1], 0)[0] == '.') | |
3747 | { | |
3748 | const char *name = XSTR (operands[1], 0); | |
3749 | rtx new_ref; | |
3750 | while (*name == '.') | |
3751 | name++; | |
3752 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
3753 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
3754 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 3755 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 3756 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 3757 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
3758 | operands[1] = new_ref; |
3759 | } | |
7509c759 | 3760 | |
ee890fe2 SS |
3761 | if (DEFAULT_ABI == ABI_DARWIN) |
3762 | { | |
ab82a49f AP |
3763 | #if TARGET_MACHO |
3764 | if (MACHO_DYNAMIC_NO_PIC_P) | |
3765 | { | |
3766 | /* Take care of any required data indirection. */ | |
3767 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
3768 | operands[1], mode, operands[0]); | |
3769 | if (operands[0] != operands[1]) | |
3770 | emit_insn (gen_rtx_SET (VOIDmode, | |
c4ad648e | 3771 | operands[0], operands[1])); |
ab82a49f AP |
3772 | return; |
3773 | } | |
3774 | #endif | |
b8a55285 AP |
3775 | emit_insn (gen_macho_high (target, operands[1])); |
3776 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
ee890fe2 SS |
3777 | return; |
3778 | } | |
3779 | ||
fb4d4348 GK |
3780 | emit_insn (gen_elf_high (target, operands[1])); |
3781 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
3782 | return; | |
3783 | } | |
3784 | ||
a9098fd0 GK |
3785 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
3786 | and we have put it in the TOC, we just need to make a TOC-relative | |
3787 | reference to it. */ | |
3788 | if (TARGET_TOC | |
3789 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 3790 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
3791 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
3792 | get_pool_mode (operands[1]))) | |
fb4d4348 | 3793 | { |
a9098fd0 | 3794 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 3795 | } |
a9098fd0 GK |
3796 | else if (mode == Pmode |
3797 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
3798 | && ((GET_CODE (operands[1]) != CONST_INT |
3799 | && ! easy_fp_constant (operands[1], mode)) | |
3800 | || (GET_CODE (operands[1]) == CONST_INT | |
3801 | && num_insns_constant (operands[1], mode) > 2) | |
3802 | || (GET_CODE (operands[0]) == REG | |
3803 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 3804 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
3805 | && ! legitimate_constant_pool_address_p (operands[1]) |
3806 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
3807 | { |
3808 | /* Emit a USE operation so that the constant isn't deleted if | |
3809 | expensive optimizations are turned on because nobody | |
3810 | references it. This should only be done for operands that | |
3811 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
3812 | This should not be done for operands that contain LABEL_REFs. | |
3813 | For now, we just handle the obvious case. */ | |
3814 | if (GET_CODE (operands[1]) != LABEL_REF) | |
3815 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
3816 | ||
c859cda6 | 3817 | #if TARGET_MACHO |
ee890fe2 | 3818 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 3819 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 3820 | { |
ee890fe2 SS |
3821 | operands[1] = |
3822 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
3823 | operands[0]); |
3824 | if (operands[0] != operands[1]) | |
3825 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
3826 | return; |
3827 | } | |
c859cda6 | 3828 | #endif |
ee890fe2 | 3829 | |
fb4d4348 GK |
3830 | /* If we are to limit the number of things we put in the TOC and |
3831 | this is a symbol plus a constant we can add in one insn, | |
3832 | just put the symbol in the TOC and add the constant. Don't do | |
3833 | this if reload is in progress. */ | |
3834 | if (GET_CODE (operands[1]) == CONST | |
3835 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
3836 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 3837 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
3838 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
3839 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
3840 | && ! side_effects_p (operands[0])) | |
3841 | { | |
a4f6c312 SS |
3842 | rtx sym = |
3843 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
3844 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
3845 | ||
a9098fd0 GK |
3846 | sym = force_reg (mode, sym); |
3847 | if (mode == SImode) | |
3848 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
3849 | else | |
3850 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
3851 | return; |
3852 | } | |
3853 | ||
a9098fd0 | 3854 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 3855 | |
f676971a | 3856 | if (TARGET_TOC |
4d588c14 | 3857 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
3858 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
3859 | get_pool_constant (XEXP (operands[1], 0)), | |
3860 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 3861 | { |
ba4828e0 | 3862 | operands[1] |
542a8afa | 3863 | = gen_const_mem (mode, |
c4ad648e | 3864 | create_TOC_reference (XEXP (operands[1], 0))); |
ba4828e0 | 3865 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); |
a9098fd0 | 3866 | } |
fb4d4348 GK |
3867 | } |
3868 | break; | |
a9098fd0 | 3869 | |
fb4d4348 | 3870 | case TImode: |
76d2b81d DJ |
3871 | rs6000_eliminate_indexed_memrefs (operands); |
3872 | ||
27dc0551 DE |
3873 | if (TARGET_POWER) |
3874 | { | |
3875 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3876 | gen_rtvec (2, | |
3877 | gen_rtx_SET (VOIDmode, | |
3878 | operands[0], operands[1]), | |
3879 | gen_rtx_CLOBBER (VOIDmode, | |
3880 | gen_rtx_SCRATCH (SImode))))); | |
3881 | return; | |
3882 | } | |
fb4d4348 GK |
3883 | break; |
3884 | ||
3885 | default: | |
37409796 | 3886 | gcc_unreachable (); |
fb4d4348 GK |
3887 | } |
3888 | ||
a9098fd0 GK |
3889 | /* Above, we may have called force_const_mem which may have returned |
3890 | an invalid address. If we can, fix this up; otherwise, reload will | |
3891 | have to deal with it. */ | |
8f4e6caf RH |
3892 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
3893 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 3894 | |
8f4e6caf | 3895 | emit_set: |
fb4d4348 GK |
3896 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
3897 | } | |
4697a36c | 3898 | \f |
2858f73a GK |
3899 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
3900 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
3901 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
3902 | && (CUM)->fregno <= FP_ARG_MAX_REG \ | |
3903 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
3904 | ||
3905 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
3906 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
3907 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
3908 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
3909 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 3910 | && (NAMED)) |
2858f73a | 3911 | |
c6e8c921 GK |
3912 | /* Return a nonzero value to say to return the function value in |
3913 | memory, just as large structures are always returned. TYPE will be | |
3914 | the data type of the value, and FNTYPE will be the type of the | |
3915 | function doing the returning, or @code{NULL} for libcalls. | |
3916 | ||
3917 | The AIX ABI for the RS/6000 specifies that all structures are | |
3918 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
3919 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
3920 | draft put them in memory, and GCC used to implement the draft | |
df01da37 | 3921 | instead of the final standard. Therefore, aix_struct_return |
c6e8c921 GK |
3922 | controls this instead of DEFAULT_ABI; V.4 targets needing backward |
3923 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
3924 | default, and -m switches get the final word. See | |
3925 | rs6000_override_options for more details. | |
3926 | ||
3927 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
3928 | long double support is enabled. These values are returned in memory. | |
3929 | ||
3930 | int_size_in_bytes returns -1 for variable size objects, which go in | |
3931 | memory always. The cast to unsigned makes -1 > 8. */ | |
3932 | ||
3933 | static bool | |
3934 | rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
3935 | { | |
594a51fe SS |
3936 | /* In the darwin64 abi, try to use registers for larger structs |
3937 | if possible. */ | |
0b5383eb | 3938 | if (rs6000_darwin64_abi |
594a51fe | 3939 | && TREE_CODE (type) == RECORD_TYPE |
0b5383eb DJ |
3940 | && int_size_in_bytes (type) > 0) |
3941 | { | |
3942 | CUMULATIVE_ARGS valcum; | |
3943 | rtx valret; | |
3944 | ||
3945 | valcum.words = 0; | |
3946 | valcum.fregno = FP_ARG_MIN_REG; | |
3947 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
3948 | /* Do a trial code generation as if this were going to be passed | |
3949 | as an argument; if any part goes in memory, we return NULL. */ | |
3950 | valret = rs6000_darwin64_record_arg (&valcum, type, 1, true); | |
3951 | if (valret) | |
3952 | return false; | |
3953 | /* Otherwise fall through to more conventional ABI rules. */ | |
3954 | } | |
594a51fe | 3955 | |
c6e8c921 | 3956 | if (AGGREGATE_TYPE_P (type) |
df01da37 | 3957 | && (aix_struct_return |
c6e8c921 GK |
3958 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) |
3959 | return true; | |
b693336b | 3960 | |
bada2eb8 DE |
3961 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector |
3962 | modes only exist for GCC vector types if -maltivec. */ | |
3963 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI | |
3964 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
3965 | return false; | |
3966 | ||
b693336b PB |
3967 | /* Return synthetic vectors in memory. */ |
3968 | if (TREE_CODE (type) == VECTOR_TYPE | |
ad630bef | 3969 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
3970 | { |
3971 | static bool warned_for_return_big_vectors = false; | |
3972 | if (!warned_for_return_big_vectors) | |
3973 | { | |
d4ee4d25 | 3974 | warning (0, "GCC vector returned by reference: " |
b693336b PB |
3975 | "non-standard ABI extension with no compatibility guarantee"); |
3976 | warned_for_return_big_vectors = true; | |
3977 | } | |
3978 | return true; | |
3979 | } | |
3980 | ||
c6e8c921 GK |
3981 | if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode) |
3982 | return true; | |
ad630bef | 3983 | |
c6e8c921 GK |
3984 | return false; |
3985 | } | |
3986 | ||
4697a36c MM |
3987 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
3988 | for a call to a function whose data type is FNTYPE. | |
3989 | For a library call, FNTYPE is 0. | |
3990 | ||
3991 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 3992 | so we never return a PARALLEL. */ |
4697a36c MM |
3993 | |
3994 | void | |
f676971a | 3995 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
3996 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
3997 | int libcall, int n_named_args) | |
4697a36c MM |
3998 | { |
3999 | static CUMULATIVE_ARGS zero_cumulative; | |
4000 | ||
4001 | *cum = zero_cumulative; | |
4002 | cum->words = 0; | |
4003 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 4004 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 4005 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
4006 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
4007 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 4008 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
4009 | cum->stdarg = fntype |
4010 | && (TYPE_ARG_TYPES (fntype) != 0 | |
4011 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
4012 | != void_type_node)); | |
4697a36c | 4013 | |
0f6937fe AM |
4014 | cum->nargs_prototype = 0; |
4015 | if (incoming || cum->prototype) | |
4016 | cum->nargs_prototype = n_named_args; | |
4697a36c | 4017 | |
a5c76ee6 | 4018 | /* Check for a longcall attribute. */ |
3eb4e360 AM |
4019 | if ((!fntype && rs6000_default_long_calls) |
4020 | || (fntype | |
4021 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
4022 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))) | |
4023 | cum->call_cookie |= CALL_LONG; | |
6a4cee5f | 4024 | |
4697a36c MM |
4025 | if (TARGET_DEBUG_ARG) |
4026 | { | |
4027 | fprintf (stderr, "\ninit_cumulative_args:"); | |
4028 | if (fntype) | |
4029 | { | |
4030 | tree ret_type = TREE_TYPE (fntype); | |
4031 | fprintf (stderr, " ret code = %s,", | |
4032 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
4033 | } | |
4034 | ||
6a4cee5f MM |
4035 | if (cum->call_cookie & CALL_LONG) |
4036 | fprintf (stderr, " longcall,"); | |
4037 | ||
4697a36c MM |
4038 | fprintf (stderr, " proto = %d, nargs = %d\n", |
4039 | cum->prototype, cum->nargs_prototype); | |
4040 | } | |
f676971a | 4041 | |
c4ad648e AM |
4042 | if (fntype |
4043 | && !TARGET_ALTIVEC | |
4044 | && TARGET_ALTIVEC_ABI | |
4045 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) | |
4046 | { | |
4047 | error ("Cannot return value in vector register because" | |
4048 | " altivec instructions are disabled, use -maltivec" | |
4049 | " to enable them."); | |
4050 | } | |
4697a36c MM |
4051 | } |
4052 | \f | |
fe984136 RH |
4053 | /* Return true if TYPE must be passed on the stack and not in registers. */ |
4054 | ||
4055 | static bool | |
4056 | rs6000_must_pass_in_stack (enum machine_mode mode, tree type) | |
4057 | { | |
4058 | if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT) | |
4059 | return must_pass_in_stack_var_size (mode, type); | |
4060 | else | |
4061 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
4062 | } | |
4063 | ||
c229cba9 DE |
4064 | /* If defined, a C expression which determines whether, and in which |
4065 | direction, to pad out an argument with extra space. The value | |
4066 | should be of type `enum direction': either `upward' to pad above | |
4067 | the argument, `downward' to pad below, or `none' to inhibit | |
4068 | padding. | |
4069 | ||
4070 | For the AIX ABI structs are always stored left shifted in their | |
4071 | argument slot. */ | |
4072 | ||
9ebbca7d | 4073 | enum direction |
a2369ed3 | 4074 | function_arg_padding (enum machine_mode mode, tree type) |
c229cba9 | 4075 | { |
6e985040 AM |
4076 | #ifndef AGGREGATE_PADDING_FIXED |
4077 | #define AGGREGATE_PADDING_FIXED 0 | |
4078 | #endif | |
4079 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
4080 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
4081 | #endif | |
4082 | ||
4083 | if (!AGGREGATE_PADDING_FIXED) | |
4084 | { | |
4085 | /* GCC used to pass structures of the same size as integer types as | |
4086 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
19525b57 | 4087 | i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were |
6e985040 AM |
4088 | passed padded downward, except that -mstrict-align further |
4089 | muddied the water in that multi-component structures of 2 and 4 | |
4090 | bytes in size were passed padded upward. | |
4091 | ||
4092 | The following arranges for best compatibility with previous | |
4093 | versions of gcc, but removes the -mstrict-align dependency. */ | |
4094 | if (BYTES_BIG_ENDIAN) | |
4095 | { | |
4096 | HOST_WIDE_INT size = 0; | |
4097 | ||
4098 | if (mode == BLKmode) | |
4099 | { | |
4100 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
4101 | size = int_size_in_bytes (type); | |
4102 | } | |
4103 | else | |
4104 | size = GET_MODE_SIZE (mode); | |
4105 | ||
4106 | if (size == 1 || size == 2 || size == 4) | |
4107 | return downward; | |
4108 | } | |
4109 | return upward; | |
4110 | } | |
4111 | ||
4112 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
4113 | { | |
4114 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
4115 | return upward; | |
4116 | } | |
c229cba9 | 4117 | |
d3704c46 KH |
4118 | /* Fall back to the default. */ |
4119 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
4120 | } |
4121 | ||
b6c9286a | 4122 | /* If defined, a C expression that gives the alignment boundary, in bits, |
f676971a | 4123 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a | 4124 | PARM_BOUNDARY is used for all arguments. |
f676971a | 4125 | |
b693336b PB |
4126 | V.4 wants long longs to be double word aligned. |
4127 | Doubleword align SPE vectors. | |
4128 | Quadword align Altivec vectors. | |
4129 | Quadword align large synthetic vector types. */ | |
b6c9286a MM |
4130 | |
4131 | int | |
b693336b | 4132 | function_arg_boundary (enum machine_mode mode, tree type) |
b6c9286a | 4133 | { |
4ed78545 AM |
4134 | if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8) |
4135 | return 64; | |
ad630bef DE |
4136 | else if (SPE_VECTOR_MODE (mode) |
4137 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4138 | && int_size_in_bytes (type) >= 8 | |
4139 | && int_size_in_bytes (type) < 16)) | |
e1f83b4d | 4140 | return 64; |
ad630bef DE |
4141 | else if (ALTIVEC_VECTOR_MODE (mode) |
4142 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4143 | && int_size_in_bytes (type) >= 16)) | |
0ac081f6 | 4144 | return 128; |
0b5383eb DJ |
4145 | else if (rs6000_darwin64_abi && mode == BLKmode |
4146 | && type && TYPE_ALIGN (type) > 64) | |
4147 | return 128; | |
9ebbca7d | 4148 | else |
b6c9286a | 4149 | return PARM_BOUNDARY; |
b6c9286a | 4150 | } |
c53bdcf5 | 4151 | |
294bd182 AM |
4152 | /* For a function parm of MODE and TYPE, return the starting word in |
4153 | the parameter area. NWORDS of the parameter area are already used. */ | |
4154 | ||
4155 | static unsigned int | |
4156 | rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords) | |
4157 | { | |
4158 | unsigned int align; | |
4159 | unsigned int parm_offset; | |
4160 | ||
4161 | align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; | |
4162 | parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6; | |
4163 | return nwords + (-(parm_offset + nwords) & align); | |
4164 | } | |
4165 | ||
c53bdcf5 AM |
4166 | /* Compute the size (in words) of a function argument. */ |
4167 | ||
4168 | static unsigned long | |
4169 | rs6000_arg_size (enum machine_mode mode, tree type) | |
4170 | { | |
4171 | unsigned long size; | |
4172 | ||
4173 | if (mode != BLKmode) | |
4174 | size = GET_MODE_SIZE (mode); | |
4175 | else | |
4176 | size = int_size_in_bytes (type); | |
4177 | ||
4178 | if (TARGET_32BIT) | |
4179 | return (size + 3) >> 2; | |
4180 | else | |
4181 | return (size + 7) >> 3; | |
4182 | } | |
b6c9286a | 4183 | \f |
0b5383eb | 4184 | /* Use this to flush pending int fields. */ |
594a51fe SS |
4185 | |
4186 | static void | |
0b5383eb DJ |
4187 | rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum, |
4188 | HOST_WIDE_INT bitpos) | |
594a51fe | 4189 | { |
0b5383eb DJ |
4190 | unsigned int startbit, endbit; |
4191 | int intregs, intoffset; | |
4192 | enum machine_mode mode; | |
594a51fe | 4193 | |
0b5383eb DJ |
4194 | if (cum->intoffset == -1) |
4195 | return; | |
594a51fe | 4196 | |
0b5383eb DJ |
4197 | intoffset = cum->intoffset; |
4198 | cum->intoffset = -1; | |
4199 | ||
4200 | if (intoffset % BITS_PER_WORD != 0) | |
4201 | { | |
4202 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, | |
4203 | MODE_INT, 0); | |
4204 | if (mode == BLKmode) | |
594a51fe | 4205 | { |
0b5383eb DJ |
4206 | /* We couldn't find an appropriate mode, which happens, |
4207 | e.g., in packed structs when there are 3 bytes to load. | |
4208 | Back intoffset back to the beginning of the word in this | |
4209 | case. */ | |
4210 | intoffset = intoffset & -BITS_PER_WORD; | |
594a51fe | 4211 | } |
594a51fe | 4212 | } |
0b5383eb DJ |
4213 | |
4214 | startbit = intoffset & -BITS_PER_WORD; | |
4215 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4216 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
4217 | cum->words += intregs; | |
4218 | } | |
4219 | ||
4220 | /* The darwin64 ABI calls for us to recurse down through structs, | |
4221 | looking for elements passed in registers. Unfortunately, we have | |
4222 | to track int register count here also because of misalignments | |
4223 | in powerpc alignment mode. */ | |
4224 | ||
4225 | static void | |
4226 | rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum, | |
4227 | tree type, | |
4228 | HOST_WIDE_INT startbitpos) | |
4229 | { | |
4230 | tree f; | |
4231 | ||
4232 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
4233 | if (TREE_CODE (f) == FIELD_DECL) | |
4234 | { | |
4235 | HOST_WIDE_INT bitpos = startbitpos; | |
4236 | tree ftype = TREE_TYPE (f); | |
4237 | enum machine_mode mode = TYPE_MODE (ftype); | |
4238 | ||
4239 | if (DECL_SIZE (f) != 0 | |
4240 | && host_integerp (bit_position (f), 1)) | |
4241 | bitpos += int_bit_position (f); | |
4242 | ||
4243 | /* ??? FIXME: else assume zero offset. */ | |
4244 | ||
4245 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
4246 | rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos); | |
4247 | else if (USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
4248 | { | |
4249 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
4250 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; | |
4251 | cum->words += (GET_MODE_SIZE (mode) + 7) >> 3; | |
4252 | } | |
4253 | else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1)) | |
4254 | { | |
4255 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
4256 | cum->vregno++; | |
4257 | cum->words += 2; | |
4258 | } | |
4259 | else if (cum->intoffset == -1) | |
4260 | cum->intoffset = bitpos; | |
4261 | } | |
594a51fe SS |
4262 | } |
4263 | ||
4697a36c MM |
4264 | /* Update the data in CUM to advance over an argument |
4265 | of mode MODE and data type TYPE. | |
b2d04ecf AM |
4266 | (TYPE is null for libcalls where that information may not be available.) |
4267 | ||
4268 | Note that for args passed by reference, function_arg will be called | |
4269 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4270 | itself. */ | |
4697a36c MM |
4271 | |
4272 | void | |
f676971a | 4273 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
594a51fe | 4274 | tree type, int named, int depth) |
4697a36c | 4275 | { |
0b5383eb DJ |
4276 | int size; |
4277 | ||
594a51fe SS |
4278 | /* Only tick off an argument if we're not recursing. */ |
4279 | if (depth == 0) | |
4280 | cum->nargs_prototype--; | |
4697a36c | 4281 | |
ad630bef DE |
4282 | if (TARGET_ALTIVEC_ABI |
4283 | && (ALTIVEC_VECTOR_MODE (mode) | |
4284 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4285 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 4286 | { |
4ed78545 AM |
4287 | bool stack = false; |
4288 | ||
2858f73a | 4289 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c4ad648e | 4290 | { |
6d0ef01e HP |
4291 | cum->vregno++; |
4292 | if (!TARGET_ALTIVEC) | |
4293 | error ("Cannot pass argument in vector register because" | |
4294 | " altivec instructions are disabled, use -maltivec" | |
4295 | " to enable them."); | |
4ed78545 AM |
4296 | |
4297 | /* PowerPC64 Linux and AIX allocate GPRs for a vector argument | |
f676971a | 4298 | even if it is going to be passed in a vector register. |
4ed78545 AM |
4299 | Darwin does the same for variable-argument functions. */ |
4300 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4301 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
4302 | stack = true; | |
6d0ef01e | 4303 | } |
4ed78545 AM |
4304 | else |
4305 | stack = true; | |
4306 | ||
4307 | if (stack) | |
c4ad648e | 4308 | { |
a594a19c | 4309 | int align; |
f676971a | 4310 | |
2858f73a GK |
4311 | /* Vector parameters must be 16-byte aligned. This places |
4312 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
4313 | the parameter save area starts at offset 24 from the | |
4314 | stack. In 64-bit mode, they just have to start on an | |
4315 | even word, since the parameter save area is 16-byte | |
4316 | aligned. Space for GPRs is reserved even if the argument | |
4317 | will be passed in memory. */ | |
4318 | if (TARGET_32BIT) | |
4ed78545 | 4319 | align = (2 - cum->words) & 3; |
2858f73a GK |
4320 | else |
4321 | align = cum->words & 1; | |
c53bdcf5 | 4322 | cum->words += align + rs6000_arg_size (mode, type); |
f676971a | 4323 | |
a594a19c GK |
4324 | if (TARGET_DEBUG_ARG) |
4325 | { | |
f676971a | 4326 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", |
a594a19c GK |
4327 | cum->words, align); |
4328 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
f676971a | 4329 | cum->nargs_prototype, cum->prototype, |
2858f73a | 4330 | GET_MODE_NAME (mode)); |
a594a19c GK |
4331 | } |
4332 | } | |
0ac081f6 | 4333 | } |
a4b0320c | 4334 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
4335 | && !cum->stdarg |
4336 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 4337 | cum->sysv_gregno++; |
594a51fe SS |
4338 | |
4339 | else if (rs6000_darwin64_abi | |
4340 | && mode == BLKmode | |
0b5383eb DJ |
4341 | && TREE_CODE (type) == RECORD_TYPE |
4342 | && (size = int_size_in_bytes (type)) > 0) | |
4343 | { | |
4344 | /* Variable sized types have size == -1 and are | |
4345 | treated as if consisting entirely of ints. | |
4346 | Pad to 16 byte boundary if needed. */ | |
4347 | if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
4348 | && (cum->words % 2) != 0) | |
4349 | cum->words++; | |
4350 | /* For varargs, we can just go up by the size of the struct. */ | |
4351 | if (!named) | |
4352 | cum->words += (size + 7) / 8; | |
4353 | else | |
4354 | { | |
4355 | /* It is tempting to say int register count just goes up by | |
4356 | sizeof(type)/8, but this is wrong in a case such as | |
4357 | { int; double; int; } [powerpc alignment]. We have to | |
4358 | grovel through the fields for these too. */ | |
4359 | cum->intoffset = 0; | |
4360 | rs6000_darwin64_record_arg_advance_recurse (cum, type, 0); | |
4361 | rs6000_darwin64_record_arg_advance_flush (cum, | |
4362 | size * BITS_PER_UNIT); | |
4363 | } | |
4364 | } | |
f607bc57 | 4365 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4366 | { |
a3170dc6 | 4367 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 4368 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 4369 | { |
4cc833b7 RH |
4370 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
4371 | cum->fregno++; | |
4372 | else | |
4373 | { | |
4374 | if (mode == DFmode) | |
c4ad648e | 4375 | cum->words += cum->words & 1; |
c53bdcf5 | 4376 | cum->words += rs6000_arg_size (mode, type); |
4cc833b7 | 4377 | } |
4697a36c | 4378 | } |
4cc833b7 RH |
4379 | else |
4380 | { | |
b2d04ecf | 4381 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4382 | int gregno = cum->sysv_gregno; |
4383 | ||
4ed78545 AM |
4384 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4385 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4386 | as complex int due to a historical mistake. */ | |
4387 | if (n_words == 2) | |
4388 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4389 | |
4ed78545 | 4390 | /* Multi-reg args are not split between registers and stack. */ |
4cc833b7 RH |
4391 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
4392 | { | |
4ed78545 AM |
4393 | /* Long long and SPE vectors are aligned on the stack. |
4394 | So are other 2 word items such as complex int due to | |
4395 | a historical mistake. */ | |
4cc833b7 RH |
4396 | if (n_words == 2) |
4397 | cum->words += cum->words & 1; | |
4398 | cum->words += n_words; | |
4399 | } | |
4697a36c | 4400 | |
4cc833b7 RH |
4401 | /* Note: continuing to accumulate gregno past when we've started |
4402 | spilling to the stack indicates the fact that we've started | |
4403 | spilling to the stack to expand_builtin_saveregs. */ | |
4404 | cum->sysv_gregno = gregno + n_words; | |
4405 | } | |
4697a36c | 4406 | |
4cc833b7 RH |
4407 | if (TARGET_DEBUG_ARG) |
4408 | { | |
4409 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4410 | cum->words, cum->fregno); | |
4411 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
4412 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
4413 | fprintf (stderr, "mode = %4s, named = %d\n", | |
4414 | GET_MODE_NAME (mode), named); | |
4415 | } | |
4697a36c MM |
4416 | } |
4417 | else | |
4cc833b7 | 4418 | { |
b2d04ecf | 4419 | int n_words = rs6000_arg_size (mode, type); |
294bd182 AM |
4420 | int start_words = cum->words; |
4421 | int align_words = rs6000_parm_start (mode, type, start_words); | |
a4f6c312 | 4422 | |
294bd182 | 4423 | cum->words = align_words + n_words; |
4697a36c | 4424 | |
a3170dc6 AH |
4425 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
4426 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
c53bdcf5 | 4427 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; |
4cc833b7 RH |
4428 | |
4429 | if (TARGET_DEBUG_ARG) | |
4430 | { | |
4431 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4432 | cum->words, cum->fregno); | |
4433 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
4434 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
594a51fe | 4435 | fprintf (stderr, "named = %d, align = %d, depth = %d\n", |
294bd182 | 4436 | named, align_words - start_words, depth); |
4cc833b7 RH |
4437 | } |
4438 | } | |
4697a36c | 4439 | } |
a6c9bed4 | 4440 | |
f82f556d AH |
4441 | static rtx |
4442 | spe_build_register_parallel (enum machine_mode mode, int gregno) | |
4443 | { | |
54b695e7 | 4444 | rtx r1, r3; |
f82f556d | 4445 | |
37409796 | 4446 | switch (mode) |
f82f556d | 4447 | { |
37409796 | 4448 | case DFmode: |
54b695e7 AH |
4449 | r1 = gen_rtx_REG (DImode, gregno); |
4450 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
4451 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1)); | |
37409796 NS |
4452 | |
4453 | case DCmode: | |
54b695e7 AH |
4454 | r1 = gen_rtx_REG (DImode, gregno); |
4455 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
4456 | r3 = gen_rtx_REG (DImode, gregno + 2); | |
4457 | r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8)); | |
4458 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3)); | |
37409796 NS |
4459 | |
4460 | default: | |
4461 | gcc_unreachable (); | |
f82f556d | 4462 | } |
f82f556d | 4463 | } |
b78d48dd | 4464 | |
f82f556d | 4465 | /* Determine where to put a SIMD argument on the SPE. */ |
a6c9bed4 | 4466 | static rtx |
f676971a | 4467 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 4468 | tree type) |
a6c9bed4 | 4469 | { |
f82f556d AH |
4470 | int gregno = cum->sysv_gregno; |
4471 | ||
4472 | /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but | |
600e1f95 | 4473 | are passed and returned in a pair of GPRs for ABI compatibility. */ |
18f63bfa | 4474 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode)) |
f82f556d | 4475 | { |
b5870bee AH |
4476 | int n_words = rs6000_arg_size (mode, type); |
4477 | ||
f82f556d | 4478 | /* Doubles go in an odd/even register pair (r5/r6, etc). */ |
b5870bee AH |
4479 | if (mode == DFmode) |
4480 | gregno += (1 - gregno) & 1; | |
f82f556d | 4481 | |
b5870bee AH |
4482 | /* Multi-reg args are not split between registers and stack. */ |
4483 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
f82f556d AH |
4484 | return NULL_RTX; |
4485 | ||
4486 | return spe_build_register_parallel (mode, gregno); | |
4487 | } | |
a6c9bed4 AH |
4488 | if (cum->stdarg) |
4489 | { | |
c53bdcf5 | 4490 | int n_words = rs6000_arg_size (mode, type); |
a6c9bed4 AH |
4491 | |
4492 | /* SPE vectors are put in odd registers. */ | |
4493 | if (n_words == 2 && (gregno & 1) == 0) | |
4494 | gregno += 1; | |
4495 | ||
4496 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
4497 | { | |
4498 | rtx r1, r2; | |
4499 | enum machine_mode m = SImode; | |
4500 | ||
4501 | r1 = gen_rtx_REG (m, gregno); | |
4502 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
4503 | r2 = gen_rtx_REG (m, gregno + 1); | |
4504 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
4505 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
4506 | } | |
4507 | else | |
b78d48dd | 4508 | return NULL_RTX; |
a6c9bed4 AH |
4509 | } |
4510 | else | |
4511 | { | |
f82f556d AH |
4512 | if (gregno <= GP_ARG_MAX_REG) |
4513 | return gen_rtx_REG (mode, gregno); | |
a6c9bed4 | 4514 | else |
b78d48dd | 4515 | return NULL_RTX; |
a6c9bed4 AH |
4516 | } |
4517 | } | |
4518 | ||
0b5383eb DJ |
4519 | /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the |
4520 | structure between cum->intoffset and bitpos to integer registers. */ | |
594a51fe | 4521 | |
0b5383eb DJ |
4522 | static void |
4523 | rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum, | |
4524 | HOST_WIDE_INT bitpos, rtx rvec[], int *k) | |
594a51fe | 4525 | { |
0b5383eb DJ |
4526 | enum machine_mode mode; |
4527 | unsigned int regno; | |
4528 | unsigned int startbit, endbit; | |
4529 | int this_regno, intregs, intoffset; | |
4530 | rtx reg; | |
594a51fe | 4531 | |
0b5383eb DJ |
4532 | if (cum->intoffset == -1) |
4533 | return; | |
4534 | ||
4535 | intoffset = cum->intoffset; | |
4536 | cum->intoffset = -1; | |
4537 | ||
4538 | /* If this is the trailing part of a word, try to only load that | |
4539 | much into the register. Otherwise load the whole register. Note | |
4540 | that in the latter case we may pick up unwanted bits. It's not a | |
4541 | problem at the moment but may wish to revisit. */ | |
4542 | ||
4543 | if (intoffset % BITS_PER_WORD != 0) | |
594a51fe | 4544 | { |
0b5383eb DJ |
4545 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
4546 | MODE_INT, 0); | |
4547 | if (mode == BLKmode) | |
4548 | { | |
4549 | /* We couldn't find an appropriate mode, which happens, | |
4550 | e.g., in packed structs when there are 3 bytes to load. | |
4551 | Back intoffset back to the beginning of the word in this | |
4552 | case. */ | |
4553 | intoffset = intoffset & -BITS_PER_WORD; | |
4554 | mode = word_mode; | |
4555 | } | |
4556 | } | |
4557 | else | |
4558 | mode = word_mode; | |
4559 | ||
4560 | startbit = intoffset & -BITS_PER_WORD; | |
4561 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4562 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
4563 | this_regno = cum->words + intoffset / BITS_PER_WORD; | |
4564 | ||
4565 | if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno) | |
4566 | cum->use_stack = 1; | |
4567 | ||
4568 | intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno); | |
4569 | if (intregs <= 0) | |
4570 | return; | |
4571 | ||
4572 | intoffset /= BITS_PER_UNIT; | |
4573 | do | |
4574 | { | |
4575 | regno = GP_ARG_MIN_REG + this_regno; | |
4576 | reg = gen_rtx_REG (mode, regno); | |
4577 | rvec[(*k)++] = | |
4578 | gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); | |
4579 | ||
4580 | this_regno += 1; | |
4581 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
4582 | mode = word_mode; | |
4583 | intregs -= 1; | |
4584 | } | |
4585 | while (intregs > 0); | |
4586 | } | |
4587 | ||
4588 | /* Recursive workhorse for the following. */ | |
4589 | ||
4590 | static void | |
4591 | rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type, | |
4592 | HOST_WIDE_INT startbitpos, rtx rvec[], | |
4593 | int *k) | |
4594 | { | |
4595 | tree f; | |
4596 | ||
4597 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
4598 | if (TREE_CODE (f) == FIELD_DECL) | |
4599 | { | |
4600 | HOST_WIDE_INT bitpos = startbitpos; | |
4601 | tree ftype = TREE_TYPE (f); | |
4602 | enum machine_mode mode = TYPE_MODE (ftype); | |
4603 | ||
4604 | if (DECL_SIZE (f) != 0 | |
4605 | && host_integerp (bit_position (f), 1)) | |
4606 | bitpos += int_bit_position (f); | |
4607 | ||
4608 | /* ??? FIXME: else assume zero offset. */ | |
4609 | ||
4610 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
4611 | rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k); | |
4612 | else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
594a51fe | 4613 | { |
0b5383eb DJ |
4614 | #if 0 |
4615 | switch (mode) | |
594a51fe | 4616 | { |
0b5383eb DJ |
4617 | case SCmode: mode = SFmode; break; |
4618 | case DCmode: mode = DFmode; break; | |
4619 | case TCmode: mode = TFmode; break; | |
4620 | default: break; | |
594a51fe | 4621 | } |
0b5383eb DJ |
4622 | #endif |
4623 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
4624 | rvec[(*k)++] | |
4625 | = gen_rtx_EXPR_LIST (VOIDmode, | |
4626 | gen_rtx_REG (mode, cum->fregno++), | |
4627 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4628 | if (mode == TFmode) | |
4629 | cum->fregno++; | |
594a51fe | 4630 | } |
0b5383eb DJ |
4631 | else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1)) |
4632 | { | |
4633 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
4634 | rvec[(*k)++] | |
4635 | = gen_rtx_EXPR_LIST (VOIDmode, | |
4636 | gen_rtx_REG (mode, cum->vregno++), | |
4637 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4638 | } | |
4639 | else if (cum->intoffset == -1) | |
4640 | cum->intoffset = bitpos; | |
4641 | } | |
4642 | } | |
594a51fe | 4643 | |
0b5383eb DJ |
4644 | /* For the darwin64 ABI, we want to construct a PARALLEL consisting of |
4645 | the register(s) to be used for each field and subfield of a struct | |
4646 | being passed by value, along with the offset of where the | |
4647 | register's value may be found in the block. FP fields go in FP | |
4648 | register, vector fields go in vector registers, and everything | |
4649 | else goes in int registers, packed as in memory. | |
8ff40a74 | 4650 | |
0b5383eb DJ |
4651 | This code is also used for function return values. RETVAL indicates |
4652 | whether this is the case. | |
8ff40a74 | 4653 | |
0b5383eb DJ |
4654 | Much of this is taken from the Sparc V9 port, which has a similar |
4655 | calling convention. */ | |
594a51fe | 4656 | |
0b5383eb DJ |
4657 | static rtx |
4658 | rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type, | |
4659 | int named, bool retval) | |
4660 | { | |
4661 | rtx rvec[FIRST_PSEUDO_REGISTER]; | |
4662 | int k = 1, kbase = 1; | |
4663 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
4664 | /* This is a copy; modifications are not visible to our caller. */ | |
4665 | CUMULATIVE_ARGS copy_cum = *orig_cum; | |
4666 | CUMULATIVE_ARGS *cum = ©_cum; | |
4667 | ||
4668 | /* Pad to 16 byte boundary if needed. */ | |
4669 | if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
4670 | && (cum->words % 2) != 0) | |
4671 | cum->words++; | |
4672 | ||
4673 | cum->intoffset = 0; | |
4674 | cum->use_stack = 0; | |
4675 | cum->named = named; | |
4676 | ||
4677 | /* Put entries into rvec[] for individual FP and vector fields, and | |
4678 | for the chunks of memory that go in int regs. Note we start at | |
4679 | element 1; 0 is reserved for an indication of using memory, and | |
4680 | may or may not be filled in below. */ | |
4681 | rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k); | |
4682 | rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k); | |
4683 | ||
4684 | /* If any part of the struct went on the stack put all of it there. | |
4685 | This hack is because the generic code for | |
4686 | FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register | |
4687 | parts of the struct are not at the beginning. */ | |
4688 | if (cum->use_stack) | |
4689 | { | |
4690 | if (retval) | |
4691 | return NULL_RTX; /* doesn't go in registers at all */ | |
4692 | kbase = 0; | |
4693 | rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4694 | } | |
4695 | if (k > 1 || cum->use_stack) | |
4696 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase])); | |
594a51fe SS |
4697 | else |
4698 | return NULL_RTX; | |
4699 | } | |
4700 | ||
b78d48dd FJ |
4701 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
4702 | ||
4703 | static rtx | |
ec6376ab | 4704 | rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) |
b78d48dd | 4705 | { |
ec6376ab AM |
4706 | int n_units; |
4707 | int i, k; | |
4708 | rtx rvec[GP_ARG_NUM_REG + 1]; | |
4709 | ||
4710 | if (align_words >= GP_ARG_NUM_REG) | |
4711 | return NULL_RTX; | |
4712 | ||
4713 | n_units = rs6000_arg_size (mode, type); | |
4714 | ||
4715 | /* Optimize the simple case where the arg fits in one gpr, except in | |
4716 | the case of BLKmode due to assign_parms assuming that registers are | |
4717 | BITS_PER_WORD wide. */ | |
4718 | if (n_units == 0 | |
4719 | || (n_units == 1 && mode != BLKmode)) | |
4720 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4721 | ||
4722 | k = 0; | |
4723 | if (align_words + n_units > GP_ARG_NUM_REG) | |
4724 | /* Not all of the arg fits in gprs. Say that it goes in memory too, | |
4725 | using a magic NULL_RTX component. | |
4726 | FIXME: This is not strictly correct. Only some of the arg | |
4727 | belongs in memory, not all of it. However, there isn't any way | |
4728 | to do this currently, apart from building rtx descriptions for | |
4729 | the pieces of memory we want stored. Due to bugs in the generic | |
4730 | code we can't use the normal function_arg_partial_nregs scheme | |
4731 | with the PARALLEL arg description we emit here. | |
4732 | In any case, the code to store the whole arg to memory is often | |
4733 | more efficient than code to store pieces, and we know that space | |
4734 | is available in the right place for the whole arg. */ | |
78a52f11 RH |
4735 | /* FIXME: This should be fixed since the conversion to |
4736 | TARGET_ARG_PARTIAL_BYTES. */ | |
ec6376ab AM |
4737 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); |
4738 | ||
4739 | i = 0; | |
4740 | do | |
36a454e1 | 4741 | { |
ec6376ab AM |
4742 | rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); |
4743 | rtx off = GEN_INT (i++ * 4); | |
4744 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
36a454e1 | 4745 | } |
ec6376ab AM |
4746 | while (++align_words < GP_ARG_NUM_REG && --n_units != 0); |
4747 | ||
4748 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
b78d48dd FJ |
4749 | } |
4750 | ||
4697a36c MM |
4751 | /* Determine where to put an argument to a function. |
4752 | Value is zero to push the argument on the stack, | |
4753 | or a hard register in which to store the argument. | |
4754 | ||
4755 | MODE is the argument's machine mode. | |
4756 | TYPE is the data type of the argument (as a tree). | |
4757 | This is null for libcalls where that information may | |
4758 | not be available. | |
4759 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
0b5383eb DJ |
4760 | the preceding args and about the function being called. It is |
4761 | not modified in this routine. | |
4697a36c MM |
4762 | NAMED is nonzero if this argument is a named parameter |
4763 | (otherwise it is an extra parameter matching an ellipsis). | |
4764 | ||
4765 | On RS/6000 the first eight words of non-FP are normally in registers | |
4766 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
4767 | Under V.4, the first 8 FP args are in registers. | |
4768 | ||
4769 | If this is floating-point and no prototype is specified, we use | |
4770 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 4771 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 4772 | so we can pass the FP value just in one register. emit_library_function |
b2d04ecf AM |
4773 | doesn't support PARALLEL anyway. |
4774 | ||
4775 | Note that for args passed by reference, function_arg will be called | |
4776 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4777 | itself. */ | |
4697a36c | 4778 | |
9390387d | 4779 | rtx |
f676971a | 4780 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 4781 | tree type, int named) |
4697a36c | 4782 | { |
4cc833b7 | 4783 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 4784 | |
a4f6c312 SS |
4785 | /* Return a marker to indicate whether CR1 needs to set or clear the |
4786 | bit that V.4 uses to say fp args were passed in registers. | |
4787 | Assume that we don't need the marker for software floating point, | |
4788 | or compiler generated library calls. */ | |
4697a36c MM |
4789 | if (mode == VOIDmode) |
4790 | { | |
f607bc57 | 4791 | if (abi == ABI_V4 |
7509c759 | 4792 | && cum->nargs_prototype < 0 |
b9599e46 FS |
4793 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
4794 | && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
7509c759 | 4795 | { |
a3170dc6 AH |
4796 | /* For the SPE, we need to crxor CR6 always. */ |
4797 | if (TARGET_SPE_ABI) | |
4798 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
4799 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
4800 | return GEN_INT (cum->call_cookie | |
4801 | | ((cum->fregno == FP_ARG_MIN_REG) | |
4802 | ? CALL_V4_SET_FP_ARGS | |
4803 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 4804 | } |
4697a36c | 4805 | |
7509c759 | 4806 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
4807 | } |
4808 | ||
0b5383eb DJ |
4809 | if (rs6000_darwin64_abi && mode == BLKmode |
4810 | && TREE_CODE (type) == RECORD_TYPE) | |
8ff40a74 | 4811 | { |
0b5383eb | 4812 | rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false); |
8ff40a74 SS |
4813 | if (rslt != NULL_RTX) |
4814 | return rslt; | |
4815 | /* Else fall through to usual handling. */ | |
4816 | } | |
4817 | ||
2858f73a | 4818 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
4819 | if (TARGET_64BIT && ! cum->prototype) |
4820 | { | |
c4ad648e AM |
4821 | /* Vector parameters get passed in vector register |
4822 | and also in GPRs or memory, in absence of prototype. */ | |
4823 | int align_words; | |
4824 | rtx slot; | |
4825 | align_words = (cum->words + 1) & ~1; | |
4826 | ||
4827 | if (align_words >= GP_ARG_NUM_REG) | |
4828 | { | |
4829 | slot = NULL_RTX; | |
4830 | } | |
4831 | else | |
4832 | { | |
4833 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4834 | } | |
4835 | return gen_rtx_PARALLEL (mode, | |
4836 | gen_rtvec (2, | |
4837 | gen_rtx_EXPR_LIST (VOIDmode, | |
4838 | slot, const0_rtx), | |
4839 | gen_rtx_EXPR_LIST (VOIDmode, | |
4840 | gen_rtx_REG (mode, cum->vregno), | |
4841 | const0_rtx))); | |
c72d6c26 HP |
4842 | } |
4843 | else | |
4844 | return gen_rtx_REG (mode, cum->vregno); | |
ad630bef DE |
4845 | else if (TARGET_ALTIVEC_ABI |
4846 | && (ALTIVEC_VECTOR_MODE (mode) | |
4847 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4848 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 4849 | { |
2858f73a | 4850 | if (named || abi == ABI_V4) |
a594a19c | 4851 | return NULL_RTX; |
0ac081f6 | 4852 | else |
a594a19c GK |
4853 | { |
4854 | /* Vector parameters to varargs functions under AIX or Darwin | |
4855 | get passed in memory and possibly also in GPRs. */ | |
ec6376ab AM |
4856 | int align, align_words, n_words; |
4857 | enum machine_mode part_mode; | |
a594a19c GK |
4858 | |
4859 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
4860 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
4861 | save area starts at offset 24 from the stack. In 64-bit mode, | |
4862 | they just have to start on an even word, since the parameter | |
4863 | save area is 16-byte aligned. */ | |
4864 | if (TARGET_32BIT) | |
4ed78545 | 4865 | align = (2 - cum->words) & 3; |
2858f73a GK |
4866 | else |
4867 | align = cum->words & 1; | |
a594a19c GK |
4868 | align_words = cum->words + align; |
4869 | ||
4870 | /* Out of registers? Memory, then. */ | |
4871 | if (align_words >= GP_ARG_NUM_REG) | |
4872 | return NULL_RTX; | |
ec6376ab AM |
4873 | |
4874 | if (TARGET_32BIT && TARGET_POWERPC64) | |
4875 | return rs6000_mixed_function_arg (mode, type, align_words); | |
4876 | ||
2858f73a GK |
4877 | /* The vector value goes in GPRs. Only the part of the |
4878 | value in GPRs is reported here. */ | |
ec6376ab AM |
4879 | part_mode = mode; |
4880 | n_words = rs6000_arg_size (mode, type); | |
4881 | if (align_words + n_words > GP_ARG_NUM_REG) | |
839a4992 | 4882 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
4883 | is either wholly in GPRs or half in GPRs and half not. */ |
4884 | part_mode = DImode; | |
ec6376ab AM |
4885 | |
4886 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 4887 | } |
0ac081f6 | 4888 | } |
f82f556d AH |
4889 | else if (TARGET_SPE_ABI && TARGET_SPE |
4890 | && (SPE_VECTOR_MODE (mode) | |
18f63bfa AH |
4891 | || (TARGET_E500_DOUBLE && (mode == DFmode |
4892 | || mode == DCmode)))) | |
a6c9bed4 | 4893 | return rs6000_spe_function_arg (cum, mode, type); |
594a51fe | 4894 | |
f607bc57 | 4895 | else if (abi == ABI_V4) |
4697a36c | 4896 | { |
a3170dc6 | 4897 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
4898 | && (mode == SFmode || mode == DFmode)) |
4899 | { | |
4900 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
4901 | return gen_rtx_REG (mode, cum->fregno); | |
4902 | else | |
b78d48dd | 4903 | return NULL_RTX; |
4cc833b7 RH |
4904 | } |
4905 | else | |
4906 | { | |
b2d04ecf | 4907 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4908 | int gregno = cum->sysv_gregno; |
4909 | ||
4ed78545 AM |
4910 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4911 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4912 | as complex int due to a historical mistake. */ | |
4913 | if (n_words == 2) | |
4914 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4915 | |
4ed78545 | 4916 | /* Multi-reg args are not split between registers and stack. */ |
ec6376ab | 4917 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
b78d48dd | 4918 | return NULL_RTX; |
ec6376ab AM |
4919 | |
4920 | if (TARGET_32BIT && TARGET_POWERPC64) | |
4921 | return rs6000_mixed_function_arg (mode, type, | |
4922 | gregno - GP_ARG_MIN_REG); | |
4923 | return gen_rtx_REG (mode, gregno); | |
4cc833b7 | 4924 | } |
4697a36c | 4925 | } |
4cc833b7 RH |
4926 | else |
4927 | { | |
294bd182 | 4928 | int align_words = rs6000_parm_start (mode, type, cum->words); |
b78d48dd | 4929 | |
2858f73a | 4930 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 | 4931 | { |
ec6376ab AM |
4932 | rtx rvec[GP_ARG_NUM_REG + 1]; |
4933 | rtx r; | |
4934 | int k; | |
c53bdcf5 AM |
4935 | bool needs_psave; |
4936 | enum machine_mode fmode = mode; | |
c53bdcf5 AM |
4937 | unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; |
4938 | ||
4939 | if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) | |
4940 | { | |
c53bdcf5 AM |
4941 | /* Currently, we only ever need one reg here because complex |
4942 | doubles are split. */ | |
37409796 | 4943 | gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode); |
ec6376ab AM |
4944 | |
4945 | /* Long double split over regs and memory. */ | |
4946 | fmode = DFmode; | |
c53bdcf5 | 4947 | } |
c53bdcf5 AM |
4948 | |
4949 | /* Do we also need to pass this arg in the parameter save | |
4950 | area? */ | |
4951 | needs_psave = (type | |
4952 | && (cum->nargs_prototype <= 0 | |
4953 | || (DEFAULT_ABI == ABI_AIX | |
de17c25f | 4954 | && TARGET_XL_COMPAT |
c53bdcf5 AM |
4955 | && align_words >= GP_ARG_NUM_REG))); |
4956 | ||
4957 | if (!needs_psave && mode == fmode) | |
ec6376ab | 4958 | return gen_rtx_REG (fmode, cum->fregno); |
c53bdcf5 | 4959 | |
ec6376ab | 4960 | k = 0; |
c53bdcf5 AM |
4961 | if (needs_psave) |
4962 | { | |
ec6376ab | 4963 | /* Describe the part that goes in gprs or the stack. |
c53bdcf5 | 4964 | This piece must come first, before the fprs. */ |
c53bdcf5 AM |
4965 | if (align_words < GP_ARG_NUM_REG) |
4966 | { | |
4967 | unsigned long n_words = rs6000_arg_size (mode, type); | |
ec6376ab AM |
4968 | |
4969 | if (align_words + n_words > GP_ARG_NUM_REG | |
4970 | || (TARGET_32BIT && TARGET_POWERPC64)) | |
4971 | { | |
4972 | /* If this is partially on the stack, then we only | |
4973 | include the portion actually in registers here. */ | |
4974 | enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; | |
4975 | rtx off; | |
2e6c9641 | 4976 | int i=0; |
c4ad648e AM |
4977 | if (align_words + n_words > GP_ARG_NUM_REG |
4978 | && (TARGET_32BIT && TARGET_POWERPC64)) | |
4979 | /* Not all of the arg fits in gprs. Say that it | |
4980 | goes in memory too, using a magic NULL_RTX | |
4981 | component. Also see comment in | |
4982 | rs6000_mixed_function_arg for why the normal | |
4983 | function_arg_partial_nregs scheme doesn't work | |
4984 | in this case. */ | |
4985 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, | |
4986 | const0_rtx); | |
ec6376ab AM |
4987 | do |
4988 | { | |
4989 | r = gen_rtx_REG (rmode, | |
4990 | GP_ARG_MIN_REG + align_words); | |
2e6c9641 | 4991 | off = GEN_INT (i++ * GET_MODE_SIZE (rmode)); |
ec6376ab AM |
4992 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); |
4993 | } | |
4994 | while (++align_words < GP_ARG_NUM_REG && --n_words != 0); | |
4995 | } | |
4996 | else | |
4997 | { | |
4998 | /* The whole arg fits in gprs. */ | |
4999 | r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5000 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5001 | } | |
c53bdcf5 | 5002 | } |
ec6376ab AM |
5003 | else |
5004 | /* It's entirely in memory. */ | |
5005 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
c53bdcf5 AM |
5006 | } |
5007 | ||
ec6376ab AM |
5008 | /* Describe where this piece goes in the fprs. */ |
5009 | r = gen_rtx_REG (fmode, cum->fregno); | |
5010 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5011 | ||
5012 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
4cc833b7 RH |
5013 | } |
5014 | else if (align_words < GP_ARG_NUM_REG) | |
b2d04ecf | 5015 | { |
ec6376ab AM |
5016 | if (TARGET_32BIT && TARGET_POWERPC64) |
5017 | return rs6000_mixed_function_arg (mode, type, align_words); | |
b2d04ecf | 5018 | |
4eeca74f AM |
5019 | if (mode == BLKmode) |
5020 | mode = Pmode; | |
5021 | ||
b2d04ecf AM |
5022 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); |
5023 | } | |
4cc833b7 RH |
5024 | else |
5025 | return NULL_RTX; | |
4697a36c | 5026 | } |
4697a36c MM |
5027 | } |
5028 | \f | |
ec6376ab | 5029 | /* For an arg passed partly in registers and partly in memory, this is |
fb63c729 AM |
5030 | the number of bytes passed in registers. For args passed entirely in |
5031 | registers or entirely in memory, zero. When an arg is described by a | |
5032 | PARALLEL, perhaps using more than one register type, this function | |
5033 | returns the number of bytes used by the first element of the PARALLEL. */ | |
4697a36c | 5034 | |
78a52f11 RH |
5035 | static int |
5036 | rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
5037 | tree type, bool named) | |
4697a36c | 5038 | { |
c53bdcf5 | 5039 | int ret = 0; |
ec6376ab | 5040 | int align_words; |
c53bdcf5 | 5041 | |
f607bc57 | 5042 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 5043 | return 0; |
4697a36c | 5044 | |
c53bdcf5 AM |
5045 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) |
5046 | && cum->nargs_prototype >= 0) | |
5047 | return 0; | |
5048 | ||
0b5383eb DJ |
5049 | /* In this complicated case we just disable the partial_nregs code. */ |
5050 | if (rs6000_darwin64_abi && mode == BLKmode | |
5051 | && TREE_CODE (type) == RECORD_TYPE | |
5052 | && int_size_in_bytes (type) > 0) | |
5053 | return 0; | |
5054 | ||
294bd182 | 5055 | align_words = rs6000_parm_start (mode, type, cum->words); |
ec6376ab AM |
5056 | |
5057 | if (USE_FP_FOR_ARG_P (cum, mode, type) | |
fb63c729 AM |
5058 | /* If we are passing this arg in the fixed parameter save area |
5059 | (gprs or memory) as well as fprs, then this function should | |
5060 | return the number of bytes passed in the parameter save area | |
5061 | rather than bytes passed in fprs. */ | |
ec6376ab AM |
5062 | && !(type |
5063 | && (cum->nargs_prototype <= 0 | |
5064 | || (DEFAULT_ABI == ABI_AIX | |
de17c25f | 5065 | && TARGET_XL_COMPAT |
ec6376ab | 5066 | && align_words >= GP_ARG_NUM_REG)))) |
4697a36c | 5067 | { |
c53bdcf5 | 5068 | if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1) |
ac7e839c | 5069 | ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8; |
c53bdcf5 | 5070 | else if (cum->nargs_prototype >= 0) |
4697a36c MM |
5071 | return 0; |
5072 | } | |
5073 | ||
ec6376ab AM |
5074 | if (align_words < GP_ARG_NUM_REG |
5075 | && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) | |
ac7e839c | 5076 | ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8); |
78a52f11 | 5077 | |
c53bdcf5 | 5078 | if (ret != 0 && TARGET_DEBUG_ARG) |
78a52f11 | 5079 | fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret); |
4697a36c | 5080 | |
c53bdcf5 | 5081 | return ret; |
4697a36c MM |
5082 | } |
5083 | \f | |
5084 | /* A C expression that indicates when an argument must be passed by | |
5085 | reference. If nonzero for an argument, a copy of that argument is | |
5086 | made in memory and a pointer to the argument is passed instead of | |
5087 | the argument itself. The pointer is passed in whatever way is | |
5088 | appropriate for passing a pointer to that type. | |
5089 | ||
b2d04ecf AM |
5090 | Under V.4, aggregates and long double are passed by reference. |
5091 | ||
5092 | As an extension to all 32-bit ABIs, AltiVec vectors are passed by | |
5093 | reference unless the AltiVec vector extension ABI is in force. | |
c8c99a68 DE |
5094 | |
5095 | As an extension to all ABIs, variable sized types are passed by | |
5096 | reference. */ | |
4697a36c | 5097 | |
8cd5a4e0 | 5098 | static bool |
f676971a | 5099 | rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
bada2eb8 DE |
5100 | enum machine_mode mode, tree type, |
5101 | bool named ATTRIBUTE_UNUSED) | |
4697a36c | 5102 | { |
bada2eb8 | 5103 | if (DEFAULT_ABI == ABI_V4 && mode == TFmode) |
4697a36c MM |
5104 | { |
5105 | if (TARGET_DEBUG_ARG) | |
bada2eb8 DE |
5106 | fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n"); |
5107 | return 1; | |
5108 | } | |
5109 | ||
5110 | if (!type) | |
5111 | return 0; | |
4697a36c | 5112 | |
bada2eb8 DE |
5113 | if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type)) |
5114 | { | |
5115 | if (TARGET_DEBUG_ARG) | |
5116 | fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n"); | |
5117 | return 1; | |
5118 | } | |
5119 | ||
5120 | if (int_size_in_bytes (type) < 0) | |
5121 | { | |
5122 | if (TARGET_DEBUG_ARG) | |
5123 | fprintf (stderr, "function_arg_pass_by_reference: variable size\n"); | |
5124 | return 1; | |
5125 | } | |
5126 | ||
5127 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector | |
5128 | modes only exist for GCC vector types if -maltivec. */ | |
5129 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
5130 | { | |
5131 | if (TARGET_DEBUG_ARG) | |
5132 | fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n"); | |
4697a36c MM |
5133 | return 1; |
5134 | } | |
b693336b PB |
5135 | |
5136 | /* Pass synthetic vectors in memory. */ | |
bada2eb8 | 5137 | if (TREE_CODE (type) == VECTOR_TYPE |
ad630bef | 5138 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
5139 | { |
5140 | static bool warned_for_pass_big_vectors = false; | |
5141 | if (TARGET_DEBUG_ARG) | |
5142 | fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n"); | |
5143 | if (!warned_for_pass_big_vectors) | |
5144 | { | |
d4ee4d25 | 5145 | warning (0, "GCC vector passed by reference: " |
b693336b PB |
5146 | "non-standard ABI extension with no compatibility guarantee"); |
5147 | warned_for_pass_big_vectors = true; | |
5148 | } | |
5149 | return 1; | |
5150 | } | |
5151 | ||
b2d04ecf | 5152 | return 0; |
4697a36c | 5153 | } |
5985c7a6 FJ |
5154 | |
5155 | static void | |
2d9db8eb | 5156 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
5157 | { |
5158 | int i; | |
5159 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
5160 | ||
5161 | if (nregs == 0) | |
5162 | return; | |
5163 | ||
c4ad648e | 5164 | for (i = 0; i < nregs; i++) |
5985c7a6 | 5165 | { |
9390387d | 5166 | rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode)); |
5985c7a6 | 5167 | if (reload_completed) |
c4ad648e AM |
5168 | { |
5169 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
5170 | tem = NULL_RTX; | |
5171 | else | |
5172 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
9390387d | 5173 | i * GET_MODE_SIZE (reg_mode)); |
c4ad648e | 5174 | } |
5985c7a6 FJ |
5175 | else |
5176 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
5177 | ||
37409796 | 5178 | gcc_assert (tem); |
5985c7a6 FJ |
5179 | |
5180 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
5181 | } | |
5182 | } | |
4697a36c MM |
5183 | \f |
5184 | /* Perform any needed actions needed for a function that is receiving a | |
f676971a | 5185 | variable number of arguments. |
4697a36c MM |
5186 | |
5187 | CUM is as above. | |
5188 | ||
5189 | MODE and TYPE are the mode and type of the current parameter. | |
5190 | ||
5191 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
5192 | that must be pushed by the prolog to pretend that our caller pushed | |
5193 | it. | |
5194 | ||
5195 | Normally, this macro will push all remaining incoming registers on the | |
5196 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
5197 | ||
c6e8c921 | 5198 | static void |
f676971a | 5199 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
c4ad648e AM |
5200 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5201 | int no_rtl) | |
4697a36c | 5202 | { |
4cc833b7 RH |
5203 | CUMULATIVE_ARGS next_cum; |
5204 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 5205 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 5206 | int first_reg_offset, set; |
4697a36c | 5207 | |
f31bf321 | 5208 | /* Skip the last named argument. */ |
d34c5b80 | 5209 | next_cum = *cum; |
594a51fe | 5210 | function_arg_advance (&next_cum, mode, type, 1, 0); |
4cc833b7 | 5211 | |
f607bc57 | 5212 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 5213 | { |
60e2d0ca | 5214 | if (! no_rtl) |
2c4974b7 | 5215 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 5216 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
5217 | |
5218 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 5219 | } |
60e2d0ca | 5220 | else |
4697a36c | 5221 | { |
d34c5b80 | 5222 | first_reg_offset = next_cum.words; |
4cc833b7 | 5223 | save_area = virtual_incoming_args_rtx; |
4697a36c | 5224 | |
fe984136 | 5225 | if (targetm.calls.must_pass_in_stack (mode, type)) |
c53bdcf5 | 5226 | first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); |
4cc833b7 | 5227 | } |
4697a36c | 5228 | |
dfafc897 | 5229 | set = get_varargs_alias_set (); |
9d30f3c1 JJ |
5230 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG |
5231 | && cfun->va_list_gpr_size) | |
4cc833b7 | 5232 | { |
9d30f3c1 JJ |
5233 | int nregs = GP_ARG_NUM_REG - first_reg_offset; |
5234 | ||
5235 | if (va_list_gpr_counter_field) | |
5236 | { | |
5237 | /* V4 va_list_gpr_size counts number of registers needed. */ | |
5238 | if (nregs > cfun->va_list_gpr_size) | |
5239 | nregs = cfun->va_list_gpr_size; | |
5240 | } | |
5241 | else | |
5242 | { | |
5243 | /* char * va_list instead counts number of bytes needed. */ | |
5244 | if (nregs > cfun->va_list_gpr_size / reg_size) | |
5245 | nregs = cfun->va_list_gpr_size / reg_size; | |
5246 | } | |
5247 | ||
dfafc897 | 5248 | mem = gen_rtx_MEM (BLKmode, |
c4ad648e | 5249 | plus_constant (save_area, |
dfafc897 | 5250 | first_reg_offset * reg_size)), |
ba4828e0 | 5251 | set_mem_alias_set (mem, set); |
8ac61af7 | 5252 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 5253 | |
f676971a | 5254 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
9d30f3c1 | 5255 | nregs); |
4697a36c MM |
5256 | } |
5257 | ||
4697a36c | 5258 | /* Save FP registers if needed. */ |
f607bc57 | 5259 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
5260 | && TARGET_HARD_FLOAT && TARGET_FPRS |
5261 | && ! no_rtl | |
9d30f3c1 JJ |
5262 | && next_cum.fregno <= FP_ARG_V4_MAX_REG |
5263 | && cfun->va_list_fpr_size) | |
4697a36c | 5264 | { |
9d30f3c1 | 5265 | int fregno = next_cum.fregno, nregs; |
9ebbca7d | 5266 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
5267 | rtx lab = gen_label_rtx (); |
5268 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 5269 | |
c4ad648e AM |
5270 | emit_jump_insn |
5271 | (gen_rtx_SET (VOIDmode, | |
5272 | pc_rtx, | |
5273 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4cc833b7 | 5274 | gen_rtx_NE (VOIDmode, cr1, |
c4ad648e | 5275 | const0_rtx), |
39403d82 | 5276 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
5277 | pc_rtx))); |
5278 | ||
9d30f3c1 JJ |
5279 | for (nregs = 0; |
5280 | fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size; | |
5281 | fregno++, off += 8, nregs++) | |
4cc833b7 | 5282 | { |
5496b36f | 5283 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
c4ad648e | 5284 | set_mem_alias_set (mem, set); |
94ff898d | 5285 | set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode)); |
dfafc897 | 5286 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4697a36c | 5287 | } |
4cc833b7 RH |
5288 | |
5289 | emit_label (lab); | |
4697a36c | 5290 | } |
4697a36c | 5291 | } |
4697a36c | 5292 | |
dfafc897 | 5293 | /* Create the va_list data type. */ |
2c4974b7 | 5294 | |
c35d187f RH |
5295 | static tree |
5296 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 5297 | { |
64c2816f | 5298 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 5299 | |
9ebbca7d GK |
5300 | /* For AIX, prefer 'char *' because that's what the system |
5301 | header files like. */ | |
f607bc57 | 5302 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 5303 | return build_pointer_type (char_type_node); |
dfafc897 | 5304 | |
f1e639b1 | 5305 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 5306 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 5307 | |
f676971a | 5308 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
9ebbca7d | 5309 | unsigned_char_type_node); |
f676971a | 5310 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), |
9ebbca7d | 5311 | unsigned_char_type_node); |
64c2816f DT |
5312 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
5313 | every user file. */ | |
5314 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
5315 | short_unsigned_type_node); | |
dfafc897 FS |
5316 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
5317 | ptr_type_node); | |
5318 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
5319 | ptr_type_node); | |
5320 | ||
9d30f3c1 JJ |
5321 | va_list_gpr_counter_field = f_gpr; |
5322 | va_list_fpr_counter_field = f_fpr; | |
5323 | ||
dfafc897 FS |
5324 | DECL_FIELD_CONTEXT (f_gpr) = record; |
5325 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 5326 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
5327 | DECL_FIELD_CONTEXT (f_ovf) = record; |
5328 | DECL_FIELD_CONTEXT (f_sav) = record; | |
5329 | ||
bab45a51 FS |
5330 | TREE_CHAIN (record) = type_decl; |
5331 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
5332 | TYPE_FIELDS (record) = f_gpr; |
5333 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
5334 | TREE_CHAIN (f_fpr) = f_res; |
5335 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
5336 | TREE_CHAIN (f_ovf) = f_sav; |
5337 | ||
5338 | layout_type (record); | |
5339 | ||
5340 | /* The correct type is an array type of one element. */ | |
5341 | return build_array_type (record, build_index_type (size_zero_node)); | |
5342 | } | |
5343 | ||
5344 | /* Implement va_start. */ | |
5345 | ||
5346 | void | |
a2369ed3 | 5347 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 5348 | { |
dfafc897 | 5349 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 5350 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 5351 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 5352 | |
dfafc897 | 5353 | /* Only SVR4 needs something special. */ |
f607bc57 | 5354 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 5355 | { |
e5faf155 | 5356 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
5357 | return; |
5358 | } | |
5359 | ||
973a648b | 5360 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 5361 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
5362 | f_res = TREE_CHAIN (f_fpr); |
5363 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
5364 | f_sav = TREE_CHAIN (f_ovf); |
5365 | ||
872a65b5 | 5366 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5367 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5368 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5369 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5370 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
dfafc897 FS |
5371 | |
5372 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 5373 | words = current_function_args_info.words; |
987732e0 DE |
5374 | n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG, |
5375 | GP_ARG_NUM_REG); | |
5376 | n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG, | |
5377 | FP_ARG_NUM_REG); | |
dfafc897 FS |
5378 | |
5379 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
5380 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
5381 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
5382 | words, n_gpr, n_fpr); | |
dfafc897 | 5383 | |
9d30f3c1 JJ |
5384 | if (cfun->va_list_gpr_size) |
5385 | { | |
5386 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, | |
5387 | build_int_cst (NULL_TREE, n_gpr)); | |
5388 | TREE_SIDE_EFFECTS (t) = 1; | |
5389 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5390 | } | |
58c8adc1 | 5391 | |
9d30f3c1 JJ |
5392 | if (cfun->va_list_fpr_size) |
5393 | { | |
5394 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, | |
5395 | build_int_cst (NULL_TREE, n_fpr)); | |
5396 | TREE_SIDE_EFFECTS (t) = 1; | |
5397 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5398 | } | |
dfafc897 FS |
5399 | |
5400 | /* Find the overflow area. */ | |
5401 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
5402 | if (words != 0) | |
5403 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
7d60be94 | 5404 | build_int_cst (NULL_TREE, words * UNITS_PER_WORD)); |
dfafc897 FS |
5405 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5406 | TREE_SIDE_EFFECTS (t) = 1; | |
5407 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5408 | ||
9d30f3c1 JJ |
5409 | /* If there were no va_arg invocations, don't set up the register |
5410 | save area. */ | |
5411 | if (!cfun->va_list_gpr_size | |
5412 | && !cfun->va_list_fpr_size | |
5413 | && n_gpr < GP_ARG_NUM_REG | |
5414 | && n_fpr < FP_ARG_V4_MAX_REG) | |
5415 | return; | |
5416 | ||
dfafc897 FS |
5417 | /* Find the register save area. */ |
5418 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
5419 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
7d60be94 | 5420 | build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE)); |
dfafc897 FS |
5421 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); |
5422 | TREE_SIDE_EFFECTS (t) = 1; | |
5423 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5424 | } | |
5425 | ||
5426 | /* Implement va_arg. */ | |
5427 | ||
23a60a04 JM |
5428 | tree |
5429 | rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) | |
cd3ce9b4 | 5430 | { |
cd3ce9b4 JM |
5431 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
5432 | tree gpr, fpr, ovf, sav, reg, t, u; | |
08b0dc1b | 5433 | int size, rsize, n_reg, sav_ofs, sav_scale; |
cd3ce9b4 JM |
5434 | tree lab_false, lab_over, addr; |
5435 | int align; | |
5436 | tree ptrtype = build_pointer_type (type); | |
5437 | ||
08b0dc1b RH |
5438 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
5439 | { | |
5440 | t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); | |
872a65b5 | 5441 | return build_va_arg_indirect_ref (t); |
08b0dc1b RH |
5442 | } |
5443 | ||
cd3ce9b4 JM |
5444 | if (DEFAULT_ABI != ABI_V4) |
5445 | { | |
08b0dc1b | 5446 | if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) |
cd3ce9b4 JM |
5447 | { |
5448 | tree elem_type = TREE_TYPE (type); | |
5449 | enum machine_mode elem_mode = TYPE_MODE (elem_type); | |
5450 | int elem_size = GET_MODE_SIZE (elem_mode); | |
5451 | ||
5452 | if (elem_size < UNITS_PER_WORD) | |
5453 | { | |
23a60a04 | 5454 | tree real_part, imag_part; |
cd3ce9b4 JM |
5455 | tree post = NULL_TREE; |
5456 | ||
23a60a04 JM |
5457 | real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5458 | &post); | |
5459 | /* Copy the value into a temporary, lest the formal temporary | |
5460 | be reused out from under us. */ | |
5461 | real_part = get_initialized_tmp_var (real_part, pre_p, &post); | |
cd3ce9b4 JM |
5462 | append_to_statement_list (post, pre_p); |
5463 | ||
23a60a04 JM |
5464 | imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5465 | post_p); | |
cd3ce9b4 | 5466 | |
23a60a04 | 5467 | return build (COMPLEX_EXPR, type, real_part, imag_part); |
cd3ce9b4 JM |
5468 | } |
5469 | } | |
5470 | ||
23a60a04 | 5471 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 JM |
5472 | } |
5473 | ||
5474 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
5475 | f_fpr = TREE_CHAIN (f_gpr); | |
5476 | f_res = TREE_CHAIN (f_fpr); | |
5477 | f_ovf = TREE_CHAIN (f_res); | |
5478 | f_sav = TREE_CHAIN (f_ovf); | |
5479 | ||
872a65b5 | 5480 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5481 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5482 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5483 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5484 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
cd3ce9b4 JM |
5485 | |
5486 | size = int_size_in_bytes (type); | |
5487 | rsize = (size + 3) / 4; | |
5488 | align = 1; | |
5489 | ||
08b0dc1b RH |
5490 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
5491 | && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode)) | |
cd3ce9b4 JM |
5492 | { |
5493 | /* FP args go in FP registers, if present. */ | |
cd3ce9b4 JM |
5494 | reg = fpr; |
5495 | n_reg = 1; | |
5496 | sav_ofs = 8*4; | |
5497 | sav_scale = 8; | |
5498 | if (TYPE_MODE (type) == DFmode) | |
5499 | align = 8; | |
5500 | } | |
5501 | else | |
5502 | { | |
5503 | /* Otherwise into GP registers. */ | |
cd3ce9b4 JM |
5504 | reg = gpr; |
5505 | n_reg = rsize; | |
5506 | sav_ofs = 0; | |
5507 | sav_scale = 4; | |
5508 | if (n_reg == 2) | |
5509 | align = 8; | |
5510 | } | |
5511 | ||
5512 | /* Pull the value out of the saved registers.... */ | |
5513 | ||
5514 | lab_over = NULL; | |
5515 | addr = create_tmp_var (ptr_type_node, "addr"); | |
5516 | DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); | |
5517 | ||
5518 | /* AltiVec vectors never go in registers when -mabi=altivec. */ | |
5519 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
5520 | align = 16; | |
5521 | else | |
5522 | { | |
5523 | lab_false = create_artificial_label (); | |
5524 | lab_over = create_artificial_label (); | |
5525 | ||
5526 | /* Long long and SPE vectors are aligned in the registers. | |
5527 | As are any other 2 gpr item such as complex int due to a | |
5528 | historical mistake. */ | |
5529 | u = reg; | |
5530 | if (n_reg == 2) | |
5531 | { | |
5532 | u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
95674810 | 5533 | size_int (n_reg - 1)); |
cd3ce9b4 JM |
5534 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u); |
5535 | } | |
5536 | ||
95674810 | 5537 | t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); |
cd3ce9b4 JM |
5538 | t = build2 (GE_EXPR, boolean_type_node, u, t); |
5539 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
5540 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
5541 | gimplify_and_add (t, pre_p); | |
5542 | ||
5543 | t = sav; | |
5544 | if (sav_ofs) | |
95674810 | 5545 | t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs)); |
cd3ce9b4 | 5546 | |
95674810 | 5547 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg)); |
cd3ce9b4 | 5548 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
95674810 | 5549 | u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale)); |
cd3ce9b4 JM |
5550 | t = build2 (PLUS_EXPR, ptr_type_node, t, u); |
5551 | ||
5552 | t = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5553 | gimplify_and_add (t, pre_p); | |
5554 | ||
5555 | t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
5556 | gimplify_and_add (t, pre_p); | |
5557 | ||
5558 | t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
5559 | append_to_statement_list (t, pre_p); | |
5560 | ||
5561 | if (n_reg > 2) | |
5562 | { | |
5563 | /* Ensure that we don't find any more args in regs. | |
5564 | Alignment has taken care of the n_reg == 2 case. */ | |
95674810 | 5565 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8)); |
cd3ce9b4 JM |
5566 | gimplify_and_add (t, pre_p); |
5567 | } | |
5568 | } | |
5569 | ||
5570 | /* ... otherwise out of the overflow area. */ | |
5571 | ||
5572 | /* Care for on-stack alignment if needed. */ | |
5573 | t = ovf; | |
5574 | if (align != 1) | |
5575 | { | |
95674810 | 5576 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1)); |
4a90aeeb | 5577 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
7d60be94 | 5578 | build_int_cst (NULL_TREE, -align)); |
cd3ce9b4 JM |
5579 | } |
5580 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
5581 | ||
5582 | u = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5583 | gimplify_and_add (u, pre_p); | |
5584 | ||
95674810 | 5585 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); |
cd3ce9b4 JM |
5586 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5587 | gimplify_and_add (t, pre_p); | |
5588 | ||
5589 | if (lab_over) | |
5590 | { | |
5591 | t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
5592 | append_to_statement_list (t, pre_p); | |
5593 | } | |
5594 | ||
08b0dc1b | 5595 | addr = fold_convert (ptrtype, addr); |
872a65b5 | 5596 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
5597 | } |
5598 | ||
0ac081f6 AH |
5599 | /* Builtins. */ |
5600 | ||
58646b77 PB |
5601 | static void |
5602 | def_builtin (int mask, const char *name, tree type, int code) | |
5603 | { | |
5604 | if (mask & target_flags) | |
5605 | { | |
5606 | if (rs6000_builtin_decls[code]) | |
5607 | abort (); | |
5608 | ||
5609 | rs6000_builtin_decls[code] = | |
5610 | lang_hooks.builtin_function (name, type, code, BUILT_IN_MD, | |
5611 | NULL, NULL_TREE); | |
5612 | } | |
5613 | } | |
0ac081f6 | 5614 | |
24408032 AH |
5615 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
5616 | ||
2212663f | 5617 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
5618 | { |
5619 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
5620 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
5621 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
5622 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
5623 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
5624 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
5625 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
5626 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
5627 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
5628 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
f676971a | 5629 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, |
aba5fb01 NS |
5630 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, |
5631 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
5632 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
5633 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
5634 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
5635 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
5636 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
5637 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
5638 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
5639 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
5640 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
5641 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
58646b77 PB |
5642 | |
5643 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD }, | |
5644 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS }, | |
5645 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD }, | |
5646 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS }, | |
5647 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM }, | |
5648 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM }, | |
5649 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM }, | |
5650 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM }, | |
5651 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM }, | |
5652 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS }, | |
5653 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS }, | |
5654 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS }, | |
5655 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB }, | |
5656 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM }, | |
5657 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL }, | |
24408032 | 5658 | }; |
2212663f | 5659 | |
95385cbb AH |
5660 | /* DST operations: void foo (void *, const int, const char). */ |
5661 | ||
5662 | static const struct builtin_description bdesc_dst[] = | |
5663 | { | |
5664 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
5665 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
5666 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
58646b77 PB |
5667 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }, |
5668 | ||
5669 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST }, | |
5670 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT }, | |
5671 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST }, | |
5672 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT } | |
95385cbb AH |
5673 | }; |
5674 | ||
2212663f | 5675 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 5676 | |
a3170dc6 | 5677 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 5678 | { |
f18c054f DB |
5679 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
5680 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
5681 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
5682 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
5683 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
5684 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
5685 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
5686 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
5687 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
5688 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
5689 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 5690 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
aba5fb01 | 5691 | { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
0ac081f6 AH |
5692 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, |
5693 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
5694 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
5695 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
5696 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
5697 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
5698 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
5699 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
5700 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
5701 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
5702 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
5703 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
5704 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
5705 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
5706 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
5707 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
5708 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
5709 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
5710 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
5711 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
5712 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
5713 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
5714 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
5715 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
5716 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
5717 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
5718 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
5719 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
5720 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
5721 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
5722 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
5723 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
5724 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
5725 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
5726 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
5727 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
5728 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
5729 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
5730 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
5731 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
5732 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
5733 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
5734 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
5735 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
5736 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
5737 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
5738 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
5739 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
5740 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
5741 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
5742 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
f96bc213 | 5743 | { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, |
f18c054f | 5744 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
5745 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
5746 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
5747 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
5748 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
5749 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
5750 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
5751 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
5752 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
5753 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
5754 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
5755 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
5756 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
5757 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
5758 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
5759 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
5760 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
5761 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
5762 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
5763 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
5764 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
5765 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
5766 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
3e0de9d1 DP |
5767 | { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
5768 | { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, | |
5769 | { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
5770 | { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, | |
5771 | { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
5772 | { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
0ac081f6 AH |
5773 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, |
5774 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
5775 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
5776 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
5777 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
5778 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
5779 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
5780 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
5781 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
5782 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
5783 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
5784 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
5785 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
5786 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
5787 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
5788 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
5789 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
5790 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 5791 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 | 5792 | |
58646b77 PB |
5793 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD }, |
5794 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP }, | |
5795 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM }, | |
5796 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM }, | |
5797 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM }, | |
5798 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC }, | |
5799 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS }, | |
5800 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS }, | |
5801 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS }, | |
5802 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS }, | |
5803 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS }, | |
5804 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS }, | |
5805 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS }, | |
5806 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND }, | |
5807 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC }, | |
5808 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG }, | |
5809 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW }, | |
5810 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW }, | |
5811 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH }, | |
5812 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH }, | |
5813 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB }, | |
5814 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB }, | |
5815 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB }, | |
5816 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ }, | |
5817 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP }, | |
5818 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW }, | |
5819 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH }, | |
5820 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB }, | |
5821 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE }, | |
5822 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT }, | |
5823 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP }, | |
5824 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW }, | |
5825 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW }, | |
5826 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH }, | |
5827 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH }, | |
5828 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB }, | |
5829 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB }, | |
5830 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE }, | |
5831 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT }, | |
5832 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX }, | |
5833 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP }, | |
5834 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW }, | |
5835 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW }, | |
5836 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH }, | |
5837 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH }, | |
5838 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB }, | |
5839 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB }, | |
5840 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH }, | |
5841 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW }, | |
5842 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH }, | |
5843 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB }, | |
5844 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL }, | |
5845 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW }, | |
5846 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH }, | |
5847 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB }, | |
5848 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN }, | |
5849 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP }, | |
5850 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW }, | |
5851 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW }, | |
5852 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH }, | |
5853 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH }, | |
5854 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB }, | |
5855 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB }, | |
5856 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE }, | |
5857 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB }, | |
5858 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB }, | |
5859 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH }, | |
5860 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH }, | |
5861 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO }, | |
5862 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH }, | |
5863 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH }, | |
5864 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB }, | |
5865 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB }, | |
5866 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR }, | |
5867 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR }, | |
5868 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK }, | |
5869 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM }, | |
5870 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM }, | |
5871 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX }, | |
5872 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS }, | |
5873 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS }, | |
5874 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS }, | |
5875 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS }, | |
5876 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS }, | |
5877 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU }, | |
5878 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS }, | |
5879 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS }, | |
5880 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL }, | |
5881 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW }, | |
5882 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH }, | |
5883 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB }, | |
5884 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL }, | |
5885 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW }, | |
5886 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH }, | |
5887 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB }, | |
5888 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL }, | |
5889 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO }, | |
5890 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR }, | |
5891 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW }, | |
5892 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH }, | |
5893 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB }, | |
5894 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA }, | |
5895 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW }, | |
5896 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH }, | |
5897 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB }, | |
5898 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL }, | |
5899 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO }, | |
5900 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB }, | |
5901 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP }, | |
5902 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM }, | |
5903 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM }, | |
5904 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM }, | |
5905 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC }, | |
5906 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS }, | |
5907 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS }, | |
5908 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS }, | |
5909 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS }, | |
5910 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS }, | |
5911 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS }, | |
5912 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS }, | |
5913 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S }, | |
5914 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS }, | |
5915 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS }, | |
5916 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS }, | |
5917 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S }, | |
5918 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS }, | |
5919 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR }, | |
5920 | ||
a3170dc6 AH |
5921 | /* Place holder, leave as first spe builtin. */ |
5922 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
5923 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
5924 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
5925 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
5926 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
5927 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
5928 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
5929 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
5930 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
5931 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
5932 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
5933 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
5934 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
5935 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
5936 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
5937 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
5938 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
5939 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
5940 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
5941 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
5942 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
5943 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
5944 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
5945 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
5946 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
5947 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
5948 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
5949 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
5950 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
5951 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
5952 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
5953 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
5954 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
5955 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
5956 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
5957 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
5958 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
5959 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
5960 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
5961 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
5962 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
5963 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
5964 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
5965 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
5966 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
5967 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
5968 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
5969 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
5970 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
5971 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
5972 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
5973 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
5974 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
5975 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
5976 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
5977 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
5978 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
5979 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
5980 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
5981 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
5982 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
5983 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
5984 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
5985 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
5986 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
5987 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
5988 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
5989 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
5990 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
5991 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
5992 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
5993 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
5994 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
5995 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
5996 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
5997 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
5998 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
5999 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
6000 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
6001 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
6002 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
6003 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
6004 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
6005 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
6006 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
6007 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
6008 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
6009 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
6010 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
6011 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
6012 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
6013 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
6014 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
6015 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
6016 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
6017 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
6018 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
6019 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
6020 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
6021 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
6022 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
6023 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
6024 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
6025 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
6026 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
6027 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
6028 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
6029 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
6030 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
6031 | ||
6032 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
6033 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
6034 | ||
6035 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
6036 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
6037 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
6038 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
6039 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
6040 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
6041 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
6042 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
6043 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
6044 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
6045 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
6046 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
6047 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
6048 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
6049 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
6050 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
6051 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
6052 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
6053 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
6054 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
6055 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
6056 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
6057 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
6058 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
6059 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
6060 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
6061 | ||
6062 | /* Place-holder. Leave as last binary SPE builtin. */ | |
58646b77 | 6063 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR } |
ae4b4a02 AH |
6064 | }; |
6065 | ||
6066 | /* AltiVec predicates. */ | |
6067 | ||
6068 | struct builtin_description_predicates | |
6069 | { | |
6070 | const unsigned int mask; | |
6071 | const enum insn_code icode; | |
6072 | const char *opcode; | |
6073 | const char *const name; | |
6074 | const enum rs6000_builtins code; | |
6075 | }; | |
6076 | ||
6077 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
6078 | { | |
6079 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
6080 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
6081 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
6082 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
6083 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
6084 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
6085 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
6086 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
6087 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
6088 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
6089 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
6090 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
58646b77 PB |
6091 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }, |
6092 | ||
6093 | { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P }, | |
6094 | { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P }, | |
6095 | { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P } | |
0ac081f6 | 6096 | }; |
24408032 | 6097 | |
a3170dc6 AH |
6098 | /* SPE predicates. */ |
6099 | static struct builtin_description bdesc_spe_predicates[] = | |
6100 | { | |
6101 | /* Place-holder. Leave as first. */ | |
6102 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
6103 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
6104 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
6105 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
6106 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
6107 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
6108 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
6109 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
6110 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
6111 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
6112 | /* Place-holder. Leave as last. */ | |
6113 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
6114 | }; | |
6115 | ||
6116 | /* SPE evsel predicates. */ | |
6117 | static struct builtin_description bdesc_spe_evsel[] = | |
6118 | { | |
6119 | /* Place-holder. Leave as first. */ | |
6120 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
6121 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
6122 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
6123 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
6124 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
6125 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
6126 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
6127 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
6128 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
6129 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
6130 | /* Place-holder. Leave as last. */ | |
6131 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
6132 | }; | |
6133 | ||
b6d08ca1 | 6134 | /* ABS* operations. */ |
100c4561 AH |
6135 | |
6136 | static const struct builtin_description bdesc_abs[] = | |
6137 | { | |
6138 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
6139 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
6140 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
6141 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
6142 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
6143 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
6144 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
6145 | }; | |
6146 | ||
617e0e1d DB |
6147 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
6148 | foo (VECa). */ | |
24408032 | 6149 | |
a3170dc6 | 6150 | static struct builtin_description bdesc_1arg[] = |
2212663f | 6151 | { |
617e0e1d DB |
6152 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
6153 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
6154 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
6155 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
6156 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
6157 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
6158 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
6159 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
6160 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
6161 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
6162 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
6163 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
6164 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
6165 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
6166 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
6167 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
6168 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 | 6169 | |
58646b77 PB |
6170 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS }, |
6171 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS }, | |
6172 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL }, | |
6173 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE }, | |
6174 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR }, | |
6175 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE }, | |
6176 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR }, | |
6177 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE }, | |
6178 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND }, | |
6179 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE }, | |
6180 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC }, | |
6181 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH }, | |
6182 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH }, | |
6183 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX }, | |
6184 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB }, | |
6185 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL }, | |
6186 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX }, | |
6187 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH }, | |
6188 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB }, | |
6189 | ||
a3170dc6 AH |
6190 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and |
6191 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
6192 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
6193 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
6194 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
6195 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
6196 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
6197 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
6198 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
6199 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
6200 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
6201 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
6202 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
6203 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
6204 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
6205 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
6206 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
6207 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
6208 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
6209 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
6210 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
6211 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
6212 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
6213 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
6214 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
6a599451 | 6215 | { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, |
a3170dc6 AH |
6216 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, |
6217 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
6218 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
6219 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
6220 | |
6221 | /* Place-holder. Leave as last unary SPE builtin. */ | |
58646b77 | 6222 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW } |
2212663f DB |
6223 | }; |
6224 | ||
6225 | static rtx | |
a2369ed3 | 6226 | rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6227 | { |
6228 | rtx pat; | |
6229 | tree arg0 = TREE_VALUE (arglist); | |
6230 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6231 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6232 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6233 | ||
0559cc77 DE |
6234 | if (icode == CODE_FOR_nothing) |
6235 | /* Builtin not supported on this processor. */ | |
6236 | return 0; | |
6237 | ||
20e26713 AH |
6238 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6239 | if (arg0 == error_mark_node) | |
9a171fcd | 6240 | return const0_rtx; |
20e26713 | 6241 | |
0559cc77 DE |
6242 | if (icode == CODE_FOR_altivec_vspltisb |
6243 | || icode == CODE_FOR_altivec_vspltish | |
6244 | || icode == CODE_FOR_altivec_vspltisw | |
6245 | || icode == CODE_FOR_spe_evsplatfi | |
6246 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
6247 | { |
6248 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 | 6249 | if (GET_CODE (op0) != CONST_INT |
afca671b DP |
6250 | || INTVAL (op0) > 15 |
6251 | || INTVAL (op0) < -16) | |
b44140e7 AH |
6252 | { |
6253 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 6254 | return const0_rtx; |
b44140e7 | 6255 | } |
b44140e7 AH |
6256 | } |
6257 | ||
c62f2db5 | 6258 | if (target == 0 |
2212663f DB |
6259 | || GET_MODE (target) != tmode |
6260 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6261 | target = gen_reg_rtx (tmode); | |
6262 | ||
6263 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6264 | op0 = copy_to_mode_reg (mode0, op0); | |
6265 | ||
6266 | pat = GEN_FCN (icode) (target, op0); | |
6267 | if (! pat) | |
6268 | return 0; | |
6269 | emit_insn (pat); | |
0ac081f6 | 6270 | |
2212663f DB |
6271 | return target; |
6272 | } | |
ae4b4a02 | 6273 | |
100c4561 | 6274 | static rtx |
a2369ed3 | 6275 | altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) |
100c4561 AH |
6276 | { |
6277 | rtx pat, scratch1, scratch2; | |
6278 | tree arg0 = TREE_VALUE (arglist); | |
6279 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6280 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6281 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6282 | ||
6283 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6284 | if (arg0 == error_mark_node) | |
9a171fcd | 6285 | return const0_rtx; |
100c4561 AH |
6286 | |
6287 | if (target == 0 | |
6288 | || GET_MODE (target) != tmode | |
6289 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6290 | target = gen_reg_rtx (tmode); | |
6291 | ||
6292 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6293 | op0 = copy_to_mode_reg (mode0, op0); | |
6294 | ||
6295 | scratch1 = gen_reg_rtx (mode0); | |
6296 | scratch2 = gen_reg_rtx (mode0); | |
6297 | ||
6298 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
6299 | if (! pat) | |
6300 | return 0; | |
6301 | emit_insn (pat); | |
6302 | ||
6303 | return target; | |
6304 | } | |
6305 | ||
0ac081f6 | 6306 | static rtx |
a2369ed3 | 6307 | rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
0ac081f6 AH |
6308 | { |
6309 | rtx pat; | |
6310 | tree arg0 = TREE_VALUE (arglist); | |
6311 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6312 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6313 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6314 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6315 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6316 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6317 | ||
0559cc77 DE |
6318 | if (icode == CODE_FOR_nothing) |
6319 | /* Builtin not supported on this processor. */ | |
6320 | return 0; | |
6321 | ||
20e26713 AH |
6322 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6323 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6324 | return const0_rtx; |
20e26713 | 6325 | |
0559cc77 DE |
6326 | if (icode == CODE_FOR_altivec_vcfux |
6327 | || icode == CODE_FOR_altivec_vcfsx | |
6328 | || icode == CODE_FOR_altivec_vctsxs | |
6329 | || icode == CODE_FOR_altivec_vctuxs | |
6330 | || icode == CODE_FOR_altivec_vspltb | |
6331 | || icode == CODE_FOR_altivec_vsplth | |
6332 | || icode == CODE_FOR_altivec_vspltw | |
6333 | || icode == CODE_FOR_spe_evaddiw | |
6334 | || icode == CODE_FOR_spe_evldd | |
6335 | || icode == CODE_FOR_spe_evldh | |
6336 | || icode == CODE_FOR_spe_evldw | |
6337 | || icode == CODE_FOR_spe_evlhhesplat | |
6338 | || icode == CODE_FOR_spe_evlhhossplat | |
6339 | || icode == CODE_FOR_spe_evlhhousplat | |
6340 | || icode == CODE_FOR_spe_evlwhe | |
6341 | || icode == CODE_FOR_spe_evlwhos | |
6342 | || icode == CODE_FOR_spe_evlwhou | |
6343 | || icode == CODE_FOR_spe_evlwhsplat | |
6344 | || icode == CODE_FOR_spe_evlwwsplat | |
6345 | || icode == CODE_FOR_spe_evrlwi | |
6346 | || icode == CODE_FOR_spe_evslwi | |
6347 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 6348 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 6349 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
6350 | { |
6351 | /* Only allow 5-bit unsigned literals. */ | |
8bb418a3 | 6352 | STRIP_NOPS (arg1); |
b44140e7 AH |
6353 | if (TREE_CODE (arg1) != INTEGER_CST |
6354 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6355 | { | |
6356 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 6357 | return const0_rtx; |
b44140e7 | 6358 | } |
b44140e7 AH |
6359 | } |
6360 | ||
c62f2db5 | 6361 | if (target == 0 |
0ac081f6 AH |
6362 | || GET_MODE (target) != tmode |
6363 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6364 | target = gen_reg_rtx (tmode); | |
6365 | ||
6366 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6367 | op0 = copy_to_mode_reg (mode0, op0); | |
6368 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6369 | op1 = copy_to_mode_reg (mode1, op1); | |
6370 | ||
6371 | pat = GEN_FCN (icode) (target, op0, op1); | |
6372 | if (! pat) | |
6373 | return 0; | |
6374 | emit_insn (pat); | |
6375 | ||
6376 | return target; | |
6377 | } | |
6525c0e7 | 6378 | |
ae4b4a02 | 6379 | static rtx |
f676971a | 6380 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
a2369ed3 | 6381 | tree arglist, rtx target) |
ae4b4a02 AH |
6382 | { |
6383 | rtx pat, scratch; | |
6384 | tree cr6_form = TREE_VALUE (arglist); | |
6385 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6386 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6387 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6388 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6389 | enum machine_mode tmode = SImode; | |
6390 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6391 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6392 | int cr6_form_int; | |
6393 | ||
6394 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
6395 | { | |
6396 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 6397 | return const0_rtx; |
ae4b4a02 AH |
6398 | } |
6399 | else | |
6400 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
6401 | ||
37409796 | 6402 | gcc_assert (mode0 == mode1); |
ae4b4a02 AH |
6403 | |
6404 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6405 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6406 | return const0_rtx; |
ae4b4a02 AH |
6407 | |
6408 | if (target == 0 | |
6409 | || GET_MODE (target) != tmode | |
6410 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6411 | target = gen_reg_rtx (tmode); | |
6412 | ||
6413 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6414 | op0 = copy_to_mode_reg (mode0, op0); | |
6415 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6416 | op1 = copy_to_mode_reg (mode1, op1); | |
6417 | ||
6418 | scratch = gen_reg_rtx (mode0); | |
6419 | ||
6420 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 6421 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
6422 | if (! pat) |
6423 | return 0; | |
6424 | emit_insn (pat); | |
6425 | ||
6426 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
6427 | different operations, but the bits in CR6 will be different | |
6428 | depending on what information we want. So we have to play tricks | |
6429 | with CR6 to get the right bits out. | |
6430 | ||
6431 | If you think this is disgusting, look at the specs for the | |
6432 | AltiVec predicates. */ | |
6433 | ||
c4ad648e AM |
6434 | switch (cr6_form_int) |
6435 | { | |
6436 | case 0: | |
6437 | emit_insn (gen_cr6_test_for_zero (target)); | |
6438 | break; | |
6439 | case 1: | |
6440 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
6441 | break; | |
6442 | case 2: | |
6443 | emit_insn (gen_cr6_test_for_lt (target)); | |
6444 | break; | |
6445 | case 3: | |
6446 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
6447 | break; | |
6448 | default: | |
6449 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
6450 | break; | |
6451 | } | |
ae4b4a02 AH |
6452 | |
6453 | return target; | |
6454 | } | |
6455 | ||
b4a62fa0 | 6456 | static rtx |
38f391a5 | 6457 | altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) |
b4a62fa0 SB |
6458 | { |
6459 | rtx pat, addr; | |
6460 | tree arg0 = TREE_VALUE (arglist); | |
6461 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6462 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6463 | enum machine_mode mode0 = Pmode; | |
6464 | enum machine_mode mode1 = Pmode; | |
6465 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6466 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6467 | ||
6468 | if (icode == CODE_FOR_nothing) | |
6469 | /* Builtin not supported on this processor. */ | |
6470 | return 0; | |
6471 | ||
6472 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6473 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6474 | return const0_rtx; | |
6475 | ||
6476 | if (target == 0 | |
6477 | || GET_MODE (target) != tmode | |
6478 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6479 | target = gen_reg_rtx (tmode); | |
6480 | ||
f676971a | 6481 | op1 = copy_to_mode_reg (mode1, op1); |
b4a62fa0 SB |
6482 | |
6483 | if (op0 == const0_rtx) | |
6484 | { | |
6485 | addr = gen_rtx_MEM (tmode, op1); | |
6486 | } | |
6487 | else | |
6488 | { | |
6489 | op0 = copy_to_mode_reg (mode0, op0); | |
6490 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
6491 | } | |
6492 | ||
6493 | pat = GEN_FCN (icode) (target, addr); | |
6494 | ||
6495 | if (! pat) | |
6496 | return 0; | |
6497 | emit_insn (pat); | |
6498 | ||
6499 | return target; | |
6500 | } | |
6501 | ||
61bea3b0 AH |
6502 | static rtx |
6503 | spe_expand_stv_builtin (enum insn_code icode, tree arglist) | |
6504 | { | |
6505 | tree arg0 = TREE_VALUE (arglist); | |
6506 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6507 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6508 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6509 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6510 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6511 | rtx pat; | |
6512 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
6513 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
6514 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
6515 | ||
6516 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6517 | if (arg0 == error_mark_node | |
6518 | || arg1 == error_mark_node | |
6519 | || arg2 == error_mark_node) | |
6520 | return const0_rtx; | |
6521 | ||
6522 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
6523 | op0 = copy_to_mode_reg (mode2, op0); | |
6524 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
6525 | op1 = copy_to_mode_reg (mode0, op1); | |
6526 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6527 | op2 = copy_to_mode_reg (mode1, op2); | |
6528 | ||
6529 | pat = GEN_FCN (icode) (op1, op2, op0); | |
6530 | if (pat) | |
6531 | emit_insn (pat); | |
6532 | return NULL_RTX; | |
6533 | } | |
6534 | ||
6525c0e7 | 6535 | static rtx |
a2369ed3 | 6536 | altivec_expand_stv_builtin (enum insn_code icode, tree arglist) |
6525c0e7 AH |
6537 | { |
6538 | tree arg0 = TREE_VALUE (arglist); | |
6539 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6540 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6541 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6542 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6543 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
b4a62fa0 SB |
6544 | rtx pat, addr; |
6545 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6546 | enum machine_mode mode1 = Pmode; | |
6547 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
6548 | |
6549 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6550 | if (arg0 == error_mark_node | |
6551 | || arg1 == error_mark_node | |
6552 | || arg2 == error_mark_node) | |
9a171fcd | 6553 | return const0_rtx; |
6525c0e7 | 6554 | |
b4a62fa0 SB |
6555 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
6556 | op0 = copy_to_mode_reg (tmode, op0); | |
6557 | ||
f676971a | 6558 | op2 = copy_to_mode_reg (mode2, op2); |
b4a62fa0 SB |
6559 | |
6560 | if (op1 == const0_rtx) | |
6561 | { | |
6562 | addr = gen_rtx_MEM (tmode, op2); | |
6563 | } | |
6564 | else | |
6565 | { | |
6566 | op1 = copy_to_mode_reg (mode1, op1); | |
6567 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
6568 | } | |
6525c0e7 | 6569 | |
b4a62fa0 | 6570 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
6571 | if (pat) |
6572 | emit_insn (pat); | |
6573 | return NULL_RTX; | |
6574 | } | |
6575 | ||
2212663f | 6576 | static rtx |
a2369ed3 | 6577 | rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6578 | { |
6579 | rtx pat; | |
6580 | tree arg0 = TREE_VALUE (arglist); | |
6581 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6582 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6583 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6584 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6585 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6586 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6587 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6588 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6589 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 6590 | |
774b5662 DE |
6591 | if (icode == CODE_FOR_nothing) |
6592 | /* Builtin not supported on this processor. */ | |
6593 | return 0; | |
6594 | ||
20e26713 AH |
6595 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6596 | if (arg0 == error_mark_node | |
6597 | || arg1 == error_mark_node | |
6598 | || arg2 == error_mark_node) | |
9a171fcd | 6599 | return const0_rtx; |
20e26713 | 6600 | |
aba5fb01 NS |
6601 | if (icode == CODE_FOR_altivec_vsldoi_v4sf |
6602 | || icode == CODE_FOR_altivec_vsldoi_v4si | |
6603 | || icode == CODE_FOR_altivec_vsldoi_v8hi | |
6604 | || icode == CODE_FOR_altivec_vsldoi_v16qi) | |
b44140e7 AH |
6605 | { |
6606 | /* Only allow 4-bit unsigned literals. */ | |
8bb418a3 | 6607 | STRIP_NOPS (arg2); |
b44140e7 AH |
6608 | if (TREE_CODE (arg2) != INTEGER_CST |
6609 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
6610 | { | |
6611 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 6612 | return const0_rtx; |
b44140e7 | 6613 | } |
b44140e7 AH |
6614 | } |
6615 | ||
c62f2db5 | 6616 | if (target == 0 |
2212663f DB |
6617 | || GET_MODE (target) != tmode |
6618 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6619 | target = gen_reg_rtx (tmode); | |
6620 | ||
6621 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6622 | op0 = copy_to_mode_reg (mode0, op0); | |
6623 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6624 | op1 = copy_to_mode_reg (mode1, op1); | |
6625 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
6626 | op2 = copy_to_mode_reg (mode2, op2); | |
6627 | ||
6628 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
6629 | if (! pat) | |
6630 | return 0; | |
6631 | emit_insn (pat); | |
6632 | ||
6633 | return target; | |
6634 | } | |
92898235 | 6635 | |
3a9b8c7e | 6636 | /* Expand the lvx builtins. */ |
0ac081f6 | 6637 | static rtx |
a2369ed3 | 6638 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 6639 | { |
0ac081f6 AH |
6640 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6641 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 6642 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
6643 | tree arg0; |
6644 | enum machine_mode tmode, mode0; | |
7c3abc73 | 6645 | rtx pat, op0; |
3a9b8c7e | 6646 | enum insn_code icode; |
92898235 | 6647 | |
0ac081f6 AH |
6648 | switch (fcode) |
6649 | { | |
f18c054f | 6650 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
81466555 | 6651 | icode = CODE_FOR_altivec_lvx_v16qi; |
3a9b8c7e | 6652 | break; |
f18c054f | 6653 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
81466555 | 6654 | icode = CODE_FOR_altivec_lvx_v8hi; |
3a9b8c7e AH |
6655 | break; |
6656 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
81466555 | 6657 | icode = CODE_FOR_altivec_lvx_v4si; |
3a9b8c7e AH |
6658 | break; |
6659 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
81466555 | 6660 | icode = CODE_FOR_altivec_lvx_v4sf; |
3a9b8c7e AH |
6661 | break; |
6662 | default: | |
6663 | *expandedp = false; | |
6664 | return NULL_RTX; | |
6665 | } | |
0ac081f6 | 6666 | |
3a9b8c7e | 6667 | *expandedp = true; |
f18c054f | 6668 | |
3a9b8c7e AH |
6669 | arg0 = TREE_VALUE (arglist); |
6670 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6671 | tmode = insn_data[icode].operand[0].mode; | |
6672 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 6673 | |
3a9b8c7e AH |
6674 | if (target == 0 |
6675 | || GET_MODE (target) != tmode | |
6676 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6677 | target = gen_reg_rtx (tmode); | |
24408032 | 6678 | |
3a9b8c7e AH |
6679 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
6680 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 6681 | |
3a9b8c7e AH |
6682 | pat = GEN_FCN (icode) (target, op0); |
6683 | if (! pat) | |
6684 | return 0; | |
6685 | emit_insn (pat); | |
6686 | return target; | |
6687 | } | |
f18c054f | 6688 | |
3a9b8c7e AH |
6689 | /* Expand the stvx builtins. */ |
6690 | static rtx | |
f676971a | 6691 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 6692 | bool *expandedp) |
3a9b8c7e AH |
6693 | { |
6694 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6695 | tree arglist = TREE_OPERAND (exp, 1); | |
6696 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6697 | tree arg0, arg1; | |
6698 | enum machine_mode mode0, mode1; | |
7c3abc73 | 6699 | rtx pat, op0, op1; |
3a9b8c7e | 6700 | enum insn_code icode; |
f18c054f | 6701 | |
3a9b8c7e AH |
6702 | switch (fcode) |
6703 | { | |
6704 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
81466555 | 6705 | icode = CODE_FOR_altivec_stvx_v16qi; |
3a9b8c7e AH |
6706 | break; |
6707 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
81466555 | 6708 | icode = CODE_FOR_altivec_stvx_v8hi; |
3a9b8c7e AH |
6709 | break; |
6710 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
81466555 | 6711 | icode = CODE_FOR_altivec_stvx_v4si; |
3a9b8c7e AH |
6712 | break; |
6713 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
81466555 | 6714 | icode = CODE_FOR_altivec_stvx_v4sf; |
3a9b8c7e AH |
6715 | break; |
6716 | default: | |
6717 | *expandedp = false; | |
6718 | return NULL_RTX; | |
6719 | } | |
24408032 | 6720 | |
3a9b8c7e AH |
6721 | arg0 = TREE_VALUE (arglist); |
6722 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6723 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6724 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6725 | mode0 = insn_data[icode].operand[0].mode; | |
6726 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 6727 | |
3a9b8c7e AH |
6728 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6729 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
6730 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
6731 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 6732 | |
3a9b8c7e AH |
6733 | pat = GEN_FCN (icode) (op0, op1); |
6734 | if (pat) | |
6735 | emit_insn (pat); | |
f18c054f | 6736 | |
3a9b8c7e AH |
6737 | *expandedp = true; |
6738 | return NULL_RTX; | |
6739 | } | |
f18c054f | 6740 | |
3a9b8c7e AH |
6741 | /* Expand the dst builtins. */ |
6742 | static rtx | |
f676971a | 6743 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 6744 | bool *expandedp) |
3a9b8c7e AH |
6745 | { |
6746 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6747 | tree arglist = TREE_OPERAND (exp, 1); | |
6748 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6749 | tree arg0, arg1, arg2; | |
6750 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 6751 | rtx pat, op0, op1, op2; |
3a9b8c7e | 6752 | struct builtin_description *d; |
a3170dc6 | 6753 | size_t i; |
f18c054f | 6754 | |
3a9b8c7e | 6755 | *expandedp = false; |
f18c054f | 6756 | |
3a9b8c7e AH |
6757 | /* Handle DST variants. */ |
6758 | d = (struct builtin_description *) bdesc_dst; | |
6759 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
6760 | if (d->code == fcode) | |
6761 | { | |
6762 | arg0 = TREE_VALUE (arglist); | |
6763 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6764 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6765 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6766 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6767 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6768 | mode0 = insn_data[d->icode].operand[0].mode; | |
6769 | mode1 = insn_data[d->icode].operand[1].mode; | |
6770 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 6771 | |
3a9b8c7e AH |
6772 | /* Invalid arguments, bail out before generating bad rtl. */ |
6773 | if (arg0 == error_mark_node | |
6774 | || arg1 == error_mark_node | |
6775 | || arg2 == error_mark_node) | |
6776 | return const0_rtx; | |
f18c054f | 6777 | |
86e7df90 | 6778 | *expandedp = true; |
8bb418a3 | 6779 | STRIP_NOPS (arg2); |
3a9b8c7e AH |
6780 | if (TREE_CODE (arg2) != INTEGER_CST |
6781 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
6782 | { | |
9e637a26 | 6783 | error ("argument to %qs must be a 2-bit unsigned literal", d->name); |
3a9b8c7e AH |
6784 | return const0_rtx; |
6785 | } | |
f18c054f | 6786 | |
3a9b8c7e | 6787 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
666158b9 | 6788 | op0 = copy_to_mode_reg (Pmode, op0); |
3a9b8c7e AH |
6789 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
6790 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 6791 | |
3a9b8c7e AH |
6792 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
6793 | if (pat != 0) | |
6794 | emit_insn (pat); | |
f18c054f | 6795 | |
3a9b8c7e AH |
6796 | return NULL_RTX; |
6797 | } | |
f18c054f | 6798 | |
3a9b8c7e AH |
6799 | return NULL_RTX; |
6800 | } | |
24408032 | 6801 | |
3a9b8c7e AH |
6802 | /* Expand the builtin in EXP and store the result in TARGET. Store |
6803 | true in *EXPANDEDP if we found a builtin to expand. */ | |
6804 | static rtx | |
a2369ed3 | 6805 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e AH |
6806 | { |
6807 | struct builtin_description *d; | |
6808 | struct builtin_description_predicates *dp; | |
6809 | size_t i; | |
6810 | enum insn_code icode; | |
6811 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6812 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
6813 | tree arg0; |
6814 | rtx op0, pat; | |
6815 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 6816 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 6817 | |
58646b77 PB |
6818 | if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
6819 | && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST) | |
6820 | { | |
6821 | *expandedp = true; | |
6822 | error ("unresolved overload for Altivec builtin %qE", fndecl); | |
6823 | return const0_rtx; | |
6824 | } | |
6825 | ||
3a9b8c7e AH |
6826 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
6827 | if (*expandedp) | |
6828 | return target; | |
0ac081f6 | 6829 | |
3a9b8c7e AH |
6830 | target = altivec_expand_st_builtin (exp, target, expandedp); |
6831 | if (*expandedp) | |
6832 | return target; | |
6833 | ||
6834 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
6835 | if (*expandedp) | |
6836 | return target; | |
6837 | ||
6838 | *expandedp = true; | |
95385cbb | 6839 | |
3a9b8c7e AH |
6840 | switch (fcode) |
6841 | { | |
6525c0e7 AH |
6842 | case ALTIVEC_BUILTIN_STVX: |
6843 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
6844 | case ALTIVEC_BUILTIN_STVEBX: | |
6845 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
6846 | case ALTIVEC_BUILTIN_STVEHX: | |
6847 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
6848 | case ALTIVEC_BUILTIN_STVEWX: | |
6849 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
6850 | case ALTIVEC_BUILTIN_STVXL: | |
6851 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 6852 | |
95385cbb AH |
6853 | case ALTIVEC_BUILTIN_MFVSCR: |
6854 | icode = CODE_FOR_altivec_mfvscr; | |
6855 | tmode = insn_data[icode].operand[0].mode; | |
6856 | ||
6857 | if (target == 0 | |
6858 | || GET_MODE (target) != tmode | |
6859 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6860 | target = gen_reg_rtx (tmode); | |
f676971a | 6861 | |
95385cbb | 6862 | pat = GEN_FCN (icode) (target); |
0ac081f6 AH |
6863 | if (! pat) |
6864 | return 0; | |
6865 | emit_insn (pat); | |
95385cbb AH |
6866 | return target; |
6867 | ||
6868 | case ALTIVEC_BUILTIN_MTVSCR: | |
6869 | icode = CODE_FOR_altivec_mtvscr; | |
6870 | arg0 = TREE_VALUE (arglist); | |
6871 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6872 | mode0 = insn_data[icode].operand[0].mode; | |
6873 | ||
6874 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6875 | if (arg0 == error_mark_node) | |
9a171fcd | 6876 | return const0_rtx; |
95385cbb AH |
6877 | |
6878 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6879 | op0 = copy_to_mode_reg (mode0, op0); | |
6880 | ||
6881 | pat = GEN_FCN (icode) (op0); | |
6882 | if (pat) | |
6883 | emit_insn (pat); | |
6884 | return NULL_RTX; | |
3a9b8c7e | 6885 | |
95385cbb AH |
6886 | case ALTIVEC_BUILTIN_DSSALL: |
6887 | emit_insn (gen_altivec_dssall ()); | |
6888 | return NULL_RTX; | |
6889 | ||
6890 | case ALTIVEC_BUILTIN_DSS: | |
6891 | icode = CODE_FOR_altivec_dss; | |
6892 | arg0 = TREE_VALUE (arglist); | |
8bb418a3 | 6893 | STRIP_NOPS (arg0); |
95385cbb AH |
6894 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
6895 | mode0 = insn_data[icode].operand[0].mode; | |
6896 | ||
6897 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6898 | if (arg0 == error_mark_node) | |
9a171fcd | 6899 | return const0_rtx; |
95385cbb | 6900 | |
b44140e7 AH |
6901 | if (TREE_CODE (arg0) != INTEGER_CST |
6902 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
6903 | { | |
6904 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 6905 | return const0_rtx; |
b44140e7 AH |
6906 | } |
6907 | ||
95385cbb AH |
6908 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6909 | op0 = copy_to_mode_reg (mode0, op0); | |
6910 | ||
6911 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 AH |
6912 | return NULL_RTX; |
6913 | } | |
24408032 | 6914 | |
100c4561 AH |
6915 | /* Expand abs* operations. */ |
6916 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 6917 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
6918 | if (d->code == fcode) |
6919 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
6920 | ||
ae4b4a02 AH |
6921 | /* Expand the AltiVec predicates. */ |
6922 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 6923 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 | 6924 | if (dp->code == fcode) |
c4ad648e AM |
6925 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, |
6926 | arglist, target); | |
ae4b4a02 | 6927 | |
6525c0e7 AH |
6928 | /* LV* are funky. We initialized them differently. */ |
6929 | switch (fcode) | |
6930 | { | |
6931 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 6932 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
c4ad648e | 6933 | arglist, target); |
6525c0e7 | 6934 | case ALTIVEC_BUILTIN_LVSR: |
b4a62fa0 | 6935 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
c4ad648e | 6936 | arglist, target); |
6525c0e7 | 6937 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 6938 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
c4ad648e | 6939 | arglist, target); |
6525c0e7 | 6940 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 6941 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
c4ad648e | 6942 | arglist, target); |
6525c0e7 | 6943 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 6944 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
c4ad648e | 6945 | arglist, target); |
6525c0e7 | 6946 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 6947 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
c4ad648e | 6948 | arglist, target); |
6525c0e7 | 6949 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 6950 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
c4ad648e | 6951 | arglist, target); |
6525c0e7 AH |
6952 | default: |
6953 | break; | |
6954 | /* Fall through. */ | |
6955 | } | |
95385cbb | 6956 | |
92898235 | 6957 | *expandedp = false; |
0ac081f6 AH |
6958 | return NULL_RTX; |
6959 | } | |
6960 | ||
a3170dc6 AH |
6961 | /* Binops that need to be initialized manually, but can be expanded |
6962 | automagically by rs6000_expand_binop_builtin. */ | |
6963 | static struct builtin_description bdesc_2arg_spe[] = | |
6964 | { | |
6965 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
6966 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
6967 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
6968 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
6969 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
6970 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
6971 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
6972 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
6973 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
6974 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
6975 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
6976 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
6977 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
6978 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
6979 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
6980 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
6981 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
6982 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
6983 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
6984 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
6985 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
6986 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
6987 | }; | |
6988 | ||
6989 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
6990 | true in *EXPANDEDP if we found a builtin to expand. | |
6991 | ||
6992 | This expands the SPE builtins that are not simple unary and binary | |
6993 | operations. */ | |
6994 | static rtx | |
a2369ed3 | 6995 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 AH |
6996 | { |
6997 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6998 | tree arglist = TREE_OPERAND (exp, 1); | |
6999 | tree arg1, arg0; | |
7000 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7001 | enum insn_code icode; | |
7002 | enum machine_mode tmode, mode0; | |
7003 | rtx pat, op0; | |
7004 | struct builtin_description *d; | |
7005 | size_t i; | |
7006 | ||
7007 | *expandedp = true; | |
7008 | ||
7009 | /* Syntax check for a 5-bit unsigned immediate. */ | |
7010 | switch (fcode) | |
7011 | { | |
7012 | case SPE_BUILTIN_EVSTDD: | |
7013 | case SPE_BUILTIN_EVSTDH: | |
7014 | case SPE_BUILTIN_EVSTDW: | |
7015 | case SPE_BUILTIN_EVSTWHE: | |
7016 | case SPE_BUILTIN_EVSTWHO: | |
7017 | case SPE_BUILTIN_EVSTWWE: | |
7018 | case SPE_BUILTIN_EVSTWWO: | |
7019 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7020 | if (TREE_CODE (arg1) != INTEGER_CST | |
7021 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
7022 | { | |
7023 | error ("argument 2 must be a 5-bit unsigned literal"); | |
7024 | return const0_rtx; | |
7025 | } | |
7026 | break; | |
7027 | default: | |
7028 | break; | |
7029 | } | |
7030 | ||
00332c9f AH |
7031 | /* The evsplat*i instructions are not quite generic. */ |
7032 | switch (fcode) | |
7033 | { | |
7034 | case SPE_BUILTIN_EVSPLATFI: | |
7035 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
7036 | arglist, target); | |
7037 | case SPE_BUILTIN_EVSPLATI: | |
7038 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
7039 | arglist, target); | |
7040 | default: | |
7041 | break; | |
7042 | } | |
7043 | ||
a3170dc6 AH |
7044 | d = (struct builtin_description *) bdesc_2arg_spe; |
7045 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
7046 | if (d->code == fcode) | |
7047 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
7048 | ||
7049 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7050 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
7051 | if (d->code == fcode) | |
7052 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
7053 | ||
7054 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7055 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
7056 | if (d->code == fcode) | |
7057 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
7058 | ||
7059 | switch (fcode) | |
7060 | { | |
7061 | case SPE_BUILTIN_EVSTDDX: | |
61bea3b0 | 7062 | return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); |
a3170dc6 | 7063 | case SPE_BUILTIN_EVSTDHX: |
61bea3b0 | 7064 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); |
a3170dc6 | 7065 | case SPE_BUILTIN_EVSTDWX: |
61bea3b0 | 7066 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); |
a3170dc6 | 7067 | case SPE_BUILTIN_EVSTWHEX: |
61bea3b0 | 7068 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); |
a3170dc6 | 7069 | case SPE_BUILTIN_EVSTWHOX: |
61bea3b0 | 7070 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); |
a3170dc6 | 7071 | case SPE_BUILTIN_EVSTWWEX: |
61bea3b0 | 7072 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); |
a3170dc6 | 7073 | case SPE_BUILTIN_EVSTWWOX: |
61bea3b0 | 7074 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); |
a3170dc6 | 7075 | case SPE_BUILTIN_EVSTDD: |
61bea3b0 | 7076 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); |
a3170dc6 | 7077 | case SPE_BUILTIN_EVSTDH: |
61bea3b0 | 7078 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); |
a3170dc6 | 7079 | case SPE_BUILTIN_EVSTDW: |
61bea3b0 | 7080 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); |
a3170dc6 | 7081 | case SPE_BUILTIN_EVSTWHE: |
61bea3b0 | 7082 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); |
a3170dc6 | 7083 | case SPE_BUILTIN_EVSTWHO: |
61bea3b0 | 7084 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); |
a3170dc6 | 7085 | case SPE_BUILTIN_EVSTWWE: |
61bea3b0 | 7086 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); |
a3170dc6 | 7087 | case SPE_BUILTIN_EVSTWWO: |
61bea3b0 | 7088 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); |
a3170dc6 AH |
7089 | case SPE_BUILTIN_MFSPEFSCR: |
7090 | icode = CODE_FOR_spe_mfspefscr; | |
7091 | tmode = insn_data[icode].operand[0].mode; | |
7092 | ||
7093 | if (target == 0 | |
7094 | || GET_MODE (target) != tmode | |
7095 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7096 | target = gen_reg_rtx (tmode); | |
f676971a | 7097 | |
a3170dc6 AH |
7098 | pat = GEN_FCN (icode) (target); |
7099 | if (! pat) | |
7100 | return 0; | |
7101 | emit_insn (pat); | |
7102 | return target; | |
7103 | case SPE_BUILTIN_MTSPEFSCR: | |
7104 | icode = CODE_FOR_spe_mtspefscr; | |
7105 | arg0 = TREE_VALUE (arglist); | |
7106 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7107 | mode0 = insn_data[icode].operand[0].mode; | |
7108 | ||
7109 | if (arg0 == error_mark_node) | |
7110 | return const0_rtx; | |
7111 | ||
7112 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
7113 | op0 = copy_to_mode_reg (mode0, op0); | |
7114 | ||
7115 | pat = GEN_FCN (icode) (op0); | |
7116 | if (pat) | |
7117 | emit_insn (pat); | |
7118 | return NULL_RTX; | |
7119 | default: | |
7120 | break; | |
7121 | } | |
7122 | ||
7123 | *expandedp = false; | |
7124 | return NULL_RTX; | |
7125 | } | |
7126 | ||
7127 | static rtx | |
a2369ed3 | 7128 | spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
7129 | { |
7130 | rtx pat, scratch, tmp; | |
7131 | tree form = TREE_VALUE (arglist); | |
7132 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7133 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7134 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7135 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7136 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7137 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7138 | int form_int; | |
7139 | enum rtx_code code; | |
7140 | ||
7141 | if (TREE_CODE (form) != INTEGER_CST) | |
7142 | { | |
7143 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
7144 | return const0_rtx; | |
7145 | } | |
7146 | else | |
7147 | form_int = TREE_INT_CST_LOW (form); | |
7148 | ||
37409796 | 7149 | gcc_assert (mode0 == mode1); |
a3170dc6 AH |
7150 | |
7151 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
7152 | return const0_rtx; | |
7153 | ||
7154 | if (target == 0 | |
7155 | || GET_MODE (target) != SImode | |
7156 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
7157 | target = gen_reg_rtx (SImode); | |
7158 | ||
7159 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7160 | op0 = copy_to_mode_reg (mode0, op0); | |
7161 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
7162 | op1 = copy_to_mode_reg (mode1, op1); | |
7163 | ||
7164 | scratch = gen_reg_rtx (CCmode); | |
7165 | ||
7166 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7167 | if (! pat) | |
7168 | return const0_rtx; | |
7169 | emit_insn (pat); | |
7170 | ||
7171 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
7172 | _lower_. We use one compare, but look in different bits of the | |
7173 | CR for each variant. | |
7174 | ||
7175 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
7176 | bits are set as follows: | |
7177 | ||
7178 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7179 | U | L | (U | L) | (U & L) | |
7180 | ||
7181 | So, for an "all" relationship, BIT 3 would be set. | |
7182 | For an "any" relationship, BIT 2 would be set. Etc. | |
7183 | ||
7184 | Following traditional nomenclature, these bits map to: | |
7185 | ||
7186 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7187 | LT | GT | EQ | OV | |
7188 | ||
7189 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
7190 | */ | |
7191 | ||
7192 | switch (form_int) | |
7193 | { | |
7194 | /* All variant. OV bit. */ | |
7195 | case 0: | |
7196 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
7197 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
992d08b1 | 7198 | that's ugly and will make validate_condition_mode die. |
a3170dc6 AH |
7199 | So let's just use another pattern. */ |
7200 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
7201 | return target; | |
7202 | /* Any variant. EQ bit. */ | |
7203 | case 1: | |
7204 | code = EQ; | |
7205 | break; | |
7206 | /* Upper variant. LT bit. */ | |
7207 | case 2: | |
7208 | code = LT; | |
7209 | break; | |
7210 | /* Lower variant. GT bit. */ | |
7211 | case 3: | |
7212 | code = GT; | |
7213 | break; | |
7214 | default: | |
7215 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
7216 | return const0_rtx; | |
7217 | } | |
7218 | ||
7219 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
7220 | emit_move_insn (target, tmp); | |
7221 | ||
7222 | return target; | |
7223 | } | |
7224 | ||
7225 | /* The evsel builtins look like this: | |
7226 | ||
7227 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
7228 | ||
7229 | and work like this: | |
7230 | ||
7231 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
7232 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
7233 | */ | |
7234 | ||
7235 | static rtx | |
a2369ed3 | 7236 | spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
7237 | { |
7238 | rtx pat, scratch; | |
7239 | tree arg0 = TREE_VALUE (arglist); | |
7240 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7241 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7242 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
7243 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7244 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7245 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
7246 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
7247 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7248 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7249 | ||
37409796 | 7250 | gcc_assert (mode0 == mode1); |
a3170dc6 AH |
7251 | |
7252 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
7253 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
7254 | return const0_rtx; | |
7255 | ||
7256 | if (target == 0 | |
7257 | || GET_MODE (target) != mode0 | |
7258 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
7259 | target = gen_reg_rtx (mode0); | |
7260 | ||
7261 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7262 | op0 = copy_to_mode_reg (mode0, op0); | |
7263 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
7264 | op1 = copy_to_mode_reg (mode0, op1); | |
7265 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
7266 | op2 = copy_to_mode_reg (mode0, op2); | |
7267 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
7268 | op3 = copy_to_mode_reg (mode0, op3); | |
7269 | ||
7270 | /* Generate the compare. */ | |
7271 | scratch = gen_reg_rtx (CCmode); | |
7272 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7273 | if (! pat) | |
7274 | return const0_rtx; | |
7275 | emit_insn (pat); | |
7276 | ||
7277 | if (mode0 == V2SImode) | |
7278 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
7279 | else | |
7280 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
7281 | ||
7282 | return target; | |
7283 | } | |
7284 | ||
0ac081f6 AH |
7285 | /* Expand an expression EXP that calls a built-in function, |
7286 | with result going to TARGET if that's convenient | |
7287 | (and in mode MODE if that's convenient). | |
7288 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
7289 | IGNORE is nonzero if the value is to be ignored. */ | |
7290 | ||
7291 | static rtx | |
a2369ed3 | 7292 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
c4ad648e AM |
7293 | enum machine_mode mode ATTRIBUTE_UNUSED, |
7294 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 7295 | { |
92898235 AH |
7296 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
7297 | tree arglist = TREE_OPERAND (exp, 1); | |
7298 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7299 | struct builtin_description *d; | |
7300 | size_t i; | |
7301 | rtx ret; | |
7302 | bool success; | |
f676971a | 7303 | |
7ccf35ed DN |
7304 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD |
7305 | || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7306 | { | |
7307 | int icode = (int) CODE_FOR_altivec_lvsr; | |
7308 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
7309 | enum machine_mode mode = insn_data[icode].operand[1].mode; | |
7310 | tree arg; | |
7311 | rtx op, addr, pat; | |
7312 | ||
37409796 | 7313 | gcc_assert (TARGET_ALTIVEC); |
7ccf35ed DN |
7314 | |
7315 | arg = TREE_VALUE (arglist); | |
37409796 | 7316 | gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE); |
7ccf35ed DN |
7317 | op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); |
7318 | addr = memory_address (mode, op); | |
7319 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7320 | op = addr; | |
7321 | else | |
7322 | { | |
7323 | /* For the load case need to negate the address. */ | |
7324 | op = gen_reg_rtx (GET_MODE (addr)); | |
7325 | emit_insn (gen_rtx_SET (VOIDmode, op, | |
7326 | gen_rtx_NEG (GET_MODE (addr), addr))); | |
c4ad648e | 7327 | } |
7ccf35ed DN |
7328 | op = gen_rtx_MEM (mode, op); |
7329 | ||
7330 | if (target == 0 | |
7331 | || GET_MODE (target) != tmode | |
7332 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7333 | target = gen_reg_rtx (tmode); | |
7334 | ||
7335 | /*pat = gen_altivec_lvsr (target, op);*/ | |
7336 | pat = GEN_FCN (icode) (target, op); | |
7337 | if (!pat) | |
7338 | return 0; | |
7339 | emit_insn (pat); | |
7340 | ||
7341 | return target; | |
7342 | } | |
7343 | ||
0ac081f6 | 7344 | if (TARGET_ALTIVEC) |
92898235 AH |
7345 | { |
7346 | ret = altivec_expand_builtin (exp, target, &success); | |
7347 | ||
a3170dc6 AH |
7348 | if (success) |
7349 | return ret; | |
7350 | } | |
7351 | if (TARGET_SPE) | |
7352 | { | |
7353 | ret = spe_expand_builtin (exp, target, &success); | |
7354 | ||
92898235 AH |
7355 | if (success) |
7356 | return ret; | |
7357 | } | |
7358 | ||
37409796 NS |
7359 | gcc_assert (TARGET_ALTIVEC || TARGET_SPE); |
7360 | ||
7361 | /* Handle simple unary operations. */ | |
7362 | d = (struct builtin_description *) bdesc_1arg; | |
7363 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
7364 | if (d->code == fcode) | |
7365 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
7366 | ||
7367 | /* Handle simple binary operations. */ | |
7368 | d = (struct builtin_description *) bdesc_2arg; | |
7369 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
7370 | if (d->code == fcode) | |
7371 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
0ac081f6 | 7372 | |
37409796 NS |
7373 | /* Handle simple ternary operations. */ |
7374 | d = (struct builtin_description *) bdesc_3arg; | |
7375 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
7376 | if (d->code == fcode) | |
7377 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
7378 | ||
7379 | gcc_unreachable (); | |
0ac081f6 AH |
7380 | } |
7381 | ||
7c62e993 PB |
7382 | static tree |
7383 | build_opaque_vector_type (tree node, int nunits) | |
7384 | { | |
7385 | node = copy_node (node); | |
7386 | TYPE_MAIN_VARIANT (node) = node; | |
7387 | return build_vector_type (node, nunits); | |
7388 | } | |
7389 | ||
0ac081f6 | 7390 | static void |
863d938c | 7391 | rs6000_init_builtins (void) |
0ac081f6 | 7392 | { |
4a5eab38 PB |
7393 | V2SI_type_node = build_vector_type (intSI_type_node, 2); |
7394 | V2SF_type_node = build_vector_type (float_type_node, 2); | |
7395 | V4HI_type_node = build_vector_type (intHI_type_node, 4); | |
7396 | V4SI_type_node = build_vector_type (intSI_type_node, 4); | |
7397 | V4SF_type_node = build_vector_type (float_type_node, 4); | |
7e463bda | 7398 | V8HI_type_node = build_vector_type (intHI_type_node, 8); |
4a5eab38 PB |
7399 | V16QI_type_node = build_vector_type (intQI_type_node, 16); |
7400 | ||
7401 | unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); | |
7402 | unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); | |
7403 | unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); | |
7404 | ||
7c62e993 PB |
7405 | opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); |
7406 | opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); | |
6035d635 | 7407 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
58646b77 | 7408 | opaque_V4SI_type_node = copy_node (V4SI_type_node); |
3fdaa45a | 7409 | |
8bb418a3 ZL |
7410 | /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' |
7411 | types, especially in C++ land. Similarly, 'vector pixel' is distinct from | |
7412 | 'vector unsigned short'. */ | |
7413 | ||
8dd16ecc NS |
7414 | bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); |
7415 | bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
7416 | bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); | |
7417 | pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
8bb418a3 | 7418 | |
58646b77 PB |
7419 | long_integer_type_internal_node = long_integer_type_node; |
7420 | long_unsigned_type_internal_node = long_unsigned_type_node; | |
7421 | intQI_type_internal_node = intQI_type_node; | |
7422 | uintQI_type_internal_node = unsigned_intQI_type_node; | |
7423 | intHI_type_internal_node = intHI_type_node; | |
7424 | uintHI_type_internal_node = unsigned_intHI_type_node; | |
7425 | intSI_type_internal_node = intSI_type_node; | |
7426 | uintSI_type_internal_node = unsigned_intSI_type_node; | |
7427 | float_type_internal_node = float_type_node; | |
7428 | void_type_internal_node = void_type_node; | |
7429 | ||
8bb418a3 ZL |
7430 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, |
7431 | get_identifier ("__bool char"), | |
7432 | bool_char_type_node)); | |
7433 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7434 | get_identifier ("__bool short"), | |
7435 | bool_short_type_node)); | |
7436 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7437 | get_identifier ("__bool int"), | |
7438 | bool_int_type_node)); | |
7439 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7440 | get_identifier ("__pixel"), | |
7441 | pixel_type_node)); | |
7442 | ||
4a5eab38 PB |
7443 | bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); |
7444 | bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); | |
7445 | bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); | |
7446 | pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); | |
8bb418a3 ZL |
7447 | |
7448 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7449 | get_identifier ("__vector unsigned char"), | |
7450 | unsigned_V16QI_type_node)); | |
7451 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7452 | get_identifier ("__vector signed char"), | |
7453 | V16QI_type_node)); | |
7454 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7455 | get_identifier ("__vector __bool char"), | |
7456 | bool_V16QI_type_node)); | |
7457 | ||
7458 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7459 | get_identifier ("__vector unsigned short"), | |
7460 | unsigned_V8HI_type_node)); | |
7461 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7462 | get_identifier ("__vector signed short"), | |
7463 | V8HI_type_node)); | |
7464 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7465 | get_identifier ("__vector __bool short"), | |
7466 | bool_V8HI_type_node)); | |
7467 | ||
7468 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7469 | get_identifier ("__vector unsigned int"), | |
7470 | unsigned_V4SI_type_node)); | |
7471 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7472 | get_identifier ("__vector signed int"), | |
7473 | V4SI_type_node)); | |
7474 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7475 | get_identifier ("__vector __bool int"), | |
7476 | bool_V4SI_type_node)); | |
7477 | ||
7478 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7479 | get_identifier ("__vector float"), | |
7480 | V4SF_type_node)); | |
7481 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7482 | get_identifier ("__vector __pixel"), | |
7483 | pixel_V8HI_type_node)); | |
7484 | ||
a3170dc6 | 7485 | if (TARGET_SPE) |
3fdaa45a | 7486 | spe_init_builtins (); |
0ac081f6 AH |
7487 | if (TARGET_ALTIVEC) |
7488 | altivec_init_builtins (); | |
0559cc77 DE |
7489 | if (TARGET_ALTIVEC || TARGET_SPE) |
7490 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
7491 | } |
7492 | ||
a3170dc6 AH |
7493 | /* Search through a set of builtins and enable the mask bits. |
7494 | DESC is an array of builtins. | |
b6d08ca1 | 7495 | SIZE is the total number of builtins. |
a3170dc6 AH |
7496 | START is the builtin enum at which to start. |
7497 | END is the builtin enum at which to end. */ | |
0ac081f6 | 7498 | static void |
a2369ed3 | 7499 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
f676971a | 7500 | enum rs6000_builtins start, |
a2369ed3 | 7501 | enum rs6000_builtins end) |
a3170dc6 AH |
7502 | { |
7503 | int i; | |
7504 | ||
7505 | for (i = 0; i < size; ++i) | |
7506 | if (desc[i].code == start) | |
7507 | break; | |
7508 | ||
7509 | if (i == size) | |
7510 | return; | |
7511 | ||
7512 | for (; i < size; ++i) | |
7513 | { | |
7514 | /* Flip all the bits on. */ | |
7515 | desc[i].mask = target_flags; | |
7516 | if (desc[i].code == end) | |
7517 | break; | |
7518 | } | |
7519 | } | |
7520 | ||
7521 | static void | |
863d938c | 7522 | spe_init_builtins (void) |
0ac081f6 | 7523 | { |
a3170dc6 AH |
7524 | tree endlink = void_list_node; |
7525 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
7526 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 7527 | struct builtin_description *d; |
0ac081f6 AH |
7528 | size_t i; |
7529 | ||
a3170dc6 AH |
7530 | tree v2si_ftype_4_v2si |
7531 | = build_function_type | |
3fdaa45a AH |
7532 | (opaque_V2SI_type_node, |
7533 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7534 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7535 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7536 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7537 | endlink))))); |
7538 | ||
7539 | tree v2sf_ftype_4_v2sf | |
7540 | = build_function_type | |
3fdaa45a AH |
7541 | (opaque_V2SF_type_node, |
7542 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7543 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7544 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7545 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7546 | endlink))))); |
7547 | ||
7548 | tree int_ftype_int_v2si_v2si | |
7549 | = build_function_type | |
7550 | (integer_type_node, | |
7551 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7552 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
7553 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7554 | endlink)))); |
7555 | ||
7556 | tree int_ftype_int_v2sf_v2sf | |
7557 | = build_function_type | |
7558 | (integer_type_node, | |
7559 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7560 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
7561 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7562 | endlink)))); |
7563 | ||
7564 | tree void_ftype_v2si_puint_int | |
7565 | = build_function_type (void_type_node, | |
3fdaa45a | 7566 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7567 | tree_cons (NULL_TREE, puint_type_node, |
7568 | tree_cons (NULL_TREE, | |
7569 | integer_type_node, | |
7570 | endlink)))); | |
7571 | ||
7572 | tree void_ftype_v2si_puint_char | |
7573 | = build_function_type (void_type_node, | |
3fdaa45a | 7574 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7575 | tree_cons (NULL_TREE, puint_type_node, |
7576 | tree_cons (NULL_TREE, | |
7577 | char_type_node, | |
7578 | endlink)))); | |
7579 | ||
7580 | tree void_ftype_v2si_pv2si_int | |
7581 | = build_function_type (void_type_node, | |
3fdaa45a | 7582 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7583 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7584 | tree_cons (NULL_TREE, |
7585 | integer_type_node, | |
7586 | endlink)))); | |
7587 | ||
7588 | tree void_ftype_v2si_pv2si_char | |
7589 | = build_function_type (void_type_node, | |
3fdaa45a | 7590 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7591 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7592 | tree_cons (NULL_TREE, |
7593 | char_type_node, | |
7594 | endlink)))); | |
7595 | ||
7596 | tree void_ftype_int | |
7597 | = build_function_type (void_type_node, | |
7598 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
7599 | ||
7600 | tree int_ftype_void | |
36e8d515 | 7601 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
7602 | |
7603 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 7604 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 7605 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7606 | tree_cons (NULL_TREE, integer_type_node, |
7607 | endlink))); | |
7608 | ||
7609 | tree v2si_ftype_puint_int | |
3fdaa45a | 7610 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7611 | tree_cons (NULL_TREE, puint_type_node, |
7612 | tree_cons (NULL_TREE, integer_type_node, | |
7613 | endlink))); | |
7614 | ||
7615 | tree v2si_ftype_pushort_int | |
3fdaa45a | 7616 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7617 | tree_cons (NULL_TREE, pushort_type_node, |
7618 | tree_cons (NULL_TREE, integer_type_node, | |
7619 | endlink))); | |
7620 | ||
00332c9f AH |
7621 | tree v2si_ftype_signed_char |
7622 | = build_function_type (opaque_V2SI_type_node, | |
7623 | tree_cons (NULL_TREE, signed_char_type_node, | |
7624 | endlink)); | |
7625 | ||
a3170dc6 AH |
7626 | /* The initialization of the simple binary and unary builtins is |
7627 | done in rs6000_common_init_builtins, but we have to enable the | |
7628 | mask bits here manually because we have run out of `target_flags' | |
7629 | bits. We really need to redesign this mask business. */ | |
7630 | ||
7631 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
7632 | ARRAY_SIZE (bdesc_2arg), | |
7633 | SPE_BUILTIN_EVADDW, | |
7634 | SPE_BUILTIN_EVXOR); | |
7635 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
7636 | ARRAY_SIZE (bdesc_1arg), | |
7637 | SPE_BUILTIN_EVABS, | |
7638 | SPE_BUILTIN_EVSUBFUSIAAW); | |
7639 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
7640 | ARRAY_SIZE (bdesc_spe_predicates), | |
7641 | SPE_BUILTIN_EVCMPEQ, | |
7642 | SPE_BUILTIN_EVFSTSTLT); | |
7643 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
7644 | ARRAY_SIZE (bdesc_spe_evsel), | |
7645 | SPE_BUILTIN_EVSEL_CMPGTS, | |
7646 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
7647 | ||
36252949 AH |
7648 | (*lang_hooks.decls.pushdecl) |
7649 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
7650 | opaque_V2SI_type_node)); | |
7651 | ||
a3170dc6 | 7652 | /* Initialize irregular SPE builtins. */ |
f676971a | 7653 | |
a3170dc6 AH |
7654 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); |
7655 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
7656 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
7657 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
7658 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
7659 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
7660 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
7661 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
7662 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
7663 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
7664 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
7665 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
7666 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
7667 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
7668 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
7669 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
7670 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
7671 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
7672 | |
7673 | /* Loads. */ | |
7674 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
7675 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
7676 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
7677 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
7678 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
7679 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
7680 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
7681 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
7682 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
7683 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
7684 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
7685 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
7686 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
7687 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
7688 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
7689 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
7690 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
7691 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
7692 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
7693 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
7694 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
7695 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
7696 | ||
7697 | /* Predicates. */ | |
7698 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7699 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
7700 | { | |
7701 | tree type; | |
7702 | ||
7703 | switch (insn_data[d->icode].operand[1].mode) | |
7704 | { | |
7705 | case V2SImode: | |
7706 | type = int_ftype_int_v2si_v2si; | |
7707 | break; | |
7708 | case V2SFmode: | |
7709 | type = int_ftype_int_v2sf_v2sf; | |
7710 | break; | |
7711 | default: | |
37409796 | 7712 | gcc_unreachable (); |
a3170dc6 AH |
7713 | } |
7714 | ||
7715 | def_builtin (d->mask, d->name, type, d->code); | |
7716 | } | |
7717 | ||
7718 | /* Evsel predicates. */ | |
7719 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7720 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
7721 | { | |
7722 | tree type; | |
7723 | ||
7724 | switch (insn_data[d->icode].operand[1].mode) | |
7725 | { | |
7726 | case V2SImode: | |
7727 | type = v2si_ftype_4_v2si; | |
7728 | break; | |
7729 | case V2SFmode: | |
7730 | type = v2sf_ftype_4_v2sf; | |
7731 | break; | |
7732 | default: | |
37409796 | 7733 | gcc_unreachable (); |
a3170dc6 AH |
7734 | } |
7735 | ||
7736 | def_builtin (d->mask, d->name, type, d->code); | |
7737 | } | |
7738 | } | |
7739 | ||
7740 | static void | |
863d938c | 7741 | altivec_init_builtins (void) |
a3170dc6 AH |
7742 | { |
7743 | struct builtin_description *d; | |
7744 | struct builtin_description_predicates *dp; | |
7745 | size_t i; | |
7746 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
7747 | tree pint_type_node = build_pointer_type (integer_type_node); | |
7748 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
7749 | tree pchar_type_node = build_pointer_type (char_type_node); | |
7750 | ||
7751 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
7752 | ||
0dbc3651 ZW |
7753 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
7754 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
7755 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
7756 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
7757 | ||
7758 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
7759 | ||
58646b77 PB |
7760 | tree int_ftype_opaque |
7761 | = build_function_type_list (integer_type_node, | |
7762 | opaque_V4SI_type_node, NULL_TREE); | |
7763 | ||
7764 | tree opaque_ftype_opaque_int | |
7765 | = build_function_type_list (opaque_V4SI_type_node, | |
7766 | opaque_V4SI_type_node, integer_type_node, NULL_TREE); | |
7767 | tree opaque_ftype_opaque_opaque_int | |
7768 | = build_function_type_list (opaque_V4SI_type_node, | |
7769 | opaque_V4SI_type_node, opaque_V4SI_type_node, | |
7770 | integer_type_node, NULL_TREE); | |
7771 | tree int_ftype_int_opaque_opaque | |
7772 | = build_function_type_list (integer_type_node, | |
7773 | integer_type_node, opaque_V4SI_type_node, | |
7774 | opaque_V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7775 | tree int_ftype_int_v4si_v4si |
7776 | = build_function_type_list (integer_type_node, | |
7777 | integer_type_node, V4SI_type_node, | |
7778 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7779 | tree v4sf_ftype_pcfloat |
7780 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 7781 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 7782 | = build_function_type_list (void_type_node, |
a3170dc6 | 7783 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
7784 | tree v4si_ftype_pcint |
7785 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
7786 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
7787 | = build_function_type_list (void_type_node, |
7788 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7789 | tree v8hi_ftype_pcshort |
7790 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 7791 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
7792 | = build_function_type_list (void_type_node, |
7793 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7794 | tree v16qi_ftype_pcchar |
7795 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 7796 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
7797 | = build_function_type_list (void_type_node, |
7798 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 7799 | tree void_ftype_v4si |
b4de2f7d | 7800 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
7801 | tree v8hi_ftype_void |
7802 | = build_function_type (V8HI_type_node, void_list_node); | |
7803 | tree void_ftype_void | |
7804 | = build_function_type (void_type_node, void_list_node); | |
e34b6648 JJ |
7805 | tree void_ftype_int |
7806 | = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); | |
0dbc3651 | 7807 | |
58646b77 PB |
7808 | tree opaque_ftype_long_pcvoid |
7809 | = build_function_type_list (opaque_V4SI_type_node, | |
7810 | long_integer_type_node, pcvoid_type_node, NULL_TREE); | |
b4a62fa0 | 7811 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 7812 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
7813 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7814 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 7815 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
7816 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7817 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 7818 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 7819 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 7820 | |
58646b77 PB |
7821 | tree void_ftype_opaque_long_pvoid |
7822 | = build_function_type_list (void_type_node, | |
7823 | opaque_V4SI_type_node, long_integer_type_node, | |
7824 | pvoid_type_node, NULL_TREE); | |
b4a62fa0 | 7825 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 7826 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7827 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 7828 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7829 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 7830 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7831 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 7832 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7833 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 7834 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7835 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 7836 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
7837 | tree int_ftype_int_v8hi_v8hi |
7838 | = build_function_type_list (integer_type_node, | |
7839 | integer_type_node, V8HI_type_node, | |
7840 | V8HI_type_node, NULL_TREE); | |
7841 | tree int_ftype_int_v16qi_v16qi | |
7842 | = build_function_type_list (integer_type_node, | |
7843 | integer_type_node, V16QI_type_node, | |
7844 | V16QI_type_node, NULL_TREE); | |
7845 | tree int_ftype_int_v4sf_v4sf | |
7846 | = build_function_type_list (integer_type_node, | |
7847 | integer_type_node, V4SF_type_node, | |
7848 | V4SF_type_node, NULL_TREE); | |
7849 | tree v4si_ftype_v4si | |
7850 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7851 | tree v8hi_ftype_v8hi | |
7852 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
7853 | tree v16qi_ftype_v16qi | |
7854 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
7855 | tree v4sf_ftype_v4sf | |
7856 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8bb418a3 | 7857 | tree void_ftype_pcvoid_int_int |
a3170dc6 | 7858 | = build_function_type_list (void_type_node, |
0dbc3651 | 7859 | pcvoid_type_node, integer_type_node, |
8bb418a3 | 7860 | integer_type_node, NULL_TREE); |
8bb418a3 | 7861 | |
0dbc3651 ZW |
7862 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, |
7863 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
7864 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
7865 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
7866 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
7867 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
7868 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
7869 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
7870 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
7871 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
7872 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
7873 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
7874 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
7875 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
7876 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
7877 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
7878 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
7879 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
7880 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
e34b6648 | 7881 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); |
b4a62fa0 SB |
7882 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
7883 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
7884 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
7885 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
7886 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
7887 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
7888 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
7889 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
7890 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
7891 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
7892 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
7893 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
58646b77 PB |
7894 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD); |
7895 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE); | |
7896 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL); | |
7897 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL); | |
7898 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR); | |
7899 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX); | |
7900 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX); | |
7901 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX); | |
7902 | def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST); | |
7903 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE); | |
7904 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL); | |
7905 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX); | |
7906 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX); | |
7907 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX); | |
7908 | ||
7909 | def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP); | |
7910 | ||
7911 | def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD); | |
7912 | def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT); | |
7913 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW); | |
7914 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH); | |
7915 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB); | |
7916 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF); | |
7917 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX); | |
7918 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX); | |
7919 | def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS); | |
7920 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU); | |
8bb418a3 | 7921 | |
a3170dc6 AH |
7922 | /* Add the DST variants. */ |
7923 | d = (struct builtin_description *) bdesc_dst; | |
7924 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
8bb418a3 | 7925 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); |
a3170dc6 AH |
7926 | |
7927 | /* Initialize the predicates. */ | |
7928 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
7929 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
7930 | { | |
7931 | enum machine_mode mode1; | |
7932 | tree type; | |
58646b77 PB |
7933 | bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
7934 | && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
a3170dc6 | 7935 | |
58646b77 PB |
7936 | if (is_overloaded) |
7937 | mode1 = VOIDmode; | |
7938 | else | |
7939 | mode1 = insn_data[dp->icode].operand[1].mode; | |
a3170dc6 AH |
7940 | |
7941 | switch (mode1) | |
7942 | { | |
58646b77 PB |
7943 | case VOIDmode: |
7944 | type = int_ftype_int_opaque_opaque; | |
7945 | break; | |
a3170dc6 AH |
7946 | case V4SImode: |
7947 | type = int_ftype_int_v4si_v4si; | |
7948 | break; | |
7949 | case V8HImode: | |
7950 | type = int_ftype_int_v8hi_v8hi; | |
7951 | break; | |
7952 | case V16QImode: | |
7953 | type = int_ftype_int_v16qi_v16qi; | |
7954 | break; | |
7955 | case V4SFmode: | |
7956 | type = int_ftype_int_v4sf_v4sf; | |
7957 | break; | |
7958 | default: | |
37409796 | 7959 | gcc_unreachable (); |
a3170dc6 | 7960 | } |
f676971a | 7961 | |
a3170dc6 AH |
7962 | def_builtin (dp->mask, dp->name, type, dp->code); |
7963 | } | |
7964 | ||
7965 | /* Initialize the abs* operators. */ | |
7966 | d = (struct builtin_description *) bdesc_abs; | |
7967 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
7968 | { | |
7969 | enum machine_mode mode0; | |
7970 | tree type; | |
7971 | ||
7972 | mode0 = insn_data[d->icode].operand[0].mode; | |
7973 | ||
7974 | switch (mode0) | |
7975 | { | |
7976 | case V4SImode: | |
7977 | type = v4si_ftype_v4si; | |
7978 | break; | |
7979 | case V8HImode: | |
7980 | type = v8hi_ftype_v8hi; | |
7981 | break; | |
7982 | case V16QImode: | |
7983 | type = v16qi_ftype_v16qi; | |
7984 | break; | |
7985 | case V4SFmode: | |
7986 | type = v4sf_ftype_v4sf; | |
7987 | break; | |
7988 | default: | |
37409796 | 7989 | gcc_unreachable (); |
a3170dc6 | 7990 | } |
f676971a | 7991 | |
a3170dc6 AH |
7992 | def_builtin (d->mask, d->name, type, d->code); |
7993 | } | |
7ccf35ed | 7994 | |
13c62176 DN |
7995 | if (TARGET_ALTIVEC) |
7996 | { | |
7997 | tree decl; | |
7998 | ||
7999 | /* Initialize target builtin that implements | |
8000 | targetm.vectorize.builtin_mask_for_load. */ | |
8001 | ||
8002 | decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load", | |
8bb46326 DN |
8003 | v16qi_ftype_long_pcvoid, |
8004 | ALTIVEC_BUILTIN_MASK_FOR_LOAD, | |
8005 | BUILT_IN_MD, NULL, | |
8006 | tree_cons (get_identifier ("const"), | |
8007 | NULL_TREE, NULL_TREE)); | |
13c62176 DN |
8008 | /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ |
8009 | altivec_builtin_mask_for_load = decl; | |
13c62176 | 8010 | } |
a3170dc6 AH |
8011 | } |
8012 | ||
8013 | static void | |
863d938c | 8014 | rs6000_common_init_builtins (void) |
a3170dc6 AH |
8015 | { |
8016 | struct builtin_description *d; | |
8017 | size_t i; | |
8018 | ||
8019 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
8020 | = build_function_type_list (V4SF_type_node, | |
8021 | V4SF_type_node, V4SF_type_node, | |
8022 | V16QI_type_node, NULL_TREE); | |
8023 | tree v4si_ftype_v4si_v4si_v16qi | |
8024 | = build_function_type_list (V4SI_type_node, | |
8025 | V4SI_type_node, V4SI_type_node, | |
8026 | V16QI_type_node, NULL_TREE); | |
8027 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
8028 | = build_function_type_list (V8HI_type_node, | |
8029 | V8HI_type_node, V8HI_type_node, | |
8030 | V16QI_type_node, NULL_TREE); | |
8031 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
8032 | = build_function_type_list (V16QI_type_node, | |
8033 | V16QI_type_node, V16QI_type_node, | |
8034 | V16QI_type_node, NULL_TREE); | |
b9e4e5d1 ZL |
8035 | tree v4si_ftype_int |
8036 | = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); | |
8037 | tree v8hi_ftype_int | |
8038 | = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); | |
8039 | tree v16qi_ftype_int | |
8040 | = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); | |
a3170dc6 AH |
8041 | tree v8hi_ftype_v16qi |
8042 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
8043 | tree v4sf_ftype_v4sf | |
8044 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8045 | ||
8046 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
8047 | = build_function_type_list (opaque_V2SI_type_node, |
8048 | opaque_V2SI_type_node, | |
8049 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8050 | |
8051 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
8052 | = build_function_type_list (opaque_V2SF_type_node, |
8053 | opaque_V2SF_type_node, | |
8054 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
8055 | |
8056 | tree v2si_ftype_int_int | |
2abe3e28 | 8057 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
8058 | integer_type_node, integer_type_node, |
8059 | NULL_TREE); | |
8060 | ||
58646b77 PB |
8061 | tree opaque_ftype_opaque |
8062 | = build_function_type_list (opaque_V4SI_type_node, | |
8063 | opaque_V4SI_type_node, NULL_TREE); | |
8064 | ||
a3170dc6 | 8065 | tree v2si_ftype_v2si |
2abe3e28 AH |
8066 | = build_function_type_list (opaque_V2SI_type_node, |
8067 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8068 | |
8069 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
8070 | = build_function_type_list (opaque_V2SF_type_node, |
8071 | opaque_V2SF_type_node, NULL_TREE); | |
f676971a | 8072 | |
a3170dc6 | 8073 | tree v2sf_ftype_v2si |
2abe3e28 AH |
8074 | = build_function_type_list (opaque_V2SF_type_node, |
8075 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8076 | |
8077 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
8078 | = build_function_type_list (opaque_V2SI_type_node, |
8079 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
8080 | |
8081 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
8082 | = build_function_type_list (opaque_V2SI_type_node, |
8083 | opaque_V2SI_type_node, | |
8084 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
8085 | |
8086 | tree v2si_ftype_int_char | |
2abe3e28 | 8087 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
8088 | integer_type_node, char_type_node, NULL_TREE); |
8089 | ||
8090 | tree v2si_ftype_char | |
2abe3e28 AH |
8091 | = build_function_type_list (opaque_V2SI_type_node, |
8092 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
8093 | |
8094 | tree int_ftype_int_int | |
8095 | = build_function_type_list (integer_type_node, | |
8096 | integer_type_node, integer_type_node, | |
8097 | NULL_TREE); | |
95385cbb | 8098 | |
58646b77 PB |
8099 | tree opaque_ftype_opaque_opaque |
8100 | = build_function_type_list (opaque_V4SI_type_node, | |
8101 | opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8102 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
8103 | = build_function_type_list (V4SI_type_node, |
8104 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
b9e4e5d1 | 8105 | tree v4sf_ftype_v4si_int |
b4de2f7d | 8106 | = build_function_type_list (V4SF_type_node, |
b9e4e5d1 ZL |
8107 | V4SI_type_node, integer_type_node, NULL_TREE); |
8108 | tree v4si_ftype_v4sf_int | |
b4de2f7d | 8109 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
8110 | V4SF_type_node, integer_type_node, NULL_TREE); |
8111 | tree v4si_ftype_v4si_int | |
b4de2f7d | 8112 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
8113 | V4SI_type_node, integer_type_node, NULL_TREE); |
8114 | tree v8hi_ftype_v8hi_int | |
b4de2f7d | 8115 | = build_function_type_list (V8HI_type_node, |
b9e4e5d1 ZL |
8116 | V8HI_type_node, integer_type_node, NULL_TREE); |
8117 | tree v16qi_ftype_v16qi_int | |
b4de2f7d | 8118 | = build_function_type_list (V16QI_type_node, |
b9e4e5d1 ZL |
8119 | V16QI_type_node, integer_type_node, NULL_TREE); |
8120 | tree v16qi_ftype_v16qi_v16qi_int | |
b4de2f7d AH |
8121 | = build_function_type_list (V16QI_type_node, |
8122 | V16QI_type_node, V16QI_type_node, | |
b9e4e5d1 ZL |
8123 | integer_type_node, NULL_TREE); |
8124 | tree v8hi_ftype_v8hi_v8hi_int | |
b4de2f7d AH |
8125 | = build_function_type_list (V8HI_type_node, |
8126 | V8HI_type_node, V8HI_type_node, | |
b9e4e5d1 ZL |
8127 | integer_type_node, NULL_TREE); |
8128 | tree v4si_ftype_v4si_v4si_int | |
b4de2f7d AH |
8129 | = build_function_type_list (V4SI_type_node, |
8130 | V4SI_type_node, V4SI_type_node, | |
b9e4e5d1 ZL |
8131 | integer_type_node, NULL_TREE); |
8132 | tree v4sf_ftype_v4sf_v4sf_int | |
b4de2f7d AH |
8133 | = build_function_type_list (V4SF_type_node, |
8134 | V4SF_type_node, V4SF_type_node, | |
b9e4e5d1 | 8135 | integer_type_node, NULL_TREE); |
0ac081f6 | 8136 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
8137 | = build_function_type_list (V4SF_type_node, |
8138 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
58646b77 PB |
8139 | tree opaque_ftype_opaque_opaque_opaque |
8140 | = build_function_type_list (opaque_V4SI_type_node, | |
8141 | opaque_V4SI_type_node, opaque_V4SI_type_node, | |
8142 | opaque_V4SI_type_node, NULL_TREE); | |
617e0e1d | 8143 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
8144 | = build_function_type_list (V4SF_type_node, |
8145 | V4SF_type_node, V4SF_type_node, | |
8146 | V4SI_type_node, NULL_TREE); | |
2212663f | 8147 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
8148 | = build_function_type_list (V4SF_type_node, |
8149 | V4SF_type_node, V4SF_type_node, | |
8150 | V4SF_type_node, NULL_TREE); | |
f676971a | 8151 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
8152 | = build_function_type_list (V4SI_type_node, |
8153 | V4SI_type_node, V4SI_type_node, | |
8154 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8155 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
8156 | = build_function_type_list (V8HI_type_node, |
8157 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 8158 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
8159 | = build_function_type_list (V8HI_type_node, |
8160 | V8HI_type_node, V8HI_type_node, | |
8161 | V8HI_type_node, NULL_TREE); | |
c4ad648e | 8162 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
8163 | = build_function_type_list (V4SI_type_node, |
8164 | V8HI_type_node, V8HI_type_node, | |
8165 | V4SI_type_node, NULL_TREE); | |
c4ad648e | 8166 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
8167 | = build_function_type_list (V4SI_type_node, |
8168 | V16QI_type_node, V16QI_type_node, | |
8169 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8170 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
8171 | = build_function_type_list (V16QI_type_node, |
8172 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8173 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
8174 | = build_function_type_list (V4SI_type_node, |
8175 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 8176 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
8177 | = build_function_type_list (V8HI_type_node, |
8178 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8179 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
8180 | = build_function_type_list (V4SI_type_node, |
8181 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8182 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
8183 | = build_function_type_list (V8HI_type_node, |
8184 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8185 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
8186 | = build_function_type_list (V16QI_type_node, |
8187 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8188 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
8189 | = build_function_type_list (V4SI_type_node, |
8190 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 8191 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
8192 | = build_function_type_list (V4SI_type_node, |
8193 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8194 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
8195 | = build_function_type_list (V4SI_type_node, |
8196 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8197 | tree v4si_ftype_v8hi |
8198 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
8199 | tree int_ftype_v4si_v4si | |
8200 | = build_function_type_list (integer_type_node, | |
8201 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
8202 | tree int_ftype_v4sf_v4sf | |
8203 | = build_function_type_list (integer_type_node, | |
8204 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8205 | tree int_ftype_v16qi_v16qi | |
8206 | = build_function_type_list (integer_type_node, | |
8207 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8208 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
8209 | = build_function_type_list (integer_type_node, |
8210 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8211 | |
6f317ef3 | 8212 | /* Add the simple ternary operators. */ |
2212663f | 8213 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 8214 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f | 8215 | { |
2212663f DB |
8216 | enum machine_mode mode0, mode1, mode2, mode3; |
8217 | tree type; | |
58646b77 PB |
8218 | bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
8219 | && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
2212663f | 8220 | |
58646b77 PB |
8221 | if (is_overloaded) |
8222 | { | |
8223 | mode0 = VOIDmode; | |
8224 | mode1 = VOIDmode; | |
8225 | mode2 = VOIDmode; | |
8226 | mode3 = VOIDmode; | |
8227 | } | |
8228 | else | |
8229 | { | |
8230 | if (d->name == 0 || d->icode == CODE_FOR_nothing) | |
8231 | continue; | |
f676971a | 8232 | |
58646b77 PB |
8233 | mode0 = insn_data[d->icode].operand[0].mode; |
8234 | mode1 = insn_data[d->icode].operand[1].mode; | |
8235 | mode2 = insn_data[d->icode].operand[2].mode; | |
8236 | mode3 = insn_data[d->icode].operand[3].mode; | |
8237 | } | |
8238 | ||
2212663f DB |
8239 | /* When all four are of the same mode. */ |
8240 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
8241 | { | |
8242 | switch (mode0) | |
8243 | { | |
58646b77 PB |
8244 | case VOIDmode: |
8245 | type = opaque_ftype_opaque_opaque_opaque; | |
8246 | break; | |
617e0e1d DB |
8247 | case V4SImode: |
8248 | type = v4si_ftype_v4si_v4si_v4si; | |
8249 | break; | |
2212663f DB |
8250 | case V4SFmode: |
8251 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
8252 | break; | |
8253 | case V8HImode: | |
8254 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
f676971a | 8255 | break; |
2212663f DB |
8256 | case V16QImode: |
8257 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 8258 | break; |
2212663f | 8259 | default: |
37409796 | 8260 | gcc_unreachable (); |
2212663f DB |
8261 | } |
8262 | } | |
8263 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
c4ad648e | 8264 | { |
2212663f DB |
8265 | switch (mode0) |
8266 | { | |
8267 | case V4SImode: | |
8268 | type = v4si_ftype_v4si_v4si_v16qi; | |
8269 | break; | |
8270 | case V4SFmode: | |
8271 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
8272 | break; | |
8273 | case V8HImode: | |
8274 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
f676971a | 8275 | break; |
2212663f DB |
8276 | case V16QImode: |
8277 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 8278 | break; |
2212663f | 8279 | default: |
37409796 | 8280 | gcc_unreachable (); |
2212663f DB |
8281 | } |
8282 | } | |
f676971a | 8283 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode |
2212663f | 8284 | && mode3 == V4SImode) |
24408032 | 8285 | type = v4si_ftype_v16qi_v16qi_v4si; |
f676971a | 8286 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
2212663f | 8287 | && mode3 == V4SImode) |
24408032 | 8288 | type = v4si_ftype_v8hi_v8hi_v4si; |
f676971a | 8289 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
617e0e1d | 8290 | && mode3 == V4SImode) |
24408032 AH |
8291 | type = v4sf_ftype_v4sf_v4sf_v4si; |
8292 | ||
8293 | /* vchar, vchar, vchar, 4 bit literal. */ | |
8294 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
8295 | && mode3 == QImode) | |
b9e4e5d1 | 8296 | type = v16qi_ftype_v16qi_v16qi_int; |
24408032 AH |
8297 | |
8298 | /* vshort, vshort, vshort, 4 bit literal. */ | |
8299 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
8300 | && mode3 == QImode) | |
b9e4e5d1 | 8301 | type = v8hi_ftype_v8hi_v8hi_int; |
24408032 AH |
8302 | |
8303 | /* vint, vint, vint, 4 bit literal. */ | |
8304 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
8305 | && mode3 == QImode) | |
b9e4e5d1 | 8306 | type = v4si_ftype_v4si_v4si_int; |
24408032 AH |
8307 | |
8308 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
8309 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
8310 | && mode3 == QImode) | |
b9e4e5d1 | 8311 | type = v4sf_ftype_v4sf_v4sf_int; |
24408032 | 8312 | |
2212663f | 8313 | else |
37409796 | 8314 | gcc_unreachable (); |
2212663f DB |
8315 | |
8316 | def_builtin (d->mask, d->name, type, d->code); | |
8317 | } | |
8318 | ||
0ac081f6 | 8319 | /* Add the simple binary operators. */ |
00b960c7 | 8320 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 8321 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
8322 | { |
8323 | enum machine_mode mode0, mode1, mode2; | |
8324 | tree type; | |
58646b77 PB |
8325 | bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
8326 | && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
0ac081f6 | 8327 | |
58646b77 PB |
8328 | if (is_overloaded) |
8329 | { | |
8330 | mode0 = VOIDmode; | |
8331 | mode1 = VOIDmode; | |
8332 | mode2 = VOIDmode; | |
8333 | } | |
8334 | else | |
8335 | { | |
8336 | if (d->name == 0 || d->icode == CODE_FOR_nothing) | |
8337 | continue; | |
f676971a | 8338 | |
58646b77 PB |
8339 | mode0 = insn_data[d->icode].operand[0].mode; |
8340 | mode1 = insn_data[d->icode].operand[1].mode; | |
8341 | mode2 = insn_data[d->icode].operand[2].mode; | |
8342 | } | |
0ac081f6 AH |
8343 | |
8344 | /* When all three operands are of the same mode. */ | |
8345 | if (mode0 == mode1 && mode1 == mode2) | |
8346 | { | |
8347 | switch (mode0) | |
8348 | { | |
58646b77 PB |
8349 | case VOIDmode: |
8350 | type = opaque_ftype_opaque_opaque; | |
8351 | break; | |
0ac081f6 AH |
8352 | case V4SFmode: |
8353 | type = v4sf_ftype_v4sf_v4sf; | |
8354 | break; | |
8355 | case V4SImode: | |
8356 | type = v4si_ftype_v4si_v4si; | |
8357 | break; | |
8358 | case V16QImode: | |
8359 | type = v16qi_ftype_v16qi_v16qi; | |
8360 | break; | |
8361 | case V8HImode: | |
8362 | type = v8hi_ftype_v8hi_v8hi; | |
8363 | break; | |
a3170dc6 AH |
8364 | case V2SImode: |
8365 | type = v2si_ftype_v2si_v2si; | |
8366 | break; | |
8367 | case V2SFmode: | |
8368 | type = v2sf_ftype_v2sf_v2sf; | |
8369 | break; | |
8370 | case SImode: | |
8371 | type = int_ftype_int_int; | |
8372 | break; | |
0ac081f6 | 8373 | default: |
37409796 | 8374 | gcc_unreachable (); |
0ac081f6 AH |
8375 | } |
8376 | } | |
8377 | ||
8378 | /* A few other combos we really don't want to do manually. */ | |
8379 | ||
8380 | /* vint, vfloat, vfloat. */ | |
8381 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
8382 | type = v4si_ftype_v4sf_v4sf; | |
8383 | ||
8384 | /* vshort, vchar, vchar. */ | |
8385 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
8386 | type = v8hi_ftype_v16qi_v16qi; | |
8387 | ||
8388 | /* vint, vshort, vshort. */ | |
8389 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
8390 | type = v4si_ftype_v8hi_v8hi; | |
8391 | ||
8392 | /* vshort, vint, vint. */ | |
8393 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
8394 | type = v8hi_ftype_v4si_v4si; | |
8395 | ||
8396 | /* vchar, vshort, vshort. */ | |
8397 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
8398 | type = v16qi_ftype_v8hi_v8hi; | |
8399 | ||
8400 | /* vint, vchar, vint. */ | |
8401 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
8402 | type = v4si_ftype_v16qi_v4si; | |
8403 | ||
fa066a23 AH |
8404 | /* vint, vchar, vchar. */ |
8405 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
8406 | type = v4si_ftype_v16qi_v16qi; | |
8407 | ||
0ac081f6 AH |
8408 | /* vint, vshort, vint. */ |
8409 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
8410 | type = v4si_ftype_v8hi_v4si; | |
f676971a | 8411 | |
2212663f DB |
8412 | /* vint, vint, 5 bit literal. */ |
8413 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8414 | type = v4si_ftype_v4si_int; |
f676971a | 8415 | |
2212663f DB |
8416 | /* vshort, vshort, 5 bit literal. */ |
8417 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
b9e4e5d1 | 8418 | type = v8hi_ftype_v8hi_int; |
f676971a | 8419 | |
2212663f DB |
8420 | /* vchar, vchar, 5 bit literal. */ |
8421 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
b9e4e5d1 | 8422 | type = v16qi_ftype_v16qi_int; |
0ac081f6 | 8423 | |
617e0e1d DB |
8424 | /* vfloat, vint, 5 bit literal. */ |
8425 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8426 | type = v4sf_ftype_v4si_int; |
f676971a | 8427 | |
617e0e1d DB |
8428 | /* vint, vfloat, 5 bit literal. */ |
8429 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
b9e4e5d1 | 8430 | type = v4si_ftype_v4sf_int; |
617e0e1d | 8431 | |
a3170dc6 AH |
8432 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
8433 | type = v2si_ftype_int_int; | |
8434 | ||
8435 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
8436 | type = v2si_ftype_v2si_char; | |
8437 | ||
8438 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
8439 | type = v2si_ftype_int_char; | |
8440 | ||
37409796 | 8441 | else |
0ac081f6 | 8442 | { |
37409796 NS |
8443 | /* int, x, x. */ |
8444 | gcc_assert (mode0 == SImode); | |
0ac081f6 AH |
8445 | switch (mode1) |
8446 | { | |
8447 | case V4SImode: | |
8448 | type = int_ftype_v4si_v4si; | |
8449 | break; | |
8450 | case V4SFmode: | |
8451 | type = int_ftype_v4sf_v4sf; | |
8452 | break; | |
8453 | case V16QImode: | |
8454 | type = int_ftype_v16qi_v16qi; | |
8455 | break; | |
8456 | case V8HImode: | |
8457 | type = int_ftype_v8hi_v8hi; | |
8458 | break; | |
8459 | default: | |
37409796 | 8460 | gcc_unreachable (); |
0ac081f6 AH |
8461 | } |
8462 | } | |
8463 | ||
2212663f DB |
8464 | def_builtin (d->mask, d->name, type, d->code); |
8465 | } | |
24408032 | 8466 | |
2212663f DB |
8467 | /* Add the simple unary operators. */ |
8468 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 8469 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
8470 | { |
8471 | enum machine_mode mode0, mode1; | |
8472 | tree type; | |
58646b77 PB |
8473 | bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
8474 | && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
8475 | ||
8476 | if (is_overloaded) | |
8477 | { | |
8478 | mode0 = VOIDmode; | |
8479 | mode1 = VOIDmode; | |
8480 | } | |
8481 | else | |
8482 | { | |
8483 | if (d->name == 0 || d->icode == CODE_FOR_nothing) | |
8484 | continue; | |
8485 | ||
8486 | mode0 = insn_data[d->icode].operand[0].mode; | |
8487 | mode1 = insn_data[d->icode].operand[1].mode; | |
8488 | } | |
2212663f DB |
8489 | |
8490 | if (mode0 == V4SImode && mode1 == QImode) | |
c4ad648e | 8491 | type = v4si_ftype_int; |
2212663f | 8492 | else if (mode0 == V8HImode && mode1 == QImode) |
c4ad648e | 8493 | type = v8hi_ftype_int; |
2212663f | 8494 | else if (mode0 == V16QImode && mode1 == QImode) |
c4ad648e | 8495 | type = v16qi_ftype_int; |
58646b77 PB |
8496 | else if (mode0 == VOIDmode && mode1 == VOIDmode) |
8497 | type = opaque_ftype_opaque; | |
617e0e1d DB |
8498 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
8499 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
8500 | else if (mode0 == V8HImode && mode1 == V16QImode) |
8501 | type = v8hi_ftype_v16qi; | |
8502 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
8503 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
8504 | else if (mode0 == V2SImode && mode1 == V2SImode) |
8505 | type = v2si_ftype_v2si; | |
8506 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
8507 | type = v2sf_ftype_v2sf; | |
8508 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
8509 | type = v2sf_ftype_v2si; | |
8510 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
8511 | type = v2si_ftype_v2sf; | |
8512 | else if (mode0 == V2SImode && mode1 == QImode) | |
8513 | type = v2si_ftype_char; | |
2212663f | 8514 | else |
37409796 | 8515 | gcc_unreachable (); |
2212663f | 8516 | |
0ac081f6 AH |
8517 | def_builtin (d->mask, d->name, type, d->code); |
8518 | } | |
8519 | } | |
8520 | ||
c15c90bb ZW |
8521 | static void |
8522 | rs6000_init_libfuncs (void) | |
8523 | { | |
8524 | if (!TARGET_HARD_FLOAT) | |
8525 | return; | |
8526 | ||
c9034561 | 8527 | if (DEFAULT_ABI != ABI_V4) |
c15c90bb | 8528 | { |
c9034561 | 8529 | if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC) |
c15c90bb | 8530 | { |
c9034561 | 8531 | /* AIX library routines for float->int conversion. */ |
85363ca0 ZW |
8532 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); |
8533 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
4274207b DE |
8534 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); |
8535 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
c15c90bb ZW |
8536 | } |
8537 | ||
98c41d98 DE |
8538 | /* AIX/Darwin/64-bit Linux quad floating point routines. */ |
8539 | if (!TARGET_XL_COMPAT) | |
8540 | { | |
8541 | set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); | |
8542 | set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); | |
8543 | set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); | |
8544 | set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); | |
8545 | } | |
8546 | else | |
8547 | { | |
8548 | set_optab_libfunc (add_optab, TFmode, "_xlqadd"); | |
8549 | set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); | |
8550 | set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); | |
8551 | set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); | |
8552 | } | |
c15c90bb | 8553 | } |
c9034561 | 8554 | else |
c15c90bb | 8555 | { |
c9034561 | 8556 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8557 | |
8558 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
8559 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
8560 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
8561 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
8562 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
8563 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
8564 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
8565 | ||
c9034561 ZW |
8566 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
8567 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
8568 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
8569 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
8570 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
8571 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
8572 | ||
85363ca0 ZW |
8573 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
8574 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
8575 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
8576 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
8577 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
8578 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
8579 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
c15c90bb ZW |
8580 | } |
8581 | } | |
fba73eb1 DE |
8582 | |
8583 | \f | |
8584 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
8585 | if we should let the compiler generate normal code. | |
8586 | ||
8587 | operands[0] is the destination | |
8588 | operands[1] is the length | |
57e84f18 | 8589 | operands[3] is the alignment */ |
fba73eb1 DE |
8590 | |
8591 | int | |
8592 | expand_block_clear (rtx operands[]) | |
8593 | { | |
8594 | rtx orig_dest = operands[0]; | |
8595 | rtx bytes_rtx = operands[1]; | |
57e84f18 | 8596 | rtx align_rtx = operands[3]; |
5514620a GK |
8597 | bool constp = (GET_CODE (bytes_rtx) == CONST_INT); |
8598 | HOST_WIDE_INT align; | |
8599 | HOST_WIDE_INT bytes; | |
fba73eb1 DE |
8600 | int offset; |
8601 | int clear_bytes; | |
5514620a | 8602 | int clear_step; |
fba73eb1 DE |
8603 | |
8604 | /* If this is not a fixed size move, just call memcpy */ | |
8605 | if (! constp) | |
8606 | return 0; | |
8607 | ||
37409796 NS |
8608 | /* This must be a fixed size alignment */ |
8609 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
fba73eb1 DE |
8610 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
8611 | ||
8612 | /* Anything to clear? */ | |
8613 | bytes = INTVAL (bytes_rtx); | |
8614 | if (bytes <= 0) | |
8615 | return 1; | |
8616 | ||
5514620a GK |
8617 | /* Use the builtin memset after a point, to avoid huge code bloat. |
8618 | When optimize_size, avoid any significant code bloat; calling | |
8619 | memset is about 4 instructions, so allow for one instruction to | |
8620 | load zero and three to do clearing. */ | |
8621 | if (TARGET_ALTIVEC && align >= 128) | |
8622 | clear_step = 16; | |
8623 | else if (TARGET_POWERPC64 && align >= 32) | |
8624 | clear_step = 8; | |
8625 | else | |
8626 | clear_step = 4; | |
fba73eb1 | 8627 | |
5514620a GK |
8628 | if (optimize_size && bytes > 3 * clear_step) |
8629 | return 0; | |
8630 | if (! optimize_size && bytes > 8 * clear_step) | |
fba73eb1 DE |
8631 | return 0; |
8632 | ||
8633 | for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) | |
8634 | { | |
fba73eb1 DE |
8635 | enum machine_mode mode = BLKmode; |
8636 | rtx dest; | |
f676971a | 8637 | |
5514620a GK |
8638 | if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) |
8639 | { | |
8640 | clear_bytes = 16; | |
8641 | mode = V4SImode; | |
8642 | } | |
8643 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8644 | /* 64-bit loads and stores require word-aligned | |
8645 | displacements. */ | |
8646 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) | |
fba73eb1 DE |
8647 | { |
8648 | clear_bytes = 8; | |
8649 | mode = DImode; | |
fba73eb1 | 8650 | } |
5514620a | 8651 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8652 | { /* move 4 bytes */ |
8653 | clear_bytes = 4; | |
8654 | mode = SImode; | |
fba73eb1 | 8655 | } |
5514620a | 8656 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8657 | { /* move 2 bytes */ |
8658 | clear_bytes = 2; | |
8659 | mode = HImode; | |
fba73eb1 DE |
8660 | } |
8661 | else /* move 1 byte at a time */ | |
8662 | { | |
8663 | clear_bytes = 1; | |
8664 | mode = QImode; | |
fba73eb1 | 8665 | } |
f676971a | 8666 | |
fba73eb1 | 8667 | dest = adjust_address (orig_dest, mode, offset); |
f676971a | 8668 | |
5514620a | 8669 | emit_move_insn (dest, CONST0_RTX (mode)); |
fba73eb1 DE |
8670 | } |
8671 | ||
8672 | return 1; | |
8673 | } | |
8674 | ||
35aff10b | 8675 | \f |
7e69e155 MM |
8676 | /* Expand a block move operation, and return 1 if successful. Return 0 |
8677 | if we should let the compiler generate normal code. | |
8678 | ||
8679 | operands[0] is the destination | |
8680 | operands[1] is the source | |
8681 | operands[2] is the length | |
8682 | operands[3] is the alignment */ | |
8683 | ||
3933e0e1 MM |
8684 | #define MAX_MOVE_REG 4 |
8685 | ||
7e69e155 | 8686 | int |
a2369ed3 | 8687 | expand_block_move (rtx operands[]) |
7e69e155 | 8688 | { |
b6c9286a MM |
8689 | rtx orig_dest = operands[0]; |
8690 | rtx orig_src = operands[1]; | |
7e69e155 | 8691 | rtx bytes_rtx = operands[2]; |
7e69e155 | 8692 | rtx align_rtx = operands[3]; |
3933e0e1 | 8693 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 8694 | int align; |
3933e0e1 MM |
8695 | int bytes; |
8696 | int offset; | |
7e69e155 | 8697 | int move_bytes; |
cabfd258 GK |
8698 | rtx stores[MAX_MOVE_REG]; |
8699 | int num_reg = 0; | |
7e69e155 | 8700 | |
3933e0e1 | 8701 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 8702 | if (! constp) |
3933e0e1 MM |
8703 | return 0; |
8704 | ||
37409796 NS |
8705 | /* This must be a fixed size alignment */ |
8706 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
fba73eb1 | 8707 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
5ee95df6 | 8708 | |
7e69e155 | 8709 | /* Anything to move? */ |
3933e0e1 MM |
8710 | bytes = INTVAL (bytes_rtx); |
8711 | if (bytes <= 0) | |
7e69e155 MM |
8712 | return 1; |
8713 | ||
ea9982a8 | 8714 | /* store_one_arg depends on expand_block_move to handle at least the size of |
f676971a | 8715 | reg_parm_stack_space. */ |
ea9982a8 | 8716 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
8717 | return 0; |
8718 | ||
cabfd258 | 8719 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 8720 | { |
cabfd258 | 8721 | union { |
70128ad9 | 8722 | rtx (*movmemsi) (rtx, rtx, rtx, rtx); |
a2369ed3 | 8723 | rtx (*mov) (rtx, rtx); |
cabfd258 GK |
8724 | } gen_func; |
8725 | enum machine_mode mode = BLKmode; | |
8726 | rtx src, dest; | |
f676971a | 8727 | |
5514620a GK |
8728 | /* Altivec first, since it will be faster than a string move |
8729 | when it applies, and usually not significantly larger. */ | |
8730 | if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) | |
8731 | { | |
8732 | move_bytes = 16; | |
8733 | mode = V4SImode; | |
8734 | gen_func.mov = gen_movv4si; | |
8735 | } | |
8736 | else if (TARGET_STRING | |
cabfd258 GK |
8737 | && bytes > 24 /* move up to 32 bytes at a time */ |
8738 | && ! fixed_regs[5] | |
8739 | && ! fixed_regs[6] | |
8740 | && ! fixed_regs[7] | |
8741 | && ! fixed_regs[8] | |
8742 | && ! fixed_regs[9] | |
8743 | && ! fixed_regs[10] | |
8744 | && ! fixed_regs[11] | |
8745 | && ! fixed_regs[12]) | |
7e69e155 | 8746 | { |
cabfd258 | 8747 | move_bytes = (bytes > 32) ? 32 : bytes; |
70128ad9 | 8748 | gen_func.movmemsi = gen_movmemsi_8reg; |
cabfd258 GK |
8749 | } |
8750 | else if (TARGET_STRING | |
8751 | && bytes > 16 /* move up to 24 bytes at a time */ | |
8752 | && ! fixed_regs[5] | |
8753 | && ! fixed_regs[6] | |
8754 | && ! fixed_regs[7] | |
8755 | && ! fixed_regs[8] | |
8756 | && ! fixed_regs[9] | |
8757 | && ! fixed_regs[10]) | |
8758 | { | |
8759 | move_bytes = (bytes > 24) ? 24 : bytes; | |
70128ad9 | 8760 | gen_func.movmemsi = gen_movmemsi_6reg; |
cabfd258 GK |
8761 | } |
8762 | else if (TARGET_STRING | |
8763 | && bytes > 8 /* move up to 16 bytes at a time */ | |
8764 | && ! fixed_regs[5] | |
8765 | && ! fixed_regs[6] | |
8766 | && ! fixed_regs[7] | |
8767 | && ! fixed_regs[8]) | |
8768 | { | |
8769 | move_bytes = (bytes > 16) ? 16 : bytes; | |
70128ad9 | 8770 | gen_func.movmemsi = gen_movmemsi_4reg; |
cabfd258 GK |
8771 | } |
8772 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8773 | /* 64-bit loads and stores require word-aligned | |
8774 | displacements. */ | |
fba73eb1 | 8775 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) |
cabfd258 GK |
8776 | { |
8777 | move_bytes = 8; | |
8778 | mode = DImode; | |
8779 | gen_func.mov = gen_movdi; | |
8780 | } | |
8781 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
8782 | { /* move up to 8 bytes at a time */ | |
8783 | move_bytes = (bytes > 8) ? 8 : bytes; | |
70128ad9 | 8784 | gen_func.movmemsi = gen_movmemsi_2reg; |
cabfd258 | 8785 | } |
cd7d9ca4 | 8786 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
8787 | { /* move 4 bytes */ |
8788 | move_bytes = 4; | |
8789 | mode = SImode; | |
8790 | gen_func.mov = gen_movsi; | |
8791 | } | |
cd7d9ca4 | 8792 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
8793 | { /* move 2 bytes */ |
8794 | move_bytes = 2; | |
8795 | mode = HImode; | |
8796 | gen_func.mov = gen_movhi; | |
8797 | } | |
8798 | else if (TARGET_STRING && bytes > 1) | |
8799 | { /* move up to 4 bytes at a time */ | |
8800 | move_bytes = (bytes > 4) ? 4 : bytes; | |
70128ad9 | 8801 | gen_func.movmemsi = gen_movmemsi_1reg; |
cabfd258 GK |
8802 | } |
8803 | else /* move 1 byte at a time */ | |
8804 | { | |
8805 | move_bytes = 1; | |
8806 | mode = QImode; | |
8807 | gen_func.mov = gen_movqi; | |
8808 | } | |
f676971a | 8809 | |
cabfd258 GK |
8810 | src = adjust_address (orig_src, mode, offset); |
8811 | dest = adjust_address (orig_dest, mode, offset); | |
f676971a EC |
8812 | |
8813 | if (mode != BLKmode) | |
cabfd258 GK |
8814 | { |
8815 | rtx tmp_reg = gen_reg_rtx (mode); | |
f676971a | 8816 | |
cabfd258 GK |
8817 | emit_insn ((*gen_func.mov) (tmp_reg, src)); |
8818 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 8819 | } |
3933e0e1 | 8820 | |
cabfd258 GK |
8821 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
8822 | { | |
8823 | int i; | |
8824 | for (i = 0; i < num_reg; i++) | |
8825 | emit_insn (stores[i]); | |
8826 | num_reg = 0; | |
8827 | } | |
35aff10b | 8828 | |
cabfd258 | 8829 | if (mode == BLKmode) |
7e69e155 | 8830 | { |
70128ad9 | 8831 | /* Move the address into scratch registers. The movmemsi |
cabfd258 GK |
8832 | patterns require zero offset. */ |
8833 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 8834 | { |
cabfd258 GK |
8835 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
8836 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 8837 | } |
cabfd258 | 8838 | set_mem_size (src, GEN_INT (move_bytes)); |
f676971a | 8839 | |
cabfd258 | 8840 | if (!REG_P (XEXP (dest, 0))) |
3933e0e1 | 8841 | { |
cabfd258 GK |
8842 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
8843 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 8844 | } |
cabfd258 | 8845 | set_mem_size (dest, GEN_INT (move_bytes)); |
f676971a | 8846 | |
70128ad9 | 8847 | emit_insn ((*gen_func.movmemsi) (dest, src, |
cabfd258 GK |
8848 | GEN_INT (move_bytes & 31), |
8849 | align_rtx)); | |
7e69e155 | 8850 | } |
7e69e155 MM |
8851 | } |
8852 | ||
8853 | return 1; | |
8854 | } | |
8855 | ||
d62294f5 | 8856 | \f |
9caa3eb2 DE |
8857 | /* Return a string to perform a load_multiple operation. |
8858 | operands[0] is the vector. | |
8859 | operands[1] is the source address. | |
8860 | operands[2] is the first destination register. */ | |
8861 | ||
8862 | const char * | |
a2369ed3 | 8863 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
8864 | { |
8865 | /* We have to handle the case where the pseudo used to contain the address | |
8866 | is assigned to one of the output registers. */ | |
8867 | int i, j; | |
8868 | int words = XVECLEN (operands[0], 0); | |
8869 | rtx xop[10]; | |
8870 | ||
8871 | if (XVECLEN (operands[0], 0) == 1) | |
8872 | return "{l|lwz} %2,0(%1)"; | |
8873 | ||
8874 | for (i = 0; i < words; i++) | |
8875 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
8876 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
8877 | { | |
8878 | if (i == words-1) | |
8879 | { | |
8880 | xop[0] = GEN_INT (4 * (words-1)); | |
8881 | xop[1] = operands[1]; | |
8882 | xop[2] = operands[2]; | |
8883 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
8884 | return ""; | |
8885 | } | |
8886 | else if (i == 0) | |
8887 | { | |
8888 | xop[0] = GEN_INT (4 * (words-1)); | |
8889 | xop[1] = operands[1]; | |
8890 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8891 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
8892 | return ""; | |
8893 | } | |
8894 | else | |
8895 | { | |
8896 | for (j = 0; j < words; j++) | |
8897 | if (j != i) | |
8898 | { | |
8899 | xop[0] = GEN_INT (j * 4); | |
8900 | xop[1] = operands[1]; | |
8901 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
8902 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
8903 | } | |
8904 | xop[0] = GEN_INT (i * 4); | |
8905 | xop[1] = operands[1]; | |
8906 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
8907 | return ""; | |
8908 | } | |
8909 | } | |
8910 | ||
8911 | return "{lsi|lswi} %2,%1,%N0"; | |
8912 | } | |
8913 | ||
9878760c | 8914 | \f |
a4f6c312 SS |
8915 | /* A validation routine: say whether CODE, a condition code, and MODE |
8916 | match. The other alternatives either don't make sense or should | |
8917 | never be generated. */ | |
39a10a29 | 8918 | |
48d72335 | 8919 | void |
a2369ed3 | 8920 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 | 8921 | { |
37409796 NS |
8922 | gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE |
8923 | || GET_RTX_CLASS (code) == RTX_COMM_COMPARE) | |
8924 | && GET_MODE_CLASS (mode) == MODE_CC); | |
39a10a29 GK |
8925 | |
8926 | /* These don't make sense. */ | |
37409796 NS |
8927 | gcc_assert ((code != GT && code != LT && code != GE && code != LE) |
8928 | || mode != CCUNSmode); | |
39a10a29 | 8929 | |
37409796 NS |
8930 | gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU) |
8931 | || mode == CCUNSmode); | |
39a10a29 | 8932 | |
37409796 NS |
8933 | gcc_assert (mode == CCFPmode |
8934 | || (code != ORDERED && code != UNORDERED | |
8935 | && code != UNEQ && code != LTGT | |
8936 | && code != UNGT && code != UNLT | |
8937 | && code != UNGE && code != UNLE)); | |
f676971a EC |
8938 | |
8939 | /* These should never be generated except for | |
bc9ec0e0 | 8940 | flag_finite_math_only. */ |
37409796 NS |
8941 | gcc_assert (mode != CCFPmode |
8942 | || flag_finite_math_only | |
8943 | || (code != LE && code != GE | |
8944 | && code != UNEQ && code != LTGT | |
8945 | && code != UNGT && code != UNLT)); | |
39a10a29 GK |
8946 | |
8947 | /* These are invalid; the information is not there. */ | |
37409796 | 8948 | gcc_assert (mode != CCEQmode || code == EQ || code == NE); |
39a10a29 GK |
8949 | } |
8950 | ||
9878760c RK |
8951 | \f |
8952 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
8953 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 8954 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
8955 | |
8956 | int | |
a2369ed3 | 8957 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 8958 | { |
e2c953b6 DE |
8959 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
8960 | ||
8961 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 8962 | |
b1765bde | 8963 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
8964 | } |
8965 | ||
8966 | /* Similar, but for right shift. */ | |
8967 | ||
8968 | int | |
a2369ed3 | 8969 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 8970 | { |
a7653a2c | 8971 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
8972 | |
8973 | shift_mask >>= INTVAL (shiftop); | |
8974 | ||
b1765bde | 8975 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
8976 | } |
8977 | ||
c5059423 AM |
8978 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
8979 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 8980 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
8981 | |
8982 | int | |
a2369ed3 | 8983 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 8984 | { |
c5059423 AM |
8985 | if (GET_CODE (andop) == CONST_INT) |
8986 | { | |
02071907 | 8987 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 8988 | |
c5059423 | 8989 | c = INTVAL (andop); |
02071907 | 8990 | if (c == 0 || c == ~0) |
c5059423 | 8991 | return 0; |
e2c953b6 | 8992 | |
02071907 | 8993 | shift_mask = ~0; |
c5059423 AM |
8994 | shift_mask <<= INTVAL (shiftop); |
8995 | ||
b6d08ca1 | 8996 | /* Find the least significant one bit. */ |
c5059423 AM |
8997 | lsb = c & -c; |
8998 | ||
8999 | /* It must coincide with the LSB of the shift mask. */ | |
9000 | if (-lsb != shift_mask) | |
9001 | return 0; | |
e2c953b6 | 9002 | |
c5059423 AM |
9003 | /* Invert to look for the next transition (if any). */ |
9004 | c = ~c; | |
9005 | ||
9006 | /* Remove the low group of ones (originally low group of zeros). */ | |
9007 | c &= -lsb; | |
9008 | ||
9009 | /* Again find the lsb, and check we have all 1's above. */ | |
9010 | lsb = c & -c; | |
9011 | return c == -lsb; | |
9012 | } | |
9013 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9014 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9015 | { | |
02071907 AM |
9016 | HOST_WIDE_INT low, high, lsb; |
9017 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
9018 | |
9019 | low = CONST_DOUBLE_LOW (andop); | |
9020 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9021 | high = CONST_DOUBLE_HIGH (andop); | |
9022 | ||
9023 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 9024 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
9025 | return 0; |
9026 | ||
9027 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9028 | { | |
02071907 | 9029 | shift_mask_high = ~0; |
c5059423 AM |
9030 | if (INTVAL (shiftop) > 32) |
9031 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9032 | ||
9033 | lsb = high & -high; | |
9034 | ||
9035 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
9036 | return 0; | |
9037 | ||
9038 | high = ~high; | |
9039 | high &= -lsb; | |
9040 | ||
9041 | lsb = high & -high; | |
9042 | return high == -lsb; | |
9043 | } | |
9044 | ||
02071907 | 9045 | shift_mask_low = ~0; |
c5059423 AM |
9046 | shift_mask_low <<= INTVAL (shiftop); |
9047 | ||
9048 | lsb = low & -low; | |
9049 | ||
9050 | if (-lsb != shift_mask_low) | |
9051 | return 0; | |
9052 | ||
9053 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9054 | high = ~high; | |
9055 | low = ~low; | |
9056 | low &= -lsb; | |
9057 | ||
9058 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9059 | { | |
9060 | lsb = high & -high; | |
9061 | return high == -lsb; | |
9062 | } | |
9063 | ||
9064 | lsb = low & -low; | |
9065 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
9066 | } | |
9067 | else | |
9068 | return 0; | |
9069 | } | |
e2c953b6 | 9070 | |
c5059423 AM |
9071 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
9072 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 9073 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 9074 | |
c5059423 | 9075 | int |
a2369ed3 | 9076 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 9077 | { |
e2c953b6 | 9078 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 9079 | { |
02071907 | 9080 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 9081 | |
02071907 | 9082 | shift_mask = ~0; |
c5059423 AM |
9083 | shift_mask <<= INTVAL (shiftop); |
9084 | c = INTVAL (andop); | |
9085 | ||
c1207243 | 9086 | /* Find the least significant one bit. */ |
c5059423 AM |
9087 | lsb = c & -c; |
9088 | ||
9089 | /* It must be covered by the shift mask. | |
a4f6c312 | 9090 | This test also rejects c == 0. */ |
c5059423 AM |
9091 | if ((lsb & shift_mask) == 0) |
9092 | return 0; | |
9093 | ||
9094 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
9095 | return c == -lsb && lsb != 1; | |
9096 | } | |
9097 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9098 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9099 | { | |
02071907 | 9100 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
9101 | |
9102 | low = CONST_DOUBLE_LOW (andop); | |
9103 | ||
9104 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9105 | { | |
02071907 | 9106 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
9107 | |
9108 | high = CONST_DOUBLE_HIGH (andop); | |
9109 | ||
9110 | if (low == 0) | |
9111 | { | |
02071907 | 9112 | shift_mask_high = ~0; |
c5059423 AM |
9113 | if (INTVAL (shiftop) > 32) |
9114 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9115 | ||
9116 | lsb = high & -high; | |
9117 | ||
9118 | if ((lsb & shift_mask_high) == 0) | |
9119 | return 0; | |
9120 | ||
9121 | return high == -lsb; | |
9122 | } | |
9123 | if (high != ~0) | |
9124 | return 0; | |
9125 | } | |
9126 | ||
02071907 | 9127 | shift_mask_low = ~0; |
c5059423 AM |
9128 | shift_mask_low <<= INTVAL (shiftop); |
9129 | ||
9130 | lsb = low & -low; | |
9131 | ||
9132 | if ((lsb & shift_mask_low) == 0) | |
9133 | return 0; | |
9134 | ||
9135 | return low == -lsb && lsb != 1; | |
9136 | } | |
e2c953b6 | 9137 | else |
c5059423 | 9138 | return 0; |
9878760c | 9139 | } |
35068b43 | 9140 | |
11ac38b2 DE |
9141 | /* Return 1 if operands will generate a valid arguments to rlwimi |
9142 | instruction for insert with right shift in 64-bit mode. The mask may | |
9143 | not start on the first bit or stop on the last bit because wrap-around | |
9144 | effects of instruction do not correspond to semantics of RTL insn. */ | |
9145 | ||
9146 | int | |
9147 | insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) | |
9148 | { | |
9149 | if (INTVAL (startop) < 64 | |
9150 | && INTVAL (startop) > 32 | |
9151 | && (INTVAL (sizeop) + INTVAL (startop) < 64) | |
9152 | && (INTVAL (sizeop) + INTVAL (startop) > 33) | |
9153 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96) | |
9154 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64) | |
9155 | && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) | |
9156 | return 1; | |
9157 | ||
9158 | return 0; | |
9159 | } | |
9160 | ||
35068b43 | 9161 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates |
90f81f99 | 9162 | for lfq and stfq insns iff the registers are hard registers. */ |
35068b43 RK |
9163 | |
9164 | int | |
a2369ed3 | 9165 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
9166 | { |
9167 | /* We might have been passed a SUBREG. */ | |
f676971a | 9168 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) |
35068b43 | 9169 | return 0; |
f676971a | 9170 | |
90f81f99 AP |
9171 | /* We might have been passed non floating point registers. */ |
9172 | if (!FP_REGNO_P (REGNO (reg1)) | |
9173 | || !FP_REGNO_P (REGNO (reg2))) | |
9174 | return 0; | |
35068b43 RK |
9175 | |
9176 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
9177 | } | |
9178 | ||
a4f6c312 SS |
9179 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
9180 | addr1 and addr2 must be in consecutive memory locations | |
9181 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
9182 | |
9183 | int | |
90f81f99 | 9184 | mems_ok_for_quad_peep (rtx mem1, rtx mem2) |
35068b43 | 9185 | { |
90f81f99 | 9186 | rtx addr1, addr2; |
e2c953b6 | 9187 | unsigned int reg1; |
35068b43 RK |
9188 | int offset1; |
9189 | ||
90f81f99 AP |
9190 | /* The mems cannot be volatile. */ |
9191 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
9192 | return 0; | |
f676971a | 9193 | |
90f81f99 AP |
9194 | addr1 = XEXP (mem1, 0); |
9195 | addr2 = XEXP (mem2, 0); | |
9196 | ||
35068b43 RK |
9197 | /* Extract an offset (if used) from the first addr. */ |
9198 | if (GET_CODE (addr1) == PLUS) | |
9199 | { | |
9200 | /* If not a REG, return zero. */ | |
9201 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
9202 | return 0; | |
9203 | else | |
9204 | { | |
c4ad648e | 9205 | reg1 = REGNO (XEXP (addr1, 0)); |
35068b43 RK |
9206 | /* The offset must be constant! */ |
9207 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
c4ad648e AM |
9208 | return 0; |
9209 | offset1 = INTVAL (XEXP (addr1, 1)); | |
35068b43 RK |
9210 | } |
9211 | } | |
9212 | else if (GET_CODE (addr1) != REG) | |
9213 | return 0; | |
9214 | else | |
9215 | { | |
9216 | reg1 = REGNO (addr1); | |
9217 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
9218 | offset1 = 0; | |
9219 | } | |
9220 | ||
a2369ed3 | 9221 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
f676971a | 9222 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same |
0f6937fe | 9223 | register as addr1. */ |
984e25ac | 9224 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) |
0f6937fe | 9225 | return 1; |
35068b43 RK |
9226 | if (GET_CODE (addr2) != PLUS) |
9227 | return 0; | |
9228 | ||
9229 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
9230 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
9231 | return 0; | |
9232 | ||
9233 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
9234 | return 0; | |
9235 | ||
9236 | /* The offset for the second addr must be 8 more than the first addr. */ | |
9237 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
9238 | return 0; | |
9239 | ||
9240 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
9241 | instructions. */ | |
9242 | return 1; | |
9243 | } | |
9878760c RK |
9244 | \f |
9245 | /* Return the register class of a scratch register needed to copy IN into | |
9246 | or out of a register in CLASS in MODE. If it can be done directly, | |
9247 | NO_REGS is returned. */ | |
9248 | ||
9249 | enum reg_class | |
f676971a | 9250 | secondary_reload_class (enum reg_class class, |
a9baceb1 GK |
9251 | enum machine_mode mode ATTRIBUTE_UNUSED, |
9252 | rtx in) | |
9878760c | 9253 | { |
5accd822 | 9254 | int regno; |
9878760c | 9255 | |
ab82a49f AP |
9256 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
9257 | #if TARGET_MACHO | |
c4ad648e | 9258 | && MACHOPIC_INDIRECT |
ab82a49f | 9259 | #endif |
c4ad648e | 9260 | )) |
46fad5b7 DJ |
9261 | { |
9262 | /* We cannot copy a symbolic operand directly into anything | |
c4ad648e AM |
9263 | other than BASE_REGS for TARGET_ELF. So indicate that a |
9264 | register from BASE_REGS is needed as an intermediate | |
9265 | register. | |
f676971a | 9266 | |
46fad5b7 DJ |
9267 | On Darwin, pic addresses require a load from memory, which |
9268 | needs a base register. */ | |
9269 | if (class != BASE_REGS | |
c4ad648e AM |
9270 | && (GET_CODE (in) == SYMBOL_REF |
9271 | || GET_CODE (in) == HIGH | |
9272 | || GET_CODE (in) == LABEL_REF | |
9273 | || GET_CODE (in) == CONST)) | |
9274 | return BASE_REGS; | |
46fad5b7 | 9275 | } |
e7b7998a | 9276 | |
5accd822 DE |
9277 | if (GET_CODE (in) == REG) |
9278 | { | |
9279 | regno = REGNO (in); | |
9280 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9281 | { | |
9282 | regno = true_regnum (in); | |
9283 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9284 | regno = -1; | |
9285 | } | |
9286 | } | |
9287 | else if (GET_CODE (in) == SUBREG) | |
9288 | { | |
9289 | regno = true_regnum (in); | |
9290 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9291 | regno = -1; | |
9292 | } | |
9293 | else | |
9294 | regno = -1; | |
9295 | ||
9878760c RK |
9296 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
9297 | into anything. */ | |
9298 | if (class == GENERAL_REGS || class == BASE_REGS | |
9299 | || (regno >= 0 && INT_REGNO_P (regno))) | |
9300 | return NO_REGS; | |
9301 | ||
9302 | /* Constants, memory, and FP registers can go into FP registers. */ | |
9303 | if ((regno == -1 || FP_REGNO_P (regno)) | |
9304 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
9305 | return NO_REGS; | |
9306 | ||
0ac081f6 AH |
9307 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
9308 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
9309 | && class == ALTIVEC_REGS) | |
9310 | return NO_REGS; | |
9311 | ||
9878760c RK |
9312 | /* We can copy among the CR registers. */ |
9313 | if ((class == CR_REGS || class == CR0_REGS) | |
9314 | && regno >= 0 && CR_REGNO_P (regno)) | |
9315 | return NO_REGS; | |
9316 | ||
9317 | /* Otherwise, we need GENERAL_REGS. */ | |
9318 | return GENERAL_REGS; | |
9319 | } | |
9320 | \f | |
9321 | /* Given a comparison operation, return the bit number in CCR to test. We | |
f676971a | 9322 | know this is a valid comparison. |
9878760c RK |
9323 | |
9324 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
9325 | used instead of %C, so the bits will be in different places. | |
9326 | ||
b4ac57ab | 9327 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
9328 | |
9329 | int | |
a2369ed3 | 9330 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
9331 | { |
9332 | enum rtx_code code = GET_CODE (op); | |
9333 | enum machine_mode cc_mode; | |
9334 | int cc_regnum; | |
9335 | int base_bit; | |
9ebbca7d | 9336 | rtx reg; |
9878760c | 9337 | |
ec8e098d | 9338 | if (!COMPARISON_P (op)) |
9878760c RK |
9339 | return -1; |
9340 | ||
9ebbca7d GK |
9341 | reg = XEXP (op, 0); |
9342 | ||
37409796 | 9343 | gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg))); |
9ebbca7d GK |
9344 | |
9345 | cc_mode = GET_MODE (reg); | |
9346 | cc_regnum = REGNO (reg); | |
9347 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 9348 | |
39a10a29 | 9349 | validate_condition_mode (code, cc_mode); |
c5defebb | 9350 | |
b7053a3f GK |
9351 | /* When generating a sCOND operation, only positive conditions are |
9352 | allowed. */ | |
37409796 NS |
9353 | gcc_assert (!scc_p |
9354 | || code == EQ || code == GT || code == LT || code == UNORDERED | |
9355 | || code == GTU || code == LTU); | |
f676971a | 9356 | |
9878760c RK |
9357 | switch (code) |
9358 | { | |
9359 | case NE: | |
9360 | return scc_p ? base_bit + 3 : base_bit + 2; | |
9361 | case EQ: | |
9362 | return base_bit + 2; | |
1c882ea4 | 9363 | case GT: case GTU: case UNLE: |
9878760c | 9364 | return base_bit + 1; |
1c882ea4 | 9365 | case LT: case LTU: case UNGE: |
9878760c | 9366 | return base_bit; |
1c882ea4 GK |
9367 | case ORDERED: case UNORDERED: |
9368 | return base_bit + 3; | |
9878760c RK |
9369 | |
9370 | case GE: case GEU: | |
39a10a29 | 9371 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
9372 | unordered position. So test that bit. For integer, this is ! LT |
9373 | unless this is an scc insn. */ | |
39a10a29 | 9374 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
9375 | |
9376 | case LE: case LEU: | |
39a10a29 | 9377 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 9378 | |
9878760c | 9379 | default: |
37409796 | 9380 | gcc_unreachable (); |
9878760c RK |
9381 | } |
9382 | } | |
1ff7789b | 9383 | \f |
8d30c4ee | 9384 | /* Return the GOT register. */ |
1ff7789b | 9385 | |
9390387d | 9386 | rtx |
a2369ed3 | 9387 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 9388 | { |
a4f6c312 SS |
9389 | /* The second flow pass currently (June 1999) can't update |
9390 | regs_ever_live without disturbing other parts of the compiler, so | |
9391 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
9392 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
9393 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 9394 | |
8d30c4ee | 9395 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 9396 | |
1ff7789b MM |
9397 | return pic_offset_table_rtx; |
9398 | } | |
a7df97e6 | 9399 | \f |
e2500fed GK |
9400 | /* Function to init struct machine_function. |
9401 | This will be called, via a pointer variable, | |
9402 | from push_function_context. */ | |
a7df97e6 | 9403 | |
e2500fed | 9404 | static struct machine_function * |
863d938c | 9405 | rs6000_init_machine_status (void) |
a7df97e6 | 9406 | { |
e2500fed | 9407 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 9408 | } |
9878760c | 9409 | \f |
0ba1b2ff AM |
9410 | /* These macros test for integers and extract the low-order bits. */ |
9411 | #define INT_P(X) \ | |
9412 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
9413 | && GET_MODE (X) == VOIDmode) | |
9414 | ||
9415 | #define INT_LOWPART(X) \ | |
9416 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
9417 | ||
9418 | int | |
a2369ed3 | 9419 | extract_MB (rtx op) |
0ba1b2ff AM |
9420 | { |
9421 | int i; | |
9422 | unsigned long val = INT_LOWPART (op); | |
9423 | ||
9424 | /* If the high bit is zero, the value is the first 1 bit we find | |
9425 | from the left. */ | |
9426 | if ((val & 0x80000000) == 0) | |
9427 | { | |
37409796 | 9428 | gcc_assert (val & 0xffffffff); |
0ba1b2ff AM |
9429 | |
9430 | i = 1; | |
9431 | while (((val <<= 1) & 0x80000000) == 0) | |
9432 | ++i; | |
9433 | return i; | |
9434 | } | |
9435 | ||
9436 | /* If the high bit is set and the low bit is not, or the mask is all | |
9437 | 1's, the value is zero. */ | |
9438 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9439 | return 0; | |
9440 | ||
9441 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9442 | from the right. */ | |
9443 | i = 31; | |
9444 | while (((val >>= 1) & 1) != 0) | |
9445 | --i; | |
9446 | ||
9447 | return i; | |
9448 | } | |
9449 | ||
9450 | int | |
a2369ed3 | 9451 | extract_ME (rtx op) |
0ba1b2ff AM |
9452 | { |
9453 | int i; | |
9454 | unsigned long val = INT_LOWPART (op); | |
9455 | ||
9456 | /* If the low bit is zero, the value is the first 1 bit we find from | |
9457 | the right. */ | |
9458 | if ((val & 1) == 0) | |
9459 | { | |
37409796 | 9460 | gcc_assert (val & 0xffffffff); |
0ba1b2ff AM |
9461 | |
9462 | i = 30; | |
9463 | while (((val >>= 1) & 1) == 0) | |
9464 | --i; | |
9465 | ||
9466 | return i; | |
9467 | } | |
9468 | ||
9469 | /* If the low bit is set and the high bit is not, or the mask is all | |
9470 | 1's, the value is 31. */ | |
9471 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9472 | return 31; | |
9473 | ||
9474 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9475 | from the left. */ | |
9476 | i = 0; | |
9477 | while (((val <<= 1) & 0x80000000) != 0) | |
9478 | ++i; | |
9479 | ||
9480 | return i; | |
9481 | } | |
9482 | ||
c4501e62 JJ |
9483 | /* Locate some local-dynamic symbol still in use by this function |
9484 | so that we can print its name in some tls_ld pattern. */ | |
9485 | ||
9486 | static const char * | |
863d938c | 9487 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
9488 | { |
9489 | rtx insn; | |
9490 | ||
9491 | if (cfun->machine->some_ld_name) | |
9492 | return cfun->machine->some_ld_name; | |
9493 | ||
9494 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
9495 | if (INSN_P (insn) | |
9496 | && for_each_rtx (&PATTERN (insn), | |
9497 | rs6000_get_some_local_dynamic_name_1, 0)) | |
9498 | return cfun->machine->some_ld_name; | |
9499 | ||
37409796 | 9500 | gcc_unreachable (); |
c4501e62 JJ |
9501 | } |
9502 | ||
9503 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
9504 | ||
9505 | static int | |
a2369ed3 | 9506 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
9507 | { |
9508 | rtx x = *px; | |
9509 | ||
9510 | if (GET_CODE (x) == SYMBOL_REF) | |
9511 | { | |
9512 | const char *str = XSTR (x, 0); | |
9513 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
9514 | { | |
9515 | cfun->machine->some_ld_name = str; | |
9516 | return 1; | |
9517 | } | |
9518 | } | |
9519 | ||
9520 | return 0; | |
9521 | } | |
9522 | ||
85b776df AM |
9523 | /* Write out a function code label. */ |
9524 | ||
9525 | void | |
9526 | rs6000_output_function_entry (FILE *file, const char *fname) | |
9527 | { | |
9528 | if (fname[0] != '.') | |
9529 | { | |
9530 | switch (DEFAULT_ABI) | |
9531 | { | |
9532 | default: | |
37409796 | 9533 | gcc_unreachable (); |
85b776df AM |
9534 | |
9535 | case ABI_AIX: | |
9536 | if (DOT_SYMBOLS) | |
9537 | putc ('.', file); | |
9538 | else | |
9539 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); | |
9540 | break; | |
9541 | ||
9542 | case ABI_V4: | |
9543 | case ABI_DARWIN: | |
9544 | break; | |
9545 | } | |
9546 | } | |
9547 | if (TARGET_AIX) | |
9548 | RS6000_OUTPUT_BASENAME (file, fname); | |
9549 | else | |
9550 | assemble_name (file, fname); | |
9551 | } | |
9552 | ||
9878760c RK |
9553 | /* Print an operand. Recognize special options, documented below. */ |
9554 | ||
38c1f2d7 | 9555 | #if TARGET_ELF |
d9407988 | 9556 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 9557 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
9558 | #else |
9559 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 9560 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
9561 | #endif |
9562 | ||
9878760c | 9563 | void |
a2369ed3 | 9564 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
9565 | { |
9566 | int i; | |
a260abc9 | 9567 | HOST_WIDE_INT val; |
0ba1b2ff | 9568 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
9569 | |
9570 | switch (code) | |
9571 | { | |
a8b3aeda | 9572 | case '.': |
a85d226b RK |
9573 | /* Write out an instruction after the call which may be replaced |
9574 | with glue code by the loader. This depends on the AIX version. */ | |
9575 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
9576 | return; |
9577 | ||
81eace42 GK |
9578 | /* %a is output_address. */ |
9579 | ||
9854d9ed RK |
9580 | case 'A': |
9581 | /* If X is a constant integer whose low-order 5 bits are zero, | |
9582 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 9583 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 9584 | writes a trash instruction. */ |
9854d9ed | 9585 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 9586 | putc ('l', file); |
9854d9ed | 9587 | else |
76229ac8 | 9588 | putc ('r', file); |
9854d9ed RK |
9589 | return; |
9590 | ||
9591 | case 'b': | |
e2c953b6 DE |
9592 | /* If constant, low-order 16 bits of constant, unsigned. |
9593 | Otherwise, write normally. */ | |
9594 | if (INT_P (x)) | |
9595 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
9596 | else | |
9597 | print_operand (file, x, 0); | |
cad12a8d RK |
9598 | return; |
9599 | ||
a260abc9 DE |
9600 | case 'B': |
9601 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
9602 | for 64-bit mask direction. */ | |
9390387d | 9603 | putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 9604 | return; |
a260abc9 | 9605 | |
81eace42 GK |
9606 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
9607 | output_operand. */ | |
9608 | ||
423c1189 AH |
9609 | case 'c': |
9610 | /* X is a CR register. Print the number of the GT bit of the CR. */ | |
9611 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9612 | output_operand_lossage ("invalid %%E value"); | |
9613 | else | |
9614 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); | |
9615 | return; | |
9616 | ||
9617 | case 'D': | |
6b1fedc3 | 9618 | /* Like 'J' but get to the EQ bit. */ |
37409796 | 9619 | gcc_assert (GET_CODE (x) == REG); |
423c1189 | 9620 | |
6b1fedc3 AH |
9621 | /* Bit 1 is EQ bit. */ |
9622 | i = 4 * (REGNO (x) - CR0_REGNO) + 2; | |
423c1189 | 9623 | |
64022b5d | 9624 | fprintf (file, "%d", i); |
423c1189 AH |
9625 | return; |
9626 | ||
9854d9ed | 9627 | case 'E': |
39a10a29 | 9628 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
9629 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
9630 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 9631 | else |
39a10a29 | 9632 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 9633 | return; |
9854d9ed RK |
9634 | |
9635 | case 'f': | |
9636 | /* X is a CR register. Print the shift count needed to move it | |
9637 | to the high-order four bits. */ | |
9638 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9639 | output_operand_lossage ("invalid %%f value"); | |
9640 | else | |
9ebbca7d | 9641 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9642 | return; |
9643 | ||
9644 | case 'F': | |
9645 | /* Similar, but print the count for the rotate in the opposite | |
9646 | direction. */ | |
9647 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9648 | output_operand_lossage ("invalid %%F value"); | |
9649 | else | |
9ebbca7d | 9650 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9651 | return; |
9652 | ||
9653 | case 'G': | |
9654 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 9655 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
9656 | if (GET_CODE (x) != CONST_INT) |
9657 | output_operand_lossage ("invalid %%G value"); | |
9658 | else if (INTVAL (x) >= 0) | |
76229ac8 | 9659 | putc ('z', file); |
9854d9ed | 9660 | else |
76229ac8 | 9661 | putc ('m', file); |
9854d9ed | 9662 | return; |
e2c953b6 | 9663 | |
9878760c | 9664 | case 'h': |
a4f6c312 SS |
9665 | /* If constant, output low-order five bits. Otherwise, write |
9666 | normally. */ | |
9878760c | 9667 | if (INT_P (x)) |
5f59ecb7 | 9668 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
9669 | else |
9670 | print_operand (file, x, 0); | |
9671 | return; | |
9672 | ||
64305719 | 9673 | case 'H': |
a4f6c312 SS |
9674 | /* If constant, output low-order six bits. Otherwise, write |
9675 | normally. */ | |
64305719 | 9676 | if (INT_P (x)) |
5f59ecb7 | 9677 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
9678 | else |
9679 | print_operand (file, x, 0); | |
9680 | return; | |
9681 | ||
9854d9ed RK |
9682 | case 'I': |
9683 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 9684 | if (INT_P (x)) |
76229ac8 | 9685 | putc ('i', file); |
9878760c RK |
9686 | return; |
9687 | ||
9854d9ed RK |
9688 | case 'j': |
9689 | /* Write the bit number in CCR for jump. */ | |
9690 | i = ccr_bit (x, 0); | |
9691 | if (i == -1) | |
9692 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 9693 | else |
9854d9ed | 9694 | fprintf (file, "%d", i); |
9878760c RK |
9695 | return; |
9696 | ||
9854d9ed RK |
9697 | case 'J': |
9698 | /* Similar, but add one for shift count in rlinm for scc and pass | |
9699 | scc flag to `ccr_bit'. */ | |
9700 | i = ccr_bit (x, 1); | |
9701 | if (i == -1) | |
9702 | output_operand_lossage ("invalid %%J code"); | |
9703 | else | |
a0466a68 RK |
9704 | /* If we want bit 31, write a shift count of zero, not 32. */ |
9705 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
9706 | return; |
9707 | ||
9854d9ed RK |
9708 | case 'k': |
9709 | /* X must be a constant. Write the 1's complement of the | |
9710 | constant. */ | |
9878760c | 9711 | if (! INT_P (x)) |
9854d9ed | 9712 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
9713 | else |
9714 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
9715 | return; |
9716 | ||
81eace42 | 9717 | case 'K': |
9ebbca7d GK |
9718 | /* X must be a symbolic constant on ELF. Write an |
9719 | expression suitable for an 'addi' that adds in the low 16 | |
9720 | bits of the MEM. */ | |
9721 | if (GET_CODE (x) != CONST) | |
9722 | { | |
9723 | print_operand_address (file, x); | |
9724 | fputs ("@l", file); | |
9725 | } | |
9726 | else | |
9727 | { | |
9728 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
9729 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
9730 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
9731 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 9732 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
9733 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
9734 | fputs ("@l", file); | |
ed8d2920 MM |
9735 | /* For GNU as, there must be a non-alphanumeric character |
9736 | between 'l' and the number. The '-' is added by | |
9737 | print_operand() already. */ | |
9738 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
9739 | fputs ("+", file); | |
9ebbca7d GK |
9740 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
9741 | } | |
81eace42 GK |
9742 | return; |
9743 | ||
9744 | /* %l is output_asm_label. */ | |
9ebbca7d | 9745 | |
9854d9ed RK |
9746 | case 'L': |
9747 | /* Write second word of DImode or DFmode reference. Works on register | |
9748 | or non-indexed memory only. */ | |
9749 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 9750 | fputs (reg_names[REGNO (x) + 1], file); |
9854d9ed RK |
9751 | else if (GET_CODE (x) == MEM) |
9752 | { | |
9753 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 9754 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
9755 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
9756 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
9757 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
9758 | UNITS_PER_WORD)); | |
9854d9ed | 9759 | else |
d7624dc0 RK |
9760 | output_address (XEXP (adjust_address_nv (x, SImode, |
9761 | UNITS_PER_WORD), | |
9762 | 0)); | |
ed8908e7 | 9763 | |
ba5e43aa | 9764 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9765 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9766 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 9767 | } |
9878760c | 9768 | return; |
f676971a | 9769 | |
9878760c RK |
9770 | case 'm': |
9771 | /* MB value for a mask operand. */ | |
b1765bde | 9772 | if (! mask_operand (x, SImode)) |
9878760c RK |
9773 | output_operand_lossage ("invalid %%m value"); |
9774 | ||
0ba1b2ff | 9775 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
9776 | return; |
9777 | ||
9778 | case 'M': | |
9779 | /* ME value for a mask operand. */ | |
b1765bde | 9780 | if (! mask_operand (x, SImode)) |
a260abc9 | 9781 | output_operand_lossage ("invalid %%M value"); |
9878760c | 9782 | |
0ba1b2ff | 9783 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
9784 | return; |
9785 | ||
81eace42 GK |
9786 | /* %n outputs the negative of its operand. */ |
9787 | ||
9878760c RK |
9788 | case 'N': |
9789 | /* Write the number of elements in the vector times 4. */ | |
9790 | if (GET_CODE (x) != PARALLEL) | |
9791 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
9792 | else |
9793 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
9794 | return; |
9795 | ||
9796 | case 'O': | |
9797 | /* Similar, but subtract 1 first. */ | |
9798 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 9799 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
9800 | else |
9801 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
9802 | return; |
9803 | ||
9854d9ed RK |
9804 | case 'p': |
9805 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
9806 | if (! INT_P (x) | |
2bfcf297 | 9807 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
9808 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
9809 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
9810 | else |
9811 | fprintf (file, "%d", i); | |
9854d9ed RK |
9812 | return; |
9813 | ||
9878760c RK |
9814 | case 'P': |
9815 | /* The operand must be an indirect memory reference. The result | |
8bb418a3 | 9816 | is the register name. */ |
9878760c RK |
9817 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
9818 | || REGNO (XEXP (x, 0)) >= 32) | |
9819 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 | 9820 | else |
fb5c67a7 | 9821 | fputs (reg_names[REGNO (XEXP (x, 0))], file); |
9878760c RK |
9822 | return; |
9823 | ||
dfbdccdb GK |
9824 | case 'q': |
9825 | /* This outputs the logical code corresponding to a boolean | |
9826 | expression. The expression may have one or both operands | |
39a10a29 | 9827 | negated (if one, only the first one). For condition register |
c4ad648e AM |
9828 | logical operations, it will also treat the negated |
9829 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 9830 | { |
63bc1d05 | 9831 | const char *const *t = 0; |
dfbdccdb GK |
9832 | const char *s; |
9833 | enum rtx_code code = GET_CODE (x); | |
9834 | static const char * const tbl[3][3] = { | |
9835 | { "and", "andc", "nor" }, | |
9836 | { "or", "orc", "nand" }, | |
9837 | { "xor", "eqv", "xor" } }; | |
9838 | ||
9839 | if (code == AND) | |
9840 | t = tbl[0]; | |
9841 | else if (code == IOR) | |
9842 | t = tbl[1]; | |
9843 | else if (code == XOR) | |
9844 | t = tbl[2]; | |
9845 | else | |
9846 | output_operand_lossage ("invalid %%q value"); | |
9847 | ||
9848 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
9849 | s = t[0]; | |
9850 | else | |
9851 | { | |
9852 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
9853 | s = t[2]; | |
9854 | else | |
9855 | s = t[1]; | |
9856 | } | |
f676971a | 9857 | |
dfbdccdb GK |
9858 | fputs (s, file); |
9859 | } | |
9860 | return; | |
9861 | ||
2c4a9cff DE |
9862 | case 'Q': |
9863 | if (TARGET_MFCRF) | |
3b6ce0af | 9864 | fputc (',', file); |
5efb1046 | 9865 | /* FALLTHRU */ |
2c4a9cff DE |
9866 | else |
9867 | return; | |
9868 | ||
9854d9ed RK |
9869 | case 'R': |
9870 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
9871 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9872 | output_operand_lossage ("invalid %%R value"); | |
9873 | else | |
9ebbca7d | 9874 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 9875 | return; |
9854d9ed RK |
9876 | |
9877 | case 's': | |
9878 | /* Low 5 bits of 32 - value */ | |
9879 | if (! INT_P (x)) | |
9880 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
9881 | else |
9882 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 9883 | return; |
9854d9ed | 9884 | |
a260abc9 | 9885 | case 'S': |
0ba1b2ff | 9886 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
9887 | CONST_INT 32-bit mask is considered sign-extended so any |
9888 | transition must occur within the CONST_INT, not on the boundary. */ | |
4ae234b0 | 9889 | if (! mask_operand (x, DImode)) |
a260abc9 DE |
9890 | output_operand_lossage ("invalid %%S value"); |
9891 | ||
0ba1b2ff | 9892 | uval = INT_LOWPART (x); |
a260abc9 | 9893 | |
0ba1b2ff | 9894 | if (uval & 1) /* Clear Left */ |
a260abc9 | 9895 | { |
f099d360 GK |
9896 | #if HOST_BITS_PER_WIDE_INT > 64 |
9897 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9898 | #endif | |
0ba1b2ff | 9899 | i = 64; |
a260abc9 | 9900 | } |
0ba1b2ff | 9901 | else /* Clear Right */ |
a260abc9 | 9902 | { |
0ba1b2ff | 9903 | uval = ~uval; |
f099d360 GK |
9904 | #if HOST_BITS_PER_WIDE_INT > 64 |
9905 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9906 | #endif | |
0ba1b2ff | 9907 | i = 63; |
a260abc9 | 9908 | } |
0ba1b2ff AM |
9909 | while (uval != 0) |
9910 | --i, uval >>= 1; | |
37409796 | 9911 | gcc_assert (i >= 0); |
0ba1b2ff AM |
9912 | fprintf (file, "%d", i); |
9913 | return; | |
a260abc9 | 9914 | |
a3170dc6 AH |
9915 | case 't': |
9916 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
37409796 | 9917 | gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode); |
a3170dc6 AH |
9918 | |
9919 | /* Bit 3 is OV bit. */ | |
9920 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
9921 | ||
9922 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
9923 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9924 | return; | |
9925 | ||
cccf3bdc DE |
9926 | case 'T': |
9927 | /* Print the symbolic name of a branch target register. */ | |
9928 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
9929 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
9930 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 9931 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
9932 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
9933 | else | |
9934 | fputs ("ctr", file); | |
9935 | return; | |
9936 | ||
9854d9ed | 9937 | case 'u': |
802a0058 | 9938 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
9939 | if (! INT_P (x)) |
9940 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 | 9941 | else |
f676971a | 9942 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
e2c953b6 | 9943 | (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
9944 | return; |
9945 | ||
802a0058 MM |
9946 | case 'v': |
9947 | /* High-order 16 bits of constant for use in signed operand. */ | |
9948 | if (! INT_P (x)) | |
9949 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 9950 | else |
134c32f6 DE |
9951 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
9952 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9953 | return; | |
802a0058 | 9954 | |
9854d9ed RK |
9955 | case 'U': |
9956 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
9957 | if (GET_CODE (x) == MEM | |
9958 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
9959 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 9960 | putc ('u', file); |
9854d9ed | 9961 | return; |
9878760c | 9962 | |
e0cd0770 JC |
9963 | case 'V': |
9964 | /* Print the trap code for this operand. */ | |
9965 | switch (GET_CODE (x)) | |
9966 | { | |
9967 | case EQ: | |
9968 | fputs ("eq", file); /* 4 */ | |
9969 | break; | |
9970 | case NE: | |
9971 | fputs ("ne", file); /* 24 */ | |
9972 | break; | |
9973 | case LT: | |
9974 | fputs ("lt", file); /* 16 */ | |
9975 | break; | |
9976 | case LE: | |
9977 | fputs ("le", file); /* 20 */ | |
9978 | break; | |
9979 | case GT: | |
9980 | fputs ("gt", file); /* 8 */ | |
9981 | break; | |
9982 | case GE: | |
9983 | fputs ("ge", file); /* 12 */ | |
9984 | break; | |
9985 | case LTU: | |
9986 | fputs ("llt", file); /* 2 */ | |
9987 | break; | |
9988 | case LEU: | |
9989 | fputs ("lle", file); /* 6 */ | |
9990 | break; | |
9991 | case GTU: | |
9992 | fputs ("lgt", file); /* 1 */ | |
9993 | break; | |
9994 | case GEU: | |
9995 | fputs ("lge", file); /* 5 */ | |
9996 | break; | |
9997 | default: | |
37409796 | 9998 | gcc_unreachable (); |
e0cd0770 JC |
9999 | } |
10000 | break; | |
10001 | ||
9854d9ed RK |
10002 | case 'w': |
10003 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
10004 | normally. */ | |
10005 | if (INT_P (x)) | |
f676971a | 10006 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5f59ecb7 | 10007 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); |
9854d9ed RK |
10008 | else |
10009 | print_operand (file, x, 0); | |
9878760c RK |
10010 | return; |
10011 | ||
9854d9ed | 10012 | case 'W': |
e2c953b6 | 10013 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
10014 | val = (GET_CODE (x) == CONST_INT |
10015 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
10016 | ||
10017 | if (val < 0) | |
10018 | i = -1; | |
9854d9ed | 10019 | else |
e2c953b6 DE |
10020 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
10021 | if ((val <<= 1) < 0) | |
10022 | break; | |
10023 | ||
10024 | #if HOST_BITS_PER_WIDE_INT == 32 | |
10025 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
10026 | i += 32; /* zero-extend high-part was all 0's */ | |
10027 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
10028 | { | |
10029 | val = CONST_DOUBLE_LOW (x); | |
10030 | ||
37409796 NS |
10031 | gcc_assert (val); |
10032 | if (val < 0) | |
e2c953b6 DE |
10033 | --i; |
10034 | else | |
10035 | for ( ; i < 64; i++) | |
10036 | if ((val <<= 1) < 0) | |
10037 | break; | |
10038 | } | |
10039 | #endif | |
10040 | ||
10041 | fprintf (file, "%d", i + 1); | |
9854d9ed | 10042 | return; |
9878760c | 10043 | |
9854d9ed RK |
10044 | case 'X': |
10045 | if (GET_CODE (x) == MEM | |
4d588c14 | 10046 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 10047 | putc ('x', file); |
9854d9ed | 10048 | return; |
9878760c | 10049 | |
9854d9ed RK |
10050 | case 'Y': |
10051 | /* Like 'L', for third word of TImode */ | |
10052 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10053 | fputs (reg_names[REGNO (x) + 2], file); |
9854d9ed | 10054 | else if (GET_CODE (x) == MEM) |
9878760c | 10055 | { |
9854d9ed RK |
10056 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
10057 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10058 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 10059 | else |
d7624dc0 | 10060 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 10061 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10062 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10063 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
10064 | } |
10065 | return; | |
f676971a | 10066 | |
9878760c | 10067 | case 'z': |
b4ac57ab RS |
10068 | /* X is a SYMBOL_REF. Write out the name preceded by a |
10069 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
10070 | names. If we are configured for System V (or the embedded ABI) on |
10071 | the PowerPC, do not emit the period, since those systems do not use | |
10072 | TOCs and the like. */ | |
37409796 | 10073 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
9878760c | 10074 | |
c4ad648e AM |
10075 | /* Mark the decl as referenced so that cgraph will output the |
10076 | function. */ | |
9bf6462a | 10077 | if (SYMBOL_REF_DECL (x)) |
c4ad648e | 10078 | mark_decl_referenced (SYMBOL_REF_DECL (x)); |
9bf6462a | 10079 | |
85b776df | 10080 | /* For macho, check to see if we need a stub. */ |
f9da97f0 AP |
10081 | if (TARGET_MACHO) |
10082 | { | |
10083 | const char *name = XSTR (x, 0); | |
a031e781 | 10084 | #if TARGET_MACHO |
3b48085e | 10085 | if (MACHOPIC_INDIRECT |
11abc112 MM |
10086 | && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION) |
10087 | name = machopic_indirection_name (x, /*stub_p=*/true); | |
f9da97f0 AP |
10088 | #endif |
10089 | assemble_name (file, name); | |
10090 | } | |
85b776df | 10091 | else if (!DOT_SYMBOLS) |
9739c90c | 10092 | assemble_name (file, XSTR (x, 0)); |
85b776df AM |
10093 | else |
10094 | rs6000_output_function_entry (file, XSTR (x, 0)); | |
9878760c RK |
10095 | return; |
10096 | ||
9854d9ed RK |
10097 | case 'Z': |
10098 | /* Like 'L', for last word of TImode. */ | |
10099 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10100 | fputs (reg_names[REGNO (x) + 3], file); |
9854d9ed RK |
10101 | else if (GET_CODE (x) == MEM) |
10102 | { | |
10103 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
10104 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10105 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 10106 | else |
d7624dc0 | 10107 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 10108 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10109 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10110 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 10111 | } |
5c23c401 | 10112 | return; |
0ac081f6 | 10113 | |
a3170dc6 | 10114 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
10115 | case 'y': |
10116 | { | |
10117 | rtx tmp; | |
10118 | ||
37409796 | 10119 | gcc_assert (GET_CODE (x) == MEM); |
0ac081f6 AH |
10120 | |
10121 | tmp = XEXP (x, 0); | |
10122 | ||
993f19a8 | 10123 | if (TARGET_E500) |
a3170dc6 AH |
10124 | { |
10125 | /* Handle [reg]. */ | |
10126 | if (GET_CODE (tmp) == REG) | |
10127 | { | |
10128 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
10129 | break; | |
10130 | } | |
10131 | /* Handle [reg+UIMM]. */ | |
10132 | else if (GET_CODE (tmp) == PLUS && | |
10133 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
10134 | { | |
10135 | int x; | |
10136 | ||
37409796 | 10137 | gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG); |
a3170dc6 AH |
10138 | |
10139 | x = INTVAL (XEXP (tmp, 1)); | |
10140 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
10141 | break; | |
10142 | } | |
10143 | ||
10144 | /* Fall through. Must be [reg+reg]. */ | |
10145 | } | |
850e8d3d DN |
10146 | if (TARGET_ALTIVEC |
10147 | && GET_CODE (tmp) == AND | |
10148 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT | |
10149 | && INTVAL (XEXP (tmp, 1)) == -16) | |
10150 | tmp = XEXP (tmp, 0); | |
0ac081f6 | 10151 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 10152 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
37409796 | 10153 | else |
0ac081f6 | 10154 | { |
37409796 NS |
10155 | gcc_assert (GET_CODE (tmp) == PLUS |
10156 | && GET_CODE (XEXP (tmp, 1)) == REG); | |
10157 | ||
0ac081f6 AH |
10158 | if (REGNO (XEXP (tmp, 0)) == 0) |
10159 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
10160 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
10161 | else | |
10162 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
10163 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
10164 | } | |
0ac081f6 AH |
10165 | break; |
10166 | } | |
f676971a | 10167 | |
9878760c RK |
10168 | case 0: |
10169 | if (GET_CODE (x) == REG) | |
10170 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
10171 | else if (GET_CODE (x) == MEM) | |
10172 | { | |
10173 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
10174 | know the width from the mode. */ | |
10175 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
10176 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
10177 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10178 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
10179 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
10180 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10181 | else |
a54d04b7 | 10182 | output_address (XEXP (x, 0)); |
9878760c RK |
10183 | } |
10184 | else | |
a54d04b7 | 10185 | output_addr_const (file, x); |
a85d226b | 10186 | return; |
9878760c | 10187 | |
c4501e62 JJ |
10188 | case '&': |
10189 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
10190 | return; | |
10191 | ||
9878760c RK |
10192 | default: |
10193 | output_operand_lossage ("invalid %%xn code"); | |
10194 | } | |
10195 | } | |
10196 | \f | |
10197 | /* Print the address of an operand. */ | |
10198 | ||
10199 | void | |
a2369ed3 | 10200 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
10201 | { |
10202 | if (GET_CODE (x) == REG) | |
4697a36c | 10203 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
10204 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
10205 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
10206 | { |
10207 | output_addr_const (file, x); | |
ba5e43aa | 10208 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10209 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10210 | reg_names[SMALL_DATA_REG]); | |
37409796 NS |
10211 | else |
10212 | gcc_assert (!TARGET_TOC); | |
9878760c RK |
10213 | } |
10214 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
10215 | { | |
10216 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
10217 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
10218 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 10219 | else |
4697a36c MM |
10220 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
10221 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
10222 | } |
10223 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
10224 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
10225 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
10226 | #if TARGET_ELF |
10227 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 10228 | && CONSTANT_P (XEXP (x, 1))) |
4697a36c MM |
10229 | { |
10230 | output_addr_const (file, XEXP (x, 1)); | |
10231 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10232 | } | |
c859cda6 DJ |
10233 | #endif |
10234 | #if TARGET_MACHO | |
10235 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 10236 | && CONSTANT_P (XEXP (x, 1))) |
c859cda6 DJ |
10237 | { |
10238 | fprintf (file, "lo16("); | |
10239 | output_addr_const (file, XEXP (x, 1)); | |
10240 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10241 | } | |
3cb999d8 | 10242 | #endif |
4d588c14 | 10243 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 10244 | { |
2bfcf297 | 10245 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 10246 | { |
2bfcf297 DB |
10247 | rtx contains_minus = XEXP (x, 1); |
10248 | rtx minus, symref; | |
10249 | const char *name; | |
f676971a | 10250 | |
9ebbca7d | 10251 | /* Find the (minus (sym) (toc)) buried in X, and temporarily |
a4f6c312 | 10252 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
10253 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
10254 | contains_minus = XEXP (contains_minus, 0); | |
10255 | ||
2bfcf297 DB |
10256 | minus = XEXP (contains_minus, 0); |
10257 | symref = XEXP (minus, 0); | |
10258 | XEXP (contains_minus, 0) = symref; | |
10259 | if (TARGET_ELF) | |
10260 | { | |
10261 | char *newname; | |
10262 | ||
10263 | name = XSTR (symref, 0); | |
10264 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
10265 | strcpy (newname, name); | |
10266 | strcat (newname, "@toc"); | |
10267 | XSTR (symref, 0) = newname; | |
10268 | } | |
10269 | output_addr_const (file, XEXP (x, 1)); | |
10270 | if (TARGET_ELF) | |
10271 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
10272 | XEXP (contains_minus, 0) = minus; |
10273 | } | |
10274 | else | |
10275 | output_addr_const (file, XEXP (x, 1)); | |
10276 | ||
10277 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
10278 | } | |
9878760c | 10279 | else |
37409796 | 10280 | gcc_unreachable (); |
9878760c RK |
10281 | } |
10282 | \f | |
88cad84b | 10283 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
10284 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
10285 | is defined. It also needs to handle DI-mode objects on 64-bit | |
10286 | targets. */ | |
10287 | ||
10288 | static bool | |
a2369ed3 | 10289 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 10290 | { |
f4f4921e | 10291 | #ifdef RELOCATABLE_NEEDS_FIXUP |
301d03af | 10292 | /* Special handling for SI values. */ |
84dcde01 | 10293 | if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p) |
301d03af | 10294 | { |
a2369ed3 | 10295 | extern int in_toc_section (void); |
301d03af | 10296 | static int recurse = 0; |
f676971a | 10297 | |
301d03af RS |
10298 | /* For -mrelocatable, we mark all addresses that need to be fixed up |
10299 | in the .fixup section. */ | |
10300 | if (TARGET_RELOCATABLE | |
10301 | && !in_toc_section () | |
10302 | && !in_text_section () | |
642af3be | 10303 | && !in_unlikely_text_section () |
301d03af RS |
10304 | && !recurse |
10305 | && GET_CODE (x) != CONST_INT | |
10306 | && GET_CODE (x) != CONST_DOUBLE | |
10307 | && CONSTANT_P (x)) | |
10308 | { | |
10309 | char buf[256]; | |
10310 | ||
10311 | recurse = 1; | |
10312 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
10313 | fixuplabelno++; | |
10314 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
10315 | fprintf (asm_out_file, "\t.long\t("); | |
10316 | output_addr_const (asm_out_file, x); | |
10317 | fprintf (asm_out_file, ")@fixup\n"); | |
10318 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
10319 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
10320 | fprintf (asm_out_file, "\t.long\t"); | |
10321 | assemble_name (asm_out_file, buf); | |
10322 | fprintf (asm_out_file, "\n\t.previous\n"); | |
10323 | recurse = 0; | |
10324 | return true; | |
10325 | } | |
10326 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
10327 | address into the address of the descriptor, not the function | |
10328 | itself. */ | |
10329 | else if (GET_CODE (x) == SYMBOL_REF | |
10330 | && XSTR (x, 0)[0] == '.' | |
10331 | && DEFAULT_ABI == ABI_AIX) | |
10332 | { | |
10333 | const char *name = XSTR (x, 0); | |
10334 | while (*name == '.') | |
10335 | name++; | |
10336 | ||
10337 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
10338 | return true; | |
10339 | } | |
10340 | } | |
f4f4921e | 10341 | #endif /* RELOCATABLE_NEEDS_FIXUP */ |
301d03af RS |
10342 | return default_assemble_integer (x, size, aligned_p); |
10343 | } | |
93638d7a AM |
10344 | |
10345 | #ifdef HAVE_GAS_HIDDEN | |
10346 | /* Emit an assembler directive to set symbol visibility for DECL to | |
10347 | VISIBILITY_TYPE. */ | |
10348 | ||
5add3202 | 10349 | static void |
a2369ed3 | 10350 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 10351 | { |
93638d7a AM |
10352 | /* Functions need to have their entry point symbol visibility set as |
10353 | well as their descriptor symbol visibility. */ | |
85b776df AM |
10354 | if (DEFAULT_ABI == ABI_AIX |
10355 | && DOT_SYMBOLS | |
10356 | && TREE_CODE (decl) == FUNCTION_DECL) | |
93638d7a | 10357 | { |
25fdb4dc | 10358 | static const char * const visibility_types[] = { |
c4ad648e | 10359 | NULL, "internal", "hidden", "protected" |
25fdb4dc RH |
10360 | }; |
10361 | ||
10362 | const char *name, *type; | |
93638d7a AM |
10363 | |
10364 | name = ((* targetm.strip_name_encoding) | |
10365 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 10366 | type = visibility_types[vis]; |
93638d7a | 10367 | |
25fdb4dc RH |
10368 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
10369 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 10370 | } |
25fdb4dc RH |
10371 | else |
10372 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
10373 | } |
10374 | #endif | |
301d03af | 10375 | \f |
39a10a29 | 10376 | enum rtx_code |
a2369ed3 | 10377 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
10378 | { |
10379 | /* Reversal of FP compares takes care -- an ordered compare | |
10380 | becomes an unordered compare and vice versa. */ | |
f676971a | 10381 | if (mode == CCFPmode |
bc9ec0e0 GK |
10382 | && (!flag_finite_math_only |
10383 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
10384 | || code == UNEQ || code == LTGT)) | |
bab6226b | 10385 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 10386 | else |
bab6226b | 10387 | return reverse_condition (code); |
39a10a29 GK |
10388 | } |
10389 | ||
39a10a29 GK |
10390 | /* Generate a compare for CODE. Return a brand-new rtx that |
10391 | represents the result of the compare. */ | |
a4f6c312 | 10392 | |
39a10a29 | 10393 | static rtx |
a2369ed3 | 10394 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
10395 | { |
10396 | enum machine_mode comp_mode; | |
10397 | rtx compare_result; | |
10398 | ||
10399 | if (rs6000_compare_fp_p) | |
10400 | comp_mode = CCFPmode; | |
10401 | else if (code == GTU || code == LTU | |
c4ad648e | 10402 | || code == GEU || code == LEU) |
39a10a29 | 10403 | comp_mode = CCUNSmode; |
60934f9c NS |
10404 | else if ((code == EQ || code == NE) |
10405 | && GET_CODE (rs6000_compare_op0) == SUBREG | |
10406 | && GET_CODE (rs6000_compare_op1) == SUBREG | |
10407 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0) | |
10408 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1)) | |
10409 | /* These are unsigned values, perhaps there will be a later | |
10410 | ordering compare that can be shared with this one. | |
10411 | Unfortunately we cannot detect the signedness of the operands | |
10412 | for non-subregs. */ | |
10413 | comp_mode = CCUNSmode; | |
39a10a29 GK |
10414 | else |
10415 | comp_mode = CCmode; | |
10416 | ||
10417 | /* First, the compare. */ | |
10418 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
10419 | |
10420 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
10421 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
10422 | && rs6000_compare_fp_p) | |
a3170dc6 | 10423 | { |
64022b5d | 10424 | rtx cmp, or_result, compare_result2; |
4d4cbc0e AH |
10425 | enum machine_mode op_mode = GET_MODE (rs6000_compare_op0); |
10426 | ||
10427 | if (op_mode == VOIDmode) | |
10428 | op_mode = GET_MODE (rs6000_compare_op1); | |
a3170dc6 | 10429 | |
423c1189 AH |
10430 | /* Note: The E500 comparison instructions set the GT bit (x + |
10431 | 1), on success. This explains the mess. */ | |
10432 | ||
a3170dc6 AH |
10433 | switch (code) |
10434 | { | |
423c1189 | 10435 | case EQ: case UNEQ: case NE: case LTGT: |
37409796 NS |
10436 | switch (op_mode) |
10437 | { | |
10438 | case SFmode: | |
10439 | cmp = flag_unsafe_math_optimizations | |
10440 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, | |
10441 | rs6000_compare_op1) | |
10442 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
10443 | rs6000_compare_op1); | |
10444 | break; | |
10445 | ||
10446 | case DFmode: | |
10447 | cmp = flag_unsafe_math_optimizations | |
10448 | ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, | |
10449 | rs6000_compare_op1) | |
10450 | : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, | |
10451 | rs6000_compare_op1); | |
10452 | break; | |
10453 | ||
10454 | default: | |
10455 | gcc_unreachable (); | |
10456 | } | |
a3170dc6 | 10457 | break; |
37409796 | 10458 | |
423c1189 | 10459 | case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: |
37409796 NS |
10460 | switch (op_mode) |
10461 | { | |
10462 | case SFmode: | |
10463 | cmp = flag_unsafe_math_optimizations | |
10464 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, | |
10465 | rs6000_compare_op1) | |
10466 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
10467 | rs6000_compare_op1); | |
10468 | break; | |
10469 | ||
10470 | case DFmode: | |
10471 | cmp = flag_unsafe_math_optimizations | |
10472 | ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, | |
10473 | rs6000_compare_op1) | |
10474 | : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, | |
10475 | rs6000_compare_op1); | |
10476 | break; | |
10477 | ||
10478 | default: | |
10479 | gcc_unreachable (); | |
10480 | } | |
a3170dc6 | 10481 | break; |
37409796 | 10482 | |
423c1189 | 10483 | case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: |
37409796 NS |
10484 | switch (op_mode) |
10485 | { | |
10486 | case SFmode: | |
10487 | cmp = flag_unsafe_math_optimizations | |
10488 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, | |
10489 | rs6000_compare_op1) | |
10490 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
10491 | rs6000_compare_op1); | |
10492 | break; | |
10493 | ||
10494 | case DFmode: | |
10495 | cmp = flag_unsafe_math_optimizations | |
10496 | ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, | |
10497 | rs6000_compare_op1) | |
10498 | : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, | |
10499 | rs6000_compare_op1); | |
10500 | break; | |
10501 | ||
10502 | default: | |
10503 | gcc_unreachable (); | |
10504 | } | |
a3170dc6 | 10505 | break; |
4d4cbc0e | 10506 | default: |
37409796 | 10507 | gcc_unreachable (); |
a3170dc6 AH |
10508 | } |
10509 | ||
10510 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
10511 | if (code == LE || code == GE || code == LEU || code == GEU) | |
10512 | { | |
a3170dc6 AH |
10513 | emit_insn (cmp); |
10514 | ||
10515 | switch (code) | |
10516 | { | |
10517 | case LE: code = LT; break; | |
10518 | case GE: code = GT; break; | |
10519 | case LEU: code = LT; break; | |
10520 | case GEU: code = GT; break; | |
37409796 | 10521 | default: gcc_unreachable (); |
a3170dc6 AH |
10522 | } |
10523 | ||
a3170dc6 AH |
10524 | compare_result2 = gen_reg_rtx (CCFPmode); |
10525 | ||
10526 | /* Do the EQ. */ | |
37409796 NS |
10527 | switch (op_mode) |
10528 | { | |
10529 | case SFmode: | |
10530 | cmp = flag_unsafe_math_optimizations | |
10531 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, | |
10532 | rs6000_compare_op1) | |
10533 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
10534 | rs6000_compare_op1); | |
10535 | break; | |
10536 | ||
10537 | case DFmode: | |
10538 | cmp = flag_unsafe_math_optimizations | |
10539 | ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, | |
10540 | rs6000_compare_op1) | |
10541 | : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, | |
10542 | rs6000_compare_op1); | |
10543 | break; | |
10544 | ||
10545 | default: | |
10546 | gcc_unreachable (); | |
10547 | } | |
a3170dc6 AH |
10548 | emit_insn (cmp); |
10549 | ||
a3170dc6 | 10550 | /* OR them together. */ |
64022b5d AH |
10551 | or_result = gen_reg_rtx (CCFPmode); |
10552 | cmp = gen_e500_cr_ior_compare (or_result, compare_result, | |
10553 | compare_result2); | |
a3170dc6 AH |
10554 | compare_result = or_result; |
10555 | code = EQ; | |
10556 | } | |
10557 | else | |
10558 | { | |
a3170dc6 | 10559 | if (code == NE || code == LTGT) |
a3170dc6 | 10560 | code = NE; |
423c1189 AH |
10561 | else |
10562 | code = EQ; | |
a3170dc6 AH |
10563 | } |
10564 | ||
10565 | emit_insn (cmp); | |
10566 | } | |
10567 | else | |
de17c25f DE |
10568 | { |
10569 | /* Generate XLC-compatible TFmode compare as PARALLEL with extra | |
10570 | CLOBBERs to match cmptf_internal2 pattern. */ | |
10571 | if (comp_mode == CCFPmode && TARGET_XL_COMPAT | |
10572 | && GET_MODE (rs6000_compare_op0) == TFmode | |
10573 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
10574 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128) | |
10575 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
10576 | gen_rtvec (9, | |
10577 | gen_rtx_SET (VOIDmode, | |
10578 | compare_result, | |
10579 | gen_rtx_COMPARE (comp_mode, | |
10580 | rs6000_compare_op0, | |
10581 | rs6000_compare_op1)), | |
10582 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10583 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10584 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10585 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10586 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10587 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10588 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10589 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode))))); | |
10590 | else | |
10591 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
10592 | gen_rtx_COMPARE (comp_mode, | |
10593 | rs6000_compare_op0, | |
10594 | rs6000_compare_op1))); | |
10595 | } | |
f676971a | 10596 | |
ca5adc63 | 10597 | /* Some kinds of FP comparisons need an OR operation; |
e7108df9 | 10598 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 10599 | if (rs6000_compare_fp_p |
e7108df9 DE |
10600 | && !flag_finite_math_only |
10601 | && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) | |
39a10a29 GK |
10602 | && (code == LE || code == GE |
10603 | || code == UNEQ || code == LTGT | |
10604 | || code == UNGT || code == UNLT)) | |
10605 | { | |
10606 | enum rtx_code or1, or2; | |
10607 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
10608 | rtx or_result = gen_reg_rtx (CCEQmode); | |
f676971a | 10609 | |
39a10a29 GK |
10610 | switch (code) |
10611 | { | |
10612 | case LE: or1 = LT; or2 = EQ; break; | |
10613 | case GE: or1 = GT; or2 = EQ; break; | |
10614 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
10615 | case LTGT: or1 = LT; or2 = GT; break; | |
10616 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
10617 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
37409796 | 10618 | default: gcc_unreachable (); |
39a10a29 GK |
10619 | } |
10620 | validate_condition_mode (or1, comp_mode); | |
10621 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
10622 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
10623 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
10624 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
10625 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
10626 | const_true_rtx); | |
10627 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
10628 | ||
10629 | compare_result = or_result; | |
10630 | code = EQ; | |
10631 | } | |
10632 | ||
10633 | validate_condition_mode (code, GET_MODE (compare_result)); | |
f676971a | 10634 | |
1c563bed | 10635 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
10636 | } |
10637 | ||
10638 | ||
10639 | /* Emit the RTL for an sCOND pattern. */ | |
10640 | ||
10641 | void | |
a2369ed3 | 10642 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
10643 | { |
10644 | rtx condition_rtx; | |
10645 | enum machine_mode op_mode; | |
b7053a3f | 10646 | enum rtx_code cond_code; |
39a10a29 GK |
10647 | |
10648 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
10649 | cond_code = GET_CODE (condition_rtx); |
10650 | ||
423c1189 AH |
10651 | if (TARGET_E500 && rs6000_compare_fp_p |
10652 | && !TARGET_FPRS && TARGET_HARD_FLOAT) | |
10653 | { | |
10654 | rtx t; | |
10655 | ||
10656 | PUT_MODE (condition_rtx, SImode); | |
10657 | t = XEXP (condition_rtx, 0); | |
10658 | ||
37409796 | 10659 | gcc_assert (cond_code == NE || cond_code == EQ); |
423c1189 AH |
10660 | |
10661 | if (cond_code == NE) | |
64022b5d | 10662 | emit_insn (gen_e500_flip_gt_bit (t, t)); |
423c1189 | 10663 | |
64022b5d | 10664 | emit_insn (gen_move_from_CR_gt_bit (result, t)); |
423c1189 AH |
10665 | return; |
10666 | } | |
10667 | ||
b7053a3f GK |
10668 | if (cond_code == NE |
10669 | || cond_code == GE || cond_code == LE | |
10670 | || cond_code == GEU || cond_code == LEU | |
10671 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
10672 | { | |
10673 | rtx not_result = gen_reg_rtx (CCEQmode); | |
10674 | rtx not_op, rev_cond_rtx; | |
10675 | enum machine_mode cc_mode; | |
f676971a | 10676 | |
b7053a3f GK |
10677 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); |
10678 | ||
1c563bed | 10679 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 10680 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
10681 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
10682 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
10683 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
10684 | } | |
39a10a29 GK |
10685 | |
10686 | op_mode = GET_MODE (rs6000_compare_op0); | |
10687 | if (op_mode == VOIDmode) | |
10688 | op_mode = GET_MODE (rs6000_compare_op1); | |
10689 | ||
10690 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10691 | { | |
10692 | PUT_MODE (condition_rtx, DImode); | |
10693 | convert_move (result, condition_rtx, 0); | |
10694 | } | |
10695 | else | |
10696 | { | |
10697 | PUT_MODE (condition_rtx, SImode); | |
10698 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
10699 | } | |
10700 | } | |
10701 | ||
39a10a29 GK |
10702 | /* Emit a branch of kind CODE to location LOC. */ |
10703 | ||
10704 | void | |
a2369ed3 | 10705 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
10706 | { |
10707 | rtx condition_rtx, loc_ref; | |
10708 | ||
10709 | condition_rtx = rs6000_generate_compare (code); | |
10710 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
10711 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
10712 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
10713 | loc_ref, pc_rtx))); | |
10714 | } | |
10715 | ||
12a4e8c5 GK |
10716 | /* Return the string to output a conditional branch to LABEL, which is |
10717 | the operand number of the label, or -1 if the branch is really a | |
f676971a | 10718 | conditional return. |
12a4e8c5 GK |
10719 | |
10720 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
10721 | condition code register and its mode specifies what kind of | |
10722 | comparison we made. | |
10723 | ||
a0ab749a | 10724 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
10725 | |
10726 | INSN is the insn. */ | |
10727 | ||
10728 | char * | |
a2369ed3 | 10729 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
10730 | { |
10731 | static char string[64]; | |
10732 | enum rtx_code code = GET_CODE (op); | |
10733 | rtx cc_reg = XEXP (op, 0); | |
10734 | enum machine_mode mode = GET_MODE (cc_reg); | |
10735 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 10736 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
10737 | int really_reversed = reversed ^ need_longbranch; |
10738 | char *s = string; | |
10739 | const char *ccode; | |
10740 | const char *pred; | |
10741 | rtx note; | |
10742 | ||
39a10a29 GK |
10743 | validate_condition_mode (code, mode); |
10744 | ||
10745 | /* Work out which way this really branches. We could use | |
10746 | reverse_condition_maybe_unordered here always but this | |
10747 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 10748 | if (really_reversed) |
de40e1df DJ |
10749 | { |
10750 | /* Reversal of FP compares takes care -- an ordered compare | |
10751 | becomes an unordered compare and vice versa. */ | |
10752 | if (mode == CCFPmode) | |
10753 | code = reverse_condition_maybe_unordered (code); | |
10754 | else | |
10755 | code = reverse_condition (code); | |
10756 | } | |
12a4e8c5 | 10757 | |
993f19a8 | 10758 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
10759 | { |
10760 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
10761 | to the GT bit. */ | |
37409796 NS |
10762 | switch (code) |
10763 | { | |
10764 | case EQ: | |
10765 | /* Opposite of GT. */ | |
10766 | code = GT; | |
10767 | break; | |
10768 | ||
10769 | case NE: | |
10770 | code = UNLE; | |
10771 | break; | |
10772 | ||
10773 | default: | |
10774 | gcc_unreachable (); | |
10775 | } | |
a3170dc6 AH |
10776 | } |
10777 | ||
39a10a29 | 10778 | switch (code) |
12a4e8c5 GK |
10779 | { |
10780 | /* Not all of these are actually distinct opcodes, but | |
10781 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
10782 | case NE: case LTGT: |
10783 | ccode = "ne"; break; | |
10784 | case EQ: case UNEQ: | |
10785 | ccode = "eq"; break; | |
f676971a | 10786 | case GE: case GEU: |
50a0b056 | 10787 | ccode = "ge"; break; |
f676971a | 10788 | case GT: case GTU: case UNGT: |
50a0b056 | 10789 | ccode = "gt"; break; |
f676971a | 10790 | case LE: case LEU: |
50a0b056 | 10791 | ccode = "le"; break; |
f676971a | 10792 | case LT: case LTU: case UNLT: |
50a0b056 | 10793 | ccode = "lt"; break; |
12a4e8c5 GK |
10794 | case UNORDERED: ccode = "un"; break; |
10795 | case ORDERED: ccode = "nu"; break; | |
10796 | case UNGE: ccode = "nl"; break; | |
10797 | case UNLE: ccode = "ng"; break; | |
10798 | default: | |
37409796 | 10799 | gcc_unreachable (); |
12a4e8c5 | 10800 | } |
f676971a EC |
10801 | |
10802 | /* Maybe we have a guess as to how likely the branch is. | |
94a54f47 | 10803 | The old mnemonics don't have a way to specify this information. */ |
f4857b9b | 10804 | pred = ""; |
12a4e8c5 GK |
10805 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
10806 | if (note != NULL_RTX) | |
10807 | { | |
10808 | /* PROB is the difference from 50%. */ | |
10809 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
10810 | |
10811 | /* Only hint for highly probable/improbable branches on newer | |
10812 | cpus as static prediction overrides processor dynamic | |
10813 | prediction. For older cpus we may as well always hint, but | |
10814 | assume not taken for branches that are very close to 50% as a | |
10815 | mispredicted taken branch is more expensive than a | |
f676971a | 10816 | mispredicted not-taken branch. */ |
ec507f2d | 10817 | if (rs6000_always_hint |
f4857b9b AM |
10818 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) |
10819 | { | |
10820 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
10821 | && ((prob > 0) ^ need_longbranch)) | |
c4ad648e | 10822 | pred = "+"; |
f4857b9b AM |
10823 | else |
10824 | pred = "-"; | |
10825 | } | |
12a4e8c5 | 10826 | } |
12a4e8c5 GK |
10827 | |
10828 | if (label == NULL) | |
94a54f47 | 10829 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 10830 | else |
94a54f47 | 10831 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 10832 | |
37c67319 | 10833 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 10834 | Assume they'd only be the first character.... */ |
37c67319 GK |
10835 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
10836 | *s++ = '%'; | |
94a54f47 | 10837 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
10838 | |
10839 | if (label != NULL) | |
10840 | { | |
10841 | /* If the branch distance was too far, we may have to use an | |
10842 | unconditional branch to go the distance. */ | |
10843 | if (need_longbranch) | |
44518ddd | 10844 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
10845 | else |
10846 | s += sprintf (s, ",%s", label); | |
10847 | } | |
10848 | ||
10849 | return string; | |
10850 | } | |
50a0b056 | 10851 | |
64022b5d | 10852 | /* Return the string to flip the GT bit on a CR. */ |
423c1189 | 10853 | char * |
64022b5d | 10854 | output_e500_flip_gt_bit (rtx dst, rtx src) |
423c1189 AH |
10855 | { |
10856 | static char string[64]; | |
10857 | int a, b; | |
10858 | ||
37409796 NS |
10859 | gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst)) |
10860 | && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src))); | |
423c1189 | 10861 | |
64022b5d AH |
10862 | /* GT bit. */ |
10863 | a = 4 * (REGNO (dst) - CR0_REGNO) + 1; | |
10864 | b = 4 * (REGNO (src) - CR0_REGNO) + 1; | |
423c1189 AH |
10865 | |
10866 | sprintf (string, "crnot %d,%d", a, b); | |
10867 | return string; | |
10868 | } | |
10869 | ||
21213b4c DP |
10870 | /* Return insn index for the vector compare instruction for given CODE, |
10871 | and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is | |
10872 | not available. */ | |
10873 | ||
10874 | static int | |
94ff898d | 10875 | get_vec_cmp_insn (enum rtx_code code, |
21213b4c DP |
10876 | enum machine_mode dest_mode, |
10877 | enum machine_mode op_mode) | |
10878 | { | |
10879 | if (!TARGET_ALTIVEC) | |
10880 | return INSN_NOT_AVAILABLE; | |
10881 | ||
10882 | switch (code) | |
10883 | { | |
10884 | case EQ: | |
10885 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
10886 | return UNSPEC_VCMPEQUB; | |
10887 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
10888 | return UNSPEC_VCMPEQUH; | |
10889 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
10890 | return UNSPEC_VCMPEQUW; | |
10891 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
10892 | return UNSPEC_VCMPEQFP; | |
10893 | break; | |
10894 | case GE: | |
10895 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
10896 | return UNSPEC_VCMPGEFP; | |
10897 | case GT: | |
10898 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
10899 | return UNSPEC_VCMPGTSB; | |
10900 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
10901 | return UNSPEC_VCMPGTSH; | |
10902 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
10903 | return UNSPEC_VCMPGTSW; | |
10904 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
10905 | return UNSPEC_VCMPGTFP; | |
10906 | break; | |
10907 | case GTU: | |
10908 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
10909 | return UNSPEC_VCMPGTUB; | |
10910 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
10911 | return UNSPEC_VCMPGTUH; | |
10912 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
10913 | return UNSPEC_VCMPGTUW; | |
10914 | break; | |
10915 | default: | |
10916 | break; | |
10917 | } | |
10918 | return INSN_NOT_AVAILABLE; | |
10919 | } | |
10920 | ||
10921 | /* Emit vector compare for operands OP0 and OP1 using code RCODE. | |
10922 | DMODE is expected destination mode. This is a recursive function. */ | |
10923 | ||
10924 | static rtx | |
10925 | rs6000_emit_vector_compare (enum rtx_code rcode, | |
10926 | rtx op0, rtx op1, | |
10927 | enum machine_mode dmode) | |
10928 | { | |
10929 | int vec_cmp_insn; | |
10930 | rtx mask; | |
10931 | enum machine_mode dest_mode; | |
10932 | enum machine_mode op_mode = GET_MODE (op1); | |
10933 | ||
37409796 NS |
10934 | gcc_assert (TARGET_ALTIVEC); |
10935 | gcc_assert (GET_MODE (op0) == GET_MODE (op1)); | |
21213b4c DP |
10936 | |
10937 | /* Floating point vector compare instructions uses destination V4SImode. | |
10938 | Move destination to appropriate mode later. */ | |
10939 | if (dmode == V4SFmode) | |
10940 | dest_mode = V4SImode; | |
10941 | else | |
10942 | dest_mode = dmode; | |
10943 | ||
10944 | mask = gen_reg_rtx (dest_mode); | |
10945 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
10946 | ||
10947 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
10948 | { | |
10949 | bool swap_operands = false; | |
10950 | bool try_again = false; | |
10951 | switch (rcode) | |
10952 | { | |
10953 | case LT: | |
10954 | rcode = GT; | |
10955 | swap_operands = true; | |
10956 | try_again = true; | |
10957 | break; | |
10958 | case LTU: | |
10959 | rcode = GTU; | |
10960 | swap_operands = true; | |
10961 | try_again = true; | |
10962 | break; | |
10963 | case NE: | |
10964 | /* Treat A != B as ~(A==B). */ | |
10965 | { | |
10966 | enum insn_code nor_code; | |
10967 | rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
10968 | dest_mode); | |
94ff898d | 10969 | |
21213b4c | 10970 | nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code; |
37409796 | 10971 | gcc_assert (nor_code != CODE_FOR_nothing); |
21213b4c DP |
10972 | emit_insn (GEN_FCN (nor_code) (mask, eq_rtx)); |
10973 | ||
10974 | if (dmode != dest_mode) | |
10975 | { | |
10976 | rtx temp = gen_reg_rtx (dest_mode); | |
10977 | convert_move (temp, mask, 0); | |
10978 | return temp; | |
10979 | } | |
10980 | return mask; | |
10981 | } | |
10982 | break; | |
10983 | case GE: | |
10984 | case GEU: | |
10985 | case LE: | |
10986 | case LEU: | |
10987 | /* Try GT/GTU/LT/LTU OR EQ */ | |
10988 | { | |
10989 | rtx c_rtx, eq_rtx; | |
10990 | enum insn_code ior_code; | |
10991 | enum rtx_code new_code; | |
10992 | ||
37409796 NS |
10993 | switch (rcode) |
10994 | { | |
10995 | case GE: | |
10996 | new_code = GT; | |
10997 | break; | |
10998 | ||
10999 | case GEU: | |
11000 | new_code = GTU; | |
11001 | break; | |
11002 | ||
11003 | case LE: | |
11004 | new_code = LT; | |
11005 | break; | |
11006 | ||
11007 | case LEU: | |
11008 | new_code = LTU; | |
11009 | break; | |
11010 | ||
11011 | default: | |
11012 | gcc_unreachable (); | |
11013 | } | |
21213b4c DP |
11014 | |
11015 | c_rtx = rs6000_emit_vector_compare (new_code, | |
11016 | op0, op1, dest_mode); | |
11017 | eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
11018 | dest_mode); | |
11019 | ||
11020 | ior_code = ior_optab->handlers[(int)dest_mode].insn_code; | |
37409796 | 11021 | gcc_assert (ior_code != CODE_FOR_nothing); |
21213b4c DP |
11022 | emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx)); |
11023 | if (dmode != dest_mode) | |
11024 | { | |
11025 | rtx temp = gen_reg_rtx (dest_mode); | |
11026 | convert_move (temp, mask, 0); | |
11027 | return temp; | |
11028 | } | |
11029 | return mask; | |
11030 | } | |
11031 | break; | |
11032 | default: | |
37409796 | 11033 | gcc_unreachable (); |
21213b4c DP |
11034 | } |
11035 | ||
11036 | if (try_again) | |
11037 | { | |
11038 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
37409796 NS |
11039 | /* You only get two chances. */ |
11040 | gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE); | |
21213b4c DP |
11041 | } |
11042 | ||
11043 | if (swap_operands) | |
11044 | { | |
11045 | rtx tmp; | |
11046 | tmp = op0; | |
11047 | op0 = op1; | |
11048 | op1 = tmp; | |
11049 | } | |
11050 | } | |
11051 | ||
915167f5 GK |
11052 | emit_insn (gen_rtx_SET (VOIDmode, mask, |
11053 | gen_rtx_UNSPEC (dest_mode, | |
11054 | gen_rtvec (2, op0, op1), | |
11055 | vec_cmp_insn))); | |
21213b4c DP |
11056 | if (dmode != dest_mode) |
11057 | { | |
11058 | rtx temp = gen_reg_rtx (dest_mode); | |
11059 | convert_move (temp, mask, 0); | |
11060 | return temp; | |
11061 | } | |
11062 | return mask; | |
11063 | } | |
11064 | ||
11065 | /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if | |
11066 | valid insn doesn exist for given mode. */ | |
11067 | ||
11068 | static int | |
11069 | get_vsel_insn (enum machine_mode mode) | |
11070 | { | |
11071 | switch (mode) | |
11072 | { | |
11073 | case V4SImode: | |
11074 | return UNSPEC_VSEL4SI; | |
11075 | break; | |
11076 | case V4SFmode: | |
11077 | return UNSPEC_VSEL4SF; | |
11078 | break; | |
11079 | case V8HImode: | |
11080 | return UNSPEC_VSEL8HI; | |
11081 | break; | |
11082 | case V16QImode: | |
11083 | return UNSPEC_VSEL16QI; | |
11084 | break; | |
11085 | default: | |
11086 | return INSN_NOT_AVAILABLE; | |
11087 | break; | |
11088 | } | |
11089 | return INSN_NOT_AVAILABLE; | |
11090 | } | |
11091 | ||
11092 | /* Emit vector select insn where DEST is destination using | |
11093 | operands OP1, OP2 and MASK. */ | |
11094 | ||
11095 | static void | |
11096 | rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask) | |
11097 | { | |
11098 | rtx t, temp; | |
11099 | enum machine_mode dest_mode = GET_MODE (dest); | |
11100 | int vsel_insn_index = get_vsel_insn (GET_MODE (dest)); | |
11101 | ||
11102 | temp = gen_reg_rtx (dest_mode); | |
94ff898d | 11103 | |
19f1ebc7 DP |
11104 | /* For each vector element, select op1 when mask is 1 otherwise |
11105 | select op2. */ | |
915167f5 GK |
11106 | t = gen_rtx_SET (VOIDmode, temp, |
11107 | gen_rtx_UNSPEC (dest_mode, | |
11108 | gen_rtvec (3, op2, op1, mask), | |
11109 | vsel_insn_index)); | |
21213b4c DP |
11110 | emit_insn (t); |
11111 | emit_move_insn (dest, temp); | |
11112 | return; | |
11113 | } | |
11114 | ||
94ff898d | 11115 | /* Emit vector conditional expression. |
21213b4c DP |
11116 | DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands. |
11117 | CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */ | |
11118 | ||
11119 | int | |
11120 | rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2, | |
11121 | rtx cond, rtx cc_op0, rtx cc_op1) | |
11122 | { | |
11123 | enum machine_mode dest_mode = GET_MODE (dest); | |
11124 | enum rtx_code rcode = GET_CODE (cond); | |
11125 | rtx mask; | |
11126 | ||
11127 | if (!TARGET_ALTIVEC) | |
11128 | return 0; | |
11129 | ||
11130 | /* Get the vector mask for the given relational operations. */ | |
11131 | mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode); | |
11132 | ||
11133 | rs6000_emit_vector_select (dest, op1, op2, mask); | |
11134 | ||
11135 | return 1; | |
11136 | } | |
11137 | ||
50a0b056 GK |
11138 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the |
11139 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
11140 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 11141 | |
50a0b056 | 11142 | int |
a2369ed3 | 11143 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
11144 | { |
11145 | enum rtx_code code = GET_CODE (op); | |
11146 | rtx op0 = rs6000_compare_op0; | |
11147 | rtx op1 = rs6000_compare_op1; | |
11148 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
11149 | enum machine_mode compare_mode = GET_MODE (op0); |
11150 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 | 11151 | rtx temp; |
add2402e | 11152 | bool is_against_zero; |
50a0b056 | 11153 | |
a3c9585f | 11154 | /* These modes should always match. */ |
a3170dc6 AH |
11155 | if (GET_MODE (op1) != compare_mode |
11156 | /* In the isel case however, we can use a compare immediate, so | |
11157 | op1 may be a small constant. */ | |
11158 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 11159 | return 0; |
178c3eff | 11160 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 11161 | return 0; |
178c3eff | 11162 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
11163 | return 0; |
11164 | ||
50a0b056 | 11165 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 11166 | if it's too slow.... */ |
50a0b056 | 11167 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
11168 | { |
11169 | if (TARGET_ISEL) | |
11170 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
11171 | return 0; | |
11172 | } | |
fef98bf2 AH |
11173 | else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS |
11174 | && GET_MODE_CLASS (compare_mode) == MODE_FLOAT) | |
11175 | return 0; | |
50a0b056 | 11176 | |
add2402e | 11177 | is_against_zero = op1 == CONST0_RTX (compare_mode); |
94ff898d | 11178 | |
add2402e GK |
11179 | /* A floating-point subtract might overflow, underflow, or produce |
11180 | an inexact result, thus changing the floating-point flags, so it | |
11181 | can't be generated if we care about that. It's safe if one side | |
11182 | of the construct is zero, since then no subtract will be | |
11183 | generated. */ | |
11184 | if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT | |
11185 | && flag_trapping_math && ! is_against_zero) | |
11186 | return 0; | |
11187 | ||
50a0b056 GK |
11188 | /* Eliminate half of the comparisons by switching operands, this |
11189 | makes the remaining code simpler. */ | |
11190 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 11191 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
11192 | { |
11193 | code = reverse_condition_maybe_unordered (code); | |
11194 | temp = true_cond; | |
11195 | true_cond = false_cond; | |
11196 | false_cond = temp; | |
11197 | } | |
11198 | ||
11199 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
11200 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 11201 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 | 11202 | return 0; |
f676971a | 11203 | |
50a0b056 GK |
11204 | if (GET_CODE (op1) == CONST_DOUBLE) |
11205 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
f676971a | 11206 | |
b6d08ca1 | 11207 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
11208 | a subtract, then comparing against zero. Unfortunately, |
11209 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 11210 | know that the operand is finite and the comparison |
50a0b056 | 11211 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 11212 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 11213 | && code != GT && code != UNGE |
045572c7 | 11214 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
11215 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
11216 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
f676971a | 11217 | || (! rtx_equal_p (op0, true_cond) |
50a0b056 GK |
11218 | && ! rtx_equal_p (op1, true_cond)))) |
11219 | return 0; | |
add2402e | 11220 | |
50a0b056 GK |
11221 | /* At this point we know we can use fsel. */ |
11222 | ||
11223 | /* Reduce the comparison to a comparison against zero. */ | |
add2402e GK |
11224 | if (! is_against_zero) |
11225 | { | |
11226 | temp = gen_reg_rtx (compare_mode); | |
11227 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
11228 | gen_rtx_MINUS (compare_mode, op0, op1))); | |
11229 | op0 = temp; | |
11230 | op1 = CONST0_RTX (compare_mode); | |
11231 | } | |
50a0b056 GK |
11232 | |
11233 | /* If we don't care about NaNs we can reduce some of the comparisons | |
11234 | down to faster ones. */ | |
bc9ec0e0 | 11235 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
11236 | switch (code) |
11237 | { | |
11238 | case GT: | |
11239 | code = LE; | |
11240 | temp = true_cond; | |
11241 | true_cond = false_cond; | |
11242 | false_cond = temp; | |
11243 | break; | |
11244 | case UNGE: | |
11245 | code = GE; | |
11246 | break; | |
11247 | case UNEQ: | |
11248 | code = EQ; | |
11249 | break; | |
11250 | default: | |
11251 | break; | |
11252 | } | |
11253 | ||
11254 | /* Now, reduce everything down to a GE. */ | |
11255 | switch (code) | |
11256 | { | |
11257 | case GE: | |
11258 | break; | |
11259 | ||
11260 | case LE: | |
3148ad6d DJ |
11261 | temp = gen_reg_rtx (compare_mode); |
11262 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
11263 | op0 = temp; |
11264 | break; | |
11265 | ||
11266 | case ORDERED: | |
3148ad6d DJ |
11267 | temp = gen_reg_rtx (compare_mode); |
11268 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
11269 | op0 = temp; |
11270 | break; | |
11271 | ||
11272 | case EQ: | |
3148ad6d | 11273 | temp = gen_reg_rtx (compare_mode); |
f676971a | 11274 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
11275 | gen_rtx_NEG (compare_mode, |
11276 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
11277 | op0 = temp; |
11278 | break; | |
11279 | ||
11280 | case UNGE: | |
bc9ec0e0 | 11281 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 11282 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 11283 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 11284 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
11285 | gen_rtx_GE (VOIDmode, |
11286 | op0, op1), | |
11287 | true_cond, false_cond))); | |
bc9ec0e0 GK |
11288 | false_cond = true_cond; |
11289 | true_cond = temp; | |
50a0b056 | 11290 | |
3148ad6d DJ |
11291 | temp = gen_reg_rtx (compare_mode); |
11292 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
11293 | op0 = temp; |
11294 | break; | |
11295 | ||
11296 | case GT: | |
bc9ec0e0 | 11297 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 11298 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 11299 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
f676971a | 11300 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
11301 | gen_rtx_GE (VOIDmode, |
11302 | op0, op1), | |
11303 | true_cond, false_cond))); | |
bc9ec0e0 GK |
11304 | true_cond = false_cond; |
11305 | false_cond = temp; | |
50a0b056 | 11306 | |
3148ad6d DJ |
11307 | temp = gen_reg_rtx (compare_mode); |
11308 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
11309 | op0 = temp; |
11310 | break; | |
11311 | ||
11312 | default: | |
37409796 | 11313 | gcc_unreachable (); |
50a0b056 GK |
11314 | } |
11315 | ||
11316 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 11317 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
11318 | gen_rtx_GE (VOIDmode, |
11319 | op0, op1), | |
11320 | true_cond, false_cond))); | |
11321 | return 1; | |
11322 | } | |
11323 | ||
a3170dc6 AH |
11324 | /* Same as above, but for ints (isel). */ |
11325 | ||
11326 | static int | |
a2369ed3 | 11327 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
11328 | { |
11329 | rtx condition_rtx, cr; | |
11330 | ||
11331 | /* All isel implementations thus far are 32-bits. */ | |
11332 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
11333 | return 0; | |
11334 | ||
11335 | /* We still have to do the compare, because isel doesn't do a | |
11336 | compare, it just looks at the CRx bits set by a previous compare | |
11337 | instruction. */ | |
11338 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
11339 | cr = XEXP (condition_rtx, 0); | |
11340 | ||
11341 | if (GET_MODE (cr) == CCmode) | |
11342 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
11343 | true_cond, false_cond, cr)); | |
11344 | else | |
11345 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
11346 | true_cond, false_cond, cr)); | |
11347 | ||
11348 | return 1; | |
11349 | } | |
11350 | ||
11351 | const char * | |
a2369ed3 | 11352 | output_isel (rtx *operands) |
a3170dc6 AH |
11353 | { |
11354 | enum rtx_code code; | |
11355 | ||
11356 | code = GET_CODE (operands[1]); | |
11357 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
11358 | { | |
11359 | PUT_CODE (operands[1], reverse_condition (code)); | |
11360 | return "isel %0,%3,%2,%j1"; | |
11361 | } | |
11362 | else | |
11363 | return "isel %0,%2,%3,%j1"; | |
11364 | } | |
11365 | ||
50a0b056 | 11366 | void |
a2369ed3 | 11367 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
11368 | { |
11369 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 11370 | enum rtx_code c; |
50a0b056 | 11371 | rtx target; |
5dc8d536 AH |
11372 | |
11373 | if (code == SMAX || code == SMIN) | |
11374 | c = GE; | |
11375 | else | |
11376 | c = GEU; | |
11377 | ||
50a0b056 | 11378 | if (code == SMAX || code == UMAX) |
f676971a | 11379 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
11380 | op0, op1, mode, 0); |
11381 | else | |
f676971a | 11382 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 | 11383 | op1, op0, mode, 0); |
37409796 | 11384 | gcc_assert (target); |
50a0b056 GK |
11385 | if (target != dest) |
11386 | emit_move_insn (dest, target); | |
11387 | } | |
46c07df8 | 11388 | |
915167f5 GK |
11389 | /* Emit instructions to perform a load-reserved/store-conditional operation. |
11390 | The operation performed is an atomic | |
11391 | (set M (CODE:MODE M OP)) | |
11392 | If not NULL, BEFORE is atomically set to M before the operation, and | |
11393 | AFTER is set to M after the operation (that is, (CODE:MODE M OP)). | |
11394 | If SYNC_P then a memory barrier is emitted before the operation. | |
11395 | Either OP or M may be wrapped in a NOT operation. */ | |
11396 | ||
11397 | void | |
11398 | rs6000_emit_sync (enum rtx_code code, enum machine_mode mode, | |
11399 | rtx m, rtx op, rtx before_param, rtx after_param, | |
11400 | bool sync_p) | |
11401 | { | |
11402 | enum machine_mode used_mode; | |
11403 | rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after; | |
11404 | rtx used_m; | |
11405 | rtvec vec; | |
11406 | HOST_WIDE_INT imask = GET_MODE_MASK (mode); | |
11407 | rtx shift = NULL_RTX; | |
11408 | ||
11409 | if (sync_p) | |
11410 | emit_insn (gen_memory_barrier ()); | |
11411 | ||
11412 | if (GET_CODE (m) == NOT) | |
11413 | used_m = XEXP (m, 0); | |
11414 | else | |
11415 | used_m = m; | |
11416 | ||
11417 | /* If this is smaller than SImode, we'll have to use SImode with | |
11418 | adjustments. */ | |
11419 | if (mode == QImode || mode == HImode) | |
11420 | { | |
11421 | rtx newop, oldop; | |
11422 | ||
11423 | if (MEM_ALIGN (used_m) >= 32) | |
11424 | { | |
11425 | int ishift = 0; | |
11426 | if (BYTES_BIG_ENDIAN) | |
11427 | ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode); | |
11428 | ||
11429 | shift = GEN_INT (ishift); | |
11430 | } | |
11431 | else | |
11432 | { | |
11433 | rtx addrSI, aligned_addr; | |
a9c9d3fa | 11434 | int shift_mask = mode == QImode ? 0x18 : 0x10; |
915167f5 GK |
11435 | |
11436 | addrSI = force_reg (SImode, gen_lowpart_common (SImode, | |
11437 | XEXP (used_m, 0))); | |
11438 | shift = gen_reg_rtx (SImode); | |
11439 | ||
11440 | emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3), | |
a9c9d3fa GK |
11441 | GEN_INT (shift_mask))); |
11442 | emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask))); | |
915167f5 GK |
11443 | |
11444 | aligned_addr = expand_binop (Pmode, and_optab, | |
11445 | XEXP (used_m, 0), | |
11446 | GEN_INT (-4), NULL_RTX, | |
11447 | 1, OPTAB_LIB_WIDEN); | |
11448 | used_m = change_address (used_m, SImode, aligned_addr); | |
11449 | set_mem_align (used_m, 32); | |
11450 | /* It's safe to keep the old alias set of USED_M, because | |
11451 | the operation is atomic and only affects the original | |
11452 | USED_M. */ | |
11453 | if (GET_CODE (m) == NOT) | |
11454 | m = gen_rtx_NOT (SImode, used_m); | |
11455 | else | |
11456 | m = used_m; | |
11457 | } | |
11458 | ||
11459 | if (GET_CODE (op) == NOT) | |
11460 | { | |
11461 | oldop = lowpart_subreg (SImode, XEXP (op, 0), mode); | |
11462 | oldop = gen_rtx_NOT (SImode, oldop); | |
11463 | } | |
11464 | else | |
11465 | oldop = lowpart_subreg (SImode, op, mode); | |
11466 | switch (code) | |
11467 | { | |
11468 | case IOR: | |
11469 | case XOR: | |
11470 | newop = expand_binop (SImode, and_optab, | |
11471 | oldop, GEN_INT (imask), NULL_RTX, | |
11472 | 1, OPTAB_LIB_WIDEN); | |
11473 | emit_insn (gen_ashlsi3 (newop, newop, shift)); | |
11474 | break; | |
11475 | ||
11476 | case AND: | |
11477 | newop = expand_binop (SImode, ior_optab, | |
11478 | oldop, GEN_INT (~imask), NULL_RTX, | |
11479 | 1, OPTAB_LIB_WIDEN); | |
a9c9d3fa | 11480 | emit_insn (gen_rotlsi3 (newop, newop, shift)); |
915167f5 GK |
11481 | break; |
11482 | ||
11483 | case PLUS: | |
11484 | { | |
11485 | rtx mask; | |
11486 | ||
11487 | newop = expand_binop (SImode, and_optab, | |
11488 | oldop, GEN_INT (imask), NULL_RTX, | |
11489 | 1, OPTAB_LIB_WIDEN); | |
11490 | emit_insn (gen_ashlsi3 (newop, newop, shift)); | |
11491 | ||
11492 | mask = gen_reg_rtx (SImode); | |
11493 | emit_move_insn (mask, GEN_INT (imask)); | |
11494 | emit_insn (gen_ashlsi3 (mask, mask, shift)); | |
11495 | ||
11496 | newop = gen_rtx_AND (SImode, gen_rtx_PLUS (SImode, m, newop), | |
11497 | mask); | |
11498 | newop = gen_rtx_IOR (SImode, newop, | |
11499 | gen_rtx_AND (SImode, | |
11500 | gen_rtx_NOT (SImode, mask), | |
11501 | m)); | |
11502 | break; | |
11503 | } | |
11504 | ||
11505 | default: | |
11506 | gcc_unreachable (); | |
11507 | } | |
11508 | ||
a9c9d3fa GK |
11509 | if (GET_CODE (m) == NOT) |
11510 | { | |
11511 | rtx mask, xorm; | |
11512 | ||
11513 | mask = gen_reg_rtx (SImode); | |
11514 | emit_move_insn (mask, GEN_INT (imask)); | |
11515 | emit_insn (gen_ashlsi3 (mask, mask, shift)); | |
11516 | ||
11517 | xorm = gen_rtx_XOR (SImode, used_m, mask); | |
11518 | /* Depending on the value of 'op', the XOR or the operation might | |
11519 | be able to be simplified away. */ | |
11520 | newop = simplify_gen_binary (code, SImode, xorm, newop); | |
11521 | } | |
915167f5 GK |
11522 | op = newop; |
11523 | used_mode = SImode; | |
11524 | before = gen_reg_rtx (used_mode); | |
11525 | after = gen_reg_rtx (used_mode); | |
11526 | } | |
11527 | else | |
11528 | { | |
11529 | used_mode = mode; | |
11530 | before = before_param; | |
11531 | after = after_param; | |
11532 | ||
11533 | if (before == NULL_RTX) | |
11534 | before = gen_reg_rtx (used_mode); | |
11535 | if (after == NULL_RTX) | |
11536 | after = gen_reg_rtx (used_mode); | |
11537 | } | |
11538 | ||
a9c9d3fa | 11539 | if ((code == PLUS || GET_CODE (m) == NOT) && used_mode != mode) |
915167f5 GK |
11540 | the_op = op; /* Computed above. */ |
11541 | else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT) | |
11542 | the_op = gen_rtx_fmt_ee (code, used_mode, op, m); | |
11543 | else | |
11544 | the_op = gen_rtx_fmt_ee (code, used_mode, m, op); | |
11545 | ||
11546 | set_after = gen_rtx_SET (VOIDmode, after, the_op); | |
11547 | set_before = gen_rtx_SET (VOIDmode, before, used_m); | |
11548 | set_atomic = gen_rtx_SET (VOIDmode, used_m, | |
11549 | gen_rtx_UNSPEC (used_mode, gen_rtvec (1, the_op), | |
11550 | UNSPEC_SYNC_OP)); | |
11551 | cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode)); | |
11552 | ||
11553 | if (code == PLUS && used_mode != mode) | |
11554 | vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch, | |
11555 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); | |
11556 | else | |
11557 | vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch); | |
11558 | emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); | |
11559 | ||
11560 | /* Shift and mask the return values properly. */ | |
11561 | if (used_mode != mode && before_param) | |
11562 | { | |
11563 | emit_insn (gen_lshrsi3 (before, before, shift)); | |
11564 | convert_move (before_param, before, 1); | |
11565 | } | |
11566 | ||
11567 | if (used_mode != mode && after_param) | |
11568 | { | |
11569 | emit_insn (gen_lshrsi3 (after, after, shift)); | |
11570 | convert_move (after_param, after, 1); | |
11571 | } | |
11572 | ||
11573 | /* The previous sequence will end with a branch that's dependent on | |
11574 | the conditional store, so placing an isync will ensure that no | |
11575 | other instructions (especially, no load or store instructions) | |
11576 | can start before the atomic operation completes. */ | |
11577 | if (sync_p) | |
11578 | emit_insn (gen_isync ()); | |
11579 | } | |
11580 | ||
a9baceb1 GK |
11581 | /* Emit instructions to move SRC to DST. Called by splitters for |
11582 | multi-register moves. It will emit at most one instruction for | |
11583 | each register that is accessed; that is, it won't emit li/lis pairs | |
11584 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
11585 | register. */ | |
46c07df8 | 11586 | |
46c07df8 | 11587 | void |
a9baceb1 | 11588 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 11589 | { |
a9baceb1 GK |
11590 | /* The register number of the first register being moved. */ |
11591 | int reg; | |
11592 | /* The mode that is to be moved. */ | |
11593 | enum machine_mode mode; | |
11594 | /* The mode that the move is being done in, and its size. */ | |
11595 | enum machine_mode reg_mode; | |
11596 | int reg_mode_size; | |
11597 | /* The number of registers that will be moved. */ | |
11598 | int nregs; | |
11599 | ||
11600 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
11601 | mode = GET_MODE (dst); | |
c8b622ff | 11602 | nregs = hard_regno_nregs[reg][mode]; |
a9baceb1 GK |
11603 | if (FP_REGNO_P (reg)) |
11604 | reg_mode = DFmode; | |
11605 | else if (ALTIVEC_REGNO_P (reg)) | |
11606 | reg_mode = V16QImode; | |
11607 | else | |
11608 | reg_mode = word_mode; | |
11609 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
f676971a | 11610 | |
37409796 | 11611 | gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode)); |
f676971a | 11612 | |
a9baceb1 GK |
11613 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) |
11614 | { | |
11615 | /* Move register range backwards, if we might have destructive | |
11616 | overlap. */ | |
11617 | int i; | |
11618 | for (i = nregs - 1; i >= 0; i--) | |
f676971a | 11619 | emit_insn (gen_rtx_SET (VOIDmode, |
a9baceb1 GK |
11620 | simplify_gen_subreg (reg_mode, dst, mode, |
11621 | i * reg_mode_size), | |
11622 | simplify_gen_subreg (reg_mode, src, mode, | |
11623 | i * reg_mode_size))); | |
11624 | } | |
46c07df8 HP |
11625 | else |
11626 | { | |
a9baceb1 GK |
11627 | int i; |
11628 | int j = -1; | |
11629 | bool used_update = false; | |
46c07df8 | 11630 | |
c1e55850 | 11631 | if (MEM_P (src) && INT_REGNO_P (reg)) |
c4ad648e AM |
11632 | { |
11633 | rtx breg; | |
3a1f863f | 11634 | |
a9baceb1 GK |
11635 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
11636 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
11637 | { |
11638 | rtx delta_rtx; | |
a9baceb1 | 11639 | breg = XEXP (XEXP (src, 0), 0); |
c4ad648e AM |
11640 | delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC |
11641 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
11642 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)))); | |
a9baceb1 GK |
11643 | emit_insn (TARGET_32BIT |
11644 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11645 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11646 | src = gen_rtx_MEM (mode, breg); |
11647 | } | |
c1e55850 GK |
11648 | else if (! offsettable_memref_p (src)) |
11649 | { | |
11650 | rtx newsrc, basereg; | |
11651 | basereg = gen_rtx_REG (Pmode, reg); | |
11652 | emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0))); | |
11653 | newsrc = gen_rtx_MEM (GET_MODE (src), basereg); | |
11654 | MEM_COPY_ATTRIBUTES (newsrc, src); | |
11655 | src = newsrc; | |
11656 | } | |
3a1f863f | 11657 | |
0423421f AM |
11658 | breg = XEXP (src, 0); |
11659 | if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM) | |
11660 | breg = XEXP (breg, 0); | |
11661 | ||
11662 | /* If the base register we are using to address memory is | |
11663 | also a destination reg, then change that register last. */ | |
11664 | if (REG_P (breg) | |
11665 | && REGNO (breg) >= REGNO (dst) | |
3a1f863f DE |
11666 | && REGNO (breg) < REGNO (dst) + nregs) |
11667 | j = REGNO (breg) - REGNO (dst); | |
c4ad648e | 11668 | } |
46c07df8 | 11669 | |
a9baceb1 | 11670 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
11671 | { |
11672 | rtx breg; | |
11673 | ||
a9baceb1 GK |
11674 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11675 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
11676 | { |
11677 | rtx delta_rtx; | |
a9baceb1 | 11678 | breg = XEXP (XEXP (dst, 0), 0); |
c4ad648e AM |
11679 | delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11680 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
11681 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)))); | |
3a1f863f DE |
11682 | |
11683 | /* We have to update the breg before doing the store. | |
11684 | Use store with update, if available. */ | |
11685 | ||
11686 | if (TARGET_UPDATE) | |
11687 | { | |
a9baceb1 | 11688 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
c4ad648e AM |
11689 | emit_insn (TARGET_32BIT |
11690 | ? (TARGET_POWERPC64 | |
11691 | ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc) | |
11692 | : gen_movsi_update (breg, breg, delta_rtx, nsrc)) | |
11693 | : gen_movdi_di_update (breg, breg, delta_rtx, nsrc)); | |
a9baceb1 | 11694 | used_update = true; |
3a1f863f DE |
11695 | } |
11696 | else | |
a9baceb1 GK |
11697 | emit_insn (TARGET_32BIT |
11698 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11699 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11700 | dst = gen_rtx_MEM (mode, breg); |
11701 | } | |
37409796 NS |
11702 | else |
11703 | gcc_assert (offsettable_memref_p (dst)); | |
3a1f863f DE |
11704 | } |
11705 | ||
46c07df8 | 11706 | for (i = 0; i < nregs; i++) |
f676971a | 11707 | { |
3a1f863f DE |
11708 | /* Calculate index to next subword. */ |
11709 | ++j; | |
f676971a | 11710 | if (j == nregs) |
3a1f863f | 11711 | j = 0; |
46c07df8 | 11712 | |
112cdef5 | 11713 | /* If compiler already emitted move of first word by |
a9baceb1 | 11714 | store with update, no need to do anything. */ |
3a1f863f | 11715 | if (j == 0 && used_update) |
a9baceb1 | 11716 | continue; |
f676971a | 11717 | |
a9baceb1 GK |
11718 | emit_insn (gen_rtx_SET (VOIDmode, |
11719 | simplify_gen_subreg (reg_mode, dst, mode, | |
11720 | j * reg_mode_size), | |
11721 | simplify_gen_subreg (reg_mode, src, mode, | |
11722 | j * reg_mode_size))); | |
3a1f863f | 11723 | } |
46c07df8 HP |
11724 | } |
11725 | } | |
11726 | ||
12a4e8c5 | 11727 | \f |
a4f6c312 SS |
11728 | /* This page contains routines that are used to determine what the |
11729 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 11730 | |
a4f6c312 SS |
11731 | /* Return the first fixed-point register that is required to be |
11732 | saved. 32 if none. */ | |
9878760c RK |
11733 | |
11734 | int | |
863d938c | 11735 | first_reg_to_save (void) |
9878760c RK |
11736 | { |
11737 | int first_reg; | |
11738 | ||
11739 | /* Find lowest numbered live register. */ | |
11740 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
f676971a | 11741 | if (regs_ever_live[first_reg] |
a38d360d | 11742 | && (! call_used_regs[first_reg] |
1db02437 | 11743 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11744 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
b4db40bf JJ |
11745 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) |
11746 | || (TARGET_TOC && TARGET_MINIMAL_TOC))))) | |
9878760c RK |
11747 | break; |
11748 | ||
ee890fe2 | 11749 | #if TARGET_MACHO |
93638d7a AM |
11750 | if (flag_pic |
11751 | && current_function_uses_pic_offset_table | |
11752 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 11753 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
11754 | #endif |
11755 | ||
9878760c RK |
11756 | return first_reg; |
11757 | } | |
11758 | ||
11759 | /* Similar, for FP regs. */ | |
11760 | ||
11761 | int | |
863d938c | 11762 | first_fp_reg_to_save (void) |
9878760c RK |
11763 | { |
11764 | int first_reg; | |
11765 | ||
11766 | /* Find lowest numbered live register. */ | |
11767 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
11768 | if (regs_ever_live[first_reg]) | |
11769 | break; | |
11770 | ||
11771 | return first_reg; | |
11772 | } | |
00b960c7 AH |
11773 | |
11774 | /* Similar, for AltiVec regs. */ | |
11775 | ||
11776 | static int | |
863d938c | 11777 | first_altivec_reg_to_save (void) |
00b960c7 AH |
11778 | { |
11779 | int i; | |
11780 | ||
11781 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
11782 | if (! TARGET_ALTIVEC_ABI) | |
11783 | return LAST_ALTIVEC_REGNO + 1; | |
11784 | ||
11785 | /* Find lowest numbered live register. */ | |
11786 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
11787 | if (regs_ever_live[i]) | |
11788 | break; | |
11789 | ||
11790 | return i; | |
11791 | } | |
11792 | ||
11793 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
11794 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
11795 | the 32-bit word is 0. */ | |
11796 | ||
11797 | static unsigned int | |
863d938c | 11798 | compute_vrsave_mask (void) |
00b960c7 AH |
11799 | { |
11800 | unsigned int i, mask = 0; | |
11801 | ||
11802 | /* First, find out if we use _any_ altivec registers. */ | |
11803 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
11804 | if (regs_ever_live[i]) | |
11805 | mask |= ALTIVEC_REG_BIT (i); | |
11806 | ||
11807 | if (mask == 0) | |
11808 | return mask; | |
11809 | ||
00b960c7 AH |
11810 | /* Next, remove the argument registers from the set. These must |
11811 | be in the VRSAVE mask set by the caller, so we don't need to add | |
11812 | them in again. More importantly, the mask we compute here is | |
11813 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
11814 | wish the argument registers to die. */ | |
a6cf80f2 | 11815 | for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
11816 | mask &= ~ALTIVEC_REG_BIT (i); |
11817 | ||
11818 | /* Similarly, remove the return value from the set. */ | |
11819 | { | |
11820 | bool yes = false; | |
11821 | diddle_return_value (is_altivec_return_reg, &yes); | |
11822 | if (yes) | |
11823 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
11824 | } | |
11825 | ||
11826 | return mask; | |
11827 | } | |
11828 | ||
d62294f5 | 11829 | /* For a very restricted set of circumstances, we can cut down the |
f57fe068 AM |
11830 | size of prologues/epilogues by calling our own save/restore-the-world |
11831 | routines. */ | |
d62294f5 FJ |
11832 | |
11833 | static void | |
f57fe068 AM |
11834 | compute_save_world_info (rs6000_stack_t *info_ptr) |
11835 | { | |
11836 | info_ptr->world_save_p = 1; | |
11837 | info_ptr->world_save_p | |
11838 | = (WORLD_SAVE_P (info_ptr) | |
11839 | && DEFAULT_ABI == ABI_DARWIN | |
11840 | && ! (current_function_calls_setjmp && flag_exceptions) | |
11841 | && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO | |
11842 | && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO | |
11843 | && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO | |
11844 | && info_ptr->cr_save_p); | |
f676971a | 11845 | |
d62294f5 FJ |
11846 | /* This will not work in conjunction with sibcalls. Make sure there |
11847 | are none. (This check is expensive, but seldom executed.) */ | |
f57fe068 | 11848 | if (WORLD_SAVE_P (info_ptr)) |
f676971a | 11849 | { |
d62294f5 FJ |
11850 | rtx insn; |
11851 | for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) | |
c4ad648e AM |
11852 | if ( GET_CODE (insn) == CALL_INSN |
11853 | && SIBLING_CALL_P (insn)) | |
11854 | { | |
11855 | info_ptr->world_save_p = 0; | |
11856 | break; | |
11857 | } | |
d62294f5 | 11858 | } |
f676971a | 11859 | |
f57fe068 | 11860 | if (WORLD_SAVE_P (info_ptr)) |
d62294f5 FJ |
11861 | { |
11862 | /* Even if we're not touching VRsave, make sure there's room on the | |
11863 | stack for it, if it looks like we're calling SAVE_WORLD, which | |
c4ad648e | 11864 | will attempt to save it. */ |
d62294f5 FJ |
11865 | info_ptr->vrsave_size = 4; |
11866 | ||
11867 | /* "Save" the VRsave register too if we're saving the world. */ | |
11868 | if (info_ptr->vrsave_mask == 0) | |
c4ad648e | 11869 | info_ptr->vrsave_mask = compute_vrsave_mask (); |
d62294f5 FJ |
11870 | |
11871 | /* Because the Darwin register save/restore routines only handle | |
c4ad648e | 11872 | F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency |
992d08b1 | 11873 | check. */ |
37409796 NS |
11874 | gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO |
11875 | && (info_ptr->first_altivec_reg_save | |
11876 | >= FIRST_SAVED_ALTIVEC_REGNO)); | |
d62294f5 | 11877 | } |
f676971a | 11878 | return; |
d62294f5 FJ |
11879 | } |
11880 | ||
11881 | ||
00b960c7 | 11882 | static void |
a2369ed3 | 11883 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
11884 | { |
11885 | bool *yes = (bool *) xyes; | |
11886 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
11887 | *yes = true; | |
11888 | } | |
11889 | ||
4697a36c MM |
11890 | \f |
11891 | /* Calculate the stack information for the current function. This is | |
11892 | complicated by having two separate calling sequences, the AIX calling | |
11893 | sequence and the V.4 calling sequence. | |
11894 | ||
592696dd | 11895 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 11896 | 32-bit 64-bit |
4697a36c | 11897 | SP----> +---------------------------------------+ |
a260abc9 | 11898 | | back chain to caller | 0 0 |
4697a36c | 11899 | +---------------------------------------+ |
a260abc9 | 11900 | | saved CR | 4 8 (8-11) |
4697a36c | 11901 | +---------------------------------------+ |
a260abc9 | 11902 | | saved LR | 8 16 |
4697a36c | 11903 | +---------------------------------------+ |
a260abc9 | 11904 | | reserved for compilers | 12 24 |
4697a36c | 11905 | +---------------------------------------+ |
a260abc9 | 11906 | | reserved for binders | 16 32 |
4697a36c | 11907 | +---------------------------------------+ |
a260abc9 | 11908 | | saved TOC pointer | 20 40 |
4697a36c | 11909 | +---------------------------------------+ |
a260abc9 | 11910 | | Parameter save area (P) | 24 48 |
4697a36c | 11911 | +---------------------------------------+ |
a260abc9 | 11912 | | Alloca space (A) | 24+P etc. |
802a0058 | 11913 | +---------------------------------------+ |
a7df97e6 | 11914 | | Local variable space (L) | 24+P+A |
4697a36c | 11915 | +---------------------------------------+ |
a7df97e6 | 11916 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 11917 | +---------------------------------------+ |
00b960c7 AH |
11918 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
11919 | +---------------------------------------+ | |
11920 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
11921 | +---------------------------------------+ | |
11922 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 11923 | +---------------------------------------+ |
00b960c7 AH |
11924 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
11925 | +---------------------------------------+ | |
11926 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
11927 | +---------------------------------------+ |
11928 | old SP->| back chain to caller's caller | | |
11929 | +---------------------------------------+ | |
11930 | ||
5376a30c KR |
11931 | The required alignment for AIX configurations is two words (i.e., 8 |
11932 | or 16 bytes). | |
11933 | ||
11934 | ||
4697a36c MM |
11935 | V.4 stack frames look like: |
11936 | ||
11937 | SP----> +---------------------------------------+ | |
11938 | | back chain to caller | 0 | |
11939 | +---------------------------------------+ | |
5eb387b8 | 11940 | | caller's saved LR | 4 |
4697a36c MM |
11941 | +---------------------------------------+ |
11942 | | Parameter save area (P) | 8 | |
11943 | +---------------------------------------+ | |
a7df97e6 | 11944 | | Alloca space (A) | 8+P |
f676971a | 11945 | +---------------------------------------+ |
a7df97e6 | 11946 | | Varargs save area (V) | 8+P+A |
f676971a | 11947 | +---------------------------------------+ |
a7df97e6 | 11948 | | Local variable space (L) | 8+P+A+V |
f676971a | 11949 | +---------------------------------------+ |
a7df97e6 | 11950 | | Float/int conversion temporary (X) | 8+P+A+V+L |
4697a36c | 11951 | +---------------------------------------+ |
00b960c7 AH |
11952 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
11953 | +---------------------------------------+ | |
11954 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
11955 | +---------------------------------------+ | |
11956 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
11957 | +---------------------------------------+ | |
c4ad648e AM |
11958 | | SPE: area for 64-bit GP registers | |
11959 | +---------------------------------------+ | |
11960 | | SPE alignment padding | | |
11961 | +---------------------------------------+ | |
00b960c7 | 11962 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
f676971a | 11963 | +---------------------------------------+ |
00b960c7 | 11964 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
f676971a | 11965 | +---------------------------------------+ |
00b960c7 | 11966 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
11967 | +---------------------------------------+ |
11968 | old SP->| back chain to caller's caller | | |
11969 | +---------------------------------------+ | |
b6c9286a | 11970 | |
5376a30c KR |
11971 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
11972 | given. (But note below and in sysv4.h that we require only 8 and | |
11973 | may round up the size of our stack frame anyways. The historical | |
11974 | reason is early versions of powerpc-linux which didn't properly | |
11975 | align the stack at program startup. A happy side-effect is that | |
11976 | -mno-eabi libraries can be used with -meabi programs.) | |
11977 | ||
50d440bc | 11978 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
11979 | the stack alignment requirements may differ. If -mno-eabi is not |
11980 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
11981 | given, the required alignment is 16 bytes. (But see V.4 comment | |
11982 | above.) */ | |
4697a36c | 11983 | |
61b2fbe7 MM |
11984 | #ifndef ABI_STACK_BOUNDARY |
11985 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
11986 | #endif | |
11987 | ||
d1d0c603 | 11988 | static rs6000_stack_t * |
863d938c | 11989 | rs6000_stack_info (void) |
4697a36c MM |
11990 | { |
11991 | static rs6000_stack_t info, zero_info; | |
11992 | rs6000_stack_t *info_ptr = &info; | |
327e5343 | 11993 | int reg_size = TARGET_32BIT ? 4 : 8; |
83720594 | 11994 | int ehrd_size; |
64045029 | 11995 | int save_align; |
44688022 | 11996 | HOST_WIDE_INT non_fixed_size; |
4697a36c | 11997 | |
a4f6c312 | 11998 | /* Zero all fields portably. */ |
4697a36c MM |
11999 | info = zero_info; |
12000 | ||
c19de7aa AH |
12001 | if (TARGET_SPE) |
12002 | { | |
12003 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f | 12004 | if (cfun->machine->insn_chain_scanned_p == 0) |
b5a5beb9 AH |
12005 | cfun->machine->insn_chain_scanned_p |
12006 | = spe_func_has_64bit_regs_p () + 1; | |
12007 | info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1; | |
c19de7aa AH |
12008 | } |
12009 | ||
a4f6c312 | 12010 | /* Select which calling sequence. */ |
178274da | 12011 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 12012 | |
a4f6c312 | 12013 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 12014 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
f676971a | 12015 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 12016 | even if it currently looks like we won't. */ |
2bfcf297 | 12017 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
12018 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
12019 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
12020 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
12021 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
12022 | else |
12023 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 12024 | |
a3170dc6 AH |
12025 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
12026 | Ideally we should save the entire 64-bits only when the upper | |
12027 | half is used in SIMD instructions. Since we only record | |
12028 | registers live (not the size they are used in), this proves | |
12029 | difficult because we'd have to traverse the instruction chain at | |
12030 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
12031 | so we opt to save the GPRs in 64-bits always if but one register |
12032 | gets used in 64-bits. Otherwise, all the registers in the frame | |
12033 | get saved in 32-bits. | |
a3170dc6 | 12034 | |
c19de7aa | 12035 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 12036 | traditional GP save area will be empty. */ |
c19de7aa | 12037 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12038 | info_ptr->gp_size = 0; |
12039 | ||
4697a36c MM |
12040 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
12041 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
12042 | ||
00b960c7 AH |
12043 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
12044 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
12045 | - info_ptr->first_altivec_reg_save); | |
12046 | ||
592696dd | 12047 | /* Does this function call anything? */ |
71f123ca FS |
12048 | info_ptr->calls_p = (! current_function_is_leaf |
12049 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 12050 | |
a4f6c312 | 12051 | /* Determine if we need to save the link register. */ |
71f123ca | 12052 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
12053 | || (DEFAULT_ABI == ABI_AIX |
12054 | && current_function_profile | |
12055 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
12056 | #ifdef TARGET_RELOCATABLE |
12057 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
12058 | #endif | |
12059 | || (info_ptr->first_fp_reg_save != 64 | |
12060 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 12061 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 12062 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
4697a36c MM |
12063 | || info_ptr->calls_p) |
12064 | { | |
12065 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 12066 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
12067 | } |
12068 | ||
9ebbca7d | 12069 | /* Determine if we need to save the condition code registers. */ |
f676971a | 12070 | if (regs_ever_live[CR2_REGNO] |
9ebbca7d GK |
12071 | || regs_ever_live[CR3_REGNO] |
12072 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
12073 | { |
12074 | info_ptr->cr_save_p = 1; | |
178274da | 12075 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
12076 | info_ptr->cr_size = reg_size; |
12077 | } | |
12078 | ||
83720594 RH |
12079 | /* If the current function calls __builtin_eh_return, then we need |
12080 | to allocate stack space for registers that will hold data for | |
12081 | the exception handler. */ | |
12082 | if (current_function_calls_eh_return) | |
12083 | { | |
12084 | unsigned int i; | |
12085 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
12086 | continue; | |
a3170dc6 AH |
12087 | |
12088 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
12089 | ehrd_size = i * (TARGET_SPE_ABI |
12090 | && info_ptr->spe_64bit_regs_used != 0 | |
12091 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
12092 | } |
12093 | else | |
12094 | ehrd_size = 0; | |
12095 | ||
592696dd | 12096 | /* Determine various sizes. */ |
4697a36c MM |
12097 | info_ptr->reg_size = reg_size; |
12098 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
12099 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 12100 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 | 12101 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
03e007d7 | 12102 | TARGET_ALTIVEC ? 16 : 8); |
00b960c7 | 12103 | |
c19de7aa | 12104 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12105 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
12106 | else | |
12107 | info_ptr->spe_gp_size = 0; | |
12108 | ||
4d774ff8 HP |
12109 | if (TARGET_ALTIVEC_ABI) |
12110 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 12111 | else |
4d774ff8 HP |
12112 | info_ptr->vrsave_mask = 0; |
12113 | ||
12114 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
12115 | info_ptr->vrsave_size = 4; | |
12116 | else | |
12117 | info_ptr->vrsave_size = 0; | |
b6c9286a | 12118 | |
d62294f5 FJ |
12119 | compute_save_world_info (info_ptr); |
12120 | ||
592696dd | 12121 | /* Calculate the offsets. */ |
178274da | 12122 | switch (DEFAULT_ABI) |
4697a36c | 12123 | { |
b6c9286a | 12124 | case ABI_NONE: |
24d304eb | 12125 | default: |
37409796 | 12126 | gcc_unreachable (); |
b6c9286a MM |
12127 | |
12128 | case ABI_AIX: | |
ee890fe2 | 12129 | case ABI_DARWIN: |
b6c9286a MM |
12130 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
12131 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
12132 | |
12133 | if (TARGET_ALTIVEC_ABI) | |
12134 | { | |
12135 | info_ptr->vrsave_save_offset | |
12136 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
12137 | ||
12138 | /* Align stack so vector save area is on a quadword boundary. */ | |
12139 | if (info_ptr->altivec_size != 0) | |
12140 | info_ptr->altivec_padding_size | |
12141 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
12142 | else | |
12143 | info_ptr->altivec_padding_size = 0; | |
12144 | ||
12145 | info_ptr->altivec_save_offset | |
12146 | = info_ptr->vrsave_save_offset | |
12147 | - info_ptr->altivec_padding_size | |
12148 | - info_ptr->altivec_size; | |
12149 | ||
12150 | /* Adjust for AltiVec case. */ | |
12151 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
12152 | } | |
12153 | else | |
12154 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
12155 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
12156 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
12157 | break; |
12158 | ||
12159 | case ABI_V4: | |
b6c9286a MM |
12160 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
12161 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 12162 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 12163 | |
c19de7aa | 12164 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
c4ad648e AM |
12165 | { |
12166 | /* Align stack so SPE GPR save area is aligned on a | |
12167 | double-word boundary. */ | |
12168 | if (info_ptr->spe_gp_size != 0) | |
12169 | info_ptr->spe_padding_size | |
12170 | = 8 - (-info_ptr->cr_save_offset % 8); | |
12171 | else | |
12172 | info_ptr->spe_padding_size = 0; | |
12173 | ||
12174 | info_ptr->spe_gp_save_offset | |
12175 | = info_ptr->cr_save_offset | |
12176 | - info_ptr->spe_padding_size | |
12177 | - info_ptr->spe_gp_size; | |
12178 | ||
12179 | /* Adjust for SPE case. */ | |
12180 | info_ptr->toc_save_offset | |
12181 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
12182 | } | |
a3170dc6 | 12183 | else if (TARGET_ALTIVEC_ABI) |
00b960c7 AH |
12184 | { |
12185 | info_ptr->vrsave_save_offset | |
12186 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
12187 | ||
12188 | /* Align stack so vector save area is on a quadword boundary. */ | |
12189 | if (info_ptr->altivec_size != 0) | |
12190 | info_ptr->altivec_padding_size | |
12191 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
12192 | else | |
12193 | info_ptr->altivec_padding_size = 0; | |
12194 | ||
12195 | info_ptr->altivec_save_offset | |
12196 | = info_ptr->vrsave_save_offset | |
12197 | - info_ptr->altivec_padding_size | |
12198 | - info_ptr->altivec_size; | |
12199 | ||
12200 | /* Adjust for AltiVec case. */ | |
12201 | info_ptr->toc_save_offset | |
12202 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
12203 | } | |
12204 | else | |
12205 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 12206 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
12207 | info_ptr->lr_save_offset = reg_size; |
12208 | break; | |
4697a36c MM |
12209 | } |
12210 | ||
64045029 | 12211 | save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8; |
00b960c7 AH |
12212 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
12213 | + info_ptr->gp_size | |
12214 | + info_ptr->altivec_size | |
12215 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
12216 | + info_ptr->spe_gp_size |
12217 | + info_ptr->spe_padding_size | |
00b960c7 AH |
12218 | + ehrd_size |
12219 | + info_ptr->cr_size | |
12220 | + info_ptr->lr_size | |
12221 | + info_ptr->vrsave_size | |
12222 | + info_ptr->toc_size, | |
64045029 | 12223 | save_align); |
00b960c7 | 12224 | |
44688022 | 12225 | non_fixed_size = (info_ptr->vars_size |
ff381587 | 12226 | + info_ptr->parm_size |
ff381587 | 12227 | + info_ptr->save_size |
44688022 | 12228 | + info_ptr->varargs_size); |
ff381587 | 12229 | |
44688022 AM |
12230 | info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, |
12231 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
12232 | |
12233 | /* Determine if we need to allocate any stack frame: | |
12234 | ||
a4f6c312 SS |
12235 | For AIX we need to push the stack if a frame pointer is needed |
12236 | (because the stack might be dynamically adjusted), if we are | |
12237 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
12238 | and local variables are more than the space needed to save all | |
12239 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
12240 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 12241 | |
a4f6c312 SS |
12242 | For V.4 we don't have the stack cushion that AIX uses, but assume |
12243 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
12244 | |
12245 | if (info_ptr->calls_p) | |
12246 | info_ptr->push_p = 1; | |
12247 | ||
178274da | 12248 | else if (DEFAULT_ABI == ABI_V4) |
44688022 | 12249 | info_ptr->push_p = non_fixed_size != 0; |
ff381587 | 12250 | |
178274da AM |
12251 | else if (frame_pointer_needed) |
12252 | info_ptr->push_p = 1; | |
12253 | ||
12254 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
12255 | info_ptr->push_p = 1; | |
12256 | ||
ff381587 | 12257 | else |
44688022 | 12258 | info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); |
ff381587 | 12259 | |
a4f6c312 | 12260 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 12261 | if (info_ptr->fp_size == 0) |
4697a36c MM |
12262 | info_ptr->fp_save_offset = 0; |
12263 | ||
8dda1a21 | 12264 | if (info_ptr->gp_size == 0) |
4697a36c MM |
12265 | info_ptr->gp_save_offset = 0; |
12266 | ||
00b960c7 AH |
12267 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
12268 | info_ptr->altivec_save_offset = 0; | |
12269 | ||
12270 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
12271 | info_ptr->vrsave_save_offset = 0; | |
12272 | ||
c19de7aa AH |
12273 | if (! TARGET_SPE_ABI |
12274 | || info_ptr->spe_64bit_regs_used == 0 | |
12275 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
12276 | info_ptr->spe_gp_save_offset = 0; |
12277 | ||
c81fc13e | 12278 | if (! info_ptr->lr_save_p) |
4697a36c MM |
12279 | info_ptr->lr_save_offset = 0; |
12280 | ||
c81fc13e | 12281 | if (! info_ptr->cr_save_p) |
4697a36c MM |
12282 | info_ptr->cr_save_offset = 0; |
12283 | ||
c81fc13e | 12284 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
12285 | info_ptr->toc_save_offset = 0; |
12286 | ||
4697a36c MM |
12287 | return info_ptr; |
12288 | } | |
12289 | ||
c19de7aa AH |
12290 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
12291 | mode. */ | |
12292 | ||
12293 | static bool | |
863d938c | 12294 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
12295 | { |
12296 | rtx insns, insn; | |
12297 | ||
12298 | /* Functions that save and restore all the call-saved registers will | |
12299 | need to save/restore the registers in 64-bits. */ | |
12300 | if (current_function_calls_eh_return | |
12301 | || current_function_calls_setjmp | |
12302 | || current_function_has_nonlocal_goto) | |
12303 | return true; | |
12304 | ||
12305 | insns = get_insns (); | |
12306 | ||
12307 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
12308 | { | |
12309 | if (INSN_P (insn)) | |
12310 | { | |
12311 | rtx i; | |
12312 | ||
b5a5beb9 AH |
12313 | /* FIXME: This should be implemented with attributes... |
12314 | ||
12315 | (set_attr "spe64" "true")....then, | |
12316 | if (get_spe64(insn)) return true; | |
12317 | ||
12318 | It's the only reliable way to do the stuff below. */ | |
12319 | ||
c19de7aa | 12320 | i = PATTERN (insn); |
f82f556d AH |
12321 | if (GET_CODE (i) == SET) |
12322 | { | |
12323 | enum machine_mode mode = GET_MODE (SET_SRC (i)); | |
12324 | ||
12325 | if (SPE_VECTOR_MODE (mode)) | |
12326 | return true; | |
12327 | if (TARGET_E500_DOUBLE && mode == DFmode) | |
12328 | return true; | |
12329 | } | |
c19de7aa AH |
12330 | } |
12331 | } | |
12332 | ||
12333 | return false; | |
12334 | } | |
12335 | ||
d1d0c603 | 12336 | static void |
a2369ed3 | 12337 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 12338 | { |
d330fd93 | 12339 | const char *abi_string; |
24d304eb | 12340 | |
c81fc13e | 12341 | if (! info) |
4697a36c MM |
12342 | info = rs6000_stack_info (); |
12343 | ||
12344 | fprintf (stderr, "\nStack information for function %s:\n", | |
12345 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
12346 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
12347 | : "<unknown>")); | |
12348 | ||
24d304eb RK |
12349 | switch (info->abi) |
12350 | { | |
b6c9286a MM |
12351 | default: abi_string = "Unknown"; break; |
12352 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 12353 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 12354 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 12355 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
12356 | } |
12357 | ||
12358 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
12359 | ||
00b960c7 AH |
12360 | if (TARGET_ALTIVEC_ABI) |
12361 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
12362 | ||
a3170dc6 AH |
12363 | if (TARGET_SPE_ABI) |
12364 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
12365 | ||
4697a36c MM |
12366 | if (info->first_gp_reg_save != 32) |
12367 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
12368 | ||
12369 | if (info->first_fp_reg_save != 64) | |
12370 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 12371 | |
00b960c7 AH |
12372 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
12373 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
12374 | info->first_altivec_reg_save); | |
12375 | ||
4697a36c MM |
12376 | if (info->lr_save_p) |
12377 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 12378 | |
4697a36c MM |
12379 | if (info->cr_save_p) |
12380 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
12381 | ||
b6c9286a MM |
12382 | if (info->toc_save_p) |
12383 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
12384 | ||
00b960c7 AH |
12385 | if (info->vrsave_mask) |
12386 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
12387 | ||
4697a36c MM |
12388 | if (info->push_p) |
12389 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
12390 | ||
12391 | if (info->calls_p) | |
12392 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
12393 | ||
4697a36c MM |
12394 | if (info->gp_save_offset) |
12395 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
12396 | ||
12397 | if (info->fp_save_offset) | |
12398 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
12399 | ||
00b960c7 AH |
12400 | if (info->altivec_save_offset) |
12401 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
12402 | info->altivec_save_offset); | |
12403 | ||
a3170dc6 AH |
12404 | if (info->spe_gp_save_offset) |
12405 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
12406 | info->spe_gp_save_offset); | |
12407 | ||
00b960c7 AH |
12408 | if (info->vrsave_save_offset) |
12409 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
12410 | info->vrsave_save_offset); | |
12411 | ||
4697a36c MM |
12412 | if (info->lr_save_offset) |
12413 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
12414 | ||
12415 | if (info->cr_save_offset) | |
12416 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
12417 | ||
b6c9286a MM |
12418 | if (info->toc_save_offset) |
12419 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
12420 | ||
4697a36c MM |
12421 | if (info->varargs_save_offset) |
12422 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
12423 | ||
12424 | if (info->total_size) | |
d1d0c603 JJ |
12425 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
12426 | info->total_size); | |
4697a36c MM |
12427 | |
12428 | if (info->varargs_size) | |
12429 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
12430 | ||
12431 | if (info->vars_size) | |
d1d0c603 JJ |
12432 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
12433 | info->vars_size); | |
4697a36c MM |
12434 | |
12435 | if (info->parm_size) | |
12436 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
12437 | ||
12438 | if (info->fixed_size) | |
12439 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
12440 | ||
12441 | if (info->gp_size) | |
12442 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
12443 | ||
a3170dc6 AH |
12444 | if (info->spe_gp_size) |
12445 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
12446 | ||
4697a36c MM |
12447 | if (info->fp_size) |
12448 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
12449 | ||
00b960c7 AH |
12450 | if (info->altivec_size) |
12451 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
12452 | ||
12453 | if (info->vrsave_size) | |
12454 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
12455 | ||
12456 | if (info->altivec_padding_size) | |
12457 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
12458 | info->altivec_padding_size); | |
12459 | ||
a3170dc6 AH |
12460 | if (info->spe_padding_size) |
12461 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
12462 | info->spe_padding_size); | |
12463 | ||
a4f6c312 | 12464 | if (info->lr_size) |
ed947a96 | 12465 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 12466 | |
4697a36c MM |
12467 | if (info->cr_size) |
12468 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
12469 | ||
a4f6c312 | 12470 | if (info->toc_size) |
b6c9286a MM |
12471 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
12472 | ||
4697a36c MM |
12473 | if (info->save_size) |
12474 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
12475 | ||
12476 | if (info->reg_size != 4) | |
12477 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
12478 | ||
12479 | fprintf (stderr, "\n"); | |
9878760c | 12480 | } |
71f123ca FS |
12481 | |
12482 | rtx | |
a2369ed3 | 12483 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 12484 | { |
a4f6c312 SS |
12485 | /* Currently we don't optimize very well between prolog and body |
12486 | code and for PIC code the code can be actually quite bad, so | |
12487 | don't try to be too clever here. */ | |
f1384257 | 12488 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
12489 | { |
12490 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
12491 | |
12492 | return | |
12493 | gen_rtx_MEM | |
12494 | (Pmode, | |
12495 | memory_address | |
12496 | (Pmode, | |
12497 | plus_constant (copy_to_reg | |
12498 | (gen_rtx_MEM (Pmode, | |
12499 | memory_address (Pmode, frame))), | |
12500 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
12501 | } |
12502 | ||
8c29550d | 12503 | cfun->machine->ra_need_lr = 1; |
9e2f7ec7 | 12504 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
12505 | } |
12506 | ||
5e1bf043 DJ |
12507 | /* Say whether a function is a candidate for sibcall handling or not. |
12508 | We do not allow indirect calls to be optimized into sibling calls. | |
12509 | Also, we can't do it if there are any vector parameters; there's | |
12510 | nowhere to put the VRsave code so it works; note that functions with | |
12511 | vector parameters are required to have a prototype, so the argument | |
12512 | type info must be available here. (The tail recursion case can work | |
12513 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 12514 | static bool |
a2369ed3 | 12515 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
12516 | { |
12517 | tree type; | |
4977bab6 | 12518 | if (decl) |
5e1bf043 DJ |
12519 | { |
12520 | if (TARGET_ALTIVEC_VRSAVE) | |
c4ad648e | 12521 | { |
4977bab6 | 12522 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
12523 | type; type = TREE_CHAIN (type)) |
12524 | { | |
c15b529f | 12525 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 12526 | return false; |
5e1bf043 | 12527 | } |
c4ad648e | 12528 | } |
5e1bf043 | 12529 | if (DEFAULT_ABI == ABI_DARWIN |
4977bab6 | 12530 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 12531 | { |
4977bab6 | 12532 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
12533 | |
12534 | if (!lookup_attribute ("longcall", attr_list) | |
12535 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 12536 | return true; |
2bcc50d0 | 12537 | } |
5e1bf043 | 12538 | } |
4977bab6 | 12539 | return false; |
5e1bf043 DJ |
12540 | } |
12541 | ||
e7e64a25 AS |
12542 | /* NULL if INSN insn is valid within a low-overhead loop. |
12543 | Otherwise return why doloop cannot be applied. | |
9419649c DE |
12544 | PowerPC uses the COUNT register for branch on table instructions. */ |
12545 | ||
e7e64a25 AS |
12546 | static const char * |
12547 | rs6000_invalid_within_doloop (rtx insn) | |
9419649c DE |
12548 | { |
12549 | if (CALL_P (insn)) | |
e7e64a25 | 12550 | return "Function call in the loop."; |
9419649c DE |
12551 | |
12552 | if (JUMP_P (insn) | |
12553 | && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
12554 | || GET_CODE (PATTERN (insn)) == ADDR_VEC)) | |
e7e64a25 | 12555 | return "Computed branch in the loop."; |
9419649c | 12556 | |
e7e64a25 | 12557 | return NULL; |
9419649c DE |
12558 | } |
12559 | ||
71f123ca | 12560 | static int |
863d938c | 12561 | rs6000_ra_ever_killed (void) |
71f123ca FS |
12562 | { |
12563 | rtx top; | |
5e1bf043 DJ |
12564 | rtx reg; |
12565 | rtx insn; | |
71f123ca | 12566 | |
dd292d0a | 12567 | if (current_function_is_thunk) |
71f123ca | 12568 | return 0; |
eb0424da | 12569 | |
36f7e964 AH |
12570 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
12571 | but this should not force saving and restoring in the | |
12572 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 12573 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 12574 | |
5e1bf043 DJ |
12575 | /* Also, the prologue can generate a store into LR that |
12576 | doesn't really count, like this: | |
36f7e964 | 12577 | |
5e1bf043 DJ |
12578 | move LR->R0 |
12579 | bcl to set PIC register | |
12580 | move LR->R31 | |
12581 | move R0->LR | |
36f7e964 AH |
12582 | |
12583 | When we're called from the epilogue, we need to avoid counting | |
12584 | this as a store. */ | |
f676971a | 12585 | |
71f123ca FS |
12586 | push_topmost_sequence (); |
12587 | top = get_insns (); | |
12588 | pop_topmost_sequence (); | |
5e1bf043 | 12589 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 12590 | |
5e1bf043 DJ |
12591 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
12592 | { | |
12593 | if (INSN_P (insn)) | |
12594 | { | |
12595 | if (FIND_REG_INC_NOTE (insn, reg)) | |
12596 | return 1; | |
f676971a | 12597 | else if (GET_CODE (insn) == CALL_INSN |
c15b529f | 12598 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 12599 | return 1; |
36f7e964 AH |
12600 | else if (set_of (reg, insn) != NULL_RTX |
12601 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
12602 | return 1; |
12603 | } | |
12604 | } | |
12605 | return 0; | |
71f123ca | 12606 | } |
4697a36c | 12607 | \f |
8cd8f856 GK |
12608 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
12609 | static void | |
a2369ed3 | 12610 | rs6000_maybe_dead (rtx insn) |
8cd8f856 GK |
12611 | { |
12612 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
12613 | const0_rtx, | |
12614 | REG_NOTES (insn)); | |
12615 | } | |
12616 | ||
9ebbca7d | 12617 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 12618 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 12619 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
12620 | |
12621 | void | |
a2369ed3 | 12622 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 12623 | { |
027fbf43 | 12624 | rtx dest, insn; |
1db02437 | 12625 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 12626 | |
7f970b70 | 12627 | if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic) |
20b71b17 | 12628 | { |
7f970b70 AM |
12629 | char buf[30]; |
12630 | rtx lab, tmp1, tmp2, got, tempLR; | |
12631 | ||
12632 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
12633 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12634 | if (flag_pic == 2) | |
12635 | got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
12636 | else | |
12637 | got = rs6000_got_sym (); | |
12638 | tmp1 = tmp2 = dest; | |
12639 | if (!fromprolog) | |
12640 | { | |
12641 | tmp1 = gen_reg_rtx (Pmode); | |
12642 | tmp2 = gen_reg_rtx (Pmode); | |
12643 | } | |
12644 | tempLR = (fromprolog | |
12645 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
12646 | : gen_reg_rtx (Pmode)); | |
12647 | insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab)); | |
12648 | if (fromprolog) | |
12649 | rs6000_maybe_dead (insn); | |
12650 | insn = emit_move_insn (tmp1, tempLR); | |
12651 | if (fromprolog) | |
12652 | rs6000_maybe_dead (insn); | |
12653 | insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab)); | |
12654 | if (fromprolog) | |
12655 | rs6000_maybe_dead (insn); | |
12656 | insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab)); | |
12657 | if (fromprolog) | |
12658 | rs6000_maybe_dead (insn); | |
12659 | } | |
12660 | else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) | |
12661 | { | |
12662 | rtx tempLR = (fromprolog | |
12663 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
12664 | : gen_reg_rtx (Pmode)); | |
12665 | ||
12666 | insn = emit_insn (gen_load_toc_v4_pic_si (tempLR)); | |
027fbf43 JJ |
12667 | if (fromprolog) |
12668 | rs6000_maybe_dead (insn); | |
7f970b70 | 12669 | insn = emit_move_insn (dest, tempLR); |
027fbf43 JJ |
12670 | if (fromprolog) |
12671 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
12672 | } |
12673 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
12674 | { | |
12675 | char buf[30]; | |
12676 | rtx tempLR = (fromprolog | |
12677 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
12678 | : gen_reg_rtx (Pmode)); | |
12679 | rtx temp0 = (fromprolog | |
12680 | ? gen_rtx_REG (Pmode, 0) | |
12681 | : gen_reg_rtx (Pmode)); | |
20b71b17 | 12682 | |
20b71b17 AM |
12683 | if (fromprolog) |
12684 | { | |
ccbca5e4 | 12685 | rtx symF, symL; |
38c1f2d7 | 12686 | |
20b71b17 AM |
12687 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
12688 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 12689 | |
20b71b17 AM |
12690 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
12691 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12692 | ||
12693 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
12694 | symF))); | |
12695 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
12696 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
12697 | symL, | |
12698 | symF))); | |
9ebbca7d GK |
12699 | } |
12700 | else | |
20b71b17 AM |
12701 | { |
12702 | rtx tocsym; | |
20b71b17 AM |
12703 | |
12704 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
ccbca5e4 | 12705 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym)); |
027fbf43 JJ |
12706 | emit_move_insn (dest, tempLR); |
12707 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 12708 | } |
027fbf43 JJ |
12709 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
12710 | if (fromprolog) | |
12711 | rs6000_maybe_dead (insn); | |
9ebbca7d | 12712 | } |
20b71b17 AM |
12713 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
12714 | { | |
12715 | /* This is for AIX code running in non-PIC ELF32. */ | |
12716 | char buf[30]; | |
12717 | rtx realsym; | |
12718 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
12719 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12720 | ||
027fbf43 JJ |
12721 | insn = emit_insn (gen_elf_high (dest, realsym)); |
12722 | if (fromprolog) | |
12723 | rs6000_maybe_dead (insn); | |
12724 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
12725 | if (fromprolog) | |
12726 | rs6000_maybe_dead (insn); | |
20b71b17 | 12727 | } |
37409796 | 12728 | else |
9ebbca7d | 12729 | { |
37409796 NS |
12730 | gcc_assert (DEFAULT_ABI == ABI_AIX); |
12731 | ||
9ebbca7d | 12732 | if (TARGET_32BIT) |
027fbf43 | 12733 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 12734 | else |
027fbf43 JJ |
12735 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
12736 | if (fromprolog) | |
12737 | rs6000_maybe_dead (insn); | |
9ebbca7d GK |
12738 | } |
12739 | } | |
12740 | ||
d1d0c603 JJ |
12741 | /* Emit instructions to restore the link register after determining where |
12742 | its value has been stored. */ | |
12743 | ||
12744 | void | |
12745 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
12746 | { | |
12747 | rs6000_stack_t *info = rs6000_stack_info (); | |
12748 | rtx operands[2]; | |
12749 | ||
12750 | operands[0] = source; | |
12751 | operands[1] = scratch; | |
12752 | ||
12753 | if (info->lr_save_p) | |
12754 | { | |
12755 | rtx frame_rtx = stack_pointer_rtx; | |
12756 | HOST_WIDE_INT sp_offset = 0; | |
12757 | rtx tmp; | |
12758 | ||
12759 | if (frame_pointer_needed | |
12760 | || current_function_calls_alloca | |
12761 | || info->total_size > 32767) | |
12762 | { | |
12763 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
12764 | frame_rtx = operands[1]; | |
12765 | } | |
12766 | else if (info->push_p) | |
12767 | sp_offset = info->total_size; | |
12768 | ||
12769 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
12770 | tmp = gen_rtx_MEM (Pmode, tmp); | |
12771 | emit_move_insn (tmp, operands[0]); | |
12772 | } | |
12773 | else | |
12774 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
12775 | } | |
12776 | ||
f103e34d GK |
12777 | static GTY(()) int set = -1; |
12778 | ||
f676971a | 12779 | int |
863d938c | 12780 | get_TOC_alias_set (void) |
9ebbca7d | 12781 | { |
f103e34d GK |
12782 | if (set == -1) |
12783 | set = new_alias_set (); | |
12784 | return set; | |
f676971a | 12785 | } |
9ebbca7d | 12786 | |
c1207243 | 12787 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
12788 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
12789 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 12790 | #if TARGET_ELF |
3c9eb5f4 | 12791 | static int |
f676971a | 12792 | uses_TOC (void) |
9ebbca7d | 12793 | { |
c4501e62 | 12794 | rtx insn; |
38c1f2d7 | 12795 | |
c4501e62 JJ |
12796 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
12797 | if (INSN_P (insn)) | |
12798 | { | |
12799 | rtx pat = PATTERN (insn); | |
12800 | int i; | |
9ebbca7d | 12801 | |
f676971a | 12802 | if (GET_CODE (pat) == PARALLEL) |
c4501e62 JJ |
12803 | for (i = 0; i < XVECLEN (pat, 0); i++) |
12804 | { | |
12805 | rtx sub = XVECEXP (pat, 0, i); | |
12806 | if (GET_CODE (sub) == USE) | |
12807 | { | |
12808 | sub = XEXP (sub, 0); | |
12809 | if (GET_CODE (sub) == UNSPEC | |
12810 | && XINT (sub, 1) == UNSPEC_TOC) | |
12811 | return 1; | |
12812 | } | |
12813 | } | |
12814 | } | |
12815 | return 0; | |
9ebbca7d | 12816 | } |
c954844a | 12817 | #endif |
38c1f2d7 | 12818 | |
9ebbca7d | 12819 | rtx |
f676971a | 12820 | create_TOC_reference (rtx symbol) |
9ebbca7d | 12821 | { |
f676971a | 12822 | return gen_rtx_PLUS (Pmode, |
a8a05998 | 12823 | gen_rtx_REG (Pmode, TOC_REGISTER), |
f676971a EC |
12824 | gen_rtx_CONST (Pmode, |
12825 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 12826 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 12827 | } |
38c1f2d7 | 12828 | |
fc4767bb JJ |
12829 | /* If _Unwind_* has been called from within the same module, |
12830 | toc register is not guaranteed to be saved to 40(1) on function | |
12831 | entry. Save it there in that case. */ | |
c7ca610e | 12832 | |
9ebbca7d | 12833 | void |
863d938c | 12834 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
12835 | { |
12836 | rtx mem; | |
12837 | rtx stack_top = gen_reg_rtx (Pmode); | |
12838 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
12839 | rtx opcode = gen_reg_rtx (SImode); |
12840 | rtx tocompare = gen_reg_rtx (SImode); | |
12841 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d GK |
12842 | |
12843 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
12844 | emit_move_insn (stack_top, mem); | |
12845 | ||
fc4767bb JJ |
12846 | mem = gen_rtx_MEM (Pmode, |
12847 | gen_rtx_PLUS (Pmode, stack_top, | |
9ebbca7d GK |
12848 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); |
12849 | emit_move_insn (opcode_addr, mem); | |
fc4767bb JJ |
12850 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
12851 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 12852 | : 0xE8410028, SImode)); |
9ebbca7d | 12853 | |
fc4767bb | 12854 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 12855 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 12856 | no_toc_save_needed); |
9ebbca7d | 12857 | |
fc4767bb JJ |
12858 | mem = gen_rtx_MEM (Pmode, |
12859 | gen_rtx_PLUS (Pmode, stack_top, | |
12860 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
12861 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); | |
12862 | emit_label (no_toc_save_needed); | |
9ebbca7d | 12863 | } |
38c1f2d7 | 12864 | \f |
ba4828e0 RK |
12865 | /* This ties together stack memory (MEM with an alias set of |
12866 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
12867 | ||
9ebbca7d | 12868 | static void |
863d938c | 12869 | rs6000_emit_stack_tie (void) |
9ebbca7d | 12870 | { |
ba4828e0 RK |
12871 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
12872 | ||
12873 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
12874 | emit_insn (gen_stack_tie (mem)); |
12875 | } | |
38c1f2d7 | 12876 | |
9ebbca7d GK |
12877 | /* Emit the correct code for allocating stack space, as insns. |
12878 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
12879 | The generated code may use hard register 0 as a temporary. */ | |
12880 | ||
12881 | static void | |
a2369ed3 | 12882 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) |
38c1f2d7 | 12883 | { |
9ebbca7d GK |
12884 | rtx insn; |
12885 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
12886 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
61168ff1 RS |
12887 | rtx todec = gen_int_mode (-size, Pmode); |
12888 | ||
12889 | if (INTVAL (todec) != -size) | |
12890 | { | |
d4ee4d25 | 12891 | warning (0, "stack frame too large"); |
61168ff1 RS |
12892 | emit_insn (gen_trap ()); |
12893 | return; | |
12894 | } | |
a157febd GK |
12895 | |
12896 | if (current_function_limit_stack) | |
12897 | { | |
12898 | if (REG_P (stack_limit_rtx) | |
f676971a | 12899 | && REGNO (stack_limit_rtx) > 1 |
a157febd GK |
12900 | && REGNO (stack_limit_rtx) <= 31) |
12901 | { | |
5b71a4e7 | 12902 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
12903 | ? gen_addsi3 (tmp_reg, |
12904 | stack_limit_rtx, | |
12905 | GEN_INT (size)) | |
12906 | : gen_adddi3 (tmp_reg, | |
12907 | stack_limit_rtx, | |
12908 | GEN_INT (size))); | |
5b71a4e7 | 12909 | |
9ebbca7d GK |
12910 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
12911 | const0_rtx)); | |
a157febd GK |
12912 | } |
12913 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 12914 | && TARGET_32BIT |
f607bc57 | 12915 | && DEFAULT_ABI == ABI_V4) |
a157febd | 12916 | { |
9ebbca7d | 12917 | rtx toload = gen_rtx_CONST (VOIDmode, |
f676971a EC |
12918 | gen_rtx_PLUS (Pmode, |
12919 | stack_limit_rtx, | |
9ebbca7d | 12920 | GEN_INT (size))); |
5b71a4e7 | 12921 | |
9ebbca7d GK |
12922 | emit_insn (gen_elf_high (tmp_reg, toload)); |
12923 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
12924 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
12925 | const0_rtx)); | |
a157febd GK |
12926 | } |
12927 | else | |
d4ee4d25 | 12928 | warning (0, "stack limit expression is not supported"); |
a157febd GK |
12929 | } |
12930 | ||
9ebbca7d GK |
12931 | if (copy_r12 || ! TARGET_UPDATE) |
12932 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
12933 | ||
38c1f2d7 MM |
12934 | if (TARGET_UPDATE) |
12935 | { | |
9ebbca7d | 12936 | if (size > 32767) |
38c1f2d7 | 12937 | { |
9ebbca7d | 12938 | /* Need a note here so that try_split doesn't get confused. */ |
9390387d | 12939 | if (get_last_insn () == NULL_RTX) |
2e040219 | 12940 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d GK |
12941 | insn = emit_move_insn (tmp_reg, todec); |
12942 | try_split (PATTERN (insn), insn, 0); | |
12943 | todec = tmp_reg; | |
38c1f2d7 | 12944 | } |
5b71a4e7 DE |
12945 | |
12946 | insn = emit_insn (TARGET_32BIT | |
12947 | ? gen_movsi_update (stack_reg, stack_reg, | |
12948 | todec, stack_reg) | |
c4ad648e | 12949 | : gen_movdi_di_update (stack_reg, stack_reg, |
9ebbca7d | 12950 | todec, stack_reg)); |
38c1f2d7 MM |
12951 | } |
12952 | else | |
12953 | { | |
5b71a4e7 DE |
12954 | insn = emit_insn (TARGET_32BIT |
12955 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
12956 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
12957 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
12958 | gen_rtx_REG (Pmode, 12)); | |
12959 | } | |
f676971a | 12960 | |
9ebbca7d | 12961 | RTX_FRAME_RELATED_P (insn) = 1; |
f676971a | 12962 | REG_NOTES (insn) = |
9ebbca7d | 12963 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, |
f676971a | 12964 | gen_rtx_SET (VOIDmode, stack_reg, |
9ebbca7d GK |
12965 | gen_rtx_PLUS (Pmode, stack_reg, |
12966 | GEN_INT (-size))), | |
12967 | REG_NOTES (insn)); | |
12968 | } | |
12969 | ||
a4f6c312 SS |
12970 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
12971 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
12972 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
12973 | deduce these equivalences by itself so it wasn't necessary to hold | |
12974 | its hand so much. */ | |
9ebbca7d GK |
12975 | |
12976 | static void | |
f676971a | 12977 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
a2369ed3 | 12978 | rtx reg2, rtx rreg) |
9ebbca7d GK |
12979 | { |
12980 | rtx real, temp; | |
12981 | ||
e56c4463 JL |
12982 | /* copy_rtx will not make unique copies of registers, so we need to |
12983 | ensure we don't have unwanted sharing here. */ | |
12984 | if (reg == reg2) | |
12985 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12986 | ||
12987 | if (reg == rreg) | |
12988 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12989 | ||
9ebbca7d GK |
12990 | real = copy_rtx (PATTERN (insn)); |
12991 | ||
89e7058f AH |
12992 | if (reg2 != NULL_RTX) |
12993 | real = replace_rtx (real, reg2, rreg); | |
f676971a EC |
12994 | |
12995 | real = replace_rtx (real, reg, | |
9ebbca7d GK |
12996 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, |
12997 | STACK_POINTER_REGNUM), | |
12998 | GEN_INT (val))); | |
f676971a | 12999 | |
9ebbca7d GK |
13000 | /* We expect that 'real' is either a SET or a PARALLEL containing |
13001 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
13002 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
13003 | ||
13004 | if (GET_CODE (real) == SET) | |
13005 | { | |
13006 | rtx set = real; | |
f676971a | 13007 | |
9ebbca7d GK |
13008 | temp = simplify_rtx (SET_SRC (set)); |
13009 | if (temp) | |
13010 | SET_SRC (set) = temp; | |
13011 | temp = simplify_rtx (SET_DEST (set)); | |
13012 | if (temp) | |
13013 | SET_DEST (set) = temp; | |
13014 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 13015 | { |
9ebbca7d GK |
13016 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
13017 | if (temp) | |
13018 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 13019 | } |
38c1f2d7 | 13020 | } |
37409796 | 13021 | else |
9ebbca7d GK |
13022 | { |
13023 | int i; | |
37409796 NS |
13024 | |
13025 | gcc_assert (GET_CODE (real) == PARALLEL); | |
9ebbca7d GK |
13026 | for (i = 0; i < XVECLEN (real, 0); i++) |
13027 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
13028 | { | |
13029 | rtx set = XVECEXP (real, 0, i); | |
f676971a | 13030 | |
9ebbca7d GK |
13031 | temp = simplify_rtx (SET_SRC (set)); |
13032 | if (temp) | |
13033 | SET_SRC (set) = temp; | |
13034 | temp = simplify_rtx (SET_DEST (set)); | |
13035 | if (temp) | |
13036 | SET_DEST (set) = temp; | |
13037 | if (GET_CODE (SET_DEST (set)) == MEM) | |
13038 | { | |
13039 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
13040 | if (temp) | |
13041 | XEXP (SET_DEST (set), 0) = temp; | |
13042 | } | |
13043 | RTX_FRAME_RELATED_P (set) = 1; | |
13044 | } | |
13045 | } | |
c19de7aa AH |
13046 | |
13047 | if (TARGET_SPE) | |
13048 | real = spe_synthesize_frame_save (real); | |
13049 | ||
9ebbca7d GK |
13050 | RTX_FRAME_RELATED_P (insn) = 1; |
13051 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13052 | real, | |
13053 | REG_NOTES (insn)); | |
38c1f2d7 MM |
13054 | } |
13055 | ||
c19de7aa AH |
13056 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
13057 | original note, plus a synthetic register save. */ | |
13058 | ||
13059 | static rtx | |
a2369ed3 | 13060 | spe_synthesize_frame_save (rtx real) |
c19de7aa AH |
13061 | { |
13062 | rtx synth, offset, reg, real2; | |
13063 | ||
13064 | if (GET_CODE (real) != SET | |
13065 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
13066 | return real; | |
13067 | ||
13068 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
13069 | frame related note. The parallel contains a set of the register | |
41f3a930 | 13070 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
13071 | This is so we can differentiate between 64-bit and 32-bit saves. |
13072 | Words cannot describe this nastiness. */ | |
13073 | ||
37409796 NS |
13074 | gcc_assert (GET_CODE (SET_DEST (real)) == MEM |
13075 | && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS | |
13076 | && GET_CODE (SET_SRC (real)) == REG); | |
c19de7aa AH |
13077 | |
13078 | /* Transform: | |
13079 | (set (mem (plus (reg x) (const y))) | |
13080 | (reg z)) | |
13081 | into: | |
13082 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 13083 | (reg z+1200)) |
c19de7aa AH |
13084 | */ |
13085 | ||
13086 | real2 = copy_rtx (real); | |
13087 | PUT_MODE (SET_DEST (real2), SImode); | |
13088 | reg = SET_SRC (real2); | |
13089 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
13090 | synth = copy_rtx (real2); | |
13091 | ||
13092 | if (BYTES_BIG_ENDIAN) | |
13093 | { | |
13094 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
13095 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
13096 | } | |
13097 | ||
13098 | reg = SET_SRC (synth); | |
41f3a930 | 13099 | |
c19de7aa | 13100 | synth = replace_rtx (synth, reg, |
41f3a930 | 13101 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
13102 | |
13103 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
13104 | synth = replace_rtx (synth, offset, | |
13105 | GEN_INT (INTVAL (offset) | |
13106 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
13107 | ||
13108 | RTX_FRAME_RELATED_P (synth) = 1; | |
13109 | RTX_FRAME_RELATED_P (real2) = 1; | |
13110 | if (BYTES_BIG_ENDIAN) | |
13111 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
13112 | else | |
13113 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
13114 | ||
13115 | return real; | |
13116 | } | |
13117 | ||
00b960c7 AH |
13118 | /* Returns an insn that has a vrsave set operation with the |
13119 | appropriate CLOBBERs. */ | |
13120 | ||
13121 | static rtx | |
a2369ed3 | 13122 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
13123 | { |
13124 | int nclobs, i; | |
13125 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 13126 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 13127 | |
a004eb82 AH |
13128 | clobs[0] |
13129 | = gen_rtx_SET (VOIDmode, | |
13130 | vrsave, | |
13131 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
13132 | gen_rtvec (2, reg, vrsave), | |
13133 | 30)); | |
00b960c7 AH |
13134 | |
13135 | nclobs = 1; | |
13136 | ||
9aa86737 AH |
13137 | /* We need to clobber the registers in the mask so the scheduler |
13138 | does not move sets to VRSAVE before sets of AltiVec registers. | |
13139 | ||
13140 | However, if the function receives nonlocal gotos, reload will set | |
13141 | all call saved registers live. We will end up with: | |
13142 | ||
13143 | (set (reg 999) (mem)) | |
13144 | (parallel [ (set (reg vrsave) (unspec blah)) | |
13145 | (clobber (reg 999))]) | |
13146 | ||
13147 | The clobber will cause the store into reg 999 to be dead, and | |
13148 | flow will attempt to delete an epilogue insn. In this case, we | |
13149 | need an unspec use/set of the register. */ | |
00b960c7 AH |
13150 | |
13151 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
44688022 | 13152 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) |
9aa86737 AH |
13153 | { |
13154 | if (!epiloguep || call_used_regs [i]) | |
13155 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
13156 | gen_rtx_REG (V4SImode, i)); | |
13157 | else | |
13158 | { | |
13159 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
13160 | |
13161 | clobs[nclobs++] | |
a004eb82 AH |
13162 | = gen_rtx_SET (VOIDmode, |
13163 | reg, | |
13164 | gen_rtx_UNSPEC (V4SImode, | |
13165 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
13166 | } |
13167 | } | |
00b960c7 AH |
13168 | |
13169 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
13170 | ||
13171 | for (i = 0; i < nclobs; ++i) | |
13172 | XVECEXP (insn, 0, i) = clobs[i]; | |
13173 | ||
13174 | return insn; | |
13175 | } | |
13176 | ||
89e7058f AH |
13177 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
13178 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
13179 | ||
13180 | static void | |
f676971a | 13181 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 13182 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
13183 | { |
13184 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
13185 | rtx replacea, replaceb; | |
13186 | ||
13187 | int_rtx = GEN_INT (offset); | |
13188 | ||
13189 | /* Some cases that need register indexed addressing. */ | |
13190 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
4d4cbc0e | 13191 | || (TARGET_E500_DOUBLE && mode == DFmode) |
a3170dc6 AH |
13192 | || (TARGET_SPE_ABI |
13193 | && SPE_VECTOR_MODE (mode) | |
13194 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
13195 | { |
13196 | /* Whomever calls us must make sure r11 is available in the | |
c4ad648e | 13197 | flow path of instructions in the prologue. */ |
89e7058f AH |
13198 | offset_rtx = gen_rtx_REG (Pmode, 11); |
13199 | emit_move_insn (offset_rtx, int_rtx); | |
13200 | ||
13201 | replacea = offset_rtx; | |
13202 | replaceb = int_rtx; | |
13203 | } | |
13204 | else | |
13205 | { | |
13206 | offset_rtx = int_rtx; | |
13207 | replacea = NULL_RTX; | |
13208 | replaceb = NULL_RTX; | |
13209 | } | |
13210 | ||
13211 | reg = gen_rtx_REG (mode, regno); | |
13212 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
13213 | mem = gen_rtx_MEM (mode, addr); | |
13214 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13215 | ||
13216 | insn = emit_move_insn (mem, reg); | |
13217 | ||
13218 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
13219 | } | |
13220 | ||
a3170dc6 AH |
13221 | /* Emit an offset memory reference suitable for a frame store, while |
13222 | converting to a valid addressing mode. */ | |
13223 | ||
13224 | static rtx | |
a2369ed3 | 13225 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
13226 | { |
13227 | rtx int_rtx, offset_rtx; | |
13228 | ||
13229 | int_rtx = GEN_INT (offset); | |
13230 | ||
4d4cbc0e AH |
13231 | if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) |
13232 | || (TARGET_E500_DOUBLE && mode == DFmode)) | |
a3170dc6 AH |
13233 | { |
13234 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13235 | emit_move_insn (offset_rtx, int_rtx); | |
13236 | } | |
13237 | else | |
13238 | offset_rtx = int_rtx; | |
13239 | ||
13240 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
13241 | } | |
13242 | ||
6d0a8091 DJ |
13243 | /* Look for user-defined global regs. We should not save and restore these, |
13244 | and cannot use stmw/lmw if there are any in its range. */ | |
13245 | ||
13246 | static bool | |
13247 | no_global_regs_above (int first_greg) | |
13248 | { | |
13249 | int i; | |
13250 | for (i = 0; i < 32 - first_greg; i++) | |
13251 | if (global_regs[first_greg + i]) | |
13252 | return false; | |
13253 | return true; | |
13254 | } | |
13255 | ||
699c914a MS |
13256 | #ifndef TARGET_FIX_AND_CONTINUE |
13257 | #define TARGET_FIX_AND_CONTINUE 0 | |
13258 | #endif | |
13259 | ||
9ebbca7d GK |
13260 | /* Emit function prologue as insns. */ |
13261 | ||
9878760c | 13262 | void |
863d938c | 13263 | rs6000_emit_prologue (void) |
9878760c | 13264 | { |
4697a36c | 13265 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a | 13266 | enum machine_mode reg_mode = Pmode; |
327e5343 | 13267 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
13268 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
13269 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
13270 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 13271 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d GK |
13272 | rtx insn; |
13273 | int saving_FPRs_inline; | |
13274 | int using_store_multiple; | |
13275 | HOST_WIDE_INT sp_offset = 0; | |
f676971a | 13276 | |
699c914a MS |
13277 | if (TARGET_FIX_AND_CONTINUE) |
13278 | { | |
13279 | /* gdb on darwin arranges to forward a function from the old | |
de2ab0ca | 13280 | address by modifying the first 5 instructions of the function |
699c914a MS |
13281 | to branch to the overriding function. This is necessary to |
13282 | permit function pointers that point to the old function to | |
13283 | actually forward to the new function. */ | |
13284 | emit_insn (gen_nop ()); | |
13285 | emit_insn (gen_nop ()); | |
de2ab0ca | 13286 | emit_insn (gen_nop ()); |
699c914a MS |
13287 | emit_insn (gen_nop ()); |
13288 | emit_insn (gen_nop ()); | |
13289 | } | |
13290 | ||
13291 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
13292 | { | |
13293 | reg_mode = V2SImode; | |
13294 | reg_size = 8; | |
13295 | } | |
a3170dc6 | 13296 | |
9ebbca7d | 13297 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
13298 | && (!TARGET_SPE_ABI |
13299 | || info->spe_64bit_regs_used == 0) | |
6d0a8091 DJ |
13300 | && info->first_gp_reg_save < 31 |
13301 | && no_global_regs_above (info->first_gp_reg_save)); | |
9ebbca7d | 13302 | saving_FPRs_inline = (info->first_fp_reg_save == 64 |
8c29550d | 13303 | || FP_SAVE_INLINE (info->first_fp_reg_save) |
acd0b319 | 13304 | || current_function_calls_eh_return |
8c29550d | 13305 | || cfun->machine->ra_need_lr); |
9ebbca7d GK |
13306 | |
13307 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
fc4767bb | 13308 | if (info->push_p |
acd0b319 AM |
13309 | && (DEFAULT_ABI == ABI_V4 |
13310 | || current_function_calls_eh_return)) | |
9ebbca7d GK |
13311 | { |
13312 | if (info->total_size < 32767) | |
13313 | sp_offset = info->total_size; | |
13314 | else | |
13315 | frame_reg_rtx = frame_ptr_rtx; | |
f676971a | 13316 | rs6000_emit_allocate_stack (info->total_size, |
9ebbca7d GK |
13317 | (frame_reg_rtx != sp_reg_rtx |
13318 | && (info->cr_save_p | |
13319 | || info->lr_save_p | |
13320 | || info->first_fp_reg_save < 64 | |
13321 | || info->first_gp_reg_save < 32 | |
13322 | ))); | |
13323 | if (frame_reg_rtx != sp_reg_rtx) | |
13324 | rs6000_emit_stack_tie (); | |
13325 | } | |
13326 | ||
d62294f5 | 13327 | /* Handle world saves specially here. */ |
f57fe068 | 13328 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
13329 | { |
13330 | int i, j, sz; | |
13331 | rtx treg; | |
13332 | rtvec p; | |
13333 | ||
13334 | /* save_world expects lr in r0. */ | |
13335 | if (info->lr_save_p) | |
c4ad648e AM |
13336 | { |
13337 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
13338 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
13339 | RTX_FRAME_RELATED_P (insn) = 1; | |
13340 | } | |
d62294f5 FJ |
13341 | |
13342 | /* The SAVE_WORLD and RESTORE_WORLD routines make a number of | |
c4ad648e | 13343 | assumptions about the offsets of various bits of the stack |
992d08b1 | 13344 | frame. */ |
37409796 NS |
13345 | gcc_assert (info->gp_save_offset == -220 |
13346 | && info->fp_save_offset == -144 | |
13347 | && info->lr_save_offset == 8 | |
13348 | && info->cr_save_offset == 4 | |
13349 | && info->push_p | |
13350 | && info->lr_save_p | |
13351 | && (!current_function_calls_eh_return | |
13352 | || info->ehrd_offset == -432) | |
13353 | && info->vrsave_save_offset == -224 | |
13354 | && info->altivec_save_offset == (-224 -16 -192)); | |
d62294f5 FJ |
13355 | |
13356 | treg = gen_rtx_REG (SImode, 11); | |
13357 | emit_move_insn (treg, GEN_INT (-info->total_size)); | |
13358 | ||
13359 | /* SAVE_WORLD takes the caller's LR in R0 and the frame size | |
c4ad648e | 13360 | in R11. It also clobbers R12, so beware! */ |
d62294f5 FJ |
13361 | |
13362 | /* Preserve CR2 for save_world prologues */ | |
13363 | sz = 6; | |
13364 | sz += 32 - info->first_gp_reg_save; | |
13365 | sz += 64 - info->first_fp_reg_save; | |
13366 | sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1; | |
13367 | p = rtvec_alloc (sz); | |
13368 | j = 0; | |
13369 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, | |
c4ad648e AM |
13370 | gen_rtx_REG (Pmode, |
13371 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 13372 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, |
c4ad648e AM |
13373 | gen_rtx_SYMBOL_REF (Pmode, |
13374 | "*save_world")); | |
d62294f5 | 13375 | /* We do floats first so that the instruction pattern matches |
c4ad648e AM |
13376 | properly. */ |
13377 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
13378 | { | |
13379 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
13380 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13381 | GEN_INT (info->fp_save_offset | |
13382 | + sp_offset + 8 * i)); | |
13383 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
13384 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13385 | ||
13386 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13387 | } | |
d62294f5 | 13388 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
13389 | { |
13390 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
13391 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13392 | GEN_INT (info->altivec_save_offset | |
13393 | + sp_offset + 16 * i)); | |
13394 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
13395 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13396 | ||
13397 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13398 | } | |
d62294f5 | 13399 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
c4ad648e AM |
13400 | { |
13401 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
13402 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13403 | GEN_INT (info->gp_save_offset | |
13404 | + sp_offset + reg_size * i)); | |
13405 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13406 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13407 | ||
13408 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13409 | } | |
13410 | ||
13411 | { | |
13412 | /* CR register traditionally saved as CR2. */ | |
13413 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
13414 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13415 | GEN_INT (info->cr_save_offset | |
13416 | + sp_offset)); | |
13417 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13418 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13419 | ||
13420 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13421 | } | |
d62294f5 FJ |
13422 | /* Prevent any attempt to delete the setting of r0 and treg! */ |
13423 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0)); | |
13424 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg); | |
13425 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx); | |
13426 | ||
13427 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
13428 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
c4ad648e | 13429 | NULL_RTX, NULL_RTX); |
d62294f5 FJ |
13430 | |
13431 | if (current_function_calls_eh_return) | |
c4ad648e AM |
13432 | { |
13433 | unsigned int i; | |
13434 | for (i = 0; ; ++i) | |
13435 | { | |
13436 | unsigned int regno = EH_RETURN_DATA_REGNO (i); | |
13437 | if (regno == INVALID_REGNUM) | |
13438 | break; | |
13439 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, | |
13440 | info->ehrd_offset + sp_offset | |
13441 | + reg_size * (int) i, | |
13442 | info->total_size); | |
13443 | } | |
13444 | } | |
d62294f5 FJ |
13445 | } |
13446 | ||
9aa86737 | 13447 | /* Save AltiVec registers if needed. */ |
f57fe068 | 13448 | if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0) |
9aa86737 AH |
13449 | { |
13450 | int i; | |
13451 | ||
13452 | /* There should be a non inline version of this, for when we | |
13453 | are saving lots of vector registers. */ | |
13454 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
13455 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
13456 | { | |
13457 | rtx areg, savereg, mem; | |
13458 | int offset; | |
13459 | ||
13460 | offset = info->altivec_save_offset + sp_offset | |
13461 | + 16 * (i - info->first_altivec_reg_save); | |
13462 | ||
13463 | savereg = gen_rtx_REG (V4SImode, i); | |
13464 | ||
13465 | areg = gen_rtx_REG (Pmode, 0); | |
13466 | emit_move_insn (areg, GEN_INT (offset)); | |
13467 | ||
13468 | /* AltiVec addressing mode is [reg+reg]. */ | |
13469 | mem = gen_rtx_MEM (V4SImode, | |
13470 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
f676971a | 13471 | |
9aa86737 AH |
13472 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
13473 | ||
13474 | insn = emit_move_insn (mem, savereg); | |
13475 | ||
5c242421 SB |
13476 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
13477 | areg, GEN_INT (offset)); | |
9aa86737 AH |
13478 | } |
13479 | } | |
13480 | ||
13481 | /* VRSAVE is a bit vector representing which AltiVec registers | |
13482 | are used. The OS uses this to determine which vector | |
13483 | registers to save on a context switch. We need to save | |
13484 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
13485 | used in this function, and do the corresponding magic in the | |
13486 | epilogue. */ | |
13487 | ||
4d774ff8 | 13488 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
bcb604b6 | 13489 | && info->vrsave_mask != 0) |
9aa86737 | 13490 | { |
a004eb82 | 13491 | rtx reg, mem, vrsave; |
9aa86737 AH |
13492 | int offset; |
13493 | ||
eab97e44 AM |
13494 | /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12 |
13495 | as frame_reg_rtx and r11 as the static chain pointer for | |
13496 | nested functions. */ | |
13497 | reg = gen_rtx_REG (SImode, 0); | |
a004eb82 | 13498 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
13499 | if (TARGET_MACHO) |
13500 | emit_insn (gen_get_vrsave_internal (reg)); | |
13501 | else | |
13502 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 | 13503 | |
bcb604b6 FJ |
13504 | if (!WORLD_SAVE_P (info)) |
13505 | { | |
13506 | /* Save VRSAVE. */ | |
13507 | offset = info->vrsave_save_offset + sp_offset; | |
13508 | mem | |
13509 | = gen_rtx_MEM (SImode, | |
13510 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
13511 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13512 | insn = emit_move_insn (mem, reg); | |
13513 | } | |
9aa86737 AH |
13514 | |
13515 | /* Include the registers in the mask. */ | |
13516 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
13517 | ||
13518 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
13519 | } | |
13520 | ||
9ebbca7d | 13521 | /* If we use the link register, get it into r0. */ |
f57fe068 | 13522 | if (!WORLD_SAVE_P (info) && info->lr_save_p) |
f8a57be8 GK |
13523 | { |
13524 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
13525 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
13526 | RTX_FRAME_RELATED_P (insn) = 1; | |
13527 | } | |
9ebbca7d GK |
13528 | |
13529 | /* If we need to save CR, put it into r12. */ | |
f57fe068 | 13530 | if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) |
9ebbca7d | 13531 | { |
f8a57be8 | 13532 | rtx set; |
f676971a | 13533 | |
9ebbca7d | 13534 | cr_save_rtx = gen_rtx_REG (SImode, 12); |
f8a57be8 GK |
13535 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
13536 | RTX_FRAME_RELATED_P (insn) = 1; | |
13537 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
13538 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. | |
13539 | But that's OK. All we have to do is specify that _one_ condition | |
13540 | code register is saved in this stack slot. The thrower's epilogue | |
13541 | will then restore all the call-saved registers. | |
13542 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
13543 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, | |
13544 | gen_rtx_REG (SImode, CR2_REGNO)); | |
13545 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13546 | set, | |
13547 | REG_NOTES (insn)); | |
9ebbca7d GK |
13548 | } |
13549 | ||
a4f6c312 SS |
13550 | /* Do any required saving of fpr's. If only one or two to save, do |
13551 | it ourselves. Otherwise, call function. */ | |
f57fe068 | 13552 | if (!WORLD_SAVE_P (info) && saving_FPRs_inline) |
9ebbca7d GK |
13553 | { |
13554 | int i; | |
13555 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 13556 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d | 13557 | && ! call_used_regs[info->first_fp_reg_save+i])) |
89e7058f AH |
13558 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
13559 | info->first_fp_reg_save + i, | |
13560 | info->fp_save_offset + sp_offset + 8 * i, | |
13561 | info->total_size); | |
9ebbca7d | 13562 | } |
f57fe068 | 13563 | else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64) |
9ebbca7d GK |
13564 | { |
13565 | int i; | |
13566 | char rname[30]; | |
520a57c8 | 13567 | const char *alloc_rname; |
9ebbca7d GK |
13568 | rtvec p; |
13569 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
f676971a EC |
13570 | |
13571 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
13572 | gen_rtx_REG (Pmode, | |
9ebbca7d GK |
13573 | LINK_REGISTER_REGNUM)); |
13574 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
13575 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 13576 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
13577 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
13578 | gen_rtx_SYMBOL_REF (Pmode, | |
13579 | alloc_rname)); | |
13580 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
13581 | { | |
13582 | rtx addr, reg, mem; | |
13583 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
13584 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a | 13585 | GEN_INT (info->fp_save_offset |
9ebbca7d GK |
13586 | + sp_offset + 8*i)); |
13587 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 13588 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13589 | |
13590 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
13591 | } | |
13592 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 13593 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d GK |
13594 | NULL_RTX, NULL_RTX); |
13595 | } | |
b6c9286a | 13596 | |
9ebbca7d GK |
13597 | /* Save GPRs. This is done as a PARALLEL if we are using |
13598 | the store-multiple instructions. */ | |
f57fe068 | 13599 | if (!WORLD_SAVE_P (info) && using_store_multiple) |
b6c9286a | 13600 | { |
308c142a | 13601 | rtvec p; |
9ebbca7d GK |
13602 | int i; |
13603 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
13604 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
13605 | { | |
13606 | rtx addr, reg, mem; | |
13607 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
f676971a EC |
13608 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13609 | GEN_INT (info->gp_save_offset | |
13610 | + sp_offset | |
9ebbca7d GK |
13611 | + reg_size * i)); |
13612 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 13613 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13614 | |
13615 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
13616 | } | |
13617 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 13618 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d | 13619 | NULL_RTX, NULL_RTX); |
b6c9286a | 13620 | } |
f57fe068 | 13621 | else if (!WORLD_SAVE_P (info)) |
b6c9286a | 13622 | { |
9ebbca7d GK |
13623 | int i; |
13624 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6d0a8091 DJ |
13625 | if ((regs_ever_live[info->first_gp_reg_save + i] |
13626 | && (!call_used_regs[info->first_gp_reg_save + i] | |
13627 | || (i + info->first_gp_reg_save | |
b4db40bf JJ |
13628 | == RS6000_PIC_OFFSET_TABLE_REGNUM |
13629 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
6d0a8091 | 13630 | || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 13631 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 13632 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
13633 | { |
13634 | rtx addr, reg, mem; | |
13635 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
13636 | ||
c19de7aa | 13637 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
13638 | { |
13639 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
13640 | rtx b; | |
13641 | ||
13642 | if (!SPE_CONST_OFFSET_OK (offset)) | |
13643 | { | |
13644 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13645 | emit_move_insn (b, GEN_INT (offset)); | |
13646 | } | |
13647 | else | |
13648 | b = GEN_INT (offset); | |
13649 | ||
13650 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
13651 | mem = gen_rtx_MEM (V2SImode, addr); | |
13652 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13653 | insn = emit_move_insn (mem, reg); | |
13654 | ||
13655 | if (GET_CODE (b) == CONST_INT) | |
13656 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
13657 | NULL_RTX, NULL_RTX); | |
13658 | else | |
13659 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
13660 | b, GEN_INT (offset)); | |
13661 | } | |
13662 | else | |
13663 | { | |
f676971a EC |
13664 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13665 | GEN_INT (info->gp_save_offset | |
13666 | + sp_offset | |
a3170dc6 AH |
13667 | + reg_size * i)); |
13668 | mem = gen_rtx_MEM (reg_mode, addr); | |
13669 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13670 | ||
13671 | insn = emit_move_insn (mem, reg); | |
f676971a | 13672 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a3170dc6 AH |
13673 | NULL_RTX, NULL_RTX); |
13674 | } | |
13675 | } | |
9ebbca7d GK |
13676 | } |
13677 | ||
83720594 RH |
13678 | /* ??? There's no need to emit actual instructions here, but it's the |
13679 | easiest way to get the frame unwind information emitted. */ | |
f57fe068 | 13680 | if (!WORLD_SAVE_P (info) && current_function_calls_eh_return) |
83720594 | 13681 | { |
78e1b90d DE |
13682 | unsigned int i, regno; |
13683 | ||
fc4767bb JJ |
13684 | /* In AIX ABI we need to pretend we save r2 here. */ |
13685 | if (TARGET_AIX) | |
13686 | { | |
13687 | rtx addr, reg, mem; | |
13688 | ||
13689 | reg = gen_rtx_REG (reg_mode, 2); | |
13690 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13691 | GEN_INT (sp_offset + 5 * reg_size)); | |
13692 | mem = gen_rtx_MEM (reg_mode, addr); | |
13693 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13694 | ||
13695 | insn = emit_move_insn (mem, reg); | |
f676971a | 13696 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
fc4767bb JJ |
13697 | NULL_RTX, NULL_RTX); |
13698 | PATTERN (insn) = gen_blockage (); | |
13699 | } | |
13700 | ||
83720594 RH |
13701 | for (i = 0; ; ++i) |
13702 | { | |
83720594 RH |
13703 | regno = EH_RETURN_DATA_REGNO (i); |
13704 | if (regno == INVALID_REGNUM) | |
13705 | break; | |
13706 | ||
89e7058f AH |
13707 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
13708 | info->ehrd_offset + sp_offset | |
13709 | + reg_size * (int) i, | |
13710 | info->total_size); | |
83720594 RH |
13711 | } |
13712 | } | |
13713 | ||
9ebbca7d | 13714 | /* Save lr if we used it. */ |
f57fe068 | 13715 | if (!WORLD_SAVE_P (info) && info->lr_save_p) |
9ebbca7d GK |
13716 | { |
13717 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13718 | GEN_INT (info->lr_save_offset + sp_offset)); | |
13719 | rtx reg = gen_rtx_REG (Pmode, 0); | |
13720 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
13721 | /* This should not be of rs6000_sr_alias_set, because of | |
13722 | __builtin_return_address. */ | |
f676971a | 13723 | |
9ebbca7d | 13724 | insn = emit_move_insn (mem, reg); |
f676971a | 13725 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 13726 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
13727 | } |
13728 | ||
13729 | /* Save CR if we use any that must be preserved. */ | |
f57fe068 | 13730 | if (!WORLD_SAVE_P (info) && info->cr_save_p) |
9ebbca7d GK |
13731 | { |
13732 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13733 | GEN_INT (info->cr_save_offset + sp_offset)); | |
13734 | rtx mem = gen_rtx_MEM (SImode, addr); | |
f8a57be8 GK |
13735 | /* See the large comment above about why CR2_REGNO is used. */ |
13736 | rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); | |
ba4828e0 RK |
13737 | |
13738 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
13739 | |
13740 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
13741 | that it's free. */ | |
13742 | if (REGNO (frame_reg_rtx) == 12) | |
13743 | { | |
f8a57be8 GK |
13744 | rtx set; |
13745 | ||
9ebbca7d | 13746 | cr_save_rtx = gen_rtx_REG (SImode, 0); |
f8a57be8 GK |
13747 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
13748 | RTX_FRAME_RELATED_P (insn) = 1; | |
13749 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); | |
13750 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13751 | set, | |
13752 | REG_NOTES (insn)); | |
f676971a | 13753 | |
9ebbca7d GK |
13754 | } |
13755 | insn = emit_move_insn (mem, cr_save_rtx); | |
13756 | ||
f676971a | 13757 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 13758 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
13759 | } |
13760 | ||
f676971a | 13761 | /* Update stack and set back pointer unless this is V.4, |
9ebbca7d | 13762 | for which it was done previously. */ |
f57fe068 | 13763 | if (!WORLD_SAVE_P (info) && info->push_p |
fc4767bb | 13764 | && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) |
9ebbca7d GK |
13765 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
13766 | ||
13767 | /* Set frame pointer, if needed. */ | |
13768 | if (frame_pointer_needed) | |
13769 | { | |
f676971a | 13770 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
13771 | sp_reg_rtx); |
13772 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 13773 | } |
9878760c | 13774 | |
1db02437 | 13775 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 13776 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
7f970b70 AM |
13777 | || (DEFAULT_ABI == ABI_V4 |
13778 | && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT)) | |
1db02437 | 13779 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
c4ad648e AM |
13780 | { |
13781 | /* If emit_load_toc_table will use the link register, we need to save | |
13782 | it. We use R12 for this purpose because emit_load_toc_table | |
13783 | can use register 0. This allows us to use a plain 'blr' to return | |
13784 | from the procedure more often. */ | |
13785 | int save_LR_around_toc_setup = (TARGET_ELF | |
13786 | && DEFAULT_ABI != ABI_AIX | |
13787 | && flag_pic | |
13788 | && ! info->lr_save_p | |
13789 | && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); | |
13790 | if (save_LR_around_toc_setup) | |
13791 | { | |
13792 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f8a57be8 | 13793 | |
c4ad648e AM |
13794 | insn = emit_move_insn (frame_ptr_rtx, lr); |
13795 | rs6000_maybe_dead (insn); | |
13796 | RTX_FRAME_RELATED_P (insn) = 1; | |
f8a57be8 | 13797 | |
c4ad648e | 13798 | rs6000_emit_load_toc_table (TRUE); |
f8a57be8 | 13799 | |
c4ad648e AM |
13800 | insn = emit_move_insn (lr, frame_ptr_rtx); |
13801 | rs6000_maybe_dead (insn); | |
13802 | RTX_FRAME_RELATED_P (insn) = 1; | |
13803 | } | |
13804 | else | |
13805 | rs6000_emit_load_toc_table (TRUE); | |
13806 | } | |
ee890fe2 | 13807 | |
fcce224d | 13808 | #if TARGET_MACHO |
ee890fe2 SS |
13809 | if (DEFAULT_ABI == ABI_DARWIN |
13810 | && flag_pic && current_function_uses_pic_offset_table) | |
13811 | { | |
f8a57be8 | 13812 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
11abc112 | 13813 | rtx src = machopic_function_base_sym (); |
ee890fe2 | 13814 | |
6d0a8091 DJ |
13815 | /* Save and restore LR locally around this call (in R0). */ |
13816 | if (!info->lr_save_p) | |
13817 | rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr)); | |
13818 | ||
f8a57be8 | 13819 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); |
ee890fe2 | 13820 | |
f676971a | 13821 | insn = emit_move_insn (gen_rtx_REG (Pmode, |
f8a57be8 GK |
13822 | RS6000_PIC_OFFSET_TABLE_REGNUM), |
13823 | lr); | |
13824 | rs6000_maybe_dead (insn); | |
6d0a8091 DJ |
13825 | |
13826 | if (!info->lr_save_p) | |
13827 | rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0))); | |
ee890fe2 | 13828 | } |
fcce224d | 13829 | #endif |
9ebbca7d GK |
13830 | } |
13831 | ||
9ebbca7d | 13832 | /* Write function prologue. */ |
a4f6c312 | 13833 | |
08c148a8 | 13834 | static void |
f676971a | 13835 | rs6000_output_function_prologue (FILE *file, |
a2369ed3 | 13836 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9ebbca7d GK |
13837 | { |
13838 | rs6000_stack_t *info = rs6000_stack_info (); | |
13839 | ||
4697a36c MM |
13840 | if (TARGET_DEBUG_STACK) |
13841 | debug_stack_info (info); | |
9878760c | 13842 | |
a4f6c312 SS |
13843 | /* Write .extern for any function we will call to save and restore |
13844 | fp values. */ | |
13845 | if (info->first_fp_reg_save < 64 | |
13846 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 13847 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 13848 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
13849 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
13850 | RESTORE_FP_SUFFIX); | |
9878760c | 13851 | |
c764f757 RK |
13852 | /* Write .extern for AIX common mode routines, if needed. */ |
13853 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
13854 | { | |
f6709c70 JW |
13855 | fputs ("\t.extern __mulh\n", file); |
13856 | fputs ("\t.extern __mull\n", file); | |
13857 | fputs ("\t.extern __divss\n", file); | |
13858 | fputs ("\t.extern __divus\n", file); | |
13859 | fputs ("\t.extern __quoss\n", file); | |
13860 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
13861 | common_mode_defined = 1; |
13862 | } | |
9878760c | 13863 | |
9ebbca7d | 13864 | if (! HAVE_prologue) |
979721f8 | 13865 | { |
9ebbca7d | 13866 | start_sequence (); |
9dda4cc8 | 13867 | |
a4f6c312 SS |
13868 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
13869 | the "toplevel" insn chain. */ | |
2e040219 | 13870 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13871 | rs6000_emit_prologue (); |
2e040219 | 13872 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 13873 | |
a3c9585f | 13874 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
13875 | { |
13876 | rtx insn; | |
13877 | unsigned addr = 0; | |
13878 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
13879 | { | |
13880 | INSN_ADDRESSES_NEW (insn, addr); | |
13881 | addr += 4; | |
13882 | } | |
13883 | } | |
9dda4cc8 | 13884 | |
9ebbca7d | 13885 | if (TARGET_DEBUG_STACK) |
a4f6c312 | 13886 | debug_rtx_list (get_insns (), 100); |
c9d691e9 | 13887 | final (get_insns (), file, FALSE); |
9ebbca7d | 13888 | end_sequence (); |
979721f8 MM |
13889 | } |
13890 | ||
9ebbca7d GK |
13891 | rs6000_pic_labelno++; |
13892 | } | |
f676971a | 13893 | |
9ebbca7d | 13894 | /* Emit function epilogue as insns. |
9878760c | 13895 | |
9ebbca7d GK |
13896 | At present, dwarf2out_frame_debug_expr doesn't understand |
13897 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
13898 | anywhere in the epilogue. Most of the insns below would in any case | |
13899 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 13900 | |
9ebbca7d | 13901 | void |
a2369ed3 | 13902 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
13903 | { |
13904 | rs6000_stack_t *info; | |
13905 | int restoring_FPRs_inline; | |
13906 | int using_load_multiple; | |
13907 | int using_mfcr_multiple; | |
13908 | int use_backchain_to_restore_sp; | |
13909 | int sp_offset = 0; | |
13910 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
13911 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a | 13912 | enum machine_mode reg_mode = Pmode; |
327e5343 | 13913 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
13914 | int i; |
13915 | ||
c19de7aa AH |
13916 | info = rs6000_stack_info (); |
13917 | ||
13918 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
13919 | { |
13920 | reg_mode = V2SImode; | |
13921 | reg_size = 8; | |
13922 | } | |
13923 | ||
9ebbca7d | 13924 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
13925 | && (!TARGET_SPE_ABI |
13926 | || info->spe_64bit_regs_used == 0) | |
6d0a8091 DJ |
13927 | && info->first_gp_reg_save < 31 |
13928 | && no_global_regs_above (info->first_gp_reg_save)); | |
9ebbca7d | 13929 | restoring_FPRs_inline = (sibcall |
83720594 | 13930 | || current_function_calls_eh_return |
9ebbca7d GK |
13931 | || info->first_fp_reg_save == 64 |
13932 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
f676971a | 13933 | use_backchain_to_restore_sp = (frame_pointer_needed |
9ebbca7d GK |
13934 | || current_function_calls_alloca |
13935 | || info->total_size > 32767); | |
13936 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
13937 | || rs6000_cpu == PROCESSOR_PPC603 | |
13938 | || rs6000_cpu == PROCESSOR_PPC750 | |
13939 | || optimize_size); | |
13940 | ||
f57fe068 | 13941 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
13942 | { |
13943 | int i, j; | |
13944 | char rname[30]; | |
13945 | const char *alloc_rname; | |
13946 | rtvec p; | |
13947 | ||
13948 | /* eh_rest_world_r10 will return to the location saved in the LR | |
c4ad648e AM |
13949 | stack slot (which is not likely to be our caller.) |
13950 | Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8. | |
13951 | rest_world is similar, except any R10 parameter is ignored. | |
13952 | The exception-handling stuff that was here in 2.95 is no | |
13953 | longer necessary. */ | |
d62294f5 FJ |
13954 | |
13955 | p = rtvec_alloc (9 | |
13956 | + 1 | |
f676971a | 13957 | + 32 - info->first_gp_reg_save |
c4ad648e AM |
13958 | + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save |
13959 | + 63 + 1 - info->first_fp_reg_save); | |
d62294f5 | 13960 | |
c4ad648e AM |
13961 | strcpy (rname, ((current_function_calls_eh_return) ? |
13962 | "*eh_rest_world_r10" : "*rest_world")); | |
d62294f5 FJ |
13963 | alloc_rname = ggc_strdup (rname); |
13964 | ||
13965 | j = 0; | |
13966 | RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); | |
13967 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, | |
c4ad648e AM |
13968 | gen_rtx_REG (Pmode, |
13969 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 13970 | RTVEC_ELT (p, j++) |
c4ad648e | 13971 | = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname)); |
d62294f5 | 13972 | /* The instruction pattern requires a clobber here; |
c4ad648e | 13973 | it is shared with the restVEC helper. */ |
d62294f5 | 13974 | RTVEC_ELT (p, j++) |
c4ad648e | 13975 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11)); |
d62294f5 FJ |
13976 | |
13977 | { | |
c4ad648e AM |
13978 | /* CR register traditionally saved as CR2. */ |
13979 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
13980 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13981 | GEN_INT (info->cr_save_offset)); | |
13982 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13983 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13984 | ||
13985 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
d62294f5 FJ |
13986 | } |
13987 | ||
13988 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
c4ad648e AM |
13989 | { |
13990 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
13991 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13992 | GEN_INT (info->gp_save_offset | |
13993 | + reg_size * i)); | |
13994 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13995 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13996 | ||
13997 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
13998 | } | |
d62294f5 | 13999 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
14000 | { |
14001 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
14002 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14003 | GEN_INT (info->altivec_save_offset | |
14004 | + 16 * i)); | |
14005 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
14006 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14007 | ||
14008 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14009 | } | |
d62294f5 | 14010 | for (i = 0; info->first_fp_reg_save + i <= 63; i++) |
c4ad648e AM |
14011 | { |
14012 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
14013 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14014 | GEN_INT (info->fp_save_offset | |
14015 | + 8 * i)); | |
14016 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
14017 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14018 | ||
14019 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14020 | } | |
d62294f5 | 14021 | RTVEC_ELT (p, j++) |
c4ad648e | 14022 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0)); |
d62294f5 | 14023 | RTVEC_ELT (p, j++) |
c4ad648e | 14024 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12)); |
d62294f5 | 14025 | RTVEC_ELT (p, j++) |
c4ad648e | 14026 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7)); |
d62294f5 | 14027 | RTVEC_ELT (p, j++) |
c4ad648e | 14028 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8)); |
d62294f5 | 14029 | RTVEC_ELT (p, j++) |
c4ad648e | 14030 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10)); |
d62294f5 FJ |
14031 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
14032 | ||
14033 | return; | |
14034 | } | |
14035 | ||
9ebbca7d GK |
14036 | /* If we have a frame pointer, a call to alloca, or a large stack |
14037 | frame, restore the old stack pointer using the backchain. Otherwise, | |
14038 | we know what size to update it with. */ | |
14039 | if (use_backchain_to_restore_sp) | |
bacbde18 | 14040 | { |
9ebbca7d GK |
14041 | /* Under V.4, don't reset the stack pointer until after we're done |
14042 | loading the saved registers. */ | |
f607bc57 | 14043 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 14044 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 14045 | |
9ebbca7d GK |
14046 | emit_move_insn (frame_reg_rtx, |
14047 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
f676971a | 14048 | |
bacbde18 | 14049 | } |
9ebbca7d | 14050 | else if (info->push_p) |
85638c0d | 14051 | { |
fc4767bb JJ |
14052 | if (DEFAULT_ABI == ABI_V4 |
14053 | || current_function_calls_eh_return) | |
9ebbca7d GK |
14054 | sp_offset = info->total_size; |
14055 | else | |
14056 | { | |
14057 | emit_insn (TARGET_32BIT | |
14058 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
14059 | GEN_INT (info->total_size)) | |
14060 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
14061 | GEN_INT (info->total_size))); | |
14062 | } | |
85638c0d | 14063 | } |
f676971a | 14064 | |
9aa86737 AH |
14065 | /* Restore AltiVec registers if needed. */ |
14066 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
14067 | { | |
14068 | int i; | |
14069 | ||
14070 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
14071 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
14072 | { | |
14073 | rtx addr, areg, mem; | |
14074 | ||
14075 | areg = gen_rtx_REG (Pmode, 0); | |
14076 | emit_move_insn | |
14077 | (areg, GEN_INT (info->altivec_save_offset | |
14078 | + sp_offset | |
14079 | + 16 * (i - info->first_altivec_reg_save))); | |
14080 | ||
14081 | /* AltiVec addressing mode is [reg+reg]. */ | |
14082 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
14083 | mem = gen_rtx_MEM (V4SImode, addr); | |
14084 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14085 | ||
14086 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
14087 | } | |
14088 | } | |
14089 | ||
14090 | /* Restore VRSAVE if needed. */ | |
44688022 | 14091 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
4d774ff8 | 14092 | && info->vrsave_mask != 0) |
9aa86737 AH |
14093 | { |
14094 | rtx addr, mem, reg; | |
14095 | ||
14096 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14097 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
14098 | mem = gen_rtx_MEM (SImode, addr); | |
14099 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14100 | reg = gen_rtx_REG (SImode, 12); | |
14101 | emit_move_insn (reg, mem); | |
14102 | ||
14103 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
14104 | } | |
14105 | ||
9ebbca7d GK |
14106 | /* Get the old lr if we saved it. */ |
14107 | if (info->lr_save_p) | |
b6c9286a | 14108 | { |
a3170dc6 AH |
14109 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
14110 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
14111 | |
14112 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 14113 | |
9ebbca7d | 14114 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 14115 | } |
f676971a | 14116 | |
9ebbca7d GK |
14117 | /* Get the old cr if we saved it. */ |
14118 | if (info->cr_save_p) | |
14119 | { | |
14120 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14121 | GEN_INT (info->cr_save_offset + sp_offset)); | |
14122 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
14123 | |
14124 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 14125 | |
9ebbca7d GK |
14126 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
14127 | } | |
f676971a | 14128 | |
9ebbca7d | 14129 | /* Set LR here to try to overlap restores below. */ |
4697a36c | 14130 | if (info->lr_save_p) |
9ebbca7d GK |
14131 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
14132 | gen_rtx_REG (Pmode, 0)); | |
f676971a | 14133 | |
83720594 RH |
14134 | /* Load exception handler data registers, if needed. */ |
14135 | if (current_function_calls_eh_return) | |
14136 | { | |
78e1b90d DE |
14137 | unsigned int i, regno; |
14138 | ||
fc4767bb JJ |
14139 | if (TARGET_AIX) |
14140 | { | |
14141 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14142 | GEN_INT (sp_offset + 5 * reg_size)); | |
14143 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
14144 | ||
14145 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14146 | ||
14147 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
14148 | } | |
14149 | ||
83720594 RH |
14150 | for (i = 0; ; ++i) |
14151 | { | |
a3170dc6 | 14152 | rtx mem; |
83720594 RH |
14153 | |
14154 | regno = EH_RETURN_DATA_REGNO (i); | |
14155 | if (regno == INVALID_REGNUM) | |
14156 | break; | |
14157 | ||
a3170dc6 AH |
14158 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
14159 | info->ehrd_offset + sp_offset | |
14160 | + reg_size * (int) i); | |
ba4828e0 | 14161 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
14162 | |
14163 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
14164 | } | |
14165 | } | |
f676971a | 14166 | |
9ebbca7d GK |
14167 | /* Restore GPRs. This is done as a PARALLEL if we are using |
14168 | the load-multiple instructions. */ | |
14169 | if (using_load_multiple) | |
979721f8 | 14170 | { |
9ebbca7d GK |
14171 | rtvec p; |
14172 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
14173 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 14174 | { |
f676971a EC |
14175 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14176 | GEN_INT (info->gp_save_offset | |
14177 | + sp_offset | |
9ebbca7d GK |
14178 | + reg_size * i)); |
14179 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
14180 | |
14181 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d | 14182 | |
f676971a | 14183 | RTVEC_ELT (p, i) = |
9ebbca7d GK |
14184 | gen_rtx_SET (VOIDmode, |
14185 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
14186 | mem); | |
979721f8 | 14187 | } |
9ebbca7d | 14188 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 14189 | } |
9ebbca7d GK |
14190 | else |
14191 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6d0a8091 DJ |
14192 | if ((regs_ever_live[info->first_gp_reg_save + i] |
14193 | && (!call_used_regs[info->first_gp_reg_save + i] | |
14194 | || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM | |
b4db40bf | 14195 | && TARGET_TOC && TARGET_MINIMAL_TOC))) |
6d0a8091 | 14196 | || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 14197 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 14198 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d | 14199 | { |
f676971a EC |
14200 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14201 | GEN_INT (info->gp_save_offset | |
14202 | + sp_offset | |
9ebbca7d GK |
14203 | + reg_size * i)); |
14204 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 14205 | |
a3170dc6 | 14206 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 14207 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
14208 | { |
14209 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
14210 | rtx b; | |
14211 | ||
14212 | if (!SPE_CONST_OFFSET_OK (offset)) | |
14213 | { | |
14214 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
14215 | emit_move_insn (b, GEN_INT (offset)); | |
14216 | } | |
14217 | else | |
14218 | b = GEN_INT (offset); | |
14219 | ||
14220 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
14221 | mem = gen_rtx_MEM (V2SImode, addr); | |
14222 | } | |
14223 | ||
ba4828e0 | 14224 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 14225 | |
f676971a | 14226 | emit_move_insn (gen_rtx_REG (reg_mode, |
a3170dc6 | 14227 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 14228 | } |
9878760c | 14229 | |
9ebbca7d GK |
14230 | /* Restore fpr's if we need to do it without calling a function. */ |
14231 | if (restoring_FPRs_inline) | |
14232 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 14233 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d GK |
14234 | && ! call_used_regs[info->first_fp_reg_save+i])) |
14235 | { | |
14236 | rtx addr, mem; | |
14237 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a EC |
14238 | GEN_INT (info->fp_save_offset |
14239 | + sp_offset | |
a4f6c312 | 14240 | + 8 * i)); |
9ebbca7d | 14241 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 14242 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 14243 | |
f676971a | 14244 | emit_move_insn (gen_rtx_REG (DFmode, |
9ebbca7d GK |
14245 | info->first_fp_reg_save + i), |
14246 | mem); | |
14247 | } | |
8d30c4ee | 14248 | |
9ebbca7d GK |
14249 | /* If we saved cr, restore it here. Just those that were used. */ |
14250 | if (info->cr_save_p) | |
979721f8 | 14251 | { |
9ebbca7d | 14252 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 14253 | int count = 0; |
f676971a | 14254 | |
9ebbca7d | 14255 | if (using_mfcr_multiple) |
979721f8 | 14256 | { |
9ebbca7d GK |
14257 | for (i = 0; i < 8; i++) |
14258 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 14259 | count++; |
37409796 | 14260 | gcc_assert (count); |
e35b9579 GK |
14261 | } |
14262 | ||
14263 | if (using_mfcr_multiple && count > 1) | |
14264 | { | |
14265 | rtvec p; | |
14266 | int ndx; | |
f676971a | 14267 | |
e35b9579 | 14268 | p = rtvec_alloc (count); |
9ebbca7d | 14269 | |
e35b9579 | 14270 | ndx = 0; |
9ebbca7d GK |
14271 | for (i = 0; i < 8; i++) |
14272 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
14273 | { | |
14274 | rtvec r = rtvec_alloc (2); | |
14275 | RTVEC_ELT (r, 0) = r12_rtx; | |
14276 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 14277 | RTVEC_ELT (p, ndx) = |
f676971a | 14278 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 14279 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 14280 | ndx++; |
9ebbca7d GK |
14281 | } |
14282 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
37409796 | 14283 | gcc_assert (ndx == count); |
979721f8 MM |
14284 | } |
14285 | else | |
9ebbca7d GK |
14286 | for (i = 0; i < 8; i++) |
14287 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 14288 | { |
f676971a | 14289 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
9ebbca7d GK |
14290 | CR0_REGNO+i), |
14291 | r12_rtx)); | |
979721f8 | 14292 | } |
979721f8 MM |
14293 | } |
14294 | ||
9ebbca7d GK |
14295 | /* If this is V.4, unwind the stack pointer after all of the loads |
14296 | have been done. We need to emit a block here so that sched | |
14297 | doesn't decide to move the sp change before the register restores | |
14298 | (which may not have any obvious dependency on the stack). This | |
14299 | doesn't hurt performance, because there is no scheduling that can | |
14300 | be done after this point. */ | |
fc4767bb JJ |
14301 | if (DEFAULT_ABI == ABI_V4 |
14302 | || current_function_calls_eh_return) | |
b6c9286a | 14303 | { |
9ebbca7d | 14304 | if (frame_reg_rtx != sp_reg_rtx) |
c4ad648e | 14305 | rs6000_emit_stack_tie (); |
b6c9286a | 14306 | |
9ebbca7d | 14307 | if (use_backchain_to_restore_sp) |
b6c9286a | 14308 | { |
9ebbca7d | 14309 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 14310 | } |
9ebbca7d | 14311 | else if (sp_offset != 0) |
13f1623b | 14312 | { |
5b71a4e7 | 14313 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
14314 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
14315 | GEN_INT (sp_offset)) | |
14316 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
14317 | GEN_INT (sp_offset))); | |
13f1623b | 14318 | } |
9ebbca7d | 14319 | } |
b6c9286a | 14320 | |
83720594 RH |
14321 | if (current_function_calls_eh_return) |
14322 | { | |
14323 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 14324 | emit_insn (TARGET_32BIT |
83720594 RH |
14325 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
14326 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
14327 | } | |
14328 | ||
9ebbca7d GK |
14329 | if (!sibcall) |
14330 | { | |
14331 | rtvec p; | |
14332 | if (! restoring_FPRs_inline) | |
14333 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
14334 | else | |
14335 | p = rtvec_alloc (2); | |
b6c9286a | 14336 | |
e35b9579 | 14337 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
f676971a EC |
14338 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
14339 | gen_rtx_REG (Pmode, | |
9ebbca7d | 14340 | LINK_REGISTER_REGNUM)); |
9ebbca7d GK |
14341 | |
14342 | /* If we have to restore more than two FP registers, branch to the | |
14343 | restore function. It will return to our caller. */ | |
14344 | if (! restoring_FPRs_inline) | |
14345 | { | |
14346 | int i; | |
14347 | char rname[30]; | |
520a57c8 | 14348 | const char *alloc_rname; |
979721f8 | 14349 | |
f676971a | 14350 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
9ebbca7d | 14351 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); |
a8a05998 | 14352 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
14353 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
14354 | gen_rtx_SYMBOL_REF (Pmode, | |
14355 | alloc_rname)); | |
b6c9286a | 14356 | |
9ebbca7d GK |
14357 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
14358 | { | |
14359 | rtx addr, mem; | |
14360 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
14361 | GEN_INT (info->fp_save_offset + 8*i)); | |
14362 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 14363 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 14364 | |
f676971a | 14365 | RTVEC_ELT (p, i+3) = |
9ebbca7d GK |
14366 | gen_rtx_SET (VOIDmode, |
14367 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
14368 | mem); | |
b6c9286a MM |
14369 | } |
14370 | } | |
f676971a | 14371 | |
9ebbca7d | 14372 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
3daf36a4 | 14373 | } |
9878760c RK |
14374 | } |
14375 | ||
14376 | /* Write function epilogue. */ | |
14377 | ||
08c148a8 | 14378 | static void |
f676971a | 14379 | rs6000_output_function_epilogue (FILE *file, |
a2369ed3 | 14380 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9878760c | 14381 | { |
4697a36c | 14382 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 14383 | |
9ebbca7d | 14384 | if (! HAVE_epilogue) |
9878760c | 14385 | { |
9ebbca7d GK |
14386 | rtx insn = get_last_insn (); |
14387 | /* If the last insn was a BARRIER, we don't have to write anything except | |
14388 | the trace table. */ | |
14389 | if (GET_CODE (insn) == NOTE) | |
14390 | insn = prev_nonnote_insn (insn); | |
14391 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 14392 | { |
9ebbca7d GK |
14393 | /* This is slightly ugly, but at least we don't have two |
14394 | copies of the epilogue-emitting code. */ | |
14395 | start_sequence (); | |
14396 | ||
14397 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
14398 | and end of the "toplevel" insn chain. */ | |
2e040219 | 14399 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 14400 | rs6000_emit_epilogue (FALSE); |
2e040219 | 14401 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 14402 | |
a3c9585f | 14403 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
14404 | { |
14405 | rtx insn; | |
14406 | unsigned addr = 0; | |
14407 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
14408 | { | |
14409 | INSN_ADDRESSES_NEW (insn, addr); | |
14410 | addr += 4; | |
14411 | } | |
14412 | } | |
14413 | ||
9ebbca7d | 14414 | if (TARGET_DEBUG_STACK) |
a4f6c312 | 14415 | debug_rtx_list (get_insns (), 100); |
c9d691e9 | 14416 | final (get_insns (), file, FALSE); |
9ebbca7d | 14417 | end_sequence (); |
4697a36c | 14418 | } |
9878760c | 14419 | } |
b4ac57ab | 14420 | |
efdba735 SH |
14421 | #if TARGET_MACHO |
14422 | macho_branch_islands (); | |
0e5da0be GK |
14423 | /* Mach-O doesn't support labels at the end of objects, so if |
14424 | it looks like we might want one, insert a NOP. */ | |
14425 | { | |
14426 | rtx insn = get_last_insn (); | |
14427 | while (insn | |
14428 | && NOTE_P (insn) | |
14429 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) | |
14430 | insn = PREV_INSN (insn); | |
f676971a EC |
14431 | if (insn |
14432 | && (LABEL_P (insn) | |
0e5da0be GK |
14433 | || (NOTE_P (insn) |
14434 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) | |
14435 | fputs ("\tnop\n", file); | |
14436 | } | |
14437 | #endif | |
14438 | ||
9b30bae2 | 14439 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
14440 | on its format. |
14441 | ||
14442 | We don't output a traceback table if -finhibit-size-directive was | |
14443 | used. The documentation for -finhibit-size-directive reads | |
14444 | ``don't output a @code{.size} assembler directive, or anything | |
14445 | else that would cause trouble if the function is split in the | |
14446 | middle, and the two halves are placed at locations far apart in | |
14447 | memory.'' The traceback table has this property, since it | |
14448 | includes the offset from the start of the function to the | |
4d30c363 MM |
14449 | traceback table itself. |
14450 | ||
14451 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 14452 | different traceback table. */ |
57ac7be9 AM |
14453 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
14454 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 14455 | { |
69c75916 | 14456 | const char *fname = NULL; |
3ac88239 | 14457 | const char *language_string = lang_hooks.name; |
6041bf2f | 14458 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 14459 | int i; |
57ac7be9 AM |
14460 | int optional_tbtab; |
14461 | ||
14462 | if (rs6000_traceback == traceback_full) | |
14463 | optional_tbtab = 1; | |
14464 | else if (rs6000_traceback == traceback_part) | |
14465 | optional_tbtab = 0; | |
14466 | else | |
14467 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 14468 | |
69c75916 AM |
14469 | if (optional_tbtab) |
14470 | { | |
14471 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
14472 | while (*fname == '.') /* V.4 encodes . in the name */ | |
14473 | fname++; | |
14474 | ||
14475 | /* Need label immediately before tbtab, so we can compute | |
14476 | its offset from the function start. */ | |
14477 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
14478 | ASM_OUTPUT_LABEL (file, fname); | |
14479 | } | |
314fc5a9 ILT |
14480 | |
14481 | /* The .tbtab pseudo-op can only be used for the first eight | |
14482 | expressions, since it can't handle the possibly variable | |
14483 | length fields that follow. However, if you omit the optional | |
14484 | fields, the assembler outputs zeros for all optional fields | |
14485 | anyways, giving each variable length field is minimum length | |
14486 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
14487 | pseudo-op at all. */ | |
14488 | ||
14489 | /* An all-zero word flags the start of the tbtab, for debuggers | |
14490 | that have to find it by searching forward from the entry | |
14491 | point or from the current pc. */ | |
19d2d16f | 14492 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
14493 | |
14494 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 14495 | fputs ("\t.byte 0,", file); |
314fc5a9 | 14496 | |
5fc921c1 DE |
14497 | /* Language type. Unfortunately, there does not seem to be any |
14498 | official way to discover the language being compiled, so we | |
14499 | use language_string. | |
14500 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
14501 | Java is 13. Objective-C is 14. */ | |
14502 | if (! strcmp (language_string, "GNU C")) | |
314fc5a9 | 14503 | i = 0; |
6de9cd9a DN |
14504 | else if (! strcmp (language_string, "GNU F77") |
14505 | || ! strcmp (language_string, "GNU F95")) | |
314fc5a9 | 14506 | i = 1; |
8b83775b | 14507 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 14508 | i = 2; |
5fc921c1 DE |
14509 | else if (! strcmp (language_string, "GNU Ada")) |
14510 | i = 3; | |
314fc5a9 ILT |
14511 | else if (! strcmp (language_string, "GNU C++")) |
14512 | i = 9; | |
9517ead8 AG |
14513 | else if (! strcmp (language_string, "GNU Java")) |
14514 | i = 13; | |
5fc921c1 DE |
14515 | else if (! strcmp (language_string, "GNU Objective-C")) |
14516 | i = 14; | |
314fc5a9 | 14517 | else |
37409796 | 14518 | gcc_unreachable (); |
314fc5a9 ILT |
14519 | fprintf (file, "%d,", i); |
14520 | ||
14521 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
14522 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
14523 | from start of procedure stored in tbtab, internal function, function | |
14524 | has controlled storage, function has no toc, function uses fp, | |
14525 | function logs/aborts fp operations. */ | |
14526 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
14527 | fprintf (file, "%d,", |
14528 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
14529 | |
14530 | /* 6 bitfields: function is interrupt handler, name present in | |
14531 | proc table, function calls alloca, on condition directives | |
14532 | (controls stack walks, 3 bits), saves condition reg, saves | |
14533 | link reg. */ | |
14534 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
14535 | set up as a frame pointer, even when there is no alloca call. */ | |
14536 | fprintf (file, "%d,", | |
6041bf2f DE |
14537 | ((optional_tbtab << 6) |
14538 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
14539 | | (info->cr_save_p << 1) | |
14540 | | (info->lr_save_p))); | |
314fc5a9 | 14541 | |
6041bf2f | 14542 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
14543 | (6 bits). */ |
14544 | fprintf (file, "%d,", | |
4697a36c | 14545 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
14546 | |
14547 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
14548 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
14549 | ||
6041bf2f DE |
14550 | if (optional_tbtab) |
14551 | { | |
14552 | /* Compute the parameter info from the function decl argument | |
14553 | list. */ | |
14554 | tree decl; | |
14555 | int next_parm_info_bit = 31; | |
314fc5a9 | 14556 | |
6041bf2f DE |
14557 | for (decl = DECL_ARGUMENTS (current_function_decl); |
14558 | decl; decl = TREE_CHAIN (decl)) | |
14559 | { | |
14560 | rtx parameter = DECL_INCOMING_RTL (decl); | |
14561 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 14562 | |
6041bf2f DE |
14563 | if (GET_CODE (parameter) == REG) |
14564 | { | |
14565 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
14566 | { | |
14567 | int bits; | |
14568 | ||
14569 | float_parms++; | |
14570 | ||
37409796 NS |
14571 | switch (mode) |
14572 | { | |
14573 | case SFmode: | |
14574 | bits = 0x2; | |
14575 | break; | |
14576 | ||
14577 | case DFmode: | |
14578 | case TFmode: | |
14579 | bits = 0x3; | |
14580 | break; | |
14581 | ||
14582 | default: | |
14583 | gcc_unreachable (); | |
14584 | } | |
6041bf2f DE |
14585 | |
14586 | /* If only one bit will fit, don't or in this entry. */ | |
14587 | if (next_parm_info_bit > 0) | |
14588 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
14589 | next_parm_info_bit -= 2; | |
14590 | } | |
14591 | else | |
14592 | { | |
14593 | fixed_parms += ((GET_MODE_SIZE (mode) | |
14594 | + (UNITS_PER_WORD - 1)) | |
14595 | / UNITS_PER_WORD); | |
14596 | next_parm_info_bit -= 1; | |
14597 | } | |
14598 | } | |
14599 | } | |
14600 | } | |
314fc5a9 ILT |
14601 | |
14602 | /* Number of fixed point parameters. */ | |
14603 | /* This is actually the number of words of fixed point parameters; thus | |
14604 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
14605 | fprintf (file, "%d,", fixed_parms); | |
14606 | ||
14607 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
14608 | all on stack. */ | |
14609 | /* This is actually the number of fp registers that hold parameters; | |
14610 | and thus the maximum value is 13. */ | |
14611 | /* Set parameters on stack bit if parameters are not in their original | |
14612 | registers, regardless of whether they are on the stack? Xlc | |
14613 | seems to set the bit when not optimizing. */ | |
14614 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
14615 | ||
6041bf2f DE |
14616 | if (! optional_tbtab) |
14617 | return; | |
14618 | ||
314fc5a9 ILT |
14619 | /* Optional fields follow. Some are variable length. */ |
14620 | ||
14621 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
14622 | 11 double float. */ | |
14623 | /* There is an entry for each parameter in a register, in the order that | |
14624 | they occur in the parameter list. Any intervening arguments on the | |
14625 | stack are ignored. If the list overflows a long (max possible length | |
14626 | 34 bits) then completely leave off all elements that don't fit. */ | |
14627 | /* Only emit this long if there was at least one parameter. */ | |
14628 | if (fixed_parms || float_parms) | |
14629 | fprintf (file, "\t.long %d\n", parm_info); | |
14630 | ||
14631 | /* Offset from start of code to tb table. */ | |
19d2d16f | 14632 | fputs ("\t.long ", file); |
314fc5a9 | 14633 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
85b776df AM |
14634 | if (TARGET_AIX) |
14635 | RS6000_OUTPUT_BASENAME (file, fname); | |
14636 | else | |
14637 | assemble_name (file, fname); | |
14638 | putc ('-', file); | |
14639 | rs6000_output_function_entry (file, fname); | |
19d2d16f | 14640 | putc ('\n', file); |
314fc5a9 ILT |
14641 | |
14642 | /* Interrupt handler mask. */ | |
14643 | /* Omit this long, since we never set the interrupt handler bit | |
14644 | above. */ | |
14645 | ||
14646 | /* Number of CTL (controlled storage) anchors. */ | |
14647 | /* Omit this long, since the has_ctl bit is never set above. */ | |
14648 | ||
14649 | /* Displacement into stack of each CTL anchor. */ | |
14650 | /* Omit this list of longs, because there are no CTL anchors. */ | |
14651 | ||
14652 | /* Length of function name. */ | |
69c75916 AM |
14653 | if (*fname == '*') |
14654 | ++fname; | |
296b8152 | 14655 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
14656 | |
14657 | /* Function name. */ | |
14658 | assemble_string (fname, strlen (fname)); | |
14659 | ||
14660 | /* Register for alloca automatic storage; this is always reg 31. | |
14661 | Only emit this if the alloca bit was set above. */ | |
14662 | if (frame_pointer_needed) | |
19d2d16f | 14663 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
14664 | |
14665 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 14666 | } |
9878760c | 14667 | } |
17167fd8 | 14668 | \f |
a4f6c312 SS |
14669 | /* A C compound statement that outputs the assembler code for a thunk |
14670 | function, used to implement C++ virtual function calls with | |
14671 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
14672 | function, adjusting the implicit object parameter before handing | |
14673 | control off to the real function. | |
14674 | ||
14675 | First, emit code to add the integer DELTA to the location that | |
14676 | contains the incoming first argument. Assume that this argument | |
14677 | contains a pointer, and is the one used to pass the `this' pointer | |
14678 | in C++. This is the incoming argument *before* the function | |
14679 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
14680 | values of all other incoming arguments. | |
17167fd8 MM |
14681 | |
14682 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
14683 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
14684 | not touch the return address. Hence returning from FUNCTION will | |
14685 | return to whoever called the current `thunk'. | |
17167fd8 | 14686 | |
a4f6c312 SS |
14687 | The effect must be as if FUNCTION had been called directly with the |
14688 | adjusted first argument. This macro is responsible for emitting | |
14689 | all of the code for a thunk function; output_function_prologue() | |
14690 | and output_function_epilogue() are not invoked. | |
17167fd8 | 14691 | |
a4f6c312 SS |
14692 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
14693 | been extracted from it.) It might possibly be useful on some | |
14694 | targets, but probably not. | |
17167fd8 | 14695 | |
a4f6c312 SS |
14696 | If you do not define this macro, the target-independent code in the |
14697 | C++ frontend will generate a less efficient heavyweight thunk that | |
14698 | calls FUNCTION instead of jumping to it. The generic approach does | |
14699 | not support varargs. */ | |
17167fd8 | 14700 | |
3961e8fe | 14701 | static void |
f676971a EC |
14702 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
14703 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
a2369ed3 | 14704 | tree function) |
17167fd8 | 14705 | { |
5b71a4e7 | 14706 | rtx this, insn, funexp; |
17167fd8 | 14707 | |
5b71a4e7 | 14708 | reload_completed = 1; |
fe3ad572 | 14709 | epilogue_completed = 1; |
5b71a4e7 | 14710 | no_new_pseudos = 1; |
6429e3be | 14711 | reset_block_changes (); |
56a7189a | 14712 | |
5b71a4e7 | 14713 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 14714 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 14715 | |
5b71a4e7 DE |
14716 | /* Find the "this" pointer. If the function returns a structure, |
14717 | the structure return pointer is in r3. */ | |
61f71b34 | 14718 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
5b71a4e7 | 14719 | this = gen_rtx_REG (Pmode, 4); |
56a7189a | 14720 | else |
5b71a4e7 | 14721 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 14722 | |
5b71a4e7 DE |
14723 | /* Apply the constant offset, if required. */ |
14724 | if (delta) | |
14725 | { | |
14726 | rtx delta_rtx = GEN_INT (delta); | |
14727 | emit_insn (TARGET_32BIT | |
14728 | ? gen_addsi3 (this, this, delta_rtx) | |
14729 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
14730 | } |
14731 | ||
5b71a4e7 DE |
14732 | /* Apply the offset from the vtable, if required. */ |
14733 | if (vcall_offset) | |
17167fd8 | 14734 | { |
5b71a4e7 DE |
14735 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
14736 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 14737 | |
5b71a4e7 | 14738 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
eeff9307 JJ |
14739 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
14740 | { | |
14741 | emit_insn (TARGET_32BIT | |
14742 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
14743 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
14744 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
14745 | } | |
14746 | else | |
14747 | { | |
14748 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
14749 | ||
14750 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
14751 | } | |
5b71a4e7 DE |
14752 | emit_insn (TARGET_32BIT |
14753 | ? gen_addsi3 (this, this, tmp) | |
14754 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
14755 | } |
14756 | ||
5b71a4e7 DE |
14757 | /* Generate a tail call to the target function. */ |
14758 | if (!TREE_USED (function)) | |
14759 | { | |
14760 | assemble_external (function); | |
14761 | TREE_USED (function) = 1; | |
14762 | } | |
14763 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 14764 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
14765 | |
14766 | #if TARGET_MACHO | |
ab82a49f | 14767 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 14768 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 14769 | #endif |
5b71a4e7 DE |
14770 | |
14771 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
992d08b1 | 14772 | generate sibcall RTL explicitly. */ |
5b71a4e7 DE |
14773 | insn = emit_call_insn ( |
14774 | gen_rtx_PARALLEL (VOIDmode, | |
14775 | gen_rtvec (4, | |
14776 | gen_rtx_CALL (VOIDmode, | |
14777 | funexp, const0_rtx), | |
14778 | gen_rtx_USE (VOIDmode, const0_rtx), | |
14779 | gen_rtx_USE (VOIDmode, | |
14780 | gen_rtx_REG (SImode, | |
14781 | LINK_REGISTER_REGNUM)), | |
14782 | gen_rtx_RETURN (VOIDmode)))); | |
14783 | SIBLING_CALL_P (insn) = 1; | |
14784 | emit_barrier (); | |
14785 | ||
14786 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
14787 | There's not really enough bulk here to make other passes such as | |
14788 | instruction scheduling worth while. Note that use_thunk calls | |
14789 | assemble_start_function and assemble_end_function. */ | |
14790 | insn = get_insns (); | |
a2855205 | 14791 | insn_locators_initialize (); |
5b71a4e7 DE |
14792 | shorten_branches (insn); |
14793 | final_start_function (insn, file, 1); | |
c9d691e9 | 14794 | final (insn, file, 1); |
5b71a4e7 DE |
14795 | final_end_function (); |
14796 | ||
14797 | reload_completed = 0; | |
fe3ad572 | 14798 | epilogue_completed = 0; |
5b71a4e7 | 14799 | no_new_pseudos = 0; |
9ebbca7d | 14800 | } |
9ebbca7d GK |
14801 | \f |
14802 | /* A quick summary of the various types of 'constant-pool tables' | |
14803 | under PowerPC: | |
14804 | ||
f676971a | 14805 | Target Flags Name One table per |
9ebbca7d GK |
14806 | AIX (none) AIX TOC object file |
14807 | AIX -mfull-toc AIX TOC object file | |
14808 | AIX -mminimal-toc AIX minimal TOC translation unit | |
14809 | SVR4/EABI (none) SVR4 SDATA object file | |
14810 | SVR4/EABI -fpic SVR4 pic object file | |
14811 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
14812 | SVR4/EABI -mrelocatable EABI TOC function | |
14813 | SVR4/EABI -maix AIX TOC object file | |
f676971a | 14814 | SVR4/EABI -maix -mminimal-toc |
9ebbca7d GK |
14815 | AIX minimal TOC translation unit |
14816 | ||
14817 | Name Reg. Set by entries contains: | |
14818 | made by addrs? fp? sum? | |
14819 | ||
14820 | AIX TOC 2 crt0 as Y option option | |
14821 | AIX minimal TOC 30 prolog gcc Y Y option | |
14822 | SVR4 SDATA 13 crt0 gcc N Y N | |
14823 | SVR4 pic 30 prolog ld Y not yet N | |
14824 | SVR4 PIC 30 prolog gcc Y option option | |
14825 | EABI TOC 30 prolog gcc Y option option | |
14826 | ||
14827 | */ | |
14828 | ||
9ebbca7d GK |
14829 | /* Hash functions for the hash table. */ |
14830 | ||
14831 | static unsigned | |
a2369ed3 | 14832 | rs6000_hash_constant (rtx k) |
9ebbca7d | 14833 | { |
46b33600 RH |
14834 | enum rtx_code code = GET_CODE (k); |
14835 | enum machine_mode mode = GET_MODE (k); | |
14836 | unsigned result = (code << 3) ^ mode; | |
14837 | const char *format; | |
14838 | int flen, fidx; | |
f676971a | 14839 | |
46b33600 RH |
14840 | format = GET_RTX_FORMAT (code); |
14841 | flen = strlen (format); | |
14842 | fidx = 0; | |
9ebbca7d | 14843 | |
46b33600 RH |
14844 | switch (code) |
14845 | { | |
14846 | case LABEL_REF: | |
14847 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
14848 | ||
14849 | case CONST_DOUBLE: | |
14850 | if (mode != VOIDmode) | |
14851 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
14852 | flen = 2; | |
14853 | break; | |
14854 | ||
14855 | case CODE_LABEL: | |
14856 | fidx = 3; | |
14857 | break; | |
14858 | ||
14859 | default: | |
14860 | break; | |
14861 | } | |
9ebbca7d GK |
14862 | |
14863 | for (; fidx < flen; fidx++) | |
14864 | switch (format[fidx]) | |
14865 | { | |
14866 | case 's': | |
14867 | { | |
14868 | unsigned i, len; | |
14869 | const char *str = XSTR (k, fidx); | |
14870 | len = strlen (str); | |
14871 | result = result * 613 + len; | |
14872 | for (i = 0; i < len; i++) | |
14873 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
14874 | break; |
14875 | } | |
9ebbca7d GK |
14876 | case 'u': |
14877 | case 'e': | |
14878 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
14879 | break; | |
14880 | case 'i': | |
14881 | case 'n': | |
14882 | result = result * 613 + (unsigned) XINT (k, fidx); | |
14883 | break; | |
14884 | case 'w': | |
14885 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
14886 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
14887 | else | |
14888 | { | |
14889 | size_t i; | |
9390387d | 14890 | for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++) |
9ebbca7d GK |
14891 | result = result * 613 + (unsigned) (XWINT (k, fidx) |
14892 | >> CHAR_BIT * i); | |
14893 | } | |
14894 | break; | |
09501938 DE |
14895 | case '0': |
14896 | break; | |
9ebbca7d | 14897 | default: |
37409796 | 14898 | gcc_unreachable (); |
9ebbca7d | 14899 | } |
46b33600 | 14900 | |
9ebbca7d GK |
14901 | return result; |
14902 | } | |
14903 | ||
14904 | static unsigned | |
a2369ed3 | 14905 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 14906 | { |
f676971a | 14907 | const struct toc_hash_struct *thc = |
a9098fd0 GK |
14908 | (const struct toc_hash_struct *) hash_entry; |
14909 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
14910 | } |
14911 | ||
14912 | /* Compare H1 and H2 for equivalence. */ | |
14913 | ||
14914 | static int | |
a2369ed3 | 14915 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
14916 | { |
14917 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
14918 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
14919 | ||
a9098fd0 GK |
14920 | if (((const struct toc_hash_struct *) h1)->key_mode |
14921 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
14922 | return 0; | |
14923 | ||
5692c7bc | 14924 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
14925 | } |
14926 | ||
28e510bd MM |
14927 | /* These are the names given by the C++ front-end to vtables, and |
14928 | vtable-like objects. Ideally, this logic should not be here; | |
14929 | instead, there should be some programmatic way of inquiring as | |
14930 | to whether or not an object is a vtable. */ | |
14931 | ||
14932 | #define VTABLE_NAME_P(NAME) \ | |
9390387d | 14933 | (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \ |
28e510bd MM |
14934 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ |
14935 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
26be75db | 14936 | || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ |
f676971a | 14937 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) |
28e510bd MM |
14938 | |
14939 | void | |
a2369ed3 | 14940 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
14941 | { |
14942 | /* Currently C++ toc references to vtables can be emitted before it | |
14943 | is decided whether the vtable is public or private. If this is | |
14944 | the case, then the linker will eventually complain that there is | |
f676971a | 14945 | a reference to an unknown section. Thus, for vtables only, |
28e510bd MM |
14946 | we emit the TOC reference to reference the symbol and not the |
14947 | section. */ | |
14948 | const char *name = XSTR (x, 0); | |
54ee9799 | 14949 | |
f676971a | 14950 | if (VTABLE_NAME_P (name)) |
54ee9799 DE |
14951 | { |
14952 | RS6000_OUTPUT_BASENAME (file, name); | |
14953 | } | |
14954 | else | |
14955 | assemble_name (file, name); | |
28e510bd MM |
14956 | } |
14957 | ||
a4f6c312 SS |
14958 | /* Output a TOC entry. We derive the entry name from what is being |
14959 | written. */ | |
9878760c RK |
14960 | |
14961 | void | |
a2369ed3 | 14962 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
14963 | { |
14964 | char buf[256]; | |
3cce094d | 14965 | const char *name = buf; |
ec940faa | 14966 | const char *real_name; |
9878760c RK |
14967 | rtx base = x; |
14968 | int offset = 0; | |
14969 | ||
37409796 | 14970 | gcc_assert (!TARGET_NO_TOC); |
4697a36c | 14971 | |
9ebbca7d GK |
14972 | /* When the linker won't eliminate them, don't output duplicate |
14973 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
14974 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
14975 | CODE_LABELs. */ | |
14976 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
14977 | { |
14978 | struct toc_hash_struct *h; | |
14979 | void * * found; | |
f676971a | 14980 | |
17211ab5 | 14981 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
c4ad648e | 14982 | time because GGC is not initialized at that point. */ |
17211ab5 | 14983 | if (toc_hash_table == NULL) |
f676971a | 14984 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, |
17211ab5 GK |
14985 | toc_hash_eq, NULL); |
14986 | ||
9ebbca7d GK |
14987 | h = ggc_alloc (sizeof (*h)); |
14988 | h->key = x; | |
a9098fd0 | 14989 | h->key_mode = mode; |
9ebbca7d | 14990 | h->labelno = labelno; |
f676971a | 14991 | |
9ebbca7d GK |
14992 | found = htab_find_slot (toc_hash_table, h, 1); |
14993 | if (*found == NULL) | |
14994 | *found = h; | |
f676971a | 14995 | else /* This is indeed a duplicate. |
9ebbca7d GK |
14996 | Set this label equal to that label. */ |
14997 | { | |
14998 | fputs ("\t.set ", file); | |
14999 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
15000 | fprintf (file, "%d,", labelno); | |
15001 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
f676971a | 15002 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) |
9ebbca7d GK |
15003 | found)->labelno)); |
15004 | return; | |
15005 | } | |
15006 | } | |
15007 | ||
15008 | /* If we're going to put a double constant in the TOC, make sure it's | |
15009 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
15010 | if (GET_CODE (x) == CONST_DOUBLE |
15011 | && STRICT_ALIGNMENT | |
a9098fd0 | 15012 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
15013 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
15014 | ASM_OUTPUT_ALIGN (file, 3); | |
15015 | } | |
15016 | ||
4977bab6 | 15017 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 15018 | |
37c37a57 RK |
15019 | /* Handle FP constants specially. Note that if we have a minimal |
15020 | TOC, things we put here aren't actually in the TOC, so we can allow | |
15021 | FP constants. */ | |
fcce224d DE |
15022 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
15023 | { | |
15024 | REAL_VALUE_TYPE rv; | |
15025 | long k[4]; | |
15026 | ||
15027 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
15028 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
15029 | ||
15030 | if (TARGET_64BIT) | |
15031 | { | |
15032 | if (TARGET_MINIMAL_TOC) | |
15033 | fputs (DOUBLE_INT_ASM_OP, file); | |
15034 | else | |
15035 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
15036 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15037 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15038 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
15039 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15040 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15041 | return; | |
15042 | } | |
15043 | else | |
15044 | { | |
15045 | if (TARGET_MINIMAL_TOC) | |
15046 | fputs ("\t.long ", file); | |
15047 | else | |
15048 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
15049 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15050 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15051 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
15052 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15053 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15054 | return; | |
15055 | } | |
15056 | } | |
15057 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 15058 | { |
042259f2 DE |
15059 | REAL_VALUE_TYPE rv; |
15060 | long k[2]; | |
0adc764e | 15061 | |
042259f2 DE |
15062 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
15063 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 15064 | |
13ded975 DE |
15065 | if (TARGET_64BIT) |
15066 | { | |
15067 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15068 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 15069 | else |
2f0552b6 AM |
15070 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
15071 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
15072 | fprintf (file, "0x%lx%08lx\n", | |
15073 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
15074 | return; |
15075 | } | |
1875cc88 | 15076 | else |
13ded975 DE |
15077 | { |
15078 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15079 | fputs ("\t.long ", file); |
13ded975 | 15080 | else |
2f0552b6 AM |
15081 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
15082 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
15083 | fprintf (file, "0x%lx,0x%lx\n", | |
15084 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
15085 | return; |
15086 | } | |
9878760c | 15087 | } |
a9098fd0 | 15088 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 15089 | { |
042259f2 DE |
15090 | REAL_VALUE_TYPE rv; |
15091 | long l; | |
9878760c | 15092 | |
042259f2 DE |
15093 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
15094 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
15095 | ||
31bfaa0b DE |
15096 | if (TARGET_64BIT) |
15097 | { | |
15098 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15099 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 15100 | else |
2f0552b6 AM |
15101 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
15102 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
15103 | return; |
15104 | } | |
042259f2 | 15105 | else |
31bfaa0b DE |
15106 | { |
15107 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15108 | fputs ("\t.long ", file); |
31bfaa0b | 15109 | else |
2f0552b6 AM |
15110 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
15111 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
15112 | return; |
15113 | } | |
042259f2 | 15114 | } |
f176e826 | 15115 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 15116 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 15117 | { |
e2c953b6 | 15118 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
15119 | HOST_WIDE_INT high; |
15120 | ||
15121 | if (GET_CODE (x) == CONST_DOUBLE) | |
15122 | { | |
15123 | low = CONST_DOUBLE_LOW (x); | |
15124 | high = CONST_DOUBLE_HIGH (x); | |
15125 | } | |
15126 | else | |
15127 | #if HOST_BITS_PER_WIDE_INT == 32 | |
15128 | { | |
15129 | low = INTVAL (x); | |
0858c623 | 15130 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
15131 | } |
15132 | #else | |
15133 | { | |
c4ad648e AM |
15134 | low = INTVAL (x) & 0xffffffff; |
15135 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; | |
042259f2 DE |
15136 | } |
15137 | #endif | |
9878760c | 15138 | |
a9098fd0 GK |
15139 | /* TOC entries are always Pmode-sized, but since this |
15140 | is a bigendian machine then if we're putting smaller | |
15141 | integer constants in the TOC we have to pad them. | |
15142 | (This is still a win over putting the constants in | |
15143 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
15144 | to have both a TOC entry _and_ the actual constant.) |
15145 | ||
15146 | For a 32-bit target, CONST_INT values are loaded and shifted | |
15147 | entirely within `low' and can be stored in one TOC entry. */ | |
15148 | ||
37409796 NS |
15149 | /* It would be easy to make this work, but it doesn't now. */ |
15150 | gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode)); | |
02a4ec28 FS |
15151 | |
15152 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
15153 | { |
15154 | #if HOST_BITS_PER_WIDE_INT == 32 | |
15155 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
15156 | POINTER_SIZE, &low, &high, 0); | |
15157 | #else | |
15158 | low |= high << 32; | |
15159 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
15160 | high = (HOST_WIDE_INT) low >> 32; | |
15161 | low &= 0xffffffff; | |
15162 | #endif | |
15163 | } | |
a9098fd0 | 15164 | |
13ded975 DE |
15165 | if (TARGET_64BIT) |
15166 | { | |
15167 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15168 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 15169 | else |
2f0552b6 AM |
15170 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
15171 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
15172 | fprintf (file, "0x%lx%08lx\n", | |
15173 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
15174 | return; |
15175 | } | |
1875cc88 | 15176 | else |
13ded975 | 15177 | { |
02a4ec28 FS |
15178 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
15179 | { | |
15180 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15181 | fputs ("\t.long ", file); |
02a4ec28 | 15182 | else |
2bfcf297 | 15183 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
15184 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
15185 | fprintf (file, "0x%lx,0x%lx\n", | |
15186 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 15187 | } |
13ded975 | 15188 | else |
02a4ec28 FS |
15189 | { |
15190 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15191 | fputs ("\t.long ", file); |
02a4ec28 | 15192 | else |
2f0552b6 AM |
15193 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
15194 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 15195 | } |
13ded975 DE |
15196 | return; |
15197 | } | |
9878760c RK |
15198 | } |
15199 | ||
15200 | if (GET_CODE (x) == CONST) | |
15201 | { | |
37409796 | 15202 | gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS); |
2bfcf297 | 15203 | |
9878760c RK |
15204 | base = XEXP (XEXP (x, 0), 0); |
15205 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
15206 | } | |
f676971a | 15207 | |
37409796 NS |
15208 | switch (GET_CODE (base)) |
15209 | { | |
15210 | case SYMBOL_REF: | |
15211 | name = XSTR (base, 0); | |
15212 | break; | |
15213 | ||
15214 | case LABEL_REF: | |
15215 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", | |
15216 | CODE_LABEL_NUMBER (XEXP (base, 0))); | |
15217 | break; | |
15218 | ||
15219 | case CODE_LABEL: | |
15220 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
15221 | break; | |
15222 | ||
15223 | default: | |
15224 | gcc_unreachable (); | |
15225 | } | |
9878760c | 15226 | |
772c5265 | 15227 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 15228 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 15229 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
15230 | else |
15231 | { | |
b6c9286a | 15232 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 15233 | |
1875cc88 JW |
15234 | if (offset < 0) |
15235 | fprintf (file, ".N%d", - offset); | |
15236 | else if (offset) | |
15237 | fprintf (file, ".P%d", offset); | |
9878760c | 15238 | |
19d2d16f | 15239 | fputs ("[TC],", file); |
1875cc88 | 15240 | } |
581bc4de MM |
15241 | |
15242 | /* Currently C++ toc references to vtables can be emitted before it | |
15243 | is decided whether the vtable is public or private. If this is | |
15244 | the case, then the linker will eventually complain that there is | |
15245 | a TOC reference to an unknown section. Thus, for vtables only, | |
15246 | we emit the TOC reference to reference the symbol and not the | |
15247 | section. */ | |
28e510bd | 15248 | if (VTABLE_NAME_P (name)) |
581bc4de | 15249 | { |
54ee9799 | 15250 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
15251 | if (offset < 0) |
15252 | fprintf (file, "%d", offset); | |
15253 | else if (offset > 0) | |
15254 | fprintf (file, "+%d", offset); | |
15255 | } | |
15256 | else | |
15257 | output_addr_const (file, x); | |
19d2d16f | 15258 | putc ('\n', file); |
9878760c RK |
15259 | } |
15260 | \f | |
15261 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
15262 | starting at P to FILE. | |
15263 | ||
15264 | On the RS/6000, we have to do this using the .byte operation and | |
15265 | write out special characters outside the quoted string. | |
15266 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 15267 | so we must artificially break them up early. */ |
9878760c RK |
15268 | |
15269 | void | |
a2369ed3 | 15270 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
15271 | { |
15272 | char c; | |
15273 | int i, count_string; | |
d330fd93 KG |
15274 | const char *for_string = "\t.byte \""; |
15275 | const char *for_decimal = "\t.byte "; | |
15276 | const char *to_close = NULL; | |
9878760c RK |
15277 | |
15278 | count_string = 0; | |
15279 | for (i = 0; i < n; i++) | |
15280 | { | |
15281 | c = *p++; | |
15282 | if (c >= ' ' && c < 0177) | |
15283 | { | |
15284 | if (for_string) | |
15285 | fputs (for_string, file); | |
15286 | putc (c, file); | |
15287 | ||
15288 | /* Write two quotes to get one. */ | |
15289 | if (c == '"') | |
15290 | { | |
15291 | putc (c, file); | |
15292 | ++count_string; | |
15293 | } | |
15294 | ||
15295 | for_string = NULL; | |
15296 | for_decimal = "\"\n\t.byte "; | |
15297 | to_close = "\"\n"; | |
15298 | ++count_string; | |
15299 | ||
15300 | if (count_string >= 512) | |
15301 | { | |
15302 | fputs (to_close, file); | |
15303 | ||
15304 | for_string = "\t.byte \""; | |
15305 | for_decimal = "\t.byte "; | |
15306 | to_close = NULL; | |
15307 | count_string = 0; | |
15308 | } | |
15309 | } | |
15310 | else | |
15311 | { | |
15312 | if (for_decimal) | |
15313 | fputs (for_decimal, file); | |
15314 | fprintf (file, "%d", c); | |
15315 | ||
15316 | for_string = "\n\t.byte \""; | |
15317 | for_decimal = ", "; | |
15318 | to_close = "\n"; | |
15319 | count_string = 0; | |
15320 | } | |
15321 | } | |
15322 | ||
15323 | /* Now close the string if we have written one. Then end the line. */ | |
15324 | if (to_close) | |
9ebbca7d | 15325 | fputs (to_close, file); |
9878760c RK |
15326 | } |
15327 | \f | |
15328 | /* Generate a unique section name for FILENAME for a section type | |
15329 | represented by SECTION_DESC. Output goes into BUF. | |
15330 | ||
15331 | SECTION_DESC can be any string, as long as it is different for each | |
15332 | possible section type. | |
15333 | ||
15334 | We name the section in the same manner as xlc. The name begins with an | |
15335 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
15336 | names) with the last period replaced by the string SECTION_DESC. If |
15337 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
15338 | the name. */ | |
9878760c RK |
15339 | |
15340 | void | |
f676971a | 15341 | rs6000_gen_section_name (char **buf, const char *filename, |
c4ad648e | 15342 | const char *section_desc) |
9878760c | 15343 | { |
9ebbca7d | 15344 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
15345 | char *p; |
15346 | int len; | |
9878760c RK |
15347 | |
15348 | after_last_slash = filename; | |
15349 | for (q = filename; *q; q++) | |
11e5fe42 RK |
15350 | { |
15351 | if (*q == '/') | |
15352 | after_last_slash = q + 1; | |
15353 | else if (*q == '.') | |
15354 | last_period = q; | |
15355 | } | |
9878760c | 15356 | |
11e5fe42 | 15357 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 15358 | *buf = (char *) xmalloc (len); |
9878760c RK |
15359 | |
15360 | p = *buf; | |
15361 | *p++ = '_'; | |
15362 | ||
15363 | for (q = after_last_slash; *q; q++) | |
15364 | { | |
11e5fe42 | 15365 | if (q == last_period) |
c4ad648e | 15366 | { |
9878760c RK |
15367 | strcpy (p, section_desc); |
15368 | p += strlen (section_desc); | |
e3981aab | 15369 | break; |
c4ad648e | 15370 | } |
9878760c | 15371 | |
e9a780ec | 15372 | else if (ISALNUM (*q)) |
c4ad648e | 15373 | *p++ = *q; |
9878760c RK |
15374 | } |
15375 | ||
11e5fe42 | 15376 | if (last_period == 0) |
9878760c RK |
15377 | strcpy (p, section_desc); |
15378 | else | |
15379 | *p = '\0'; | |
15380 | } | |
e165f3f0 | 15381 | \f |
a4f6c312 | 15382 | /* Emit profile function. */ |
411707f4 | 15383 | |
411707f4 | 15384 | void |
a2369ed3 | 15385 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 15386 | { |
858081ad AH |
15387 | /* Non-standard profiling for kernels, which just saves LR then calls |
15388 | _mcount without worrying about arg saves. The idea is to change | |
15389 | the function prologue as little as possible as it isn't easy to | |
15390 | account for arg save/restore code added just for _mcount. */ | |
ffcfcb5f AM |
15391 | if (TARGET_PROFILE_KERNEL) |
15392 | return; | |
15393 | ||
8480e480 CC |
15394 | if (DEFAULT_ABI == ABI_AIX) |
15395 | { | |
9739c90c JJ |
15396 | #ifndef NO_PROFILE_COUNTERS |
15397 | # define NO_PROFILE_COUNTERS 0 | |
15398 | #endif | |
f676971a | 15399 | if (NO_PROFILE_COUNTERS) |
9739c90c JJ |
15400 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); |
15401 | else | |
15402 | { | |
15403 | char buf[30]; | |
15404 | const char *label_name; | |
15405 | rtx fun; | |
411707f4 | 15406 | |
9739c90c JJ |
15407 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
15408 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
15409 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 15410 | |
9739c90c JJ |
15411 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
15412 | fun, Pmode); | |
15413 | } | |
8480e480 | 15414 | } |
ee890fe2 SS |
15415 | else if (DEFAULT_ABI == ABI_DARWIN) |
15416 | { | |
d5fa86ba | 15417 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
15418 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
15419 | ||
15420 | /* Be conservative and always set this, at least for now. */ | |
15421 | current_function_uses_pic_offset_table = 1; | |
15422 | ||
15423 | #if TARGET_MACHO | |
15424 | /* For PIC code, set up a stub and collect the caller's address | |
15425 | from r0, which is where the prologue puts it. */ | |
11abc112 MM |
15426 | if (MACHOPIC_INDIRECT |
15427 | && current_function_uses_pic_offset_table) | |
15428 | caller_addr_regno = 0; | |
ee890fe2 SS |
15429 | #endif |
15430 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
15431 | 0, VOIDmode, 1, | |
15432 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
15433 | } | |
411707f4 CC |
15434 | } |
15435 | ||
a4f6c312 | 15436 | /* Write function profiler code. */ |
e165f3f0 RK |
15437 | |
15438 | void | |
a2369ed3 | 15439 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 15440 | { |
3daf36a4 | 15441 | char buf[100]; |
e165f3f0 | 15442 | |
38c1f2d7 | 15443 | switch (DEFAULT_ABI) |
3daf36a4 | 15444 | { |
38c1f2d7 | 15445 | default: |
37409796 | 15446 | gcc_unreachable (); |
38c1f2d7 MM |
15447 | |
15448 | case ABI_V4: | |
09eeeacb AM |
15449 | if (!TARGET_32BIT) |
15450 | { | |
d4ee4d25 | 15451 | warning (0, "no profiling of 64-bit code for this ABI"); |
09eeeacb AM |
15452 | return; |
15453 | } | |
ffcfcb5f | 15454 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 15455 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
71625f3d AM |
15456 | if (NO_PROFILE_COUNTERS) |
15457 | { | |
15458 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
15459 | reg_names[0], reg_names[1]); | |
15460 | } | |
15461 | else if (TARGET_SECURE_PLT && flag_pic) | |
15462 | { | |
15463 | asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n", | |
15464 | reg_names[0], reg_names[1]); | |
15465 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); | |
15466 | asm_fprintf (file, "\t{cau|addis} %s,%s,", | |
15467 | reg_names[12], reg_names[12]); | |
15468 | assemble_name (file, buf); | |
15469 | asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]); | |
15470 | assemble_name (file, buf); | |
15471 | asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]); | |
15472 | } | |
15473 | else if (flag_pic == 1) | |
38c1f2d7 | 15474 | { |
dfdfa60f | 15475 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
71625f3d AM |
15476 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
15477 | reg_names[0], reg_names[1]); | |
17167fd8 | 15478 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 15479 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 15480 | assemble_name (file, buf); |
17167fd8 | 15481 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 15482 | } |
9ebbca7d | 15483 | else if (flag_pic > 1) |
38c1f2d7 | 15484 | { |
71625f3d AM |
15485 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
15486 | reg_names[0], reg_names[1]); | |
9ebbca7d | 15487 | /* Now, we need to get the address of the label. */ |
71625f3d | 15488 | fputs ("\tbcl 20,31,1f\n\t.long ", file); |
034e84c4 | 15489 | assemble_name (file, buf); |
9ebbca7d GK |
15490 | fputs ("-.\n1:", file); |
15491 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
f676971a | 15492 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", |
9ebbca7d GK |
15493 | reg_names[0], reg_names[11]); |
15494 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
15495 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 15496 | } |
38c1f2d7 MM |
15497 | else |
15498 | { | |
17167fd8 | 15499 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 15500 | assemble_name (file, buf); |
dfdfa60f | 15501 | fputs ("@ha\n", file); |
71625f3d AM |
15502 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
15503 | reg_names[0], reg_names[1]); | |
a260abc9 | 15504 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 15505 | assemble_name (file, buf); |
17167fd8 | 15506 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
15507 | } |
15508 | ||
50d440bc | 15509 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
3b6ce0af DE |
15510 | fprintf (file, "\tbl %s%s\n", |
15511 | RS6000_MCOUNT, flag_pic ? "@plt" : ""); | |
38c1f2d7 MM |
15512 | break; |
15513 | ||
15514 | case ABI_AIX: | |
ee890fe2 | 15515 | case ABI_DARWIN: |
ffcfcb5f AM |
15516 | if (!TARGET_PROFILE_KERNEL) |
15517 | { | |
a3c9585f | 15518 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
15519 | } |
15520 | else | |
15521 | { | |
37409796 | 15522 | gcc_assert (!TARGET_32BIT); |
ffcfcb5f AM |
15523 | |
15524 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
15525 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
15526 | ||
6de9cd9a | 15527 | if (cfun->static_chain_decl != NULL) |
ffcfcb5f AM |
15528 | { |
15529 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
15530 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
15531 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
15532 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
15533 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
15534 | } | |
15535 | else | |
15536 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
15537 | } | |
38c1f2d7 MM |
15538 | break; |
15539 | } | |
e165f3f0 | 15540 | } |
a251ffd0 | 15541 | |
b54cf83a | 15542 | \f |
b54cf83a DE |
15543 | /* Power4 load update and store update instructions are cracked into a |
15544 | load or store and an integer insn which are executed in the same cycle. | |
15545 | Branches have their own dispatch slot which does not count against the | |
15546 | GCC issue rate, but it changes the program flow so there are no other | |
15547 | instructions to issue in this cycle. */ | |
15548 | ||
15549 | static int | |
f676971a EC |
15550 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
15551 | int verbose ATTRIBUTE_UNUSED, | |
a2369ed3 | 15552 | rtx insn, int more) |
b54cf83a DE |
15553 | { |
15554 | if (GET_CODE (PATTERN (insn)) == USE | |
15555 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15556 | return more; | |
15557 | ||
ec507f2d | 15558 | if (rs6000_sched_groups) |
b54cf83a | 15559 | { |
cbe26ab8 | 15560 | if (is_microcoded_insn (insn)) |
c4ad648e | 15561 | return 0; |
cbe26ab8 | 15562 | else if (is_cracked_insn (insn)) |
c4ad648e | 15563 | return more > 2 ? more - 2 : 0; |
b54cf83a | 15564 | } |
165b263e DE |
15565 | |
15566 | return more - 1; | |
b54cf83a DE |
15567 | } |
15568 | ||
a251ffd0 TG |
15569 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
15570 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
15571 | ||
c237e94a | 15572 | static int |
0a4f0294 | 15573 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
a251ffd0 TG |
15574 | { |
15575 | if (! recog_memoized (insn)) | |
15576 | return 0; | |
15577 | ||
15578 | if (REG_NOTE_KIND (link) != 0) | |
15579 | return 0; | |
15580 | ||
15581 | if (REG_NOTE_KIND (link) == 0) | |
15582 | { | |
ed947a96 DJ |
15583 | /* Data dependency; DEP_INSN writes a register that INSN reads |
15584 | some cycles later. */ | |
c9dbf840 DE |
15585 | |
15586 | /* Separate a load from a narrower, dependent store. */ | |
15587 | if (rs6000_sched_groups | |
15588 | && GET_CODE (PATTERN (insn)) == SET | |
15589 | && GET_CODE (PATTERN (dep_insn)) == SET | |
15590 | && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM | |
15591 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM | |
15592 | && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1))) | |
15593 | > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0))))) | |
15594 | return cost + 14; | |
15595 | ||
ed947a96 DJ |
15596 | switch (get_attr_type (insn)) |
15597 | { | |
15598 | case TYPE_JMPREG: | |
309323c2 | 15599 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
15600 | a mtctr and bctr (and mtlr and br/blr). The first |
15601 | scheduling pass will not know about this latency since | |
15602 | the mtctr instruction, which has the latency associated | |
15603 | to it, will be generated by reload. */ | |
309323c2 | 15604 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
15605 | case TYPE_BRANCH: |
15606 | /* Leave some extra cycles between a compare and its | |
15607 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
15608 | if ((rs6000_cpu_attr == CPU_PPC603 |
15609 | || rs6000_cpu_attr == CPU_PPC604 | |
15610 | || rs6000_cpu_attr == CPU_PPC604E | |
15611 | || rs6000_cpu_attr == CPU_PPC620 | |
15612 | || rs6000_cpu_attr == CPU_PPC630 | |
15613 | || rs6000_cpu_attr == CPU_PPC750 | |
15614 | || rs6000_cpu_attr == CPU_PPC7400 | |
15615 | || rs6000_cpu_attr == CPU_PPC7450 | |
ec507f2d DE |
15616 | || rs6000_cpu_attr == CPU_POWER4 |
15617 | || rs6000_cpu_attr == CPU_POWER5) | |
ed947a96 DJ |
15618 | && recog_memoized (dep_insn) |
15619 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
15620 | && (get_attr_type (dep_insn) == TYPE_CMP |
15621 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 15622 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
15623 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
15624 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 15625 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
15626 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
15627 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
15628 | return cost + 2; |
15629 | default: | |
15630 | break; | |
15631 | } | |
a251ffd0 TG |
15632 | /* Fall out to return default cost. */ |
15633 | } | |
15634 | ||
15635 | return cost; | |
15636 | } | |
b6c9286a | 15637 | |
cbe26ab8 | 15638 | /* The function returns a true if INSN is microcoded. |
839a4992 | 15639 | Return false otherwise. */ |
cbe26ab8 DN |
15640 | |
15641 | static bool | |
15642 | is_microcoded_insn (rtx insn) | |
15643 | { | |
15644 | if (!insn || !INSN_P (insn) | |
15645 | || GET_CODE (PATTERN (insn)) == USE | |
15646 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15647 | return false; | |
15648 | ||
ec507f2d | 15649 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15650 | { |
15651 | enum attr_type type = get_attr_type (insn); | |
15652 | if (type == TYPE_LOAD_EXT_U | |
15653 | || type == TYPE_LOAD_EXT_UX | |
15654 | || type == TYPE_LOAD_UX | |
15655 | || type == TYPE_STORE_UX | |
15656 | || type == TYPE_MFCR) | |
c4ad648e | 15657 | return true; |
cbe26ab8 DN |
15658 | } |
15659 | ||
15660 | return false; | |
15661 | } | |
15662 | ||
5c425df5 | 15663 | /* The function returns a nonzero value if INSN can be scheduled only |
cbe26ab8 DN |
15664 | as the first insn in a dispatch group ("dispatch-slot restricted"). |
15665 | In this case, the returned value indicates how many dispatch slots | |
15666 | the insn occupies (at the beginning of the group). | |
79ae11c4 DN |
15667 | Return 0 otherwise. */ |
15668 | ||
cbe26ab8 | 15669 | static int |
79ae11c4 DN |
15670 | is_dispatch_slot_restricted (rtx insn) |
15671 | { | |
15672 | enum attr_type type; | |
15673 | ||
ec507f2d | 15674 | if (!rs6000_sched_groups) |
79ae11c4 DN |
15675 | return 0; |
15676 | ||
15677 | if (!insn | |
15678 | || insn == NULL_RTX | |
15679 | || GET_CODE (insn) == NOTE | |
15680 | || GET_CODE (PATTERN (insn)) == USE | |
15681 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15682 | return 0; | |
15683 | ||
15684 | type = get_attr_type (insn); | |
15685 | ||
ec507f2d DE |
15686 | switch (type) |
15687 | { | |
15688 | case TYPE_MFCR: | |
15689 | case TYPE_MFCRF: | |
15690 | case TYPE_MTCR: | |
15691 | case TYPE_DELAYED_CR: | |
15692 | case TYPE_CR_LOGICAL: | |
15693 | case TYPE_MTJMPR: | |
15694 | case TYPE_MFJMPR: | |
15695 | return 1; | |
15696 | case TYPE_IDIV: | |
15697 | case TYPE_LDIV: | |
15698 | return 2; | |
15699 | default: | |
15700 | if (rs6000_cpu == PROCESSOR_POWER5 | |
15701 | && is_cracked_insn (insn)) | |
15702 | return 2; | |
15703 | return 0; | |
15704 | } | |
79ae11c4 DN |
15705 | } |
15706 | ||
cbe26ab8 DN |
15707 | /* The function returns true if INSN is cracked into 2 instructions |
15708 | by the processor (and therefore occupies 2 issue slots). */ | |
15709 | ||
15710 | static bool | |
15711 | is_cracked_insn (rtx insn) | |
15712 | { | |
15713 | if (!insn || !INSN_P (insn) | |
15714 | || GET_CODE (PATTERN (insn)) == USE | |
15715 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15716 | return false; | |
15717 | ||
ec507f2d | 15718 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15719 | { |
15720 | enum attr_type type = get_attr_type (insn); | |
15721 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
c4ad648e AM |
15722 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U |
15723 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
15724 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
15725 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
15726 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
15727 | || type == TYPE_IDIV || type == TYPE_LDIV | |
15728 | || type == TYPE_INSERT_WORD) | |
15729 | return true; | |
cbe26ab8 DN |
15730 | } |
15731 | ||
15732 | return false; | |
15733 | } | |
15734 | ||
15735 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 15736 | the branch slot. */ |
cbe26ab8 DN |
15737 | |
15738 | static bool | |
15739 | is_branch_slot_insn (rtx insn) | |
15740 | { | |
15741 | if (!insn || !INSN_P (insn) | |
15742 | || GET_CODE (PATTERN (insn)) == USE | |
15743 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15744 | return false; | |
15745 | ||
ec507f2d | 15746 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15747 | { |
15748 | enum attr_type type = get_attr_type (insn); | |
15749 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
f676971a | 15750 | return true; |
cbe26ab8 DN |
15751 | return false; |
15752 | } | |
15753 | ||
15754 | return false; | |
15755 | } | |
79ae11c4 | 15756 | |
a4f6c312 | 15757 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
15758 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
15759 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
15760 | define this macro if you do not need to adjust the scheduling |
15761 | priorities of insns. */ | |
bef84347 | 15762 | |
c237e94a | 15763 | static int |
a2369ed3 | 15764 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 15765 | { |
a4f6c312 SS |
15766 | /* On machines (like the 750) which have asymmetric integer units, |
15767 | where one integer unit can do multiply and divides and the other | |
15768 | can't, reduce the priority of multiply/divide so it is scheduled | |
15769 | before other integer operations. */ | |
bef84347 VM |
15770 | |
15771 | #if 0 | |
2c3c49de | 15772 | if (! INSN_P (insn)) |
bef84347 VM |
15773 | return priority; |
15774 | ||
15775 | if (GET_CODE (PATTERN (insn)) == USE) | |
15776 | return priority; | |
15777 | ||
15778 | switch (rs6000_cpu_attr) { | |
15779 | case CPU_PPC750: | |
15780 | switch (get_attr_type (insn)) | |
15781 | { | |
15782 | default: | |
15783 | break; | |
15784 | ||
15785 | case TYPE_IMUL: | |
15786 | case TYPE_IDIV: | |
3cb999d8 DE |
15787 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
15788 | priority, priority); | |
bef84347 VM |
15789 | if (priority >= 0 && priority < 0x01000000) |
15790 | priority >>= 3; | |
15791 | break; | |
15792 | } | |
15793 | } | |
15794 | #endif | |
15795 | ||
79ae11c4 DN |
15796 | if (is_dispatch_slot_restricted (insn) |
15797 | && reload_completed | |
f676971a | 15798 | && current_sched_info->sched_max_insns_priority |
79ae11c4 DN |
15799 | && rs6000_sched_restricted_insns_priority) |
15800 | { | |
15801 | ||
c4ad648e AM |
15802 | /* Prioritize insns that can be dispatched only in the first |
15803 | dispatch slot. */ | |
79ae11c4 | 15804 | if (rs6000_sched_restricted_insns_priority == 1) |
f676971a EC |
15805 | /* Attach highest priority to insn. This means that in |
15806 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
79ae11c4 | 15807 | precede 'priority' (critical path) considerations. */ |
f676971a | 15808 | return current_sched_info->sched_max_insns_priority; |
79ae11c4 | 15809 | else if (rs6000_sched_restricted_insns_priority == 2) |
f676971a | 15810 | /* Increase priority of insn by a minimal amount. This means that in |
c4ad648e AM |
15811 | haifa-sched.c:ready_sort(), only 'priority' (critical path) |
15812 | considerations precede dispatch-slot restriction considerations. */ | |
f676971a EC |
15813 | return (priority + 1); |
15814 | } | |
79ae11c4 | 15815 | |
bef84347 VM |
15816 | return priority; |
15817 | } | |
15818 | ||
a4f6c312 SS |
15819 | /* Return how many instructions the machine can issue per cycle. */ |
15820 | ||
c237e94a | 15821 | static int |
863d938c | 15822 | rs6000_issue_rate (void) |
b6c9286a | 15823 | { |
3317bab1 DE |
15824 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
15825 | if (!reload_completed) | |
15826 | return 1; | |
15827 | ||
b6c9286a | 15828 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
15829 | case CPU_RIOS1: /* ? */ |
15830 | case CPU_RS64A: | |
15831 | case CPU_PPC601: /* ? */ | |
ed947a96 | 15832 | case CPU_PPC7450: |
3cb999d8 | 15833 | return 3; |
b54cf83a | 15834 | case CPU_PPC440: |
b6c9286a | 15835 | case CPU_PPC603: |
bef84347 | 15836 | case CPU_PPC750: |
ed947a96 | 15837 | case CPU_PPC7400: |
be12c2b0 | 15838 | case CPU_PPC8540: |
f676971a | 15839 | return 2; |
3cb999d8 | 15840 | case CPU_RIOS2: |
b6c9286a | 15841 | case CPU_PPC604: |
19684119 | 15842 | case CPU_PPC604E: |
b6c9286a | 15843 | case CPU_PPC620: |
3cb999d8 | 15844 | case CPU_PPC630: |
b6c9286a | 15845 | return 4; |
cbe26ab8 | 15846 | case CPU_POWER4: |
ec507f2d | 15847 | case CPU_POWER5: |
cbe26ab8 | 15848 | return 5; |
b6c9286a MM |
15849 | default: |
15850 | return 1; | |
15851 | } | |
15852 | } | |
15853 | ||
be12c2b0 VM |
15854 | /* Return how many instructions to look ahead for better insn |
15855 | scheduling. */ | |
15856 | ||
15857 | static int | |
863d938c | 15858 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
15859 | { |
15860 | if (rs6000_cpu_attr == CPU_PPC8540) | |
15861 | return 4; | |
15862 | return 0; | |
15863 | } | |
15864 | ||
569fa502 DN |
15865 | /* Determine is PAT refers to memory. */ |
15866 | ||
15867 | static bool | |
15868 | is_mem_ref (rtx pat) | |
15869 | { | |
15870 | const char * fmt; | |
15871 | int i, j; | |
15872 | bool ret = false; | |
15873 | ||
15874 | if (GET_CODE (pat) == MEM) | |
15875 | return true; | |
15876 | ||
15877 | /* Recursively process the pattern. */ | |
15878 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
15879 | ||
15880 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
15881 | { | |
15882 | if (fmt[i] == 'e') | |
15883 | ret |= is_mem_ref (XEXP (pat, i)); | |
15884 | else if (fmt[i] == 'E') | |
15885 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
15886 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
15887 | } | |
15888 | ||
15889 | return ret; | |
15890 | } | |
15891 | ||
15892 | /* Determine if PAT is a PATTERN of a load insn. */ | |
f676971a | 15893 | |
569fa502 DN |
15894 | static bool |
15895 | is_load_insn1 (rtx pat) | |
15896 | { | |
15897 | if (!pat || pat == NULL_RTX) | |
15898 | return false; | |
15899 | ||
15900 | if (GET_CODE (pat) == SET) | |
15901 | return is_mem_ref (SET_SRC (pat)); | |
15902 | ||
15903 | if (GET_CODE (pat) == PARALLEL) | |
15904 | { | |
15905 | int i; | |
15906 | ||
15907 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
15908 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
15909 | return true; | |
15910 | } | |
15911 | ||
15912 | return false; | |
15913 | } | |
15914 | ||
15915 | /* Determine if INSN loads from memory. */ | |
15916 | ||
15917 | static bool | |
15918 | is_load_insn (rtx insn) | |
15919 | { | |
15920 | if (!insn || !INSN_P (insn)) | |
15921 | return false; | |
15922 | ||
15923 | if (GET_CODE (insn) == CALL_INSN) | |
15924 | return false; | |
15925 | ||
15926 | return is_load_insn1 (PATTERN (insn)); | |
15927 | } | |
15928 | ||
15929 | /* Determine if PAT is a PATTERN of a store insn. */ | |
15930 | ||
15931 | static bool | |
15932 | is_store_insn1 (rtx pat) | |
15933 | { | |
15934 | if (!pat || pat == NULL_RTX) | |
15935 | return false; | |
15936 | ||
15937 | if (GET_CODE (pat) == SET) | |
15938 | return is_mem_ref (SET_DEST (pat)); | |
15939 | ||
15940 | if (GET_CODE (pat) == PARALLEL) | |
15941 | { | |
15942 | int i; | |
15943 | ||
15944 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
15945 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
15946 | return true; | |
15947 | } | |
15948 | ||
15949 | return false; | |
15950 | } | |
15951 | ||
15952 | /* Determine if INSN stores to memory. */ | |
15953 | ||
15954 | static bool | |
15955 | is_store_insn (rtx insn) | |
15956 | { | |
15957 | if (!insn || !INSN_P (insn)) | |
15958 | return false; | |
15959 | ||
15960 | return is_store_insn1 (PATTERN (insn)); | |
15961 | } | |
15962 | ||
15963 | /* Returns whether the dependence between INSN and NEXT is considered | |
15964 | costly by the given target. */ | |
15965 | ||
15966 | static bool | |
c4ad648e AM |
15967 | rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, |
15968 | int distance) | |
f676971a | 15969 | { |
aabcd309 | 15970 | /* If the flag is not enabled - no dependence is considered costly; |
f676971a | 15971 | allow all dependent insns in the same group. |
569fa502 DN |
15972 | This is the most aggressive option. */ |
15973 | if (rs6000_sched_costly_dep == no_dep_costly) | |
15974 | return false; | |
15975 | ||
f676971a | 15976 | /* If the flag is set to 1 - a dependence is always considered costly; |
569fa502 DN |
15977 | do not allow dependent instructions in the same group. |
15978 | This is the most conservative option. */ | |
15979 | if (rs6000_sched_costly_dep == all_deps_costly) | |
f676971a | 15980 | return true; |
569fa502 | 15981 | |
f676971a EC |
15982 | if (rs6000_sched_costly_dep == store_to_load_dep_costly |
15983 | && is_load_insn (next) | |
569fa502 DN |
15984 | && is_store_insn (insn)) |
15985 | /* Prevent load after store in the same group. */ | |
15986 | return true; | |
15987 | ||
15988 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
f676971a | 15989 | && is_load_insn (next) |
569fa502 DN |
15990 | && is_store_insn (insn) |
15991 | && (!link || (int) REG_NOTE_KIND (link) == 0)) | |
c4ad648e AM |
15992 | /* Prevent load after store in the same group if it is a true |
15993 | dependence. */ | |
569fa502 | 15994 | return true; |
f676971a EC |
15995 | |
15996 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
569fa502 DN |
15997 | and will not be scheduled in the same group. */ |
15998 | if (rs6000_sched_costly_dep <= max_dep_latency | |
15999 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
16000 | return true; | |
16001 | ||
16002 | return false; | |
16003 | } | |
16004 | ||
f676971a | 16005 | /* Return the next insn after INSN that is found before TAIL is reached, |
cbe26ab8 DN |
16006 | skipping any "non-active" insns - insns that will not actually occupy |
16007 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
16008 | ||
16009 | static rtx | |
16010 | get_next_active_insn (rtx insn, rtx tail) | |
16011 | { | |
16012 | rtx next_insn; | |
16013 | ||
16014 | if (!insn || insn == tail) | |
16015 | return NULL_RTX; | |
16016 | ||
16017 | next_insn = NEXT_INSN (insn); | |
16018 | ||
16019 | while (next_insn | |
16020 | && next_insn != tail | |
9390387d | 16021 | && (GET_CODE (next_insn) == NOTE |
cbe26ab8 DN |
16022 | || GET_CODE (PATTERN (next_insn)) == USE |
16023 | || GET_CODE (PATTERN (next_insn)) == CLOBBER)) | |
16024 | { | |
16025 | next_insn = NEXT_INSN (next_insn); | |
16026 | } | |
16027 | ||
16028 | if (!next_insn || next_insn == tail) | |
16029 | return NULL_RTX; | |
16030 | ||
16031 | return next_insn; | |
16032 | } | |
16033 | ||
839a4992 | 16034 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
16035 | of group WHICH_GROUP. |
16036 | ||
16037 | If WHICH_GROUP == current_group, this function will return true if INSN | |
16038 | causes the termination of the current group (i.e, the dispatch group to | |
16039 | which INSN belongs). This means that INSN will be the last insn in the | |
16040 | group it belongs to. | |
16041 | ||
16042 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
16043 | causes the termination of the previous group (i.e, the dispatch group that | |
16044 | precedes the group to which INSN belongs). This means that INSN will be | |
16045 | the first insn in the group it belongs to). */ | |
16046 | ||
16047 | static bool | |
16048 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
16049 | { | |
16050 | enum attr_type type; | |
16051 | ||
16052 | if (! insn) | |
16053 | return false; | |
569fa502 | 16054 | |
cbe26ab8 DN |
16055 | type = get_attr_type (insn); |
16056 | ||
16057 | if (is_microcoded_insn (insn)) | |
16058 | return true; | |
16059 | ||
16060 | if (which_group == current_group) | |
16061 | { | |
16062 | if (is_branch_slot_insn (insn)) | |
c4ad648e | 16063 | return true; |
cbe26ab8 DN |
16064 | return false; |
16065 | } | |
16066 | else if (which_group == previous_group) | |
16067 | { | |
16068 | if (is_dispatch_slot_restricted (insn)) | |
c4ad648e | 16069 | return true; |
cbe26ab8 DN |
16070 | return false; |
16071 | } | |
16072 | ||
16073 | return false; | |
16074 | } | |
16075 | ||
839a4992 | 16076 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
16077 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
16078 | ||
16079 | static bool | |
16080 | is_costly_group (rtx *group_insns, rtx next_insn) | |
16081 | { | |
16082 | int i; | |
16083 | rtx link; | |
16084 | int cost; | |
16085 | int issue_rate = rs6000_issue_rate (); | |
16086 | ||
16087 | for (i = 0; i < issue_rate; i++) | |
16088 | { | |
16089 | rtx insn = group_insns[i]; | |
16090 | if (!insn) | |
c4ad648e | 16091 | continue; |
cbe26ab8 | 16092 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) |
c4ad648e AM |
16093 | { |
16094 | rtx next = XEXP (link, 0); | |
16095 | if (next == next_insn) | |
16096 | { | |
16097 | cost = insn_cost (insn, link, next_insn); | |
16098 | if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) | |
16099 | return true; | |
16100 | } | |
16101 | } | |
cbe26ab8 DN |
16102 | } |
16103 | ||
16104 | return false; | |
16105 | } | |
16106 | ||
f676971a | 16107 | /* Utility of the function redefine_groups. |
cbe26ab8 DN |
16108 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS |
16109 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
16110 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
16111 | one of the following schemes, depending on the value of the flag | |
16112 | -minsert_sched_nops = X: | |
16113 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 16114 | in order to force NEXT_INSN into a separate group. |
f676971a EC |
16115 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
16116 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
cbe26ab8 DN |
16117 | insertion (has a group just ended, how many vacant issue slots remain in the |
16118 | last group, and how many dispatch groups were encountered so far). */ | |
16119 | ||
f676971a | 16120 | static int |
c4ad648e AM |
16121 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, |
16122 | rtx next_insn, bool *group_end, int can_issue_more, | |
16123 | int *group_count) | |
cbe26ab8 DN |
16124 | { |
16125 | rtx nop; | |
16126 | bool force; | |
16127 | int issue_rate = rs6000_issue_rate (); | |
16128 | bool end = *group_end; | |
16129 | int i; | |
16130 | ||
16131 | if (next_insn == NULL_RTX) | |
16132 | return can_issue_more; | |
16133 | ||
16134 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
16135 | return can_issue_more; | |
16136 | ||
16137 | force = is_costly_group (group_insns, next_insn); | |
16138 | if (!force) | |
16139 | return can_issue_more; | |
16140 | ||
16141 | if (sched_verbose > 6) | |
16142 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
c4ad648e | 16143 | *group_count ,can_issue_more); |
cbe26ab8 DN |
16144 | |
16145 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
16146 | { | |
16147 | if (*group_end) | |
c4ad648e | 16148 | can_issue_more = 0; |
cbe26ab8 DN |
16149 | |
16150 | /* Since only a branch can be issued in the last issue_slot, it is | |
16151 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
16152 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
c4ad648e AM |
16153 | in this case the last nop will start a new group and the branch |
16154 | will be forced to the new group. */ | |
cbe26ab8 | 16155 | if (can_issue_more && !is_branch_slot_insn (next_insn)) |
c4ad648e | 16156 | can_issue_more--; |
cbe26ab8 DN |
16157 | |
16158 | while (can_issue_more > 0) | |
c4ad648e | 16159 | { |
9390387d | 16160 | nop = gen_nop (); |
c4ad648e AM |
16161 | emit_insn_before (nop, next_insn); |
16162 | can_issue_more--; | |
16163 | } | |
cbe26ab8 DN |
16164 | |
16165 | *group_end = true; | |
16166 | return 0; | |
f676971a | 16167 | } |
cbe26ab8 DN |
16168 | |
16169 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
16170 | { | |
16171 | int n_nops = rs6000_sched_insert_nops; | |
16172 | ||
f676971a | 16173 | /* Nops can't be issued from the branch slot, so the effective |
c4ad648e | 16174 | issue_rate for nops is 'issue_rate - 1'. */ |
cbe26ab8 | 16175 | if (can_issue_more == 0) |
c4ad648e | 16176 | can_issue_more = issue_rate; |
cbe26ab8 DN |
16177 | can_issue_more--; |
16178 | if (can_issue_more == 0) | |
c4ad648e AM |
16179 | { |
16180 | can_issue_more = issue_rate - 1; | |
16181 | (*group_count)++; | |
16182 | end = true; | |
16183 | for (i = 0; i < issue_rate; i++) | |
16184 | { | |
16185 | group_insns[i] = 0; | |
16186 | } | |
16187 | } | |
cbe26ab8 DN |
16188 | |
16189 | while (n_nops > 0) | |
c4ad648e AM |
16190 | { |
16191 | nop = gen_nop (); | |
16192 | emit_insn_before (nop, next_insn); | |
16193 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
16194 | end = false; | |
16195 | can_issue_more--; | |
16196 | if (can_issue_more == 0) | |
16197 | { | |
16198 | can_issue_more = issue_rate - 1; | |
16199 | (*group_count)++; | |
16200 | end = true; | |
16201 | for (i = 0; i < issue_rate; i++) | |
16202 | { | |
16203 | group_insns[i] = 0; | |
16204 | } | |
16205 | } | |
16206 | n_nops--; | |
16207 | } | |
cbe26ab8 DN |
16208 | |
16209 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
f676971a | 16210 | can_issue_more++; |
cbe26ab8 | 16211 | |
c4ad648e AM |
16212 | /* Is next_insn going to start a new group? */ |
16213 | *group_end | |
16214 | = (end | |
cbe26ab8 DN |
16215 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) |
16216 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
16217 | || (can_issue_more < issue_rate && | |
c4ad648e | 16218 | insn_terminates_group_p (next_insn, previous_group))); |
cbe26ab8 | 16219 | if (*group_end && end) |
c4ad648e | 16220 | (*group_count)--; |
cbe26ab8 DN |
16221 | |
16222 | if (sched_verbose > 6) | |
c4ad648e AM |
16223 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", |
16224 | *group_count, can_issue_more); | |
f676971a EC |
16225 | return can_issue_more; |
16226 | } | |
cbe26ab8 DN |
16227 | |
16228 | return can_issue_more; | |
16229 | } | |
16230 | ||
16231 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
f676971a | 16232 | with the dispatch groups that the processor dispatcher is expected to |
cbe26ab8 DN |
16233 | form in practice. It tries to achieve this synchronization by forcing the |
16234 | estimated processor grouping on the compiler (as opposed to the function | |
16235 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
16236 | ||
16237 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
16238 | examines the (estimated) dispatch groups that will be formed by the processor | |
16239 | dispatcher. It marks these group boundaries to reflect the estimated | |
16240 | processor grouping, overriding the grouping that the scheduler had marked. | |
16241 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
16242 | force certain insns into separate groups or force a certain distance between | |
16243 | them by inserting nops, for example, if there exists a "costly dependence" | |
16244 | between the insns. | |
16245 | ||
16246 | The function estimates the group boundaries that the processor will form as | |
0fa2e4df | 16247 | follows: It keeps track of how many vacant issue slots are available after |
cbe26ab8 DN |
16248 | each insn. A subsequent insn will start a new group if one of the following |
16249 | 4 cases applies: | |
16250 | - no more vacant issue slots remain in the current dispatch group. | |
16251 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
16252 | insn is not a branch. | |
16253 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
16254 | which means that a cracked insn (which occupies two issue slots) can't be | |
16255 | issued in this group. | |
f676971a | 16256 | - less than 'issue_rate' slots are vacant, and the next insn always needs to |
cbe26ab8 DN |
16257 | start a new group. */ |
16258 | ||
16259 | static int | |
16260 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
16261 | { | |
16262 | rtx insn, next_insn; | |
16263 | int issue_rate; | |
16264 | int can_issue_more; | |
16265 | int slot, i; | |
16266 | bool group_end; | |
16267 | int group_count = 0; | |
16268 | rtx *group_insns; | |
16269 | ||
16270 | /* Initialize. */ | |
16271 | issue_rate = rs6000_issue_rate (); | |
16272 | group_insns = alloca (issue_rate * sizeof (rtx)); | |
f676971a | 16273 | for (i = 0; i < issue_rate; i++) |
cbe26ab8 DN |
16274 | { |
16275 | group_insns[i] = 0; | |
16276 | } | |
16277 | can_issue_more = issue_rate; | |
16278 | slot = 0; | |
16279 | insn = get_next_active_insn (prev_head_insn, tail); | |
16280 | group_end = false; | |
16281 | ||
16282 | while (insn != NULL_RTX) | |
16283 | { | |
16284 | slot = (issue_rate - can_issue_more); | |
16285 | group_insns[slot] = insn; | |
16286 | can_issue_more = | |
c4ad648e | 16287 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); |
cbe26ab8 | 16288 | if (insn_terminates_group_p (insn, current_group)) |
c4ad648e | 16289 | can_issue_more = 0; |
cbe26ab8 DN |
16290 | |
16291 | next_insn = get_next_active_insn (insn, tail); | |
16292 | if (next_insn == NULL_RTX) | |
c4ad648e | 16293 | return group_count + 1; |
cbe26ab8 | 16294 | |
c4ad648e AM |
16295 | /* Is next_insn going to start a new group? */ |
16296 | group_end | |
16297 | = (can_issue_more == 0 | |
16298 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
16299 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
16300 | || (can_issue_more < issue_rate && | |
16301 | insn_terminates_group_p (next_insn, previous_group))); | |
cbe26ab8 | 16302 | |
f676971a | 16303 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, |
c4ad648e AM |
16304 | next_insn, &group_end, can_issue_more, |
16305 | &group_count); | |
cbe26ab8 DN |
16306 | |
16307 | if (group_end) | |
c4ad648e AM |
16308 | { |
16309 | group_count++; | |
16310 | can_issue_more = 0; | |
16311 | for (i = 0; i < issue_rate; i++) | |
16312 | { | |
16313 | group_insns[i] = 0; | |
16314 | } | |
16315 | } | |
cbe26ab8 DN |
16316 | |
16317 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
9390387d | 16318 | PUT_MODE (next_insn, VOIDmode); |
cbe26ab8 | 16319 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) |
c4ad648e | 16320 | PUT_MODE (next_insn, TImode); |
cbe26ab8 DN |
16321 | |
16322 | insn = next_insn; | |
16323 | if (can_issue_more == 0) | |
c4ad648e AM |
16324 | can_issue_more = issue_rate; |
16325 | } /* while */ | |
cbe26ab8 DN |
16326 | |
16327 | return group_count; | |
16328 | } | |
16329 | ||
16330 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
16331 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
16332 | any dispatch groups which have vacant issue slots, in order to force the | |
16333 | scheduler's grouping on the processor dispatcher. The function | |
16334 | returns the number of dispatch groups found. */ | |
16335 | ||
16336 | static int | |
16337 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
16338 | { | |
16339 | rtx insn, next_insn; | |
16340 | rtx nop; | |
16341 | int issue_rate; | |
16342 | int can_issue_more; | |
16343 | int group_end; | |
16344 | int group_count = 0; | |
16345 | ||
16346 | /* Initialize issue_rate. */ | |
16347 | issue_rate = rs6000_issue_rate (); | |
16348 | can_issue_more = issue_rate; | |
16349 | ||
16350 | insn = get_next_active_insn (prev_head_insn, tail); | |
16351 | next_insn = get_next_active_insn (insn, tail); | |
16352 | ||
16353 | while (insn != NULL_RTX) | |
16354 | { | |
16355 | can_issue_more = | |
16356 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
16357 | ||
16358 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
16359 | ||
16360 | if (next_insn == NULL_RTX) | |
c4ad648e | 16361 | break; |
cbe26ab8 DN |
16362 | |
16363 | if (group_end) | |
c4ad648e AM |
16364 | { |
16365 | /* If the scheduler had marked group termination at this location | |
16366 | (between insn and next_indn), and neither insn nor next_insn will | |
16367 | force group termination, pad the group with nops to force group | |
16368 | termination. */ | |
16369 | if (can_issue_more | |
16370 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
16371 | && !insn_terminates_group_p (insn, current_group) | |
16372 | && !insn_terminates_group_p (next_insn, previous_group)) | |
16373 | { | |
9390387d | 16374 | if (!is_branch_slot_insn (next_insn)) |
c4ad648e AM |
16375 | can_issue_more--; |
16376 | ||
16377 | while (can_issue_more) | |
16378 | { | |
16379 | nop = gen_nop (); | |
16380 | emit_insn_before (nop, next_insn); | |
16381 | can_issue_more--; | |
16382 | } | |
16383 | } | |
16384 | ||
16385 | can_issue_more = issue_rate; | |
16386 | group_count++; | |
16387 | } | |
cbe26ab8 DN |
16388 | |
16389 | insn = next_insn; | |
16390 | next_insn = get_next_active_insn (insn, tail); | |
16391 | } | |
16392 | ||
16393 | return group_count; | |
16394 | } | |
16395 | ||
16396 | /* The following function is called at the end of scheduling BB. | |
16397 | After reload, it inserts nops at insn group bundling. */ | |
16398 | ||
16399 | static void | |
38f391a5 | 16400 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
16401 | { |
16402 | int n_groups; | |
16403 | ||
16404 | if (sched_verbose) | |
16405 | fprintf (dump, "=== Finishing schedule.\n"); | |
16406 | ||
ec507f2d | 16407 | if (reload_completed && rs6000_sched_groups) |
cbe26ab8 DN |
16408 | { |
16409 | if (rs6000_sched_insert_nops == sched_finish_none) | |
c4ad648e | 16410 | return; |
cbe26ab8 DN |
16411 | |
16412 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
c4ad648e AM |
16413 | n_groups = pad_groups (dump, sched_verbose, |
16414 | current_sched_info->prev_head, | |
16415 | current_sched_info->next_tail); | |
cbe26ab8 | 16416 | else |
c4ad648e AM |
16417 | n_groups = redefine_groups (dump, sched_verbose, |
16418 | current_sched_info->prev_head, | |
16419 | current_sched_info->next_tail); | |
cbe26ab8 DN |
16420 | |
16421 | if (sched_verbose >= 6) | |
16422 | { | |
16423 | fprintf (dump, "ngroups = %d\n", n_groups); | |
16424 | print_rtl (dump, current_sched_info->prev_head); | |
16425 | fprintf (dump, "Done finish_sched\n"); | |
16426 | } | |
16427 | } | |
16428 | } | |
b6c9286a | 16429 | \f |
b6c9286a MM |
16430 | /* Length in units of the trampoline for entering a nested function. */ |
16431 | ||
16432 | int | |
863d938c | 16433 | rs6000_trampoline_size (void) |
b6c9286a MM |
16434 | { |
16435 | int ret = 0; | |
16436 | ||
16437 | switch (DEFAULT_ABI) | |
16438 | { | |
16439 | default: | |
37409796 | 16440 | gcc_unreachable (); |
b6c9286a MM |
16441 | |
16442 | case ABI_AIX: | |
8f802bfb | 16443 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
16444 | break; |
16445 | ||
4dabc42d | 16446 | case ABI_DARWIN: |
b6c9286a | 16447 | case ABI_V4: |
03a7e1a5 | 16448 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 16449 | break; |
b6c9286a MM |
16450 | } |
16451 | ||
16452 | return ret; | |
16453 | } | |
16454 | ||
16455 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
16456 | FNADDR is an RTX for the address of the function's pure code. | |
16457 | CXT is an RTX for the static chain value for the function. */ | |
16458 | ||
16459 | void | |
a2369ed3 | 16460 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 16461 | { |
ac2a93a1 | 16462 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
16463 | int regsize = (TARGET_32BIT) ? 4 : 8; |
16464 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
16465 | |
16466 | switch (DEFAULT_ABI) | |
16467 | { | |
16468 | default: | |
37409796 | 16469 | gcc_unreachable (); |
b6c9286a | 16470 | |
8bd04c56 | 16471 | /* Macros to shorten the code expansions below. */ |
39403d82 | 16472 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
16473 | #define MEM_PLUS(addr,offset) \ |
16474 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 16475 | |
b6c9286a MM |
16476 | /* Under AIX, just build the 3 word function descriptor */ |
16477 | case ABI_AIX: | |
8bd04c56 MM |
16478 | { |
16479 | rtx fn_reg = gen_reg_rtx (pmode); | |
16480 | rtx toc_reg = gen_reg_rtx (pmode); | |
16481 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 16482 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
16483 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
16484 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
16485 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
16486 | } | |
b6c9286a MM |
16487 | break; |
16488 | ||
4dabc42d TC |
16489 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
16490 | case ABI_DARWIN: | |
b6c9286a | 16491 | case ABI_V4: |
39403d82 | 16492 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
16493 | FALSE, VOIDmode, 4, |
16494 | addr, pmode, | |
16495 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
16496 | fnaddr, pmode, | |
16497 | ctx_reg, pmode); | |
b6c9286a | 16498 | break; |
b6c9286a MM |
16499 | } |
16500 | ||
16501 | return; | |
16502 | } | |
7509c759 MM |
16503 | |
16504 | \f | |
91d231cb | 16505 | /* Table of valid machine attributes. */ |
a4f6c312 | 16506 | |
91d231cb | 16507 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 16508 | { |
91d231cb | 16509 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8bb418a3 | 16510 | { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, |
a5c76ee6 ZW |
16511 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
16512 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
005c1a13 GK |
16513 | #ifdef SUBTARGET_ATTRIBUTE_TABLE |
16514 | SUBTARGET_ATTRIBUTE_TABLE, | |
16515 | #endif | |
a5c76ee6 | 16516 | { NULL, 0, 0, false, false, false, NULL } |
91d231cb | 16517 | }; |
7509c759 | 16518 | |
8bb418a3 ZL |
16519 | /* Handle the "altivec" attribute. The attribute may have |
16520 | arguments as follows: | |
f676971a | 16521 | |
8bb418a3 ZL |
16522 | __attribute__((altivec(vector__))) |
16523 | __attribute__((altivec(pixel__))) (always followed by 'unsigned short') | |
16524 | __attribute__((altivec(bool__))) (always followed by 'unsigned') | |
16525 | ||
16526 | and may appear more than once (e.g., 'vector bool char') in a | |
16527 | given declaration. */ | |
16528 | ||
16529 | static tree | |
f90ac3f0 UP |
16530 | rs6000_handle_altivec_attribute (tree *node, |
16531 | tree name ATTRIBUTE_UNUSED, | |
16532 | tree args, | |
8bb418a3 ZL |
16533 | int flags ATTRIBUTE_UNUSED, |
16534 | bool *no_add_attrs) | |
16535 | { | |
16536 | tree type = *node, result = NULL_TREE; | |
16537 | enum machine_mode mode; | |
16538 | int unsigned_p; | |
16539 | char altivec_type | |
16540 | = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) | |
16541 | && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) | |
16542 | ? *IDENTIFIER_POINTER (TREE_VALUE (args)) | |
f676971a | 16543 | : '?'); |
8bb418a3 ZL |
16544 | |
16545 | while (POINTER_TYPE_P (type) | |
16546 | || TREE_CODE (type) == FUNCTION_TYPE | |
16547 | || TREE_CODE (type) == METHOD_TYPE | |
16548 | || TREE_CODE (type) == ARRAY_TYPE) | |
16549 | type = TREE_TYPE (type); | |
16550 | ||
16551 | mode = TYPE_MODE (type); | |
16552 | ||
f90ac3f0 UP |
16553 | /* Check for invalid AltiVec type qualifiers. */ |
16554 | if (type == long_unsigned_type_node || type == long_integer_type_node) | |
16555 | { | |
16556 | if (TARGET_64BIT) | |
16557 | error ("use of %<long%> in AltiVec types is invalid for 64-bit code"); | |
16558 | else if (rs6000_warn_altivec_long) | |
d4ee4d25 | 16559 | warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>"); |
f90ac3f0 UP |
16560 | } |
16561 | else if (type == long_long_unsigned_type_node | |
16562 | || type == long_long_integer_type_node) | |
16563 | error ("use of %<long long%> in AltiVec types is invalid"); | |
16564 | else if (type == double_type_node) | |
16565 | error ("use of %<double%> in AltiVec types is invalid"); | |
16566 | else if (type == long_double_type_node) | |
16567 | error ("use of %<long double%> in AltiVec types is invalid"); | |
16568 | else if (type == boolean_type_node) | |
16569 | error ("use of boolean types in AltiVec types is invalid"); | |
16570 | else if (TREE_CODE (type) == COMPLEX_TYPE) | |
16571 | error ("use of %<complex%> in AltiVec types is invalid"); | |
8bb418a3 ZL |
16572 | |
16573 | switch (altivec_type) | |
16574 | { | |
16575 | case 'v': | |
8df83eae | 16576 | unsigned_p = TYPE_UNSIGNED (type); |
8bb418a3 ZL |
16577 | switch (mode) |
16578 | { | |
c4ad648e AM |
16579 | case SImode: |
16580 | result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); | |
16581 | break; | |
16582 | case HImode: | |
16583 | result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); | |
16584 | break; | |
16585 | case QImode: | |
16586 | result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); | |
16587 | break; | |
16588 | case SFmode: result = V4SF_type_node; break; | |
16589 | /* If the user says 'vector int bool', we may be handed the 'bool' | |
16590 | attribute _before_ the 'vector' attribute, and so select the | |
16591 | proper type in the 'b' case below. */ | |
16592 | case V4SImode: case V8HImode: case V16QImode: case V4SFmode: | |
16593 | result = type; | |
16594 | default: break; | |
8bb418a3 ZL |
16595 | } |
16596 | break; | |
16597 | case 'b': | |
16598 | switch (mode) | |
16599 | { | |
c4ad648e AM |
16600 | case SImode: case V4SImode: result = bool_V4SI_type_node; break; |
16601 | case HImode: case V8HImode: result = bool_V8HI_type_node; break; | |
16602 | case QImode: case V16QImode: result = bool_V16QI_type_node; | |
16603 | default: break; | |
8bb418a3 ZL |
16604 | } |
16605 | break; | |
16606 | case 'p': | |
16607 | switch (mode) | |
16608 | { | |
c4ad648e AM |
16609 | case V8HImode: result = pixel_V8HI_type_node; |
16610 | default: break; | |
8bb418a3 ZL |
16611 | } |
16612 | default: break; | |
16613 | } | |
16614 | ||
7958a2a6 FJ |
16615 | if (result && result != type && TYPE_READONLY (type)) |
16616 | result = build_qualified_type (result, TYPE_QUAL_CONST); | |
16617 | ||
8bb418a3 ZL |
16618 | *no_add_attrs = true; /* No need to hang on to the attribute. */ |
16619 | ||
f90ac3f0 | 16620 | if (result) |
8bb418a3 ZL |
16621 | *node = reconstruct_complex_type (*node, result); |
16622 | ||
16623 | return NULL_TREE; | |
16624 | } | |
16625 | ||
f18eca82 ZL |
16626 | /* AltiVec defines four built-in scalar types that serve as vector |
16627 | elements; we must teach the compiler how to mangle them. */ | |
16628 | ||
16629 | static const char * | |
16630 | rs6000_mangle_fundamental_type (tree type) | |
16631 | { | |
16632 | if (type == bool_char_type_node) return "U6__boolc"; | |
16633 | if (type == bool_short_type_node) return "U6__bools"; | |
16634 | if (type == pixel_type_node) return "u7__pixel"; | |
16635 | if (type == bool_int_type_node) return "U6__booli"; | |
16636 | ||
16637 | /* For all other types, use normal C++ mangling. */ | |
16638 | return NULL; | |
16639 | } | |
16640 | ||
a5c76ee6 ZW |
16641 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
16642 | struct attribute_spec.handler. */ | |
a4f6c312 | 16643 | |
91d231cb | 16644 | static tree |
f676971a EC |
16645 | rs6000_handle_longcall_attribute (tree *node, tree name, |
16646 | tree args ATTRIBUTE_UNUSED, | |
16647 | int flags ATTRIBUTE_UNUSED, | |
a2369ed3 | 16648 | bool *no_add_attrs) |
91d231cb JM |
16649 | { |
16650 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
16651 | && TREE_CODE (*node) != FIELD_DECL | |
16652 | && TREE_CODE (*node) != TYPE_DECL) | |
16653 | { | |
5c498b10 | 16654 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
91d231cb JM |
16655 | IDENTIFIER_POINTER (name)); |
16656 | *no_add_attrs = true; | |
16657 | } | |
6a4cee5f | 16658 | |
91d231cb | 16659 | return NULL_TREE; |
7509c759 MM |
16660 | } |
16661 | ||
a5c76ee6 ZW |
16662 | /* Set longcall attributes on all functions declared when |
16663 | rs6000_default_long_calls is true. */ | |
16664 | static void | |
a2369ed3 | 16665 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
16666 | { |
16667 | if (rs6000_default_long_calls | |
16668 | && (TREE_CODE (type) == FUNCTION_TYPE | |
16669 | || TREE_CODE (type) == METHOD_TYPE)) | |
16670 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
16671 | NULL_TREE, | |
16672 | TYPE_ATTRIBUTES (type)); | |
16673 | } | |
16674 | ||
3cb999d8 DE |
16675 | /* Return a reference suitable for calling a function with the |
16676 | longcall attribute. */ | |
a4f6c312 | 16677 | |
9390387d | 16678 | rtx |
a2369ed3 | 16679 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 16680 | { |
d330fd93 | 16681 | const char *call_name; |
6a4cee5f MM |
16682 | tree node; |
16683 | ||
16684 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
16685 | return call_ref; | |
16686 | ||
16687 | /* System V adds '.' to the internal name, so skip them. */ | |
16688 | call_name = XSTR (call_ref, 0); | |
16689 | if (*call_name == '.') | |
16690 | { | |
16691 | while (*call_name == '.') | |
16692 | call_name++; | |
16693 | ||
16694 | node = get_identifier (call_name); | |
39403d82 | 16695 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
16696 | } |
16697 | ||
16698 | return force_reg (Pmode, call_ref); | |
16699 | } | |
7509c759 | 16700 | \f |
b64a1b53 RH |
16701 | #ifdef USING_ELFOS_H |
16702 | ||
7509c759 MM |
16703 | /* A C statement or statements to switch to the appropriate section |
16704 | for output of RTX in mode MODE. You can assume that RTX is some | |
16705 | kind of constant in RTL. The argument MODE is redundant except in | |
16706 | the case of a `const_int' rtx. Select the section by calling | |
16707 | `text_section' or one of the alternatives for other sections. | |
16708 | ||
16709 | Do not define this macro if you put all constants in the read-only | |
16710 | data section. */ | |
16711 | ||
b64a1b53 | 16712 | static void |
f676971a | 16713 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
a2369ed3 | 16714 | unsigned HOST_WIDE_INT align) |
7509c759 | 16715 | { |
a9098fd0 | 16716 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 16717 | toc_section (); |
7509c759 | 16718 | else |
b64a1b53 | 16719 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
16720 | } |
16721 | ||
16722 | /* A C statement or statements to switch to the appropriate | |
16723 | section for output of DECL. DECL is either a `VAR_DECL' node | |
16724 | or a constant of some sort. RELOC indicates whether forming | |
16725 | the initial value of DECL requires link-time relocations. */ | |
16726 | ||
ae46c4e0 | 16727 | static void |
f676971a | 16728 | rs6000_elf_select_section (tree decl, int reloc, |
a2369ed3 | 16729 | unsigned HOST_WIDE_INT align) |
7509c759 | 16730 | { |
f1384257 AM |
16731 | /* Pretend that we're always building for a shared library when |
16732 | ABI_AIX, because otherwise we end up with dynamic relocations | |
16733 | in read-only sections. This happens for function pointers, | |
16734 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
16735 | default_elf_select_section_1 (decl, reloc, align, |
16736 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
16737 | } |
16738 | ||
16739 | /* A C statement to build up a unique section name, expressed as a | |
16740 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
16741 | RELOC indicates whether the initial value of EXP requires | |
16742 | link-time relocations. If you do not define this macro, GCC will use | |
16743 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 16744 | macro can now be called for uninitialized data items as well as |
4912a07c | 16745 | initialized data and functions. */ |
63019373 | 16746 | |
ae46c4e0 | 16747 | static void |
a2369ed3 | 16748 | rs6000_elf_unique_section (tree decl, int reloc) |
63019373 | 16749 | { |
f1384257 AM |
16750 | /* As above, pretend that we're always building for a shared library |
16751 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
16752 | default_unique_section_1 (decl, reloc, |
16753 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 16754 | } |
d9407988 | 16755 | \f |
d1908feb JJ |
16756 | /* For a SYMBOL_REF, set generic flags and then perform some |
16757 | target-specific processing. | |
16758 | ||
d1908feb JJ |
16759 | When the AIX ABI is requested on a non-AIX system, replace the |
16760 | function name with the real name (with a leading .) rather than the | |
16761 | function descriptor name. This saves a lot of overriding code to | |
16762 | read the prefixes. */ | |
d9407988 | 16763 | |
fb49053f | 16764 | static void |
a2369ed3 | 16765 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 16766 | { |
d1908feb | 16767 | default_encode_section_info (decl, rtl, first); |
b2003250 | 16768 | |
d1908feb JJ |
16769 | if (first |
16770 | && TREE_CODE (decl) == FUNCTION_DECL | |
16771 | && !TARGET_AIX | |
16772 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 16773 | { |
c6a2438a | 16774 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
16775 | size_t len = strlen (XSTR (sym_ref, 0)); |
16776 | char *str = alloca (len + 2); | |
16777 | str[0] = '.'; | |
16778 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
16779 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 16780 | } |
d9407988 MM |
16781 | } |
16782 | ||
0e5dbd9b | 16783 | static bool |
a2369ed3 | 16784 | rs6000_elf_in_small_data_p (tree decl) |
0e5dbd9b DE |
16785 | { |
16786 | if (rs6000_sdata == SDATA_NONE) | |
16787 | return false; | |
16788 | ||
7482ad25 AF |
16789 | /* We want to merge strings, so we never consider them small data. */ |
16790 | if (TREE_CODE (decl) == STRING_CST) | |
16791 | return false; | |
16792 | ||
16793 | /* Functions are never in the small data area. */ | |
16794 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
16795 | return false; | |
16796 | ||
0e5dbd9b DE |
16797 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) |
16798 | { | |
16799 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
16800 | if (strcmp (section, ".sdata") == 0 | |
16801 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
16802 | || strcmp (section, ".sbss") == 0 |
16803 | || strcmp (section, ".sbss2") == 0 | |
16804 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
16805 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
16806 | return true; |
16807 | } | |
16808 | else | |
16809 | { | |
16810 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
16811 | ||
16812 | if (size > 0 | |
307b599c | 16813 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
16814 | /* If it's not public, and we're not going to reference it there, |
16815 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
16816 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
16817 | return true; | |
16818 | } | |
16819 | ||
16820 | return false; | |
16821 | } | |
16822 | ||
b91da81f | 16823 | #endif /* USING_ELFOS_H */ |
000034eb | 16824 | |
a6c2a102 | 16825 | \f |
000034eb | 16826 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
16827 | ADDR can be effectively incremented by incrementing REG. |
16828 | ||
16829 | r0 is special and we must not select it as an address | |
16830 | register by this routine since our caller will try to | |
16831 | increment the returned register via an "la" instruction. */ | |
000034eb | 16832 | |
9390387d | 16833 | rtx |
a2369ed3 | 16834 | find_addr_reg (rtx addr) |
000034eb DE |
16835 | { |
16836 | while (GET_CODE (addr) == PLUS) | |
16837 | { | |
02441cd6 JL |
16838 | if (GET_CODE (XEXP (addr, 0)) == REG |
16839 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 16840 | addr = XEXP (addr, 0); |
02441cd6 JL |
16841 | else if (GET_CODE (XEXP (addr, 1)) == REG |
16842 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
16843 | addr = XEXP (addr, 1); |
16844 | else if (CONSTANT_P (XEXP (addr, 0))) | |
16845 | addr = XEXP (addr, 1); | |
16846 | else if (CONSTANT_P (XEXP (addr, 1))) | |
16847 | addr = XEXP (addr, 0); | |
16848 | else | |
37409796 | 16849 | gcc_unreachable (); |
000034eb | 16850 | } |
37409796 NS |
16851 | gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0); |
16852 | return addr; | |
000034eb DE |
16853 | } |
16854 | ||
a6c2a102 | 16855 | void |
a2369ed3 | 16856 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
16857 | { |
16858 | fatal_insn ("bad address", op); | |
16859 | } | |
c8023011 | 16860 | |
ee890fe2 SS |
16861 | #if TARGET_MACHO |
16862 | ||
efdba735 | 16863 | static tree branch_island_list = 0; |
ee890fe2 | 16864 | |
efdba735 SH |
16865 | /* Remember to generate a branch island for far calls to the given |
16866 | function. */ | |
ee890fe2 | 16867 | |
f676971a | 16868 | static void |
c4ad648e AM |
16869 | add_compiler_branch_island (tree label_name, tree function_name, |
16870 | int line_number) | |
ee890fe2 | 16871 | { |
efdba735 | 16872 | tree branch_island = build_tree_list (function_name, label_name); |
7d60be94 | 16873 | TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number); |
efdba735 SH |
16874 | TREE_CHAIN (branch_island) = branch_island_list; |
16875 | branch_island_list = branch_island; | |
ee890fe2 SS |
16876 | } |
16877 | ||
efdba735 SH |
16878 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
16879 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
16880 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
16881 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 16882 | |
efdba735 SH |
16883 | /* Generate far-jump branch islands for everything on the |
16884 | branch_island_list. Invoked immediately after the last instruction | |
16885 | of the epilogue has been emitted; the branch-islands must be | |
16886 | appended to, and contiguous with, the function body. Mach-O stubs | |
16887 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 16888 | |
efdba735 SH |
16889 | static void |
16890 | macho_branch_islands (void) | |
16891 | { | |
16892 | char tmp_buf[512]; | |
16893 | tree branch_island; | |
16894 | ||
16895 | for (branch_island = branch_island_list; | |
16896 | branch_island; | |
16897 | branch_island = TREE_CHAIN (branch_island)) | |
16898 | { | |
16899 | const char *label = | |
16900 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
16901 | const char *name = | |
11abc112 | 16902 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)); |
efdba735 SH |
16903 | char name_buf[512]; |
16904 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
16905 | if (name[0] == '*' || name[0] == '&') | |
16906 | strcpy (name_buf, name+1); | |
16907 | else | |
16908 | { | |
16909 | name_buf[0] = '_'; | |
16910 | strcpy (name_buf+1, name); | |
16911 | } | |
16912 | strcpy (tmp_buf, "\n"); | |
16913 | strcat (tmp_buf, label); | |
ee890fe2 | 16914 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 16915 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 16916 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 16917 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
16918 | if (flag_pic) |
16919 | { | |
16920 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
16921 | strcat (tmp_buf, label); | |
16922 | strcat (tmp_buf, "_pic\n"); | |
16923 | strcat (tmp_buf, label); | |
16924 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
f676971a | 16925 | |
efdba735 SH |
16926 | strcat (tmp_buf, "\taddis r11,r11,ha16("); |
16927 | strcat (tmp_buf, name_buf); | |
16928 | strcat (tmp_buf, " - "); | |
16929 | strcat (tmp_buf, label); | |
16930 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 16931 | |
efdba735 | 16932 | strcat (tmp_buf, "\tmtlr r0\n"); |
f676971a | 16933 | |
efdba735 SH |
16934 | strcat (tmp_buf, "\taddi r12,r11,lo16("); |
16935 | strcat (tmp_buf, name_buf); | |
16936 | strcat (tmp_buf, " - "); | |
16937 | strcat (tmp_buf, label); | |
16938 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 16939 | |
efdba735 SH |
16940 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); |
16941 | } | |
16942 | else | |
16943 | { | |
16944 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
16945 | strcat (tmp_buf, name_buf); | |
16946 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
16947 | strcat (tmp_buf, name_buf); | |
16948 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
16949 | } | |
16950 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 16951 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 16952 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 16953 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 16954 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 16955 | } |
ee890fe2 | 16956 | |
efdba735 | 16957 | branch_island_list = 0; |
ee890fe2 SS |
16958 | } |
16959 | ||
16960 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
16961 | already there or not. */ | |
16962 | ||
efdba735 | 16963 | static int |
a2369ed3 | 16964 | no_previous_def (tree function_name) |
ee890fe2 | 16965 | { |
efdba735 SH |
16966 | tree branch_island; |
16967 | for (branch_island = branch_island_list; | |
16968 | branch_island; | |
16969 | branch_island = TREE_CHAIN (branch_island)) | |
16970 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
16971 | return 0; |
16972 | return 1; | |
16973 | } | |
16974 | ||
16975 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
16976 | the function. */ | |
16977 | ||
efdba735 | 16978 | static tree |
a2369ed3 | 16979 | get_prev_label (tree function_name) |
ee890fe2 | 16980 | { |
efdba735 SH |
16981 | tree branch_island; |
16982 | for (branch_island = branch_island_list; | |
16983 | branch_island; | |
16984 | branch_island = TREE_CHAIN (branch_island)) | |
16985 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
16986 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
16987 | return 0; |
16988 | } | |
16989 | ||
16990 | /* INSN is either a function call or a millicode call. It may have an | |
f676971a | 16991 | unconditional jump in its delay slot. |
ee890fe2 SS |
16992 | |
16993 | CALL_DEST is the routine we are calling. */ | |
16994 | ||
16995 | char * | |
c4ad648e AM |
16996 | output_call (rtx insn, rtx *operands, int dest_operand_number, |
16997 | int cookie_operand_number) | |
ee890fe2 SS |
16998 | { |
16999 | static char buf[256]; | |
efdba735 SH |
17000 | if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF |
17001 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) | |
ee890fe2 SS |
17002 | { |
17003 | tree labelname; | |
efdba735 | 17004 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
f676971a | 17005 | |
ee890fe2 SS |
17006 | if (no_previous_def (funname)) |
17007 | { | |
308c142a | 17008 | int line_number = 0; |
ee890fe2 SS |
17009 | rtx label_rtx = gen_label_rtx (); |
17010 | char *label_buf, temp_buf[256]; | |
17011 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
17012 | CODE_LABEL_NUMBER (label_rtx)); | |
17013 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
17014 | labelname = get_identifier (label_buf); | |
17015 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
17016 | if (insn) | |
17017 | line_number = NOTE_LINE_NUMBER (insn); | |
efdba735 | 17018 | add_compiler_branch_island (labelname, funname, line_number); |
ee890fe2 SS |
17019 | } |
17020 | else | |
17021 | labelname = get_prev_label (funname); | |
17022 | ||
efdba735 SH |
17023 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
17024 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
17025 | "L42" should be a 'branch island', that will do a far jump to | |
17026 | 'foo'. Branch islands are generated in | |
17027 | macho_branch_islands(). */ | |
ee890fe2 | 17028 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 17029 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
17030 | } |
17031 | else | |
efdba735 SH |
17032 | sprintf (buf, "bl %%z%d", dest_operand_number); |
17033 | return buf; | |
ee890fe2 SS |
17034 | } |
17035 | ||
ee890fe2 SS |
17036 | /* Generate PIC and indirect symbol stubs. */ |
17037 | ||
17038 | void | |
a2369ed3 | 17039 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
17040 | { |
17041 | unsigned int length; | |
a4f6c312 SS |
17042 | char *symbol_name, *lazy_ptr_name; |
17043 | char *local_label_0; | |
ee890fe2 SS |
17044 | static int label = 0; |
17045 | ||
df56a27f | 17046 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 17047 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 17048 | |
ee890fe2 | 17049 | |
ee890fe2 SS |
17050 | length = strlen (symb); |
17051 | symbol_name = alloca (length + 32); | |
17052 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
17053 | ||
17054 | lazy_ptr_name = alloca (length + 32); | |
17055 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
17056 | ||
ee890fe2 | 17057 | if (flag_pic == 2) |
d3c300d2 | 17058 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 17059 | else |
d3c300d2 | 17060 | machopic_symbol_stub1_section (); |
ee890fe2 SS |
17061 | |
17062 | if (flag_pic == 2) | |
17063 | { | |
d974312d DJ |
17064 | fprintf (file, "\t.align 5\n"); |
17065 | ||
17066 | fprintf (file, "%s:\n", stub); | |
17067 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
17068 | ||
876455fa | 17069 | label++; |
89da1f32 | 17070 | local_label_0 = alloca (sizeof ("\"L00000000000$spb\"")); |
876455fa | 17071 | sprintf (local_label_0, "\"L%011d$spb\"", label); |
f676971a | 17072 | |
ee890fe2 SS |
17073 | fprintf (file, "\tmflr r0\n"); |
17074 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
17075 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
17076 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
17077 | lazy_ptr_name, local_label_0); | |
17078 | fprintf (file, "\tmtlr r0\n"); | |
3d0e2d58 SS |
17079 | fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n", |
17080 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
ee890fe2 SS |
17081 | lazy_ptr_name, local_label_0); |
17082 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
17083 | fprintf (file, "\tbctr\n"); |
17084 | } | |
17085 | else | |
d974312d DJ |
17086 | { |
17087 | fprintf (file, "\t.align 4\n"); | |
17088 | ||
17089 | fprintf (file, "%s:\n", stub); | |
17090 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
17091 | ||
17092 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
d9e4e4f5 SS |
17093 | fprintf (file, "\t%s r12,lo16(%s)(r11)\n", |
17094 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
17095 | lazy_ptr_name); | |
d974312d DJ |
17096 | fprintf (file, "\tmtctr r12\n"); |
17097 | fprintf (file, "\tbctr\n"); | |
17098 | } | |
f676971a | 17099 | |
ee890fe2 SS |
17100 | machopic_lazy_symbol_ptr_section (); |
17101 | fprintf (file, "%s:\n", lazy_ptr_name); | |
17102 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
49bd1d27 SS |
17103 | fprintf (file, "%sdyld_stub_binding_helper\n", |
17104 | (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t")); | |
ee890fe2 SS |
17105 | } |
17106 | ||
17107 | /* Legitimize PIC addresses. If the address is already | |
17108 | position-independent, we return ORIG. Newly generated | |
17109 | position-independent addresses go into a reg. This is REG if non | |
17110 | zero, otherwise we allocate register(s) as necessary. */ | |
17111 | ||
9390387d | 17112 | #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000) |
ee890fe2 SS |
17113 | |
17114 | rtx | |
f676971a | 17115 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
a2369ed3 | 17116 | rtx reg) |
ee890fe2 SS |
17117 | { |
17118 | rtx base, offset; | |
17119 | ||
17120 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
17121 | reg = gen_reg_rtx (Pmode); | |
17122 | ||
17123 | if (GET_CODE (orig) == CONST) | |
17124 | { | |
37409796 NS |
17125 | rtx reg_temp; |
17126 | ||
ee890fe2 SS |
17127 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
17128 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
17129 | return orig; | |
17130 | ||
37409796 NS |
17131 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
17132 | ||
17133 | /* Use a different reg for the intermediate value, as | |
17134 | it will be marked UNCHANGING. */ | |
17135 | reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); | |
17136 | base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
17137 | Pmode, reg_temp); | |
17138 | offset = | |
17139 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
17140 | Pmode, reg); | |
17141 | ||
ee890fe2 SS |
17142 | if (GET_CODE (offset) == CONST_INT) |
17143 | { | |
17144 | if (SMALL_INT (offset)) | |
ed8908e7 | 17145 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
17146 | else if (! reload_in_progress && ! reload_completed) |
17147 | offset = force_reg (Pmode, offset); | |
17148 | else | |
c859cda6 DJ |
17149 | { |
17150 | rtx mem = force_const_mem (Pmode, orig); | |
17151 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
17152 | } | |
ee890fe2 | 17153 | } |
f1c25d3b | 17154 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
17155 | } |
17156 | ||
17157 | /* Fall back on generic machopic code. */ | |
17158 | return machopic_legitimize_pic_address (orig, mode, reg); | |
17159 | } | |
17160 | ||
17161 | /* This is just a placeholder to make linking work without having to | |
17162 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
17163 | ever needed for Darwin (not too likely!) this would have to get a | |
17164 | real definition. */ | |
17165 | ||
17166 | void | |
863d938c | 17167 | toc_section (void) |
ee890fe2 SS |
17168 | { |
17169 | } | |
17170 | ||
c4e18b1c GK |
17171 | /* Output a .machine directive for the Darwin assembler, and call |
17172 | the generic start_file routine. */ | |
17173 | ||
17174 | static void | |
17175 | rs6000_darwin_file_start (void) | |
17176 | { | |
94ff898d | 17177 | static const struct |
c4e18b1c GK |
17178 | { |
17179 | const char *arg; | |
17180 | const char *name; | |
17181 | int if_set; | |
17182 | } mapping[] = { | |
55dbfb48 | 17183 | { "ppc64", "ppc64", MASK_64BIT }, |
c4e18b1c GK |
17184 | { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, |
17185 | { "power4", "ppc970", 0 }, | |
17186 | { "G5", "ppc970", 0 }, | |
17187 | { "7450", "ppc7450", 0 }, | |
17188 | { "7400", "ppc7400", MASK_ALTIVEC }, | |
17189 | { "G4", "ppc7400", 0 }, | |
17190 | { "750", "ppc750", 0 }, | |
17191 | { "740", "ppc750", 0 }, | |
17192 | { "G3", "ppc750", 0 }, | |
17193 | { "604e", "ppc604e", 0 }, | |
17194 | { "604", "ppc604", 0 }, | |
17195 | { "603e", "ppc603", 0 }, | |
17196 | { "603", "ppc603", 0 }, | |
17197 | { "601", "ppc601", 0 }, | |
17198 | { NULL, "ppc", 0 } }; | |
17199 | const char *cpu_id = ""; | |
17200 | size_t i; | |
94ff898d | 17201 | |
9390387d | 17202 | rs6000_file_start (); |
c4e18b1c GK |
17203 | |
17204 | /* Determine the argument to -mcpu=. Default to G3 if not specified. */ | |
17205 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) | |
17206 | if (rs6000_select[i].set_arch_p && rs6000_select[i].string | |
17207 | && rs6000_select[i].string[0] != '\0') | |
17208 | cpu_id = rs6000_select[i].string; | |
17209 | ||
17210 | /* Look through the mapping array. Pick the first name that either | |
17211 | matches the argument, has a bit set in IF_SET that is also set | |
17212 | in the target flags, or has a NULL name. */ | |
17213 | ||
17214 | i = 0; | |
17215 | while (mapping[i].arg != NULL | |
17216 | && strcmp (mapping[i].arg, cpu_id) != 0 | |
17217 | && (mapping[i].if_set & target_flags) == 0) | |
17218 | i++; | |
17219 | ||
17220 | fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); | |
17221 | } | |
17222 | ||
ee890fe2 | 17223 | #endif /* TARGET_MACHO */ |
7c262518 RH |
17224 | |
17225 | #if TARGET_ELF | |
17226 | static unsigned int | |
a2369ed3 | 17227 | rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) |
7c262518 | 17228 | { |
1ff8f81a AM |
17229 | return default_section_type_flags_1 (decl, name, reloc, |
17230 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 17231 | } |
d9f6800d RH |
17232 | |
17233 | /* Record an element in the table of global constructors. SYMBOL is | |
17234 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
17235 | between 0 and MAX_INIT_PRIORITY. | |
17236 | ||
17237 | This differs from default_named_section_asm_out_constructor in | |
17238 | that we have special handling for -mrelocatable. */ | |
17239 | ||
17240 | static void | |
a2369ed3 | 17241 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
17242 | { |
17243 | const char *section = ".ctors"; | |
17244 | char buf[16]; | |
17245 | ||
17246 | if (priority != DEFAULT_INIT_PRIORITY) | |
17247 | { | |
17248 | sprintf (buf, ".ctors.%.5u", | |
c4ad648e AM |
17249 | /* Invert the numbering so the linker puts us in the proper |
17250 | order; constructors are run from right to left, and the | |
17251 | linker sorts in increasing order. */ | |
17252 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
17253 | section = buf; |
17254 | } | |
17255 | ||
715bdd29 RH |
17256 | named_section_flags (section, SECTION_WRITE); |
17257 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
17258 | |
17259 | if (TARGET_RELOCATABLE) | |
17260 | { | |
17261 | fputs ("\t.long (", asm_out_file); | |
17262 | output_addr_const (asm_out_file, symbol); | |
17263 | fputs (")@fixup\n", asm_out_file); | |
17264 | } | |
17265 | else | |
c8af3574 | 17266 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
17267 | } |
17268 | ||
17269 | static void | |
a2369ed3 | 17270 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
17271 | { |
17272 | const char *section = ".dtors"; | |
17273 | char buf[16]; | |
17274 | ||
17275 | if (priority != DEFAULT_INIT_PRIORITY) | |
17276 | { | |
17277 | sprintf (buf, ".dtors.%.5u", | |
c4ad648e AM |
17278 | /* Invert the numbering so the linker puts us in the proper |
17279 | order; constructors are run from right to left, and the | |
17280 | linker sorts in increasing order. */ | |
17281 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
17282 | section = buf; |
17283 | } | |
17284 | ||
715bdd29 RH |
17285 | named_section_flags (section, SECTION_WRITE); |
17286 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
17287 | |
17288 | if (TARGET_RELOCATABLE) | |
17289 | { | |
17290 | fputs ("\t.long (", asm_out_file); | |
17291 | output_addr_const (asm_out_file, symbol); | |
17292 | fputs (")@fixup\n", asm_out_file); | |
17293 | } | |
17294 | else | |
c8af3574 | 17295 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 17296 | } |
9739c90c JJ |
17297 | |
17298 | void | |
a2369ed3 | 17299 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
17300 | { |
17301 | if (TARGET_64BIT) | |
17302 | { | |
17303 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
17304 | ASM_OUTPUT_LABEL (file, name); | |
17305 | fputs (DOUBLE_INT_ASM_OP, file); | |
85b776df AM |
17306 | rs6000_output_function_entry (file, name); |
17307 | fputs (",.TOC.@tocbase,0\n\t.previous\n", file); | |
17308 | if (DOT_SYMBOLS) | |
9739c90c | 17309 | { |
85b776df | 17310 | fputs ("\t.size\t", file); |
9739c90c | 17311 | assemble_name (file, name); |
85b776df AM |
17312 | fputs (",24\n\t.type\t.", file); |
17313 | assemble_name (file, name); | |
17314 | fputs (",@function\n", file); | |
17315 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
17316 | { | |
17317 | fputs ("\t.globl\t.", file); | |
17318 | assemble_name (file, name); | |
17319 | putc ('\n', file); | |
17320 | } | |
9739c90c | 17321 | } |
85b776df AM |
17322 | else |
17323 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
9739c90c | 17324 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); |
85b776df AM |
17325 | rs6000_output_function_entry (file, name); |
17326 | fputs (":\n", file); | |
9739c90c JJ |
17327 | return; |
17328 | } | |
17329 | ||
17330 | if (TARGET_RELOCATABLE | |
7f970b70 | 17331 | && !TARGET_SECURE_PLT |
9739c90c | 17332 | && (get_pool_size () != 0 || current_function_profile) |
3c9eb5f4 | 17333 | && uses_TOC ()) |
9739c90c JJ |
17334 | { |
17335 | char buf[256]; | |
17336 | ||
17337 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
17338 | ||
17339 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
17340 | fprintf (file, "\t.long "); | |
17341 | assemble_name (file, buf); | |
17342 | putc ('-', file); | |
17343 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
17344 | assemble_name (file, buf); | |
17345 | putc ('\n', file); | |
17346 | } | |
17347 | ||
17348 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
17349 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
17350 | ||
17351 | if (DEFAULT_ABI == ABI_AIX) | |
17352 | { | |
17353 | const char *desc_name, *orig_name; | |
17354 | ||
17355 | orig_name = (*targetm.strip_name_encoding) (name); | |
17356 | desc_name = orig_name; | |
17357 | while (*desc_name == '.') | |
17358 | desc_name++; | |
17359 | ||
17360 | if (TREE_PUBLIC (decl)) | |
17361 | fprintf (file, "\t.globl %s\n", desc_name); | |
17362 | ||
17363 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
17364 | fprintf (file, "%s:\n", desc_name); | |
17365 | fprintf (file, "\t.long %s\n", orig_name); | |
17366 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
17367 | if (DEFAULT_ABI == ABI_AIX) | |
17368 | fputs ("\t.long 0\n", file); | |
17369 | fprintf (file, "\t.previous\n"); | |
17370 | } | |
17371 | ASM_OUTPUT_LABEL (file, name); | |
17372 | } | |
1334b570 AM |
17373 | |
17374 | static void | |
17375 | rs6000_elf_end_indicate_exec_stack (void) | |
17376 | { | |
17377 | if (TARGET_32BIT) | |
17378 | file_end_indicate_exec_stack (); | |
17379 | } | |
7c262518 RH |
17380 | #endif |
17381 | ||
cbaaba19 | 17382 | #if TARGET_XCOFF |
7c262518 | 17383 | static void |
a2369ed3 | 17384 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
17385 | { |
17386 | fputs (GLOBAL_ASM_OP, stream); | |
17387 | RS6000_OUTPUT_BASENAME (stream, name); | |
17388 | putc ('\n', stream); | |
17389 | } | |
17390 | ||
17391 | static void | |
c18a5b6c MM |
17392 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags, |
17393 | tree decl ATTRIBUTE_UNUSED) | |
7c262518 | 17394 | { |
0e5dbd9b DE |
17395 | int smclass; |
17396 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
17397 | ||
17398 | if (flags & SECTION_CODE) | |
17399 | smclass = 0; | |
17400 | else if (flags & SECTION_WRITE) | |
17401 | smclass = 2; | |
17402 | else | |
17403 | smclass = 1; | |
17404 | ||
5b5198f7 | 17405 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 17406 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 17407 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 17408 | } |
ae46c4e0 RH |
17409 | |
17410 | static void | |
f676971a | 17411 | rs6000_xcoff_select_section (tree decl, int reloc, |
c4ad648e | 17412 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
ae46c4e0 | 17413 | { |
5add3202 | 17414 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 17415 | { |
0e5dbd9b | 17416 | if (TREE_PUBLIC (decl)) |
c4ad648e | 17417 | read_only_data_section (); |
ae46c4e0 | 17418 | else |
c4ad648e | 17419 | read_only_private_data_section (); |
ae46c4e0 RH |
17420 | } |
17421 | else | |
17422 | { | |
0e5dbd9b | 17423 | if (TREE_PUBLIC (decl)) |
c4ad648e | 17424 | data_section (); |
ae46c4e0 | 17425 | else |
c4ad648e | 17426 | private_data_section (); |
ae46c4e0 RH |
17427 | } |
17428 | } | |
17429 | ||
17430 | static void | |
a2369ed3 | 17431 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
17432 | { |
17433 | const char *name; | |
ae46c4e0 | 17434 | |
5b5198f7 DE |
17435 | /* Use select_section for private and uninitialized data. */ |
17436 | if (!TREE_PUBLIC (decl) | |
17437 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
17438 | || DECL_INITIAL (decl) == NULL_TREE |
17439 | || DECL_INITIAL (decl) == error_mark_node | |
17440 | || (flag_zero_initialized_in_bss | |
17441 | && initializer_zerop (DECL_INITIAL (decl)))) | |
17442 | return; | |
17443 | ||
17444 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
17445 | name = (*targetm.strip_name_encoding) (name); | |
17446 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 17447 | } |
b64a1b53 | 17448 | |
fb49053f RH |
17449 | /* Select section for constant in constant pool. |
17450 | ||
17451 | On RS/6000, all constants are in the private read-only data area. | |
17452 | However, if this is being placed in the TOC it must be output as a | |
17453 | toc entry. */ | |
17454 | ||
b64a1b53 | 17455 | static void |
f676971a | 17456 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
c4ad648e | 17457 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
b64a1b53 RH |
17458 | { |
17459 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
17460 | toc_section (); | |
17461 | else | |
17462 | read_only_private_data_section (); | |
17463 | } | |
772c5265 RH |
17464 | |
17465 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
17466 | ||
17467 | static const char * | |
a2369ed3 | 17468 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
17469 | { |
17470 | size_t len; | |
17471 | if (*name == '*') | |
17472 | name++; | |
17473 | len = strlen (name); | |
17474 | if (name[len - 1] == ']') | |
17475 | return ggc_alloc_string (name, len - 4); | |
17476 | else | |
17477 | return name; | |
17478 | } | |
17479 | ||
5add3202 DE |
17480 | /* Section attributes. AIX is always PIC. */ |
17481 | ||
17482 | static unsigned int | |
a2369ed3 | 17483 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 17484 | { |
5b5198f7 DE |
17485 | unsigned int align; |
17486 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
17487 | ||
17488 | /* Align to at least UNIT size. */ | |
17489 | if (flags & SECTION_CODE) | |
17490 | align = MIN_UNITS_PER_WORD; | |
17491 | else | |
17492 | /* Increase alignment of large objects if not already stricter. */ | |
17493 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
17494 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
17495 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
17496 | ||
17497 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 17498 | } |
a5fe455b | 17499 | |
1bc7c5b6 ZW |
17500 | /* Output at beginning of assembler file. |
17501 | ||
17502 | Initialize the section names for the RS/6000 at this point. | |
17503 | ||
17504 | Specify filename, including full path, to assembler. | |
17505 | ||
17506 | We want to go into the TOC section so at least one .toc will be emitted. | |
17507 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
17508 | [RW] section emitted. | |
17509 | ||
17510 | Finally, declare mcount when profiling to make the assembler happy. */ | |
17511 | ||
17512 | static void | |
863d938c | 17513 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
17514 | { |
17515 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
17516 | main_input_filename, ".bss_"); | |
17517 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
17518 | main_input_filename, ".rw_"); | |
17519 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
17520 | main_input_filename, ".ro_"); | |
17521 | ||
17522 | fputs ("\t.file\t", asm_out_file); | |
17523 | output_quoted_string (asm_out_file, main_input_filename); | |
17524 | fputc ('\n', asm_out_file); | |
1bc7c5b6 ZW |
17525 | if (write_symbols != NO_DEBUG) |
17526 | private_data_section (); | |
17527 | text_section (); | |
17528 | if (profile_flag) | |
17529 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
17530 | rs6000_file_start (); | |
17531 | } | |
17532 | ||
a5fe455b ZW |
17533 | /* Output at end of assembler file. |
17534 | On the RS/6000, referencing data should automatically pull in text. */ | |
17535 | ||
17536 | static void | |
863d938c | 17537 | rs6000_xcoff_file_end (void) |
a5fe455b ZW |
17538 | { |
17539 | text_section (); | |
17540 | fputs ("_section_.text:\n", asm_out_file); | |
17541 | data_section (); | |
17542 | fputs (TARGET_32BIT | |
17543 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
17544 | asm_out_file); | |
17545 | } | |
f1384257 | 17546 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 17547 | |
3c50106f RH |
17548 | /* Compute a (partial) cost for rtx X. Return true if the complete |
17549 | cost has been computed, and false if subexpressions should be | |
17550 | scanned. In either case, *TOTAL contains the cost result. */ | |
17551 | ||
17552 | static bool | |
1494c534 | 17553 | rs6000_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f | 17554 | { |
f0517163 RS |
17555 | enum machine_mode mode = GET_MODE (x); |
17556 | ||
3c50106f RH |
17557 | switch (code) |
17558 | { | |
30a555d9 | 17559 | /* On the RS/6000, if it is valid in the insn, it is free. */ |
3c50106f | 17560 | case CONST_INT: |
066cd967 DE |
17561 | if (((outer_code == SET |
17562 | || outer_code == PLUS | |
17563 | || outer_code == MINUS) | |
17564 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
17565 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))) | |
066cd967 DE |
17566 | || (outer_code == AND |
17567 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
22e54023 DE |
17568 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), |
17569 | mode == SImode ? 'L' : 'J')) | |
d5861a7a | 17570 | || mask_operand (x, VOIDmode))) |
22e54023 DE |
17571 | || ((outer_code == IOR || outer_code == XOR) |
17572 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
17573 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), | |
17574 | mode == SImode ? 'L' : 'J')))) | |
066cd967 DE |
17575 | || outer_code == ASHIFT |
17576 | || outer_code == ASHIFTRT | |
17577 | || outer_code == LSHIFTRT | |
17578 | || outer_code == ROTATE | |
17579 | || outer_code == ROTATERT | |
d5861a7a | 17580 | || outer_code == ZERO_EXTRACT |
066cd967 DE |
17581 | || (outer_code == MULT |
17582 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
22e54023 DE |
17583 | || ((outer_code == DIV || outer_code == UDIV |
17584 | || outer_code == MOD || outer_code == UMOD) | |
17585 | && exact_log2 (INTVAL (x)) >= 0) | |
066cd967 DE |
17586 | || (outer_code == COMPARE |
17587 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
22e54023 DE |
17588 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K'))) |
17589 | || (outer_code == EQ | |
17590 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
17591 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
17592 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), | |
17593 | mode == SImode ? 'L' : 'J')))) | |
17594 | || (outer_code == GTU | |
17595 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
17596 | || (outer_code == LTU | |
17597 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P'))) | |
066cd967 DE |
17598 | { |
17599 | *total = 0; | |
17600 | return true; | |
17601 | } | |
17602 | else if ((outer_code == PLUS | |
4ae234b0 | 17603 | && reg_or_add_cint_operand (x, VOIDmode)) |
066cd967 | 17604 | || (outer_code == MINUS |
4ae234b0 | 17605 | && reg_or_sub_cint_operand (x, VOIDmode)) |
066cd967 DE |
17606 | || ((outer_code == SET |
17607 | || outer_code == IOR | |
17608 | || outer_code == XOR) | |
17609 | && (INTVAL (x) | |
17610 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0)) | |
17611 | { | |
17612 | *total = COSTS_N_INSNS (1); | |
17613 | return true; | |
17614 | } | |
17615 | /* FALLTHRU */ | |
17616 | ||
17617 | case CONST_DOUBLE: | |
17618 | if (mode == DImode | |
17619 | && ((outer_code == AND | |
17620 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
17621 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L') | |
4ae234b0 | 17622 | || mask_operand (x, DImode))) |
066cd967 DE |
17623 | || ((outer_code == IOR || outer_code == XOR) |
17624 | && CONST_DOUBLE_HIGH (x) == 0 | |
17625 | && (CONST_DOUBLE_LOW (x) | |
17626 | & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0))) | |
17627 | { | |
17628 | *total = 0; | |
17629 | return true; | |
17630 | } | |
17631 | else if (mode == DImode | |
17632 | && (outer_code == SET | |
17633 | || outer_code == IOR | |
17634 | || outer_code == XOR) | |
17635 | && CONST_DOUBLE_HIGH (x) == 0) | |
17636 | { | |
17637 | *total = COSTS_N_INSNS (1); | |
17638 | return true; | |
17639 | } | |
17640 | /* FALLTHRU */ | |
17641 | ||
3c50106f | 17642 | case CONST: |
066cd967 | 17643 | case HIGH: |
3c50106f | 17644 | case SYMBOL_REF: |
066cd967 DE |
17645 | case MEM: |
17646 | /* When optimizing for size, MEM should be slightly more expensive | |
17647 | than generating address, e.g., (plus (reg) (const)). | |
c112cf2b | 17648 | L1 cache latency is about two instructions. */ |
066cd967 | 17649 | *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); |
3c50106f RH |
17650 | return true; |
17651 | ||
30a555d9 DE |
17652 | case LABEL_REF: |
17653 | *total = 0; | |
17654 | return true; | |
17655 | ||
3c50106f | 17656 | case PLUS: |
f0517163 | 17657 | if (mode == DFmode) |
066cd967 DE |
17658 | { |
17659 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
17660 | { | |
17661 | /* FNMA accounted in outer NEG. */ | |
17662 | if (outer_code == NEG) | |
17663 | *total = rs6000_cost->dmul - rs6000_cost->fp; | |
17664 | else | |
17665 | *total = rs6000_cost->dmul; | |
17666 | } | |
17667 | else | |
17668 | *total = rs6000_cost->fp; | |
17669 | } | |
f0517163 | 17670 | else if (mode == SFmode) |
066cd967 DE |
17671 | { |
17672 | /* FNMA accounted in outer NEG. */ | |
17673 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
17674 | *total = 0; | |
17675 | else | |
17676 | *total = rs6000_cost->fp; | |
17677 | } | |
938bf747 RS |
17678 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
17679 | { | |
17680 | /* The rs6000 doesn't have shift-and-add instructions. */ | |
17681 | rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total); | |
17682 | *total += COSTS_N_INSNS (1); | |
17683 | } | |
f0517163 | 17684 | else |
066cd967 DE |
17685 | *total = COSTS_N_INSNS (1); |
17686 | return false; | |
3c50106f | 17687 | |
52190329 | 17688 | case MINUS: |
f0517163 | 17689 | if (mode == DFmode) |
066cd967 DE |
17690 | { |
17691 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
17692 | { | |
17693 | /* FNMA accounted in outer NEG. */ | |
17694 | if (outer_code == NEG) | |
17695 | *total = 0; | |
17696 | else | |
17697 | *total = rs6000_cost->dmul; | |
17698 | } | |
17699 | else | |
17700 | *total = rs6000_cost->fp; | |
17701 | } | |
f0517163 | 17702 | else if (mode == SFmode) |
066cd967 DE |
17703 | { |
17704 | /* FNMA accounted in outer NEG. */ | |
17705 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
17706 | *total = 0; | |
17707 | else | |
17708 | *total = rs6000_cost->fp; | |
17709 | } | |
938bf747 RS |
17710 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
17711 | { | |
17712 | /* The rs6000 doesn't have shift-and-sub instructions. */ | |
17713 | rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total); | |
17714 | *total += COSTS_N_INSNS (1); | |
17715 | } | |
f0517163 | 17716 | else |
c4ad648e | 17717 | *total = COSTS_N_INSNS (1); |
066cd967 | 17718 | return false; |
3c50106f RH |
17719 | |
17720 | case MULT: | |
c9dbf840 DE |
17721 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
17722 | && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I')) | |
3c50106f | 17723 | { |
8b897cfa RS |
17724 | if (INTVAL (XEXP (x, 1)) >= -256 |
17725 | && INTVAL (XEXP (x, 1)) <= 255) | |
06a67bdd | 17726 | *total = rs6000_cost->mulsi_const9; |
8b897cfa | 17727 | else |
06a67bdd | 17728 | *total = rs6000_cost->mulsi_const; |
3c50106f | 17729 | } |
066cd967 DE |
17730 | /* FMA accounted in outer PLUS/MINUS. */ |
17731 | else if ((mode == DFmode || mode == SFmode) | |
17732 | && (outer_code == PLUS || outer_code == MINUS)) | |
17733 | *total = 0; | |
f0517163 | 17734 | else if (mode == DFmode) |
06a67bdd | 17735 | *total = rs6000_cost->dmul; |
f0517163 | 17736 | else if (mode == SFmode) |
06a67bdd | 17737 | *total = rs6000_cost->fp; |
f0517163 | 17738 | else if (mode == DImode) |
06a67bdd | 17739 | *total = rs6000_cost->muldi; |
8b897cfa | 17740 | else |
06a67bdd | 17741 | *total = rs6000_cost->mulsi; |
066cd967 | 17742 | return false; |
3c50106f RH |
17743 | |
17744 | case DIV: | |
17745 | case MOD: | |
f0517163 RS |
17746 | if (FLOAT_MODE_P (mode)) |
17747 | { | |
06a67bdd RS |
17748 | *total = mode == DFmode ? rs6000_cost->ddiv |
17749 | : rs6000_cost->sdiv; | |
066cd967 | 17750 | return false; |
f0517163 | 17751 | } |
5efb1046 | 17752 | /* FALLTHRU */ |
3c50106f RH |
17753 | |
17754 | case UDIV: | |
17755 | case UMOD: | |
627b6fe2 DJ |
17756 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
17757 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
17758 | { | |
17759 | if (code == DIV || code == MOD) | |
17760 | /* Shift, addze */ | |
17761 | *total = COSTS_N_INSNS (2); | |
17762 | else | |
17763 | /* Shift */ | |
17764 | *total = COSTS_N_INSNS (1); | |
17765 | } | |
c4ad648e | 17766 | else |
627b6fe2 DJ |
17767 | { |
17768 | if (GET_MODE (XEXP (x, 1)) == DImode) | |
17769 | *total = rs6000_cost->divdi; | |
17770 | else | |
17771 | *total = rs6000_cost->divsi; | |
17772 | } | |
17773 | /* Add in shift and subtract for MOD. */ | |
17774 | if (code == MOD || code == UMOD) | |
17775 | *total += COSTS_N_INSNS (2); | |
066cd967 | 17776 | return false; |
3c50106f RH |
17777 | |
17778 | case FFS: | |
17779 | *total = COSTS_N_INSNS (4); | |
066cd967 | 17780 | return false; |
3c50106f | 17781 | |
06a67bdd | 17782 | case NOT: |
066cd967 DE |
17783 | if (outer_code == AND || outer_code == IOR || outer_code == XOR) |
17784 | { | |
17785 | *total = 0; | |
17786 | return false; | |
17787 | } | |
17788 | /* FALLTHRU */ | |
17789 | ||
17790 | case AND: | |
17791 | case IOR: | |
17792 | case XOR: | |
d5861a7a DE |
17793 | case ZERO_EXTRACT: |
17794 | *total = COSTS_N_INSNS (1); | |
17795 | return false; | |
17796 | ||
066cd967 DE |
17797 | case ASHIFT: |
17798 | case ASHIFTRT: | |
17799 | case LSHIFTRT: | |
17800 | case ROTATE: | |
17801 | case ROTATERT: | |
d5861a7a | 17802 | /* Handle mul_highpart. */ |
066cd967 DE |
17803 | if (outer_code == TRUNCATE |
17804 | && GET_CODE (XEXP (x, 0)) == MULT) | |
17805 | { | |
17806 | if (mode == DImode) | |
17807 | *total = rs6000_cost->muldi; | |
17808 | else | |
17809 | *total = rs6000_cost->mulsi; | |
17810 | return true; | |
17811 | } | |
d5861a7a DE |
17812 | else if (outer_code == AND) |
17813 | *total = 0; | |
17814 | else | |
17815 | *total = COSTS_N_INSNS (1); | |
17816 | return false; | |
17817 | ||
17818 | case SIGN_EXTEND: | |
17819 | case ZERO_EXTEND: | |
17820 | if (GET_CODE (XEXP (x, 0)) == MEM) | |
17821 | *total = 0; | |
17822 | else | |
17823 | *total = COSTS_N_INSNS (1); | |
066cd967 | 17824 | return false; |
06a67bdd | 17825 | |
066cd967 DE |
17826 | case COMPARE: |
17827 | case NEG: | |
17828 | case ABS: | |
17829 | if (!FLOAT_MODE_P (mode)) | |
17830 | { | |
17831 | *total = COSTS_N_INSNS (1); | |
17832 | return false; | |
17833 | } | |
17834 | /* FALLTHRU */ | |
17835 | ||
17836 | case FLOAT: | |
17837 | case UNSIGNED_FLOAT: | |
17838 | case FIX: | |
17839 | case UNSIGNED_FIX: | |
17840 | case FLOAT_EXTEND: | |
06a67bdd RS |
17841 | case FLOAT_TRUNCATE: |
17842 | *total = rs6000_cost->fp; | |
066cd967 | 17843 | return false; |
06a67bdd RS |
17844 | |
17845 | case UNSPEC: | |
17846 | switch (XINT (x, 1)) | |
17847 | { | |
17848 | case UNSPEC_FRSP: | |
17849 | *total = rs6000_cost->fp; | |
17850 | return true; | |
17851 | ||
17852 | default: | |
17853 | break; | |
17854 | } | |
17855 | break; | |
17856 | ||
17857 | case CALL: | |
17858 | case IF_THEN_ELSE: | |
17859 | if (optimize_size) | |
17860 | { | |
17861 | *total = COSTS_N_INSNS (1); | |
17862 | return true; | |
17863 | } | |
066cd967 DE |
17864 | else if (FLOAT_MODE_P (mode) |
17865 | && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS) | |
17866 | { | |
17867 | *total = rs6000_cost->fp; | |
17868 | return false; | |
17869 | } | |
06a67bdd RS |
17870 | break; |
17871 | ||
c0600ecd DE |
17872 | case EQ: |
17873 | case GTU: | |
17874 | case LTU: | |
22e54023 DE |
17875 | /* Carry bit requires mode == Pmode. |
17876 | NEG or PLUS already counted so only add one. */ | |
17877 | if (mode == Pmode | |
17878 | && (outer_code == NEG || outer_code == PLUS)) | |
c0600ecd | 17879 | { |
22e54023 DE |
17880 | *total = COSTS_N_INSNS (1); |
17881 | return true; | |
17882 | } | |
17883 | if (outer_code == SET) | |
17884 | { | |
17885 | if (XEXP (x, 1) == const0_rtx) | |
c0600ecd | 17886 | { |
22e54023 | 17887 | *total = COSTS_N_INSNS (2); |
c0600ecd | 17888 | return true; |
c0600ecd | 17889 | } |
22e54023 DE |
17890 | else if (mode == Pmode) |
17891 | { | |
17892 | *total = COSTS_N_INSNS (3); | |
17893 | return false; | |
17894 | } | |
17895 | } | |
17896 | /* FALLTHRU */ | |
17897 | ||
17898 | case GT: | |
17899 | case LT: | |
17900 | case UNORDERED: | |
17901 | if (outer_code == SET && (XEXP (x, 1) == const0_rtx)) | |
17902 | { | |
17903 | *total = COSTS_N_INSNS (2); | |
17904 | return true; | |
c0600ecd | 17905 | } |
22e54023 DE |
17906 | /* CC COMPARE. */ |
17907 | if (outer_code == COMPARE) | |
17908 | { | |
17909 | *total = 0; | |
17910 | return true; | |
17911 | } | |
17912 | break; | |
c0600ecd | 17913 | |
3c50106f | 17914 | default: |
06a67bdd | 17915 | break; |
3c50106f | 17916 | } |
06a67bdd RS |
17917 | |
17918 | return false; | |
3c50106f RH |
17919 | } |
17920 | ||
34bb030a DE |
17921 | /* A C expression returning the cost of moving data from a register of class |
17922 | CLASS1 to one of CLASS2. */ | |
17923 | ||
17924 | int | |
f676971a | 17925 | rs6000_register_move_cost (enum machine_mode mode, |
a2369ed3 | 17926 | enum reg_class from, enum reg_class to) |
34bb030a DE |
17927 | { |
17928 | /* Moves from/to GENERAL_REGS. */ | |
17929 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
17930 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
17931 | { | |
17932 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
17933 | from = to; | |
17934 | ||
17935 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
17936 | return (rs6000_memory_move_cost (mode, from, 0) | |
17937 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
17938 | ||
c4ad648e AM |
17939 | /* It's more expensive to move CR_REGS than CR0_REGS because of the |
17940 | shift. */ | |
34bb030a DE |
17941 | else if (from == CR_REGS) |
17942 | return 4; | |
17943 | ||
17944 | else | |
c4ad648e | 17945 | /* A move will cost one instruction per GPR moved. */ |
c8b622ff | 17946 | return 2 * hard_regno_nregs[0][mode]; |
34bb030a DE |
17947 | } |
17948 | ||
c4ad648e | 17949 | /* Moving between two similar registers is just one instruction. */ |
34bb030a DE |
17950 | else if (reg_classes_intersect_p (to, from)) |
17951 | return mode == TFmode ? 4 : 2; | |
17952 | ||
c4ad648e | 17953 | /* Everything else has to go through GENERAL_REGS. */ |
34bb030a | 17954 | else |
f676971a | 17955 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) |
34bb030a DE |
17956 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); |
17957 | } | |
17958 | ||
17959 | /* A C expressions returning the cost of moving data of MODE from a register to | |
17960 | or from memory. */ | |
17961 | ||
17962 | int | |
f676971a | 17963 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, |
a2369ed3 | 17964 | int in ATTRIBUTE_UNUSED) |
34bb030a DE |
17965 | { |
17966 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
c8b622ff | 17967 | return 4 * hard_regno_nregs[0][mode]; |
34bb030a | 17968 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) |
c8b622ff | 17969 | return 4 * hard_regno_nregs[32][mode]; |
34bb030a | 17970 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) |
c8b622ff | 17971 | return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode]; |
34bb030a DE |
17972 | else |
17973 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
17974 | } | |
17975 | ||
ef765ea9 DE |
17976 | /* Newton-Raphson approximation of single-precision floating point divide n/d. |
17977 | Assumes no trapping math and finite arguments. */ | |
17978 | ||
17979 | void | |
17980 | rs6000_emit_swdivsf (rtx res, rtx n, rtx d) | |
17981 | { | |
17982 | rtx x0, e0, e1, y1, u0, v0, one; | |
17983 | ||
17984 | x0 = gen_reg_rtx (SFmode); | |
17985 | e0 = gen_reg_rtx (SFmode); | |
17986 | e1 = gen_reg_rtx (SFmode); | |
17987 | y1 = gen_reg_rtx (SFmode); | |
17988 | u0 = gen_reg_rtx (SFmode); | |
17989 | v0 = gen_reg_rtx (SFmode); | |
17990 | one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode)); | |
17991 | ||
17992 | /* x0 = 1./d estimate */ | |
17993 | emit_insn (gen_rtx_SET (VOIDmode, x0, | |
17994 | gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d), | |
17995 | UNSPEC_FRES))); | |
17996 | /* e0 = 1. - d * x0 */ | |
17997 | emit_insn (gen_rtx_SET (VOIDmode, e0, | |
17998 | gen_rtx_MINUS (SFmode, one, | |
17999 | gen_rtx_MULT (SFmode, d, x0)))); | |
18000 | /* e1 = e0 + e0 * e0 */ | |
18001 | emit_insn (gen_rtx_SET (VOIDmode, e1, | |
18002 | gen_rtx_PLUS (SFmode, | |
18003 | gen_rtx_MULT (SFmode, e0, e0), e0))); | |
18004 | /* y1 = x0 + e1 * x0 */ | |
18005 | emit_insn (gen_rtx_SET (VOIDmode, y1, | |
18006 | gen_rtx_PLUS (SFmode, | |
18007 | gen_rtx_MULT (SFmode, e1, x0), x0))); | |
18008 | /* u0 = n * y1 */ | |
18009 | emit_insn (gen_rtx_SET (VOIDmode, u0, | |
18010 | gen_rtx_MULT (SFmode, n, y1))); | |
18011 | /* v0 = n - d * u0 */ | |
18012 | emit_insn (gen_rtx_SET (VOIDmode, v0, | |
18013 | gen_rtx_MINUS (SFmode, n, | |
18014 | gen_rtx_MULT (SFmode, d, u0)))); | |
18015 | /* res = u0 + v0 * y1 */ | |
18016 | emit_insn (gen_rtx_SET (VOIDmode, res, | |
18017 | gen_rtx_PLUS (SFmode, | |
18018 | gen_rtx_MULT (SFmode, v0, y1), u0))); | |
18019 | } | |
18020 | ||
18021 | /* Newton-Raphson approximation of double-precision floating point divide n/d. | |
18022 | Assumes no trapping math and finite arguments. */ | |
18023 | ||
18024 | void | |
18025 | rs6000_emit_swdivdf (rtx res, rtx n, rtx d) | |
18026 | { | |
18027 | rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one; | |
18028 | ||
18029 | x0 = gen_reg_rtx (DFmode); | |
18030 | e0 = gen_reg_rtx (DFmode); | |
18031 | e1 = gen_reg_rtx (DFmode); | |
18032 | e2 = gen_reg_rtx (DFmode); | |
18033 | y1 = gen_reg_rtx (DFmode); | |
18034 | y2 = gen_reg_rtx (DFmode); | |
18035 | y3 = gen_reg_rtx (DFmode); | |
18036 | u0 = gen_reg_rtx (DFmode); | |
18037 | v0 = gen_reg_rtx (DFmode); | |
18038 | one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode)); | |
18039 | ||
18040 | /* x0 = 1./d estimate */ | |
18041 | emit_insn (gen_rtx_SET (VOIDmode, x0, | |
18042 | gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d), | |
18043 | UNSPEC_FRES))); | |
18044 | /* e0 = 1. - d * x0 */ | |
18045 | emit_insn (gen_rtx_SET (VOIDmode, e0, | |
18046 | gen_rtx_MINUS (DFmode, one, | |
18047 | gen_rtx_MULT (SFmode, d, x0)))); | |
18048 | /* y1 = x0 + e0 * x0 */ | |
18049 | emit_insn (gen_rtx_SET (VOIDmode, y1, | |
18050 | gen_rtx_PLUS (DFmode, | |
18051 | gen_rtx_MULT (DFmode, e0, x0), x0))); | |
18052 | /* e1 = e0 * e0 */ | |
18053 | emit_insn (gen_rtx_SET (VOIDmode, e1, | |
18054 | gen_rtx_MULT (DFmode, e0, e0))); | |
18055 | /* y2 = y1 + e1 * y1 */ | |
18056 | emit_insn (gen_rtx_SET (VOIDmode, y2, | |
18057 | gen_rtx_PLUS (DFmode, | |
18058 | gen_rtx_MULT (DFmode, e1, y1), y1))); | |
18059 | /* e2 = e1 * e1 */ | |
18060 | emit_insn (gen_rtx_SET (VOIDmode, e2, | |
18061 | gen_rtx_MULT (DFmode, e1, e1))); | |
18062 | /* y3 = y2 + e2 * y2 */ | |
18063 | emit_insn (gen_rtx_SET (VOIDmode, y3, | |
18064 | gen_rtx_PLUS (DFmode, | |
18065 | gen_rtx_MULT (DFmode, e2, y2), y2))); | |
18066 | /* u0 = n * y3 */ | |
18067 | emit_insn (gen_rtx_SET (VOIDmode, u0, | |
18068 | gen_rtx_MULT (DFmode, n, y3))); | |
18069 | /* v0 = n - d * u0 */ | |
18070 | emit_insn (gen_rtx_SET (VOIDmode, v0, | |
18071 | gen_rtx_MINUS (DFmode, n, | |
18072 | gen_rtx_MULT (DFmode, d, u0)))); | |
18073 | /* res = u0 + v0 * y3 */ | |
18074 | emit_insn (gen_rtx_SET (VOIDmode, res, | |
18075 | gen_rtx_PLUS (DFmode, | |
18076 | gen_rtx_MULT (DFmode, v0, y3), u0))); | |
18077 | } | |
18078 | ||
ded9bf77 AH |
18079 | /* Return an RTX representing where to find the function value of a |
18080 | function returning MODE. */ | |
18081 | static rtx | |
18082 | rs6000_complex_function_value (enum machine_mode mode) | |
18083 | { | |
18084 | unsigned int regno; | |
18085 | rtx r1, r2; | |
18086 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 18087 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 | 18088 | |
18f63bfa AH |
18089 | if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
18090 | regno = FP_ARG_RETURN; | |
354ed18f AH |
18091 | else |
18092 | { | |
18f63bfa | 18093 | regno = GP_ARG_RETURN; |
ded9bf77 | 18094 | |
18f63bfa AH |
18095 | /* 32-bit is OK since it'll go in r3/r4. */ |
18096 | if (TARGET_32BIT && inner_bytes >= 4) | |
ded9bf77 AH |
18097 | return gen_rtx_REG (mode, regno); |
18098 | } | |
18099 | ||
18f63bfa AH |
18100 | if (inner_bytes >= 8) |
18101 | return gen_rtx_REG (mode, regno); | |
18102 | ||
ded9bf77 AH |
18103 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
18104 | const0_rtx); | |
18105 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 18106 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
18107 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
18108 | } | |
18109 | ||
a6ebc39a AH |
18110 | /* Define how to find the value returned by a function. |
18111 | VALTYPE is the data type of the value (as a tree). | |
18112 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
18113 | otherwise, FUNC is 0. | |
18114 | ||
18115 | On the SPE, both FPs and vectors are returned in r3. | |
18116 | ||
18117 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
18118 | fp1, unless -msoft-float. */ | |
18119 | ||
18120 | rtx | |
18121 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
18122 | { | |
18123 | enum machine_mode mode; | |
2a8fa26c | 18124 | unsigned int regno; |
a6ebc39a | 18125 | |
594a51fe SS |
18126 | /* Special handling for structs in darwin64. */ |
18127 | if (rs6000_darwin64_abi | |
18128 | && TYPE_MODE (valtype) == BLKmode | |
0b5383eb DJ |
18129 | && TREE_CODE (valtype) == RECORD_TYPE |
18130 | && int_size_in_bytes (valtype) > 0) | |
594a51fe SS |
18131 | { |
18132 | CUMULATIVE_ARGS valcum; | |
18133 | rtx valret; | |
18134 | ||
0b5383eb | 18135 | valcum.words = 0; |
594a51fe SS |
18136 | valcum.fregno = FP_ARG_MIN_REG; |
18137 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
0b5383eb DJ |
18138 | /* Do a trial code generation as if this were going to be passed as |
18139 | an argument; if any part goes in memory, we return NULL. */ | |
18140 | valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true); | |
594a51fe SS |
18141 | if (valret) |
18142 | return valret; | |
18143 | /* Otherwise fall through to standard ABI rules. */ | |
18144 | } | |
18145 | ||
0e67400a FJ |
18146 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
18147 | { | |
18148 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
18149 | return gen_rtx_PARALLEL (DImode, | |
18150 | gen_rtvec (2, | |
18151 | gen_rtx_EXPR_LIST (VOIDmode, | |
18152 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
18153 | const0_rtx), | |
18154 | gen_rtx_EXPR_LIST (VOIDmode, | |
18155 | gen_rtx_REG (SImode, | |
18156 | GP_ARG_RETURN + 1), | |
18157 | GEN_INT (4)))); | |
18158 | } | |
18159 | ||
a6ebc39a AH |
18160 | if ((INTEGRAL_TYPE_P (valtype) |
18161 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
18162 | || POINTER_TYPE_P (valtype)) | |
b78d48dd | 18163 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a AH |
18164 | else |
18165 | mode = TYPE_MODE (valtype); | |
18166 | ||
4ed78545 | 18167 | if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) |
2a8fa26c | 18168 | regno = FP_ARG_RETURN; |
ded9bf77 | 18169 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
42ba5130 | 18170 | && targetm.calls.split_complex_arg) |
ded9bf77 | 18171 | return rs6000_complex_function_value (mode); |
44688022 | 18172 | else if (TREE_CODE (valtype) == VECTOR_TYPE |
d0b2079e | 18173 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI |
23ba09f0 | 18174 | && ALTIVEC_VECTOR_MODE (mode)) |
a6ebc39a | 18175 | regno = ALTIVEC_ARG_RETURN; |
18f63bfa AH |
18176 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
18177 | && (mode == DFmode || mode == DCmode)) | |
18178 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
a6ebc39a AH |
18179 | else |
18180 | regno = GP_ARG_RETURN; | |
18181 | ||
18182 | return gen_rtx_REG (mode, regno); | |
18183 | } | |
18184 | ||
ded9bf77 AH |
18185 | /* Define how to find the value returned by a library function |
18186 | assuming the value has mode MODE. */ | |
18187 | rtx | |
18188 | rs6000_libcall_value (enum machine_mode mode) | |
18189 | { | |
18190 | unsigned int regno; | |
18191 | ||
2e6c9641 FJ |
18192 | if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode) |
18193 | { | |
18194 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
18195 | return gen_rtx_PARALLEL (DImode, | |
18196 | gen_rtvec (2, | |
18197 | gen_rtx_EXPR_LIST (VOIDmode, | |
18198 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
18199 | const0_rtx), | |
18200 | gen_rtx_EXPR_LIST (VOIDmode, | |
18201 | gen_rtx_REG (SImode, | |
18202 | GP_ARG_RETURN + 1), | |
18203 | GEN_INT (4)))); | |
18204 | } | |
18205 | ||
ded9bf77 AH |
18206 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
18207 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
18208 | regno = FP_ARG_RETURN; | |
44688022 AM |
18209 | else if (ALTIVEC_VECTOR_MODE (mode) |
18210 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
ded9bf77 | 18211 | regno = ALTIVEC_ARG_RETURN; |
42ba5130 | 18212 | else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) |
ded9bf77 | 18213 | return rs6000_complex_function_value (mode); |
18f63bfa AH |
18214 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
18215 | && (mode == DFmode || mode == DCmode)) | |
18216 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
ded9bf77 AH |
18217 | else |
18218 | regno = GP_ARG_RETURN; | |
18219 | ||
18220 | return gen_rtx_REG (mode, regno); | |
18221 | } | |
18222 | ||
d1d0c603 JJ |
18223 | /* Define the offset between two registers, FROM to be eliminated and its |
18224 | replacement TO, at the start of a routine. */ | |
18225 | HOST_WIDE_INT | |
18226 | rs6000_initial_elimination_offset (int from, int to) | |
18227 | { | |
18228 | rs6000_stack_t *info = rs6000_stack_info (); | |
18229 | HOST_WIDE_INT offset; | |
18230 | ||
18231 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
18232 | offset = info->push_p ? 0 : -info->total_size; | |
18233 | else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
18234 | offset = info->total_size; | |
18235 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
18236 | offset = info->push_p ? info->total_size : 0; | |
18237 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
18238 | offset = 0; | |
18239 | else | |
37409796 | 18240 | gcc_unreachable (); |
d1d0c603 JJ |
18241 | |
18242 | return offset; | |
18243 | } | |
18244 | ||
58646b77 | 18245 | /* Return true if TYPE is a SPE or AltiVec opaque type. */ |
62e1dfcf | 18246 | |
c8e4f0e9 | 18247 | static bool |
58646b77 | 18248 | rs6000_is_opaque_type (tree type) |
62e1dfcf | 18249 | { |
58646b77 | 18250 | return (type == opaque_V2SI_type_node |
2abe3e28 | 18251 | || type == opaque_V2SF_type_node |
58646b77 PB |
18252 | || type == opaque_p_V2SI_type_node |
18253 | || type == opaque_V4SI_type_node); | |
62e1dfcf NC |
18254 | } |
18255 | ||
96714395 | 18256 | static rtx |
a2369ed3 | 18257 | rs6000_dwarf_register_span (rtx reg) |
96714395 AH |
18258 | { |
18259 | unsigned regno; | |
18260 | ||
4d4cbc0e AH |
18261 | if (TARGET_SPE |
18262 | && (SPE_VECTOR_MODE (GET_MODE (reg)) | |
18263 | || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode))) | |
18264 | ; | |
18265 | else | |
96714395 AH |
18266 | return NULL_RTX; |
18267 | ||
18268 | regno = REGNO (reg); | |
18269 | ||
18270 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
18271 | This is a way of distinguishing r0 in 32-bits from r0 in | |
18272 | 64-bits. */ | |
18273 | return | |
18274 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
18275 | BYTES_BIG_ENDIAN |
18276 | ? gen_rtvec (2, | |
18277 | gen_rtx_REG (SImode, regno + 1200), | |
18278 | gen_rtx_REG (SImode, regno)) | |
18279 | : gen_rtvec (2, | |
18280 | gen_rtx_REG (SImode, regno), | |
18281 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
18282 | } |
18283 | ||
93c9d1ba AM |
18284 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
18285 | ||
18286 | unsigned int | |
18287 | rs6000_dbx_register_number (unsigned int regno) | |
18288 | { | |
18289 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
18290 | return regno; | |
18291 | if (regno == MQ_REGNO) | |
18292 | return 100; | |
18293 | if (regno == LINK_REGISTER_REGNUM) | |
18294 | return 108; | |
18295 | if (regno == COUNT_REGISTER_REGNUM) | |
18296 | return 109; | |
18297 | if (CR_REGNO_P (regno)) | |
18298 | return regno - CR0_REGNO + 86; | |
18299 | if (regno == XER_REGNO) | |
18300 | return 101; | |
18301 | if (ALTIVEC_REGNO_P (regno)) | |
18302 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
18303 | if (regno == VRSAVE_REGNO) | |
18304 | return 356; | |
18305 | if (regno == VSCR_REGNO) | |
18306 | return 67; | |
18307 | if (regno == SPE_ACC_REGNO) | |
18308 | return 99; | |
18309 | if (regno == SPEFSCR_REGNO) | |
18310 | return 612; | |
18311 | /* SPE high reg number. We get these values of regno from | |
18312 | rs6000_dwarf_register_span. */ | |
37409796 NS |
18313 | gcc_assert (regno >= 1200 && regno < 1232); |
18314 | return regno; | |
93c9d1ba AM |
18315 | } |
18316 | ||
93f90be6 | 18317 | /* target hook eh_return_filter_mode */ |
f676971a | 18318 | static enum machine_mode |
93f90be6 FJ |
18319 | rs6000_eh_return_filter_mode (void) |
18320 | { | |
18321 | return TARGET_32BIT ? SImode : word_mode; | |
18322 | } | |
18323 | ||
f676971a EC |
18324 | /* Target hook for vector_mode_supported_p. */ |
18325 | static bool | |
18326 | rs6000_vector_mode_supported_p (enum machine_mode mode) | |
18327 | { | |
18328 | ||
18329 | if (TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
18330 | return true; | |
18331 | ||
18332 | else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
18333 | return true; | |
18334 | ||
18335 | else | |
18336 | return false; | |
18337 | } | |
18338 | ||
4d3e6fae FJ |
18339 | /* Target hook for invalid_arg_for_unprototyped_fn. */ |
18340 | static const char * | |
18341 | invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val) | |
18342 | { | |
18343 | return (!rs6000_darwin64_abi | |
18344 | && typelist == 0 | |
18345 | && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE | |
18346 | && (funcdecl == NULL_TREE | |
18347 | || (TREE_CODE (funcdecl) == FUNCTION_DECL | |
18348 | && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD))) | |
18349 | ? N_("AltiVec argument passed to unprototyped function") | |
18350 | : NULL; | |
18351 | } | |
18352 | ||
17211ab5 | 18353 | #include "gt-rs6000.h" |