]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/rs6000/rs6000.c
projects / thirdparty / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
c-common.c (resolve_overloaded_builtin): Forward to target hook for BUILT_IN_MD built...
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.c
CommitLineData
9878760c 1/* Subroutines used for code generation on IBM RS/6000.
f676971a 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5b86a469 3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
fab3bcc3 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
9878760c 5
5de601cf 6 This file is part of GCC.
9878760c 7
5de601cf
NC		 8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
9878760c 12
5de601cf
NC		 13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
9878760c 17
5de601cf
NC		 18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
9878760c 22
956d6950 23#include "config.h"
c4d38ccb 24#include "system.h"
4977bab6
ZW		 25#include "coretypes.h"
26#include "tm.h"
9878760c
RK		 27#include "rtl.h"
28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
9878760c
RK		 33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
9878760c 36#include "obstack.h"
9b30bae2 37#include "tree.h"
dfafc897 38#include "expr.h"
2fc1c679 39#include "optabs.h"
2a430ec1 40#include "except.h"
a7df97e6 41#include "function.h"
296b8152 42#include "output.h"
d5fa86ba 43#include "basic-block.h"
d0101753 44#include "integrate.h"
296b8152 45#include "toplev.h"
c8023011 46#include "ggc.h"
9ebbca7d
GK		 47#include "hashtab.h"
48#include "tm_p.h"
672a6f42
NB		 49#include "target.h"
50#include "target-def.h"
3ac88239 51#include "langhooks.h"
24ea750e 52#include "reload.h"
117dca74 53#include "cfglayout.h"
79ae11c4 54#include "sched-int.h"
cd3ce9b4 55#include "tree-gimple.h"
4d3e6fae 56#include "intl.h"
1bc7c5b6
ZW		 57#if TARGET_XCOFF
58#include "xcoffout.h" /* get declarations of xcoff_*_section_name */
59#endif
93a27b7b
ZW		 60#if TARGET_MACHO
61#include "gstab.h" /* for N_SLINE */
62#endif
9b30bae2 63
7509c759
MM		 64#ifndef TARGET_NO_PROTOTYPE
65#define TARGET_NO_PROTOTYPE 0
66#endif
67
9878760c
RK		 68#define min(A,B) ((A) < (B) ? (A) : (B))
69#define max(A,B) ((A) > (B) ? (A) : (B))
70
d1d0c603
JJ		 71/* Structure used to define the rs6000 stack */
72typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
c4ad648e 82 int world_save_p; /* true if we're saving *everything*:
d62294f5 83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
d1d0c603
JJ		 84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
108 not in save_size */
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
114} rs6000_stack_t;
115
5248c961
RK		 116/* Target cpu type */
117
118enum processor_type rs6000_cpu;
8e3f41e7
MM		 119struct rs6000_cpu_select rs6000_select[3] =
120{
815cdc52
MM		 121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
8e3f41e7 125};
5248c961 126
ec507f2d
DE		 127/* Always emit branch hint bits. */
128static GTY(()) bool rs6000_always_hint;
129
130/* Schedule instructions for group formation. */
131static GTY(()) bool rs6000_sched_groups;
132
f676971a 133/* Support adjust_priority scheduler hook
79ae11c4
DN		 134 and -mprioritize-restricted-insns= option. */
135const char *rs6000_sched_restricted_insns_priority_str;
136int rs6000_sched_restricted_insns_priority;
137
569fa502
DN		 138/* Support for -msched-costly-dep option. */
139const char *rs6000_sched_costly_dep_str;
140enum rs6000_dependence_cost rs6000_sched_costly_dep;
141
cbe26ab8
DN		 142/* Support for -minsert-sched-nops option. */
143const char *rs6000_sched_insert_nops_str;
144enum rs6000_nop_insertion rs6000_sched_insert_nops;
145
7ccf35ed 146/* Support targetm.vectorize.builtin_mask_for_load. */
13c62176 147static GTY(()) tree altivec_builtin_mask_for_load;
7ccf35ed 148
6fa3f289
ZW		 149/* Size of long double */
150const char *rs6000_long_double_size_string;
151int rs6000_long_double_type_size;
152
153/* Whether -mabi=altivec has appeared */
154int rs6000_altivec_abi;
155
08b57fb3
AH		 156/* Whether VRSAVE instructions should be generated. */
157int rs6000_altivec_vrsave;
158
159/* String from -mvrsave= option. */
160const char *rs6000_altivec_vrsave_string;
161
a3170dc6
AH		 162/* Nonzero if we want SPE ABI extensions. */
163int rs6000_spe_abi;
164
165/* Whether isel instructions should be generated. */
166int rs6000_isel;
167
993f19a8
AH		 168/* Whether SPE simd instructions should be generated. */
169int rs6000_spe;
170
5da702b1
AH		 171/* Nonzero if floating point operations are done in the GPRs. */
172int rs6000_float_gprs = 0;
173
594a51fe
SS		 174/* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175int rs6000_darwin64_abi;
176
5da702b1
AH		 177/* String from -mfloat-gprs=. */
178const char *rs6000_float_gprs_string;
a3170dc6
AH		 179
180/* String from -misel=. */
181const char *rs6000_isel_string;
182
993f19a8
AH		 183/* String from -mspe=. */
184const char *rs6000_spe_string;
185
a0ab749a 186/* Set to nonzero once AIX common-mode calls have been defined. */
bbfb86aa 187static GTY(()) int common_mode_defined;
c81bebd7 188
9878760c
RK		 189/* Save information from a "cmpxx" operation until the branch or scc is
190 emitted. */
9878760c
RK		 191rtx rs6000_compare_op0, rs6000_compare_op1;
192int rs6000_compare_fp_p;
874a0744 193
874a0744
MM		 194/* Label number of label created for -mrelocatable, to call to so we can
195 get the address of the GOT section */
196int rs6000_pic_labelno;
c81bebd7 197
b91da81f 198#ifdef USING_ELFOS_H
c81bebd7 199/* Which abi to adhere to */
9739c90c 200const char *rs6000_abi_name;
d9407988
MM		 201
202/* Semantics of the small data area */
203enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
204
205/* Which small data model to use */
815cdc52 206const char *rs6000_sdata_name = (char *)0;
9ebbca7d
GK		 207
208/* Counter for labels which are to be placed in .fixup. */
209int fixuplabelno = 0;
874a0744 210#endif
4697a36c 211
c4501e62
JJ		 212/* Bit size of immediate TLS offsets and string from which it is decoded. */
213int rs6000_tls_size = 32;
214const char *rs6000_tls_size_string;
215
b6c9286a
MM		 216/* ABI enumeration available for subtarget to use. */
217enum rs6000_abi rs6000_current_abi;
218
0ac081f6
AH		 219/* ABI string from -mabi= option. */
220const char *rs6000_abi_string;
221
85b776df
AM		 222/* Whether to use variant of AIX ABI for PowerPC64 Linux. */
223int dot_symbols;
224
38c1f2d7 225/* Debug flags */
815cdc52 226const char *rs6000_debug_name;
38c1f2d7
MM		 227int rs6000_debug_stack; /* debug stack applications */
228int rs6000_debug_arg; /* debug argument handling */
229
aabcd309 230/* Value is TRUE if register/mode pair is acceptable. */
0d1fbc8c
AH		 231bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
232
58646b77
PB		 233/* Built in types. */
234
235tree rs6000_builtin_types[RS6000_BTI_MAX];
236tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
8bb418a3
ZL		 237
238int rs6000_warn_altivec_long = 1; /* On by default. */
239const char *rs6000_warn_altivec_long_switch;
240
57ac7be9
AM		 241const char *rs6000_traceback_name;
242static enum {
243 traceback_default = 0,
244 traceback_none,
245 traceback_part,
246 traceback_full
247} rs6000_traceback;
248
38c1f2d7
MM		 249/* Flag to say the TOC is initialized */
250int toc_initialized;
9ebbca7d 251char toc_label_name[10];
38c1f2d7 252
9ebbca7d 253/* Alias set for saves and restores from the rs6000 stack. */
f103e34d 254static GTY(()) int rs6000_sr_alias_set;
c8023011 255
a5c76ee6
ZW		 256/* Call distance, overridden by -mlongcall and #pragma longcall(1).
257 The only place that looks at this is rs6000_set_default_type_attributes;
258 everywhere else should rely on the presence or absence of a longcall
3eb4e360
AM		 259 attribute on the function declaration. Exception: init_cumulative_args
260 looks at it too, for libcalls. */
a5c76ee6
ZW		 261int rs6000_default_long_calls;
262const char *rs6000_longcall_switch;
263
a3c9585f
KH		 264/* Control alignment for fields within structures. */
265/* String from -malign-XXXXX. */
025d9908
KH		 266const char *rs6000_alignment_string;
267int rs6000_alignment_flags;
268
a3170dc6
AH		 269struct builtin_description
270{
271 /* mask is not const because we're going to alter it below. This
272 nonsense will go away when we rewrite the -march infrastructure
273 to give us more target flag bits. */
274 unsigned int mask;
275 const enum insn_code icode;
276 const char *const name;
277 const enum rs6000_builtins code;
278};
8b897cfa
RS		 279\f
280/* Target cpu costs. */
281
282struct processor_costs {
c4ad648e 283 const int mulsi; /* cost of SImode multiplication. */
8b897cfa
RS		 284 const int mulsi_const; /* cost of SImode multiplication by constant. */
285 const int mulsi_const9; /* cost of SImode mult by short constant. */
c4ad648e
AM		 286 const int muldi; /* cost of DImode multiplication. */
287 const int divsi; /* cost of SImode division. */
288 const int divdi; /* cost of DImode division. */
289 const int fp; /* cost of simple SFmode and DFmode insns. */
290 const int dmul; /* cost of DFmode multiplication (and fmadd). */
291 const int sdiv; /* cost of SFmode division (fdivs). */
292 const int ddiv; /* cost of DFmode division (fdiv). */
8b897cfa
RS		 293};
294
295const struct processor_costs *rs6000_cost;
296
297/* Processor costs (relative to an add) */
298
299/* Instruction size costs on 32bit processors. */
300static const
301struct processor_costs size32_cost = {
06a67bdd
RS		 302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 312};
313
314/* Instruction size costs on 64bit processors. */
315static const
316struct processor_costs size64_cost = {
06a67bdd
RS		 317 COSTS_N_INSNS (1), /* mulsi */
318 COSTS_N_INSNS (1), /* mulsi_const */
319 COSTS_N_INSNS (1), /* mulsi_const9 */
320 COSTS_N_INSNS (1), /* muldi */
321 COSTS_N_INSNS (1), /* divsi */
322 COSTS_N_INSNS (1), /* divdi */
323 COSTS_N_INSNS (1), /* fp */
324 COSTS_N_INSNS (1), /* dmul */
325 COSTS_N_INSNS (1), /* sdiv */
326 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 327};
328
329/* Instruction costs on RIOS1 processors. */
330static const
331struct processor_costs rios1_cost = {
06a67bdd
RS		 332 COSTS_N_INSNS (5), /* mulsi */
333 COSTS_N_INSNS (4), /* mulsi_const */
334 COSTS_N_INSNS (3), /* mulsi_const9 */
335 COSTS_N_INSNS (5), /* muldi */
336 COSTS_N_INSNS (19), /* divsi */
337 COSTS_N_INSNS (19), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (19), /* sdiv */
341 COSTS_N_INSNS (19), /* ddiv */
8b897cfa
RS		 342};
343
344/* Instruction costs on RIOS2 processors. */
345static const
346struct processor_costs rios2_cost = {
06a67bdd
RS		 347 COSTS_N_INSNS (2), /* mulsi */
348 COSTS_N_INSNS (2), /* mulsi_const */
349 COSTS_N_INSNS (2), /* mulsi_const9 */
350 COSTS_N_INSNS (2), /* muldi */
351 COSTS_N_INSNS (13), /* divsi */
352 COSTS_N_INSNS (13), /* divdi */
353 COSTS_N_INSNS (2), /* fp */
354 COSTS_N_INSNS (2), /* dmul */
355 COSTS_N_INSNS (17), /* sdiv */
356 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 357};
358
359/* Instruction costs on RS64A processors. */
360static const
361struct processor_costs rs64a_cost = {
06a67bdd
RS		 362 COSTS_N_INSNS (20), /* mulsi */
363 COSTS_N_INSNS (12), /* mulsi_const */
364 COSTS_N_INSNS (8), /* mulsi_const9 */
365 COSTS_N_INSNS (34), /* muldi */
366 COSTS_N_INSNS (65), /* divsi */
367 COSTS_N_INSNS (67), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (4), /* dmul */
370 COSTS_N_INSNS (31), /* sdiv */
371 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 372};
373
374/* Instruction costs on MPCCORE processors. */
375static const
376struct processor_costs mpccore_cost = {
06a67bdd
RS		 377 COSTS_N_INSNS (2), /* mulsi */
378 COSTS_N_INSNS (2), /* mulsi_const */
379 COSTS_N_INSNS (2), /* mulsi_const9 */
380 COSTS_N_INSNS (2), /* muldi */
381 COSTS_N_INSNS (6), /* divsi */
382 COSTS_N_INSNS (6), /* divdi */
383 COSTS_N_INSNS (4), /* fp */
384 COSTS_N_INSNS (5), /* dmul */
385 COSTS_N_INSNS (10), /* sdiv */
386 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 387};
388
389/* Instruction costs on PPC403 processors. */
390static const
391struct processor_costs ppc403_cost = {
06a67bdd
RS		 392 COSTS_N_INSNS (4), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (4), /* mulsi_const9 */
395 COSTS_N_INSNS (4), /* muldi */
396 COSTS_N_INSNS (33), /* divsi */
397 COSTS_N_INSNS (33), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 402};
403
404/* Instruction costs on PPC405 processors. */
405static const
406struct processor_costs ppc405_cost = {
06a67bdd
RS		 407 COSTS_N_INSNS (5), /* mulsi */
408 COSTS_N_INSNS (4), /* mulsi_const */
409 COSTS_N_INSNS (3), /* mulsi_const9 */
410 COSTS_N_INSNS (5), /* muldi */
411 COSTS_N_INSNS (35), /* divsi */
412 COSTS_N_INSNS (35), /* divdi */
413 COSTS_N_INSNS (11), /* fp */
414 COSTS_N_INSNS (11), /* dmul */
415 COSTS_N_INSNS (11), /* sdiv */
416 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 417};
418
419/* Instruction costs on PPC440 processors. */
420static const
421struct processor_costs ppc440_cost = {
06a67bdd
RS		 422 COSTS_N_INSNS (3), /* mulsi */
423 COSTS_N_INSNS (2), /* mulsi_const */
424 COSTS_N_INSNS (2), /* mulsi_const9 */
425 COSTS_N_INSNS (3), /* muldi */
426 COSTS_N_INSNS (34), /* divsi */
427 COSTS_N_INSNS (34), /* divdi */
428 COSTS_N_INSNS (5), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (19), /* sdiv */
431 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 432};
433
434/* Instruction costs on PPC601 processors. */
435static const
436struct processor_costs ppc601_cost = {
06a67bdd
RS		 437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (5), /* mulsi_const */
439 COSTS_N_INSNS (5), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (36), /* divsi */
442 COSTS_N_INSNS (36), /* divdi */
443 COSTS_N_INSNS (4), /* fp */
444 COSTS_N_INSNS (5), /* dmul */
445 COSTS_N_INSNS (17), /* sdiv */
446 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 447};
448
449/* Instruction costs on PPC603 processors. */
450static const
451struct processor_costs ppc603_cost = {
06a67bdd
RS		 452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (3), /* mulsi_const */
454 COSTS_N_INSNS (2), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (37), /* divsi */
457 COSTS_N_INSNS (37), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (4), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 462};
463
464/* Instruction costs on PPC604 processors. */
465static const
466struct processor_costs ppc604_cost = {
06a67bdd
RS		 467 COSTS_N_INSNS (4), /* mulsi */
468 COSTS_N_INSNS (4), /* mulsi_const */
469 COSTS_N_INSNS (4), /* mulsi_const9 */
470 COSTS_N_INSNS (4), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 477};
478
479/* Instruction costs on PPC604e processors. */
480static const
481struct processor_costs ppc604e_cost = {
06a67bdd
RS		 482 COSTS_N_INSNS (2), /* mulsi */
483 COSTS_N_INSNS (2), /* mulsi_const */
484 COSTS_N_INSNS (2), /* mulsi_const9 */
485 COSTS_N_INSNS (2), /* muldi */
486 COSTS_N_INSNS (20), /* divsi */
487 COSTS_N_INSNS (20), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 492};
493
f0517163 494/* Instruction costs on PPC620 processors. */
8b897cfa
RS		 495static const
496struct processor_costs ppc620_cost = {
06a67bdd
RS		 497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (18), /* sdiv */
506 COSTS_N_INSNS (32), /* ddiv */
f0517163
RS		 507};
508
509/* Instruction costs on PPC630 processors. */
510static const
511struct processor_costs ppc630_cost = {
06a67bdd
RS		 512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (4), /* mulsi_const */
514 COSTS_N_INSNS (3), /* mulsi_const9 */
515 COSTS_N_INSNS (7), /* muldi */
516 COSTS_N_INSNS (21), /* divsi */
517 COSTS_N_INSNS (37), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (21), /* ddiv */
8b897cfa
RS		 522};
523
524/* Instruction costs on PPC750 and PPC7400 processors. */
525static const
526struct processor_costs ppc750_cost = {
06a67bdd
RS		 527 COSTS_N_INSNS (5), /* mulsi */
528 COSTS_N_INSNS (3), /* mulsi_const */
529 COSTS_N_INSNS (2), /* mulsi_const9 */
530 COSTS_N_INSNS (5), /* muldi */
531 COSTS_N_INSNS (17), /* divsi */
532 COSTS_N_INSNS (17), /* divdi */
533 COSTS_N_INSNS (3), /* fp */
534 COSTS_N_INSNS (3), /* dmul */
535 COSTS_N_INSNS (17), /* sdiv */
536 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 537};
538
539/* Instruction costs on PPC7450 processors. */
540static const
541struct processor_costs ppc7450_cost = {
06a67bdd
RS		 542 COSTS_N_INSNS (4), /* mulsi */
543 COSTS_N_INSNS (3), /* mulsi_const */
544 COSTS_N_INSNS (3), /* mulsi_const9 */
545 COSTS_N_INSNS (4), /* muldi */
546 COSTS_N_INSNS (23), /* divsi */
547 COSTS_N_INSNS (23), /* divdi */
548 COSTS_N_INSNS (5), /* fp */
549 COSTS_N_INSNS (5), /* dmul */
550 COSTS_N_INSNS (21), /* sdiv */
551 COSTS_N_INSNS (35), /* ddiv */
8b897cfa 552};
a3170dc6 553
8b897cfa
RS		 554/* Instruction costs on PPC8540 processors. */
555static const
556struct processor_costs ppc8540_cost = {
06a67bdd
RS		 557 COSTS_N_INSNS (4), /* mulsi */
558 COSTS_N_INSNS (4), /* mulsi_const */
559 COSTS_N_INSNS (4), /* mulsi_const9 */
560 COSTS_N_INSNS (4), /* muldi */
561 COSTS_N_INSNS (19), /* divsi */
562 COSTS_N_INSNS (19), /* divdi */
563 COSTS_N_INSNS (4), /* fp */
564 COSTS_N_INSNS (4), /* dmul */
565 COSTS_N_INSNS (29), /* sdiv */
566 COSTS_N_INSNS (29), /* ddiv */
8b897cfa
RS		 567};
568
569/* Instruction costs on POWER4 and POWER5 processors. */
570static const
571struct processor_costs power4_cost = {
06a67bdd
RS		 572 COSTS_N_INSNS (3), /* mulsi */
573 COSTS_N_INSNS (2), /* mulsi_const */
574 COSTS_N_INSNS (2), /* mulsi_const9 */
575 COSTS_N_INSNS (4), /* muldi */
576 COSTS_N_INSNS (18), /* divsi */
577 COSTS_N_INSNS (34), /* divdi */
578 COSTS_N_INSNS (3), /* fp */
579 COSTS_N_INSNS (3), /* dmul */
580 COSTS_N_INSNS (17), /* sdiv */
581 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 582};
583
584\f
a2369ed3 585static bool rs6000_function_ok_for_sibcall (tree, tree);
a2369ed3
DJ		 586static rtx rs6000_generate_compare (enum rtx_code);
587static void rs6000_maybe_dead (rtx);
588static void rs6000_emit_stack_tie (void);
589static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
590static rtx spe_synthesize_frame_save (rtx);
591static bool spe_func_has_64bit_regs_p (void);
b20a9cca 592static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
d1d0c603 593 int, HOST_WIDE_INT);
a2369ed3
DJ		 594static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
595static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
596static unsigned rs6000_hash_constant (rtx);
597static unsigned toc_hash_function (const void *);
598static int toc_hash_eq (const void *, const void *);
599static int constant_pool_expr_1 (rtx, int *, int *);
600static bool constant_pool_expr_p (rtx);
a2369ed3 601static bool legitimate_small_data_p (enum machine_mode, rtx);
a2369ed3 602static bool legitimate_indexed_address_p (rtx, int);
a2369ed3
DJ		 603static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
604static struct machine_function * rs6000_init_machine_status (void);
605static bool rs6000_assemble_integer (rtx, unsigned int, int);
5add3202 606#ifdef HAVE_GAS_HIDDEN
a2369ed3 607static void rs6000_assemble_visibility (tree, int);
5add3202 608#endif
a2369ed3
DJ		 609static int rs6000_ra_ever_killed (void);
610static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
8bb418a3 611static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
76d2b81d 612static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
f18eca82 613static const char *rs6000_mangle_fundamental_type (tree);
b86fe7b4 614extern const struct attribute_spec rs6000_attribute_table[];
a2369ed3
DJ		 615static void rs6000_set_default_type_attributes (tree);
616static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
617static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
b20a9cca
AM		 618static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
619 tree);
a2369ed3 620static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
c6e8c921 621static bool rs6000_return_in_memory (tree, tree);
a2369ed3 622static void rs6000_file_start (void);
7c262518 623#if TARGET_ELF
a2369ed3
DJ		 624static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
625static void rs6000_elf_asm_out_constructor (rtx, int);
626static void rs6000_elf_asm_out_destructor (rtx, int);
1334b570 627static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
a2369ed3
DJ		 628static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
629static void rs6000_elf_unique_section (tree, int);
630static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
b20a9cca 631 unsigned HOST_WIDE_INT);
a56d7372 632static void rs6000_elf_encode_section_info (tree, rtx, int)
0e5dbd9b 633 ATTRIBUTE_UNUSED;
a2369ed3 634static bool rs6000_elf_in_small_data_p (tree);
7c262518 635#endif
cbaaba19 636#if TARGET_XCOFF
a2369ed3 637static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
8210e4c4 638static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
a2369ed3
DJ		 639static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
640static void rs6000_xcoff_unique_section (tree, int);
641static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
b20a9cca 642 unsigned HOST_WIDE_INT);
a2369ed3
DJ		 643static const char * rs6000_xcoff_strip_name_encoding (const char *);
644static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
645static void rs6000_xcoff_file_start (void);
646static void rs6000_xcoff_file_end (void);
f1384257
AM		 647#endif
648#if TARGET_MACHO
a2369ed3 649static bool rs6000_binds_local_p (tree);
f1384257 650#endif
a2369ed3
DJ		 651static int rs6000_variable_issue (FILE *, int, rtx, int);
652static bool rs6000_rtx_costs (rtx, int, int, int *);
653static int rs6000_adjust_cost (rtx, rtx, rtx, int);
cbe26ab8 654static bool is_microcoded_insn (rtx);
79ae11c4 655static int is_dispatch_slot_restricted (rtx);
cbe26ab8
DN		 656static bool is_cracked_insn (rtx);
657static bool is_branch_slot_insn (rtx);
a2369ed3
DJ		 658static int rs6000_adjust_priority (rtx, int);
659static int rs6000_issue_rate (void);
569fa502 660static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
cbe26ab8
DN		 661static rtx get_next_active_insn (rtx, rtx);
662static bool insn_terminates_group_p (rtx , enum group_termination);
663static bool is_costly_group (rtx *, rtx);
664static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
665static int redefine_groups (FILE *, int, rtx, rtx);
666static int pad_groups (FILE *, int, rtx, rtx);
667static void rs6000_sched_finish (FILE *, int);
a2369ed3 668static int rs6000_use_sched_lookahead (void);
7ccf35ed 669static tree rs6000_builtin_mask_for_load (void);
a2369ed3 670
58646b77 671static void def_builtin (int, const char *, tree, int);
a2369ed3
DJ		 672static void rs6000_init_builtins (void);
673static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
674static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
675static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
676static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
677static void altivec_init_builtins (void);
678static void rs6000_common_init_builtins (void);
c15c90bb 679static void rs6000_init_libfuncs (void);
a2369ed3 680
b20a9cca
AM		 681static void enable_mask_for_builtins (struct builtin_description *, int,
682 enum rs6000_builtins,
683 enum rs6000_builtins);
7c62e993 684static tree build_opaque_vector_type (tree, int);
a2369ed3
DJ		 685static void spe_init_builtins (void);
686static rtx spe_expand_builtin (tree, rtx, bool *);
61bea3b0 687static rtx spe_expand_stv_builtin (enum insn_code, tree);
a2369ed3
DJ		 688static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
689static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
690static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
d1d0c603
JJ		 691static rs6000_stack_t *rs6000_stack_info (void);
692static void debug_stack_info (rs6000_stack_t *);
a2369ed3
DJ		 693
694static rtx altivec_expand_builtin (tree, rtx, bool *);
695static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
696static rtx altivec_expand_st_builtin (tree, rtx, bool *);
697static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
698static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
f676971a 699static rtx altivec_expand_predicate_builtin (enum insn_code,
c4ad648e 700 const char *, tree, rtx);
b4a62fa0 701static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
a2369ed3
DJ		 702static rtx altivec_expand_stv_builtin (enum insn_code, tree);
703static void rs6000_parse_abi_options (void);
704static void rs6000_parse_alignment_option (void);
705static void rs6000_parse_tls_size_option (void);
5da702b1 706static void rs6000_parse_yes_no_option (const char *, const char *, int *);
4d4cbc0e 707static void rs6000_parse_float_gprs_option (void);
a2369ed3
DJ		 708static int first_altivec_reg_to_save (void);
709static unsigned int compute_vrsave_mask (void);
9390387d 710static void compute_save_world_info (rs6000_stack_t *info_ptr);
a2369ed3
DJ		 711static void is_altivec_return_reg (rtx, void *);
712static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
713int easy_vector_constant (rtx, enum machine_mode);
58646b77 714static bool rs6000_is_opaque_type (tree);
a2369ed3
DJ		 715static rtx rs6000_dwarf_register_span (rtx);
716static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
717static rtx rs6000_tls_get_addr (void);
718static rtx rs6000_got_sym (void);
9390387d 719static int rs6000_tls_symbol_ref_1 (rtx *, void *);
a2369ed3
DJ		 720static const char *rs6000_get_some_local_dynamic_name (void);
721static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
ded9bf77 722static rtx rs6000_complex_function_value (enum machine_mode);
b20a9cca 723static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
a2369ed3 724 enum machine_mode, tree);
0b5383eb
DJ		 725static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
726 HOST_WIDE_INT);
727static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
728 tree, HOST_WIDE_INT);
729static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
730 HOST_WIDE_INT,
731 rtx[], int *);
732static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
733 tree, HOST_WIDE_INT,
734 rtx[], int *);
735static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
ec6376ab 736static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
b1917422 737static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
c6e8c921
GK		 738static void setup_incoming_varargs (CUMULATIVE_ARGS *,
739 enum machine_mode, tree,
740 int *, int);
8cd5a4e0
RH		 741static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
742 tree, bool);
78a52f11
RH		 743static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
744 tree, bool);
4d3e6fae 745static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
efdba735
SH		 746#if TARGET_MACHO
747static void macho_branch_islands (void);
748static void add_compiler_branch_island (tree, tree, int);
749static int no_previous_def (tree function_name);
750static tree get_prev_label (tree function_name);
c4e18b1c 751static void rs6000_darwin_file_start (void);
efdba735
SH		 752#endif
753
c35d187f 754static tree rs6000_build_builtin_va_list (void);
23a60a04 755static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
fe984136 756static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
f676971a 757static bool rs6000_vector_mode_supported_p (enum machine_mode);
94ff898d 758static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
21213b4c 759 enum machine_mode);
94ff898d 760static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
21213b4c
DP		 761 enum machine_mode);
762static int get_vsel_insn (enum machine_mode);
763static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
17211ab5 764
21213b4c
DP		 765
766const int INSN_NOT_AVAILABLE = -1;
93f90be6
FJ		 767static enum machine_mode rs6000_eh_return_filter_mode (void);
768
17211ab5
GK		 769/* Hash table stuff for keeping track of TOC entries. */
770
771struct toc_hash_struct GTY(())
772{
773 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
774 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
775 rtx key;
776 enum machine_mode key_mode;
777 int labelno;
778};
779
780static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
c81bebd7
MM		 781\f
782/* Default register names. */
783char rs6000_reg_names[][8] =
784{
802a0058
MM		 785 "0", "1", "2", "3", "4", "5", "6", "7",
786 "8", "9", "10", "11", "12", "13", "14", "15",
787 "16", "17", "18", "19", "20", "21", "22", "23",
788 "24", "25", "26", "27", "28", "29", "30", "31",
789 "0", "1", "2", "3", "4", "5", "6", "7",
790 "8", "9", "10", "11", "12", "13", "14", "15",
791 "16", "17", "18", "19", "20", "21", "22", "23",
792 "24", "25", "26", "27", "28", "29", "30", "31",
793 "mq", "lr", "ctr","ap",
794 "0", "1", "2", "3", "4", "5", "6", "7",
0ac081f6
AH		 795 "xer",
796 /* AltiVec registers. */
0cd5e3a1
AH		 797 "0", "1", "2", "3", "4", "5", "6", "7",
798 "8", "9", "10", "11", "12", "13", "14", "15",
799 "16", "17", "18", "19", "20", "21", "22", "23",
800 "24", "25", "26", "27", "28", "29", "30", "31",
59a4c851
AH		 801 "vrsave", "vscr",
802 /* SPE registers. */
803 "spe_acc", "spefscr"
c81bebd7
MM		 804};
805
806#ifdef TARGET_REGNAMES
8b60264b 807static const char alt_reg_names[][8] =
c81bebd7 808{
802a0058
MM		 809 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
810 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
811 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
812 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
813 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
814 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
815 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
816 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
817 "mq", "lr", "ctr", "ap",
818 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
0ac081f6 819 "xer",
59a4c851 820 /* AltiVec registers. */
0ac081f6 821 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
59a4c851
AH		 822 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
823 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
824 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
825 "vrsave", "vscr",
826 /* SPE registers. */
827 "spe_acc", "spefscr"
c81bebd7
MM		 828};
829#endif
9878760c 830\f
daf11973
MM		 831#ifndef MASK_STRICT_ALIGN
832#define MASK_STRICT_ALIGN 0
833#endif
ffcfcb5f
AM		 834#ifndef TARGET_PROFILE_KERNEL
835#define TARGET_PROFILE_KERNEL 0
836#endif
3961e8fe
RH		 837
838/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
839#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
672a6f42
NB		 840\f
841/* Initialize the GCC target structure. */
91d231cb
JM		 842#undef TARGET_ATTRIBUTE_TABLE
843#define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
a5c76ee6
ZW		 844#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
845#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
daf11973 846
301d03af
RS		 847#undef TARGET_ASM_ALIGNED_DI_OP
848#define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
849
850/* Default unaligned ops are only provided for ELF. Find the ops needed
851 for non-ELF systems. */
852#ifndef OBJECT_FORMAT_ELF
cbaaba19 853#if TARGET_XCOFF
ae6c1efd 854/* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
301d03af
RS		 855 64-bit targets. */
856#undef TARGET_ASM_UNALIGNED_HI_OP
857#define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
858#undef TARGET_ASM_UNALIGNED_SI_OP
859#define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
860#undef TARGET_ASM_UNALIGNED_DI_OP
861#define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
862#else
863/* For Darwin. */
864#undef TARGET_ASM_UNALIGNED_HI_OP
865#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
866#undef TARGET_ASM_UNALIGNED_SI_OP
867#define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
49bd1d27
SS		 868#undef TARGET_ASM_UNALIGNED_DI_OP
869#define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
870#undef TARGET_ASM_ALIGNED_DI_OP
871#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
301d03af
RS		 872#endif
873#endif
874
875/* This hook deals with fixups for relocatable code and DI-mode objects
876 in 64-bit code. */
877#undef TARGET_ASM_INTEGER
878#define TARGET_ASM_INTEGER rs6000_assemble_integer
879
93638d7a
AM		 880#ifdef HAVE_GAS_HIDDEN
881#undef TARGET_ASM_ASSEMBLE_VISIBILITY
882#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
883#endif
884
c4501e62
JJ		 885#undef TARGET_HAVE_TLS
886#define TARGET_HAVE_TLS HAVE_AS_TLS
887
888#undef TARGET_CANNOT_FORCE_CONST_MEM
889#define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
890
08c148a8
NB		 891#undef TARGET_ASM_FUNCTION_PROLOGUE
892#define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
893#undef TARGET_ASM_FUNCTION_EPILOGUE
894#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
895
b54cf83a
DE		 896#undef TARGET_SCHED_VARIABLE_ISSUE
897#define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
898
c237e94a
ZW		 899#undef TARGET_SCHED_ISSUE_RATE
900#define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
901#undef TARGET_SCHED_ADJUST_COST
902#define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
903#undef TARGET_SCHED_ADJUST_PRIORITY
904#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
f676971a 905#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
569fa502 906#define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
cbe26ab8
DN		 907#undef TARGET_SCHED_FINISH
908#define TARGET_SCHED_FINISH rs6000_sched_finish
c237e94a 909
be12c2b0
VM		 910#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
911#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
912
7ccf35ed
DN		 913#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
914#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
915
0ac081f6
AH		 916#undef TARGET_INIT_BUILTINS
917#define TARGET_INIT_BUILTINS rs6000_init_builtins
918
919#undef TARGET_EXPAND_BUILTIN
920#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
921
f18eca82
ZL		 922#undef TARGET_MANGLE_FUNDAMENTAL_TYPE
923#define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
924
c15c90bb
ZW		 925#undef TARGET_INIT_LIBFUNCS
926#define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
927
f1384257 928#if TARGET_MACHO
0e5dbd9b
DE		 929#undef TARGET_BINDS_LOCAL_P
930#define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
f1384257 931#endif
0e5dbd9b 932
3961e8fe
RH		 933#undef TARGET_ASM_OUTPUT_MI_THUNK
934#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
935
3961e8fe 936#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5b71a4e7 937#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
00b960c7 938
4977bab6
ZW		 939#undef TARGET_FUNCTION_OK_FOR_SIBCALL
940#define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
941
3c50106f
RH		 942#undef TARGET_RTX_COSTS
943#define TARGET_RTX_COSTS rs6000_rtx_costs
dcefdf67
RH		 944#undef TARGET_ADDRESS_COST
945#define TARGET_ADDRESS_COST hook_int_rtx_0
3c50106f 946
c8e4f0e9 947#undef TARGET_VECTOR_OPAQUE_P
58646b77 948#define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
62e1dfcf 949
96714395
AH		 950#undef TARGET_DWARF_REGISTER_SPAN
951#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
952
c6e8c921
GK		 953/* On rs6000, function arguments are promoted, as are function return
954 values. */
955#undef TARGET_PROMOTE_FUNCTION_ARGS
956#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
957#undef TARGET_PROMOTE_FUNCTION_RETURN
958#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
959
c6e8c921
GK		 960#undef TARGET_RETURN_IN_MEMORY
961#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
962
963#undef TARGET_SETUP_INCOMING_VARARGS
964#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
965
966/* Always strict argument naming on rs6000. */
967#undef TARGET_STRICT_ARGUMENT_NAMING
968#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
969#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
970#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
42ba5130
RH		 971#undef TARGET_SPLIT_COMPLEX_ARG
972#define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
fe984136
RH		 973#undef TARGET_MUST_PASS_IN_STACK
974#define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
8cd5a4e0
RH		 975#undef TARGET_PASS_BY_REFERENCE
976#define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
78a52f11
RH		 977#undef TARGET_ARG_PARTIAL_BYTES
978#define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
c6e8c921 979
c35d187f
RH		 980#undef TARGET_BUILD_BUILTIN_VA_LIST
981#define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
982
cd3ce9b4
JM		 983#undef TARGET_GIMPLIFY_VA_ARG_EXPR
984#define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
985
93f90be6
FJ		 986#undef TARGET_EH_RETURN_FILTER_MODE
987#define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
988
f676971a
EC		 989#undef TARGET_VECTOR_MODE_SUPPORTED_P
990#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
991
4d3e6fae
FJ		 992#undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
993#define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
994
445cf5eb
JM		 995/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
996 The PowerPC architecture requires only weak consistency among
997 processors--that is, memory accesses between processors need not be
998 sequentially consistent and memory accesses among processors can occur
999 in any order. The ability to order memory accesses weakly provides
1000 opportunities for more efficient use of the system bus. Unless a
1001 dependency exists, the 604e allows read operations to precede store
1002 operations. */
1003#undef TARGET_RELAXED_ORDERING
1004#define TARGET_RELAXED_ORDERING true
1005
f6897b10 1006struct gcc_target targetm = TARGET_INITIALIZER;
672a6f42 1007\f
0d1fbc8c
AH		 1008
1009/* Value is 1 if hard register REGNO can hold a value of machine-mode
1010 MODE. */
1011static int
1012rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1013{
1014 /* The GPRs can hold any mode, but values bigger than one register
1015 cannot go past R31. */
1016 if (INT_REGNO_P (regno))
1017 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1018
1019 /* The float registers can only hold floating modes and DImode. */
1020 if (FP_REGNO_P (regno))
1021 return
1022 (GET_MODE_CLASS (mode) == MODE_FLOAT
1023 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1024 || (GET_MODE_CLASS (mode) == MODE_INT
1025 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1026
1027 /* The CR register can only hold CC modes. */
1028 if (CR_REGNO_P (regno))
1029 return GET_MODE_CLASS (mode) == MODE_CC;
1030
1031 if (XER_REGNO_P (regno))
1032 return mode == PSImode;
1033
1034 /* AltiVec only in AldyVec registers. */
1035 if (ALTIVEC_REGNO_P (regno))
1036 return ALTIVEC_VECTOR_MODE (mode);
1037
1038 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1039 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1040 return 1;
1041
1042 /* We cannot put TImode anywhere except general register and it must be
1043 able to fit within the register set. */
1044
1045 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1046}
1047
1048/* Initialize rs6000_hard_regno_mode_ok_p table. */
1049static void
1050rs6000_init_hard_regno_mode_ok (void)
1051{
1052 int r, m;
1053
1054 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1055 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1056 if (rs6000_hard_regno_mode_ok (r, m))
1057 rs6000_hard_regno_mode_ok_p[m][r] = true;
1058}
1059
c1e55850
GK		 1060/* If not otherwise specified by a target, make 'long double' equivalent to
1061 'double'. */
1062
1063#ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1064#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1065#endif
1066
5248c961
RK		 1067/* Override command line options. Mostly we process the processor
1068 type and sometimes adjust other TARGET_ options. */
1069
1070void
d779d0dc 1071rs6000_override_options (const char *default_cpu)
5248c961 1072{
c4d38ccb 1073 size_t i, j;
8e3f41e7 1074 struct rs6000_cpu_select *ptr;
66188a7e 1075 int set_masks;
5248c961 1076
66188a7e 1077 /* Simplifications for entries below. */
85638c0d 1078
66188a7e
GK		 1079 enum {
1080 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1081 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1082 };
85638c0d 1083
66188a7e
GK		 1084 /* This table occasionally claims that a processor does not support
1085 a particular feature even though it does, but the feature is slower
1086 than the alternative. Thus, it shouldn't be relied on as a
f676971a 1087 complete description of the processor's support.
66188a7e
GK		 1088
1089 Please keep this list in order, and don't forget to update the
1090 documentation in invoke.texi when adding a new processor or
1091 flag. */
5248c961
RK		 1092 static struct ptt
1093 {
8b60264b
KG		 1094 const char *const name; /* Canonical processor name. */
1095 const enum processor_type processor; /* Processor type enum value. */
1096 const int target_enable; /* Target flags to enable. */
8b60264b 1097 } const processor_target_table[]
66188a7e 1098 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
49a0b204 1099 {"403", PROCESSOR_PPC403,
66188a7e
GK		 1100 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1101 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1102 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1103 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1104 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1105 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
5248c961 1106 {"601", PROCESSOR_PPC601,
66188a7e
GK		 1107 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1108 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1109 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1110 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1111 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1112 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
7ddb6568
AM		 1113 {"620", PROCESSOR_PPC620,
1114 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1115 {"630", PROCESSOR_PPC630,
1116 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
66188a7e
GK		 1117 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1118 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1119 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1120 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1121 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1122 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1123 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1124 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
4d4cbc0e
AH		 1125 /* 8548 has a dummy entry for now. */
1126 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
66188a7e 1127 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
7177e720 1128 {"970", PROCESSOR_POWER4,
66188a7e
GK		 1129 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1130 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1131 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1132 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1133 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
49ffe578 1134 {"G5", PROCESSOR_POWER4,
66188a7e
GK		 1135 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1136 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1137 {"power2", PROCESSOR_POWER,
1138 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
7ddb6568
AM		 1139 {"power3", PROCESSOR_PPC630,
1140 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1141 {"power4", PROCESSOR_POWER4,
fc091c8e 1142 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
ec507f2d 1143 {"power5", PROCESSOR_POWER5,
fc091c8e 1144 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
66188a7e
GK		 1145 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1146 {"powerpc64", PROCESSOR_POWERPC64,
98c41d98 1147 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
66188a7e
GK		 1148 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1149 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1150 {"rios2", PROCESSOR_RIOS2,
1151 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1152 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1153 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
98c41d98
DE		 1154 {"rs64", PROCESSOR_RS64A,
1155 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
66188a7e 1156 };
5248c961 1157
ca7558fc 1158 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
5248c961 1159
66188a7e
GK		 1160 /* Some OSs don't support saving the high part of 64-bit registers on
1161 context switch. Other OSs don't support saving Altivec registers.
1162 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1163 settings; if the user wants either, the user must explicitly specify
1164 them and we won't interfere with the user's specification. */
1165
1166 enum {
1167 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
f676971a 1168 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
66188a7e
GK		 1169 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1170 | MASK_MFCRF)
1171 };
0d1fbc8c
AH		 1172
1173 rs6000_init_hard_regno_mode_ok ();
1174
c4ad648e 1175 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
66188a7e
GK		 1176#ifdef OS_MISSING_POWERPC64
1177 if (OS_MISSING_POWERPC64)
1178 set_masks &= ~MASK_POWERPC64;
1179#endif
1180#ifdef OS_MISSING_ALTIVEC
1181 if (OS_MISSING_ALTIVEC)
1182 set_masks &= ~MASK_ALTIVEC;
1183#endif
1184
768875a8
AM		 1185 /* Don't override by the processor default if given explicitly. */
1186 set_masks &= ~target_flags_explicit;
957211c3 1187
a4f6c312 1188 /* Identify the processor type. */
8e3f41e7 1189 rs6000_select[0].string = default_cpu;
3cb999d8 1190 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
8e3f41e7 1191
b6a1cbae 1192 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
5248c961 1193 {
8e3f41e7
MM		 1194 ptr = &rs6000_select[i];
1195 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
5248c961 1196 {
8e3f41e7
MM		 1197 for (j = 0; j < ptt_size; j++)
1198 if (! strcmp (ptr->string, processor_target_table[j].name))
1199 {
1200 if (ptr->set_tune_p)
1201 rs6000_cpu = processor_target_table[j].processor;
1202
1203 if (ptr->set_arch_p)
1204 {
66188a7e
GK		 1205 target_flags &= ~set_masks;
1206 target_flags |= (processor_target_table[j].target_enable
1207 & set_masks);
8e3f41e7
MM		 1208 }
1209 break;
1210 }
1211
4406229e 1212 if (j == ptt_size)
8e3f41e7 1213 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
5248c961
RK		 1214 }
1215 }
8a61d227 1216
993f19a8 1217 if (TARGET_E500)
a3170dc6
AH		 1218 rs6000_isel = 1;
1219
dff9f1b6
DE		 1220 /* If we are optimizing big endian systems for space, use the load/store
1221 multiple and string instructions. */
ef792183 1222 if (BYTES_BIG_ENDIAN && optimize_size)
957211c3 1223 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
938937d8 1224
a4f6c312
SS		 1225 /* Don't allow -mmultiple or -mstring on little endian systems
1226 unless the cpu is a 750, because the hardware doesn't support the
1227 instructions used in little endian mode, and causes an alignment
1228 trap. The 750 does not cause an alignment trap (except when the
1229 target is unaligned). */
bef84347 1230
b21fb038 1231 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
7e69e155
MM		 1232 {
1233 if (TARGET_MULTIPLE)
1234 {
1235 target_flags &= ~MASK_MULTIPLE;
b21fb038 1236 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
d4ee4d25 1237 warning (0, "-mmultiple is not supported on little endian systems");
7e69e155
MM		 1238 }
1239
1240 if (TARGET_STRING)
1241 {
1242 target_flags &= ~MASK_STRING;
b21fb038 1243 if ((target_flags_explicit & MASK_STRING) != 0)
d4ee4d25 1244 warning (0, "-mstring is not supported on little endian systems");
7e69e155
MM		 1245 }
1246 }
3933e0e1 1247
38c1f2d7
MM		 1248 /* Set debug flags */
1249 if (rs6000_debug_name)
1250 {
bfc79d3b 1251 if (! strcmp (rs6000_debug_name, "all"))
38c1f2d7 1252 rs6000_debug_stack = rs6000_debug_arg = 1;
bfc79d3b 1253 else if (! strcmp (rs6000_debug_name, "stack"))
38c1f2d7 1254 rs6000_debug_stack = 1;
bfc79d3b 1255 else if (! strcmp (rs6000_debug_name, "arg"))
38c1f2d7
MM		 1256 rs6000_debug_arg = 1;
1257 else
c725bd79 1258 error ("unknown -mdebug-%s switch", rs6000_debug_name);
38c1f2d7
MM		 1259 }
1260
57ac7be9
AM		 1261 if (rs6000_traceback_name)
1262 {
1263 if (! strncmp (rs6000_traceback_name, "full", 4))
1264 rs6000_traceback = traceback_full;
1265 else if (! strncmp (rs6000_traceback_name, "part", 4))
1266 rs6000_traceback = traceback_part;
1267 else if (! strncmp (rs6000_traceback_name, "no", 2))
1268 rs6000_traceback = traceback_none;
1269 else
9e637a26 1270 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
57ac7be9
AM		 1271 rs6000_traceback_name);
1272 }
1273
6fa3f289 1274 /* Set size of long double */
c1e55850 1275 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
6fa3f289
ZW		 1276 if (rs6000_long_double_size_string)
1277 {
1278 char *tail;
1279 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1280 if (*tail != '\0' || (size != 64 && size != 128))
1281 error ("Unknown switch -mlong-double-%s",
1282 rs6000_long_double_size_string);
1283 else
1284 rs6000_long_double_type_size = size;
1285 }
1286
6d0ef01e
HP		 1287 /* Set Altivec ABI as default for powerpc64 linux. */
1288 if (TARGET_ELF && TARGET_64BIT)
1289 {
1290 rs6000_altivec_abi = 1;
1291 rs6000_altivec_vrsave = 1;
1292 }
1293
594a51fe
SS		 1294 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1295 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1296 {
1297 rs6000_darwin64_abi = 1;
9c7956fd 1298#if TARGET_MACHO
6ac49599 1299 darwin_one_byte_bool = 1;
9c7956fd 1300#endif
d9168963
SS		 1301 /* Default to natural alignment, for better performance. */
1302 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
594a51fe
SS		 1303 }
1304
0ac081f6
AH		 1305 /* Handle -mabi= options. */
1306 rs6000_parse_abi_options ();
1307
025d9908
KH		 1308 /* Handle -malign-XXXXX option. */
1309 rs6000_parse_alignment_option ();
1310
4d4cbc0e
AH		 1311 rs6000_parse_float_gprs_option ();
1312
5da702b1
AH		 1313 /* Handle generic -mFOO=YES/NO options. */
1314 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1315 &rs6000_altivec_vrsave);
1316 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1317 &rs6000_isel);
1318 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
993f19a8 1319
c4501e62
JJ		 1320 /* Handle -mtls-size option. */
1321 rs6000_parse_tls_size_option ();
1322
a7ae18e2
AH		 1323#ifdef SUBTARGET_OVERRIDE_OPTIONS
1324 SUBTARGET_OVERRIDE_OPTIONS;
1325#endif
1326#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1327 SUBSUBTARGET_OVERRIDE_OPTIONS;
1328#endif
4d4cbc0e
AH		 1329#ifdef SUB3TARGET_OVERRIDE_OPTIONS
1330 SUB3TARGET_OVERRIDE_OPTIONS;
1331#endif
a7ae18e2 1332
5da702b1
AH		 1333 if (TARGET_E500)
1334 {
e4463bf1
AH		 1335 if (TARGET_ALTIVEC)
1336 error ("AltiVec and E500 instructions cannot coexist");
1337
5da702b1
AH		 1338 /* The e500 does not have string instructions, and we set
1339 MASK_STRING above when optimizing for size. */
1340 if ((target_flags & MASK_STRING) != 0)
1341 target_flags = target_flags & ~MASK_STRING;
b6e59a3a
AH		 1342
1343 /* No SPE means 64-bit long doubles, even if an E500. */
1344 if (rs6000_spe_string != 0
c4ad648e 1345 && !strcmp (rs6000_spe_string, "no"))
b6e59a3a 1346 rs6000_long_double_type_size = 64;
5da702b1
AH		 1347 }
1348 else if (rs6000_select[1].string != NULL)
1349 {
1350 /* For the powerpc-eabispe configuration, we set all these by
1351 default, so let's unset them if we manually set another
1352 CPU that is not the E500. */
1353 if (rs6000_abi_string == 0)
1354 rs6000_spe_abi = 0;
1355 if (rs6000_spe_string == 0)
1356 rs6000_spe = 0;
1357 if (rs6000_float_gprs_string == 0)
1358 rs6000_float_gprs = 0;
1359 if (rs6000_isel_string == 0)
1360 rs6000_isel = 0;
b6e59a3a 1361 if (rs6000_long_double_size_string == 0)
c1e55850 1362 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
5da702b1 1363 }
b5044283 1364
ec507f2d
DE		 1365 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1366 && rs6000_cpu != PROCESSOR_POWER5);
1367 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1368 || rs6000_cpu == PROCESSOR_POWER5);
1369
a5c76ee6
ZW		 1370 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1371 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1372 bits in target_flags so TARGET_SWITCHES cannot be used.
1373 Assumption here is that rs6000_longcall_switch points into the
1374 text of the complete option, rather than being a copy, so we can
1375 scan back for the presence or absence of the no- modifier. */
1376 if (rs6000_longcall_switch)
1377 {
1378 const char *base = rs6000_longcall_switch;
1379 while (base[-1] != 'm') base--;
1380
1381 if (*rs6000_longcall_switch != '\0')
9e637a26 1382 error ("invalid option %qs", base);
a5c76ee6
ZW		 1383 rs6000_default_long_calls = (base[0] != 'n');
1384 }
1385
8bb418a3
ZL		 1386 /* Handle -m(no-)warn-altivec-long similarly. */
1387 if (rs6000_warn_altivec_long_switch)
1388 {
1389 const char *base = rs6000_warn_altivec_long_switch;
1390 while (base[-1] != 'm') base--;
1391
1392 if (*rs6000_warn_altivec_long_switch != '\0')
9e637a26 1393 error ("invalid option %qs", base);
8bb418a3
ZL		 1394 rs6000_warn_altivec_long = (base[0] != 'n');
1395 }
1396
cbe26ab8 1397 /* Handle -mprioritize-restricted-insns option. */
ec507f2d
DE		 1398 rs6000_sched_restricted_insns_priority
1399 = (rs6000_sched_groups ? 1 : 0);
79ae11c4
DN		 1400 if (rs6000_sched_restricted_insns_priority_str)
1401 rs6000_sched_restricted_insns_priority =
1402 atoi (rs6000_sched_restricted_insns_priority_str);
1403
569fa502 1404 /* Handle -msched-costly-dep option. */
ec507f2d
DE		 1405 rs6000_sched_costly_dep
1406 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
569fa502
DN		 1407 if (rs6000_sched_costly_dep_str)
1408 {
f676971a 1409 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
c4ad648e 1410 rs6000_sched_costly_dep = no_dep_costly;
569fa502 1411 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
c4ad648e 1412 rs6000_sched_costly_dep = all_deps_costly;
569fa502 1413 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
c4ad648e 1414 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
569fa502 1415 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
c4ad648e 1416 rs6000_sched_costly_dep = store_to_load_dep_costly;
f676971a 1417 else
c4ad648e 1418 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
cbe26ab8
DN		 1419 }
1420
1421 /* Handle -minsert-sched-nops option. */
ec507f2d
DE		 1422 rs6000_sched_insert_nops
1423 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
cbe26ab8
DN		 1424 if (rs6000_sched_insert_nops_str)
1425 {
1426 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
c4ad648e 1427 rs6000_sched_insert_nops = sched_finish_none;
cbe26ab8 1428 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
c4ad648e 1429 rs6000_sched_insert_nops = sched_finish_pad_groups;
cbe26ab8 1430 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
c4ad648e 1431 rs6000_sched_insert_nops = sched_finish_regroup_exact;
cbe26ab8 1432 else
c4ad648e 1433 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
569fa502
DN		 1434 }
1435
c81bebd7 1436#ifdef TARGET_REGNAMES
a4f6c312
SS		 1437 /* If the user desires alternate register names, copy in the
1438 alternate names now. */
c81bebd7 1439 if (TARGET_REGNAMES)
4e135bdd 1440 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
c81bebd7
MM		 1441#endif
1442
6fa3f289
ZW		 1443 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1444 If -maix-struct-return or -msvr4-struct-return was explicitly
1445 used, don't override with the ABI default. */
b21fb038 1446 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
6fa3f289
ZW		 1447 {
1448 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1449 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1450 else
1451 target_flags |= MASK_AIX_STRUCT_RET;
1452 }
1453
fcce224d
DE		 1454 if (TARGET_LONG_DOUBLE_128
1455 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
70a01792 1456 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
fcce224d 1457
9ebbca7d
GK		 1458 /* Allocate an alias set for register saves & restores from stack. */
1459 rs6000_sr_alias_set = new_alias_set ();
1460
f676971a 1461 if (TARGET_TOC)
9ebbca7d 1462 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
71f123ca 1463
301d03af
RS		 1464 /* We can only guarantee the availability of DI pseudo-ops when
1465 assembling for 64-bit targets. */
ae6c1efd 1466 if (!TARGET_64BIT)
301d03af
RS		 1467 {
1468 targetm.asm_out.aligned_op.di = NULL;
1469 targetm.asm_out.unaligned_op.di = NULL;
1470 }
1471
1494c534
DE		 1472 /* Set branch target alignment, if not optimizing for size. */
1473 if (!optimize_size)
1474 {
1475 if (rs6000_sched_groups)
1476 {
1477 if (align_functions <= 0)
1478 align_functions = 16;
1479 if (align_jumps <= 0)
1480 align_jumps = 16;
1481 if (align_loops <= 0)
1482 align_loops = 16;
1483 }
1484 if (align_jumps_max_skip <= 0)
1485 align_jumps_max_skip = 15;
1486 if (align_loops_max_skip <= 0)
1487 align_loops_max_skip = 15;
1488 }
2792d578 1489
71f123ca
FS		 1490 /* Arrange to save and restore machine status around nested functions. */
1491 init_machine_status = rs6000_init_machine_status;
42ba5130
RH		 1492
1493 /* We should always be splitting complex arguments, but we can't break
1494 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
18f63bfa 1495 if (DEFAULT_ABI != ABI_AIX)
42ba5130 1496 targetm.calls.split_complex_arg = NULL;
8b897cfa
RS		 1497
1498 /* Initialize rs6000_cost with the appropriate target costs. */
1499 if (optimize_size)
1500 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1501 else
1502 switch (rs6000_cpu)
1503 {
1504 case PROCESSOR_RIOS1:
1505 rs6000_cost = &rios1_cost;
1506 break;
1507
1508 case PROCESSOR_RIOS2:
1509 rs6000_cost = &rios2_cost;
1510 break;
1511
1512 case PROCESSOR_RS64A:
1513 rs6000_cost = &rs64a_cost;
1514 break;
1515
1516 case PROCESSOR_MPCCORE:
1517 rs6000_cost = &mpccore_cost;
1518 break;
1519
1520 case PROCESSOR_PPC403:
1521 rs6000_cost = &ppc403_cost;
1522 break;
1523
1524 case PROCESSOR_PPC405:
1525 rs6000_cost = &ppc405_cost;
1526 break;
1527
1528 case PROCESSOR_PPC440:
1529 rs6000_cost = &ppc440_cost;
1530 break;
1531
1532 case PROCESSOR_PPC601:
1533 rs6000_cost = &ppc601_cost;
1534 break;
1535
1536 case PROCESSOR_PPC603:
1537 rs6000_cost = &ppc603_cost;
1538 break;
1539
1540 case PROCESSOR_PPC604:
1541 rs6000_cost = &ppc604_cost;
1542 break;
1543
1544 case PROCESSOR_PPC604e:
1545 rs6000_cost = &ppc604e_cost;
1546 break;
1547
1548 case PROCESSOR_PPC620:
8b897cfa
RS		 1549 rs6000_cost = &ppc620_cost;
1550 break;
1551
f0517163
RS		 1552 case PROCESSOR_PPC630:
1553 rs6000_cost = &ppc630_cost;
1554 break;
1555
8b897cfa
RS		 1556 case PROCESSOR_PPC750:
1557 case PROCESSOR_PPC7400:
1558 rs6000_cost = &ppc750_cost;
1559 break;
1560
1561 case PROCESSOR_PPC7450:
1562 rs6000_cost = &ppc7450_cost;
1563 break;
1564
1565 case PROCESSOR_PPC8540:
1566 rs6000_cost = &ppc8540_cost;
1567 break;
1568
1569 case PROCESSOR_POWER4:
1570 case PROCESSOR_POWER5:
1571 rs6000_cost = &power4_cost;
1572 break;
1573
1574 default:
37409796 1575 gcc_unreachable ();
8b897cfa 1576 }
5248c961 1577}
5accd822 1578
7ccf35ed
DN		 1579/* Implement targetm.vectorize.builtin_mask_for_load. */
1580static tree
1581rs6000_builtin_mask_for_load (void)
1582{
1583 if (TARGET_ALTIVEC)
1584 return altivec_builtin_mask_for_load;
1585 else
1586 return 0;
1587}
1588
5da702b1
AH		 1589/* Handle generic options of the form -mfoo=yes/no.
1590 NAME is the option name.
1591 VALUE is the option value.
1592 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1593 whether the option value is 'yes' or 'no' respectively. */
993f19a8 1594static void
5da702b1 1595rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
993f19a8 1596{
5da702b1 1597 if (value == 0)
993f19a8 1598 return;
5da702b1
AH		 1599 else if (!strcmp (value, "yes"))
1600 *flag = 1;
1601 else if (!strcmp (value, "no"))
1602 *flag = 0;
08b57fb3 1603 else
5da702b1 1604 error ("unknown -m%s= option specified: '%s'", name, value);
08b57fb3
AH		 1605}
1606
0ac081f6 1607/* Handle -mabi= options. */
00b960c7 1608static void
863d938c 1609rs6000_parse_abi_options (void)
0ac081f6
AH		 1610{
1611 if (rs6000_abi_string == 0)
1612 return;
1613 else if (! strcmp (rs6000_abi_string, "altivec"))
5cc73f91
AH		 1614 {
1615 rs6000_altivec_abi = 1;
1616 rs6000_spe_abi = 0;
1617 }
76a773f3
AH		 1618 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1619 rs6000_altivec_abi = 0;
a3170dc6 1620 else if (! strcmp (rs6000_abi_string, "spe"))
01f4962d
NS		 1621 {
1622 rs6000_spe_abi = 1;
5cc73f91 1623 rs6000_altivec_abi = 0;
01f4962d
NS		 1624 if (!TARGET_SPE_ABI)
1625 error ("not configured for ABI: '%s'", rs6000_abi_string);
1626 }
f676971a 1627
594a51fe
SS		 1628 /* These are here for testing during development only, do not
1629 document in the manual please. */
1630 else if (! strcmp (rs6000_abi_string, "d64"))
1631 {
1632 rs6000_darwin64_abi = 1;
d4ee4d25 1633 warning (0, "Using darwin64 ABI");
594a51fe
SS		 1634 }
1635 else if (! strcmp (rs6000_abi_string, "d32"))
1636 {
1637 rs6000_darwin64_abi = 0;
d4ee4d25 1638 warning (0, "Using old darwin ABI");
594a51fe
SS		 1639 }
1640
a3170dc6
AH		 1641 else if (! strcmp (rs6000_abi_string, "no-spe"))
1642 rs6000_spe_abi = 0;
0ac081f6 1643 else
c725bd79 1644 error ("unknown ABI specified: '%s'", rs6000_abi_string);
0ac081f6
AH		 1645}
1646
4d4cbc0e
AH		 1647/* Handle -mfloat-gprs= options. */
1648static void
1649rs6000_parse_float_gprs_option (void)
1650{
1651 if (rs6000_float_gprs_string == 0)
1652 return;
1653 else if (! strcmp (rs6000_float_gprs_string, "yes")
1654 || ! strcmp (rs6000_float_gprs_string, "single"))
1655 rs6000_float_gprs = 1;
1656 else if (! strcmp (rs6000_float_gprs_string, "double"))
1657 rs6000_float_gprs = 2;
1658 else if (! strcmp (rs6000_float_gprs_string, "no"))
1659 rs6000_float_gprs = 0;
1660 else
1661 error ("invalid option for -mfloat-gprs");
1662}
1663
025d9908
KH		 1664/* Handle -malign-XXXXXX options. */
1665static void
863d938c 1666rs6000_parse_alignment_option (void)
025d9908 1667{
b20a9cca
AM		 1668 if (rs6000_alignment_string == 0)
1669 return;
1670 else if (! strcmp (rs6000_alignment_string, "power"))
d9168963
SS		 1671 {
1672 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1673 some C library functions, so warn about it. The flag may be
1674 useful for performance studies from time to time though, so
1675 don't disable it entirely. */
1676 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
d4ee4d25 1677 warning (0, "-malign-power is not supported for 64-bit Darwin;"
d9168963
SS		 1678 " it is incompatible with the installed C and C++ libraries");
1679 rs6000_alignment_flags = MASK_ALIGN_POWER;
1680 }
025d9908
KH		 1681 else if (! strcmp (rs6000_alignment_string, "natural"))
1682 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1683 else
1684 error ("unknown -malign-XXXXX option specified: '%s'",
1685 rs6000_alignment_string);
1686}
1687
c4501e62
JJ		 1688/* Validate and record the size specified with the -mtls-size option. */
1689
1690static void
863d938c 1691rs6000_parse_tls_size_option (void)
c4501e62
JJ		 1692{
1693 if (rs6000_tls_size_string == 0)
1694 return;
1695 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1696 rs6000_tls_size = 16;
1697 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1698 rs6000_tls_size = 32;
1699 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1700 rs6000_tls_size = 64;
1701 else
9e637a26 1702 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
c4501e62
JJ		 1703}
1704
5accd822 1705void
a2369ed3 1706optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
5accd822 1707{
5accd822 1708}
3cfa4909
MM		 1709\f
1710/* Do anything needed at the start of the asm file. */
1711
1bc7c5b6 1712static void
863d938c 1713rs6000_file_start (void)
3cfa4909 1714{
c4d38ccb 1715 size_t i;
3cfa4909 1716 char buffer[80];
d330fd93 1717 const char *start = buffer;
3cfa4909 1718 struct rs6000_cpu_select *ptr;
1bc7c5b6
ZW		 1719 const char *default_cpu = TARGET_CPU_DEFAULT;
1720 FILE *file = asm_out_file;
1721
1722 default_file_start ();
1723
1724#ifdef TARGET_BI_ARCH
1725 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1726 default_cpu = 0;
1727#endif
3cfa4909
MM		 1728
1729 if (flag_verbose_asm)
1730 {
1731 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1732 rs6000_select[0].string = default_cpu;
1733
b6a1cbae 1734 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
3cfa4909
MM		 1735 {
1736 ptr = &rs6000_select[i];
1737 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1738 {
1739 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1740 start = "";
1741 }
1742 }
1743
b91da81f 1744#ifdef USING_ELFOS_H
3cfa4909
MM		 1745 switch (rs6000_sdata)
1746 {
1747 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1748 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1749 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1750 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1751 }
1752
1753 if (rs6000_sdata && g_switch_value)
1754 {
307b599c
MK		 1755 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1756 g_switch_value);
3cfa4909
MM		 1757 start = "";
1758 }
1759#endif
1760
1761 if (*start == '\0')
949ea356 1762 putc ('\n', file);
3cfa4909 1763 }
b723e82f
JJ		 1764
1765 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1766 {
1767 toc_section ();
1768 text_section ();
1769 }
3cfa4909 1770}
c4e18b1c 1771
5248c961 1772\f
a0ab749a 1773/* Return nonzero if this function is known to have a null epilogue. */
9878760c
RK		 1774
1775int
863d938c 1776direct_return (void)
9878760c 1777{
4697a36c
MM		 1778 if (reload_completed)
1779 {
1780 rs6000_stack_t *info = rs6000_stack_info ();
1781
1782 if (info->first_gp_reg_save == 32
1783 && info->first_fp_reg_save == 64
00b960c7 1784 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
c81fc13e
DE		 1785 && ! info->lr_save_p
1786 && ! info->cr_save_p
00b960c7 1787 && info->vrsave_mask == 0
c81fc13e 1788 && ! info->push_p)
4697a36c
MM		 1789 return 1;
1790 }
1791
1792 return 0;
9878760c
RK		 1793}
1794
4e74d8ec
MM		 1795/* Return the number of instructions it takes to form a constant in an
1796 integer register. */
1797
48d72335 1798int
a2369ed3 1799num_insns_constant_wide (HOST_WIDE_INT value)
4e74d8ec
MM		 1800{
1801 /* signed constant loadable with {cal|addi} */
5f59ecb7 1802 if (CONST_OK_FOR_LETTER_P (value, 'I'))
0865c631
GK		 1803 return 1;
1804
4e74d8ec 1805 /* constant loadable with {cau|addis} */
5f59ecb7 1806 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
4e74d8ec
MM		 1807 return 1;
1808
5f59ecb7 1809#if HOST_BITS_PER_WIDE_INT == 64
c81fc13e 1810 else if (TARGET_POWERPC64)
4e74d8ec 1811 {
a65c591c
DE		 1812 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1813 HOST_WIDE_INT high = value >> 31;
4e74d8ec 1814
a65c591c 1815 if (high == 0 || high == -1)
4e74d8ec
MM		 1816 return 2;
1817
a65c591c 1818 high >>= 1;
4e74d8ec 1819
a65c591c 1820 if (low == 0)
4e74d8ec 1821 return num_insns_constant_wide (high) + 1;
4e74d8ec
MM		 1822 else
1823 return (num_insns_constant_wide (high)
e396202a 1824 + num_insns_constant_wide (low) + 1);
4e74d8ec
MM		 1825 }
1826#endif
1827
1828 else
1829 return 2;
1830}
1831
1832int
a2369ed3 1833num_insns_constant (rtx op, enum machine_mode mode)
4e74d8ec 1834{
37409796
NS		 1835 HOST_WIDE_INT low, high;
1836
1837 switch (GET_CODE (op))
0d30d435 1838 {
37409796 1839 case CONST_INT:
0d30d435 1840#if HOST_BITS_PER_WIDE_INT == 64
4e2c1c44
DE		 1841 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1842 && mask64_operand (op, mode))
c4ad648e 1843 return 2;
0d30d435
DE		 1844 else
1845#endif
1846 return num_insns_constant_wide (INTVAL (op));
4e74d8ec 1847
37409796
NS		 1848 case CONST_DOUBLE:
1849 if (mode == SFmode)
1850 {
1851 long l;
1852 REAL_VALUE_TYPE rv;
1853
1854 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1855 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1856 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1857 }
a260abc9 1858
37409796
NS		 1859 if (mode == VOIDmode || mode == DImode)
1860 {
1861 high = CONST_DOUBLE_HIGH (op);
1862 low = CONST_DOUBLE_LOW (op);
1863 }
1864 else
1865 {
1866 long l[2];
1867 REAL_VALUE_TYPE rv;
1868
1869 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1870 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1871 high = l[WORDS_BIG_ENDIAN == 0];
1872 low = l[WORDS_BIG_ENDIAN != 0];
1873 }
47ad8c61 1874
37409796
NS		 1875 if (TARGET_32BIT)
1876 return (num_insns_constant_wide (low)
1877 + num_insns_constant_wide (high));
1878 else
1879 {
1880 if ((high == 0 && low >= 0)
1881 || (high == -1 && low < 0))
1882 return num_insns_constant_wide (low);
1883
1884 else if (mask64_operand (op, mode))
1885 return 2;
1886
1887 else if (low == 0)
1888 return num_insns_constant_wide (high) + 1;
1889
1890 else
1891 return (num_insns_constant_wide (high)
1892 + num_insns_constant_wide (low) + 1);
1893 }
1894
1895 default:
1896 gcc_unreachable ();
4e74d8ec 1897 }
4e74d8ec
MM		 1898}
1899
effa5d5d 1900/* Returns the constant for the splat instruction, if exists. */
452a7d36 1901
48d72335 1902int
452a7d36
HP		 1903easy_vector_splat_const (int cst, enum machine_mode mode)
1904{
f676971a 1905 switch (mode)
452a7d36
HP		 1906 {
1907 case V4SImode:
f676971a
EC		 1908 if (EASY_VECTOR_15 (cst)
1909 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 1910 return cst;
1911 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1912 break;
1913 cst = cst >> 16;
c4ad648e
AM		 1914 /* Fall thru */
1915
452a7d36 1916 case V8HImode:
f676971a
EC		 1917 if (EASY_VECTOR_15 (cst)
1918 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 1919 return cst;
1920 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1921 break;
1922 cst = cst >> 8;
c4ad648e
AM		 1923 /* Fall thru */
1924
452a7d36 1925 case V16QImode:
c4ad648e
AM		 1926 if (EASY_VECTOR_15 (cst)
1927 || EASY_VECTOR_15_ADD_SELF (cst))
1928 return cst;
f676971a 1929 default:
452a7d36
HP		 1930 break;
1931 }
1932 return 0;
1933}
1934
72ac76be 1935/* Return nonzero if all elements of a vector have the same value. */
69ef87e2 1936
48d72335 1937int
a2369ed3 1938easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d744e06e
AH		 1939{
1940 int units, i, cst;
1941
1942 units = CONST_VECTOR_NUNITS (op);
1943
1944 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1945 for (i = 1; i < units; ++i)
1946 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1947 break;
452a7d36 1948 if (i == units && easy_vector_splat_const (cst, mode))
d744e06e
AH		 1949 return 1;
1950 return 0;
1951}
1952
452a7d36 1953/* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
d744e06e 1954
f676971a 1955rtx
452a7d36
HP		 1956gen_easy_vector_constant_add_self (rtx op)
1957{
1958 int i, units;
1959 rtvec v;
1960 units = GET_MODE_NUNITS (GET_MODE (op));
1961 v = rtvec_alloc (units);
1962
1963 for (i = 0; i < units; i++)
f676971a 1964 RTVEC_ELT (v, i) =
452a7d36
HP		 1965 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1966 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
d744e06e
AH		 1967}
1968
1969const char *
a2369ed3 1970output_vec_const_move (rtx *operands)
d744e06e
AH		 1971{
1972 int cst, cst2;
1973 enum machine_mode mode;
1974 rtx dest, vec;
1975
1976 dest = operands[0];
1977 vec = operands[1];
69ef87e2 1978
d744e06e
AH		 1979 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
1980 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
1981 mode = GET_MODE (dest);
69ef87e2 1982
d744e06e
AH		 1983 if (TARGET_ALTIVEC)
1984 {
1985 if (zero_constant (vec, mode))
1986 return "vxor %0,%0,%0";
37409796
NS		 1987
1988 gcc_assert (easy_vector_constant (vec, mode));
1989
1990 operands[1] = GEN_INT (cst);
1991 switch (mode)
98ef3137 1992 {
37409796
NS		 1993 case V4SImode:
1994 if (EASY_VECTOR_15 (cst))
d744e06e 1995 {
37409796
NS		 1996 operands[1] = GEN_INT (cst);
1997 return "vspltisw %0,%1";
1998 }
1999 else if (EASY_VECTOR_15_ADD_SELF (cst))
2000 return "#";
2001 cst = cst >> 16;
2002 /* Fall thru */
c4ad648e 2003
37409796
NS		 2004 case V8HImode:
2005 if (EASY_VECTOR_15 (cst))
2006 {
2007 operands[1] = GEN_INT (cst);
2008 return "vspltish %0,%1";
2009 }
2010 else if (EASY_VECTOR_15_ADD_SELF (cst))
2011 return "#";
2012 cst = cst >> 8;
2013 /* Fall thru */
c4ad648e 2014
37409796
NS		 2015 case V16QImode:
2016 if (EASY_VECTOR_15 (cst))
2017 {
2018 operands[1] = GEN_INT (cst);
2019 return "vspltisb %0,%1";
d744e06e 2020 }
37409796
NS		 2021 else if (EASY_VECTOR_15_ADD_SELF (cst))
2022 return "#";
2023
2024 default:
2025 gcc_unreachable ();
98ef3137 2026 }
69ef87e2
AH		 2027 }
2028
37409796
NS		 2029 gcc_assert (TARGET_SPE);
2030
2031 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2032 pattern of V1DI, V4HI, and V2SF.
2033
2034 FIXME: We should probably return # and add post reload
2035 splitters for these, but this way is so easy ;-). */
2036 operands[1] = GEN_INT (cst);
2037 operands[2] = GEN_INT (cst2);
2038 if (cst == cst2)
2039 return "li %0,%1\n\tevmergelo %0,%0,%0";
2040 else
2041 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
69ef87e2
AH		 2042}
2043
914c2e77 2044int
e1e2e653
NS		 2045mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2046 bool allow_one)
0ba1b2ff
AM		 2047{
2048 if (GET_CODE (op) == CONST_INT)
a260abc9 2049 {
0ba1b2ff 2050 HOST_WIDE_INT c, lsb;
e1e2e653
NS		 2051 bool one_ok;
2052
0ba1b2ff 2053 c = INTVAL (op);
a260abc9 2054
0ba1b2ff
AM		 2055 /* Disallow all zeros. */
2056 if (c == 0)
2057 return 0;
a260abc9 2058
e1e2e653
NS		 2059 /* We can use a single rlwinm insn if no upper bits of C are set
2060 AND there are zero, one or two transitions in the _whole_ of
2061 C. */
2062 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2063
0ba1b2ff
AM		 2064 /* We don't change the number of transitions by inverting,
2065 so make sure we start with the LS bit zero. */
2066 if (c & 1)
2067 c = ~c;
a260abc9 2068
0ba1b2ff
AM		 2069 /* Find the first transition. */
2070 lsb = c & -c;
a260abc9 2071
0ba1b2ff
AM		 2072 /* Invert to look for a second transition. */
2073 c = ~c;
2074
2075 /* Erase first transition. */
2076 c &= -lsb;
2077
2078 /* Find the second transition. */
2079 lsb = c & -c;
2080
2081 /* Invert to look for a third transition. */
2082 c = ~c;
2083
2084 /* Erase second transition. */
2085 c &= -lsb;
2086
e1e2e653
NS		 2087 if (one_ok && !(allow_one || c))
2088 return 0;
2089
0ba1b2ff
AM		 2090 /* Find the third transition (if any). */
2091 lsb = c & -c;
2092
2093 /* Match if all the bits above are 1's (or c is zero). */
2094 return c == -lsb;
2095 }
2096 return 0;
2097}
2098
2099/* Generates shifts and masks for a pair of rldicl or rldicr insns to
2100 implement ANDing by the mask IN. */
2101void
a2369ed3 2102build_mask64_2_operands (rtx in, rtx *out)
0ba1b2ff
AM		 2103{
2104#if HOST_BITS_PER_WIDE_INT >= 64
2105 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2106 int shift;
2107
37409796 2108 gcc_assert (GET_CODE (in) == CONST_INT);
0ba1b2ff
AM		 2109
2110 c = INTVAL (in);
2111 if (c & 1)
2112 {
2113 /* Assume c initially something like 0x00fff000000fffff. The idea
2114 is to rotate the word so that the middle ^^^^^^ group of zeros
2115 is at the MS end and can be cleared with an rldicl mask. We then
2116 rotate back and clear off the MS ^^ group of zeros with a
2117 second rldicl. */
2118 c = ~c; /* c == 0xff000ffffff00000 */
2119 lsb = c & -c; /* lsb == 0x0000000000100000 */
2120 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2121 c = ~c; /* c == 0x00fff000000fffff */
2122 c &= -lsb; /* c == 0x00fff00000000000 */
2123 lsb = c & -c; /* lsb == 0x0000100000000000 */
2124 c = ~c; /* c == 0xff000fffffffffff */
2125 c &= -lsb; /* c == 0xff00000000000000 */
2126 shift = 0;
2127 while ((lsb >>= 1) != 0)
2128 shift++; /* shift == 44 on exit from loop */
2129 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2130 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2131 m2 = ~c; /* m2 == 0x00ffffffffffffff */
a260abc9
DE		 2132 }
2133 else
0ba1b2ff
AM		 2134 {
2135 /* Assume c initially something like 0xff000f0000000000. The idea
2136 is to rotate the word so that the ^^^ middle group of zeros
2137 is at the LS end and can be cleared with an rldicr mask. We then
2138 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2139 a second rldicr. */
2140 lsb = c & -c; /* lsb == 0x0000010000000000 */
2141 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2142 c = ~c; /* c == 0x00fff0ffffffffff */
2143 c &= -lsb; /* c == 0x00fff00000000000 */
2144 lsb = c & -c; /* lsb == 0x0000100000000000 */
2145 c = ~c; /* c == 0xff000fffffffffff */
2146 c &= -lsb; /* c == 0xff00000000000000 */
2147 shift = 0;
2148 while ((lsb >>= 1) != 0)
2149 shift++; /* shift == 44 on exit from loop */
2150 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2151 m1 >>= shift; /* m1 == 0x0000000000000fff */
2152 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2153 }
2154
2155 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2156 masks will be all 1's. We are guaranteed more than one transition. */
2157 out[0] = GEN_INT (64 - shift);
2158 out[1] = GEN_INT (m1);
2159 out[2] = GEN_INT (shift);
2160 out[3] = GEN_INT (m2);
2161#else
045572c7
GK		 2162 (void)in;
2163 (void)out;
37409796 2164 gcc_unreachable ();
0ba1b2ff 2165#endif
a260abc9
DE		 2166}
2167
54b695e7 2168/* Return TRUE if OP is an invalid SUBREG operation on the e500. */
48d72335
DE		 2169
2170bool
54b695e7
AH		 2171invalid_e500_subreg (rtx op, enum machine_mode mode)
2172{
2173 /* Reject (subreg:SI (reg:DF)). */
2174 if (GET_CODE (op) == SUBREG
2175 && mode == SImode
2176 && REG_P (SUBREG_REG (op))
2177 && GET_MODE (SUBREG_REG (op)) == DFmode)
2178 return true;
2179
2180 /* Reject (subreg:DF (reg:DI)). */
2181 if (GET_CODE (op) == SUBREG
2182 && mode == DFmode
2183 && REG_P (SUBREG_REG (op))
2184 && GET_MODE (SUBREG_REG (op)) == DImode)
2185 return true;
2186
2187 return false;
2188}
2189
95727fb8
AP		 2190/* Darwin, AIX increases natural record alignment to doubleword if the first
2191 field is an FP double while the FP fields remain word aligned. */
2192
19d66194 2193unsigned int
95727fb8
AP		 2194rs6000_special_round_type_align (tree type, int computed, int specified)
2195{
2196 tree field = TYPE_FIELDS (type);
95727fb8 2197
85962ac8
AP		 2198 /* Skip all non field decls */
2199 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
95727fb8
AP		 2200 field = TREE_CHAIN (field);
2201
3ce5437a 2202 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
95727fb8
AP		 2203 return MAX (computed, specified);
2204
2205 return MAX (MAX (computed, specified), 64);
2206}
2207
a4f6c312 2208/* Return 1 for an operand in small memory on V.4/eabi. */
7509c759
MM		 2209
2210int
f676971a 2211small_data_operand (rtx op ATTRIBUTE_UNUSED,
a2369ed3 2212 enum machine_mode mode ATTRIBUTE_UNUSED)
7509c759 2213{
38c1f2d7 2214#if TARGET_ELF
5f59ecb7 2215 rtx sym_ref;
7509c759 2216
d9407988 2217 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
a54d04b7 2218 return 0;
a54d04b7 2219
f607bc57 2220 if (DEFAULT_ABI != ABI_V4)
7509c759
MM		 2221 return 0;
2222
88228c4b
MM		 2223 if (GET_CODE (op) == SYMBOL_REF)
2224 sym_ref = op;
2225
2226 else if (GET_CODE (op) != CONST
2227 || GET_CODE (XEXP (op, 0)) != PLUS
2228 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2229 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7509c759
MM		 2230 return 0;
2231
88228c4b 2232 else
dbf55e53
MM		 2233 {
2234 rtx sum = XEXP (op, 0);
2235 HOST_WIDE_INT summand;
2236
2237 /* We have to be careful here, because it is the referenced address
c4ad648e 2238 that must be 32k from _SDA_BASE_, not just the symbol. */
dbf55e53 2239 summand = INTVAL (XEXP (sum, 1));
307b599c 2240 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
9390387d 2241 return 0;
dbf55e53
MM		 2242
2243 sym_ref = XEXP (sum, 0);
2244 }
88228c4b 2245
20bfcd69 2246 return SYMBOL_REF_SMALL_P (sym_ref);
d9407988
MM		 2247#else
2248 return 0;
2249#endif
7509c759 2250}
46c07df8 2251
3a1f863f 2252/* Return true if either operand is a general purpose register. */
46c07df8 2253
3a1f863f
DE		 2254bool
2255gpr_or_gpr_p (rtx op0, rtx op1)
46c07df8 2256{
3a1f863f
DE		 2257 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2258 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
46c07df8
HP		 2259}
2260
9ebbca7d 2261\f
4d588c14
RH		 2262/* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2263
f676971a
EC		 2264static int
2265constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
9ebbca7d 2266{
9390387d 2267 switch (GET_CODE (op))
9ebbca7d
GK		 2268 {
2269 case SYMBOL_REF:
c4501e62
JJ		 2270 if (RS6000_SYMBOL_REF_TLS_P (op))
2271 return 0;
2272 else if (CONSTANT_POOL_ADDRESS_P (op))
a4f6c312
SS		 2273 {
2274 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2275 {
2276 *have_sym = 1;
2277 return 1;
2278 }
2279 else
2280 return 0;
2281 }
2282 else if (! strcmp (XSTR (op, 0), toc_label_name))
2283 {
2284 *have_toc = 1;
2285 return 1;
2286 }
2287 else
2288 return 0;
9ebbca7d
GK		 2289 case PLUS:
2290 case MINUS:
c1f11548
DE		 2291 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2292 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
9ebbca7d 2293 case CONST:
a4f6c312 2294 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
9ebbca7d 2295 case CONST_INT:
a4f6c312 2296 return 1;
9ebbca7d 2297 default:
a4f6c312 2298 return 0;
9ebbca7d
GK		 2299 }
2300}
2301
4d588c14 2302static bool
a2369ed3 2303constant_pool_expr_p (rtx op)
9ebbca7d
GK		 2304{
2305 int have_sym = 0;
2306 int have_toc = 0;
2307 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2308}
2309
48d72335 2310bool
a2369ed3 2311toc_relative_expr_p (rtx op)
9ebbca7d 2312{
4d588c14
RH		 2313 int have_sym = 0;
2314 int have_toc = 0;
2315 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2316}
2317
4d588c14 2318bool
a2369ed3 2319legitimate_constant_pool_address_p (rtx x)
4d588c14
RH		 2320{
2321 return (TARGET_TOC
2322 && GET_CODE (x) == PLUS
2323 && GET_CODE (XEXP (x, 0)) == REG
2324 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2325 && constant_pool_expr_p (XEXP (x, 1)));
2326}
2327
2328static bool
a2369ed3 2329legitimate_small_data_p (enum machine_mode mode, rtx x)
4d588c14
RH		 2330{
2331 return (DEFAULT_ABI == ABI_V4
2332 && !flag_pic && !TARGET_TOC
2333 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2334 && small_data_operand (x, mode));
2335}
2336
60cdabab
DE		 2337/* SPE offset addressing is limited to 5-bits worth of double words. */
2338#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2339
76d2b81d
DJ		 2340bool
2341rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2342{
2343 unsigned HOST_WIDE_INT offset, extra;
2344
2345 if (GET_CODE (x) != PLUS)
2346 return false;
2347 if (GET_CODE (XEXP (x, 0)) != REG)
2348 return false;
2349 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2350 return false;
60cdabab
DE		 2351 if (legitimate_constant_pool_address_p (x))
2352 return true;
4d588c14
RH		 2353 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2354 return false;
2355
2356 offset = INTVAL (XEXP (x, 1));
2357 extra = 0;
2358 switch (mode)
2359 {
2360 case V16QImode:
2361 case V8HImode:
2362 case V4SFmode:
2363 case V4SImode:
2364 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2365 which leaves the only valid constant offset of zero, which by
2366 canonicalization rules is also invalid. */
2367 return false;
2368
2369 case V4HImode:
2370 case V2SImode:
2371 case V1DImode:
2372 case V2SFmode:
2373 /* SPE vector modes. */
2374 return SPE_CONST_OFFSET_OK (offset);
2375
2376 case DFmode:
4d4cbc0e
AH		 2377 if (TARGET_E500_DOUBLE)
2378 return SPE_CONST_OFFSET_OK (offset);
2379
4d588c14 2380 case DImode:
54b695e7
AH		 2381 /* On e500v2, we may have:
2382
2383 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2384
2385 Which gets addressed with evldd instructions. */
2386 if (TARGET_E500_DOUBLE)
2387 return SPE_CONST_OFFSET_OK (offset);
2388
3364872d 2389 if (mode == DFmode || !TARGET_POWERPC64)
4d588c14
RH		 2390 extra = 4;
2391 else if (offset & 3)
2392 return false;
2393 break;
2394
2395 case TFmode:
2396 case TImode:
3364872d 2397 if (mode == TFmode || !TARGET_POWERPC64)
4d588c14
RH		 2398 extra = 12;
2399 else if (offset & 3)
2400 return false;
2401 else
2402 extra = 8;
2403 break;
2404
2405 default:
2406 break;
2407 }
2408
b1917422
AM		 2409 offset += 0x8000;
2410 return (offset < 0x10000) && (offset + extra < 0x10000);
4d588c14
RH		 2411}
2412
2413static bool
a2369ed3 2414legitimate_indexed_address_p (rtx x, int strict)
4d588c14
RH		 2415{
2416 rtx op0, op1;
2417
2418 if (GET_CODE (x) != PLUS)
2419 return false;
850e8d3d 2420
4d588c14
RH		 2421 op0 = XEXP (x, 0);
2422 op1 = XEXP (x, 1);
2423
2424 if (!REG_P (op0) || !REG_P (op1))
2425 return false;
2426
2427 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2428 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2429 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2430 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
9ebbca7d
GK		 2431}
2432
48d72335 2433inline bool
a2369ed3 2434legitimate_indirect_address_p (rtx x, int strict)
4d588c14
RH		 2435{
2436 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2437}
2438
48d72335 2439bool
4c81e946
FJ		 2440macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2441{
c4ad648e 2442 if (!TARGET_MACHO || !flag_pic
9390387d 2443 || mode != SImode || GET_CODE (x) != MEM)
c4ad648e
AM		 2444 return false;
2445 x = XEXP (x, 0);
4c81e946
FJ		 2446
2447 if (GET_CODE (x) != LO_SUM)
2448 return false;
2449 if (GET_CODE (XEXP (x, 0)) != REG)
2450 return false;
2451 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2452 return false;
2453 x = XEXP (x, 1);
2454
2455 return CONSTANT_P (x);
2456}
2457
4d588c14 2458static bool
a2369ed3 2459legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2460{
2461 if (GET_CODE (x) != LO_SUM)
2462 return false;
2463 if (GET_CODE (XEXP (x, 0)) != REG)
2464 return false;
2465 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2466 return false;
54b695e7
AH		 2467 /* Restrict addressing for DI because of our SUBREG hackery. */
2468 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
f82f556d 2469 return false;
4d588c14
RH		 2470 x = XEXP (x, 1);
2471
8622e235 2472 if (TARGET_ELF || TARGET_MACHO)
4d588c14 2473 {
a29077da 2474 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
4d588c14
RH		 2475 return false;
2476 if (TARGET_TOC)
2477 return false;
2478 if (GET_MODE_NUNITS (mode) != 1)
2479 return false;
5e5f01b9 2480 if (GET_MODE_BITSIZE (mode) > 64
3c028f65
AM		 2481 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2482 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
4d588c14
RH		 2483 return false;
2484
2485 return CONSTANT_P (x);
2486 }
2487
2488 return false;
2489}
2490
2491
9ebbca7d
GK		 2492/* Try machine-dependent ways of modifying an illegitimate address
2493 to be legitimate. If we find one, return the new, valid address.
2494 This is used from only one place: `memory_address' in explow.c.
2495
a4f6c312
SS		 2496 OLDX is the address as it was before break_out_memory_refs was
2497 called. In some cases it is useful to look at this to decide what
2498 needs to be done.
9ebbca7d 2499
a4f6c312 2500 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
9ebbca7d 2501
a4f6c312
SS		 2502 It is always safe for this function to do nothing. It exists to
2503 recognize opportunities to optimize the output.
9ebbca7d
GK		 2504
2505 On RS/6000, first check for the sum of a register with a constant
2506 integer that is out of range. If so, generate code to add the
2507 constant with the low-order 16 bits masked to the register and force
2508 this result into another register (this can be done with `cau').
2509 Then generate an address of REG+(CONST&0xffff), allowing for the
2510 possibility of bit 16 being a one.
2511
2512 Then check for the sum of a register and something not constant, try to
2513 load the other things into a register and return the sum. */
4d588c14 2514
9ebbca7d 2515rtx
a2369ed3
DJ		 2516rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2517 enum machine_mode mode)
0ac081f6 2518{
c4501e62
JJ		 2519 if (GET_CODE (x) == SYMBOL_REF)
2520 {
2521 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2522 if (model != 0)
2523 return rs6000_legitimize_tls_address (x, model);
2524 }
2525
f676971a 2526 if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2527 && GET_CODE (XEXP (x, 0)) == REG
2528 && GET_CODE (XEXP (x, 1)) == CONST_INT
2529 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
f676971a 2530 {
9ebbca7d
GK		 2531 HOST_WIDE_INT high_int, low_int;
2532 rtx sum;
a65c591c
DE		 2533 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2534 high_int = INTVAL (XEXP (x, 1)) - low_int;
9ebbca7d
GK		 2535 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2536 GEN_INT (high_int)), 0);
2537 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2538 }
f676971a 2539 else if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2540 && GET_CODE (XEXP (x, 0)) == REG
2541 && GET_CODE (XEXP (x, 1)) != CONST_INT
6ac7bf2c 2542 && GET_MODE_NUNITS (mode) == 1
a3170dc6
AH		 2543 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2544 || TARGET_POWERPC64
54b695e7
AH		 2545 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2546 && mode != TFmode))
9ebbca7d
GK		 2547 && (TARGET_POWERPC64 || mode != DImode)
2548 && mode != TImode)
2549 {
2550 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2551 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2552 }
0ac081f6
AH		 2553 else if (ALTIVEC_VECTOR_MODE (mode))
2554 {
2555 rtx reg;
2556
2557 /* Make sure both operands are registers. */
2558 if (GET_CODE (x) == PLUS)
9f85ed45 2559 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
0ac081f6
AH		 2560 force_reg (Pmode, XEXP (x, 1)));
2561
2562 reg = force_reg (Pmode, x);
2563 return reg;
2564 }
4d4cbc0e 2565 else if (SPE_VECTOR_MODE (mode)
54b695e7
AH		 2566 || (TARGET_E500_DOUBLE && (mode == DFmode
2567 || mode == DImode)))
a3170dc6 2568 {
54b695e7
AH		 2569 if (mode == DImode)
2570 return NULL_RTX;
a3170dc6
AH		 2571 /* We accept [reg + reg] and [reg + OFFSET]. */
2572
2573 if (GET_CODE (x) == PLUS)
c4ad648e
AM		 2574 {
2575 rtx op1 = XEXP (x, 0);
2576 rtx op2 = XEXP (x, 1);
a3170dc6 2577
c4ad648e 2578 op1 = force_reg (Pmode, op1);
a3170dc6 2579
c4ad648e
AM		 2580 if (GET_CODE (op2) != REG
2581 && (GET_CODE (op2) != CONST_INT
2582 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2583 op2 = force_reg (Pmode, op2);
a3170dc6 2584
c4ad648e
AM		 2585 return gen_rtx_PLUS (Pmode, op1, op2);
2586 }
a3170dc6
AH		 2587
2588 return force_reg (Pmode, x);
2589 }
f1384257
AM		 2590 else if (TARGET_ELF
2591 && TARGET_32BIT
2592 && TARGET_NO_TOC
2593 && ! flag_pic
9ebbca7d 2594 && GET_CODE (x) != CONST_INT
f676971a 2595 && GET_CODE (x) != CONST_DOUBLE
9ebbca7d 2596 && CONSTANT_P (x)
6ac7bf2c
GK		 2597 && GET_MODE_NUNITS (mode) == 1
2598 && (GET_MODE_BITSIZE (mode) <= 32
a3170dc6 2599 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
9ebbca7d
GK		 2600 {
2601 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2602 emit_insn (gen_elf_high (reg, x));
2603 return gen_rtx_LO_SUM (Pmode, reg, x);
9ebbca7d 2604 }
ee890fe2
SS		 2605 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2606 && ! flag_pic
ab82a49f
AP		 2607#if TARGET_MACHO
2608 && ! MACHO_DYNAMIC_NO_PIC_P
2609#endif
ee890fe2 2610 && GET_CODE (x) != CONST_INT
f676971a 2611 && GET_CODE (x) != CONST_DOUBLE
ee890fe2 2612 && CONSTANT_P (x)
f82f556d 2613 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
f676971a 2614 && mode != DImode
ee890fe2
SS		 2615 && mode != TImode)
2616 {
2617 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2618 emit_insn (gen_macho_high (reg, x));
2619 return gen_rtx_LO_SUM (Pmode, reg, x);
ee890fe2 2620 }
f676971a 2621 else if (TARGET_TOC
4d588c14 2622 && constant_pool_expr_p (x)
a9098fd0 2623 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
9ebbca7d
GK		 2624 {
2625 return create_TOC_reference (x);
2626 }
2627 else
2628 return NULL_RTX;
2629}
258bfae2 2630
c973d557
JJ		 2631/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2632 We need to emit DTP-relative relocations. */
2633
2634void
2635rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2636{
2637 switch (size)
2638 {
2639 case 4:
2640 fputs ("\t.long\t", file);
2641 break;
2642 case 8:
2643 fputs (DOUBLE_INT_ASM_OP, file);
2644 break;
2645 default:
37409796 2646 gcc_unreachable ();
c973d557
JJ		 2647 }
2648 output_addr_const (file, x);
2649 fputs ("@dtprel+0x8000", file);
2650}
2651
c4501e62
JJ		 2652/* Construct the SYMBOL_REF for the tls_get_addr function. */
2653
2654static GTY(()) rtx rs6000_tls_symbol;
2655static rtx
863d938c 2656rs6000_tls_get_addr (void)
c4501e62
JJ		 2657{
2658 if (!rs6000_tls_symbol)
2659 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2660
2661 return rs6000_tls_symbol;
2662}
2663
2664/* Construct the SYMBOL_REF for TLS GOT references. */
2665
2666static GTY(()) rtx rs6000_got_symbol;
2667static rtx
863d938c 2668rs6000_got_sym (void)
c4501e62
JJ		 2669{
2670 if (!rs6000_got_symbol)
2671 {
2672 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2673 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2674 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
f676971a 2675 }
c4501e62
JJ		 2676
2677 return rs6000_got_symbol;
2678}
2679
2680/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2681 this (thread-local) address. */
2682
2683static rtx
a2369ed3 2684rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
c4501e62
JJ		 2685{
2686 rtx dest, insn;
2687
2688 dest = gen_reg_rtx (Pmode);
2689 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2690 {
2691 rtx tlsreg;
2692
2693 if (TARGET_64BIT)
2694 {
2695 tlsreg = gen_rtx_REG (Pmode, 13);
2696 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2697 }
2698 else
2699 {
2700 tlsreg = gen_rtx_REG (Pmode, 2);
2701 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2702 }
2703 emit_insn (insn);
2704 }
2705 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2706 {
2707 rtx tlsreg, tmp;
2708
2709 tmp = gen_reg_rtx (Pmode);
2710 if (TARGET_64BIT)
2711 {
2712 tlsreg = gen_rtx_REG (Pmode, 13);
2713 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2714 }
2715 else
2716 {
2717 tlsreg = gen_rtx_REG (Pmode, 2);
2718 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2719 }
2720 emit_insn (insn);
2721 if (TARGET_64BIT)
2722 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2723 else
2724 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2725 emit_insn (insn);
2726 }
2727 else
2728 {
2729 rtx r3, got, tga, tmp1, tmp2, eqv;
2730
2731 if (TARGET_64BIT)
2732 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2733 else
2734 {
2735 if (flag_pic == 1)
2736 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2737 else
2738 {
2739 rtx gsym = rs6000_got_sym ();
2740 got = gen_reg_rtx (Pmode);
2741 if (flag_pic == 0)
2742 rs6000_emit_move (got, gsym, Pmode);
2743 else
2744 {
ccbca5e4 2745 rtx tempLR, tmp3, mem;
c4501e62
JJ		 2746 rtx first, last;
2747
c4501e62
JJ		 2748 tempLR = gen_reg_rtx (Pmode);
2749 tmp1 = gen_reg_rtx (Pmode);
2750 tmp2 = gen_reg_rtx (Pmode);
2751 tmp3 = gen_reg_rtx (Pmode);
542a8afa 2752 mem = gen_const_mem (Pmode, tmp1);
c4501e62 2753
ccbca5e4 2754 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
c4501e62
JJ		 2755 emit_move_insn (tmp1, tempLR);
2756 emit_move_insn (tmp2, mem);
2757 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2758 last = emit_move_insn (got, tmp3);
2759 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2760 REG_NOTES (last));
2761 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2762 REG_NOTES (first));
2763 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2764 REG_NOTES (last));
2765 }
2766 }
2767 }
2768
2769 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2770 {
2771 r3 = gen_rtx_REG (Pmode, 3);
2772 if (TARGET_64BIT)
2773 insn = gen_tls_gd_64 (r3, got, addr);
2774 else
2775 insn = gen_tls_gd_32 (r3, got, addr);
2776 start_sequence ();
2777 emit_insn (insn);
2778 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2779 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2780 insn = emit_call_insn (insn);
2781 CONST_OR_PURE_CALL_P (insn) = 1;
2782 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2783 insn = get_insns ();
2784 end_sequence ();
2785 emit_libcall_block (insn, dest, r3, addr);
2786 }
2787 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2788 {
2789 r3 = gen_rtx_REG (Pmode, 3);
2790 if (TARGET_64BIT)
2791 insn = gen_tls_ld_64 (r3, got);
2792 else
2793 insn = gen_tls_ld_32 (r3, got);
2794 start_sequence ();
2795 emit_insn (insn);
2796 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2797 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2798 insn = emit_call_insn (insn);
2799 CONST_OR_PURE_CALL_P (insn) = 1;
2800 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2801 insn = get_insns ();
2802 end_sequence ();
2803 tmp1 = gen_reg_rtx (Pmode);
2804 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2805 UNSPEC_TLSLD);
2806 emit_libcall_block (insn, tmp1, r3, eqv);
2807 if (rs6000_tls_size == 16)
2808 {
2809 if (TARGET_64BIT)
2810 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2811 else
2812 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2813 }
2814 else if (rs6000_tls_size == 32)
2815 {
2816 tmp2 = gen_reg_rtx (Pmode);
2817 if (TARGET_64BIT)
2818 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2819 else
2820 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2821 emit_insn (insn);
2822 if (TARGET_64BIT)
2823 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2824 else
2825 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2826 }
2827 else
2828 {
2829 tmp2 = gen_reg_rtx (Pmode);
2830 if (TARGET_64BIT)
2831 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2832 else
2833 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2834 emit_insn (insn);
2835 insn = gen_rtx_SET (Pmode, dest,
2836 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2837 }
2838 emit_insn (insn);
2839 }
2840 else
2841 {
2842 /* IE, or 64 bit offset LE. */
2843 tmp2 = gen_reg_rtx (Pmode);
2844 if (TARGET_64BIT)
2845 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2846 else
2847 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2848 emit_insn (insn);
2849 if (TARGET_64BIT)
2850 insn = gen_tls_tls_64 (dest, tmp2, addr);
2851 else
2852 insn = gen_tls_tls_32 (dest, tmp2, addr);
2853 emit_insn (insn);
2854 }
2855 }
2856
2857 return dest;
2858}
2859
c4501e62
JJ		 2860/* Return 1 if X contains a thread-local symbol. */
2861
2862bool
a2369ed3 2863rs6000_tls_referenced_p (rtx x)
c4501e62 2864{
cd413cab
AP		 2865 if (! TARGET_HAVE_TLS)
2866 return false;
2867
c4501e62
JJ		 2868 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2869}
2870
2871/* Return 1 if *X is a thread-local symbol. This is the same as
2872 rs6000_tls_symbol_ref except for the type of the unused argument. */
2873
9390387d 2874static int
a2369ed3 2875rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 2876{
2877 return RS6000_SYMBOL_REF_TLS_P (*x);
2878}
2879
24ea750e
DJ		 2880/* The convention appears to be to define this wherever it is used.
2881 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2882 is now used here. */
2883#ifndef REG_MODE_OK_FOR_BASE_P
2884#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2885#endif
2886
2887/* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2888 replace the input X, or the original X if no replacement is called for.
2889 The output parameter *WIN is 1 if the calling macro should goto WIN,
2890 0 if it should not.
2891
2892 For RS/6000, we wish to handle large displacements off a base
2893 register by splitting the addend across an addiu/addis and the mem insn.
2894 This cuts number of extra insns needed from 3 to 1.
2895
2896 On Darwin, we use this to generate code for floating point constants.
2897 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2898 The Darwin code is inside #if TARGET_MACHO because only then is
2899 machopic_function_base_name() defined. */
2900rtx
f676971a 2901rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
c4ad648e
AM		 2902 int opnum, int type,
2903 int ind_levels ATTRIBUTE_UNUSED, int *win)
24ea750e 2904{
f676971a 2905 /* We must recognize output that we have already generated ourselves. */
24ea750e
DJ		 2906 if (GET_CODE (x) == PLUS
2907 && GET_CODE (XEXP (x, 0)) == PLUS
2908 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2909 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2910 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2911 {
2912 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 2913 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2914 opnum, (enum reload_type)type);
24ea750e
DJ		 2915 *win = 1;
2916 return x;
2917 }
3deb2758 2918
24ea750e
DJ		 2919#if TARGET_MACHO
2920 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2921 && GET_CODE (x) == LO_SUM
2922 && GET_CODE (XEXP (x, 0)) == PLUS
2923 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2924 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2925 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2926 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2927 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
2928 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
2929 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
2930 {
2931 /* Result of previous invocation of this function on Darwin
6f317ef3 2932 floating point constant. */
24ea750e 2933 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 2934 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2935 opnum, (enum reload_type)type);
24ea750e
DJ		 2936 *win = 1;
2937 return x;
2938 }
2939#endif
4937d02d
DE		 2940
2941 /* Force ld/std non-word aligned offset into base register by wrapping
2942 in offset 0. */
2943 if (GET_CODE (x) == PLUS
2944 && GET_CODE (XEXP (x, 0)) == REG
2945 && REGNO (XEXP (x, 0)) < 32
2946 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
2947 && GET_CODE (XEXP (x, 1)) == CONST_INT
2948 && (INTVAL (XEXP (x, 1)) & 3) != 0
78796ad5 2949 && !ALTIVEC_VECTOR_MODE (mode)
4937d02d
DE		 2950 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
2951 && TARGET_POWERPC64)
2952 {
2953 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
2954 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2955 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2956 opnum, (enum reload_type) type);
2957 *win = 1;
2958 return x;
2959 }
2960
24ea750e
DJ		 2961 if (GET_CODE (x) == PLUS
2962 && GET_CODE (XEXP (x, 0)) == REG
2963 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2964 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
78c875e8 2965 && GET_CODE (XEXP (x, 1)) == CONST_INT
93638d7a 2966 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 2967 && !(TARGET_E500_DOUBLE && (mode == DFmode
2968 || mode == DImode))
78c875e8 2969 && !ALTIVEC_VECTOR_MODE (mode))
24ea750e
DJ		 2970 {
2971 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2972 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2973 HOST_WIDE_INT high
c4ad648e 2974 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
24ea750e
DJ		 2975
2976 /* Check for 32-bit overflow. */
2977 if (high + low != val)
c4ad648e 2978 {
24ea750e
DJ		 2979 *win = 0;
2980 return x;
2981 }
2982
2983 /* Reload the high part into a base reg; leave the low part
c4ad648e 2984 in the mem directly. */
24ea750e
DJ		 2985
2986 x = gen_rtx_PLUS (GET_MODE (x),
c4ad648e
AM		 2987 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
2988 GEN_INT (high)),
2989 GEN_INT (low));
24ea750e
DJ		 2990
2991 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 2992 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2993 opnum, (enum reload_type)type);
24ea750e
DJ		 2994 *win = 1;
2995 return x;
2996 }
4937d02d 2997
24ea750e
DJ		 2998#if TARGET_MACHO
2999 if (GET_CODE (x) == SYMBOL_REF
3000 && DEFAULT_ABI == ABI_DARWIN
69ef87e2 3001 && !ALTIVEC_VECTOR_MODE (mode)
a29077da 3002 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
0d8c1c97
AM		 3003 /* Don't do this for TFmode, since the result isn't offsettable.
3004 The same goes for DImode without 64-bit gprs. */
3005 && mode != TFmode
3006 && (mode != DImode || TARGET_POWERPC64))
24ea750e 3007 {
a29077da
GK		 3008 if (flag_pic)
3009 {
3010 rtx offset = gen_rtx_CONST (Pmode,
3011 gen_rtx_MINUS (Pmode, x,
11abc112 3012 machopic_function_base_sym ()));
a29077da
GK		 3013 x = gen_rtx_LO_SUM (GET_MODE (x),
3014 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3015 gen_rtx_HIGH (Pmode, offset)), offset);
3016 }
3017 else
3018 x = gen_rtx_LO_SUM (GET_MODE (x),
c4ad648e 3019 gen_rtx_HIGH (Pmode, x), x);
a29077da 3020
24ea750e 3021 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
a29077da
GK		 3022 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3023 opnum, (enum reload_type)type);
24ea750e
DJ		 3024 *win = 1;
3025 return x;
3026 }
3027#endif
4937d02d 3028
24ea750e 3029 if (TARGET_TOC
4d588c14 3030 && constant_pool_expr_p (x)
c1f11548 3031 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
24ea750e
DJ		 3032 {
3033 (x) = create_TOC_reference (x);
3034 *win = 1;
3035 return x;
3036 }
3037 *win = 0;
3038 return x;
f676971a 3039}
24ea750e 3040
258bfae2
FS		 3041/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3042 that is a valid memory address for an instruction.
3043 The MODE argument is the machine mode for the MEM expression
3044 that wants to use this address.
3045
3046 On the RS/6000, there are four valid address: a SYMBOL_REF that
3047 refers to a constant pool entry of an address (or the sum of it
3048 plus a constant), a short (16-bit signed) constant plus a register,
3049 the sum of two registers, or a register indirect, possibly with an
5bdc5878 3050 auto-increment. For DFmode and DImode with a constant plus register,
258bfae2
FS		 3051 we must ensure that both words are addressable or PowerPC64 with offset
3052 word aligned.
3053
3054 For modes spanning multiple registers (DFmode in 32-bit GPRs,
76d2b81d 3055 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
258bfae2
FS		 3056 adjacent memory cells are accessed by adding word-sized offsets
3057 during assembly output. */
3058int
a2369ed3 3059rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
258bfae2 3060{
850e8d3d
DN		 3061 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3062 if (TARGET_ALTIVEC
3063 && ALTIVEC_VECTOR_MODE (mode)
3064 && GET_CODE (x) == AND
3065 && GET_CODE (XEXP (x, 1)) == CONST_INT
3066 && INTVAL (XEXP (x, 1)) == -16)
3067 x = XEXP (x, 0);
3068
c4501e62
JJ		 3069 if (RS6000_SYMBOL_REF_TLS_P (x))
3070 return 0;
4d588c14 3071 if (legitimate_indirect_address_p (x, reg_ok_strict))
258bfae2
FS		 3072 return 1;
3073 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
0d6d6892 3074 && !ALTIVEC_VECTOR_MODE (mode)
a3170dc6 3075 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 3076 /* Restrict addressing for DI because of our SUBREG hackery. */
3077 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
258bfae2 3078 && TARGET_UPDATE
4d588c14 3079 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
258bfae2 3080 return 1;
4d588c14 3081 if (legitimate_small_data_p (mode, x))
258bfae2 3082 return 1;
4d588c14 3083 if (legitimate_constant_pool_address_p (x))
258bfae2
FS		 3084 return 1;
3085 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3086 if (! reg_ok_strict
3087 && GET_CODE (x) == PLUS
3088 && GET_CODE (XEXP (x, 0)) == REG
708d2456 3089 && (XEXP (x, 0) == virtual_stack_vars_rtx
c4ad648e 3090 || XEXP (x, 0) == arg_pointer_rtx)
258bfae2
FS		 3091 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3092 return 1;
76d2b81d 3093 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3094 return 1;
3095 if (mode != TImode
76d2b81d 3096 && mode != TFmode
a3170dc6
AH		 3097 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3098 || TARGET_POWERPC64
4d4cbc0e 3099 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
258bfae2 3100 && (TARGET_POWERPC64 || mode != DImode)
4d588c14 3101 && legitimate_indexed_address_p (x, reg_ok_strict))
258bfae2 3102 return 1;
4d588c14 3103 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3104 return 1;
3105 return 0;
3106}
4d588c14
RH		 3107
3108/* Go to LABEL if ADDR (a legitimate address expression)
3109 has an effect that depends on the machine mode it is used for.
3110
3111 On the RS/6000 this is true of all integral offsets (since AltiVec
3112 modes don't allow them) or is a pre-increment or decrement.
3113
3114 ??? Except that due to conceptual problems in offsettable_address_p
3115 we can't really report the problems of integral offsets. So leave
f676971a 3116 this assuming that the adjustable offset must be valid for the
4d588c14
RH		 3117 sub-words of a TFmode operand, which is what we had before. */
3118
3119bool
a2369ed3 3120rs6000_mode_dependent_address (rtx addr)
4d588c14
RH		 3121{
3122 switch (GET_CODE (addr))
3123 {
3124 case PLUS:
3125 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3126 {
3127 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3128 return val + 12 + 0x8000 >= 0x10000;
3129 }
3130 break;
3131
3132 case LO_SUM:
3133 return true;
3134
3135 case PRE_INC:
3136 case PRE_DEC:
3137 return TARGET_UPDATE;
3138
3139 default:
3140 break;
3141 }
3142
3143 return false;
3144}
d8ecbcdb
AH		 3145
3146/* Return number of consecutive hard regs needed starting at reg REGNO
3147 to hold something of mode MODE.
3148 This is ordinarily the length in words of a value of mode MODE
3149 but can be less for certain modes in special long registers.
3150
3151 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3152 scalar instructions. The upper 32 bits are only available to the
3153 SIMD instructions.
3154
3155 POWER and PowerPC GPRs hold 32 bits worth;
3156 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3157
3158int
3159rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3160{
3161 if (FP_REGNO_P (regno))
3162 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3163
4d4cbc0e
AH		 3164 if (TARGET_E500_DOUBLE && mode == DFmode)
3165 return 1;
3166
d8ecbcdb
AH		 3167 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3168 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3169
3170 if (ALTIVEC_REGNO_P (regno))
3171 return
3172 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3173
3174 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3175}
2aa4498c
AH		 3176
3177/* Change register usage conditional on target flags. */
3178void
3179rs6000_conditional_register_usage (void)
3180{
3181 int i;
3182
3183 /* Set MQ register fixed (already call_used) if not POWER
3184 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3185 be allocated. */
3186 if (! TARGET_POWER)
3187 fixed_regs[64] = 1;
3188
3189 /* 64-bit AIX reserves GPR13 for thread-private data. */
3190 if (TARGET_64BIT)
3191 fixed_regs[13] = call_used_regs[13]
3192 = call_really_used_regs[13] = 1;
3193
3194 /* Conditionally disable FPRs. */
3195 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3196 for (i = 32; i < 64; i++)
3197 fixed_regs[i] = call_used_regs[i]
c4ad648e 3198 = call_really_used_regs[i] = 1;
2aa4498c
AH		 3199
3200 if (DEFAULT_ABI == ABI_V4
3201 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3202 && flag_pic == 2)
3203 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3204
3205 if (DEFAULT_ABI == ABI_V4
3206 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3207 && flag_pic == 1)
3208 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3209 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3210 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3211
3212 if (DEFAULT_ABI == ABI_DARWIN
3213 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3214 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3215 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3216 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3217 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3218
b4db40bf
JJ		 3219 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3220 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3221 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3222
2aa4498c
AH		 3223 if (TARGET_ALTIVEC)
3224 global_regs[VSCR_REGNO] = 1;
3225
3226 if (TARGET_SPE)
3227 {
3228 global_regs[SPEFSCR_REGNO] = 1;
3229 fixed_regs[FIXED_SCRATCH]
c4ad648e 3230 = call_used_regs[FIXED_SCRATCH]
2aa4498c
AH		 3231 = call_really_used_regs[FIXED_SCRATCH] = 1;
3232 }
3233
3234 if (! TARGET_ALTIVEC)
3235 {
3236 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3237 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3238 call_really_used_regs[VRSAVE_REGNO] = 1;
3239 }
3240
3241 if (TARGET_ALTIVEC_ABI)
3242 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3243 call_used_regs[i] = call_really_used_regs[i] = 1;
3244}
fb4d4348 3245\f
a4f6c312
SS		 3246/* Try to output insns to set TARGET equal to the constant C if it can
3247 be done in less than N insns. Do all computations in MODE.
3248 Returns the place where the output has been placed if it can be
3249 done and the insns have been emitted. If it would take more than N
3250 insns, zero is returned and no insns and emitted. */
2bfcf297
DB		 3251
3252rtx
f676971a 3253rs6000_emit_set_const (rtx dest, enum machine_mode mode,
a2369ed3 3254 rtx source, int n ATTRIBUTE_UNUSED)
2bfcf297 3255{
af8cb5c5 3256 rtx result, insn, set;
2bfcf297
DB		 3257 HOST_WIDE_INT c0, c1;
3258
37409796 3259 switch (mode)
2bfcf297 3260 {
37409796
NS		 3261 case QImode:
3262 case HImode:
2bfcf297 3263 if (dest == NULL)
c4ad648e 3264 dest = gen_reg_rtx (mode);
2bfcf297
DB		 3265 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3266 return dest;
37409796
NS		 3267
3268 case SImode:
af8cb5c5 3269 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
37409796 3270
af8cb5c5
DE		 3271 emit_insn (gen_rtx_SET (VOIDmode, result,
3272 GEN_INT (INTVAL (source)
3273 & (~ (HOST_WIDE_INT) 0xffff))));
3274 emit_insn (gen_rtx_SET (VOIDmode, dest,
3275 gen_rtx_IOR (SImode, result,
3276 GEN_INT (INTVAL (source) & 0xffff))));
3277 result = dest;
37409796
NS		 3278 break;
3279
3280 case DImode:
3281 switch (GET_CODE (source))
af8cb5c5 3282 {
37409796 3283 case CONST_INT:
af8cb5c5
DE		 3284 c0 = INTVAL (source);
3285 c1 = -(c0 < 0);
37409796
NS		 3286 break;
3287
3288 case CONST_DOUBLE:
2bfcf297 3289#if HOST_BITS_PER_WIDE_INT >= 64
af8cb5c5
DE		 3290 c0 = CONST_DOUBLE_LOW (source);
3291 c1 = -(c0 < 0);
2bfcf297 3292#else
af8cb5c5
DE		 3293 c0 = CONST_DOUBLE_LOW (source);
3294 c1 = CONST_DOUBLE_HIGH (source);
2bfcf297 3295#endif
37409796
NS		 3296 break;
3297
3298 default:
3299 gcc_unreachable ();
af8cb5c5 3300 }
af8cb5c5
DE		 3301
3302 result = rs6000_emit_set_long_const (dest, c0, c1);
37409796
NS		 3303 break;
3304
3305 default:
3306 gcc_unreachable ();
2bfcf297 3307 }
2bfcf297 3308
af8cb5c5
DE		 3309 insn = get_last_insn ();
3310 set = single_set (insn);
3311 if (! CONSTANT_P (SET_SRC (set)))
3312 set_unique_reg_note (insn, REG_EQUAL, source);
3313
3314 return result;
2bfcf297
DB		 3315}
3316
3317/* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3318 fall back to a straight forward decomposition. We do this to avoid
3319 exponential run times encountered when looking for longer sequences
3320 with rs6000_emit_set_const. */
3321static rtx
a2369ed3 3322rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
2bfcf297
DB		 3323{
3324 if (!TARGET_POWERPC64)
3325 {
3326 rtx operand1, operand2;
3327
3328 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3329 DImode);
3330 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3331 DImode);
3332 emit_move_insn (operand1, GEN_INT (c1));
3333 emit_move_insn (operand2, GEN_INT (c2));
3334 }
3335 else
3336 {
bc06712d 3337 HOST_WIDE_INT ud1, ud2, ud3, ud4;
252b88f7 3338
bc06712d 3339 ud1 = c1 & 0xffff;
f921c9c9 3340 ud2 = (c1 & 0xffff0000) >> 16;
2bfcf297 3341#if HOST_BITS_PER_WIDE_INT >= 64
bc06712d 3342 c2 = c1 >> 32;
2bfcf297 3343#endif
bc06712d 3344 ud3 = c2 & 0xffff;
f921c9c9 3345 ud4 = (c2 & 0xffff0000) >> 16;
2bfcf297 3346
f676971a 3347 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
bc06712d 3348 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
2bfcf297 3349 {
bc06712d 3350 if (ud1 & 0x8000)
b78d48dd 3351 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
bc06712d
TR		 3352 else
3353 emit_move_insn (dest, GEN_INT (ud1));
2bfcf297 3354 }
2bfcf297 3355
f676971a 3356 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
bc06712d 3357 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
252b88f7 3358 {
bc06712d 3359 if (ud2 & 0x8000)
f676971a 3360 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
bc06712d 3361 - 0x80000000));
252b88f7 3362 else
bc06712d
TR		 3363 emit_move_insn (dest, GEN_INT (ud2 << 16));
3364 if (ud1 != 0)
3365 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
252b88f7 3366 }
f676971a 3367 else if ((ud4 == 0xffff && (ud3 & 0x8000))
bc06712d
TR		 3368 || (ud4 == 0 && ! (ud3 & 0x8000)))
3369 {
3370 if (ud3 & 0x8000)
f676971a 3371 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
bc06712d
TR		 3372 - 0x80000000));
3373 else
3374 emit_move_insn (dest, GEN_INT (ud3 << 16));
3375
3376 if (ud2 != 0)
3377 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3378 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3379 if (ud1 != 0)
3380 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3381 }
f676971a 3382 else
bc06712d
TR		 3383 {
3384 if (ud4 & 0x8000)
f676971a 3385 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
bc06712d
TR		 3386 - 0x80000000));
3387 else
3388 emit_move_insn (dest, GEN_INT (ud4 << 16));
3389
3390 if (ud3 != 0)
3391 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
2bfcf297 3392
bc06712d
TR		 3393 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3394 if (ud2 != 0)
f676971a
EC		 3395 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3396 GEN_INT (ud2 << 16)));
bc06712d
TR		 3397 if (ud1 != 0)
3398 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3399 }
3400 }
2bfcf297
DB		 3401 return dest;
3402}
3403
76d2b81d
DJ		 3404/* Helper for the following. Get rid of [r+r] memory refs
3405 in cases where it won't work (TImode, TFmode). */
3406
3407static void
3408rs6000_eliminate_indexed_memrefs (rtx operands[2])
3409{
3410 if (GET_CODE (operands[0]) == MEM
3411 && GET_CODE (XEXP (operands[0], 0)) != REG
55aa0757 3412 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
76d2b81d
DJ		 3413 && ! reload_in_progress)
3414 operands[0]
3415 = replace_equiv_address (operands[0],
3416 copy_addr_to_reg (XEXP (operands[0], 0)));
3417
3418 if (GET_CODE (operands[1]) == MEM
3419 && GET_CODE (XEXP (operands[1], 0)) != REG
55aa0757 3420 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
76d2b81d
DJ		 3421 && ! reload_in_progress)
3422 operands[1]
3423 = replace_equiv_address (operands[1],
3424 copy_addr_to_reg (XEXP (operands[1], 0)));
3425}
3426
fb4d4348
GK		 3427/* Emit a move from SOURCE to DEST in mode MODE. */
3428void
a2369ed3 3429rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
fb4d4348
GK		 3430{
3431 rtx operands[2];
3432 operands[0] = dest;
3433 operands[1] = source;
f676971a 3434
fb4d4348
GK		 3435 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3436 if (GET_CODE (operands[1]) == CONST_DOUBLE
3437 && ! FLOAT_MODE_P (mode)
3438 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3439 {
3440 /* FIXME. This should never happen. */
3441 /* Since it seems that it does, do the safe thing and convert
3442 to a CONST_INT. */
2496c7bd 3443 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
fb4d4348 3444 }
37409796
NS		 3445 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3446 || FLOAT_MODE_P (mode)
3447 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3448 || CONST_DOUBLE_LOW (operands[1]) < 0)
3449 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3450 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3451
c9e8cb32
DD		 3452 /* Check if GCC is setting up a block move that will end up using FP
3453 registers as temporaries. We must make sure this is acceptable. */
3454 if (GET_CODE (operands[0]) == MEM
3455 && GET_CODE (operands[1]) == MEM
3456 && mode == DImode
41543739
GK		 3457 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3458 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3459 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3460 ? 32 : MEM_ALIGN (operands[0])))
3461 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
f676971a 3462 ? 32
41543739
GK		 3463 : MEM_ALIGN (operands[1]))))
3464 && ! MEM_VOLATILE_P (operands [0])
3465 && ! MEM_VOLATILE_P (operands [1]))
c9e8cb32 3466 {
41543739
GK		 3467 emit_move_insn (adjust_address (operands[0], SImode, 0),
3468 adjust_address (operands[1], SImode, 0));
3469 emit_move_insn (adjust_address (operands[0], SImode, 4),
3470 adjust_address (operands[1], SImode, 4));
c9e8cb32
DD		 3471 return;
3472 }
630d42a0 3473
55aa0757 3474 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
c9dbf840 3475 && !gpc_reg_operand (operands[1], mode))
f6219a5e 3476 operands[1] = force_reg (mode, operands[1]);
a9098fd0 3477
a3170dc6
AH		 3478 if (mode == SFmode && ! TARGET_POWERPC
3479 && TARGET_HARD_FLOAT && TARGET_FPRS
ffc14f31 3480 && GET_CODE (operands[0]) == MEM)
fb4d4348 3481 {
ffc14f31
GK		 3482 int regnum;
3483
3484 if (reload_in_progress || reload_completed)
3485 regnum = true_regnum (operands[1]);
3486 else if (GET_CODE (operands[1]) == REG)
3487 regnum = REGNO (operands[1]);
3488 else
3489 regnum = -1;
f676971a 3490
fb4d4348
GK		 3491 /* If operands[1] is a register, on POWER it may have
3492 double-precision data in it, so truncate it to single
3493 precision. */
3494 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3495 {
3496 rtx newreg;
3497 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3498 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3499 operands[1] = newreg;
3500 }
3501 }
3502
c4501e62
JJ		 3503 /* Recognize the case where operand[1] is a reference to thread-local
3504 data and load its address to a register. */
3505 if (GET_CODE (operands[1]) == SYMBOL_REF)
3506 {
3507 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3508 if (model != 0)
3509 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3510 }
3511
8f4e6caf
RH		 3512 /* Handle the case where reload calls us with an invalid address. */
3513 if (reload_in_progress && mode == Pmode
69ef87e2 3514 && (! general_operand (operands[1], mode)
8f4e6caf
RH		 3515 || ! nonimmediate_operand (operands[0], mode)))
3516 goto emit_set;
3517
a9baceb1
GK		 3518 /* 128-bit constant floating-point values on Darwin should really be
3519 loaded as two parts. */
3520 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3521 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3522 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3523 {
3524 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3525 know how to get a DFmode SUBREG of a TFmode. */
3526 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3527 simplify_gen_subreg (DImode, operands[1], mode, 0),
3528 DImode);
3529 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3530 GET_MODE_SIZE (DImode)),
3531 simplify_gen_subreg (DImode, operands[1], mode,
3532 GET_MODE_SIZE (DImode)),
3533 DImode);
3534 return;
3535 }
3536
fb4d4348
GK		 3537 /* FIXME: In the long term, this switch statement should go away
3538 and be replaced by a sequence of tests based on things like
3539 mode == Pmode. */
3540 switch (mode)
3541 {
3542 case HImode:
3543 case QImode:
3544 if (CONSTANT_P (operands[1])
3545 && GET_CODE (operands[1]) != CONST_INT)
a9098fd0 3546 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348
GK		 3547 break;
3548
06f4e019 3549 case TFmode:
76d2b81d
DJ		 3550 rs6000_eliminate_indexed_memrefs (operands);
3551 /* fall through */
3552
fb4d4348
GK		 3553 case DFmode:
3554 case SFmode:
f676971a 3555 if (CONSTANT_P (operands[1])
fb4d4348 3556 && ! easy_fp_constant (operands[1], mode))
a9098fd0 3557 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3558 break;
f676971a 3559
0ac081f6
AH		 3560 case V16QImode:
3561 case V8HImode:
3562 case V4SFmode:
3563 case V4SImode:
a3170dc6
AH		 3564 case V4HImode:
3565 case V2SFmode:
3566 case V2SImode:
00a892b8 3567 case V1DImode:
69ef87e2 3568 if (CONSTANT_P (operands[1])
d744e06e 3569 && !easy_vector_constant (operands[1], mode))
0ac081f6
AH		 3570 operands[1] = force_const_mem (mode, operands[1]);
3571 break;
f676971a 3572
fb4d4348 3573 case SImode:
a9098fd0 3574 case DImode:
fb4d4348
GK		 3575 /* Use default pattern for address of ELF small data */
3576 if (TARGET_ELF
a9098fd0 3577 && mode == Pmode
f607bc57 3578 && DEFAULT_ABI == ABI_V4
f676971a 3579 && (GET_CODE (operands[1]) == SYMBOL_REF
a9098fd0
GK		 3580 || GET_CODE (operands[1]) == CONST)
3581 && small_data_operand (operands[1], mode))
fb4d4348
GK		 3582 {
3583 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3584 return;
3585 }
3586
f607bc57 3587 if (DEFAULT_ABI == ABI_V4
a9098fd0
GK		 3588 && mode == Pmode && mode == SImode
3589 && flag_pic == 1 && got_operand (operands[1], mode))
fb4d4348
GK		 3590 {
3591 emit_insn (gen_movsi_got (operands[0], operands[1]));
3592 return;
3593 }
3594
ee890fe2 3595 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
f1384257
AM		 3596 && TARGET_NO_TOC
3597 && ! flag_pic
a9098fd0 3598 && mode == Pmode
fb4d4348
GK		 3599 && CONSTANT_P (operands[1])
3600 && GET_CODE (operands[1]) != HIGH
3601 && GET_CODE (operands[1]) != CONST_INT)
3602 {
a9098fd0 3603 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
fb4d4348
GK		 3604
3605 /* If this is a function address on -mcall-aixdesc,
3606 convert it to the address of the descriptor. */
3607 if (DEFAULT_ABI == ABI_AIX
3608 && GET_CODE (operands[1]) == SYMBOL_REF
3609 && XSTR (operands[1], 0)[0] == '.')
3610 {
3611 const char *name = XSTR (operands[1], 0);
3612 rtx new_ref;
3613 while (*name == '.')
3614 name++;
3615 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3616 CONSTANT_POOL_ADDRESS_P (new_ref)
3617 = CONSTANT_POOL_ADDRESS_P (operands[1]);
d1908feb 3618 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
fb4d4348 3619 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
d1908feb 3620 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
fb4d4348
GK		 3621 operands[1] = new_ref;
3622 }
7509c759 3623
ee890fe2
SS		 3624 if (DEFAULT_ABI == ABI_DARWIN)
3625 {
ab82a49f
AP		 3626#if TARGET_MACHO
3627 if (MACHO_DYNAMIC_NO_PIC_P)
3628 {
3629 /* Take care of any required data indirection. */
3630 operands[1] = rs6000_machopic_legitimize_pic_address (
3631 operands[1], mode, operands[0]);
3632 if (operands[0] != operands[1])
3633 emit_insn (gen_rtx_SET (VOIDmode,
c4ad648e 3634 operands[0], operands[1]));
ab82a49f
AP		 3635 return;
3636 }
3637#endif
b8a55285
AP		 3638 emit_insn (gen_macho_high (target, operands[1]));
3639 emit_insn (gen_macho_low (operands[0], target, operands[1]));
ee890fe2
SS		 3640 return;
3641 }
3642
fb4d4348
GK		 3643 emit_insn (gen_elf_high (target, operands[1]));
3644 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3645 return;
3646 }
3647
a9098fd0
GK		 3648 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3649 and we have put it in the TOC, we just need to make a TOC-relative
3650 reference to it. */
3651 if (TARGET_TOC
3652 && GET_CODE (operands[1]) == SYMBOL_REF
4d588c14 3653 && constant_pool_expr_p (operands[1])
a9098fd0
GK		 3654 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3655 get_pool_mode (operands[1])))
fb4d4348 3656 {
a9098fd0 3657 operands[1] = create_TOC_reference (operands[1]);
fb4d4348 3658 }
a9098fd0
GK		 3659 else if (mode == Pmode
3660 && CONSTANT_P (operands[1])
38886f37
AO		 3661 && ((GET_CODE (operands[1]) != CONST_INT
3662 && ! easy_fp_constant (operands[1], mode))
3663 || (GET_CODE (operands[1]) == CONST_INT
3664 && num_insns_constant (operands[1], mode) > 2)
3665 || (GET_CODE (operands[0]) == REG
3666 && FP_REGNO_P (REGNO (operands[0]))))
a9098fd0 3667 && GET_CODE (operands[1]) != HIGH
4d588c14
RH		 3668 && ! legitimate_constant_pool_address_p (operands[1])
3669 && ! toc_relative_expr_p (operands[1]))
fb4d4348
GK		 3670 {
3671 /* Emit a USE operation so that the constant isn't deleted if
3672 expensive optimizations are turned on because nobody
3673 references it. This should only be done for operands that
3674 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3675 This should not be done for operands that contain LABEL_REFs.
3676 For now, we just handle the obvious case. */
3677 if (GET_CODE (operands[1]) != LABEL_REF)
3678 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3679
c859cda6 3680#if TARGET_MACHO
ee890fe2 3681 /* Darwin uses a special PIC legitimizer. */
ab82a49f 3682 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
ee890fe2 3683 {
ee890fe2
SS		 3684 operands[1] =
3685 rs6000_machopic_legitimize_pic_address (operands[1], mode,
c859cda6
DJ		 3686 operands[0]);
3687 if (operands[0] != operands[1])
3688 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
ee890fe2
SS		 3689 return;
3690 }
c859cda6 3691#endif
ee890fe2 3692
fb4d4348
GK		 3693 /* If we are to limit the number of things we put in the TOC and
3694 this is a symbol plus a constant we can add in one insn,
3695 just put the symbol in the TOC and add the constant. Don't do
3696 this if reload is in progress. */
3697 if (GET_CODE (operands[1]) == CONST
3698 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3699 && GET_CODE (XEXP (operands[1], 0)) == PLUS
a9098fd0 3700 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
fb4d4348
GK		 3701 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3702 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3703 && ! side_effects_p (operands[0]))
3704 {
a4f6c312
SS		 3705 rtx sym =
3706 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
fb4d4348
GK		 3707 rtx other = XEXP (XEXP (operands[1], 0), 1);
3708
a9098fd0
GK		 3709 sym = force_reg (mode, sym);
3710 if (mode == SImode)
3711 emit_insn (gen_addsi3 (operands[0], sym, other));
3712 else
3713 emit_insn (gen_adddi3 (operands[0], sym, other));
fb4d4348
GK		 3714 return;
3715 }
3716
a9098fd0 3717 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3718
f676971a 3719 if (TARGET_TOC
4d588c14 3720 && constant_pool_expr_p (XEXP (operands[1], 0))
d34c5b80
DE		 3721 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3722 get_pool_constant (XEXP (operands[1], 0)),
3723 get_pool_mode (XEXP (operands[1], 0))))
a9098fd0 3724 {
ba4828e0 3725 operands[1]
542a8afa 3726 = gen_const_mem (mode,
c4ad648e 3727 create_TOC_reference (XEXP (operands[1], 0)));
ba4828e0 3728 set_mem_alias_set (operands[1], get_TOC_alias_set ());
a9098fd0 3729 }
fb4d4348
GK		 3730 }
3731 break;
a9098fd0 3732
fb4d4348 3733 case TImode:
76d2b81d
DJ		 3734 rs6000_eliminate_indexed_memrefs (operands);
3735
27dc0551
DE		 3736 if (TARGET_POWER)
3737 {
3738 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3739 gen_rtvec (2,
3740 gen_rtx_SET (VOIDmode,
3741 operands[0], operands[1]),
3742 gen_rtx_CLOBBER (VOIDmode,
3743 gen_rtx_SCRATCH (SImode)))));
3744 return;
3745 }
fb4d4348
GK		 3746 break;
3747
3748 default:
37409796 3749 gcc_unreachable ();
fb4d4348
GK		 3750 }
3751
a9098fd0
GK		 3752 /* Above, we may have called force_const_mem which may have returned
3753 an invalid address. If we can, fix this up; otherwise, reload will
3754 have to deal with it. */
8f4e6caf
RH		 3755 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3756 operands[1] = validize_mem (operands[1]);
a9098fd0 3757
8f4e6caf 3758 emit_set:
fb4d4348
GK		 3759 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3760}
4697a36c 3761\f
2858f73a
GK		 3762/* Nonzero if we can use a floating-point register to pass this arg. */
3763#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3764 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3765 && (CUM)->fregno <= FP_ARG_MAX_REG \
3766 && TARGET_HARD_FLOAT && TARGET_FPRS)
3767
3768/* Nonzero if we can use an AltiVec register to pass this arg. */
3769#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3770 (ALTIVEC_VECTOR_MODE (MODE) \
3771 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3772 && TARGET_ALTIVEC_ABI \
83953138 3773 && (NAMED))
2858f73a 3774
c6e8c921
GK		 3775/* Return a nonzero value to say to return the function value in
3776 memory, just as large structures are always returned. TYPE will be
3777 the data type of the value, and FNTYPE will be the type of the
3778 function doing the returning, or @code{NULL} for libcalls.
3779
3780 The AIX ABI for the RS/6000 specifies that all structures are
3781 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3782 specifies that structures <= 8 bytes are returned in r3/r4, but a
3783 draft put them in memory, and GCC used to implement the draft
3784 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3785 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3786 compatibility can change DRAFT_V4_STRUCT_RET to override the
3787 default, and -m switches get the final word. See
3788 rs6000_override_options for more details.
3789
3790 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3791 long double support is enabled. These values are returned in memory.
3792
3793 int_size_in_bytes returns -1 for variable size objects, which go in
3794 memory always. The cast to unsigned makes -1 > 8. */
3795
3796static bool
3797rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3798{
594a51fe
SS		 3799 /* In the darwin64 abi, try to use registers for larger structs
3800 if possible. */
0b5383eb 3801 if (rs6000_darwin64_abi
594a51fe 3802 && TREE_CODE (type) == RECORD_TYPE
0b5383eb
DJ		 3803 && int_size_in_bytes (type) > 0)
3804 {
3805 CUMULATIVE_ARGS valcum;
3806 rtx valret;
3807
3808 valcum.words = 0;
3809 valcum.fregno = FP_ARG_MIN_REG;
3810 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3811 /* Do a trial code generation as if this were going to be passed
3812 as an argument; if any part goes in memory, we return NULL. */
3813 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3814 if (valret)
3815 return false;
3816 /* Otherwise fall through to more conventional ABI rules. */
3817 }
594a51fe 3818
c6e8c921
GK		 3819 if (AGGREGATE_TYPE_P (type)
3820 && (TARGET_AIX_STRUCT_RET
3821 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3822 return true;
b693336b 3823
bada2eb8
DE		 3824 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3825 modes only exist for GCC vector types if -maltivec. */
3826 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3827 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3828 return false;
3829
b693336b
PB		 3830 /* Return synthetic vectors in memory. */
3831 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 3832 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 3833 {
3834 static bool warned_for_return_big_vectors = false;
3835 if (!warned_for_return_big_vectors)
3836 {
d4ee4d25 3837 warning (0, "GCC vector returned by reference: "
b693336b
PB		 3838 "non-standard ABI extension with no compatibility guarantee");
3839 warned_for_return_big_vectors = true;
3840 }
3841 return true;
3842 }
3843
c6e8c921
GK		 3844 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3845 return true;
ad630bef 3846
c6e8c921
GK		 3847 return false;
3848}
3849
4697a36c
MM		 3850/* Initialize a variable CUM of type CUMULATIVE_ARGS
3851 for a call to a function whose data type is FNTYPE.
3852 For a library call, FNTYPE is 0.
3853
3854 For incoming args we set the number of arguments in the prototype large
1c20ae99 3855 so we never return a PARALLEL. */
4697a36c
MM		 3856
3857void
f676971a 3858init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
0f6937fe
AM		 3859 rtx libname ATTRIBUTE_UNUSED, int incoming,
3860 int libcall, int n_named_args)
4697a36c
MM		 3861{
3862 static CUMULATIVE_ARGS zero_cumulative;
3863
3864 *cum = zero_cumulative;
3865 cum->words = 0;
3866 cum->fregno = FP_ARG_MIN_REG;
0ac081f6 3867 cum->vregno = ALTIVEC_ARG_MIN_REG;
4697a36c 3868 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
ddcc8263
DE		 3869 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3870 ? CALL_LIBCALL : CALL_NORMAL);
4cc833b7 3871 cum->sysv_gregno = GP_ARG_MIN_REG;
a6c9bed4
AH		 3872 cum->stdarg = fntype
3873 && (TYPE_ARG_TYPES (fntype) != 0
3874 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3875 != void_type_node));
4697a36c 3876
0f6937fe
AM		 3877 cum->nargs_prototype = 0;
3878 if (incoming || cum->prototype)
3879 cum->nargs_prototype = n_named_args;
4697a36c 3880
a5c76ee6 3881 /* Check for a longcall attribute. */
3eb4e360
AM		 3882 if ((!fntype && rs6000_default_long_calls)
3883 || (fntype
3884 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3885 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
3886 cum->call_cookie |= CALL_LONG;
6a4cee5f 3887
4697a36c
MM		 3888 if (TARGET_DEBUG_ARG)
3889 {
3890 fprintf (stderr, "\ninit_cumulative_args:");
3891 if (fntype)
3892 {
3893 tree ret_type = TREE_TYPE (fntype);
3894 fprintf (stderr, " ret code = %s,",
3895 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3896 }
3897
6a4cee5f
MM		 3898 if (cum->call_cookie & CALL_LONG)
3899 fprintf (stderr, " longcall,");
3900
4697a36c
MM		 3901 fprintf (stderr, " proto = %d, nargs = %d\n",
3902 cum->prototype, cum->nargs_prototype);
3903 }
f676971a 3904
c4ad648e
AM		 3905 if (fntype
3906 && !TARGET_ALTIVEC
3907 && TARGET_ALTIVEC_ABI
3908 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3909 {
3910 error ("Cannot return value in vector register because"
3911 " altivec instructions are disabled, use -maltivec"
3912 " to enable them.");
3913 }
4697a36c
MM		 3914}
3915\f
fe984136
RH		 3916/* Return true if TYPE must be passed on the stack and not in registers. */
3917
3918static bool
3919rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
3920{
3921 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
3922 return must_pass_in_stack_var_size (mode, type);
3923 else
3924 return must_pass_in_stack_var_size_or_pad (mode, type);
3925}
3926
c229cba9
DE		 3927/* If defined, a C expression which determines whether, and in which
3928 direction, to pad out an argument with extra space. The value
3929 should be of type `enum direction': either `upward' to pad above
3930 the argument, `downward' to pad below, or `none' to inhibit
3931 padding.
3932
3933 For the AIX ABI structs are always stored left shifted in their
3934 argument slot. */
3935
9ebbca7d 3936enum direction
a2369ed3 3937function_arg_padding (enum machine_mode mode, tree type)
c229cba9 3938{
6e985040
AM		 3939#ifndef AGGREGATE_PADDING_FIXED
3940#define AGGREGATE_PADDING_FIXED 0
3941#endif
3942#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3943#define AGGREGATES_PAD_UPWARD_ALWAYS 0
3944#endif
3945
3946 if (!AGGREGATE_PADDING_FIXED)
3947 {
3948 /* GCC used to pass structures of the same size as integer types as
3949 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
19525b57 3950 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
6e985040
AM		 3951 passed padded downward, except that -mstrict-align further
3952 muddied the water in that multi-component structures of 2 and 4
3953 bytes in size were passed padded upward.
3954
3955 The following arranges for best compatibility with previous
3956 versions of gcc, but removes the -mstrict-align dependency. */
3957 if (BYTES_BIG_ENDIAN)
3958 {
3959 HOST_WIDE_INT size = 0;
3960
3961 if (mode == BLKmode)
3962 {
3963 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
3964 size = int_size_in_bytes (type);
3965 }
3966 else
3967 size = GET_MODE_SIZE (mode);
3968
3969 if (size == 1 || size == 2 || size == 4)
3970 return downward;
3971 }
3972 return upward;
3973 }
3974
3975 if (AGGREGATES_PAD_UPWARD_ALWAYS)
3976 {
3977 if (type != 0 && AGGREGATE_TYPE_P (type))
3978 return upward;
3979 }
c229cba9 3980
d3704c46
KH		 3981 /* Fall back to the default. */
3982 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
c229cba9
DE		 3983}
3984
b6c9286a 3985/* If defined, a C expression that gives the alignment boundary, in bits,
f676971a 3986 of an argument with the specified mode and type. If it is not defined,
b6c9286a 3987 PARM_BOUNDARY is used for all arguments.
f676971a 3988
b693336b
PB		 3989 V.4 wants long longs to be double word aligned.
3990 Doubleword align SPE vectors.
3991 Quadword align Altivec vectors.
3992 Quadword align large synthetic vector types. */
b6c9286a
MM		 3993
3994int
b693336b 3995function_arg_boundary (enum machine_mode mode, tree type)
b6c9286a 3996{
4ed78545
AM		 3997 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
3998 return 64;
ad630bef
DE		 3999 else if (SPE_VECTOR_MODE (mode)
4000 || (type && TREE_CODE (type) == VECTOR_TYPE
4001 && int_size_in_bytes (type) >= 8
4002 && int_size_in_bytes (type) < 16))
e1f83b4d 4003 return 64;
ad630bef
DE		 4004 else if (ALTIVEC_VECTOR_MODE (mode)
4005 || (type && TREE_CODE (type) == VECTOR_TYPE
4006 && int_size_in_bytes (type) >= 16))
0ac081f6 4007 return 128;
0b5383eb
DJ		 4008 else if (rs6000_darwin64_abi && mode == BLKmode
4009 && type && TYPE_ALIGN (type) > 64)
4010 return 128;
9ebbca7d 4011 else
b6c9286a 4012 return PARM_BOUNDARY;
b6c9286a 4013}
c53bdcf5 4014
294bd182
AM		 4015/* For a function parm of MODE and TYPE, return the starting word in
4016 the parameter area. NWORDS of the parameter area are already used. */
4017
4018static unsigned int
4019rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4020{
4021 unsigned int align;
4022 unsigned int parm_offset;
4023
4024 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4025 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4026 return nwords + (-(parm_offset + nwords) & align);
4027}
4028
c53bdcf5
AM		 4029/* Compute the size (in words) of a function argument. */
4030
4031static unsigned long
4032rs6000_arg_size (enum machine_mode mode, tree type)
4033{
4034 unsigned long size;
4035
4036 if (mode != BLKmode)
4037 size = GET_MODE_SIZE (mode);
4038 else
4039 size = int_size_in_bytes (type);
4040
4041 if (TARGET_32BIT)
4042 return (size + 3) >> 2;
4043 else
4044 return (size + 7) >> 3;
4045}
b6c9286a 4046\f
0b5383eb 4047/* Use this to flush pending int fields. */
594a51fe
SS		 4048
4049static void
0b5383eb
DJ		 4050rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4051 HOST_WIDE_INT bitpos)
594a51fe 4052{
0b5383eb
DJ		 4053 unsigned int startbit, endbit;
4054 int intregs, intoffset;
4055 enum machine_mode mode;
594a51fe 4056
0b5383eb
DJ		 4057 if (cum->intoffset == -1)
4058 return;
594a51fe 4059
0b5383eb
DJ		 4060 intoffset = cum->intoffset;
4061 cum->intoffset = -1;
4062
4063 if (intoffset % BITS_PER_WORD != 0)
4064 {
4065 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4066 MODE_INT, 0);
4067 if (mode == BLKmode)
594a51fe 4068 {
0b5383eb
DJ		 4069 /* We couldn't find an appropriate mode, which happens,
4070 e.g., in packed structs when there are 3 bytes to load.
4071 Back intoffset back to the beginning of the word in this
4072 case. */
4073 intoffset = intoffset & -BITS_PER_WORD;
594a51fe 4074 }
594a51fe 4075 }
0b5383eb
DJ		 4076
4077 startbit = intoffset & -BITS_PER_WORD;
4078 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4079 intregs = (endbit - startbit) / BITS_PER_WORD;
4080 cum->words += intregs;
4081}
4082
4083/* The darwin64 ABI calls for us to recurse down through structs,
4084 looking for elements passed in registers. Unfortunately, we have
4085 to track int register count here also because of misalignments
4086 in powerpc alignment mode. */
4087
4088static void
4089rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4090 tree type,
4091 HOST_WIDE_INT startbitpos)
4092{
4093 tree f;
4094
4095 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4096 if (TREE_CODE (f) == FIELD_DECL)
4097 {
4098 HOST_WIDE_INT bitpos = startbitpos;
4099 tree ftype = TREE_TYPE (f);
4100 enum machine_mode mode = TYPE_MODE (ftype);
4101
4102 if (DECL_SIZE (f) != 0
4103 && host_integerp (bit_position (f), 1))
4104 bitpos += int_bit_position (f);
4105
4106 /* ??? FIXME: else assume zero offset. */
4107
4108 if (TREE_CODE (ftype) == RECORD_TYPE)
4109 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4110 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4111 {
4112 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4113 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4114 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4115 }
4116 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4117 {
4118 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4119 cum->vregno++;
4120 cum->words += 2;
4121 }
4122 else if (cum->intoffset == -1)
4123 cum->intoffset = bitpos;
4124 }
594a51fe
SS		 4125}
4126
4697a36c
MM		 4127/* Update the data in CUM to advance over an argument
4128 of mode MODE and data type TYPE.
b2d04ecf
AM		 4129 (TYPE is null for libcalls where that information may not be available.)
4130
4131 Note that for args passed by reference, function_arg will be called
4132 with MODE and TYPE set to that of the pointer to the arg, not the arg
4133 itself. */
4697a36c
MM		 4134
4135void
f676971a 4136function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
594a51fe 4137 tree type, int named, int depth)
4697a36c 4138{
0b5383eb
DJ		 4139 int size;
4140
594a51fe
SS		 4141 /* Only tick off an argument if we're not recursing. */
4142 if (depth == 0)
4143 cum->nargs_prototype--;
4697a36c 4144
ad630bef
DE		 4145 if (TARGET_ALTIVEC_ABI
4146 && (ALTIVEC_VECTOR_MODE (mode)
4147 || (type && TREE_CODE (type) == VECTOR_TYPE
4148 && int_size_in_bytes (type) == 16)))
0ac081f6 4149 {
4ed78545
AM		 4150 bool stack = false;
4151
2858f73a 4152 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c4ad648e 4153 {
6d0ef01e
HP		 4154 cum->vregno++;
4155 if (!TARGET_ALTIVEC)
4156 error ("Cannot pass argument in vector register because"
4157 " altivec instructions are disabled, use -maltivec"
4158 " to enable them.");
4ed78545
AM		 4159
4160 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
f676971a 4161 even if it is going to be passed in a vector register.
4ed78545
AM		 4162 Darwin does the same for variable-argument functions. */
4163 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4164 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4165 stack = true;
6d0ef01e 4166 }
4ed78545
AM		 4167 else
4168 stack = true;
4169
4170 if (stack)
c4ad648e 4171 {
a594a19c 4172 int align;
f676971a 4173
2858f73a
GK		 4174 /* Vector parameters must be 16-byte aligned. This places
4175 them at 2 mod 4 in terms of words in 32-bit mode, since
4176 the parameter save area starts at offset 24 from the
4177 stack. In 64-bit mode, they just have to start on an
4178 even word, since the parameter save area is 16-byte
4179 aligned. Space for GPRs is reserved even if the argument
4180 will be passed in memory. */
4181 if (TARGET_32BIT)
4ed78545 4182 align = (2 - cum->words) & 3;
2858f73a
GK		 4183 else
4184 align = cum->words & 1;
c53bdcf5 4185 cum->words += align + rs6000_arg_size (mode, type);
f676971a 4186
a594a19c
GK		 4187 if (TARGET_DEBUG_ARG)
4188 {
f676971a 4189 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
a594a19c
GK		 4190 cum->words, align);
4191 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
f676971a 4192 cum->nargs_prototype, cum->prototype,
2858f73a 4193 GET_MODE_NAME (mode));
a594a19c
GK		 4194 }
4195 }
0ac081f6 4196 }
a4b0320c 4197 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
a6c9bed4
AH		 4198 && !cum->stdarg
4199 && cum->sysv_gregno <= GP_ARG_MAX_REG)
a4b0320c 4200 cum->sysv_gregno++;
594a51fe
SS		 4201
4202 else if (rs6000_darwin64_abi
4203 && mode == BLKmode
0b5383eb
DJ		 4204 && TREE_CODE (type) == RECORD_TYPE
4205 && (size = int_size_in_bytes (type)) > 0)
4206 {
4207 /* Variable sized types have size == -1 and are
4208 treated as if consisting entirely of ints.
4209 Pad to 16 byte boundary if needed. */
4210 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4211 && (cum->words % 2) != 0)
4212 cum->words++;
4213 /* For varargs, we can just go up by the size of the struct. */
4214 if (!named)
4215 cum->words += (size + 7) / 8;
4216 else
4217 {
4218 /* It is tempting to say int register count just goes up by
4219 sizeof(type)/8, but this is wrong in a case such as
4220 { int; double; int; } [powerpc alignment]. We have to
4221 grovel through the fields for these too. */
4222 cum->intoffset = 0;
4223 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4224 rs6000_darwin64_record_arg_advance_flush (cum,
4225 size * BITS_PER_UNIT);
4226 }
4227 }
f607bc57 4228 else if (DEFAULT_ABI == ABI_V4)
4697a36c 4229 {
a3170dc6 4230 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7 4231 && (mode == SFmode || mode == DFmode))
4697a36c 4232 {
4cc833b7
RH		 4233 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4234 cum->fregno++;
4235 else
4236 {
4237 if (mode == DFmode)
c4ad648e 4238 cum->words += cum->words & 1;
c53bdcf5 4239 cum->words += rs6000_arg_size (mode, type);
4cc833b7 4240 }
4697a36c 4241 }
4cc833b7
RH		 4242 else
4243 {
b2d04ecf 4244 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4245 int gregno = cum->sysv_gregno;
4246
4ed78545
AM		 4247 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4248 (r7,r8) or (r9,r10). As does any other 2 word item such
4249 as complex int due to a historical mistake. */
4250 if (n_words == 2)
4251 gregno += (1 - gregno) & 1;
4cc833b7 4252
4ed78545 4253 /* Multi-reg args are not split between registers and stack. */
4cc833b7
RH		 4254 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4255 {
4ed78545
AM		 4256 /* Long long and SPE vectors are aligned on the stack.
4257 So are other 2 word items such as complex int due to
4258 a historical mistake. */
4cc833b7
RH		 4259 if (n_words == 2)
4260 cum->words += cum->words & 1;
4261 cum->words += n_words;
4262 }
4697a36c 4263
4cc833b7
RH		 4264 /* Note: continuing to accumulate gregno past when we've started
4265 spilling to the stack indicates the fact that we've started
4266 spilling to the stack to expand_builtin_saveregs. */
4267 cum->sysv_gregno = gregno + n_words;
4268 }
4697a36c 4269
4cc833b7
RH		 4270 if (TARGET_DEBUG_ARG)
4271 {
4272 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4273 cum->words, cum->fregno);
4274 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4275 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4276 fprintf (stderr, "mode = %4s, named = %d\n",
4277 GET_MODE_NAME (mode), named);
4278 }
4697a36c
MM		 4279 }
4280 else
4cc833b7 4281 {
b2d04ecf 4282 int n_words = rs6000_arg_size (mode, type);
294bd182
AM		 4283 int start_words = cum->words;
4284 int align_words = rs6000_parm_start (mode, type, start_words);
a4f6c312 4285
294bd182 4286 cum->words = align_words + n_words;
4697a36c 4287
a3170dc6
AH		 4288 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4289 && TARGET_HARD_FLOAT && TARGET_FPRS)
c53bdcf5 4290 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4cc833b7
RH		 4291
4292 if (TARGET_DEBUG_ARG)
4293 {
4294 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4295 cum->words, cum->fregno);
4296 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4297 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
594a51fe 4298 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
294bd182 4299 named, align_words - start_words, depth);
4cc833b7
RH		 4300 }
4301 }
4697a36c 4302}
a6c9bed4 4303
f82f556d
AH		 4304static rtx
4305spe_build_register_parallel (enum machine_mode mode, int gregno)
4306{
54b695e7 4307 rtx r1, r3;
f82f556d 4308
37409796 4309 switch (mode)
f82f556d 4310 {
37409796 4311 case DFmode:
54b695e7
AH		 4312 r1 = gen_rtx_REG (DImode, gregno);
4313 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4314 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
37409796
NS		 4315
4316 case DCmode:
54b695e7
AH		 4317 r1 = gen_rtx_REG (DImode, gregno);
4318 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4319 r3 = gen_rtx_REG (DImode, gregno + 2);
4320 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4321 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
37409796
NS		 4322
4323 default:
4324 gcc_unreachable ();
f82f556d 4325 }
f82f556d 4326}
b78d48dd 4327
f82f556d 4328/* Determine where to put a SIMD argument on the SPE. */
a6c9bed4 4329static rtx
f676971a 4330rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4331 tree type)
a6c9bed4 4332{
f82f556d
AH		 4333 int gregno = cum->sysv_gregno;
4334
4335 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
600e1f95 4336 are passed and returned in a pair of GPRs for ABI compatibility. */
18f63bfa 4337 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
f82f556d 4338 {
b5870bee
AH		 4339 int n_words = rs6000_arg_size (mode, type);
4340
f82f556d 4341 /* Doubles go in an odd/even register pair (r5/r6, etc). */
b5870bee
AH		 4342 if (mode == DFmode)
4343 gregno += (1 - gregno) & 1;
f82f556d 4344
b5870bee
AH		 4345 /* Multi-reg args are not split between registers and stack. */
4346 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
f82f556d
AH		 4347 return NULL_RTX;
4348
4349 return spe_build_register_parallel (mode, gregno);
4350 }
a6c9bed4
AH		 4351 if (cum->stdarg)
4352 {
c53bdcf5 4353 int n_words = rs6000_arg_size (mode, type);
a6c9bed4
AH		 4354
4355 /* SPE vectors are put in odd registers. */
4356 if (n_words == 2 && (gregno & 1) == 0)
4357 gregno += 1;
4358
4359 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4360 {
4361 rtx r1, r2;
4362 enum machine_mode m = SImode;
4363
4364 r1 = gen_rtx_REG (m, gregno);
4365 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4366 r2 = gen_rtx_REG (m, gregno + 1);
4367 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4368 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4369 }
4370 else
b78d48dd 4371 return NULL_RTX;
a6c9bed4
AH		 4372 }
4373 else
4374 {
f82f556d
AH		 4375 if (gregno <= GP_ARG_MAX_REG)
4376 return gen_rtx_REG (mode, gregno);
a6c9bed4 4377 else
b78d48dd 4378 return NULL_RTX;
a6c9bed4
AH		 4379 }
4380}
4381
0b5383eb
DJ		 4382/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4383 structure between cum->intoffset and bitpos to integer registers. */
594a51fe 4384
0b5383eb
DJ		 4385static void
4386rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4387 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
594a51fe 4388{
0b5383eb
DJ		 4389 enum machine_mode mode;
4390 unsigned int regno;
4391 unsigned int startbit, endbit;
4392 int this_regno, intregs, intoffset;
4393 rtx reg;
594a51fe 4394
0b5383eb
DJ		 4395 if (cum->intoffset == -1)
4396 return;
4397
4398 intoffset = cum->intoffset;
4399 cum->intoffset = -1;
4400
4401 /* If this is the trailing part of a word, try to only load that
4402 much into the register. Otherwise load the whole register. Note
4403 that in the latter case we may pick up unwanted bits. It's not a
4404 problem at the moment but may wish to revisit. */
4405
4406 if (intoffset % BITS_PER_WORD != 0)
594a51fe 4407 {
0b5383eb
DJ		 4408 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4409 MODE_INT, 0);
4410 if (mode == BLKmode)
4411 {
4412 /* We couldn't find an appropriate mode, which happens,
4413 e.g., in packed structs when there are 3 bytes to load.
4414 Back intoffset back to the beginning of the word in this
4415 case. */
4416 intoffset = intoffset & -BITS_PER_WORD;
4417 mode = word_mode;
4418 }
4419 }
4420 else
4421 mode = word_mode;
4422
4423 startbit = intoffset & -BITS_PER_WORD;
4424 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4425 intregs = (endbit - startbit) / BITS_PER_WORD;
4426 this_regno = cum->words + intoffset / BITS_PER_WORD;
4427
4428 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4429 cum->use_stack = 1;
4430
4431 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4432 if (intregs <= 0)
4433 return;
4434
4435 intoffset /= BITS_PER_UNIT;
4436 do
4437 {
4438 regno = GP_ARG_MIN_REG + this_regno;
4439 reg = gen_rtx_REG (mode, regno);
4440 rvec[(*k)++] =
4441 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4442
4443 this_regno += 1;
4444 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4445 mode = word_mode;
4446 intregs -= 1;
4447 }
4448 while (intregs > 0);
4449}
4450
4451/* Recursive workhorse for the following. */
4452
4453static void
4454rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4455 HOST_WIDE_INT startbitpos, rtx rvec[],
4456 int *k)
4457{
4458 tree f;
4459
4460 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4461 if (TREE_CODE (f) == FIELD_DECL)
4462 {
4463 HOST_WIDE_INT bitpos = startbitpos;
4464 tree ftype = TREE_TYPE (f);
4465 enum machine_mode mode = TYPE_MODE (ftype);
4466
4467 if (DECL_SIZE (f) != 0
4468 && host_integerp (bit_position (f), 1))
4469 bitpos += int_bit_position (f);
4470
4471 /* ??? FIXME: else assume zero offset. */
4472
4473 if (TREE_CODE (ftype) == RECORD_TYPE)
4474 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4475 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
594a51fe 4476 {
0b5383eb
DJ		 4477#if 0
4478 switch (mode)
594a51fe 4479 {
0b5383eb
DJ		 4480 case SCmode: mode = SFmode; break;
4481 case DCmode: mode = DFmode; break;
4482 case TCmode: mode = TFmode; break;
4483 default: break;
594a51fe 4484 }
0b5383eb
DJ		 4485#endif
4486 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4487 rvec[(*k)++]
4488 = gen_rtx_EXPR_LIST (VOIDmode,
4489 gen_rtx_REG (mode, cum->fregno++),
4490 GEN_INT (bitpos / BITS_PER_UNIT));
4491 if (mode == TFmode)
4492 cum->fregno++;
594a51fe 4493 }
0b5383eb
DJ		 4494 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4495 {
4496 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4497 rvec[(*k)++]
4498 = gen_rtx_EXPR_LIST (VOIDmode,
4499 gen_rtx_REG (mode, cum->vregno++),
4500 GEN_INT (bitpos / BITS_PER_UNIT));
4501 }
4502 else if (cum->intoffset == -1)
4503 cum->intoffset = bitpos;
4504 }
4505}
594a51fe 4506
0b5383eb
DJ		 4507/* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4508 the register(s) to be used for each field and subfield of a struct
4509 being passed by value, along with the offset of where the
4510 register's value may be found in the block. FP fields go in FP
4511 register, vector fields go in vector registers, and everything
4512 else goes in int registers, packed as in memory.
8ff40a74 4513
0b5383eb
DJ		 4514 This code is also used for function return values. RETVAL indicates
4515 whether this is the case.
8ff40a74 4516
0b5383eb
DJ		 4517 Much of this is taken from the Sparc V9 port, which has a similar
4518 calling convention. */
594a51fe 4519
0b5383eb
DJ		 4520static rtx
4521rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4522 int named, bool retval)
4523{
4524 rtx rvec[FIRST_PSEUDO_REGISTER];
4525 int k = 1, kbase = 1;
4526 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4527 /* This is a copy; modifications are not visible to our caller. */
4528 CUMULATIVE_ARGS copy_cum = *orig_cum;
4529 CUMULATIVE_ARGS *cum = &copy_cum;
4530
4531 /* Pad to 16 byte boundary if needed. */
4532 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4533 && (cum->words % 2) != 0)
4534 cum->words++;
4535
4536 cum->intoffset = 0;
4537 cum->use_stack = 0;
4538 cum->named = named;
4539
4540 /* Put entries into rvec[] for individual FP and vector fields, and
4541 for the chunks of memory that go in int regs. Note we start at
4542 element 1; 0 is reserved for an indication of using memory, and
4543 may or may not be filled in below. */
4544 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4545 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4546
4547 /* If any part of the struct went on the stack put all of it there.
4548 This hack is because the generic code for
4549 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4550 parts of the struct are not at the beginning. */
4551 if (cum->use_stack)
4552 {
4553 if (retval)
4554 return NULL_RTX; /* doesn't go in registers at all */
4555 kbase = 0;
4556 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4557 }
4558 if (k > 1 || cum->use_stack)
4559 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
594a51fe
SS		 4560 else
4561 return NULL_RTX;
4562}
4563
b78d48dd
FJ		 4564/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4565
4566static rtx
ec6376ab 4567rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
b78d48dd 4568{
ec6376ab
AM		 4569 int n_units;
4570 int i, k;
4571 rtx rvec[GP_ARG_NUM_REG + 1];
4572
4573 if (align_words >= GP_ARG_NUM_REG)
4574 return NULL_RTX;
4575
4576 n_units = rs6000_arg_size (mode, type);
4577
4578 /* Optimize the simple case where the arg fits in one gpr, except in
4579 the case of BLKmode due to assign_parms assuming that registers are
4580 BITS_PER_WORD wide. */
4581 if (n_units == 0
4582 || (n_units == 1 && mode != BLKmode))
4583 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4584
4585 k = 0;
4586 if (align_words + n_units > GP_ARG_NUM_REG)
4587 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4588 using a magic NULL_RTX component.
4589 FIXME: This is not strictly correct. Only some of the arg
4590 belongs in memory, not all of it. However, there isn't any way
4591 to do this currently, apart from building rtx descriptions for
4592 the pieces of memory we want stored. Due to bugs in the generic
4593 code we can't use the normal function_arg_partial_nregs scheme
4594 with the PARALLEL arg description we emit here.
4595 In any case, the code to store the whole arg to memory is often
4596 more efficient than code to store pieces, and we know that space
4597 is available in the right place for the whole arg. */
78a52f11
RH		 4598 /* FIXME: This should be fixed since the conversion to
4599 TARGET_ARG_PARTIAL_BYTES. */
ec6376ab
AM		 4600 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4601
4602 i = 0;
4603 do
36a454e1 4604 {
ec6376ab
AM		 4605 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4606 rtx off = GEN_INT (i++ * 4);
4607 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36a454e1 4608 }
ec6376ab
AM		 4609 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4610
4611 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
b78d48dd
FJ		 4612}
4613
4697a36c
MM		 4614/* Determine where to put an argument to a function.
4615 Value is zero to push the argument on the stack,
4616 or a hard register in which to store the argument.
4617
4618 MODE is the argument's machine mode.
4619 TYPE is the data type of the argument (as a tree).
4620 This is null for libcalls where that information may
4621 not be available.
4622 CUM is a variable of type CUMULATIVE_ARGS which gives info about
0b5383eb
DJ		 4623 the preceding args and about the function being called. It is
4624 not modified in this routine.
4697a36c
MM		 4625 NAMED is nonzero if this argument is a named parameter
4626 (otherwise it is an extra parameter matching an ellipsis).
4627
4628 On RS/6000 the first eight words of non-FP are normally in registers
4629 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4630 Under V.4, the first 8 FP args are in registers.
4631
4632 If this is floating-point and no prototype is specified, we use
4633 both an FP and integer register (or possibly FP reg and stack). Library
b9599e46 4634 functions (when CALL_LIBCALL is set) always have the proper types for args,
4697a36c 4635 so we can pass the FP value just in one register. emit_library_function
b2d04ecf
AM		 4636 doesn't support PARALLEL anyway.
4637
4638 Note that for args passed by reference, function_arg will be called
4639 with MODE and TYPE set to that of the pointer to the arg, not the arg
4640 itself. */
4697a36c 4641
9390387d 4642rtx
f676971a 4643function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4644 tree type, int named)
4697a36c 4645{
4cc833b7 4646 enum rs6000_abi abi = DEFAULT_ABI;
4697a36c 4647
a4f6c312
SS		 4648 /* Return a marker to indicate whether CR1 needs to set or clear the
4649 bit that V.4 uses to say fp args were passed in registers.
4650 Assume that we don't need the marker for software floating point,
4651 or compiler generated library calls. */
4697a36c
MM		 4652 if (mode == VOIDmode)
4653 {
f607bc57 4654 if (abi == ABI_V4
7509c759 4655 && cum->nargs_prototype < 0
b9599e46
FS		 4656 && (cum->call_cookie & CALL_LIBCALL) == 0
4657 && (cum->prototype || TARGET_NO_PROTOTYPE))
7509c759 4658 {
a3170dc6
AH		 4659 /* For the SPE, we need to crxor CR6 always. */
4660 if (TARGET_SPE_ABI)
4661 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4662 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4663 return GEN_INT (cum->call_cookie
4664 | ((cum->fregno == FP_ARG_MIN_REG)
4665 ? CALL_V4_SET_FP_ARGS
4666 : CALL_V4_CLEAR_FP_ARGS));
7509c759 4667 }
4697a36c 4668
7509c759 4669 return GEN_INT (cum->call_cookie);
4697a36c
MM		 4670 }
4671
0b5383eb
DJ		 4672 if (rs6000_darwin64_abi && mode == BLKmode
4673 && TREE_CODE (type) == RECORD_TYPE)
8ff40a74 4674 {
0b5383eb 4675 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
8ff40a74
SS		 4676 if (rslt != NULL_RTX)
4677 return rslt;
4678 /* Else fall through to usual handling. */
4679 }
4680
2858f73a 4681 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c72d6c26
HP		 4682 if (TARGET_64BIT && ! cum->prototype)
4683 {
c4ad648e
AM		 4684 /* Vector parameters get passed in vector register
4685 and also in GPRs or memory, in absence of prototype. */
4686 int align_words;
4687 rtx slot;
4688 align_words = (cum->words + 1) & ~1;
4689
4690 if (align_words >= GP_ARG_NUM_REG)
4691 {
4692 slot = NULL_RTX;
4693 }
4694 else
4695 {
4696 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4697 }
4698 return gen_rtx_PARALLEL (mode,
4699 gen_rtvec (2,
4700 gen_rtx_EXPR_LIST (VOIDmode,
4701 slot, const0_rtx),
4702 gen_rtx_EXPR_LIST (VOIDmode,
4703 gen_rtx_REG (mode, cum->vregno),
4704 const0_rtx)));
c72d6c26
HP		 4705 }
4706 else
4707 return gen_rtx_REG (mode, cum->vregno);
ad630bef
DE		 4708 else if (TARGET_ALTIVEC_ABI
4709 && (ALTIVEC_VECTOR_MODE (mode)
4710 || (type && TREE_CODE (type) == VECTOR_TYPE
4711 && int_size_in_bytes (type) == 16)))
0ac081f6 4712 {
2858f73a 4713 if (named || abi == ABI_V4)
a594a19c 4714 return NULL_RTX;
0ac081f6 4715 else
a594a19c
GK		 4716 {
4717 /* Vector parameters to varargs functions under AIX or Darwin
4718 get passed in memory and possibly also in GPRs. */
ec6376ab
AM		 4719 int align, align_words, n_words;
4720 enum machine_mode part_mode;
a594a19c
GK		 4721
4722 /* Vector parameters must be 16-byte aligned. This places them at
2858f73a
GK		 4723 2 mod 4 in terms of words in 32-bit mode, since the parameter
4724 save area starts at offset 24 from the stack. In 64-bit mode,
4725 they just have to start on an even word, since the parameter
4726 save area is 16-byte aligned. */
4727 if (TARGET_32BIT)
4ed78545 4728 align = (2 - cum->words) & 3;
2858f73a
GK		 4729 else
4730 align = cum->words & 1;
a594a19c
GK		 4731 align_words = cum->words + align;
4732
4733 /* Out of registers? Memory, then. */
4734 if (align_words >= GP_ARG_NUM_REG)
4735 return NULL_RTX;
ec6376ab
AM		 4736
4737 if (TARGET_32BIT && TARGET_POWERPC64)
4738 return rs6000_mixed_function_arg (mode, type, align_words);
4739
2858f73a
GK		 4740 /* The vector value goes in GPRs. Only the part of the
4741 value in GPRs is reported here. */
ec6376ab
AM		 4742 part_mode = mode;
4743 n_words = rs6000_arg_size (mode, type);
4744 if (align_words + n_words > GP_ARG_NUM_REG)
839a4992 4745 /* Fortunately, there are only two possibilities, the value
2858f73a
GK		 4746 is either wholly in GPRs or half in GPRs and half not. */
4747 part_mode = DImode;
ec6376ab
AM		 4748
4749 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
a594a19c 4750 }
0ac081f6 4751 }
f82f556d
AH		 4752 else if (TARGET_SPE_ABI && TARGET_SPE
4753 && (SPE_VECTOR_MODE (mode)
18f63bfa
AH		 4754 || (TARGET_E500_DOUBLE && (mode == DFmode
4755 || mode == DCmode))))
a6c9bed4 4756 return rs6000_spe_function_arg (cum, mode, type);
594a51fe 4757
f607bc57 4758 else if (abi == ABI_V4)
4697a36c 4759 {
a3170dc6 4760 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7
RH		 4761 && (mode == SFmode || mode == DFmode))
4762 {
4763 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4764 return gen_rtx_REG (mode, cum->fregno);
4765 else
b78d48dd 4766 return NULL_RTX;
4cc833b7
RH		 4767 }
4768 else
4769 {
b2d04ecf 4770 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4771 int gregno = cum->sysv_gregno;
4772
4ed78545
AM		 4773 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4774 (r7,r8) or (r9,r10). As does any other 2 word item such
4775 as complex int due to a historical mistake. */
4776 if (n_words == 2)
4777 gregno += (1 - gregno) & 1;
4cc833b7 4778
4ed78545 4779 /* Multi-reg args are not split between registers and stack. */
ec6376ab 4780 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
b78d48dd 4781 return NULL_RTX;
ec6376ab
AM		 4782
4783 if (TARGET_32BIT && TARGET_POWERPC64)
4784 return rs6000_mixed_function_arg (mode, type,
4785 gregno - GP_ARG_MIN_REG);
4786 return gen_rtx_REG (mode, gregno);
4cc833b7 4787 }
4697a36c 4788 }
4cc833b7
RH		 4789 else
4790 {
294bd182 4791 int align_words = rs6000_parm_start (mode, type, cum->words);
b78d48dd 4792
2858f73a 4793 if (USE_FP_FOR_ARG_P (cum, mode, type))
4cc833b7 4794 {
ec6376ab
AM		 4795 rtx rvec[GP_ARG_NUM_REG + 1];
4796 rtx r;
4797 int k;
c53bdcf5
AM		 4798 bool needs_psave;
4799 enum machine_mode fmode = mode;
c53bdcf5
AM		 4800 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4801
4802 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4803 {
c53bdcf5
AM		 4804 /* Currently, we only ever need one reg here because complex
4805 doubles are split. */
37409796 4806 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
ec6376ab
AM		 4807
4808 /* Long double split over regs and memory. */
4809 fmode = DFmode;
c53bdcf5 4810 }
c53bdcf5
AM		 4811
4812 /* Do we also need to pass this arg in the parameter save
4813 area? */
4814 needs_psave = (type
4815 && (cum->nargs_prototype <= 0
4816 || (DEFAULT_ABI == ABI_AIX
de17c25f 4817 && TARGET_XL_COMPAT
c53bdcf5
AM		 4818 && align_words >= GP_ARG_NUM_REG)));
4819
4820 if (!needs_psave && mode == fmode)
ec6376ab 4821 return gen_rtx_REG (fmode, cum->fregno);
c53bdcf5 4822
ec6376ab 4823 k = 0;
c53bdcf5
AM		 4824 if (needs_psave)
4825 {
ec6376ab 4826 /* Describe the part that goes in gprs or the stack.
c53bdcf5 4827 This piece must come first, before the fprs. */
c53bdcf5
AM		 4828 if (align_words < GP_ARG_NUM_REG)
4829 {
4830 unsigned long n_words = rs6000_arg_size (mode, type);
ec6376ab
AM		 4831
4832 if (align_words + n_words > GP_ARG_NUM_REG
4833 || (TARGET_32BIT && TARGET_POWERPC64))
4834 {
4835 /* If this is partially on the stack, then we only
4836 include the portion actually in registers here. */
4837 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4838 rtx off;
2e6c9641 4839 int i=0;
c4ad648e
AM		 4840 if (align_words + n_words > GP_ARG_NUM_REG
4841 && (TARGET_32BIT && TARGET_POWERPC64))
4842 /* Not all of the arg fits in gprs. Say that it
4843 goes in memory too, using a magic NULL_RTX
4844 component. Also see comment in
4845 rs6000_mixed_function_arg for why the normal
4846 function_arg_partial_nregs scheme doesn't work
4847 in this case. */
4848 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4849 const0_rtx);
ec6376ab
AM		 4850 do
4851 {
4852 r = gen_rtx_REG (rmode,
4853 GP_ARG_MIN_REG + align_words);
2e6c9641 4854 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
ec6376ab
AM		 4855 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4856 }
4857 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
4858 }
4859 else
4860 {
4861 /* The whole arg fits in gprs. */
4862 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4863 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4864 }
c53bdcf5 4865 }
ec6376ab
AM		 4866 else
4867 /* It's entirely in memory. */
4868 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
c53bdcf5
AM		 4869 }
4870
ec6376ab
AM		 4871 /* Describe where this piece goes in the fprs. */
4872 r = gen_rtx_REG (fmode, cum->fregno);
4873 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4874
4875 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4cc833b7
RH		 4876 }
4877 else if (align_words < GP_ARG_NUM_REG)
b2d04ecf 4878 {
ec6376ab
AM		 4879 if (TARGET_32BIT && TARGET_POWERPC64)
4880 return rs6000_mixed_function_arg (mode, type, align_words);
b2d04ecf 4881
4eeca74f
AM		 4882 if (mode == BLKmode)
4883 mode = Pmode;
4884
b2d04ecf
AM		 4885 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4886 }
4cc833b7
RH		 4887 else
4888 return NULL_RTX;
4697a36c 4889 }
4697a36c
MM		 4890}
4891\f
ec6376ab 4892/* For an arg passed partly in registers and partly in memory, this is
fb63c729
AM		 4893 the number of bytes passed in registers. For args passed entirely in
4894 registers or entirely in memory, zero. When an arg is described by a
4895 PARALLEL, perhaps using more than one register type, this function
4896 returns the number of bytes used by the first element of the PARALLEL. */
4697a36c 4897
78a52f11
RH		 4898static int
4899rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4900 tree type, bool named)
4697a36c 4901{
c53bdcf5 4902 int ret = 0;
ec6376ab 4903 int align_words;
c53bdcf5 4904
f607bc57 4905 if (DEFAULT_ABI == ABI_V4)
4697a36c 4906 return 0;
4697a36c 4907
c53bdcf5
AM		 4908 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4909 && cum->nargs_prototype >= 0)
4910 return 0;
4911
0b5383eb
DJ		 4912 /* In this complicated case we just disable the partial_nregs code. */
4913 if (rs6000_darwin64_abi && mode == BLKmode
4914 && TREE_CODE (type) == RECORD_TYPE
4915 && int_size_in_bytes (type) > 0)
4916 return 0;
4917
294bd182 4918 align_words = rs6000_parm_start (mode, type, cum->words);
ec6376ab
AM		 4919
4920 if (USE_FP_FOR_ARG_P (cum, mode, type)
fb63c729
AM		 4921 /* If we are passing this arg in the fixed parameter save area
4922 (gprs or memory) as well as fprs, then this function should
4923 return the number of bytes passed in the parameter save area
4924 rather than bytes passed in fprs. */
ec6376ab
AM		 4925 && !(type
4926 && (cum->nargs_prototype <= 0
4927 || (DEFAULT_ABI == ABI_AIX
de17c25f 4928 && TARGET_XL_COMPAT
ec6376ab 4929 && align_words >= GP_ARG_NUM_REG))))
4697a36c 4930 {
c53bdcf5 4931 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
ac7e839c 4932 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
c53bdcf5 4933 else if (cum->nargs_prototype >= 0)
4697a36c
MM		 4934 return 0;
4935 }
4936
ec6376ab
AM		 4937 if (align_words < GP_ARG_NUM_REG
4938 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
ac7e839c 4939 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
78a52f11 4940
c53bdcf5 4941 if (ret != 0 && TARGET_DEBUG_ARG)
78a52f11 4942 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
4697a36c 4943
c53bdcf5 4944 return ret;
4697a36c
MM		 4945}
4946\f
4947/* A C expression that indicates when an argument must be passed by
4948 reference. If nonzero for an argument, a copy of that argument is
4949 made in memory and a pointer to the argument is passed instead of
4950 the argument itself. The pointer is passed in whatever way is
4951 appropriate for passing a pointer to that type.
4952
b2d04ecf
AM		 4953 Under V.4, aggregates and long double are passed by reference.
4954
4955 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
4956 reference unless the AltiVec vector extension ABI is in force.
c8c99a68
DE		 4957
4958 As an extension to all ABIs, variable sized types are passed by
4959 reference. */
4697a36c 4960
8cd5a4e0 4961static bool
f676971a 4962rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
bada2eb8
DE		 4963 enum machine_mode mode, tree type,
4964 bool named ATTRIBUTE_UNUSED)
4697a36c 4965{
bada2eb8 4966 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
4697a36c
MM		 4967 {
4968 if (TARGET_DEBUG_ARG)
bada2eb8
DE		 4969 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
4970 return 1;
4971 }
4972
4973 if (!type)
4974 return 0;
4697a36c 4975
bada2eb8
DE		 4976 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
4977 {
4978 if (TARGET_DEBUG_ARG)
4979 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
4980 return 1;
4981 }
4982
4983 if (int_size_in_bytes (type) < 0)
4984 {
4985 if (TARGET_DEBUG_ARG)
4986 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
4987 return 1;
4988 }
4989
4990 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4991 modes only exist for GCC vector types if -maltivec. */
4992 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4993 {
4994 if (TARGET_DEBUG_ARG)
4995 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
4697a36c
MM		 4996 return 1;
4997 }
b693336b
PB		 4998
4999 /* Pass synthetic vectors in memory. */
bada2eb8 5000 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 5001 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 5002 {
5003 static bool warned_for_pass_big_vectors = false;
5004 if (TARGET_DEBUG_ARG)
5005 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5006 if (!warned_for_pass_big_vectors)
5007 {
d4ee4d25 5008 warning (0, "GCC vector passed by reference: "
b693336b
PB		 5009 "non-standard ABI extension with no compatibility guarantee");
5010 warned_for_pass_big_vectors = true;
5011 }
5012 return 1;
5013 }
5014
b2d04ecf 5015 return 0;
4697a36c 5016}
5985c7a6
FJ		 5017
5018static void
2d9db8eb 5019rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5985c7a6
FJ		 5020{
5021 int i;
5022 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5023
5024 if (nregs == 0)
5025 return;
5026
c4ad648e 5027 for (i = 0; i < nregs; i++)
5985c7a6 5028 {
9390387d 5029 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5985c7a6 5030 if (reload_completed)
c4ad648e
AM		 5031 {
5032 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5033 tem = NULL_RTX;
5034 else
5035 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
9390387d 5036 i * GET_MODE_SIZE (reg_mode));
c4ad648e 5037 }
5985c7a6
FJ		 5038 else
5039 tem = replace_equiv_address (tem, XEXP (tem, 0));
5040
37409796 5041 gcc_assert (tem);
5985c7a6
FJ		 5042
5043 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5044 }
5045}
4697a36c
MM		 5046\f
5047/* Perform any needed actions needed for a function that is receiving a
f676971a 5048 variable number of arguments.
4697a36c
MM		 5049
5050 CUM is as above.
5051
5052 MODE and TYPE are the mode and type of the current parameter.
5053
5054 PRETEND_SIZE is a variable that should be set to the amount of stack
5055 that must be pushed by the prolog to pretend that our caller pushed
5056 it.
5057
5058 Normally, this macro will push all remaining incoming registers on the
5059 stack and set PRETEND_SIZE to the length of the registers pushed. */
5060
c6e8c921 5061static void
f676971a 5062setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
c4ad648e
AM		 5063 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5064 int no_rtl)
4697a36c 5065{
4cc833b7
RH		 5066 CUMULATIVE_ARGS next_cum;
5067 int reg_size = TARGET_32BIT ? 4 : 8;
ca5adc63 5068 rtx save_area = NULL_RTX, mem;
dfafc897 5069 int first_reg_offset, set;
4697a36c 5070
f31bf321 5071 /* Skip the last named argument. */
d34c5b80 5072 next_cum = *cum;
594a51fe 5073 function_arg_advance (&next_cum, mode, type, 1, 0);
4cc833b7 5074
f607bc57 5075 if (DEFAULT_ABI == ABI_V4)
d34c5b80 5076 {
60e2d0ca 5077 if (! no_rtl)
2c4974b7 5078 save_area = plus_constant (virtual_stack_vars_rtx,
bd227acc 5079 - RS6000_VARARGS_SIZE);
4cc833b7
RH		 5080
5081 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4697a36c 5082 }
60e2d0ca 5083 else
4697a36c 5084 {
d34c5b80 5085 first_reg_offset = next_cum.words;
4cc833b7 5086 save_area = virtual_incoming_args_rtx;
4697a36c 5087
fe984136 5088 if (targetm.calls.must_pass_in_stack (mode, type))
c53bdcf5 5089 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
4cc833b7 5090 }
4697a36c 5091
dfafc897 5092 set = get_varargs_alias_set ();
9d30f3c1
JJ		 5093 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5094 && cfun->va_list_gpr_size)
4cc833b7 5095 {
9d30f3c1
JJ		 5096 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5097
5098 if (va_list_gpr_counter_field)
5099 {
5100 /* V4 va_list_gpr_size counts number of registers needed. */
5101 if (nregs > cfun->va_list_gpr_size)
5102 nregs = cfun->va_list_gpr_size;
5103 }
5104 else
5105 {
5106 /* char * va_list instead counts number of bytes needed. */
5107 if (nregs > cfun->va_list_gpr_size / reg_size)
5108 nregs = cfun->va_list_gpr_size / reg_size;
5109 }
5110
dfafc897 5111 mem = gen_rtx_MEM (BLKmode,
c4ad648e 5112 plus_constant (save_area,
dfafc897 5113 first_reg_offset * reg_size)),
ba4828e0 5114 set_mem_alias_set (mem, set);
8ac61af7 5115 set_mem_align (mem, BITS_PER_WORD);
dfafc897 5116
f676971a 5117 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
9d30f3c1 5118 nregs);
4697a36c
MM		 5119 }
5120
4697a36c 5121 /* Save FP registers if needed. */
f607bc57 5122 if (DEFAULT_ABI == ABI_V4
a3170dc6
AH		 5123 && TARGET_HARD_FLOAT && TARGET_FPRS
5124 && ! no_rtl
9d30f3c1
JJ		 5125 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5126 && cfun->va_list_fpr_size)
4697a36c 5127 {
9d30f3c1 5128 int fregno = next_cum.fregno, nregs;
9ebbca7d 5129 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4cc833b7
RH		 5130 rtx lab = gen_label_rtx ();
5131 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4697a36c 5132
c4ad648e
AM		 5133 emit_jump_insn
5134 (gen_rtx_SET (VOIDmode,
5135 pc_rtx,
5136 gen_rtx_IF_THEN_ELSE (VOIDmode,
4cc833b7 5137 gen_rtx_NE (VOIDmode, cr1,
c4ad648e 5138 const0_rtx),
39403d82 5139 gen_rtx_LABEL_REF (VOIDmode, lab),
4697a36c
MM		 5140 pc_rtx)));
5141
9d30f3c1
JJ		 5142 for (nregs = 0;
5143 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5144 fregno++, off += 8, nregs++)
4cc833b7 5145 {
5496b36f 5146 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
c4ad648e 5147 set_mem_alias_set (mem, set);
94ff898d 5148 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
dfafc897 5149 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4697a36c 5150 }
4cc833b7
RH		 5151
5152 emit_label (lab);
4697a36c 5153 }
4697a36c 5154}
4697a36c 5155
dfafc897 5156/* Create the va_list data type. */
2c4974b7 5157
c35d187f
RH		 5158static tree
5159rs6000_build_builtin_va_list (void)
dfafc897 5160{
64c2816f 5161 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4697a36c 5162
9ebbca7d
GK		 5163 /* For AIX, prefer 'char *' because that's what the system
5164 header files like. */
f607bc57 5165 if (DEFAULT_ABI != ABI_V4)
9ebbca7d 5166 return build_pointer_type (char_type_node);
dfafc897 5167
f1e639b1 5168 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
bab45a51 5169 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
0f4fd75d 5170
f676971a 5171 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
9ebbca7d 5172 unsigned_char_type_node);
f676971a 5173 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
9ebbca7d 5174 unsigned_char_type_node);
64c2816f
DT		 5175 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5176 every user file. */
5177 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5178 short_unsigned_type_node);
dfafc897
FS		 5179 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5180 ptr_type_node);
5181 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5182 ptr_type_node);
5183
9d30f3c1
JJ		 5184 va_list_gpr_counter_field = f_gpr;
5185 va_list_fpr_counter_field = f_fpr;
5186
dfafc897
FS		 5187 DECL_FIELD_CONTEXT (f_gpr) = record;
5188 DECL_FIELD_CONTEXT (f_fpr) = record;
64c2816f 5189 DECL_FIELD_CONTEXT (f_res) = record;
dfafc897
FS		 5190 DECL_FIELD_CONTEXT (f_ovf) = record;
5191 DECL_FIELD_CONTEXT (f_sav) = record;
5192
bab45a51
FS		 5193 TREE_CHAIN (record) = type_decl;
5194 TYPE_NAME (record) = type_decl;
dfafc897
FS		 5195 TYPE_FIELDS (record) = f_gpr;
5196 TREE_CHAIN (f_gpr) = f_fpr;
64c2816f
DT		 5197 TREE_CHAIN (f_fpr) = f_res;
5198 TREE_CHAIN (f_res) = f_ovf;
dfafc897
FS		 5199 TREE_CHAIN (f_ovf) = f_sav;
5200
5201 layout_type (record);
5202
5203 /* The correct type is an array type of one element. */
5204 return build_array_type (record, build_index_type (size_zero_node));
5205}
5206
5207/* Implement va_start. */
5208
5209void
a2369ed3 5210rs6000_va_start (tree valist, rtx nextarg)
4697a36c 5211{
dfafc897 5212 HOST_WIDE_INT words, n_gpr, n_fpr;
c566f9bd 5213 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
dfafc897 5214 tree gpr, fpr, ovf, sav, t;
2c4974b7 5215
dfafc897 5216 /* Only SVR4 needs something special. */
f607bc57 5217 if (DEFAULT_ABI != ABI_V4)
dfafc897 5218 {
e5faf155 5219 std_expand_builtin_va_start (valist, nextarg);
dfafc897
FS		 5220 return;
5221 }
5222
973a648b 5223 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
dfafc897 5224 f_fpr = TREE_CHAIN (f_gpr);
c566f9bd
DT		 5225 f_res = TREE_CHAIN (f_fpr);
5226 f_ovf = TREE_CHAIN (f_res);
dfafc897
FS		 5227 f_sav = TREE_CHAIN (f_ovf);
5228
872a65b5 5229 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5230 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5231 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5232 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5233 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
dfafc897
FS		 5234
5235 /* Count number of gp and fp argument registers used. */
4cc833b7 5236 words = current_function_args_info.words;
987732e0
DE		 5237 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5238 GP_ARG_NUM_REG);
5239 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5240 FP_ARG_NUM_REG);
dfafc897
FS		 5241
5242 if (TARGET_DEBUG_ARG)
4a0a75dd
KG		 5243 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5244 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5245 words, n_gpr, n_fpr);
dfafc897 5246
9d30f3c1
JJ		 5247 if (cfun->va_list_gpr_size)
5248 {
5249 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5250 build_int_cst (NULL_TREE, n_gpr));
5251 TREE_SIDE_EFFECTS (t) = 1;
5252 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5253 }
58c8adc1 5254
9d30f3c1
JJ		 5255 if (cfun->va_list_fpr_size)
5256 {
5257 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5258 build_int_cst (NULL_TREE, n_fpr));
5259 TREE_SIDE_EFFECTS (t) = 1;
5260 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5261 }
dfafc897
FS		 5262
5263 /* Find the overflow area. */
5264 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5265 if (words != 0)
5266 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
7d60be94 5267 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
dfafc897
FS		 5268 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5269 TREE_SIDE_EFFECTS (t) = 1;
5270 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5271
9d30f3c1
JJ		 5272 /* If there were no va_arg invocations, don't set up the register
5273 save area. */
5274 if (!cfun->va_list_gpr_size
5275 && !cfun->va_list_fpr_size
5276 && n_gpr < GP_ARG_NUM_REG
5277 && n_fpr < FP_ARG_V4_MAX_REG)
5278 return;
5279
dfafc897
FS		 5280 /* Find the register save area. */
5281 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5282 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
7d60be94 5283 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
dfafc897
FS		 5284 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5285 TREE_SIDE_EFFECTS (t) = 1;
5286 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5287}
5288
5289/* Implement va_arg. */
5290
23a60a04
JM		 5291tree
5292rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
cd3ce9b4 5293{
cd3ce9b4
JM		 5294 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5295 tree gpr, fpr, ovf, sav, reg, t, u;
08b0dc1b 5296 int size, rsize, n_reg, sav_ofs, sav_scale;
cd3ce9b4
JM		 5297 tree lab_false, lab_over, addr;
5298 int align;
5299 tree ptrtype = build_pointer_type (type);
5300
08b0dc1b
RH		 5301 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5302 {
5303 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
872a65b5 5304 return build_va_arg_indirect_ref (t);
08b0dc1b
RH		 5305 }
5306
cd3ce9b4
JM		 5307 if (DEFAULT_ABI != ABI_V4)
5308 {
08b0dc1b 5309 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
cd3ce9b4
JM		 5310 {
5311 tree elem_type = TREE_TYPE (type);
5312 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5313 int elem_size = GET_MODE_SIZE (elem_mode);
5314
5315 if (elem_size < UNITS_PER_WORD)
5316 {
23a60a04 5317 tree real_part, imag_part;
cd3ce9b4
JM		 5318 tree post = NULL_TREE;
5319
23a60a04
JM		 5320 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5321 &post);
5322 /* Copy the value into a temporary, lest the formal temporary
5323 be reused out from under us. */
5324 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
cd3ce9b4
JM		 5325 append_to_statement_list (post, pre_p);
5326
23a60a04
JM		 5327 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5328 post_p);
cd3ce9b4 5329
23a60a04 5330 return build (COMPLEX_EXPR, type, real_part, imag_part);
cd3ce9b4
JM		 5331 }
5332 }
5333
23a60a04 5334 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
cd3ce9b4
JM		 5335 }
5336
5337 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5338 f_fpr = TREE_CHAIN (f_gpr);
5339 f_res = TREE_CHAIN (f_fpr);
5340 f_ovf = TREE_CHAIN (f_res);
5341 f_sav = TREE_CHAIN (f_ovf);
5342
872a65b5 5343 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5344 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5345 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5346 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5347 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
cd3ce9b4
JM		 5348
5349 size = int_size_in_bytes (type);
5350 rsize = (size + 3) / 4;
5351 align = 1;
5352
08b0dc1b
RH		 5353 if (TARGET_HARD_FLOAT && TARGET_FPRS
5354 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
cd3ce9b4
JM		 5355 {
5356 /* FP args go in FP registers, if present. */
cd3ce9b4
JM		 5357 reg = fpr;
5358 n_reg = 1;
5359 sav_ofs = 8*4;
5360 sav_scale = 8;
5361 if (TYPE_MODE (type) == DFmode)
5362 align = 8;
5363 }
5364 else
5365 {
5366 /* Otherwise into GP registers. */
cd3ce9b4
JM		 5367 reg = gpr;
5368 n_reg = rsize;
5369 sav_ofs = 0;
5370 sav_scale = 4;
5371 if (n_reg == 2)
5372 align = 8;
5373 }
5374
5375 /* Pull the value out of the saved registers.... */
5376
5377 lab_over = NULL;
5378 addr = create_tmp_var (ptr_type_node, "addr");
5379 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5380
5381 /* AltiVec vectors never go in registers when -mabi=altivec. */
5382 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5383 align = 16;
5384 else
5385 {
5386 lab_false = create_artificial_label ();
5387 lab_over = create_artificial_label ();
5388
5389 /* Long long and SPE vectors are aligned in the registers.
5390 As are any other 2 gpr item such as complex int due to a
5391 historical mistake. */
5392 u = reg;
5393 if (n_reg == 2)
5394 {
5395 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
95674810 5396 size_int (n_reg - 1));
cd3ce9b4
JM		 5397 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5398 }
5399
95674810 5400 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
cd3ce9b4
JM		 5401 t = build2 (GE_EXPR, boolean_type_node, u, t);
5402 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5403 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5404 gimplify_and_add (t, pre_p);
5405
5406 t = sav;
5407 if (sav_ofs)
95674810 5408 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
cd3ce9b4 5409
95674810 5410 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
cd3ce9b4 5411 u = build1 (CONVERT_EXPR, integer_type_node, u);
95674810 5412 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
cd3ce9b4
JM		 5413 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5414
5415 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5416 gimplify_and_add (t, pre_p);
5417
5418 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5419 gimplify_and_add (t, pre_p);
5420
5421 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5422 append_to_statement_list (t, pre_p);
5423
5424 if (n_reg > 2)
5425 {
5426 /* Ensure that we don't find any more args in regs.
5427 Alignment has taken care of the n_reg == 2 case. */
95674810 5428 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
cd3ce9b4
JM		 5429 gimplify_and_add (t, pre_p);
5430 }
5431 }
5432
5433 /* ... otherwise out of the overflow area. */
5434
5435 /* Care for on-stack alignment if needed. */
5436 t = ovf;
5437 if (align != 1)
5438 {
95674810 5439 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
4a90aeeb 5440 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7d60be94 5441 build_int_cst (NULL_TREE, -align));
cd3ce9b4
JM		 5442 }
5443 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5444
5445 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5446 gimplify_and_add (u, pre_p);
5447
95674810 5448 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
cd3ce9b4
JM		 5449 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5450 gimplify_and_add (t, pre_p);
5451
5452 if (lab_over)
5453 {
5454 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5455 append_to_statement_list (t, pre_p);
5456 }
5457
08b0dc1b 5458 addr = fold_convert (ptrtype, addr);
872a65b5 5459 return build_va_arg_indirect_ref (addr);
cd3ce9b4
JM		 5460}
5461
0ac081f6
AH		 5462/* Builtins. */
5463
58646b77
PB		 5464static void
5465def_builtin (int mask, const char *name, tree type, int code)
5466{
5467 if (mask & target_flags)
5468 {
5469 if (rs6000_builtin_decls[code])
5470 abort ();
5471
5472 rs6000_builtin_decls[code] =
5473 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5474 NULL, NULL_TREE);
5475 }
5476}
0ac081f6 5477
24408032
AH		 5478/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5479
2212663f 5480static const struct builtin_description bdesc_3arg[] =
24408032
AH		 5481{
5482 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5483 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5484 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5485 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5486 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5487 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5488 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5489 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5490 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5491 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
f676971a 5492 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
aba5fb01
NS		 5493 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5494 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5495 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5496 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5497 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5498 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5499 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5500 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5501 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5502 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5503 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5504 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
58646b77
PB		 5505
5506 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5507 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5508 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5509 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
5510 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
5511 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
5512 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
5513 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
5514 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
5515 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
5516 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
5517 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
5518 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
5519 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
5520 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
24408032 5521};
2212663f 5522
95385cbb
AH		 5523/* DST operations: void foo (void *, const int, const char). */
5524
5525static const struct builtin_description bdesc_dst[] =
5526{
5527 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5528 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5529 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
58646b77
PB		 5530 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
5531
5532 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
5533 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
5534 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
5535 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
95385cbb
AH		 5536};
5537
2212663f 5538/* Simple binary operations: VECc = foo (VECa, VECb). */
24408032 5539
a3170dc6 5540static struct builtin_description bdesc_2arg[] =
0ac081f6 5541{
f18c054f
DB		 5542 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5543 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5544 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5545 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
0ac081f6
AH		 5546 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5547 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5548 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5549 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5550 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5551 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5552 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
f18c054f 5553 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
aba5fb01 5554 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
0ac081f6
AH		 5555 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5556 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5557 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5558 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5559 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5560 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
617e0e1d
DB		 5561 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5562 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
0ac081f6
AH		 5563 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5564 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5565 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5566 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5567 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5568 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5569 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5570 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5571 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5572 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5573 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5574 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5575 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
617e0e1d
DB		 5576 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5577 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
f18c054f
DB		 5578 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5579 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
df966bff
AH		 5580 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5581 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5582 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5583 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5584 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
0ac081f6
AH		 5585 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5586 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5587 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5588 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5589 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5590 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
f18c054f
DB		 5591 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5592 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5593 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5594 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5595 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5596 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5597 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
0ac081f6
AH		 5598 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5599 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5600 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5601 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5602 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5603 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5604 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5605 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
f96bc213 5606 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
f18c054f 5607 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
0ac081f6
AH		 5608 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5609 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5610 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5611 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5612 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5613 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5614 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5615 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5616 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5617 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5618 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5619 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5620 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5621 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5622 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5623 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5624 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5625 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5626 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
2212663f
DB		 5627 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5628 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5629 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
3e0de9d1
DP		 5630 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5631 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5632 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5633 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5634 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5635 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
0ac081f6
AH		 5636 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5637 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
f18c054f
DB		 5638 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5639 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5640 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5641 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
0ac081f6
AH		 5642 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5643 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5644 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5645 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5646 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5647 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5648 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5649 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5650 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5651 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5652 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5653 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
f18c054f 5654 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
a3170dc6 5655
58646b77
PB		 5656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
5657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
5658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
5659 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
5660 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
5661 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
5662 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
5663 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
5664 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
5665 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
5666 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
5667 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
5668 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
5669 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
5670 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
5671 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
5672 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
5673 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
5674 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
5675 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
5676 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
5677 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
5678 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
5679 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
5680 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
5681 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
5682 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
5683 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
5684 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
5685 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
5686 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
5687 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
5688 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
5689 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
5690 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
5691 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
5692 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
5693 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
5694 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
5695 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
5696 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
5697 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
5698 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
5699 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
5700 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
5701 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
5702 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
5703 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
5704 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
5705 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
5706 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
5707 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
5708 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
5709 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
5710 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
5711 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
5712 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
5713 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
5714 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
5715 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
5716 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
5717 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
5718 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
5719 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
5720 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
5721 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
5722 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
5723 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
5724 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
5725 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
5726 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
5727 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
5728 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
5729 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
5730 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
5731 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
5732 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
5733 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
5734 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
5735 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
5736 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
5737 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
5738 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
5739 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
5740 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
5741 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
5742 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
5743 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
5744 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
5745 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
5746 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
5747 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
5748 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
5749 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
5750 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
5751 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
5752 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
5753 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
5754 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
5755 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
5756 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
5757 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
5758 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
5759 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
5760 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
5761 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
5762 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
5763 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
5764 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
5765 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
5766 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
5767 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
5768 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
5769 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
5770 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
5771 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
5772 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
5773 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
5774 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
5775 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
5776 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
5777 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
5778 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
5779 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
5780 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
5781 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
5782 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
5783
a3170dc6
AH		 5784 /* Place holder, leave as first spe builtin. */
5785 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5786 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5787 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5788 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5789 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5790 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5791 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5792 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5793 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5794 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5795 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5796 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5797 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5798 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5799 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5800 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5801 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5802 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5803 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5804 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5805 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5806 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5807 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5808 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5809 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5810 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5811 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5812 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5813 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5814 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5815 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5816 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5817 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5818 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5819 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5820 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5821 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5822 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5823 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5824 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5825 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5826 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5827 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5828 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5829 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5830 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5831 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5832 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5833 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5834 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5835 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5836 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5837 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5838 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5839 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5840 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5841 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5842 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5843 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5844 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5845 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5846 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5847 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5848 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5849 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5850 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5851 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5852 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5853 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5854 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5855 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5856 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5857 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5858 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
a3170dc6
AH		 5859 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5860 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
a3170dc6
AH		 5861 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5862 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5863 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5864 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5865 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5866 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5867 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5868 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5869 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5870 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5871 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5872 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5873 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5874 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5875 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5876 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5877 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5878 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5879 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5880 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5881 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5882 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5883 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5884 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5885 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5886 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5887 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5888 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5889 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5890 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5891 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5892 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5893 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5894
5895 /* SPE binary operations expecting a 5-bit unsigned literal. */
5896 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5897
5898 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5899 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5900 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5901 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5902 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5903 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5904 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5905 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5906 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5907 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5908 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5909 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5910 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5911 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5912 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5913 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5914 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5915 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5916 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5917 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5918 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5919 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5920 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5921 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5922 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5923 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5924
5925 /* Place-holder. Leave as last binary SPE builtin. */
58646b77 5926 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
ae4b4a02
AH		 5927};
5928
5929/* AltiVec predicates. */
5930
5931struct builtin_description_predicates
5932{
5933 const unsigned int mask;
5934 const enum insn_code icode;
5935 const char *opcode;
5936 const char *const name;
5937 const enum rs6000_builtins code;
5938};
5939
5940static const struct builtin_description_predicates bdesc_altivec_preds[] =
5941{
5942 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5943 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5944 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5945 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5946 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5947 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5948 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5949 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5950 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5951 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5952 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5953 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
58646b77
PB		 5954 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
5955
5956 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
5957 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
5958 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
0ac081f6 5959};
24408032 5960
a3170dc6
AH		 5961/* SPE predicates. */
5962static struct builtin_description bdesc_spe_predicates[] =
5963{
5964 /* Place-holder. Leave as first. */
5965 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5966 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5967 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5968 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5969 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5970 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5971 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5972 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5973 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5974 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5975 /* Place-holder. Leave as last. */
5976 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5977};
5978
5979/* SPE evsel predicates. */
5980static struct builtin_description bdesc_spe_evsel[] =
5981{
5982 /* Place-holder. Leave as first. */
5983 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5984 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5985 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5986 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5987 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5988 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5989 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5990 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5991 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5992 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5993 /* Place-holder. Leave as last. */
5994 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5995};
5996
b6d08ca1 5997/* ABS* operations. */
100c4561
AH		 5998
5999static const struct builtin_description bdesc_abs[] =
6000{
6001 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6002 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6003 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6004 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6005 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6006 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6007 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6008};
6009
617e0e1d
DB		 6010/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6011 foo (VECa). */
24408032 6012
a3170dc6 6013static struct builtin_description bdesc_1arg[] =
2212663f 6014{
617e0e1d
DB		 6015 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6016 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6017 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6018 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6019 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6020 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6021 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6022 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
2212663f
DB		 6023 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6024 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6025 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
20e26713
AH		 6026 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6027 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6028 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6029 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6030 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6031 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
a3170dc6 6032
58646b77
PB		 6033 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6034 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6035 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6036 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6037 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6038 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6039 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6040 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6041 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6042 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6043 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6044 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6045 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6046 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6047 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6048 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6049 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6050 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6051 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6052
a3170dc6
AH		 6053 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6054 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6055 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6056 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6057 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6058 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6059 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6060 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6061 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6062 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6063 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6064 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6065 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6066 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6067 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6068 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6069 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6070 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6071 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6072 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6073 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6074 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6075 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6076 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6077 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6a599451 6078 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
a3170dc6
AH		 6079 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6080 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6081 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6082 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
a3170dc6
AH		 6083
6084 /* Place-holder. Leave as last unary SPE builtin. */
58646b77 6085 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
2212663f
DB		 6086};
6087
6088static rtx
a2369ed3 6089rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 6090{
6091 rtx pat;
6092 tree arg0 = TREE_VALUE (arglist);
6093 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6094 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6095 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6096
0559cc77
DE		 6097 if (icode == CODE_FOR_nothing)
6098 /* Builtin not supported on this processor. */
6099 return 0;
6100
20e26713
AH		 6101 /* If we got invalid arguments bail out before generating bad rtl. */
6102 if (arg0 == error_mark_node)
9a171fcd 6103 return const0_rtx;
20e26713 6104
0559cc77
DE		 6105 if (icode == CODE_FOR_altivec_vspltisb
6106 || icode == CODE_FOR_altivec_vspltish
6107 || icode == CODE_FOR_altivec_vspltisw
6108 || icode == CODE_FOR_spe_evsplatfi
6109 || icode == CODE_FOR_spe_evsplati)
b44140e7
AH		 6110 {
6111 /* Only allow 5-bit *signed* literals. */
b44140e7
AH		 6112 if (GET_CODE (op0) != CONST_INT
6113 || INTVAL (op0) > 0x1f
6114 || INTVAL (op0) < -0x1f)
6115 {
6116 error ("argument 1 must be a 5-bit signed literal");
9a171fcd 6117 return const0_rtx;
b44140e7 6118 }
b44140e7
AH		 6119 }
6120
c62f2db5 6121 if (target == 0
2212663f
DB		 6122 || GET_MODE (target) != tmode
6123 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6124 target = gen_reg_rtx (tmode);
6125
6126 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6127 op0 = copy_to_mode_reg (mode0, op0);
6128
6129 pat = GEN_FCN (icode) (target, op0);
6130 if (! pat)
6131 return 0;
6132 emit_insn (pat);
0ac081f6 6133
2212663f
DB		 6134 return target;
6135}
ae4b4a02 6136
100c4561 6137static rtx
a2369ed3 6138altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
100c4561
AH		 6139{
6140 rtx pat, scratch1, scratch2;
6141 tree arg0 = TREE_VALUE (arglist);
6142 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6143 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6144 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6145
6146 /* If we have invalid arguments, bail out before generating bad rtl. */
6147 if (arg0 == error_mark_node)
9a171fcd 6148 return const0_rtx;
100c4561
AH		 6149
6150 if (target == 0
6151 || GET_MODE (target) != tmode
6152 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6153 target = gen_reg_rtx (tmode);
6154
6155 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6156 op0 = copy_to_mode_reg (mode0, op0);
6157
6158 scratch1 = gen_reg_rtx (mode0);
6159 scratch2 = gen_reg_rtx (mode0);
6160
6161 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6162 if (! pat)
6163 return 0;
6164 emit_insn (pat);
6165
6166 return target;
6167}
6168
0ac081f6 6169static rtx
a2369ed3 6170rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
0ac081f6
AH		 6171{
6172 rtx pat;
6173 tree arg0 = TREE_VALUE (arglist);
6174 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6175 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6176 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6177 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6178 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6179 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6180
0559cc77
DE		 6181 if (icode == CODE_FOR_nothing)
6182 /* Builtin not supported on this processor. */
6183 return 0;
6184
20e26713
AH		 6185 /* If we got invalid arguments bail out before generating bad rtl. */
6186 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6187 return const0_rtx;
20e26713 6188
0559cc77
DE		 6189 if (icode == CODE_FOR_altivec_vcfux
6190 || icode == CODE_FOR_altivec_vcfsx
6191 || icode == CODE_FOR_altivec_vctsxs
6192 || icode == CODE_FOR_altivec_vctuxs
6193 || icode == CODE_FOR_altivec_vspltb
6194 || icode == CODE_FOR_altivec_vsplth
6195 || icode == CODE_FOR_altivec_vspltw
6196 || icode == CODE_FOR_spe_evaddiw
6197 || icode == CODE_FOR_spe_evldd
6198 || icode == CODE_FOR_spe_evldh
6199 || icode == CODE_FOR_spe_evldw
6200 || icode == CODE_FOR_spe_evlhhesplat
6201 || icode == CODE_FOR_spe_evlhhossplat
6202 || icode == CODE_FOR_spe_evlhhousplat
6203 || icode == CODE_FOR_spe_evlwhe
6204 || icode == CODE_FOR_spe_evlwhos
6205 || icode == CODE_FOR_spe_evlwhou
6206 || icode == CODE_FOR_spe_evlwhsplat
6207 || icode == CODE_FOR_spe_evlwwsplat
6208 || icode == CODE_FOR_spe_evrlwi
6209 || icode == CODE_FOR_spe_evslwi
6210 || icode == CODE_FOR_spe_evsrwis
f5119d10 6211 || icode == CODE_FOR_spe_evsubifw
0559cc77 6212 || icode == CODE_FOR_spe_evsrwiu)
b44140e7
AH		 6213 {
6214 /* Only allow 5-bit unsigned literals. */
8bb418a3 6215 STRIP_NOPS (arg1);
b44140e7
AH		 6216 if (TREE_CODE (arg1) != INTEGER_CST
6217 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6218 {
6219 error ("argument 2 must be a 5-bit unsigned literal");
9a171fcd 6220 return const0_rtx;
b44140e7 6221 }
b44140e7
AH		 6222 }
6223
c62f2db5 6224 if (target == 0
0ac081f6
AH		 6225 || GET_MODE (target) != tmode
6226 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6227 target = gen_reg_rtx (tmode);
6228
6229 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6230 op0 = copy_to_mode_reg (mode0, op0);
6231 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6232 op1 = copy_to_mode_reg (mode1, op1);
6233
6234 pat = GEN_FCN (icode) (target, op0, op1);
6235 if (! pat)
6236 return 0;
6237 emit_insn (pat);
6238
6239 return target;
6240}
6525c0e7 6241
ae4b4a02 6242static rtx
f676971a 6243altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
a2369ed3 6244 tree arglist, rtx target)
ae4b4a02
AH		 6245{
6246 rtx pat, scratch;
6247 tree cr6_form = TREE_VALUE (arglist);
6248 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6249 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6250 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6251 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6252 enum machine_mode tmode = SImode;
6253 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6254 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6255 int cr6_form_int;
6256
6257 if (TREE_CODE (cr6_form) != INTEGER_CST)
6258 {
6259 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9a171fcd 6260 return const0_rtx;
ae4b4a02
AH		 6261 }
6262 else
6263 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6264
37409796 6265 gcc_assert (mode0 == mode1);
ae4b4a02
AH		 6266
6267 /* If we have invalid arguments, bail out before generating bad rtl. */
6268 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6269 return const0_rtx;
ae4b4a02
AH		 6270
6271 if (target == 0
6272 || GET_MODE (target) != tmode
6273 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6274 target = gen_reg_rtx (tmode);
6275
6276 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6277 op0 = copy_to_mode_reg (mode0, op0);
6278 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6279 op1 = copy_to_mode_reg (mode1, op1);
6280
6281 scratch = gen_reg_rtx (mode0);
6282
6283 pat = GEN_FCN (icode) (scratch, op0, op1,
f1c25d3b 6284 gen_rtx_SYMBOL_REF (Pmode, opcode));
ae4b4a02
AH		 6285 if (! pat)
6286 return 0;
6287 emit_insn (pat);
6288
6289 /* The vec_any* and vec_all* predicates use the same opcodes for two
6290 different operations, but the bits in CR6 will be different
6291 depending on what information we want. So we have to play tricks
6292 with CR6 to get the right bits out.
6293
6294 If you think this is disgusting, look at the specs for the
6295 AltiVec predicates. */
6296
c4ad648e
AM		 6297 switch (cr6_form_int)
6298 {
6299 case 0:
6300 emit_insn (gen_cr6_test_for_zero (target));
6301 break;
6302 case 1:
6303 emit_insn (gen_cr6_test_for_zero_reverse (target));
6304 break;
6305 case 2:
6306 emit_insn (gen_cr6_test_for_lt (target));
6307 break;
6308 case 3:
6309 emit_insn (gen_cr6_test_for_lt_reverse (target));
6310 break;
6311 default:
6312 error ("argument 1 of __builtin_altivec_predicate is out of range");
6313 break;
6314 }
ae4b4a02
AH		 6315
6316 return target;
6317}
6318
b4a62fa0 6319static rtx
38f391a5 6320altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
b4a62fa0
SB		 6321{
6322 rtx pat, addr;
6323 tree arg0 = TREE_VALUE (arglist);
6324 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6325 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6326 enum machine_mode mode0 = Pmode;
6327 enum machine_mode mode1 = Pmode;
6328 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6329 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6330
6331 if (icode == CODE_FOR_nothing)
6332 /* Builtin not supported on this processor. */
6333 return 0;
6334
6335 /* If we got invalid arguments bail out before generating bad rtl. */
6336 if (arg0 == error_mark_node || arg1 == error_mark_node)
6337 return const0_rtx;
6338
6339 if (target == 0
6340 || GET_MODE (target) != tmode
6341 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6342 target = gen_reg_rtx (tmode);
6343
f676971a 6344 op1 = copy_to_mode_reg (mode1, op1);
b4a62fa0
SB		 6345
6346 if (op0 == const0_rtx)
6347 {
6348 addr = gen_rtx_MEM (tmode, op1);
6349 }
6350 else
6351 {
6352 op0 = copy_to_mode_reg (mode0, op0);
6353 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6354 }
6355
6356 pat = GEN_FCN (icode) (target, addr);
6357
6358 if (! pat)
6359 return 0;
6360 emit_insn (pat);
6361
6362 return target;
6363}
6364
61bea3b0
AH		 6365static rtx
6366spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6367{
6368 tree arg0 = TREE_VALUE (arglist);
6369 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6370 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6371 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6372 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6373 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6374 rtx pat;
6375 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6376 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6377 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6378
6379 /* Invalid arguments. Bail before doing anything stoopid! */
6380 if (arg0 == error_mark_node
6381 || arg1 == error_mark_node
6382 || arg2 == error_mark_node)
6383 return const0_rtx;
6384
6385 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6386 op0 = copy_to_mode_reg (mode2, op0);
6387 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6388 op1 = copy_to_mode_reg (mode0, op1);
6389 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6390 op2 = copy_to_mode_reg (mode1, op2);
6391
6392 pat = GEN_FCN (icode) (op1, op2, op0);
6393 if (pat)
6394 emit_insn (pat);
6395 return NULL_RTX;
6396}
6397
6525c0e7 6398static rtx
a2369ed3 6399altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6525c0e7
AH		 6400{
6401 tree arg0 = TREE_VALUE (arglist);
6402 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6403 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6404 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6405 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6406 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
b4a62fa0
SB		 6407 rtx pat, addr;
6408 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6409 enum machine_mode mode1 = Pmode;
6410 enum machine_mode mode2 = Pmode;
6525c0e7
AH		 6411
6412 /* Invalid arguments. Bail before doing anything stoopid! */
6413 if (arg0 == error_mark_node
6414 || arg1 == error_mark_node
6415 || arg2 == error_mark_node)
9a171fcd 6416 return const0_rtx;
6525c0e7 6417
b4a62fa0
SB		 6418 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6419 op0 = copy_to_mode_reg (tmode, op0);
6420
f676971a 6421 op2 = copy_to_mode_reg (mode2, op2);
b4a62fa0
SB		 6422
6423 if (op1 == const0_rtx)
6424 {
6425 addr = gen_rtx_MEM (tmode, op2);
6426 }
6427 else
6428 {
6429 op1 = copy_to_mode_reg (mode1, op1);
6430 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6431 }
6525c0e7 6432
b4a62fa0 6433 pat = GEN_FCN (icode) (addr, op0);
6525c0e7
AH		 6434 if (pat)
6435 emit_insn (pat);
6436 return NULL_RTX;
6437}
6438
2212663f 6439static rtx
a2369ed3 6440rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 6441{
6442 rtx pat;
6443 tree arg0 = TREE_VALUE (arglist);
6444 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6445 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6446 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6447 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6448 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6449 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6450 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6451 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6452 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
0ac081f6 6453
774b5662
DE		 6454 if (icode == CODE_FOR_nothing)
6455 /* Builtin not supported on this processor. */
6456 return 0;
6457
20e26713
AH		 6458 /* If we got invalid arguments bail out before generating bad rtl. */
6459 if (arg0 == error_mark_node
6460 || arg1 == error_mark_node
6461 || arg2 == error_mark_node)
9a171fcd 6462 return const0_rtx;
20e26713 6463
aba5fb01
NS		 6464 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6465 || icode == CODE_FOR_altivec_vsldoi_v4si
6466 || icode == CODE_FOR_altivec_vsldoi_v8hi
6467 || icode == CODE_FOR_altivec_vsldoi_v16qi)
b44140e7
AH		 6468 {
6469 /* Only allow 4-bit unsigned literals. */
8bb418a3 6470 STRIP_NOPS (arg2);
b44140e7
AH		 6471 if (TREE_CODE (arg2) != INTEGER_CST
6472 || TREE_INT_CST_LOW (arg2) & ~0xf)
6473 {
6474 error ("argument 3 must be a 4-bit unsigned literal");
e3277ffb 6475 return const0_rtx;
b44140e7 6476 }
b44140e7
AH		 6477 }
6478
c62f2db5 6479 if (target == 0
2212663f
DB		 6480 || GET_MODE (target) != tmode
6481 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6482 target = gen_reg_rtx (tmode);
6483
6484 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6485 op0 = copy_to_mode_reg (mode0, op0);
6486 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6487 op1 = copy_to_mode_reg (mode1, op1);
6488 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6489 op2 = copy_to_mode_reg (mode2, op2);
6490
6491 pat = GEN_FCN (icode) (target, op0, op1, op2);
6492 if (! pat)
6493 return 0;
6494 emit_insn (pat);
6495
6496 return target;
6497}
92898235 6498
3a9b8c7e 6499/* Expand the lvx builtins. */
0ac081f6 6500static rtx
a2369ed3 6501altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
0ac081f6 6502{
0ac081f6
AH		 6503 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6504 tree arglist = TREE_OPERAND (exp, 1);
0ac081f6 6505 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3a9b8c7e
AH		 6506 tree arg0;
6507 enum machine_mode tmode, mode0;
7c3abc73 6508 rtx pat, op0;
3a9b8c7e 6509 enum insn_code icode;
92898235 6510
0ac081f6
AH		 6511 switch (fcode)
6512 {
f18c054f 6513 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
81466555 6514 icode = CODE_FOR_altivec_lvx_v16qi;
3a9b8c7e 6515 break;
f18c054f 6516 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
81466555 6517 icode = CODE_FOR_altivec_lvx_v8hi;
3a9b8c7e
AH		 6518 break;
6519 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
81466555 6520 icode = CODE_FOR_altivec_lvx_v4si;
3a9b8c7e
AH		 6521 break;
6522 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
81466555 6523 icode = CODE_FOR_altivec_lvx_v4sf;
3a9b8c7e
AH		 6524 break;
6525 default:
6526 *expandedp = false;
6527 return NULL_RTX;
6528 }
0ac081f6 6529
3a9b8c7e 6530 *expandedp = true;
f18c054f 6531
3a9b8c7e
AH		 6532 arg0 = TREE_VALUE (arglist);
6533 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6534 tmode = insn_data[icode].operand[0].mode;
6535 mode0 = insn_data[icode].operand[1].mode;
f18c054f 6536
3a9b8c7e
AH		 6537 if (target == 0
6538 || GET_MODE (target) != tmode
6539 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6540 target = gen_reg_rtx (tmode);
24408032 6541
3a9b8c7e
AH		 6542 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6543 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
f18c054f 6544
3a9b8c7e
AH		 6545 pat = GEN_FCN (icode) (target, op0);
6546 if (! pat)
6547 return 0;
6548 emit_insn (pat);
6549 return target;
6550}
f18c054f 6551
3a9b8c7e
AH		 6552/* Expand the stvx builtins. */
6553static rtx
f676971a 6554altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6555 bool *expandedp)
3a9b8c7e
AH		 6556{
6557 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6558 tree arglist = TREE_OPERAND (exp, 1);
6559 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6560 tree arg0, arg1;
6561 enum machine_mode mode0, mode1;
7c3abc73 6562 rtx pat, op0, op1;
3a9b8c7e 6563 enum insn_code icode;
f18c054f 6564
3a9b8c7e
AH		 6565 switch (fcode)
6566 {
6567 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
81466555 6568 icode = CODE_FOR_altivec_stvx_v16qi;
3a9b8c7e
AH		 6569 break;
6570 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
81466555 6571 icode = CODE_FOR_altivec_stvx_v8hi;
3a9b8c7e
AH		 6572 break;
6573 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
81466555 6574 icode = CODE_FOR_altivec_stvx_v4si;
3a9b8c7e
AH		 6575 break;
6576 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
81466555 6577 icode = CODE_FOR_altivec_stvx_v4sf;
3a9b8c7e
AH		 6578 break;
6579 default:
6580 *expandedp = false;
6581 return NULL_RTX;
6582 }
24408032 6583
3a9b8c7e
AH		 6584 arg0 = TREE_VALUE (arglist);
6585 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6586 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6587 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6588 mode0 = insn_data[icode].operand[0].mode;
6589 mode1 = insn_data[icode].operand[1].mode;
f18c054f 6590
3a9b8c7e
AH		 6591 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6592 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6593 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6594 op1 = copy_to_mode_reg (mode1, op1);
f18c054f 6595
3a9b8c7e
AH		 6596 pat = GEN_FCN (icode) (op0, op1);
6597 if (pat)
6598 emit_insn (pat);
f18c054f 6599
3a9b8c7e
AH		 6600 *expandedp = true;
6601 return NULL_RTX;
6602}
f18c054f 6603
3a9b8c7e
AH		 6604/* Expand the dst builtins. */
6605static rtx
f676971a 6606altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6607 bool *expandedp)
3a9b8c7e
AH		 6608{
6609 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6610 tree arglist = TREE_OPERAND (exp, 1);
6611 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6612 tree arg0, arg1, arg2;
6613 enum machine_mode mode0, mode1, mode2;
7c3abc73 6614 rtx pat, op0, op1, op2;
3a9b8c7e 6615 struct builtin_description *d;
a3170dc6 6616 size_t i;
f18c054f 6617
3a9b8c7e 6618 *expandedp = false;
f18c054f 6619
3a9b8c7e
AH		 6620 /* Handle DST variants. */
6621 d = (struct builtin_description *) bdesc_dst;
6622 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6623 if (d->code == fcode)
6624 {
6625 arg0 = TREE_VALUE (arglist);
6626 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6627 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6628 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6629 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6630 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6631 mode0 = insn_data[d->icode].operand[0].mode;
6632 mode1 = insn_data[d->icode].operand[1].mode;
6633 mode2 = insn_data[d->icode].operand[2].mode;
24408032 6634
3a9b8c7e
AH		 6635 /* Invalid arguments, bail out before generating bad rtl. */
6636 if (arg0 == error_mark_node
6637 || arg1 == error_mark_node
6638 || arg2 == error_mark_node)
6639 return const0_rtx;
f18c054f 6640
86e7df90 6641 *expandedp = true;
8bb418a3 6642 STRIP_NOPS (arg2);
3a9b8c7e
AH		 6643 if (TREE_CODE (arg2) != INTEGER_CST
6644 || TREE_INT_CST_LOW (arg2) & ~0x3)
6645 {
9e637a26 6646 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
3a9b8c7e
AH		 6647 return const0_rtx;
6648 }
f18c054f 6649
3a9b8c7e 6650 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
666158b9 6651 op0 = copy_to_mode_reg (Pmode, op0);
3a9b8c7e
AH		 6652 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6653 op1 = copy_to_mode_reg (mode1, op1);
24408032 6654
3a9b8c7e
AH		 6655 pat = GEN_FCN (d->icode) (op0, op1, op2);
6656 if (pat != 0)
6657 emit_insn (pat);
f18c054f 6658
3a9b8c7e
AH		 6659 return NULL_RTX;
6660 }
f18c054f 6661
3a9b8c7e
AH		 6662 return NULL_RTX;
6663}
24408032 6664
3a9b8c7e
AH		 6665/* Expand the builtin in EXP and store the result in TARGET. Store
6666 true in *EXPANDEDP if we found a builtin to expand. */
6667static rtx
a2369ed3 6668altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
3a9b8c7e
AH		 6669{
6670 struct builtin_description *d;
6671 struct builtin_description_predicates *dp;
6672 size_t i;
6673 enum insn_code icode;
6674 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6675 tree arglist = TREE_OPERAND (exp, 1);
7c3abc73
AH		 6676 tree arg0;
6677 rtx op0, pat;
6678 enum machine_mode tmode, mode0;
3a9b8c7e 6679 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
0ac081f6 6680
58646b77
PB		 6681 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
6682 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
6683 {
6684 *expandedp = true;
6685 error ("unresolved overload for Altivec builtin %qE", fndecl);
6686 return const0_rtx;
6687 }
6688
3a9b8c7e
AH		 6689 target = altivec_expand_ld_builtin (exp, target, expandedp);
6690 if (*expandedp)
6691 return target;
0ac081f6 6692
3a9b8c7e
AH		 6693 target = altivec_expand_st_builtin (exp, target, expandedp);
6694 if (*expandedp)
6695 return target;
6696
6697 target = altivec_expand_dst_builtin (exp, target, expandedp);
6698 if (*expandedp)
6699 return target;
6700
6701 *expandedp = true;
95385cbb 6702
3a9b8c7e
AH		 6703 switch (fcode)
6704 {
6525c0e7
AH		 6705 case ALTIVEC_BUILTIN_STVX:
6706 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6707 case ALTIVEC_BUILTIN_STVEBX:
6708 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6709 case ALTIVEC_BUILTIN_STVEHX:
6710 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6711 case ALTIVEC_BUILTIN_STVEWX:
6712 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6713 case ALTIVEC_BUILTIN_STVXL:
6714 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
3a9b8c7e 6715
95385cbb
AH		 6716 case ALTIVEC_BUILTIN_MFVSCR:
6717 icode = CODE_FOR_altivec_mfvscr;
6718 tmode = insn_data[icode].operand[0].mode;
6719
6720 if (target == 0
6721 || GET_MODE (target) != tmode
6722 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6723 target = gen_reg_rtx (tmode);
f676971a 6724
95385cbb 6725 pat = GEN_FCN (icode) (target);
0ac081f6
AH		 6726 if (! pat)
6727 return 0;
6728 emit_insn (pat);
95385cbb
AH		 6729 return target;
6730
6731 case ALTIVEC_BUILTIN_MTVSCR:
6732 icode = CODE_FOR_altivec_mtvscr;
6733 arg0 = TREE_VALUE (arglist);
6734 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6735 mode0 = insn_data[icode].operand[0].mode;
6736
6737 /* If we got invalid arguments bail out before generating bad rtl. */
6738 if (arg0 == error_mark_node)
9a171fcd 6739 return const0_rtx;
95385cbb
AH		 6740
6741 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6742 op0 = copy_to_mode_reg (mode0, op0);
6743
6744 pat = GEN_FCN (icode) (op0);
6745 if (pat)
6746 emit_insn (pat);
6747 return NULL_RTX;
3a9b8c7e 6748
95385cbb
AH		 6749 case ALTIVEC_BUILTIN_DSSALL:
6750 emit_insn (gen_altivec_dssall ());
6751 return NULL_RTX;
6752
6753 case ALTIVEC_BUILTIN_DSS:
6754 icode = CODE_FOR_altivec_dss;
6755 arg0 = TREE_VALUE (arglist);
8bb418a3 6756 STRIP_NOPS (arg0);
95385cbb
AH		 6757 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6758 mode0 = insn_data[icode].operand[0].mode;
6759
6760 /* If we got invalid arguments bail out before generating bad rtl. */
6761 if (arg0 == error_mark_node)
9a171fcd 6762 return const0_rtx;
95385cbb 6763
b44140e7
AH		 6764 if (TREE_CODE (arg0) != INTEGER_CST
6765 || TREE_INT_CST_LOW (arg0) & ~0x3)
6766 {
6767 error ("argument to dss must be a 2-bit unsigned literal");
9a171fcd 6768 return const0_rtx;
b44140e7
AH		 6769 }
6770
95385cbb
AH		 6771 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6772 op0 = copy_to_mode_reg (mode0, op0);
6773
6774 emit_insn (gen_altivec_dss (op0));
0ac081f6
AH		 6775 return NULL_RTX;
6776 }
24408032 6777
100c4561
AH		 6778 /* Expand abs* operations. */
6779 d = (struct builtin_description *) bdesc_abs;
ca7558fc 6780 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
100c4561
AH		 6781 if (d->code == fcode)
6782 return altivec_expand_abs_builtin (d->icode, arglist, target);
6783
ae4b4a02
AH		 6784 /* Expand the AltiVec predicates. */
6785 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
ca7558fc 6786 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
ae4b4a02 6787 if (dp->code == fcode)
c4ad648e
AM		 6788 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6789 arglist, target);
ae4b4a02 6790
6525c0e7
AH		 6791 /* LV* are funky. We initialized them differently. */
6792 switch (fcode)
6793 {
6794 case ALTIVEC_BUILTIN_LVSL:
b4a62fa0 6795 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
c4ad648e 6796 arglist, target);
6525c0e7 6797 case ALTIVEC_BUILTIN_LVSR:
b4a62fa0 6798 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
c4ad648e 6799 arglist, target);
6525c0e7 6800 case ALTIVEC_BUILTIN_LVEBX:
b4a62fa0 6801 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
c4ad648e 6802 arglist, target);
6525c0e7 6803 case ALTIVEC_BUILTIN_LVEHX:
b4a62fa0 6804 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
c4ad648e 6805 arglist, target);
6525c0e7 6806 case ALTIVEC_BUILTIN_LVEWX:
b4a62fa0 6807 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
c4ad648e 6808 arglist, target);
6525c0e7 6809 case ALTIVEC_BUILTIN_LVXL:
b4a62fa0 6810 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
c4ad648e 6811 arglist, target);
6525c0e7 6812 case ALTIVEC_BUILTIN_LVX:
b4a62fa0 6813 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
c4ad648e 6814 arglist, target);
6525c0e7
AH		 6815 default:
6816 break;
6817 /* Fall through. */
6818 }
95385cbb 6819
92898235 6820 *expandedp = false;
0ac081f6
AH		 6821 return NULL_RTX;
6822}
6823
a3170dc6
AH		 6824/* Binops that need to be initialized manually, but can be expanded
6825 automagically by rs6000_expand_binop_builtin. */
6826static struct builtin_description bdesc_2arg_spe[] =
6827{
6828 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6829 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6830 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6831 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6832 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6833 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6834 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6835 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6836 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6837 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6838 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6839 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6840 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6841 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6842 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6843 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6844 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6845 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6846 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6847 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6848 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6849 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6850};
6851
6852/* Expand the builtin in EXP and store the result in TARGET. Store
6853 true in *EXPANDEDP if we found a builtin to expand.
6854
6855 This expands the SPE builtins that are not simple unary and binary
6856 operations. */
6857static rtx
a2369ed3 6858spe_expand_builtin (tree exp, rtx target, bool *expandedp)
a3170dc6
AH		 6859{
6860 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6861 tree arglist = TREE_OPERAND (exp, 1);
6862 tree arg1, arg0;
6863 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6864 enum insn_code icode;
6865 enum machine_mode tmode, mode0;
6866 rtx pat, op0;
6867 struct builtin_description *d;
6868 size_t i;
6869
6870 *expandedp = true;
6871
6872 /* Syntax check for a 5-bit unsigned immediate. */
6873 switch (fcode)
6874 {
6875 case SPE_BUILTIN_EVSTDD:
6876 case SPE_BUILTIN_EVSTDH:
6877 case SPE_BUILTIN_EVSTDW:
6878 case SPE_BUILTIN_EVSTWHE:
6879 case SPE_BUILTIN_EVSTWHO:
6880 case SPE_BUILTIN_EVSTWWE:
6881 case SPE_BUILTIN_EVSTWWO:
6882 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6883 if (TREE_CODE (arg1) != INTEGER_CST
6884 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6885 {
6886 error ("argument 2 must be a 5-bit unsigned literal");
6887 return const0_rtx;
6888 }
6889 break;
6890 default:
6891 break;
6892 }
6893
00332c9f
AH		 6894 /* The evsplat*i instructions are not quite generic. */
6895 switch (fcode)
6896 {
6897 case SPE_BUILTIN_EVSPLATFI:
6898 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6899 arglist, target);
6900 case SPE_BUILTIN_EVSPLATI:
6901 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6902 arglist, target);
6903 default:
6904 break;
6905 }
6906
a3170dc6
AH		 6907 d = (struct builtin_description *) bdesc_2arg_spe;
6908 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6909 if (d->code == fcode)
6910 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6911
6912 d = (struct builtin_description *) bdesc_spe_predicates;
6913 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6914 if (d->code == fcode)
6915 return spe_expand_predicate_builtin (d->icode, arglist, target);
6916
6917 d = (struct builtin_description *) bdesc_spe_evsel;
6918 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6919 if (d->code == fcode)
6920 return spe_expand_evsel_builtin (d->icode, arglist, target);
6921
6922 switch (fcode)
6923 {
6924 case SPE_BUILTIN_EVSTDDX:
61bea3b0 6925 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
a3170dc6 6926 case SPE_BUILTIN_EVSTDHX:
61bea3b0 6927 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
a3170dc6 6928 case SPE_BUILTIN_EVSTDWX:
61bea3b0 6929 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
a3170dc6 6930 case SPE_BUILTIN_EVSTWHEX:
61bea3b0 6931 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
a3170dc6 6932 case SPE_BUILTIN_EVSTWHOX:
61bea3b0 6933 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
a3170dc6 6934 case SPE_BUILTIN_EVSTWWEX:
61bea3b0 6935 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
a3170dc6 6936 case SPE_BUILTIN_EVSTWWOX:
61bea3b0 6937 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
a3170dc6 6938 case SPE_BUILTIN_EVSTDD:
61bea3b0 6939 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
a3170dc6 6940 case SPE_BUILTIN_EVSTDH:
61bea3b0 6941 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
a3170dc6 6942 case SPE_BUILTIN_EVSTDW:
61bea3b0 6943 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
a3170dc6 6944 case SPE_BUILTIN_EVSTWHE:
61bea3b0 6945 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
a3170dc6 6946 case SPE_BUILTIN_EVSTWHO:
61bea3b0 6947 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
a3170dc6 6948 case SPE_BUILTIN_EVSTWWE:
61bea3b0 6949 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
a3170dc6 6950 case SPE_BUILTIN_EVSTWWO:
61bea3b0 6951 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
a3170dc6
AH		 6952 case SPE_BUILTIN_MFSPEFSCR:
6953 icode = CODE_FOR_spe_mfspefscr;
6954 tmode = insn_data[icode].operand[0].mode;
6955
6956 if (target == 0
6957 || GET_MODE (target) != tmode
6958 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6959 target = gen_reg_rtx (tmode);
f676971a 6960
a3170dc6
AH		 6961 pat = GEN_FCN (icode) (target);
6962 if (! pat)
6963 return 0;
6964 emit_insn (pat);
6965 return target;
6966 case SPE_BUILTIN_MTSPEFSCR:
6967 icode = CODE_FOR_spe_mtspefscr;
6968 arg0 = TREE_VALUE (arglist);
6969 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6970 mode0 = insn_data[icode].operand[0].mode;
6971
6972 if (arg0 == error_mark_node)
6973 return const0_rtx;
6974
6975 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6976 op0 = copy_to_mode_reg (mode0, op0);
6977
6978 pat = GEN_FCN (icode) (op0);
6979 if (pat)
6980 emit_insn (pat);
6981 return NULL_RTX;
6982 default:
6983 break;
6984 }
6985
6986 *expandedp = false;
6987 return NULL_RTX;
6988}
6989
6990static rtx
a2369ed3 6991spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 6992{
6993 rtx pat, scratch, tmp;
6994 tree form = TREE_VALUE (arglist);
6995 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6996 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6997 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6998 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6999 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7000 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7001 int form_int;
7002 enum rtx_code code;
7003
7004 if (TREE_CODE (form) != INTEGER_CST)
7005 {
7006 error ("argument 1 of __builtin_spe_predicate must be a constant");
7007 return const0_rtx;
7008 }
7009 else
7010 form_int = TREE_INT_CST_LOW (form);
7011
37409796 7012 gcc_assert (mode0 == mode1);
a3170dc6
AH		 7013
7014 if (arg0 == error_mark_node || arg1 == error_mark_node)
7015 return const0_rtx;
7016
7017 if (target == 0
7018 || GET_MODE (target) != SImode
7019 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7020 target = gen_reg_rtx (SImode);
7021
7022 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7023 op0 = copy_to_mode_reg (mode0, op0);
7024 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7025 op1 = copy_to_mode_reg (mode1, op1);
7026
7027 scratch = gen_reg_rtx (CCmode);
7028
7029 pat = GEN_FCN (icode) (scratch, op0, op1);
7030 if (! pat)
7031 return const0_rtx;
7032 emit_insn (pat);
7033
7034 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7035 _lower_. We use one compare, but look in different bits of the
7036 CR for each variant.
7037
7038 There are 2 elements in each SPE simd type (upper/lower). The CR
7039 bits are set as follows:
7040
7041 BIT0 | BIT 1 | BIT 2 | BIT 3
7042 U | L | (U | L) | (U & L)
7043
7044 So, for an "all" relationship, BIT 3 would be set.
7045 For an "any" relationship, BIT 2 would be set. Etc.
7046
7047 Following traditional nomenclature, these bits map to:
7048
7049 BIT0 | BIT 1 | BIT 2 | BIT 3
7050 LT | GT | EQ | OV
7051
7052 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7053 */
7054
7055 switch (form_int)
7056 {
7057 /* All variant. OV bit. */
7058 case 0:
7059 /* We need to get to the OV bit, which is the ORDERED bit. We
7060 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7061 that's ugly and will trigger a validate_condition_mode abort.
7062 So let's just use another pattern. */
7063 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7064 return target;
7065 /* Any variant. EQ bit. */
7066 case 1:
7067 code = EQ;
7068 break;
7069 /* Upper variant. LT bit. */
7070 case 2:
7071 code = LT;
7072 break;
7073 /* Lower variant. GT bit. */
7074 case 3:
7075 code = GT;
7076 break;
7077 default:
7078 error ("argument 1 of __builtin_spe_predicate is out of range");
7079 return const0_rtx;
7080 }
7081
7082 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7083 emit_move_insn (target, tmp);
7084
7085 return target;
7086}
7087
7088/* The evsel builtins look like this:
7089
7090 e = __builtin_spe_evsel_OP (a, b, c, d);
7091
7092 and work like this:
7093
7094 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7095 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7096*/
7097
7098static rtx
a2369ed3 7099spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 7100{
7101 rtx pat, scratch;
7102 tree arg0 = TREE_VALUE (arglist);
7103 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7104 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7105 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7106 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7107 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7108 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7109 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7110 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7111 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7112
37409796 7113 gcc_assert (mode0 == mode1);
a3170dc6
AH		 7114
7115 if (arg0 == error_mark_node || arg1 == error_mark_node
7116 || arg2 == error_mark_node || arg3 == error_mark_node)
7117 return const0_rtx;
7118
7119 if (target == 0
7120 || GET_MODE (target) != mode0
7121 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7122 target = gen_reg_rtx (mode0);
7123
7124 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7125 op0 = copy_to_mode_reg (mode0, op0);
7126 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7127 op1 = copy_to_mode_reg (mode0, op1);
7128 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7129 op2 = copy_to_mode_reg (mode0, op2);
7130 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7131 op3 = copy_to_mode_reg (mode0, op3);
7132
7133 /* Generate the compare. */
7134 scratch = gen_reg_rtx (CCmode);
7135 pat = GEN_FCN (icode) (scratch, op0, op1);
7136 if (! pat)
7137 return const0_rtx;
7138 emit_insn (pat);
7139
7140 if (mode0 == V2SImode)
7141 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7142 else
7143 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7144
7145 return target;
7146}
7147
0ac081f6
AH		 7148/* Expand an expression EXP that calls a built-in function,
7149 with result going to TARGET if that's convenient
7150 (and in mode MODE if that's convenient).
7151 SUBTARGET may be used as the target for computing one of EXP's operands.
7152 IGNORE is nonzero if the value is to be ignored. */
7153
7154static rtx
a2369ed3 7155rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
c4ad648e
AM		 7156 enum machine_mode mode ATTRIBUTE_UNUSED,
7157 int ignore ATTRIBUTE_UNUSED)
0ac081f6 7158{
92898235
AH		 7159 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7160 tree arglist = TREE_OPERAND (exp, 1);
7161 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7162 struct builtin_description *d;
7163 size_t i;
7164 rtx ret;
7165 bool success;
f676971a 7166
7ccf35ed
DN		 7167 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7168 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7169 {
7170 int icode = (int) CODE_FOR_altivec_lvsr;
7171 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7172 enum machine_mode mode = insn_data[icode].operand[1].mode;
7173 tree arg;
7174 rtx op, addr, pat;
7175
37409796 7176 gcc_assert (TARGET_ALTIVEC);
7ccf35ed
DN		 7177
7178 arg = TREE_VALUE (arglist);
37409796 7179 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7ccf35ed
DN		 7180 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7181 addr = memory_address (mode, op);
7182 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7183 op = addr;
7184 else
7185 {
7186 /* For the load case need to negate the address. */
7187 op = gen_reg_rtx (GET_MODE (addr));
7188 emit_insn (gen_rtx_SET (VOIDmode, op,
7189 gen_rtx_NEG (GET_MODE (addr), addr)));
c4ad648e 7190 }
7ccf35ed
DN		 7191 op = gen_rtx_MEM (mode, op);
7192
7193 if (target == 0
7194 || GET_MODE (target) != tmode
7195 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7196 target = gen_reg_rtx (tmode);
7197
7198 /*pat = gen_altivec_lvsr (target, op);*/
7199 pat = GEN_FCN (icode) (target, op);
7200 if (!pat)
7201 return 0;
7202 emit_insn (pat);
7203
7204 return target;
7205 }
7206
0ac081f6 7207 if (TARGET_ALTIVEC)
92898235
AH		 7208 {
7209 ret = altivec_expand_builtin (exp, target, &success);
7210
a3170dc6
AH		 7211 if (success)
7212 return ret;
7213 }
7214 if (TARGET_SPE)
7215 {
7216 ret = spe_expand_builtin (exp, target, &success);
7217
92898235
AH		 7218 if (success)
7219 return ret;
7220 }
7221
37409796
NS		 7222 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7223
7224 /* Handle simple unary operations. */
7225 d = (struct builtin_description *) bdesc_1arg;
7226 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7227 if (d->code == fcode)
7228 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7229
7230 /* Handle simple binary operations. */
7231 d = (struct builtin_description *) bdesc_2arg;
7232 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7233 if (d->code == fcode)
7234 return rs6000_expand_binop_builtin (d->icode, arglist, target);
0ac081f6 7235
37409796
NS		 7236 /* Handle simple ternary operations. */
7237 d = (struct builtin_description *) bdesc_3arg;
7238 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7239 if (d->code == fcode)
7240 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7241
7242 gcc_unreachable ();
0ac081f6
AH		 7243}
7244
7c62e993
PB		 7245static tree
7246build_opaque_vector_type (tree node, int nunits)
7247{
7248 node = copy_node (node);
7249 TYPE_MAIN_VARIANT (node) = node;
7250 return build_vector_type (node, nunits);
7251}
7252
0ac081f6 7253static void
863d938c 7254rs6000_init_builtins (void)
0ac081f6 7255{
4a5eab38
PB		 7256 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7257 V2SF_type_node = build_vector_type (float_type_node, 2);
7258 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7259 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7260 V4SF_type_node = build_vector_type (float_type_node, 4);
7e463bda 7261 V8HI_type_node = build_vector_type (intHI_type_node, 8);
4a5eab38
PB		 7262 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7263
7264 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7265 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7266 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7267
7c62e993
PB		 7268 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7269 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
6035d635 7270 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
58646b77 7271 opaque_V4SI_type_node = copy_node (V4SI_type_node);
3fdaa45a 7272
8bb418a3
ZL		 7273 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7274 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7275 'vector unsigned short'. */
7276
8dd16ecc
NS		 7277 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7278 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7279 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7280 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8bb418a3 7281
58646b77
PB		 7282 long_integer_type_internal_node = long_integer_type_node;
7283 long_unsigned_type_internal_node = long_unsigned_type_node;
7284 intQI_type_internal_node = intQI_type_node;
7285 uintQI_type_internal_node = unsigned_intQI_type_node;
7286 intHI_type_internal_node = intHI_type_node;
7287 uintHI_type_internal_node = unsigned_intHI_type_node;
7288 intSI_type_internal_node = intSI_type_node;
7289 uintSI_type_internal_node = unsigned_intSI_type_node;
7290 float_type_internal_node = float_type_node;
7291 void_type_internal_node = void_type_node;
7292
8bb418a3
ZL		 7293 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7294 get_identifier ("__bool char"),
7295 bool_char_type_node));
7296 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7297 get_identifier ("__bool short"),
7298 bool_short_type_node));
7299 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7300 get_identifier ("__bool int"),
7301 bool_int_type_node));
7302 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7303 get_identifier ("__pixel"),
7304 pixel_type_node));
7305
4a5eab38
PB		 7306 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7307 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7308 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7309 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8bb418a3
ZL		 7310
7311 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7312 get_identifier ("__vector unsigned char"),
7313 unsigned_V16QI_type_node));
7314 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7315 get_identifier ("__vector signed char"),
7316 V16QI_type_node));
7317 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7318 get_identifier ("__vector __bool char"),
7319 bool_V16QI_type_node));
7320
7321 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7322 get_identifier ("__vector unsigned short"),
7323 unsigned_V8HI_type_node));
7324 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7325 get_identifier ("__vector signed short"),
7326 V8HI_type_node));
7327 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7328 get_identifier ("__vector __bool short"),
7329 bool_V8HI_type_node));
7330
7331 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7332 get_identifier ("__vector unsigned int"),
7333 unsigned_V4SI_type_node));
7334 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7335 get_identifier ("__vector signed int"),
7336 V4SI_type_node));
7337 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7338 get_identifier ("__vector __bool int"),
7339 bool_V4SI_type_node));
7340
7341 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7342 get_identifier ("__vector float"),
7343 V4SF_type_node));
7344 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7345 get_identifier ("__vector __pixel"),
7346 pixel_V8HI_type_node));
7347
a3170dc6 7348 if (TARGET_SPE)
3fdaa45a 7349 spe_init_builtins ();
0ac081f6
AH		 7350 if (TARGET_ALTIVEC)
7351 altivec_init_builtins ();
0559cc77
DE		 7352 if (TARGET_ALTIVEC || TARGET_SPE)
7353 rs6000_common_init_builtins ();
0ac081f6
AH		 7354}
7355
a3170dc6
AH		 7356/* Search through a set of builtins and enable the mask bits.
7357 DESC is an array of builtins.
b6d08ca1 7358 SIZE is the total number of builtins.
a3170dc6
AH		 7359 START is the builtin enum at which to start.
7360 END is the builtin enum at which to end. */
0ac081f6 7361static void
a2369ed3 7362enable_mask_for_builtins (struct builtin_description *desc, int size,
f676971a 7363 enum rs6000_builtins start,
a2369ed3 7364 enum rs6000_builtins end)
a3170dc6
AH		 7365{
7366 int i;
7367
7368 for (i = 0; i < size; ++i)
7369 if (desc[i].code == start)
7370 break;
7371
7372 if (i == size)
7373 return;
7374
7375 for (; i < size; ++i)
7376 {
7377 /* Flip all the bits on. */
7378 desc[i].mask = target_flags;
7379 if (desc[i].code == end)
7380 break;
7381 }
7382}
7383
7384static void
863d938c 7385spe_init_builtins (void)
0ac081f6 7386{
a3170dc6
AH		 7387 tree endlink = void_list_node;
7388 tree puint_type_node = build_pointer_type (unsigned_type_node);
7389 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
ae4b4a02 7390 struct builtin_description *d;
0ac081f6
AH		 7391 size_t i;
7392
a3170dc6
AH		 7393 tree v2si_ftype_4_v2si
7394 = build_function_type
3fdaa45a
AH		 7395 (opaque_V2SI_type_node,
7396 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7397 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7398 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7399 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7400 endlink)))));
7401
7402 tree v2sf_ftype_4_v2sf
7403 = build_function_type
3fdaa45a
AH		 7404 (opaque_V2SF_type_node,
7405 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7406 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7407 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7408 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7409 endlink)))));
7410
7411 tree int_ftype_int_v2si_v2si
7412 = build_function_type
7413 (integer_type_node,
7414 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7415 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7416 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7417 endlink))));
7418
7419 tree int_ftype_int_v2sf_v2sf
7420 = build_function_type
7421 (integer_type_node,
7422 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7423 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7424 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7425 endlink))));
7426
7427 tree void_ftype_v2si_puint_int
7428 = build_function_type (void_type_node,
3fdaa45a 7429 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7430 tree_cons (NULL_TREE, puint_type_node,
7431 tree_cons (NULL_TREE,
7432 integer_type_node,
7433 endlink))));
7434
7435 tree void_ftype_v2si_puint_char
7436 = build_function_type (void_type_node,
3fdaa45a 7437 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7438 tree_cons (NULL_TREE, puint_type_node,
7439 tree_cons (NULL_TREE,
7440 char_type_node,
7441 endlink))));
7442
7443 tree void_ftype_v2si_pv2si_int
7444 = build_function_type (void_type_node,
3fdaa45a 7445 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7446 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7447 tree_cons (NULL_TREE,
7448 integer_type_node,
7449 endlink))));
7450
7451 tree void_ftype_v2si_pv2si_char
7452 = build_function_type (void_type_node,
3fdaa45a 7453 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7454 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7455 tree_cons (NULL_TREE,
7456 char_type_node,
7457 endlink))));
7458
7459 tree void_ftype_int
7460 = build_function_type (void_type_node,
7461 tree_cons (NULL_TREE, integer_type_node, endlink));
7462
7463 tree int_ftype_void
36e8d515 7464 = build_function_type (integer_type_node, endlink);
a3170dc6
AH		 7465
7466 tree v2si_ftype_pv2si_int
3fdaa45a 7467 = build_function_type (opaque_V2SI_type_node,
6035d635 7468 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7469 tree_cons (NULL_TREE, integer_type_node,
7470 endlink)));
7471
7472 tree v2si_ftype_puint_int
3fdaa45a 7473 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7474 tree_cons (NULL_TREE, puint_type_node,
7475 tree_cons (NULL_TREE, integer_type_node,
7476 endlink)));
7477
7478 tree v2si_ftype_pushort_int
3fdaa45a 7479 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7480 tree_cons (NULL_TREE, pushort_type_node,
7481 tree_cons (NULL_TREE, integer_type_node,
7482 endlink)));
7483
00332c9f
AH		 7484 tree v2si_ftype_signed_char
7485 = build_function_type (opaque_V2SI_type_node,
7486 tree_cons (NULL_TREE, signed_char_type_node,
7487 endlink));
7488
a3170dc6
AH		 7489 /* The initialization of the simple binary and unary builtins is
7490 done in rs6000_common_init_builtins, but we have to enable the
7491 mask bits here manually because we have run out of `target_flags'
7492 bits. We really need to redesign this mask business. */
7493
7494 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7495 ARRAY_SIZE (bdesc_2arg),
7496 SPE_BUILTIN_EVADDW,
7497 SPE_BUILTIN_EVXOR);
7498 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7499 ARRAY_SIZE (bdesc_1arg),
7500 SPE_BUILTIN_EVABS,
7501 SPE_BUILTIN_EVSUBFUSIAAW);
7502 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7503 ARRAY_SIZE (bdesc_spe_predicates),
7504 SPE_BUILTIN_EVCMPEQ,
7505 SPE_BUILTIN_EVFSTSTLT);
7506 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7507 ARRAY_SIZE (bdesc_spe_evsel),
7508 SPE_BUILTIN_EVSEL_CMPGTS,
7509 SPE_BUILTIN_EVSEL_FSTSTEQ);
7510
36252949
AH		 7511 (*lang_hooks.decls.pushdecl)
7512 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7513 opaque_V2SI_type_node));
7514
a3170dc6 7515 /* Initialize irregular SPE builtins. */
f676971a 7516
a3170dc6
AH		 7517 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7518 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7519 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7520 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7521 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7522 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7523 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7524 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7525 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7526 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7527 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7528 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7529 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7530 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7531 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7532 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
00332c9f
AH		 7533 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7534 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
a3170dc6
AH		 7535
7536 /* Loads. */
7537 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7538 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7539 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7540 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7541 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7542 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7543 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7544 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7545 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7546 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7547 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7548 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7549 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7550 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7551 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7552 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7553 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7554 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7555 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7556 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7557 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7558 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7559
7560 /* Predicates. */
7561 d = (struct builtin_description *) bdesc_spe_predicates;
7562 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7563 {
7564 tree type;
7565
7566 switch (insn_data[d->icode].operand[1].mode)
7567 {
7568 case V2SImode:
7569 type = int_ftype_int_v2si_v2si;
7570 break;
7571 case V2SFmode:
7572 type = int_ftype_int_v2sf_v2sf;
7573 break;
7574 default:
37409796 7575 gcc_unreachable ();
a3170dc6
AH		 7576 }
7577
7578 def_builtin (d->mask, d->name, type, d->code);
7579 }
7580
7581 /* Evsel predicates. */
7582 d = (struct builtin_description *) bdesc_spe_evsel;
7583 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7584 {
7585 tree type;
7586
7587 switch (insn_data[d->icode].operand[1].mode)
7588 {
7589 case V2SImode:
7590 type = v2si_ftype_4_v2si;
7591 break;
7592 case V2SFmode:
7593 type = v2sf_ftype_4_v2sf;
7594 break;
7595 default:
37409796 7596 gcc_unreachable ();
a3170dc6
AH		 7597 }
7598
7599 def_builtin (d->mask, d->name, type, d->code);
7600 }
7601}
7602
7603static void
863d938c 7604altivec_init_builtins (void)
a3170dc6
AH		 7605{
7606 struct builtin_description *d;
7607 struct builtin_description_predicates *dp;
7608 size_t i;
7609 tree pfloat_type_node = build_pointer_type (float_type_node);
7610 tree pint_type_node = build_pointer_type (integer_type_node);
7611 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7612 tree pchar_type_node = build_pointer_type (char_type_node);
7613
7614 tree pvoid_type_node = build_pointer_type (void_type_node);
7615
0dbc3651
ZW		 7616 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7617 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7618 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7619 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7620
7621 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7622
58646b77
PB		 7623 tree int_ftype_opaque
7624 = build_function_type_list (integer_type_node,
7625 opaque_V4SI_type_node, NULL_TREE);
7626
7627 tree opaque_ftype_opaque_int
7628 = build_function_type_list (opaque_V4SI_type_node,
7629 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
7630 tree opaque_ftype_opaque_opaque_int
7631 = build_function_type_list (opaque_V4SI_type_node,
7632 opaque_V4SI_type_node, opaque_V4SI_type_node,
7633 integer_type_node, NULL_TREE);
7634 tree int_ftype_int_opaque_opaque
7635 = build_function_type_list (integer_type_node,
7636 integer_type_node, opaque_V4SI_type_node,
7637 opaque_V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7638 tree int_ftype_int_v4si_v4si
7639 = build_function_type_list (integer_type_node,
7640 integer_type_node, V4SI_type_node,
7641 V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7642 tree v4sf_ftype_pcfloat
7643 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
a3170dc6 7644 tree void_ftype_pfloat_v4sf
b4de2f7d 7645 = build_function_type_list (void_type_node,
a3170dc6 7646 pfloat_type_node, V4SF_type_node, NULL_TREE);
0dbc3651
ZW		 7647 tree v4si_ftype_pcint
7648 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7649 tree void_ftype_pint_v4si
b4de2f7d
AH		 7650 = build_function_type_list (void_type_node,
7651 pint_type_node, V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7652 tree v8hi_ftype_pcshort
7653 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
f18c054f 7654 tree void_ftype_pshort_v8hi
b4de2f7d
AH		 7655 = build_function_type_list (void_type_node,
7656 pshort_type_node, V8HI_type_node, NULL_TREE);
0dbc3651
ZW		 7657 tree v16qi_ftype_pcchar
7658 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
f18c054f 7659 tree void_ftype_pchar_v16qi
b4de2f7d
AH		 7660 = build_function_type_list (void_type_node,
7661 pchar_type_node, V16QI_type_node, NULL_TREE);
95385cbb 7662 tree void_ftype_v4si
b4de2f7d 7663 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7664 tree v8hi_ftype_void
7665 = build_function_type (V8HI_type_node, void_list_node);
7666 tree void_ftype_void
7667 = build_function_type (void_type_node, void_list_node);
e34b6648
JJ		 7668 tree void_ftype_int
7669 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
0dbc3651 7670
58646b77
PB		 7671 tree opaque_ftype_long_pcvoid
7672 = build_function_type_list (opaque_V4SI_type_node,
7673 long_integer_type_node, pcvoid_type_node, NULL_TREE);
b4a62fa0 7674 tree v16qi_ftype_long_pcvoid
a3170dc6 7675 = build_function_type_list (V16QI_type_node,
b4a62fa0
SB		 7676 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7677 tree v8hi_ftype_long_pcvoid
a3170dc6 7678 = build_function_type_list (V8HI_type_node,
b4a62fa0
SB		 7679 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7680 tree v4si_ftype_long_pcvoid
a3170dc6 7681 = build_function_type_list (V4SI_type_node,
b4a62fa0 7682 long_integer_type_node, pcvoid_type_node, NULL_TREE);
0dbc3651 7683
58646b77
PB		 7684 tree void_ftype_opaque_long_pvoid
7685 = build_function_type_list (void_type_node,
7686 opaque_V4SI_type_node, long_integer_type_node,
7687 pvoid_type_node, NULL_TREE);
b4a62fa0 7688 tree void_ftype_v4si_long_pvoid
b4de2f7d 7689 = build_function_type_list (void_type_node,
b4a62fa0 7690 V4SI_type_node, long_integer_type_node,
b4de2f7d 7691 pvoid_type_node, NULL_TREE);
b4a62fa0 7692 tree void_ftype_v16qi_long_pvoid
b4de2f7d 7693 = build_function_type_list (void_type_node,
b4a62fa0 7694 V16QI_type_node, long_integer_type_node,
b4de2f7d 7695 pvoid_type_node, NULL_TREE);
b4a62fa0 7696 tree void_ftype_v8hi_long_pvoid
b4de2f7d 7697 = build_function_type_list (void_type_node,
b4a62fa0 7698 V8HI_type_node, long_integer_type_node,
b4de2f7d 7699 pvoid_type_node, NULL_TREE);
a3170dc6
AH		 7700 tree int_ftype_int_v8hi_v8hi
7701 = build_function_type_list (integer_type_node,
7702 integer_type_node, V8HI_type_node,
7703 V8HI_type_node, NULL_TREE);
7704 tree int_ftype_int_v16qi_v16qi
7705 = build_function_type_list (integer_type_node,
7706 integer_type_node, V16QI_type_node,
7707 V16QI_type_node, NULL_TREE);
7708 tree int_ftype_int_v4sf_v4sf
7709 = build_function_type_list (integer_type_node,
7710 integer_type_node, V4SF_type_node,
7711 V4SF_type_node, NULL_TREE);
7712 tree v4si_ftype_v4si
7713 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7714 tree v8hi_ftype_v8hi
7715 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7716 tree v16qi_ftype_v16qi
7717 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7718 tree v4sf_ftype_v4sf
7719 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8bb418a3 7720 tree void_ftype_pcvoid_int_int
a3170dc6 7721 = build_function_type_list (void_type_node,
0dbc3651 7722 pcvoid_type_node, integer_type_node,
8bb418a3 7723 integer_type_node, NULL_TREE);
8bb418a3 7724
0dbc3651
ZW		 7725 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7726 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7727 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7728 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7729 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7730 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7731 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7732 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7733 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7734 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7735 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7736 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7737 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7738 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7739 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7740 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
a3170dc6
AH		 7741 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7742 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7743 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
e34b6648 7744 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
b4a62fa0
SB		 7745 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7746 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7747 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7748 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7749 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7750 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7751 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7752 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7753 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7754 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7755 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7756 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
58646b77
PB		 7757 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
7758 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
7759 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
7760 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
7761 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
7762 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
7763 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
7764 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
7765 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
7766 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
7767 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
7768 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
7769 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
7770 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
7771
7772 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
7773
7774 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
7775 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
7776 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
7777 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
7778 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
7779 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
7780 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
7781 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
7782 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
7783 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8bb418a3 7784
a3170dc6
AH		 7785 /* Add the DST variants. */
7786 d = (struct builtin_description *) bdesc_dst;
7787 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8bb418a3 7788 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
a3170dc6
AH		 7789
7790 /* Initialize the predicates. */
7791 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7792 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7793 {
7794 enum machine_mode mode1;
7795 tree type;
58646b77
PB		 7796 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7797 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
a3170dc6 7798
58646b77
PB		 7799 if (is_overloaded)
7800 mode1 = VOIDmode;
7801 else
7802 mode1 = insn_data[dp->icode].operand[1].mode;
a3170dc6
AH		 7803
7804 switch (mode1)
7805 {
58646b77
PB		 7806 case VOIDmode:
7807 type = int_ftype_int_opaque_opaque;
7808 break;
a3170dc6
AH		 7809 case V4SImode:
7810 type = int_ftype_int_v4si_v4si;
7811 break;
7812 case V8HImode:
7813 type = int_ftype_int_v8hi_v8hi;
7814 break;
7815 case V16QImode:
7816 type = int_ftype_int_v16qi_v16qi;
7817 break;
7818 case V4SFmode:
7819 type = int_ftype_int_v4sf_v4sf;
7820 break;
7821 default:
37409796 7822 gcc_unreachable ();
a3170dc6 7823 }
f676971a 7824
a3170dc6
AH		 7825 def_builtin (dp->mask, dp->name, type, dp->code);
7826 }
7827
7828 /* Initialize the abs* operators. */
7829 d = (struct builtin_description *) bdesc_abs;
7830 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7831 {
7832 enum machine_mode mode0;
7833 tree type;
7834
7835 mode0 = insn_data[d->icode].operand[0].mode;
7836
7837 switch (mode0)
7838 {
7839 case V4SImode:
7840 type = v4si_ftype_v4si;
7841 break;
7842 case V8HImode:
7843 type = v8hi_ftype_v8hi;
7844 break;
7845 case V16QImode:
7846 type = v16qi_ftype_v16qi;
7847 break;
7848 case V4SFmode:
7849 type = v4sf_ftype_v4sf;
7850 break;
7851 default:
37409796 7852 gcc_unreachable ();
a3170dc6 7853 }
f676971a 7854
a3170dc6
AH		 7855 def_builtin (d->mask, d->name, type, d->code);
7856 }
7ccf35ed 7857
13c62176
DN		 7858 if (TARGET_ALTIVEC)
7859 {
7860 tree decl;
7861
7862 /* Initialize target builtin that implements
7863 targetm.vectorize.builtin_mask_for_load. */
7864
7865 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8bb46326
DN		 7866 v16qi_ftype_long_pcvoid,
7867 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7868 BUILT_IN_MD, NULL,
7869 tree_cons (get_identifier ("const"),
7870 NULL_TREE, NULL_TREE));
13c62176
DN		 7871 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7872 altivec_builtin_mask_for_load = decl;
13c62176 7873 }
a3170dc6
AH		 7874}
7875
7876static void
863d938c 7877rs6000_common_init_builtins (void)
a3170dc6
AH		 7878{
7879 struct builtin_description *d;
7880 size_t i;
7881
7882 tree v4sf_ftype_v4sf_v4sf_v16qi
7883 = build_function_type_list (V4SF_type_node,
7884 V4SF_type_node, V4SF_type_node,
7885 V16QI_type_node, NULL_TREE);
7886 tree v4si_ftype_v4si_v4si_v16qi
7887 = build_function_type_list (V4SI_type_node,
7888 V4SI_type_node, V4SI_type_node,
7889 V16QI_type_node, NULL_TREE);
7890 tree v8hi_ftype_v8hi_v8hi_v16qi
7891 = build_function_type_list (V8HI_type_node,
7892 V8HI_type_node, V8HI_type_node,
7893 V16QI_type_node, NULL_TREE);
7894 tree v16qi_ftype_v16qi_v16qi_v16qi
7895 = build_function_type_list (V16QI_type_node,
7896 V16QI_type_node, V16QI_type_node,
7897 V16QI_type_node, NULL_TREE);
b9e4e5d1
ZL		 7898 tree v4si_ftype_int
7899 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7900 tree v8hi_ftype_int
7901 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7902 tree v16qi_ftype_int
7903 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
a3170dc6
AH		 7904 tree v8hi_ftype_v16qi
7905 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7906 tree v4sf_ftype_v4sf
7907 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7908
7909 tree v2si_ftype_v2si_v2si
2abe3e28
AH		 7910 = build_function_type_list (opaque_V2SI_type_node,
7911 opaque_V2SI_type_node,
7912 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7913
7914 tree v2sf_ftype_v2sf_v2sf
2abe3e28
AH		 7915 = build_function_type_list (opaque_V2SF_type_node,
7916 opaque_V2SF_type_node,
7917 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 7918
7919 tree v2si_ftype_int_int
2abe3e28 7920 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 7921 integer_type_node, integer_type_node,
7922 NULL_TREE);
7923
58646b77
PB		 7924 tree opaque_ftype_opaque
7925 = build_function_type_list (opaque_V4SI_type_node,
7926 opaque_V4SI_type_node, NULL_TREE);
7927
a3170dc6 7928 tree v2si_ftype_v2si
2abe3e28
AH		 7929 = build_function_type_list (opaque_V2SI_type_node,
7930 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7931
7932 tree v2sf_ftype_v2sf
2abe3e28
AH		 7933 = build_function_type_list (opaque_V2SF_type_node,
7934 opaque_V2SF_type_node, NULL_TREE);
f676971a 7935
a3170dc6 7936 tree v2sf_ftype_v2si
2abe3e28
AH		 7937 = build_function_type_list (opaque_V2SF_type_node,
7938 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7939
7940 tree v2si_ftype_v2sf
2abe3e28
AH		 7941 = build_function_type_list (opaque_V2SI_type_node,
7942 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 7943
7944 tree v2si_ftype_v2si_char
2abe3e28
AH		 7945 = build_function_type_list (opaque_V2SI_type_node,
7946 opaque_V2SI_type_node,
7947 char_type_node, NULL_TREE);
a3170dc6
AH		 7948
7949 tree v2si_ftype_int_char
2abe3e28 7950 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 7951 integer_type_node, char_type_node, NULL_TREE);
7952
7953 tree v2si_ftype_char
2abe3e28
AH		 7954 = build_function_type_list (opaque_V2SI_type_node,
7955 char_type_node, NULL_TREE);
a3170dc6
AH		 7956
7957 tree int_ftype_int_int
7958 = build_function_type_list (integer_type_node,
7959 integer_type_node, integer_type_node,
7960 NULL_TREE);
95385cbb 7961
58646b77
PB		 7962 tree opaque_ftype_opaque_opaque
7963 = build_function_type_list (opaque_V4SI_type_node,
7964 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
0ac081f6 7965 tree v4si_ftype_v4si_v4si
b4de2f7d
AH		 7966 = build_function_type_list (V4SI_type_node,
7967 V4SI_type_node, V4SI_type_node, NULL_TREE);
b9e4e5d1 7968 tree v4sf_ftype_v4si_int
b4de2f7d 7969 = build_function_type_list (V4SF_type_node,
b9e4e5d1
ZL		 7970 V4SI_type_node, integer_type_node, NULL_TREE);
7971 tree v4si_ftype_v4sf_int
b4de2f7d 7972 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 7973 V4SF_type_node, integer_type_node, NULL_TREE);
7974 tree v4si_ftype_v4si_int
b4de2f7d 7975 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 7976 V4SI_type_node, integer_type_node, NULL_TREE);
7977 tree v8hi_ftype_v8hi_int
b4de2f7d 7978 = build_function_type_list (V8HI_type_node,
b9e4e5d1
ZL		 7979 V8HI_type_node, integer_type_node, NULL_TREE);
7980 tree v16qi_ftype_v16qi_int
b4de2f7d 7981 = build_function_type_list (V16QI_type_node,
b9e4e5d1
ZL		 7982 V16QI_type_node, integer_type_node, NULL_TREE);
7983 tree v16qi_ftype_v16qi_v16qi_int
b4de2f7d
AH		 7984 = build_function_type_list (V16QI_type_node,
7985 V16QI_type_node, V16QI_type_node,
b9e4e5d1
ZL		 7986 integer_type_node, NULL_TREE);
7987 tree v8hi_ftype_v8hi_v8hi_int
b4de2f7d
AH		 7988 = build_function_type_list (V8HI_type_node,
7989 V8HI_type_node, V8HI_type_node,
b9e4e5d1
ZL		 7990 integer_type_node, NULL_TREE);
7991 tree v4si_ftype_v4si_v4si_int
b4de2f7d
AH		 7992 = build_function_type_list (V4SI_type_node,
7993 V4SI_type_node, V4SI_type_node,
b9e4e5d1
ZL		 7994 integer_type_node, NULL_TREE);
7995 tree v4sf_ftype_v4sf_v4sf_int
b4de2f7d
AH		 7996 = build_function_type_list (V4SF_type_node,
7997 V4SF_type_node, V4SF_type_node,
b9e4e5d1 7998 integer_type_node, NULL_TREE);
0ac081f6 7999 tree v4sf_ftype_v4sf_v4sf
b4de2f7d
AH		 8000 = build_function_type_list (V4SF_type_node,
8001 V4SF_type_node, V4SF_type_node, NULL_TREE);
58646b77
PB		 8002 tree opaque_ftype_opaque_opaque_opaque
8003 = build_function_type_list (opaque_V4SI_type_node,
8004 opaque_V4SI_type_node, opaque_V4SI_type_node,
8005 opaque_V4SI_type_node, NULL_TREE);
617e0e1d 8006 tree v4sf_ftype_v4sf_v4sf_v4si
b4de2f7d
AH		 8007 = build_function_type_list (V4SF_type_node,
8008 V4SF_type_node, V4SF_type_node,
8009 V4SI_type_node, NULL_TREE);
2212663f 8010 tree v4sf_ftype_v4sf_v4sf_v4sf
b4de2f7d
AH		 8011 = build_function_type_list (V4SF_type_node,
8012 V4SF_type_node, V4SF_type_node,
8013 V4SF_type_node, NULL_TREE);
f676971a 8014 tree v4si_ftype_v4si_v4si_v4si
b4de2f7d
AH		 8015 = build_function_type_list (V4SI_type_node,
8016 V4SI_type_node, V4SI_type_node,
8017 V4SI_type_node, NULL_TREE);
0ac081f6 8018 tree v8hi_ftype_v8hi_v8hi
b4de2f7d
AH		 8019 = build_function_type_list (V8HI_type_node,
8020 V8HI_type_node, V8HI_type_node, NULL_TREE);
2212663f 8021 tree v8hi_ftype_v8hi_v8hi_v8hi
b4de2f7d
AH		 8022 = build_function_type_list (V8HI_type_node,
8023 V8HI_type_node, V8HI_type_node,
8024 V8HI_type_node, NULL_TREE);
c4ad648e 8025 tree v4si_ftype_v8hi_v8hi_v4si
b4de2f7d
AH		 8026 = build_function_type_list (V4SI_type_node,
8027 V8HI_type_node, V8HI_type_node,
8028 V4SI_type_node, NULL_TREE);
c4ad648e 8029 tree v4si_ftype_v16qi_v16qi_v4si
b4de2f7d
AH		 8030 = build_function_type_list (V4SI_type_node,
8031 V16QI_type_node, V16QI_type_node,
8032 V4SI_type_node, NULL_TREE);
0ac081f6 8033 tree v16qi_ftype_v16qi_v16qi
b4de2f7d
AH		 8034 = build_function_type_list (V16QI_type_node,
8035 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8036 tree v4si_ftype_v4sf_v4sf
b4de2f7d
AH		 8037 = build_function_type_list (V4SI_type_node,
8038 V4SF_type_node, V4SF_type_node, NULL_TREE);
0ac081f6 8039 tree v8hi_ftype_v16qi_v16qi
b4de2f7d
AH		 8040 = build_function_type_list (V8HI_type_node,
8041 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8042 tree v4si_ftype_v8hi_v8hi
b4de2f7d
AH		 8043 = build_function_type_list (V4SI_type_node,
8044 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 8045 tree v8hi_ftype_v4si_v4si
b4de2f7d
AH		 8046 = build_function_type_list (V8HI_type_node,
8047 V4SI_type_node, V4SI_type_node, NULL_TREE);
0ac081f6 8048 tree v16qi_ftype_v8hi_v8hi
b4de2f7d
AH		 8049 = build_function_type_list (V16QI_type_node,
8050 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 8051 tree v4si_ftype_v16qi_v4si
b4de2f7d
AH		 8052 = build_function_type_list (V4SI_type_node,
8053 V16QI_type_node, V4SI_type_node, NULL_TREE);
fa066a23 8054 tree v4si_ftype_v16qi_v16qi
b4de2f7d
AH		 8055 = build_function_type_list (V4SI_type_node,
8056 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8057 tree v4si_ftype_v8hi_v4si
b4de2f7d
AH		 8058 = build_function_type_list (V4SI_type_node,
8059 V8HI_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 8060 tree v4si_ftype_v8hi
8061 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8062 tree int_ftype_v4si_v4si
8063 = build_function_type_list (integer_type_node,
8064 V4SI_type_node, V4SI_type_node, NULL_TREE);
8065 tree int_ftype_v4sf_v4sf
8066 = build_function_type_list (integer_type_node,
8067 V4SF_type_node, V4SF_type_node, NULL_TREE);
8068 tree int_ftype_v16qi_v16qi
8069 = build_function_type_list (integer_type_node,
8070 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8071 tree int_ftype_v8hi_v8hi
b4de2f7d
AH		 8072 = build_function_type_list (integer_type_node,
8073 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 8074
6f317ef3 8075 /* Add the simple ternary operators. */
2212663f 8076 d = (struct builtin_description *) bdesc_3arg;
ca7558fc 8077 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
2212663f 8078 {
2212663f
DB		 8079 enum machine_mode mode0, mode1, mode2, mode3;
8080 tree type;
58646b77
PB		 8081 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8082 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
2212663f 8083
58646b77
PB		 8084 if (is_overloaded)
8085 {
8086 mode0 = VOIDmode;
8087 mode1 = VOIDmode;
8088 mode2 = VOIDmode;
8089 mode3 = VOIDmode;
8090 }
8091 else
8092 {
8093 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8094 continue;
f676971a 8095
58646b77
PB		 8096 mode0 = insn_data[d->icode].operand[0].mode;
8097 mode1 = insn_data[d->icode].operand[1].mode;
8098 mode2 = insn_data[d->icode].operand[2].mode;
8099 mode3 = insn_data[d->icode].operand[3].mode;
8100 }
8101
2212663f
DB		 8102 /* When all four are of the same mode. */
8103 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8104 {
8105 switch (mode0)
8106 {
58646b77
PB		 8107 case VOIDmode:
8108 type = opaque_ftype_opaque_opaque_opaque;
8109 break;
617e0e1d
DB		 8110 case V4SImode:
8111 type = v4si_ftype_v4si_v4si_v4si;
8112 break;
2212663f
DB		 8113 case V4SFmode:
8114 type = v4sf_ftype_v4sf_v4sf_v4sf;
8115 break;
8116 case V8HImode:
8117 type = v8hi_ftype_v8hi_v8hi_v8hi;
f676971a 8118 break;
2212663f
DB		 8119 case V16QImode:
8120 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 8121 break;
2212663f 8122 default:
37409796 8123 gcc_unreachable ();
2212663f
DB		 8124 }
8125 }
8126 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
c4ad648e 8127 {
2212663f
DB		 8128 switch (mode0)
8129 {
8130 case V4SImode:
8131 type = v4si_ftype_v4si_v4si_v16qi;
8132 break;
8133 case V4SFmode:
8134 type = v4sf_ftype_v4sf_v4sf_v16qi;
8135 break;
8136 case V8HImode:
8137 type = v8hi_ftype_v8hi_v8hi_v16qi;
f676971a 8138 break;
2212663f
DB		 8139 case V16QImode:
8140 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 8141 break;
2212663f 8142 default:
37409796 8143 gcc_unreachable ();
2212663f
DB		 8144 }
8145 }
f676971a 8146 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
2212663f 8147 && mode3 == V4SImode)
24408032 8148 type = v4si_ftype_v16qi_v16qi_v4si;
f676971a 8149 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
2212663f 8150 && mode3 == V4SImode)
24408032 8151 type = v4si_ftype_v8hi_v8hi_v4si;
f676971a 8152 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
617e0e1d 8153 && mode3 == V4SImode)
24408032
AH		 8154 type = v4sf_ftype_v4sf_v4sf_v4si;
8155
8156 /* vchar, vchar, vchar, 4 bit literal. */
8157 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8158 && mode3 == QImode)
b9e4e5d1 8159 type = v16qi_ftype_v16qi_v16qi_int;
24408032
AH		 8160
8161 /* vshort, vshort, vshort, 4 bit literal. */
8162 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8163 && mode3 == QImode)
b9e4e5d1 8164 type = v8hi_ftype_v8hi_v8hi_int;
24408032
AH		 8165
8166 /* vint, vint, vint, 4 bit literal. */
8167 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8168 && mode3 == QImode)
b9e4e5d1 8169 type = v4si_ftype_v4si_v4si_int;
24408032
AH		 8170
8171 /* vfloat, vfloat, vfloat, 4 bit literal. */
8172 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8173 && mode3 == QImode)
b9e4e5d1 8174 type = v4sf_ftype_v4sf_v4sf_int;
24408032 8175
2212663f 8176 else
37409796 8177 gcc_unreachable ();
2212663f
DB		 8178
8179 def_builtin (d->mask, d->name, type, d->code);
8180 }
8181
0ac081f6 8182 /* Add the simple binary operators. */
00b960c7 8183 d = (struct builtin_description *) bdesc_2arg;
ca7558fc 8184 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
0ac081f6
AH		 8185 {
8186 enum machine_mode mode0, mode1, mode2;
8187 tree type;
58646b77
PB		 8188 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8189 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
0ac081f6 8190
58646b77
PB		 8191 if (is_overloaded)
8192 {
8193 mode0 = VOIDmode;
8194 mode1 = VOIDmode;
8195 mode2 = VOIDmode;
8196 }
8197 else
8198 {
8199 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8200 continue;
f676971a 8201
58646b77
PB		 8202 mode0 = insn_data[d->icode].operand[0].mode;
8203 mode1 = insn_data[d->icode].operand[1].mode;
8204 mode2 = insn_data[d->icode].operand[2].mode;
8205 }
0ac081f6
AH		 8206
8207 /* When all three operands are of the same mode. */
8208 if (mode0 == mode1 && mode1 == mode2)
8209 {
8210 switch (mode0)
8211 {
58646b77
PB		 8212 case VOIDmode:
8213 type = opaque_ftype_opaque_opaque;
8214 break;
0ac081f6
AH		 8215 case V4SFmode:
8216 type = v4sf_ftype_v4sf_v4sf;
8217 break;
8218 case V4SImode:
8219 type = v4si_ftype_v4si_v4si;
8220 break;
8221 case V16QImode:
8222 type = v16qi_ftype_v16qi_v16qi;
8223 break;
8224 case V8HImode:
8225 type = v8hi_ftype_v8hi_v8hi;
8226 break;
a3170dc6
AH		 8227 case V2SImode:
8228 type = v2si_ftype_v2si_v2si;
8229 break;
8230 case V2SFmode:
8231 type = v2sf_ftype_v2sf_v2sf;
8232 break;
8233 case SImode:
8234 type = int_ftype_int_int;
8235 break;
0ac081f6 8236 default:
37409796 8237 gcc_unreachable ();
0ac081f6
AH		 8238 }
8239 }
8240
8241 /* A few other combos we really don't want to do manually. */
8242
8243 /* vint, vfloat, vfloat. */
8244 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8245 type = v4si_ftype_v4sf_v4sf;
8246
8247 /* vshort, vchar, vchar. */
8248 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8249 type = v8hi_ftype_v16qi_v16qi;
8250
8251 /* vint, vshort, vshort. */
8252 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8253 type = v4si_ftype_v8hi_v8hi;
8254
8255 /* vshort, vint, vint. */
8256 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8257 type = v8hi_ftype_v4si_v4si;
8258
8259 /* vchar, vshort, vshort. */
8260 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8261 type = v16qi_ftype_v8hi_v8hi;
8262
8263 /* vint, vchar, vint. */
8264 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8265 type = v4si_ftype_v16qi_v4si;
8266
fa066a23
AH		 8267 /* vint, vchar, vchar. */
8268 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8269 type = v4si_ftype_v16qi_v16qi;
8270
0ac081f6
AH		 8271 /* vint, vshort, vint. */
8272 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8273 type = v4si_ftype_v8hi_v4si;
f676971a 8274
2212663f
DB		 8275 /* vint, vint, 5 bit literal. */
8276 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8277 type = v4si_ftype_v4si_int;
f676971a 8278
2212663f
DB		 8279 /* vshort, vshort, 5 bit literal. */
8280 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
b9e4e5d1 8281 type = v8hi_ftype_v8hi_int;
f676971a 8282
2212663f
DB		 8283 /* vchar, vchar, 5 bit literal. */
8284 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
b9e4e5d1 8285 type = v16qi_ftype_v16qi_int;
0ac081f6 8286
617e0e1d
DB		 8287 /* vfloat, vint, 5 bit literal. */
8288 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8289 type = v4sf_ftype_v4si_int;
f676971a 8290
617e0e1d
DB		 8291 /* vint, vfloat, 5 bit literal. */
8292 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
b9e4e5d1 8293 type = v4si_ftype_v4sf_int;
617e0e1d 8294
a3170dc6
AH		 8295 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8296 type = v2si_ftype_int_int;
8297
8298 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8299 type = v2si_ftype_v2si_char;
8300
8301 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8302 type = v2si_ftype_int_char;
8303
37409796 8304 else
0ac081f6 8305 {
37409796
NS		 8306 /* int, x, x. */
8307 gcc_assert (mode0 == SImode);
0ac081f6
AH		 8308 switch (mode1)
8309 {
8310 case V4SImode:
8311 type = int_ftype_v4si_v4si;
8312 break;
8313 case V4SFmode:
8314 type = int_ftype_v4sf_v4sf;
8315 break;
8316 case V16QImode:
8317 type = int_ftype_v16qi_v16qi;
8318 break;
8319 case V8HImode:
8320 type = int_ftype_v8hi_v8hi;
8321 break;
8322 default:
37409796 8323 gcc_unreachable ();
0ac081f6
AH		 8324 }
8325 }
8326
2212663f
DB		 8327 def_builtin (d->mask, d->name, type, d->code);
8328 }
24408032 8329
2212663f
DB		 8330 /* Add the simple unary operators. */
8331 d = (struct builtin_description *) bdesc_1arg;
ca7558fc 8332 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
2212663f
DB		 8333 {
8334 enum machine_mode mode0, mode1;
8335 tree type;
58646b77
PB		 8336 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8337 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8338
8339 if (is_overloaded)
8340 {
8341 mode0 = VOIDmode;
8342 mode1 = VOIDmode;
8343 }
8344 else
8345 {
8346 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8347 continue;
8348
8349 mode0 = insn_data[d->icode].operand[0].mode;
8350 mode1 = insn_data[d->icode].operand[1].mode;
8351 }
2212663f
DB		 8352
8353 if (mode0 == V4SImode && mode1 == QImode)
c4ad648e 8354 type = v4si_ftype_int;
2212663f 8355 else if (mode0 == V8HImode && mode1 == QImode)
c4ad648e 8356 type = v8hi_ftype_int;
2212663f 8357 else if (mode0 == V16QImode && mode1 == QImode)
c4ad648e 8358 type = v16qi_ftype_int;
58646b77
PB		 8359 else if (mode0 == VOIDmode && mode1 == VOIDmode)
8360 type = opaque_ftype_opaque;
617e0e1d
DB		 8361 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8362 type = v4sf_ftype_v4sf;
20e26713
AH		 8363 else if (mode0 == V8HImode && mode1 == V16QImode)
8364 type = v8hi_ftype_v16qi;
8365 else if (mode0 == V4SImode && mode1 == V8HImode)
8366 type = v4si_ftype_v8hi;
a3170dc6
AH		 8367 else if (mode0 == V2SImode && mode1 == V2SImode)
8368 type = v2si_ftype_v2si;
8369 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8370 type = v2sf_ftype_v2sf;
8371 else if (mode0 == V2SFmode && mode1 == V2SImode)
8372 type = v2sf_ftype_v2si;
8373 else if (mode0 == V2SImode && mode1 == V2SFmode)
8374 type = v2si_ftype_v2sf;
8375 else if (mode0 == V2SImode && mode1 == QImode)
8376 type = v2si_ftype_char;
2212663f 8377 else
37409796 8378 gcc_unreachable ();
2212663f 8379
0ac081f6
AH		 8380 def_builtin (d->mask, d->name, type, d->code);
8381 }
8382}
8383
c15c90bb
ZW		 8384static void
8385rs6000_init_libfuncs (void)
8386{
8387 if (!TARGET_HARD_FLOAT)
8388 return;
8389
c9034561 8390 if (DEFAULT_ABI != ABI_V4)
c15c90bb 8391 {
c9034561 8392 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
c15c90bb 8393 {
c9034561 8394 /* AIX library routines for float->int conversion. */
85363ca0
ZW		 8395 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8396 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
4274207b
DE		 8397 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8398 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
c15c90bb
ZW		 8399 }
8400
98c41d98
DE		 8401 /* AIX/Darwin/64-bit Linux quad floating point routines. */
8402 if (!TARGET_XL_COMPAT)
8403 {
8404 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8405 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8406 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8407 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
8408 }
8409 else
8410 {
8411 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8412 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8413 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8414 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8415 }
c15c90bb 8416 }
c9034561 8417 else
c15c90bb 8418 {
c9034561 8419 /* 32-bit SVR4 quad floating point routines. */
c15c90bb
ZW		 8420
8421 set_optab_libfunc (add_optab, TFmode, "_q_add");
8422 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8423 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8424 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8425 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8426 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8427 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8428
c9034561
ZW		 8429 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8430 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8431 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8432 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8433 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8434 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8435
85363ca0
ZW		 8436 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8437 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8438 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8439 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8440 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8441 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8442 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
c15c90bb
ZW		 8443 }
8444}
fba73eb1
DE		 8445
8446\f
8447/* Expand a block clear operation, and return 1 if successful. Return 0
8448 if we should let the compiler generate normal code.
8449
8450 operands[0] is the destination
8451 operands[1] is the length
8452 operands[2] is the alignment */
8453
8454int
8455expand_block_clear (rtx operands[])
8456{
8457 rtx orig_dest = operands[0];
8458 rtx bytes_rtx = operands[1];
8459 rtx align_rtx = operands[2];
5514620a
GK		 8460 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8461 HOST_WIDE_INT align;
8462 HOST_WIDE_INT bytes;
fba73eb1
DE		 8463 int offset;
8464 int clear_bytes;
5514620a 8465 int clear_step;
fba73eb1
DE		 8466
8467 /* If this is not a fixed size move, just call memcpy */
8468 if (! constp)
8469 return 0;
8470
37409796
NS		 8471 /* This must be a fixed size alignment */
8472 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
fba73eb1
DE		 8473 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8474
8475 /* Anything to clear? */
8476 bytes = INTVAL (bytes_rtx);
8477 if (bytes <= 0)
8478 return 1;
8479
5514620a
GK		 8480 /* Use the builtin memset after a point, to avoid huge code bloat.
8481 When optimize_size, avoid any significant code bloat; calling
8482 memset is about 4 instructions, so allow for one instruction to
8483 load zero and three to do clearing. */
8484 if (TARGET_ALTIVEC && align >= 128)
8485 clear_step = 16;
8486 else if (TARGET_POWERPC64 && align >= 32)
8487 clear_step = 8;
8488 else
8489 clear_step = 4;
fba73eb1 8490
5514620a
GK		 8491 if (optimize_size && bytes > 3 * clear_step)
8492 return 0;
8493 if (! optimize_size && bytes > 8 * clear_step)
fba73eb1
DE		 8494 return 0;
8495
8496 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8497 {
fba73eb1
DE		 8498 enum machine_mode mode = BLKmode;
8499 rtx dest;
f676971a 8500
5514620a
GK		 8501 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8502 {
8503 clear_bytes = 16;
8504 mode = V4SImode;
8505 }
8506 else if (bytes >= 8 && TARGET_POWERPC64
8507 /* 64-bit loads and stores require word-aligned
8508 displacements. */
8509 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
fba73eb1
DE		 8510 {
8511 clear_bytes = 8;
8512 mode = DImode;
fba73eb1 8513 }
5514620a 8514 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8515 { /* move 4 bytes */
8516 clear_bytes = 4;
8517 mode = SImode;
fba73eb1 8518 }
5514620a 8519 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8520 { /* move 2 bytes */
8521 clear_bytes = 2;
8522 mode = HImode;
fba73eb1
DE		 8523 }
8524 else /* move 1 byte at a time */
8525 {
8526 clear_bytes = 1;
8527 mode = QImode;
fba73eb1 8528 }
f676971a 8529
fba73eb1 8530 dest = adjust_address (orig_dest, mode, offset);
f676971a 8531
5514620a 8532 emit_move_insn (dest, CONST0_RTX (mode));
fba73eb1
DE		 8533 }
8534
8535 return 1;
8536}
8537
35aff10b 8538\f
7e69e155
MM		 8539/* Expand a block move operation, and return 1 if successful. Return 0
8540 if we should let the compiler generate normal code.
8541
8542 operands[0] is the destination
8543 operands[1] is the source
8544 operands[2] is the length
8545 operands[3] is the alignment */
8546
3933e0e1
MM		 8547#define MAX_MOVE_REG 4
8548
7e69e155 8549int
a2369ed3 8550expand_block_move (rtx operands[])
7e69e155 8551{
b6c9286a
MM		 8552 rtx orig_dest = operands[0];
8553 rtx orig_src = operands[1];
7e69e155 8554 rtx bytes_rtx = operands[2];
7e69e155 8555 rtx align_rtx = operands[3];
3933e0e1 8556 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
5ee95df6 8557 int align;
3933e0e1
MM		 8558 int bytes;
8559 int offset;
7e69e155 8560 int move_bytes;
cabfd258
GK		 8561 rtx stores[MAX_MOVE_REG];
8562 int num_reg = 0;
7e69e155 8563
3933e0e1 8564 /* If this is not a fixed size move, just call memcpy */
cc0d9ba8 8565 if (! constp)
3933e0e1
MM		 8566 return 0;
8567
37409796
NS		 8568 /* This must be a fixed size alignment */
8569 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
fba73eb1 8570 align = INTVAL (align_rtx) * BITS_PER_UNIT;
5ee95df6 8571
7e69e155 8572 /* Anything to move? */
3933e0e1
MM		 8573 bytes = INTVAL (bytes_rtx);
8574 if (bytes <= 0)
7e69e155
MM		 8575 return 1;
8576
ea9982a8 8577 /* store_one_arg depends on expand_block_move to handle at least the size of
f676971a 8578 reg_parm_stack_space. */
ea9982a8 8579 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7e69e155
MM		 8580 return 0;
8581
cabfd258 8582 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7e69e155 8583 {
cabfd258 8584 union {
70128ad9 8585 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
a2369ed3 8586 rtx (*mov) (rtx, rtx);
cabfd258
GK		 8587 } gen_func;
8588 enum machine_mode mode = BLKmode;
8589 rtx src, dest;
f676971a 8590
5514620a
GK		 8591 /* Altivec first, since it will be faster than a string move
8592 when it applies, and usually not significantly larger. */
8593 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8594 {
8595 move_bytes = 16;
8596 mode = V4SImode;
8597 gen_func.mov = gen_movv4si;
8598 }
8599 else if (TARGET_STRING
cabfd258
GK		 8600 && bytes > 24 /* move up to 32 bytes at a time */
8601 && ! fixed_regs[5]
8602 && ! fixed_regs[6]
8603 && ! fixed_regs[7]
8604 && ! fixed_regs[8]
8605 && ! fixed_regs[9]
8606 && ! fixed_regs[10]
8607 && ! fixed_regs[11]
8608 && ! fixed_regs[12])
7e69e155 8609 {
cabfd258 8610 move_bytes = (bytes > 32) ? 32 : bytes;
70128ad9 8611 gen_func.movmemsi = gen_movmemsi_8reg;
cabfd258
GK		 8612 }
8613 else if (TARGET_STRING
8614 && bytes > 16 /* move up to 24 bytes at a time */
8615 && ! fixed_regs[5]
8616 && ! fixed_regs[6]
8617 && ! fixed_regs[7]
8618 && ! fixed_regs[8]
8619 && ! fixed_regs[9]
8620 && ! fixed_regs[10])
8621 {
8622 move_bytes = (bytes > 24) ? 24 : bytes;
70128ad9 8623 gen_func.movmemsi = gen_movmemsi_6reg;
cabfd258
GK		 8624 }
8625 else if (TARGET_STRING
8626 && bytes > 8 /* move up to 16 bytes at a time */
8627 && ! fixed_regs[5]
8628 && ! fixed_regs[6]
8629 && ! fixed_regs[7]
8630 && ! fixed_regs[8])
8631 {
8632 move_bytes = (bytes > 16) ? 16 : bytes;
70128ad9 8633 gen_func.movmemsi = gen_movmemsi_4reg;
cabfd258
GK		 8634 }
8635 else if (bytes >= 8 && TARGET_POWERPC64
8636 /* 64-bit loads and stores require word-aligned
8637 displacements. */
fba73eb1 8638 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
cabfd258
GK		 8639 {
8640 move_bytes = 8;
8641 mode = DImode;
8642 gen_func.mov = gen_movdi;
8643 }
8644 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8645 { /* move up to 8 bytes at a time */
8646 move_bytes = (bytes > 8) ? 8 : bytes;
70128ad9 8647 gen_func.movmemsi = gen_movmemsi_2reg;
cabfd258 8648 }
cd7d9ca4 8649 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
cabfd258
GK		 8650 { /* move 4 bytes */
8651 move_bytes = 4;
8652 mode = SImode;
8653 gen_func.mov = gen_movsi;
8654 }
cd7d9ca4 8655 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
cabfd258
GK		 8656 { /* move 2 bytes */
8657 move_bytes = 2;
8658 mode = HImode;
8659 gen_func.mov = gen_movhi;
8660 }
8661 else if (TARGET_STRING && bytes > 1)
8662 { /* move up to 4 bytes at a time */
8663 move_bytes = (bytes > 4) ? 4 : bytes;
70128ad9 8664 gen_func.movmemsi = gen_movmemsi_1reg;
cabfd258
GK		 8665 }
8666 else /* move 1 byte at a time */
8667 {
8668 move_bytes = 1;
8669 mode = QImode;
8670 gen_func.mov = gen_movqi;
8671 }
f676971a 8672
cabfd258
GK		 8673 src = adjust_address (orig_src, mode, offset);
8674 dest = adjust_address (orig_dest, mode, offset);
f676971a
EC		 8675
8676 if (mode != BLKmode)
cabfd258
GK		 8677 {
8678 rtx tmp_reg = gen_reg_rtx (mode);
f676971a 8679
cabfd258
GK		 8680 emit_insn ((*gen_func.mov) (tmp_reg, src));
8681 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
4c64a852 8682 }
3933e0e1 8683
cabfd258
GK		 8684 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8685 {
8686 int i;
8687 for (i = 0; i < num_reg; i++)
8688 emit_insn (stores[i]);
8689 num_reg = 0;
8690 }
35aff10b 8691
cabfd258 8692 if (mode == BLKmode)
7e69e155 8693 {
70128ad9 8694 /* Move the address into scratch registers. The movmemsi
cabfd258
GK		 8695 patterns require zero offset. */
8696 if (!REG_P (XEXP (src, 0)))
b6c9286a 8697 {
cabfd258
GK		 8698 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8699 src = replace_equiv_address (src, src_reg);
b6c9286a 8700 }
cabfd258 8701 set_mem_size (src, GEN_INT (move_bytes));
f676971a 8702
cabfd258 8703 if (!REG_P (XEXP (dest, 0)))
3933e0e1 8704 {
cabfd258
GK		 8705 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8706 dest = replace_equiv_address (dest, dest_reg);
7e69e155 8707 }
cabfd258 8708 set_mem_size (dest, GEN_INT (move_bytes));
f676971a 8709
70128ad9 8710 emit_insn ((*gen_func.movmemsi) (dest, src,
cabfd258
GK		 8711 GEN_INT (move_bytes & 31),
8712 align_rtx));
7e69e155 8713 }
7e69e155
MM		 8714 }
8715
8716 return 1;
8717}
8718
d62294f5 8719\f
9caa3eb2
DE		 8720/* Return a string to perform a load_multiple operation.
8721 operands[0] is the vector.
8722 operands[1] is the source address.
8723 operands[2] is the first destination register. */
8724
8725const char *
a2369ed3 8726rs6000_output_load_multiple (rtx operands[3])
9caa3eb2
DE		 8727{
8728 /* We have to handle the case where the pseudo used to contain the address
8729 is assigned to one of the output registers. */
8730 int i, j;
8731 int words = XVECLEN (operands[0], 0);
8732 rtx xop[10];
8733
8734 if (XVECLEN (operands[0], 0) == 1)
8735 return "{l|lwz} %2,0(%1)";
8736
8737 for (i = 0; i < words; i++)
8738 if (refers_to_regno_p (REGNO (operands[2]) + i,
8739 REGNO (operands[2]) + i + 1, operands[1], 0))
8740 {
8741 if (i == words-1)
8742 {
8743 xop[0] = GEN_INT (4 * (words-1));
8744 xop[1] = operands[1];
8745 xop[2] = operands[2];
8746 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8747 return "";
8748 }
8749 else if (i == 0)
8750 {
8751 xop[0] = GEN_INT (4 * (words-1));
8752 xop[1] = operands[1];
8753 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8754 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8755 return "";
8756 }
8757 else
8758 {
8759 for (j = 0; j < words; j++)
8760 if (j != i)
8761 {
8762 xop[0] = GEN_INT (j * 4);
8763 xop[1] = operands[1];
8764 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8765 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8766 }
8767 xop[0] = GEN_INT (i * 4);
8768 xop[1] = operands[1];
8769 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8770 return "";
8771 }
8772 }
8773
8774 return "{lsi|lswi} %2,%1,%N0";
8775}
8776
9878760c 8777\f
a4f6c312
SS		 8778/* A validation routine: say whether CODE, a condition code, and MODE
8779 match. The other alternatives either don't make sense or should
8780 never be generated. */
39a10a29 8781
48d72335 8782void
a2369ed3 8783validate_condition_mode (enum rtx_code code, enum machine_mode mode)
39a10a29 8784{
37409796
NS		 8785 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
8786 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
8787 && GET_MODE_CLASS (mode) == MODE_CC);
39a10a29
GK		 8788
8789 /* These don't make sense. */
37409796
NS		 8790 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
8791 || mode != CCUNSmode);
39a10a29 8792
37409796
NS		 8793 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
8794 || mode == CCUNSmode);
39a10a29 8795
37409796
NS		 8796 gcc_assert (mode == CCFPmode
8797 || (code != ORDERED && code != UNORDERED
8798 && code != UNEQ && code != LTGT
8799 && code != UNGT && code != UNLT
8800 && code != UNGE && code != UNLE));
f676971a
EC		 8801
8802 /* These should never be generated except for
bc9ec0e0 8803 flag_finite_math_only. */
37409796
NS		 8804 gcc_assert (mode != CCFPmode
8805 || flag_finite_math_only
8806 || (code != LE && code != GE
8807 && code != UNEQ && code != LTGT
8808 && code != UNGT && code != UNLT));
39a10a29
GK		 8809
8810 /* These are invalid; the information is not there. */
37409796 8811 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
39a10a29
GK		 8812}
8813
9878760c
RK		 8814\f
8815/* Return 1 if ANDOP is a mask that has no bits on that are not in the
8816 mask required to convert the result of a rotate insn into a shift
b1765bde 8817 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9878760c
RK		 8818
8819int
a2369ed3 8820includes_lshift_p (rtx shiftop, rtx andop)
9878760c 8821{
e2c953b6
DE		 8822 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8823
8824 shift_mask <<= INTVAL (shiftop);
9878760c 8825
b1765bde 8826 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9878760c
RK		 8827}
8828
8829/* Similar, but for right shift. */
8830
8831int
a2369ed3 8832includes_rshift_p (rtx shiftop, rtx andop)
9878760c 8833{
a7653a2c 8834 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9878760c
RK		 8835
8836 shift_mask >>= INTVAL (shiftop);
8837
b1765bde 8838 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
e2c953b6
DE		 8839}
8840
c5059423
AM		 8841/* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8842 to perform a left shift. It must have exactly SHIFTOP least
b6d08ca1 8843 significant 0's, then one or more 1's, then zero or more 0's. */
e2c953b6
DE		 8844
8845int
a2369ed3 8846includes_rldic_lshift_p (rtx shiftop, rtx andop)
e2c953b6 8847{
c5059423
AM		 8848 if (GET_CODE (andop) == CONST_INT)
8849 {
02071907 8850 HOST_WIDE_INT c, lsb, shift_mask;
e2c953b6 8851
c5059423 8852 c = INTVAL (andop);
02071907 8853 if (c == 0 || c == ~0)
c5059423 8854 return 0;
e2c953b6 8855
02071907 8856 shift_mask = ~0;
c5059423
AM		 8857 shift_mask <<= INTVAL (shiftop);
8858
b6d08ca1 8859 /* Find the least significant one bit. */
c5059423
AM		 8860 lsb = c & -c;
8861
8862 /* It must coincide with the LSB of the shift mask. */
8863 if (-lsb != shift_mask)
8864 return 0;
e2c953b6 8865
c5059423
AM		 8866 /* Invert to look for the next transition (if any). */
8867 c = ~c;
8868
8869 /* Remove the low group of ones (originally low group of zeros). */
8870 c &= -lsb;
8871
8872 /* Again find the lsb, and check we have all 1's above. */
8873 lsb = c & -c;
8874 return c == -lsb;
8875 }
8876 else if (GET_CODE (andop) == CONST_DOUBLE
8877 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8878 {
02071907
AM		 8879 HOST_WIDE_INT low, high, lsb;
8880 HOST_WIDE_INT shift_mask_low, shift_mask_high;
c5059423
AM		 8881
8882 low = CONST_DOUBLE_LOW (andop);
8883 if (HOST_BITS_PER_WIDE_INT < 64)
8884 high = CONST_DOUBLE_HIGH (andop);
8885
8886 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
02071907 8887 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
c5059423
AM		 8888 return 0;
8889
8890 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8891 {
02071907 8892 shift_mask_high = ~0;
c5059423
AM		 8893 if (INTVAL (shiftop) > 32)
8894 shift_mask_high <<= INTVAL (shiftop) - 32;
8895
8896 lsb = high & -high;
8897
8898 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8899 return 0;
8900
8901 high = ~high;
8902 high &= -lsb;
8903
8904 lsb = high & -high;
8905 return high == -lsb;
8906 }
8907
02071907 8908 shift_mask_low = ~0;
c5059423
AM		 8909 shift_mask_low <<= INTVAL (shiftop);
8910
8911 lsb = low & -low;
8912
8913 if (-lsb != shift_mask_low)
8914 return 0;
8915
8916 if (HOST_BITS_PER_WIDE_INT < 64)
8917 high = ~high;
8918 low = ~low;
8919 low &= -lsb;
8920
8921 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8922 {
8923 lsb = high & -high;
8924 return high == -lsb;
8925 }
8926
8927 lsb = low & -low;
8928 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8929 }
8930 else
8931 return 0;
8932}
e2c953b6 8933
c5059423
AM		 8934/* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8935 to perform a left shift. It must have SHIFTOP or more least
c1207243 8936 significant 0's, with the remainder of the word 1's. */
e2c953b6 8937
c5059423 8938int
a2369ed3 8939includes_rldicr_lshift_p (rtx shiftop, rtx andop)
c5059423 8940{
e2c953b6 8941 if (GET_CODE (andop) == CONST_INT)
c5059423 8942 {
02071907 8943 HOST_WIDE_INT c, lsb, shift_mask;
c5059423 8944
02071907 8945 shift_mask = ~0;
c5059423
AM		 8946 shift_mask <<= INTVAL (shiftop);
8947 c = INTVAL (andop);
8948
c1207243 8949 /* Find the least significant one bit. */
c5059423
AM		 8950 lsb = c & -c;
8951
8952 /* It must be covered by the shift mask.
a4f6c312 8953 This test also rejects c == 0. */
c5059423
AM		 8954 if ((lsb & shift_mask) == 0)
8955 return 0;
8956
8957 /* Check we have all 1's above the transition, and reject all 1's. */
8958 return c == -lsb && lsb != 1;
8959 }
8960 else if (GET_CODE (andop) == CONST_DOUBLE
8961 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8962 {
02071907 8963 HOST_WIDE_INT low, lsb, shift_mask_low;
c5059423
AM		 8964
8965 low = CONST_DOUBLE_LOW (andop);
8966
8967 if (HOST_BITS_PER_WIDE_INT < 64)
8968 {
02071907 8969 HOST_WIDE_INT high, shift_mask_high;
c5059423
AM		 8970
8971 high = CONST_DOUBLE_HIGH (andop);
8972
8973 if (low == 0)
8974 {
02071907 8975 shift_mask_high = ~0;
c5059423
AM		 8976 if (INTVAL (shiftop) > 32)
8977 shift_mask_high <<= INTVAL (shiftop) - 32;
8978
8979 lsb = high & -high;
8980
8981 if ((lsb & shift_mask_high) == 0)
8982 return 0;
8983
8984 return high == -lsb;
8985 }
8986 if (high != ~0)
8987 return 0;
8988 }
8989
02071907 8990 shift_mask_low = ~0;
c5059423
AM		 8991 shift_mask_low <<= INTVAL (shiftop);
8992
8993 lsb = low & -low;
8994
8995 if ((lsb & shift_mask_low) == 0)
8996 return 0;
8997
8998 return low == -lsb && lsb != 1;
8999 }
e2c953b6 9000 else
c5059423 9001 return 0;
9878760c 9002}
35068b43 9003
11ac38b2
DE		 9004/* Return 1 if operands will generate a valid arguments to rlwimi
9005instruction for insert with right shift in 64-bit mode. The mask may
9006not start on the first bit or stop on the last bit because wrap-around
9007effects of instruction do not correspond to semantics of RTL insn. */
9008
9009int
9010insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9011{
9012 if (INTVAL (startop) < 64
9013 && INTVAL (startop) > 32
9014 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9015 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9016 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9017 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9018 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9019 return 1;
9020
9021 return 0;
9022}
9023
35068b43 9024/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
90f81f99 9025 for lfq and stfq insns iff the registers are hard registers. */
35068b43
RK		 9026
9027int
a2369ed3 9028registers_ok_for_quad_peep (rtx reg1, rtx reg2)
35068b43
RK		 9029{
9030 /* We might have been passed a SUBREG. */
f676971a 9031 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
35068b43 9032 return 0;
f676971a 9033
90f81f99
AP		 9034 /* We might have been passed non floating point registers. */
9035 if (!FP_REGNO_P (REGNO (reg1))
9036 || !FP_REGNO_P (REGNO (reg2)))
9037 return 0;
35068b43
RK		 9038
9039 return (REGNO (reg1) == REGNO (reg2) - 1);
9040}
9041
a4f6c312
SS		 9042/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9043 addr1 and addr2 must be in consecutive memory locations
9044 (addr2 == addr1 + 8). */
35068b43
RK		 9045
9046int
90f81f99 9047mems_ok_for_quad_peep (rtx mem1, rtx mem2)
35068b43 9048{
90f81f99 9049 rtx addr1, addr2;
e2c953b6 9050 unsigned int reg1;
35068b43
RK		 9051 int offset1;
9052
90f81f99
AP		 9053 /* The mems cannot be volatile. */
9054 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9055 return 0;
f676971a 9056
90f81f99
AP		 9057 addr1 = XEXP (mem1, 0);
9058 addr2 = XEXP (mem2, 0);
9059
35068b43
RK		 9060 /* Extract an offset (if used) from the first addr. */
9061 if (GET_CODE (addr1) == PLUS)
9062 {
9063 /* If not a REG, return zero. */
9064 if (GET_CODE (XEXP (addr1, 0)) != REG)
9065 return 0;
9066 else
9067 {
c4ad648e 9068 reg1 = REGNO (XEXP (addr1, 0));
35068b43
RK		 9069 /* The offset must be constant! */
9070 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
c4ad648e
AM		 9071 return 0;
9072 offset1 = INTVAL (XEXP (addr1, 1));
35068b43
RK		 9073 }
9074 }
9075 else if (GET_CODE (addr1) != REG)
9076 return 0;
9077 else
9078 {
9079 reg1 = REGNO (addr1);
9080 /* This was a simple (mem (reg)) expression. Offset is 0. */
9081 offset1 = 0;
9082 }
9083
a2369ed3 9084 /* Make sure the second address is a (mem (plus (reg) (const_int)))
f676971a 9085 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
0f6937fe 9086 register as addr1. */
984e25ac 9087 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
0f6937fe 9088 return 1;
35068b43
RK		 9089 if (GET_CODE (addr2) != PLUS)
9090 return 0;
9091
9092 if (GET_CODE (XEXP (addr2, 0)) != REG
9093 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9094 return 0;
9095
9096 if (reg1 != REGNO (XEXP (addr2, 0)))
9097 return 0;
9098
9099 /* The offset for the second addr must be 8 more than the first addr. */
9100 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
9101 return 0;
9102
9103 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9104 instructions. */
9105 return 1;
9106}
9878760c
RK		 9107\f
9108/* Return the register class of a scratch register needed to copy IN into
9109 or out of a register in CLASS in MODE. If it can be done directly,
9110 NO_REGS is returned. */
9111
9112enum reg_class
f676971a 9113secondary_reload_class (enum reg_class class,
a9baceb1
GK		 9114 enum machine_mode mode ATTRIBUTE_UNUSED,
9115 rtx in)
9878760c 9116{
5accd822 9117 int regno;
9878760c 9118
ab82a49f
AP		 9119 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9120#if TARGET_MACHO
c4ad648e 9121 && MACHOPIC_INDIRECT
ab82a49f 9122#endif
c4ad648e 9123 ))
46fad5b7
DJ		 9124 {
9125 /* We cannot copy a symbolic operand directly into anything
c4ad648e
AM		 9126 other than BASE_REGS for TARGET_ELF. So indicate that a
9127 register from BASE_REGS is needed as an intermediate
9128 register.
f676971a 9129
46fad5b7
DJ		 9130 On Darwin, pic addresses require a load from memory, which
9131 needs a base register. */
9132 if (class != BASE_REGS
c4ad648e
AM		 9133 && (GET_CODE (in) == SYMBOL_REF
9134 || GET_CODE (in) == HIGH
9135 || GET_CODE (in) == LABEL_REF
9136 || GET_CODE (in) == CONST))
9137 return BASE_REGS;
46fad5b7 9138 }
e7b7998a 9139
5accd822
DE		 9140 if (GET_CODE (in) == REG)
9141 {
9142 regno = REGNO (in);
9143 if (regno >= FIRST_PSEUDO_REGISTER)
9144 {
9145 regno = true_regnum (in);
9146 if (regno >= FIRST_PSEUDO_REGISTER)
9147 regno = -1;
9148 }
9149 }
9150 else if (GET_CODE (in) == SUBREG)
9151 {
9152 regno = true_regnum (in);
9153 if (regno >= FIRST_PSEUDO_REGISTER)
9154 regno = -1;
9155 }
9156 else
9157 regno = -1;
9158
9878760c
RK		 9159 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9160 into anything. */
9161 if (class == GENERAL_REGS || class == BASE_REGS
9162 || (regno >= 0 && INT_REGNO_P (regno)))
9163 return NO_REGS;
9164
9165 /* Constants, memory, and FP registers can go into FP registers. */
9166 if ((regno == -1 || FP_REGNO_P (regno))
9167 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9168 return NO_REGS;
9169
0ac081f6
AH		 9170 /* Memory, and AltiVec registers can go into AltiVec registers. */
9171 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9172 && class == ALTIVEC_REGS)
9173 return NO_REGS;
9174
9878760c
RK		 9175 /* We can copy among the CR registers. */
9176 if ((class == CR_REGS || class == CR0_REGS)
9177 && regno >= 0 && CR_REGNO_P (regno))
9178 return NO_REGS;
9179
9180 /* Otherwise, we need GENERAL_REGS. */
9181 return GENERAL_REGS;
9182}
9183\f
9184/* Given a comparison operation, return the bit number in CCR to test. We
f676971a 9185 know this is a valid comparison.
9878760c
RK		 9186
9187 SCC_P is 1 if this is for an scc. That means that %D will have been
9188 used instead of %C, so the bits will be in different places.
9189
b4ac57ab 9190 Return -1 if OP isn't a valid comparison for some reason. */
9878760c
RK		 9191
9192int
a2369ed3 9193ccr_bit (rtx op, int scc_p)
9878760c
RK		 9194{
9195 enum rtx_code code = GET_CODE (op);
9196 enum machine_mode cc_mode;
9197 int cc_regnum;
9198 int base_bit;
9ebbca7d 9199 rtx reg;
9878760c 9200
ec8e098d 9201 if (!COMPARISON_P (op))
9878760c
RK		 9202 return -1;
9203
9ebbca7d
GK		 9204 reg = XEXP (op, 0);
9205
37409796 9206 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9ebbca7d
GK		 9207
9208 cc_mode = GET_MODE (reg);
9209 cc_regnum = REGNO (reg);
9210 base_bit = 4 * (cc_regnum - CR0_REGNO);
9878760c 9211
39a10a29 9212 validate_condition_mode (code, cc_mode);
c5defebb 9213
b7053a3f
GK		 9214 /* When generating a sCOND operation, only positive conditions are
9215 allowed. */
37409796
NS		 9216 gcc_assert (!scc_p
9217 || code == EQ || code == GT || code == LT || code == UNORDERED
9218 || code == GTU || code == LTU);
f676971a 9219
9878760c
RK		 9220 switch (code)
9221 {
9222 case NE:
9223 return scc_p ? base_bit + 3 : base_bit + 2;
9224 case EQ:
9225 return base_bit + 2;
1c882ea4 9226 case GT: case GTU: case UNLE:
9878760c 9227 return base_bit + 1;
1c882ea4 9228 case LT: case LTU: case UNGE:
9878760c 9229 return base_bit;
1c882ea4
GK		 9230 case ORDERED: case UNORDERED:
9231 return base_bit + 3;
9878760c
RK		 9232
9233 case GE: case GEU:
39a10a29 9234 /* If scc, we will have done a cror to put the bit in the
9878760c
RK		 9235 unordered position. So test that bit. For integer, this is ! LT
9236 unless this is an scc insn. */
39a10a29 9237 return scc_p ? base_bit + 3 : base_bit;
9878760c
RK		 9238
9239 case LE: case LEU:
39a10a29 9240 return scc_p ? base_bit + 3 : base_bit + 1;
1c882ea4 9241
9878760c 9242 default:
37409796 9243 gcc_unreachable ();
9878760c
RK		 9244 }
9245}
1ff7789b 9246\f
8d30c4ee 9247/* Return the GOT register. */
1ff7789b 9248
9390387d 9249rtx
a2369ed3 9250rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
1ff7789b 9251{
a4f6c312
SS		 9252 /* The second flow pass currently (June 1999) can't update
9253 regs_ever_live without disturbing other parts of the compiler, so
9254 update it here to make the prolog/epilogue code happy. */
1db02437
FS		 9255 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9256 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
1ff7789b 9257
8d30c4ee 9258 current_function_uses_pic_offset_table = 1;
3cb999d8 9259
1ff7789b
MM		 9260 return pic_offset_table_rtx;
9261}
a7df97e6 9262\f
e2500fed
GK		 9263/* Function to init struct machine_function.
9264 This will be called, via a pointer variable,
9265 from push_function_context. */
a7df97e6 9266
e2500fed 9267static struct machine_function *
863d938c 9268rs6000_init_machine_status (void)
a7df97e6 9269{
e2500fed 9270 return ggc_alloc_cleared (sizeof (machine_function));
a7df97e6 9271}
9878760c 9272\f
0ba1b2ff
AM		 9273/* These macros test for integers and extract the low-order bits. */
9274#define INT_P(X) \
9275((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9276 && GET_MODE (X) == VOIDmode)
9277
9278#define INT_LOWPART(X) \
9279 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9280
9281int
a2369ed3 9282extract_MB (rtx op)
0ba1b2ff
AM		 9283{
9284 int i;
9285 unsigned long val = INT_LOWPART (op);
9286
9287 /* If the high bit is zero, the value is the first 1 bit we find
9288 from the left. */
9289 if ((val & 0x80000000) == 0)
9290 {
37409796 9291 gcc_assert (val & 0xffffffff);
0ba1b2ff
AM		 9292
9293 i = 1;
9294 while (((val <<= 1) & 0x80000000) == 0)
9295 ++i;
9296 return i;
9297 }
9298
9299 /* If the high bit is set and the low bit is not, or the mask is all
9300 1's, the value is zero. */
9301 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9302 return 0;
9303
9304 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9305 from the right. */
9306 i = 31;
9307 while (((val >>= 1) & 1) != 0)
9308 --i;
9309
9310 return i;
9311}
9312
9313int
a2369ed3 9314extract_ME (rtx op)
0ba1b2ff
AM		 9315{
9316 int i;
9317 unsigned long val = INT_LOWPART (op);
9318
9319 /* If the low bit is zero, the value is the first 1 bit we find from
9320 the right. */
9321 if ((val & 1) == 0)
9322 {
37409796 9323 gcc_assert (val & 0xffffffff);
0ba1b2ff
AM		 9324
9325 i = 30;
9326 while (((val >>= 1) & 1) == 0)
9327 --i;
9328
9329 return i;
9330 }
9331
9332 /* If the low bit is set and the high bit is not, or the mask is all
9333 1's, the value is 31. */
9334 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9335 return 31;
9336
9337 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9338 from the left. */
9339 i = 0;
9340 while (((val <<= 1) & 0x80000000) != 0)
9341 ++i;
9342
9343 return i;
9344}
9345
c4501e62
JJ		 9346/* Locate some local-dynamic symbol still in use by this function
9347 so that we can print its name in some tls_ld pattern. */
9348
9349static const char *
863d938c 9350rs6000_get_some_local_dynamic_name (void)
c4501e62
JJ		 9351{
9352 rtx insn;
9353
9354 if (cfun->machine->some_ld_name)
9355 return cfun->machine->some_ld_name;
9356
9357 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9358 if (INSN_P (insn)
9359 && for_each_rtx (&PATTERN (insn),
9360 rs6000_get_some_local_dynamic_name_1, 0))
9361 return cfun->machine->some_ld_name;
9362
37409796 9363 gcc_unreachable ();
c4501e62
JJ		 9364}
9365
9366/* Helper function for rs6000_get_some_local_dynamic_name. */
9367
9368static int
a2369ed3 9369rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 9370{
9371 rtx x = *px;
9372
9373 if (GET_CODE (x) == SYMBOL_REF)
9374 {
9375 const char *str = XSTR (x, 0);
9376 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9377 {
9378 cfun->machine->some_ld_name = str;
9379 return 1;
9380 }
9381 }
9382
9383 return 0;
9384}
9385
85b776df
AM		 9386/* Write out a function code label. */
9387
9388void
9389rs6000_output_function_entry (FILE *file, const char *fname)
9390{
9391 if (fname[0] != '.')
9392 {
9393 switch (DEFAULT_ABI)
9394 {
9395 default:
37409796 9396 gcc_unreachable ();
85b776df
AM		 9397
9398 case ABI_AIX:
9399 if (DOT_SYMBOLS)
9400 putc ('.', file);
9401 else
9402 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9403 break;
9404
9405 case ABI_V4:
9406 case ABI_DARWIN:
9407 break;
9408 }
9409 }
9410 if (TARGET_AIX)
9411 RS6000_OUTPUT_BASENAME (file, fname);
9412 else
9413 assemble_name (file, fname);
9414}
9415
9878760c
RK		 9416/* Print an operand. Recognize special options, documented below. */
9417
38c1f2d7 9418#if TARGET_ELF
d9407988 9419#define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8fbd2dc7 9420#define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
ba5e43aa
MM		 9421#else
9422#define SMALL_DATA_RELOC "sda21"
8fbd2dc7 9423#define SMALL_DATA_REG 0
ba5e43aa
MM		 9424#endif
9425
9878760c 9426void
a2369ed3 9427print_operand (FILE *file, rtx x, int code)
9878760c
RK		 9428{
9429 int i;
a260abc9 9430 HOST_WIDE_INT val;
0ba1b2ff 9431 unsigned HOST_WIDE_INT uval;
9878760c
RK		 9432
9433 switch (code)
9434 {
a8b3aeda 9435 case '.':
a85d226b
RK		 9436 /* Write out an instruction after the call which may be replaced
9437 with glue code by the loader. This depends on the AIX version. */
9438 asm_fprintf (file, RS6000_CALL_GLUE);
a8b3aeda
RK		 9439 return;
9440
81eace42
GK		 9441 /* %a is output_address. */
9442
9854d9ed
RK		 9443 case 'A':
9444 /* If X is a constant integer whose low-order 5 bits are zero,
9445 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
76229ac8 9446 in the AIX assembler where "sri" with a zero shift count
20e26713 9447 writes a trash instruction. */
9854d9ed 9448 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
76229ac8 9449 putc ('l', file);
9854d9ed 9450 else
76229ac8 9451 putc ('r', file);
9854d9ed
RK		 9452 return;
9453
9454 case 'b':
e2c953b6
DE		 9455 /* If constant, low-order 16 bits of constant, unsigned.
9456 Otherwise, write normally. */
9457 if (INT_P (x))
9458 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9459 else
9460 print_operand (file, x, 0);
cad12a8d
RK		 9461 return;
9462
a260abc9
DE		 9463 case 'B':
9464 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9465 for 64-bit mask direction. */
9390387d 9466 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
a238cd8b 9467 return;
a260abc9 9468
81eace42
GK		 9469 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9470 output_operand. */
9471
423c1189
AH		 9472 case 'c':
9473 /* X is a CR register. Print the number of the GT bit of the CR. */
9474 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9475 output_operand_lossage ("invalid %%E value");
9476 else
9477 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9478 return;
9479
9480 case 'D':
6b1fedc3 9481 /* Like 'J' but get to the EQ bit. */
37409796 9482 gcc_assert (GET_CODE (x) == REG);
423c1189 9483
6b1fedc3
AH		 9484 /* Bit 1 is EQ bit. */
9485 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
423c1189 9486
64022b5d 9487 fprintf (file, "%d", i);
423c1189
AH		 9488 return;
9489
9854d9ed 9490 case 'E':
39a10a29 9491 /* X is a CR register. Print the number of the EQ bit of the CR */
9854d9ed
RK		 9492 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9493 output_operand_lossage ("invalid %%E value");
78fbdbf7 9494 else
39a10a29 9495 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
a85d226b 9496 return;
9854d9ed
RK		 9497
9498 case 'f':
9499 /* X is a CR register. Print the shift count needed to move it
9500 to the high-order four bits. */
9501 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9502 output_operand_lossage ("invalid %%f value");
9503 else
9ebbca7d 9504 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9505 return;
9506
9507 case 'F':
9508 /* Similar, but print the count for the rotate in the opposite
9509 direction. */
9510 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9511 output_operand_lossage ("invalid %%F value");
9512 else
9ebbca7d 9513 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9514 return;
9515
9516 case 'G':
9517 /* X is a constant integer. If it is negative, print "m",
43aa4e05 9518 otherwise print "z". This is to make an aze or ame insn. */
9854d9ed
RK		 9519 if (GET_CODE (x) != CONST_INT)
9520 output_operand_lossage ("invalid %%G value");
9521 else if (INTVAL (x) >= 0)
76229ac8 9522 putc ('z', file);
9854d9ed 9523 else
76229ac8 9524 putc ('m', file);
9854d9ed 9525 return;
e2c953b6 9526
9878760c 9527 case 'h':
a4f6c312
SS		 9528 /* If constant, output low-order five bits. Otherwise, write
9529 normally. */
9878760c 9530 if (INT_P (x))
5f59ecb7 9531 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9878760c
RK		 9532 else
9533 print_operand (file, x, 0);
9534 return;
9535
64305719 9536 case 'H':
a4f6c312
SS		 9537 /* If constant, output low-order six bits. Otherwise, write
9538 normally. */
64305719 9539 if (INT_P (x))
5f59ecb7 9540 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
64305719
DE		 9541 else
9542 print_operand (file, x, 0);
9543 return;
9544
9854d9ed
RK		 9545 case 'I':
9546 /* Print `i' if this is a constant, else nothing. */
9878760c 9547 if (INT_P (x))
76229ac8 9548 putc ('i', file);
9878760c
RK		 9549 return;
9550
9854d9ed
RK		 9551 case 'j':
9552 /* Write the bit number in CCR for jump. */
9553 i = ccr_bit (x, 0);
9554 if (i == -1)
9555 output_operand_lossage ("invalid %%j code");
9878760c 9556 else
9854d9ed 9557 fprintf (file, "%d", i);
9878760c
RK		 9558 return;
9559
9854d9ed
RK		 9560 case 'J':
9561 /* Similar, but add one for shift count in rlinm for scc and pass
9562 scc flag to `ccr_bit'. */
9563 i = ccr_bit (x, 1);
9564 if (i == -1)
9565 output_operand_lossage ("invalid %%J code");
9566 else
a0466a68
RK		 9567 /* If we want bit 31, write a shift count of zero, not 32. */
9568 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9878760c
RK		 9569 return;
9570
9854d9ed
RK		 9571 case 'k':
9572 /* X must be a constant. Write the 1's complement of the
9573 constant. */
9878760c 9574 if (! INT_P (x))
9854d9ed 9575 output_operand_lossage ("invalid %%k value");
e2c953b6
DE		 9576 else
9577 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9878760c
RK		 9578 return;
9579
81eace42 9580 case 'K':
9ebbca7d
GK		 9581 /* X must be a symbolic constant on ELF. Write an
9582 expression suitable for an 'addi' that adds in the low 16
9583 bits of the MEM. */
9584 if (GET_CODE (x) != CONST)
9585 {
9586 print_operand_address (file, x);
9587 fputs ("@l", file);
9588 }
9589 else
9590 {
9591 if (GET_CODE (XEXP (x, 0)) != PLUS
9592 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9593 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9594 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
53cd5d6c 9595 output_operand_lossage ("invalid %%K value");
9ebbca7d
GK		 9596 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9597 fputs ("@l", file);
ed8d2920
MM		 9598 /* For GNU as, there must be a non-alphanumeric character
9599 between 'l' and the number. The '-' is added by
9600 print_operand() already. */
9601 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9602 fputs ("+", file);
9ebbca7d
GK		 9603 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9604 }
81eace42
GK		 9605 return;
9606
9607 /* %l is output_asm_label. */
9ebbca7d 9608
9854d9ed
RK		 9609 case 'L':
9610 /* Write second word of DImode or DFmode reference. Works on register
9611 or non-indexed memory only. */
9612 if (GET_CODE (x) == REG)
fb5c67a7 9613 fputs (reg_names[REGNO (x) + 1], file);
9854d9ed
RK		 9614 else if (GET_CODE (x) == MEM)
9615 {
9616 /* Handle possible auto-increment. Since it is pre-increment and
1427100a 9617 we have already done it, we can just use an offset of word. */
9854d9ed
RK		 9618 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9619 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
ed8908e7
RK		 9620 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9621 UNITS_PER_WORD));
9854d9ed 9622 else
d7624dc0
RK		 9623 output_address (XEXP (adjust_address_nv (x, SImode,
9624 UNITS_PER_WORD),
9625 0));
ed8908e7 9626
ba5e43aa 9627 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9628 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9629 reg_names[SMALL_DATA_REG]);
9854d9ed 9630 }
9878760c 9631 return;
f676971a 9632
9878760c
RK		 9633 case 'm':
9634 /* MB value for a mask operand. */
b1765bde 9635 if (! mask_operand (x, SImode))
9878760c
RK		 9636 output_operand_lossage ("invalid %%m value");
9637
0ba1b2ff 9638 fprintf (file, "%d", extract_MB (x));
9878760c
RK		 9639 return;
9640
9641 case 'M':
9642 /* ME value for a mask operand. */
b1765bde 9643 if (! mask_operand (x, SImode))
a260abc9 9644 output_operand_lossage ("invalid %%M value");
9878760c 9645
0ba1b2ff 9646 fprintf (file, "%d", extract_ME (x));
9878760c
RK		 9647 return;
9648
81eace42
GK		 9649 /* %n outputs the negative of its operand. */
9650
9878760c
RK		 9651 case 'N':
9652 /* Write the number of elements in the vector times 4. */
9653 if (GET_CODE (x) != PARALLEL)
9654 output_operand_lossage ("invalid %%N value");
e2c953b6
DE		 9655 else
9656 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9878760c
RK		 9657 return;
9658
9659 case 'O':
9660 /* Similar, but subtract 1 first. */
9661 if (GET_CODE (x) != PARALLEL)
1427100a 9662 output_operand_lossage ("invalid %%O value");
e2c953b6
DE		 9663 else
9664 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9878760c
RK		 9665 return;
9666
9854d9ed
RK		 9667 case 'p':
9668 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9669 if (! INT_P (x)
2bfcf297 9670 || INT_LOWPART (x) < 0
9854d9ed
RK		 9671 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9672 output_operand_lossage ("invalid %%p value");
e2c953b6
DE		 9673 else
9674 fprintf (file, "%d", i);
9854d9ed
RK		 9675 return;
9676
9878760c
RK		 9677 case 'P':
9678 /* The operand must be an indirect memory reference. The result
8bb418a3 9679 is the register name. */
9878760c
RK		 9680 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9681 || REGNO (XEXP (x, 0)) >= 32)
9682 output_operand_lossage ("invalid %%P value");
e2c953b6 9683 else
fb5c67a7 9684 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9878760c
RK		 9685 return;
9686
dfbdccdb
GK		 9687 case 'q':
9688 /* This outputs the logical code corresponding to a boolean
9689 expression. The expression may have one or both operands
39a10a29 9690 negated (if one, only the first one). For condition register
c4ad648e
AM		 9691 logical operations, it will also treat the negated
9692 CR codes as NOTs, but not handle NOTs of them. */
dfbdccdb 9693 {
63bc1d05 9694 const char *const *t = 0;
dfbdccdb
GK		 9695 const char *s;
9696 enum rtx_code code = GET_CODE (x);
9697 static const char * const tbl[3][3] = {
9698 { "and", "andc", "nor" },
9699 { "or", "orc", "nand" },
9700 { "xor", "eqv", "xor" } };
9701
9702 if (code == AND)
9703 t = tbl[0];
9704 else if (code == IOR)
9705 t = tbl[1];
9706 else if (code == XOR)
9707 t = tbl[2];
9708 else
9709 output_operand_lossage ("invalid %%q value");
9710
9711 if (GET_CODE (XEXP (x, 0)) != NOT)
9712 s = t[0];
9713 else
9714 {
9715 if (GET_CODE (XEXP (x, 1)) == NOT)
9716 s = t[2];
9717 else
9718 s = t[1];
9719 }
f676971a 9720
dfbdccdb
GK		 9721 fputs (s, file);
9722 }
9723 return;
9724
2c4a9cff
DE		 9725 case 'Q':
9726 if (TARGET_MFCRF)
3b6ce0af 9727 fputc (',', file);
5efb1046 9728 /* FALLTHRU */
2c4a9cff
DE		 9729 else
9730 return;
9731
9854d9ed
RK		 9732 case 'R':
9733 /* X is a CR register. Print the mask for `mtcrf'. */
9734 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9735 output_operand_lossage ("invalid %%R value");
9736 else
9ebbca7d 9737 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9878760c 9738 return;
9854d9ed
RK		 9739
9740 case 's':
9741 /* Low 5 bits of 32 - value */
9742 if (! INT_P (x))
9743 output_operand_lossage ("invalid %%s value");
e2c953b6
DE		 9744 else
9745 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9878760c 9746 return;
9854d9ed 9747
a260abc9 9748 case 'S':
0ba1b2ff 9749 /* PowerPC64 mask position. All 0's is excluded.
a260abc9
DE		 9750 CONST_INT 32-bit mask is considered sign-extended so any
9751 transition must occur within the CONST_INT, not on the boundary. */
b1765bde 9752 if (! mask64_operand (x, DImode))
a260abc9
DE		 9753 output_operand_lossage ("invalid %%S value");
9754
0ba1b2ff 9755 uval = INT_LOWPART (x);
a260abc9 9756
0ba1b2ff 9757 if (uval & 1) /* Clear Left */
a260abc9 9758 {
f099d360
GK		 9759#if HOST_BITS_PER_WIDE_INT > 64
9760 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9761#endif
0ba1b2ff 9762 i = 64;
a260abc9 9763 }
0ba1b2ff 9764 else /* Clear Right */
a260abc9 9765 {
0ba1b2ff 9766 uval = ~uval;
f099d360
GK		 9767#if HOST_BITS_PER_WIDE_INT > 64
9768 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9769#endif
0ba1b2ff 9770 i = 63;
a260abc9 9771 }
0ba1b2ff
AM		 9772 while (uval != 0)
9773 --i, uval >>= 1;
37409796 9774 gcc_assert (i >= 0);
0ba1b2ff
AM		 9775 fprintf (file, "%d", i);
9776 return;
a260abc9 9777
a3170dc6
AH		 9778 case 't':
9779 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
37409796 9780 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
a3170dc6
AH		 9781
9782 /* Bit 3 is OV bit. */
9783 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9784
9785 /* If we want bit 31, write a shift count of zero, not 32. */
9786 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9787 return;
9788
cccf3bdc
DE		 9789 case 'T':
9790 /* Print the symbolic name of a branch target register. */
9791 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9792 && REGNO (x) != COUNT_REGISTER_REGNUM))
9793 output_operand_lossage ("invalid %%T value");
e2c953b6 9794 else if (REGNO (x) == LINK_REGISTER_REGNUM)
cccf3bdc
DE		 9795 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9796 else
9797 fputs ("ctr", file);
9798 return;
9799
9854d9ed 9800 case 'u':
802a0058 9801 /* High-order 16 bits of constant for use in unsigned operand. */
9854d9ed
RK		 9802 if (! INT_P (x))
9803 output_operand_lossage ("invalid %%u value");
e2c953b6 9804 else
f676971a 9805 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
e2c953b6 9806 (INT_LOWPART (x) >> 16) & 0xffff);
9878760c
RK		 9807 return;
9808
802a0058
MM		 9809 case 'v':
9810 /* High-order 16 bits of constant for use in signed operand. */
9811 if (! INT_P (x))
9812 output_operand_lossage ("invalid %%v value");
e2c953b6 9813 else
134c32f6
DE		 9814 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9815 (INT_LOWPART (x) >> 16) & 0xffff);
9816 return;
802a0058 9817
9854d9ed
RK		 9818 case 'U':
9819 /* Print `u' if this has an auto-increment or auto-decrement. */
9820 if (GET_CODE (x) == MEM
9821 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9822 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
76229ac8 9823 putc ('u', file);
9854d9ed 9824 return;
9878760c 9825
e0cd0770
JC		 9826 case 'V':
9827 /* Print the trap code for this operand. */
9828 switch (GET_CODE (x))
9829 {
9830 case EQ:
9831 fputs ("eq", file); /* 4 */
9832 break;
9833 case NE:
9834 fputs ("ne", file); /* 24 */
9835 break;
9836 case LT:
9837 fputs ("lt", file); /* 16 */
9838 break;
9839 case LE:
9840 fputs ("le", file); /* 20 */
9841 break;
9842 case GT:
9843 fputs ("gt", file); /* 8 */
9844 break;
9845 case GE:
9846 fputs ("ge", file); /* 12 */
9847 break;
9848 case LTU:
9849 fputs ("llt", file); /* 2 */
9850 break;
9851 case LEU:
9852 fputs ("lle", file); /* 6 */
9853 break;
9854 case GTU:
9855 fputs ("lgt", file); /* 1 */
9856 break;
9857 case GEU:
9858 fputs ("lge", file); /* 5 */
9859 break;
9860 default:
37409796 9861 gcc_unreachable ();
e0cd0770
JC		 9862 }
9863 break;
9864
9854d9ed
RK		 9865 case 'w':
9866 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9867 normally. */
9868 if (INT_P (x))
f676971a 9869 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5f59ecb7 9870 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9854d9ed
RK		 9871 else
9872 print_operand (file, x, 0);
9878760c
RK		 9873 return;
9874
9854d9ed 9875 case 'W':
e2c953b6 9876 /* MB value for a PowerPC64 rldic operand. */
e2c953b6
DE		 9877 val = (GET_CODE (x) == CONST_INT
9878 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9879
9880 if (val < 0)
9881 i = -1;
9854d9ed 9882 else
e2c953b6
DE		 9883 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9884 if ((val <<= 1) < 0)
9885 break;
9886
9887#if HOST_BITS_PER_WIDE_INT == 32
9888 if (GET_CODE (x) == CONST_INT && i >= 0)
9889 i += 32; /* zero-extend high-part was all 0's */
9890 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9891 {
9892 val = CONST_DOUBLE_LOW (x);
9893
37409796
NS		 9894 gcc_assert (val);
9895 if (val < 0)
e2c953b6
DE		 9896 --i;
9897 else
9898 for ( ; i < 64; i++)
9899 if ((val <<= 1) < 0)
9900 break;
9901 }
9902#endif
9903
9904 fprintf (file, "%d", i + 1);
9854d9ed 9905 return;
9878760c 9906
9854d9ed
RK		 9907 case 'X':
9908 if (GET_CODE (x) == MEM
4d588c14 9909 && legitimate_indexed_address_p (XEXP (x, 0), 0))
76229ac8 9910 putc ('x', file);
9854d9ed 9911 return;
9878760c 9912
9854d9ed
RK		 9913 case 'Y':
9914 /* Like 'L', for third word of TImode */
9915 if (GET_CODE (x) == REG)
fb5c67a7 9916 fputs (reg_names[REGNO (x) + 2], file);
9854d9ed 9917 else if (GET_CODE (x) == MEM)
9878760c 9918 {
9854d9ed
RK		 9919 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9920 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 9921 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9854d9ed 9922 else
d7624dc0 9923 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
ba5e43aa 9924 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9925 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9926 reg_names[SMALL_DATA_REG]);
9878760c
RK		 9927 }
9928 return;
f676971a 9929
9878760c 9930 case 'z':
b4ac57ab
RS		 9931 /* X is a SYMBOL_REF. Write out the name preceded by a
9932 period and without any trailing data in brackets. Used for function
4d30c363
MM		 9933 names. If we are configured for System V (or the embedded ABI) on
9934 the PowerPC, do not emit the period, since those systems do not use
9935 TOCs and the like. */
37409796 9936 gcc_assert (GET_CODE (x) == SYMBOL_REF);
9878760c 9937
c4ad648e
AM		 9938 /* Mark the decl as referenced so that cgraph will output the
9939 function. */
9bf6462a 9940 if (SYMBOL_REF_DECL (x))
c4ad648e 9941 mark_decl_referenced (SYMBOL_REF_DECL (x));
9bf6462a 9942
85b776df 9943 /* For macho, check to see if we need a stub. */
f9da97f0
AP		 9944 if (TARGET_MACHO)
9945 {
9946 const char *name = XSTR (x, 0);
a031e781 9947#if TARGET_MACHO
3b48085e 9948 if (MACHOPIC_INDIRECT
11abc112
MM		 9949 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9950 name = machopic_indirection_name (x, /*stub_p=*/true);
f9da97f0
AP		 9951#endif
9952 assemble_name (file, name);
9953 }
85b776df 9954 else if (!DOT_SYMBOLS)
9739c90c 9955 assemble_name (file, XSTR (x, 0));
85b776df
AM		 9956 else
9957 rs6000_output_function_entry (file, XSTR (x, 0));
9878760c
RK		 9958 return;
9959
9854d9ed
RK		 9960 case 'Z':
9961 /* Like 'L', for last word of TImode. */
9962 if (GET_CODE (x) == REG)
fb5c67a7 9963 fputs (reg_names[REGNO (x) + 3], file);
9854d9ed
RK		 9964 else if (GET_CODE (x) == MEM)
9965 {
9966 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9967 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 9968 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9854d9ed 9969 else
d7624dc0 9970 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
ba5e43aa 9971 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9972 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9973 reg_names[SMALL_DATA_REG]);
9854d9ed 9974 }
5c23c401 9975 return;
0ac081f6 9976
a3170dc6 9977 /* Print AltiVec or SPE memory operand. */
0ac081f6
AH		 9978 case 'y':
9979 {
9980 rtx tmp;
9981
37409796 9982 gcc_assert (GET_CODE (x) == MEM);
0ac081f6
AH		 9983
9984 tmp = XEXP (x, 0);
9985
993f19a8 9986 if (TARGET_E500)
a3170dc6
AH		 9987 {
9988 /* Handle [reg]. */
9989 if (GET_CODE (tmp) == REG)
9990 {
9991 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9992 break;
9993 }
9994 /* Handle [reg+UIMM]. */
9995 else if (GET_CODE (tmp) == PLUS &&
9996 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9997 {
9998 int x;
9999
37409796 10000 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
a3170dc6
AH		 10001
10002 x = INTVAL (XEXP (tmp, 1));
10003 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10004 break;
10005 }
10006
10007 /* Fall through. Must be [reg+reg]. */
10008 }
850e8d3d
DN		 10009 if (TARGET_ALTIVEC
10010 && GET_CODE (tmp) == AND
10011 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10012 && INTVAL (XEXP (tmp, 1)) == -16)
10013 tmp = XEXP (tmp, 0);
0ac081f6 10014 if (GET_CODE (tmp) == REG)
c62f2db5 10015 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
37409796 10016 else
0ac081f6 10017 {
37409796
NS		 10018 gcc_assert (GET_CODE (tmp) == PLUS
10019 && GET_CODE (XEXP (tmp, 1)) == REG);
10020
0ac081f6
AH		 10021 if (REGNO (XEXP (tmp, 0)) == 0)
10022 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10023 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10024 else
10025 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10026 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10027 }
0ac081f6
AH		 10028 break;
10029 }
f676971a 10030
9878760c
RK		 10031 case 0:
10032 if (GET_CODE (x) == REG)
10033 fprintf (file, "%s", reg_names[REGNO (x)]);
10034 else if (GET_CODE (x) == MEM)
10035 {
10036 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10037 know the width from the mode. */
10038 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
79ba6d34
MM		 10039 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10040 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 10041 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
79ba6d34
MM		 10042 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10043 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 10044 else
a54d04b7 10045 output_address (XEXP (x, 0));
9878760c
RK		 10046 }
10047 else
a54d04b7 10048 output_addr_const (file, x);
a85d226b 10049 return;
9878760c 10050
c4501e62
JJ		 10051 case '&':
10052 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10053 return;
10054
9878760c
RK		 10055 default:
10056 output_operand_lossage ("invalid %%xn code");
10057 }
10058}
10059\f
10060/* Print the address of an operand. */
10061
10062void
a2369ed3 10063print_operand_address (FILE *file, rtx x)
9878760c
RK		 10064{
10065 if (GET_CODE (x) == REG)
4697a36c 10066 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9ebbca7d
GK		 10067 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10068 || GET_CODE (x) == LABEL_REF)
9878760c
RK		 10069 {
10070 output_addr_const (file, x);
ba5e43aa 10071 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 10072 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10073 reg_names[SMALL_DATA_REG]);
37409796
NS		 10074 else
10075 gcc_assert (!TARGET_TOC);
9878760c
RK		 10076 }
10077 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10078 {
10079 if (REGNO (XEXP (x, 0)) == 0)
4697a36c
MM		 10080 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10081 reg_names[ REGNO (XEXP (x, 0)) ]);
9878760c 10082 else
4697a36c
MM		 10083 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10084 reg_names[ REGNO (XEXP (x, 1)) ]);
9878760c
RK		 10085 }
10086 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
4a0a75dd
KG		 10087 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10088 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
3cb999d8
DE		 10089#if TARGET_ELF
10090 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 10091 && CONSTANT_P (XEXP (x, 1)))
4697a36c
MM		 10092 {
10093 output_addr_const (file, XEXP (x, 1));
10094 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10095 }
c859cda6
DJ		 10096#endif
10097#if TARGET_MACHO
10098 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 10099 && CONSTANT_P (XEXP (x, 1)))
c859cda6
DJ		 10100 {
10101 fprintf (file, "lo16(");
10102 output_addr_const (file, XEXP (x, 1));
10103 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10104 }
3cb999d8 10105#endif
4d588c14 10106 else if (legitimate_constant_pool_address_p (x))
9ebbca7d 10107 {
2bfcf297 10108 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9ebbca7d 10109 {
2bfcf297
DB		 10110 rtx contains_minus = XEXP (x, 1);
10111 rtx minus, symref;
10112 const char *name;
f676971a 10113
9ebbca7d 10114 /* Find the (minus (sym) (toc)) buried in X, and temporarily
a4f6c312 10115 turn it into (sym) for output_addr_const. */
9ebbca7d
GK		 10116 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10117 contains_minus = XEXP (contains_minus, 0);
10118
2bfcf297
DB		 10119 minus = XEXP (contains_minus, 0);
10120 symref = XEXP (minus, 0);
10121 XEXP (contains_minus, 0) = symref;
10122 if (TARGET_ELF)
10123 {
10124 char *newname;
10125
10126 name = XSTR (symref, 0);
10127 newname = alloca (strlen (name) + sizeof ("@toc"));
10128 strcpy (newname, name);
10129 strcat (newname, "@toc");
10130 XSTR (symref, 0) = newname;
10131 }
10132 output_addr_const (file, XEXP (x, 1));
10133 if (TARGET_ELF)
10134 XSTR (symref, 0) = name;
9ebbca7d
GK		 10135 XEXP (contains_minus, 0) = minus;
10136 }
10137 else
10138 output_addr_const (file, XEXP (x, 1));
10139
10140 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10141 }
9878760c 10142 else
37409796 10143 gcc_unreachable ();
9878760c
RK		 10144}
10145\f
88cad84b 10146/* Target hook for assembling integer objects. The PowerPC version has
301d03af
RS		 10147 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10148 is defined. It also needs to handle DI-mode objects on 64-bit
10149 targets. */
10150
10151static bool
a2369ed3 10152rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
301d03af 10153{
f4f4921e 10154#ifdef RELOCATABLE_NEEDS_FIXUP
301d03af 10155 /* Special handling for SI values. */
84dcde01 10156 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
301d03af 10157 {
a2369ed3 10158 extern int in_toc_section (void);
301d03af 10159 static int recurse = 0;
f676971a 10160
301d03af
RS		 10161 /* For -mrelocatable, we mark all addresses that need to be fixed up
10162 in the .fixup section. */
10163 if (TARGET_RELOCATABLE
10164 && !in_toc_section ()
10165 && !in_text_section ()
642af3be 10166 && !in_unlikely_text_section ()
301d03af
RS		 10167 && !recurse
10168 && GET_CODE (x) != CONST_INT
10169 && GET_CODE (x) != CONST_DOUBLE
10170 && CONSTANT_P (x))
10171 {
10172 char buf[256];
10173
10174 recurse = 1;
10175 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10176 fixuplabelno++;
10177 ASM_OUTPUT_LABEL (asm_out_file, buf);
10178 fprintf (asm_out_file, "\t.long\t(");
10179 output_addr_const (asm_out_file, x);
10180 fprintf (asm_out_file, ")@fixup\n");
10181 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10182 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10183 fprintf (asm_out_file, "\t.long\t");
10184 assemble_name (asm_out_file, buf);
10185 fprintf (asm_out_file, "\n\t.previous\n");
10186 recurse = 0;
10187 return true;
10188 }
10189 /* Remove initial .'s to turn a -mcall-aixdesc function
10190 address into the address of the descriptor, not the function
10191 itself. */
10192 else if (GET_CODE (x) == SYMBOL_REF
10193 && XSTR (x, 0)[0] == '.'
10194 && DEFAULT_ABI == ABI_AIX)
10195 {
10196 const char *name = XSTR (x, 0);
10197 while (*name == '.')
10198 name++;
10199
10200 fprintf (asm_out_file, "\t.long\t%s\n", name);
10201 return true;
10202 }
10203 }
f4f4921e 10204#endif /* RELOCATABLE_NEEDS_FIXUP */
301d03af
RS		 10205 return default_assemble_integer (x, size, aligned_p);
10206}
93638d7a
AM		 10207
10208#ifdef HAVE_GAS_HIDDEN
10209/* Emit an assembler directive to set symbol visibility for DECL to
10210 VISIBILITY_TYPE. */
10211
5add3202 10212static void
a2369ed3 10213rs6000_assemble_visibility (tree decl, int vis)
93638d7a 10214{
93638d7a
AM		 10215 /* Functions need to have their entry point symbol visibility set as
10216 well as their descriptor symbol visibility. */
85b776df
AM		 10217 if (DEFAULT_ABI == ABI_AIX
10218 && DOT_SYMBOLS
10219 && TREE_CODE (decl) == FUNCTION_DECL)
93638d7a 10220 {
25fdb4dc 10221 static const char * const visibility_types[] = {
c4ad648e 10222 NULL, "internal", "hidden", "protected"
25fdb4dc
RH		 10223 };
10224
10225 const char *name, *type;
93638d7a
AM		 10226
10227 name = ((* targetm.strip_name_encoding)
10228 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
25fdb4dc 10229 type = visibility_types[vis];
93638d7a 10230
25fdb4dc
RH		 10231 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10232 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
93638d7a 10233 }
25fdb4dc
RH		 10234 else
10235 default_assemble_visibility (decl, vis);
93638d7a
AM		 10236}
10237#endif
301d03af 10238\f
39a10a29 10239enum rtx_code
a2369ed3 10240rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
39a10a29
GK		 10241{
10242 /* Reversal of FP compares takes care -- an ordered compare
10243 becomes an unordered compare and vice versa. */
f676971a 10244 if (mode == CCFPmode
bc9ec0e0
GK		 10245 && (!flag_finite_math_only
10246 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10247 || code == UNEQ || code == LTGT))
bab6226b 10248 return reverse_condition_maybe_unordered (code);
39a10a29 10249 else
bab6226b 10250 return reverse_condition (code);
39a10a29
GK		 10251}
10252
39a10a29
GK		 10253/* Generate a compare for CODE. Return a brand-new rtx that
10254 represents the result of the compare. */
a4f6c312 10255
39a10a29 10256static rtx
a2369ed3 10257rs6000_generate_compare (enum rtx_code code)
39a10a29
GK		 10258{
10259 enum machine_mode comp_mode;
10260 rtx compare_result;
10261
10262 if (rs6000_compare_fp_p)
10263 comp_mode = CCFPmode;
10264 else if (code == GTU || code == LTU
c4ad648e 10265 || code == GEU || code == LEU)
39a10a29 10266 comp_mode = CCUNSmode;
60934f9c
NS		 10267 else if ((code == EQ || code == NE)
10268 && GET_CODE (rs6000_compare_op0) == SUBREG
10269 && GET_CODE (rs6000_compare_op1) == SUBREG
10270 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10271 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10272 /* These are unsigned values, perhaps there will be a later
10273 ordering compare that can be shared with this one.
10274 Unfortunately we cannot detect the signedness of the operands
10275 for non-subregs. */
10276 comp_mode = CCUNSmode;
39a10a29
GK		 10277 else
10278 comp_mode = CCmode;
10279
10280 /* First, the compare. */
10281 compare_result = gen_reg_rtx (comp_mode);
a3170dc6
AH		 10282
10283 /* SPE FP compare instructions on the GPRs. Yuck! */
993f19a8
AH		 10284 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10285 && rs6000_compare_fp_p)
a3170dc6 10286 {
64022b5d 10287 rtx cmp, or_result, compare_result2;
4d4cbc0e
AH		 10288 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10289
10290 if (op_mode == VOIDmode)
10291 op_mode = GET_MODE (rs6000_compare_op1);
a3170dc6 10292
423c1189
AH		 10293 /* Note: The E500 comparison instructions set the GT bit (x +
10294 1), on success. This explains the mess. */
10295
a3170dc6
AH		 10296 switch (code)
10297 {
423c1189 10298 case EQ: case UNEQ: case NE: case LTGT:
37409796
NS		 10299 switch (op_mode)
10300 {
10301 case SFmode:
10302 cmp = flag_unsafe_math_optimizations
10303 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10304 rs6000_compare_op1)
10305 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10306 rs6000_compare_op1);
10307 break;
10308
10309 case DFmode:
10310 cmp = flag_unsafe_math_optimizations
10311 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10312 rs6000_compare_op1)
10313 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10314 rs6000_compare_op1);
10315 break;
10316
10317 default:
10318 gcc_unreachable ();
10319 }
a3170dc6 10320 break;
37409796 10321
423c1189 10322 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
37409796
NS		 10323 switch (op_mode)
10324 {
10325 case SFmode:
10326 cmp = flag_unsafe_math_optimizations
10327 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10328 rs6000_compare_op1)
10329 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10330 rs6000_compare_op1);
10331 break;
10332
10333 case DFmode:
10334 cmp = flag_unsafe_math_optimizations
10335 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10336 rs6000_compare_op1)
10337 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10338 rs6000_compare_op1);
10339 break;
10340
10341 default:
10342 gcc_unreachable ();
10343 }
a3170dc6 10344 break;
37409796 10345
423c1189 10346 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
37409796
NS		 10347 switch (op_mode)
10348 {
10349 case SFmode:
10350 cmp = flag_unsafe_math_optimizations
10351 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10352 rs6000_compare_op1)
10353 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10354 rs6000_compare_op1);
10355 break;
10356
10357 case DFmode:
10358 cmp = flag_unsafe_math_optimizations
10359 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10360 rs6000_compare_op1)
10361 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10362 rs6000_compare_op1);
10363 break;
10364
10365 default:
10366 gcc_unreachable ();
10367 }
a3170dc6 10368 break;
4d4cbc0e 10369 default:
37409796 10370 gcc_unreachable ();
a3170dc6
AH		 10371 }
10372
10373 /* Synthesize LE and GE from LT/GT || EQ. */
10374 if (code == LE || code == GE || code == LEU || code == GEU)
10375 {
a3170dc6
AH		 10376 emit_insn (cmp);
10377
10378 switch (code)
10379 {
10380 case LE: code = LT; break;
10381 case GE: code = GT; break;
10382 case LEU: code = LT; break;
10383 case GEU: code = GT; break;
37409796 10384 default: gcc_unreachable ();
a3170dc6
AH		 10385 }
10386
a3170dc6
AH		 10387 compare_result2 = gen_reg_rtx (CCFPmode);
10388
10389 /* Do the EQ. */
37409796
NS		 10390 switch (op_mode)
10391 {
10392 case SFmode:
10393 cmp = flag_unsafe_math_optimizations
10394 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10395 rs6000_compare_op1)
10396 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10397 rs6000_compare_op1);
10398 break;
10399
10400 case DFmode:
10401 cmp = flag_unsafe_math_optimizations
10402 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10403 rs6000_compare_op1)
10404 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10405 rs6000_compare_op1);
10406 break;
10407
10408 default:
10409 gcc_unreachable ();
10410 }
a3170dc6
AH		 10411 emit_insn (cmp);
10412
a3170dc6 10413 /* OR them together. */
64022b5d
AH		 10414 or_result = gen_reg_rtx (CCFPmode);
10415 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
10416 compare_result2);
a3170dc6
AH		 10417 compare_result = or_result;
10418 code = EQ;
10419 }
10420 else
10421 {
a3170dc6 10422 if (code == NE || code == LTGT)
a3170dc6 10423 code = NE;
423c1189
AH		 10424 else
10425 code = EQ;
a3170dc6
AH		 10426 }
10427
10428 emit_insn (cmp);
10429 }
10430 else
de17c25f
DE		 10431 {
10432 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10433 CLOBBERs to match cmptf_internal2 pattern. */
10434 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10435 && GET_MODE (rs6000_compare_op0) == TFmode
10436 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10437 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10438 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10439 gen_rtvec (9,
10440 gen_rtx_SET (VOIDmode,
10441 compare_result,
10442 gen_rtx_COMPARE (comp_mode,
10443 rs6000_compare_op0,
10444 rs6000_compare_op1)),
10445 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10446 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10447 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10448 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10449 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10450 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10451 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10452 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10453 else
10454 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10455 gen_rtx_COMPARE (comp_mode,
10456 rs6000_compare_op0,
10457 rs6000_compare_op1)));
10458 }
f676971a 10459
ca5adc63 10460 /* Some kinds of FP comparisons need an OR operation;
e7108df9 10461 under flag_finite_math_only we don't bother. */
39a10a29 10462 if (rs6000_compare_fp_p
e7108df9
DE		 10463 && !flag_finite_math_only
10464 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
39a10a29
GK		 10465 && (code == LE || code == GE
10466 || code == UNEQ || code == LTGT
10467 || code == UNGT || code == UNLT))
10468 {
10469 enum rtx_code or1, or2;
10470 rtx or1_rtx, or2_rtx, compare2_rtx;
10471 rtx or_result = gen_reg_rtx (CCEQmode);
f676971a 10472
39a10a29
GK		 10473 switch (code)
10474 {
10475 case LE: or1 = LT; or2 = EQ; break;
10476 case GE: or1 = GT; or2 = EQ; break;
10477 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10478 case LTGT: or1 = LT; or2 = GT; break;
10479 case UNGT: or1 = UNORDERED; or2 = GT; break;
10480 case UNLT: or1 = UNORDERED; or2 = LT; break;
37409796 10481 default: gcc_unreachable ();
39a10a29
GK		 10482 }
10483 validate_condition_mode (or1, comp_mode);
10484 validate_condition_mode (or2, comp_mode);
1c563bed
KH		 10485 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10486 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
39a10a29
GK		 10487 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10488 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10489 const_true_rtx);
10490 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10491
10492 compare_result = or_result;
10493 code = EQ;
10494 }
10495
10496 validate_condition_mode (code, GET_MODE (compare_result));
f676971a 10497
1c563bed 10498 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
39a10a29
GK		 10499}
10500
10501
10502/* Emit the RTL for an sCOND pattern. */
10503
10504void
a2369ed3 10505rs6000_emit_sCOND (enum rtx_code code, rtx result)
39a10a29
GK		 10506{
10507 rtx condition_rtx;
10508 enum machine_mode op_mode;
b7053a3f 10509 enum rtx_code cond_code;
39a10a29
GK		 10510
10511 condition_rtx = rs6000_generate_compare (code);
b7053a3f
GK		 10512 cond_code = GET_CODE (condition_rtx);
10513
423c1189
AH		 10514 if (TARGET_E500 && rs6000_compare_fp_p
10515 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10516 {
10517 rtx t;
10518
10519 PUT_MODE (condition_rtx, SImode);
10520 t = XEXP (condition_rtx, 0);
10521
37409796 10522 gcc_assert (cond_code == NE || cond_code == EQ);
423c1189
AH		 10523
10524 if (cond_code == NE)
64022b5d 10525 emit_insn (gen_e500_flip_gt_bit (t, t));
423c1189 10526
64022b5d 10527 emit_insn (gen_move_from_CR_gt_bit (result, t));
423c1189
AH		 10528 return;
10529 }
10530
b7053a3f
GK		 10531 if (cond_code == NE
10532 || cond_code == GE || cond_code == LE
10533 || cond_code == GEU || cond_code == LEU
10534 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10535 {
10536 rtx not_result = gen_reg_rtx (CCEQmode);
10537 rtx not_op, rev_cond_rtx;
10538 enum machine_mode cc_mode;
f676971a 10539
b7053a3f
GK		 10540 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10541
1c563bed 10542 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
0f4c242b 10543 SImode, XEXP (condition_rtx, 0), const0_rtx);
b7053a3f
GK		 10544 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10545 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10546 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10547 }
39a10a29
GK		 10548
10549 op_mode = GET_MODE (rs6000_compare_op0);
10550 if (op_mode == VOIDmode)
10551 op_mode = GET_MODE (rs6000_compare_op1);
10552
10553 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10554 {
10555 PUT_MODE (condition_rtx, DImode);
10556 convert_move (result, condition_rtx, 0);
10557 }
10558 else
10559 {
10560 PUT_MODE (condition_rtx, SImode);
10561 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10562 }
10563}
10564
39a10a29
GK		 10565/* Emit a branch of kind CODE to location LOC. */
10566
10567void
a2369ed3 10568rs6000_emit_cbranch (enum rtx_code code, rtx loc)
39a10a29
GK		 10569{
10570 rtx condition_rtx, loc_ref;
10571
10572 condition_rtx = rs6000_generate_compare (code);
10573 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10574 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10575 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10576 loc_ref, pc_rtx)));
10577}
10578
12a4e8c5
GK		 10579/* Return the string to output a conditional branch to LABEL, which is
10580 the operand number of the label, or -1 if the branch is really a
f676971a 10581 conditional return.
12a4e8c5
GK		 10582
10583 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10584 condition code register and its mode specifies what kind of
10585 comparison we made.
10586
a0ab749a 10587 REVERSED is nonzero if we should reverse the sense of the comparison.
12a4e8c5
GK		 10588
10589 INSN is the insn. */
10590
10591char *
a2369ed3 10592output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12a4e8c5
GK		 10593{
10594 static char string[64];
10595 enum rtx_code code = GET_CODE (op);
10596 rtx cc_reg = XEXP (op, 0);
10597 enum machine_mode mode = GET_MODE (cc_reg);
10598 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
39a10a29 10599 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12a4e8c5
GK		 10600 int really_reversed = reversed ^ need_longbranch;
10601 char *s = string;
10602 const char *ccode;
10603 const char *pred;
10604 rtx note;
10605
39a10a29
GK		 10606 validate_condition_mode (code, mode);
10607
10608 /* Work out which way this really branches. We could use
10609 reverse_condition_maybe_unordered here always but this
10610 makes the resulting assembler clearer. */
12a4e8c5 10611 if (really_reversed)
de40e1df
DJ		 10612 {
10613 /* Reversal of FP compares takes care -- an ordered compare
10614 becomes an unordered compare and vice versa. */
10615 if (mode == CCFPmode)
10616 code = reverse_condition_maybe_unordered (code);
10617 else
10618 code = reverse_condition (code);
10619 }
12a4e8c5 10620
993f19a8 10621 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
a3170dc6
AH		 10622 {
10623 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10624 to the GT bit. */
37409796
NS		 10625 switch (code)
10626 {
10627 case EQ:
10628 /* Opposite of GT. */
10629 code = GT;
10630 break;
10631
10632 case NE:
10633 code = UNLE;
10634 break;
10635
10636 default:
10637 gcc_unreachable ();
10638 }
a3170dc6
AH		 10639 }
10640
39a10a29 10641 switch (code)
12a4e8c5
GK		 10642 {
10643 /* Not all of these are actually distinct opcodes, but
10644 we distinguish them for clarity of the resulting assembler. */
50a0b056
GK		 10645 case NE: case LTGT:
10646 ccode = "ne"; break;
10647 case EQ: case UNEQ:
10648 ccode = "eq"; break;
f676971a 10649 case GE: case GEU:
50a0b056 10650 ccode = "ge"; break;
f676971a 10651 case GT: case GTU: case UNGT:
50a0b056 10652 ccode = "gt"; break;
f676971a 10653 case LE: case LEU:
50a0b056 10654 ccode = "le"; break;
f676971a 10655 case LT: case LTU: case UNLT:
50a0b056 10656 ccode = "lt"; break;
12a4e8c5
GK		 10657 case UNORDERED: ccode = "un"; break;
10658 case ORDERED: ccode = "nu"; break;
10659 case UNGE: ccode = "nl"; break;
10660 case UNLE: ccode = "ng"; break;
10661 default:
37409796 10662 gcc_unreachable ();
12a4e8c5 10663 }
f676971a
EC		 10664
10665 /* Maybe we have a guess as to how likely the branch is.
94a54f47 10666 The old mnemonics don't have a way to specify this information. */
f4857b9b 10667 pred = "";
12a4e8c5
GK		 10668 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10669 if (note != NULL_RTX)
10670 {
10671 /* PROB is the difference from 50%. */
10672 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
f4857b9b
AM		 10673
10674 /* Only hint for highly probable/improbable branches on newer
10675 cpus as static prediction overrides processor dynamic
10676 prediction. For older cpus we may as well always hint, but
10677 assume not taken for branches that are very close to 50% as a
10678 mispredicted taken branch is more expensive than a
f676971a 10679 mispredicted not-taken branch. */
ec507f2d 10680 if (rs6000_always_hint
f4857b9b
AM		 10681 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10682 {
10683 if (abs (prob) > REG_BR_PROB_BASE / 20
10684 && ((prob > 0) ^ need_longbranch))
c4ad648e 10685 pred = "+";
f4857b9b
AM		 10686 else
10687 pred = "-";
10688 }
12a4e8c5 10689 }
12a4e8c5
GK		 10690
10691 if (label == NULL)
94a54f47 10692 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12a4e8c5 10693 else
94a54f47 10694 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12a4e8c5 10695
37c67319 10696 /* We need to escape any '%' characters in the reg_names string.
a3c9585f 10697 Assume they'd only be the first character.... */
37c67319
GK		 10698 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10699 *s++ = '%';
94a54f47 10700 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12a4e8c5
GK		 10701
10702 if (label != NULL)
10703 {
10704 /* If the branch distance was too far, we may have to use an
10705 unconditional branch to go the distance. */
10706 if (need_longbranch)
44518ddd 10707 s += sprintf (s, ",$+8\n\tb %s", label);
12a4e8c5
GK		 10708 else
10709 s += sprintf (s, ",%s", label);
10710 }
10711
10712 return string;
10713}
50a0b056 10714
64022b5d 10715/* Return the string to flip the GT bit on a CR. */
423c1189 10716char *
64022b5d 10717output_e500_flip_gt_bit (rtx dst, rtx src)
423c1189
AH		 10718{
10719 static char string[64];
10720 int a, b;
10721
37409796
NS		 10722 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
10723 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
423c1189 10724
64022b5d
AH		 10725 /* GT bit. */
10726 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10727 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
423c1189
AH		 10728
10729 sprintf (string, "crnot %d,%d", a, b);
10730 return string;
10731}
10732
21213b4c
DP		 10733/* Return insn index for the vector compare instruction for given CODE,
10734 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10735 not available. */
10736
10737static int
94ff898d 10738get_vec_cmp_insn (enum rtx_code code,
21213b4c
DP		 10739 enum machine_mode dest_mode,
10740 enum machine_mode op_mode)
10741{
10742 if (!TARGET_ALTIVEC)
10743 return INSN_NOT_AVAILABLE;
10744
10745 switch (code)
10746 {
10747 case EQ:
10748 if (dest_mode == V16QImode && op_mode == V16QImode)
10749 return UNSPEC_VCMPEQUB;
10750 if (dest_mode == V8HImode && op_mode == V8HImode)
10751 return UNSPEC_VCMPEQUH;
10752 if (dest_mode == V4SImode && op_mode == V4SImode)
10753 return UNSPEC_VCMPEQUW;
10754 if (dest_mode == V4SImode && op_mode == V4SFmode)
10755 return UNSPEC_VCMPEQFP;
10756 break;
10757 case GE:
10758 if (dest_mode == V4SImode && op_mode == V4SFmode)
10759 return UNSPEC_VCMPGEFP;
10760 case GT:
10761 if (dest_mode == V16QImode && op_mode == V16QImode)
10762 return UNSPEC_VCMPGTSB;
10763 if (dest_mode == V8HImode && op_mode == V8HImode)
10764 return UNSPEC_VCMPGTSH;
10765 if (dest_mode == V4SImode && op_mode == V4SImode)
10766 return UNSPEC_VCMPGTSW;
10767 if (dest_mode == V4SImode && op_mode == V4SFmode)
10768 return UNSPEC_VCMPGTFP;
10769 break;
10770 case GTU:
10771 if (dest_mode == V16QImode && op_mode == V16QImode)
10772 return UNSPEC_VCMPGTUB;
10773 if (dest_mode == V8HImode && op_mode == V8HImode)
10774 return UNSPEC_VCMPGTUH;
10775 if (dest_mode == V4SImode && op_mode == V4SImode)
10776 return UNSPEC_VCMPGTUW;
10777 break;
10778 default:
10779 break;
10780 }
10781 return INSN_NOT_AVAILABLE;
10782}
10783
10784/* Emit vector compare for operands OP0 and OP1 using code RCODE.
10785 DMODE is expected destination mode. This is a recursive function. */
10786
10787static rtx
10788rs6000_emit_vector_compare (enum rtx_code rcode,
10789 rtx op0, rtx op1,
10790 enum machine_mode dmode)
10791{
10792 int vec_cmp_insn;
10793 rtx mask;
10794 enum machine_mode dest_mode;
10795 enum machine_mode op_mode = GET_MODE (op1);
10796
37409796
NS		 10797 gcc_assert (TARGET_ALTIVEC);
10798 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
21213b4c
DP		 10799
10800 /* Floating point vector compare instructions uses destination V4SImode.
10801 Move destination to appropriate mode later. */
10802 if (dmode == V4SFmode)
10803 dest_mode = V4SImode;
10804 else
10805 dest_mode = dmode;
10806
10807 mask = gen_reg_rtx (dest_mode);
10808 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10809
10810 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10811 {
10812 bool swap_operands = false;
10813 bool try_again = false;
10814 switch (rcode)
10815 {
10816 case LT:
10817 rcode = GT;
10818 swap_operands = true;
10819 try_again = true;
10820 break;
10821 case LTU:
10822 rcode = GTU;
10823 swap_operands = true;
10824 try_again = true;
10825 break;
10826 case NE:
10827 /* Treat A != B as ~(A==B). */
10828 {
10829 enum insn_code nor_code;
10830 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10831 dest_mode);
94ff898d 10832
21213b4c 10833 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
37409796 10834 gcc_assert (nor_code != CODE_FOR_nothing);
21213b4c
DP		 10835 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10836
10837 if (dmode != dest_mode)
10838 {
10839 rtx temp = gen_reg_rtx (dest_mode);
10840 convert_move (temp, mask, 0);
10841 return temp;
10842 }
10843 return mask;
10844 }
10845 break;
10846 case GE:
10847 case GEU:
10848 case LE:
10849 case LEU:
10850 /* Try GT/GTU/LT/LTU OR EQ */
10851 {
10852 rtx c_rtx, eq_rtx;
10853 enum insn_code ior_code;
10854 enum rtx_code new_code;
10855
37409796
NS		 10856 switch (rcode)
10857 {
10858 case GE:
10859 new_code = GT;
10860 break;
10861
10862 case GEU:
10863 new_code = GTU;
10864 break;
10865
10866 case LE:
10867 new_code = LT;
10868 break;
10869
10870 case LEU:
10871 new_code = LTU;
10872 break;
10873
10874 default:
10875 gcc_unreachable ();
10876 }
21213b4c
DP		 10877
10878 c_rtx = rs6000_emit_vector_compare (new_code,
10879 op0, op1, dest_mode);
10880 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10881 dest_mode);
10882
10883 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
37409796 10884 gcc_assert (ior_code != CODE_FOR_nothing);
21213b4c
DP		 10885 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
10886 if (dmode != dest_mode)
10887 {
10888 rtx temp = gen_reg_rtx (dest_mode);
10889 convert_move (temp, mask, 0);
10890 return temp;
10891 }
10892 return mask;
10893 }
10894 break;
10895 default:
37409796 10896 gcc_unreachable ();
21213b4c
DP		 10897 }
10898
10899 if (try_again)
10900 {
10901 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
37409796
NS		 10902 /* You only get two chances. */
10903 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
21213b4c
DP		 10904 }
10905
10906 if (swap_operands)
10907 {
10908 rtx tmp;
10909 tmp = op0;
10910 op0 = op1;
10911 op1 = tmp;
10912 }
10913 }
10914
915167f5
GK		 10915 emit_insn (gen_rtx_SET (VOIDmode, mask,
10916 gen_rtx_UNSPEC (dest_mode,
10917 gen_rtvec (2, op0, op1),
10918 vec_cmp_insn)));
21213b4c
DP		 10919 if (dmode != dest_mode)
10920 {
10921 rtx temp = gen_reg_rtx (dest_mode);
10922 convert_move (temp, mask, 0);
10923 return temp;
10924 }
10925 return mask;
10926}
10927
10928/* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
10929 valid insn doesn exist for given mode. */
10930
10931static int
10932get_vsel_insn (enum machine_mode mode)
10933{
10934 switch (mode)
10935 {
10936 case V4SImode:
10937 return UNSPEC_VSEL4SI;
10938 break;
10939 case V4SFmode:
10940 return UNSPEC_VSEL4SF;
10941 break;
10942 case V8HImode:
10943 return UNSPEC_VSEL8HI;
10944 break;
10945 case V16QImode:
10946 return UNSPEC_VSEL16QI;
10947 break;
10948 default:
10949 return INSN_NOT_AVAILABLE;
10950 break;
10951 }
10952 return INSN_NOT_AVAILABLE;
10953}
10954
10955/* Emit vector select insn where DEST is destination using
10956 operands OP1, OP2 and MASK. */
10957
10958static void
10959rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
10960{
10961 rtx t, temp;
10962 enum machine_mode dest_mode = GET_MODE (dest);
10963 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
10964
10965 temp = gen_reg_rtx (dest_mode);
94ff898d 10966
19f1ebc7
DP		 10967 /* For each vector element, select op1 when mask is 1 otherwise
10968 select op2. */
915167f5
GK		 10969 t = gen_rtx_SET (VOIDmode, temp,
10970 gen_rtx_UNSPEC (dest_mode,
10971 gen_rtvec (3, op2, op1, mask),
10972 vsel_insn_index));
21213b4c
DP		 10973 emit_insn (t);
10974 emit_move_insn (dest, temp);
10975 return;
10976}
10977
94ff898d 10978/* Emit vector conditional expression.
21213b4c
DP		 10979 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
10980 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
10981
10982int
10983rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
10984 rtx cond, rtx cc_op0, rtx cc_op1)
10985{
10986 enum machine_mode dest_mode = GET_MODE (dest);
10987 enum rtx_code rcode = GET_CODE (cond);
10988 rtx mask;
10989
10990 if (!TARGET_ALTIVEC)
10991 return 0;
10992
10993 /* Get the vector mask for the given relational operations. */
10994 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
10995
10996 rs6000_emit_vector_select (dest, op1, op2, mask);
10997
10998 return 1;
10999}
11000
50a0b056
GK		 11001/* Emit a conditional move: move TRUE_COND to DEST if OP of the
11002 operands of the last comparison is nonzero/true, FALSE_COND if it
11003 is zero/false. Return 0 if the hardware has no such operation. */
a4f6c312 11004
50a0b056 11005int
a2369ed3 11006rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
50a0b056
GK		 11007{
11008 enum rtx_code code = GET_CODE (op);
11009 rtx op0 = rs6000_compare_op0;
11010 rtx op1 = rs6000_compare_op1;
11011 REAL_VALUE_TYPE c1;
3148ad6d
DJ		 11012 enum machine_mode compare_mode = GET_MODE (op0);
11013 enum machine_mode result_mode = GET_MODE (dest);
50a0b056 11014 rtx temp;
add2402e 11015 bool is_against_zero;
50a0b056 11016
a3c9585f 11017 /* These modes should always match. */
a3170dc6
AH		 11018 if (GET_MODE (op1) != compare_mode
11019 /* In the isel case however, we can use a compare immediate, so
11020 op1 may be a small constant. */
11021 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
3148ad6d 11022 return 0;
178c3eff 11023 if (GET_MODE (true_cond) != result_mode)
3148ad6d 11024 return 0;
178c3eff 11025 if (GET_MODE (false_cond) != result_mode)
3148ad6d
DJ		 11026 return 0;
11027
50a0b056 11028 /* First, work out if the hardware can do this at all, or
a3c9585f 11029 if it's too slow.... */
50a0b056 11030 if (! rs6000_compare_fp_p)
a3170dc6
AH		 11031 {
11032 if (TARGET_ISEL)
11033 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11034 return 0;
11035 }
fef98bf2
AH		 11036 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11037 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11038 return 0;
50a0b056 11039
add2402e 11040 is_against_zero = op1 == CONST0_RTX (compare_mode);
94ff898d 11041
add2402e
GK		 11042 /* A floating-point subtract might overflow, underflow, or produce
11043 an inexact result, thus changing the floating-point flags, so it
11044 can't be generated if we care about that. It's safe if one side
11045 of the construct is zero, since then no subtract will be
11046 generated. */
11047 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11048 && flag_trapping_math && ! is_against_zero)
11049 return 0;
11050
50a0b056
GK		 11051 /* Eliminate half of the comparisons by switching operands, this
11052 makes the remaining code simpler. */
11053 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
bc9ec0e0 11054 || code == LTGT || code == LT || code == UNLE)
50a0b056
GK		 11055 {
11056 code = reverse_condition_maybe_unordered (code);
11057 temp = true_cond;
11058 true_cond = false_cond;
11059 false_cond = temp;
11060 }
11061
11062 /* UNEQ and LTGT take four instructions for a comparison with zero,
11063 it'll probably be faster to use a branch here too. */
bc9ec0e0 11064 if (code == UNEQ && HONOR_NANS (compare_mode))
50a0b056 11065 return 0;
f676971a 11066
50a0b056
GK		 11067 if (GET_CODE (op1) == CONST_DOUBLE)
11068 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
f676971a 11069
b6d08ca1 11070 /* We're going to try to implement comparisons by performing
50a0b056
GK		 11071 a subtract, then comparing against zero. Unfortunately,
11072 Inf - Inf is NaN which is not zero, and so if we don't
27d30956 11073 know that the operand is finite and the comparison
50a0b056 11074 would treat EQ different to UNORDERED, we can't do it. */
bc9ec0e0 11075 if (HONOR_INFINITIES (compare_mode)
50a0b056 11076 && code != GT && code != UNGE
045572c7 11077 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
50a0b056
GK		 11078 /* Constructs of the form (a OP b ? a : b) are safe. */
11079 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
f676971a 11080 || (! rtx_equal_p (op0, true_cond)
50a0b056
GK		 11081 && ! rtx_equal_p (op1, true_cond))))
11082 return 0;
add2402e 11083
50a0b056
GK		 11084 /* At this point we know we can use fsel. */
11085
11086 /* Reduce the comparison to a comparison against zero. */
add2402e
GK		 11087 if (! is_against_zero)
11088 {
11089 temp = gen_reg_rtx (compare_mode);
11090 emit_insn (gen_rtx_SET (VOIDmode, temp,
11091 gen_rtx_MINUS (compare_mode, op0, op1)));
11092 op0 = temp;
11093 op1 = CONST0_RTX (compare_mode);
11094 }
50a0b056
GK		 11095
11096 /* If we don't care about NaNs we can reduce some of the comparisons
11097 down to faster ones. */
bc9ec0e0 11098 if (! HONOR_NANS (compare_mode))
50a0b056
GK		 11099 switch (code)
11100 {
11101 case GT:
11102 code = LE;
11103 temp = true_cond;
11104 true_cond = false_cond;
11105 false_cond = temp;
11106 break;
11107 case UNGE:
11108 code = GE;
11109 break;
11110 case UNEQ:
11111 code = EQ;
11112 break;
11113 default:
11114 break;
11115 }
11116
11117 /* Now, reduce everything down to a GE. */
11118 switch (code)
11119 {
11120 case GE:
11121 break;
11122
11123 case LE:
3148ad6d
DJ		 11124 temp = gen_reg_rtx (compare_mode);
11125 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 11126 op0 = temp;
11127 break;
11128
11129 case ORDERED:
3148ad6d
DJ		 11130 temp = gen_reg_rtx (compare_mode);
11131 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
50a0b056
GK		 11132 op0 = temp;
11133 break;
11134
11135 case EQ:
3148ad6d 11136 temp = gen_reg_rtx (compare_mode);
f676971a 11137 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d
DJ		 11138 gen_rtx_NEG (compare_mode,
11139 gen_rtx_ABS (compare_mode, op0))));
50a0b056
GK		 11140 op0 = temp;
11141 break;
11142
11143 case UNGE:
bc9ec0e0 11144 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
3148ad6d 11145 temp = gen_reg_rtx (result_mode);
50a0b056 11146 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d 11147 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 11148 gen_rtx_GE (VOIDmode,
11149 op0, op1),
11150 true_cond, false_cond)));
bc9ec0e0
GK		 11151 false_cond = true_cond;
11152 true_cond = temp;
50a0b056 11153
3148ad6d
DJ		 11154 temp = gen_reg_rtx (compare_mode);
11155 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 11156 op0 = temp;
11157 break;
11158
11159 case GT:
bc9ec0e0 11160 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
3148ad6d 11161 temp = gen_reg_rtx (result_mode);
50a0b056 11162 emit_insn (gen_rtx_SET (VOIDmode, temp,
f676971a 11163 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 11164 gen_rtx_GE (VOIDmode,
11165 op0, op1),
11166 true_cond, false_cond)));
bc9ec0e0
GK		 11167 true_cond = false_cond;
11168 false_cond = temp;
50a0b056 11169
3148ad6d
DJ		 11170 temp = gen_reg_rtx (compare_mode);
11171 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 11172 op0 = temp;
11173 break;
11174
11175 default:
37409796 11176 gcc_unreachable ();
50a0b056
GK		 11177 }
11178
11179 emit_insn (gen_rtx_SET (VOIDmode, dest,
3148ad6d 11180 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 11181 gen_rtx_GE (VOIDmode,
11182 op0, op1),
11183 true_cond, false_cond)));
11184 return 1;
11185}
11186
a3170dc6
AH		 11187/* Same as above, but for ints (isel). */
11188
11189static int
a2369ed3 11190rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
a3170dc6
AH		 11191{
11192 rtx condition_rtx, cr;
11193
11194 /* All isel implementations thus far are 32-bits. */
11195 if (GET_MODE (rs6000_compare_op0) != SImode)
11196 return 0;
11197
11198 /* We still have to do the compare, because isel doesn't do a
11199 compare, it just looks at the CRx bits set by a previous compare
11200 instruction. */
11201 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11202 cr = XEXP (condition_rtx, 0);
11203
11204 if (GET_MODE (cr) == CCmode)
11205 emit_insn (gen_isel_signed (dest, condition_rtx,
11206 true_cond, false_cond, cr));
11207 else
11208 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11209 true_cond, false_cond, cr));
11210
11211 return 1;
11212}
11213
11214const char *
a2369ed3 11215output_isel (rtx *operands)
a3170dc6
AH		 11216{
11217 enum rtx_code code;
11218
11219 code = GET_CODE (operands[1]);
11220 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11221 {
11222 PUT_CODE (operands[1], reverse_condition (code));
11223 return "isel %0,%3,%2,%j1";
11224 }
11225 else
11226 return "isel %0,%2,%3,%j1";
11227}
11228
50a0b056 11229void
a2369ed3 11230rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
50a0b056
GK		 11231{
11232 enum machine_mode mode = GET_MODE (op0);
5dc8d536 11233 enum rtx_code c;
50a0b056 11234 rtx target;
5dc8d536
AH		 11235
11236 if (code == SMAX || code == SMIN)
11237 c = GE;
11238 else
11239 c = GEU;
11240
50a0b056 11241 if (code == SMAX || code == UMAX)
f676971a 11242 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056
GK		 11243 op0, op1, mode, 0);
11244 else
f676971a 11245 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056 11246 op1, op0, mode, 0);
37409796 11247 gcc_assert (target);
50a0b056
GK		 11248 if (target != dest)
11249 emit_move_insn (dest, target);
11250}
46c07df8 11251
915167f5
GK		 11252/* Emit instructions to perform a load-reserved/store-conditional operation.
11253 The operation performed is an atomic
11254 (set M (CODE:MODE M OP))
11255 If not NULL, BEFORE is atomically set to M before the operation, and
11256 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11257 If SYNC_P then a memory barrier is emitted before the operation.
11258 Either OP or M may be wrapped in a NOT operation. */
11259
11260void
11261rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11262 rtx m, rtx op, rtx before_param, rtx after_param,
11263 bool sync_p)
11264{
11265 enum machine_mode used_mode;
11266 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11267 rtx used_m;
11268 rtvec vec;
11269 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11270 rtx shift = NULL_RTX;
11271
11272 if (sync_p)
11273 emit_insn (gen_memory_barrier ());
11274
11275 if (GET_CODE (m) == NOT)
11276 used_m = XEXP (m, 0);
11277 else
11278 used_m = m;
11279
11280 /* If this is smaller than SImode, we'll have to use SImode with
11281 adjustments. */
11282 if (mode == QImode || mode == HImode)
11283 {
11284 rtx newop, oldop;
11285
11286 if (MEM_ALIGN (used_m) >= 32)
11287 {
11288 int ishift = 0;
11289 if (BYTES_BIG_ENDIAN)
11290 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
11291
11292 shift = GEN_INT (ishift);
11293 }
11294 else
11295 {
11296 rtx addrSI, aligned_addr;
11297
11298 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
11299 XEXP (used_m, 0)));
11300 shift = gen_reg_rtx (SImode);
11301
11302 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
11303 GEN_INT (0x18)));
11304
11305 aligned_addr = expand_binop (Pmode, and_optab,
11306 XEXP (used_m, 0),
11307 GEN_INT (-4), NULL_RTX,
11308 1, OPTAB_LIB_WIDEN);
11309 used_m = change_address (used_m, SImode, aligned_addr);
11310 set_mem_align (used_m, 32);
11311 /* It's safe to keep the old alias set of USED_M, because
11312 the operation is atomic and only affects the original
11313 USED_M. */
11314 if (GET_CODE (m) == NOT)
11315 m = gen_rtx_NOT (SImode, used_m);
11316 else
11317 m = used_m;
11318 }
11319
11320 if (GET_CODE (op) == NOT)
11321 {
11322 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
11323 oldop = gen_rtx_NOT (SImode, oldop);
11324 }
11325 else
11326 oldop = lowpart_subreg (SImode, op, mode);
11327 switch (code)
11328 {
11329 case IOR:
11330 case XOR:
11331 newop = expand_binop (SImode, and_optab,
11332 oldop, GEN_INT (imask), NULL_RTX,
11333 1, OPTAB_LIB_WIDEN);
11334 emit_insn (gen_ashlsi3 (newop, newop, shift));
11335 break;
11336
11337 case AND:
11338 newop = expand_binop (SImode, ior_optab,
11339 oldop, GEN_INT (~imask), NULL_RTX,
11340 1, OPTAB_LIB_WIDEN);
11341 emit_insn (gen_ashlsi3 (newop, newop, shift));
11342 break;
11343
11344 case PLUS:
11345 {
11346 rtx mask;
11347
11348 newop = expand_binop (SImode, and_optab,
11349 oldop, GEN_INT (imask), NULL_RTX,
11350 1, OPTAB_LIB_WIDEN);
11351 emit_insn (gen_ashlsi3 (newop, newop, shift));
11352
11353 mask = gen_reg_rtx (SImode);
11354 emit_move_insn (mask, GEN_INT (imask));
11355 emit_insn (gen_ashlsi3 (mask, mask, shift));
11356
11357 newop = gen_rtx_AND (SImode, gen_rtx_PLUS (SImode, m, newop),
11358 mask);
11359 newop = gen_rtx_IOR (SImode, newop,
11360 gen_rtx_AND (SImode,
11361 gen_rtx_NOT (SImode, mask),
11362 m));
11363 break;
11364 }
11365
11366 default:
11367 gcc_unreachable ();
11368 }
11369
11370 op = newop;
11371 used_mode = SImode;
11372 before = gen_reg_rtx (used_mode);
11373 after = gen_reg_rtx (used_mode);
11374 }
11375 else
11376 {
11377 used_mode = mode;
11378 before = before_param;
11379 after = after_param;
11380
11381 if (before == NULL_RTX)
11382 before = gen_reg_rtx (used_mode);
11383 if (after == NULL_RTX)
11384 after = gen_reg_rtx (used_mode);
11385 }
11386
11387 if (code == PLUS && used_mode != mode)
11388 the_op = op; /* Computed above. */
11389 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
11390 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
11391 else
11392 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
11393
11394 set_after = gen_rtx_SET (VOIDmode, after, the_op);
11395 set_before = gen_rtx_SET (VOIDmode, before, used_m);
11396 set_atomic = gen_rtx_SET (VOIDmode, used_m,
11397 gen_rtx_UNSPEC (used_mode, gen_rtvec (1, the_op),
11398 UNSPEC_SYNC_OP));
11399 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
11400
11401 if (code == PLUS && used_mode != mode)
11402 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
11403 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
11404 else
11405 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
11406 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
11407
11408 /* Shift and mask the return values properly. */
11409 if (used_mode != mode && before_param)
11410 {
11411 emit_insn (gen_lshrsi3 (before, before, shift));
11412 convert_move (before_param, before, 1);
11413 }
11414
11415 if (used_mode != mode && after_param)
11416 {
11417 emit_insn (gen_lshrsi3 (after, after, shift));
11418 convert_move (after_param, after, 1);
11419 }
11420
11421 /* The previous sequence will end with a branch that's dependent on
11422 the conditional store, so placing an isync will ensure that no
11423 other instructions (especially, no load or store instructions)
11424 can start before the atomic operation completes. */
11425 if (sync_p)
11426 emit_insn (gen_isync ());
11427}
11428
a9baceb1
GK		 11429/* Emit instructions to move SRC to DST. Called by splitters for
11430 multi-register moves. It will emit at most one instruction for
11431 each register that is accessed; that is, it won't emit li/lis pairs
11432 (or equivalent for 64-bit code). One of SRC or DST must be a hard
11433 register. */
46c07df8 11434
46c07df8 11435void
a9baceb1 11436rs6000_split_multireg_move (rtx dst, rtx src)
46c07df8 11437{
a9baceb1
GK		 11438 /* The register number of the first register being moved. */
11439 int reg;
11440 /* The mode that is to be moved. */
11441 enum machine_mode mode;
11442 /* The mode that the move is being done in, and its size. */
11443 enum machine_mode reg_mode;
11444 int reg_mode_size;
11445 /* The number of registers that will be moved. */
11446 int nregs;
11447
11448 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
11449 mode = GET_MODE (dst);
11450 nregs = HARD_REGNO_NREGS (reg, mode);
11451 if (FP_REGNO_P (reg))
11452 reg_mode = DFmode;
11453 else if (ALTIVEC_REGNO_P (reg))
11454 reg_mode = V16QImode;
11455 else
11456 reg_mode = word_mode;
11457 reg_mode_size = GET_MODE_SIZE (reg_mode);
f676971a 11458
37409796 11459 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
f676971a 11460
a9baceb1
GK		 11461 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11462 {
11463 /* Move register range backwards, if we might have destructive
11464 overlap. */
11465 int i;
11466 for (i = nregs - 1; i >= 0; i--)
f676971a 11467 emit_insn (gen_rtx_SET (VOIDmode,
a9baceb1
GK		 11468 simplify_gen_subreg (reg_mode, dst, mode,
11469 i * reg_mode_size),
11470 simplify_gen_subreg (reg_mode, src, mode,
11471 i * reg_mode_size)));
11472 }
46c07df8
HP		 11473 else
11474 {
a9baceb1
GK		 11475 int i;
11476 int j = -1;
11477 bool used_update = false;
46c07df8 11478
c1e55850 11479 if (MEM_P (src) && INT_REGNO_P (reg))
c4ad648e
AM		 11480 {
11481 rtx breg;
3a1f863f 11482
a9baceb1
GK		 11483 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11484 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
3a1f863f
DE		 11485 {
11486 rtx delta_rtx;
a9baceb1 11487 breg = XEXP (XEXP (src, 0), 0);
c4ad648e
AM		 11488 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11489 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11490 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
a9baceb1
GK		 11491 emit_insn (TARGET_32BIT
11492 ? gen_addsi3 (breg, breg, delta_rtx)
11493 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11494 src = gen_rtx_MEM (mode, breg);
11495 }
c1e55850
GK		 11496 else if (! offsettable_memref_p (src))
11497 {
11498 rtx newsrc, basereg;
11499 basereg = gen_rtx_REG (Pmode, reg);
11500 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11501 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11502 MEM_COPY_ATTRIBUTES (newsrc, src);
11503 src = newsrc;
11504 }
3a1f863f 11505
0423421f
AM		 11506 breg = XEXP (src, 0);
11507 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11508 breg = XEXP (breg, 0);
11509
11510 /* If the base register we are using to address memory is
11511 also a destination reg, then change that register last. */
11512 if (REG_P (breg)
11513 && REGNO (breg) >= REGNO (dst)
3a1f863f
DE		 11514 && REGNO (breg) < REGNO (dst) + nregs)
11515 j = REGNO (breg) - REGNO (dst);
c4ad648e 11516 }
46c07df8 11517
a9baceb1 11518 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
3a1f863f
DE		 11519 {
11520 rtx breg;
11521
a9baceb1
GK		 11522 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11523 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
3a1f863f
DE		 11524 {
11525 rtx delta_rtx;
a9baceb1 11526 breg = XEXP (XEXP (dst, 0), 0);
c4ad648e
AM		 11527 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11528 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11529 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
3a1f863f
DE		 11530
11531 /* We have to update the breg before doing the store.
11532 Use store with update, if available. */
11533
11534 if (TARGET_UPDATE)
11535 {
a9baceb1 11536 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
c4ad648e
AM		 11537 emit_insn (TARGET_32BIT
11538 ? (TARGET_POWERPC64
11539 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11540 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11541 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
a9baceb1 11542 used_update = true;
3a1f863f
DE		 11543 }
11544 else
a9baceb1
GK		 11545 emit_insn (TARGET_32BIT
11546 ? gen_addsi3 (breg, breg, delta_rtx)
11547 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11548 dst = gen_rtx_MEM (mode, breg);
11549 }
37409796
NS		 11550 else
11551 gcc_assert (offsettable_memref_p (dst));
3a1f863f
DE		 11552 }
11553
46c07df8 11554 for (i = 0; i < nregs; i++)
f676971a 11555 {
3a1f863f
DE		 11556 /* Calculate index to next subword. */
11557 ++j;
f676971a 11558 if (j == nregs)
3a1f863f 11559 j = 0;
46c07df8 11560
112cdef5 11561 /* If compiler already emitted move of first word by
a9baceb1 11562 store with update, no need to do anything. */
3a1f863f 11563 if (j == 0 && used_update)
a9baceb1 11564 continue;
f676971a 11565
a9baceb1
GK		 11566 emit_insn (gen_rtx_SET (VOIDmode,
11567 simplify_gen_subreg (reg_mode, dst, mode,
11568 j * reg_mode_size),
11569 simplify_gen_subreg (reg_mode, src, mode,
11570 j * reg_mode_size)));
3a1f863f 11571 }
46c07df8
HP		 11572 }
11573}
11574
12a4e8c5 11575\f
a4f6c312
SS		 11576/* This page contains routines that are used to determine what the
11577 function prologue and epilogue code will do and write them out. */
9878760c 11578
a4f6c312
SS		 11579/* Return the first fixed-point register that is required to be
11580 saved. 32 if none. */
9878760c
RK		 11581
11582int
863d938c 11583first_reg_to_save (void)
9878760c
RK		 11584{
11585 int first_reg;
11586
11587 /* Find lowest numbered live register. */
11588 for (first_reg = 13; first_reg <= 31; first_reg++)
f676971a 11589 if (regs_ever_live[first_reg]
a38d360d 11590 && (! call_used_regs[first_reg]
1db02437 11591 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 11592 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
b4db40bf
JJ		 11593 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11594 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
9878760c
RK		 11595 break;
11596
ee890fe2 11597#if TARGET_MACHO
93638d7a
AM		 11598 if (flag_pic
11599 && current_function_uses_pic_offset_table
11600 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
1db02437 11601 return RS6000_PIC_OFFSET_TABLE_REGNUM;
ee890fe2
SS		 11602#endif
11603
9878760c
RK		 11604 return first_reg;
11605}
11606
11607/* Similar, for FP regs. */
11608
11609int
863d938c 11610first_fp_reg_to_save (void)
9878760c
RK		 11611{
11612 int first_reg;
11613
11614 /* Find lowest numbered live register. */
11615 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11616 if (regs_ever_live[first_reg])
11617 break;
11618
11619 return first_reg;
11620}
00b960c7
AH		 11621
11622/* Similar, for AltiVec regs. */
11623
11624static int
863d938c 11625first_altivec_reg_to_save (void)
00b960c7
AH		 11626{
11627 int i;
11628
11629 /* Stack frame remains as is unless we are in AltiVec ABI. */
11630 if (! TARGET_ALTIVEC_ABI)
11631 return LAST_ALTIVEC_REGNO + 1;
11632
11633 /* Find lowest numbered live register. */
11634 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11635 if (regs_ever_live[i])
11636 break;
11637
11638 return i;
11639}
11640
11641/* Return a 32-bit mask of the AltiVec registers we need to set in
11642 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11643 the 32-bit word is 0. */
11644
11645static unsigned int
863d938c 11646compute_vrsave_mask (void)
00b960c7
AH		 11647{
11648 unsigned int i, mask = 0;
11649
11650 /* First, find out if we use _any_ altivec registers. */
11651 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11652 if (regs_ever_live[i])
11653 mask |= ALTIVEC_REG_BIT (i);
11654
11655 if (mask == 0)
11656 return mask;
11657
00b960c7
AH		 11658 /* Next, remove the argument registers from the set. These must
11659 be in the VRSAVE mask set by the caller, so we don't need to add
11660 them in again. More importantly, the mask we compute here is
11661 used to generate CLOBBERs in the set_vrsave insn, and we do not
11662 wish the argument registers to die. */
a6cf80f2 11663 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
00b960c7
AH		 11664 mask &= ~ALTIVEC_REG_BIT (i);
11665
11666 /* Similarly, remove the return value from the set. */
11667 {
11668 bool yes = false;
11669 diddle_return_value (is_altivec_return_reg, &yes);
11670 if (yes)
11671 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11672 }
11673
11674 return mask;
11675}
11676
d62294f5 11677/* For a very restricted set of circumstances, we can cut down the
f57fe068
AM		 11678 size of prologues/epilogues by calling our own save/restore-the-world
11679 routines. */
d62294f5
FJ		 11680
11681static void
f57fe068
AM		 11682compute_save_world_info (rs6000_stack_t *info_ptr)
11683{
11684 info_ptr->world_save_p = 1;
11685 info_ptr->world_save_p
11686 = (WORLD_SAVE_P (info_ptr)
11687 && DEFAULT_ABI == ABI_DARWIN
11688 && ! (current_function_calls_setjmp && flag_exceptions)
11689 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11690 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11691 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11692 && info_ptr->cr_save_p);
f676971a 11693
d62294f5
FJ		 11694 /* This will not work in conjunction with sibcalls. Make sure there
11695 are none. (This check is expensive, but seldom executed.) */
f57fe068 11696 if (WORLD_SAVE_P (info_ptr))
f676971a 11697 {
d62294f5
FJ		 11698 rtx insn;
11699 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
c4ad648e
AM		 11700 if ( GET_CODE (insn) == CALL_INSN
11701 && SIBLING_CALL_P (insn))
11702 {
11703 info_ptr->world_save_p = 0;
11704 break;
11705 }
d62294f5 11706 }
f676971a 11707
f57fe068 11708 if (WORLD_SAVE_P (info_ptr))
d62294f5
FJ		 11709 {
11710 /* Even if we're not touching VRsave, make sure there's room on the
11711 stack for it, if it looks like we're calling SAVE_WORLD, which
c4ad648e 11712 will attempt to save it. */
d62294f5
FJ		 11713 info_ptr->vrsave_size = 4;
11714
11715 /* "Save" the VRsave register too if we're saving the world. */
11716 if (info_ptr->vrsave_mask == 0)
c4ad648e 11717 info_ptr->vrsave_mask = compute_vrsave_mask ();
d62294f5
FJ		 11718
11719 /* Because the Darwin register save/restore routines only handle
c4ad648e
AM		 11720 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11721 check and abort if there's something worng. */
37409796
NS		 11722 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
11723 && (info_ptr->first_altivec_reg_save
11724 >= FIRST_SAVED_ALTIVEC_REGNO));
d62294f5 11725 }
f676971a 11726 return;
d62294f5
FJ		 11727}
11728
11729
00b960c7 11730static void
a2369ed3 11731is_altivec_return_reg (rtx reg, void *xyes)
00b960c7
AH		 11732{
11733 bool *yes = (bool *) xyes;
11734 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11735 *yes = true;
11736}
11737
4697a36c
MM		 11738\f
11739/* Calculate the stack information for the current function. This is
11740 complicated by having two separate calling sequences, the AIX calling
11741 sequence and the V.4 calling sequence.
11742
592696dd 11743 AIX (and Darwin/Mac OS X) stack frames look like:
a260abc9 11744 32-bit 64-bit
4697a36c 11745 SP----> +---------------------------------------+
a260abc9 11746 | back chain to caller | 0 0
4697a36c 11747 +---------------------------------------+
a260abc9 11748 | saved CR | 4 8 (8-11)
4697a36c 11749 +---------------------------------------+
a260abc9 11750 | saved LR | 8 16
4697a36c 11751 +---------------------------------------+
a260abc9 11752 | reserved for compilers | 12 24
4697a36c 11753 +---------------------------------------+
a260abc9 11754 | reserved for binders | 16 32
4697a36c 11755 +---------------------------------------+
a260abc9 11756 | saved TOC pointer | 20 40
4697a36c 11757 +---------------------------------------+
a260abc9 11758 | Parameter save area (P) | 24 48
4697a36c 11759 +---------------------------------------+
a260abc9 11760 | Alloca space (A) | 24+P etc.
802a0058 11761 +---------------------------------------+
a7df97e6 11762 | Local variable space (L) | 24+P+A
4697a36c 11763 +---------------------------------------+
a7df97e6 11764 | Float/int conversion temporary (X) | 24+P+A+L
4697a36c 11765 +---------------------------------------+
00b960c7
AH		 11766 | Save area for AltiVec registers (W) | 24+P+A+L+X
11767 +---------------------------------------+
11768 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11769 +---------------------------------------+
11770 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
4697a36c 11771 +---------------------------------------+
00b960c7
AH		 11772 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11773 +---------------------------------------+
11774 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
4697a36c
MM		 11775 +---------------------------------------+
11776 old SP->| back chain to caller's caller |
11777 +---------------------------------------+
11778
5376a30c
KR		 11779 The required alignment for AIX configurations is two words (i.e., 8
11780 or 16 bytes).
11781
11782
4697a36c
MM		 11783 V.4 stack frames look like:
11784
11785 SP----> +---------------------------------------+
11786 | back chain to caller | 0
11787 +---------------------------------------+
5eb387b8 11788 | caller's saved LR | 4
4697a36c
MM		 11789 +---------------------------------------+
11790 | Parameter save area (P) | 8
11791 +---------------------------------------+
a7df97e6 11792 | Alloca space (A) | 8+P
f676971a 11793 +---------------------------------------+
a7df97e6 11794 | Varargs save area (V) | 8+P+A
f676971a 11795 +---------------------------------------+
a7df97e6 11796 | Local variable space (L) | 8+P+A+V
f676971a 11797 +---------------------------------------+
a7df97e6 11798 | Float/int conversion temporary (X) | 8+P+A+V+L
4697a36c 11799 +---------------------------------------+
00b960c7
AH		 11800 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11801 +---------------------------------------+
11802 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11803 +---------------------------------------+
11804 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11805 +---------------------------------------+
c4ad648e
AM		 11806 | SPE: area for 64-bit GP registers |
11807 +---------------------------------------+
11808 | SPE alignment padding |
11809 +---------------------------------------+
00b960c7 11810 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
f676971a 11811 +---------------------------------------+
00b960c7 11812 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
f676971a 11813 +---------------------------------------+
00b960c7 11814 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
4697a36c
MM		 11815 +---------------------------------------+
11816 old SP->| back chain to caller's caller |
11817 +---------------------------------------+
b6c9286a 11818
5376a30c
KR		 11819 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11820 given. (But note below and in sysv4.h that we require only 8 and
11821 may round up the size of our stack frame anyways. The historical
11822 reason is early versions of powerpc-linux which didn't properly
11823 align the stack at program startup. A happy side-effect is that
11824 -mno-eabi libraries can be used with -meabi programs.)
11825
50d440bc 11826 The EABI configuration defaults to the V.4 layout. However,
5376a30c
KR		 11827 the stack alignment requirements may differ. If -mno-eabi is not
11828 given, the required stack alignment is 8 bytes; if -mno-eabi is
11829 given, the required alignment is 16 bytes. (But see V.4 comment
11830 above.) */
4697a36c 11831
61b2fbe7
MM		 11832#ifndef ABI_STACK_BOUNDARY
11833#define ABI_STACK_BOUNDARY STACK_BOUNDARY
11834#endif
11835
d1d0c603 11836static rs6000_stack_t *
863d938c 11837rs6000_stack_info (void)
4697a36c
MM		 11838{
11839 static rs6000_stack_t info, zero_info;
11840 rs6000_stack_t *info_ptr = &info;
327e5343 11841 int reg_size = TARGET_32BIT ? 4 : 8;
83720594 11842 int ehrd_size;
64045029 11843 int save_align;
44688022 11844 HOST_WIDE_INT non_fixed_size;
4697a36c 11845
a4f6c312 11846 /* Zero all fields portably. */
4697a36c
MM		 11847 info = zero_info;
11848
c19de7aa
AH		 11849 if (TARGET_SPE)
11850 {
11851 /* Cache value so we don't rescan instruction chain over and over. */
9b7b447f 11852 if (cfun->machine->insn_chain_scanned_p == 0)
b5a5beb9
AH		 11853 cfun->machine->insn_chain_scanned_p
11854 = spe_func_has_64bit_regs_p () + 1;
11855 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
c19de7aa
AH		 11856 }
11857
a4f6c312 11858 /* Select which calling sequence. */
178274da 11859 info_ptr->abi = DEFAULT_ABI;
9878760c 11860
a4f6c312 11861 /* Calculate which registers need to be saved & save area size. */
4697a36c 11862 info_ptr->first_gp_reg_save = first_reg_to_save ();
f676971a 11863 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
906fb125 11864 even if it currently looks like we won't. */
2bfcf297 11865 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
178274da
AM		 11866 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
11867 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
1db02437
FS		 11868 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
11869 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
906fb125
GK		 11870 else
11871 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
4697a36c 11872
a3170dc6
AH		 11873 /* For the SPE, we have an additional upper 32-bits on each GPR.
11874 Ideally we should save the entire 64-bits only when the upper
11875 half is used in SIMD instructions. Since we only record
11876 registers live (not the size they are used in), this proves
11877 difficult because we'd have to traverse the instruction chain at
11878 the right time, taking reload into account. This is a real pain,
c19de7aa
AH		 11879 so we opt to save the GPRs in 64-bits always if but one register
11880 gets used in 64-bits. Otherwise, all the registers in the frame
11881 get saved in 32-bits.
a3170dc6 11882
c19de7aa 11883 So... since when we save all GPRs (except the SP) in 64-bits, the
a3170dc6 11884 traditional GP save area will be empty. */
c19de7aa 11885 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 11886 info_ptr->gp_size = 0;
11887
4697a36c
MM		 11888 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
11889 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
11890
00b960c7
AH		 11891 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
11892 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
11893 - info_ptr->first_altivec_reg_save);
11894
592696dd 11895 /* Does this function call anything? */
71f123ca
FS		 11896 info_ptr->calls_p = (! current_function_is_leaf
11897 || cfun->machine->ra_needs_full_frame);
b6c9286a 11898
a4f6c312 11899 /* Determine if we need to save the link register. */
71f123ca 11900 if (rs6000_ra_ever_killed ()
ffcfcb5f
AM		 11901 || (DEFAULT_ABI == ABI_AIX
11902 && current_function_profile
11903 && !TARGET_PROFILE_KERNEL)
4697a36c
MM		 11904#ifdef TARGET_RELOCATABLE
11905 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
11906#endif
11907 || (info_ptr->first_fp_reg_save != 64
11908 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
00b960c7 11909 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
178274da 11910 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
a4f6c312
SS		 11911 || (DEFAULT_ABI == ABI_DARWIN
11912 && flag_pic
11913 && current_function_uses_pic_offset_table)
4697a36c
MM		 11914 || info_ptr->calls_p)
11915 {
11916 info_ptr->lr_save_p = 1;
9ebbca7d 11917 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
4697a36c
MM		 11918 }
11919
9ebbca7d 11920 /* Determine if we need to save the condition code registers. */
f676971a 11921 if (regs_ever_live[CR2_REGNO]
9ebbca7d
GK		 11922 || regs_ever_live[CR3_REGNO]
11923 || regs_ever_live[CR4_REGNO])
4697a36c
MM		 11924 {
11925 info_ptr->cr_save_p = 1;
178274da 11926 if (DEFAULT_ABI == ABI_V4)
4697a36c
MM		 11927 info_ptr->cr_size = reg_size;
11928 }
11929
83720594
RH		 11930 /* If the current function calls __builtin_eh_return, then we need
11931 to allocate stack space for registers that will hold data for
11932 the exception handler. */
11933 if (current_function_calls_eh_return)
11934 {
11935 unsigned int i;
11936 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
11937 continue;
a3170dc6
AH		 11938
11939 /* SPE saves EH registers in 64-bits. */
c19de7aa
AH		 11940 ehrd_size = i * (TARGET_SPE_ABI
11941 && info_ptr->spe_64bit_regs_used != 0
11942 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
83720594
RH		 11943 }
11944 else
11945 ehrd_size = 0;
11946
592696dd 11947 /* Determine various sizes. */
4697a36c
MM		 11948 info_ptr->reg_size = reg_size;
11949 info_ptr->fixed_size = RS6000_SAVE_AREA;
11950 info_ptr->varargs_size = RS6000_VARARGS_AREA;
189e03e3 11951 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
a4f6c312 11952 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
03e007d7 11953 TARGET_ALTIVEC ? 16 : 8);
00b960c7 11954
c19de7aa 11955 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 11956 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
11957 else
11958 info_ptr->spe_gp_size = 0;
11959
4d774ff8
HP		 11960 if (TARGET_ALTIVEC_ABI)
11961 info_ptr->vrsave_mask = compute_vrsave_mask ();
00b960c7 11962 else
4d774ff8
HP		 11963 info_ptr->vrsave_mask = 0;
11964
11965 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
11966 info_ptr->vrsave_size = 4;
11967 else
11968 info_ptr->vrsave_size = 0;
b6c9286a 11969
d62294f5
FJ		 11970 compute_save_world_info (info_ptr);
11971
592696dd 11972 /* Calculate the offsets. */
178274da 11973 switch (DEFAULT_ABI)
4697a36c 11974 {
b6c9286a 11975 case ABI_NONE:
24d304eb 11976 default:
37409796 11977 gcc_unreachable ();
b6c9286a
MM		 11978
11979 case ABI_AIX:
ee890fe2 11980 case ABI_DARWIN:
b6c9286a
MM		 11981 info_ptr->fp_save_offset = - info_ptr->fp_size;
11982 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
00b960c7
AH		 11983
11984 if (TARGET_ALTIVEC_ABI)
11985 {
11986 info_ptr->vrsave_save_offset
11987 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
11988
11989 /* Align stack so vector save area is on a quadword boundary. */
11990 if (info_ptr->altivec_size != 0)
11991 info_ptr->altivec_padding_size
11992 = 16 - (-info_ptr->vrsave_save_offset % 16);
11993 else
11994 info_ptr->altivec_padding_size = 0;
11995
11996 info_ptr->altivec_save_offset
11997 = info_ptr->vrsave_save_offset
11998 - info_ptr->altivec_padding_size
11999 - info_ptr->altivec_size;
12000
12001 /* Adjust for AltiVec case. */
12002 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12003 }
12004 else
12005 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
a260abc9
DE		 12006 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12007 info_ptr->lr_save_offset = 2*reg_size;
24d304eb
RK		 12008 break;
12009
12010 case ABI_V4:
b6c9286a
MM		 12011 info_ptr->fp_save_offset = - info_ptr->fp_size;
12012 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
a7df97e6 12013 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
00b960c7 12014
c19de7aa 12015 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
c4ad648e
AM		 12016 {
12017 /* Align stack so SPE GPR save area is aligned on a
12018 double-word boundary. */
12019 if (info_ptr->spe_gp_size != 0)
12020 info_ptr->spe_padding_size
12021 = 8 - (-info_ptr->cr_save_offset % 8);
12022 else
12023 info_ptr->spe_padding_size = 0;
12024
12025 info_ptr->spe_gp_save_offset
12026 = info_ptr->cr_save_offset
12027 - info_ptr->spe_padding_size
12028 - info_ptr->spe_gp_size;
12029
12030 /* Adjust for SPE case. */
12031 info_ptr->toc_save_offset
12032 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12033 }
a3170dc6 12034 else if (TARGET_ALTIVEC_ABI)
00b960c7
AH		 12035 {
12036 info_ptr->vrsave_save_offset
12037 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12038
12039 /* Align stack so vector save area is on a quadword boundary. */
12040 if (info_ptr->altivec_size != 0)
12041 info_ptr->altivec_padding_size
12042 = 16 - (-info_ptr->vrsave_save_offset % 16);
12043 else
12044 info_ptr->altivec_padding_size = 0;
12045
12046 info_ptr->altivec_save_offset
12047 = info_ptr->vrsave_save_offset
12048 - info_ptr->altivec_padding_size
12049 - info_ptr->altivec_size;
12050
12051 /* Adjust for AltiVec case. */
12052 info_ptr->toc_save_offset
12053 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12054 }
12055 else
12056 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
83720594 12057 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
b6c9286a
MM		 12058 info_ptr->lr_save_offset = reg_size;
12059 break;
4697a36c
MM		 12060 }
12061
64045029 12062 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
00b960c7
AH		 12063 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12064 + info_ptr->gp_size
12065 + info_ptr->altivec_size
12066 + info_ptr->altivec_padding_size
a3170dc6
AH		 12067 + info_ptr->spe_gp_size
12068 + info_ptr->spe_padding_size
00b960c7
AH		 12069 + ehrd_size
12070 + info_ptr->cr_size
12071 + info_ptr->lr_size
12072 + info_ptr->vrsave_size
12073 + info_ptr->toc_size,
64045029 12074 save_align);
00b960c7 12075
44688022 12076 non_fixed_size = (info_ptr->vars_size
ff381587 12077 + info_ptr->parm_size
ff381587 12078 + info_ptr->save_size
44688022 12079 + info_ptr->varargs_size);
ff381587 12080
44688022
AM		 12081 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12082 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
ff381587
MM		 12083
12084 /* Determine if we need to allocate any stack frame:
12085
a4f6c312
SS		 12086 For AIX we need to push the stack if a frame pointer is needed
12087 (because the stack might be dynamically adjusted), if we are
12088 debugging, if we make calls, or if the sum of fp_save, gp_save,
12089 and local variables are more than the space needed to save all
12090 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12091 + 18*8 = 288 (GPR13 reserved).
ff381587 12092
a4f6c312
SS		 12093 For V.4 we don't have the stack cushion that AIX uses, but assume
12094 that the debugger can handle stackless frames. */
ff381587
MM		 12095
12096 if (info_ptr->calls_p)
12097 info_ptr->push_p = 1;
12098
178274da 12099 else if (DEFAULT_ABI == ABI_V4)
44688022 12100 info_ptr->push_p = non_fixed_size != 0;
ff381587 12101
178274da
AM		 12102 else if (frame_pointer_needed)
12103 info_ptr->push_p = 1;
12104
12105 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12106 info_ptr->push_p = 1;
12107
ff381587 12108 else
44688022 12109 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
ff381587 12110
a4f6c312 12111 /* Zero offsets if we're not saving those registers. */
8dda1a21 12112 if (info_ptr->fp_size == 0)
4697a36c
MM		 12113 info_ptr->fp_save_offset = 0;
12114
8dda1a21 12115 if (info_ptr->gp_size == 0)
4697a36c
MM		 12116 info_ptr->gp_save_offset = 0;
12117
00b960c7
AH		 12118 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12119 info_ptr->altivec_save_offset = 0;
12120
12121 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12122 info_ptr->vrsave_save_offset = 0;
12123
c19de7aa
AH		 12124 if (! TARGET_SPE_ABI
12125 || info_ptr->spe_64bit_regs_used == 0
12126 || info_ptr->spe_gp_size == 0)
a3170dc6
AH		 12127 info_ptr->spe_gp_save_offset = 0;
12128
c81fc13e 12129 if (! info_ptr->lr_save_p)
4697a36c
MM		 12130 info_ptr->lr_save_offset = 0;
12131
c81fc13e 12132 if (! info_ptr->cr_save_p)
4697a36c
MM		 12133 info_ptr->cr_save_offset = 0;
12134
c81fc13e 12135 if (! info_ptr->toc_save_p)
b6c9286a
MM		 12136 info_ptr->toc_save_offset = 0;
12137
4697a36c
MM		 12138 return info_ptr;
12139}
12140
c19de7aa
AH		 12141/* Return true if the current function uses any GPRs in 64-bit SIMD
12142 mode. */
12143
12144static bool
863d938c 12145spe_func_has_64bit_regs_p (void)
c19de7aa
AH		 12146{
12147 rtx insns, insn;
12148
12149 /* Functions that save and restore all the call-saved registers will
12150 need to save/restore the registers in 64-bits. */
12151 if (current_function_calls_eh_return
12152 || current_function_calls_setjmp
12153 || current_function_has_nonlocal_goto)
12154 return true;
12155
12156 insns = get_insns ();
12157
12158 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12159 {
12160 if (INSN_P (insn))
12161 {
12162 rtx i;
12163
b5a5beb9
AH		 12164 /* FIXME: This should be implemented with attributes...
12165
12166 (set_attr "spe64" "true")....then,
12167 if (get_spe64(insn)) return true;
12168
12169 It's the only reliable way to do the stuff below. */
12170
c19de7aa 12171 i = PATTERN (insn);
f82f556d
AH		 12172 if (GET_CODE (i) == SET)
12173 {
12174 enum machine_mode mode = GET_MODE (SET_SRC (i));
12175
12176 if (SPE_VECTOR_MODE (mode))
12177 return true;
12178 if (TARGET_E500_DOUBLE && mode == DFmode)
12179 return true;
12180 }
c19de7aa
AH		 12181 }
12182 }
12183
12184 return false;
12185}
12186
d1d0c603 12187static void
a2369ed3 12188debug_stack_info (rs6000_stack_t *info)
9878760c 12189{
d330fd93 12190 const char *abi_string;
24d304eb 12191
c81fc13e 12192 if (! info)
4697a36c
MM		 12193 info = rs6000_stack_info ();
12194
12195 fprintf (stderr, "\nStack information for function %s:\n",
12196 ((current_function_decl && DECL_NAME (current_function_decl))
12197 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12198 : "<unknown>"));
12199
24d304eb
RK		 12200 switch (info->abi)
12201 {
b6c9286a
MM		 12202 default: abi_string = "Unknown"; break;
12203 case ABI_NONE: abi_string = "NONE"; break;
50d440bc 12204 case ABI_AIX: abi_string = "AIX"; break;
ee890fe2 12205 case ABI_DARWIN: abi_string = "Darwin"; break;
b6c9286a 12206 case ABI_V4: abi_string = "V.4"; break;
24d304eb
RK		 12207 }
12208
12209 fprintf (stderr, "\tABI = %5s\n", abi_string);
12210
00b960c7
AH		 12211 if (TARGET_ALTIVEC_ABI)
12212 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12213
a3170dc6
AH		 12214 if (TARGET_SPE_ABI)
12215 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12216
4697a36c
MM		 12217 if (info->first_gp_reg_save != 32)
12218 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12219
12220 if (info->first_fp_reg_save != 64)
12221 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
9878760c 12222
00b960c7
AH		 12223 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12224 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12225 info->first_altivec_reg_save);
12226
4697a36c
MM		 12227 if (info->lr_save_p)
12228 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
9878760c 12229
4697a36c
MM		 12230 if (info->cr_save_p)
12231 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12232
b6c9286a
MM		 12233 if (info->toc_save_p)
12234 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
12235
00b960c7
AH		 12236 if (info->vrsave_mask)
12237 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
12238
4697a36c
MM		 12239 if (info->push_p)
12240 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
12241
12242 if (info->calls_p)
12243 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
12244
4697a36c
MM		 12245 if (info->gp_save_offset)
12246 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
12247
12248 if (info->fp_save_offset)
12249 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
12250
00b960c7
AH		 12251 if (info->altivec_save_offset)
12252 fprintf (stderr, "\taltivec_save_offset = %5d\n",
12253 info->altivec_save_offset);
12254
a3170dc6
AH		 12255 if (info->spe_gp_save_offset)
12256 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
12257 info->spe_gp_save_offset);
12258
00b960c7
AH		 12259 if (info->vrsave_save_offset)
12260 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
12261 info->vrsave_save_offset);
12262
4697a36c
MM		 12263 if (info->lr_save_offset)
12264 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
12265
12266 if (info->cr_save_offset)
12267 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
12268
b6c9286a
MM		 12269 if (info->toc_save_offset)
12270 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
12271
4697a36c
MM		 12272 if (info->varargs_save_offset)
12273 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
12274
12275 if (info->total_size)
d1d0c603
JJ		 12276 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12277 info->total_size);
4697a36c
MM		 12278
12279 if (info->varargs_size)
12280 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
12281
12282 if (info->vars_size)
d1d0c603
JJ		 12283 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12284 info->vars_size);
4697a36c
MM		 12285
12286 if (info->parm_size)
12287 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
12288
12289 if (info->fixed_size)
12290 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
12291
12292 if (info->gp_size)
12293 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
12294
a3170dc6
AH		 12295 if (info->spe_gp_size)
12296 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
12297
4697a36c
MM		 12298 if (info->fp_size)
12299 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
12300
00b960c7
AH		 12301 if (info->altivec_size)
12302 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
12303
12304 if (info->vrsave_size)
12305 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
12306
12307 if (info->altivec_padding_size)
12308 fprintf (stderr, "\taltivec_padding_size= %5d\n",
12309 info->altivec_padding_size);
12310
a3170dc6
AH		 12311 if (info->spe_padding_size)
12312 fprintf (stderr, "\tspe_padding_size = %5d\n",
12313 info->spe_padding_size);
12314
a4f6c312 12315 if (info->lr_size)
ed947a96 12316 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
b6c9286a 12317
4697a36c
MM		 12318 if (info->cr_size)
12319 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
12320
a4f6c312 12321 if (info->toc_size)
b6c9286a
MM		 12322 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
12323
4697a36c
MM		 12324 if (info->save_size)
12325 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
12326
12327 if (info->reg_size != 4)
12328 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
12329
12330 fprintf (stderr, "\n");
9878760c 12331}
71f123ca
FS		 12332
12333rtx
a2369ed3 12334rs6000_return_addr (int count, rtx frame)
71f123ca 12335{
a4f6c312
SS		 12336 /* Currently we don't optimize very well between prolog and body
12337 code and for PIC code the code can be actually quite bad, so
12338 don't try to be too clever here. */
f1384257 12339 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
71f123ca
FS		 12340 {
12341 cfun->machine->ra_needs_full_frame = 1;
8ac61af7
RK		 12342
12343 return
12344 gen_rtx_MEM
12345 (Pmode,
12346 memory_address
12347 (Pmode,
12348 plus_constant (copy_to_reg
12349 (gen_rtx_MEM (Pmode,
12350 memory_address (Pmode, frame))),
12351 RETURN_ADDRESS_OFFSET)));
71f123ca
FS		 12352 }
12353
8c29550d 12354 cfun->machine->ra_need_lr = 1;
9e2f7ec7 12355 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
71f123ca
FS		 12356}
12357
5e1bf043
DJ		 12358/* Say whether a function is a candidate for sibcall handling or not.
12359 We do not allow indirect calls to be optimized into sibling calls.
12360 Also, we can't do it if there are any vector parameters; there's
12361 nowhere to put the VRsave code so it works; note that functions with
12362 vector parameters are required to have a prototype, so the argument
12363 type info must be available here. (The tail recursion case can work
12364 with vector parameters, but there's no way to distinguish here.) */
4977bab6 12365static bool
a2369ed3 12366rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5e1bf043
DJ		 12367{
12368 tree type;
4977bab6 12369 if (decl)
5e1bf043
DJ		 12370 {
12371 if (TARGET_ALTIVEC_VRSAVE)
c4ad648e 12372 {
4977bab6 12373 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
5e1bf043
DJ		 12374 type; type = TREE_CHAIN (type))
12375 {
c15b529f 12376 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
4977bab6 12377 return false;
5e1bf043 12378 }
c4ad648e 12379 }
5e1bf043 12380 if (DEFAULT_ABI == ABI_DARWIN
4977bab6 12381 || (*targetm.binds_local_p) (decl))
2bcc50d0 12382 {
4977bab6 12383 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
2bcc50d0
AM		 12384
12385 if (!lookup_attribute ("longcall", attr_list)
12386 || lookup_attribute ("shortcall", attr_list))
4977bab6 12387 return true;
2bcc50d0 12388 }
5e1bf043 12389 }
4977bab6 12390 return false;
5e1bf043
DJ		 12391}
12392
71f123ca 12393static int
863d938c 12394rs6000_ra_ever_killed (void)
71f123ca
FS		 12395{
12396 rtx top;
5e1bf043
DJ		 12397 rtx reg;
12398 rtx insn;
71f123ca 12399
dd292d0a 12400 if (current_function_is_thunk)
71f123ca 12401 return 0;
eb0424da 12402
36f7e964
AH		 12403 /* regs_ever_live has LR marked as used if any sibcalls are present,
12404 but this should not force saving and restoring in the
12405 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
a3c9585f 12406 clobbers LR, so that is inappropriate. */
36f7e964 12407
5e1bf043
DJ		 12408 /* Also, the prologue can generate a store into LR that
12409 doesn't really count, like this:
36f7e964 12410
5e1bf043
DJ		 12411 move LR->R0
12412 bcl to set PIC register
12413 move LR->R31
12414 move R0->LR
36f7e964
AH		 12415
12416 When we're called from the epilogue, we need to avoid counting
12417 this as a store. */
f676971a 12418
71f123ca
FS		 12419 push_topmost_sequence ();
12420 top = get_insns ();
12421 pop_topmost_sequence ();
5e1bf043 12422 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
71f123ca 12423
5e1bf043
DJ		 12424 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
12425 {
12426 if (INSN_P (insn))
12427 {
12428 if (FIND_REG_INC_NOTE (insn, reg))
12429 return 1;
f676971a 12430 else if (GET_CODE (insn) == CALL_INSN
c15b529f 12431 && !SIBLING_CALL_P (insn))
5e1bf043 12432 return 1;
36f7e964
AH		 12433 else if (set_of (reg, insn) != NULL_RTX
12434 && !prologue_epilogue_contains (insn))
5e1bf043
DJ		 12435 return 1;
12436 }
12437 }
12438 return 0;
71f123ca 12439}
4697a36c 12440\f
8cd8f856
GK		 12441/* Add a REG_MAYBE_DEAD note to the insn. */
12442static void
a2369ed3 12443rs6000_maybe_dead (rtx insn)
8cd8f856
GK		 12444{
12445 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
12446 const0_rtx,
12447 REG_NOTES (insn));
12448}
12449
9ebbca7d 12450/* Emit instructions needed to load the TOC register.
c7ca610e 12451 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
9ebbca7d 12452 a constant pool; or for SVR4 -fpic. */
c7ca610e
RK		 12453
12454void
a2369ed3 12455rs6000_emit_load_toc_table (int fromprolog)
c7ca610e 12456{
027fbf43 12457 rtx dest, insn;
1db02437 12458 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
c7ca610e 12459
20b71b17
AM		 12460 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12461 {
12462 rtx temp = (fromprolog
12463 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12464 : gen_reg_rtx (Pmode));
027fbf43
JJ		 12465 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
12466 if (fromprolog)
12467 rs6000_maybe_dead (insn);
12468 insn = emit_move_insn (dest, temp);
12469 if (fromprolog)
12470 rs6000_maybe_dead (insn);
20b71b17
AM		 12471 }
12472 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12473 {
12474 char buf[30];
12475 rtx tempLR = (fromprolog
12476 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12477 : gen_reg_rtx (Pmode));
12478 rtx temp0 = (fromprolog
12479 ? gen_rtx_REG (Pmode, 0)
12480 : gen_reg_rtx (Pmode));
20b71b17 12481
20b71b17
AM		 12482 if (fromprolog)
12483 {
ccbca5e4 12484 rtx symF, symL;
38c1f2d7 12485
20b71b17
AM		 12486 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12487 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d 12488
20b71b17
AM		 12489 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12490 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12491
12492 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12493 symF)));
12494 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12495 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12496 symL,
12497 symF)));
9ebbca7d
GK		 12498 }
12499 else
20b71b17
AM		 12500 {
12501 rtx tocsym;
20b71b17
AM		 12502
12503 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
ccbca5e4 12504 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
027fbf43
JJ		 12505 emit_move_insn (dest, tempLR);
12506 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
20b71b17 12507 }
027fbf43
JJ		 12508 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12509 if (fromprolog)
12510 rs6000_maybe_dead (insn);
9ebbca7d 12511 }
20b71b17
AM		 12512 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12513 {
12514 /* This is for AIX code running in non-PIC ELF32. */
12515 char buf[30];
12516 rtx realsym;
12517 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12518 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12519
027fbf43
JJ		 12520 insn = emit_insn (gen_elf_high (dest, realsym));
12521 if (fromprolog)
12522 rs6000_maybe_dead (insn);
12523 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12524 if (fromprolog)
12525 rs6000_maybe_dead (insn);
20b71b17 12526 }
37409796 12527 else
9ebbca7d 12528 {
37409796
NS		 12529 gcc_assert (DEFAULT_ABI == ABI_AIX);
12530
9ebbca7d 12531 if (TARGET_32BIT)
027fbf43 12532 insn = emit_insn (gen_load_toc_aix_si (dest));
9ebbca7d 12533 else
027fbf43
JJ		 12534 insn = emit_insn (gen_load_toc_aix_di (dest));
12535 if (fromprolog)
12536 rs6000_maybe_dead (insn);
9ebbca7d
GK		 12537 }
12538}
12539
d1d0c603
JJ		 12540/* Emit instructions to restore the link register after determining where
12541 its value has been stored. */
12542
12543void
12544rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12545{
12546 rs6000_stack_t *info = rs6000_stack_info ();
12547 rtx operands[2];
12548
12549 operands[0] = source;
12550 operands[1] = scratch;
12551
12552 if (info->lr_save_p)
12553 {
12554 rtx frame_rtx = stack_pointer_rtx;
12555 HOST_WIDE_INT sp_offset = 0;
12556 rtx tmp;
12557
12558 if (frame_pointer_needed
12559 || current_function_calls_alloca
12560 || info->total_size > 32767)
12561 {
12562 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12563 frame_rtx = operands[1];
12564 }
12565 else if (info->push_p)
12566 sp_offset = info->total_size;
12567
12568 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12569 tmp = gen_rtx_MEM (Pmode, tmp);
12570 emit_move_insn (tmp, operands[0]);
12571 }
12572 else
12573 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12574}
12575
f103e34d
GK		 12576static GTY(()) int set = -1;
12577
f676971a 12578int
863d938c 12579get_TOC_alias_set (void)
9ebbca7d 12580{
f103e34d
GK		 12581 if (set == -1)
12582 set = new_alias_set ();
12583 return set;
f676971a 12584}
9ebbca7d 12585
c1207243 12586/* This returns nonzero if the current function uses the TOC. This is
3c9eb5f4
AM		 12587 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12588 is generated by the ABI_V4 load_toc_* patterns. */
c954844a 12589#if TARGET_ELF
3c9eb5f4 12590static int
f676971a 12591uses_TOC (void)
9ebbca7d 12592{
c4501e62 12593 rtx insn;
38c1f2d7 12594
c4501e62
JJ		 12595 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12596 if (INSN_P (insn))
12597 {
12598 rtx pat = PATTERN (insn);
12599 int i;
9ebbca7d 12600
f676971a 12601 if (GET_CODE (pat) == PARALLEL)
c4501e62
JJ		 12602 for (i = 0; i < XVECLEN (pat, 0); i++)
12603 {
12604 rtx sub = XVECEXP (pat, 0, i);
12605 if (GET_CODE (sub) == USE)
12606 {
12607 sub = XEXP (sub, 0);
12608 if (GET_CODE (sub) == UNSPEC
12609 && XINT (sub, 1) == UNSPEC_TOC)
12610 return 1;
12611 }
12612 }
12613 }
12614 return 0;
9ebbca7d 12615}
c954844a 12616#endif
38c1f2d7 12617
9ebbca7d 12618rtx
f676971a 12619create_TOC_reference (rtx symbol)
9ebbca7d 12620{
f676971a 12621 return gen_rtx_PLUS (Pmode,
a8a05998 12622 gen_rtx_REG (Pmode, TOC_REGISTER),
f676971a
EC		 12623 gen_rtx_CONST (Pmode,
12624 gen_rtx_MINUS (Pmode, symbol,
b999aaeb 12625 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
9ebbca7d 12626}
38c1f2d7 12627
fc4767bb
JJ		 12628/* If _Unwind_* has been called from within the same module,
12629 toc register is not guaranteed to be saved to 40(1) on function
12630 entry. Save it there in that case. */
c7ca610e 12631
9ebbca7d 12632void
863d938c 12633rs6000_aix_emit_builtin_unwind_init (void)
9ebbca7d
GK		 12634{
12635 rtx mem;
12636 rtx stack_top = gen_reg_rtx (Pmode);
12637 rtx opcode_addr = gen_reg_rtx (Pmode);
fc4767bb
JJ		 12638 rtx opcode = gen_reg_rtx (SImode);
12639 rtx tocompare = gen_reg_rtx (SImode);
12640 rtx no_toc_save_needed = gen_label_rtx ();
9ebbca7d
GK		 12641
12642 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12643 emit_move_insn (stack_top, mem);
12644
fc4767bb
JJ		 12645 mem = gen_rtx_MEM (Pmode,
12646 gen_rtx_PLUS (Pmode, stack_top,
9ebbca7d
GK		 12647 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12648 emit_move_insn (opcode_addr, mem);
fc4767bb
JJ		 12649 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12650 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
2496c7bd 12651 : 0xE8410028, SImode));
9ebbca7d 12652
fc4767bb 12653 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
06f4e019 12654 SImode, NULL_RTX, NULL_RTX,
fc4767bb 12655 no_toc_save_needed);
9ebbca7d 12656
fc4767bb
JJ		 12657 mem = gen_rtx_MEM (Pmode,
12658 gen_rtx_PLUS (Pmode, stack_top,
12659 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12660 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12661 emit_label (no_toc_save_needed);
9ebbca7d 12662}
38c1f2d7 12663\f
ba4828e0
RK		 12664/* This ties together stack memory (MEM with an alias set of
12665 rs6000_sr_alias_set) and the change to the stack pointer. */
12666
9ebbca7d 12667static void
863d938c 12668rs6000_emit_stack_tie (void)
9ebbca7d 12669{
ba4828e0
RK		 12670 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12671
12672 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 12673 emit_insn (gen_stack_tie (mem));
12674}
38c1f2d7 12675
9ebbca7d
GK		 12676/* Emit the correct code for allocating stack space, as insns.
12677 If COPY_R12, make sure a copy of the old frame is left in r12.
12678 The generated code may use hard register 0 as a temporary. */
12679
12680static void
a2369ed3 12681rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
38c1f2d7 12682{
9ebbca7d
GK		 12683 rtx insn;
12684 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12685 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
61168ff1
RS		 12686 rtx todec = gen_int_mode (-size, Pmode);
12687
12688 if (INTVAL (todec) != -size)
12689 {
d4ee4d25 12690 warning (0, "stack frame too large");
61168ff1
RS		 12691 emit_insn (gen_trap ());
12692 return;
12693 }
a157febd
GK		 12694
12695 if (current_function_limit_stack)
12696 {
12697 if (REG_P (stack_limit_rtx)
f676971a 12698 && REGNO (stack_limit_rtx) > 1
a157febd
GK		 12699 && REGNO (stack_limit_rtx) <= 31)
12700 {
5b71a4e7 12701 emit_insn (TARGET_32BIT
9ebbca7d
GK		 12702 ? gen_addsi3 (tmp_reg,
12703 stack_limit_rtx,
12704 GEN_INT (size))
12705 : gen_adddi3 (tmp_reg,
12706 stack_limit_rtx,
12707 GEN_INT (size)));
5b71a4e7 12708
9ebbca7d
GK		 12709 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12710 const0_rtx));
a157febd
GK		 12711 }
12712 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
9ebbca7d 12713 && TARGET_32BIT
f607bc57 12714 && DEFAULT_ABI == ABI_V4)
a157febd 12715 {
9ebbca7d 12716 rtx toload = gen_rtx_CONST (VOIDmode,
f676971a
EC		 12717 gen_rtx_PLUS (Pmode,
12718 stack_limit_rtx,
9ebbca7d 12719 GEN_INT (size)));
5b71a4e7 12720
9ebbca7d
GK		 12721 emit_insn (gen_elf_high (tmp_reg, toload));
12722 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12723 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12724 const0_rtx));
a157febd
GK		 12725 }
12726 else
d4ee4d25 12727 warning (0, "stack limit expression is not supported");
a157febd
GK		 12728 }
12729
9ebbca7d
GK		 12730 if (copy_r12 || ! TARGET_UPDATE)
12731 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12732
38c1f2d7
MM		 12733 if (TARGET_UPDATE)
12734 {
9ebbca7d 12735 if (size > 32767)
38c1f2d7 12736 {
9ebbca7d 12737 /* Need a note here so that try_split doesn't get confused. */
9390387d 12738 if (get_last_insn () == NULL_RTX)
2e040219 12739 emit_note (NOTE_INSN_DELETED);
9ebbca7d
GK		 12740 insn = emit_move_insn (tmp_reg, todec);
12741 try_split (PATTERN (insn), insn, 0);
12742 todec = tmp_reg;
38c1f2d7 12743 }
5b71a4e7
DE		 12744
12745 insn = emit_insn (TARGET_32BIT
12746 ? gen_movsi_update (stack_reg, stack_reg,
12747 todec, stack_reg)
c4ad648e 12748 : gen_movdi_di_update (stack_reg, stack_reg,
9ebbca7d 12749 todec, stack_reg));
38c1f2d7
MM		 12750 }
12751 else
12752 {
5b71a4e7
DE		 12753 insn = emit_insn (TARGET_32BIT
12754 ? gen_addsi3 (stack_reg, stack_reg, todec)
12755 : gen_adddi3 (stack_reg, stack_reg, todec));
9ebbca7d
GK		 12756 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12757 gen_rtx_REG (Pmode, 12));
12758 }
f676971a 12759
9ebbca7d 12760 RTX_FRAME_RELATED_P (insn) = 1;
f676971a 12761 REG_NOTES (insn) =
9ebbca7d 12762 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
f676971a 12763 gen_rtx_SET (VOIDmode, stack_reg,
9ebbca7d
GK		 12764 gen_rtx_PLUS (Pmode, stack_reg,
12765 GEN_INT (-size))),
12766 REG_NOTES (insn));
12767}
12768
a4f6c312
SS		 12769/* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12770 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12771 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12772 deduce these equivalences by itself so it wasn't necessary to hold
12773 its hand so much. */
9ebbca7d
GK		 12774
12775static void
f676971a 12776rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
a2369ed3 12777 rtx reg2, rtx rreg)
9ebbca7d
GK		 12778{
12779 rtx real, temp;
12780
e56c4463
JL		 12781 /* copy_rtx will not make unique copies of registers, so we need to
12782 ensure we don't have unwanted sharing here. */
12783 if (reg == reg2)
12784 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12785
12786 if (reg == rreg)
12787 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12788
9ebbca7d
GK		 12789 real = copy_rtx (PATTERN (insn));
12790
89e7058f
AH		 12791 if (reg2 != NULL_RTX)
12792 real = replace_rtx (real, reg2, rreg);
f676971a
EC		 12793
12794 real = replace_rtx (real, reg,
9ebbca7d
GK		 12795 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12796 STACK_POINTER_REGNUM),
12797 GEN_INT (val)));
f676971a 12798
9ebbca7d
GK		 12799 /* We expect that 'real' is either a SET or a PARALLEL containing
12800 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12801 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12802
12803 if (GET_CODE (real) == SET)
12804 {
12805 rtx set = real;
f676971a 12806
9ebbca7d
GK		 12807 temp = simplify_rtx (SET_SRC (set));
12808 if (temp)
12809 SET_SRC (set) = temp;
12810 temp = simplify_rtx (SET_DEST (set));
12811 if (temp)
12812 SET_DEST (set) = temp;
12813 if (GET_CODE (SET_DEST (set)) == MEM)
38c1f2d7 12814 {
9ebbca7d
GK		 12815 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12816 if (temp)
12817 XEXP (SET_DEST (set), 0) = temp;
38c1f2d7 12818 }
38c1f2d7 12819 }
37409796 12820 else
9ebbca7d
GK		 12821 {
12822 int i;
37409796
NS		 12823
12824 gcc_assert (GET_CODE (real) == PARALLEL);
9ebbca7d
GK		 12825 for (i = 0; i < XVECLEN (real, 0); i++)
12826 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
12827 {
12828 rtx set = XVECEXP (real, 0, i);
f676971a 12829
9ebbca7d
GK		 12830 temp = simplify_rtx (SET_SRC (set));
12831 if (temp)
12832 SET_SRC (set) = temp;
12833 temp = simplify_rtx (SET_DEST (set));
12834 if (temp)
12835 SET_DEST (set) = temp;
12836 if (GET_CODE (SET_DEST (set)) == MEM)
12837 {
12838 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12839 if (temp)
12840 XEXP (SET_DEST (set), 0) = temp;
12841 }
12842 RTX_FRAME_RELATED_P (set) = 1;
12843 }
12844 }
c19de7aa
AH		 12845
12846 if (TARGET_SPE)
12847 real = spe_synthesize_frame_save (real);
12848
9ebbca7d
GK		 12849 RTX_FRAME_RELATED_P (insn) = 1;
12850 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12851 real,
12852 REG_NOTES (insn));
38c1f2d7
MM		 12853}
12854
c19de7aa
AH		 12855/* Given an SPE frame note, return a PARALLEL of SETs with the
12856 original note, plus a synthetic register save. */
12857
12858static rtx
a2369ed3 12859spe_synthesize_frame_save (rtx real)
c19de7aa
AH		 12860{
12861 rtx synth, offset, reg, real2;
12862
12863 if (GET_CODE (real) != SET
12864 || GET_MODE (SET_SRC (real)) != V2SImode)
12865 return real;
12866
12867 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12868 frame related note. The parallel contains a set of the register
41f3a930 12869 being saved, and another set to a synthetic register (n+1200).
c19de7aa
AH		 12870 This is so we can differentiate between 64-bit and 32-bit saves.
12871 Words cannot describe this nastiness. */
12872
37409796
NS		 12873 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
12874 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
12875 && GET_CODE (SET_SRC (real)) == REG);
c19de7aa
AH		 12876
12877 /* Transform:
12878 (set (mem (plus (reg x) (const y)))
12879 (reg z))
12880 into:
12881 (set (mem (plus (reg x) (const y+4)))
41f3a930 12882 (reg z+1200))
c19de7aa
AH		 12883 */
12884
12885 real2 = copy_rtx (real);
12886 PUT_MODE (SET_DEST (real2), SImode);
12887 reg = SET_SRC (real2);
12888 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
12889 synth = copy_rtx (real2);
12890
12891 if (BYTES_BIG_ENDIAN)
12892 {
12893 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
12894 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
12895 }
12896
12897 reg = SET_SRC (synth);
41f3a930 12898
c19de7aa 12899 synth = replace_rtx (synth, reg,
41f3a930 12900 gen_rtx_REG (SImode, REGNO (reg) + 1200));
c19de7aa
AH		 12901
12902 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
12903 synth = replace_rtx (synth, offset,
12904 GEN_INT (INTVAL (offset)
12905 + (BYTES_BIG_ENDIAN ? 0 : 4)));
12906
12907 RTX_FRAME_RELATED_P (synth) = 1;
12908 RTX_FRAME_RELATED_P (real2) = 1;
12909 if (BYTES_BIG_ENDIAN)
12910 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
12911 else
12912 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
12913
12914 return real;
12915}
12916
00b960c7
AH		 12917/* Returns an insn that has a vrsave set operation with the
12918 appropriate CLOBBERs. */
12919
12920static rtx
a2369ed3 12921generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
00b960c7
AH		 12922{
12923 int nclobs, i;
12924 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
a004eb82 12925 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
00b960c7 12926
a004eb82
AH		 12927 clobs[0]
12928 = gen_rtx_SET (VOIDmode,
12929 vrsave,
12930 gen_rtx_UNSPEC_VOLATILE (SImode,
12931 gen_rtvec (2, reg, vrsave),
12932 30));
00b960c7
AH		 12933
12934 nclobs = 1;
12935
9aa86737
AH		 12936 /* We need to clobber the registers in the mask so the scheduler
12937 does not move sets to VRSAVE before sets of AltiVec registers.
12938
12939 However, if the function receives nonlocal gotos, reload will set
12940 all call saved registers live. We will end up with:
12941
12942 (set (reg 999) (mem))
12943 (parallel [ (set (reg vrsave) (unspec blah))
12944 (clobber (reg 999))])
12945
12946 The clobber will cause the store into reg 999 to be dead, and
12947 flow will attempt to delete an epilogue insn. In this case, we
12948 need an unspec use/set of the register. */
00b960c7
AH		 12949
12950 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
44688022 12951 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
9aa86737
AH		 12952 {
12953 if (!epiloguep || call_used_regs [i])
12954 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
12955 gen_rtx_REG (V4SImode, i));
12956 else
12957 {
12958 rtx reg = gen_rtx_REG (V4SImode, i);
9aa86737
AH		 12959
12960 clobs[nclobs++]
a004eb82
AH		 12961 = gen_rtx_SET (VOIDmode,
12962 reg,
12963 gen_rtx_UNSPEC (V4SImode,
12964 gen_rtvec (1, reg), 27));
9aa86737
AH		 12965 }
12966 }
00b960c7
AH		 12967
12968 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
12969
12970 for (i = 0; i < nclobs; ++i)
12971 XVECEXP (insn, 0, i) = clobs[i];
12972
12973 return insn;
12974}
12975
89e7058f
AH		 12976/* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12977 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12978
12979static void
f676971a 12980emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
d1d0c603 12981 unsigned int regno, int offset, HOST_WIDE_INT total_size)
89e7058f
AH		 12982{
12983 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
12984 rtx replacea, replaceb;
12985
12986 int_rtx = GEN_INT (offset);
12987
12988 /* Some cases that need register indexed addressing. */
12989 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4d4cbc0e 12990 || (TARGET_E500_DOUBLE && mode == DFmode)
a3170dc6
AH		 12991 || (TARGET_SPE_ABI
12992 && SPE_VECTOR_MODE (mode)
12993 && !SPE_CONST_OFFSET_OK (offset)))
89e7058f
AH		 12994 {
12995 /* Whomever calls us must make sure r11 is available in the
c4ad648e 12996 flow path of instructions in the prologue. */
89e7058f
AH		 12997 offset_rtx = gen_rtx_REG (Pmode, 11);
12998 emit_move_insn (offset_rtx, int_rtx);
12999
13000 replacea = offset_rtx;
13001 replaceb = int_rtx;
13002 }
13003 else
13004 {
13005 offset_rtx = int_rtx;
13006 replacea = NULL_RTX;
13007 replaceb = NULL_RTX;
13008 }
13009
13010 reg = gen_rtx_REG (mode, regno);
13011 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13012 mem = gen_rtx_MEM (mode, addr);
13013 set_mem_alias_set (mem, rs6000_sr_alias_set);
13014
13015 insn = emit_move_insn (mem, reg);
13016
13017 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13018}
13019
a3170dc6
AH		 13020/* Emit an offset memory reference suitable for a frame store, while
13021 converting to a valid addressing mode. */
13022
13023static rtx
a2369ed3 13024gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
a3170dc6
AH		 13025{
13026 rtx int_rtx, offset_rtx;
13027
13028 int_rtx = GEN_INT (offset);
13029
4d4cbc0e
AH		 13030 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13031 || (TARGET_E500_DOUBLE && mode == DFmode))
a3170dc6
AH		 13032 {
13033 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13034 emit_move_insn (offset_rtx, int_rtx);
13035 }
13036 else
13037 offset_rtx = int_rtx;
13038
13039 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13040}
13041
699c914a
MS		 13042#ifndef TARGET_FIX_AND_CONTINUE
13043#define TARGET_FIX_AND_CONTINUE 0
13044#endif
13045
9ebbca7d
GK		 13046/* Emit function prologue as insns. */
13047
9878760c 13048void
863d938c 13049rs6000_emit_prologue (void)
9878760c 13050{
4697a36c 13051 rs6000_stack_t *info = rs6000_stack_info ();
0e67400a 13052 enum machine_mode reg_mode = Pmode;
327e5343 13053 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 13054 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13055 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13056 rtx frame_reg_rtx = sp_reg_rtx;
b78d48dd 13057 rtx cr_save_rtx = NULL_RTX;
9ebbca7d
GK		 13058 rtx insn;
13059 int saving_FPRs_inline;
13060 int using_store_multiple;
13061 HOST_WIDE_INT sp_offset = 0;
f676971a 13062
699c914a
MS		 13063 if (TARGET_FIX_AND_CONTINUE)
13064 {
13065 /* gdb on darwin arranges to forward a function from the old
de2ab0ca 13066 address by modifying the first 5 instructions of the function
699c914a
MS		 13067 to branch to the overriding function. This is necessary to
13068 permit function pointers that point to the old function to
13069 actually forward to the new function. */
13070 emit_insn (gen_nop ());
13071 emit_insn (gen_nop ());
de2ab0ca 13072 emit_insn (gen_nop ());
699c914a
MS		 13073 emit_insn (gen_nop ());
13074 emit_insn (gen_nop ());
13075 }
13076
13077 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13078 {
13079 reg_mode = V2SImode;
13080 reg_size = 8;
13081 }
a3170dc6 13082
9ebbca7d 13083 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 13084 && (!TARGET_SPE_ABI
13085 || info->spe_64bit_regs_used == 0)
9ebbca7d
GK		 13086 && info->first_gp_reg_save < 31);
13087 saving_FPRs_inline = (info->first_fp_reg_save == 64
8c29550d 13088 || FP_SAVE_INLINE (info->first_fp_reg_save)
acd0b319 13089 || current_function_calls_eh_return
8c29550d 13090 || cfun->machine->ra_need_lr);
9ebbca7d
GK		 13091
13092 /* For V.4, update stack before we do any saving and set back pointer. */
fc4767bb 13093 if (info->push_p
acd0b319
AM		 13094 && (DEFAULT_ABI == ABI_V4
13095 || current_function_calls_eh_return))
9ebbca7d
GK		 13096 {
13097 if (info->total_size < 32767)
13098 sp_offset = info->total_size;
13099 else
13100 frame_reg_rtx = frame_ptr_rtx;
f676971a 13101 rs6000_emit_allocate_stack (info->total_size,
9ebbca7d
GK		 13102 (frame_reg_rtx != sp_reg_rtx
13103 && (info->cr_save_p
13104 || info->lr_save_p
13105 || info->first_fp_reg_save < 64
13106 || info->first_gp_reg_save < 32
13107 )));
13108 if (frame_reg_rtx != sp_reg_rtx)
13109 rs6000_emit_stack_tie ();
13110 }
13111
d62294f5 13112 /* Handle world saves specially here. */
f57fe068 13113 if (WORLD_SAVE_P (info))
d62294f5
FJ		 13114 {
13115 int i, j, sz;
13116 rtx treg;
13117 rtvec p;
13118
13119 /* save_world expects lr in r0. */
13120 if (info->lr_save_p)
c4ad648e
AM		 13121 {
13122 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13123 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13124 RTX_FRAME_RELATED_P (insn) = 1;
13125 }
d62294f5
FJ		 13126
13127 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
c4ad648e
AM		 13128 assumptions about the offsets of various bits of the stack
13129 frame. Abort if things aren't what they should be. */
37409796
NS		 13130 gcc_assert (info->gp_save_offset == -220
13131 && info->fp_save_offset == -144
13132 && info->lr_save_offset == 8
13133 && info->cr_save_offset == 4
13134 && info->push_p
13135 && info->lr_save_p
13136 && (!current_function_calls_eh_return
13137 || info->ehrd_offset == -432)
13138 && info->vrsave_save_offset == -224
13139 && info->altivec_save_offset == (-224 -16 -192));
d62294f5
FJ		 13140
13141 treg = gen_rtx_REG (SImode, 11);
13142 emit_move_insn (treg, GEN_INT (-info->total_size));
13143
13144 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
c4ad648e 13145 in R11. It also clobbers R12, so beware! */
d62294f5
FJ		 13146
13147 /* Preserve CR2 for save_world prologues */
13148 sz = 6;
13149 sz += 32 - info->first_gp_reg_save;
13150 sz += 64 - info->first_fp_reg_save;
13151 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13152 p = rtvec_alloc (sz);
13153 j = 0;
13154 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
c4ad648e
AM		 13155 gen_rtx_REG (Pmode,
13156 LINK_REGISTER_REGNUM));
d62294f5 13157 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 13158 gen_rtx_SYMBOL_REF (Pmode,
13159 "*save_world"));
d62294f5 13160 /* We do floats first so that the instruction pattern matches
c4ad648e
AM		 13161 properly. */
13162 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13163 {
13164 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13165 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13166 GEN_INT (info->fp_save_offset
13167 + sp_offset + 8 * i));
13168 rtx mem = gen_rtx_MEM (DFmode, addr);
13169 set_mem_alias_set (mem, rs6000_sr_alias_set);
13170
13171 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13172 }
d62294f5 13173 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 13174 {
13175 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13176 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13177 GEN_INT (info->altivec_save_offset
13178 + sp_offset + 16 * i));
13179 rtx mem = gen_rtx_MEM (V4SImode, addr);
13180 set_mem_alias_set (mem, rs6000_sr_alias_set);
13181
13182 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13183 }
d62294f5 13184 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 13185 {
13186 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13187 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13188 GEN_INT (info->gp_save_offset
13189 + sp_offset + reg_size * i));
13190 rtx mem = gen_rtx_MEM (reg_mode, addr);
13191 set_mem_alias_set (mem, rs6000_sr_alias_set);
13192
13193 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13194 }
13195
13196 {
13197 /* CR register traditionally saved as CR2. */
13198 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13199 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13200 GEN_INT (info->cr_save_offset
13201 + sp_offset));
13202 rtx mem = gen_rtx_MEM (reg_mode, addr);
13203 set_mem_alias_set (mem, rs6000_sr_alias_set);
13204
13205 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13206 }
d62294f5
FJ		 13207 /* Prevent any attempt to delete the setting of r0 and treg! */
13208 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13209 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13210 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13211
13212 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13213 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
c4ad648e 13214 NULL_RTX, NULL_RTX);
d62294f5
FJ		 13215
13216 if (current_function_calls_eh_return)
c4ad648e
AM		 13217 {
13218 unsigned int i;
13219 for (i = 0; ; ++i)
13220 {
13221 unsigned int regno = EH_RETURN_DATA_REGNO (i);
13222 if (regno == INVALID_REGNUM)
13223 break;
13224 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13225 info->ehrd_offset + sp_offset
13226 + reg_size * (int) i,
13227 info->total_size);
13228 }
13229 }
d62294f5
FJ		 13230 }
13231
9aa86737 13232 /* Save AltiVec registers if needed. */
f57fe068 13233 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
9aa86737
AH		 13234 {
13235 int i;
13236
13237 /* There should be a non inline version of this, for when we
13238 are saving lots of vector registers. */
13239 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13240 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13241 {
13242 rtx areg, savereg, mem;
13243 int offset;
13244
13245 offset = info->altivec_save_offset + sp_offset
13246 + 16 * (i - info->first_altivec_reg_save);
13247
13248 savereg = gen_rtx_REG (V4SImode, i);
13249
13250 areg = gen_rtx_REG (Pmode, 0);
13251 emit_move_insn (areg, GEN_INT (offset));
13252
13253 /* AltiVec addressing mode is [reg+reg]. */
13254 mem = gen_rtx_MEM (V4SImode,
13255 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
f676971a 13256
9aa86737
AH		 13257 set_mem_alias_set (mem, rs6000_sr_alias_set);
13258
13259 insn = emit_move_insn (mem, savereg);
13260
5c242421
SB		 13261 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13262 areg, GEN_INT (offset));
9aa86737
AH		 13263 }
13264 }
13265
13266 /* VRSAVE is a bit vector representing which AltiVec registers
13267 are used. The OS uses this to determine which vector
13268 registers to save on a context switch. We need to save
13269 VRSAVE on the stack frame, add whatever AltiVec registers we
13270 used in this function, and do the corresponding magic in the
13271 epilogue. */
13272
4d774ff8 13273 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
f57fe068 13274 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
9aa86737 13275 {
a004eb82 13276 rtx reg, mem, vrsave;
9aa86737
AH		 13277 int offset;
13278
eab97e44
AM		 13279 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
13280 as frame_reg_rtx and r11 as the static chain pointer for
13281 nested functions. */
13282 reg = gen_rtx_REG (SImode, 0);
a004eb82 13283 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
b188f760
AH		 13284 if (TARGET_MACHO)
13285 emit_insn (gen_get_vrsave_internal (reg));
13286 else
13287 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
9aa86737
AH		 13288
13289 /* Save VRSAVE. */
13290 offset = info->vrsave_save_offset + sp_offset;
13291 mem
13292 = gen_rtx_MEM (SImode,
13293 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
13294 set_mem_alias_set (mem, rs6000_sr_alias_set);
13295 insn = emit_move_insn (mem, reg);
13296
13297 /* Include the registers in the mask. */
13298 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
13299
13300 insn = emit_insn (generate_set_vrsave (reg, info, 0));
13301 }
13302
9ebbca7d 13303 /* If we use the link register, get it into r0. */
f57fe068 13304 if (!WORLD_SAVE_P (info) && info->lr_save_p)
f8a57be8
GK		 13305 {
13306 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13307 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13308 RTX_FRAME_RELATED_P (insn) = 1;
13309 }
9ebbca7d
GK		 13310
13311 /* If we need to save CR, put it into r12. */
f57fe068 13312 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
9ebbca7d 13313 {
f8a57be8 13314 rtx set;
f676971a 13315
9ebbca7d 13316 cr_save_rtx = gen_rtx_REG (SImode, 12);
f8a57be8
GK		 13317 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13318 RTX_FRAME_RELATED_P (insn) = 1;
13319 /* Now, there's no way that dwarf2out_frame_debug_expr is going
13320 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
13321 But that's OK. All we have to do is specify that _one_ condition
13322 code register is saved in this stack slot. The thrower's epilogue
13323 will then restore all the call-saved registers.
13324 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
13325 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
13326 gen_rtx_REG (SImode, CR2_REGNO));
13327 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13328 set,
13329 REG_NOTES (insn));
9ebbca7d
GK		 13330 }
13331
a4f6c312
SS		 13332 /* Do any required saving of fpr's. If only one or two to save, do
13333 it ourselves. Otherwise, call function. */
f57fe068 13334 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
9ebbca7d
GK		 13335 {
13336 int i;
13337 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 13338 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d 13339 && ! call_used_regs[info->first_fp_reg_save+i]))
89e7058f
AH		 13340 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
13341 info->first_fp_reg_save + i,
13342 info->fp_save_offset + sp_offset + 8 * i,
13343 info->total_size);
9ebbca7d 13344 }
f57fe068 13345 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
9ebbca7d
GK		 13346 {
13347 int i;
13348 char rname[30];
520a57c8 13349 const char *alloc_rname;
9ebbca7d
GK		 13350 rtvec p;
13351 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
f676971a
EC		 13352
13353 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
13354 gen_rtx_REG (Pmode,
9ebbca7d
GK		 13355 LINK_REGISTER_REGNUM));
13356 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
13357 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
a8a05998 13358 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 13359 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13360 gen_rtx_SYMBOL_REF (Pmode,
13361 alloc_rname));
13362 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13363 {
13364 rtx addr, reg, mem;
13365 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13366 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a 13367 GEN_INT (info->fp_save_offset
9ebbca7d
GK		 13368 + sp_offset + 8*i));
13369 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 13370 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13371
13372 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
13373 }
13374 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 13375 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d
GK		 13376 NULL_RTX, NULL_RTX);
13377 }
b6c9286a 13378
9ebbca7d
GK		 13379 /* Save GPRs. This is done as a PARALLEL if we are using
13380 the store-multiple instructions. */
f57fe068 13381 if (!WORLD_SAVE_P (info) && using_store_multiple)
b6c9286a 13382 {
308c142a 13383 rtvec p;
9ebbca7d
GK		 13384 int i;
13385 p = rtvec_alloc (32 - info->first_gp_reg_save);
9ebbca7d
GK		 13386 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13387 {
13388 rtx addr, reg, mem;
13389 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
f676971a
EC		 13390 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13391 GEN_INT (info->gp_save_offset
13392 + sp_offset
9ebbca7d
GK		 13393 + reg_size * i));
13394 mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 13395 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13396
13397 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
13398 }
13399 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 13400 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d 13401 NULL_RTX, NULL_RTX);
b6c9286a 13402 }
f57fe068 13403 else if (!WORLD_SAVE_P (info))
b6c9286a 13404 {
9ebbca7d
GK		 13405 int i;
13406 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
f676971a 13407 if ((regs_ever_live[info->first_gp_reg_save+i]
b4db40bf
JJ		 13408 && (! call_used_regs[info->first_gp_reg_save+i]
13409 || (i+info->first_gp_reg_save
13410 == RS6000_PIC_OFFSET_TABLE_REGNUM
13411 && TARGET_TOC && TARGET_MINIMAL_TOC)))
1db02437 13412 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 13413 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 13414 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
a3170dc6
AH		 13415 {
13416 rtx addr, reg, mem;
13417 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13418
c19de7aa 13419 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13420 {
13421 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13422 rtx b;
13423
13424 if (!SPE_CONST_OFFSET_OK (offset))
13425 {
13426 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13427 emit_move_insn (b, GEN_INT (offset));
13428 }
13429 else
13430 b = GEN_INT (offset);
13431
13432 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13433 mem = gen_rtx_MEM (V2SImode, addr);
13434 set_mem_alias_set (mem, rs6000_sr_alias_set);
13435 insn = emit_move_insn (mem, reg);
13436
13437 if (GET_CODE (b) == CONST_INT)
13438 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13439 NULL_RTX, NULL_RTX);
13440 else
13441 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13442 b, GEN_INT (offset));
13443 }
13444 else
13445 {
f676971a
EC		 13446 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13447 GEN_INT (info->gp_save_offset
13448 + sp_offset
a3170dc6
AH		 13449 + reg_size * i));
13450 mem = gen_rtx_MEM (reg_mode, addr);
13451 set_mem_alias_set (mem, rs6000_sr_alias_set);
13452
13453 insn = emit_move_insn (mem, reg);
f676971a 13454 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
a3170dc6
AH		 13455 NULL_RTX, NULL_RTX);
13456 }
13457 }
9ebbca7d
GK		 13458 }
13459
83720594
RH		 13460 /* ??? There's no need to emit actual instructions here, but it's the
13461 easiest way to get the frame unwind information emitted. */
f57fe068 13462 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
83720594 13463 {
78e1b90d
DE		 13464 unsigned int i, regno;
13465
fc4767bb
JJ		 13466 /* In AIX ABI we need to pretend we save r2 here. */
13467 if (TARGET_AIX)
13468 {
13469 rtx addr, reg, mem;
13470
13471 reg = gen_rtx_REG (reg_mode, 2);
13472 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13473 GEN_INT (sp_offset + 5 * reg_size));
13474 mem = gen_rtx_MEM (reg_mode, addr);
13475 set_mem_alias_set (mem, rs6000_sr_alias_set);
13476
13477 insn = emit_move_insn (mem, reg);
f676971a 13478 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
fc4767bb
JJ		 13479 NULL_RTX, NULL_RTX);
13480 PATTERN (insn) = gen_blockage ();
13481 }
13482
83720594
RH		 13483 for (i = 0; ; ++i)
13484 {
83720594
RH		 13485 regno = EH_RETURN_DATA_REGNO (i);
13486 if (regno == INVALID_REGNUM)
13487 break;
13488
89e7058f
AH		 13489 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13490 info->ehrd_offset + sp_offset
13491 + reg_size * (int) i,
13492 info->total_size);
83720594
RH		 13493 }
13494 }
13495
9ebbca7d 13496 /* Save lr if we used it. */
f57fe068 13497 if (!WORLD_SAVE_P (info) && info->lr_save_p)
9ebbca7d
GK		 13498 {
13499 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13500 GEN_INT (info->lr_save_offset + sp_offset));
13501 rtx reg = gen_rtx_REG (Pmode, 0);
13502 rtx mem = gen_rtx_MEM (Pmode, addr);
13503 /* This should not be of rs6000_sr_alias_set, because of
13504 __builtin_return_address. */
f676971a 13505
9ebbca7d 13506 insn = emit_move_insn (mem, reg);
f676971a 13507 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13508 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13509 }
13510
13511 /* Save CR if we use any that must be preserved. */
f57fe068 13512 if (!WORLD_SAVE_P (info) && info->cr_save_p)
9ebbca7d
GK		 13513 {
13514 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13515 GEN_INT (info->cr_save_offset + sp_offset));
13516 rtx mem = gen_rtx_MEM (SImode, addr);
f8a57be8
GK		 13517 /* See the large comment above about why CR2_REGNO is used. */
13518 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
ba4828e0
RK		 13519
13520 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13521
13522 /* If r12 was used to hold the original sp, copy cr into r0 now
13523 that it's free. */
13524 if (REGNO (frame_reg_rtx) == 12)
13525 {
f8a57be8
GK		 13526 rtx set;
13527
9ebbca7d 13528 cr_save_rtx = gen_rtx_REG (SImode, 0);
f8a57be8
GK		 13529 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13530 RTX_FRAME_RELATED_P (insn) = 1;
13531 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13532 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13533 set,
13534 REG_NOTES (insn));
f676971a 13535
9ebbca7d
GK		 13536 }
13537 insn = emit_move_insn (mem, cr_save_rtx);
13538
f676971a 13539 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13540 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13541 }
13542
f676971a 13543 /* Update stack and set back pointer unless this is V.4,
9ebbca7d 13544 for which it was done previously. */
f57fe068 13545 if (!WORLD_SAVE_P (info) && info->push_p
fc4767bb 13546 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
9ebbca7d
GK		 13547 rs6000_emit_allocate_stack (info->total_size, FALSE);
13548
13549 /* Set frame pointer, if needed. */
13550 if (frame_pointer_needed)
13551 {
f676971a 13552 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
9ebbca7d
GK		 13553 sp_reg_rtx);
13554 RTX_FRAME_RELATED_P (insn) = 1;
b6c9286a 13555 }
9878760c 13556
1db02437 13557 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
9ebbca7d 13558 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
f607bc57 13559 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
1db02437 13560 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
c4ad648e
AM		 13561 {
13562 /* If emit_load_toc_table will use the link register, we need to save
13563 it. We use R12 for this purpose because emit_load_toc_table
13564 can use register 0. This allows us to use a plain 'blr' to return
13565 from the procedure more often. */
13566 int save_LR_around_toc_setup = (TARGET_ELF
13567 && DEFAULT_ABI != ABI_AIX
13568 && flag_pic
13569 && ! info->lr_save_p
13570 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13571 if (save_LR_around_toc_setup)
13572 {
13573 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
f8a57be8 13574
c4ad648e
AM		 13575 insn = emit_move_insn (frame_ptr_rtx, lr);
13576 rs6000_maybe_dead (insn);
13577 RTX_FRAME_RELATED_P (insn) = 1;
f8a57be8 13578
c4ad648e 13579 rs6000_emit_load_toc_table (TRUE);
f8a57be8 13580
c4ad648e
AM		 13581 insn = emit_move_insn (lr, frame_ptr_rtx);
13582 rs6000_maybe_dead (insn);
13583 RTX_FRAME_RELATED_P (insn) = 1;
13584 }
13585 else
13586 rs6000_emit_load_toc_table (TRUE);
13587 }
ee890fe2 13588
fcce224d 13589#if TARGET_MACHO
ee890fe2
SS		 13590 if (DEFAULT_ABI == ABI_DARWIN
13591 && flag_pic && current_function_uses_pic_offset_table)
13592 {
f8a57be8 13593 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11abc112 13594 rtx src = machopic_function_base_sym ();
ee890fe2 13595
f8a57be8 13596 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
ee890fe2 13597
f676971a 13598 insn = emit_move_insn (gen_rtx_REG (Pmode,
f8a57be8
GK		 13599 RS6000_PIC_OFFSET_TABLE_REGNUM),
13600 lr);
13601 rs6000_maybe_dead (insn);
ee890fe2 13602 }
fcce224d 13603#endif
9ebbca7d
GK		 13604}
13605
9ebbca7d 13606/* Write function prologue. */
a4f6c312 13607
08c148a8 13608static void
f676971a 13609rs6000_output_function_prologue (FILE *file,
a2369ed3 13610 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9ebbca7d
GK		 13611{
13612 rs6000_stack_t *info = rs6000_stack_info ();
13613
4697a36c
MM		 13614 if (TARGET_DEBUG_STACK)
13615 debug_stack_info (info);
9878760c 13616
a4f6c312
SS		 13617 /* Write .extern for any function we will call to save and restore
13618 fp values. */
13619 if (info->first_fp_reg_save < 64
13620 && !FP_SAVE_INLINE (info->first_fp_reg_save))
4d30c363 13621 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
4697a36c 13622 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
a4f6c312
SS		 13623 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13624 RESTORE_FP_SUFFIX);
9878760c 13625
c764f757
RK		 13626 /* Write .extern for AIX common mode routines, if needed. */
13627 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13628 {
f6709c70
JW		 13629 fputs ("\t.extern __mulh\n", file);
13630 fputs ("\t.extern __mull\n", file);
13631 fputs ("\t.extern __divss\n", file);
13632 fputs ("\t.extern __divus\n", file);
13633 fputs ("\t.extern __quoss\n", file);
13634 fputs ("\t.extern __quous\n", file);
c764f757
RK		 13635 common_mode_defined = 1;
13636 }
9878760c 13637
9ebbca7d 13638 if (! HAVE_prologue)
979721f8 13639 {
9ebbca7d 13640 start_sequence ();
9dda4cc8 13641
a4f6c312
SS		 13642 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13643 the "toplevel" insn chain. */
2e040219 13644 emit_note (NOTE_INSN_DELETED);
9ebbca7d 13645 rs6000_emit_prologue ();
2e040219 13646 emit_note (NOTE_INSN_DELETED);
178c3eff 13647
a3c9585f 13648 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 13649 {
13650 rtx insn;
13651 unsigned addr = 0;
13652 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13653 {
13654 INSN_ADDRESSES_NEW (insn, addr);
13655 addr += 4;
13656 }
13657 }
9dda4cc8 13658
9ebbca7d 13659 if (TARGET_DEBUG_STACK)
a4f6c312 13660 debug_rtx_list (get_insns (), 100);
c9d691e9 13661 final (get_insns (), file, FALSE);
9ebbca7d 13662 end_sequence ();
979721f8
MM		 13663 }
13664
9ebbca7d
GK		 13665 rs6000_pic_labelno++;
13666}
f676971a 13667
9ebbca7d 13668/* Emit function epilogue as insns.
9878760c 13669
9ebbca7d
GK		 13670 At present, dwarf2out_frame_debug_expr doesn't understand
13671 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13672 anywhere in the epilogue. Most of the insns below would in any case
13673 need special notes to explain where r11 is in relation to the stack. */
9878760c 13674
9ebbca7d 13675void
a2369ed3 13676rs6000_emit_epilogue (int sibcall)
9ebbca7d
GK		 13677{
13678 rs6000_stack_t *info;
13679 int restoring_FPRs_inline;
13680 int using_load_multiple;
13681 int using_mfcr_multiple;
13682 int use_backchain_to_restore_sp;
13683 int sp_offset = 0;
13684 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13685 rtx frame_reg_rtx = sp_reg_rtx;
0e67400a 13686 enum machine_mode reg_mode = Pmode;
327e5343 13687 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 13688 int i;
13689
c19de7aa
AH		 13690 info = rs6000_stack_info ();
13691
13692 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13693 {
13694 reg_mode = V2SImode;
13695 reg_size = 8;
13696 }
13697
9ebbca7d 13698 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 13699 && (!TARGET_SPE_ABI
13700 || info->spe_64bit_regs_used == 0)
9ebbca7d
GK		 13701 && info->first_gp_reg_save < 31);
13702 restoring_FPRs_inline = (sibcall
83720594 13703 || current_function_calls_eh_return
9ebbca7d
GK		 13704 || info->first_fp_reg_save == 64
13705 || FP_SAVE_INLINE (info->first_fp_reg_save));
f676971a 13706 use_backchain_to_restore_sp = (frame_pointer_needed
9ebbca7d
GK		 13707 || current_function_calls_alloca
13708 || info->total_size > 32767);
13709 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13710 || rs6000_cpu == PROCESSOR_PPC603
13711 || rs6000_cpu == PROCESSOR_PPC750
13712 || optimize_size);
13713
f57fe068 13714 if (WORLD_SAVE_P (info))
d62294f5
FJ		 13715 {
13716 int i, j;
13717 char rname[30];
13718 const char *alloc_rname;
13719 rtvec p;
13720
13721 /* eh_rest_world_r10 will return to the location saved in the LR
c4ad648e
AM		 13722 stack slot (which is not likely to be our caller.)
13723 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13724 rest_world is similar, except any R10 parameter is ignored.
13725 The exception-handling stuff that was here in 2.95 is no
13726 longer necessary. */
d62294f5
FJ		 13727
13728 p = rtvec_alloc (9
13729 + 1
f676971a 13730 + 32 - info->first_gp_reg_save
c4ad648e
AM		 13731 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13732 + 63 + 1 - info->first_fp_reg_save);
d62294f5 13733
c4ad648e
AM		 13734 strcpy (rname, ((current_function_calls_eh_return) ?
13735 "*eh_rest_world_r10" : "*rest_world"));
d62294f5
FJ		 13736 alloc_rname = ggc_strdup (rname);
13737
13738 j = 0;
13739 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13740 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 13741 gen_rtx_REG (Pmode,
13742 LINK_REGISTER_REGNUM));
d62294f5 13743 RTVEC_ELT (p, j++)
c4ad648e 13744 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
d62294f5 13745 /* The instruction pattern requires a clobber here;
c4ad648e 13746 it is shared with the restVEC helper. */
d62294f5 13747 RTVEC_ELT (p, j++)
c4ad648e 13748 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
d62294f5
FJ		 13749
13750 {
c4ad648e
AM		 13751 /* CR register traditionally saved as CR2. */
13752 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13753 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13754 GEN_INT (info->cr_save_offset));
13755 rtx mem = gen_rtx_MEM (reg_mode, addr);
13756 set_mem_alias_set (mem, rs6000_sr_alias_set);
13757
13758 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
d62294f5
FJ		 13759 }
13760
13761 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 13762 {
13763 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13764 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13765 GEN_INT (info->gp_save_offset
13766 + reg_size * i));
13767 rtx mem = gen_rtx_MEM (reg_mode, addr);
13768 set_mem_alias_set (mem, rs6000_sr_alias_set);
13769
13770 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13771 }
d62294f5 13772 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 13773 {
13774 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13775 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13776 GEN_INT (info->altivec_save_offset
13777 + 16 * i));
13778 rtx mem = gen_rtx_MEM (V4SImode, addr);
13779 set_mem_alias_set (mem, rs6000_sr_alias_set);
13780
13781 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13782 }
d62294f5 13783 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
c4ad648e
AM		 13784 {
13785 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13786 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13787 GEN_INT (info->fp_save_offset
13788 + 8 * i));
13789 rtx mem = gen_rtx_MEM (DFmode, addr);
13790 set_mem_alias_set (mem, rs6000_sr_alias_set);
13791
13792 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13793 }
d62294f5 13794 RTVEC_ELT (p, j++)
c4ad648e 13795 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
d62294f5 13796 RTVEC_ELT (p, j++)
c4ad648e 13797 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
d62294f5 13798 RTVEC_ELT (p, j++)
c4ad648e 13799 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
d62294f5 13800 RTVEC_ELT (p, j++)
c4ad648e 13801 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
d62294f5 13802 RTVEC_ELT (p, j++)
c4ad648e 13803 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
d62294f5
FJ		 13804 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13805
13806 return;
13807 }
13808
9ebbca7d
GK		 13809 /* If we have a frame pointer, a call to alloca, or a large stack
13810 frame, restore the old stack pointer using the backchain. Otherwise,
13811 we know what size to update it with. */
13812 if (use_backchain_to_restore_sp)
bacbde18 13813 {
9ebbca7d
GK		 13814 /* Under V.4, don't reset the stack pointer until after we're done
13815 loading the saved registers. */
f607bc57 13816 if (DEFAULT_ABI == ABI_V4)
9ebbca7d 13817 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
4697a36c 13818
9ebbca7d
GK		 13819 emit_move_insn (frame_reg_rtx,
13820 gen_rtx_MEM (Pmode, sp_reg_rtx));
f676971a 13821
bacbde18 13822 }
9ebbca7d 13823 else if (info->push_p)
85638c0d 13824 {
fc4767bb
JJ		 13825 if (DEFAULT_ABI == ABI_V4
13826 || current_function_calls_eh_return)
9ebbca7d
GK		 13827 sp_offset = info->total_size;
13828 else
13829 {
13830 emit_insn (TARGET_32BIT
13831 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13832 GEN_INT (info->total_size))
13833 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13834 GEN_INT (info->total_size)));
13835 }
85638c0d 13836 }
f676971a 13837
9aa86737
AH		 13838 /* Restore AltiVec registers if needed. */
13839 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13840 {
13841 int i;
13842
13843 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13844 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13845 {
13846 rtx addr, areg, mem;
13847
13848 areg = gen_rtx_REG (Pmode, 0);
13849 emit_move_insn
13850 (areg, GEN_INT (info->altivec_save_offset
13851 + sp_offset
13852 + 16 * (i - info->first_altivec_reg_save)));
13853
13854 /* AltiVec addressing mode is [reg+reg]. */
13855 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
13856 mem = gen_rtx_MEM (V4SImode, addr);
13857 set_mem_alias_set (mem, rs6000_sr_alias_set);
13858
13859 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
13860 }
13861 }
13862
13863 /* Restore VRSAVE if needed. */
44688022 13864 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
4d774ff8 13865 && info->vrsave_mask != 0)
9aa86737
AH		 13866 {
13867 rtx addr, mem, reg;
13868
13869 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13870 GEN_INT (info->vrsave_save_offset + sp_offset));
13871 mem = gen_rtx_MEM (SImode, addr);
13872 set_mem_alias_set (mem, rs6000_sr_alias_set);
13873 reg = gen_rtx_REG (SImode, 12);
13874 emit_move_insn (reg, mem);
13875
13876 emit_insn (generate_set_vrsave (reg, info, 1));
13877 }
13878
9ebbca7d
GK		 13879 /* Get the old lr if we saved it. */
13880 if (info->lr_save_p)
b6c9286a 13881 {
a3170dc6
AH		 13882 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
13883 info->lr_save_offset + sp_offset);
ba4828e0
RK		 13884
13885 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 13886
9ebbca7d 13887 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
b6c9286a 13888 }
f676971a 13889
9ebbca7d
GK		 13890 /* Get the old cr if we saved it. */
13891 if (info->cr_save_p)
13892 {
13893 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13894 GEN_INT (info->cr_save_offset + sp_offset));
13895 rtx mem = gen_rtx_MEM (SImode, addr);
ba4828e0
RK		 13896
13897 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 13898
9ebbca7d
GK		 13899 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
13900 }
f676971a 13901
9ebbca7d 13902 /* Set LR here to try to overlap restores below. */
4697a36c 13903 if (info->lr_save_p)
9ebbca7d
GK		 13904 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
13905 gen_rtx_REG (Pmode, 0));
f676971a 13906
83720594
RH		 13907 /* Load exception handler data registers, if needed. */
13908 if (current_function_calls_eh_return)
13909 {
78e1b90d
DE		 13910 unsigned int i, regno;
13911
fc4767bb
JJ		 13912 if (TARGET_AIX)
13913 {
13914 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13915 GEN_INT (sp_offset + 5 * reg_size));
13916 rtx mem = gen_rtx_MEM (reg_mode, addr);
13917
13918 set_mem_alias_set (mem, rs6000_sr_alias_set);
13919
13920 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
13921 }
13922
83720594
RH		 13923 for (i = 0; ; ++i)
13924 {
a3170dc6 13925 rtx mem;
83720594
RH		 13926
13927 regno = EH_RETURN_DATA_REGNO (i);
13928 if (regno == INVALID_REGNUM)
13929 break;
13930
a3170dc6
AH		 13931 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
13932 info->ehrd_offset + sp_offset
13933 + reg_size * (int) i);
ba4828e0 13934 set_mem_alias_set (mem, rs6000_sr_alias_set);
83720594
RH		 13935
13936 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
13937 }
13938 }
f676971a 13939
9ebbca7d
GK		 13940 /* Restore GPRs. This is done as a PARALLEL if we are using
13941 the load-multiple instructions. */
13942 if (using_load_multiple)
979721f8 13943 {
9ebbca7d
GK		 13944 rtvec p;
13945 p = rtvec_alloc (32 - info->first_gp_reg_save);
13946 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
979721f8 13947 {
f676971a
EC		 13948 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13949 GEN_INT (info->gp_save_offset
13950 + sp_offset
9ebbca7d
GK		 13951 + reg_size * i));
13952 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0
RK		 13953
13954 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13955
f676971a 13956 RTVEC_ELT (p, i) =
9ebbca7d
GK		 13957 gen_rtx_SET (VOIDmode,
13958 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
13959 mem);
979721f8 13960 }
9ebbca7d 13961 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
979721f8 13962 }
9ebbca7d
GK		 13963 else
13964 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
f676971a 13965 if ((regs_ever_live[info->first_gp_reg_save+i]
b4db40bf
JJ		 13966 && (! call_used_regs[info->first_gp_reg_save+i]
13967 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13968 && TARGET_TOC && TARGET_MINIMAL_TOC)))
1db02437 13969 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 13970 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 13971 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
9ebbca7d 13972 {
f676971a
EC		 13973 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13974 GEN_INT (info->gp_save_offset
13975 + sp_offset
9ebbca7d
GK		 13976 + reg_size * i));
13977 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 13978
a3170dc6 13979 /* Restore 64-bit quantities for SPE. */
c19de7aa 13980 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13981 {
13982 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13983 rtx b;
13984
13985 if (!SPE_CONST_OFFSET_OK (offset))
13986 {
13987 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13988 emit_move_insn (b, GEN_INT (offset));
13989 }
13990 else
13991 b = GEN_INT (offset);
13992
13993 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13994 mem = gen_rtx_MEM (V2SImode, addr);
13995 }
13996
ba4828e0 13997 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13998
f676971a 13999 emit_move_insn (gen_rtx_REG (reg_mode,
a3170dc6 14000 info->first_gp_reg_save + i), mem);
9ebbca7d 14001 }
9878760c 14002
9ebbca7d
GK		 14003 /* Restore fpr's if we need to do it without calling a function. */
14004 if (restoring_FPRs_inline)
14005 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 14006 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d
GK		 14007 && ! call_used_regs[info->first_fp_reg_save+i]))
14008 {
14009 rtx addr, mem;
14010 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a
EC		 14011 GEN_INT (info->fp_save_offset
14012 + sp_offset
a4f6c312 14013 + 8 * i));
9ebbca7d 14014 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 14015 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14016
f676971a 14017 emit_move_insn (gen_rtx_REG (DFmode,
9ebbca7d
GK		 14018 info->first_fp_reg_save + i),
14019 mem);
14020 }
8d30c4ee 14021
9ebbca7d
GK		 14022 /* If we saved cr, restore it here. Just those that were used. */
14023 if (info->cr_save_p)
979721f8 14024 {
9ebbca7d 14025 rtx r12_rtx = gen_rtx_REG (SImode, 12);
e35b9579 14026 int count = 0;
f676971a 14027
9ebbca7d 14028 if (using_mfcr_multiple)
979721f8 14029 {
9ebbca7d
GK		 14030 for (i = 0; i < 8; i++)
14031 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
e35b9579 14032 count++;
37409796 14033 gcc_assert (count);
e35b9579
GK		 14034 }
14035
14036 if (using_mfcr_multiple && count > 1)
14037 {
14038 rtvec p;
14039 int ndx;
f676971a 14040
e35b9579 14041 p = rtvec_alloc (count);
9ebbca7d 14042
e35b9579 14043 ndx = 0;
9ebbca7d
GK		 14044 for (i = 0; i < 8; i++)
14045 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14046 {
14047 rtvec r = rtvec_alloc (2);
14048 RTVEC_ELT (r, 0) = r12_rtx;
14049 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
e35b9579 14050 RTVEC_ELT (p, ndx) =
f676971a 14051 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
615158e2 14052 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
e35b9579 14053 ndx++;
9ebbca7d
GK		 14054 }
14055 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
37409796 14056 gcc_assert (ndx == count);
979721f8
MM		 14057 }
14058 else
9ebbca7d
GK		 14059 for (i = 0; i < 8; i++)
14060 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
979721f8 14061 {
f676971a 14062 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
9ebbca7d
GK		 14063 CR0_REGNO+i),
14064 r12_rtx));
979721f8 14065 }
979721f8
MM		 14066 }
14067
9ebbca7d
GK		 14068 /* If this is V.4, unwind the stack pointer after all of the loads
14069 have been done. We need to emit a block here so that sched
14070 doesn't decide to move the sp change before the register restores
14071 (which may not have any obvious dependency on the stack). This
14072 doesn't hurt performance, because there is no scheduling that can
14073 be done after this point. */
fc4767bb
JJ		 14074 if (DEFAULT_ABI == ABI_V4
14075 || current_function_calls_eh_return)
b6c9286a 14076 {
9ebbca7d 14077 if (frame_reg_rtx != sp_reg_rtx)
c4ad648e 14078 rs6000_emit_stack_tie ();
b6c9286a 14079
9ebbca7d 14080 if (use_backchain_to_restore_sp)
b6c9286a 14081 {
9ebbca7d 14082 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
b6c9286a 14083 }
9ebbca7d 14084 else if (sp_offset != 0)
13f1623b 14085 {
5b71a4e7 14086 emit_insn (TARGET_32BIT
9ebbca7d
GK		 14087 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14088 GEN_INT (sp_offset))
14089 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14090 GEN_INT (sp_offset)));
13f1623b 14091 }
9ebbca7d 14092 }
b6c9286a 14093
83720594
RH		 14094 if (current_function_calls_eh_return)
14095 {
14096 rtx sa = EH_RETURN_STACKADJ_RTX;
5b71a4e7 14097 emit_insn (TARGET_32BIT
83720594
RH		 14098 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14099 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14100 }
14101
9ebbca7d
GK		 14102 if (!sibcall)
14103 {
14104 rtvec p;
14105 if (! restoring_FPRs_inline)
14106 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14107 else
14108 p = rtvec_alloc (2);
b6c9286a 14109
e35b9579 14110 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
f676971a
EC		 14111 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14112 gen_rtx_REG (Pmode,
9ebbca7d 14113 LINK_REGISTER_REGNUM));
9ebbca7d
GK		 14114
14115 /* If we have to restore more than two FP registers, branch to the
14116 restore function. It will return to our caller. */
14117 if (! restoring_FPRs_inline)
14118 {
14119 int i;
14120 char rname[30];
520a57c8 14121 const char *alloc_rname;
979721f8 14122
f676971a 14123 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
9ebbca7d 14124 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
a8a05998 14125 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 14126 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14127 gen_rtx_SYMBOL_REF (Pmode,
14128 alloc_rname));
b6c9286a 14129
9ebbca7d
GK		 14130 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14131 {
14132 rtx addr, mem;
14133 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14134 GEN_INT (info->fp_save_offset + 8*i));
14135 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 14136 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14137
f676971a 14138 RTVEC_ELT (p, i+3) =
9ebbca7d
GK		 14139 gen_rtx_SET (VOIDmode,
14140 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14141 mem);
b6c9286a
MM		 14142 }
14143 }
f676971a 14144
9ebbca7d 14145 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
3daf36a4 14146 }
9878760c
RK		 14147}
14148
14149/* Write function epilogue. */
14150
08c148a8 14151static void
f676971a 14152rs6000_output_function_epilogue (FILE *file,
a2369ed3 14153 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9878760c 14154{
4697a36c 14155 rs6000_stack_t *info = rs6000_stack_info ();
9878760c 14156
9ebbca7d 14157 if (! HAVE_epilogue)
9878760c 14158 {
9ebbca7d
GK		 14159 rtx insn = get_last_insn ();
14160 /* If the last insn was a BARRIER, we don't have to write anything except
14161 the trace table. */
14162 if (GET_CODE (insn) == NOTE)
14163 insn = prev_nonnote_insn (insn);
14164 if (insn == 0 || GET_CODE (insn) != BARRIER)
4697a36c 14165 {
9ebbca7d
GK		 14166 /* This is slightly ugly, but at least we don't have two
14167 copies of the epilogue-emitting code. */
14168 start_sequence ();
14169
14170 /* A NOTE_INSN_DELETED is supposed to be at the start
14171 and end of the "toplevel" insn chain. */
2e040219 14172 emit_note (NOTE_INSN_DELETED);
9ebbca7d 14173 rs6000_emit_epilogue (FALSE);
2e040219 14174 emit_note (NOTE_INSN_DELETED);
9ebbca7d 14175
a3c9585f 14176 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 14177 {
14178 rtx insn;
14179 unsigned addr = 0;
14180 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14181 {
14182 INSN_ADDRESSES_NEW (insn, addr);
14183 addr += 4;
14184 }
14185 }
14186
9ebbca7d 14187 if (TARGET_DEBUG_STACK)
a4f6c312 14188 debug_rtx_list (get_insns (), 100);
c9d691e9 14189 final (get_insns (), file, FALSE);
9ebbca7d 14190 end_sequence ();
4697a36c 14191 }
9878760c 14192 }
b4ac57ab 14193
efdba735
SH		 14194#if TARGET_MACHO
14195 macho_branch_islands ();
0e5da0be
GK		 14196 /* Mach-O doesn't support labels at the end of objects, so if
14197 it looks like we might want one, insert a NOP. */
14198 {
14199 rtx insn = get_last_insn ();
14200 while (insn
14201 && NOTE_P (insn)
14202 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14203 insn = PREV_INSN (insn);
f676971a
EC		 14204 if (insn
14205 && (LABEL_P (insn)
0e5da0be
GK		 14206 || (NOTE_P (insn)
14207 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14208 fputs ("\tnop\n", file);
14209 }
14210#endif
14211
9b30bae2 14212 /* Output a traceback table here. See /usr/include/sys/debug.h for info
314fc5a9
ILT		 14213 on its format.
14214
14215 We don't output a traceback table if -finhibit-size-directive was
14216 used. The documentation for -finhibit-size-directive reads
14217 ``don't output a @code{.size} assembler directive, or anything
14218 else that would cause trouble if the function is split in the
14219 middle, and the two halves are placed at locations far apart in
14220 memory.'' The traceback table has this property, since it
14221 includes the offset from the start of the function to the
4d30c363
MM		 14222 traceback table itself.
14223
14224 System V.4 Powerpc's (and the embedded ABI derived from it) use a
b6c9286a 14225 different traceback table. */
57ac7be9
AM		 14226 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
14227 && rs6000_traceback != traceback_none)
9b30bae2 14228 {
69c75916 14229 const char *fname = NULL;
3ac88239 14230 const char *language_string = lang_hooks.name;
6041bf2f 14231 int fixed_parms = 0, float_parms = 0, parm_info = 0;
314fc5a9 14232 int i;
57ac7be9
AM		 14233 int optional_tbtab;
14234
14235 if (rs6000_traceback == traceback_full)
14236 optional_tbtab = 1;
14237 else if (rs6000_traceback == traceback_part)
14238 optional_tbtab = 0;
14239 else
14240 optional_tbtab = !optimize_size && !TARGET_ELF;
314fc5a9 14241
69c75916
AM		 14242 if (optional_tbtab)
14243 {
14244 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14245 while (*fname == '.') /* V.4 encodes . in the name */
14246 fname++;
14247
14248 /* Need label immediately before tbtab, so we can compute
14249 its offset from the function start. */
14250 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14251 ASM_OUTPUT_LABEL (file, fname);
14252 }
314fc5a9
ILT		 14253
14254 /* The .tbtab pseudo-op can only be used for the first eight
14255 expressions, since it can't handle the possibly variable
14256 length fields that follow. However, if you omit the optional
14257 fields, the assembler outputs zeros for all optional fields
14258 anyways, giving each variable length field is minimum length
14259 (as defined in sys/debug.h). Thus we can not use the .tbtab
14260 pseudo-op at all. */
14261
14262 /* An all-zero word flags the start of the tbtab, for debuggers
14263 that have to find it by searching forward from the entry
14264 point or from the current pc. */
19d2d16f 14265 fputs ("\t.long 0\n", file);
314fc5a9
ILT		 14266
14267 /* Tbtab format type. Use format type 0. */
19d2d16f 14268 fputs ("\t.byte 0,", file);
314fc5a9 14269
5fc921c1
DE		 14270 /* Language type. Unfortunately, there does not seem to be any
14271 official way to discover the language being compiled, so we
14272 use language_string.
14273 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
14274 Java is 13. Objective-C is 14. */
14275 if (! strcmp (language_string, "GNU C"))
314fc5a9 14276 i = 0;
6de9cd9a
DN		 14277 else if (! strcmp (language_string, "GNU F77")
14278 || ! strcmp (language_string, "GNU F95"))
314fc5a9 14279 i = 1;
8b83775b 14280 else if (! strcmp (language_string, "GNU Pascal"))
314fc5a9 14281 i = 2;
5fc921c1
DE		 14282 else if (! strcmp (language_string, "GNU Ada"))
14283 i = 3;
314fc5a9
ILT		 14284 else if (! strcmp (language_string, "GNU C++"))
14285 i = 9;
9517ead8
AG		 14286 else if (! strcmp (language_string, "GNU Java"))
14287 i = 13;
5fc921c1
DE		 14288 else if (! strcmp (language_string, "GNU Objective-C"))
14289 i = 14;
314fc5a9 14290 else
37409796 14291 gcc_unreachable ();
314fc5a9
ILT		 14292 fprintf (file, "%d,", i);
14293
14294 /* 8 single bit fields: global linkage (not set for C extern linkage,
14295 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
14296 from start of procedure stored in tbtab, internal function, function
14297 has controlled storage, function has no toc, function uses fp,
14298 function logs/aborts fp operations. */
14299 /* Assume that fp operations are used if any fp reg must be saved. */
6041bf2f
DE		 14300 fprintf (file, "%d,",
14301 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
314fc5a9
ILT		 14302
14303 /* 6 bitfields: function is interrupt handler, name present in
14304 proc table, function calls alloca, on condition directives
14305 (controls stack walks, 3 bits), saves condition reg, saves
14306 link reg. */
14307 /* The `function calls alloca' bit seems to be set whenever reg 31 is
14308 set up as a frame pointer, even when there is no alloca call. */
14309 fprintf (file, "%d,",
6041bf2f
DE		 14310 ((optional_tbtab << 6)
14311 | ((optional_tbtab & frame_pointer_needed) << 5)
14312 | (info->cr_save_p << 1)
14313 | (info->lr_save_p)));
314fc5a9 14314
6041bf2f 14315 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
314fc5a9
ILT		 14316 (6 bits). */
14317 fprintf (file, "%d,",
4697a36c 14318 (info->push_p << 7) | (64 - info->first_fp_reg_save));
314fc5a9
ILT		 14319
14320 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
14321 fprintf (file, "%d,", (32 - first_reg_to_save ()));
14322
6041bf2f
DE		 14323 if (optional_tbtab)
14324 {
14325 /* Compute the parameter info from the function decl argument
14326 list. */
14327 tree decl;
14328 int next_parm_info_bit = 31;
314fc5a9 14329
6041bf2f
DE		 14330 for (decl = DECL_ARGUMENTS (current_function_decl);
14331 decl; decl = TREE_CHAIN (decl))
14332 {
14333 rtx parameter = DECL_INCOMING_RTL (decl);
14334 enum machine_mode mode = GET_MODE (parameter);
314fc5a9 14335
6041bf2f
DE		 14336 if (GET_CODE (parameter) == REG)
14337 {
14338 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
14339 {
14340 int bits;
14341
14342 float_parms++;
14343
37409796
NS		 14344 switch (mode)
14345 {
14346 case SFmode:
14347 bits = 0x2;
14348 break;
14349
14350 case DFmode:
14351 case TFmode:
14352 bits = 0x3;
14353 break;
14354
14355 default:
14356 gcc_unreachable ();
14357 }
6041bf2f
DE		 14358
14359 /* If only one bit will fit, don't or in this entry. */
14360 if (next_parm_info_bit > 0)
14361 parm_info |= (bits << (next_parm_info_bit - 1));
14362 next_parm_info_bit -= 2;
14363 }
14364 else
14365 {
14366 fixed_parms += ((GET_MODE_SIZE (mode)
14367 + (UNITS_PER_WORD - 1))
14368 / UNITS_PER_WORD);
14369 next_parm_info_bit -= 1;
14370 }
14371 }
14372 }
14373 }
314fc5a9
ILT		 14374
14375 /* Number of fixed point parameters. */
14376 /* This is actually the number of words of fixed point parameters; thus
14377 an 8 byte struct counts as 2; and thus the maximum value is 8. */
14378 fprintf (file, "%d,", fixed_parms);
14379
14380 /* 2 bitfields: number of floating point parameters (7 bits), parameters
14381 all on stack. */
14382 /* This is actually the number of fp registers that hold parameters;
14383 and thus the maximum value is 13. */
14384 /* Set parameters on stack bit if parameters are not in their original
14385 registers, regardless of whether they are on the stack? Xlc
14386 seems to set the bit when not optimizing. */
14387 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
14388
6041bf2f
DE		 14389 if (! optional_tbtab)
14390 return;
14391
314fc5a9
ILT		 14392 /* Optional fields follow. Some are variable length. */
14393
14394 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
14395 11 double float. */
14396 /* There is an entry for each parameter in a register, in the order that
14397 they occur in the parameter list. Any intervening arguments on the
14398 stack are ignored. If the list overflows a long (max possible length
14399 34 bits) then completely leave off all elements that don't fit. */
14400 /* Only emit this long if there was at least one parameter. */
14401 if (fixed_parms || float_parms)
14402 fprintf (file, "\t.long %d\n", parm_info);
14403
14404 /* Offset from start of code to tb table. */
19d2d16f 14405 fputs ("\t.long ", file);
314fc5a9 14406 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
85b776df
AM		 14407 if (TARGET_AIX)
14408 RS6000_OUTPUT_BASENAME (file, fname);
14409 else
14410 assemble_name (file, fname);
14411 putc ('-', file);
14412 rs6000_output_function_entry (file, fname);
19d2d16f 14413 putc ('\n', file);
314fc5a9
ILT		 14414
14415 /* Interrupt handler mask. */
14416 /* Omit this long, since we never set the interrupt handler bit
14417 above. */
14418
14419 /* Number of CTL (controlled storage) anchors. */
14420 /* Omit this long, since the has_ctl bit is never set above. */
14421
14422 /* Displacement into stack of each CTL anchor. */
14423 /* Omit this list of longs, because there are no CTL anchors. */
14424
14425 /* Length of function name. */
69c75916
AM		 14426 if (*fname == '*')
14427 ++fname;
296b8152 14428 fprintf (file, "\t.short %d\n", (int) strlen (fname));
314fc5a9
ILT		 14429
14430 /* Function name. */
14431 assemble_string (fname, strlen (fname));
14432
14433 /* Register for alloca automatic storage; this is always reg 31.
14434 Only emit this if the alloca bit was set above. */
14435 if (frame_pointer_needed)
19d2d16f 14436 fputs ("\t.byte 31\n", file);
b1765bde
DE		 14437
14438 fputs ("\t.align 2\n", file);
9b30bae2 14439 }
9878760c 14440}
17167fd8 14441\f
a4f6c312
SS		 14442/* A C compound statement that outputs the assembler code for a thunk
14443 function, used to implement C++ virtual function calls with
14444 multiple inheritance. The thunk acts as a wrapper around a virtual
14445 function, adjusting the implicit object parameter before handing
14446 control off to the real function.
14447
14448 First, emit code to add the integer DELTA to the location that
14449 contains the incoming first argument. Assume that this argument
14450 contains a pointer, and is the one used to pass the `this' pointer
14451 in C++. This is the incoming argument *before* the function
14452 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14453 values of all other incoming arguments.
17167fd8
MM		 14454
14455 After the addition, emit code to jump to FUNCTION, which is a
a4f6c312
SS		 14456 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14457 not touch the return address. Hence returning from FUNCTION will
14458 return to whoever called the current `thunk'.
17167fd8 14459
a4f6c312
SS		 14460 The effect must be as if FUNCTION had been called directly with the
14461 adjusted first argument. This macro is responsible for emitting
14462 all of the code for a thunk function; output_function_prologue()
14463 and output_function_epilogue() are not invoked.
17167fd8 14464
a4f6c312
SS		 14465 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14466 been extracted from it.) It might possibly be useful on some
14467 targets, but probably not.
17167fd8 14468
a4f6c312
SS		 14469 If you do not define this macro, the target-independent code in the
14470 C++ frontend will generate a less efficient heavyweight thunk that
14471 calls FUNCTION instead of jumping to it. The generic approach does
14472 not support varargs. */
17167fd8 14473
3961e8fe 14474static void
f676971a
EC		 14475rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14476 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
a2369ed3 14477 tree function)
17167fd8 14478{
5b71a4e7 14479 rtx this, insn, funexp;
17167fd8 14480
5b71a4e7 14481 reload_completed = 1;
fe3ad572 14482 epilogue_completed = 1;
5b71a4e7 14483 no_new_pseudos = 1;
6429e3be 14484 reset_block_changes ();
56a7189a 14485
5b71a4e7 14486 /* Mark the end of the (empty) prologue. */
2e040219 14487 emit_note (NOTE_INSN_PROLOGUE_END);
17167fd8 14488
5b71a4e7
DE		 14489 /* Find the "this" pointer. If the function returns a structure,
14490 the structure return pointer is in r3. */
61f71b34 14491 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
5b71a4e7 14492 this = gen_rtx_REG (Pmode, 4);
56a7189a 14493 else
5b71a4e7 14494 this = gen_rtx_REG (Pmode, 3);
17167fd8 14495
5b71a4e7
DE		 14496 /* Apply the constant offset, if required. */
14497 if (delta)
14498 {
14499 rtx delta_rtx = GEN_INT (delta);
14500 emit_insn (TARGET_32BIT
14501 ? gen_addsi3 (this, this, delta_rtx)
14502 : gen_adddi3 (this, this, delta_rtx));
17167fd8
MM		 14503 }
14504
5b71a4e7
DE		 14505 /* Apply the offset from the vtable, if required. */
14506 if (vcall_offset)
17167fd8 14507 {
5b71a4e7
DE		 14508 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14509 rtx tmp = gen_rtx_REG (Pmode, 12);
17167fd8 14510
5b71a4e7 14511 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
eeff9307
JJ		 14512 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14513 {
14514 emit_insn (TARGET_32BIT
14515 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14516 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14517 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14518 }
14519 else
14520 {
14521 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14522
14523 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14524 }
5b71a4e7
DE		 14525 emit_insn (TARGET_32BIT
14526 ? gen_addsi3 (this, this, tmp)
14527 : gen_adddi3 (this, this, tmp));
17167fd8
MM		 14528 }
14529
5b71a4e7
DE		 14530 /* Generate a tail call to the target function. */
14531 if (!TREE_USED (function))
14532 {
14533 assemble_external (function);
14534 TREE_USED (function) = 1;
14535 }
14536 funexp = XEXP (DECL_RTL (function), 0);
5b71a4e7 14537 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
ee890fe2
SS		 14538
14539#if TARGET_MACHO
ab82a49f 14540 if (MACHOPIC_INDIRECT)
5b71a4e7 14541 funexp = machopic_indirect_call_target (funexp);
ee890fe2 14542#endif
5b71a4e7
DE		 14543
14544 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14545 generate sibcall RTL explicitly to avoid constraint abort. */
14546 insn = emit_call_insn (
14547 gen_rtx_PARALLEL (VOIDmode,
14548 gen_rtvec (4,
14549 gen_rtx_CALL (VOIDmode,
14550 funexp, const0_rtx),
14551 gen_rtx_USE (VOIDmode, const0_rtx),
14552 gen_rtx_USE (VOIDmode,
14553 gen_rtx_REG (SImode,
14554 LINK_REGISTER_REGNUM)),
14555 gen_rtx_RETURN (VOIDmode))));
14556 SIBLING_CALL_P (insn) = 1;
14557 emit_barrier ();
14558
14559 /* Run just enough of rest_of_compilation to get the insns emitted.
14560 There's not really enough bulk here to make other passes such as
14561 instruction scheduling worth while. Note that use_thunk calls
14562 assemble_start_function and assemble_end_function. */
14563 insn = get_insns ();
a2855205 14564 insn_locators_initialize ();
5b71a4e7
DE		 14565 shorten_branches (insn);
14566 final_start_function (insn, file, 1);
c9d691e9 14567 final (insn, file, 1);
5b71a4e7
DE		 14568 final_end_function ();
14569
14570 reload_completed = 0;
fe3ad572 14571 epilogue_completed = 0;
5b71a4e7 14572 no_new_pseudos = 0;
9ebbca7d 14573}
9ebbca7d
GK		 14574\f
14575/* A quick summary of the various types of 'constant-pool tables'
14576 under PowerPC:
14577
f676971a 14578 Target Flags Name One table per
9ebbca7d
GK		 14579 AIX (none) AIX TOC object file
14580 AIX -mfull-toc AIX TOC object file
14581 AIX -mminimal-toc AIX minimal TOC translation unit
14582 SVR4/EABI (none) SVR4 SDATA object file
14583 SVR4/EABI -fpic SVR4 pic object file
14584 SVR4/EABI -fPIC SVR4 PIC translation unit
14585 SVR4/EABI -mrelocatable EABI TOC function
14586 SVR4/EABI -maix AIX TOC object file
f676971a 14587 SVR4/EABI -maix -mminimal-toc
9ebbca7d
GK		 14588 AIX minimal TOC translation unit
14589
14590 Name Reg. Set by entries contains:
14591 made by addrs? fp? sum?
14592
14593 AIX TOC 2 crt0 as Y option option
14594 AIX minimal TOC 30 prolog gcc Y Y option
14595 SVR4 SDATA 13 crt0 gcc N Y N
14596 SVR4 pic 30 prolog ld Y not yet N
14597 SVR4 PIC 30 prolog gcc Y option option
14598 EABI TOC 30 prolog gcc Y option option
14599
14600*/
14601
9ebbca7d
GK		 14602/* Hash functions for the hash table. */
14603
14604static unsigned
a2369ed3 14605rs6000_hash_constant (rtx k)
9ebbca7d 14606{
46b33600
RH		 14607 enum rtx_code code = GET_CODE (k);
14608 enum machine_mode mode = GET_MODE (k);
14609 unsigned result = (code << 3) ^ mode;
14610 const char *format;
14611 int flen, fidx;
f676971a 14612
46b33600
RH		 14613 format = GET_RTX_FORMAT (code);
14614 flen = strlen (format);
14615 fidx = 0;
9ebbca7d 14616
46b33600
RH		 14617 switch (code)
14618 {
14619 case LABEL_REF:
14620 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14621
14622 case CONST_DOUBLE:
14623 if (mode != VOIDmode)
14624 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14625 flen = 2;
14626 break;
14627
14628 case CODE_LABEL:
14629 fidx = 3;
14630 break;
14631
14632 default:
14633 break;
14634 }
9ebbca7d
GK		 14635
14636 for (; fidx < flen; fidx++)
14637 switch (format[fidx])
14638 {
14639 case 's':
14640 {
14641 unsigned i, len;
14642 const char *str = XSTR (k, fidx);
14643 len = strlen (str);
14644 result = result * 613 + len;
14645 for (i = 0; i < len; i++)
14646 result = result * 613 + (unsigned) str[i];
17167fd8
MM		 14647 break;
14648 }
9ebbca7d
GK		 14649 case 'u':
14650 case 'e':
14651 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14652 break;
14653 case 'i':
14654 case 'n':
14655 result = result * 613 + (unsigned) XINT (k, fidx);
14656 break;
14657 case 'w':
14658 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14659 result = result * 613 + (unsigned) XWINT (k, fidx);
14660 else
14661 {
14662 size_t i;
9390387d 14663 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
9ebbca7d
GK		 14664 result = result * 613 + (unsigned) (XWINT (k, fidx)
14665 >> CHAR_BIT * i);
14666 }
14667 break;
09501938
DE		 14668 case '0':
14669 break;
9ebbca7d 14670 default:
37409796 14671 gcc_unreachable ();
9ebbca7d 14672 }
46b33600 14673
9ebbca7d
GK		 14674 return result;
14675}
14676
14677static unsigned
a2369ed3 14678toc_hash_function (const void *hash_entry)
9ebbca7d 14679{
f676971a 14680 const struct toc_hash_struct *thc =
a9098fd0
GK		 14681 (const struct toc_hash_struct *) hash_entry;
14682 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
9ebbca7d
GK		 14683}
14684
14685/* Compare H1 and H2 for equivalence. */
14686
14687static int
a2369ed3 14688toc_hash_eq (const void *h1, const void *h2)
9ebbca7d
GK		 14689{
14690 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14691 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14692
a9098fd0
GK		 14693 if (((const struct toc_hash_struct *) h1)->key_mode
14694 != ((const struct toc_hash_struct *) h2)->key_mode)
14695 return 0;
14696
5692c7bc 14697 return rtx_equal_p (r1, r2);
9ebbca7d
GK		 14698}
14699
28e510bd
MM		 14700/* These are the names given by the C++ front-end to vtables, and
14701 vtable-like objects. Ideally, this logic should not be here;
14702 instead, there should be some programmatic way of inquiring as
14703 to whether or not an object is a vtable. */
14704
14705#define VTABLE_NAME_P(NAME) \
9390387d 14706 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
28e510bd
MM		 14707 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14708 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
26be75db 14709 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
f676971a 14710 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
28e510bd
MM		 14711
14712void
a2369ed3 14713rs6000_output_symbol_ref (FILE *file, rtx x)
28e510bd
MM		 14714{
14715 /* Currently C++ toc references to vtables can be emitted before it
14716 is decided whether the vtable is public or private. If this is
14717 the case, then the linker will eventually complain that there is
f676971a 14718 a reference to an unknown section. Thus, for vtables only,
28e510bd
MM		 14719 we emit the TOC reference to reference the symbol and not the
14720 section. */
14721 const char *name = XSTR (x, 0);
54ee9799 14722
f676971a 14723 if (VTABLE_NAME_P (name))
54ee9799
DE		 14724 {
14725 RS6000_OUTPUT_BASENAME (file, name);
14726 }
14727 else
14728 assemble_name (file, name);
28e510bd
MM		 14729}
14730
a4f6c312
SS		 14731/* Output a TOC entry. We derive the entry name from what is being
14732 written. */
9878760c
RK		 14733
14734void
a2369ed3 14735output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
9878760c
RK		 14736{
14737 char buf[256];
3cce094d 14738 const char *name = buf;
ec940faa 14739 const char *real_name;
9878760c
RK		 14740 rtx base = x;
14741 int offset = 0;
14742
37409796 14743 gcc_assert (!TARGET_NO_TOC);
4697a36c 14744
9ebbca7d
GK		 14745 /* When the linker won't eliminate them, don't output duplicate
14746 TOC entries (this happens on AIX if there is any kind of TOC,
17211ab5
GK		 14747 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14748 CODE_LABELs. */
14749 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
9ebbca7d
GK		 14750 {
14751 struct toc_hash_struct *h;
14752 void * * found;
f676971a 14753
17211ab5 14754 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
c4ad648e 14755 time because GGC is not initialized at that point. */
17211ab5 14756 if (toc_hash_table == NULL)
f676971a 14757 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
17211ab5
GK		 14758 toc_hash_eq, NULL);
14759
9ebbca7d
GK		 14760 h = ggc_alloc (sizeof (*h));
14761 h->key = x;
a9098fd0 14762 h->key_mode = mode;
9ebbca7d 14763 h->labelno = labelno;
f676971a 14764
9ebbca7d
GK		 14765 found = htab_find_slot (toc_hash_table, h, 1);
14766 if (*found == NULL)
14767 *found = h;
f676971a 14768 else /* This is indeed a duplicate.
9ebbca7d
GK		 14769 Set this label equal to that label. */
14770 {
14771 fputs ("\t.set ", file);
14772 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14773 fprintf (file, "%d,", labelno);
14774 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
f676971a 14775 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
9ebbca7d
GK		 14776 found)->labelno));
14777 return;
14778 }
14779 }
14780
14781 /* If we're going to put a double constant in the TOC, make sure it's
14782 aligned properly when strict alignment is on. */
ff1720ed
RK		 14783 if (GET_CODE (x) == CONST_DOUBLE
14784 && STRICT_ALIGNMENT
a9098fd0 14785 && GET_MODE_BITSIZE (mode) >= 64
ff1720ed
RK		 14786 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
14787 ASM_OUTPUT_ALIGN (file, 3);
14788 }
14789
4977bab6 14790 (*targetm.asm_out.internal_label) (file, "LC", labelno);
9878760c 14791
37c37a57
RK		 14792 /* Handle FP constants specially. Note that if we have a minimal
14793 TOC, things we put here aren't actually in the TOC, so we can allow
14794 FP constants. */
fcce224d
DE		 14795 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
14796 {
14797 REAL_VALUE_TYPE rv;
14798 long k[4];
14799
14800 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14801 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
14802
14803 if (TARGET_64BIT)
14804 {
14805 if (TARGET_MINIMAL_TOC)
14806 fputs (DOUBLE_INT_ASM_OP, file);
14807 else
14808 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14809 k[0] & 0xffffffff, k[1] & 0xffffffff,
14810 k[2] & 0xffffffff, k[3] & 0xffffffff);
14811 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
14812 k[0] & 0xffffffff, k[1] & 0xffffffff,
14813 k[2] & 0xffffffff, k[3] & 0xffffffff);
14814 return;
14815 }
14816 else
14817 {
14818 if (TARGET_MINIMAL_TOC)
14819 fputs ("\t.long ", file);
14820 else
14821 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14822 k[0] & 0xffffffff, k[1] & 0xffffffff,
14823 k[2] & 0xffffffff, k[3] & 0xffffffff);
14824 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14825 k[0] & 0xffffffff, k[1] & 0xffffffff,
14826 k[2] & 0xffffffff, k[3] & 0xffffffff);
14827 return;
14828 }
14829 }
14830 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9878760c 14831 {
042259f2
DE		 14832 REAL_VALUE_TYPE rv;
14833 long k[2];
0adc764e 14834
042259f2
DE		 14835 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14836 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
31bfaa0b 14837
13ded975
DE		 14838 if (TARGET_64BIT)
14839 {
14840 if (TARGET_MINIMAL_TOC)
2bfcf297 14841 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 14842 else
2f0552b6
AM		 14843 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14844 k[0] & 0xffffffff, k[1] & 0xffffffff);
14845 fprintf (file, "0x%lx%08lx\n",
14846 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 14847 return;
14848 }
1875cc88 14849 else
13ded975
DE		 14850 {
14851 if (TARGET_MINIMAL_TOC)
2bfcf297 14852 fputs ("\t.long ", file);
13ded975 14853 else
2f0552b6
AM		 14854 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14855 k[0] & 0xffffffff, k[1] & 0xffffffff);
14856 fprintf (file, "0x%lx,0x%lx\n",
14857 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 14858 return;
14859 }
9878760c 14860 }
a9098fd0 14861 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9878760c 14862 {
042259f2
DE		 14863 REAL_VALUE_TYPE rv;
14864 long l;
9878760c 14865
042259f2
DE		 14866 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14867 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
14868
31bfaa0b
DE		 14869 if (TARGET_64BIT)
14870 {
14871 if (TARGET_MINIMAL_TOC)
2bfcf297 14872 fputs (DOUBLE_INT_ASM_OP, file);
31bfaa0b 14873 else
2f0552b6
AM		 14874 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14875 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
31bfaa0b
DE		 14876 return;
14877 }
042259f2 14878 else
31bfaa0b
DE		 14879 {
14880 if (TARGET_MINIMAL_TOC)
2bfcf297 14881 fputs ("\t.long ", file);
31bfaa0b 14882 else
2f0552b6
AM		 14883 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14884 fprintf (file, "0x%lx\n", l & 0xffffffff);
31bfaa0b
DE		 14885 return;
14886 }
042259f2 14887 }
f176e826 14888 else if (GET_MODE (x) == VOIDmode
a9098fd0 14889 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
042259f2 14890 {
e2c953b6 14891 unsigned HOST_WIDE_INT low;
042259f2
DE		 14892 HOST_WIDE_INT high;
14893
14894 if (GET_CODE (x) == CONST_DOUBLE)
14895 {
14896 low = CONST_DOUBLE_LOW (x);
14897 high = CONST_DOUBLE_HIGH (x);
14898 }
14899 else
14900#if HOST_BITS_PER_WIDE_INT == 32
14901 {
14902 low = INTVAL (x);
0858c623 14903 high = (low & 0x80000000) ? ~0 : 0;
042259f2
DE		 14904 }
14905#else
14906 {
c4ad648e
AM		 14907 low = INTVAL (x) & 0xffffffff;
14908 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
042259f2
DE		 14909 }
14910#endif
9878760c 14911
a9098fd0
GK		 14912 /* TOC entries are always Pmode-sized, but since this
14913 is a bigendian machine then if we're putting smaller
14914 integer constants in the TOC we have to pad them.
14915 (This is still a win over putting the constants in
14916 a separate constant pool, because then we'd have
02a4ec28
FS		 14917 to have both a TOC entry _and_ the actual constant.)
14918
14919 For a 32-bit target, CONST_INT values are loaded and shifted
14920 entirely within `low' and can be stored in one TOC entry. */
14921
37409796
NS		 14922 /* It would be easy to make this work, but it doesn't now. */
14923 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
02a4ec28
FS		 14924
14925 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
fb52d8de
AM		 14926 {
14927#if HOST_BITS_PER_WIDE_INT == 32
14928 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
14929 POINTER_SIZE, &low, &high, 0);
14930#else
14931 low |= high << 32;
14932 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
14933 high = (HOST_WIDE_INT) low >> 32;
14934 low &= 0xffffffff;
14935#endif
14936 }
a9098fd0 14937
13ded975
DE		 14938 if (TARGET_64BIT)
14939 {
14940 if (TARGET_MINIMAL_TOC)
2bfcf297 14941 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 14942 else
2f0552b6
AM		 14943 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14944 (long) high & 0xffffffff, (long) low & 0xffffffff);
14945 fprintf (file, "0x%lx%08lx\n",
14946 (long) high & 0xffffffff, (long) low & 0xffffffff);
13ded975
DE		 14947 return;
14948 }
1875cc88 14949 else
13ded975 14950 {
02a4ec28
FS		 14951 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
14952 {
14953 if (TARGET_MINIMAL_TOC)
2bfcf297 14954 fputs ("\t.long ", file);
02a4ec28 14955 else
2bfcf297 14956 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
2f0552b6
AM		 14957 (long) high & 0xffffffff, (long) low & 0xffffffff);
14958 fprintf (file, "0x%lx,0x%lx\n",
14959 (long) high & 0xffffffff, (long) low & 0xffffffff);
02a4ec28 14960 }
13ded975 14961 else
02a4ec28
FS		 14962 {
14963 if (TARGET_MINIMAL_TOC)
2bfcf297 14964 fputs ("\t.long ", file);
02a4ec28 14965 else
2f0552b6
AM		 14966 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
14967 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
02a4ec28 14968 }
13ded975
DE		 14969 return;
14970 }
9878760c
RK		 14971 }
14972
14973 if (GET_CODE (x) == CONST)
14974 {
37409796 14975 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
2bfcf297 14976
9878760c
RK		 14977 base = XEXP (XEXP (x, 0), 0);
14978 offset = INTVAL (XEXP (XEXP (x, 0), 1));
14979 }
f676971a 14980
37409796
NS		 14981 switch (GET_CODE (base))
14982 {
14983 case SYMBOL_REF:
14984 name = XSTR (base, 0);
14985 break;
14986
14987 case LABEL_REF:
14988 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
14989 CODE_LABEL_NUMBER (XEXP (base, 0)));
14990 break;
14991
14992 case CODE_LABEL:
14993 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
14994 break;
14995
14996 default:
14997 gcc_unreachable ();
14998 }
9878760c 14999
772c5265 15000 real_name = (*targetm.strip_name_encoding) (name);
1875cc88 15001 if (TARGET_MINIMAL_TOC)
2bfcf297 15002 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
1875cc88
JW		 15003 else
15004 {
b6c9286a 15005 fprintf (file, "\t.tc %s", real_name);
9878760c 15006
1875cc88
JW		 15007 if (offset < 0)
15008 fprintf (file, ".N%d", - offset);
15009 else if (offset)
15010 fprintf (file, ".P%d", offset);
9878760c 15011
19d2d16f 15012 fputs ("[TC],", file);
1875cc88 15013 }
581bc4de
MM		 15014
15015 /* Currently C++ toc references to vtables can be emitted before it
15016 is decided whether the vtable is public or private. If this is
15017 the case, then the linker will eventually complain that there is
15018 a TOC reference to an unknown section. Thus, for vtables only,
15019 we emit the TOC reference to reference the symbol and not the
15020 section. */
28e510bd 15021 if (VTABLE_NAME_P (name))
581bc4de 15022 {
54ee9799 15023 RS6000_OUTPUT_BASENAME (file, name);
581bc4de
MM		 15024 if (offset < 0)
15025 fprintf (file, "%d", offset);
15026 else if (offset > 0)
15027 fprintf (file, "+%d", offset);
15028 }
15029 else
15030 output_addr_const (file, x);
19d2d16f 15031 putc ('\n', file);
9878760c
RK		 15032}
15033\f
15034/* Output an assembler pseudo-op to write an ASCII string of N characters
15035 starting at P to FILE.
15036
15037 On the RS/6000, we have to do this using the .byte operation and
15038 write out special characters outside the quoted string.
15039 Also, the assembler is broken; very long strings are truncated,
a4f6c312 15040 so we must artificially break them up early. */
9878760c
RK		 15041
15042void
a2369ed3 15043output_ascii (FILE *file, const char *p, int n)
9878760c
RK		 15044{
15045 char c;
15046 int i, count_string;
d330fd93
KG		 15047 const char *for_string = "\t.byte \"";
15048 const char *for_decimal = "\t.byte ";
15049 const char *to_close = NULL;
9878760c
RK		 15050
15051 count_string = 0;
15052 for (i = 0; i < n; i++)
15053 {
15054 c = *p++;
15055 if (c >= ' ' && c < 0177)
15056 {
15057 if (for_string)
15058 fputs (for_string, file);
15059 putc (c, file);
15060
15061 /* Write two quotes to get one. */
15062 if (c == '"')
15063 {
15064 putc (c, file);
15065 ++count_string;
15066 }
15067
15068 for_string = NULL;
15069 for_decimal = "\"\n\t.byte ";
15070 to_close = "\"\n";
15071 ++count_string;
15072
15073 if (count_string >= 512)
15074 {
15075 fputs (to_close, file);
15076
15077 for_string = "\t.byte \"";
15078 for_decimal = "\t.byte ";
15079 to_close = NULL;
15080 count_string = 0;
15081 }
15082 }
15083 else
15084 {
15085 if (for_decimal)
15086 fputs (for_decimal, file);
15087 fprintf (file, "%d", c);
15088
15089 for_string = "\n\t.byte \"";
15090 for_decimal = ", ";
15091 to_close = "\n";
15092 count_string = 0;
15093 }
15094 }
15095
15096 /* Now close the string if we have written one. Then end the line. */
15097 if (to_close)
9ebbca7d 15098 fputs (to_close, file);
9878760c
RK		 15099}
15100\f
15101/* Generate a unique section name for FILENAME for a section type
15102 represented by SECTION_DESC. Output goes into BUF.
15103
15104 SECTION_DESC can be any string, as long as it is different for each
15105 possible section type.
15106
15107 We name the section in the same manner as xlc. The name begins with an
15108 underscore followed by the filename (after stripping any leading directory
11e5fe42
RK		 15109 names) with the last period replaced by the string SECTION_DESC. If
15110 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15111 the name. */
9878760c
RK		 15112
15113void
f676971a 15114rs6000_gen_section_name (char **buf, const char *filename,
c4ad648e 15115 const char *section_desc)
9878760c 15116{
9ebbca7d 15117 const char *q, *after_last_slash, *last_period = 0;
9878760c
RK		 15118 char *p;
15119 int len;
9878760c
RK		 15120
15121 after_last_slash = filename;
15122 for (q = filename; *q; q++)
11e5fe42
RK		 15123 {
15124 if (*q == '/')
15125 after_last_slash = q + 1;
15126 else if (*q == '.')
15127 last_period = q;
15128 }
9878760c 15129
11e5fe42 15130 len = strlen (after_last_slash) + strlen (section_desc) + 2;
6d9f628e 15131 *buf = (char *) xmalloc (len);
9878760c
RK		 15132
15133 p = *buf;
15134 *p++ = '_';
15135
15136 for (q = after_last_slash; *q; q++)
15137 {
11e5fe42 15138 if (q == last_period)
c4ad648e 15139 {
9878760c
RK		 15140 strcpy (p, section_desc);
15141 p += strlen (section_desc);
e3981aab 15142 break;
c4ad648e 15143 }
9878760c 15144
e9a780ec 15145 else if (ISALNUM (*q))
c4ad648e 15146 *p++ = *q;
9878760c
RK		 15147 }
15148
11e5fe42 15149 if (last_period == 0)
9878760c
RK		 15150 strcpy (p, section_desc);
15151 else
15152 *p = '\0';
15153}
e165f3f0 15154\f
a4f6c312 15155/* Emit profile function. */
411707f4 15156
411707f4 15157void
a2369ed3 15158output_profile_hook (int labelno ATTRIBUTE_UNUSED)
411707f4 15159{
ffcfcb5f
AM		 15160 if (TARGET_PROFILE_KERNEL)
15161 return;
15162
8480e480
CC		 15163 if (DEFAULT_ABI == ABI_AIX)
15164 {
9739c90c
JJ		 15165#ifndef NO_PROFILE_COUNTERS
15166# define NO_PROFILE_COUNTERS 0
15167#endif
f676971a 15168 if (NO_PROFILE_COUNTERS)
9739c90c
JJ		 15169 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15170 else
15171 {
15172 char buf[30];
15173 const char *label_name;
15174 rtx fun;
411707f4 15175
9739c90c
JJ		 15176 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15177 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15178 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
411707f4 15179
9739c90c
JJ		 15180 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15181 fun, Pmode);
15182 }
8480e480 15183 }
ee890fe2
SS		 15184 else if (DEFAULT_ABI == ABI_DARWIN)
15185 {
d5fa86ba 15186 const char *mcount_name = RS6000_MCOUNT;
ee890fe2
SS		 15187 int caller_addr_regno = LINK_REGISTER_REGNUM;
15188
15189 /* Be conservative and always set this, at least for now. */
15190 current_function_uses_pic_offset_table = 1;
15191
15192#if TARGET_MACHO
15193 /* For PIC code, set up a stub and collect the caller's address
15194 from r0, which is where the prologue puts it. */
11abc112
MM		 15195 if (MACHOPIC_INDIRECT
15196 && current_function_uses_pic_offset_table)
15197 caller_addr_regno = 0;
ee890fe2
SS		 15198#endif
15199 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15200 0, VOIDmode, 1,
15201 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15202 }
411707f4
CC		 15203}
15204
a4f6c312 15205/* Write function profiler code. */
e165f3f0
RK		 15206
15207void
a2369ed3 15208output_function_profiler (FILE *file, int labelno)
e165f3f0 15209{
3daf36a4 15210 char buf[100];
09eeeacb 15211 int save_lr = 8;
e165f3f0 15212
38c1f2d7 15213 switch (DEFAULT_ABI)
3daf36a4 15214 {
38c1f2d7 15215 default:
37409796 15216 gcc_unreachable ();
38c1f2d7
MM		 15217
15218 case ABI_V4:
09eeeacb 15219 save_lr = 4;
09eeeacb
AM		 15220 if (!TARGET_32BIT)
15221 {
d4ee4d25 15222 warning (0, "no profiling of 64-bit code for this ABI");
09eeeacb
AM		 15223 return;
15224 }
ffcfcb5f 15225 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
38c1f2d7
MM		 15226 fprintf (file, "\tmflr %s\n", reg_names[0]);
15227 if (flag_pic == 1)
15228 {
dfdfa60f 15229 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
09eeeacb
AM		 15230 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15231 reg_names[0], save_lr, reg_names[1]);
17167fd8 15232 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
dfdfa60f 15233 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
38c1f2d7 15234 assemble_name (file, buf);
17167fd8 15235 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
38c1f2d7 15236 }
9ebbca7d 15237 else if (flag_pic > 1)
38c1f2d7 15238 {
09eeeacb
AM		 15239 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15240 reg_names[0], save_lr, reg_names[1]);
9ebbca7d
GK		 15241 /* Now, we need to get the address of the label. */
15242 fputs ("\tbl 1f\n\t.long ", file);
034e84c4 15243 assemble_name (file, buf);
9ebbca7d
GK		 15244 fputs ("-.\n1:", file);
15245 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
f676971a 15246 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
9ebbca7d
GK		 15247 reg_names[0], reg_names[11]);
15248 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
15249 reg_names[0], reg_names[0], reg_names[11]);
38c1f2d7 15250 }
38c1f2d7
MM		 15251 else
15252 {
17167fd8 15253 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
38c1f2d7 15254 assemble_name (file, buf);
dfdfa60f 15255 fputs ("@ha\n", file);
09eeeacb
AM		 15256 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15257 reg_names[0], save_lr, reg_names[1]);
a260abc9 15258 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
38c1f2d7 15259 assemble_name (file, buf);
17167fd8 15260 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
38c1f2d7
MM		 15261 }
15262
50d440bc 15263 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
3b6ce0af
DE		 15264 fprintf (file, "\tbl %s%s\n",
15265 RS6000_MCOUNT, flag_pic ? "@plt" : "");
38c1f2d7
MM		 15266 break;
15267
15268 case ABI_AIX:
ee890fe2 15269 case ABI_DARWIN:
ffcfcb5f
AM		 15270 if (!TARGET_PROFILE_KERNEL)
15271 {
a3c9585f 15272 /* Don't do anything, done in output_profile_hook (). */
ffcfcb5f
AM		 15273 }
15274 else
15275 {
37409796 15276 gcc_assert (!TARGET_32BIT);
ffcfcb5f
AM		 15277
15278 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
15279 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
15280
6de9cd9a 15281 if (cfun->static_chain_decl != NULL)
ffcfcb5f
AM		 15282 {
15283 asm_fprintf (file, "\tstd %s,24(%s)\n",
15284 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15285 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15286 asm_fprintf (file, "\tld %s,24(%s)\n",
15287 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15288 }
15289 else
15290 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15291 }
38c1f2d7
MM		 15292 break;
15293 }
e165f3f0 15294}
a251ffd0 15295
b54cf83a 15296\f
b54cf83a
DE		 15297/* Power4 load update and store update instructions are cracked into a
15298 load or store and an integer insn which are executed in the same cycle.
15299 Branches have their own dispatch slot which does not count against the
15300 GCC issue rate, but it changes the program flow so there are no other
15301 instructions to issue in this cycle. */
15302
15303static int
f676971a
EC		 15304rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
15305 int verbose ATTRIBUTE_UNUSED,
a2369ed3 15306 rtx insn, int more)
b54cf83a
DE		 15307{
15308 if (GET_CODE (PATTERN (insn)) == USE
15309 || GET_CODE (PATTERN (insn)) == CLOBBER)
15310 return more;
15311
ec507f2d 15312 if (rs6000_sched_groups)
b54cf83a 15313 {
cbe26ab8 15314 if (is_microcoded_insn (insn))
c4ad648e 15315 return 0;
cbe26ab8 15316 else if (is_cracked_insn (insn))
c4ad648e 15317 return more > 2 ? more - 2 : 0;
b54cf83a 15318 }
165b263e
DE		 15319
15320 return more - 1;
b54cf83a
DE		 15321}
15322
a251ffd0
TG		 15323/* Adjust the cost of a scheduling dependency. Return the new cost of
15324 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
15325
c237e94a 15326static int
0a4f0294 15327rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
a251ffd0
TG		 15328{
15329 if (! recog_memoized (insn))
15330 return 0;
15331
15332 if (REG_NOTE_KIND (link) != 0)
15333 return 0;
15334
15335 if (REG_NOTE_KIND (link) == 0)
15336 {
ed947a96
DJ		 15337 /* Data dependency; DEP_INSN writes a register that INSN reads
15338 some cycles later. */
c9dbf840
DE		 15339
15340 /* Separate a load from a narrower, dependent store. */
15341 if (rs6000_sched_groups
15342 && GET_CODE (PATTERN (insn)) == SET
15343 && GET_CODE (PATTERN (dep_insn)) == SET
15344 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
15345 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
15346 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
15347 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
15348 return cost + 14;
15349
ed947a96
DJ		 15350 switch (get_attr_type (insn))
15351 {
15352 case TYPE_JMPREG:
309323c2 15353 /* Tell the first scheduling pass about the latency between
ed947a96
DJ		 15354 a mtctr and bctr (and mtlr and br/blr). The first
15355 scheduling pass will not know about this latency since
15356 the mtctr instruction, which has the latency associated
15357 to it, will be generated by reload. */
309323c2 15358 return TARGET_POWER ? 5 : 4;
ed947a96
DJ		 15359 case TYPE_BRANCH:
15360 /* Leave some extra cycles between a compare and its
15361 dependent branch, to inhibit expensive mispredicts. */
309323c2
DE		 15362 if ((rs6000_cpu_attr == CPU_PPC603
15363 || rs6000_cpu_attr == CPU_PPC604
15364 || rs6000_cpu_attr == CPU_PPC604E
15365 || rs6000_cpu_attr == CPU_PPC620
15366 || rs6000_cpu_attr == CPU_PPC630
15367 || rs6000_cpu_attr == CPU_PPC750
15368 || rs6000_cpu_attr == CPU_PPC7400
15369 || rs6000_cpu_attr == CPU_PPC7450
ec507f2d
DE		 15370 || rs6000_cpu_attr == CPU_POWER4
15371 || rs6000_cpu_attr == CPU_POWER5)
ed947a96
DJ		 15372 && recog_memoized (dep_insn)
15373 && (INSN_CODE (dep_insn) >= 0)
b54cf83a
DE		 15374 && (get_attr_type (dep_insn) == TYPE_CMP
15375 || get_attr_type (dep_insn) == TYPE_COMPARE
ed947a96 15376 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
9259f3b0
DE		 15377 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
15378 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
ed947a96 15379 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
b54cf83a
DE		 15380 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
15381 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
ed947a96
DJ		 15382 return cost + 2;
15383 default:
15384 break;
15385 }
a251ffd0
TG		 15386 /* Fall out to return default cost. */
15387 }
15388
15389 return cost;
15390}
b6c9286a 15391
cbe26ab8 15392/* The function returns a true if INSN is microcoded.
839a4992 15393 Return false otherwise. */
cbe26ab8
DN		 15394
15395static bool
15396is_microcoded_insn (rtx insn)
15397{
15398 if (!insn || !INSN_P (insn)
15399 || GET_CODE (PATTERN (insn)) == USE
15400 || GET_CODE (PATTERN (insn)) == CLOBBER)
15401 return false;
15402
ec507f2d 15403 if (rs6000_sched_groups)
cbe26ab8
DN		 15404 {
15405 enum attr_type type = get_attr_type (insn);
15406 if (type == TYPE_LOAD_EXT_U
15407 || type == TYPE_LOAD_EXT_UX
15408 || type == TYPE_LOAD_UX
15409 || type == TYPE_STORE_UX
15410 || type == TYPE_MFCR)
c4ad648e 15411 return true;
cbe26ab8
DN		 15412 }
15413
15414 return false;
15415}
15416
5c425df5 15417/* The function returns a nonzero value if INSN can be scheduled only
cbe26ab8
DN		 15418 as the first insn in a dispatch group ("dispatch-slot restricted").
15419 In this case, the returned value indicates how many dispatch slots
15420 the insn occupies (at the beginning of the group).
79ae11c4
DN		 15421 Return 0 otherwise. */
15422
cbe26ab8 15423static int
79ae11c4
DN		 15424is_dispatch_slot_restricted (rtx insn)
15425{
15426 enum attr_type type;
15427
ec507f2d 15428 if (!rs6000_sched_groups)
79ae11c4
DN		 15429 return 0;
15430
15431 if (!insn
15432 || insn == NULL_RTX
15433 || GET_CODE (insn) == NOTE
15434 || GET_CODE (PATTERN (insn)) == USE
15435 || GET_CODE (PATTERN (insn)) == CLOBBER)
15436 return 0;
15437
15438 type = get_attr_type (insn);
15439
ec507f2d
DE		 15440 switch (type)
15441 {
15442 case TYPE_MFCR:
15443 case TYPE_MFCRF:
15444 case TYPE_MTCR:
15445 case TYPE_DELAYED_CR:
15446 case TYPE_CR_LOGICAL:
15447 case TYPE_MTJMPR:
15448 case TYPE_MFJMPR:
15449 return 1;
15450 case TYPE_IDIV:
15451 case TYPE_LDIV:
15452 return 2;
15453 default:
15454 if (rs6000_cpu == PROCESSOR_POWER5
15455 && is_cracked_insn (insn))
15456 return 2;
15457 return 0;
15458 }
79ae11c4
DN		 15459}
15460
cbe26ab8
DN		 15461/* The function returns true if INSN is cracked into 2 instructions
15462 by the processor (and therefore occupies 2 issue slots). */
15463
15464static bool
15465is_cracked_insn (rtx insn)
15466{
15467 if (!insn || !INSN_P (insn)
15468 || GET_CODE (PATTERN (insn)) == USE
15469 || GET_CODE (PATTERN (insn)) == CLOBBER)
15470 return false;
15471
ec507f2d 15472 if (rs6000_sched_groups)
cbe26ab8
DN		 15473 {
15474 enum attr_type type = get_attr_type (insn);
15475 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
c4ad648e
AM		 15476 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15477 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15478 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15479 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15480 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15481 || type == TYPE_IDIV || type == TYPE_LDIV
15482 || type == TYPE_INSERT_WORD)
15483 return true;
cbe26ab8
DN		 15484 }
15485
15486 return false;
15487}
15488
15489/* The function returns true if INSN can be issued only from
a3c9585f 15490 the branch slot. */
cbe26ab8
DN		 15491
15492static bool
15493is_branch_slot_insn (rtx insn)
15494{
15495 if (!insn || !INSN_P (insn)
15496 || GET_CODE (PATTERN (insn)) == USE
15497 || GET_CODE (PATTERN (insn)) == CLOBBER)
15498 return false;
15499
ec507f2d 15500 if (rs6000_sched_groups)
cbe26ab8
DN		 15501 {
15502 enum attr_type type = get_attr_type (insn);
15503 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
f676971a 15504 return true;
cbe26ab8
DN		 15505 return false;
15506 }
15507
15508 return false;
15509}
79ae11c4 15510
a4f6c312 15511/* A C statement (sans semicolon) to update the integer scheduling
79ae11c4
DN		 15512 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15513 INSN earlier, reduce the priority to execute INSN later. Do not
a4f6c312
SS		 15514 define this macro if you do not need to adjust the scheduling
15515 priorities of insns. */
bef84347 15516
c237e94a 15517static int
a2369ed3 15518rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
bef84347 15519{
a4f6c312
SS		 15520 /* On machines (like the 750) which have asymmetric integer units,
15521 where one integer unit can do multiply and divides and the other
15522 can't, reduce the priority of multiply/divide so it is scheduled
15523 before other integer operations. */
bef84347
VM		 15524
15525#if 0
2c3c49de 15526 if (! INSN_P (insn))
bef84347
VM		 15527 return priority;
15528
15529 if (GET_CODE (PATTERN (insn)) == USE)
15530 return priority;
15531
15532 switch (rs6000_cpu_attr) {
15533 case CPU_PPC750:
15534 switch (get_attr_type (insn))
15535 {
15536 default:
15537 break;
15538
15539 case TYPE_IMUL:
15540 case TYPE_IDIV:
3cb999d8
DE		 15541 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15542 priority, priority);
bef84347
VM		 15543 if (priority >= 0 && priority < 0x01000000)
15544 priority >>= 3;
15545 break;
15546 }
15547 }
15548#endif
15549
79ae11c4
DN		 15550 if (is_dispatch_slot_restricted (insn)
15551 && reload_completed
f676971a 15552 && current_sched_info->sched_max_insns_priority
79ae11c4
DN		 15553 && rs6000_sched_restricted_insns_priority)
15554 {
15555
c4ad648e
AM		 15556 /* Prioritize insns that can be dispatched only in the first
15557 dispatch slot. */
79ae11c4 15558 if (rs6000_sched_restricted_insns_priority == 1)
f676971a
EC		 15559 /* Attach highest priority to insn. This means that in
15560 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
79ae11c4 15561 precede 'priority' (critical path) considerations. */
f676971a 15562 return current_sched_info->sched_max_insns_priority;
79ae11c4 15563 else if (rs6000_sched_restricted_insns_priority == 2)
f676971a 15564 /* Increase priority of insn by a minimal amount. This means that in
c4ad648e
AM		 15565 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15566 considerations precede dispatch-slot restriction considerations. */
f676971a
EC		 15567 return (priority + 1);
15568 }
79ae11c4 15569
bef84347
VM		 15570 return priority;
15571}
15572
a4f6c312
SS		 15573/* Return how many instructions the machine can issue per cycle. */
15574
c237e94a 15575static int
863d938c 15576rs6000_issue_rate (void)
b6c9286a 15577{
3317bab1
DE		 15578 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15579 if (!reload_completed)
15580 return 1;
15581
b6c9286a 15582 switch (rs6000_cpu_attr) {
3cb999d8
DE		 15583 case CPU_RIOS1: /* ? */
15584 case CPU_RS64A:
15585 case CPU_PPC601: /* ? */
ed947a96 15586 case CPU_PPC7450:
3cb999d8 15587 return 3;
b54cf83a 15588 case CPU_PPC440:
b6c9286a 15589 case CPU_PPC603:
bef84347 15590 case CPU_PPC750:
ed947a96 15591 case CPU_PPC7400:
be12c2b0 15592 case CPU_PPC8540:
f676971a 15593 return 2;
3cb999d8 15594 case CPU_RIOS2:
b6c9286a 15595 case CPU_PPC604:
19684119 15596 case CPU_PPC604E:
b6c9286a 15597 case CPU_PPC620:
3cb999d8 15598 case CPU_PPC630:
b6c9286a 15599 return 4;
cbe26ab8 15600 case CPU_POWER4:
ec507f2d 15601 case CPU_POWER5:
cbe26ab8 15602 return 5;
b6c9286a
MM		 15603 default:
15604 return 1;
15605 }
15606}
15607
be12c2b0
VM		 15608/* Return how many instructions to look ahead for better insn
15609 scheduling. */
15610
15611static int
863d938c 15612rs6000_use_sched_lookahead (void)
be12c2b0
VM		 15613{
15614 if (rs6000_cpu_attr == CPU_PPC8540)
15615 return 4;
15616 return 0;
15617}
15618
569fa502
DN		 15619/* Determine is PAT refers to memory. */
15620
15621static bool
15622is_mem_ref (rtx pat)
15623{
15624 const char * fmt;
15625 int i, j;
15626 bool ret = false;
15627
15628 if (GET_CODE (pat) == MEM)
15629 return true;
15630
15631 /* Recursively process the pattern. */
15632 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15633
15634 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15635 {
15636 if (fmt[i] == 'e')
15637 ret |= is_mem_ref (XEXP (pat, i));
15638 else if (fmt[i] == 'E')
15639 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15640 ret |= is_mem_ref (XVECEXP (pat, i, j));
15641 }
15642
15643 return ret;
15644}
15645
15646/* Determine if PAT is a PATTERN of a load insn. */
f676971a 15647
569fa502
DN		 15648static bool
15649is_load_insn1 (rtx pat)
15650{
15651 if (!pat || pat == NULL_RTX)
15652 return false;
15653
15654 if (GET_CODE (pat) == SET)
15655 return is_mem_ref (SET_SRC (pat));
15656
15657 if (GET_CODE (pat) == PARALLEL)
15658 {
15659 int i;
15660
15661 for (i = 0; i < XVECLEN (pat, 0); i++)
15662 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15663 return true;
15664 }
15665
15666 return false;
15667}
15668
15669/* Determine if INSN loads from memory. */
15670
15671static bool
15672is_load_insn (rtx insn)
15673{
15674 if (!insn || !INSN_P (insn))
15675 return false;
15676
15677 if (GET_CODE (insn) == CALL_INSN)
15678 return false;
15679
15680 return is_load_insn1 (PATTERN (insn));
15681}
15682
15683/* Determine if PAT is a PATTERN of a store insn. */
15684
15685static bool
15686is_store_insn1 (rtx pat)
15687{
15688 if (!pat || pat == NULL_RTX)
15689 return false;
15690
15691 if (GET_CODE (pat) == SET)
15692 return is_mem_ref (SET_DEST (pat));
15693
15694 if (GET_CODE (pat) == PARALLEL)
15695 {
15696 int i;
15697
15698 for (i = 0; i < XVECLEN (pat, 0); i++)
15699 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15700 return true;
15701 }
15702
15703 return false;
15704}
15705
15706/* Determine if INSN stores to memory. */
15707
15708static bool
15709is_store_insn (rtx insn)
15710{
15711 if (!insn || !INSN_P (insn))
15712 return false;
15713
15714 return is_store_insn1 (PATTERN (insn));
15715}
15716
15717/* Returns whether the dependence between INSN and NEXT is considered
15718 costly by the given target. */
15719
15720static bool
c4ad648e
AM		 15721rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15722 int distance)
f676971a 15723{
aabcd309 15724 /* If the flag is not enabled - no dependence is considered costly;
f676971a 15725 allow all dependent insns in the same group.
569fa502
DN		 15726 This is the most aggressive option. */
15727 if (rs6000_sched_costly_dep == no_dep_costly)
15728 return false;
15729
f676971a 15730 /* If the flag is set to 1 - a dependence is always considered costly;
569fa502
DN		 15731 do not allow dependent instructions in the same group.
15732 This is the most conservative option. */
15733 if (rs6000_sched_costly_dep == all_deps_costly)
f676971a 15734 return true;
569fa502 15735
f676971a
EC		 15736 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15737 && is_load_insn (next)
569fa502
DN		 15738 && is_store_insn (insn))
15739 /* Prevent load after store in the same group. */
15740 return true;
15741
15742 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
f676971a 15743 && is_load_insn (next)
569fa502
DN		 15744 && is_store_insn (insn)
15745 && (!link || (int) REG_NOTE_KIND (link) == 0))
c4ad648e
AM		 15746 /* Prevent load after store in the same group if it is a true
15747 dependence. */
569fa502 15748 return true;
f676971a
EC		 15749
15750 /* The flag is set to X; dependences with latency >= X are considered costly,
569fa502
DN		 15751 and will not be scheduled in the same group. */
15752 if (rs6000_sched_costly_dep <= max_dep_latency
15753 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
15754 return true;
15755
15756 return false;
15757}
15758
f676971a 15759/* Return the next insn after INSN that is found before TAIL is reached,
cbe26ab8
DN		 15760 skipping any "non-active" insns - insns that will not actually occupy
15761 an issue slot. Return NULL_RTX if such an insn is not found. */
15762
15763static rtx
15764get_next_active_insn (rtx insn, rtx tail)
15765{
15766 rtx next_insn;
15767
15768 if (!insn || insn == tail)
15769 return NULL_RTX;
15770
15771 next_insn = NEXT_INSN (insn);
15772
15773 while (next_insn
15774 && next_insn != tail
9390387d 15775 && (GET_CODE (next_insn) == NOTE
cbe26ab8
DN		 15776 || GET_CODE (PATTERN (next_insn)) == USE
15777 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
15778 {
15779 next_insn = NEXT_INSN (next_insn);
15780 }
15781
15782 if (!next_insn || next_insn == tail)
15783 return NULL_RTX;
15784
15785 return next_insn;
15786}
15787
839a4992 15788/* Return whether the presence of INSN causes a dispatch group termination
cbe26ab8
DN		 15789 of group WHICH_GROUP.
15790
15791 If WHICH_GROUP == current_group, this function will return true if INSN
15792 causes the termination of the current group (i.e, the dispatch group to
15793 which INSN belongs). This means that INSN will be the last insn in the
15794 group it belongs to.
15795
15796 If WHICH_GROUP == previous_group, this function will return true if INSN
15797 causes the termination of the previous group (i.e, the dispatch group that
15798 precedes the group to which INSN belongs). This means that INSN will be
15799 the first insn in the group it belongs to). */
15800
15801static bool
15802insn_terminates_group_p (rtx insn, enum group_termination which_group)
15803{
15804 enum attr_type type;
15805
15806 if (! insn)
15807 return false;
569fa502 15808
cbe26ab8
DN		 15809 type = get_attr_type (insn);
15810
15811 if (is_microcoded_insn (insn))
15812 return true;
15813
15814 if (which_group == current_group)
15815 {
15816 if (is_branch_slot_insn (insn))
c4ad648e 15817 return true;
cbe26ab8
DN		 15818 return false;
15819 }
15820 else if (which_group == previous_group)
15821 {
15822 if (is_dispatch_slot_restricted (insn))
c4ad648e 15823 return true;
cbe26ab8
DN		 15824 return false;
15825 }
15826
15827 return false;
15828}
15829
839a4992 15830/* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
cbe26ab8
DN		 15831 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15832
15833static bool
15834is_costly_group (rtx *group_insns, rtx next_insn)
15835{
15836 int i;
15837 rtx link;
15838 int cost;
15839 int issue_rate = rs6000_issue_rate ();
15840
15841 for (i = 0; i < issue_rate; i++)
15842 {
15843 rtx insn = group_insns[i];
15844 if (!insn)
c4ad648e 15845 continue;
cbe26ab8 15846 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
c4ad648e
AM		 15847 {
15848 rtx next = XEXP (link, 0);
15849 if (next == next_insn)
15850 {
15851 cost = insn_cost (insn, link, next_insn);
15852 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
15853 return true;
15854 }
15855 }
cbe26ab8
DN		 15856 }
15857
15858 return false;
15859}
15860
f676971a 15861/* Utility of the function redefine_groups.
cbe26ab8
DN		 15862 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15863 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15864 to keep it "far" (in a separate group) from GROUP_INSNS, following
15865 one of the following schemes, depending on the value of the flag
15866 -minsert_sched_nops = X:
15867 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
839a4992 15868 in order to force NEXT_INSN into a separate group.
f676971a
EC		 15869 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15870 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
cbe26ab8
DN		 15871 insertion (has a group just ended, how many vacant issue slots remain in the
15872 last group, and how many dispatch groups were encountered so far). */
15873
f676971a 15874static int
c4ad648e
AM		 15875force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
15876 rtx next_insn, bool *group_end, int can_issue_more,
15877 int *group_count)
cbe26ab8
DN		 15878{
15879 rtx nop;
15880 bool force;
15881 int issue_rate = rs6000_issue_rate ();
15882 bool end = *group_end;
15883 int i;
15884
15885 if (next_insn == NULL_RTX)
15886 return can_issue_more;
15887
15888 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
15889 return can_issue_more;
15890
15891 force = is_costly_group (group_insns, next_insn);
15892 if (!force)
15893 return can_issue_more;
15894
15895 if (sched_verbose > 6)
15896 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
c4ad648e 15897 *group_count ,can_issue_more);
cbe26ab8
DN		 15898
15899 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
15900 {
15901 if (*group_end)
c4ad648e 15902 can_issue_more = 0;
cbe26ab8
DN		 15903
15904 /* Since only a branch can be issued in the last issue_slot, it is
15905 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15906 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
c4ad648e
AM		 15907 in this case the last nop will start a new group and the branch
15908 will be forced to the new group. */
cbe26ab8 15909 if (can_issue_more && !is_branch_slot_insn (next_insn))
c4ad648e 15910 can_issue_more--;
cbe26ab8
DN		 15911
15912 while (can_issue_more > 0)
c4ad648e 15913 {
9390387d 15914 nop = gen_nop ();
c4ad648e
AM		 15915 emit_insn_before (nop, next_insn);
15916 can_issue_more--;
15917 }
cbe26ab8
DN		 15918
15919 *group_end = true;
15920 return 0;
f676971a 15921 }
cbe26ab8
DN		 15922
15923 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
15924 {
15925 int n_nops = rs6000_sched_insert_nops;
15926
f676971a 15927 /* Nops can't be issued from the branch slot, so the effective
c4ad648e 15928 issue_rate for nops is 'issue_rate - 1'. */
cbe26ab8 15929 if (can_issue_more == 0)
c4ad648e 15930 can_issue_more = issue_rate;
cbe26ab8
DN		 15931 can_issue_more--;
15932 if (can_issue_more == 0)
c4ad648e
AM		 15933 {
15934 can_issue_more = issue_rate - 1;
15935 (*group_count)++;
15936 end = true;
15937 for (i = 0; i < issue_rate; i++)
15938 {
15939 group_insns[i] = 0;
15940 }
15941 }
cbe26ab8
DN		 15942
15943 while (n_nops > 0)
c4ad648e
AM		 15944 {
15945 nop = gen_nop ();
15946 emit_insn_before (nop, next_insn);
15947 if (can_issue_more == issue_rate - 1) /* new group begins */
15948 end = false;
15949 can_issue_more--;
15950 if (can_issue_more == 0)
15951 {
15952 can_issue_more = issue_rate - 1;
15953 (*group_count)++;
15954 end = true;
15955 for (i = 0; i < issue_rate; i++)
15956 {
15957 group_insns[i] = 0;
15958 }
15959 }
15960 n_nops--;
15961 }
cbe26ab8
DN		 15962
15963 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
f676971a 15964 can_issue_more++;
cbe26ab8 15965
c4ad648e
AM		 15966 /* Is next_insn going to start a new group? */
15967 *group_end
15968 = (end
cbe26ab8
DN		 15969 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15970 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15971 || (can_issue_more < issue_rate &&
c4ad648e 15972 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 15973 if (*group_end && end)
c4ad648e 15974 (*group_count)--;
cbe26ab8
DN		 15975
15976 if (sched_verbose > 6)
c4ad648e
AM		 15977 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
15978 *group_count, can_issue_more);
f676971a
EC		 15979 return can_issue_more;
15980 }
cbe26ab8
DN		 15981
15982 return can_issue_more;
15983}
15984
15985/* This function tries to synch the dispatch groups that the compiler "sees"
f676971a 15986 with the dispatch groups that the processor dispatcher is expected to
cbe26ab8
DN		 15987 form in practice. It tries to achieve this synchronization by forcing the
15988 estimated processor grouping on the compiler (as opposed to the function
15989 'pad_goups' which tries to force the scheduler's grouping on the processor).
15990
15991 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15992 examines the (estimated) dispatch groups that will be formed by the processor
15993 dispatcher. It marks these group boundaries to reflect the estimated
15994 processor grouping, overriding the grouping that the scheduler had marked.
15995 Depending on the value of the flag '-minsert-sched-nops' this function can
15996 force certain insns into separate groups or force a certain distance between
15997 them by inserting nops, for example, if there exists a "costly dependence"
15998 between the insns.
15999
16000 The function estimates the group boundaries that the processor will form as
16001 folllows: It keeps track of how many vacant issue slots are available after
16002 each insn. A subsequent insn will start a new group if one of the following
16003 4 cases applies:
16004 - no more vacant issue slots remain in the current dispatch group.
16005 - only the last issue slot, which is the branch slot, is vacant, but the next
16006 insn is not a branch.
16007 - only the last 2 or less issue slots, including the branch slot, are vacant,
16008 which means that a cracked insn (which occupies two issue slots) can't be
16009 issued in this group.
f676971a 16010 - less than 'issue_rate' slots are vacant, and the next insn always needs to
cbe26ab8
DN		 16011 start a new group. */
16012
16013static int
16014redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16015{
16016 rtx insn, next_insn;
16017 int issue_rate;
16018 int can_issue_more;
16019 int slot, i;
16020 bool group_end;
16021 int group_count = 0;
16022 rtx *group_insns;
16023
16024 /* Initialize. */
16025 issue_rate = rs6000_issue_rate ();
16026 group_insns = alloca (issue_rate * sizeof (rtx));
f676971a 16027 for (i = 0; i < issue_rate; i++)
cbe26ab8
DN		 16028 {
16029 group_insns[i] = 0;
16030 }
16031 can_issue_more = issue_rate;
16032 slot = 0;
16033 insn = get_next_active_insn (prev_head_insn, tail);
16034 group_end = false;
16035
16036 while (insn != NULL_RTX)
16037 {
16038 slot = (issue_rate - can_issue_more);
16039 group_insns[slot] = insn;
16040 can_issue_more =
c4ad648e 16041 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
cbe26ab8 16042 if (insn_terminates_group_p (insn, current_group))
c4ad648e 16043 can_issue_more = 0;
cbe26ab8
DN		 16044
16045 next_insn = get_next_active_insn (insn, tail);
16046 if (next_insn == NULL_RTX)
c4ad648e 16047 return group_count + 1;
cbe26ab8 16048
c4ad648e
AM		 16049 /* Is next_insn going to start a new group? */
16050 group_end
16051 = (can_issue_more == 0
16052 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16053 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16054 || (can_issue_more < issue_rate &&
16055 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 16056
f676971a 16057 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
c4ad648e
AM		 16058 next_insn, &group_end, can_issue_more,
16059 &group_count);
cbe26ab8
DN		 16060
16061 if (group_end)
c4ad648e
AM		 16062 {
16063 group_count++;
16064 can_issue_more = 0;
16065 for (i = 0; i < issue_rate; i++)
16066 {
16067 group_insns[i] = 0;
16068 }
16069 }
cbe26ab8
DN		 16070
16071 if (GET_MODE (next_insn) == TImode && can_issue_more)
9390387d 16072 PUT_MODE (next_insn, VOIDmode);
cbe26ab8 16073 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
c4ad648e 16074 PUT_MODE (next_insn, TImode);
cbe26ab8
DN		 16075
16076 insn = next_insn;
16077 if (can_issue_more == 0)
c4ad648e
AM		 16078 can_issue_more = issue_rate;
16079 } /* while */
cbe26ab8
DN		 16080
16081 return group_count;
16082}
16083
16084/* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16085 dispatch group boundaries that the scheduler had marked. Pad with nops
16086 any dispatch groups which have vacant issue slots, in order to force the
16087 scheduler's grouping on the processor dispatcher. The function
16088 returns the number of dispatch groups found. */
16089
16090static int
16091pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16092{
16093 rtx insn, next_insn;
16094 rtx nop;
16095 int issue_rate;
16096 int can_issue_more;
16097 int group_end;
16098 int group_count = 0;
16099
16100 /* Initialize issue_rate. */
16101 issue_rate = rs6000_issue_rate ();
16102 can_issue_more = issue_rate;
16103
16104 insn = get_next_active_insn (prev_head_insn, tail);
16105 next_insn = get_next_active_insn (insn, tail);
16106
16107 while (insn != NULL_RTX)
16108 {
16109 can_issue_more =
16110 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16111
16112 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16113
16114 if (next_insn == NULL_RTX)
c4ad648e 16115 break;
cbe26ab8
DN		 16116
16117 if (group_end)
c4ad648e
AM		 16118 {
16119 /* If the scheduler had marked group termination at this location
16120 (between insn and next_indn), and neither insn nor next_insn will
16121 force group termination, pad the group with nops to force group
16122 termination. */
16123 if (can_issue_more
16124 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16125 && !insn_terminates_group_p (insn, current_group)
16126 && !insn_terminates_group_p (next_insn, previous_group))
16127 {
9390387d 16128 if (!is_branch_slot_insn (next_insn))
c4ad648e
AM		 16129 can_issue_more--;
16130
16131 while (can_issue_more)
16132 {
16133 nop = gen_nop ();
16134 emit_insn_before (nop, next_insn);
16135 can_issue_more--;
16136 }
16137 }
16138
16139 can_issue_more = issue_rate;
16140 group_count++;
16141 }
cbe26ab8
DN		 16142
16143 insn = next_insn;
16144 next_insn = get_next_active_insn (insn, tail);
16145 }
16146
16147 return group_count;
16148}
16149
16150/* The following function is called at the end of scheduling BB.
16151 After reload, it inserts nops at insn group bundling. */
16152
16153static void
38f391a5 16154rs6000_sched_finish (FILE *dump, int sched_verbose)
cbe26ab8
DN		 16155{
16156 int n_groups;
16157
16158 if (sched_verbose)
16159 fprintf (dump, "=== Finishing schedule.\n");
16160
ec507f2d 16161 if (reload_completed && rs6000_sched_groups)
cbe26ab8
DN		 16162 {
16163 if (rs6000_sched_insert_nops == sched_finish_none)
c4ad648e 16164 return;
cbe26ab8
DN		 16165
16166 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
c4ad648e
AM		 16167 n_groups = pad_groups (dump, sched_verbose,
16168 current_sched_info->prev_head,
16169 current_sched_info->next_tail);
cbe26ab8 16170 else
c4ad648e
AM		 16171 n_groups = redefine_groups (dump, sched_verbose,
16172 current_sched_info->prev_head,
16173 current_sched_info->next_tail);
cbe26ab8
DN		 16174
16175 if (sched_verbose >= 6)
16176 {
16177 fprintf (dump, "ngroups = %d\n", n_groups);
16178 print_rtl (dump, current_sched_info->prev_head);
16179 fprintf (dump, "Done finish_sched\n");
16180 }
16181 }
16182}
b6c9286a 16183\f
b6c9286a
MM		 16184/* Length in units of the trampoline for entering a nested function. */
16185
16186int
863d938c 16187rs6000_trampoline_size (void)
b6c9286a
MM		 16188{
16189 int ret = 0;
16190
16191 switch (DEFAULT_ABI)
16192 {
16193 default:
37409796 16194 gcc_unreachable ();
b6c9286a
MM		 16195
16196 case ABI_AIX:
8f802bfb 16197 ret = (TARGET_32BIT) ? 12 : 24;
b6c9286a
MM		 16198 break;
16199
4dabc42d 16200 case ABI_DARWIN:
b6c9286a 16201 case ABI_V4:
03a7e1a5 16202 ret = (TARGET_32BIT) ? 40 : 48;
b6c9286a 16203 break;
b6c9286a
MM		 16204 }
16205
16206 return ret;
16207}
16208
16209/* Emit RTL insns to initialize the variable parts of a trampoline.
16210 FNADDR is an RTX for the address of the function's pure code.
16211 CXT is an RTX for the static chain value for the function. */
16212
16213void
a2369ed3 16214rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
b6c9286a 16215{
ac2a93a1 16216 enum machine_mode pmode = Pmode;
8bd04c56
MM		 16217 int regsize = (TARGET_32BIT) ? 4 : 8;
16218 rtx ctx_reg = force_reg (pmode, cxt);
b6c9286a
MM		 16219
16220 switch (DEFAULT_ABI)
16221 {
16222 default:
37409796 16223 gcc_unreachable ();
b6c9286a 16224
8bd04c56 16225/* Macros to shorten the code expansions below. */
39403d82 16226#define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
c5c76735
JL		 16227#define MEM_PLUS(addr,offset) \
16228 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
7c59dc5d 16229
b6c9286a
MM		 16230 /* Under AIX, just build the 3 word function descriptor */
16231 case ABI_AIX:
8bd04c56
MM		 16232 {
16233 rtx fn_reg = gen_reg_rtx (pmode);
16234 rtx toc_reg = gen_reg_rtx (pmode);
16235 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
1cb18e3c 16236 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
8bd04c56
MM		 16237 emit_move_insn (MEM_DEREF (addr), fn_reg);
16238 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
16239 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
16240 }
b6c9286a
MM		 16241 break;
16242
4dabc42d
TC		 16243 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16244 case ABI_DARWIN:
b6c9286a 16245 case ABI_V4:
39403d82 16246 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
eaf1bcf1
MM		 16247 FALSE, VOIDmode, 4,
16248 addr, pmode,
16249 GEN_INT (rs6000_trampoline_size ()), SImode,
16250 fnaddr, pmode,
16251 ctx_reg, pmode);
b6c9286a 16252 break;
b6c9286a
MM		 16253 }
16254
16255 return;
16256}
7509c759
MM		 16257
16258\f
91d231cb 16259/* Table of valid machine attributes. */
a4f6c312 16260
91d231cb 16261const struct attribute_spec rs6000_attribute_table[] =
7509c759 16262{
91d231cb 16263 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8bb418a3 16264 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
a5c76ee6
ZW		 16265 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16266 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
005c1a13
GK		 16267#ifdef SUBTARGET_ATTRIBUTE_TABLE
16268 SUBTARGET_ATTRIBUTE_TABLE,
16269#endif
a5c76ee6 16270 { NULL, 0, 0, false, false, false, NULL }
91d231cb 16271};
7509c759 16272
8bb418a3
ZL		 16273/* Handle the "altivec" attribute. The attribute may have
16274 arguments as follows:
f676971a 16275
8bb418a3
ZL		 16276 __attribute__((altivec(vector__)))
16277 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
16278 __attribute__((altivec(bool__))) (always followed by 'unsigned')
16279
16280 and may appear more than once (e.g., 'vector bool char') in a
16281 given declaration. */
16282
16283static tree
f90ac3f0
UP		 16284rs6000_handle_altivec_attribute (tree *node,
16285 tree name ATTRIBUTE_UNUSED,
16286 tree args,
8bb418a3
ZL		 16287 int flags ATTRIBUTE_UNUSED,
16288 bool *no_add_attrs)
16289{
16290 tree type = *node, result = NULL_TREE;
16291 enum machine_mode mode;
16292 int unsigned_p;
16293 char altivec_type
16294 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
16295 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
16296 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
f676971a 16297 : '?');
8bb418a3
ZL		 16298
16299 while (POINTER_TYPE_P (type)
16300 || TREE_CODE (type) == FUNCTION_TYPE
16301 || TREE_CODE (type) == METHOD_TYPE
16302 || TREE_CODE (type) == ARRAY_TYPE)
16303 type = TREE_TYPE (type);
16304
16305 mode = TYPE_MODE (type);
16306
f90ac3f0
UP		 16307 /* Check for invalid AltiVec type qualifiers. */
16308 if (type == long_unsigned_type_node || type == long_integer_type_node)
16309 {
16310 if (TARGET_64BIT)
16311 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
16312 else if (rs6000_warn_altivec_long)
d4ee4d25 16313 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
f90ac3f0
UP		 16314 }
16315 else if (type == long_long_unsigned_type_node
16316 || type == long_long_integer_type_node)
16317 error ("use of %<long long%> in AltiVec types is invalid");
16318 else if (type == double_type_node)
16319 error ("use of %<double%> in AltiVec types is invalid");
16320 else if (type == long_double_type_node)
16321 error ("use of %<long double%> in AltiVec types is invalid");
16322 else if (type == boolean_type_node)
16323 error ("use of boolean types in AltiVec types is invalid");
16324 else if (TREE_CODE (type) == COMPLEX_TYPE)
16325 error ("use of %<complex%> in AltiVec types is invalid");
8bb418a3
ZL		 16326
16327 switch (altivec_type)
16328 {
16329 case 'v':
8df83eae 16330 unsigned_p = TYPE_UNSIGNED (type);
8bb418a3
ZL		 16331 switch (mode)
16332 {
c4ad648e
AM		 16333 case SImode:
16334 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
16335 break;
16336 case HImode:
16337 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
16338 break;
16339 case QImode:
16340 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
16341 break;
16342 case SFmode: result = V4SF_type_node; break;
16343 /* If the user says 'vector int bool', we may be handed the 'bool'
16344 attribute _before_ the 'vector' attribute, and so select the
16345 proper type in the 'b' case below. */
16346 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
16347 result = type;
16348 default: break;
8bb418a3
ZL		 16349 }
16350 break;
16351 case 'b':
16352 switch (mode)
16353 {
c4ad648e
AM		 16354 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
16355 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
16356 case QImode: case V16QImode: result = bool_V16QI_type_node;
16357 default: break;
8bb418a3
ZL		 16358 }
16359 break;
16360 case 'p':
16361 switch (mode)
16362 {
c4ad648e
AM		 16363 case V8HImode: result = pixel_V8HI_type_node;
16364 default: break;
8bb418a3
ZL		 16365 }
16366 default: break;
16367 }
16368
7958a2a6
FJ		 16369 if (result && result != type && TYPE_READONLY (type))
16370 result = build_qualified_type (result, TYPE_QUAL_CONST);
16371
8bb418a3
ZL		 16372 *no_add_attrs = true; /* No need to hang on to the attribute. */
16373
f90ac3f0 16374 if (result)
8bb418a3
ZL		 16375 *node = reconstruct_complex_type (*node, result);
16376
16377 return NULL_TREE;
16378}
16379
f18eca82
ZL		 16380/* AltiVec defines four built-in scalar types that serve as vector
16381 elements; we must teach the compiler how to mangle them. */
16382
16383static const char *
16384rs6000_mangle_fundamental_type (tree type)
16385{
16386 if (type == bool_char_type_node) return "U6__boolc";
16387 if (type == bool_short_type_node) return "U6__bools";
16388 if (type == pixel_type_node) return "u7__pixel";
16389 if (type == bool_int_type_node) return "U6__booli";
16390
16391 /* For all other types, use normal C++ mangling. */
16392 return NULL;
16393}
16394
a5c76ee6
ZW		 16395/* Handle a "longcall" or "shortcall" attribute; arguments as in
16396 struct attribute_spec.handler. */
a4f6c312 16397
91d231cb 16398static tree
f676971a
EC		 16399rs6000_handle_longcall_attribute (tree *node, tree name,
16400 tree args ATTRIBUTE_UNUSED,
16401 int flags ATTRIBUTE_UNUSED,
a2369ed3 16402 bool *no_add_attrs)
91d231cb
JM		 16403{
16404 if (TREE_CODE (*node) != FUNCTION_TYPE
16405 && TREE_CODE (*node) != FIELD_DECL
16406 && TREE_CODE (*node) != TYPE_DECL)
16407 {
d4ee4d25 16408 warning (0, "%qs attribute only applies to functions",
91d231cb
JM		 16409 IDENTIFIER_POINTER (name));
16410 *no_add_attrs = true;
16411 }
6a4cee5f 16412
91d231cb 16413 return NULL_TREE;
7509c759
MM		 16414}
16415
a5c76ee6
ZW		 16416/* Set longcall attributes on all functions declared when
16417 rs6000_default_long_calls is true. */
16418static void
a2369ed3 16419rs6000_set_default_type_attributes (tree type)
a5c76ee6
ZW		 16420{
16421 if (rs6000_default_long_calls
16422 && (TREE_CODE (type) == FUNCTION_TYPE
16423 || TREE_CODE (type) == METHOD_TYPE))
16424 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
16425 NULL_TREE,
16426 TYPE_ATTRIBUTES (type));
16427}
16428
3cb999d8
DE		 16429/* Return a reference suitable for calling a function with the
16430 longcall attribute. */
a4f6c312 16431
9390387d 16432rtx
a2369ed3 16433rs6000_longcall_ref (rtx call_ref)
6a4cee5f 16434{
d330fd93 16435 const char *call_name;
6a4cee5f
MM		 16436 tree node;
16437
16438 if (GET_CODE (call_ref) != SYMBOL_REF)
16439 return call_ref;
16440
16441 /* System V adds '.' to the internal name, so skip them. */
16442 call_name = XSTR (call_ref, 0);
16443 if (*call_name == '.')
16444 {
16445 while (*call_name == '.')
16446 call_name++;
16447
16448 node = get_identifier (call_name);
39403d82 16449 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
6a4cee5f
MM		 16450 }
16451
16452 return force_reg (Pmode, call_ref);
16453}
7509c759 16454\f
b64a1b53
RH		 16455#ifdef USING_ELFOS_H
16456
7509c759
MM		 16457/* A C statement or statements to switch to the appropriate section
16458 for output of RTX in mode MODE. You can assume that RTX is some
16459 kind of constant in RTL. The argument MODE is redundant except in
16460 the case of a `const_int' rtx. Select the section by calling
16461 `text_section' or one of the alternatives for other sections.
16462
16463 Do not define this macro if you put all constants in the read-only
16464 data section. */
16465
b64a1b53 16466static void
f676971a 16467rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
a2369ed3 16468 unsigned HOST_WIDE_INT align)
7509c759 16469{
a9098fd0 16470 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
7509c759 16471 toc_section ();
7509c759 16472 else
b64a1b53 16473 default_elf_select_rtx_section (mode, x, align);
7509c759
MM		 16474}
16475
16476/* A C statement or statements to switch to the appropriate
16477 section for output of DECL. DECL is either a `VAR_DECL' node
16478 or a constant of some sort. RELOC indicates whether forming
16479 the initial value of DECL requires link-time relocations. */
16480
ae46c4e0 16481static void
f676971a 16482rs6000_elf_select_section (tree decl, int reloc,
a2369ed3 16483 unsigned HOST_WIDE_INT align)
7509c759 16484{
f1384257
AM		 16485 /* Pretend that we're always building for a shared library when
16486 ABI_AIX, because otherwise we end up with dynamic relocations
16487 in read-only sections. This happens for function pointers,
16488 references to vtables in typeinfo, and probably other cases. */
0e5dbd9b
DE		 16489 default_elf_select_section_1 (decl, reloc, align,
16490 flag_pic || DEFAULT_ABI == ABI_AIX);
63019373
GK		 16491}
16492
16493/* A C statement to build up a unique section name, expressed as a
16494 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16495 RELOC indicates whether the initial value of EXP requires
16496 link-time relocations. If you do not define this macro, GCC will use
16497 the symbol name prefixed by `.' as the section name. Note - this
f5143c46 16498 macro can now be called for uninitialized data items as well as
4912a07c 16499 initialized data and functions. */
63019373 16500
ae46c4e0 16501static void
a2369ed3 16502rs6000_elf_unique_section (tree decl, int reloc)
63019373 16503{
f1384257
AM		 16504 /* As above, pretend that we're always building for a shared library
16505 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
0e5dbd9b
DE		 16506 default_unique_section_1 (decl, reloc,
16507 flag_pic || DEFAULT_ABI == ABI_AIX);
7509c759 16508}
d9407988 16509\f
d1908feb
JJ		 16510/* For a SYMBOL_REF, set generic flags and then perform some
16511 target-specific processing.
16512
d1908feb
JJ		 16513 When the AIX ABI is requested on a non-AIX system, replace the
16514 function name with the real name (with a leading .) rather than the
16515 function descriptor name. This saves a lot of overriding code to
16516 read the prefixes. */
d9407988 16517
fb49053f 16518static void
a2369ed3 16519rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
d9407988 16520{
d1908feb 16521 default_encode_section_info (decl, rtl, first);
b2003250 16522
d1908feb
JJ		 16523 if (first
16524 && TREE_CODE (decl) == FUNCTION_DECL
16525 && !TARGET_AIX
16526 && DEFAULT_ABI == ABI_AIX)
d9407988 16527 {
c6a2438a 16528 rtx sym_ref = XEXP (rtl, 0);
d1908feb
JJ		 16529 size_t len = strlen (XSTR (sym_ref, 0));
16530 char *str = alloca (len + 2);
16531 str[0] = '.';
16532 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16533 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
d9407988 16534 }
d9407988
MM		 16535}
16536
0e5dbd9b 16537static bool
a2369ed3 16538rs6000_elf_in_small_data_p (tree decl)
0e5dbd9b
DE		 16539{
16540 if (rs6000_sdata == SDATA_NONE)
16541 return false;
16542
7482ad25
AF		 16543 /* We want to merge strings, so we never consider them small data. */
16544 if (TREE_CODE (decl) == STRING_CST)
16545 return false;
16546
16547 /* Functions are never in the small data area. */
16548 if (TREE_CODE (decl) == FUNCTION_DECL)
16549 return false;
16550
0e5dbd9b
DE		 16551 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16552 {
16553 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16554 if (strcmp (section, ".sdata") == 0
16555 || strcmp (section, ".sdata2") == 0
20bfcd69
GK		 16556 || strcmp (section, ".sbss") == 0
16557 || strcmp (section, ".sbss2") == 0
16558 || strcmp (section, ".PPC.EMB.sdata0") == 0
16559 || strcmp (section, ".PPC.EMB.sbss0") == 0)
0e5dbd9b
DE		 16560 return true;
16561 }
16562 else
16563 {
16564 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16565
16566 if (size > 0
307b599c 16567 && (unsigned HOST_WIDE_INT) size <= g_switch_value
20bfcd69
GK		 16568 /* If it's not public, and we're not going to reference it there,
16569 there's no need to put it in the small data section. */
0e5dbd9b
DE		 16570 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16571 return true;
16572 }
16573
16574 return false;
16575}
16576
b91da81f 16577#endif /* USING_ELFOS_H */
000034eb 16578
a6c2a102 16579\f
000034eb 16580/* Return a REG that occurs in ADDR with coefficient 1.
02441cd6
JL		 16581 ADDR can be effectively incremented by incrementing REG.
16582
16583 r0 is special and we must not select it as an address
16584 register by this routine since our caller will try to
16585 increment the returned register via an "la" instruction. */
000034eb 16586
9390387d 16587rtx
a2369ed3 16588find_addr_reg (rtx addr)
000034eb
DE		 16589{
16590 while (GET_CODE (addr) == PLUS)
16591 {
02441cd6
JL		 16592 if (GET_CODE (XEXP (addr, 0)) == REG
16593 && REGNO (XEXP (addr, 0)) != 0)
000034eb 16594 addr = XEXP (addr, 0);
02441cd6
JL		 16595 else if (GET_CODE (XEXP (addr, 1)) == REG
16596 && REGNO (XEXP (addr, 1)) != 0)
000034eb
DE		 16597 addr = XEXP (addr, 1);
16598 else if (CONSTANT_P (XEXP (addr, 0)))
16599 addr = XEXP (addr, 1);
16600 else if (CONSTANT_P (XEXP (addr, 1)))
16601 addr = XEXP (addr, 0);
16602 else
37409796 16603 gcc_unreachable ();
000034eb 16604 }
37409796
NS		 16605 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
16606 return addr;
000034eb
DE		 16607}
16608
a6c2a102 16609void
a2369ed3 16610rs6000_fatal_bad_address (rtx op)
a6c2a102
DE		 16611{
16612 fatal_insn ("bad address", op);
16613}
c8023011 16614
ee890fe2
SS		 16615#if TARGET_MACHO
16616
efdba735 16617static tree branch_island_list = 0;
ee890fe2 16618
efdba735
SH		 16619/* Remember to generate a branch island for far calls to the given
16620 function. */
ee890fe2 16621
f676971a 16622static void
c4ad648e
AM		 16623add_compiler_branch_island (tree label_name, tree function_name,
16624 int line_number)
ee890fe2 16625{
efdba735 16626 tree branch_island = build_tree_list (function_name, label_name);
7d60be94 16627 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
efdba735
SH		 16628 TREE_CHAIN (branch_island) = branch_island_list;
16629 branch_island_list = branch_island;
ee890fe2
SS		 16630}
16631
efdba735
SH		 16632#define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16633#define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16634#define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16635 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
ee890fe2 16636
efdba735
SH		 16637/* Generate far-jump branch islands for everything on the
16638 branch_island_list. Invoked immediately after the last instruction
16639 of the epilogue has been emitted; the branch-islands must be
16640 appended to, and contiguous with, the function body. Mach-O stubs
16641 are generated in machopic_output_stub(). */
ee890fe2 16642
efdba735
SH		 16643static void
16644macho_branch_islands (void)
16645{
16646 char tmp_buf[512];
16647 tree branch_island;
16648
16649 for (branch_island = branch_island_list;
16650 branch_island;
16651 branch_island = TREE_CHAIN (branch_island))
16652 {
16653 const char *label =
16654 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16655 const char *name =
11abc112 16656 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
efdba735
SH		 16657 char name_buf[512];
16658 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16659 if (name[0] == '*' || name[0] == '&')
16660 strcpy (name_buf, name+1);
16661 else
16662 {
16663 name_buf[0] = '_';
16664 strcpy (name_buf+1, name);
16665 }
16666 strcpy (tmp_buf, "\n");
16667 strcat (tmp_buf, label);
ee890fe2 16668#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16669 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16670 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16671#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735
SH		 16672 if (flag_pic)
16673 {
16674 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16675 strcat (tmp_buf, label);
16676 strcat (tmp_buf, "_pic\n");
16677 strcat (tmp_buf, label);
16678 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
f676971a 16679
efdba735
SH		 16680 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16681 strcat (tmp_buf, name_buf);
16682 strcat (tmp_buf, " - ");
16683 strcat (tmp_buf, label);
16684 strcat (tmp_buf, "_pic)\n");
f676971a 16685
efdba735 16686 strcat (tmp_buf, "\tmtlr r0\n");
f676971a 16687
efdba735
SH		 16688 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16689 strcat (tmp_buf, name_buf);
16690 strcat (tmp_buf, " - ");
16691 strcat (tmp_buf, label);
16692 strcat (tmp_buf, "_pic)\n");
f676971a 16693
efdba735
SH		 16694 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16695 }
16696 else
16697 {
16698 strcat (tmp_buf, ":\nlis r12,hi16(");
16699 strcat (tmp_buf, name_buf);
16700 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16701 strcat (tmp_buf, name_buf);
16702 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16703 }
16704 output_asm_insn (tmp_buf, 0);
ee890fe2 16705#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16706 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16707 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16708#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735 16709 }
ee890fe2 16710
efdba735 16711 branch_island_list = 0;
ee890fe2
SS		 16712}
16713
16714/* NO_PREVIOUS_DEF checks in the link list whether the function name is
16715 already there or not. */
16716
efdba735 16717static int
a2369ed3 16718no_previous_def (tree function_name)
ee890fe2 16719{
efdba735
SH		 16720 tree branch_island;
16721 for (branch_island = branch_island_list;
16722 branch_island;
16723 branch_island = TREE_CHAIN (branch_island))
16724 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
ee890fe2
SS		 16725 return 0;
16726 return 1;
16727}
16728
16729/* GET_PREV_LABEL gets the label name from the previous definition of
16730 the function. */
16731
efdba735 16732static tree
a2369ed3 16733get_prev_label (tree function_name)
ee890fe2 16734{
efdba735
SH		 16735 tree branch_island;
16736 for (branch_island = branch_island_list;
16737 branch_island;
16738 branch_island = TREE_CHAIN (branch_island))
16739 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16740 return BRANCH_ISLAND_LABEL_NAME (branch_island);
ee890fe2
SS		 16741 return 0;
16742}
16743
16744/* INSN is either a function call or a millicode call. It may have an
f676971a 16745 unconditional jump in its delay slot.
ee890fe2
SS		 16746
16747 CALL_DEST is the routine we are calling. */
16748
16749char *
c4ad648e
AM		 16750output_call (rtx insn, rtx *operands, int dest_operand_number,
16751 int cookie_operand_number)
ee890fe2
SS		 16752{
16753 static char buf[256];
efdba735
SH		 16754 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
16755 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
ee890fe2
SS		 16756 {
16757 tree labelname;
efdba735 16758 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
f676971a 16759
ee890fe2
SS		 16760 if (no_previous_def (funname))
16761 {
308c142a 16762 int line_number = 0;
ee890fe2
SS		 16763 rtx label_rtx = gen_label_rtx ();
16764 char *label_buf, temp_buf[256];
16765 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
16766 CODE_LABEL_NUMBER (label_rtx));
16767 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
16768 labelname = get_identifier (label_buf);
16769 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
16770 if (insn)
16771 line_number = NOTE_LINE_NUMBER (insn);
efdba735 16772 add_compiler_branch_island (labelname, funname, line_number);
ee890fe2
SS		 16773 }
16774 else
16775 labelname = get_prev_label (funname);
16776
efdba735
SH		 16777 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16778 instruction will reach 'foo', otherwise link as 'bl L42'".
16779 "L42" should be a 'branch island', that will do a far jump to
16780 'foo'. Branch islands are generated in
16781 macho_branch_islands(). */
ee890fe2 16782 sprintf (buf, "jbsr %%z%d,%.246s",
efdba735 16783 dest_operand_number, IDENTIFIER_POINTER (labelname));
ee890fe2
SS		 16784 }
16785 else
efdba735
SH		 16786 sprintf (buf, "bl %%z%d", dest_operand_number);
16787 return buf;
ee890fe2
SS		 16788}
16789
ee890fe2
SS		 16790/* Generate PIC and indirect symbol stubs. */
16791
16792void
a2369ed3 16793machopic_output_stub (FILE *file, const char *symb, const char *stub)
ee890fe2
SS		 16794{
16795 unsigned int length;
a4f6c312
SS		 16796 char *symbol_name, *lazy_ptr_name;
16797 char *local_label_0;
ee890fe2
SS		 16798 static int label = 0;
16799
df56a27f 16800 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
772c5265 16801 symb = (*targetm.strip_name_encoding) (symb);
df56a27f 16802
ee890fe2 16803
ee890fe2
SS		 16804 length = strlen (symb);
16805 symbol_name = alloca (length + 32);
16806 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16807
16808 lazy_ptr_name = alloca (length + 32);
16809 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
16810
ee890fe2 16811 if (flag_pic == 2)
d3c300d2 16812 machopic_picsymbol_stub1_section ();
ee890fe2 16813 else
d3c300d2 16814 machopic_symbol_stub1_section ();
ee890fe2
SS		 16815
16816 if (flag_pic == 2)
16817 {
d974312d
DJ		 16818 fprintf (file, "\t.align 5\n");
16819
16820 fprintf (file, "%s:\n", stub);
16821 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16822
876455fa 16823 label++;
89da1f32 16824 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
876455fa 16825 sprintf (local_label_0, "\"L%011d$spb\"", label);
f676971a 16826
ee890fe2
SS		 16827 fprintf (file, "\tmflr r0\n");
16828 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
16829 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
16830 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
16831 lazy_ptr_name, local_label_0);
16832 fprintf (file, "\tmtlr r0\n");
3d0e2d58
SS		 16833 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
16834 (TARGET_64BIT ? "ldu" : "lwzu"),
ee890fe2
SS		 16835 lazy_ptr_name, local_label_0);
16836 fprintf (file, "\tmtctr r12\n");
ee890fe2
SS		 16837 fprintf (file, "\tbctr\n");
16838 }
16839 else
d974312d
DJ		 16840 {
16841 fprintf (file, "\t.align 4\n");
16842
16843 fprintf (file, "%s:\n", stub);
16844 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16845
16846 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
d9e4e4f5
SS		 16847 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
16848 (TARGET_64BIT ? "ldu" : "lwzu"),
16849 lazy_ptr_name);
d974312d
DJ		 16850 fprintf (file, "\tmtctr r12\n");
16851 fprintf (file, "\tbctr\n");
16852 }
f676971a 16853
ee890fe2
SS		 16854 machopic_lazy_symbol_ptr_section ();
16855 fprintf (file, "%s:\n", lazy_ptr_name);
16856 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
49bd1d27
SS		 16857 fprintf (file, "%sdyld_stub_binding_helper\n",
16858 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
ee890fe2
SS		 16859}
16860
16861/* Legitimize PIC addresses. If the address is already
16862 position-independent, we return ORIG. Newly generated
16863 position-independent addresses go into a reg. This is REG if non
16864 zero, otherwise we allocate register(s) as necessary. */
16865
9390387d 16866#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
ee890fe2
SS		 16867
16868rtx
f676971a 16869rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
a2369ed3 16870 rtx reg)
ee890fe2
SS		 16871{
16872 rtx base, offset;
16873
16874 if (reg == NULL && ! reload_in_progress && ! reload_completed)
16875 reg = gen_reg_rtx (Pmode);
16876
16877 if (GET_CODE (orig) == CONST)
16878 {
37409796
NS		 16879 rtx reg_temp;
16880
ee890fe2
SS		 16881 if (GET_CODE (XEXP (orig, 0)) == PLUS
16882 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
16883 return orig;
16884
37409796
NS		 16885 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
16886
16887 /* Use a different reg for the intermediate value, as
16888 it will be marked UNCHANGING. */
16889 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
16890 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
16891 Pmode, reg_temp);
16892 offset =
16893 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
16894 Pmode, reg);
16895
ee890fe2
SS		 16896 if (GET_CODE (offset) == CONST_INT)
16897 {
16898 if (SMALL_INT (offset))
ed8908e7 16899 return plus_constant (base, INTVAL (offset));
ee890fe2
SS		 16900 else if (! reload_in_progress && ! reload_completed)
16901 offset = force_reg (Pmode, offset);
16902 else
c859cda6
DJ		 16903 {
16904 rtx mem = force_const_mem (Pmode, orig);
16905 return machopic_legitimize_pic_address (mem, Pmode, reg);
16906 }
ee890fe2 16907 }
f1c25d3b 16908 return gen_rtx_PLUS (Pmode, base, offset);
ee890fe2
SS		 16909 }
16910
16911 /* Fall back on generic machopic code. */
16912 return machopic_legitimize_pic_address (orig, mode, reg);
16913}
16914
16915/* This is just a placeholder to make linking work without having to
16916 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16917 ever needed for Darwin (not too likely!) this would have to get a
16918 real definition. */
16919
16920void
863d938c 16921toc_section (void)
ee890fe2
SS		 16922{
16923}
16924
c4e18b1c
GK		 16925/* Output a .machine directive for the Darwin assembler, and call
16926 the generic start_file routine. */
16927
16928static void
16929rs6000_darwin_file_start (void)
16930{
94ff898d 16931 static const struct
c4e18b1c
GK		 16932 {
16933 const char *arg;
16934 const char *name;
16935 int if_set;
16936 } mapping[] = {
55dbfb48 16937 { "ppc64", "ppc64", MASK_64BIT },
c4e18b1c
GK		 16938 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
16939 { "power4", "ppc970", 0 },
16940 { "G5", "ppc970", 0 },
16941 { "7450", "ppc7450", 0 },
16942 { "7400", "ppc7400", MASK_ALTIVEC },
16943 { "G4", "ppc7400", 0 },
16944 { "750", "ppc750", 0 },
16945 { "740", "ppc750", 0 },
16946 { "G3", "ppc750", 0 },
16947 { "604e", "ppc604e", 0 },
16948 { "604", "ppc604", 0 },
16949 { "603e", "ppc603", 0 },
16950 { "603", "ppc603", 0 },
16951 { "601", "ppc601", 0 },
16952 { NULL, "ppc", 0 } };
16953 const char *cpu_id = "";
16954 size_t i;
94ff898d 16955
9390387d 16956 rs6000_file_start ();
c4e18b1c
GK		 16957
16958 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
16959 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
16960 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
16961 && rs6000_select[i].string[0] != '\0')
16962 cpu_id = rs6000_select[i].string;
16963
16964 /* Look through the mapping array. Pick the first name that either
16965 matches the argument, has a bit set in IF_SET that is also set
16966 in the target flags, or has a NULL name. */
16967
16968 i = 0;
16969 while (mapping[i].arg != NULL
16970 && strcmp (mapping[i].arg, cpu_id) != 0
16971 && (mapping[i].if_set & target_flags) == 0)
16972 i++;
16973
16974 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
16975}
16976
ee890fe2 16977#endif /* TARGET_MACHO */
7c262518
RH		 16978
16979#if TARGET_ELF
16980static unsigned int
a2369ed3 16981rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
7c262518 16982{
1ff8f81a
AM		 16983 return default_section_type_flags_1 (decl, name, reloc,
16984 flag_pic || DEFAULT_ABI == ABI_AIX);
7c262518 16985}
d9f6800d
RH		 16986
16987/* Record an element in the table of global constructors. SYMBOL is
16988 a SYMBOL_REF of the function to be called; PRIORITY is a number
16989 between 0 and MAX_INIT_PRIORITY.
16990
16991 This differs from default_named_section_asm_out_constructor in
16992 that we have special handling for -mrelocatable. */
16993
16994static void
a2369ed3 16995rs6000_elf_asm_out_constructor (rtx symbol, int priority)
d9f6800d
RH		 16996{
16997 const char *section = ".ctors";
16998 char buf[16];
16999
17000 if (priority != DEFAULT_INIT_PRIORITY)
17001 {
17002 sprintf (buf, ".ctors.%.5u",
c4ad648e
AM		 17003 /* Invert the numbering so the linker puts us in the proper
17004 order; constructors are run from right to left, and the
17005 linker sorts in increasing order. */
17006 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 17007 section = buf;
17008 }
17009
715bdd29
RH		 17010 named_section_flags (section, SECTION_WRITE);
17011 assemble_align (POINTER_SIZE);
d9f6800d
RH		 17012
17013 if (TARGET_RELOCATABLE)
17014 {
17015 fputs ("\t.long (", asm_out_file);
17016 output_addr_const (asm_out_file, symbol);
17017 fputs (")@fixup\n", asm_out_file);
17018 }
17019 else
c8af3574 17020 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d
RH		 17021}
17022
17023static void
a2369ed3 17024rs6000_elf_asm_out_destructor (rtx symbol, int priority)
d9f6800d
RH		 17025{
17026 const char *section = ".dtors";
17027 char buf[16];
17028
17029 if (priority != DEFAULT_INIT_PRIORITY)
17030 {
17031 sprintf (buf, ".dtors.%.5u",
c4ad648e
AM		 17032 /* Invert the numbering so the linker puts us in the proper
17033 order; constructors are run from right to left, and the
17034 linker sorts in increasing order. */
17035 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 17036 section = buf;
17037 }
17038
715bdd29
RH		 17039 named_section_flags (section, SECTION_WRITE);
17040 assemble_align (POINTER_SIZE);
d9f6800d
RH		 17041
17042 if (TARGET_RELOCATABLE)
17043 {
17044 fputs ("\t.long (", asm_out_file);
17045 output_addr_const (asm_out_file, symbol);
17046 fputs (")@fixup\n", asm_out_file);
17047 }
17048 else
c8af3574 17049 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d 17050}
9739c90c
JJ		 17051
17052void
a2369ed3 17053rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
9739c90c
JJ		 17054{
17055 if (TARGET_64BIT)
17056 {
17057 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17058 ASM_OUTPUT_LABEL (file, name);
17059 fputs (DOUBLE_INT_ASM_OP, file);
85b776df
AM		 17060 rs6000_output_function_entry (file, name);
17061 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17062 if (DOT_SYMBOLS)
9739c90c 17063 {
85b776df 17064 fputs ("\t.size\t", file);
9739c90c 17065 assemble_name (file, name);
85b776df
AM		 17066 fputs (",24\n\t.type\t.", file);
17067 assemble_name (file, name);
17068 fputs (",@function\n", file);
17069 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17070 {
17071 fputs ("\t.globl\t.", file);
17072 assemble_name (file, name);
17073 putc ('\n', file);
17074 }
9739c90c 17075 }
85b776df
AM		 17076 else
17077 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
9739c90c 17078 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
85b776df
AM		 17079 rs6000_output_function_entry (file, name);
17080 fputs (":\n", file);
9739c90c
JJ		 17081 return;
17082 }
17083
17084 if (TARGET_RELOCATABLE
17085 && (get_pool_size () != 0 || current_function_profile)
3c9eb5f4 17086 && uses_TOC ())
9739c90c
JJ		 17087 {
17088 char buf[256];
17089
17090 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17091
17092 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17093 fprintf (file, "\t.long ");
17094 assemble_name (file, buf);
17095 putc ('-', file);
17096 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17097 assemble_name (file, buf);
17098 putc ('\n', file);
17099 }
17100
17101 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17102 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17103
17104 if (DEFAULT_ABI == ABI_AIX)
17105 {
17106 const char *desc_name, *orig_name;
17107
17108 orig_name = (*targetm.strip_name_encoding) (name);
17109 desc_name = orig_name;
17110 while (*desc_name == '.')
17111 desc_name++;
17112
17113 if (TREE_PUBLIC (decl))
17114 fprintf (file, "\t.globl %s\n", desc_name);
17115
17116 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17117 fprintf (file, "%s:\n", desc_name);
17118 fprintf (file, "\t.long %s\n", orig_name);
17119 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17120 if (DEFAULT_ABI == ABI_AIX)
17121 fputs ("\t.long 0\n", file);
17122 fprintf (file, "\t.previous\n");
17123 }
17124 ASM_OUTPUT_LABEL (file, name);
17125}
1334b570
AM		 17126
17127static void
17128rs6000_elf_end_indicate_exec_stack (void)
17129{
17130 if (TARGET_32BIT)
17131 file_end_indicate_exec_stack ();
17132}
7c262518
RH		 17133#endif
17134
cbaaba19 17135#if TARGET_XCOFF
7c262518 17136static void
a2369ed3 17137rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
b275d088
DE		 17138{
17139 fputs (GLOBAL_ASM_OP, stream);
17140 RS6000_OUTPUT_BASENAME (stream, name);
17141 putc ('\n', stream);
17142}
17143
17144static void
c18a5b6c
MM		 17145rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17146 tree decl ATTRIBUTE_UNUSED)
7c262518 17147{
0e5dbd9b
DE		 17148 int smclass;
17149 static const char * const suffix[3] = { "PR", "RO", "RW" };
17150
17151 if (flags & SECTION_CODE)
17152 smclass = 0;
17153 else if (flags & SECTION_WRITE)
17154 smclass = 2;
17155 else
17156 smclass = 1;
17157
5b5198f7 17158 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
0e5dbd9b 17159 (flags & SECTION_CODE) ? "." : "",
5b5198f7 17160 name, suffix[smclass], flags & SECTION_ENTSIZE);
7c262518 17161}
ae46c4e0
RH		 17162
17163static void
f676971a 17164rs6000_xcoff_select_section (tree decl, int reloc,
c4ad648e 17165 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
ae46c4e0 17166{
5add3202 17167 if (decl_readonly_section_1 (decl, reloc, 1))
ae46c4e0 17168 {
0e5dbd9b 17169 if (TREE_PUBLIC (decl))
c4ad648e 17170 read_only_data_section ();
ae46c4e0 17171 else
c4ad648e 17172 read_only_private_data_section ();
ae46c4e0
RH		 17173 }
17174 else
17175 {
0e5dbd9b 17176 if (TREE_PUBLIC (decl))
c4ad648e 17177 data_section ();
ae46c4e0 17178 else
c4ad648e 17179 private_data_section ();
ae46c4e0
RH		 17180 }
17181}
17182
17183static void
a2369ed3 17184rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
ae46c4e0
RH		 17185{
17186 const char *name;
ae46c4e0 17187
5b5198f7
DE		 17188 /* Use select_section for private and uninitialized data. */
17189 if (!TREE_PUBLIC (decl)
17190 || DECL_COMMON (decl)
0e5dbd9b
DE		 17191 || DECL_INITIAL (decl) == NULL_TREE
17192 || DECL_INITIAL (decl) == error_mark_node
17193 || (flag_zero_initialized_in_bss
17194 && initializer_zerop (DECL_INITIAL (decl))))
17195 return;
17196
17197 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17198 name = (*targetm.strip_name_encoding) (name);
17199 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
ae46c4e0 17200}
b64a1b53 17201
fb49053f
RH		 17202/* Select section for constant in constant pool.
17203
17204 On RS/6000, all constants are in the private read-only data area.
17205 However, if this is being placed in the TOC it must be output as a
17206 toc entry. */
17207
b64a1b53 17208static void
f676971a 17209rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
c4ad648e 17210 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
b64a1b53
RH		 17211{
17212 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17213 toc_section ();
17214 else
17215 read_only_private_data_section ();
17216}
772c5265
RH		 17217
17218/* Remove any trailing [DS] or the like from the symbol name. */
17219
17220static const char *
a2369ed3 17221rs6000_xcoff_strip_name_encoding (const char *name)
772c5265
RH		 17222{
17223 size_t len;
17224 if (*name == '*')
17225 name++;
17226 len = strlen (name);
17227 if (name[len - 1] == ']')
17228 return ggc_alloc_string (name, len - 4);
17229 else
17230 return name;
17231}
17232
5add3202
DE		 17233/* Section attributes. AIX is always PIC. */
17234
17235static unsigned int
a2369ed3 17236rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
5add3202 17237{
5b5198f7
DE		 17238 unsigned int align;
17239 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
17240
17241 /* Align to at least UNIT size. */
17242 if (flags & SECTION_CODE)
17243 align = MIN_UNITS_PER_WORD;
17244 else
17245 /* Increase alignment of large objects if not already stricter. */
17246 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
17247 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
17248 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
17249
17250 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
5add3202 17251}
a5fe455b 17252
1bc7c5b6
ZW		 17253/* Output at beginning of assembler file.
17254
17255 Initialize the section names for the RS/6000 at this point.
17256
17257 Specify filename, including full path, to assembler.
17258
17259 We want to go into the TOC section so at least one .toc will be emitted.
17260 Also, in order to output proper .bs/.es pairs, we need at least one static
17261 [RW] section emitted.
17262
17263 Finally, declare mcount when profiling to make the assembler happy. */
17264
17265static void
863d938c 17266rs6000_xcoff_file_start (void)
1bc7c5b6
ZW		 17267{
17268 rs6000_gen_section_name (&xcoff_bss_section_name,
17269 main_input_filename, ".bss_");
17270 rs6000_gen_section_name (&xcoff_private_data_section_name,
17271 main_input_filename, ".rw_");
17272 rs6000_gen_section_name (&xcoff_read_only_section_name,
17273 main_input_filename, ".ro_");
17274
17275 fputs ("\t.file\t", asm_out_file);
17276 output_quoted_string (asm_out_file, main_input_filename);
17277 fputc ('\n', asm_out_file);
1bc7c5b6
ZW		 17278 if (write_symbols != NO_DEBUG)
17279 private_data_section ();
17280 text_section ();
17281 if (profile_flag)
17282 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
17283 rs6000_file_start ();
17284}
17285
a5fe455b
ZW		 17286/* Output at end of assembler file.
17287 On the RS/6000, referencing data should automatically pull in text. */
17288
17289static void
863d938c 17290rs6000_xcoff_file_end (void)
a5fe455b
ZW		 17291{
17292 text_section ();
17293 fputs ("_section_.text:\n", asm_out_file);
17294 data_section ();
17295 fputs (TARGET_32BIT
17296 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17297 asm_out_file);
17298}
f1384257 17299#endif /* TARGET_XCOFF */
0e5dbd9b 17300
f1384257
AM		 17301#if TARGET_MACHO
17302/* Cross-module name binding. Darwin does not support overriding
7f3d8013 17303 functions at dynamic-link time. */
0e5dbd9b 17304
2bcc50d0 17305static bool
a2369ed3 17306rs6000_binds_local_p (tree decl)
0e5dbd9b 17307{
f1384257 17308 return default_binds_local_p_1 (decl, 0);
0e5dbd9b 17309}
f1384257 17310#endif
34bb030a 17311
3c50106f
RH		 17312/* Compute a (partial) cost for rtx X. Return true if the complete
17313 cost has been computed, and false if subexpressions should be
17314 scanned. In either case, *TOTAL contains the cost result. */
17315
17316static bool
1494c534 17317rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
3c50106f 17318{
f0517163
RS		 17319 enum machine_mode mode = GET_MODE (x);
17320
3c50106f
RH		 17321 switch (code)
17322 {
30a555d9 17323 /* On the RS/6000, if it is valid in the insn, it is free. */
3c50106f 17324 case CONST_INT:
066cd967
DE		 17325 if (((outer_code == SET
17326 || outer_code == PLUS
17327 || outer_code == MINUS)
17328 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17329 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
066cd967
DE		 17330 || (outer_code == AND
17331 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
22e54023
DE		 17332 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17333 mode == SImode ? 'L' : 'J'))
d5861a7a 17334 || mask_operand (x, VOIDmode)))
22e54023
DE		 17335 || ((outer_code == IOR || outer_code == XOR)
17336 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17337 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17338 mode == SImode ? 'L' : 'J'))))
066cd967
DE		 17339 || outer_code == ASHIFT
17340 || outer_code == ASHIFTRT
17341 || outer_code == LSHIFTRT
17342 || outer_code == ROTATE
17343 || outer_code == ROTATERT
d5861a7a 17344 || outer_code == ZERO_EXTRACT
066cd967
DE		 17345 || (outer_code == MULT
17346 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
22e54023
DE		 17347 || ((outer_code == DIV || outer_code == UDIV
17348 || outer_code == MOD || outer_code == UMOD)
17349 && exact_log2 (INTVAL (x)) >= 0)
066cd967
DE		 17350 || (outer_code == COMPARE
17351 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
22e54023
DE		 17352 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
17353 || (outer_code == EQ
17354 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17355 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17356 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17357 mode == SImode ? 'L' : 'J'))))
17358 || (outer_code == GTU
17359 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
17360 || (outer_code == LTU
17361 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
066cd967
DE		 17362 {
17363 *total = 0;
17364 return true;
17365 }
17366 else if ((outer_code == PLUS
17367 && reg_or_add_cint64_operand (x, VOIDmode))
17368 || (outer_code == MINUS
17369 && reg_or_sub_cint64_operand (x, VOIDmode))
17370 || ((outer_code == SET
17371 || outer_code == IOR
17372 || outer_code == XOR)
17373 && (INTVAL (x)
17374 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
17375 {
17376 *total = COSTS_N_INSNS (1);
17377 return true;
17378 }
17379 /* FALLTHRU */
17380
17381 case CONST_DOUBLE:
17382 if (mode == DImode
17383 && ((outer_code == AND
17384 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17385 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
d5861a7a 17386 || mask64_operand (x, DImode)))
066cd967
DE		 17387 || ((outer_code == IOR || outer_code == XOR)
17388 && CONST_DOUBLE_HIGH (x) == 0
17389 && (CONST_DOUBLE_LOW (x)
17390 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
17391 {
17392 *total = 0;
17393 return true;
17394 }
17395 else if (mode == DImode
17396 && (outer_code == SET
17397 || outer_code == IOR
17398 || outer_code == XOR)
17399 && CONST_DOUBLE_HIGH (x) == 0)
17400 {
17401 *total = COSTS_N_INSNS (1);
17402 return true;
17403 }
17404 /* FALLTHRU */
17405
3c50106f 17406 case CONST:
066cd967 17407 case HIGH:
3c50106f 17408 case SYMBOL_REF:
066cd967
DE		 17409 case MEM:
17410 /* When optimizing for size, MEM should be slightly more expensive
17411 than generating address, e.g., (plus (reg) (const)).
c112cf2b 17412 L1 cache latency is about two instructions. */
066cd967 17413 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
3c50106f
RH		 17414 return true;
17415
30a555d9
DE		 17416 case LABEL_REF:
17417 *total = 0;
17418 return true;
17419
3c50106f 17420 case PLUS:
f0517163 17421 if (mode == DFmode)
066cd967
DE		 17422 {
17423 if (GET_CODE (XEXP (x, 0)) == MULT)
17424 {
17425 /* FNMA accounted in outer NEG. */
17426 if (outer_code == NEG)
17427 *total = rs6000_cost->dmul - rs6000_cost->fp;
17428 else
17429 *total = rs6000_cost->dmul;
17430 }
17431 else
17432 *total = rs6000_cost->fp;
17433 }
f0517163 17434 else if (mode == SFmode)
066cd967
DE		 17435 {
17436 /* FNMA accounted in outer NEG. */
17437 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17438 *total = 0;
17439 else
17440 *total = rs6000_cost->fp;
17441 }
938bf747
RS		 17442 else if (GET_CODE (XEXP (x, 0)) == MULT)
17443 {
17444 /* The rs6000 doesn't have shift-and-add instructions. */
17445 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
17446 *total += COSTS_N_INSNS (1);
17447 }
f0517163 17448 else
066cd967
DE		 17449 *total = COSTS_N_INSNS (1);
17450 return false;
3c50106f 17451
52190329 17452 case MINUS:
f0517163 17453 if (mode == DFmode)
066cd967
DE		 17454 {
17455 if (GET_CODE (XEXP (x, 0)) == MULT)
17456 {
17457 /* FNMA accounted in outer NEG. */
17458 if (outer_code == NEG)
17459 *total = 0;
17460 else
17461 *total = rs6000_cost->dmul;
17462 }
17463 else
17464 *total = rs6000_cost->fp;
17465 }
f0517163 17466 else if (mode == SFmode)
066cd967
DE		 17467 {
17468 /* FNMA accounted in outer NEG. */
17469 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17470 *total = 0;
17471 else
17472 *total = rs6000_cost->fp;
17473 }
938bf747
RS		 17474 else if (GET_CODE (XEXP (x, 0)) == MULT)
17475 {
17476 /* The rs6000 doesn't have shift-and-sub instructions. */
17477 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17478 *total += COSTS_N_INSNS (1);
17479 }
f0517163 17480 else
c4ad648e 17481 *total = COSTS_N_INSNS (1);
066cd967 17482 return false;
3c50106f
RH		 17483
17484 case MULT:
c9dbf840
DE		 17485 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17486 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
3c50106f 17487 {
8b897cfa
RS		 17488 if (INTVAL (XEXP (x, 1)) >= -256
17489 && INTVAL (XEXP (x, 1)) <= 255)
06a67bdd 17490 *total = rs6000_cost->mulsi_const9;
8b897cfa 17491 else
06a67bdd 17492 *total = rs6000_cost->mulsi_const;
3c50106f 17493 }
066cd967
DE		 17494 /* FMA accounted in outer PLUS/MINUS. */
17495 else if ((mode == DFmode || mode == SFmode)
17496 && (outer_code == PLUS || outer_code == MINUS))
17497 *total = 0;
f0517163 17498 else if (mode == DFmode)
06a67bdd 17499 *total = rs6000_cost->dmul;
f0517163 17500 else if (mode == SFmode)
06a67bdd 17501 *total = rs6000_cost->fp;
f0517163 17502 else if (mode == DImode)
06a67bdd 17503 *total = rs6000_cost->muldi;
8b897cfa 17504 else
06a67bdd 17505 *total = rs6000_cost->mulsi;
066cd967 17506 return false;
3c50106f
RH		 17507
17508 case DIV:
17509 case MOD:
f0517163
RS		 17510 if (FLOAT_MODE_P (mode))
17511 {
06a67bdd
RS		 17512 *total = mode == DFmode ? rs6000_cost->ddiv
17513 : rs6000_cost->sdiv;
066cd967 17514 return false;
f0517163 17515 }
5efb1046 17516 /* FALLTHRU */
3c50106f
RH		 17517
17518 case UDIV:
17519 case UMOD:
627b6fe2
DJ		 17520 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17521 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17522 {
17523 if (code == DIV || code == MOD)
17524 /* Shift, addze */
17525 *total = COSTS_N_INSNS (2);
17526 else
17527 /* Shift */
17528 *total = COSTS_N_INSNS (1);
17529 }
c4ad648e 17530 else
627b6fe2
DJ		 17531 {
17532 if (GET_MODE (XEXP (x, 1)) == DImode)
17533 *total = rs6000_cost->divdi;
17534 else
17535 *total = rs6000_cost->divsi;
17536 }
17537 /* Add in shift and subtract for MOD. */
17538 if (code == MOD || code == UMOD)
17539 *total += COSTS_N_INSNS (2);
066cd967 17540 return false;
3c50106f
RH		 17541
17542 case FFS:
17543 *total = COSTS_N_INSNS (4);
066cd967 17544 return false;
3c50106f 17545
06a67bdd 17546 case NOT:
066cd967
DE		 17547 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17548 {
17549 *total = 0;
17550 return false;
17551 }
17552 /* FALLTHRU */
17553
17554 case AND:
17555 case IOR:
17556 case XOR:
d5861a7a
DE		 17557 case ZERO_EXTRACT:
17558 *total = COSTS_N_INSNS (1);
17559 return false;
17560
066cd967
DE		 17561 case ASHIFT:
17562 case ASHIFTRT:
17563 case LSHIFTRT:
17564 case ROTATE:
17565 case ROTATERT:
d5861a7a 17566 /* Handle mul_highpart. */
066cd967
DE		 17567 if (outer_code == TRUNCATE
17568 && GET_CODE (XEXP (x, 0)) == MULT)
17569 {
17570 if (mode == DImode)
17571 *total = rs6000_cost->muldi;
17572 else
17573 *total = rs6000_cost->mulsi;
17574 return true;
17575 }
d5861a7a
DE		 17576 else if (outer_code == AND)
17577 *total = 0;
17578 else
17579 *total = COSTS_N_INSNS (1);
17580 return false;
17581
17582 case SIGN_EXTEND:
17583 case ZERO_EXTEND:
17584 if (GET_CODE (XEXP (x, 0)) == MEM)
17585 *total = 0;
17586 else
17587 *total = COSTS_N_INSNS (1);
066cd967 17588 return false;
06a67bdd 17589
066cd967
DE		 17590 case COMPARE:
17591 case NEG:
17592 case ABS:
17593 if (!FLOAT_MODE_P (mode))
17594 {
17595 *total = COSTS_N_INSNS (1);
17596 return false;
17597 }
17598 /* FALLTHRU */
17599
17600 case FLOAT:
17601 case UNSIGNED_FLOAT:
17602 case FIX:
17603 case UNSIGNED_FIX:
17604 case FLOAT_EXTEND:
06a67bdd
RS		 17605 case FLOAT_TRUNCATE:
17606 *total = rs6000_cost->fp;
066cd967 17607 return false;
06a67bdd
RS		 17608
17609 case UNSPEC:
17610 switch (XINT (x, 1))
17611 {
17612 case UNSPEC_FRSP:
17613 *total = rs6000_cost->fp;
17614 return true;
17615
17616 default:
17617 break;
17618 }
17619 break;
17620
17621 case CALL:
17622 case IF_THEN_ELSE:
17623 if (optimize_size)
17624 {
17625 *total = COSTS_N_INSNS (1);
17626 return true;
17627 }
066cd967
DE		 17628 else if (FLOAT_MODE_P (mode)
17629 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17630 {
17631 *total = rs6000_cost->fp;
17632 return false;
17633 }
06a67bdd
RS		 17634 break;
17635
c0600ecd
DE		 17636 case EQ:
17637 case GTU:
17638 case LTU:
22e54023
DE		 17639 /* Carry bit requires mode == Pmode.
17640 NEG or PLUS already counted so only add one. */
17641 if (mode == Pmode
17642 && (outer_code == NEG || outer_code == PLUS))
c0600ecd 17643 {
22e54023
DE		 17644 *total = COSTS_N_INSNS (1);
17645 return true;
17646 }
17647 if (outer_code == SET)
17648 {
17649 if (XEXP (x, 1) == const0_rtx)
c0600ecd 17650 {
22e54023 17651 *total = COSTS_N_INSNS (2);
c0600ecd 17652 return true;
c0600ecd 17653 }
22e54023
DE		 17654 else if (mode == Pmode)
17655 {
17656 *total = COSTS_N_INSNS (3);
17657 return false;
17658 }
17659 }
17660 /* FALLTHRU */
17661
17662 case GT:
17663 case LT:
17664 case UNORDERED:
17665 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17666 {
17667 *total = COSTS_N_INSNS (2);
17668 return true;
c0600ecd 17669 }
22e54023
DE		 17670 /* CC COMPARE. */
17671 if (outer_code == COMPARE)
17672 {
17673 *total = 0;
17674 return true;
17675 }
17676 break;
c0600ecd 17677
3c50106f 17678 default:
06a67bdd 17679 break;
3c50106f 17680 }
06a67bdd
RS		 17681
17682 return false;
3c50106f
RH		 17683}
17684
34bb030a
DE		 17685/* A C expression returning the cost of moving data from a register of class
17686 CLASS1 to one of CLASS2. */
17687
17688int
f676971a 17689rs6000_register_move_cost (enum machine_mode mode,
a2369ed3 17690 enum reg_class from, enum reg_class to)
34bb030a
DE		 17691{
17692 /* Moves from/to GENERAL_REGS. */
17693 if (reg_classes_intersect_p (to, GENERAL_REGS)
17694 || reg_classes_intersect_p (from, GENERAL_REGS))
17695 {
17696 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17697 from = to;
17698
17699 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17700 return (rs6000_memory_move_cost (mode, from, 0)
17701 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17702
c4ad648e
AM		 17703 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17704 shift. */
34bb030a
DE		 17705 else if (from == CR_REGS)
17706 return 4;
17707
17708 else
c4ad648e 17709 /* A move will cost one instruction per GPR moved. */
34bb030a
DE		 17710 return 2 * HARD_REGNO_NREGS (0, mode);
17711 }
17712
c4ad648e 17713 /* Moving between two similar registers is just one instruction. */
34bb030a
DE		 17714 else if (reg_classes_intersect_p (to, from))
17715 return mode == TFmode ? 4 : 2;
17716
c4ad648e 17717 /* Everything else has to go through GENERAL_REGS. */
34bb030a 17718 else
f676971a 17719 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34bb030a
DE		 17720 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17721}
17722
17723/* A C expressions returning the cost of moving data of MODE from a register to
17724 or from memory. */
17725
17726int
f676971a 17727rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
a2369ed3 17728 int in ATTRIBUTE_UNUSED)
34bb030a
DE		 17729{
17730 if (reg_classes_intersect_p (class, GENERAL_REGS))
17731 return 4 * HARD_REGNO_NREGS (0, mode);
17732 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17733 return 4 * HARD_REGNO_NREGS (32, mode);
17734 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17735 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
17736 else
17737 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17738}
17739
ded9bf77
AH		 17740/* Return an RTX representing where to find the function value of a
17741 function returning MODE. */
17742static rtx
17743rs6000_complex_function_value (enum machine_mode mode)
17744{
17745 unsigned int regno;
17746 rtx r1, r2;
17747 enum machine_mode inner = GET_MODE_INNER (mode);
fb7e4164 17748 unsigned int inner_bytes = GET_MODE_SIZE (inner);
ded9bf77 17749
18f63bfa
AH		 17750 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
17751 regno = FP_ARG_RETURN;
354ed18f
AH		 17752 else
17753 {
18f63bfa 17754 regno = GP_ARG_RETURN;
ded9bf77 17755
18f63bfa
AH		 17756 /* 32-bit is OK since it'll go in r3/r4. */
17757 if (TARGET_32BIT && inner_bytes >= 4)
ded9bf77
AH		 17758 return gen_rtx_REG (mode, regno);
17759 }
17760
18f63bfa
AH		 17761 if (inner_bytes >= 8)
17762 return gen_rtx_REG (mode, regno);
17763
ded9bf77
AH		 17764 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
17765 const0_rtx);
17766 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
fb7e4164 17767 GEN_INT (inner_bytes));
ded9bf77
AH		 17768 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
17769}
17770
a6ebc39a
AH		 17771/* Define how to find the value returned by a function.
17772 VALTYPE is the data type of the value (as a tree).
17773 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17774 otherwise, FUNC is 0.
17775
17776 On the SPE, both FPs and vectors are returned in r3.
17777
17778 On RS/6000 an integer value is in r3 and a floating-point value is in
17779 fp1, unless -msoft-float. */
17780
17781rtx
17782rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
17783{
17784 enum machine_mode mode;
2a8fa26c 17785 unsigned int regno;
a6ebc39a 17786
594a51fe
SS		 17787 /* Special handling for structs in darwin64. */
17788 if (rs6000_darwin64_abi
17789 && TYPE_MODE (valtype) == BLKmode
0b5383eb
DJ		 17790 && TREE_CODE (valtype) == RECORD_TYPE
17791 && int_size_in_bytes (valtype) > 0)
594a51fe
SS		 17792 {
17793 CUMULATIVE_ARGS valcum;
17794 rtx valret;
17795
0b5383eb 17796 valcum.words = 0;
594a51fe
SS		 17797 valcum.fregno = FP_ARG_MIN_REG;
17798 valcum.vregno = ALTIVEC_ARG_MIN_REG;
0b5383eb
DJ		 17799 /* Do a trial code generation as if this were going to be passed as
17800 an argument; if any part goes in memory, we return NULL. */
17801 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
594a51fe
SS		 17802 if (valret)
17803 return valret;
17804 /* Otherwise fall through to standard ABI rules. */
17805 }
17806
0e67400a
FJ		 17807 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
17808 {
17809 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17810 return gen_rtx_PARALLEL (DImode,
17811 gen_rtvec (2,
17812 gen_rtx_EXPR_LIST (VOIDmode,
17813 gen_rtx_REG (SImode, GP_ARG_RETURN),
17814 const0_rtx),
17815 gen_rtx_EXPR_LIST (VOIDmode,
17816 gen_rtx_REG (SImode,
17817 GP_ARG_RETURN + 1),
17818 GEN_INT (4))));
17819 }
17820
a6ebc39a
AH		 17821 if ((INTEGRAL_TYPE_P (valtype)
17822 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
17823 || POINTER_TYPE_P (valtype))
b78d48dd 17824 mode = TARGET_32BIT ? SImode : DImode;
a6ebc39a
AH		 17825 else
17826 mode = TYPE_MODE (valtype);
17827
4ed78545 17828 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
2a8fa26c 17829 regno = FP_ARG_RETURN;
ded9bf77 17830 else if (TREE_CODE (valtype) == COMPLEX_TYPE
42ba5130 17831 && targetm.calls.split_complex_arg)
ded9bf77 17832 return rs6000_complex_function_value (mode);
44688022 17833 else if (TREE_CODE (valtype) == VECTOR_TYPE
d0b2079e 17834 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
23ba09f0 17835 && ALTIVEC_VECTOR_MODE (mode))
a6ebc39a 17836 regno = ALTIVEC_ARG_RETURN;
18f63bfa
AH		 17837 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17838 && (mode == DFmode || mode == DCmode))
17839 return spe_build_register_parallel (mode, GP_ARG_RETURN);
a6ebc39a
AH		 17840 else
17841 regno = GP_ARG_RETURN;
17842
17843 return gen_rtx_REG (mode, regno);
17844}
17845
ded9bf77
AH		 17846/* Define how to find the value returned by a library function
17847 assuming the value has mode MODE. */
17848rtx
17849rs6000_libcall_value (enum machine_mode mode)
17850{
17851 unsigned int regno;
17852
2e6c9641
FJ		 17853 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
17854 {
17855 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17856 return gen_rtx_PARALLEL (DImode,
17857 gen_rtvec (2,
17858 gen_rtx_EXPR_LIST (VOIDmode,
17859 gen_rtx_REG (SImode, GP_ARG_RETURN),
17860 const0_rtx),
17861 gen_rtx_EXPR_LIST (VOIDmode,
17862 gen_rtx_REG (SImode,
17863 GP_ARG_RETURN + 1),
17864 GEN_INT (4))));
17865 }
17866
ded9bf77
AH		 17867 if (GET_MODE_CLASS (mode) == MODE_FLOAT
17868 && TARGET_HARD_FLOAT && TARGET_FPRS)
17869 regno = FP_ARG_RETURN;
44688022
AM		 17870 else if (ALTIVEC_VECTOR_MODE (mode)
17871 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
ded9bf77 17872 regno = ALTIVEC_ARG_RETURN;
42ba5130 17873 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
ded9bf77 17874 return rs6000_complex_function_value (mode);
18f63bfa
AH		 17875 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17876 && (mode == DFmode || mode == DCmode))
17877 return spe_build_register_parallel (mode, GP_ARG_RETURN);
ded9bf77
AH		 17878 else
17879 regno = GP_ARG_RETURN;
17880
17881 return gen_rtx_REG (mode, regno);
17882}
17883
d1d0c603
JJ		 17884/* Define the offset between two registers, FROM to be eliminated and its
17885 replacement TO, at the start of a routine. */
17886HOST_WIDE_INT
17887rs6000_initial_elimination_offset (int from, int to)
17888{
17889 rs6000_stack_t *info = rs6000_stack_info ();
17890 HOST_WIDE_INT offset;
17891
17892 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17893 offset = info->push_p ? 0 : -info->total_size;
17894 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
17895 offset = info->total_size;
17896 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17897 offset = info->push_p ? info->total_size : 0;
17898 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
17899 offset = 0;
17900 else
37409796 17901 gcc_unreachable ();
d1d0c603
JJ		 17902
17903 return offset;
17904}
17905
58646b77 17906/* Return true if TYPE is a SPE or AltiVec opaque type. */
62e1dfcf 17907
c8e4f0e9 17908static bool
58646b77 17909rs6000_is_opaque_type (tree type)
62e1dfcf 17910{
58646b77 17911 return (type == opaque_V2SI_type_node
2abe3e28 17912 || type == opaque_V2SF_type_node
58646b77
PB		 17913 || type == opaque_p_V2SI_type_node
17914 || type == opaque_V4SI_type_node);
62e1dfcf
NC		 17915}
17916
96714395 17917static rtx
a2369ed3 17918rs6000_dwarf_register_span (rtx reg)
96714395
AH		 17919{
17920 unsigned regno;
17921
4d4cbc0e
AH		 17922 if (TARGET_SPE
17923 && (SPE_VECTOR_MODE (GET_MODE (reg))
17924 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
17925 ;
17926 else
96714395
AH		 17927 return NULL_RTX;
17928
17929 regno = REGNO (reg);
17930
17931 /* The duality of the SPE register size wreaks all kinds of havoc.
17932 This is a way of distinguishing r0 in 32-bits from r0 in
17933 64-bits. */
17934 return
17935 gen_rtx_PARALLEL (VOIDmode,
3bd104d1
AH		 17936 BYTES_BIG_ENDIAN
17937 ? gen_rtvec (2,
17938 gen_rtx_REG (SImode, regno + 1200),
17939 gen_rtx_REG (SImode, regno))
17940 : gen_rtvec (2,
17941 gen_rtx_REG (SImode, regno),
17942 gen_rtx_REG (SImode, regno + 1200)));
96714395
AH		 17943}
17944
93c9d1ba
AM		 17945/* Map internal gcc register numbers to DWARF2 register numbers. */
17946
17947unsigned int
17948rs6000_dbx_register_number (unsigned int regno)
17949{
17950 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
17951 return regno;
17952 if (regno == MQ_REGNO)
17953 return 100;
17954 if (regno == LINK_REGISTER_REGNUM)
17955 return 108;
17956 if (regno == COUNT_REGISTER_REGNUM)
17957 return 109;
17958 if (CR_REGNO_P (regno))
17959 return regno - CR0_REGNO + 86;
17960 if (regno == XER_REGNO)
17961 return 101;
17962 if (ALTIVEC_REGNO_P (regno))
17963 return regno - FIRST_ALTIVEC_REGNO + 1124;
17964 if (regno == VRSAVE_REGNO)
17965 return 356;
17966 if (regno == VSCR_REGNO)
17967 return 67;
17968 if (regno == SPE_ACC_REGNO)
17969 return 99;
17970 if (regno == SPEFSCR_REGNO)
17971 return 612;
17972 /* SPE high reg number. We get these values of regno from
17973 rs6000_dwarf_register_span. */
37409796
NS		 17974 gcc_assert (regno >= 1200 && regno < 1232);
17975 return regno;
93c9d1ba
AM		 17976}
17977
93f90be6 17978/* target hook eh_return_filter_mode */
f676971a 17979static enum machine_mode
93f90be6
FJ		 17980rs6000_eh_return_filter_mode (void)
17981{
17982 return TARGET_32BIT ? SImode : word_mode;
17983}
17984
f676971a
EC		 17985/* Target hook for vector_mode_supported_p. */
17986static bool
17987rs6000_vector_mode_supported_p (enum machine_mode mode)
17988{
17989
17990 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
17991 return true;
17992
17993 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
17994 return true;
17995
17996 else
17997 return false;
17998}
17999
4d3e6fae
FJ		 18000/* Target hook for invalid_arg_for_unprototyped_fn. */
18001static const char *
18002invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
18003{
18004 return (!rs6000_darwin64_abi
18005 && typelist == 0
18006 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
18007 && (funcdecl == NULL_TREE
18008 || (TREE_CODE (funcdecl) == FUNCTION_DECL
18009 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
18010 ? N_("AltiVec argument passed to unprototyped function")
18011 : NULL;
18012}
18013
17211ab5 18014#include "gt-rs6000.h"
Mirror of https://gcc.gnu.org/git/gcc.git