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Commit | Line | Data |
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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
f676971a | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
93c9d1ba | 3 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
cd3ce9b4 | 55 | #include "tree-gimple.h" |
1bc7c5b6 ZW |
56 | #if TARGET_XCOFF |
57 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
58 | #endif | |
93a27b7b ZW |
59 | #if TARGET_MACHO |
60 | #include "gstab.h" /* for N_SLINE */ | |
61 | #endif | |
9b30bae2 | 62 | |
7509c759 MM |
63 | #ifndef TARGET_NO_PROTOTYPE |
64 | #define TARGET_NO_PROTOTYPE 0 | |
65 | #endif | |
66 | ||
452a7d36 | 67 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
c4ad648e | 68 | #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1)) |
d744e06e | 69 | |
9878760c RK |
70 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
71 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
72 | ||
d1d0c603 JJ |
73 | /* Structure used to define the rs6000 stack */ |
74 | typedef struct rs6000_stack { | |
75 | int first_gp_reg_save; /* first callee saved GP register used */ | |
76 | int first_fp_reg_save; /* first callee saved FP register used */ | |
77 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
78 | int lr_save_p; /* true if the link reg needs to be saved */ | |
79 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
80 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
81 | int toc_save_p; /* true if the TOC needs to be saved */ | |
82 | int push_p; /* true if we need to allocate stack space */ | |
83 | int calls_p; /* true if the function makes any calls */ | |
c4ad648e | 84 | int world_save_p; /* true if we're saving *everything*: |
d62294f5 | 85 | r13-r31, cr, f14-f31, vrsave, v20-v31 */ |
d1d0c603 JJ |
86 | enum rs6000_abi abi; /* which ABI to use */ |
87 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
88 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
89 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
90 | int lr_save_offset; /* offset to save LR from initial SP */ | |
91 | int cr_save_offset; /* offset to save CR from initial SP */ | |
92 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
93 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
94 | int toc_save_offset; /* offset to save the TOC pointer */ | |
95 | int varargs_save_offset; /* offset to save the varargs registers */ | |
96 | int ehrd_offset; /* offset to EH return data */ | |
97 | int reg_size; /* register size (4 or 8) */ | |
98 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
99 | HOST_WIDE_INT vars_size; /* variable save area size */ | |
100 | int parm_size; /* outgoing parameter size */ | |
101 | int save_size; /* save area size */ | |
102 | int fixed_size; /* fixed size of stack frame */ | |
103 | int gp_size; /* size of saved GP registers */ | |
104 | int fp_size; /* size of saved FP registers */ | |
105 | int altivec_size; /* size of saved AltiVec registers */ | |
106 | int cr_size; /* size to hold CR if not in save_size */ | |
107 | int lr_size; /* size to hold LR if not in save_size */ | |
108 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ | |
109 | int altivec_padding_size; /* size of altivec alignment padding if | |
110 | not in save_size */ | |
111 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
112 | int spe_padding_size; | |
113 | int toc_size; /* size to hold TOC if not in save_size */ | |
114 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ | |
115 | int spe_64bit_regs_used; | |
116 | } rs6000_stack_t; | |
117 | ||
5248c961 RK |
118 | /* Target cpu type */ |
119 | ||
120 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
121 | struct rs6000_cpu_select rs6000_select[3] = |
122 | { | |
815cdc52 MM |
123 | /* switch name, tune arch */ |
124 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
125 | { (const char *)0, "-mcpu=", 1, 1 }, | |
126 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 127 | }; |
5248c961 | 128 | |
ec507f2d DE |
129 | /* Always emit branch hint bits. */ |
130 | static GTY(()) bool rs6000_always_hint; | |
131 | ||
132 | /* Schedule instructions for group formation. */ | |
133 | static GTY(()) bool rs6000_sched_groups; | |
134 | ||
f676971a | 135 | /* Support adjust_priority scheduler hook |
79ae11c4 DN |
136 | and -mprioritize-restricted-insns= option. */ |
137 | const char *rs6000_sched_restricted_insns_priority_str; | |
138 | int rs6000_sched_restricted_insns_priority; | |
139 | ||
569fa502 DN |
140 | /* Support for -msched-costly-dep option. */ |
141 | const char *rs6000_sched_costly_dep_str; | |
142 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
143 | ||
cbe26ab8 DN |
144 | /* Support for -minsert-sched-nops option. */ |
145 | const char *rs6000_sched_insert_nops_str; | |
146 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
147 | ||
7ccf35ed | 148 | /* Support targetm.vectorize.builtin_mask_for_load. */ |
13c62176 | 149 | static GTY(()) tree altivec_builtin_mask_for_load; |
7ccf35ed | 150 | /* Support targetm.vectorize.builtin_mask_for_store. */ |
13c62176 | 151 | static GTY(()) tree altivec_builtin_mask_for_store; |
7ccf35ed | 152 | |
6fa3f289 ZW |
153 | /* Size of long double */ |
154 | const char *rs6000_long_double_size_string; | |
155 | int rs6000_long_double_type_size; | |
156 | ||
157 | /* Whether -mabi=altivec has appeared */ | |
158 | int rs6000_altivec_abi; | |
159 | ||
08b57fb3 AH |
160 | /* Whether VRSAVE instructions should be generated. */ |
161 | int rs6000_altivec_vrsave; | |
162 | ||
163 | /* String from -mvrsave= option. */ | |
164 | const char *rs6000_altivec_vrsave_string; | |
165 | ||
a3170dc6 AH |
166 | /* Nonzero if we want SPE ABI extensions. */ |
167 | int rs6000_spe_abi; | |
168 | ||
169 | /* Whether isel instructions should be generated. */ | |
170 | int rs6000_isel; | |
171 | ||
993f19a8 AH |
172 | /* Whether SPE simd instructions should be generated. */ |
173 | int rs6000_spe; | |
174 | ||
5da702b1 AH |
175 | /* Nonzero if floating point operations are done in the GPRs. */ |
176 | int rs6000_float_gprs = 0; | |
177 | ||
594a51fe SS |
178 | /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */ |
179 | int rs6000_darwin64_abi; | |
180 | ||
5da702b1 AH |
181 | /* String from -mfloat-gprs=. */ |
182 | const char *rs6000_float_gprs_string; | |
a3170dc6 AH |
183 | |
184 | /* String from -misel=. */ | |
185 | const char *rs6000_isel_string; | |
186 | ||
993f19a8 AH |
187 | /* String from -mspe=. */ |
188 | const char *rs6000_spe_string; | |
189 | ||
a0ab749a | 190 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 191 | static GTY(()) int common_mode_defined; |
c81bebd7 | 192 | |
9878760c RK |
193 | /* Save information from a "cmpxx" operation until the branch or scc is |
194 | emitted. */ | |
9878760c RK |
195 | rtx rs6000_compare_op0, rs6000_compare_op1; |
196 | int rs6000_compare_fp_p; | |
874a0744 | 197 | |
874a0744 MM |
198 | /* Label number of label created for -mrelocatable, to call to so we can |
199 | get the address of the GOT section */ | |
200 | int rs6000_pic_labelno; | |
c81bebd7 | 201 | |
b91da81f | 202 | #ifdef USING_ELFOS_H |
c81bebd7 | 203 | /* Which abi to adhere to */ |
9739c90c | 204 | const char *rs6000_abi_name; |
d9407988 MM |
205 | |
206 | /* Semantics of the small data area */ | |
207 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
208 | ||
209 | /* Which small data model to use */ | |
815cdc52 | 210 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
211 | |
212 | /* Counter for labels which are to be placed in .fixup. */ | |
213 | int fixuplabelno = 0; | |
874a0744 | 214 | #endif |
4697a36c | 215 | |
c4501e62 JJ |
216 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
217 | int rs6000_tls_size = 32; | |
218 | const char *rs6000_tls_size_string; | |
219 | ||
b6c9286a MM |
220 | /* ABI enumeration available for subtarget to use. */ |
221 | enum rs6000_abi rs6000_current_abi; | |
222 | ||
0ac081f6 AH |
223 | /* ABI string from -mabi= option. */ |
224 | const char *rs6000_abi_string; | |
225 | ||
85b776df AM |
226 | /* Whether to use variant of AIX ABI for PowerPC64 Linux. */ |
227 | int dot_symbols; | |
228 | ||
38c1f2d7 | 229 | /* Debug flags */ |
815cdc52 | 230 | const char *rs6000_debug_name; |
38c1f2d7 MM |
231 | int rs6000_debug_stack; /* debug stack applications */ |
232 | int rs6000_debug_arg; /* debug argument handling */ | |
233 | ||
0d1fbc8c AH |
234 | /* Value is TRUE if register/mode pair is accepatable. */ |
235 | bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; | |
236 | ||
6035d635 | 237 | /* Opaque types. */ |
2abe3e28 | 238 | static GTY(()) tree opaque_V2SI_type_node; |
2abe3e28 | 239 | static GTY(()) tree opaque_V2SF_type_node; |
6035d635 | 240 | static GTY(()) tree opaque_p_V2SI_type_node; |
4a5eab38 PB |
241 | static GTY(()) tree V16QI_type_node; |
242 | static GTY(()) tree V2SI_type_node; | |
243 | static GTY(()) tree V2SF_type_node; | |
244 | static GTY(()) tree V4HI_type_node; | |
245 | static GTY(()) tree V4SI_type_node; | |
246 | static GTY(()) tree V4SF_type_node; | |
247 | static GTY(()) tree V8HI_type_node; | |
248 | static GTY(()) tree unsigned_V16QI_type_node; | |
249 | static GTY(()) tree unsigned_V8HI_type_node; | |
250 | static GTY(()) tree unsigned_V4SI_type_node; | |
8bb418a3 ZL |
251 | static GTY(()) tree bool_char_type_node; /* __bool char */ |
252 | static GTY(()) tree bool_short_type_node; /* __bool short */ | |
253 | static GTY(()) tree bool_int_type_node; /* __bool int */ | |
254 | static GTY(()) tree pixel_type_node; /* __pixel */ | |
255 | static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */ | |
256 | static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */ | |
257 | static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */ | |
258 | static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */ | |
259 | ||
260 | int rs6000_warn_altivec_long = 1; /* On by default. */ | |
261 | const char *rs6000_warn_altivec_long_switch; | |
262 | ||
57ac7be9 AM |
263 | const char *rs6000_traceback_name; |
264 | static enum { | |
265 | traceback_default = 0, | |
266 | traceback_none, | |
267 | traceback_part, | |
268 | traceback_full | |
269 | } rs6000_traceback; | |
270 | ||
38c1f2d7 MM |
271 | /* Flag to say the TOC is initialized */ |
272 | int toc_initialized; | |
9ebbca7d | 273 | char toc_label_name[10]; |
38c1f2d7 | 274 | |
9ebbca7d | 275 | /* Alias set for saves and restores from the rs6000 stack. */ |
f103e34d | 276 | static GTY(()) int rs6000_sr_alias_set; |
c8023011 | 277 | |
a5c76ee6 ZW |
278 | /* Call distance, overridden by -mlongcall and #pragma longcall(1). |
279 | The only place that looks at this is rs6000_set_default_type_attributes; | |
280 | everywhere else should rely on the presence or absence of a longcall | |
281 | attribute on the function declaration. */ | |
282 | int rs6000_default_long_calls; | |
283 | const char *rs6000_longcall_switch; | |
284 | ||
a3c9585f KH |
285 | /* Control alignment for fields within structures. */ |
286 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
287 | const char *rs6000_alignment_string; |
288 | int rs6000_alignment_flags; | |
289 | ||
a3170dc6 AH |
290 | struct builtin_description |
291 | { | |
292 | /* mask is not const because we're going to alter it below. This | |
293 | nonsense will go away when we rewrite the -march infrastructure | |
294 | to give us more target flag bits. */ | |
295 | unsigned int mask; | |
296 | const enum insn_code icode; | |
297 | const char *const name; | |
298 | const enum rs6000_builtins code; | |
299 | }; | |
8b897cfa RS |
300 | \f |
301 | /* Target cpu costs. */ | |
302 | ||
303 | struct processor_costs { | |
c4ad648e | 304 | const int mulsi; /* cost of SImode multiplication. */ |
8b897cfa RS |
305 | const int mulsi_const; /* cost of SImode multiplication by constant. */ |
306 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
c4ad648e AM |
307 | const int muldi; /* cost of DImode multiplication. */ |
308 | const int divsi; /* cost of SImode division. */ | |
309 | const int divdi; /* cost of DImode division. */ | |
310 | const int fp; /* cost of simple SFmode and DFmode insns. */ | |
311 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
312 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
313 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
8b897cfa RS |
314 | }; |
315 | ||
316 | const struct processor_costs *rs6000_cost; | |
317 | ||
318 | /* Processor costs (relative to an add) */ | |
319 | ||
320 | /* Instruction size costs on 32bit processors. */ | |
321 | static const | |
322 | struct processor_costs size32_cost = { | |
06a67bdd RS |
323 | COSTS_N_INSNS (1), /* mulsi */ |
324 | COSTS_N_INSNS (1), /* mulsi_const */ | |
325 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
326 | COSTS_N_INSNS (1), /* muldi */ | |
327 | COSTS_N_INSNS (1), /* divsi */ | |
328 | COSTS_N_INSNS (1), /* divdi */ | |
329 | COSTS_N_INSNS (1), /* fp */ | |
330 | COSTS_N_INSNS (1), /* dmul */ | |
331 | COSTS_N_INSNS (1), /* sdiv */ | |
332 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
333 | }; |
334 | ||
335 | /* Instruction size costs on 64bit processors. */ | |
336 | static const | |
337 | struct processor_costs size64_cost = { | |
06a67bdd RS |
338 | COSTS_N_INSNS (1), /* mulsi */ |
339 | COSTS_N_INSNS (1), /* mulsi_const */ | |
340 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
341 | COSTS_N_INSNS (1), /* muldi */ | |
342 | COSTS_N_INSNS (1), /* divsi */ | |
343 | COSTS_N_INSNS (1), /* divdi */ | |
344 | COSTS_N_INSNS (1), /* fp */ | |
345 | COSTS_N_INSNS (1), /* dmul */ | |
346 | COSTS_N_INSNS (1), /* sdiv */ | |
347 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
348 | }; |
349 | ||
350 | /* Instruction costs on RIOS1 processors. */ | |
351 | static const | |
352 | struct processor_costs rios1_cost = { | |
06a67bdd RS |
353 | COSTS_N_INSNS (5), /* mulsi */ |
354 | COSTS_N_INSNS (4), /* mulsi_const */ | |
355 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
356 | COSTS_N_INSNS (5), /* muldi */ | |
357 | COSTS_N_INSNS (19), /* divsi */ | |
358 | COSTS_N_INSNS (19), /* divdi */ | |
359 | COSTS_N_INSNS (2), /* fp */ | |
360 | COSTS_N_INSNS (2), /* dmul */ | |
361 | COSTS_N_INSNS (19), /* sdiv */ | |
362 | COSTS_N_INSNS (19), /* ddiv */ | |
8b897cfa RS |
363 | }; |
364 | ||
365 | /* Instruction costs on RIOS2 processors. */ | |
366 | static const | |
367 | struct processor_costs rios2_cost = { | |
06a67bdd RS |
368 | COSTS_N_INSNS (2), /* mulsi */ |
369 | COSTS_N_INSNS (2), /* mulsi_const */ | |
370 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
371 | COSTS_N_INSNS (2), /* muldi */ | |
372 | COSTS_N_INSNS (13), /* divsi */ | |
373 | COSTS_N_INSNS (13), /* divdi */ | |
374 | COSTS_N_INSNS (2), /* fp */ | |
375 | COSTS_N_INSNS (2), /* dmul */ | |
376 | COSTS_N_INSNS (17), /* sdiv */ | |
377 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
378 | }; |
379 | ||
380 | /* Instruction costs on RS64A processors. */ | |
381 | static const | |
382 | struct processor_costs rs64a_cost = { | |
06a67bdd RS |
383 | COSTS_N_INSNS (20), /* mulsi */ |
384 | COSTS_N_INSNS (12), /* mulsi_const */ | |
385 | COSTS_N_INSNS (8), /* mulsi_const9 */ | |
386 | COSTS_N_INSNS (34), /* muldi */ | |
387 | COSTS_N_INSNS (65), /* divsi */ | |
388 | COSTS_N_INSNS (67), /* divdi */ | |
389 | COSTS_N_INSNS (4), /* fp */ | |
390 | COSTS_N_INSNS (4), /* dmul */ | |
391 | COSTS_N_INSNS (31), /* sdiv */ | |
392 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
393 | }; |
394 | ||
395 | /* Instruction costs on MPCCORE processors. */ | |
396 | static const | |
397 | struct processor_costs mpccore_cost = { | |
06a67bdd RS |
398 | COSTS_N_INSNS (2), /* mulsi */ |
399 | COSTS_N_INSNS (2), /* mulsi_const */ | |
400 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
401 | COSTS_N_INSNS (2), /* muldi */ | |
402 | COSTS_N_INSNS (6), /* divsi */ | |
403 | COSTS_N_INSNS (6), /* divdi */ | |
404 | COSTS_N_INSNS (4), /* fp */ | |
405 | COSTS_N_INSNS (5), /* dmul */ | |
406 | COSTS_N_INSNS (10), /* sdiv */ | |
407 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
408 | }; |
409 | ||
410 | /* Instruction costs on PPC403 processors. */ | |
411 | static const | |
412 | struct processor_costs ppc403_cost = { | |
06a67bdd RS |
413 | COSTS_N_INSNS (4), /* mulsi */ |
414 | COSTS_N_INSNS (4), /* mulsi_const */ | |
415 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
416 | COSTS_N_INSNS (4), /* muldi */ | |
417 | COSTS_N_INSNS (33), /* divsi */ | |
418 | COSTS_N_INSNS (33), /* divdi */ | |
419 | COSTS_N_INSNS (11), /* fp */ | |
420 | COSTS_N_INSNS (11), /* dmul */ | |
421 | COSTS_N_INSNS (11), /* sdiv */ | |
422 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
423 | }; |
424 | ||
425 | /* Instruction costs on PPC405 processors. */ | |
426 | static const | |
427 | struct processor_costs ppc405_cost = { | |
06a67bdd RS |
428 | COSTS_N_INSNS (5), /* mulsi */ |
429 | COSTS_N_INSNS (4), /* mulsi_const */ | |
430 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
431 | COSTS_N_INSNS (5), /* muldi */ | |
432 | COSTS_N_INSNS (35), /* divsi */ | |
433 | COSTS_N_INSNS (35), /* divdi */ | |
434 | COSTS_N_INSNS (11), /* fp */ | |
435 | COSTS_N_INSNS (11), /* dmul */ | |
436 | COSTS_N_INSNS (11), /* sdiv */ | |
437 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
438 | }; |
439 | ||
440 | /* Instruction costs on PPC440 processors. */ | |
441 | static const | |
442 | struct processor_costs ppc440_cost = { | |
06a67bdd RS |
443 | COSTS_N_INSNS (3), /* mulsi */ |
444 | COSTS_N_INSNS (2), /* mulsi_const */ | |
445 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
446 | COSTS_N_INSNS (3), /* muldi */ | |
447 | COSTS_N_INSNS (34), /* divsi */ | |
448 | COSTS_N_INSNS (34), /* divdi */ | |
449 | COSTS_N_INSNS (5), /* fp */ | |
450 | COSTS_N_INSNS (5), /* dmul */ | |
451 | COSTS_N_INSNS (19), /* sdiv */ | |
452 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
453 | }; |
454 | ||
455 | /* Instruction costs on PPC601 processors. */ | |
456 | static const | |
457 | struct processor_costs ppc601_cost = { | |
06a67bdd RS |
458 | COSTS_N_INSNS (5), /* mulsi */ |
459 | COSTS_N_INSNS (5), /* mulsi_const */ | |
460 | COSTS_N_INSNS (5), /* mulsi_const9 */ | |
461 | COSTS_N_INSNS (5), /* muldi */ | |
462 | COSTS_N_INSNS (36), /* divsi */ | |
463 | COSTS_N_INSNS (36), /* divdi */ | |
464 | COSTS_N_INSNS (4), /* fp */ | |
465 | COSTS_N_INSNS (5), /* dmul */ | |
466 | COSTS_N_INSNS (17), /* sdiv */ | |
467 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
468 | }; |
469 | ||
470 | /* Instruction costs on PPC603 processors. */ | |
471 | static const | |
472 | struct processor_costs ppc603_cost = { | |
06a67bdd RS |
473 | COSTS_N_INSNS (5), /* mulsi */ |
474 | COSTS_N_INSNS (3), /* mulsi_const */ | |
475 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
476 | COSTS_N_INSNS (5), /* muldi */ | |
477 | COSTS_N_INSNS (37), /* divsi */ | |
478 | COSTS_N_INSNS (37), /* divdi */ | |
479 | COSTS_N_INSNS (3), /* fp */ | |
480 | COSTS_N_INSNS (4), /* dmul */ | |
481 | COSTS_N_INSNS (18), /* sdiv */ | |
482 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
483 | }; |
484 | ||
485 | /* Instruction costs on PPC604 processors. */ | |
486 | static const | |
487 | struct processor_costs ppc604_cost = { | |
06a67bdd RS |
488 | COSTS_N_INSNS (4), /* mulsi */ |
489 | COSTS_N_INSNS (4), /* mulsi_const */ | |
490 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
491 | COSTS_N_INSNS (4), /* muldi */ | |
492 | COSTS_N_INSNS (20), /* divsi */ | |
493 | COSTS_N_INSNS (20), /* divdi */ | |
494 | COSTS_N_INSNS (3), /* fp */ | |
495 | COSTS_N_INSNS (3), /* dmul */ | |
496 | COSTS_N_INSNS (18), /* sdiv */ | |
497 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
498 | }; |
499 | ||
500 | /* Instruction costs on PPC604e processors. */ | |
501 | static const | |
502 | struct processor_costs ppc604e_cost = { | |
06a67bdd RS |
503 | COSTS_N_INSNS (2), /* mulsi */ |
504 | COSTS_N_INSNS (2), /* mulsi_const */ | |
505 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
506 | COSTS_N_INSNS (2), /* muldi */ | |
507 | COSTS_N_INSNS (20), /* divsi */ | |
508 | COSTS_N_INSNS (20), /* divdi */ | |
509 | COSTS_N_INSNS (3), /* fp */ | |
510 | COSTS_N_INSNS (3), /* dmul */ | |
511 | COSTS_N_INSNS (18), /* sdiv */ | |
512 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
513 | }; |
514 | ||
f0517163 | 515 | /* Instruction costs on PPC620 processors. */ |
8b897cfa RS |
516 | static const |
517 | struct processor_costs ppc620_cost = { | |
06a67bdd RS |
518 | COSTS_N_INSNS (5), /* mulsi */ |
519 | COSTS_N_INSNS (4), /* mulsi_const */ | |
520 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
521 | COSTS_N_INSNS (7), /* muldi */ | |
522 | COSTS_N_INSNS (21), /* divsi */ | |
523 | COSTS_N_INSNS (37), /* divdi */ | |
524 | COSTS_N_INSNS (3), /* fp */ | |
525 | COSTS_N_INSNS (3), /* dmul */ | |
526 | COSTS_N_INSNS (18), /* sdiv */ | |
527 | COSTS_N_INSNS (32), /* ddiv */ | |
f0517163 RS |
528 | }; |
529 | ||
530 | /* Instruction costs on PPC630 processors. */ | |
531 | static const | |
532 | struct processor_costs ppc630_cost = { | |
06a67bdd RS |
533 | COSTS_N_INSNS (5), /* mulsi */ |
534 | COSTS_N_INSNS (4), /* mulsi_const */ | |
535 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
536 | COSTS_N_INSNS (7), /* muldi */ | |
537 | COSTS_N_INSNS (21), /* divsi */ | |
538 | COSTS_N_INSNS (37), /* divdi */ | |
539 | COSTS_N_INSNS (3), /* fp */ | |
540 | COSTS_N_INSNS (3), /* dmul */ | |
541 | COSTS_N_INSNS (17), /* sdiv */ | |
542 | COSTS_N_INSNS (21), /* ddiv */ | |
8b897cfa RS |
543 | }; |
544 | ||
545 | /* Instruction costs on PPC750 and PPC7400 processors. */ | |
546 | static const | |
547 | struct processor_costs ppc750_cost = { | |
06a67bdd RS |
548 | COSTS_N_INSNS (5), /* mulsi */ |
549 | COSTS_N_INSNS (3), /* mulsi_const */ | |
550 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
551 | COSTS_N_INSNS (5), /* muldi */ | |
552 | COSTS_N_INSNS (17), /* divsi */ | |
553 | COSTS_N_INSNS (17), /* divdi */ | |
554 | COSTS_N_INSNS (3), /* fp */ | |
555 | COSTS_N_INSNS (3), /* dmul */ | |
556 | COSTS_N_INSNS (17), /* sdiv */ | |
557 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
558 | }; |
559 | ||
560 | /* Instruction costs on PPC7450 processors. */ | |
561 | static const | |
562 | struct processor_costs ppc7450_cost = { | |
06a67bdd RS |
563 | COSTS_N_INSNS (4), /* mulsi */ |
564 | COSTS_N_INSNS (3), /* mulsi_const */ | |
565 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
566 | COSTS_N_INSNS (4), /* muldi */ | |
567 | COSTS_N_INSNS (23), /* divsi */ | |
568 | COSTS_N_INSNS (23), /* divdi */ | |
569 | COSTS_N_INSNS (5), /* fp */ | |
570 | COSTS_N_INSNS (5), /* dmul */ | |
571 | COSTS_N_INSNS (21), /* sdiv */ | |
572 | COSTS_N_INSNS (35), /* ddiv */ | |
8b897cfa | 573 | }; |
a3170dc6 | 574 | |
8b897cfa RS |
575 | /* Instruction costs on PPC8540 processors. */ |
576 | static const | |
577 | struct processor_costs ppc8540_cost = { | |
06a67bdd RS |
578 | COSTS_N_INSNS (4), /* mulsi */ |
579 | COSTS_N_INSNS (4), /* mulsi_const */ | |
580 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
581 | COSTS_N_INSNS (4), /* muldi */ | |
582 | COSTS_N_INSNS (19), /* divsi */ | |
583 | COSTS_N_INSNS (19), /* divdi */ | |
584 | COSTS_N_INSNS (4), /* fp */ | |
585 | COSTS_N_INSNS (4), /* dmul */ | |
586 | COSTS_N_INSNS (29), /* sdiv */ | |
587 | COSTS_N_INSNS (29), /* ddiv */ | |
8b897cfa RS |
588 | }; |
589 | ||
590 | /* Instruction costs on POWER4 and POWER5 processors. */ | |
591 | static const | |
592 | struct processor_costs power4_cost = { | |
06a67bdd RS |
593 | COSTS_N_INSNS (3), /* mulsi */ |
594 | COSTS_N_INSNS (2), /* mulsi_const */ | |
595 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
596 | COSTS_N_INSNS (4), /* muldi */ | |
597 | COSTS_N_INSNS (18), /* divsi */ | |
598 | COSTS_N_INSNS (34), /* divdi */ | |
599 | COSTS_N_INSNS (3), /* fp */ | |
600 | COSTS_N_INSNS (3), /* dmul */ | |
601 | COSTS_N_INSNS (17), /* sdiv */ | |
602 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
603 | }; |
604 | ||
605 | \f | |
a2369ed3 DJ |
606 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
607 | static int num_insns_constant_wide (HOST_WIDE_INT); | |
608 | static void validate_condition_mode (enum rtx_code, enum machine_mode); | |
609 | static rtx rs6000_generate_compare (enum rtx_code); | |
610 | static void rs6000_maybe_dead (rtx); | |
611 | static void rs6000_emit_stack_tie (void); | |
612 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
613 | static rtx spe_synthesize_frame_save (rtx); | |
614 | static bool spe_func_has_64bit_regs_p (void); | |
b20a9cca | 615 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 616 | int, HOST_WIDE_INT); |
a2369ed3 DJ |
617 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
618 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); | |
619 | static unsigned rs6000_hash_constant (rtx); | |
620 | static unsigned toc_hash_function (const void *); | |
621 | static int toc_hash_eq (const void *, const void *); | |
622 | static int constant_pool_expr_1 (rtx, int *, int *); | |
623 | static bool constant_pool_expr_p (rtx); | |
624 | static bool toc_relative_expr_p (rtx); | |
625 | static bool legitimate_small_data_p (enum machine_mode, rtx); | |
a2369ed3 DJ |
626 | static bool legitimate_indexed_address_p (rtx, int); |
627 | static bool legitimate_indirect_address_p (rtx, int); | |
4c81e946 | 628 | static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode); |
a2369ed3 DJ |
629 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
630 | static struct machine_function * rs6000_init_machine_status (void); | |
631 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
5add3202 | 632 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 633 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 634 | #endif |
a2369ed3 DJ |
635 | static int rs6000_ra_ever_killed (void); |
636 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
8bb418a3 | 637 | static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); |
76d2b81d | 638 | static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); |
f18eca82 | 639 | static const char *rs6000_mangle_fundamental_type (tree); |
b86fe7b4 | 640 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 DJ |
641 | static void rs6000_set_default_type_attributes (tree); |
642 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); | |
643 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
644 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
645 | tree); | |
a2369ed3 | 646 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
c6e8c921 | 647 | static bool rs6000_return_in_memory (tree, tree); |
a2369ed3 | 648 | static void rs6000_file_start (void); |
7c262518 | 649 | #if TARGET_ELF |
a2369ed3 DJ |
650 | static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); |
651 | static void rs6000_elf_asm_out_constructor (rtx, int); | |
652 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
653 | static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); | |
654 | static void rs6000_elf_unique_section (tree, int); | |
655 | static void rs6000_elf_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 656 | unsigned HOST_WIDE_INT); |
a56d7372 | 657 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 658 | ATTRIBUTE_UNUSED; |
a2369ed3 | 659 | static bool rs6000_elf_in_small_data_p (tree); |
7c262518 | 660 | #endif |
cbaaba19 | 661 | #if TARGET_XCOFF |
a2369ed3 | 662 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
8210e4c4 | 663 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree); |
a2369ed3 DJ |
664 | static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT); |
665 | static void rs6000_xcoff_unique_section (tree, int); | |
666 | static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 667 | unsigned HOST_WIDE_INT); |
a2369ed3 DJ |
668 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
669 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
670 | static void rs6000_xcoff_file_start (void); | |
671 | static void rs6000_xcoff_file_end (void); | |
f1384257 AM |
672 | #endif |
673 | #if TARGET_MACHO | |
a2369ed3 | 674 | static bool rs6000_binds_local_p (tree); |
f1384257 | 675 | #endif |
a2369ed3 DJ |
676 | static int rs6000_variable_issue (FILE *, int, rtx, int); |
677 | static bool rs6000_rtx_costs (rtx, int, int, int *); | |
678 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); | |
cbe26ab8 | 679 | static bool is_microcoded_insn (rtx); |
79ae11c4 | 680 | static int is_dispatch_slot_restricted (rtx); |
cbe26ab8 DN |
681 | static bool is_cracked_insn (rtx); |
682 | static bool is_branch_slot_insn (rtx); | |
a2369ed3 DJ |
683 | static int rs6000_adjust_priority (rtx, int); |
684 | static int rs6000_issue_rate (void); | |
569fa502 | 685 | static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); |
cbe26ab8 DN |
686 | static rtx get_next_active_insn (rtx, rtx); |
687 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
688 | static bool is_costly_group (rtx *, rtx); | |
689 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
690 | static int redefine_groups (FILE *, int, rtx, rtx); | |
691 | static int pad_groups (FILE *, int, rtx, rtx); | |
692 | static void rs6000_sched_finish (FILE *, int); | |
a2369ed3 | 693 | static int rs6000_use_sched_lookahead (void); |
7ccf35ed DN |
694 | static tree rs6000_builtin_mask_for_load (void); |
695 | static tree rs6000_builtin_mask_for_store (void); | |
a2369ed3 DJ |
696 | |
697 | static void rs6000_init_builtins (void); | |
698 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
699 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
700 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
701 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
702 | static void altivec_init_builtins (void); | |
703 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 704 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 705 | |
b20a9cca AM |
706 | static void enable_mask_for_builtins (struct builtin_description *, int, |
707 | enum rs6000_builtins, | |
708 | enum rs6000_builtins); | |
7c62e993 | 709 | static tree build_opaque_vector_type (tree, int); |
a2369ed3 DJ |
710 | static void spe_init_builtins (void); |
711 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
61bea3b0 | 712 | static rtx spe_expand_stv_builtin (enum insn_code, tree); |
a2369ed3 DJ |
713 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); |
714 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
715 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
716 | static rs6000_stack_t *rs6000_stack_info (void); |
717 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
718 | |
719 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
720 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
721 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
722 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
723 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
f676971a | 724 | static rtx altivec_expand_predicate_builtin (enum insn_code, |
c4ad648e | 725 | const char *, tree, rtx); |
b4a62fa0 | 726 | static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); |
a2369ed3 DJ |
727 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
728 | static void rs6000_parse_abi_options (void); | |
729 | static void rs6000_parse_alignment_option (void); | |
730 | static void rs6000_parse_tls_size_option (void); | |
5da702b1 | 731 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
4d4cbc0e | 732 | static void rs6000_parse_float_gprs_option (void); |
a2369ed3 DJ |
733 | static int first_altivec_reg_to_save (void); |
734 | static unsigned int compute_vrsave_mask (void); | |
d62294f5 | 735 | static void compute_save_world_info(rs6000_stack_t *info_ptr); |
a2369ed3 DJ |
736 | static void is_altivec_return_reg (rtx, void *); |
737 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
738 | int easy_vector_constant (rtx, enum machine_mode); | |
739 | static int easy_vector_same (rtx, enum machine_mode); | |
452a7d36 | 740 | static int easy_vector_splat_const (int, enum machine_mode); |
a2369ed3 DJ |
741 | static bool is_ev64_opaque_type (tree); |
742 | static rtx rs6000_dwarf_register_span (rtx); | |
743 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); | |
744 | static rtx rs6000_tls_get_addr (void); | |
745 | static rtx rs6000_got_sym (void); | |
746 | static inline int rs6000_tls_symbol_ref_1 (rtx *, void *); | |
747 | static const char *rs6000_get_some_local_dynamic_name (void); | |
748 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 749 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 750 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 751 | enum machine_mode, tree); |
594a51fe SS |
752 | static rtx rs6000_darwin64_function_arg (CUMULATIVE_ARGS *, |
753 | enum machine_mode, tree, int); | |
ec6376ab | 754 | static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); |
b1917422 | 755 | static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); |
c6e8c921 GK |
756 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
757 | enum machine_mode, tree, | |
758 | int *, int); | |
8cd5a4e0 RH |
759 | static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
760 | tree, bool); | |
efdba735 SH |
761 | #if TARGET_MACHO |
762 | static void macho_branch_islands (void); | |
763 | static void add_compiler_branch_island (tree, tree, int); | |
764 | static int no_previous_def (tree function_name); | |
765 | static tree get_prev_label (tree function_name); | |
c4e18b1c | 766 | static void rs6000_darwin_file_start (void); |
efdba735 SH |
767 | #endif |
768 | ||
c35d187f | 769 | static tree rs6000_build_builtin_va_list (void); |
23a60a04 | 770 | static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); |
fe984136 | 771 | static bool rs6000_must_pass_in_stack (enum machine_mode, tree); |
f676971a | 772 | static bool rs6000_vector_mode_supported_p (enum machine_mode); |
94ff898d | 773 | static int get_vec_cmp_insn (enum rtx_code, enum machine_mode, |
21213b4c | 774 | enum machine_mode); |
94ff898d | 775 | static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx, |
21213b4c DP |
776 | enum machine_mode); |
777 | static int get_vsel_insn (enum machine_mode); | |
778 | static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx); | |
17211ab5 | 779 | |
21213b4c DP |
780 | |
781 | const int INSN_NOT_AVAILABLE = -1; | |
93f90be6 FJ |
782 | static enum machine_mode rs6000_eh_return_filter_mode (void); |
783 | ||
17211ab5 GK |
784 | /* Hash table stuff for keeping track of TOC entries. */ |
785 | ||
786 | struct toc_hash_struct GTY(()) | |
787 | { | |
788 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
789 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
790 | rtx key; | |
791 | enum machine_mode key_mode; | |
792 | int labelno; | |
793 | }; | |
794 | ||
795 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
796 | \f |
797 | /* Default register names. */ | |
798 | char rs6000_reg_names[][8] = | |
799 | { | |
802a0058 MM |
800 | "0", "1", "2", "3", "4", "5", "6", "7", |
801 | "8", "9", "10", "11", "12", "13", "14", "15", | |
802 | "16", "17", "18", "19", "20", "21", "22", "23", | |
803 | "24", "25", "26", "27", "28", "29", "30", "31", | |
804 | "0", "1", "2", "3", "4", "5", "6", "7", | |
805 | "8", "9", "10", "11", "12", "13", "14", "15", | |
806 | "16", "17", "18", "19", "20", "21", "22", "23", | |
807 | "24", "25", "26", "27", "28", "29", "30", "31", | |
808 | "mq", "lr", "ctr","ap", | |
809 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
810 | "xer", |
811 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
812 | "0", "1", "2", "3", "4", "5", "6", "7", |
813 | "8", "9", "10", "11", "12", "13", "14", "15", | |
814 | "16", "17", "18", "19", "20", "21", "22", "23", | |
815 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
816 | "vrsave", "vscr", |
817 | /* SPE registers. */ | |
818 | "spe_acc", "spefscr" | |
c81bebd7 MM |
819 | }; |
820 | ||
821 | #ifdef TARGET_REGNAMES | |
8b60264b | 822 | static const char alt_reg_names[][8] = |
c81bebd7 | 823 | { |
802a0058 MM |
824 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
825 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
826 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
827 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
828 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
829 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
830 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
831 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
832 | "mq", "lr", "ctr", "ap", | |
833 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 834 | "xer", |
59a4c851 | 835 | /* AltiVec registers. */ |
0ac081f6 | 836 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
837 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
838 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
839 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
840 | "vrsave", "vscr", | |
841 | /* SPE registers. */ | |
842 | "spe_acc", "spefscr" | |
c81bebd7 MM |
843 | }; |
844 | #endif | |
9878760c | 845 | \f |
daf11973 MM |
846 | #ifndef MASK_STRICT_ALIGN |
847 | #define MASK_STRICT_ALIGN 0 | |
848 | #endif | |
ffcfcb5f AM |
849 | #ifndef TARGET_PROFILE_KERNEL |
850 | #define TARGET_PROFILE_KERNEL 0 | |
851 | #endif | |
3961e8fe RH |
852 | |
853 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
854 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
c4501e62 JJ |
855 | |
856 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ | |
857 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
858 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
672a6f42 NB |
859 | \f |
860 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
861 | #undef TARGET_ATTRIBUTE_TABLE |
862 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
863 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
864 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 865 | |
301d03af RS |
866 | #undef TARGET_ASM_ALIGNED_DI_OP |
867 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
868 | ||
869 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
870 | for non-ELF systems. */ | |
871 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 872 | #if TARGET_XCOFF |
ae6c1efd | 873 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
874 | 64-bit targets. */ |
875 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
876 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
877 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
878 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
879 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
880 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
881 | #else | |
882 | /* For Darwin. */ | |
883 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
884 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
885 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
886 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
49bd1d27 SS |
887 | #undef TARGET_ASM_UNALIGNED_DI_OP |
888 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t" | |
889 | #undef TARGET_ASM_ALIGNED_DI_OP | |
890 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
301d03af RS |
891 | #endif |
892 | #endif | |
893 | ||
894 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
895 | in 64-bit code. */ | |
896 | #undef TARGET_ASM_INTEGER | |
897 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
898 | ||
93638d7a AM |
899 | #ifdef HAVE_GAS_HIDDEN |
900 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
901 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
902 | #endif | |
903 | ||
c4501e62 JJ |
904 | #undef TARGET_HAVE_TLS |
905 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
906 | ||
907 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
908 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p | |
909 | ||
08c148a8 NB |
910 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
911 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
912 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
913 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
914 | ||
b54cf83a DE |
915 | #undef TARGET_SCHED_VARIABLE_ISSUE |
916 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
917 | ||
c237e94a ZW |
918 | #undef TARGET_SCHED_ISSUE_RATE |
919 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
920 | #undef TARGET_SCHED_ADJUST_COST | |
921 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
922 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
923 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
f676971a | 924 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
569fa502 | 925 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence |
cbe26ab8 DN |
926 | #undef TARGET_SCHED_FINISH |
927 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
c237e94a | 928 | |
be12c2b0 VM |
929 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
930 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
931 | ||
7ccf35ed DN |
932 | #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD |
933 | #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load | |
934 | ||
935 | #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE | |
936 | #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE rs6000_builtin_mask_for_store | |
937 | ||
0ac081f6 AH |
938 | #undef TARGET_INIT_BUILTINS |
939 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
940 | ||
941 | #undef TARGET_EXPAND_BUILTIN | |
942 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
943 | ||
f18eca82 ZL |
944 | #undef TARGET_MANGLE_FUNDAMENTAL_TYPE |
945 | #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type | |
946 | ||
c15c90bb ZW |
947 | #undef TARGET_INIT_LIBFUNCS |
948 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
949 | ||
f1384257 | 950 | #if TARGET_MACHO |
0e5dbd9b DE |
951 | #undef TARGET_BINDS_LOCAL_P |
952 | #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p | |
f1384257 | 953 | #endif |
0e5dbd9b | 954 | |
3961e8fe RH |
955 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
956 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
957 | ||
3961e8fe | 958 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 959 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 960 | |
4977bab6 ZW |
961 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
962 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
963 | ||
3c50106f RH |
964 | #undef TARGET_RTX_COSTS |
965 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
966 | #undef TARGET_ADDRESS_COST |
967 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 968 | |
c8e4f0e9 AH |
969 | #undef TARGET_VECTOR_OPAQUE_P |
970 | #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type | |
62e1dfcf | 971 | |
96714395 AH |
972 | #undef TARGET_DWARF_REGISTER_SPAN |
973 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
974 | ||
c6e8c921 GK |
975 | /* On rs6000, function arguments are promoted, as are function return |
976 | values. */ | |
977 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
978 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
979 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
980 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
981 | ||
c6e8c921 GK |
982 | #undef TARGET_RETURN_IN_MEMORY |
983 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
984 | ||
985 | #undef TARGET_SETUP_INCOMING_VARARGS | |
986 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
987 | ||
988 | /* Always strict argument naming on rs6000. */ | |
989 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
990 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
991 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
992 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
42ba5130 RH |
993 | #undef TARGET_SPLIT_COMPLEX_ARG |
994 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true | |
fe984136 RH |
995 | #undef TARGET_MUST_PASS_IN_STACK |
996 | #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack | |
8cd5a4e0 RH |
997 | #undef TARGET_PASS_BY_REFERENCE |
998 | #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference | |
c6e8c921 | 999 | |
c35d187f RH |
1000 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
1001 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
1002 | ||
cd3ce9b4 JM |
1003 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
1004 | #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg | |
1005 | ||
93f90be6 FJ |
1006 | #undef TARGET_EH_RETURN_FILTER_MODE |
1007 | #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode | |
1008 | ||
f676971a EC |
1009 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
1010 | #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p | |
1011 | ||
f6897b10 | 1012 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 1013 | \f |
0d1fbc8c AH |
1014 | |
1015 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
1016 | MODE. */ | |
1017 | static int | |
1018 | rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
1019 | { | |
1020 | /* The GPRs can hold any mode, but values bigger than one register | |
1021 | cannot go past R31. */ | |
1022 | if (INT_REGNO_P (regno)) | |
1023 | return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); | |
1024 | ||
1025 | /* The float registers can only hold floating modes and DImode. */ | |
1026 | if (FP_REGNO_P (regno)) | |
1027 | return | |
1028 | (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1029 | && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) | |
1030 | || (GET_MODE_CLASS (mode) == MODE_INT | |
1031 | && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD); | |
1032 | ||
1033 | /* The CR register can only hold CC modes. */ | |
1034 | if (CR_REGNO_P (regno)) | |
1035 | return GET_MODE_CLASS (mode) == MODE_CC; | |
1036 | ||
1037 | if (XER_REGNO_P (regno)) | |
1038 | return mode == PSImode; | |
1039 | ||
1040 | /* AltiVec only in AldyVec registers. */ | |
1041 | if (ALTIVEC_REGNO_P (regno)) | |
1042 | return ALTIVEC_VECTOR_MODE (mode); | |
1043 | ||
1044 | /* ...but GPRs can hold SIMD data on the SPE in one register. */ | |
1045 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
1046 | return 1; | |
1047 | ||
1048 | /* We cannot put TImode anywhere except general register and it must be | |
1049 | able to fit within the register set. */ | |
1050 | ||
1051 | return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; | |
1052 | } | |
1053 | ||
1054 | /* Initialize rs6000_hard_regno_mode_ok_p table. */ | |
1055 | static void | |
1056 | rs6000_init_hard_regno_mode_ok (void) | |
1057 | { | |
1058 | int r, m; | |
1059 | ||
1060 | for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) | |
1061 | for (m = 0; m < NUM_MACHINE_MODES; ++m) | |
1062 | if (rs6000_hard_regno_mode_ok (r, m)) | |
1063 | rs6000_hard_regno_mode_ok_p[m][r] = true; | |
1064 | } | |
1065 | ||
c1e55850 GK |
1066 | /* If not otherwise specified by a target, make 'long double' equivalent to |
1067 | 'double'. */ | |
1068 | ||
1069 | #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE | |
1070 | #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 | |
1071 | #endif | |
1072 | ||
5248c961 RK |
1073 | /* Override command line options. Mostly we process the processor |
1074 | type and sometimes adjust other TARGET_ options. */ | |
1075 | ||
1076 | void | |
d779d0dc | 1077 | rs6000_override_options (const char *default_cpu) |
5248c961 | 1078 | { |
c4d38ccb | 1079 | size_t i, j; |
8e3f41e7 | 1080 | struct rs6000_cpu_select *ptr; |
66188a7e | 1081 | int set_masks; |
5248c961 | 1082 | |
66188a7e | 1083 | /* Simplifications for entries below. */ |
85638c0d | 1084 | |
66188a7e GK |
1085 | enum { |
1086 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
1087 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
1088 | }; | |
85638c0d | 1089 | |
66188a7e GK |
1090 | /* This table occasionally claims that a processor does not support |
1091 | a particular feature even though it does, but the feature is slower | |
1092 | than the alternative. Thus, it shouldn't be relied on as a | |
f676971a | 1093 | complete description of the processor's support. |
66188a7e GK |
1094 | |
1095 | Please keep this list in order, and don't forget to update the | |
1096 | documentation in invoke.texi when adding a new processor or | |
1097 | flag. */ | |
5248c961 RK |
1098 | static struct ptt |
1099 | { | |
8b60264b KG |
1100 | const char *const name; /* Canonical processor name. */ |
1101 | const enum processor_type processor; /* Processor type enum value. */ | |
1102 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 1103 | } const processor_target_table[] |
66188a7e | 1104 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 1105 | {"403", PROCESSOR_PPC403, |
66188a7e GK |
1106 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
1107 | {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1108 | {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK}, | |
1109 | {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1110 | {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK}, | |
1111 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, | |
5248c961 | 1112 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
1113 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
1114 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1115 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1116 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1117 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1118 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
1119 | {"620", PROCESSOR_PPC620, |
1120 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1121 | {"630", PROCESSOR_PPC630, | |
1122 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
1123 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
1124 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
1125 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
1126 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1127 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1128 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1129 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1130 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
4d4cbc0e AH |
1131 | /* 8548 has a dummy entry for now. */ |
1132 | {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
66188a7e | 1133 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
7177e720 | 1134 | {"970", PROCESSOR_POWER4, |
66188a7e GK |
1135 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1136 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, | |
1137 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1138 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1139 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 1140 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
1141 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1142 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1143 | {"power2", PROCESSOR_POWER, | |
1144 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
1145 | {"power3", PROCESSOR_PPC630, |
1146 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1147 | {"power4", PROCESSOR_POWER4, | |
fc091c8e | 1148 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
ec507f2d | 1149 | {"power5", PROCESSOR_POWER5, |
fc091c8e | 1150 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
66188a7e GK |
1151 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
1152 | {"powerpc64", PROCESSOR_POWERPC64, | |
1153 | POWERPC_BASE_MASK | MASK_POWERPC64}, | |
1154 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1155 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1156 | {"rios2", PROCESSOR_RIOS2, | |
1157 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
1158 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1159 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 | 1160 | {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64}, |
66188a7e | 1161 | }; |
5248c961 | 1162 | |
ca7558fc | 1163 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 1164 | |
66188a7e GK |
1165 | /* Some OSs don't support saving the high part of 64-bit registers on |
1166 | context switch. Other OSs don't support saving Altivec registers. | |
1167 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
1168 | settings; if the user wants either, the user must explicitly specify | |
1169 | them and we won't interfere with the user's specification. */ | |
1170 | ||
1171 | enum { | |
1172 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
f676971a | 1173 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT |
66188a7e GK |
1174 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC |
1175 | | MASK_MFCRF) | |
1176 | }; | |
0d1fbc8c AH |
1177 | |
1178 | rs6000_init_hard_regno_mode_ok (); | |
1179 | ||
c4ad648e | 1180 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; |
66188a7e GK |
1181 | #ifdef OS_MISSING_POWERPC64 |
1182 | if (OS_MISSING_POWERPC64) | |
1183 | set_masks &= ~MASK_POWERPC64; | |
1184 | #endif | |
1185 | #ifdef OS_MISSING_ALTIVEC | |
1186 | if (OS_MISSING_ALTIVEC) | |
1187 | set_masks &= ~MASK_ALTIVEC; | |
1188 | #endif | |
1189 | ||
957211c3 AM |
1190 | /* Don't override these by the processor default if given explicitly. */ |
1191 | set_masks &= ~(target_flags_explicit | |
1192 | & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT)); | |
1193 | ||
a4f6c312 | 1194 | /* Identify the processor type. */ |
8e3f41e7 | 1195 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 1196 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 1197 | |
b6a1cbae | 1198 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 1199 | { |
8e3f41e7 MM |
1200 | ptr = &rs6000_select[i]; |
1201 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 1202 | { |
8e3f41e7 MM |
1203 | for (j = 0; j < ptt_size; j++) |
1204 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
1205 | { | |
1206 | if (ptr->set_tune_p) | |
1207 | rs6000_cpu = processor_target_table[j].processor; | |
1208 | ||
1209 | if (ptr->set_arch_p) | |
1210 | { | |
66188a7e GK |
1211 | target_flags &= ~set_masks; |
1212 | target_flags |= (processor_target_table[j].target_enable | |
1213 | & set_masks); | |
8e3f41e7 MM |
1214 | } |
1215 | break; | |
1216 | } | |
1217 | ||
4406229e | 1218 | if (j == ptt_size) |
8e3f41e7 | 1219 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
1220 | } |
1221 | } | |
8a61d227 | 1222 | |
993f19a8 | 1223 | if (TARGET_E500) |
a3170dc6 AH |
1224 | rs6000_isel = 1; |
1225 | ||
dff9f1b6 DE |
1226 | /* If we are optimizing big endian systems for space, use the load/store |
1227 | multiple and string instructions. */ | |
ef792183 | 1228 | if (BYTES_BIG_ENDIAN && optimize_size) |
957211c3 | 1229 | target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); |
938937d8 | 1230 | |
a4f6c312 SS |
1231 | /* Don't allow -mmultiple or -mstring on little endian systems |
1232 | unless the cpu is a 750, because the hardware doesn't support the | |
1233 | instructions used in little endian mode, and causes an alignment | |
1234 | trap. The 750 does not cause an alignment trap (except when the | |
1235 | target is unaligned). */ | |
bef84347 | 1236 | |
b21fb038 | 1237 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
1238 | { |
1239 | if (TARGET_MULTIPLE) | |
1240 | { | |
1241 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 1242 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
7e69e155 MM |
1243 | warning ("-mmultiple is not supported on little endian systems"); |
1244 | } | |
1245 | ||
1246 | if (TARGET_STRING) | |
1247 | { | |
1248 | target_flags &= ~MASK_STRING; | |
b21fb038 | 1249 | if ((target_flags_explicit & MASK_STRING) != 0) |
938937d8 | 1250 | warning ("-mstring is not supported on little endian systems"); |
7e69e155 MM |
1251 | } |
1252 | } | |
3933e0e1 | 1253 | |
38c1f2d7 MM |
1254 | /* Set debug flags */ |
1255 | if (rs6000_debug_name) | |
1256 | { | |
bfc79d3b | 1257 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 1258 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 1259 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 1260 | rs6000_debug_stack = 1; |
bfc79d3b | 1261 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
1262 | rs6000_debug_arg = 1; |
1263 | else | |
c725bd79 | 1264 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
1265 | } |
1266 | ||
57ac7be9 AM |
1267 | if (rs6000_traceback_name) |
1268 | { | |
1269 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
1270 | rs6000_traceback = traceback_full; | |
1271 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
1272 | rs6000_traceback = traceback_part; | |
1273 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
1274 | rs6000_traceback = traceback_none; | |
1275 | else | |
9e637a26 | 1276 | error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>", |
57ac7be9 AM |
1277 | rs6000_traceback_name); |
1278 | } | |
1279 | ||
6fa3f289 | 1280 | /* Set size of long double */ |
c1e55850 | 1281 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
6fa3f289 ZW |
1282 | if (rs6000_long_double_size_string) |
1283 | { | |
1284 | char *tail; | |
1285 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
1286 | if (*tail != '\0' || (size != 64 && size != 128)) | |
1287 | error ("Unknown switch -mlong-double-%s", | |
1288 | rs6000_long_double_size_string); | |
1289 | else | |
1290 | rs6000_long_double_type_size = size; | |
1291 | } | |
1292 | ||
6d0ef01e HP |
1293 | /* Set Altivec ABI as default for powerpc64 linux. */ |
1294 | if (TARGET_ELF && TARGET_64BIT) | |
1295 | { | |
1296 | rs6000_altivec_abi = 1; | |
1297 | rs6000_altivec_vrsave = 1; | |
1298 | } | |
1299 | ||
594a51fe SS |
1300 | /* Set the Darwin64 ABI as default for 64-bit Darwin. */ |
1301 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
1302 | { | |
1303 | rs6000_darwin64_abi = 1; | |
1304 | } | |
1305 | ||
0ac081f6 AH |
1306 | /* Handle -mabi= options. */ |
1307 | rs6000_parse_abi_options (); | |
1308 | ||
025d9908 KH |
1309 | /* Handle -malign-XXXXX option. */ |
1310 | rs6000_parse_alignment_option (); | |
1311 | ||
4d4cbc0e AH |
1312 | rs6000_parse_float_gprs_option (); |
1313 | ||
5da702b1 AH |
1314 | /* Handle generic -mFOO=YES/NO options. */ |
1315 | rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string, | |
1316 | &rs6000_altivec_vrsave); | |
1317 | rs6000_parse_yes_no_option ("isel", rs6000_isel_string, | |
1318 | &rs6000_isel); | |
1319 | rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe); | |
993f19a8 | 1320 | |
c4501e62 JJ |
1321 | /* Handle -mtls-size option. */ |
1322 | rs6000_parse_tls_size_option (); | |
1323 | ||
a7ae18e2 AH |
1324 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1325 | SUBTARGET_OVERRIDE_OPTIONS; | |
1326 | #endif | |
1327 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
1328 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
1329 | #endif | |
4d4cbc0e AH |
1330 | #ifdef SUB3TARGET_OVERRIDE_OPTIONS |
1331 | SUB3TARGET_OVERRIDE_OPTIONS; | |
1332 | #endif | |
a7ae18e2 | 1333 | |
5da702b1 AH |
1334 | if (TARGET_E500) |
1335 | { | |
e4463bf1 AH |
1336 | if (TARGET_ALTIVEC) |
1337 | error ("AltiVec and E500 instructions cannot coexist"); | |
1338 | ||
5da702b1 AH |
1339 | /* The e500 does not have string instructions, and we set |
1340 | MASK_STRING above when optimizing for size. */ | |
1341 | if ((target_flags & MASK_STRING) != 0) | |
1342 | target_flags = target_flags & ~MASK_STRING; | |
b6e59a3a AH |
1343 | |
1344 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
1345 | if (rs6000_spe_string != 0 | |
c4ad648e | 1346 | && !strcmp (rs6000_spe_string, "no")) |
b6e59a3a | 1347 | rs6000_long_double_type_size = 64; |
5da702b1 AH |
1348 | } |
1349 | else if (rs6000_select[1].string != NULL) | |
1350 | { | |
1351 | /* For the powerpc-eabispe configuration, we set all these by | |
1352 | default, so let's unset them if we manually set another | |
1353 | CPU that is not the E500. */ | |
1354 | if (rs6000_abi_string == 0) | |
1355 | rs6000_spe_abi = 0; | |
1356 | if (rs6000_spe_string == 0) | |
1357 | rs6000_spe = 0; | |
1358 | if (rs6000_float_gprs_string == 0) | |
1359 | rs6000_float_gprs = 0; | |
1360 | if (rs6000_isel_string == 0) | |
1361 | rs6000_isel = 0; | |
b6e59a3a | 1362 | if (rs6000_long_double_size_string == 0) |
c1e55850 | 1363 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
5da702b1 | 1364 | } |
b5044283 | 1365 | |
ec507f2d DE |
1366 | rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 |
1367 | && rs6000_cpu != PROCESSOR_POWER5); | |
1368 | rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 | |
1369 | || rs6000_cpu == PROCESSOR_POWER5); | |
1370 | ||
a5c76ee6 ZW |
1371 | /* Handle -m(no-)longcall option. This is a bit of a cheap hack, |
1372 | using TARGET_OPTIONS to handle a toggle switch, but we're out of | |
1373 | bits in target_flags so TARGET_SWITCHES cannot be used. | |
1374 | Assumption here is that rs6000_longcall_switch points into the | |
1375 | text of the complete option, rather than being a copy, so we can | |
1376 | scan back for the presence or absence of the no- modifier. */ | |
1377 | if (rs6000_longcall_switch) | |
1378 | { | |
1379 | const char *base = rs6000_longcall_switch; | |
1380 | while (base[-1] != 'm') base--; | |
1381 | ||
1382 | if (*rs6000_longcall_switch != '\0') | |
9e637a26 | 1383 | error ("invalid option %qs", base); |
a5c76ee6 ZW |
1384 | rs6000_default_long_calls = (base[0] != 'n'); |
1385 | } | |
1386 | ||
8bb418a3 ZL |
1387 | /* Handle -m(no-)warn-altivec-long similarly. */ |
1388 | if (rs6000_warn_altivec_long_switch) | |
1389 | { | |
1390 | const char *base = rs6000_warn_altivec_long_switch; | |
1391 | while (base[-1] != 'm') base--; | |
1392 | ||
1393 | if (*rs6000_warn_altivec_long_switch != '\0') | |
9e637a26 | 1394 | error ("invalid option %qs", base); |
8bb418a3 ZL |
1395 | rs6000_warn_altivec_long = (base[0] != 'n'); |
1396 | } | |
1397 | ||
cbe26ab8 | 1398 | /* Handle -mprioritize-restricted-insns option. */ |
ec507f2d DE |
1399 | rs6000_sched_restricted_insns_priority |
1400 | = (rs6000_sched_groups ? 1 : 0); | |
79ae11c4 DN |
1401 | if (rs6000_sched_restricted_insns_priority_str) |
1402 | rs6000_sched_restricted_insns_priority = | |
1403 | atoi (rs6000_sched_restricted_insns_priority_str); | |
1404 | ||
569fa502 | 1405 | /* Handle -msched-costly-dep option. */ |
ec507f2d DE |
1406 | rs6000_sched_costly_dep |
1407 | = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); | |
569fa502 DN |
1408 | if (rs6000_sched_costly_dep_str) |
1409 | { | |
f676971a | 1410 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) |
c4ad648e | 1411 | rs6000_sched_costly_dep = no_dep_costly; |
569fa502 | 1412 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) |
c4ad648e | 1413 | rs6000_sched_costly_dep = all_deps_costly; |
569fa502 | 1414 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) |
c4ad648e | 1415 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; |
569fa502 | 1416 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) |
c4ad648e | 1417 | rs6000_sched_costly_dep = store_to_load_dep_costly; |
f676971a | 1418 | else |
c4ad648e | 1419 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); |
cbe26ab8 DN |
1420 | } |
1421 | ||
1422 | /* Handle -minsert-sched-nops option. */ | |
ec507f2d DE |
1423 | rs6000_sched_insert_nops |
1424 | = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); | |
cbe26ab8 DN |
1425 | if (rs6000_sched_insert_nops_str) |
1426 | { | |
1427 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
c4ad648e | 1428 | rs6000_sched_insert_nops = sched_finish_none; |
cbe26ab8 | 1429 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) |
c4ad648e | 1430 | rs6000_sched_insert_nops = sched_finish_pad_groups; |
cbe26ab8 | 1431 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) |
c4ad648e | 1432 | rs6000_sched_insert_nops = sched_finish_regroup_exact; |
cbe26ab8 | 1433 | else |
c4ad648e | 1434 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); |
569fa502 DN |
1435 | } |
1436 | ||
c81bebd7 | 1437 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
1438 | /* If the user desires alternate register names, copy in the |
1439 | alternate names now. */ | |
c81bebd7 | 1440 | if (TARGET_REGNAMES) |
4e135bdd | 1441 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
1442 | #endif |
1443 | ||
6fa3f289 ZW |
1444 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
1445 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
1446 | used, don't override with the ABI default. */ | |
b21fb038 | 1447 | if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0) |
6fa3f289 ZW |
1448 | { |
1449 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
1450 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
1451 | else | |
1452 | target_flags |= MASK_AIX_STRUCT_RET; | |
1453 | } | |
1454 | ||
fcce224d DE |
1455 | if (TARGET_LONG_DOUBLE_128 |
1456 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
70a01792 | 1457 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 1458 | |
9ebbca7d GK |
1459 | /* Allocate an alias set for register saves & restores from stack. */ |
1460 | rs6000_sr_alias_set = new_alias_set (); | |
1461 | ||
f676971a | 1462 | if (TARGET_TOC) |
9ebbca7d | 1463 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); |
71f123ca | 1464 | |
301d03af RS |
1465 | /* We can only guarantee the availability of DI pseudo-ops when |
1466 | assembling for 64-bit targets. */ | |
ae6c1efd | 1467 | if (!TARGET_64BIT) |
301d03af RS |
1468 | { |
1469 | targetm.asm_out.aligned_op.di = NULL; | |
1470 | targetm.asm_out.unaligned_op.di = NULL; | |
1471 | } | |
1472 | ||
1494c534 DE |
1473 | /* Set branch target alignment, if not optimizing for size. */ |
1474 | if (!optimize_size) | |
1475 | { | |
1476 | if (rs6000_sched_groups) | |
1477 | { | |
1478 | if (align_functions <= 0) | |
1479 | align_functions = 16; | |
1480 | if (align_jumps <= 0) | |
1481 | align_jumps = 16; | |
1482 | if (align_loops <= 0) | |
1483 | align_loops = 16; | |
1484 | } | |
1485 | if (align_jumps_max_skip <= 0) | |
1486 | align_jumps_max_skip = 15; | |
1487 | if (align_loops_max_skip <= 0) | |
1488 | align_loops_max_skip = 15; | |
1489 | } | |
2792d578 | 1490 | |
71f123ca FS |
1491 | /* Arrange to save and restore machine status around nested functions. */ |
1492 | init_machine_status = rs6000_init_machine_status; | |
42ba5130 RH |
1493 | |
1494 | /* We should always be splitting complex arguments, but we can't break | |
1495 | Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ | |
18f63bfa | 1496 | if (DEFAULT_ABI != ABI_AIX) |
42ba5130 | 1497 | targetm.calls.split_complex_arg = NULL; |
8b897cfa RS |
1498 | |
1499 | /* Initialize rs6000_cost with the appropriate target costs. */ | |
1500 | if (optimize_size) | |
1501 | rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; | |
1502 | else | |
1503 | switch (rs6000_cpu) | |
1504 | { | |
1505 | case PROCESSOR_RIOS1: | |
1506 | rs6000_cost = &rios1_cost; | |
1507 | break; | |
1508 | ||
1509 | case PROCESSOR_RIOS2: | |
1510 | rs6000_cost = &rios2_cost; | |
1511 | break; | |
1512 | ||
1513 | case PROCESSOR_RS64A: | |
1514 | rs6000_cost = &rs64a_cost; | |
1515 | break; | |
1516 | ||
1517 | case PROCESSOR_MPCCORE: | |
1518 | rs6000_cost = &mpccore_cost; | |
1519 | break; | |
1520 | ||
1521 | case PROCESSOR_PPC403: | |
1522 | rs6000_cost = &ppc403_cost; | |
1523 | break; | |
1524 | ||
1525 | case PROCESSOR_PPC405: | |
1526 | rs6000_cost = &ppc405_cost; | |
1527 | break; | |
1528 | ||
1529 | case PROCESSOR_PPC440: | |
1530 | rs6000_cost = &ppc440_cost; | |
1531 | break; | |
1532 | ||
1533 | case PROCESSOR_PPC601: | |
1534 | rs6000_cost = &ppc601_cost; | |
1535 | break; | |
1536 | ||
1537 | case PROCESSOR_PPC603: | |
1538 | rs6000_cost = &ppc603_cost; | |
1539 | break; | |
1540 | ||
1541 | case PROCESSOR_PPC604: | |
1542 | rs6000_cost = &ppc604_cost; | |
1543 | break; | |
1544 | ||
1545 | case PROCESSOR_PPC604e: | |
1546 | rs6000_cost = &ppc604e_cost; | |
1547 | break; | |
1548 | ||
1549 | case PROCESSOR_PPC620: | |
8b897cfa RS |
1550 | rs6000_cost = &ppc620_cost; |
1551 | break; | |
1552 | ||
f0517163 RS |
1553 | case PROCESSOR_PPC630: |
1554 | rs6000_cost = &ppc630_cost; | |
1555 | break; | |
1556 | ||
8b897cfa RS |
1557 | case PROCESSOR_PPC750: |
1558 | case PROCESSOR_PPC7400: | |
1559 | rs6000_cost = &ppc750_cost; | |
1560 | break; | |
1561 | ||
1562 | case PROCESSOR_PPC7450: | |
1563 | rs6000_cost = &ppc7450_cost; | |
1564 | break; | |
1565 | ||
1566 | case PROCESSOR_PPC8540: | |
1567 | rs6000_cost = &ppc8540_cost; | |
1568 | break; | |
1569 | ||
1570 | case PROCESSOR_POWER4: | |
1571 | case PROCESSOR_POWER5: | |
1572 | rs6000_cost = &power4_cost; | |
1573 | break; | |
1574 | ||
1575 | default: | |
1576 | abort (); | |
1577 | } | |
5248c961 | 1578 | } |
5accd822 | 1579 | |
7ccf35ed DN |
1580 | /* Implement targetm.vectorize.builtin_mask_for_load. */ |
1581 | static tree | |
1582 | rs6000_builtin_mask_for_load (void) | |
1583 | { | |
1584 | if (TARGET_ALTIVEC) | |
1585 | return altivec_builtin_mask_for_load; | |
1586 | else | |
1587 | return 0; | |
1588 | } | |
1589 | ||
1590 | /* Implement targetm.vectorize.builtin_mask_for_store. */ | |
1591 | static tree | |
1592 | rs6000_builtin_mask_for_store (void) | |
1593 | { | |
1594 | if (TARGET_ALTIVEC) | |
1595 | return altivec_builtin_mask_for_store; | |
1596 | else | |
1597 | return 0; | |
1598 | } | |
1599 | ||
5da702b1 AH |
1600 | /* Handle generic options of the form -mfoo=yes/no. |
1601 | NAME is the option name. | |
1602 | VALUE is the option value. | |
1603 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
1604 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 1605 | static void |
5da702b1 | 1606 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 1607 | { |
5da702b1 | 1608 | if (value == 0) |
993f19a8 | 1609 | return; |
5da702b1 AH |
1610 | else if (!strcmp (value, "yes")) |
1611 | *flag = 1; | |
1612 | else if (!strcmp (value, "no")) | |
1613 | *flag = 0; | |
08b57fb3 | 1614 | else |
5da702b1 | 1615 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
1616 | } |
1617 | ||
0ac081f6 | 1618 | /* Handle -mabi= options. */ |
00b960c7 | 1619 | static void |
863d938c | 1620 | rs6000_parse_abi_options (void) |
0ac081f6 AH |
1621 | { |
1622 | if (rs6000_abi_string == 0) | |
1623 | return; | |
1624 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
5cc73f91 AH |
1625 | { |
1626 | rs6000_altivec_abi = 1; | |
1627 | rs6000_spe_abi = 0; | |
1628 | } | |
76a773f3 AH |
1629 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
1630 | rs6000_altivec_abi = 0; | |
a3170dc6 | 1631 | else if (! strcmp (rs6000_abi_string, "spe")) |
01f4962d NS |
1632 | { |
1633 | rs6000_spe_abi = 1; | |
5cc73f91 | 1634 | rs6000_altivec_abi = 0; |
01f4962d NS |
1635 | if (!TARGET_SPE_ABI) |
1636 | error ("not configured for ABI: '%s'", rs6000_abi_string); | |
1637 | } | |
f676971a | 1638 | |
594a51fe SS |
1639 | /* These are here for testing during development only, do not |
1640 | document in the manual please. */ | |
1641 | else if (! strcmp (rs6000_abi_string, "d64")) | |
1642 | { | |
1643 | rs6000_darwin64_abi = 1; | |
1644 | warning ("Using darwin64 ABI"); | |
1645 | } | |
1646 | else if (! strcmp (rs6000_abi_string, "d32")) | |
1647 | { | |
1648 | rs6000_darwin64_abi = 0; | |
1649 | warning ("Using old darwin ABI"); | |
1650 | } | |
1651 | ||
a3170dc6 AH |
1652 | else if (! strcmp (rs6000_abi_string, "no-spe")) |
1653 | rs6000_spe_abi = 0; | |
0ac081f6 | 1654 | else |
c725bd79 | 1655 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
1656 | } |
1657 | ||
4d4cbc0e AH |
1658 | /* Handle -mfloat-gprs= options. */ |
1659 | static void | |
1660 | rs6000_parse_float_gprs_option (void) | |
1661 | { | |
1662 | if (rs6000_float_gprs_string == 0) | |
1663 | return; | |
1664 | else if (! strcmp (rs6000_float_gprs_string, "yes") | |
1665 | || ! strcmp (rs6000_float_gprs_string, "single")) | |
1666 | rs6000_float_gprs = 1; | |
1667 | else if (! strcmp (rs6000_float_gprs_string, "double")) | |
1668 | rs6000_float_gprs = 2; | |
1669 | else if (! strcmp (rs6000_float_gprs_string, "no")) | |
1670 | rs6000_float_gprs = 0; | |
1671 | else | |
1672 | error ("invalid option for -mfloat-gprs"); | |
1673 | } | |
1674 | ||
025d9908 KH |
1675 | /* Handle -malign-XXXXXX options. */ |
1676 | static void | |
863d938c | 1677 | rs6000_parse_alignment_option (void) |
025d9908 | 1678 | { |
b20a9cca AM |
1679 | if (rs6000_alignment_string == 0) |
1680 | return; | |
1681 | else if (! strcmp (rs6000_alignment_string, "power")) | |
025d9908 KH |
1682 | rs6000_alignment_flags = MASK_ALIGN_POWER; |
1683 | else if (! strcmp (rs6000_alignment_string, "natural")) | |
1684 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
1685 | else | |
1686 | error ("unknown -malign-XXXXX option specified: '%s'", | |
1687 | rs6000_alignment_string); | |
1688 | } | |
1689 | ||
c4501e62 JJ |
1690 | /* Validate and record the size specified with the -mtls-size option. */ |
1691 | ||
1692 | static void | |
863d938c | 1693 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
1694 | { |
1695 | if (rs6000_tls_size_string == 0) | |
1696 | return; | |
1697 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
1698 | rs6000_tls_size = 16; | |
1699 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
1700 | rs6000_tls_size = 32; | |
1701 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
1702 | rs6000_tls_size = 64; | |
1703 | else | |
9e637a26 | 1704 | error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string); |
c4501e62 JJ |
1705 | } |
1706 | ||
5accd822 | 1707 | void |
a2369ed3 | 1708 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 1709 | { |
5accd822 | 1710 | } |
3cfa4909 MM |
1711 | \f |
1712 | /* Do anything needed at the start of the asm file. */ | |
1713 | ||
1bc7c5b6 | 1714 | static void |
863d938c | 1715 | rs6000_file_start (void) |
3cfa4909 | 1716 | { |
c4d38ccb | 1717 | size_t i; |
3cfa4909 | 1718 | char buffer[80]; |
d330fd93 | 1719 | const char *start = buffer; |
3cfa4909 | 1720 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
1721 | const char *default_cpu = TARGET_CPU_DEFAULT; |
1722 | FILE *file = asm_out_file; | |
1723 | ||
1724 | default_file_start (); | |
1725 | ||
1726 | #ifdef TARGET_BI_ARCH | |
1727 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
1728 | default_cpu = 0; | |
1729 | #endif | |
3cfa4909 MM |
1730 | |
1731 | if (flag_verbose_asm) | |
1732 | { | |
1733 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
1734 | rs6000_select[0].string = default_cpu; | |
1735 | ||
b6a1cbae | 1736 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
1737 | { |
1738 | ptr = &rs6000_select[i]; | |
1739 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
1740 | { | |
1741 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
1742 | start = ""; | |
1743 | } | |
1744 | } | |
1745 | ||
b91da81f | 1746 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
1747 | switch (rs6000_sdata) |
1748 | { | |
1749 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
1750 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
1751 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
1752 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
1753 | } | |
1754 | ||
1755 | if (rs6000_sdata && g_switch_value) | |
1756 | { | |
307b599c MK |
1757 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
1758 | g_switch_value); | |
3cfa4909 MM |
1759 | start = ""; |
1760 | } | |
1761 | #endif | |
1762 | ||
1763 | if (*start == '\0') | |
949ea356 | 1764 | putc ('\n', file); |
3cfa4909 MM |
1765 | } |
1766 | } | |
c4e18b1c | 1767 | |
5248c961 | 1768 | \f |
a0ab749a | 1769 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1770 | |
1771 | int | |
863d938c | 1772 | direct_return (void) |
9878760c | 1773 | { |
4697a36c MM |
1774 | if (reload_completed) |
1775 | { | |
1776 | rs6000_stack_t *info = rs6000_stack_info (); | |
1777 | ||
1778 | if (info->first_gp_reg_save == 32 | |
1779 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1780 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1781 | && ! info->lr_save_p |
1782 | && ! info->cr_save_p | |
00b960c7 | 1783 | && info->vrsave_mask == 0 |
c81fc13e | 1784 | && ! info->push_p) |
4697a36c MM |
1785 | return 1; |
1786 | } | |
1787 | ||
1788 | return 0; | |
9878760c RK |
1789 | } |
1790 | ||
1791 | /* Returns 1 always. */ | |
1792 | ||
1793 | int | |
f676971a | 1794 | any_operand (rtx op ATTRIBUTE_UNUSED, |
a2369ed3 | 1795 | enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
1796 | { |
1797 | return 1; | |
1798 | } | |
1799 | ||
85d346f1 DE |
1800 | /* Returns 1 always. */ |
1801 | ||
1802 | int | |
f676971a | 1803 | any_parallel_operand (rtx op ATTRIBUTE_UNUSED, |
85d346f1 DE |
1804 | enum machine_mode mode ATTRIBUTE_UNUSED) |
1805 | { | |
1806 | return 1; | |
1807 | } | |
1808 | ||
a4f6c312 | 1809 | /* Returns 1 if op is the count register. */ |
85d346f1 | 1810 | |
38c1f2d7 | 1811 | int |
a2369ed3 | 1812 | count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
b6c9286a MM |
1813 | { |
1814 | if (GET_CODE (op) != REG) | |
1815 | return 0; | |
1816 | ||
1817 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
1818 | return 1; | |
1819 | ||
1820 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
1821 | return 1; | |
1822 | ||
1823 | return 0; | |
1824 | } | |
1825 | ||
0ec4e2a8 | 1826 | /* Returns 1 if op is an altivec register. */ |
85d346f1 | 1827 | |
0ec4e2a8 | 1828 | int |
a2369ed3 | 1829 | altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ec4e2a8 | 1830 | { |
0ec4e2a8 AH |
1831 | return (register_operand (op, mode) |
1832 | && (GET_CODE (op) != REG | |
1833 | || REGNO (op) > FIRST_PSEUDO_REGISTER | |
1834 | || ALTIVEC_REGNO_P (REGNO (op)))); | |
1835 | } | |
1836 | ||
38c1f2d7 | 1837 | int |
a2369ed3 | 1838 | xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
802a0058 MM |
1839 | { |
1840 | if (GET_CODE (op) != REG) | |
1841 | return 0; | |
1842 | ||
9ebbca7d | 1843 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
1844 | return 1; |
1845 | ||
802a0058 MM |
1846 | return 0; |
1847 | } | |
1848 | ||
c859cda6 | 1849 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 1850 | by such constants completes more quickly. */ |
c859cda6 DJ |
1851 | |
1852 | int | |
a2369ed3 | 1853 | s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c859cda6 | 1854 | { |
c4ad648e | 1855 | return (GET_CODE (op) == CONST_INT |
c859cda6 DJ |
1856 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); |
1857 | } | |
1858 | ||
9878760c RK |
1859 | /* Return 1 if OP is a constant that can fit in a D field. */ |
1860 | ||
1861 | int | |
a2369ed3 | 1862 | short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1863 | { |
5f59ecb7 DE |
1864 | return (GET_CODE (op) == CONST_INT |
1865 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
1866 | } |
1867 | ||
5519a4f9 | 1868 | /* Similar for an unsigned D field. */ |
9878760c RK |
1869 | |
1870 | int | |
a2369ed3 | 1871 | u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1872 | { |
19684119 | 1873 | return (GET_CODE (op) == CONST_INT |
c1f11548 | 1874 | && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K')); |
9878760c RK |
1875 | } |
1876 | ||
dcfedcd0 RK |
1877 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
1878 | ||
1879 | int | |
a2369ed3 | 1880 | non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
1881 | { |
1882 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1883 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
1884 | } |
1885 | ||
2bfcf297 DB |
1886 | /* Returns 1 if OP is a CONST_INT that is a positive value |
1887 | and an exact power of 2. */ | |
1888 | ||
1889 | int | |
a2369ed3 | 1890 | exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bfcf297 DB |
1891 | { |
1892 | return (GET_CODE (op) == CONST_INT | |
1893 | && INTVAL (op) > 0 | |
1894 | && exact_log2 (INTVAL (op)) >= 0); | |
1895 | } | |
1896 | ||
9878760c RK |
1897 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
1898 | ctr, or lr). */ | |
1899 | ||
1900 | int | |
a2369ed3 | 1901 | gpc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1902 | { |
1903 | return (register_operand (op, mode) | |
802a0058 | 1904 | && (GET_CODE (op) != REG |
f676971a | 1905 | || (REGNO (op) >= ARG_POINTER_REGNUM |
9ebbca7d GK |
1906 | && !XER_REGNO_P (REGNO (op))) |
1907 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
1908 | } |
1909 | ||
1910 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
1911 | CR field. */ | |
1912 | ||
1913 | int | |
a2369ed3 | 1914 | cc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1915 | { |
1916 | return (register_operand (op, mode) | |
1917 | && (GET_CODE (op) != REG | |
1918 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1919 | || CR_REGNO_P (REGNO (op)))); | |
1920 | } | |
1921 | ||
815cdc52 MM |
1922 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
1923 | CR field that isn't CR0. */ | |
1924 | ||
1925 | int | |
a2369ed3 | 1926 | cc_reg_not_cr0_operand (rtx op, enum machine_mode mode) |
815cdc52 MM |
1927 | { |
1928 | return (register_operand (op, mode) | |
1929 | && (GET_CODE (op) != REG | |
1930 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1931 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
1932 | } | |
1933 | ||
a4f6c312 SS |
1934 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
1935 | a non-special register. If a register, it must be in the proper | |
1936 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
1937 | |
1938 | int | |
a2369ed3 | 1939 | reg_or_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1940 | { |
f5a28898 | 1941 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1942 | } |
1943 | ||
a4f6c312 | 1944 | /* Similar, except check if the negation of the constant would be |
42f806e5 AM |
1945 | valid for a D-field. Don't allow a constant zero, since all the |
1946 | patterns that call this predicate use "addic r1,r2,-constant" on | |
1947 | a constant value to set a carry when r2 is greater or equal to | |
1948 | "constant". That doesn't work for zero. */ | |
9878760c RK |
1949 | |
1950 | int | |
a2369ed3 | 1951 | reg_or_neg_short_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1952 | { |
1953 | if (GET_CODE (op) == CONST_INT) | |
42f806e5 | 1954 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0; |
9878760c | 1955 | |
cd2b37d9 | 1956 | return gpc_reg_operand (op, mode); |
9878760c RK |
1957 | } |
1958 | ||
768070a0 TR |
1959 | /* Returns 1 if OP is either a constant integer valid for a DS-field or |
1960 | a non-special register. If a register, it must be in the proper | |
1961 | mode unless MODE is VOIDmode. */ | |
1962 | ||
1963 | int | |
a2369ed3 | 1964 | reg_or_aligned_short_operand (rtx op, enum machine_mode mode) |
768070a0 TR |
1965 | { |
1966 | if (gpc_reg_operand (op, mode)) | |
1967 | return 1; | |
1968 | else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3)) | |
1969 | return 1; | |
1970 | ||
1971 | return 0; | |
1972 | } | |
1973 | ||
1974 | ||
a4f6c312 SS |
1975 | /* Return 1 if the operand is either a register or an integer whose |
1976 | high-order 16 bits are zero. */ | |
9878760c RK |
1977 | |
1978 | int | |
a2369ed3 | 1979 | reg_or_u_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1980 | { |
e675f625 | 1981 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1982 | } |
1983 | ||
1984 | /* Return 1 is the operand is either a non-special register or ANY | |
1985 | constant integer. */ | |
1986 | ||
1987 | int | |
a2369ed3 | 1988 | reg_or_cint_operand (rtx op, enum machine_mode mode) |
9878760c | 1989 | { |
a4f6c312 | 1990 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
1991 | } |
1992 | ||
1993 | /* Return 1 is the operand is either a non-special register or ANY | |
1994 | 32-bit signed constant integer. */ | |
1995 | ||
1996 | int | |
a2369ed3 | 1997 | reg_or_arith_cint_operand (rtx op, enum machine_mode mode) |
f6bf7de2 | 1998 | { |
a4f6c312 SS |
1999 | return (gpc_reg_operand (op, mode) |
2000 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 2001 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
2002 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
2003 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 2004 | #endif |
a4f6c312 | 2005 | )); |
9878760c RK |
2006 | } |
2007 | ||
2bfcf297 DB |
2008 | /* Return 1 is the operand is either a non-special register or a 32-bit |
2009 | signed constant integer valid for 64-bit addition. */ | |
2010 | ||
2011 | int | |
a2369ed3 | 2012 | reg_or_add_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 2013 | { |
a4f6c312 SS |
2014 | return (gpc_reg_operand (op, mode) |
2015 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 2016 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 2017 | && INTVAL (op) < 0x7fff8000 |
a65c591c | 2018 | #else |
a4f6c312 SS |
2019 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
2020 | < 0x100000000ll) | |
2bfcf297 | 2021 | #endif |
a4f6c312 | 2022 | )); |
2bfcf297 DB |
2023 | } |
2024 | ||
2025 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
2026 | signed constant integer valid for 64-bit subtraction. */ | |
2027 | ||
2028 | int | |
a2369ed3 | 2029 | reg_or_sub_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 2030 | { |
a4f6c312 SS |
2031 | return (gpc_reg_operand (op, mode) |
2032 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 2033 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 2034 | && (- INTVAL (op)) < 0x7fff8000 |
a65c591c | 2035 | #else |
a4f6c312 SS |
2036 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
2037 | < 0x100000000ll) | |
2bfcf297 | 2038 | #endif |
a4f6c312 | 2039 | )); |
2bfcf297 DB |
2040 | } |
2041 | ||
9ebbca7d GK |
2042 | /* Return 1 is the operand is either a non-special register or ANY |
2043 | 32-bit unsigned constant integer. */ | |
2044 | ||
2045 | int | |
a2369ed3 | 2046 | reg_or_logical_cint_operand (rtx op, enum machine_mode mode) |
9ebbca7d | 2047 | { |
1d328b19 GK |
2048 | if (GET_CODE (op) == CONST_INT) |
2049 | { | |
2050 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
2051 | { | |
2052 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 2053 | abort (); |
1d328b19 GK |
2054 | |
2055 | if (INTVAL (op) < 0) | |
2056 | return 0; | |
2057 | } | |
2058 | ||
2059 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 2060 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
2061 | } |
2062 | else if (GET_CODE (op) == CONST_DOUBLE) | |
2063 | { | |
2064 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
2065 | || mode != DImode) | |
a4f6c312 | 2066 | abort (); |
1d328b19 GK |
2067 | |
2068 | return CONST_DOUBLE_HIGH (op) == 0; | |
2069 | } | |
f676971a | 2070 | else |
1d328b19 | 2071 | return gpc_reg_operand (op, mode); |
9ebbca7d GK |
2072 | } |
2073 | ||
51d3e7d6 | 2074 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
2075 | |
2076 | int | |
a2369ed3 | 2077 | got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
766a866c MM |
2078 | { |
2079 | return (GET_CODE (op) == SYMBOL_REF | |
2080 | || GET_CODE (op) == CONST | |
2081 | || GET_CODE (op) == LABEL_REF); | |
2082 | } | |
2083 | ||
38c1f2d7 MM |
2084 | /* Return 1 if the operand is a simple references that can be loaded via |
2085 | the GOT (labels involving addition aren't allowed). */ | |
2086 | ||
2087 | int | |
a2369ed3 | 2088 | got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
38c1f2d7 MM |
2089 | { |
2090 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
2091 | } | |
2092 | ||
4e74d8ec MM |
2093 | /* Return the number of instructions it takes to form a constant in an |
2094 | integer register. */ | |
2095 | ||
2096 | static int | |
a2369ed3 | 2097 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
2098 | { |
2099 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 2100 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
2101 | return 1; |
2102 | ||
4e74d8ec | 2103 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 2104 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
2105 | return 1; |
2106 | ||
5f59ecb7 | 2107 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 2108 | else if (TARGET_POWERPC64) |
4e74d8ec | 2109 | { |
a65c591c DE |
2110 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
2111 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 2112 | |
a65c591c | 2113 | if (high == 0 || high == -1) |
4e74d8ec MM |
2114 | return 2; |
2115 | ||
a65c591c | 2116 | high >>= 1; |
4e74d8ec | 2117 | |
a65c591c | 2118 | if (low == 0) |
4e74d8ec | 2119 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
2120 | else |
2121 | return (num_insns_constant_wide (high) | |
e396202a | 2122 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
2123 | } |
2124 | #endif | |
2125 | ||
2126 | else | |
2127 | return 2; | |
2128 | } | |
2129 | ||
2130 | int | |
a2369ed3 | 2131 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 2132 | { |
4e74d8ec | 2133 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
2134 | { |
2135 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
2136 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
2137 | && mask64_operand (op, mode)) | |
c4ad648e | 2138 | return 2; |
0d30d435 DE |
2139 | else |
2140 | #endif | |
2141 | return num_insns_constant_wide (INTVAL (op)); | |
2142 | } | |
4e74d8ec | 2143 | |
6fc48950 MM |
2144 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
2145 | { | |
2146 | long l; | |
2147 | REAL_VALUE_TYPE rv; | |
2148 | ||
2149 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2150 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
e72247f4 | 2151 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
6fc48950 MM |
2152 | } |
2153 | ||
47ad8c61 | 2154 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 2155 | { |
47ad8c61 MM |
2156 | HOST_WIDE_INT low; |
2157 | HOST_WIDE_INT high; | |
2158 | long l[2]; | |
2159 | REAL_VALUE_TYPE rv; | |
2160 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 2161 | |
47ad8c61 MM |
2162 | if (mode == VOIDmode || mode == DImode) |
2163 | { | |
2164 | high = CONST_DOUBLE_HIGH (op); | |
2165 | low = CONST_DOUBLE_LOW (op); | |
2166 | } | |
2167 | else | |
2168 | { | |
2169 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2170 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
2171 | high = l[endian]; | |
2172 | low = l[1 - endian]; | |
2173 | } | |
4e74d8ec | 2174 | |
47ad8c61 MM |
2175 | if (TARGET_32BIT) |
2176 | return (num_insns_constant_wide (low) | |
2177 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
2178 | |
2179 | else | |
47ad8c61 | 2180 | { |
e72247f4 | 2181 | if (high == 0 && low >= 0) |
47ad8c61 MM |
2182 | return num_insns_constant_wide (low); |
2183 | ||
e72247f4 | 2184 | else if (high == -1 && low < 0) |
47ad8c61 MM |
2185 | return num_insns_constant_wide (low); |
2186 | ||
a260abc9 DE |
2187 | else if (mask64_operand (op, mode)) |
2188 | return 2; | |
2189 | ||
47ad8c61 MM |
2190 | else if (low == 0) |
2191 | return num_insns_constant_wide (high) + 1; | |
2192 | ||
2193 | else | |
2194 | return (num_insns_constant_wide (high) | |
2195 | + num_insns_constant_wide (low) + 1); | |
2196 | } | |
4e74d8ec MM |
2197 | } |
2198 | ||
2199 | else | |
2200 | abort (); | |
2201 | } | |
2202 | ||
a4f6c312 SS |
2203 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
2204 | register with one instruction per word. We only do this if we can | |
2205 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
2206 | |
2207 | int | |
a2369ed3 | 2208 | easy_fp_constant (rtx op, enum machine_mode mode) |
9878760c | 2209 | { |
9878760c RK |
2210 | if (GET_CODE (op) != CONST_DOUBLE |
2211 | || GET_MODE (op) != mode | |
4e74d8ec | 2212 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
2213 | return 0; |
2214 | ||
a4f6c312 | 2215 | /* Consider all constants with -msoft-float to be easy. */ |
4d4cbc0e | 2216 | if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) |
a3170dc6 | 2217 | && mode != DImode) |
b6c9286a MM |
2218 | return 1; |
2219 | ||
a4f6c312 | 2220 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 2221 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
2222 | return 0; |
2223 | ||
5ae4759c | 2224 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
2225 | /* Similarly if we are using -mrelocatable, consider all constants |
2226 | to be hard. */ | |
5ae4759c MM |
2227 | if (TARGET_RELOCATABLE) |
2228 | return 0; | |
2229 | #endif | |
2230 | ||
fcce224d DE |
2231 | if (mode == TFmode) |
2232 | { | |
2233 | long k[4]; | |
2234 | REAL_VALUE_TYPE rv; | |
2235 | ||
2236 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2237 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
2238 | ||
2239 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
2240 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
2241 | && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
2242 | && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
2243 | } | |
2244 | ||
2245 | else if (mode == DFmode) | |
042259f2 DE |
2246 | { |
2247 | long k[2]; | |
2248 | REAL_VALUE_TYPE rv; | |
2249 | ||
4d4cbc0e AH |
2250 | if (TARGET_E500_DOUBLE) |
2251 | return 0; | |
2252 | ||
042259f2 DE |
2253 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
2254 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 2255 | |
a65c591c DE |
2256 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 |
2257 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
042259f2 | 2258 | } |
4e74d8ec MM |
2259 | |
2260 | else if (mode == SFmode) | |
042259f2 DE |
2261 | { |
2262 | long l; | |
2263 | REAL_VALUE_TYPE rv; | |
2264 | ||
2265 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2266 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 2267 | |
4e74d8ec | 2268 | return num_insns_constant_wide (l) == 1; |
042259f2 | 2269 | } |
4e74d8ec | 2270 | |
a260abc9 | 2271 | else if (mode == DImode) |
c81fc13e | 2272 | return ((TARGET_POWERPC64 |
a260abc9 DE |
2273 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
2274 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 2275 | |
a9098fd0 GK |
2276 | else if (mode == SImode) |
2277 | return 1; | |
4e74d8ec MM |
2278 | else |
2279 | abort (); | |
9878760c | 2280 | } |
8f75773e | 2281 | |
effa5d5d | 2282 | /* Returns the constant for the splat instruction, if exists. */ |
452a7d36 HP |
2283 | |
2284 | static int | |
2285 | easy_vector_splat_const (int cst, enum machine_mode mode) | |
2286 | { | |
f676971a | 2287 | switch (mode) |
452a7d36 HP |
2288 | { |
2289 | case V4SImode: | |
f676971a EC |
2290 | if (EASY_VECTOR_15 (cst) |
2291 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
2292 | return cst; |
2293 | if ((cst & 0xffff) != ((cst >> 16) & 0xffff)) | |
2294 | break; | |
2295 | cst = cst >> 16; | |
c4ad648e AM |
2296 | /* Fall thru */ |
2297 | ||
452a7d36 | 2298 | case V8HImode: |
f676971a EC |
2299 | if (EASY_VECTOR_15 (cst) |
2300 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
2301 | return cst; |
2302 | if ((cst & 0xff) != ((cst >> 8) & 0xff)) | |
2303 | break; | |
2304 | cst = cst >> 8; | |
c4ad648e AM |
2305 | /* Fall thru */ |
2306 | ||
452a7d36 | 2307 | case V16QImode: |
c4ad648e AM |
2308 | if (EASY_VECTOR_15 (cst) |
2309 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
2310 | return cst; | |
f676971a | 2311 | default: |
452a7d36 HP |
2312 | break; |
2313 | } | |
2314 | return 0; | |
2315 | } | |
2316 | ||
2317 | ||
72ac76be | 2318 | /* Return nonzero if all elements of a vector have the same value. */ |
69ef87e2 AH |
2319 | |
2320 | static int | |
a2369ed3 | 2321 | easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d744e06e AH |
2322 | { |
2323 | int units, i, cst; | |
2324 | ||
2325 | units = CONST_VECTOR_NUNITS (op); | |
2326 | ||
2327 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
2328 | for (i = 1; i < units; ++i) | |
2329 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
2330 | break; | |
452a7d36 | 2331 | if (i == units && easy_vector_splat_const (cst, mode)) |
d744e06e AH |
2332 | return 1; |
2333 | return 0; | |
2334 | } | |
2335 | ||
2336 | /* Return 1 if the operand is a CONST_INT and can be put into a | |
2337 | register without using memory. */ | |
2338 | ||
2339 | int | |
a2369ed3 | 2340 | easy_vector_constant (rtx op, enum machine_mode mode) |
69ef87e2 | 2341 | { |
d744e06e | 2342 | int cst, cst2; |
69ef87e2 | 2343 | |
d744e06e AH |
2344 | if (GET_CODE (op) != CONST_VECTOR |
2345 | || (!TARGET_ALTIVEC | |
2346 | && !TARGET_SPE)) | |
69ef87e2 AH |
2347 | return 0; |
2348 | ||
d744e06e AH |
2349 | if (zero_constant (op, mode) |
2350 | && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
2351 | || (TARGET_SPE && SPE_VECTOR_MODE (mode)))) | |
2352 | return 1; | |
69ef87e2 | 2353 | |
d744e06e AH |
2354 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) |
2355 | return 0; | |
2356 | ||
f5119d10 AH |
2357 | if (TARGET_SPE && mode == V1DImode) |
2358 | return 0; | |
2359 | ||
d744e06e AH |
2360 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); |
2361 | cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
2362 | ||
2363 | /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
2364 | li r0, CONSTANT1 | |
2365 | evmergelo r0, r0, r0 | |
2366 | li r0, CONSTANT2 | |
2367 | ||
2368 | I don't know how efficient it would be to allow bigger constants, | |
2369 | considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
2370 | instructions is better than a 64-bit memory load, but I don't | |
2371 | have the e500 timing specs. */ | |
2372 | if (TARGET_SPE && mode == V2SImode | |
2373 | && cst >= -0x7fff && cst <= 0x7fff | |
f5119d10 | 2374 | && cst2 >= -0x7fff && cst2 <= 0x7fff) |
d744e06e AH |
2375 | return 1; |
2376 | ||
f676971a | 2377 | if (TARGET_ALTIVEC |
452a7d36 HP |
2378 | && easy_vector_same (op, mode)) |
2379 | { | |
2380 | cst = easy_vector_splat_const (cst, mode); | |
f676971a | 2381 | if (EASY_VECTOR_15_ADD_SELF (cst) |
452a7d36 HP |
2382 | || EASY_VECTOR_15 (cst)) |
2383 | return 1; | |
f676971a | 2384 | } |
d744e06e AH |
2385 | return 0; |
2386 | } | |
2387 | ||
2388 | /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */ | |
2389 | ||
2390 | int | |
a2369ed3 | 2391 | easy_vector_constant_add_self (rtx op, enum machine_mode mode) |
d744e06e AH |
2392 | { |
2393 | int cst; | |
452a7d36 HP |
2394 | if (TARGET_ALTIVEC |
2395 | && GET_CODE (op) == CONST_VECTOR | |
2396 | && easy_vector_same (op, mode)) | |
2397 | { | |
2398 | cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode); | |
2399 | if (EASY_VECTOR_15_ADD_SELF (cst)) | |
f676971a | 2400 | return 1; |
452a7d36 HP |
2401 | } |
2402 | return 0; | |
2403 | } | |
d744e06e | 2404 | |
452a7d36 | 2405 | /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */ |
d744e06e | 2406 | |
f676971a | 2407 | rtx |
452a7d36 HP |
2408 | gen_easy_vector_constant_add_self (rtx op) |
2409 | { | |
2410 | int i, units; | |
2411 | rtvec v; | |
2412 | units = GET_MODE_NUNITS (GET_MODE (op)); | |
2413 | v = rtvec_alloc (units); | |
2414 | ||
2415 | for (i = 0; i < units; i++) | |
f676971a | 2416 | RTVEC_ELT (v, i) = |
452a7d36 HP |
2417 | GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1); |
2418 | return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v); | |
d744e06e AH |
2419 | } |
2420 | ||
2421 | const char * | |
a2369ed3 | 2422 | output_vec_const_move (rtx *operands) |
d744e06e AH |
2423 | { |
2424 | int cst, cst2; | |
2425 | enum machine_mode mode; | |
2426 | rtx dest, vec; | |
2427 | ||
2428 | dest = operands[0]; | |
2429 | vec = operands[1]; | |
69ef87e2 | 2430 | |
d744e06e AH |
2431 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
2432 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
2433 | mode = GET_MODE (dest); | |
69ef87e2 | 2434 | |
d744e06e AH |
2435 | if (TARGET_ALTIVEC) |
2436 | { | |
2437 | if (zero_constant (vec, mode)) | |
2438 | return "vxor %0,%0,%0"; | |
ce1f50b2 | 2439 | else if (easy_vector_constant (vec, mode)) |
98ef3137 | 2440 | { |
d744e06e AH |
2441 | operands[1] = GEN_INT (cst); |
2442 | switch (mode) | |
2443 | { | |
2444 | case V4SImode: | |
452a7d36 | 2445 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2446 | { |
2447 | operands[1] = GEN_INT (cst); | |
2448 | return "vspltisw %0,%1"; | |
2449 | } | |
452a7d36 HP |
2450 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2451 | return "#"; | |
ce1f50b2 | 2452 | cst = cst >> 16; |
c4ad648e AM |
2453 | /* Fall thru */ |
2454 | ||
d744e06e | 2455 | case V8HImode: |
452a7d36 | 2456 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2457 | { |
2458 | operands[1] = GEN_INT (cst); | |
2459 | return "vspltish %0,%1"; | |
2460 | } | |
452a7d36 HP |
2461 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2462 | return "#"; | |
ce1f50b2 | 2463 | cst = cst >> 8; |
c4ad648e AM |
2464 | /* Fall thru */ |
2465 | ||
d744e06e | 2466 | case V16QImode: |
452a7d36 | 2467 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2468 | { |
2469 | operands[1] = GEN_INT (cst); | |
2470 | return "vspltisb %0,%1"; | |
2471 | } | |
452a7d36 HP |
2472 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2473 | return "#"; | |
c4ad648e | 2474 | |
d744e06e AH |
2475 | default: |
2476 | abort (); | |
2477 | } | |
98ef3137 | 2478 | } |
d744e06e AH |
2479 | else |
2480 | abort (); | |
69ef87e2 AH |
2481 | } |
2482 | ||
d744e06e AH |
2483 | if (TARGET_SPE) |
2484 | { | |
2485 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
2486 | pattern of V1DI, V4HI, and V2SF. | |
2487 | ||
c1207243 | 2488 | FIXME: We should probably return # and add post reload |
c4ad648e | 2489 | splitters for these, but this way is so easy ;-). */ |
d744e06e AH |
2490 | operands[1] = GEN_INT (cst); |
2491 | operands[2] = GEN_INT (cst2); | |
2492 | if (cst == cst2) | |
2493 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
2494 | else | |
2495 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
2496 | } | |
2497 | ||
2498 | abort (); | |
69ef87e2 AH |
2499 | } |
2500 | ||
2501 | /* Return 1 if the operand is the constant 0. This works for scalars | |
2502 | as well as vectors. */ | |
2503 | int | |
a2369ed3 | 2504 | zero_constant (rtx op, enum machine_mode mode) |
69ef87e2 AH |
2505 | { |
2506 | return op == CONST0_RTX (mode); | |
2507 | } | |
2508 | ||
50a0b056 GK |
2509 | /* Return 1 if the operand is 0.0. */ |
2510 | int | |
a2369ed3 | 2511 | zero_fp_constant (rtx op, enum machine_mode mode) |
50a0b056 GK |
2512 | { |
2513 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
2514 | } | |
2515 | ||
a4f6c312 SS |
2516 | /* Return 1 if the operand is in volatile memory. Note that during |
2517 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
2518 | volatile memory references. So this function allows us to |
2519 | recognize volatile references where its safe. */ | |
2520 | ||
2521 | int | |
a2369ed3 | 2522 | volatile_mem_operand (rtx op, enum machine_mode mode) |
b6c9286a MM |
2523 | { |
2524 | if (GET_CODE (op) != MEM) | |
2525 | return 0; | |
2526 | ||
2527 | if (!MEM_VOLATILE_P (op)) | |
2528 | return 0; | |
2529 | ||
2530 | if (mode != GET_MODE (op)) | |
2531 | return 0; | |
2532 | ||
2533 | if (reload_completed) | |
2534 | return memory_operand (op, mode); | |
2535 | ||
2536 | if (reload_in_progress) | |
2537 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
2538 | ||
2539 | return memory_address_p (mode, XEXP (op, 0)); | |
2540 | } | |
2541 | ||
97f6e72f | 2542 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
2543 | |
2544 | int | |
a2369ed3 | 2545 | offsettable_mem_operand (rtx op, enum machine_mode mode) |
914c2e77 | 2546 | { |
97f6e72f | 2547 | return ((GET_CODE (op) == MEM) |
677a9668 | 2548 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 2549 | mode, XEXP (op, 0))); |
914c2e77 RK |
2550 | } |
2551 | ||
9878760c RK |
2552 | /* Return 1 if the operand is either an easy FP constant (see above) or |
2553 | memory. */ | |
2554 | ||
2555 | int | |
a2369ed3 | 2556 | mem_or_easy_const_operand (rtx op, enum machine_mode mode) |
9878760c RK |
2557 | { |
2558 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
2559 | } | |
2560 | ||
2561 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 2562 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
2563 | |
2564 | int | |
a2369ed3 | 2565 | add_operand (rtx op, enum machine_mode mode) |
9878760c | 2566 | { |
2bfcf297 | 2567 | if (GET_CODE (op) == CONST_INT) |
e72247f4 DE |
2568 | return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
2569 | || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
2bfcf297 DB |
2570 | |
2571 | return gpc_reg_operand (op, mode); | |
9878760c RK |
2572 | } |
2573 | ||
dcfedcd0 RK |
2574 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
2575 | ||
2576 | int | |
a2369ed3 | 2577 | non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
2578 | { |
2579 | return (GET_CODE (op) == CONST_INT | |
e72247f4 DE |
2580 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
2581 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
dcfedcd0 RK |
2582 | } |
2583 | ||
9878760c RK |
2584 | /* Return 1 if the operand is a non-special register or a constant that |
2585 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
2586 | ||
2587 | int | |
a2369ed3 | 2588 | logical_operand (rtx op, enum machine_mode mode) |
9878760c | 2589 | { |
40501e5f | 2590 | HOST_WIDE_INT opl, oph; |
1d328b19 | 2591 | |
dfbdccdb GK |
2592 | if (gpc_reg_operand (op, mode)) |
2593 | return 1; | |
1d328b19 | 2594 | |
dfbdccdb | 2595 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
2596 | { |
2597 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
2598 | ||
2599 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
2600 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
2601 | return 0; | |
2602 | #endif | |
2603 | } | |
dfbdccdb GK |
2604 | else if (GET_CODE (op) == CONST_DOUBLE) |
2605 | { | |
1d328b19 | 2606 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 2607 | abort (); |
1d328b19 GK |
2608 | |
2609 | opl = CONST_DOUBLE_LOW (op); | |
2610 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 2611 | if (oph != 0) |
38886f37 | 2612 | return 0; |
dfbdccdb GK |
2613 | } |
2614 | else | |
2615 | return 0; | |
1d328b19 | 2616 | |
40501e5f AM |
2617 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
2618 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
2619 | } |
2620 | ||
dcfedcd0 | 2621 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 2622 | above), but could be split into one. */ |
dcfedcd0 RK |
2623 | |
2624 | int | |
a2369ed3 | 2625 | non_logical_cint_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 2626 | { |
dfbdccdb | 2627 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
2628 | && ! logical_operand (op, mode) |
2629 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
2630 | } |
2631 | ||
19ba8161 | 2632 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
2633 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
2634 | Reject all ones and all zeros, since these should have been optimized | |
2635 | away and confuse the making of MB and ME. */ | |
2636 | ||
2637 | int | |
a2369ed3 | 2638 | mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 2639 | { |
02071907 | 2640 | HOST_WIDE_INT c, lsb; |
9878760c | 2641 | |
19ba8161 DE |
2642 | if (GET_CODE (op) != CONST_INT) |
2643 | return 0; | |
2644 | ||
2645 | c = INTVAL (op); | |
2646 | ||
57deb3a1 AM |
2647 | /* Fail in 64-bit mode if the mask wraps around because the upper |
2648 | 32-bits of the mask will all be 1s, contrary to GCC's internal view. */ | |
2649 | if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001) | |
2650 | return 0; | |
2651 | ||
c5059423 AM |
2652 | /* We don't change the number of transitions by inverting, |
2653 | so make sure we start with the LS bit zero. */ | |
2654 | if (c & 1) | |
2655 | c = ~c; | |
2656 | ||
2657 | /* Reject all zeros or all ones. */ | |
2658 | if (c == 0) | |
9878760c RK |
2659 | return 0; |
2660 | ||
c5059423 AM |
2661 | /* Find the first transition. */ |
2662 | lsb = c & -c; | |
2663 | ||
2664 | /* Invert to look for a second transition. */ | |
2665 | c = ~c; | |
9878760c | 2666 | |
c5059423 AM |
2667 | /* Erase first transition. */ |
2668 | c &= -lsb; | |
9878760c | 2669 | |
c5059423 AM |
2670 | /* Find the second transition (if any). */ |
2671 | lsb = c & -c; | |
2672 | ||
2673 | /* Match if all the bits above are 1's (or c is zero). */ | |
2674 | return c == -lsb; | |
9878760c RK |
2675 | } |
2676 | ||
0ba1b2ff AM |
2677 | /* Return 1 for the PowerPC64 rlwinm corner case. */ |
2678 | ||
2679 | int | |
a2369ed3 | 2680 | mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ba1b2ff AM |
2681 | { |
2682 | HOST_WIDE_INT c, lsb; | |
2683 | ||
2684 | if (GET_CODE (op) != CONST_INT) | |
2685 | return 0; | |
2686 | ||
2687 | c = INTVAL (op); | |
2688 | ||
2689 | if ((c & 0x80000001) != 0x80000001) | |
2690 | return 0; | |
2691 | ||
2692 | c = ~c; | |
2693 | if (c == 0) | |
2694 | return 0; | |
2695 | ||
2696 | lsb = c & -c; | |
2697 | c = ~c; | |
2698 | c &= -lsb; | |
2699 | lsb = c & -c; | |
2700 | return c == -lsb; | |
2701 | } | |
2702 | ||
a260abc9 DE |
2703 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
2704 | It is if there are no more than one 1->0 or 0->1 transitions. | |
0ba1b2ff AM |
2705 | Reject all zeros, since zero should have been optimized away and |
2706 | confuses the making of MB and ME. */ | |
9878760c RK |
2707 | |
2708 | int | |
a2369ed3 | 2709 | mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
a260abc9 DE |
2710 | { |
2711 | if (GET_CODE (op) == CONST_INT) | |
2712 | { | |
02071907 | 2713 | HOST_WIDE_INT c, lsb; |
a260abc9 | 2714 | |
c5059423 | 2715 | c = INTVAL (op); |
a260abc9 | 2716 | |
0ba1b2ff | 2717 | /* Reject all zeros. */ |
c5059423 | 2718 | if (c == 0) |
e2c953b6 DE |
2719 | return 0; |
2720 | ||
0ba1b2ff AM |
2721 | /* We don't change the number of transitions by inverting, |
2722 | so make sure we start with the LS bit zero. */ | |
2723 | if (c & 1) | |
2724 | c = ~c; | |
2725 | ||
c5059423 AM |
2726 | /* Find the transition, and check that all bits above are 1's. */ |
2727 | lsb = c & -c; | |
e3981aab DE |
2728 | |
2729 | /* Match if all the bits above are 1's (or c is zero). */ | |
c5059423 | 2730 | return c == -lsb; |
e2c953b6 | 2731 | } |
0ba1b2ff AM |
2732 | return 0; |
2733 | } | |
2734 | ||
e1e2e653 NS |
2735 | static int |
2736 | mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED, | |
2737 | bool allow_one) | |
0ba1b2ff AM |
2738 | { |
2739 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 2740 | { |
0ba1b2ff | 2741 | HOST_WIDE_INT c, lsb; |
e1e2e653 NS |
2742 | bool one_ok; |
2743 | ||
0ba1b2ff | 2744 | c = INTVAL (op); |
a260abc9 | 2745 | |
0ba1b2ff AM |
2746 | /* Disallow all zeros. */ |
2747 | if (c == 0) | |
2748 | return 0; | |
a260abc9 | 2749 | |
e1e2e653 NS |
2750 | /* We can use a single rlwinm insn if no upper bits of C are set |
2751 | AND there are zero, one or two transitions in the _whole_ of | |
2752 | C. */ | |
2753 | one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff); | |
2754 | ||
0ba1b2ff AM |
2755 | /* We don't change the number of transitions by inverting, |
2756 | so make sure we start with the LS bit zero. */ | |
2757 | if (c & 1) | |
2758 | c = ~c; | |
a260abc9 | 2759 | |
0ba1b2ff AM |
2760 | /* Find the first transition. */ |
2761 | lsb = c & -c; | |
a260abc9 | 2762 | |
0ba1b2ff AM |
2763 | /* Invert to look for a second transition. */ |
2764 | c = ~c; | |
2765 | ||
2766 | /* Erase first transition. */ | |
2767 | c &= -lsb; | |
2768 | ||
2769 | /* Find the second transition. */ | |
2770 | lsb = c & -c; | |
2771 | ||
2772 | /* Invert to look for a third transition. */ | |
2773 | c = ~c; | |
2774 | ||
2775 | /* Erase second transition. */ | |
2776 | c &= -lsb; | |
2777 | ||
e1e2e653 NS |
2778 | if (one_ok && !(allow_one || c)) |
2779 | return 0; | |
2780 | ||
0ba1b2ff AM |
2781 | /* Find the third transition (if any). */ |
2782 | lsb = c & -c; | |
2783 | ||
2784 | /* Match if all the bits above are 1's (or c is zero). */ | |
2785 | return c == -lsb; | |
2786 | } | |
2787 | return 0; | |
2788 | } | |
2789 | ||
e1e2e653 NS |
2790 | /* Like mask64_operand, but allow up to three transitions. This |
2791 | predicate is used by insn patterns that generate two rldicl or | |
2792 | rldicr machine insns. */ | |
2793 | int mask64_2_operand (rtx op, enum machine_mode mode) | |
2794 | { | |
2795 | return mask64_1or2_operand (op, mode, false); | |
2796 | } | |
2797 | ||
0ba1b2ff AM |
2798 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to |
2799 | implement ANDing by the mask IN. */ | |
2800 | void | |
a2369ed3 | 2801 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
2802 | { |
2803 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2804 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2805 | int shift; | |
2806 | ||
2807 | if (GET_CODE (in) != CONST_INT) | |
2808 | abort (); | |
2809 | ||
2810 | c = INTVAL (in); | |
2811 | if (c & 1) | |
2812 | { | |
2813 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2814 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2815 | is at the MS end and can be cleared with an rldicl mask. We then | |
2816 | rotate back and clear off the MS ^^ group of zeros with a | |
2817 | second rldicl. */ | |
2818 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2819 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2820 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2821 | c = ~c; /* c == 0x00fff000000fffff */ | |
2822 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2823 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2824 | c = ~c; /* c == 0xff000fffffffffff */ | |
2825 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2826 | shift = 0; | |
2827 | while ((lsb >>= 1) != 0) | |
2828 | shift++; /* shift == 44 on exit from loop */ | |
2829 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2830 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2831 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2832 | } |
2833 | else | |
0ba1b2ff AM |
2834 | { |
2835 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2836 | is to rotate the word so that the ^^^ middle group of zeros | |
2837 | is at the LS end and can be cleared with an rldicr mask. We then | |
2838 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2839 | a second rldicr. */ | |
2840 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2841 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2842 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2843 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2844 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2845 | c = ~c; /* c == 0xff000fffffffffff */ | |
2846 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2847 | shift = 0; | |
2848 | while ((lsb >>= 1) != 0) | |
2849 | shift++; /* shift == 44 on exit from loop */ | |
2850 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2851 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2852 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2853 | } | |
2854 | ||
2855 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2856 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2857 | out[0] = GEN_INT (64 - shift); | |
2858 | out[1] = GEN_INT (m1); | |
2859 | out[2] = GEN_INT (shift); | |
2860 | out[3] = GEN_INT (m2); | |
2861 | #else | |
045572c7 GK |
2862 | (void)in; |
2863 | (void)out; | |
0ba1b2ff AM |
2864 | abort (); |
2865 | #endif | |
a260abc9 DE |
2866 | } |
2867 | ||
2868 | /* Return 1 if the operand is either a non-special register or a constant | |
2869 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
2870 | ||
2871 | int | |
a2369ed3 | 2872 | and64_operand (rtx op, enum machine_mode mode) |
9878760c | 2873 | { |
a4f6c312 | 2874 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2875 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
2876 | ||
2877 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
2878 | } |
2879 | ||
0ba1b2ff AM |
2880 | /* Like the above, but also match constants that can be implemented |
2881 | with two rldicl or rldicr insns. */ | |
2882 | ||
2883 | int | |
a2369ed3 | 2884 | and64_2_operand (rtx op, enum machine_mode mode) |
0ba1b2ff | 2885 | { |
a3c9585f | 2886 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
e1e2e653 | 2887 | return gpc_reg_operand (op, mode) || mask64_1or2_operand (op, mode, true); |
0ba1b2ff | 2888 | |
e1e2e653 | 2889 | return logical_operand (op, mode) || mask64_1or2_operand (op, mode, true); |
0ba1b2ff AM |
2890 | } |
2891 | ||
a260abc9 DE |
2892 | /* Return 1 if the operand is either a non-special register or a |
2893 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
2894 | |
2895 | int | |
a2369ed3 | 2896 | and_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 2897 | { |
a4f6c312 | 2898 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2899 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
2900 | ||
2901 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
2902 | } |
2903 | ||
9878760c RK |
2904 | /* Return 1 if the operand is a general register or memory operand. */ |
2905 | ||
2906 | int | |
a2369ed3 | 2907 | reg_or_mem_operand (rtx op, enum machine_mode mode) |
9878760c | 2908 | { |
b6c9286a MM |
2909 | return (gpc_reg_operand (op, mode) |
2910 | || memory_operand (op, mode) | |
4c81e946 | 2911 | || macho_lo_sum_memory_operand (op, mode) |
b6c9286a | 2912 | || volatile_mem_operand (op, mode)); |
9878760c RK |
2913 | } |
2914 | ||
a7a813f7 | 2915 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 2916 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
2917 | instruction. */ |
2918 | ||
2919 | int | |
a2369ed3 | 2920 | lwa_operand (rtx op, enum machine_mode mode) |
a7a813f7 RK |
2921 | { |
2922 | rtx inner = op; | |
2923 | ||
2924 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
2925 | inner = SUBREG_REG (inner); | |
f676971a | 2926 | |
a7a813f7 RK |
2927 | return gpc_reg_operand (inner, mode) |
2928 | || (memory_operand (inner, mode) | |
2929 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
2930 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
2931 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
2932 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
2933 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
2934 | } |
2935 | ||
cc4d5fec JH |
2936 | /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */ |
2937 | ||
2938 | int | |
a2369ed3 | 2939 | symbol_ref_operand (rtx op, enum machine_mode mode) |
cc4d5fec JH |
2940 | { |
2941 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2942 | return 0; | |
2943 | ||
473f51b6 DE |
2944 | return (GET_CODE (op) == SYMBOL_REF |
2945 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))); | |
cc4d5fec JH |
2946 | } |
2947 | ||
9878760c | 2948 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
cc4d5fec | 2949 | to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */ |
9878760c RK |
2950 | |
2951 | int | |
a2369ed3 | 2952 | call_operand (rtx op, enum machine_mode mode) |
9878760c RK |
2953 | { |
2954 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2955 | return 0; | |
2956 | ||
2957 | return (GET_CODE (op) == SYMBOL_REF | |
cc4d5fec JH |
2958 | || (GET_CODE (op) == REG |
2959 | && (REGNO (op) == LINK_REGISTER_REGNUM | |
2960 | || REGNO (op) == COUNT_REGISTER_REGNUM | |
2961 | || REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
9878760c RK |
2962 | } |
2963 | ||
2af3d377 | 2964 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
d1908feb | 2965 | this file. */ |
2af3d377 RK |
2966 | |
2967 | int | |
f676971a | 2968 | current_file_function_operand (rtx op, |
c4ad648e | 2969 | enum machine_mode mode ATTRIBUTE_UNUSED) |
2af3d377 | 2970 | { |
473f51b6 DE |
2971 | return (GET_CODE (op) == SYMBOL_REF |
2972 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
2973 | && (SYMBOL_REF_LOCAL_P (op) | |
2974 | || (op == XEXP (DECL_RTL (current_function_decl), 0)))); | |
2af3d377 RK |
2975 | } |
2976 | ||
9878760c RK |
2977 | /* Return 1 if this operand is a valid input for a move insn. */ |
2978 | ||
2979 | int | |
a2369ed3 | 2980 | input_operand (rtx op, enum machine_mode mode) |
9878760c | 2981 | { |
eb4e8003 | 2982 | /* Memory is always valid. */ |
9878760c RK |
2983 | if (memory_operand (op, mode)) |
2984 | return 1; | |
2985 | ||
eb4e8003 RK |
2986 | /* For floating-point, easy constants are valid. */ |
2987 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2988 | && CONSTANT_P (op) | |
2989 | && easy_fp_constant (op, mode)) | |
2990 | return 1; | |
2991 | ||
4e74d8ec MM |
2992 | /* Allow any integer constant. */ |
2993 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 2994 | && (GET_CODE (op) == CONST_INT |
e675f625 | 2995 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
2996 | return 1; |
2997 | ||
d744e06e AH |
2998 | /* Allow easy vector constants. */ |
2999 | if (GET_CODE (op) == CONST_VECTOR | |
3000 | && easy_vector_constant (op, mode)) | |
3001 | return 1; | |
3002 | ||
eb4e8003 RK |
3003 | /* For floating-point or multi-word mode, the only remaining valid type |
3004 | is a register. */ | |
9878760c RK |
3005 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
3006 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 3007 | return register_operand (op, mode); |
9878760c | 3008 | |
88fe15a1 RK |
3009 | /* The only cases left are integral modes one word or smaller (we |
3010 | do not get called for MODE_CC values). These can be in any | |
3011 | register. */ | |
3012 | if (register_operand (op, mode)) | |
a8b3aeda | 3013 | return 1; |
88fe15a1 | 3014 | |
84cf9dda | 3015 | /* A SYMBOL_REF referring to the TOC is valid. */ |
4d588c14 | 3016 | if (legitimate_constant_pool_address_p (op)) |
84cf9dda RK |
3017 | return 1; |
3018 | ||
9ebbca7d | 3019 | /* A constant pool expression (relative to the TOC) is valid */ |
4d588c14 | 3020 | if (toc_relative_expr_p (op)) |
b6c9286a MM |
3021 | return 1; |
3022 | ||
88228c4b MM |
3023 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
3024 | to be valid. */ | |
f607bc57 | 3025 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
3026 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
3027 | && small_data_operand (op, Pmode)) | |
3028 | return 1; | |
3029 | ||
042259f2 | 3030 | return 0; |
9878760c | 3031 | } |
7509c759 | 3032 | |
95727fb8 AP |
3033 | |
3034 | /* Darwin, AIX increases natural record alignment to doubleword if the first | |
3035 | field is an FP double while the FP fields remain word aligned. */ | |
3036 | ||
19d66194 | 3037 | unsigned int |
95727fb8 AP |
3038 | rs6000_special_round_type_align (tree type, int computed, int specified) |
3039 | { | |
3040 | tree field = TYPE_FIELDS (type); | |
95727fb8 AP |
3041 | |
3042 | /* Skip all the static variables only if ABI is greater than | |
71cc389b | 3043 | 1 or equal to 0. */ |
3ce5437a | 3044 | while (field != NULL && TREE_CODE (field) == VAR_DECL) |
95727fb8 AP |
3045 | field = TREE_CHAIN (field); |
3046 | ||
3ce5437a | 3047 | if (field == NULL || field == type || DECL_MODE (field) != DFmode) |
95727fb8 AP |
3048 | return MAX (computed, specified); |
3049 | ||
3050 | return MAX (MAX (computed, specified), 64); | |
3051 | } | |
3052 | ||
a4f6c312 | 3053 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
3054 | |
3055 | int | |
f676971a | 3056 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
a2369ed3 | 3057 | enum machine_mode mode ATTRIBUTE_UNUSED) |
7509c759 | 3058 | { |
38c1f2d7 | 3059 | #if TARGET_ELF |
5f59ecb7 | 3060 | rtx sym_ref; |
7509c759 | 3061 | |
d9407988 | 3062 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 3063 | return 0; |
a54d04b7 | 3064 | |
f607bc57 | 3065 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
3066 | return 0; |
3067 | ||
88228c4b MM |
3068 | if (GET_CODE (op) == SYMBOL_REF) |
3069 | sym_ref = op; | |
3070 | ||
3071 | else if (GET_CODE (op) != CONST | |
3072 | || GET_CODE (XEXP (op, 0)) != PLUS | |
3073 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
3074 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
3075 | return 0; |
3076 | ||
88228c4b | 3077 | else |
dbf55e53 MM |
3078 | { |
3079 | rtx sum = XEXP (op, 0); | |
3080 | HOST_WIDE_INT summand; | |
3081 | ||
3082 | /* We have to be careful here, because it is the referenced address | |
c4ad648e | 3083 | that must be 32k from _SDA_BASE_, not just the symbol. */ |
dbf55e53 | 3084 | summand = INTVAL (XEXP (sum, 1)); |
307b599c | 3085 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
dbf55e53 MM |
3086 | return 0; |
3087 | ||
3088 | sym_ref = XEXP (sum, 0); | |
3089 | } | |
88228c4b | 3090 | |
20bfcd69 | 3091 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
3092 | #else |
3093 | return 0; | |
3094 | #endif | |
7509c759 | 3095 | } |
46c07df8 | 3096 | |
d2288d5d HP |
3097 | /* Return true, if operand is a memory operand and has a |
3098 | displacement divisible by 4. */ | |
3099 | ||
3100 | int | |
3101 | word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
3102 | { | |
3103 | rtx addr; | |
3104 | int off = 0; | |
3105 | ||
3106 | if (!memory_operand (op, mode)) | |
3107 | return 0; | |
3108 | ||
3109 | addr = XEXP (op, 0); | |
3110 | if (GET_CODE (addr) == PLUS | |
3111 | && GET_CODE (XEXP (addr, 0)) == REG | |
3112 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3113 | off = INTVAL (XEXP (addr, 1)); | |
3114 | ||
3115 | return (off % 4) == 0; | |
3116 | } | |
3117 | ||
3a1f863f | 3118 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 3119 | |
3a1f863f DE |
3120 | bool |
3121 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 3122 | { |
3a1f863f DE |
3123 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
3124 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
3125 | } |
3126 | ||
9ebbca7d | 3127 | \f |
4d588c14 RH |
3128 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
3129 | ||
f676971a EC |
3130 | static int |
3131 | constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) | |
9ebbca7d | 3132 | { |
f676971a | 3133 | switch (GET_CODE(op)) |
9ebbca7d GK |
3134 | { |
3135 | case SYMBOL_REF: | |
c4501e62 JJ |
3136 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
3137 | return 0; | |
3138 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
3139 | { |
3140 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
3141 | { | |
3142 | *have_sym = 1; | |
3143 | return 1; | |
3144 | } | |
3145 | else | |
3146 | return 0; | |
3147 | } | |
3148 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
3149 | { | |
3150 | *have_toc = 1; | |
3151 | return 1; | |
3152 | } | |
3153 | else | |
3154 | return 0; | |
9ebbca7d GK |
3155 | case PLUS: |
3156 | case MINUS: | |
c1f11548 DE |
3157 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
3158 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 3159 | case CONST: |
a4f6c312 | 3160 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 3161 | case CONST_INT: |
a4f6c312 | 3162 | return 1; |
9ebbca7d | 3163 | default: |
a4f6c312 | 3164 | return 0; |
9ebbca7d GK |
3165 | } |
3166 | } | |
3167 | ||
4d588c14 | 3168 | static bool |
a2369ed3 | 3169 | constant_pool_expr_p (rtx op) |
9ebbca7d GK |
3170 | { |
3171 | int have_sym = 0; | |
3172 | int have_toc = 0; | |
3173 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
3174 | } | |
3175 | ||
4d588c14 | 3176 | static bool |
a2369ed3 | 3177 | toc_relative_expr_p (rtx op) |
9ebbca7d | 3178 | { |
4d588c14 RH |
3179 | int have_sym = 0; |
3180 | int have_toc = 0; | |
3181 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
3182 | } | |
3183 | ||
4d588c14 | 3184 | bool |
a2369ed3 | 3185 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
3186 | { |
3187 | return (TARGET_TOC | |
3188 | && GET_CODE (x) == PLUS | |
3189 | && GET_CODE (XEXP (x, 0)) == REG | |
3190 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
3191 | && constant_pool_expr_p (XEXP (x, 1))); | |
3192 | } | |
3193 | ||
3194 | static bool | |
a2369ed3 | 3195 | legitimate_small_data_p (enum machine_mode mode, rtx x) |
4d588c14 RH |
3196 | { |
3197 | return (DEFAULT_ABI == ABI_V4 | |
3198 | && !flag_pic && !TARGET_TOC | |
3199 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
3200 | && small_data_operand (x, mode)); | |
3201 | } | |
3202 | ||
60cdabab DE |
3203 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
3204 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
3205 | ||
76d2b81d DJ |
3206 | bool |
3207 | rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) | |
4d588c14 RH |
3208 | { |
3209 | unsigned HOST_WIDE_INT offset, extra; | |
3210 | ||
3211 | if (GET_CODE (x) != PLUS) | |
3212 | return false; | |
3213 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3214 | return false; | |
3215 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
3216 | return false; | |
60cdabab DE |
3217 | if (legitimate_constant_pool_address_p (x)) |
3218 | return true; | |
4d588c14 RH |
3219 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
3220 | return false; | |
3221 | ||
3222 | offset = INTVAL (XEXP (x, 1)); | |
3223 | extra = 0; | |
3224 | switch (mode) | |
3225 | { | |
3226 | case V16QImode: | |
3227 | case V8HImode: | |
3228 | case V4SFmode: | |
3229 | case V4SImode: | |
3230 | /* AltiVec vector modes. Only reg+reg addressing is valid here, | |
3231 | which leaves the only valid constant offset of zero, which by | |
3232 | canonicalization rules is also invalid. */ | |
3233 | return false; | |
3234 | ||
3235 | case V4HImode: | |
3236 | case V2SImode: | |
3237 | case V1DImode: | |
3238 | case V2SFmode: | |
3239 | /* SPE vector modes. */ | |
3240 | return SPE_CONST_OFFSET_OK (offset); | |
3241 | ||
3242 | case DFmode: | |
4d4cbc0e AH |
3243 | if (TARGET_E500_DOUBLE) |
3244 | return SPE_CONST_OFFSET_OK (offset); | |
3245 | ||
4d588c14 | 3246 | case DImode: |
3364872d | 3247 | if (mode == DFmode || !TARGET_POWERPC64) |
4d588c14 RH |
3248 | extra = 4; |
3249 | else if (offset & 3) | |
3250 | return false; | |
3251 | break; | |
3252 | ||
3253 | case TFmode: | |
3254 | case TImode: | |
3364872d | 3255 | if (mode == TFmode || !TARGET_POWERPC64) |
4d588c14 RH |
3256 | extra = 12; |
3257 | else if (offset & 3) | |
3258 | return false; | |
3259 | else | |
3260 | extra = 8; | |
3261 | break; | |
3262 | ||
3263 | default: | |
3264 | break; | |
3265 | } | |
3266 | ||
b1917422 AM |
3267 | offset += 0x8000; |
3268 | return (offset < 0x10000) && (offset + extra < 0x10000); | |
4d588c14 RH |
3269 | } |
3270 | ||
3271 | static bool | |
a2369ed3 | 3272 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
3273 | { |
3274 | rtx op0, op1; | |
3275 | ||
3276 | if (GET_CODE (x) != PLUS) | |
3277 | return false; | |
850e8d3d | 3278 | |
4d588c14 RH |
3279 | op0 = XEXP (x, 0); |
3280 | op1 = XEXP (x, 1); | |
3281 | ||
3282 | if (!REG_P (op0) || !REG_P (op1)) | |
3283 | return false; | |
3284 | ||
3285 | return ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
3286 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
3287 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
3288 | && INT_REG_OK_FOR_INDEX_P (op0, strict))); | |
9ebbca7d GK |
3289 | } |
3290 | ||
4d588c14 | 3291 | static inline bool |
a2369ed3 | 3292 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
3293 | { |
3294 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
3295 | } | |
3296 | ||
4c81e946 FJ |
3297 | static bool |
3298 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) | |
3299 | { | |
c4ad648e AM |
3300 | if (!TARGET_MACHO || !flag_pic |
3301 | || mode != SImode || GET_CODE(x) != MEM) | |
3302 | return false; | |
3303 | x = XEXP (x, 0); | |
4c81e946 FJ |
3304 | |
3305 | if (GET_CODE (x) != LO_SUM) | |
3306 | return false; | |
3307 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3308 | return false; | |
3309 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
3310 | return false; | |
3311 | x = XEXP (x, 1); | |
3312 | ||
3313 | return CONSTANT_P (x); | |
3314 | } | |
3315 | ||
4d588c14 | 3316 | static bool |
a2369ed3 | 3317 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
3318 | { |
3319 | if (GET_CODE (x) != LO_SUM) | |
3320 | return false; | |
3321 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3322 | return false; | |
3323 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
3324 | return false; | |
f82f556d AH |
3325 | if (TARGET_E500_DOUBLE && mode == DFmode) |
3326 | return false; | |
4d588c14 RH |
3327 | x = XEXP (x, 1); |
3328 | ||
8622e235 | 3329 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 3330 | { |
a29077da | 3331 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
3332 | return false; |
3333 | if (TARGET_TOC) | |
3334 | return false; | |
3335 | if (GET_MODE_NUNITS (mode) != 1) | |
3336 | return false; | |
c1e55850 | 3337 | if (GET_MODE_BITSIZE (mode) > 64) |
4d588c14 RH |
3338 | return false; |
3339 | ||
3340 | return CONSTANT_P (x); | |
3341 | } | |
3342 | ||
3343 | return false; | |
3344 | } | |
3345 | ||
3346 | ||
9ebbca7d GK |
3347 | /* Try machine-dependent ways of modifying an illegitimate address |
3348 | to be legitimate. If we find one, return the new, valid address. | |
3349 | This is used from only one place: `memory_address' in explow.c. | |
3350 | ||
a4f6c312 SS |
3351 | OLDX is the address as it was before break_out_memory_refs was |
3352 | called. In some cases it is useful to look at this to decide what | |
3353 | needs to be done. | |
9ebbca7d | 3354 | |
a4f6c312 | 3355 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 3356 | |
a4f6c312 SS |
3357 | It is always safe for this function to do nothing. It exists to |
3358 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
3359 | |
3360 | On RS/6000, first check for the sum of a register with a constant | |
3361 | integer that is out of range. If so, generate code to add the | |
3362 | constant with the low-order 16 bits masked to the register and force | |
3363 | this result into another register (this can be done with `cau'). | |
3364 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
3365 | possibility of bit 16 being a one. | |
3366 | ||
3367 | Then check for the sum of a register and something not constant, try to | |
3368 | load the other things into a register and return the sum. */ | |
4d588c14 | 3369 | |
9ebbca7d | 3370 | rtx |
a2369ed3 DJ |
3371 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
3372 | enum machine_mode mode) | |
0ac081f6 | 3373 | { |
c4501e62 JJ |
3374 | if (GET_CODE (x) == SYMBOL_REF) |
3375 | { | |
3376 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
3377 | if (model != 0) | |
3378 | return rs6000_legitimize_tls_address (x, model); | |
3379 | } | |
3380 | ||
f676971a | 3381 | if (GET_CODE (x) == PLUS |
9ebbca7d GK |
3382 | && GET_CODE (XEXP (x, 0)) == REG |
3383 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3384 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
f676971a | 3385 | { |
9ebbca7d GK |
3386 | HOST_WIDE_INT high_int, low_int; |
3387 | rtx sum; | |
a65c591c DE |
3388 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
3389 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
3390 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
3391 | GEN_INT (high_int)), 0); | |
3392 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
3393 | } | |
f676971a | 3394 | else if (GET_CODE (x) == PLUS |
9ebbca7d GK |
3395 | && GET_CODE (XEXP (x, 0)) == REG |
3396 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 3397 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
3398 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3399 | || TARGET_POWERPC64 | |
4d4cbc0e | 3400 | || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode)) |
9ebbca7d GK |
3401 | && (TARGET_POWERPC64 || mode != DImode) |
3402 | && mode != TImode) | |
3403 | { | |
3404 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3405 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
3406 | } | |
0ac081f6 AH |
3407 | else if (ALTIVEC_VECTOR_MODE (mode)) |
3408 | { | |
3409 | rtx reg; | |
3410 | ||
3411 | /* Make sure both operands are registers. */ | |
3412 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 3413 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
3414 | force_reg (Pmode, XEXP (x, 1))); |
3415 | ||
3416 | reg = force_reg (Pmode, x); | |
3417 | return reg; | |
3418 | } | |
4d4cbc0e AH |
3419 | else if (SPE_VECTOR_MODE (mode) |
3420 | || (TARGET_E500_DOUBLE && mode == DFmode)) | |
a3170dc6 AH |
3421 | { |
3422 | /* We accept [reg + reg] and [reg + OFFSET]. */ | |
3423 | ||
3424 | if (GET_CODE (x) == PLUS) | |
c4ad648e AM |
3425 | { |
3426 | rtx op1 = XEXP (x, 0); | |
3427 | rtx op2 = XEXP (x, 1); | |
a3170dc6 | 3428 | |
c4ad648e | 3429 | op1 = force_reg (Pmode, op1); |
a3170dc6 | 3430 | |
c4ad648e AM |
3431 | if (GET_CODE (op2) != REG |
3432 | && (GET_CODE (op2) != CONST_INT | |
3433 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
3434 | op2 = force_reg (Pmode, op2); | |
a3170dc6 | 3435 | |
c4ad648e AM |
3436 | return gen_rtx_PLUS (Pmode, op1, op2); |
3437 | } | |
a3170dc6 AH |
3438 | |
3439 | return force_reg (Pmode, x); | |
3440 | } | |
f1384257 AM |
3441 | else if (TARGET_ELF |
3442 | && TARGET_32BIT | |
3443 | && TARGET_NO_TOC | |
3444 | && ! flag_pic | |
9ebbca7d | 3445 | && GET_CODE (x) != CONST_INT |
f676971a | 3446 | && GET_CODE (x) != CONST_DOUBLE |
9ebbca7d | 3447 | && CONSTANT_P (x) |
6ac7bf2c GK |
3448 | && GET_MODE_NUNITS (mode) == 1 |
3449 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 3450 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
3451 | { |
3452 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3453 | emit_insn (gen_elf_high (reg, x)); |
3454 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 3455 | } |
ee890fe2 SS |
3456 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
3457 | && ! flag_pic | |
ab82a49f AP |
3458 | #if TARGET_MACHO |
3459 | && ! MACHO_DYNAMIC_NO_PIC_P | |
3460 | #endif | |
ee890fe2 | 3461 | && GET_CODE (x) != CONST_INT |
f676971a | 3462 | && GET_CODE (x) != CONST_DOUBLE |
ee890fe2 | 3463 | && CONSTANT_P (x) |
f82f556d | 3464 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
f676971a | 3465 | && mode != DImode |
ee890fe2 SS |
3466 | && mode != TImode) |
3467 | { | |
3468 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3469 | emit_insn (gen_macho_high (reg, x)); |
3470 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 3471 | } |
f676971a | 3472 | else if (TARGET_TOC |
4d588c14 | 3473 | && constant_pool_expr_p (x) |
a9098fd0 | 3474 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
3475 | { |
3476 | return create_TOC_reference (x); | |
3477 | } | |
3478 | else | |
3479 | return NULL_RTX; | |
3480 | } | |
258bfae2 | 3481 | |
c973d557 JJ |
3482 | /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. |
3483 | We need to emit DTP-relative relocations. */ | |
3484 | ||
3485 | void | |
3486 | rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
3487 | { | |
3488 | switch (size) | |
3489 | { | |
3490 | case 4: | |
3491 | fputs ("\t.long\t", file); | |
3492 | break; | |
3493 | case 8: | |
3494 | fputs (DOUBLE_INT_ASM_OP, file); | |
3495 | break; | |
3496 | default: | |
3497 | abort (); | |
3498 | } | |
3499 | output_addr_const (file, x); | |
3500 | fputs ("@dtprel+0x8000", file); | |
3501 | } | |
3502 | ||
c4501e62 JJ |
3503 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
3504 | ||
3505 | static GTY(()) rtx rs6000_tls_symbol; | |
3506 | static rtx | |
863d938c | 3507 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
3508 | { |
3509 | if (!rs6000_tls_symbol) | |
3510 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
3511 | ||
3512 | return rs6000_tls_symbol; | |
3513 | } | |
3514 | ||
3515 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
3516 | ||
3517 | static GTY(()) rtx rs6000_got_symbol; | |
3518 | static rtx | |
863d938c | 3519 | rs6000_got_sym (void) |
c4501e62 JJ |
3520 | { |
3521 | if (!rs6000_got_symbol) | |
3522 | { | |
3523 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3524 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
3525 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
f676971a | 3526 | } |
c4501e62 JJ |
3527 | |
3528 | return rs6000_got_symbol; | |
3529 | } | |
3530 | ||
3531 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3532 | this (thread-local) address. */ | |
3533 | ||
3534 | static rtx | |
a2369ed3 | 3535 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
3536 | { |
3537 | rtx dest, insn; | |
3538 | ||
3539 | dest = gen_reg_rtx (Pmode); | |
3540 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
3541 | { | |
3542 | rtx tlsreg; | |
3543 | ||
3544 | if (TARGET_64BIT) | |
3545 | { | |
3546 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3547 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
3548 | } | |
3549 | else | |
3550 | { | |
3551 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3552 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
3553 | } | |
3554 | emit_insn (insn); | |
3555 | } | |
3556 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
3557 | { | |
3558 | rtx tlsreg, tmp; | |
3559 | ||
3560 | tmp = gen_reg_rtx (Pmode); | |
3561 | if (TARGET_64BIT) | |
3562 | { | |
3563 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3564 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
3565 | } | |
3566 | else | |
3567 | { | |
3568 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3569 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
3570 | } | |
3571 | emit_insn (insn); | |
3572 | if (TARGET_64BIT) | |
3573 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
3574 | else | |
3575 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
3576 | emit_insn (insn); | |
3577 | } | |
3578 | else | |
3579 | { | |
3580 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
3581 | ||
3582 | if (TARGET_64BIT) | |
3583 | got = gen_rtx_REG (Pmode, TOC_REGISTER); | |
3584 | else | |
3585 | { | |
3586 | if (flag_pic == 1) | |
3587 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
3588 | else | |
3589 | { | |
3590 | rtx gsym = rs6000_got_sym (); | |
3591 | got = gen_reg_rtx (Pmode); | |
3592 | if (flag_pic == 0) | |
3593 | rs6000_emit_move (got, gsym, Pmode); | |
3594 | else | |
3595 | { | |
3596 | char buf[30]; | |
3597 | static int tls_got_labelno = 0; | |
3598 | rtx tempLR, lab, tmp3, mem; | |
3599 | rtx first, last; | |
3600 | ||
3601 | ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++); | |
3602 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
3603 | tempLR = gen_reg_rtx (Pmode); | |
3604 | tmp1 = gen_reg_rtx (Pmode); | |
3605 | tmp2 = gen_reg_rtx (Pmode); | |
3606 | tmp3 = gen_reg_rtx (Pmode); | |
542a8afa | 3607 | mem = gen_const_mem (Pmode, tmp1); |
c4501e62 JJ |
3608 | |
3609 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab, | |
3610 | gsym)); | |
3611 | emit_move_insn (tmp1, tempLR); | |
3612 | emit_move_insn (tmp2, mem); | |
3613 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
3614 | last = emit_move_insn (got, tmp3); | |
3615 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
3616 | REG_NOTES (last)); | |
3617 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
3618 | REG_NOTES (first)); | |
3619 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
3620 | REG_NOTES (last)); | |
3621 | } | |
3622 | } | |
3623 | } | |
3624 | ||
3625 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
3626 | { | |
3627 | r3 = gen_rtx_REG (Pmode, 3); | |
3628 | if (TARGET_64BIT) | |
3629 | insn = gen_tls_gd_64 (r3, got, addr); | |
3630 | else | |
3631 | insn = gen_tls_gd_32 (r3, got, addr); | |
3632 | start_sequence (); | |
3633 | emit_insn (insn); | |
3634 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3635 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3636 | insn = emit_call_insn (insn); | |
3637 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3638 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3639 | insn = get_insns (); | |
3640 | end_sequence (); | |
3641 | emit_libcall_block (insn, dest, r3, addr); | |
3642 | } | |
3643 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
3644 | { | |
3645 | r3 = gen_rtx_REG (Pmode, 3); | |
3646 | if (TARGET_64BIT) | |
3647 | insn = gen_tls_ld_64 (r3, got); | |
3648 | else | |
3649 | insn = gen_tls_ld_32 (r3, got); | |
3650 | start_sequence (); | |
3651 | emit_insn (insn); | |
3652 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3653 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3654 | insn = emit_call_insn (insn); | |
3655 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3656 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3657 | insn = get_insns (); | |
3658 | end_sequence (); | |
3659 | tmp1 = gen_reg_rtx (Pmode); | |
3660 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
3661 | UNSPEC_TLSLD); | |
3662 | emit_libcall_block (insn, tmp1, r3, eqv); | |
3663 | if (rs6000_tls_size == 16) | |
3664 | { | |
3665 | if (TARGET_64BIT) | |
3666 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
3667 | else | |
3668 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
3669 | } | |
3670 | else if (rs6000_tls_size == 32) | |
3671 | { | |
3672 | tmp2 = gen_reg_rtx (Pmode); | |
3673 | if (TARGET_64BIT) | |
3674 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
3675 | else | |
3676 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
3677 | emit_insn (insn); | |
3678 | if (TARGET_64BIT) | |
3679 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
3680 | else | |
3681 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
3682 | } | |
3683 | else | |
3684 | { | |
3685 | tmp2 = gen_reg_rtx (Pmode); | |
3686 | if (TARGET_64BIT) | |
3687 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
3688 | else | |
3689 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
3690 | emit_insn (insn); | |
3691 | insn = gen_rtx_SET (Pmode, dest, | |
3692 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
3693 | } | |
3694 | emit_insn (insn); | |
3695 | } | |
3696 | else | |
3697 | { | |
3698 | /* IE, or 64 bit offset LE. */ | |
3699 | tmp2 = gen_reg_rtx (Pmode); | |
3700 | if (TARGET_64BIT) | |
3701 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
3702 | else | |
3703 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
3704 | emit_insn (insn); | |
3705 | if (TARGET_64BIT) | |
3706 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
3707 | else | |
3708 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
3709 | emit_insn (insn); | |
3710 | } | |
3711 | } | |
3712 | ||
3713 | return dest; | |
3714 | } | |
3715 | ||
3716 | /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in | |
3717 | instruction definitions. */ | |
3718 | ||
3719 | int | |
a2369ed3 | 3720 | rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
c4501e62 JJ |
3721 | { |
3722 | return RS6000_SYMBOL_REF_TLS_P (x); | |
3723 | } | |
3724 | ||
3725 | /* Return 1 if X contains a thread-local symbol. */ | |
3726 | ||
3727 | bool | |
a2369ed3 | 3728 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 3729 | { |
cd413cab AP |
3730 | if (! TARGET_HAVE_TLS) |
3731 | return false; | |
3732 | ||
c4501e62 JJ |
3733 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
3734 | } | |
3735 | ||
3736 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
3737 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
3738 | ||
3739 | static inline int | |
a2369ed3 | 3740 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
3741 | { |
3742 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
3743 | } | |
3744 | ||
24ea750e DJ |
3745 | /* The convention appears to be to define this wherever it is used. |
3746 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
3747 | is now used here. */ | |
3748 | #ifndef REG_MODE_OK_FOR_BASE_P | |
3749 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
3750 | #endif | |
3751 | ||
3752 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
3753 | replace the input X, or the original X if no replacement is called for. | |
3754 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
3755 | 0 if it should not. | |
3756 | ||
3757 | For RS/6000, we wish to handle large displacements off a base | |
3758 | register by splitting the addend across an addiu/addis and the mem insn. | |
3759 | This cuts number of extra insns needed from 3 to 1. | |
3760 | ||
3761 | On Darwin, we use this to generate code for floating point constants. | |
3762 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
3763 | The Darwin code is inside #if TARGET_MACHO because only then is | |
3764 | machopic_function_base_name() defined. */ | |
3765 | rtx | |
f676971a | 3766 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
c4ad648e AM |
3767 | int opnum, int type, |
3768 | int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e | 3769 | { |
f676971a | 3770 | /* We must recognize output that we have already generated ourselves. */ |
24ea750e DJ |
3771 | if (GET_CODE (x) == PLUS |
3772 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3773 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
3774 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3775 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3776 | { | |
3777 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3778 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3779 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3780 | *win = 1; |
3781 | return x; | |
3782 | } | |
3deb2758 | 3783 | |
24ea750e DJ |
3784 | #if TARGET_MACHO |
3785 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
3786 | && GET_CODE (x) == LO_SUM | |
3787 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3788 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
3789 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
3790 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
3791 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
3792 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
3793 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
3794 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
3795 | { | |
3796 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 3797 | floating point constant. */ |
24ea750e | 3798 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
c4ad648e AM |
3799 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3800 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3801 | *win = 1; |
3802 | return x; | |
3803 | } | |
3804 | #endif | |
3805 | if (GET_CODE (x) == PLUS | |
3806 | && GET_CODE (XEXP (x, 0)) == REG | |
3807 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
3808 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 3809 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 3810 | && !SPE_VECTOR_MODE (mode) |
4d4cbc0e | 3811 | && !(TARGET_E500_DOUBLE && mode == DFmode) |
78c875e8 | 3812 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
3813 | { |
3814 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
3815 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
3816 | HOST_WIDE_INT high | |
c4ad648e | 3817 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; |
24ea750e DJ |
3818 | |
3819 | /* Check for 32-bit overflow. */ | |
3820 | if (high + low != val) | |
c4ad648e | 3821 | { |
24ea750e DJ |
3822 | *win = 0; |
3823 | return x; | |
3824 | } | |
3825 | ||
3826 | /* Reload the high part into a base reg; leave the low part | |
c4ad648e | 3827 | in the mem directly. */ |
24ea750e DJ |
3828 | |
3829 | x = gen_rtx_PLUS (GET_MODE (x), | |
c4ad648e AM |
3830 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), |
3831 | GEN_INT (high)), | |
3832 | GEN_INT (low)); | |
24ea750e DJ |
3833 | |
3834 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3835 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3836 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3837 | *win = 1; |
3838 | return x; | |
3839 | } | |
3840 | #if TARGET_MACHO | |
3841 | if (GET_CODE (x) == SYMBOL_REF | |
3842 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 3843 | && !ALTIVEC_VECTOR_MODE (mode) |
a29077da GK |
3844 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
3845 | /* Don't do this for TFmode, since the result isn't offsettable. */ | |
3846 | && mode != TFmode) | |
24ea750e | 3847 | { |
a29077da GK |
3848 | if (flag_pic) |
3849 | { | |
3850 | rtx offset = gen_rtx_CONST (Pmode, | |
3851 | gen_rtx_MINUS (Pmode, x, | |
11abc112 | 3852 | machopic_function_base_sym ())); |
a29077da GK |
3853 | x = gen_rtx_LO_SUM (GET_MODE (x), |
3854 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
3855 | gen_rtx_HIGH (Pmode, offset)), offset); | |
3856 | } | |
3857 | else | |
3858 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
c4ad648e | 3859 | gen_rtx_HIGH (Pmode, x), x); |
a29077da | 3860 | |
24ea750e | 3861 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
3862 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3863 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3864 | *win = 1; |
3865 | return x; | |
3866 | } | |
3867 | #endif | |
3868 | if (TARGET_TOC | |
4d588c14 | 3869 | && constant_pool_expr_p (x) |
c1f11548 | 3870 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3871 | { |
3872 | (x) = create_TOC_reference (x); | |
3873 | *win = 1; | |
3874 | return x; | |
3875 | } | |
3876 | *win = 0; | |
3877 | return x; | |
f676971a | 3878 | } |
24ea750e | 3879 | |
258bfae2 FS |
3880 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3881 | that is a valid memory address for an instruction. | |
3882 | The MODE argument is the machine mode for the MEM expression | |
3883 | that wants to use this address. | |
3884 | ||
3885 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3886 | refers to a constant pool entry of an address (or the sum of it | |
3887 | plus a constant), a short (16-bit signed) constant plus a register, | |
3888 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3889 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3890 | we must ensure that both words are addressable or PowerPC64 with offset |
3891 | word aligned. | |
3892 | ||
3893 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
76d2b81d | 3894 | 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because |
258bfae2 FS |
3895 | adjacent memory cells are accessed by adding word-sized offsets |
3896 | during assembly output. */ | |
3897 | int | |
a2369ed3 | 3898 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 3899 | { |
850e8d3d DN |
3900 | /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ |
3901 | if (TARGET_ALTIVEC | |
3902 | && ALTIVEC_VECTOR_MODE (mode) | |
3903 | && GET_CODE (x) == AND | |
3904 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3905 | && INTVAL (XEXP (x, 1)) == -16) | |
3906 | x = XEXP (x, 0); | |
3907 | ||
c4501e62 JJ |
3908 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3909 | return 0; | |
4d588c14 | 3910 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3911 | return 1; |
3912 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3913 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3914 | && !SPE_VECTOR_MODE (mode) |
4d4cbc0e | 3915 | && !(TARGET_E500_DOUBLE && mode == DFmode) |
258bfae2 | 3916 | && TARGET_UPDATE |
4d588c14 | 3917 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3918 | return 1; |
4d588c14 | 3919 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 3920 | return 1; |
4d588c14 | 3921 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3922 | return 1; |
3923 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3924 | if (! reg_ok_strict | |
3925 | && GET_CODE (x) == PLUS | |
3926 | && GET_CODE (XEXP (x, 0)) == REG | |
708d2456 | 3927 | && (XEXP (x, 0) == virtual_stack_vars_rtx |
c4ad648e | 3928 | || XEXP (x, 0) == arg_pointer_rtx) |
258bfae2 FS |
3929 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
3930 | return 1; | |
76d2b81d | 3931 | if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3932 | return 1; |
3933 | if (mode != TImode | |
76d2b81d | 3934 | && mode != TFmode |
a3170dc6 AH |
3935 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3936 | || TARGET_POWERPC64 | |
4d4cbc0e | 3937 | || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode)) |
258bfae2 | 3938 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3939 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3940 | return 1; |
4d588c14 | 3941 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3942 | return 1; |
3943 | return 0; | |
3944 | } | |
4d588c14 RH |
3945 | |
3946 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3947 | has an effect that depends on the machine mode it is used for. | |
3948 | ||
3949 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3950 | modes don't allow them) or is a pre-increment or decrement. | |
3951 | ||
3952 | ??? Except that due to conceptual problems in offsettable_address_p | |
3953 | we can't really report the problems of integral offsets. So leave | |
f676971a | 3954 | this assuming that the adjustable offset must be valid for the |
4d588c14 RH |
3955 | sub-words of a TFmode operand, which is what we had before. */ |
3956 | ||
3957 | bool | |
a2369ed3 | 3958 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
3959 | { |
3960 | switch (GET_CODE (addr)) | |
3961 | { | |
3962 | case PLUS: | |
3963 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3964 | { | |
3965 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3966 | return val + 12 + 0x8000 >= 0x10000; | |
3967 | } | |
3968 | break; | |
3969 | ||
3970 | case LO_SUM: | |
3971 | return true; | |
3972 | ||
3973 | case PRE_INC: | |
3974 | case PRE_DEC: | |
3975 | return TARGET_UPDATE; | |
3976 | ||
3977 | default: | |
3978 | break; | |
3979 | } | |
3980 | ||
3981 | return false; | |
3982 | } | |
d8ecbcdb AH |
3983 | |
3984 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
3985 | to hold something of mode MODE. | |
3986 | This is ordinarily the length in words of a value of mode MODE | |
3987 | but can be less for certain modes in special long registers. | |
3988 | ||
3989 | For the SPE, GPRs are 64 bits but only 32 bits are visible in | |
3990 | scalar instructions. The upper 32 bits are only available to the | |
3991 | SIMD instructions. | |
3992 | ||
3993 | POWER and PowerPC GPRs hold 32 bits worth; | |
3994 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
3995 | ||
3996 | int | |
3997 | rs6000_hard_regno_nregs (int regno, enum machine_mode mode) | |
3998 | { | |
3999 | if (FP_REGNO_P (regno)) | |
4000 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; | |
4001 | ||
4d4cbc0e AH |
4002 | if (TARGET_E500_DOUBLE && mode == DFmode) |
4003 | return 1; | |
4004 | ||
d8ecbcdb AH |
4005 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
4006 | return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; | |
4007 | ||
4008 | if (ALTIVEC_REGNO_P (regno)) | |
4009 | return | |
4010 | (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; | |
4011 | ||
4012 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4013 | } | |
2aa4498c AH |
4014 | |
4015 | /* Change register usage conditional on target flags. */ | |
4016 | void | |
4017 | rs6000_conditional_register_usage (void) | |
4018 | { | |
4019 | int i; | |
4020 | ||
4021 | /* Set MQ register fixed (already call_used) if not POWER | |
4022 | architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not | |
4023 | be allocated. */ | |
4024 | if (! TARGET_POWER) | |
4025 | fixed_regs[64] = 1; | |
4026 | ||
4027 | /* 64-bit AIX reserves GPR13 for thread-private data. */ | |
4028 | if (TARGET_64BIT) | |
4029 | fixed_regs[13] = call_used_regs[13] | |
4030 | = call_really_used_regs[13] = 1; | |
4031 | ||
4032 | /* Conditionally disable FPRs. */ | |
4033 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
4034 | for (i = 32; i < 64; i++) | |
4035 | fixed_regs[i] = call_used_regs[i] | |
c4ad648e | 4036 | = call_really_used_regs[i] = 1; |
2aa4498c AH |
4037 | |
4038 | if (DEFAULT_ABI == ABI_V4 | |
4039 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
4040 | && flag_pic == 2) | |
4041 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4042 | ||
4043 | if (DEFAULT_ABI == ABI_V4 | |
4044 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
4045 | && flag_pic == 1) | |
4046 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4047 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4048 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4049 | ||
4050 | if (DEFAULT_ABI == ABI_DARWIN | |
4051 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
4052 | global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4053 | = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4054 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4055 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4056 | ||
b4db40bf JJ |
4057 | if (TARGET_TOC && TARGET_MINIMAL_TOC) |
4058 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4059 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4060 | ||
2aa4498c AH |
4061 | if (TARGET_ALTIVEC) |
4062 | global_regs[VSCR_REGNO] = 1; | |
4063 | ||
4064 | if (TARGET_SPE) | |
4065 | { | |
4066 | global_regs[SPEFSCR_REGNO] = 1; | |
4067 | fixed_regs[FIXED_SCRATCH] | |
c4ad648e | 4068 | = call_used_regs[FIXED_SCRATCH] |
2aa4498c AH |
4069 | = call_really_used_regs[FIXED_SCRATCH] = 1; |
4070 | } | |
4071 | ||
4072 | if (! TARGET_ALTIVEC) | |
4073 | { | |
4074 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
4075 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
4076 | call_really_used_regs[VRSAVE_REGNO] = 1; | |
4077 | } | |
4078 | ||
4079 | if (TARGET_ALTIVEC_ABI) | |
4080 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) | |
4081 | call_used_regs[i] = call_really_used_regs[i] = 1; | |
4082 | } | |
fb4d4348 | 4083 | \f |
a4f6c312 SS |
4084 | /* Try to output insns to set TARGET equal to the constant C if it can |
4085 | be done in less than N insns. Do all computations in MODE. | |
4086 | Returns the place where the output has been placed if it can be | |
4087 | done and the insns have been emitted. If it would take more than N | |
4088 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
4089 | |
4090 | rtx | |
f676971a | 4091 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
a2369ed3 | 4092 | rtx source, int n ATTRIBUTE_UNUSED) |
2bfcf297 | 4093 | { |
af8cb5c5 | 4094 | rtx result, insn, set; |
2bfcf297 DB |
4095 | HOST_WIDE_INT c0, c1; |
4096 | ||
af8cb5c5 | 4097 | if (mode == QImode || mode == HImode) |
2bfcf297 DB |
4098 | { |
4099 | if (dest == NULL) | |
c4ad648e | 4100 | dest = gen_reg_rtx (mode); |
2bfcf297 DB |
4101 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); |
4102 | return dest; | |
4103 | } | |
af8cb5c5 | 4104 | else if (mode == SImode) |
2bfcf297 | 4105 | { |
af8cb5c5 DE |
4106 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
4107 | ||
4108 | emit_insn (gen_rtx_SET (VOIDmode, result, | |
4109 | GEN_INT (INTVAL (source) | |
4110 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
4111 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
4112 | gen_rtx_IOR (SImode, result, | |
4113 | GEN_INT (INTVAL (source) & 0xffff)))); | |
4114 | result = dest; | |
2bfcf297 | 4115 | } |
af8cb5c5 | 4116 | else if (mode == DImode) |
2bfcf297 | 4117 | { |
af8cb5c5 DE |
4118 | if (GET_CODE (source) == CONST_INT) |
4119 | { | |
4120 | c0 = INTVAL (source); | |
4121 | c1 = -(c0 < 0); | |
4122 | } | |
4123 | else if (GET_CODE (source) == CONST_DOUBLE) | |
4124 | { | |
2bfcf297 | 4125 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
4126 | c0 = CONST_DOUBLE_LOW (source); |
4127 | c1 = -(c0 < 0); | |
2bfcf297 | 4128 | #else |
af8cb5c5 DE |
4129 | c0 = CONST_DOUBLE_LOW (source); |
4130 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 4131 | #endif |
af8cb5c5 DE |
4132 | } |
4133 | else | |
4134 | abort (); | |
4135 | ||
4136 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
2bfcf297 DB |
4137 | } |
4138 | else | |
a4f6c312 | 4139 | abort (); |
2bfcf297 | 4140 | |
af8cb5c5 DE |
4141 | insn = get_last_insn (); |
4142 | set = single_set (insn); | |
4143 | if (! CONSTANT_P (SET_SRC (set))) | |
4144 | set_unique_reg_note (insn, REG_EQUAL, source); | |
4145 | ||
4146 | return result; | |
2bfcf297 DB |
4147 | } |
4148 | ||
4149 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
4150 | fall back to a straight forward decomposition. We do this to avoid | |
4151 | exponential run times encountered when looking for longer sequences | |
4152 | with rs6000_emit_set_const. */ | |
4153 | static rtx | |
a2369ed3 | 4154 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
4155 | { |
4156 | if (!TARGET_POWERPC64) | |
4157 | { | |
4158 | rtx operand1, operand2; | |
4159 | ||
4160 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
4161 | DImode); | |
4162 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
4163 | DImode); | |
4164 | emit_move_insn (operand1, GEN_INT (c1)); | |
4165 | emit_move_insn (operand2, GEN_INT (c2)); | |
4166 | } | |
4167 | else | |
4168 | { | |
bc06712d | 4169 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 4170 | |
bc06712d | 4171 | ud1 = c1 & 0xffff; |
f921c9c9 | 4172 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 4173 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 4174 | c2 = c1 >> 32; |
2bfcf297 | 4175 | #endif |
bc06712d | 4176 | ud3 = c2 & 0xffff; |
f921c9c9 | 4177 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 4178 | |
f676971a | 4179 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
bc06712d | 4180 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) |
2bfcf297 | 4181 | { |
bc06712d | 4182 | if (ud1 & 0x8000) |
b78d48dd | 4183 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
4184 | else |
4185 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 4186 | } |
2bfcf297 | 4187 | |
f676971a | 4188 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
bc06712d | 4189 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) |
252b88f7 | 4190 | { |
bc06712d | 4191 | if (ud2 & 0x8000) |
f676971a | 4192 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) |
bc06712d | 4193 | - 0x80000000)); |
252b88f7 | 4194 | else |
bc06712d TR |
4195 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
4196 | if (ud1 != 0) | |
4197 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 4198 | } |
f676971a | 4199 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
bc06712d TR |
4200 | || (ud4 == 0 && ! (ud3 & 0x8000))) |
4201 | { | |
4202 | if (ud3 & 0x8000) | |
f676971a | 4203 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) |
bc06712d TR |
4204 | - 0x80000000)); |
4205 | else | |
4206 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
4207 | ||
4208 | if (ud2 != 0) | |
4209 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
4210 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
4211 | if (ud1 != 0) | |
4212 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
4213 | } | |
f676971a | 4214 | else |
bc06712d TR |
4215 | { |
4216 | if (ud4 & 0x8000) | |
f676971a | 4217 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) |
bc06712d TR |
4218 | - 0x80000000)); |
4219 | else | |
4220 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
4221 | ||
4222 | if (ud3 != 0) | |
4223 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 4224 | |
bc06712d TR |
4225 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
4226 | if (ud2 != 0) | |
f676971a EC |
4227 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, |
4228 | GEN_INT (ud2 << 16))); | |
bc06712d TR |
4229 | if (ud1 != 0) |
4230 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
4231 | } | |
4232 | } | |
2bfcf297 DB |
4233 | return dest; |
4234 | } | |
4235 | ||
76d2b81d DJ |
4236 | /* Helper for the following. Get rid of [r+r] memory refs |
4237 | in cases where it won't work (TImode, TFmode). */ | |
4238 | ||
4239 | static void | |
4240 | rs6000_eliminate_indexed_memrefs (rtx operands[2]) | |
4241 | { | |
4242 | if (GET_CODE (operands[0]) == MEM | |
4243 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
4244 | && ! reload_in_progress) | |
4245 | operands[0] | |
4246 | = replace_equiv_address (operands[0], | |
4247 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
4248 | ||
4249 | if (GET_CODE (operands[1]) == MEM | |
4250 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
4251 | && ! reload_in_progress) | |
4252 | operands[1] | |
4253 | = replace_equiv_address (operands[1], | |
4254 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
4255 | } | |
4256 | ||
fb4d4348 GK |
4257 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
4258 | void | |
a2369ed3 | 4259 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
4260 | { |
4261 | rtx operands[2]; | |
4262 | operands[0] = dest; | |
4263 | operands[1] = source; | |
f676971a | 4264 | |
fb4d4348 GK |
4265 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ |
4266 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
4267 | && ! FLOAT_MODE_P (mode) | |
4268 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
4269 | { | |
4270 | /* FIXME. This should never happen. */ | |
4271 | /* Since it seems that it does, do the safe thing and convert | |
4272 | to a CONST_INT. */ | |
2496c7bd | 4273 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 GK |
4274 | } |
4275 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
4276 | && ! FLOAT_MODE_P (mode) | |
4277 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
4278 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
4279 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
4280 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
4281 | abort (); | |
c9e8cb32 DD |
4282 | |
4283 | /* Check if GCC is setting up a block move that will end up using FP | |
4284 | registers as temporaries. We must make sure this is acceptable. */ | |
4285 | if (GET_CODE (operands[0]) == MEM | |
4286 | && GET_CODE (operands[1]) == MEM | |
4287 | && mode == DImode | |
41543739 GK |
4288 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
4289 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
4290 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
4291 | ? 32 : MEM_ALIGN (operands[0]))) | |
4292 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
f676971a | 4293 | ? 32 |
41543739 GK |
4294 | : MEM_ALIGN (operands[1])))) |
4295 | && ! MEM_VOLATILE_P (operands [0]) | |
4296 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 4297 | { |
41543739 GK |
4298 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
4299 | adjust_address (operands[1], SImode, 0)); | |
4300 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
4301 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
4302 | return; |
4303 | } | |
630d42a0 | 4304 | |
c9dbf840 DE |
4305 | if (!no_new_pseudos && GET_CODE (operands[0]) != REG |
4306 | && !gpc_reg_operand (operands[1], mode)) | |
f6219a5e | 4307 | operands[1] = force_reg (mode, operands[1]); |
a9098fd0 | 4308 | |
a3170dc6 AH |
4309 | if (mode == SFmode && ! TARGET_POWERPC |
4310 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 4311 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 4312 | { |
ffc14f31 GK |
4313 | int regnum; |
4314 | ||
4315 | if (reload_in_progress || reload_completed) | |
4316 | regnum = true_regnum (operands[1]); | |
4317 | else if (GET_CODE (operands[1]) == REG) | |
4318 | regnum = REGNO (operands[1]); | |
4319 | else | |
4320 | regnum = -1; | |
f676971a | 4321 | |
fb4d4348 GK |
4322 | /* If operands[1] is a register, on POWER it may have |
4323 | double-precision data in it, so truncate it to single | |
4324 | precision. */ | |
4325 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
4326 | { | |
4327 | rtx newreg; | |
4328 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
4329 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
4330 | operands[1] = newreg; | |
4331 | } | |
4332 | } | |
4333 | ||
c4501e62 JJ |
4334 | /* Recognize the case where operand[1] is a reference to thread-local |
4335 | data and load its address to a register. */ | |
4336 | if (GET_CODE (operands[1]) == SYMBOL_REF) | |
4337 | { | |
4338 | enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]); | |
4339 | if (model != 0) | |
4340 | operands[1] = rs6000_legitimize_tls_address (operands[1], model); | |
4341 | } | |
4342 | ||
8f4e6caf RH |
4343 | /* Handle the case where reload calls us with an invalid address. */ |
4344 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 4345 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
4346 | || ! nonimmediate_operand (operands[0], mode))) |
4347 | goto emit_set; | |
4348 | ||
a9baceb1 GK |
4349 | /* 128-bit constant floating-point values on Darwin should really be |
4350 | loaded as two parts. */ | |
4351 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
4352 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
4353 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) | |
4354 | { | |
4355 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
4356 | know how to get a DFmode SUBREG of a TFmode. */ | |
4357 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), | |
4358 | simplify_gen_subreg (DImode, operands[1], mode, 0), | |
4359 | DImode); | |
4360 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, | |
4361 | GET_MODE_SIZE (DImode)), | |
4362 | simplify_gen_subreg (DImode, operands[1], mode, | |
4363 | GET_MODE_SIZE (DImode)), | |
4364 | DImode); | |
4365 | return; | |
4366 | } | |
4367 | ||
fb4d4348 GK |
4368 | /* FIXME: In the long term, this switch statement should go away |
4369 | and be replaced by a sequence of tests based on things like | |
4370 | mode == Pmode. */ | |
4371 | switch (mode) | |
4372 | { | |
4373 | case HImode: | |
4374 | case QImode: | |
4375 | if (CONSTANT_P (operands[1]) | |
4376 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 4377 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
4378 | break; |
4379 | ||
06f4e019 | 4380 | case TFmode: |
76d2b81d DJ |
4381 | rs6000_eliminate_indexed_memrefs (operands); |
4382 | /* fall through */ | |
4383 | ||
fb4d4348 GK |
4384 | case DFmode: |
4385 | case SFmode: | |
f676971a | 4386 | if (CONSTANT_P (operands[1]) |
fb4d4348 | 4387 | && ! easy_fp_constant (operands[1], mode)) |
a9098fd0 | 4388 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 4389 | break; |
f676971a | 4390 | |
0ac081f6 AH |
4391 | case V16QImode: |
4392 | case V8HImode: | |
4393 | case V4SFmode: | |
4394 | case V4SImode: | |
a3170dc6 AH |
4395 | case V4HImode: |
4396 | case V2SFmode: | |
4397 | case V2SImode: | |
00a892b8 | 4398 | case V1DImode: |
69ef87e2 | 4399 | if (CONSTANT_P (operands[1]) |
d744e06e | 4400 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
4401 | operands[1] = force_const_mem (mode, operands[1]); |
4402 | break; | |
f676971a | 4403 | |
fb4d4348 | 4404 | case SImode: |
a9098fd0 | 4405 | case DImode: |
fb4d4348 GK |
4406 | /* Use default pattern for address of ELF small data */ |
4407 | if (TARGET_ELF | |
a9098fd0 | 4408 | && mode == Pmode |
f607bc57 | 4409 | && DEFAULT_ABI == ABI_V4 |
f676971a | 4410 | && (GET_CODE (operands[1]) == SYMBOL_REF |
a9098fd0 GK |
4411 | || GET_CODE (operands[1]) == CONST) |
4412 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
4413 | { |
4414 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
4415 | return; | |
4416 | } | |
4417 | ||
f607bc57 | 4418 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
4419 | && mode == Pmode && mode == SImode |
4420 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
4421 | { |
4422 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
4423 | return; | |
4424 | } | |
4425 | ||
ee890fe2 | 4426 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
4427 | && TARGET_NO_TOC |
4428 | && ! flag_pic | |
a9098fd0 | 4429 | && mode == Pmode |
fb4d4348 GK |
4430 | && CONSTANT_P (operands[1]) |
4431 | && GET_CODE (operands[1]) != HIGH | |
4432 | && GET_CODE (operands[1]) != CONST_INT) | |
4433 | { | |
a9098fd0 | 4434 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
4435 | |
4436 | /* If this is a function address on -mcall-aixdesc, | |
4437 | convert it to the address of the descriptor. */ | |
4438 | if (DEFAULT_ABI == ABI_AIX | |
4439 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4440 | && XSTR (operands[1], 0)[0] == '.') | |
4441 | { | |
4442 | const char *name = XSTR (operands[1], 0); | |
4443 | rtx new_ref; | |
4444 | while (*name == '.') | |
4445 | name++; | |
4446 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
4447 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
4448 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 4449 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 4450 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 4451 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
4452 | operands[1] = new_ref; |
4453 | } | |
7509c759 | 4454 | |
ee890fe2 SS |
4455 | if (DEFAULT_ABI == ABI_DARWIN) |
4456 | { | |
ab82a49f AP |
4457 | #if TARGET_MACHO |
4458 | if (MACHO_DYNAMIC_NO_PIC_P) | |
4459 | { | |
4460 | /* Take care of any required data indirection. */ | |
4461 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
4462 | operands[1], mode, operands[0]); | |
4463 | if (operands[0] != operands[1]) | |
4464 | emit_insn (gen_rtx_SET (VOIDmode, | |
c4ad648e | 4465 | operands[0], operands[1])); |
ab82a49f AP |
4466 | return; |
4467 | } | |
4468 | #endif | |
b8a55285 AP |
4469 | emit_insn (gen_macho_high (target, operands[1])); |
4470 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
ee890fe2 SS |
4471 | return; |
4472 | } | |
4473 | ||
fb4d4348 GK |
4474 | emit_insn (gen_elf_high (target, operands[1])); |
4475 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
4476 | return; | |
4477 | } | |
4478 | ||
a9098fd0 GK |
4479 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
4480 | and we have put it in the TOC, we just need to make a TOC-relative | |
4481 | reference to it. */ | |
4482 | if (TARGET_TOC | |
4483 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 4484 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
4485 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
4486 | get_pool_mode (operands[1]))) | |
fb4d4348 | 4487 | { |
a9098fd0 | 4488 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 4489 | } |
a9098fd0 GK |
4490 | else if (mode == Pmode |
4491 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
4492 | && ((GET_CODE (operands[1]) != CONST_INT |
4493 | && ! easy_fp_constant (operands[1], mode)) | |
4494 | || (GET_CODE (operands[1]) == CONST_INT | |
4495 | && num_insns_constant (operands[1], mode) > 2) | |
4496 | || (GET_CODE (operands[0]) == REG | |
4497 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 4498 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
4499 | && ! legitimate_constant_pool_address_p (operands[1]) |
4500 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
4501 | { |
4502 | /* Emit a USE operation so that the constant isn't deleted if | |
4503 | expensive optimizations are turned on because nobody | |
4504 | references it. This should only be done for operands that | |
4505 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
4506 | This should not be done for operands that contain LABEL_REFs. | |
4507 | For now, we just handle the obvious case. */ | |
4508 | if (GET_CODE (operands[1]) != LABEL_REF) | |
4509 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
4510 | ||
c859cda6 | 4511 | #if TARGET_MACHO |
ee890fe2 | 4512 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 4513 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 4514 | { |
ee890fe2 SS |
4515 | operands[1] = |
4516 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
4517 | operands[0]); |
4518 | if (operands[0] != operands[1]) | |
4519 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
4520 | return; |
4521 | } | |
c859cda6 | 4522 | #endif |
ee890fe2 | 4523 | |
fb4d4348 GK |
4524 | /* If we are to limit the number of things we put in the TOC and |
4525 | this is a symbol plus a constant we can add in one insn, | |
4526 | just put the symbol in the TOC and add the constant. Don't do | |
4527 | this if reload is in progress. */ | |
4528 | if (GET_CODE (operands[1]) == CONST | |
4529 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
4530 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 4531 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
4532 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
4533 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
4534 | && ! side_effects_p (operands[0])) | |
4535 | { | |
a4f6c312 SS |
4536 | rtx sym = |
4537 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
4538 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
4539 | ||
a9098fd0 GK |
4540 | sym = force_reg (mode, sym); |
4541 | if (mode == SImode) | |
4542 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
4543 | else | |
4544 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
4545 | return; |
4546 | } | |
4547 | ||
a9098fd0 | 4548 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 4549 | |
f676971a | 4550 | if (TARGET_TOC |
4d588c14 | 4551 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
4552 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
4553 | get_pool_constant (XEXP (operands[1], 0)), | |
4554 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 4555 | { |
ba4828e0 | 4556 | operands[1] |
542a8afa | 4557 | = gen_const_mem (mode, |
c4ad648e | 4558 | create_TOC_reference (XEXP (operands[1], 0))); |
ba4828e0 | 4559 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); |
a9098fd0 | 4560 | } |
fb4d4348 GK |
4561 | } |
4562 | break; | |
a9098fd0 | 4563 | |
fb4d4348 | 4564 | case TImode: |
76d2b81d DJ |
4565 | rs6000_eliminate_indexed_memrefs (operands); |
4566 | ||
27dc0551 DE |
4567 | if (TARGET_POWER) |
4568 | { | |
4569 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
4570 | gen_rtvec (2, | |
4571 | gen_rtx_SET (VOIDmode, | |
4572 | operands[0], operands[1]), | |
4573 | gen_rtx_CLOBBER (VOIDmode, | |
4574 | gen_rtx_SCRATCH (SImode))))); | |
4575 | return; | |
4576 | } | |
fb4d4348 GK |
4577 | break; |
4578 | ||
4579 | default: | |
4580 | abort (); | |
4581 | } | |
4582 | ||
a9098fd0 GK |
4583 | /* Above, we may have called force_const_mem which may have returned |
4584 | an invalid address. If we can, fix this up; otherwise, reload will | |
4585 | have to deal with it. */ | |
8f4e6caf RH |
4586 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
4587 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 4588 | |
8f4e6caf | 4589 | emit_set: |
fb4d4348 GK |
4590 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
4591 | } | |
4697a36c | 4592 | \f |
2858f73a GK |
4593 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
4594 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
4595 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
4596 | && (CUM)->fregno <= FP_ARG_MAX_REG \ | |
4597 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
4598 | ||
4599 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
4600 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
4601 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
4602 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
4603 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 4604 | && (NAMED)) |
2858f73a | 4605 | |
c6e8c921 GK |
4606 | /* Return a nonzero value to say to return the function value in |
4607 | memory, just as large structures are always returned. TYPE will be | |
4608 | the data type of the value, and FNTYPE will be the type of the | |
4609 | function doing the returning, or @code{NULL} for libcalls. | |
4610 | ||
4611 | The AIX ABI for the RS/6000 specifies that all structures are | |
4612 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
4613 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
4614 | draft put them in memory, and GCC used to implement the draft | |
4615 | instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET | |
4616 | controls this instead of DEFAULT_ABI; V.4 targets needing backward | |
4617 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
4618 | default, and -m switches get the final word. See | |
4619 | rs6000_override_options for more details. | |
4620 | ||
4621 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
4622 | long double support is enabled. These values are returned in memory. | |
4623 | ||
4624 | int_size_in_bytes returns -1 for variable size objects, which go in | |
4625 | memory always. The cast to unsigned makes -1 > 8. */ | |
4626 | ||
4627 | static bool | |
4628 | rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
4629 | { | |
594a51fe SS |
4630 | /* In the darwin64 abi, try to use registers for larger structs |
4631 | if possible. */ | |
4632 | if (AGGREGATE_TYPE_P (type) | |
4633 | && rs6000_darwin64_abi | |
4634 | && TREE_CODE (type) == RECORD_TYPE | |
4635 | && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 32) | |
4636 | && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 0)) | |
4637 | return false; | |
4638 | ||
c6e8c921 GK |
4639 | if (AGGREGATE_TYPE_P (type) |
4640 | && (TARGET_AIX_STRUCT_RET | |
4641 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) | |
4642 | return true; | |
b693336b PB |
4643 | |
4644 | /* Return synthetic vectors in memory. */ | |
4645 | if (TREE_CODE (type) == VECTOR_TYPE | |
4646 | && int_size_in_bytes (type) > (TARGET_ALTIVEC ? 16 : 8)) | |
4647 | { | |
4648 | static bool warned_for_return_big_vectors = false; | |
4649 | if (!warned_for_return_big_vectors) | |
4650 | { | |
4651 | warning ("synthetic vectors returned by reference: " | |
4652 | "non-standard ABI extension with no compatibility guarantee"); | |
4653 | warned_for_return_big_vectors = true; | |
4654 | } | |
4655 | return true; | |
4656 | } | |
4657 | ||
c6e8c921 GK |
4658 | if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode) |
4659 | return true; | |
4660 | return false; | |
4661 | } | |
4662 | ||
4697a36c MM |
4663 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
4664 | for a call to a function whose data type is FNTYPE. | |
4665 | For a library call, FNTYPE is 0. | |
4666 | ||
4667 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 4668 | so we never return a PARALLEL. */ |
4697a36c MM |
4669 | |
4670 | void | |
f676971a | 4671 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
4672 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
4673 | int libcall, int n_named_args) | |
4697a36c MM |
4674 | { |
4675 | static CUMULATIVE_ARGS zero_cumulative; | |
4676 | ||
4677 | *cum = zero_cumulative; | |
4678 | cum->words = 0; | |
4679 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 4680 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 4681 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
4682 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
4683 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 4684 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
4685 | cum->stdarg = fntype |
4686 | && (TYPE_ARG_TYPES (fntype) != 0 | |
4687 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
4688 | != void_type_node)); | |
4697a36c | 4689 | |
0f6937fe AM |
4690 | cum->nargs_prototype = 0; |
4691 | if (incoming || cum->prototype) | |
4692 | cum->nargs_prototype = n_named_args; | |
4697a36c | 4693 | |
a5c76ee6 ZW |
4694 | /* Check for a longcall attribute. */ |
4695 | if (fntype | |
4696 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
4697 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
4698 | cum->call_cookie = CALL_LONG; |
4699 | ||
4697a36c MM |
4700 | if (TARGET_DEBUG_ARG) |
4701 | { | |
4702 | fprintf (stderr, "\ninit_cumulative_args:"); | |
4703 | if (fntype) | |
4704 | { | |
4705 | tree ret_type = TREE_TYPE (fntype); | |
4706 | fprintf (stderr, " ret code = %s,", | |
4707 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
4708 | } | |
4709 | ||
6a4cee5f MM |
4710 | if (cum->call_cookie & CALL_LONG) |
4711 | fprintf (stderr, " longcall,"); | |
4712 | ||
4697a36c MM |
4713 | fprintf (stderr, " proto = %d, nargs = %d\n", |
4714 | cum->prototype, cum->nargs_prototype); | |
4715 | } | |
f676971a | 4716 | |
c4ad648e AM |
4717 | if (fntype |
4718 | && !TARGET_ALTIVEC | |
4719 | && TARGET_ALTIVEC_ABI | |
4720 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) | |
4721 | { | |
4722 | error ("Cannot return value in vector register because" | |
4723 | " altivec instructions are disabled, use -maltivec" | |
4724 | " to enable them."); | |
4725 | } | |
4697a36c MM |
4726 | } |
4727 | \f | |
fe984136 RH |
4728 | /* Return true if TYPE must be passed on the stack and not in registers. */ |
4729 | ||
4730 | static bool | |
4731 | rs6000_must_pass_in_stack (enum machine_mode mode, tree type) | |
4732 | { | |
4733 | if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT) | |
4734 | return must_pass_in_stack_var_size (mode, type); | |
4735 | else | |
4736 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
4737 | } | |
4738 | ||
c229cba9 DE |
4739 | /* If defined, a C expression which determines whether, and in which |
4740 | direction, to pad out an argument with extra space. The value | |
4741 | should be of type `enum direction': either `upward' to pad above | |
4742 | the argument, `downward' to pad below, or `none' to inhibit | |
4743 | padding. | |
4744 | ||
4745 | For the AIX ABI structs are always stored left shifted in their | |
4746 | argument slot. */ | |
4747 | ||
9ebbca7d | 4748 | enum direction |
a2369ed3 | 4749 | function_arg_padding (enum machine_mode mode, tree type) |
c229cba9 | 4750 | { |
6e985040 AM |
4751 | #ifndef AGGREGATE_PADDING_FIXED |
4752 | #define AGGREGATE_PADDING_FIXED 0 | |
4753 | #endif | |
4754 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
4755 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
4756 | #endif | |
4757 | ||
4758 | if (!AGGREGATE_PADDING_FIXED) | |
4759 | { | |
4760 | /* GCC used to pass structures of the same size as integer types as | |
4761 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
19525b57 | 4762 | i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were |
6e985040 AM |
4763 | passed padded downward, except that -mstrict-align further |
4764 | muddied the water in that multi-component structures of 2 and 4 | |
4765 | bytes in size were passed padded upward. | |
4766 | ||
4767 | The following arranges for best compatibility with previous | |
4768 | versions of gcc, but removes the -mstrict-align dependency. */ | |
4769 | if (BYTES_BIG_ENDIAN) | |
4770 | { | |
4771 | HOST_WIDE_INT size = 0; | |
4772 | ||
4773 | if (mode == BLKmode) | |
4774 | { | |
4775 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
4776 | size = int_size_in_bytes (type); | |
4777 | } | |
4778 | else | |
4779 | size = GET_MODE_SIZE (mode); | |
4780 | ||
4781 | if (size == 1 || size == 2 || size == 4) | |
4782 | return downward; | |
4783 | } | |
4784 | return upward; | |
4785 | } | |
4786 | ||
4787 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
4788 | { | |
4789 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
4790 | return upward; | |
4791 | } | |
c229cba9 | 4792 | |
d3704c46 KH |
4793 | /* Fall back to the default. */ |
4794 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
4795 | } |
4796 | ||
b6c9286a | 4797 | /* If defined, a C expression that gives the alignment boundary, in bits, |
f676971a | 4798 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a | 4799 | PARM_BOUNDARY is used for all arguments. |
f676971a | 4800 | |
b693336b PB |
4801 | V.4 wants long longs to be double word aligned. |
4802 | Doubleword align SPE vectors. | |
4803 | Quadword align Altivec vectors. | |
4804 | Quadword align large synthetic vector types. */ | |
b6c9286a MM |
4805 | |
4806 | int | |
b693336b | 4807 | function_arg_boundary (enum machine_mode mode, tree type) |
b6c9286a | 4808 | { |
4ed78545 AM |
4809 | if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8) |
4810 | return 64; | |
4811 | else if (SPE_VECTOR_MODE (mode)) | |
e1f83b4d | 4812 | return 64; |
b2d04ecf | 4813 | else if (ALTIVEC_VECTOR_MODE (mode)) |
0ac081f6 | 4814 | return 128; |
b693336b PB |
4815 | else if (type && TREE_CODE (type) == VECTOR_TYPE |
4816 | && int_size_in_bytes (type) > 16) | |
4817 | return 128; | |
9ebbca7d | 4818 | else |
b6c9286a | 4819 | return PARM_BOUNDARY; |
b6c9286a | 4820 | } |
c53bdcf5 AM |
4821 | |
4822 | /* Compute the size (in words) of a function argument. */ | |
4823 | ||
4824 | static unsigned long | |
4825 | rs6000_arg_size (enum machine_mode mode, tree type) | |
4826 | { | |
4827 | unsigned long size; | |
4828 | ||
4829 | if (mode != BLKmode) | |
4830 | size = GET_MODE_SIZE (mode); | |
4831 | else | |
4832 | size = int_size_in_bytes (type); | |
4833 | ||
4834 | if (TARGET_32BIT) | |
4835 | return (size + 3) >> 2; | |
4836 | else | |
4837 | return (size + 7) >> 3; | |
4838 | } | |
b6c9286a | 4839 | \f |
594a51fe SS |
4840 | /* The darwin64 ABI calls for us to recurse down through structs, |
4841 | applying the same rules to struct elements as if a reference to | |
4842 | each were being passed directly. */ | |
4843 | ||
4844 | static void | |
4845 | darwin64_function_arg_advance (CUMULATIVE_ARGS *cum, tree type, | |
4846 | int named, int depth) | |
4847 | { | |
4848 | tree f, ftype; | |
4849 | int i, tot; | |
4850 | ||
4851 | switch (TREE_CODE (type)) | |
4852 | { | |
4853 | case RECORD_TYPE: | |
4854 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
4855 | if (TREE_CODE (f) == FIELD_DECL) | |
4856 | { | |
4857 | ftype = TREE_TYPE (f); | |
4858 | function_arg_advance (cum, TYPE_MODE (ftype), ftype, | |
4859 | named, depth + 1); | |
4860 | } | |
4861 | break; | |
4862 | ||
4863 | case ARRAY_TYPE: | |
4864 | tot = int_size_in_bytes (type); | |
4865 | if (tot <= 0) | |
4866 | return; | |
4867 | ftype = TREE_TYPE (type); | |
4868 | tot /= int_size_in_bytes (ftype); | |
4869 | ||
4870 | for (i = 0; i < tot; ++i) | |
4871 | { | |
4872 | function_arg_advance (cum, TYPE_MODE (ftype), ftype, | |
4873 | named, depth + 1); | |
4874 | } | |
4875 | break; | |
4876 | ||
4877 | default: | |
4878 | abort (); | |
4879 | } | |
4880 | } | |
4881 | ||
4697a36c MM |
4882 | /* Update the data in CUM to advance over an argument |
4883 | of mode MODE and data type TYPE. | |
b2d04ecf AM |
4884 | (TYPE is null for libcalls where that information may not be available.) |
4885 | ||
4886 | Note that for args passed by reference, function_arg will be called | |
4887 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4888 | itself. */ | |
4697a36c MM |
4889 | |
4890 | void | |
f676971a | 4891 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
594a51fe | 4892 | tree type, int named, int depth) |
4697a36c | 4893 | { |
594a51fe SS |
4894 | /* Only tick off an argument if we're not recursing. */ |
4895 | if (depth == 0) | |
4896 | cum->nargs_prototype--; | |
4697a36c | 4897 | |
0ac081f6 AH |
4898 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
4899 | { | |
4ed78545 AM |
4900 | bool stack = false; |
4901 | ||
2858f73a | 4902 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c4ad648e | 4903 | { |
6d0ef01e HP |
4904 | cum->vregno++; |
4905 | if (!TARGET_ALTIVEC) | |
4906 | error ("Cannot pass argument in vector register because" | |
4907 | " altivec instructions are disabled, use -maltivec" | |
4908 | " to enable them."); | |
4ed78545 AM |
4909 | |
4910 | /* PowerPC64 Linux and AIX allocate GPRs for a vector argument | |
f676971a | 4911 | even if it is going to be passed in a vector register. |
4ed78545 AM |
4912 | Darwin does the same for variable-argument functions. */ |
4913 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4914 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
4915 | stack = true; | |
6d0ef01e | 4916 | } |
4ed78545 AM |
4917 | else |
4918 | stack = true; | |
4919 | ||
4920 | if (stack) | |
c4ad648e | 4921 | { |
a594a19c | 4922 | int align; |
f676971a | 4923 | |
2858f73a GK |
4924 | /* Vector parameters must be 16-byte aligned. This places |
4925 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
4926 | the parameter save area starts at offset 24 from the | |
4927 | stack. In 64-bit mode, they just have to start on an | |
4928 | even word, since the parameter save area is 16-byte | |
4929 | aligned. Space for GPRs is reserved even if the argument | |
4930 | will be passed in memory. */ | |
4931 | if (TARGET_32BIT) | |
4ed78545 | 4932 | align = (2 - cum->words) & 3; |
2858f73a GK |
4933 | else |
4934 | align = cum->words & 1; | |
c53bdcf5 | 4935 | cum->words += align + rs6000_arg_size (mode, type); |
f676971a | 4936 | |
a594a19c GK |
4937 | if (TARGET_DEBUG_ARG) |
4938 | { | |
f676971a | 4939 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", |
a594a19c GK |
4940 | cum->words, align); |
4941 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
f676971a | 4942 | cum->nargs_prototype, cum->prototype, |
2858f73a | 4943 | GET_MODE_NAME (mode)); |
a594a19c GK |
4944 | } |
4945 | } | |
0ac081f6 | 4946 | } |
a4b0320c | 4947 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
4948 | && !cum->stdarg |
4949 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 4950 | cum->sysv_gregno++; |
594a51fe SS |
4951 | |
4952 | else if (rs6000_darwin64_abi | |
4953 | && mode == BLKmode | |
4954 | && (TREE_CODE (type) == RECORD_TYPE | |
4955 | || TREE_CODE (type) == ARRAY_TYPE)) | |
4956 | darwin64_function_arg_advance (cum, type, named, depth); | |
4957 | ||
f607bc57 | 4958 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4959 | { |
a3170dc6 | 4960 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 4961 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 4962 | { |
4cc833b7 RH |
4963 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
4964 | cum->fregno++; | |
4965 | else | |
4966 | { | |
4967 | if (mode == DFmode) | |
c4ad648e | 4968 | cum->words += cum->words & 1; |
c53bdcf5 | 4969 | cum->words += rs6000_arg_size (mode, type); |
4cc833b7 | 4970 | } |
4697a36c | 4971 | } |
4cc833b7 RH |
4972 | else |
4973 | { | |
b2d04ecf | 4974 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4975 | int gregno = cum->sysv_gregno; |
4976 | ||
4ed78545 AM |
4977 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4978 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4979 | as complex int due to a historical mistake. */ | |
4980 | if (n_words == 2) | |
4981 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4982 | |
4ed78545 | 4983 | /* Multi-reg args are not split between registers and stack. */ |
4cc833b7 RH |
4984 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
4985 | { | |
4ed78545 AM |
4986 | /* Long long and SPE vectors are aligned on the stack. |
4987 | So are other 2 word items such as complex int due to | |
4988 | a historical mistake. */ | |
4cc833b7 RH |
4989 | if (n_words == 2) |
4990 | cum->words += cum->words & 1; | |
4991 | cum->words += n_words; | |
4992 | } | |
4697a36c | 4993 | |
4cc833b7 RH |
4994 | /* Note: continuing to accumulate gregno past when we've started |
4995 | spilling to the stack indicates the fact that we've started | |
4996 | spilling to the stack to expand_builtin_saveregs. */ | |
4997 | cum->sysv_gregno = gregno + n_words; | |
4998 | } | |
4697a36c | 4999 | |
4cc833b7 RH |
5000 | if (TARGET_DEBUG_ARG) |
5001 | { | |
5002 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
5003 | cum->words, cum->fregno); | |
5004 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
5005 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
5006 | fprintf (stderr, "mode = %4s, named = %d\n", | |
5007 | GET_MODE_NAME (mode), named); | |
5008 | } | |
4697a36c MM |
5009 | } |
5010 | else | |
4cc833b7 | 5011 | { |
b2d04ecf AM |
5012 | int n_words = rs6000_arg_size (mode, type); |
5013 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; | |
a4f6c312 | 5014 | |
b2d04ecf AM |
5015 | /* The simple alignment calculation here works because |
5016 | function_arg_boundary / PARM_BOUNDARY will only be 1 or 2. | |
5017 | If we ever want to handle alignments larger than 8 bytes for | |
5018 | 32-bit or 16 bytes for 64-bit, then we'll need to take into | |
5019 | account the offset to the start of the parm save area. */ | |
5020 | align &= cum->words; | |
5021 | cum->words += align + n_words; | |
4697a36c | 5022 | |
a3170dc6 AH |
5023 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
5024 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
c53bdcf5 | 5025 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; |
4cc833b7 RH |
5026 | |
5027 | if (TARGET_DEBUG_ARG) | |
5028 | { | |
5029 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
5030 | cum->words, cum->fregno); | |
5031 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
5032 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
594a51fe SS |
5033 | fprintf (stderr, "named = %d, align = %d, depth = %d\n", |
5034 | named, align, depth); | |
4cc833b7 RH |
5035 | } |
5036 | } | |
4697a36c | 5037 | } |
a6c9bed4 | 5038 | |
f82f556d AH |
5039 | static rtx |
5040 | spe_build_register_parallel (enum machine_mode mode, int gregno) | |
5041 | { | |
18f63bfa AH |
5042 | rtx r1, r2, r3, r4; |
5043 | enum machine_mode inner = SImode; | |
f82f556d AH |
5044 | |
5045 | if (mode == DFmode) | |
5046 | { | |
18f63bfa AH |
5047 | r1 = gen_rtx_REG (inner, gregno); |
5048 | r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx); | |
5049 | r2 = gen_rtx_REG (inner, gregno + 1); | |
5050 | r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (4)); | |
5051 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
5052 | } | |
5053 | else if (mode == DCmode) | |
5054 | { | |
5055 | r1 = gen_rtx_REG (inner, gregno); | |
5056 | r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx); | |
5057 | r2 = gen_rtx_REG (inner, gregno + 1); | |
5058 | r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (4)); | |
5059 | r3 = gen_rtx_REG (inner, gregno + 2); | |
5060 | r3 = gen_rtx_EXPR_LIST (SImode, r3, GEN_INT (8)); | |
5061 | r4 = gen_rtx_REG (inner, gregno + 3); | |
5062 | r4 = gen_rtx_EXPR_LIST (SImode, r4, GEN_INT (12)); | |
5063 | return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r2, r3, r4)); | |
f82f556d | 5064 | } |
f82f556d | 5065 | |
18f63bfa AH |
5066 | abort (); |
5067 | return NULL_RTX; | |
f82f556d | 5068 | } |
b78d48dd | 5069 | |
f82f556d | 5070 | /* Determine where to put a SIMD argument on the SPE. */ |
a6c9bed4 | 5071 | static rtx |
f676971a | 5072 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 5073 | tree type) |
a6c9bed4 | 5074 | { |
f82f556d AH |
5075 | int gregno = cum->sysv_gregno; |
5076 | ||
5077 | /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but | |
600e1f95 | 5078 | are passed and returned in a pair of GPRs for ABI compatibility. */ |
18f63bfa | 5079 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode)) |
f82f556d AH |
5080 | { |
5081 | /* Doubles go in an odd/even register pair (r5/r6, etc). */ | |
5082 | gregno += (1 - gregno) & 1; | |
5083 | ||
5084 | /* We do not split between registers and stack. */ | |
5085 | if (gregno + 1 > GP_ARG_MAX_REG) | |
5086 | return NULL_RTX; | |
5087 | ||
5088 | return spe_build_register_parallel (mode, gregno); | |
5089 | } | |
a6c9bed4 AH |
5090 | if (cum->stdarg) |
5091 | { | |
c53bdcf5 | 5092 | int n_words = rs6000_arg_size (mode, type); |
a6c9bed4 AH |
5093 | |
5094 | /* SPE vectors are put in odd registers. */ | |
5095 | if (n_words == 2 && (gregno & 1) == 0) | |
5096 | gregno += 1; | |
5097 | ||
5098 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
5099 | { | |
5100 | rtx r1, r2; | |
5101 | enum machine_mode m = SImode; | |
5102 | ||
5103 | r1 = gen_rtx_REG (m, gregno); | |
5104 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
5105 | r2 = gen_rtx_REG (m, gregno + 1); | |
5106 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
5107 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
5108 | } | |
5109 | else | |
b78d48dd | 5110 | return NULL_RTX; |
a6c9bed4 AH |
5111 | } |
5112 | else | |
5113 | { | |
f82f556d AH |
5114 | if (gregno <= GP_ARG_MAX_REG) |
5115 | return gen_rtx_REG (mode, gregno); | |
a6c9bed4 | 5116 | else |
b78d48dd | 5117 | return NULL_RTX; |
a6c9bed4 AH |
5118 | } |
5119 | } | |
5120 | ||
594a51fe SS |
5121 | /* For the darwin64 ABI, we want to construct a PARALLEL consisting of |
5122 | the register(s) to be used for each field and subfield of a struct | |
5123 | being passed by value, along with the offset of where the | |
5124 | register's value may be found in the block. */ | |
5125 | ||
5126 | static rtx | |
5127 | rs6000_darwin64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
5128 | tree type, int named) | |
5129 | { | |
5130 | tree f, ftype, offset; | |
5131 | rtx rvec[FIRST_PSEUDO_REGISTER], sub, suboff, roffset; | |
5132 | int k = 0, i, j, bytepos, subbytepos, tot; | |
5133 | CUMULATIVE_ARGS saved_cum = *cum; | |
5134 | enum machine_mode submode; | |
5135 | ||
5136 | switch (TREE_CODE (type)) | |
5137 | { | |
5138 | case RECORD_TYPE: | |
5139 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
5140 | if (TREE_CODE (f) == FIELD_DECL) | |
5141 | { | |
5142 | ftype = TREE_TYPE (f); | |
5143 | offset = DECL_FIELD_OFFSET (f); | |
5144 | bytepos = int_bit_position (f) / BITS_PER_UNIT; | |
5145 | /* Force substructs to be handled as BLKmode even if | |
5146 | they're small enough to be recorded as DImode, so we | |
5147 | drill through to non-record fields. */ | |
5148 | submode = TYPE_MODE (ftype); | |
5149 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
5150 | submode = BLKmode; | |
5151 | sub = function_arg (cum, submode, ftype, named); | |
5152 | if (sub == NULL_RTX) | |
5153 | return NULL_RTX; | |
5154 | if (GET_CODE (sub) == PARALLEL) | |
5155 | { | |
5156 | for (i = 0; i < XVECLEN (sub, 0); i++) | |
5157 | { | |
5158 | rtx subsub = XVECEXP (sub, 0, i); | |
5159 | suboff = XEXP (subsub, 1); | |
5160 | subbytepos = INTVAL (suboff); | |
5161 | subbytepos += bytepos; | |
5162 | roffset = gen_rtx_CONST_INT (SImode, subbytepos); | |
5163 | subsub = XEXP (subsub, 0); | |
5164 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset); | |
5165 | } | |
5166 | } | |
5167 | else | |
5168 | { | |
5169 | roffset = gen_rtx_CONST_INT (SImode, bytepos); | |
5170 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset); | |
5171 | } | |
5172 | /* Now do an arg advance to get all the cumulative arg | |
5173 | stuff set correctly for the next subfield. Note that it | |
5174 | has no lasting effect, because it is being done on a | |
5175 | temporary copy of the cumulative arg data. */ | |
5176 | function_arg_advance (cum, submode, ftype, named, 1); | |
5177 | } | |
5178 | break; | |
5179 | ||
8ff40a74 SS |
5180 | case UNION_TYPE: |
5181 | tot = rs6000_arg_size (mode, type); | |
5182 | if (tot <= 0) | |
5183 | return NULL_RTX; | |
5184 | bytepos = 0; | |
5185 | ||
5186 | for (j = 0; j < tot; ++j) | |
5187 | { | |
5188 | sub = gen_rtx_REG ((TARGET_64BIT ? DImode : SImode), GP_ARG_MIN_REG + cum->words++); | |
5189 | roffset = gen_rtx_CONST_INT (SImode, bytepos); | |
5190 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset); | |
5191 | if (cum->words >= GP_ARG_NUM_REG) | |
5192 | break; | |
5193 | bytepos += (TARGET_64BIT ? 8 : 4); | |
5194 | } | |
5195 | break; | |
5196 | ||
594a51fe SS |
5197 | case ARRAY_TYPE: |
5198 | tot = int_size_in_bytes (type); | |
5199 | if (tot <= 0) | |
5200 | return NULL_RTX; | |
5201 | ftype = TREE_TYPE (type); | |
5202 | tot /= int_size_in_bytes (ftype); | |
5203 | bytepos = 0; | |
5204 | ||
5205 | for (j = 0; j < tot; ++j) | |
5206 | { | |
5207 | /* Force substructs to be handled as BLKmode even if | |
5208 | they're small enough to be recorded as DImode, so we | |
5209 | drill through to non-record fields. */ | |
5210 | submode = TYPE_MODE (ftype); | |
5211 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
5212 | submode = BLKmode; | |
5213 | sub = function_arg (cum, submode, ftype, named); | |
5214 | if (sub == NULL_RTX) | |
5215 | return NULL_RTX; | |
5216 | if (GET_CODE (sub) == PARALLEL) | |
5217 | { | |
5218 | for (i = 0; i < XVECLEN (sub, 0); i++) | |
5219 | { | |
5220 | rtx subsub = XVECEXP (sub, 0, i); | |
5221 | ||
5222 | suboff = XEXP (subsub, 1); | |
5223 | subbytepos = INTVAL (suboff); | |
5224 | subbytepos += bytepos; | |
5225 | roffset = gen_rtx_CONST_INT (SImode, subbytepos); | |
5226 | subsub = XEXP (subsub, 0); | |
5227 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset); | |
5228 | } | |
5229 | } | |
5230 | else | |
5231 | { | |
5232 | roffset = gen_rtx_CONST_INT (SImode, bytepos); | |
5233 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset); | |
5234 | } | |
5235 | /* Now do an arg advance to get all the cumulative arg | |
5236 | stuff set correctly for the next subfield. Note that it | |
5237 | has no lasting effect, because it is being done on a | |
5238 | temporary copy of the cumulative arg data. */ | |
5239 | function_arg_advance (cum, submode, ftype, named, 1); | |
5240 | bytepos += int_size_in_bytes (ftype); | |
5241 | } | |
5242 | break; | |
5243 | ||
5244 | default: | |
5245 | abort (); | |
5246 | } | |
5247 | ||
5248 | *cum = saved_cum; | |
5249 | if (k > 0) | |
5250 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
5251 | else | |
5252 | return NULL_RTX; | |
5253 | } | |
5254 | ||
b78d48dd FJ |
5255 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
5256 | ||
5257 | static rtx | |
ec6376ab | 5258 | rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) |
b78d48dd | 5259 | { |
ec6376ab AM |
5260 | int n_units; |
5261 | int i, k; | |
5262 | rtx rvec[GP_ARG_NUM_REG + 1]; | |
5263 | ||
5264 | if (align_words >= GP_ARG_NUM_REG) | |
5265 | return NULL_RTX; | |
5266 | ||
5267 | n_units = rs6000_arg_size (mode, type); | |
5268 | ||
5269 | /* Optimize the simple case where the arg fits in one gpr, except in | |
5270 | the case of BLKmode due to assign_parms assuming that registers are | |
5271 | BITS_PER_WORD wide. */ | |
5272 | if (n_units == 0 | |
5273 | || (n_units == 1 && mode != BLKmode)) | |
5274 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5275 | ||
5276 | k = 0; | |
5277 | if (align_words + n_units > GP_ARG_NUM_REG) | |
5278 | /* Not all of the arg fits in gprs. Say that it goes in memory too, | |
5279 | using a magic NULL_RTX component. | |
5280 | FIXME: This is not strictly correct. Only some of the arg | |
5281 | belongs in memory, not all of it. However, there isn't any way | |
5282 | to do this currently, apart from building rtx descriptions for | |
5283 | the pieces of memory we want stored. Due to bugs in the generic | |
5284 | code we can't use the normal function_arg_partial_nregs scheme | |
5285 | with the PARALLEL arg description we emit here. | |
5286 | In any case, the code to store the whole arg to memory is often | |
5287 | more efficient than code to store pieces, and we know that space | |
5288 | is available in the right place for the whole arg. */ | |
5289 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
5290 | ||
5291 | i = 0; | |
5292 | do | |
36a454e1 | 5293 | { |
ec6376ab AM |
5294 | rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); |
5295 | rtx off = GEN_INT (i++ * 4); | |
5296 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
36a454e1 | 5297 | } |
ec6376ab AM |
5298 | while (++align_words < GP_ARG_NUM_REG && --n_units != 0); |
5299 | ||
5300 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
b78d48dd FJ |
5301 | } |
5302 | ||
4697a36c MM |
5303 | /* Determine where to put an argument to a function. |
5304 | Value is zero to push the argument on the stack, | |
5305 | or a hard register in which to store the argument. | |
5306 | ||
5307 | MODE is the argument's machine mode. | |
5308 | TYPE is the data type of the argument (as a tree). | |
5309 | This is null for libcalls where that information may | |
5310 | not be available. | |
5311 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
5312 | the preceding args and about the function being called. | |
5313 | NAMED is nonzero if this argument is a named parameter | |
5314 | (otherwise it is an extra parameter matching an ellipsis). | |
5315 | ||
5316 | On RS/6000 the first eight words of non-FP are normally in registers | |
5317 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
5318 | Under V.4, the first 8 FP args are in registers. | |
5319 | ||
5320 | If this is floating-point and no prototype is specified, we use | |
5321 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 5322 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 5323 | so we can pass the FP value just in one register. emit_library_function |
b2d04ecf AM |
5324 | doesn't support PARALLEL anyway. |
5325 | ||
5326 | Note that for args passed by reference, function_arg will be called | |
5327 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
5328 | itself. */ | |
4697a36c MM |
5329 | |
5330 | struct rtx_def * | |
f676971a | 5331 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 5332 | tree type, int named) |
4697a36c | 5333 | { |
4cc833b7 | 5334 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 5335 | |
a4f6c312 SS |
5336 | /* Return a marker to indicate whether CR1 needs to set or clear the |
5337 | bit that V.4 uses to say fp args were passed in registers. | |
5338 | Assume that we don't need the marker for software floating point, | |
5339 | or compiler generated library calls. */ | |
4697a36c MM |
5340 | if (mode == VOIDmode) |
5341 | { | |
f607bc57 | 5342 | if (abi == ABI_V4 |
7509c759 | 5343 | && cum->nargs_prototype < 0 |
b9599e46 FS |
5344 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
5345 | && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
7509c759 | 5346 | { |
a3170dc6 AH |
5347 | /* For the SPE, we need to crxor CR6 always. */ |
5348 | if (TARGET_SPE_ABI) | |
5349 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
5350 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
5351 | return GEN_INT (cum->call_cookie | |
5352 | | ((cum->fregno == FP_ARG_MIN_REG) | |
5353 | ? CALL_V4_SET_FP_ARGS | |
5354 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 5355 | } |
4697a36c | 5356 | |
7509c759 | 5357 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
5358 | } |
5359 | ||
8ff40a74 SS |
5360 | if (mode == BLKmode |
5361 | && rs6000_darwin64_abi | |
5362 | && (TREE_CODE (type) == RECORD_TYPE | |
5363 | || TREE_CODE (type) == UNION_TYPE | |
5364 | || TREE_CODE (type) == ARRAY_TYPE)) | |
5365 | { | |
5366 | rtx rslt = rs6000_darwin64_function_arg (cum, mode, type, named); | |
5367 | if (rslt != NULL_RTX) | |
5368 | return rslt; | |
5369 | /* Else fall through to usual handling. */ | |
5370 | } | |
5371 | ||
2858f73a | 5372 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
5373 | if (TARGET_64BIT && ! cum->prototype) |
5374 | { | |
c4ad648e AM |
5375 | /* Vector parameters get passed in vector register |
5376 | and also in GPRs or memory, in absence of prototype. */ | |
5377 | int align_words; | |
5378 | rtx slot; | |
5379 | align_words = (cum->words + 1) & ~1; | |
5380 | ||
5381 | if (align_words >= GP_ARG_NUM_REG) | |
5382 | { | |
5383 | slot = NULL_RTX; | |
5384 | } | |
5385 | else | |
5386 | { | |
5387 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5388 | } | |
5389 | return gen_rtx_PARALLEL (mode, | |
5390 | gen_rtvec (2, | |
5391 | gen_rtx_EXPR_LIST (VOIDmode, | |
5392 | slot, const0_rtx), | |
5393 | gen_rtx_EXPR_LIST (VOIDmode, | |
5394 | gen_rtx_REG (mode, cum->vregno), | |
5395 | const0_rtx))); | |
c72d6c26 HP |
5396 | } |
5397 | else | |
5398 | return gen_rtx_REG (mode, cum->vregno); | |
2858f73a | 5399 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
0ac081f6 | 5400 | { |
2858f73a | 5401 | if (named || abi == ABI_V4) |
a594a19c | 5402 | return NULL_RTX; |
0ac081f6 | 5403 | else |
a594a19c GK |
5404 | { |
5405 | /* Vector parameters to varargs functions under AIX or Darwin | |
5406 | get passed in memory and possibly also in GPRs. */ | |
ec6376ab AM |
5407 | int align, align_words, n_words; |
5408 | enum machine_mode part_mode; | |
a594a19c GK |
5409 | |
5410 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
5411 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
5412 | save area starts at offset 24 from the stack. In 64-bit mode, | |
5413 | they just have to start on an even word, since the parameter | |
5414 | save area is 16-byte aligned. */ | |
5415 | if (TARGET_32BIT) | |
4ed78545 | 5416 | align = (2 - cum->words) & 3; |
2858f73a GK |
5417 | else |
5418 | align = cum->words & 1; | |
a594a19c GK |
5419 | align_words = cum->words + align; |
5420 | ||
5421 | /* Out of registers? Memory, then. */ | |
5422 | if (align_words >= GP_ARG_NUM_REG) | |
5423 | return NULL_RTX; | |
ec6376ab AM |
5424 | |
5425 | if (TARGET_32BIT && TARGET_POWERPC64) | |
5426 | return rs6000_mixed_function_arg (mode, type, align_words); | |
5427 | ||
2858f73a GK |
5428 | /* The vector value goes in GPRs. Only the part of the |
5429 | value in GPRs is reported here. */ | |
ec6376ab AM |
5430 | part_mode = mode; |
5431 | n_words = rs6000_arg_size (mode, type); | |
5432 | if (align_words + n_words > GP_ARG_NUM_REG) | |
839a4992 | 5433 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
5434 | is either wholly in GPRs or half in GPRs and half not. */ |
5435 | part_mode = DImode; | |
ec6376ab AM |
5436 | |
5437 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 5438 | } |
0ac081f6 | 5439 | } |
f82f556d AH |
5440 | else if (TARGET_SPE_ABI && TARGET_SPE |
5441 | && (SPE_VECTOR_MODE (mode) | |
18f63bfa AH |
5442 | || (TARGET_E500_DOUBLE && (mode == DFmode |
5443 | || mode == DCmode)))) | |
a6c9bed4 | 5444 | return rs6000_spe_function_arg (cum, mode, type); |
594a51fe | 5445 | |
f607bc57 | 5446 | else if (abi == ABI_V4) |
4697a36c | 5447 | { |
a3170dc6 | 5448 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
5449 | && (mode == SFmode || mode == DFmode)) |
5450 | { | |
5451 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
5452 | return gen_rtx_REG (mode, cum->fregno); | |
5453 | else | |
b78d48dd | 5454 | return NULL_RTX; |
4cc833b7 RH |
5455 | } |
5456 | else | |
5457 | { | |
b2d04ecf | 5458 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
5459 | int gregno = cum->sysv_gregno; |
5460 | ||
4ed78545 AM |
5461 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
5462 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
5463 | as complex int due to a historical mistake. */ | |
5464 | if (n_words == 2) | |
5465 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 5466 | |
4ed78545 | 5467 | /* Multi-reg args are not split between registers and stack. */ |
ec6376ab | 5468 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
b78d48dd | 5469 | return NULL_RTX; |
ec6376ab AM |
5470 | |
5471 | if (TARGET_32BIT && TARGET_POWERPC64) | |
5472 | return rs6000_mixed_function_arg (mode, type, | |
5473 | gregno - GP_ARG_MIN_REG); | |
5474 | return gen_rtx_REG (mode, gregno); | |
4cc833b7 | 5475 | } |
4697a36c | 5476 | } |
4cc833b7 RH |
5477 | else |
5478 | { | |
b2d04ecf AM |
5479 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
5480 | int align_words = cum->words + (cum->words & align); | |
b78d48dd | 5481 | |
2858f73a | 5482 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 | 5483 | { |
ec6376ab AM |
5484 | rtx rvec[GP_ARG_NUM_REG + 1]; |
5485 | rtx r; | |
5486 | int k; | |
c53bdcf5 AM |
5487 | bool needs_psave; |
5488 | enum machine_mode fmode = mode; | |
c53bdcf5 AM |
5489 | unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; |
5490 | ||
5491 | if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) | |
5492 | { | |
c53bdcf5 AM |
5493 | /* Currently, we only ever need one reg here because complex |
5494 | doubles are split. */ | |
ec6376ab | 5495 | if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode) |
c53bdcf5 | 5496 | abort (); |
ec6376ab AM |
5497 | |
5498 | /* Long double split over regs and memory. */ | |
5499 | fmode = DFmode; | |
c53bdcf5 | 5500 | } |
c53bdcf5 AM |
5501 | |
5502 | /* Do we also need to pass this arg in the parameter save | |
5503 | area? */ | |
5504 | needs_psave = (type | |
5505 | && (cum->nargs_prototype <= 0 | |
5506 | || (DEFAULT_ABI == ABI_AIX | |
5507 | && TARGET_XL_CALL | |
5508 | && align_words >= GP_ARG_NUM_REG))); | |
5509 | ||
5510 | if (!needs_psave && mode == fmode) | |
ec6376ab | 5511 | return gen_rtx_REG (fmode, cum->fregno); |
c53bdcf5 | 5512 | |
ec6376ab | 5513 | k = 0; |
c53bdcf5 AM |
5514 | if (needs_psave) |
5515 | { | |
ec6376ab | 5516 | /* Describe the part that goes in gprs or the stack. |
c53bdcf5 | 5517 | This piece must come first, before the fprs. */ |
c53bdcf5 AM |
5518 | if (align_words < GP_ARG_NUM_REG) |
5519 | { | |
5520 | unsigned long n_words = rs6000_arg_size (mode, type); | |
ec6376ab AM |
5521 | |
5522 | if (align_words + n_words > GP_ARG_NUM_REG | |
5523 | || (TARGET_32BIT && TARGET_POWERPC64)) | |
5524 | { | |
5525 | /* If this is partially on the stack, then we only | |
5526 | include the portion actually in registers here. */ | |
5527 | enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; | |
5528 | rtx off; | |
2e6c9641 | 5529 | int i=0; |
c4ad648e AM |
5530 | if (align_words + n_words > GP_ARG_NUM_REG |
5531 | && (TARGET_32BIT && TARGET_POWERPC64)) | |
5532 | /* Not all of the arg fits in gprs. Say that it | |
5533 | goes in memory too, using a magic NULL_RTX | |
5534 | component. Also see comment in | |
5535 | rs6000_mixed_function_arg for why the normal | |
5536 | function_arg_partial_nregs scheme doesn't work | |
5537 | in this case. */ | |
5538 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, | |
5539 | const0_rtx); | |
ec6376ab AM |
5540 | do |
5541 | { | |
5542 | r = gen_rtx_REG (rmode, | |
5543 | GP_ARG_MIN_REG + align_words); | |
2e6c9641 | 5544 | off = GEN_INT (i++ * GET_MODE_SIZE (rmode)); |
ec6376ab AM |
5545 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); |
5546 | } | |
5547 | while (++align_words < GP_ARG_NUM_REG && --n_words != 0); | |
5548 | } | |
5549 | else | |
5550 | { | |
5551 | /* The whole arg fits in gprs. */ | |
5552 | r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5553 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5554 | } | |
c53bdcf5 | 5555 | } |
ec6376ab AM |
5556 | else |
5557 | /* It's entirely in memory. */ | |
5558 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
c53bdcf5 AM |
5559 | } |
5560 | ||
ec6376ab AM |
5561 | /* Describe where this piece goes in the fprs. */ |
5562 | r = gen_rtx_REG (fmode, cum->fregno); | |
5563 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5564 | ||
5565 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
4cc833b7 RH |
5566 | } |
5567 | else if (align_words < GP_ARG_NUM_REG) | |
b2d04ecf | 5568 | { |
ec6376ab AM |
5569 | if (TARGET_32BIT && TARGET_POWERPC64) |
5570 | return rs6000_mixed_function_arg (mode, type, align_words); | |
b2d04ecf | 5571 | |
4eeca74f AM |
5572 | if (mode == BLKmode) |
5573 | mode = Pmode; | |
5574 | ||
b2d04ecf AM |
5575 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); |
5576 | } | |
4cc833b7 RH |
5577 | else |
5578 | return NULL_RTX; | |
4697a36c | 5579 | } |
4697a36c MM |
5580 | } |
5581 | \f | |
ec6376ab AM |
5582 | /* For an arg passed partly in registers and partly in memory, this is |
5583 | the number of registers used. For args passed entirely in registers | |
5584 | or entirely in memory, zero. When an arg is described by a PARALLEL, | |
5585 | perhaps using more than one register type, this function returns the | |
5586 | number of registers used by the first element of the PARALLEL. */ | |
4697a36c MM |
5587 | |
5588 | int | |
f676971a | 5589 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
2858f73a | 5590 | tree type, int named) |
4697a36c | 5591 | { |
c53bdcf5 | 5592 | int ret = 0; |
ec6376ab AM |
5593 | int align; |
5594 | int parm_offset; | |
5595 | int align_words; | |
c53bdcf5 | 5596 | |
f607bc57 | 5597 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 5598 | return 0; |
4697a36c | 5599 | |
c53bdcf5 AM |
5600 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) |
5601 | && cum->nargs_prototype >= 0) | |
5602 | return 0; | |
5603 | ||
ec6376ab AM |
5604 | align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
5605 | parm_offset = TARGET_32BIT ? 2 : 0; | |
5606 | align_words = cum->words + ((parm_offset - cum->words) & align); | |
5607 | ||
5608 | if (USE_FP_FOR_ARG_P (cum, mode, type) | |
5609 | /* If we are passing this arg in gprs as well, then this function | |
5610 | should return the number of gprs (or memory) partially passed, | |
5611 | *not* the number of fprs. */ | |
5612 | && !(type | |
5613 | && (cum->nargs_prototype <= 0 | |
5614 | || (DEFAULT_ABI == ABI_AIX | |
5615 | && TARGET_XL_CALL | |
5616 | && align_words >= GP_ARG_NUM_REG)))) | |
4697a36c | 5617 | { |
c53bdcf5 | 5618 | if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1) |
ec6376ab | 5619 | ret = FP_ARG_MAX_REG + 1 - cum->fregno; |
c53bdcf5 | 5620 | else if (cum->nargs_prototype >= 0) |
4697a36c MM |
5621 | return 0; |
5622 | } | |
5623 | ||
ec6376ab AM |
5624 | if (align_words < GP_ARG_NUM_REG |
5625 | && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) | |
5626 | ret = GP_ARG_NUM_REG - align_words; | |
4697a36c | 5627 | |
c53bdcf5 AM |
5628 | if (ret != 0 && TARGET_DEBUG_ARG) |
5629 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
4697a36c | 5630 | |
c53bdcf5 | 5631 | return ret; |
4697a36c MM |
5632 | } |
5633 | \f | |
5634 | /* A C expression that indicates when an argument must be passed by | |
5635 | reference. If nonzero for an argument, a copy of that argument is | |
5636 | made in memory and a pointer to the argument is passed instead of | |
5637 | the argument itself. The pointer is passed in whatever way is | |
5638 | appropriate for passing a pointer to that type. | |
5639 | ||
b2d04ecf AM |
5640 | Under V.4, aggregates and long double are passed by reference. |
5641 | ||
5642 | As an extension to all 32-bit ABIs, AltiVec vectors are passed by | |
5643 | reference unless the AltiVec vector extension ABI is in force. | |
c8c99a68 DE |
5644 | |
5645 | As an extension to all ABIs, variable sized types are passed by | |
5646 | reference. */ | |
4697a36c | 5647 | |
8cd5a4e0 | 5648 | static bool |
f676971a EC |
5649 | rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
5650 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
8cd5a4e0 | 5651 | tree type, bool named ATTRIBUTE_UNUSED) |
4697a36c | 5652 | { |
b2d04ecf AM |
5653 | if ((DEFAULT_ABI == ABI_V4 |
5654 | && ((type && AGGREGATE_TYPE_P (type)) | |
5655 | || mode == TFmode)) | |
5656 | || (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
5657 | || (type && int_size_in_bytes (type) < 0)) | |
4697a36c MM |
5658 | { |
5659 | if (TARGET_DEBUG_ARG) | |
b2d04ecf | 5660 | fprintf (stderr, "function_arg_pass_by_reference\n"); |
4697a36c MM |
5661 | |
5662 | return 1; | |
5663 | } | |
b693336b PB |
5664 | |
5665 | /* Pass synthetic vectors in memory. */ | |
5666 | if (type && TREE_CODE (type) == VECTOR_TYPE | |
5667 | && int_size_in_bytes (type) > (TARGET_ALTIVEC ? 16 : 8)) | |
5668 | { | |
5669 | static bool warned_for_pass_big_vectors = false; | |
5670 | if (TARGET_DEBUG_ARG) | |
5671 | fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n"); | |
5672 | if (!warned_for_pass_big_vectors) | |
5673 | { | |
5674 | warning ("synthetic vector passed by reference: " | |
5675 | "non-standard ABI extension with no compatibility guarantee"); | |
5676 | warned_for_pass_big_vectors = true; | |
5677 | } | |
5678 | return 1; | |
5679 | } | |
5680 | ||
b2d04ecf | 5681 | return 0; |
4697a36c | 5682 | } |
5985c7a6 FJ |
5683 | |
5684 | static void | |
2d9db8eb | 5685 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
5686 | { |
5687 | int i; | |
5688 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
5689 | ||
5690 | if (nregs == 0) | |
5691 | return; | |
5692 | ||
c4ad648e | 5693 | for (i = 0; i < nregs; i++) |
5985c7a6 FJ |
5694 | { |
5695 | rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode)); | |
5696 | if (reload_completed) | |
c4ad648e AM |
5697 | { |
5698 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
5699 | tem = NULL_RTX; | |
5700 | else | |
5701 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
5702 | i * GET_MODE_SIZE(reg_mode)); | |
5703 | } | |
5985c7a6 FJ |
5704 | else |
5705 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
5706 | ||
5707 | if (tem == NULL_RTX) | |
c4ad648e | 5708 | abort (); |
5985c7a6 FJ |
5709 | |
5710 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
5711 | } | |
5712 | } | |
4697a36c MM |
5713 | \f |
5714 | /* Perform any needed actions needed for a function that is receiving a | |
f676971a | 5715 | variable number of arguments. |
4697a36c MM |
5716 | |
5717 | CUM is as above. | |
5718 | ||
5719 | MODE and TYPE are the mode and type of the current parameter. | |
5720 | ||
5721 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
5722 | that must be pushed by the prolog to pretend that our caller pushed | |
5723 | it. | |
5724 | ||
5725 | Normally, this macro will push all remaining incoming registers on the | |
5726 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
5727 | ||
c6e8c921 | 5728 | static void |
f676971a | 5729 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
c4ad648e AM |
5730 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5731 | int no_rtl) | |
4697a36c | 5732 | { |
4cc833b7 RH |
5733 | CUMULATIVE_ARGS next_cum; |
5734 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 5735 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 5736 | int first_reg_offset, set; |
4697a36c | 5737 | |
f31bf321 | 5738 | /* Skip the last named argument. */ |
d34c5b80 | 5739 | next_cum = *cum; |
594a51fe | 5740 | function_arg_advance (&next_cum, mode, type, 1, 0); |
4cc833b7 | 5741 | |
f607bc57 | 5742 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 5743 | { |
60e2d0ca | 5744 | if (! no_rtl) |
2c4974b7 | 5745 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 5746 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
5747 | |
5748 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 5749 | } |
60e2d0ca | 5750 | else |
4697a36c | 5751 | { |
d34c5b80 | 5752 | first_reg_offset = next_cum.words; |
4cc833b7 | 5753 | save_area = virtual_incoming_args_rtx; |
4697a36c | 5754 | |
fe984136 | 5755 | if (targetm.calls.must_pass_in_stack (mode, type)) |
c53bdcf5 | 5756 | first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); |
4cc833b7 | 5757 | } |
4697a36c | 5758 | |
dfafc897 | 5759 | set = get_varargs_alias_set (); |
5496b36f | 5760 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 5761 | { |
dfafc897 | 5762 | mem = gen_rtx_MEM (BLKmode, |
c4ad648e | 5763 | plus_constant (save_area, |
dfafc897 | 5764 | first_reg_offset * reg_size)), |
ba4828e0 | 5765 | set_mem_alias_set (mem, set); |
8ac61af7 | 5766 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 5767 | |
f676971a | 5768 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
c4ad648e | 5769 | GP_ARG_NUM_REG - first_reg_offset); |
4697a36c MM |
5770 | } |
5771 | ||
4697a36c | 5772 | /* Save FP registers if needed. */ |
f607bc57 | 5773 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
5774 | && TARGET_HARD_FLOAT && TARGET_FPRS |
5775 | && ! no_rtl | |
5496b36f | 5776 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 5777 | { |
5496b36f | 5778 | int fregno = next_cum.fregno; |
9ebbca7d | 5779 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
5780 | rtx lab = gen_label_rtx (); |
5781 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 5782 | |
c4ad648e AM |
5783 | emit_jump_insn |
5784 | (gen_rtx_SET (VOIDmode, | |
5785 | pc_rtx, | |
5786 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4cc833b7 | 5787 | gen_rtx_NE (VOIDmode, cr1, |
c4ad648e | 5788 | const0_rtx), |
39403d82 | 5789 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
5790 | pc_rtx))); |
5791 | ||
5496b36f | 5792 | while (fregno <= FP_ARG_V4_MAX_REG) |
4cc833b7 | 5793 | { |
5496b36f | 5794 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
c4ad648e | 5795 | set_mem_alias_set (mem, set); |
94ff898d | 5796 | set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode)); |
dfafc897 | 5797 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
5496b36f JJ |
5798 | fregno++; |
5799 | off += 8; | |
4697a36c | 5800 | } |
4cc833b7 RH |
5801 | |
5802 | emit_label (lab); | |
4697a36c | 5803 | } |
4697a36c | 5804 | } |
4697a36c | 5805 | |
dfafc897 | 5806 | /* Create the va_list data type. */ |
2c4974b7 | 5807 | |
c35d187f RH |
5808 | static tree |
5809 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 5810 | { |
64c2816f | 5811 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 5812 | |
9ebbca7d GK |
5813 | /* For AIX, prefer 'char *' because that's what the system |
5814 | header files like. */ | |
f607bc57 | 5815 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 5816 | return build_pointer_type (char_type_node); |
dfafc897 | 5817 | |
f1e639b1 | 5818 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 5819 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 5820 | |
f676971a | 5821 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
9ebbca7d | 5822 | unsigned_char_type_node); |
f676971a | 5823 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), |
9ebbca7d | 5824 | unsigned_char_type_node); |
64c2816f DT |
5825 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
5826 | every user file. */ | |
5827 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
5828 | short_unsigned_type_node); | |
dfafc897 FS |
5829 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
5830 | ptr_type_node); | |
5831 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
5832 | ptr_type_node); | |
5833 | ||
5834 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
5835 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 5836 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
5837 | DECL_FIELD_CONTEXT (f_ovf) = record; |
5838 | DECL_FIELD_CONTEXT (f_sav) = record; | |
5839 | ||
bab45a51 FS |
5840 | TREE_CHAIN (record) = type_decl; |
5841 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
5842 | TYPE_FIELDS (record) = f_gpr; |
5843 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
5844 | TREE_CHAIN (f_fpr) = f_res; |
5845 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
5846 | TREE_CHAIN (f_ovf) = f_sav; |
5847 | ||
5848 | layout_type (record); | |
5849 | ||
5850 | /* The correct type is an array type of one element. */ | |
5851 | return build_array_type (record, build_index_type (size_zero_node)); | |
5852 | } | |
5853 | ||
5854 | /* Implement va_start. */ | |
5855 | ||
5856 | void | |
a2369ed3 | 5857 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 5858 | { |
dfafc897 | 5859 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 5860 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 5861 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 5862 | |
dfafc897 | 5863 | /* Only SVR4 needs something special. */ |
f607bc57 | 5864 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 5865 | { |
e5faf155 | 5866 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
5867 | return; |
5868 | } | |
5869 | ||
973a648b | 5870 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 5871 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
5872 | f_res = TREE_CHAIN (f_fpr); |
5873 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
5874 | f_sav = TREE_CHAIN (f_ovf); |
5875 | ||
872a65b5 | 5876 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5877 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5878 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5879 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5880 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
dfafc897 FS |
5881 | |
5882 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 5883 | words = current_function_args_info.words; |
dfafc897 FS |
5884 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
5885 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
5886 | ||
5887 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
5888 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
5889 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
5890 | words, n_gpr, n_fpr); | |
dfafc897 | 5891 | |
5496b36f JJ |
5892 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, |
5893 | build_int_cst (NULL_TREE, n_gpr)); | |
5894 | TREE_SIDE_EFFECTS (t) = 1; | |
5895 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
58c8adc1 | 5896 | |
5496b36f JJ |
5897 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, |
5898 | build_int_cst (NULL_TREE, n_fpr)); | |
5899 | TREE_SIDE_EFFECTS (t) = 1; | |
5900 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
dfafc897 FS |
5901 | |
5902 | /* Find the overflow area. */ | |
5903 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
5904 | if (words != 0) | |
5905 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
7d60be94 | 5906 | build_int_cst (NULL_TREE, words * UNITS_PER_WORD)); |
dfafc897 FS |
5907 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5908 | TREE_SIDE_EFFECTS (t) = 1; | |
5909 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5910 | ||
5911 | /* Find the register save area. */ | |
5912 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
5913 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
7d60be94 | 5914 | build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE)); |
dfafc897 FS |
5915 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); |
5916 | TREE_SIDE_EFFECTS (t) = 1; | |
5917 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5918 | } | |
5919 | ||
5920 | /* Implement va_arg. */ | |
5921 | ||
23a60a04 JM |
5922 | tree |
5923 | rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) | |
cd3ce9b4 | 5924 | { |
cd3ce9b4 JM |
5925 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
5926 | tree gpr, fpr, ovf, sav, reg, t, u; | |
08b0dc1b | 5927 | int size, rsize, n_reg, sav_ofs, sav_scale; |
cd3ce9b4 JM |
5928 | tree lab_false, lab_over, addr; |
5929 | int align; | |
5930 | tree ptrtype = build_pointer_type (type); | |
5931 | ||
08b0dc1b RH |
5932 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
5933 | { | |
5934 | t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); | |
872a65b5 | 5935 | return build_va_arg_indirect_ref (t); |
08b0dc1b RH |
5936 | } |
5937 | ||
cd3ce9b4 JM |
5938 | if (DEFAULT_ABI != ABI_V4) |
5939 | { | |
08b0dc1b | 5940 | if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) |
cd3ce9b4 JM |
5941 | { |
5942 | tree elem_type = TREE_TYPE (type); | |
5943 | enum machine_mode elem_mode = TYPE_MODE (elem_type); | |
5944 | int elem_size = GET_MODE_SIZE (elem_mode); | |
5945 | ||
5946 | if (elem_size < UNITS_PER_WORD) | |
5947 | { | |
23a60a04 | 5948 | tree real_part, imag_part; |
cd3ce9b4 JM |
5949 | tree post = NULL_TREE; |
5950 | ||
23a60a04 JM |
5951 | real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5952 | &post); | |
5953 | /* Copy the value into a temporary, lest the formal temporary | |
5954 | be reused out from under us. */ | |
5955 | real_part = get_initialized_tmp_var (real_part, pre_p, &post); | |
cd3ce9b4 JM |
5956 | append_to_statement_list (post, pre_p); |
5957 | ||
23a60a04 JM |
5958 | imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5959 | post_p); | |
cd3ce9b4 | 5960 | |
23a60a04 | 5961 | return build (COMPLEX_EXPR, type, real_part, imag_part); |
cd3ce9b4 JM |
5962 | } |
5963 | } | |
5964 | ||
23a60a04 | 5965 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 JM |
5966 | } |
5967 | ||
5968 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
5969 | f_fpr = TREE_CHAIN (f_gpr); | |
5970 | f_res = TREE_CHAIN (f_fpr); | |
5971 | f_ovf = TREE_CHAIN (f_res); | |
5972 | f_sav = TREE_CHAIN (f_ovf); | |
5973 | ||
872a65b5 | 5974 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5975 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5976 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5977 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5978 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
cd3ce9b4 JM |
5979 | |
5980 | size = int_size_in_bytes (type); | |
5981 | rsize = (size + 3) / 4; | |
5982 | align = 1; | |
5983 | ||
08b0dc1b RH |
5984 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
5985 | && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode)) | |
cd3ce9b4 JM |
5986 | { |
5987 | /* FP args go in FP registers, if present. */ | |
cd3ce9b4 JM |
5988 | reg = fpr; |
5989 | n_reg = 1; | |
5990 | sav_ofs = 8*4; | |
5991 | sav_scale = 8; | |
5992 | if (TYPE_MODE (type) == DFmode) | |
5993 | align = 8; | |
5994 | } | |
5995 | else | |
5996 | { | |
5997 | /* Otherwise into GP registers. */ | |
cd3ce9b4 JM |
5998 | reg = gpr; |
5999 | n_reg = rsize; | |
6000 | sav_ofs = 0; | |
6001 | sav_scale = 4; | |
6002 | if (n_reg == 2) | |
6003 | align = 8; | |
6004 | } | |
6005 | ||
6006 | /* Pull the value out of the saved registers.... */ | |
6007 | ||
6008 | lab_over = NULL; | |
6009 | addr = create_tmp_var (ptr_type_node, "addr"); | |
6010 | DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); | |
6011 | ||
6012 | /* AltiVec vectors never go in registers when -mabi=altivec. */ | |
6013 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
6014 | align = 16; | |
6015 | else | |
6016 | { | |
6017 | lab_false = create_artificial_label (); | |
6018 | lab_over = create_artificial_label (); | |
6019 | ||
6020 | /* Long long and SPE vectors are aligned in the registers. | |
6021 | As are any other 2 gpr item such as complex int due to a | |
6022 | historical mistake. */ | |
6023 | u = reg; | |
6024 | if (n_reg == 2) | |
6025 | { | |
6026 | u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
95674810 | 6027 | size_int (n_reg - 1)); |
cd3ce9b4 JM |
6028 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u); |
6029 | } | |
6030 | ||
95674810 | 6031 | t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); |
cd3ce9b4 JM |
6032 | t = build2 (GE_EXPR, boolean_type_node, u, t); |
6033 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
6034 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
6035 | gimplify_and_add (t, pre_p); | |
6036 | ||
6037 | t = sav; | |
6038 | if (sav_ofs) | |
95674810 | 6039 | t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs)); |
cd3ce9b4 | 6040 | |
95674810 | 6041 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg)); |
cd3ce9b4 | 6042 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
95674810 | 6043 | u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale)); |
cd3ce9b4 JM |
6044 | t = build2 (PLUS_EXPR, ptr_type_node, t, u); |
6045 | ||
6046 | t = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
6047 | gimplify_and_add (t, pre_p); | |
6048 | ||
6049 | t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
6050 | gimplify_and_add (t, pre_p); | |
6051 | ||
6052 | t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
6053 | append_to_statement_list (t, pre_p); | |
6054 | ||
6055 | if (n_reg > 2) | |
6056 | { | |
6057 | /* Ensure that we don't find any more args in regs. | |
6058 | Alignment has taken care of the n_reg == 2 case. */ | |
95674810 | 6059 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8)); |
cd3ce9b4 JM |
6060 | gimplify_and_add (t, pre_p); |
6061 | } | |
6062 | } | |
6063 | ||
6064 | /* ... otherwise out of the overflow area. */ | |
6065 | ||
6066 | /* Care for on-stack alignment if needed. */ | |
6067 | t = ovf; | |
6068 | if (align != 1) | |
6069 | { | |
95674810 | 6070 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1)); |
4a90aeeb | 6071 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
7d60be94 | 6072 | build_int_cst (NULL_TREE, -align)); |
cd3ce9b4 JM |
6073 | } |
6074 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
6075 | ||
6076 | u = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
6077 | gimplify_and_add (u, pre_p); | |
6078 | ||
95674810 | 6079 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); |
cd3ce9b4 JM |
6080 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
6081 | gimplify_and_add (t, pre_p); | |
6082 | ||
6083 | if (lab_over) | |
6084 | { | |
6085 | t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
6086 | append_to_statement_list (t, pre_p); | |
6087 | } | |
6088 | ||
08b0dc1b | 6089 | addr = fold_convert (ptrtype, addr); |
872a65b5 | 6090 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
6091 | } |
6092 | ||
0ac081f6 AH |
6093 | /* Builtins. */ |
6094 | ||
6e34d3a3 JM |
6095 | #define def_builtin(MASK, NAME, TYPE, CODE) \ |
6096 | do { \ | |
6097 | if ((MASK) & target_flags) \ | |
6098 | lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ | |
6099 | NULL, NULL_TREE); \ | |
0ac081f6 AH |
6100 | } while (0) |
6101 | ||
24408032 AH |
6102 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
6103 | ||
2212663f | 6104 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
6105 | { |
6106 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
6107 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
6108 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
6109 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
6110 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
6111 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
6112 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
6113 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
6114 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
6115 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
f676971a | 6116 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, |
24408032 AH |
6117 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, |
6118 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
6119 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
6120 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
6121 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
6122 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
6123 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
6124 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
6125 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
6126 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
6127 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
6128 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
6129 | }; | |
2212663f | 6130 | |
95385cbb AH |
6131 | /* DST operations: void foo (void *, const int, const char). */ |
6132 | ||
6133 | static const struct builtin_description bdesc_dst[] = | |
6134 | { | |
6135 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
6136 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
6137 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
6138 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
6139 | }; | |
6140 | ||
2212663f | 6141 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 6142 | |
a3170dc6 | 6143 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 6144 | { |
f18c054f DB |
6145 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
6146 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
6147 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
6148 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
6149 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
6150 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
6151 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
6152 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
6153 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
6154 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
6155 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 6156 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
6157 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
6158 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
6159 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
6160 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
6161 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
6162 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
6163 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
6164 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
6165 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
6166 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
6167 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
6168 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
6169 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
6170 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
6171 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
6172 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
6173 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
6174 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
6175 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
6176 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
6177 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
6178 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
6179 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
6180 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
6181 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
6182 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
6183 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
6184 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
6185 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
6186 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
6187 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
6188 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
6189 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
6190 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
6191 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
6192 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
6193 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
6194 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
6195 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
6196 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
6197 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
6198 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
6199 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
6200 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
6201 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
6202 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
6203 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
6204 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
6205 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
6206 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
6207 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
6208 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
6209 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 6210 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
6211 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
6212 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
6213 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
6214 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
6215 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
6216 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
6217 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
6218 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
6219 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
6220 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
6221 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
6222 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
6223 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
6224 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
6225 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
6226 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
6227 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
6228 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
6229 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
6230 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
6231 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
6232 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 6233 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
6234 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
6235 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
6236 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
6237 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
6238 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
6239 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
6240 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
6241 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
6242 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
6243 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
6244 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
6245 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
6246 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
6247 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
6248 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
6249 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
6250 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
6251 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
6252 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
6253 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
6254 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
6255 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
6256 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 6257 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 AH |
6258 | |
6259 | /* Place holder, leave as first spe builtin. */ | |
6260 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
6261 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
6262 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
6263 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
6264 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
6265 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
6266 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
6267 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
6268 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
6269 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
6270 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
6271 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
6272 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
6273 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
6274 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
6275 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
6276 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
6277 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
6278 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
6279 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
6280 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
6281 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
6282 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
6283 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
6284 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
6285 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
6286 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
6287 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
6288 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
6289 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
6290 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
6291 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
6292 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
6293 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
6294 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
6295 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
6296 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
6297 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
6298 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
6299 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
6300 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
6301 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
6302 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
6303 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
6304 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
6305 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
6306 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
6307 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
6308 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
6309 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
6310 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
6311 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
6312 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
6313 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
6314 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
6315 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
6316 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
6317 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
6318 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
6319 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
6320 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
6321 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
6322 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
6323 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
6324 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
6325 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
6326 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
6327 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
6328 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
6329 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
6330 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
6331 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
6332 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
6333 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
6334 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
6335 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
6336 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
6337 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
6338 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
6339 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
6340 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
6341 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
6342 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
6343 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
6344 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
6345 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
6346 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
6347 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
6348 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
6349 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
6350 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
6351 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
6352 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
6353 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
6354 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
6355 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
6356 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
6357 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
6358 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
6359 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
6360 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
6361 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
6362 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
6363 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
6364 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
6365 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
6366 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
6367 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
6368 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
6369 | ||
6370 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
6371 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
6372 | ||
6373 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
6374 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
6375 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
6376 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
6377 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
6378 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
6379 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
6380 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
6381 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
6382 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
6383 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
6384 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
6385 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
6386 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
6387 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
6388 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
6389 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
6390 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
6391 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
6392 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
6393 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
6394 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
6395 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
6396 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
6397 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
6398 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
6399 | ||
6400 | /* Place-holder. Leave as last binary SPE builtin. */ | |
17edbda5 | 6401 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, |
ae4b4a02 AH |
6402 | }; |
6403 | ||
6404 | /* AltiVec predicates. */ | |
6405 | ||
6406 | struct builtin_description_predicates | |
6407 | { | |
6408 | const unsigned int mask; | |
6409 | const enum insn_code icode; | |
6410 | const char *opcode; | |
6411 | const char *const name; | |
6412 | const enum rs6000_builtins code; | |
6413 | }; | |
6414 | ||
6415 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
6416 | { | |
6417 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
6418 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
6419 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
6420 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
6421 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
6422 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
6423 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
6424 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
6425 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
6426 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
6427 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
6428 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
6429 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 6430 | }; |
24408032 | 6431 | |
a3170dc6 AH |
6432 | /* SPE predicates. */ |
6433 | static struct builtin_description bdesc_spe_predicates[] = | |
6434 | { | |
6435 | /* Place-holder. Leave as first. */ | |
6436 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
6437 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
6438 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
6439 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
6440 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
6441 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
6442 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
6443 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
6444 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
6445 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
6446 | /* Place-holder. Leave as last. */ | |
6447 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
6448 | }; | |
6449 | ||
6450 | /* SPE evsel predicates. */ | |
6451 | static struct builtin_description bdesc_spe_evsel[] = | |
6452 | { | |
6453 | /* Place-holder. Leave as first. */ | |
6454 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
6455 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
6456 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
6457 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
6458 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
6459 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
6460 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
6461 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
6462 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
6463 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
6464 | /* Place-holder. Leave as last. */ | |
6465 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
6466 | }; | |
6467 | ||
b6d08ca1 | 6468 | /* ABS* operations. */ |
100c4561 AH |
6469 | |
6470 | static const struct builtin_description bdesc_abs[] = | |
6471 | { | |
6472 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
6473 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
6474 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
6475 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
6476 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
6477 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
6478 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
6479 | }; | |
6480 | ||
617e0e1d DB |
6481 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
6482 | foo (VECa). */ | |
24408032 | 6483 | |
a3170dc6 | 6484 | static struct builtin_description bdesc_1arg[] = |
2212663f | 6485 | { |
617e0e1d DB |
6486 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
6487 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
6488 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
6489 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
6490 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
6491 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
6492 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
6493 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
6494 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
6495 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
6496 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
6497 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
6498 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
6499 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
6500 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
6501 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
6502 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 AH |
6503 | |
6504 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and | |
6505 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
6506 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
6507 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
6508 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
6509 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
6510 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
6511 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
6512 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
6513 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
6514 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
6515 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
6516 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
6517 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
6518 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
6519 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
6520 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
6521 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
6522 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
6523 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
6524 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
6525 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
6526 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
6527 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
6528 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
6a599451 | 6529 | { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, |
a3170dc6 AH |
6530 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, |
6531 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
6532 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
6533 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
6534 | |
6535 | /* Place-holder. Leave as last unary SPE builtin. */ | |
6536 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, | |
2212663f DB |
6537 | }; |
6538 | ||
6539 | static rtx | |
a2369ed3 | 6540 | rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6541 | { |
6542 | rtx pat; | |
6543 | tree arg0 = TREE_VALUE (arglist); | |
6544 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6545 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6546 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6547 | ||
0559cc77 DE |
6548 | if (icode == CODE_FOR_nothing) |
6549 | /* Builtin not supported on this processor. */ | |
6550 | return 0; | |
6551 | ||
20e26713 AH |
6552 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6553 | if (arg0 == error_mark_node) | |
9a171fcd | 6554 | return const0_rtx; |
20e26713 | 6555 | |
0559cc77 DE |
6556 | if (icode == CODE_FOR_altivec_vspltisb |
6557 | || icode == CODE_FOR_altivec_vspltish | |
6558 | || icode == CODE_FOR_altivec_vspltisw | |
6559 | || icode == CODE_FOR_spe_evsplatfi | |
6560 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
6561 | { |
6562 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 AH |
6563 | if (GET_CODE (op0) != CONST_INT |
6564 | || INTVAL (op0) > 0x1f | |
6565 | || INTVAL (op0) < -0x1f) | |
6566 | { | |
6567 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 6568 | return const0_rtx; |
b44140e7 | 6569 | } |
b44140e7 AH |
6570 | } |
6571 | ||
c62f2db5 | 6572 | if (target == 0 |
2212663f DB |
6573 | || GET_MODE (target) != tmode |
6574 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6575 | target = gen_reg_rtx (tmode); | |
6576 | ||
6577 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6578 | op0 = copy_to_mode_reg (mode0, op0); | |
6579 | ||
6580 | pat = GEN_FCN (icode) (target, op0); | |
6581 | if (! pat) | |
6582 | return 0; | |
6583 | emit_insn (pat); | |
0ac081f6 | 6584 | |
2212663f DB |
6585 | return target; |
6586 | } | |
ae4b4a02 | 6587 | |
100c4561 | 6588 | static rtx |
a2369ed3 | 6589 | altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) |
100c4561 AH |
6590 | { |
6591 | rtx pat, scratch1, scratch2; | |
6592 | tree arg0 = TREE_VALUE (arglist); | |
6593 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6594 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6595 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6596 | ||
6597 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6598 | if (arg0 == error_mark_node) | |
9a171fcd | 6599 | return const0_rtx; |
100c4561 AH |
6600 | |
6601 | if (target == 0 | |
6602 | || GET_MODE (target) != tmode | |
6603 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6604 | target = gen_reg_rtx (tmode); | |
6605 | ||
6606 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6607 | op0 = copy_to_mode_reg (mode0, op0); | |
6608 | ||
6609 | scratch1 = gen_reg_rtx (mode0); | |
6610 | scratch2 = gen_reg_rtx (mode0); | |
6611 | ||
6612 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
6613 | if (! pat) | |
6614 | return 0; | |
6615 | emit_insn (pat); | |
6616 | ||
6617 | return target; | |
6618 | } | |
6619 | ||
0ac081f6 | 6620 | static rtx |
a2369ed3 | 6621 | rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
0ac081f6 AH |
6622 | { |
6623 | rtx pat; | |
6624 | tree arg0 = TREE_VALUE (arglist); | |
6625 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6626 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6627 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6628 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6629 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6630 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6631 | ||
0559cc77 DE |
6632 | if (icode == CODE_FOR_nothing) |
6633 | /* Builtin not supported on this processor. */ | |
6634 | return 0; | |
6635 | ||
20e26713 AH |
6636 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6637 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6638 | return const0_rtx; |
20e26713 | 6639 | |
0559cc77 DE |
6640 | if (icode == CODE_FOR_altivec_vcfux |
6641 | || icode == CODE_FOR_altivec_vcfsx | |
6642 | || icode == CODE_FOR_altivec_vctsxs | |
6643 | || icode == CODE_FOR_altivec_vctuxs | |
6644 | || icode == CODE_FOR_altivec_vspltb | |
6645 | || icode == CODE_FOR_altivec_vsplth | |
6646 | || icode == CODE_FOR_altivec_vspltw | |
6647 | || icode == CODE_FOR_spe_evaddiw | |
6648 | || icode == CODE_FOR_spe_evldd | |
6649 | || icode == CODE_FOR_spe_evldh | |
6650 | || icode == CODE_FOR_spe_evldw | |
6651 | || icode == CODE_FOR_spe_evlhhesplat | |
6652 | || icode == CODE_FOR_spe_evlhhossplat | |
6653 | || icode == CODE_FOR_spe_evlhhousplat | |
6654 | || icode == CODE_FOR_spe_evlwhe | |
6655 | || icode == CODE_FOR_spe_evlwhos | |
6656 | || icode == CODE_FOR_spe_evlwhou | |
6657 | || icode == CODE_FOR_spe_evlwhsplat | |
6658 | || icode == CODE_FOR_spe_evlwwsplat | |
6659 | || icode == CODE_FOR_spe_evrlwi | |
6660 | || icode == CODE_FOR_spe_evslwi | |
6661 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 6662 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 6663 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
6664 | { |
6665 | /* Only allow 5-bit unsigned literals. */ | |
8bb418a3 | 6666 | STRIP_NOPS (arg1); |
b44140e7 AH |
6667 | if (TREE_CODE (arg1) != INTEGER_CST |
6668 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6669 | { | |
6670 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 6671 | return const0_rtx; |
b44140e7 | 6672 | } |
b44140e7 AH |
6673 | } |
6674 | ||
c62f2db5 | 6675 | if (target == 0 |
0ac081f6 AH |
6676 | || GET_MODE (target) != tmode |
6677 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6678 | target = gen_reg_rtx (tmode); | |
6679 | ||
6680 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6681 | op0 = copy_to_mode_reg (mode0, op0); | |
6682 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6683 | op1 = copy_to_mode_reg (mode1, op1); | |
6684 | ||
6685 | pat = GEN_FCN (icode) (target, op0, op1); | |
6686 | if (! pat) | |
6687 | return 0; | |
6688 | emit_insn (pat); | |
6689 | ||
6690 | return target; | |
6691 | } | |
6525c0e7 | 6692 | |
ae4b4a02 | 6693 | static rtx |
f676971a | 6694 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
a2369ed3 | 6695 | tree arglist, rtx target) |
ae4b4a02 AH |
6696 | { |
6697 | rtx pat, scratch; | |
6698 | tree cr6_form = TREE_VALUE (arglist); | |
6699 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6700 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6701 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6702 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6703 | enum machine_mode tmode = SImode; | |
6704 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6705 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6706 | int cr6_form_int; | |
6707 | ||
6708 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
6709 | { | |
6710 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 6711 | return const0_rtx; |
ae4b4a02 AH |
6712 | } |
6713 | else | |
6714 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
6715 | ||
6716 | if (mode0 != mode1) | |
6717 | abort (); | |
6718 | ||
6719 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6720 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6721 | return const0_rtx; |
ae4b4a02 AH |
6722 | |
6723 | if (target == 0 | |
6724 | || GET_MODE (target) != tmode | |
6725 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6726 | target = gen_reg_rtx (tmode); | |
6727 | ||
6728 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6729 | op0 = copy_to_mode_reg (mode0, op0); | |
6730 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6731 | op1 = copy_to_mode_reg (mode1, op1); | |
6732 | ||
6733 | scratch = gen_reg_rtx (mode0); | |
6734 | ||
6735 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 6736 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
6737 | if (! pat) |
6738 | return 0; | |
6739 | emit_insn (pat); | |
6740 | ||
6741 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
6742 | different operations, but the bits in CR6 will be different | |
6743 | depending on what information we want. So we have to play tricks | |
6744 | with CR6 to get the right bits out. | |
6745 | ||
6746 | If you think this is disgusting, look at the specs for the | |
6747 | AltiVec predicates. */ | |
6748 | ||
c4ad648e AM |
6749 | switch (cr6_form_int) |
6750 | { | |
6751 | case 0: | |
6752 | emit_insn (gen_cr6_test_for_zero (target)); | |
6753 | break; | |
6754 | case 1: | |
6755 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
6756 | break; | |
6757 | case 2: | |
6758 | emit_insn (gen_cr6_test_for_lt (target)); | |
6759 | break; | |
6760 | case 3: | |
6761 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
6762 | break; | |
6763 | default: | |
6764 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
6765 | break; | |
6766 | } | |
ae4b4a02 AH |
6767 | |
6768 | return target; | |
6769 | } | |
6770 | ||
b4a62fa0 | 6771 | static rtx |
38f391a5 | 6772 | altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) |
b4a62fa0 SB |
6773 | { |
6774 | rtx pat, addr; | |
6775 | tree arg0 = TREE_VALUE (arglist); | |
6776 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6777 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6778 | enum machine_mode mode0 = Pmode; | |
6779 | enum machine_mode mode1 = Pmode; | |
6780 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6781 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6782 | ||
6783 | if (icode == CODE_FOR_nothing) | |
6784 | /* Builtin not supported on this processor. */ | |
6785 | return 0; | |
6786 | ||
6787 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6788 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6789 | return const0_rtx; | |
6790 | ||
6791 | if (target == 0 | |
6792 | || GET_MODE (target) != tmode | |
6793 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6794 | target = gen_reg_rtx (tmode); | |
6795 | ||
f676971a | 6796 | op1 = copy_to_mode_reg (mode1, op1); |
b4a62fa0 SB |
6797 | |
6798 | if (op0 == const0_rtx) | |
6799 | { | |
6800 | addr = gen_rtx_MEM (tmode, op1); | |
6801 | } | |
6802 | else | |
6803 | { | |
6804 | op0 = copy_to_mode_reg (mode0, op0); | |
6805 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
6806 | } | |
6807 | ||
6808 | pat = GEN_FCN (icode) (target, addr); | |
6809 | ||
6810 | if (! pat) | |
6811 | return 0; | |
6812 | emit_insn (pat); | |
6813 | ||
6814 | return target; | |
6815 | } | |
6816 | ||
61bea3b0 AH |
6817 | static rtx |
6818 | spe_expand_stv_builtin (enum insn_code icode, tree arglist) | |
6819 | { | |
6820 | tree arg0 = TREE_VALUE (arglist); | |
6821 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6822 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6823 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6824 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6825 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6826 | rtx pat; | |
6827 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
6828 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
6829 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
6830 | ||
6831 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6832 | if (arg0 == error_mark_node | |
6833 | || arg1 == error_mark_node | |
6834 | || arg2 == error_mark_node) | |
6835 | return const0_rtx; | |
6836 | ||
6837 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
6838 | op0 = copy_to_mode_reg (mode2, op0); | |
6839 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
6840 | op1 = copy_to_mode_reg (mode0, op1); | |
6841 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6842 | op2 = copy_to_mode_reg (mode1, op2); | |
6843 | ||
6844 | pat = GEN_FCN (icode) (op1, op2, op0); | |
6845 | if (pat) | |
6846 | emit_insn (pat); | |
6847 | return NULL_RTX; | |
6848 | } | |
6849 | ||
6525c0e7 | 6850 | static rtx |
a2369ed3 | 6851 | altivec_expand_stv_builtin (enum insn_code icode, tree arglist) |
6525c0e7 AH |
6852 | { |
6853 | tree arg0 = TREE_VALUE (arglist); | |
6854 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6855 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6856 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6857 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6858 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
b4a62fa0 SB |
6859 | rtx pat, addr; |
6860 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6861 | enum machine_mode mode1 = Pmode; | |
6862 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
6863 | |
6864 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6865 | if (arg0 == error_mark_node | |
6866 | || arg1 == error_mark_node | |
6867 | || arg2 == error_mark_node) | |
9a171fcd | 6868 | return const0_rtx; |
6525c0e7 | 6869 | |
b4a62fa0 SB |
6870 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
6871 | op0 = copy_to_mode_reg (tmode, op0); | |
6872 | ||
f676971a | 6873 | op2 = copy_to_mode_reg (mode2, op2); |
b4a62fa0 SB |
6874 | |
6875 | if (op1 == const0_rtx) | |
6876 | { | |
6877 | addr = gen_rtx_MEM (tmode, op2); | |
6878 | } | |
6879 | else | |
6880 | { | |
6881 | op1 = copy_to_mode_reg (mode1, op1); | |
6882 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
6883 | } | |
6525c0e7 | 6884 | |
b4a62fa0 | 6885 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
6886 | if (pat) |
6887 | emit_insn (pat); | |
6888 | return NULL_RTX; | |
6889 | } | |
6890 | ||
2212663f | 6891 | static rtx |
a2369ed3 | 6892 | rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6893 | { |
6894 | rtx pat; | |
6895 | tree arg0 = TREE_VALUE (arglist); | |
6896 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6897 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6898 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6899 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6900 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6901 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6902 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6903 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6904 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 6905 | |
774b5662 DE |
6906 | if (icode == CODE_FOR_nothing) |
6907 | /* Builtin not supported on this processor. */ | |
6908 | return 0; | |
6909 | ||
20e26713 AH |
6910 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6911 | if (arg0 == error_mark_node | |
6912 | || arg1 == error_mark_node | |
6913 | || arg2 == error_mark_node) | |
9a171fcd | 6914 | return const0_rtx; |
20e26713 | 6915 | |
774b5662 DE |
6916 | if (icode == CODE_FOR_altivec_vsldoi_4sf |
6917 | || icode == CODE_FOR_altivec_vsldoi_4si | |
6918 | || icode == CODE_FOR_altivec_vsldoi_8hi | |
6919 | || icode == CODE_FOR_altivec_vsldoi_16qi) | |
b44140e7 AH |
6920 | { |
6921 | /* Only allow 4-bit unsigned literals. */ | |
8bb418a3 | 6922 | STRIP_NOPS (arg2); |
b44140e7 AH |
6923 | if (TREE_CODE (arg2) != INTEGER_CST |
6924 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
6925 | { | |
6926 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 6927 | return const0_rtx; |
b44140e7 | 6928 | } |
b44140e7 AH |
6929 | } |
6930 | ||
c62f2db5 | 6931 | if (target == 0 |
2212663f DB |
6932 | || GET_MODE (target) != tmode |
6933 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6934 | target = gen_reg_rtx (tmode); | |
6935 | ||
6936 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6937 | op0 = copy_to_mode_reg (mode0, op0); | |
6938 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6939 | op1 = copy_to_mode_reg (mode1, op1); | |
6940 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
6941 | op2 = copy_to_mode_reg (mode2, op2); | |
6942 | ||
6943 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
6944 | if (! pat) | |
6945 | return 0; | |
6946 | emit_insn (pat); | |
6947 | ||
6948 | return target; | |
6949 | } | |
92898235 | 6950 | |
3a9b8c7e | 6951 | /* Expand the lvx builtins. */ |
0ac081f6 | 6952 | static rtx |
a2369ed3 | 6953 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 6954 | { |
0ac081f6 AH |
6955 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6956 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 6957 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
6958 | tree arg0; |
6959 | enum machine_mode tmode, mode0; | |
7c3abc73 | 6960 | rtx pat, op0; |
3a9b8c7e | 6961 | enum insn_code icode; |
92898235 | 6962 | |
0ac081f6 AH |
6963 | switch (fcode) |
6964 | { | |
f18c054f | 6965 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
81466555 | 6966 | icode = CODE_FOR_altivec_lvx_v16qi; |
3a9b8c7e | 6967 | break; |
f18c054f | 6968 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
81466555 | 6969 | icode = CODE_FOR_altivec_lvx_v8hi; |
3a9b8c7e AH |
6970 | break; |
6971 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
81466555 | 6972 | icode = CODE_FOR_altivec_lvx_v4si; |
3a9b8c7e AH |
6973 | break; |
6974 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
81466555 | 6975 | icode = CODE_FOR_altivec_lvx_v4sf; |
3a9b8c7e AH |
6976 | break; |
6977 | default: | |
6978 | *expandedp = false; | |
6979 | return NULL_RTX; | |
6980 | } | |
0ac081f6 | 6981 | |
3a9b8c7e | 6982 | *expandedp = true; |
f18c054f | 6983 | |
3a9b8c7e AH |
6984 | arg0 = TREE_VALUE (arglist); |
6985 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6986 | tmode = insn_data[icode].operand[0].mode; | |
6987 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 6988 | |
3a9b8c7e AH |
6989 | if (target == 0 |
6990 | || GET_MODE (target) != tmode | |
6991 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6992 | target = gen_reg_rtx (tmode); | |
24408032 | 6993 | |
3a9b8c7e AH |
6994 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
6995 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 6996 | |
3a9b8c7e AH |
6997 | pat = GEN_FCN (icode) (target, op0); |
6998 | if (! pat) | |
6999 | return 0; | |
7000 | emit_insn (pat); | |
7001 | return target; | |
7002 | } | |
f18c054f | 7003 | |
3a9b8c7e AH |
7004 | /* Expand the stvx builtins. */ |
7005 | static rtx | |
f676971a | 7006 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 7007 | bool *expandedp) |
3a9b8c7e AH |
7008 | { |
7009 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
7010 | tree arglist = TREE_OPERAND (exp, 1); | |
7011 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7012 | tree arg0, arg1; | |
7013 | enum machine_mode mode0, mode1; | |
7c3abc73 | 7014 | rtx pat, op0, op1; |
3a9b8c7e | 7015 | enum insn_code icode; |
f18c054f | 7016 | |
3a9b8c7e AH |
7017 | switch (fcode) |
7018 | { | |
7019 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
81466555 | 7020 | icode = CODE_FOR_altivec_stvx_v16qi; |
3a9b8c7e AH |
7021 | break; |
7022 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
81466555 | 7023 | icode = CODE_FOR_altivec_stvx_v8hi; |
3a9b8c7e AH |
7024 | break; |
7025 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
81466555 | 7026 | icode = CODE_FOR_altivec_stvx_v4si; |
3a9b8c7e AH |
7027 | break; |
7028 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
81466555 | 7029 | icode = CODE_FOR_altivec_stvx_v4sf; |
3a9b8c7e AH |
7030 | break; |
7031 | default: | |
7032 | *expandedp = false; | |
7033 | return NULL_RTX; | |
7034 | } | |
24408032 | 7035 | |
3a9b8c7e AH |
7036 | arg0 = TREE_VALUE (arglist); |
7037 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7038 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7039 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7040 | mode0 = insn_data[icode].operand[0].mode; | |
7041 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 7042 | |
3a9b8c7e AH |
7043 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
7044 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
7045 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
7046 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 7047 | |
3a9b8c7e AH |
7048 | pat = GEN_FCN (icode) (op0, op1); |
7049 | if (pat) | |
7050 | emit_insn (pat); | |
f18c054f | 7051 | |
3a9b8c7e AH |
7052 | *expandedp = true; |
7053 | return NULL_RTX; | |
7054 | } | |
f18c054f | 7055 | |
3a9b8c7e AH |
7056 | /* Expand the dst builtins. */ |
7057 | static rtx | |
f676971a | 7058 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 7059 | bool *expandedp) |
3a9b8c7e AH |
7060 | { |
7061 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
7062 | tree arglist = TREE_OPERAND (exp, 1); | |
7063 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7064 | tree arg0, arg1, arg2; | |
7065 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 7066 | rtx pat, op0, op1, op2; |
3a9b8c7e | 7067 | struct builtin_description *d; |
a3170dc6 | 7068 | size_t i; |
f18c054f | 7069 | |
3a9b8c7e | 7070 | *expandedp = false; |
f18c054f | 7071 | |
3a9b8c7e AH |
7072 | /* Handle DST variants. */ |
7073 | d = (struct builtin_description *) bdesc_dst; | |
7074 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
7075 | if (d->code == fcode) | |
7076 | { | |
7077 | arg0 = TREE_VALUE (arglist); | |
7078 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7079 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7080 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7081 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7082 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
7083 | mode0 = insn_data[d->icode].operand[0].mode; | |
7084 | mode1 = insn_data[d->icode].operand[1].mode; | |
7085 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 7086 | |
3a9b8c7e AH |
7087 | /* Invalid arguments, bail out before generating bad rtl. */ |
7088 | if (arg0 == error_mark_node | |
7089 | || arg1 == error_mark_node | |
7090 | || arg2 == error_mark_node) | |
7091 | return const0_rtx; | |
f18c054f | 7092 | |
86e7df90 | 7093 | *expandedp = true; |
8bb418a3 | 7094 | STRIP_NOPS (arg2); |
3a9b8c7e AH |
7095 | if (TREE_CODE (arg2) != INTEGER_CST |
7096 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
7097 | { | |
9e637a26 | 7098 | error ("argument to %qs must be a 2-bit unsigned literal", d->name); |
3a9b8c7e AH |
7099 | return const0_rtx; |
7100 | } | |
f18c054f | 7101 | |
3a9b8c7e | 7102 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
b4a62fa0 | 7103 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); |
3a9b8c7e AH |
7104 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
7105 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 7106 | |
3a9b8c7e AH |
7107 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
7108 | if (pat != 0) | |
7109 | emit_insn (pat); | |
f18c054f | 7110 | |
3a9b8c7e AH |
7111 | return NULL_RTX; |
7112 | } | |
f18c054f | 7113 | |
3a9b8c7e AH |
7114 | return NULL_RTX; |
7115 | } | |
24408032 | 7116 | |
3a9b8c7e AH |
7117 | /* Expand the builtin in EXP and store the result in TARGET. Store |
7118 | true in *EXPANDEDP if we found a builtin to expand. */ | |
7119 | static rtx | |
a2369ed3 | 7120 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e AH |
7121 | { |
7122 | struct builtin_description *d; | |
7123 | struct builtin_description_predicates *dp; | |
7124 | size_t i; | |
7125 | enum insn_code icode; | |
7126 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
7127 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
7128 | tree arg0; |
7129 | rtx op0, pat; | |
7130 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 7131 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 7132 | |
3a9b8c7e AH |
7133 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
7134 | if (*expandedp) | |
7135 | return target; | |
0ac081f6 | 7136 | |
3a9b8c7e AH |
7137 | target = altivec_expand_st_builtin (exp, target, expandedp); |
7138 | if (*expandedp) | |
7139 | return target; | |
7140 | ||
7141 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
7142 | if (*expandedp) | |
7143 | return target; | |
7144 | ||
7145 | *expandedp = true; | |
95385cbb | 7146 | |
3a9b8c7e AH |
7147 | switch (fcode) |
7148 | { | |
6525c0e7 AH |
7149 | case ALTIVEC_BUILTIN_STVX: |
7150 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
7151 | case ALTIVEC_BUILTIN_STVEBX: | |
7152 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
7153 | case ALTIVEC_BUILTIN_STVEHX: | |
7154 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
7155 | case ALTIVEC_BUILTIN_STVEWX: | |
7156 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
7157 | case ALTIVEC_BUILTIN_STVXL: | |
7158 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 7159 | |
95385cbb AH |
7160 | case ALTIVEC_BUILTIN_MFVSCR: |
7161 | icode = CODE_FOR_altivec_mfvscr; | |
7162 | tmode = insn_data[icode].operand[0].mode; | |
7163 | ||
7164 | if (target == 0 | |
7165 | || GET_MODE (target) != tmode | |
7166 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7167 | target = gen_reg_rtx (tmode); | |
f676971a | 7168 | |
95385cbb | 7169 | pat = GEN_FCN (icode) (target); |
0ac081f6 AH |
7170 | if (! pat) |
7171 | return 0; | |
7172 | emit_insn (pat); | |
95385cbb AH |
7173 | return target; |
7174 | ||
7175 | case ALTIVEC_BUILTIN_MTVSCR: | |
7176 | icode = CODE_FOR_altivec_mtvscr; | |
7177 | arg0 = TREE_VALUE (arglist); | |
7178 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7179 | mode0 = insn_data[icode].operand[0].mode; | |
7180 | ||
7181 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
7182 | if (arg0 == error_mark_node) | |
9a171fcd | 7183 | return const0_rtx; |
95385cbb AH |
7184 | |
7185 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
7186 | op0 = copy_to_mode_reg (mode0, op0); | |
7187 | ||
7188 | pat = GEN_FCN (icode) (op0); | |
7189 | if (pat) | |
7190 | emit_insn (pat); | |
7191 | return NULL_RTX; | |
3a9b8c7e | 7192 | |
95385cbb AH |
7193 | case ALTIVEC_BUILTIN_DSSALL: |
7194 | emit_insn (gen_altivec_dssall ()); | |
7195 | return NULL_RTX; | |
7196 | ||
7197 | case ALTIVEC_BUILTIN_DSS: | |
7198 | icode = CODE_FOR_altivec_dss; | |
7199 | arg0 = TREE_VALUE (arglist); | |
8bb418a3 | 7200 | STRIP_NOPS (arg0); |
95385cbb AH |
7201 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
7202 | mode0 = insn_data[icode].operand[0].mode; | |
7203 | ||
7204 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
7205 | if (arg0 == error_mark_node) | |
9a171fcd | 7206 | return const0_rtx; |
95385cbb | 7207 | |
b44140e7 AH |
7208 | if (TREE_CODE (arg0) != INTEGER_CST |
7209 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
7210 | { | |
7211 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 7212 | return const0_rtx; |
b44140e7 AH |
7213 | } |
7214 | ||
95385cbb AH |
7215 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
7216 | op0 = copy_to_mode_reg (mode0, op0); | |
7217 | ||
7218 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 | 7219 | return NULL_RTX; |
f676971a | 7220 | |
8bb418a3 ZL |
7221 | case ALTIVEC_BUILTIN_COMPILETIME_ERROR: |
7222 | arg0 = TREE_VALUE (arglist); | |
97dc04b3 | 7223 | while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR |
c4ad648e | 7224 | || TREE_CODE (arg0) == ARRAY_REF) |
8bb418a3 | 7225 | arg0 = TREE_OPERAND (arg0, 0); |
9e637a26 | 7226 | error ("invalid parameter combination for %qs AltiVec intrinsic", |
8bb418a3 ZL |
7227 | TREE_STRING_POINTER (arg0)); |
7228 | ||
7229 | return const0_rtx; | |
0ac081f6 | 7230 | } |
24408032 | 7231 | |
100c4561 AH |
7232 | /* Expand abs* operations. */ |
7233 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 7234 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
7235 | if (d->code == fcode) |
7236 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
7237 | ||
ae4b4a02 AH |
7238 | /* Expand the AltiVec predicates. */ |
7239 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 7240 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 | 7241 | if (dp->code == fcode) |
c4ad648e AM |
7242 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, |
7243 | arglist, target); | |
ae4b4a02 | 7244 | |
6525c0e7 AH |
7245 | /* LV* are funky. We initialized them differently. */ |
7246 | switch (fcode) | |
7247 | { | |
7248 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 7249 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
c4ad648e | 7250 | arglist, target); |
6525c0e7 | 7251 | case ALTIVEC_BUILTIN_LVSR: |
b4a62fa0 | 7252 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
c4ad648e | 7253 | arglist, target); |
6525c0e7 | 7254 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 7255 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
c4ad648e | 7256 | arglist, target); |
6525c0e7 | 7257 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 7258 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
c4ad648e | 7259 | arglist, target); |
6525c0e7 | 7260 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 7261 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
c4ad648e | 7262 | arglist, target); |
6525c0e7 | 7263 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 7264 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
c4ad648e | 7265 | arglist, target); |
6525c0e7 | 7266 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 7267 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
c4ad648e | 7268 | arglist, target); |
6525c0e7 AH |
7269 | default: |
7270 | break; | |
7271 | /* Fall through. */ | |
7272 | } | |
95385cbb | 7273 | |
92898235 | 7274 | *expandedp = false; |
0ac081f6 AH |
7275 | return NULL_RTX; |
7276 | } | |
7277 | ||
a3170dc6 AH |
7278 | /* Binops that need to be initialized manually, but can be expanded |
7279 | automagically by rs6000_expand_binop_builtin. */ | |
7280 | static struct builtin_description bdesc_2arg_spe[] = | |
7281 | { | |
7282 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
7283 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
7284 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
7285 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
7286 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
7287 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
7288 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
7289 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
7290 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
7291 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
7292 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
7293 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
7294 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
7295 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
7296 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
7297 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
7298 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
7299 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
7300 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
7301 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
7302 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
7303 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
7304 | }; | |
7305 | ||
7306 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
7307 | true in *EXPANDEDP if we found a builtin to expand. | |
7308 | ||
7309 | This expands the SPE builtins that are not simple unary and binary | |
7310 | operations. */ | |
7311 | static rtx | |
a2369ed3 | 7312 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 AH |
7313 | { |
7314 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
7315 | tree arglist = TREE_OPERAND (exp, 1); | |
7316 | tree arg1, arg0; | |
7317 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7318 | enum insn_code icode; | |
7319 | enum machine_mode tmode, mode0; | |
7320 | rtx pat, op0; | |
7321 | struct builtin_description *d; | |
7322 | size_t i; | |
7323 | ||
7324 | *expandedp = true; | |
7325 | ||
7326 | /* Syntax check for a 5-bit unsigned immediate. */ | |
7327 | switch (fcode) | |
7328 | { | |
7329 | case SPE_BUILTIN_EVSTDD: | |
7330 | case SPE_BUILTIN_EVSTDH: | |
7331 | case SPE_BUILTIN_EVSTDW: | |
7332 | case SPE_BUILTIN_EVSTWHE: | |
7333 | case SPE_BUILTIN_EVSTWHO: | |
7334 | case SPE_BUILTIN_EVSTWWE: | |
7335 | case SPE_BUILTIN_EVSTWWO: | |
7336 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7337 | if (TREE_CODE (arg1) != INTEGER_CST | |
7338 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
7339 | { | |
7340 | error ("argument 2 must be a 5-bit unsigned literal"); | |
7341 | return const0_rtx; | |
7342 | } | |
7343 | break; | |
7344 | default: | |
7345 | break; | |
7346 | } | |
7347 | ||
00332c9f AH |
7348 | /* The evsplat*i instructions are not quite generic. */ |
7349 | switch (fcode) | |
7350 | { | |
7351 | case SPE_BUILTIN_EVSPLATFI: | |
7352 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
7353 | arglist, target); | |
7354 | case SPE_BUILTIN_EVSPLATI: | |
7355 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
7356 | arglist, target); | |
7357 | default: | |
7358 | break; | |
7359 | } | |
7360 | ||
a3170dc6 AH |
7361 | d = (struct builtin_description *) bdesc_2arg_spe; |
7362 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
7363 | if (d->code == fcode) | |
7364 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
7365 | ||
7366 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7367 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
7368 | if (d->code == fcode) | |
7369 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
7370 | ||
7371 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7372 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
7373 | if (d->code == fcode) | |
7374 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
7375 | ||
7376 | switch (fcode) | |
7377 | { | |
7378 | case SPE_BUILTIN_EVSTDDX: | |
61bea3b0 | 7379 | return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); |
a3170dc6 | 7380 | case SPE_BUILTIN_EVSTDHX: |
61bea3b0 | 7381 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); |
a3170dc6 | 7382 | case SPE_BUILTIN_EVSTDWX: |
61bea3b0 | 7383 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); |
a3170dc6 | 7384 | case SPE_BUILTIN_EVSTWHEX: |
61bea3b0 | 7385 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); |
a3170dc6 | 7386 | case SPE_BUILTIN_EVSTWHOX: |
61bea3b0 | 7387 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); |
a3170dc6 | 7388 | case SPE_BUILTIN_EVSTWWEX: |
61bea3b0 | 7389 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); |
a3170dc6 | 7390 | case SPE_BUILTIN_EVSTWWOX: |
61bea3b0 | 7391 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); |
a3170dc6 | 7392 | case SPE_BUILTIN_EVSTDD: |
61bea3b0 | 7393 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); |
a3170dc6 | 7394 | case SPE_BUILTIN_EVSTDH: |
61bea3b0 | 7395 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); |
a3170dc6 | 7396 | case SPE_BUILTIN_EVSTDW: |
61bea3b0 | 7397 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); |
a3170dc6 | 7398 | case SPE_BUILTIN_EVSTWHE: |
61bea3b0 | 7399 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); |
a3170dc6 | 7400 | case SPE_BUILTIN_EVSTWHO: |
61bea3b0 | 7401 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); |
a3170dc6 | 7402 | case SPE_BUILTIN_EVSTWWE: |
61bea3b0 | 7403 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); |
a3170dc6 | 7404 | case SPE_BUILTIN_EVSTWWO: |
61bea3b0 | 7405 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); |
a3170dc6 AH |
7406 | case SPE_BUILTIN_MFSPEFSCR: |
7407 | icode = CODE_FOR_spe_mfspefscr; | |
7408 | tmode = insn_data[icode].operand[0].mode; | |
7409 | ||
7410 | if (target == 0 | |
7411 | || GET_MODE (target) != tmode | |
7412 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7413 | target = gen_reg_rtx (tmode); | |
f676971a | 7414 | |
a3170dc6 AH |
7415 | pat = GEN_FCN (icode) (target); |
7416 | if (! pat) | |
7417 | return 0; | |
7418 | emit_insn (pat); | |
7419 | return target; | |
7420 | case SPE_BUILTIN_MTSPEFSCR: | |
7421 | icode = CODE_FOR_spe_mtspefscr; | |
7422 | arg0 = TREE_VALUE (arglist); | |
7423 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7424 | mode0 = insn_data[icode].operand[0].mode; | |
7425 | ||
7426 | if (arg0 == error_mark_node) | |
7427 | return const0_rtx; | |
7428 | ||
7429 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
7430 | op0 = copy_to_mode_reg (mode0, op0); | |
7431 | ||
7432 | pat = GEN_FCN (icode) (op0); | |
7433 | if (pat) | |
7434 | emit_insn (pat); | |
7435 | return NULL_RTX; | |
7436 | default: | |
7437 | break; | |
7438 | } | |
7439 | ||
7440 | *expandedp = false; | |
7441 | return NULL_RTX; | |
7442 | } | |
7443 | ||
7444 | static rtx | |
a2369ed3 | 7445 | spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
7446 | { |
7447 | rtx pat, scratch, tmp; | |
7448 | tree form = TREE_VALUE (arglist); | |
7449 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7450 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7451 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7452 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7453 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7454 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7455 | int form_int; | |
7456 | enum rtx_code code; | |
7457 | ||
7458 | if (TREE_CODE (form) != INTEGER_CST) | |
7459 | { | |
7460 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
7461 | return const0_rtx; | |
7462 | } | |
7463 | else | |
7464 | form_int = TREE_INT_CST_LOW (form); | |
7465 | ||
7466 | if (mode0 != mode1) | |
7467 | abort (); | |
7468 | ||
7469 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
7470 | return const0_rtx; | |
7471 | ||
7472 | if (target == 0 | |
7473 | || GET_MODE (target) != SImode | |
7474 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
7475 | target = gen_reg_rtx (SImode); | |
7476 | ||
7477 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7478 | op0 = copy_to_mode_reg (mode0, op0); | |
7479 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
7480 | op1 = copy_to_mode_reg (mode1, op1); | |
7481 | ||
7482 | scratch = gen_reg_rtx (CCmode); | |
7483 | ||
7484 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7485 | if (! pat) | |
7486 | return const0_rtx; | |
7487 | emit_insn (pat); | |
7488 | ||
7489 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
7490 | _lower_. We use one compare, but look in different bits of the | |
7491 | CR for each variant. | |
7492 | ||
7493 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
7494 | bits are set as follows: | |
7495 | ||
7496 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7497 | U | L | (U | L) | (U & L) | |
7498 | ||
7499 | So, for an "all" relationship, BIT 3 would be set. | |
7500 | For an "any" relationship, BIT 2 would be set. Etc. | |
7501 | ||
7502 | Following traditional nomenclature, these bits map to: | |
7503 | ||
7504 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7505 | LT | GT | EQ | OV | |
7506 | ||
7507 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
7508 | */ | |
7509 | ||
7510 | switch (form_int) | |
7511 | { | |
7512 | /* All variant. OV bit. */ | |
7513 | case 0: | |
7514 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
7515 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
7516 | that's ugly and will trigger a validate_condition_mode abort. | |
7517 | So let's just use another pattern. */ | |
7518 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
7519 | return target; | |
7520 | /* Any variant. EQ bit. */ | |
7521 | case 1: | |
7522 | code = EQ; | |
7523 | break; | |
7524 | /* Upper variant. LT bit. */ | |
7525 | case 2: | |
7526 | code = LT; | |
7527 | break; | |
7528 | /* Lower variant. GT bit. */ | |
7529 | case 3: | |
7530 | code = GT; | |
7531 | break; | |
7532 | default: | |
7533 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
7534 | return const0_rtx; | |
7535 | } | |
7536 | ||
7537 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
7538 | emit_move_insn (target, tmp); | |
7539 | ||
7540 | return target; | |
7541 | } | |
7542 | ||
7543 | /* The evsel builtins look like this: | |
7544 | ||
7545 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
7546 | ||
7547 | and work like this: | |
7548 | ||
7549 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
7550 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
7551 | */ | |
7552 | ||
7553 | static rtx | |
a2369ed3 | 7554 | spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
7555 | { |
7556 | rtx pat, scratch; | |
7557 | tree arg0 = TREE_VALUE (arglist); | |
7558 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7559 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7560 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
7561 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7562 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7563 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
7564 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
7565 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7566 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7567 | ||
7568 | if (mode0 != mode1) | |
7569 | abort (); | |
7570 | ||
7571 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
7572 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
7573 | return const0_rtx; | |
7574 | ||
7575 | if (target == 0 | |
7576 | || GET_MODE (target) != mode0 | |
7577 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
7578 | target = gen_reg_rtx (mode0); | |
7579 | ||
7580 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7581 | op0 = copy_to_mode_reg (mode0, op0); | |
7582 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
7583 | op1 = copy_to_mode_reg (mode0, op1); | |
7584 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
7585 | op2 = copy_to_mode_reg (mode0, op2); | |
7586 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
7587 | op3 = copy_to_mode_reg (mode0, op3); | |
7588 | ||
7589 | /* Generate the compare. */ | |
7590 | scratch = gen_reg_rtx (CCmode); | |
7591 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7592 | if (! pat) | |
7593 | return const0_rtx; | |
7594 | emit_insn (pat); | |
7595 | ||
7596 | if (mode0 == V2SImode) | |
7597 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
7598 | else | |
7599 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
7600 | ||
7601 | return target; | |
7602 | } | |
7603 | ||
0ac081f6 AH |
7604 | /* Expand an expression EXP that calls a built-in function, |
7605 | with result going to TARGET if that's convenient | |
7606 | (and in mode MODE if that's convenient). | |
7607 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
7608 | IGNORE is nonzero if the value is to be ignored. */ | |
7609 | ||
7610 | static rtx | |
a2369ed3 | 7611 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
c4ad648e AM |
7612 | enum machine_mode mode ATTRIBUTE_UNUSED, |
7613 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 7614 | { |
92898235 AH |
7615 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
7616 | tree arglist = TREE_OPERAND (exp, 1); | |
7617 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7618 | struct builtin_description *d; | |
7619 | size_t i; | |
7620 | rtx ret; | |
7621 | bool success; | |
f676971a | 7622 | |
7ccf35ed DN |
7623 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD |
7624 | || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7625 | { | |
7626 | int icode = (int) CODE_FOR_altivec_lvsr; | |
7627 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
7628 | enum machine_mode mode = insn_data[icode].operand[1].mode; | |
7629 | tree arg; | |
7630 | rtx op, addr, pat; | |
7631 | ||
7632 | if (!TARGET_ALTIVEC) | |
7633 | abort (); | |
7634 | ||
7635 | arg = TREE_VALUE (arglist); | |
7636 | if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE) | |
7637 | abort (); | |
7638 | op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); | |
7639 | addr = memory_address (mode, op); | |
7640 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7641 | op = addr; | |
7642 | else | |
7643 | { | |
7644 | /* For the load case need to negate the address. */ | |
7645 | op = gen_reg_rtx (GET_MODE (addr)); | |
7646 | emit_insn (gen_rtx_SET (VOIDmode, op, | |
7647 | gen_rtx_NEG (GET_MODE (addr), addr))); | |
c4ad648e | 7648 | } |
7ccf35ed DN |
7649 | op = gen_rtx_MEM (mode, op); |
7650 | ||
7651 | if (target == 0 | |
7652 | || GET_MODE (target) != tmode | |
7653 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7654 | target = gen_reg_rtx (tmode); | |
7655 | ||
7656 | /*pat = gen_altivec_lvsr (target, op);*/ | |
7657 | pat = GEN_FCN (icode) (target, op); | |
7658 | if (!pat) | |
7659 | return 0; | |
7660 | emit_insn (pat); | |
7661 | ||
7662 | return target; | |
7663 | } | |
7664 | ||
0ac081f6 | 7665 | if (TARGET_ALTIVEC) |
92898235 AH |
7666 | { |
7667 | ret = altivec_expand_builtin (exp, target, &success); | |
7668 | ||
a3170dc6 AH |
7669 | if (success) |
7670 | return ret; | |
7671 | } | |
7672 | if (TARGET_SPE) | |
7673 | { | |
7674 | ret = spe_expand_builtin (exp, target, &success); | |
7675 | ||
92898235 AH |
7676 | if (success) |
7677 | return ret; | |
7678 | } | |
7679 | ||
0559cc77 DE |
7680 | if (TARGET_ALTIVEC || TARGET_SPE) |
7681 | { | |
7682 | /* Handle simple unary operations. */ | |
7683 | d = (struct builtin_description *) bdesc_1arg; | |
7684 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
7685 | if (d->code == fcode) | |
7686 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
7687 | ||
7688 | /* Handle simple binary operations. */ | |
7689 | d = (struct builtin_description *) bdesc_2arg; | |
7690 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
7691 | if (d->code == fcode) | |
7692 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
7693 | ||
7694 | /* Handle simple ternary operations. */ | |
7695 | d = (struct builtin_description *) bdesc_3arg; | |
7696 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
7697 | if (d->code == fcode) | |
7698 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
7699 | } | |
0ac081f6 AH |
7700 | |
7701 | abort (); | |
92898235 | 7702 | return NULL_RTX; |
0ac081f6 AH |
7703 | } |
7704 | ||
7c62e993 PB |
7705 | static tree |
7706 | build_opaque_vector_type (tree node, int nunits) | |
7707 | { | |
7708 | node = copy_node (node); | |
7709 | TYPE_MAIN_VARIANT (node) = node; | |
7710 | return build_vector_type (node, nunits); | |
7711 | } | |
7712 | ||
0ac081f6 | 7713 | static void |
863d938c | 7714 | rs6000_init_builtins (void) |
0ac081f6 | 7715 | { |
4a5eab38 PB |
7716 | V2SI_type_node = build_vector_type (intSI_type_node, 2); |
7717 | V2SF_type_node = build_vector_type (float_type_node, 2); | |
7718 | V4HI_type_node = build_vector_type (intHI_type_node, 4); | |
7719 | V4SI_type_node = build_vector_type (intSI_type_node, 4); | |
7720 | V4SF_type_node = build_vector_type (float_type_node, 4); | |
7e463bda | 7721 | V8HI_type_node = build_vector_type (intHI_type_node, 8); |
4a5eab38 PB |
7722 | V16QI_type_node = build_vector_type (intQI_type_node, 16); |
7723 | ||
7724 | unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); | |
7725 | unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); | |
7726 | unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); | |
7727 | ||
7c62e993 PB |
7728 | opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); |
7729 | opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); | |
6035d635 | 7730 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
3fdaa45a | 7731 | |
8bb418a3 ZL |
7732 | /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' |
7733 | types, especially in C++ land. Similarly, 'vector pixel' is distinct from | |
7734 | 'vector unsigned short'. */ | |
7735 | ||
8dd16ecc NS |
7736 | bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); |
7737 | bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
7738 | bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); | |
7739 | pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
8bb418a3 ZL |
7740 | |
7741 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7742 | get_identifier ("__bool char"), | |
7743 | bool_char_type_node)); | |
7744 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7745 | get_identifier ("__bool short"), | |
7746 | bool_short_type_node)); | |
7747 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7748 | get_identifier ("__bool int"), | |
7749 | bool_int_type_node)); | |
7750 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7751 | get_identifier ("__pixel"), | |
7752 | pixel_type_node)); | |
7753 | ||
4a5eab38 PB |
7754 | bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); |
7755 | bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); | |
7756 | bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); | |
7757 | pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); | |
8bb418a3 ZL |
7758 | |
7759 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7760 | get_identifier ("__vector unsigned char"), | |
7761 | unsigned_V16QI_type_node)); | |
7762 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7763 | get_identifier ("__vector signed char"), | |
7764 | V16QI_type_node)); | |
7765 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7766 | get_identifier ("__vector __bool char"), | |
7767 | bool_V16QI_type_node)); | |
7768 | ||
7769 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7770 | get_identifier ("__vector unsigned short"), | |
7771 | unsigned_V8HI_type_node)); | |
7772 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7773 | get_identifier ("__vector signed short"), | |
7774 | V8HI_type_node)); | |
7775 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7776 | get_identifier ("__vector __bool short"), | |
7777 | bool_V8HI_type_node)); | |
7778 | ||
7779 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7780 | get_identifier ("__vector unsigned int"), | |
7781 | unsigned_V4SI_type_node)); | |
7782 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7783 | get_identifier ("__vector signed int"), | |
7784 | V4SI_type_node)); | |
7785 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7786 | get_identifier ("__vector __bool int"), | |
7787 | bool_V4SI_type_node)); | |
7788 | ||
7789 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7790 | get_identifier ("__vector float"), | |
7791 | V4SF_type_node)); | |
7792 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7793 | get_identifier ("__vector __pixel"), | |
7794 | pixel_V8HI_type_node)); | |
7795 | ||
a3170dc6 | 7796 | if (TARGET_SPE) |
3fdaa45a | 7797 | spe_init_builtins (); |
0ac081f6 AH |
7798 | if (TARGET_ALTIVEC) |
7799 | altivec_init_builtins (); | |
0559cc77 DE |
7800 | if (TARGET_ALTIVEC || TARGET_SPE) |
7801 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
7802 | } |
7803 | ||
a3170dc6 AH |
7804 | /* Search through a set of builtins and enable the mask bits. |
7805 | DESC is an array of builtins. | |
b6d08ca1 | 7806 | SIZE is the total number of builtins. |
a3170dc6 AH |
7807 | START is the builtin enum at which to start. |
7808 | END is the builtin enum at which to end. */ | |
0ac081f6 | 7809 | static void |
a2369ed3 | 7810 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
f676971a | 7811 | enum rs6000_builtins start, |
a2369ed3 | 7812 | enum rs6000_builtins end) |
a3170dc6 AH |
7813 | { |
7814 | int i; | |
7815 | ||
7816 | for (i = 0; i < size; ++i) | |
7817 | if (desc[i].code == start) | |
7818 | break; | |
7819 | ||
7820 | if (i == size) | |
7821 | return; | |
7822 | ||
7823 | for (; i < size; ++i) | |
7824 | { | |
7825 | /* Flip all the bits on. */ | |
7826 | desc[i].mask = target_flags; | |
7827 | if (desc[i].code == end) | |
7828 | break; | |
7829 | } | |
7830 | } | |
7831 | ||
7832 | static void | |
863d938c | 7833 | spe_init_builtins (void) |
0ac081f6 | 7834 | { |
a3170dc6 AH |
7835 | tree endlink = void_list_node; |
7836 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
7837 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 7838 | struct builtin_description *d; |
0ac081f6 AH |
7839 | size_t i; |
7840 | ||
a3170dc6 AH |
7841 | tree v2si_ftype_4_v2si |
7842 | = build_function_type | |
3fdaa45a AH |
7843 | (opaque_V2SI_type_node, |
7844 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7845 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7846 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7847 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7848 | endlink))))); |
7849 | ||
7850 | tree v2sf_ftype_4_v2sf | |
7851 | = build_function_type | |
3fdaa45a AH |
7852 | (opaque_V2SF_type_node, |
7853 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7854 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7855 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7856 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7857 | endlink))))); |
7858 | ||
7859 | tree int_ftype_int_v2si_v2si | |
7860 | = build_function_type | |
7861 | (integer_type_node, | |
7862 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7863 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
7864 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7865 | endlink)))); |
7866 | ||
7867 | tree int_ftype_int_v2sf_v2sf | |
7868 | = build_function_type | |
7869 | (integer_type_node, | |
7870 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7871 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
7872 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7873 | endlink)))); |
7874 | ||
7875 | tree void_ftype_v2si_puint_int | |
7876 | = build_function_type (void_type_node, | |
3fdaa45a | 7877 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7878 | tree_cons (NULL_TREE, puint_type_node, |
7879 | tree_cons (NULL_TREE, | |
7880 | integer_type_node, | |
7881 | endlink)))); | |
7882 | ||
7883 | tree void_ftype_v2si_puint_char | |
7884 | = build_function_type (void_type_node, | |
3fdaa45a | 7885 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7886 | tree_cons (NULL_TREE, puint_type_node, |
7887 | tree_cons (NULL_TREE, | |
7888 | char_type_node, | |
7889 | endlink)))); | |
7890 | ||
7891 | tree void_ftype_v2si_pv2si_int | |
7892 | = build_function_type (void_type_node, | |
3fdaa45a | 7893 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7894 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7895 | tree_cons (NULL_TREE, |
7896 | integer_type_node, | |
7897 | endlink)))); | |
7898 | ||
7899 | tree void_ftype_v2si_pv2si_char | |
7900 | = build_function_type (void_type_node, | |
3fdaa45a | 7901 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7902 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7903 | tree_cons (NULL_TREE, |
7904 | char_type_node, | |
7905 | endlink)))); | |
7906 | ||
7907 | tree void_ftype_int | |
7908 | = build_function_type (void_type_node, | |
7909 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
7910 | ||
7911 | tree int_ftype_void | |
36e8d515 | 7912 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
7913 | |
7914 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 7915 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 7916 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7917 | tree_cons (NULL_TREE, integer_type_node, |
7918 | endlink))); | |
7919 | ||
7920 | tree v2si_ftype_puint_int | |
3fdaa45a | 7921 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7922 | tree_cons (NULL_TREE, puint_type_node, |
7923 | tree_cons (NULL_TREE, integer_type_node, | |
7924 | endlink))); | |
7925 | ||
7926 | tree v2si_ftype_pushort_int | |
3fdaa45a | 7927 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7928 | tree_cons (NULL_TREE, pushort_type_node, |
7929 | tree_cons (NULL_TREE, integer_type_node, | |
7930 | endlink))); | |
7931 | ||
00332c9f AH |
7932 | tree v2si_ftype_signed_char |
7933 | = build_function_type (opaque_V2SI_type_node, | |
7934 | tree_cons (NULL_TREE, signed_char_type_node, | |
7935 | endlink)); | |
7936 | ||
a3170dc6 AH |
7937 | /* The initialization of the simple binary and unary builtins is |
7938 | done in rs6000_common_init_builtins, but we have to enable the | |
7939 | mask bits here manually because we have run out of `target_flags' | |
7940 | bits. We really need to redesign this mask business. */ | |
7941 | ||
7942 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
7943 | ARRAY_SIZE (bdesc_2arg), | |
7944 | SPE_BUILTIN_EVADDW, | |
7945 | SPE_BUILTIN_EVXOR); | |
7946 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
7947 | ARRAY_SIZE (bdesc_1arg), | |
7948 | SPE_BUILTIN_EVABS, | |
7949 | SPE_BUILTIN_EVSUBFUSIAAW); | |
7950 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
7951 | ARRAY_SIZE (bdesc_spe_predicates), | |
7952 | SPE_BUILTIN_EVCMPEQ, | |
7953 | SPE_BUILTIN_EVFSTSTLT); | |
7954 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
7955 | ARRAY_SIZE (bdesc_spe_evsel), | |
7956 | SPE_BUILTIN_EVSEL_CMPGTS, | |
7957 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
7958 | ||
36252949 AH |
7959 | (*lang_hooks.decls.pushdecl) |
7960 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
7961 | opaque_V2SI_type_node)); | |
7962 | ||
a3170dc6 | 7963 | /* Initialize irregular SPE builtins. */ |
f676971a | 7964 | |
a3170dc6 AH |
7965 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); |
7966 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
7967 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
7968 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
7969 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
7970 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
7971 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
7972 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
7973 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
7974 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
7975 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
7976 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
7977 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
7978 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
7979 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
7980 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
7981 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
7982 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
7983 | |
7984 | /* Loads. */ | |
7985 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
7986 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
7987 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
7988 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
7989 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
7990 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
7991 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
7992 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
7993 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
7994 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
7995 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
7996 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
7997 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
7998 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
7999 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
8000 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
8001 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
8002 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
8003 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
8004 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
8005 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
8006 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
8007 | ||
8008 | /* Predicates. */ | |
8009 | d = (struct builtin_description *) bdesc_spe_predicates; | |
8010 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
8011 | { | |
8012 | tree type; | |
8013 | ||
8014 | switch (insn_data[d->icode].operand[1].mode) | |
8015 | { | |
8016 | case V2SImode: | |
8017 | type = int_ftype_int_v2si_v2si; | |
8018 | break; | |
8019 | case V2SFmode: | |
8020 | type = int_ftype_int_v2sf_v2sf; | |
8021 | break; | |
8022 | default: | |
8023 | abort (); | |
8024 | } | |
8025 | ||
8026 | def_builtin (d->mask, d->name, type, d->code); | |
8027 | } | |
8028 | ||
8029 | /* Evsel predicates. */ | |
8030 | d = (struct builtin_description *) bdesc_spe_evsel; | |
8031 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
8032 | { | |
8033 | tree type; | |
8034 | ||
8035 | switch (insn_data[d->icode].operand[1].mode) | |
8036 | { | |
8037 | case V2SImode: | |
8038 | type = v2si_ftype_4_v2si; | |
8039 | break; | |
8040 | case V2SFmode: | |
8041 | type = v2sf_ftype_4_v2sf; | |
8042 | break; | |
8043 | default: | |
8044 | abort (); | |
8045 | } | |
8046 | ||
8047 | def_builtin (d->mask, d->name, type, d->code); | |
8048 | } | |
8049 | } | |
8050 | ||
8051 | static void | |
863d938c | 8052 | altivec_init_builtins (void) |
a3170dc6 AH |
8053 | { |
8054 | struct builtin_description *d; | |
8055 | struct builtin_description_predicates *dp; | |
8056 | size_t i; | |
8057 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
8058 | tree pint_type_node = build_pointer_type (integer_type_node); | |
8059 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
8060 | tree pchar_type_node = build_pointer_type (char_type_node); | |
8061 | ||
8062 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
8063 | ||
0dbc3651 ZW |
8064 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
8065 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
8066 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
8067 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
8068 | ||
8069 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
8070 | ||
a3170dc6 AH |
8071 | tree int_ftype_int_v4si_v4si |
8072 | = build_function_type_list (integer_type_node, | |
8073 | integer_type_node, V4SI_type_node, | |
8074 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
8075 | tree v4sf_ftype_pcfloat |
8076 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 8077 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 8078 | = build_function_type_list (void_type_node, |
a3170dc6 | 8079 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
8080 | tree v4si_ftype_pcint |
8081 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
8082 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
8083 | = build_function_type_list (void_type_node, |
8084 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
8085 | tree v8hi_ftype_pcshort |
8086 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 8087 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
8088 | = build_function_type_list (void_type_node, |
8089 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
8090 | tree v16qi_ftype_pcchar |
8091 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 8092 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
8093 | = build_function_type_list (void_type_node, |
8094 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 8095 | tree void_ftype_v4si |
b4de2f7d | 8096 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
8097 | tree v8hi_ftype_void |
8098 | = build_function_type (V8HI_type_node, void_list_node); | |
8099 | tree void_ftype_void | |
8100 | = build_function_type (void_type_node, void_list_node); | |
e34b6648 JJ |
8101 | tree void_ftype_int |
8102 | = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); | |
0dbc3651 | 8103 | |
b4a62fa0 | 8104 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 8105 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
8106 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
8107 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 8108 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
8109 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
8110 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 8111 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 8112 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 8113 | |
b4a62fa0 | 8114 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 8115 | = build_function_type_list (void_type_node, |
b4a62fa0 | 8116 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 8117 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 8118 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 8119 | = build_function_type_list (void_type_node, |
b4a62fa0 | 8120 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 8121 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 8122 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 8123 | = build_function_type_list (void_type_node, |
b4a62fa0 | 8124 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 8125 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
8126 | tree int_ftype_int_v8hi_v8hi |
8127 | = build_function_type_list (integer_type_node, | |
8128 | integer_type_node, V8HI_type_node, | |
8129 | V8HI_type_node, NULL_TREE); | |
8130 | tree int_ftype_int_v16qi_v16qi | |
8131 | = build_function_type_list (integer_type_node, | |
8132 | integer_type_node, V16QI_type_node, | |
8133 | V16QI_type_node, NULL_TREE); | |
8134 | tree int_ftype_int_v4sf_v4sf | |
8135 | = build_function_type_list (integer_type_node, | |
8136 | integer_type_node, V4SF_type_node, | |
8137 | V4SF_type_node, NULL_TREE); | |
8138 | tree v4si_ftype_v4si | |
8139 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
8140 | tree v8hi_ftype_v8hi | |
8141 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
8142 | tree v16qi_ftype_v16qi | |
8143 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
8144 | tree v4sf_ftype_v4sf | |
8145 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8bb418a3 | 8146 | tree void_ftype_pcvoid_int_int |
a3170dc6 | 8147 | = build_function_type_list (void_type_node, |
0dbc3651 | 8148 | pcvoid_type_node, integer_type_node, |
8bb418a3 ZL |
8149 | integer_type_node, NULL_TREE); |
8150 | tree int_ftype_pcchar | |
8151 | = build_function_type_list (integer_type_node, | |
8152 | pcchar_type_node, NULL_TREE); | |
8153 | ||
0dbc3651 ZW |
8154 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, |
8155 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
8156 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
8157 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
8158 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
8159 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
8160 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
8161 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
8162 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
8163 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
8164 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
8165 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
8166 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
8167 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
8168 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
8169 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
8170 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
8171 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
8172 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
e34b6648 | 8173 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); |
b4a62fa0 SB |
8174 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
8175 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
8176 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
8177 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
8178 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
8179 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
8180 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
8181 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
8182 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
8183 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
8184 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
8185 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
a3170dc6 | 8186 | |
8bb418a3 ZL |
8187 | /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */ |
8188 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar, | |
8189 | ALTIVEC_BUILTIN_COMPILETIME_ERROR); | |
8190 | ||
a3170dc6 AH |
8191 | /* Add the DST variants. */ |
8192 | d = (struct builtin_description *) bdesc_dst; | |
8193 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
8bb418a3 | 8194 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); |
a3170dc6 AH |
8195 | |
8196 | /* Initialize the predicates. */ | |
8197 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
8198 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
8199 | { | |
8200 | enum machine_mode mode1; | |
8201 | tree type; | |
8202 | ||
8203 | mode1 = insn_data[dp->icode].operand[1].mode; | |
8204 | ||
8205 | switch (mode1) | |
8206 | { | |
8207 | case V4SImode: | |
8208 | type = int_ftype_int_v4si_v4si; | |
8209 | break; | |
8210 | case V8HImode: | |
8211 | type = int_ftype_int_v8hi_v8hi; | |
8212 | break; | |
8213 | case V16QImode: | |
8214 | type = int_ftype_int_v16qi_v16qi; | |
8215 | break; | |
8216 | case V4SFmode: | |
8217 | type = int_ftype_int_v4sf_v4sf; | |
8218 | break; | |
8219 | default: | |
8220 | abort (); | |
8221 | } | |
f676971a | 8222 | |
a3170dc6 AH |
8223 | def_builtin (dp->mask, dp->name, type, dp->code); |
8224 | } | |
8225 | ||
8226 | /* Initialize the abs* operators. */ | |
8227 | d = (struct builtin_description *) bdesc_abs; | |
8228 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
8229 | { | |
8230 | enum machine_mode mode0; | |
8231 | tree type; | |
8232 | ||
8233 | mode0 = insn_data[d->icode].operand[0].mode; | |
8234 | ||
8235 | switch (mode0) | |
8236 | { | |
8237 | case V4SImode: | |
8238 | type = v4si_ftype_v4si; | |
8239 | break; | |
8240 | case V8HImode: | |
8241 | type = v8hi_ftype_v8hi; | |
8242 | break; | |
8243 | case V16QImode: | |
8244 | type = v16qi_ftype_v16qi; | |
8245 | break; | |
8246 | case V4SFmode: | |
8247 | type = v4sf_ftype_v4sf; | |
8248 | break; | |
8249 | default: | |
8250 | abort (); | |
8251 | } | |
f676971a | 8252 | |
a3170dc6 AH |
8253 | def_builtin (d->mask, d->name, type, d->code); |
8254 | } | |
7ccf35ed | 8255 | |
13c62176 DN |
8256 | if (TARGET_ALTIVEC) |
8257 | { | |
8258 | tree decl; | |
8259 | ||
8260 | /* Initialize target builtin that implements | |
8261 | targetm.vectorize.builtin_mask_for_load. */ | |
8262 | ||
8263 | decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load", | |
8264 | v16qi_ftype_long_pcvoid, | |
8265 | ALTIVEC_BUILTIN_MASK_FOR_LOAD, | |
8266 | BUILT_IN_MD, NULL, NULL_TREE); | |
8267 | /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ | |
8268 | altivec_builtin_mask_for_load = decl; | |
8269 | ||
8270 | ||
8271 | /* Initialize target builtin that implements | |
8272 | targetm.vectorize.builtin_mask_for_store. */ | |
8273 | ||
8274 | decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_store", | |
8275 | v16qi_ftype_long_pcvoid, | |
8276 | ALTIVEC_BUILTIN_MASK_FOR_STORE, | |
8277 | BUILT_IN_MD, NULL, NULL_TREE); | |
8278 | /* Record the decl. Will be used by rs6000_builtin_mask_for_store. */ | |
8279 | altivec_builtin_mask_for_store = decl; | |
8280 | } | |
a3170dc6 AH |
8281 | } |
8282 | ||
8283 | static void | |
863d938c | 8284 | rs6000_common_init_builtins (void) |
a3170dc6 AH |
8285 | { |
8286 | struct builtin_description *d; | |
8287 | size_t i; | |
8288 | ||
8289 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
8290 | = build_function_type_list (V4SF_type_node, | |
8291 | V4SF_type_node, V4SF_type_node, | |
8292 | V16QI_type_node, NULL_TREE); | |
8293 | tree v4si_ftype_v4si_v4si_v16qi | |
8294 | = build_function_type_list (V4SI_type_node, | |
8295 | V4SI_type_node, V4SI_type_node, | |
8296 | V16QI_type_node, NULL_TREE); | |
8297 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
8298 | = build_function_type_list (V8HI_type_node, | |
8299 | V8HI_type_node, V8HI_type_node, | |
8300 | V16QI_type_node, NULL_TREE); | |
8301 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
8302 | = build_function_type_list (V16QI_type_node, | |
8303 | V16QI_type_node, V16QI_type_node, | |
8304 | V16QI_type_node, NULL_TREE); | |
b9e4e5d1 ZL |
8305 | tree v4si_ftype_int |
8306 | = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); | |
8307 | tree v8hi_ftype_int | |
8308 | = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); | |
8309 | tree v16qi_ftype_int | |
8310 | = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); | |
a3170dc6 AH |
8311 | tree v8hi_ftype_v16qi |
8312 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
8313 | tree v4sf_ftype_v4sf | |
8314 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8315 | ||
8316 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
8317 | = build_function_type_list (opaque_V2SI_type_node, |
8318 | opaque_V2SI_type_node, | |
8319 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8320 | |
8321 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
8322 | = build_function_type_list (opaque_V2SF_type_node, |
8323 | opaque_V2SF_type_node, | |
8324 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
8325 | |
8326 | tree v2si_ftype_int_int | |
2abe3e28 | 8327 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
8328 | integer_type_node, integer_type_node, |
8329 | NULL_TREE); | |
8330 | ||
8331 | tree v2si_ftype_v2si | |
2abe3e28 AH |
8332 | = build_function_type_list (opaque_V2SI_type_node, |
8333 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8334 | |
8335 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
8336 | = build_function_type_list (opaque_V2SF_type_node, |
8337 | opaque_V2SF_type_node, NULL_TREE); | |
f676971a | 8338 | |
a3170dc6 | 8339 | tree v2sf_ftype_v2si |
2abe3e28 AH |
8340 | = build_function_type_list (opaque_V2SF_type_node, |
8341 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8342 | |
8343 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
8344 | = build_function_type_list (opaque_V2SI_type_node, |
8345 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
8346 | |
8347 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
8348 | = build_function_type_list (opaque_V2SI_type_node, |
8349 | opaque_V2SI_type_node, | |
8350 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
8351 | |
8352 | tree v2si_ftype_int_char | |
2abe3e28 | 8353 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
8354 | integer_type_node, char_type_node, NULL_TREE); |
8355 | ||
8356 | tree v2si_ftype_char | |
2abe3e28 AH |
8357 | = build_function_type_list (opaque_V2SI_type_node, |
8358 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
8359 | |
8360 | tree int_ftype_int_int | |
8361 | = build_function_type_list (integer_type_node, | |
8362 | integer_type_node, integer_type_node, | |
8363 | NULL_TREE); | |
95385cbb | 8364 | |
0ac081f6 | 8365 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
8366 | = build_function_type_list (V4SI_type_node, |
8367 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
b9e4e5d1 | 8368 | tree v4sf_ftype_v4si_int |
b4de2f7d | 8369 | = build_function_type_list (V4SF_type_node, |
b9e4e5d1 ZL |
8370 | V4SI_type_node, integer_type_node, NULL_TREE); |
8371 | tree v4si_ftype_v4sf_int | |
b4de2f7d | 8372 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
8373 | V4SF_type_node, integer_type_node, NULL_TREE); |
8374 | tree v4si_ftype_v4si_int | |
b4de2f7d | 8375 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
8376 | V4SI_type_node, integer_type_node, NULL_TREE); |
8377 | tree v8hi_ftype_v8hi_int | |
b4de2f7d | 8378 | = build_function_type_list (V8HI_type_node, |
b9e4e5d1 ZL |
8379 | V8HI_type_node, integer_type_node, NULL_TREE); |
8380 | tree v16qi_ftype_v16qi_int | |
b4de2f7d | 8381 | = build_function_type_list (V16QI_type_node, |
b9e4e5d1 ZL |
8382 | V16QI_type_node, integer_type_node, NULL_TREE); |
8383 | tree v16qi_ftype_v16qi_v16qi_int | |
b4de2f7d AH |
8384 | = build_function_type_list (V16QI_type_node, |
8385 | V16QI_type_node, V16QI_type_node, | |
b9e4e5d1 ZL |
8386 | integer_type_node, NULL_TREE); |
8387 | tree v8hi_ftype_v8hi_v8hi_int | |
b4de2f7d AH |
8388 | = build_function_type_list (V8HI_type_node, |
8389 | V8HI_type_node, V8HI_type_node, | |
b9e4e5d1 ZL |
8390 | integer_type_node, NULL_TREE); |
8391 | tree v4si_ftype_v4si_v4si_int | |
b4de2f7d AH |
8392 | = build_function_type_list (V4SI_type_node, |
8393 | V4SI_type_node, V4SI_type_node, | |
b9e4e5d1 ZL |
8394 | integer_type_node, NULL_TREE); |
8395 | tree v4sf_ftype_v4sf_v4sf_int | |
b4de2f7d AH |
8396 | = build_function_type_list (V4SF_type_node, |
8397 | V4SF_type_node, V4SF_type_node, | |
b9e4e5d1 | 8398 | integer_type_node, NULL_TREE); |
0ac081f6 | 8399 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
8400 | = build_function_type_list (V4SF_type_node, |
8401 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
617e0e1d | 8402 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
8403 | = build_function_type_list (V4SF_type_node, |
8404 | V4SF_type_node, V4SF_type_node, | |
8405 | V4SI_type_node, NULL_TREE); | |
2212663f | 8406 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
8407 | = build_function_type_list (V4SF_type_node, |
8408 | V4SF_type_node, V4SF_type_node, | |
8409 | V4SF_type_node, NULL_TREE); | |
f676971a | 8410 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
8411 | = build_function_type_list (V4SI_type_node, |
8412 | V4SI_type_node, V4SI_type_node, | |
8413 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8414 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
8415 | = build_function_type_list (V8HI_type_node, |
8416 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 8417 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
8418 | = build_function_type_list (V8HI_type_node, |
8419 | V8HI_type_node, V8HI_type_node, | |
8420 | V8HI_type_node, NULL_TREE); | |
c4ad648e | 8421 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
8422 | = build_function_type_list (V4SI_type_node, |
8423 | V8HI_type_node, V8HI_type_node, | |
8424 | V4SI_type_node, NULL_TREE); | |
c4ad648e | 8425 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
8426 | = build_function_type_list (V4SI_type_node, |
8427 | V16QI_type_node, V16QI_type_node, | |
8428 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8429 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
8430 | = build_function_type_list (V16QI_type_node, |
8431 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8432 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
8433 | = build_function_type_list (V4SI_type_node, |
8434 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 8435 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
8436 | = build_function_type_list (V8HI_type_node, |
8437 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8438 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
8439 | = build_function_type_list (V4SI_type_node, |
8440 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8441 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
8442 | = build_function_type_list (V8HI_type_node, |
8443 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8444 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
8445 | = build_function_type_list (V16QI_type_node, |
8446 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8447 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
8448 | = build_function_type_list (V4SI_type_node, |
8449 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 8450 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
8451 | = build_function_type_list (V4SI_type_node, |
8452 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8453 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
8454 | = build_function_type_list (V4SI_type_node, |
8455 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8456 | tree v4si_ftype_v8hi |
8457 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
8458 | tree int_ftype_v4si_v4si | |
8459 | = build_function_type_list (integer_type_node, | |
8460 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
8461 | tree int_ftype_v4sf_v4sf | |
8462 | = build_function_type_list (integer_type_node, | |
8463 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8464 | tree int_ftype_v16qi_v16qi | |
8465 | = build_function_type_list (integer_type_node, | |
8466 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8467 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
8468 | = build_function_type_list (integer_type_node, |
8469 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8470 | |
6f317ef3 | 8471 | /* Add the simple ternary operators. */ |
2212663f | 8472 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 8473 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f | 8474 | { |
f676971a | 8475 | |
2212663f DB |
8476 | enum machine_mode mode0, mode1, mode2, mode3; |
8477 | tree type; | |
8478 | ||
0559cc77 | 8479 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f | 8480 | continue; |
f676971a | 8481 | |
2212663f DB |
8482 | mode0 = insn_data[d->icode].operand[0].mode; |
8483 | mode1 = insn_data[d->icode].operand[1].mode; | |
8484 | mode2 = insn_data[d->icode].operand[2].mode; | |
8485 | mode3 = insn_data[d->icode].operand[3].mode; | |
f676971a | 8486 | |
2212663f DB |
8487 | /* When all four are of the same mode. */ |
8488 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
8489 | { | |
8490 | switch (mode0) | |
8491 | { | |
617e0e1d DB |
8492 | case V4SImode: |
8493 | type = v4si_ftype_v4si_v4si_v4si; | |
8494 | break; | |
2212663f DB |
8495 | case V4SFmode: |
8496 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
8497 | break; | |
8498 | case V8HImode: | |
8499 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
f676971a | 8500 | break; |
2212663f DB |
8501 | case V16QImode: |
8502 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 8503 | break; |
2212663f | 8504 | default: |
f676971a | 8505 | abort(); |
2212663f DB |
8506 | } |
8507 | } | |
8508 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
c4ad648e | 8509 | { |
2212663f DB |
8510 | switch (mode0) |
8511 | { | |
8512 | case V4SImode: | |
8513 | type = v4si_ftype_v4si_v4si_v16qi; | |
8514 | break; | |
8515 | case V4SFmode: | |
8516 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
8517 | break; | |
8518 | case V8HImode: | |
8519 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
f676971a | 8520 | break; |
2212663f DB |
8521 | case V16QImode: |
8522 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 8523 | break; |
2212663f | 8524 | default: |
f676971a | 8525 | abort(); |
2212663f DB |
8526 | } |
8527 | } | |
f676971a | 8528 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode |
2212663f | 8529 | && mode3 == V4SImode) |
24408032 | 8530 | type = v4si_ftype_v16qi_v16qi_v4si; |
f676971a | 8531 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
2212663f | 8532 | && mode3 == V4SImode) |
24408032 | 8533 | type = v4si_ftype_v8hi_v8hi_v4si; |
f676971a | 8534 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
617e0e1d | 8535 | && mode3 == V4SImode) |
24408032 AH |
8536 | type = v4sf_ftype_v4sf_v4sf_v4si; |
8537 | ||
8538 | /* vchar, vchar, vchar, 4 bit literal. */ | |
8539 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
8540 | && mode3 == QImode) | |
b9e4e5d1 | 8541 | type = v16qi_ftype_v16qi_v16qi_int; |
24408032 AH |
8542 | |
8543 | /* vshort, vshort, vshort, 4 bit literal. */ | |
8544 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
8545 | && mode3 == QImode) | |
b9e4e5d1 | 8546 | type = v8hi_ftype_v8hi_v8hi_int; |
24408032 AH |
8547 | |
8548 | /* vint, vint, vint, 4 bit literal. */ | |
8549 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
8550 | && mode3 == QImode) | |
b9e4e5d1 | 8551 | type = v4si_ftype_v4si_v4si_int; |
24408032 AH |
8552 | |
8553 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
8554 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
8555 | && mode3 == QImode) | |
b9e4e5d1 | 8556 | type = v4sf_ftype_v4sf_v4sf_int; |
24408032 | 8557 | |
2212663f DB |
8558 | else |
8559 | abort (); | |
8560 | ||
8561 | def_builtin (d->mask, d->name, type, d->code); | |
8562 | } | |
8563 | ||
0ac081f6 | 8564 | /* Add the simple binary operators. */ |
00b960c7 | 8565 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 8566 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
8567 | { |
8568 | enum machine_mode mode0, mode1, mode2; | |
8569 | tree type; | |
8570 | ||
0559cc77 | 8571 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
0ac081f6 | 8572 | continue; |
f676971a | 8573 | |
0ac081f6 AH |
8574 | mode0 = insn_data[d->icode].operand[0].mode; |
8575 | mode1 = insn_data[d->icode].operand[1].mode; | |
8576 | mode2 = insn_data[d->icode].operand[2].mode; | |
8577 | ||
8578 | /* When all three operands are of the same mode. */ | |
8579 | if (mode0 == mode1 && mode1 == mode2) | |
8580 | { | |
8581 | switch (mode0) | |
8582 | { | |
8583 | case V4SFmode: | |
8584 | type = v4sf_ftype_v4sf_v4sf; | |
8585 | break; | |
8586 | case V4SImode: | |
8587 | type = v4si_ftype_v4si_v4si; | |
8588 | break; | |
8589 | case V16QImode: | |
8590 | type = v16qi_ftype_v16qi_v16qi; | |
8591 | break; | |
8592 | case V8HImode: | |
8593 | type = v8hi_ftype_v8hi_v8hi; | |
8594 | break; | |
a3170dc6 AH |
8595 | case V2SImode: |
8596 | type = v2si_ftype_v2si_v2si; | |
8597 | break; | |
8598 | case V2SFmode: | |
8599 | type = v2sf_ftype_v2sf_v2sf; | |
8600 | break; | |
8601 | case SImode: | |
8602 | type = int_ftype_int_int; | |
8603 | break; | |
0ac081f6 AH |
8604 | default: |
8605 | abort (); | |
8606 | } | |
8607 | } | |
8608 | ||
8609 | /* A few other combos we really don't want to do manually. */ | |
8610 | ||
8611 | /* vint, vfloat, vfloat. */ | |
8612 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
8613 | type = v4si_ftype_v4sf_v4sf; | |
8614 | ||
8615 | /* vshort, vchar, vchar. */ | |
8616 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
8617 | type = v8hi_ftype_v16qi_v16qi; | |
8618 | ||
8619 | /* vint, vshort, vshort. */ | |
8620 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
8621 | type = v4si_ftype_v8hi_v8hi; | |
8622 | ||
8623 | /* vshort, vint, vint. */ | |
8624 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
8625 | type = v8hi_ftype_v4si_v4si; | |
8626 | ||
8627 | /* vchar, vshort, vshort. */ | |
8628 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
8629 | type = v16qi_ftype_v8hi_v8hi; | |
8630 | ||
8631 | /* vint, vchar, vint. */ | |
8632 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
8633 | type = v4si_ftype_v16qi_v4si; | |
8634 | ||
fa066a23 AH |
8635 | /* vint, vchar, vchar. */ |
8636 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
8637 | type = v4si_ftype_v16qi_v16qi; | |
8638 | ||
0ac081f6 AH |
8639 | /* vint, vshort, vint. */ |
8640 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
8641 | type = v4si_ftype_v8hi_v4si; | |
f676971a | 8642 | |
2212663f DB |
8643 | /* vint, vint, 5 bit literal. */ |
8644 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8645 | type = v4si_ftype_v4si_int; |
f676971a | 8646 | |
2212663f DB |
8647 | /* vshort, vshort, 5 bit literal. */ |
8648 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
b9e4e5d1 | 8649 | type = v8hi_ftype_v8hi_int; |
f676971a | 8650 | |
2212663f DB |
8651 | /* vchar, vchar, 5 bit literal. */ |
8652 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
b9e4e5d1 | 8653 | type = v16qi_ftype_v16qi_int; |
0ac081f6 | 8654 | |
617e0e1d DB |
8655 | /* vfloat, vint, 5 bit literal. */ |
8656 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8657 | type = v4sf_ftype_v4si_int; |
f676971a | 8658 | |
617e0e1d DB |
8659 | /* vint, vfloat, 5 bit literal. */ |
8660 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
b9e4e5d1 | 8661 | type = v4si_ftype_v4sf_int; |
617e0e1d | 8662 | |
a3170dc6 AH |
8663 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
8664 | type = v2si_ftype_int_int; | |
8665 | ||
8666 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
8667 | type = v2si_ftype_v2si_char; | |
8668 | ||
8669 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
8670 | type = v2si_ftype_int_char; | |
8671 | ||
0ac081f6 AH |
8672 | /* int, x, x. */ |
8673 | else if (mode0 == SImode) | |
8674 | { | |
8675 | switch (mode1) | |
8676 | { | |
8677 | case V4SImode: | |
8678 | type = int_ftype_v4si_v4si; | |
8679 | break; | |
8680 | case V4SFmode: | |
8681 | type = int_ftype_v4sf_v4sf; | |
8682 | break; | |
8683 | case V16QImode: | |
8684 | type = int_ftype_v16qi_v16qi; | |
8685 | break; | |
8686 | case V8HImode: | |
8687 | type = int_ftype_v8hi_v8hi; | |
8688 | break; | |
8689 | default: | |
8690 | abort (); | |
8691 | } | |
8692 | } | |
8693 | ||
8694 | else | |
8695 | abort (); | |
8696 | ||
2212663f DB |
8697 | def_builtin (d->mask, d->name, type, d->code); |
8698 | } | |
24408032 | 8699 | |
2212663f DB |
8700 | /* Add the simple unary operators. */ |
8701 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 8702 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
8703 | { |
8704 | enum machine_mode mode0, mode1; | |
8705 | tree type; | |
8706 | ||
0559cc77 | 8707 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f | 8708 | continue; |
f676971a | 8709 | |
2212663f DB |
8710 | mode0 = insn_data[d->icode].operand[0].mode; |
8711 | mode1 = insn_data[d->icode].operand[1].mode; | |
8712 | ||
8713 | if (mode0 == V4SImode && mode1 == QImode) | |
c4ad648e | 8714 | type = v4si_ftype_int; |
2212663f | 8715 | else if (mode0 == V8HImode && mode1 == QImode) |
c4ad648e | 8716 | type = v8hi_ftype_int; |
2212663f | 8717 | else if (mode0 == V16QImode && mode1 == QImode) |
c4ad648e | 8718 | type = v16qi_ftype_int; |
617e0e1d DB |
8719 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
8720 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
8721 | else if (mode0 == V8HImode && mode1 == V16QImode) |
8722 | type = v8hi_ftype_v16qi; | |
8723 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
8724 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
8725 | else if (mode0 == V2SImode && mode1 == V2SImode) |
8726 | type = v2si_ftype_v2si; | |
8727 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
8728 | type = v2sf_ftype_v2sf; | |
8729 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
8730 | type = v2sf_ftype_v2si; | |
8731 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
8732 | type = v2si_ftype_v2sf; | |
8733 | else if (mode0 == V2SImode && mode1 == QImode) | |
8734 | type = v2si_ftype_char; | |
2212663f DB |
8735 | else |
8736 | abort (); | |
8737 | ||
0ac081f6 AH |
8738 | def_builtin (d->mask, d->name, type, d->code); |
8739 | } | |
8740 | } | |
8741 | ||
c15c90bb ZW |
8742 | static void |
8743 | rs6000_init_libfuncs (void) | |
8744 | { | |
8745 | if (!TARGET_HARD_FLOAT) | |
8746 | return; | |
8747 | ||
c9034561 | 8748 | if (DEFAULT_ABI != ABI_V4) |
c15c90bb | 8749 | { |
c9034561 | 8750 | if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC) |
c15c90bb | 8751 | { |
c9034561 | 8752 | /* AIX library routines for float->int conversion. */ |
85363ca0 ZW |
8753 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); |
8754 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
4274207b DE |
8755 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); |
8756 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
c15c90bb ZW |
8757 | } |
8758 | ||
c9034561 | 8759 | /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8760 | set_optab_libfunc (add_optab, TFmode, "_xlqadd"); |
8761 | set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); | |
8762 | set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); | |
8763 | set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); | |
8764 | } | |
c9034561 | 8765 | else |
c15c90bb | 8766 | { |
c9034561 | 8767 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8768 | |
8769 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
8770 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
8771 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
8772 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
8773 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
8774 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
8775 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
8776 | ||
c9034561 ZW |
8777 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
8778 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
8779 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
8780 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
8781 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
8782 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
8783 | ||
85363ca0 ZW |
8784 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
8785 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
8786 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
8787 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
8788 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
8789 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
8790 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
c15c90bb ZW |
8791 | } |
8792 | } | |
fba73eb1 DE |
8793 | |
8794 | \f | |
8795 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
8796 | if we should let the compiler generate normal code. | |
8797 | ||
8798 | operands[0] is the destination | |
8799 | operands[1] is the length | |
8800 | operands[2] is the alignment */ | |
8801 | ||
8802 | int | |
8803 | expand_block_clear (rtx operands[]) | |
8804 | { | |
8805 | rtx orig_dest = operands[0]; | |
8806 | rtx bytes_rtx = operands[1]; | |
8807 | rtx align_rtx = operands[2]; | |
5514620a GK |
8808 | bool constp = (GET_CODE (bytes_rtx) == CONST_INT); |
8809 | HOST_WIDE_INT align; | |
8810 | HOST_WIDE_INT bytes; | |
fba73eb1 DE |
8811 | int offset; |
8812 | int clear_bytes; | |
5514620a | 8813 | int clear_step; |
fba73eb1 DE |
8814 | |
8815 | /* If this is not a fixed size move, just call memcpy */ | |
8816 | if (! constp) | |
8817 | return 0; | |
8818 | ||
8819 | /* If this is not a fixed size alignment, abort */ | |
8820 | if (GET_CODE (align_rtx) != CONST_INT) | |
8821 | abort (); | |
8822 | align = INTVAL (align_rtx) * BITS_PER_UNIT; | |
8823 | ||
8824 | /* Anything to clear? */ | |
8825 | bytes = INTVAL (bytes_rtx); | |
8826 | if (bytes <= 0) | |
8827 | return 1; | |
8828 | ||
5514620a GK |
8829 | /* Use the builtin memset after a point, to avoid huge code bloat. |
8830 | When optimize_size, avoid any significant code bloat; calling | |
8831 | memset is about 4 instructions, so allow for one instruction to | |
8832 | load zero and three to do clearing. */ | |
8833 | if (TARGET_ALTIVEC && align >= 128) | |
8834 | clear_step = 16; | |
8835 | else if (TARGET_POWERPC64 && align >= 32) | |
8836 | clear_step = 8; | |
8837 | else | |
8838 | clear_step = 4; | |
fba73eb1 | 8839 | |
5514620a GK |
8840 | if (optimize_size && bytes > 3 * clear_step) |
8841 | return 0; | |
8842 | if (! optimize_size && bytes > 8 * clear_step) | |
fba73eb1 DE |
8843 | return 0; |
8844 | ||
8845 | for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) | |
8846 | { | |
fba73eb1 DE |
8847 | enum machine_mode mode = BLKmode; |
8848 | rtx dest; | |
f676971a | 8849 | |
5514620a GK |
8850 | if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) |
8851 | { | |
8852 | clear_bytes = 16; | |
8853 | mode = V4SImode; | |
8854 | } | |
8855 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8856 | /* 64-bit loads and stores require word-aligned | |
8857 | displacements. */ | |
8858 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) | |
fba73eb1 DE |
8859 | { |
8860 | clear_bytes = 8; | |
8861 | mode = DImode; | |
fba73eb1 | 8862 | } |
5514620a | 8863 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8864 | { /* move 4 bytes */ |
8865 | clear_bytes = 4; | |
8866 | mode = SImode; | |
fba73eb1 | 8867 | } |
5514620a | 8868 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8869 | { /* move 2 bytes */ |
8870 | clear_bytes = 2; | |
8871 | mode = HImode; | |
fba73eb1 DE |
8872 | } |
8873 | else /* move 1 byte at a time */ | |
8874 | { | |
8875 | clear_bytes = 1; | |
8876 | mode = QImode; | |
fba73eb1 | 8877 | } |
f676971a | 8878 | |
fba73eb1 | 8879 | dest = adjust_address (orig_dest, mode, offset); |
f676971a | 8880 | |
5514620a | 8881 | emit_move_insn (dest, CONST0_RTX (mode)); |
fba73eb1 DE |
8882 | } |
8883 | ||
8884 | return 1; | |
8885 | } | |
8886 | ||
35aff10b | 8887 | \f |
7e69e155 MM |
8888 | /* Expand a block move operation, and return 1 if successful. Return 0 |
8889 | if we should let the compiler generate normal code. | |
8890 | ||
8891 | operands[0] is the destination | |
8892 | operands[1] is the source | |
8893 | operands[2] is the length | |
8894 | operands[3] is the alignment */ | |
8895 | ||
3933e0e1 MM |
8896 | #define MAX_MOVE_REG 4 |
8897 | ||
7e69e155 | 8898 | int |
a2369ed3 | 8899 | expand_block_move (rtx operands[]) |
7e69e155 | 8900 | { |
b6c9286a MM |
8901 | rtx orig_dest = operands[0]; |
8902 | rtx orig_src = operands[1]; | |
7e69e155 | 8903 | rtx bytes_rtx = operands[2]; |
7e69e155 | 8904 | rtx align_rtx = operands[3]; |
3933e0e1 | 8905 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 8906 | int align; |
3933e0e1 MM |
8907 | int bytes; |
8908 | int offset; | |
7e69e155 | 8909 | int move_bytes; |
cabfd258 GK |
8910 | rtx stores[MAX_MOVE_REG]; |
8911 | int num_reg = 0; | |
7e69e155 | 8912 | |
3933e0e1 | 8913 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 8914 | if (! constp) |
3933e0e1 MM |
8915 | return 0; |
8916 | ||
5ee95df6 FS |
8917 | /* If this is not a fixed size alignment, abort */ |
8918 | if (GET_CODE (align_rtx) != CONST_INT) | |
8919 | abort (); | |
fba73eb1 | 8920 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
5ee95df6 | 8921 | |
7e69e155 | 8922 | /* Anything to move? */ |
3933e0e1 MM |
8923 | bytes = INTVAL (bytes_rtx); |
8924 | if (bytes <= 0) | |
7e69e155 MM |
8925 | return 1; |
8926 | ||
ea9982a8 | 8927 | /* store_one_arg depends on expand_block_move to handle at least the size of |
f676971a | 8928 | reg_parm_stack_space. */ |
ea9982a8 | 8929 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
8930 | return 0; |
8931 | ||
cabfd258 | 8932 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 8933 | { |
cabfd258 | 8934 | union { |
70128ad9 | 8935 | rtx (*movmemsi) (rtx, rtx, rtx, rtx); |
a2369ed3 | 8936 | rtx (*mov) (rtx, rtx); |
cabfd258 GK |
8937 | } gen_func; |
8938 | enum machine_mode mode = BLKmode; | |
8939 | rtx src, dest; | |
f676971a | 8940 | |
5514620a GK |
8941 | /* Altivec first, since it will be faster than a string move |
8942 | when it applies, and usually not significantly larger. */ | |
8943 | if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) | |
8944 | { | |
8945 | move_bytes = 16; | |
8946 | mode = V4SImode; | |
8947 | gen_func.mov = gen_movv4si; | |
8948 | } | |
8949 | else if (TARGET_STRING | |
cabfd258 GK |
8950 | && bytes > 24 /* move up to 32 bytes at a time */ |
8951 | && ! fixed_regs[5] | |
8952 | && ! fixed_regs[6] | |
8953 | && ! fixed_regs[7] | |
8954 | && ! fixed_regs[8] | |
8955 | && ! fixed_regs[9] | |
8956 | && ! fixed_regs[10] | |
8957 | && ! fixed_regs[11] | |
8958 | && ! fixed_regs[12]) | |
7e69e155 | 8959 | { |
cabfd258 | 8960 | move_bytes = (bytes > 32) ? 32 : bytes; |
70128ad9 | 8961 | gen_func.movmemsi = gen_movmemsi_8reg; |
cabfd258 GK |
8962 | } |
8963 | else if (TARGET_STRING | |
8964 | && bytes > 16 /* move up to 24 bytes at a time */ | |
8965 | && ! fixed_regs[5] | |
8966 | && ! fixed_regs[6] | |
8967 | && ! fixed_regs[7] | |
8968 | && ! fixed_regs[8] | |
8969 | && ! fixed_regs[9] | |
8970 | && ! fixed_regs[10]) | |
8971 | { | |
8972 | move_bytes = (bytes > 24) ? 24 : bytes; | |
70128ad9 | 8973 | gen_func.movmemsi = gen_movmemsi_6reg; |
cabfd258 GK |
8974 | } |
8975 | else if (TARGET_STRING | |
8976 | && bytes > 8 /* move up to 16 bytes at a time */ | |
8977 | && ! fixed_regs[5] | |
8978 | && ! fixed_regs[6] | |
8979 | && ! fixed_regs[7] | |
8980 | && ! fixed_regs[8]) | |
8981 | { | |
8982 | move_bytes = (bytes > 16) ? 16 : bytes; | |
70128ad9 | 8983 | gen_func.movmemsi = gen_movmemsi_4reg; |
cabfd258 GK |
8984 | } |
8985 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8986 | /* 64-bit loads and stores require word-aligned | |
8987 | displacements. */ | |
fba73eb1 | 8988 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) |
cabfd258 GK |
8989 | { |
8990 | move_bytes = 8; | |
8991 | mode = DImode; | |
8992 | gen_func.mov = gen_movdi; | |
8993 | } | |
8994 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
8995 | { /* move up to 8 bytes at a time */ | |
8996 | move_bytes = (bytes > 8) ? 8 : bytes; | |
70128ad9 | 8997 | gen_func.movmemsi = gen_movmemsi_2reg; |
cabfd258 | 8998 | } |
cd7d9ca4 | 8999 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
9000 | { /* move 4 bytes */ |
9001 | move_bytes = 4; | |
9002 | mode = SImode; | |
9003 | gen_func.mov = gen_movsi; | |
9004 | } | |
cd7d9ca4 | 9005 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
9006 | { /* move 2 bytes */ |
9007 | move_bytes = 2; | |
9008 | mode = HImode; | |
9009 | gen_func.mov = gen_movhi; | |
9010 | } | |
9011 | else if (TARGET_STRING && bytes > 1) | |
9012 | { /* move up to 4 bytes at a time */ | |
9013 | move_bytes = (bytes > 4) ? 4 : bytes; | |
70128ad9 | 9014 | gen_func.movmemsi = gen_movmemsi_1reg; |
cabfd258 GK |
9015 | } |
9016 | else /* move 1 byte at a time */ | |
9017 | { | |
9018 | move_bytes = 1; | |
9019 | mode = QImode; | |
9020 | gen_func.mov = gen_movqi; | |
9021 | } | |
f676971a | 9022 | |
cabfd258 GK |
9023 | src = adjust_address (orig_src, mode, offset); |
9024 | dest = adjust_address (orig_dest, mode, offset); | |
f676971a EC |
9025 | |
9026 | if (mode != BLKmode) | |
cabfd258 GK |
9027 | { |
9028 | rtx tmp_reg = gen_reg_rtx (mode); | |
f676971a | 9029 | |
cabfd258 GK |
9030 | emit_insn ((*gen_func.mov) (tmp_reg, src)); |
9031 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 9032 | } |
3933e0e1 | 9033 | |
cabfd258 GK |
9034 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
9035 | { | |
9036 | int i; | |
9037 | for (i = 0; i < num_reg; i++) | |
9038 | emit_insn (stores[i]); | |
9039 | num_reg = 0; | |
9040 | } | |
35aff10b | 9041 | |
cabfd258 | 9042 | if (mode == BLKmode) |
7e69e155 | 9043 | { |
70128ad9 | 9044 | /* Move the address into scratch registers. The movmemsi |
cabfd258 GK |
9045 | patterns require zero offset. */ |
9046 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 9047 | { |
cabfd258 GK |
9048 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
9049 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 9050 | } |
cabfd258 | 9051 | set_mem_size (src, GEN_INT (move_bytes)); |
f676971a | 9052 | |
cabfd258 | 9053 | if (!REG_P (XEXP (dest, 0))) |
3933e0e1 | 9054 | { |
cabfd258 GK |
9055 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
9056 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 9057 | } |
cabfd258 | 9058 | set_mem_size (dest, GEN_INT (move_bytes)); |
f676971a | 9059 | |
70128ad9 | 9060 | emit_insn ((*gen_func.movmemsi) (dest, src, |
cabfd258 GK |
9061 | GEN_INT (move_bytes & 31), |
9062 | align_rtx)); | |
7e69e155 | 9063 | } |
7e69e155 MM |
9064 | } |
9065 | ||
9066 | return 1; | |
9067 | } | |
9068 | ||
d62294f5 FJ |
9069 | \f |
9070 | /* Return 1 if OP is suitable for a save_world call in prologue. It is | |
9071 | known to be a PARALLEL. */ | |
9072 | int | |
9073 | save_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
9074 | { | |
9075 | int index; | |
9076 | int i; | |
9077 | rtx elt; | |
9078 | int count = XVECLEN (op, 0); | |
9079 | ||
9080 | if (count != 55) | |
9081 | return 0; | |
9082 | ||
9083 | index = 0; | |
9084 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
9085 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
9086 | return 0; | |
9087 | ||
9088 | for (i=1; i <= 18; i++) | |
9089 | { | |
9090 | elt = XVECEXP (op, 0, index++); | |
9091 | if (GET_CODE (elt) != SET | |
9092 | || GET_CODE (SET_DEST (elt)) != MEM | |
9093 | || ! memory_operand (SET_DEST (elt), DFmode) | |
9094 | || GET_CODE (SET_SRC (elt)) != REG | |
9095 | || GET_MODE (SET_SRC (elt)) != DFmode) | |
9096 | return 0; | |
9097 | } | |
9098 | ||
9099 | for (i=1; i <= 12; i++) | |
9100 | { | |
9101 | elt = XVECEXP (op, 0, index++); | |
9102 | if (GET_CODE (elt) != SET | |
9103 | || GET_CODE (SET_DEST (elt)) != MEM | |
9104 | || GET_CODE (SET_SRC (elt)) != REG | |
9105 | || GET_MODE (SET_SRC (elt)) != V4SImode) | |
9106 | return 0; | |
9107 | } | |
9108 | ||
9109 | for (i=1; i <= 19; i++) | |
9110 | { | |
9111 | elt = XVECEXP (op, 0, index++); | |
9112 | if (GET_CODE (elt) != SET | |
9113 | || GET_CODE (SET_DEST (elt)) != MEM | |
9114 | || ! memory_operand (SET_DEST (elt), Pmode) | |
9115 | || GET_CODE (SET_SRC (elt)) != REG | |
9116 | || GET_MODE (SET_SRC (elt)) != Pmode) | |
9117 | return 0; | |
9118 | } | |
9119 | ||
9120 | elt = XVECEXP (op, 0, index++); | |
9121 | if (GET_CODE (elt) != SET | |
9122 | || GET_CODE (SET_DEST (elt)) != MEM | |
9123 | || ! memory_operand (SET_DEST (elt), Pmode) | |
9124 | || GET_CODE (SET_SRC (elt)) != REG | |
9125 | || REGNO (SET_SRC (elt)) != CR2_REGNO | |
9126 | || GET_MODE (SET_SRC (elt)) != Pmode) | |
9127 | return 0; | |
9128 | ||
9129 | if (GET_CODE (XVECEXP (op, 0, index++)) != USE | |
9130 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
9131 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) | |
9132 | return 0; | |
9133 | return 1; | |
9134 | } | |
9135 | ||
9136 | /* Return 1 if OP is suitable for a save_world call in prologue. It is | |
9137 | known to be a PARALLEL. */ | |
9138 | int | |
9139 | restore_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
9140 | { | |
9141 | int index; | |
9142 | int i; | |
9143 | rtx elt; | |
9144 | int count = XVECLEN (op, 0); | |
9145 | ||
9146 | if (count != 59) | |
9147 | return 0; | |
9148 | ||
9149 | index = 0; | |
9150 | if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN | |
9151 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
9152 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
9153 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) | |
9154 | return 0; | |
9155 | ||
9156 | elt = XVECEXP (op, 0, index++); | |
9157 | if (GET_CODE (elt) != SET | |
9158 | || GET_CODE (SET_SRC (elt)) != MEM | |
9159 | || ! memory_operand (SET_SRC (elt), Pmode) | |
9160 | || GET_CODE (SET_DEST (elt)) != REG | |
9161 | || REGNO (SET_DEST (elt)) != CR2_REGNO | |
9162 | || GET_MODE (SET_DEST (elt)) != Pmode) | |
9163 | return 0; | |
9164 | ||
9165 | for (i=1; i <= 19; i++) | |
9166 | { | |
9167 | elt = XVECEXP (op, 0, index++); | |
9168 | if (GET_CODE (elt) != SET | |
9169 | || GET_CODE (SET_SRC (elt)) != MEM | |
9170 | || ! memory_operand (SET_SRC (elt), Pmode) | |
9171 | || GET_CODE (SET_DEST (elt)) != REG | |
9172 | || GET_MODE (SET_DEST (elt)) != Pmode) | |
9173 | return 0; | |
9174 | } | |
9175 | ||
9176 | for (i=1; i <= 12; i++) | |
9177 | { | |
9178 | elt = XVECEXP (op, 0, index++); | |
9179 | if (GET_CODE (elt) != SET | |
9180 | || GET_CODE (SET_SRC (elt)) != MEM | |
9181 | || GET_CODE (SET_DEST (elt)) != REG | |
9182 | || GET_MODE (SET_DEST (elt)) != V4SImode) | |
9183 | return 0; | |
9184 | } | |
9185 | ||
9186 | for (i=1; i <= 18; i++) | |
9187 | { | |
9188 | elt = XVECEXP (op, 0, index++); | |
9189 | if (GET_CODE (elt) != SET | |
9190 | || GET_CODE (SET_SRC (elt)) != MEM | |
9191 | || ! memory_operand (SET_SRC (elt), DFmode) | |
9192 | || GET_CODE (SET_DEST (elt)) != REG | |
9193 | || GET_MODE (SET_DEST (elt)) != DFmode) | |
9194 | return 0; | |
9195 | } | |
9196 | ||
9197 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
9198 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
9199 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
9200 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
9201 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
9202 | return 0; | |
9203 | return 1; | |
9204 | } | |
9205 | ||
9878760c RK |
9206 | \f |
9207 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
9208 | PARALLEL and the first section will be tested. */ | |
9209 | ||
9210 | int | |
a2369ed3 | 9211 | load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
9212 | { |
9213 | int count = XVECLEN (op, 0); | |
e2c953b6 | 9214 | unsigned int dest_regno; |
9878760c RK |
9215 | rtx src_addr; |
9216 | int i; | |
9217 | ||
9218 | /* Perform a quick check so we don't blow up below. */ | |
9219 | if (count <= 1 | |
9220 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9221 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
9222 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
9223 | return 0; | |
9224 | ||
9225 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
9226 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
9227 | ||
9228 | for (i = 1; i < count; i++) | |
9229 | { | |
9230 | rtx elt = XVECEXP (op, 0, i); | |
9231 | ||
9232 | if (GET_CODE (elt) != SET | |
9233 | || GET_CODE (SET_DEST (elt)) != REG | |
9234 | || GET_MODE (SET_DEST (elt)) != SImode | |
9235 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
9236 | || GET_CODE (SET_SRC (elt)) != MEM | |
9237 | || GET_MODE (SET_SRC (elt)) != SImode | |
9238 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
9239 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
9240 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
9241 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
9242 | return 0; | |
9243 | } | |
9244 | ||
9245 | return 1; | |
9246 | } | |
9247 | ||
9248 | /* Similar, but tests for store multiple. Here, the second vector element | |
9249 | is a CLOBBER. It will be tested later. */ | |
9250 | ||
9251 | int | |
a2369ed3 | 9252 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
9253 | { |
9254 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 9255 | unsigned int src_regno; |
9878760c RK |
9256 | rtx dest_addr; |
9257 | int i; | |
9258 | ||
9259 | /* Perform a quick check so we don't blow up below. */ | |
9260 | if (count <= 1 | |
9261 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9262 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
9263 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
9264 | return 0; | |
9265 | ||
9266 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
9267 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
9268 | ||
9269 | for (i = 1; i < count; i++) | |
9270 | { | |
9271 | rtx elt = XVECEXP (op, 0, i + 1); | |
9272 | ||
9273 | if (GET_CODE (elt) != SET | |
9274 | || GET_CODE (SET_SRC (elt)) != REG | |
9275 | || GET_MODE (SET_SRC (elt)) != SImode | |
9276 | || REGNO (SET_SRC (elt)) != src_regno + i | |
9277 | || GET_CODE (SET_DEST (elt)) != MEM | |
9278 | || GET_MODE (SET_DEST (elt)) != SImode | |
9279 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
9280 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
9281 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
9282 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
9283 | return 0; | |
9284 | } | |
9285 | ||
9286 | return 1; | |
9287 | } | |
9ebbca7d | 9288 | |
9caa3eb2 DE |
9289 | /* Return a string to perform a load_multiple operation. |
9290 | operands[0] is the vector. | |
9291 | operands[1] is the source address. | |
9292 | operands[2] is the first destination register. */ | |
9293 | ||
9294 | const char * | |
a2369ed3 | 9295 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
9296 | { |
9297 | /* We have to handle the case where the pseudo used to contain the address | |
9298 | is assigned to one of the output registers. */ | |
9299 | int i, j; | |
9300 | int words = XVECLEN (operands[0], 0); | |
9301 | rtx xop[10]; | |
9302 | ||
9303 | if (XVECLEN (operands[0], 0) == 1) | |
9304 | return "{l|lwz} %2,0(%1)"; | |
9305 | ||
9306 | for (i = 0; i < words; i++) | |
9307 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
9308 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
9309 | { | |
9310 | if (i == words-1) | |
9311 | { | |
9312 | xop[0] = GEN_INT (4 * (words-1)); | |
9313 | xop[1] = operands[1]; | |
9314 | xop[2] = operands[2]; | |
9315 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
9316 | return ""; | |
9317 | } | |
9318 | else if (i == 0) | |
9319 | { | |
9320 | xop[0] = GEN_INT (4 * (words-1)); | |
9321 | xop[1] = operands[1]; | |
9322 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
9323 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
9324 | return ""; | |
9325 | } | |
9326 | else | |
9327 | { | |
9328 | for (j = 0; j < words; j++) | |
9329 | if (j != i) | |
9330 | { | |
9331 | xop[0] = GEN_INT (j * 4); | |
9332 | xop[1] = operands[1]; | |
9333 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
9334 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
9335 | } | |
9336 | xop[0] = GEN_INT (i * 4); | |
9337 | xop[1] = operands[1]; | |
9338 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
9339 | return ""; | |
9340 | } | |
9341 | } | |
9342 | ||
9343 | return "{lsi|lswi} %2,%1,%N0"; | |
9344 | } | |
9345 | ||
00b960c7 AH |
9346 | /* Return 1 for a parallel vrsave operation. */ |
9347 | ||
9348 | int | |
a2369ed3 | 9349 | vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
00b960c7 AH |
9350 | { |
9351 | int count = XVECLEN (op, 0); | |
9352 | unsigned int dest_regno, src_regno; | |
9353 | int i; | |
9354 | ||
9355 | if (count <= 1 | |
9356 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9357 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 9358 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
9359 | return 0; |
9360 | ||
9361 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
9362 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
9363 | ||
9364 | if (dest_regno != VRSAVE_REGNO | |
9365 | && src_regno != VRSAVE_REGNO) | |
9366 | return 0; | |
9367 | ||
9368 | for (i = 1; i < count; i++) | |
9369 | { | |
9370 | rtx elt = XVECEXP (op, 0, i); | |
9371 | ||
9aa86737 AH |
9372 | if (GET_CODE (elt) != CLOBBER |
9373 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
9374 | return 0; |
9375 | } | |
9376 | ||
9377 | return 1; | |
9378 | } | |
9379 | ||
2c4a9cff DE |
9380 | /* Return 1 for an PARALLEL suitable for mfcr. */ |
9381 | ||
9382 | int | |
a2369ed3 | 9383 | mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2c4a9cff DE |
9384 | { |
9385 | int count = XVECLEN (op, 0); | |
9386 | int i; | |
9387 | ||
9388 | /* Perform a quick check so we don't blow up below. */ | |
9389 | if (count < 1 | |
9390 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9391 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
9392 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9393 | return 0; | |
9394 | ||
9395 | for (i = 0; i < count; i++) | |
9396 | { | |
9397 | rtx exp = XVECEXP (op, 0, i); | |
9398 | rtx unspec; | |
9399 | int maskval; | |
9400 | rtx src_reg; | |
9401 | ||
9402 | src_reg = XVECEXP (SET_SRC (exp), 0, 0); | |
9403 | ||
9404 | if (GET_CODE (src_reg) != REG | |
9405 | || GET_MODE (src_reg) != CCmode | |
9406 | || ! CR_REGNO_P (REGNO (src_reg))) | |
9407 | return 0; | |
9408 | ||
9409 | if (GET_CODE (exp) != SET | |
9410 | || GET_CODE (SET_DEST (exp)) != REG | |
9411 | || GET_MODE (SET_DEST (exp)) != SImode | |
9412 | || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) | |
9413 | return 0; | |
9414 | unspec = SET_SRC (exp); | |
9415 | maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); | |
9416 | ||
9417 | if (GET_CODE (unspec) != UNSPEC | |
9418 | || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR | |
9419 | || XVECLEN (unspec, 0) != 2 | |
9420 | || XVECEXP (unspec, 0, 0) != src_reg | |
9421 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
9422 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
9423 | return 0; | |
9424 | } | |
9425 | return 1; | |
9426 | } | |
9427 | ||
a4f6c312 | 9428 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
9429 | |
9430 | int | |
a2369ed3 | 9431 | mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
9432 | { |
9433 | int count = XVECLEN (op, 0); | |
9434 | int i; | |
9ebbca7d GK |
9435 | rtx src_reg; |
9436 | ||
9437 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
9438 | if (count < 1 |
9439 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9440 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
9441 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 9442 | return 0; |
e35b9579 | 9443 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
f676971a | 9444 | |
9ebbca7d GK |
9445 | if (GET_CODE (src_reg) != REG |
9446 | || GET_MODE (src_reg) != SImode | |
9447 | || ! INT_REGNO_P (REGNO (src_reg))) | |
9448 | return 0; | |
9449 | ||
e35b9579 | 9450 | for (i = 0; i < count; i++) |
9ebbca7d GK |
9451 | { |
9452 | rtx exp = XVECEXP (op, 0, i); | |
9453 | rtx unspec; | |
9454 | int maskval; | |
f676971a | 9455 | |
9ebbca7d GK |
9456 | if (GET_CODE (exp) != SET |
9457 | || GET_CODE (SET_DEST (exp)) != REG | |
9458 | || GET_MODE (SET_DEST (exp)) != CCmode | |
9459 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
9460 | return 0; | |
9461 | unspec = SET_SRC (exp); | |
9462 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
f676971a | 9463 | |
9ebbca7d | 9464 | if (GET_CODE (unspec) != UNSPEC |
615158e2 | 9465 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR |
9ebbca7d GK |
9466 | || XVECLEN (unspec, 0) != 2 |
9467 | || XVECEXP (unspec, 0, 0) != src_reg | |
9468 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
9469 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
9470 | return 0; | |
9471 | } | |
e35b9579 | 9472 | return 1; |
9ebbca7d GK |
9473 | } |
9474 | ||
a4f6c312 | 9475 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
9476 | |
9477 | int | |
a2369ed3 | 9478 | lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
9479 | { |
9480 | int count = XVECLEN (op, 0); | |
e2c953b6 | 9481 | unsigned int dest_regno; |
9ebbca7d | 9482 | rtx src_addr; |
e2c953b6 | 9483 | unsigned int base_regno; |
9ebbca7d GK |
9484 | HOST_WIDE_INT offset; |
9485 | int i; | |
9486 | ||
9487 | /* Perform a quick check so we don't blow up below. */ | |
9488 | if (count <= 1 | |
9489 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9490 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
9491 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
9492 | return 0; | |
9493 | ||
9494 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
9495 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
9496 | ||
9497 | if (dest_regno > 31 | |
e2c953b6 | 9498 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
9499 | return 0; |
9500 | ||
4d588c14 | 9501 | if (legitimate_indirect_address_p (src_addr, 0)) |
9ebbca7d GK |
9502 | { |
9503 | offset = 0; | |
9504 | base_regno = REGNO (src_addr); | |
9505 | if (base_regno == 0) | |
9506 | return 0; | |
9507 | } | |
76d2b81d | 9508 | else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0)) |
9ebbca7d GK |
9509 | { |
9510 | offset = INTVAL (XEXP (src_addr, 1)); | |
9511 | base_regno = REGNO (XEXP (src_addr, 0)); | |
9512 | } | |
9513 | else | |
9514 | return 0; | |
9515 | ||
9516 | for (i = 0; i < count; i++) | |
9517 | { | |
9518 | rtx elt = XVECEXP (op, 0, i); | |
9519 | rtx newaddr; | |
9520 | rtx addr_reg; | |
9521 | HOST_WIDE_INT newoffset; | |
9522 | ||
9523 | if (GET_CODE (elt) != SET | |
9524 | || GET_CODE (SET_DEST (elt)) != REG | |
9525 | || GET_MODE (SET_DEST (elt)) != SImode | |
9526 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
9527 | || GET_CODE (SET_SRC (elt)) != MEM | |
9528 | || GET_MODE (SET_SRC (elt)) != SImode) | |
9529 | return 0; | |
9530 | newaddr = XEXP (SET_SRC (elt), 0); | |
4d588c14 | 9531 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
9532 | { |
9533 | newoffset = 0; | |
9534 | addr_reg = newaddr; | |
9535 | } | |
76d2b81d | 9536 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
9537 | { |
9538 | addr_reg = XEXP (newaddr, 0); | |
9539 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
9540 | } | |
9541 | else | |
9542 | return 0; | |
9543 | if (REGNO (addr_reg) != base_regno | |
9544 | || newoffset != offset + 4 * i) | |
9545 | return 0; | |
9546 | } | |
9547 | ||
9548 | return 1; | |
9549 | } | |
9550 | ||
a4f6c312 | 9551 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
9552 | |
9553 | int | |
a2369ed3 | 9554 | stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
9555 | { |
9556 | int count = XVECLEN (op, 0); | |
e2c953b6 | 9557 | unsigned int src_regno; |
9ebbca7d | 9558 | rtx dest_addr; |
e2c953b6 | 9559 | unsigned int base_regno; |
9ebbca7d GK |
9560 | HOST_WIDE_INT offset; |
9561 | int i; | |
9562 | ||
9563 | /* Perform a quick check so we don't blow up below. */ | |
9564 | if (count <= 1 | |
9565 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9566 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
9567 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
9568 | return 0; | |
9569 | ||
9570 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
9571 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
9572 | ||
9573 | if (src_regno > 31 | |
e2c953b6 | 9574 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
9575 | return 0; |
9576 | ||
4d588c14 | 9577 | if (legitimate_indirect_address_p (dest_addr, 0)) |
9ebbca7d GK |
9578 | { |
9579 | offset = 0; | |
9580 | base_regno = REGNO (dest_addr); | |
9581 | if (base_regno == 0) | |
9582 | return 0; | |
9583 | } | |
76d2b81d | 9584 | else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0)) |
9ebbca7d GK |
9585 | { |
9586 | offset = INTVAL (XEXP (dest_addr, 1)); | |
9587 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
9588 | } | |
9589 | else | |
9590 | return 0; | |
9591 | ||
9592 | for (i = 0; i < count; i++) | |
9593 | { | |
9594 | rtx elt = XVECEXP (op, 0, i); | |
9595 | rtx newaddr; | |
9596 | rtx addr_reg; | |
9597 | HOST_WIDE_INT newoffset; | |
9598 | ||
9599 | if (GET_CODE (elt) != SET | |
9600 | || GET_CODE (SET_SRC (elt)) != REG | |
9601 | || GET_MODE (SET_SRC (elt)) != SImode | |
9602 | || REGNO (SET_SRC (elt)) != src_regno + i | |
9603 | || GET_CODE (SET_DEST (elt)) != MEM | |
9604 | || GET_MODE (SET_DEST (elt)) != SImode) | |
9605 | return 0; | |
9606 | newaddr = XEXP (SET_DEST (elt), 0); | |
4d588c14 | 9607 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
9608 | { |
9609 | newoffset = 0; | |
9610 | addr_reg = newaddr; | |
9611 | } | |
76d2b81d | 9612 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
9613 | { |
9614 | addr_reg = XEXP (newaddr, 0); | |
9615 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
9616 | } | |
9617 | else | |
9618 | return 0; | |
9619 | if (REGNO (addr_reg) != base_regno | |
9620 | || newoffset != offset + 4 * i) | |
9621 | return 0; | |
9622 | } | |
9623 | ||
9624 | return 1; | |
9625 | } | |
9878760c | 9626 | \f |
a4f6c312 SS |
9627 | /* A validation routine: say whether CODE, a condition code, and MODE |
9628 | match. The other alternatives either don't make sense or should | |
9629 | never be generated. */ | |
39a10a29 | 9630 | |
39a10a29 | 9631 | static void |
a2369ed3 | 9632 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 | 9633 | { |
ec8e098d PB |
9634 | if ((GET_RTX_CLASS (code) != RTX_COMPARE |
9635 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE) | |
39a10a29 GK |
9636 | || GET_MODE_CLASS (mode) != MODE_CC) |
9637 | abort (); | |
9638 | ||
9639 | /* These don't make sense. */ | |
9640 | if ((code == GT || code == LT || code == GE || code == LE) | |
9641 | && mode == CCUNSmode) | |
9642 | abort (); | |
9643 | ||
9644 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
9645 | && mode != CCUNSmode) | |
9646 | abort (); | |
9647 | ||
9648 | if (mode != CCFPmode | |
9649 | && (code == ORDERED || code == UNORDERED | |
9650 | || code == UNEQ || code == LTGT | |
9651 | || code == UNGT || code == UNLT | |
9652 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 9653 | abort (); |
f676971a EC |
9654 | |
9655 | /* These should never be generated except for | |
bc9ec0e0 | 9656 | flag_finite_math_only. */ |
39a10a29 | 9657 | if (mode == CCFPmode |
ad72b533 | 9658 | && ! flag_finite_math_only |
39a10a29 GK |
9659 | && (code == LE || code == GE |
9660 | || code == UNEQ || code == LTGT | |
9661 | || code == UNGT || code == UNLT)) | |
9662 | abort (); | |
9663 | ||
9664 | /* These are invalid; the information is not there. */ | |
f676971a | 9665 | if (mode == CCEQmode |
39a10a29 GK |
9666 | && code != EQ && code != NE) |
9667 | abort (); | |
9668 | } | |
9669 | ||
9878760c RK |
9670 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
9671 | We only check the opcode against the mode of the CC value here. */ | |
9672 | ||
9673 | int | |
a2369ed3 | 9674 | branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
9675 | { |
9676 | enum rtx_code code = GET_CODE (op); | |
9677 | enum machine_mode cc_mode; | |
9678 | ||
ec8e098d | 9679 | if (!COMPARISON_P (op)) |
9878760c RK |
9680 | return 0; |
9681 | ||
9682 | cc_mode = GET_MODE (XEXP (op, 0)); | |
9683 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
9684 | return 0; | |
9685 | ||
39a10a29 | 9686 | validate_condition_mode (code, cc_mode); |
9878760c | 9687 | |
39a10a29 GK |
9688 | return 1; |
9689 | } | |
9690 | ||
9691 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
9692 | insn and which is true if the corresponding bit in the CC register | |
9693 | is set. */ | |
9694 | ||
9695 | int | |
a2369ed3 | 9696 | branch_positive_comparison_operator (rtx op, enum machine_mode mode) |
39a10a29 GK |
9697 | { |
9698 | enum rtx_code code; | |
9699 | ||
8daf2e65 | 9700 | if (! branch_comparison_operator (op, mode)) |
9878760c RK |
9701 | return 0; |
9702 | ||
39a10a29 GK |
9703 | code = GET_CODE (op); |
9704 | return (code == EQ || code == LT || code == GT | |
9705 | || code == LTU || code == GTU | |
9706 | || code == UNORDERED); | |
9878760c RK |
9707 | } |
9708 | ||
b7053a3f GK |
9709 | /* Return 1 if OP is a comparison operation that is valid for an scc |
9710 | insn: it must be a positive comparison. */ | |
9878760c RK |
9711 | |
9712 | int | |
a2369ed3 | 9713 | scc_comparison_operator (rtx op, enum machine_mode mode) |
9878760c | 9714 | { |
b7053a3f | 9715 | return branch_positive_comparison_operator (op, mode); |
9878760c | 9716 | } |
e0cd0770 JC |
9717 | |
9718 | int | |
a2369ed3 | 9719 | trap_comparison_operator (rtx op, enum machine_mode mode) |
e0cd0770 JC |
9720 | { |
9721 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
9722 | return 0; | |
ec8e098d | 9723 | return COMPARISON_P (op); |
e0cd0770 | 9724 | } |
dfbdccdb GK |
9725 | |
9726 | int | |
a2369ed3 | 9727 | boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dfbdccdb GK |
9728 | { |
9729 | enum rtx_code code = GET_CODE (op); | |
9730 | return (code == AND || code == IOR || code == XOR); | |
9731 | } | |
1d328b19 GK |
9732 | |
9733 | int | |
a2369ed3 | 9734 | boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
1d328b19 GK |
9735 | { |
9736 | enum rtx_code code = GET_CODE (op); | |
9737 | return (code == IOR || code == XOR); | |
9738 | } | |
50a0b056 GK |
9739 | |
9740 | int | |
a2369ed3 | 9741 | min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
50a0b056 GK |
9742 | { |
9743 | enum rtx_code code = GET_CODE (op); | |
9744 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
9745 | } | |
9878760c RK |
9746 | \f |
9747 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
9748 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 9749 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
9750 | |
9751 | int | |
a2369ed3 | 9752 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 9753 | { |
e2c953b6 DE |
9754 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9755 | ||
9756 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 9757 | |
b1765bde | 9758 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
9759 | } |
9760 | ||
9761 | /* Similar, but for right shift. */ | |
9762 | ||
9763 | int | |
a2369ed3 | 9764 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 9765 | { |
a7653a2c | 9766 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
9767 | |
9768 | shift_mask >>= INTVAL (shiftop); | |
9769 | ||
b1765bde | 9770 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
9771 | } |
9772 | ||
c5059423 AM |
9773 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
9774 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 9775 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
9776 | |
9777 | int | |
a2369ed3 | 9778 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 9779 | { |
c5059423 AM |
9780 | if (GET_CODE (andop) == CONST_INT) |
9781 | { | |
02071907 | 9782 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 9783 | |
c5059423 | 9784 | c = INTVAL (andop); |
02071907 | 9785 | if (c == 0 || c == ~0) |
c5059423 | 9786 | return 0; |
e2c953b6 | 9787 | |
02071907 | 9788 | shift_mask = ~0; |
c5059423 AM |
9789 | shift_mask <<= INTVAL (shiftop); |
9790 | ||
b6d08ca1 | 9791 | /* Find the least significant one bit. */ |
c5059423 AM |
9792 | lsb = c & -c; |
9793 | ||
9794 | /* It must coincide with the LSB of the shift mask. */ | |
9795 | if (-lsb != shift_mask) | |
9796 | return 0; | |
e2c953b6 | 9797 | |
c5059423 AM |
9798 | /* Invert to look for the next transition (if any). */ |
9799 | c = ~c; | |
9800 | ||
9801 | /* Remove the low group of ones (originally low group of zeros). */ | |
9802 | c &= -lsb; | |
9803 | ||
9804 | /* Again find the lsb, and check we have all 1's above. */ | |
9805 | lsb = c & -c; | |
9806 | return c == -lsb; | |
9807 | } | |
9808 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9809 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9810 | { | |
02071907 AM |
9811 | HOST_WIDE_INT low, high, lsb; |
9812 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
9813 | |
9814 | low = CONST_DOUBLE_LOW (andop); | |
9815 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9816 | high = CONST_DOUBLE_HIGH (andop); | |
9817 | ||
9818 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 9819 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
9820 | return 0; |
9821 | ||
9822 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9823 | { | |
02071907 | 9824 | shift_mask_high = ~0; |
c5059423 AM |
9825 | if (INTVAL (shiftop) > 32) |
9826 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9827 | ||
9828 | lsb = high & -high; | |
9829 | ||
9830 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
9831 | return 0; | |
9832 | ||
9833 | high = ~high; | |
9834 | high &= -lsb; | |
9835 | ||
9836 | lsb = high & -high; | |
9837 | return high == -lsb; | |
9838 | } | |
9839 | ||
02071907 | 9840 | shift_mask_low = ~0; |
c5059423 AM |
9841 | shift_mask_low <<= INTVAL (shiftop); |
9842 | ||
9843 | lsb = low & -low; | |
9844 | ||
9845 | if (-lsb != shift_mask_low) | |
9846 | return 0; | |
9847 | ||
9848 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9849 | high = ~high; | |
9850 | low = ~low; | |
9851 | low &= -lsb; | |
9852 | ||
9853 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9854 | { | |
9855 | lsb = high & -high; | |
9856 | return high == -lsb; | |
9857 | } | |
9858 | ||
9859 | lsb = low & -low; | |
9860 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
9861 | } | |
9862 | else | |
9863 | return 0; | |
9864 | } | |
e2c953b6 | 9865 | |
c5059423 AM |
9866 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
9867 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 9868 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 9869 | |
c5059423 | 9870 | int |
a2369ed3 | 9871 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 9872 | { |
e2c953b6 | 9873 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 9874 | { |
02071907 | 9875 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 9876 | |
02071907 | 9877 | shift_mask = ~0; |
c5059423 AM |
9878 | shift_mask <<= INTVAL (shiftop); |
9879 | c = INTVAL (andop); | |
9880 | ||
c1207243 | 9881 | /* Find the least significant one bit. */ |
c5059423 AM |
9882 | lsb = c & -c; |
9883 | ||
9884 | /* It must be covered by the shift mask. | |
a4f6c312 | 9885 | This test also rejects c == 0. */ |
c5059423 AM |
9886 | if ((lsb & shift_mask) == 0) |
9887 | return 0; | |
9888 | ||
9889 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
9890 | return c == -lsb && lsb != 1; | |
9891 | } | |
9892 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9893 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9894 | { | |
02071907 | 9895 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
9896 | |
9897 | low = CONST_DOUBLE_LOW (andop); | |
9898 | ||
9899 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9900 | { | |
02071907 | 9901 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
9902 | |
9903 | high = CONST_DOUBLE_HIGH (andop); | |
9904 | ||
9905 | if (low == 0) | |
9906 | { | |
02071907 | 9907 | shift_mask_high = ~0; |
c5059423 AM |
9908 | if (INTVAL (shiftop) > 32) |
9909 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9910 | ||
9911 | lsb = high & -high; | |
9912 | ||
9913 | if ((lsb & shift_mask_high) == 0) | |
9914 | return 0; | |
9915 | ||
9916 | return high == -lsb; | |
9917 | } | |
9918 | if (high != ~0) | |
9919 | return 0; | |
9920 | } | |
9921 | ||
02071907 | 9922 | shift_mask_low = ~0; |
c5059423 AM |
9923 | shift_mask_low <<= INTVAL (shiftop); |
9924 | ||
9925 | lsb = low & -low; | |
9926 | ||
9927 | if ((lsb & shift_mask_low) == 0) | |
9928 | return 0; | |
9929 | ||
9930 | return low == -lsb && lsb != 1; | |
9931 | } | |
e2c953b6 | 9932 | else |
c5059423 | 9933 | return 0; |
9878760c | 9934 | } |
35068b43 | 9935 | |
11ac38b2 DE |
9936 | /* Return 1 if operands will generate a valid arguments to rlwimi |
9937 | instruction for insert with right shift in 64-bit mode. The mask may | |
9938 | not start on the first bit or stop on the last bit because wrap-around | |
9939 | effects of instruction do not correspond to semantics of RTL insn. */ | |
9940 | ||
9941 | int | |
9942 | insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) | |
9943 | { | |
9944 | if (INTVAL (startop) < 64 | |
9945 | && INTVAL (startop) > 32 | |
9946 | && (INTVAL (sizeop) + INTVAL (startop) < 64) | |
9947 | && (INTVAL (sizeop) + INTVAL (startop) > 33) | |
9948 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96) | |
9949 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64) | |
9950 | && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) | |
9951 | return 1; | |
9952 | ||
9953 | return 0; | |
9954 | } | |
9955 | ||
35068b43 | 9956 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates |
90f81f99 | 9957 | for lfq and stfq insns iff the registers are hard registers. */ |
35068b43 RK |
9958 | |
9959 | int | |
a2369ed3 | 9960 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
9961 | { |
9962 | /* We might have been passed a SUBREG. */ | |
f676971a | 9963 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) |
35068b43 | 9964 | return 0; |
f676971a | 9965 | |
90f81f99 AP |
9966 | /* We might have been passed non floating point registers. */ |
9967 | if (!FP_REGNO_P (REGNO (reg1)) | |
9968 | || !FP_REGNO_P (REGNO (reg2))) | |
9969 | return 0; | |
35068b43 RK |
9970 | |
9971 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
9972 | } | |
9973 | ||
a4f6c312 SS |
9974 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
9975 | addr1 and addr2 must be in consecutive memory locations | |
9976 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
9977 | |
9978 | int | |
90f81f99 | 9979 | mems_ok_for_quad_peep (rtx mem1, rtx mem2) |
35068b43 | 9980 | { |
90f81f99 | 9981 | rtx addr1, addr2; |
e2c953b6 | 9982 | unsigned int reg1; |
35068b43 RK |
9983 | int offset1; |
9984 | ||
90f81f99 AP |
9985 | /* The mems cannot be volatile. */ |
9986 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
9987 | return 0; | |
f676971a | 9988 | |
90f81f99 AP |
9989 | addr1 = XEXP (mem1, 0); |
9990 | addr2 = XEXP (mem2, 0); | |
9991 | ||
35068b43 RK |
9992 | /* Extract an offset (if used) from the first addr. */ |
9993 | if (GET_CODE (addr1) == PLUS) | |
9994 | { | |
9995 | /* If not a REG, return zero. */ | |
9996 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
9997 | return 0; | |
9998 | else | |
9999 | { | |
c4ad648e | 10000 | reg1 = REGNO (XEXP (addr1, 0)); |
35068b43 RK |
10001 | /* The offset must be constant! */ |
10002 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
c4ad648e AM |
10003 | return 0; |
10004 | offset1 = INTVAL (XEXP (addr1, 1)); | |
35068b43 RK |
10005 | } |
10006 | } | |
10007 | else if (GET_CODE (addr1) != REG) | |
10008 | return 0; | |
10009 | else | |
10010 | { | |
10011 | reg1 = REGNO (addr1); | |
10012 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
10013 | offset1 = 0; | |
10014 | } | |
10015 | ||
a2369ed3 | 10016 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
f676971a | 10017 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same |
0f6937fe | 10018 | register as addr1. */ |
984e25ac | 10019 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) |
0f6937fe | 10020 | return 1; |
35068b43 RK |
10021 | if (GET_CODE (addr2) != PLUS) |
10022 | return 0; | |
10023 | ||
10024 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
10025 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
10026 | return 0; | |
10027 | ||
10028 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
10029 | return 0; | |
10030 | ||
10031 | /* The offset for the second addr must be 8 more than the first addr. */ | |
10032 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
10033 | return 0; | |
10034 | ||
10035 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
10036 | instructions. */ | |
10037 | return 1; | |
10038 | } | |
9878760c RK |
10039 | \f |
10040 | /* Return the register class of a scratch register needed to copy IN into | |
10041 | or out of a register in CLASS in MODE. If it can be done directly, | |
10042 | NO_REGS is returned. */ | |
10043 | ||
10044 | enum reg_class | |
f676971a | 10045 | secondary_reload_class (enum reg_class class, |
a9baceb1 GK |
10046 | enum machine_mode mode ATTRIBUTE_UNUSED, |
10047 | rtx in) | |
9878760c | 10048 | { |
5accd822 | 10049 | int regno; |
9878760c | 10050 | |
ab82a49f AP |
10051 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
10052 | #if TARGET_MACHO | |
c4ad648e | 10053 | && MACHOPIC_INDIRECT |
ab82a49f | 10054 | #endif |
c4ad648e | 10055 | )) |
46fad5b7 DJ |
10056 | { |
10057 | /* We cannot copy a symbolic operand directly into anything | |
c4ad648e AM |
10058 | other than BASE_REGS for TARGET_ELF. So indicate that a |
10059 | register from BASE_REGS is needed as an intermediate | |
10060 | register. | |
f676971a | 10061 | |
46fad5b7 DJ |
10062 | On Darwin, pic addresses require a load from memory, which |
10063 | needs a base register. */ | |
10064 | if (class != BASE_REGS | |
c4ad648e AM |
10065 | && (GET_CODE (in) == SYMBOL_REF |
10066 | || GET_CODE (in) == HIGH | |
10067 | || GET_CODE (in) == LABEL_REF | |
10068 | || GET_CODE (in) == CONST)) | |
10069 | return BASE_REGS; | |
46fad5b7 | 10070 | } |
e7b7998a | 10071 | |
5accd822 DE |
10072 | if (GET_CODE (in) == REG) |
10073 | { | |
10074 | regno = REGNO (in); | |
10075 | if (regno >= FIRST_PSEUDO_REGISTER) | |
10076 | { | |
10077 | regno = true_regnum (in); | |
10078 | if (regno >= FIRST_PSEUDO_REGISTER) | |
10079 | regno = -1; | |
10080 | } | |
10081 | } | |
10082 | else if (GET_CODE (in) == SUBREG) | |
10083 | { | |
10084 | regno = true_regnum (in); | |
10085 | if (regno >= FIRST_PSEUDO_REGISTER) | |
10086 | regno = -1; | |
10087 | } | |
10088 | else | |
10089 | regno = -1; | |
10090 | ||
9878760c RK |
10091 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
10092 | into anything. */ | |
10093 | if (class == GENERAL_REGS || class == BASE_REGS | |
10094 | || (regno >= 0 && INT_REGNO_P (regno))) | |
10095 | return NO_REGS; | |
10096 | ||
10097 | /* Constants, memory, and FP registers can go into FP registers. */ | |
10098 | if ((regno == -1 || FP_REGNO_P (regno)) | |
10099 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
10100 | return NO_REGS; | |
10101 | ||
0ac081f6 AH |
10102 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
10103 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
10104 | && class == ALTIVEC_REGS) | |
10105 | return NO_REGS; | |
10106 | ||
9878760c RK |
10107 | /* We can copy among the CR registers. */ |
10108 | if ((class == CR_REGS || class == CR0_REGS) | |
10109 | && regno >= 0 && CR_REGNO_P (regno)) | |
10110 | return NO_REGS; | |
10111 | ||
10112 | /* Otherwise, we need GENERAL_REGS. */ | |
10113 | return GENERAL_REGS; | |
10114 | } | |
10115 | \f | |
10116 | /* Given a comparison operation, return the bit number in CCR to test. We | |
f676971a | 10117 | know this is a valid comparison. |
9878760c RK |
10118 | |
10119 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
10120 | used instead of %C, so the bits will be in different places. | |
10121 | ||
b4ac57ab | 10122 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
10123 | |
10124 | int | |
a2369ed3 | 10125 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
10126 | { |
10127 | enum rtx_code code = GET_CODE (op); | |
10128 | enum machine_mode cc_mode; | |
10129 | int cc_regnum; | |
10130 | int base_bit; | |
9ebbca7d | 10131 | rtx reg; |
9878760c | 10132 | |
ec8e098d | 10133 | if (!COMPARISON_P (op)) |
9878760c RK |
10134 | return -1; |
10135 | ||
9ebbca7d GK |
10136 | reg = XEXP (op, 0); |
10137 | ||
10138 | if (GET_CODE (reg) != REG | |
10139 | || ! CR_REGNO_P (REGNO (reg))) | |
10140 | abort (); | |
10141 | ||
10142 | cc_mode = GET_MODE (reg); | |
10143 | cc_regnum = REGNO (reg); | |
10144 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 10145 | |
39a10a29 | 10146 | validate_condition_mode (code, cc_mode); |
c5defebb | 10147 | |
b7053a3f GK |
10148 | /* When generating a sCOND operation, only positive conditions are |
10149 | allowed. */ | |
10150 | if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED | |
10151 | && code != GTU && code != LTU) | |
10152 | abort (); | |
f676971a | 10153 | |
9878760c RK |
10154 | switch (code) |
10155 | { | |
10156 | case NE: | |
10157 | return scc_p ? base_bit + 3 : base_bit + 2; | |
10158 | case EQ: | |
10159 | return base_bit + 2; | |
1c882ea4 | 10160 | case GT: case GTU: case UNLE: |
9878760c | 10161 | return base_bit + 1; |
1c882ea4 | 10162 | case LT: case LTU: case UNGE: |
9878760c | 10163 | return base_bit; |
1c882ea4 GK |
10164 | case ORDERED: case UNORDERED: |
10165 | return base_bit + 3; | |
9878760c RK |
10166 | |
10167 | case GE: case GEU: | |
39a10a29 | 10168 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
10169 | unordered position. So test that bit. For integer, this is ! LT |
10170 | unless this is an scc insn. */ | |
39a10a29 | 10171 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
10172 | |
10173 | case LE: case LEU: | |
39a10a29 | 10174 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 10175 | |
9878760c RK |
10176 | default: |
10177 | abort (); | |
10178 | } | |
10179 | } | |
1ff7789b | 10180 | \f |
8d30c4ee | 10181 | /* Return the GOT register. */ |
1ff7789b MM |
10182 | |
10183 | struct rtx_def * | |
a2369ed3 | 10184 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 10185 | { |
a4f6c312 SS |
10186 | /* The second flow pass currently (June 1999) can't update |
10187 | regs_ever_live without disturbing other parts of the compiler, so | |
10188 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
10189 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
10190 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 10191 | |
8d30c4ee | 10192 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 10193 | |
1ff7789b MM |
10194 | return pic_offset_table_rtx; |
10195 | } | |
a7df97e6 | 10196 | \f |
e2500fed GK |
10197 | /* Function to init struct machine_function. |
10198 | This will be called, via a pointer variable, | |
10199 | from push_function_context. */ | |
a7df97e6 | 10200 | |
e2500fed | 10201 | static struct machine_function * |
863d938c | 10202 | rs6000_init_machine_status (void) |
a7df97e6 | 10203 | { |
e2500fed | 10204 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 10205 | } |
9878760c | 10206 | \f |
0ba1b2ff AM |
10207 | /* These macros test for integers and extract the low-order bits. */ |
10208 | #define INT_P(X) \ | |
10209 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
10210 | && GET_MODE (X) == VOIDmode) | |
10211 | ||
10212 | #define INT_LOWPART(X) \ | |
10213 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
10214 | ||
10215 | int | |
a2369ed3 | 10216 | extract_MB (rtx op) |
0ba1b2ff AM |
10217 | { |
10218 | int i; | |
10219 | unsigned long val = INT_LOWPART (op); | |
10220 | ||
10221 | /* If the high bit is zero, the value is the first 1 bit we find | |
10222 | from the left. */ | |
10223 | if ((val & 0x80000000) == 0) | |
10224 | { | |
10225 | if ((val & 0xffffffff) == 0) | |
10226 | abort (); | |
10227 | ||
10228 | i = 1; | |
10229 | while (((val <<= 1) & 0x80000000) == 0) | |
10230 | ++i; | |
10231 | return i; | |
10232 | } | |
10233 | ||
10234 | /* If the high bit is set and the low bit is not, or the mask is all | |
10235 | 1's, the value is zero. */ | |
10236 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
10237 | return 0; | |
10238 | ||
10239 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
10240 | from the right. */ | |
10241 | i = 31; | |
10242 | while (((val >>= 1) & 1) != 0) | |
10243 | --i; | |
10244 | ||
10245 | return i; | |
10246 | } | |
10247 | ||
10248 | int | |
a2369ed3 | 10249 | extract_ME (rtx op) |
0ba1b2ff AM |
10250 | { |
10251 | int i; | |
10252 | unsigned long val = INT_LOWPART (op); | |
10253 | ||
10254 | /* If the low bit is zero, the value is the first 1 bit we find from | |
10255 | the right. */ | |
10256 | if ((val & 1) == 0) | |
10257 | { | |
10258 | if ((val & 0xffffffff) == 0) | |
10259 | abort (); | |
10260 | ||
10261 | i = 30; | |
10262 | while (((val >>= 1) & 1) == 0) | |
10263 | --i; | |
10264 | ||
10265 | return i; | |
10266 | } | |
10267 | ||
10268 | /* If the low bit is set and the high bit is not, or the mask is all | |
10269 | 1's, the value is 31. */ | |
10270 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
10271 | return 31; | |
10272 | ||
10273 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
10274 | from the left. */ | |
10275 | i = 0; | |
10276 | while (((val <<= 1) & 0x80000000) != 0) | |
10277 | ++i; | |
10278 | ||
10279 | return i; | |
10280 | } | |
10281 | ||
c4501e62 JJ |
10282 | /* Locate some local-dynamic symbol still in use by this function |
10283 | so that we can print its name in some tls_ld pattern. */ | |
10284 | ||
10285 | static const char * | |
863d938c | 10286 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
10287 | { |
10288 | rtx insn; | |
10289 | ||
10290 | if (cfun->machine->some_ld_name) | |
10291 | return cfun->machine->some_ld_name; | |
10292 | ||
10293 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
10294 | if (INSN_P (insn) | |
10295 | && for_each_rtx (&PATTERN (insn), | |
10296 | rs6000_get_some_local_dynamic_name_1, 0)) | |
10297 | return cfun->machine->some_ld_name; | |
10298 | ||
10299 | abort (); | |
10300 | } | |
10301 | ||
10302 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
10303 | ||
10304 | static int | |
a2369ed3 | 10305 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
10306 | { |
10307 | rtx x = *px; | |
10308 | ||
10309 | if (GET_CODE (x) == SYMBOL_REF) | |
10310 | { | |
10311 | const char *str = XSTR (x, 0); | |
10312 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
10313 | { | |
10314 | cfun->machine->some_ld_name = str; | |
10315 | return 1; | |
10316 | } | |
10317 | } | |
10318 | ||
10319 | return 0; | |
10320 | } | |
10321 | ||
85b776df AM |
10322 | /* Write out a function code label. */ |
10323 | ||
10324 | void | |
10325 | rs6000_output_function_entry (FILE *file, const char *fname) | |
10326 | { | |
10327 | if (fname[0] != '.') | |
10328 | { | |
10329 | switch (DEFAULT_ABI) | |
10330 | { | |
10331 | default: | |
10332 | abort (); | |
10333 | ||
10334 | case ABI_AIX: | |
10335 | if (DOT_SYMBOLS) | |
10336 | putc ('.', file); | |
10337 | else | |
10338 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); | |
10339 | break; | |
10340 | ||
10341 | case ABI_V4: | |
10342 | case ABI_DARWIN: | |
10343 | break; | |
10344 | } | |
10345 | } | |
10346 | if (TARGET_AIX) | |
10347 | RS6000_OUTPUT_BASENAME (file, fname); | |
10348 | else | |
10349 | assemble_name (file, fname); | |
10350 | } | |
10351 | ||
9878760c RK |
10352 | /* Print an operand. Recognize special options, documented below. */ |
10353 | ||
38c1f2d7 | 10354 | #if TARGET_ELF |
d9407988 | 10355 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 10356 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
10357 | #else |
10358 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 10359 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
10360 | #endif |
10361 | ||
9878760c | 10362 | void |
a2369ed3 | 10363 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
10364 | { |
10365 | int i; | |
a260abc9 | 10366 | HOST_WIDE_INT val; |
0ba1b2ff | 10367 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
10368 | |
10369 | switch (code) | |
10370 | { | |
a8b3aeda | 10371 | case '.': |
a85d226b RK |
10372 | /* Write out an instruction after the call which may be replaced |
10373 | with glue code by the loader. This depends on the AIX version. */ | |
10374 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
10375 | return; |
10376 | ||
81eace42 GK |
10377 | /* %a is output_address. */ |
10378 | ||
9854d9ed RK |
10379 | case 'A': |
10380 | /* If X is a constant integer whose low-order 5 bits are zero, | |
10381 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 10382 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 10383 | writes a trash instruction. */ |
9854d9ed | 10384 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 10385 | putc ('l', file); |
9854d9ed | 10386 | else |
76229ac8 | 10387 | putc ('r', file); |
9854d9ed RK |
10388 | return; |
10389 | ||
10390 | case 'b': | |
e2c953b6 DE |
10391 | /* If constant, low-order 16 bits of constant, unsigned. |
10392 | Otherwise, write normally. */ | |
10393 | if (INT_P (x)) | |
10394 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
10395 | else | |
10396 | print_operand (file, x, 0); | |
cad12a8d RK |
10397 | return; |
10398 | ||
a260abc9 DE |
10399 | case 'B': |
10400 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
10401 | for 64-bit mask direction. */ | |
296b8152 | 10402 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 10403 | return; |
a260abc9 | 10404 | |
81eace42 GK |
10405 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
10406 | output_operand. */ | |
10407 | ||
423c1189 AH |
10408 | case 'c': |
10409 | /* X is a CR register. Print the number of the GT bit of the CR. */ | |
10410 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10411 | output_operand_lossage ("invalid %%E value"); | |
10412 | else | |
10413 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); | |
10414 | return; | |
10415 | ||
10416 | case 'D': | |
6b1fedc3 | 10417 | /* Like 'J' but get to the EQ bit. */ |
423c1189 AH |
10418 | if (GET_CODE (x) != REG) |
10419 | abort (); | |
10420 | ||
6b1fedc3 AH |
10421 | /* Bit 1 is EQ bit. */ |
10422 | i = 4 * (REGNO (x) - CR0_REGNO) + 2; | |
423c1189 AH |
10423 | |
10424 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
10425 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
10426 | return; | |
10427 | ||
9854d9ed | 10428 | case 'E': |
39a10a29 | 10429 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
10430 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
10431 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 10432 | else |
39a10a29 | 10433 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 10434 | return; |
9854d9ed RK |
10435 | |
10436 | case 'f': | |
10437 | /* X is a CR register. Print the shift count needed to move it | |
10438 | to the high-order four bits. */ | |
10439 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10440 | output_operand_lossage ("invalid %%f value"); | |
10441 | else | |
9ebbca7d | 10442 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
10443 | return; |
10444 | ||
10445 | case 'F': | |
10446 | /* Similar, but print the count for the rotate in the opposite | |
10447 | direction. */ | |
10448 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10449 | output_operand_lossage ("invalid %%F value"); | |
10450 | else | |
9ebbca7d | 10451 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
10452 | return; |
10453 | ||
10454 | case 'G': | |
10455 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 10456 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
10457 | if (GET_CODE (x) != CONST_INT) |
10458 | output_operand_lossage ("invalid %%G value"); | |
10459 | else if (INTVAL (x) >= 0) | |
76229ac8 | 10460 | putc ('z', file); |
9854d9ed | 10461 | else |
76229ac8 | 10462 | putc ('m', file); |
9854d9ed | 10463 | return; |
e2c953b6 | 10464 | |
9878760c | 10465 | case 'h': |
a4f6c312 SS |
10466 | /* If constant, output low-order five bits. Otherwise, write |
10467 | normally. */ | |
9878760c | 10468 | if (INT_P (x)) |
5f59ecb7 | 10469 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
10470 | else |
10471 | print_operand (file, x, 0); | |
10472 | return; | |
10473 | ||
64305719 | 10474 | case 'H': |
a4f6c312 SS |
10475 | /* If constant, output low-order six bits. Otherwise, write |
10476 | normally. */ | |
64305719 | 10477 | if (INT_P (x)) |
5f59ecb7 | 10478 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
10479 | else |
10480 | print_operand (file, x, 0); | |
10481 | return; | |
10482 | ||
9854d9ed RK |
10483 | case 'I': |
10484 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 10485 | if (INT_P (x)) |
76229ac8 | 10486 | putc ('i', file); |
9878760c RK |
10487 | return; |
10488 | ||
9854d9ed RK |
10489 | case 'j': |
10490 | /* Write the bit number in CCR for jump. */ | |
10491 | i = ccr_bit (x, 0); | |
10492 | if (i == -1) | |
10493 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 10494 | else |
9854d9ed | 10495 | fprintf (file, "%d", i); |
9878760c RK |
10496 | return; |
10497 | ||
9854d9ed RK |
10498 | case 'J': |
10499 | /* Similar, but add one for shift count in rlinm for scc and pass | |
10500 | scc flag to `ccr_bit'. */ | |
10501 | i = ccr_bit (x, 1); | |
10502 | if (i == -1) | |
10503 | output_operand_lossage ("invalid %%J code"); | |
10504 | else | |
a0466a68 RK |
10505 | /* If we want bit 31, write a shift count of zero, not 32. */ |
10506 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
10507 | return; |
10508 | ||
9854d9ed RK |
10509 | case 'k': |
10510 | /* X must be a constant. Write the 1's complement of the | |
10511 | constant. */ | |
9878760c | 10512 | if (! INT_P (x)) |
9854d9ed | 10513 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
10514 | else |
10515 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
10516 | return; |
10517 | ||
81eace42 | 10518 | case 'K': |
9ebbca7d GK |
10519 | /* X must be a symbolic constant on ELF. Write an |
10520 | expression suitable for an 'addi' that adds in the low 16 | |
10521 | bits of the MEM. */ | |
10522 | if (GET_CODE (x) != CONST) | |
10523 | { | |
10524 | print_operand_address (file, x); | |
10525 | fputs ("@l", file); | |
10526 | } | |
10527 | else | |
10528 | { | |
10529 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
10530 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
10531 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
10532 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 10533 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
10534 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
10535 | fputs ("@l", file); | |
ed8d2920 MM |
10536 | /* For GNU as, there must be a non-alphanumeric character |
10537 | between 'l' and the number. The '-' is added by | |
10538 | print_operand() already. */ | |
10539 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
10540 | fputs ("+", file); | |
9ebbca7d GK |
10541 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
10542 | } | |
81eace42 GK |
10543 | return; |
10544 | ||
10545 | /* %l is output_asm_label. */ | |
9ebbca7d | 10546 | |
9854d9ed RK |
10547 | case 'L': |
10548 | /* Write second word of DImode or DFmode reference. Works on register | |
10549 | or non-indexed memory only. */ | |
10550 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10551 | fputs (reg_names[REGNO (x) + 1], file); |
9854d9ed RK |
10552 | else if (GET_CODE (x) == MEM) |
10553 | { | |
10554 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 10555 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
10556 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
10557 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
10558 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
10559 | UNITS_PER_WORD)); | |
9854d9ed | 10560 | else |
d7624dc0 RK |
10561 | output_address (XEXP (adjust_address_nv (x, SImode, |
10562 | UNITS_PER_WORD), | |
10563 | 0)); | |
ed8908e7 | 10564 | |
ba5e43aa | 10565 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10566 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10567 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 10568 | } |
9878760c | 10569 | return; |
f676971a | 10570 | |
9878760c RK |
10571 | case 'm': |
10572 | /* MB value for a mask operand. */ | |
b1765bde | 10573 | if (! mask_operand (x, SImode)) |
9878760c RK |
10574 | output_operand_lossage ("invalid %%m value"); |
10575 | ||
0ba1b2ff | 10576 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
10577 | return; |
10578 | ||
10579 | case 'M': | |
10580 | /* ME value for a mask operand. */ | |
b1765bde | 10581 | if (! mask_operand (x, SImode)) |
a260abc9 | 10582 | output_operand_lossage ("invalid %%M value"); |
9878760c | 10583 | |
0ba1b2ff | 10584 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
10585 | return; |
10586 | ||
81eace42 GK |
10587 | /* %n outputs the negative of its operand. */ |
10588 | ||
9878760c RK |
10589 | case 'N': |
10590 | /* Write the number of elements in the vector times 4. */ | |
10591 | if (GET_CODE (x) != PARALLEL) | |
10592 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
10593 | else |
10594 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
10595 | return; |
10596 | ||
10597 | case 'O': | |
10598 | /* Similar, but subtract 1 first. */ | |
10599 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 10600 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
10601 | else |
10602 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
10603 | return; |
10604 | ||
9854d9ed RK |
10605 | case 'p': |
10606 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
10607 | if (! INT_P (x) | |
2bfcf297 | 10608 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
10609 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
10610 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
10611 | else |
10612 | fprintf (file, "%d", i); | |
9854d9ed RK |
10613 | return; |
10614 | ||
9878760c RK |
10615 | case 'P': |
10616 | /* The operand must be an indirect memory reference. The result | |
8bb418a3 | 10617 | is the register name. */ |
9878760c RK |
10618 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
10619 | || REGNO (XEXP (x, 0)) >= 32) | |
10620 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 | 10621 | else |
fb5c67a7 | 10622 | fputs (reg_names[REGNO (XEXP (x, 0))], file); |
9878760c RK |
10623 | return; |
10624 | ||
dfbdccdb GK |
10625 | case 'q': |
10626 | /* This outputs the logical code corresponding to a boolean | |
10627 | expression. The expression may have one or both operands | |
39a10a29 | 10628 | negated (if one, only the first one). For condition register |
c4ad648e AM |
10629 | logical operations, it will also treat the negated |
10630 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 10631 | { |
63bc1d05 | 10632 | const char *const *t = 0; |
dfbdccdb GK |
10633 | const char *s; |
10634 | enum rtx_code code = GET_CODE (x); | |
10635 | static const char * const tbl[3][3] = { | |
10636 | { "and", "andc", "nor" }, | |
10637 | { "or", "orc", "nand" }, | |
10638 | { "xor", "eqv", "xor" } }; | |
10639 | ||
10640 | if (code == AND) | |
10641 | t = tbl[0]; | |
10642 | else if (code == IOR) | |
10643 | t = tbl[1]; | |
10644 | else if (code == XOR) | |
10645 | t = tbl[2]; | |
10646 | else | |
10647 | output_operand_lossage ("invalid %%q value"); | |
10648 | ||
10649 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
10650 | s = t[0]; | |
10651 | else | |
10652 | { | |
10653 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
10654 | s = t[2]; | |
10655 | else | |
10656 | s = t[1]; | |
10657 | } | |
f676971a | 10658 | |
dfbdccdb GK |
10659 | fputs (s, file); |
10660 | } | |
10661 | return; | |
10662 | ||
2c4a9cff DE |
10663 | case 'Q': |
10664 | if (TARGET_MFCRF) | |
3b6ce0af | 10665 | fputc (',', file); |
5efb1046 | 10666 | /* FALLTHRU */ |
2c4a9cff DE |
10667 | else |
10668 | return; | |
10669 | ||
9854d9ed RK |
10670 | case 'R': |
10671 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
10672 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10673 | output_operand_lossage ("invalid %%R value"); | |
10674 | else | |
9ebbca7d | 10675 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 10676 | return; |
9854d9ed RK |
10677 | |
10678 | case 's': | |
10679 | /* Low 5 bits of 32 - value */ | |
10680 | if (! INT_P (x)) | |
10681 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
10682 | else |
10683 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 10684 | return; |
9854d9ed | 10685 | |
a260abc9 | 10686 | case 'S': |
0ba1b2ff | 10687 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
10688 | CONST_INT 32-bit mask is considered sign-extended so any |
10689 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 10690 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
10691 | output_operand_lossage ("invalid %%S value"); |
10692 | ||
0ba1b2ff | 10693 | uval = INT_LOWPART (x); |
a260abc9 | 10694 | |
0ba1b2ff | 10695 | if (uval & 1) /* Clear Left */ |
a260abc9 | 10696 | { |
f099d360 GK |
10697 | #if HOST_BITS_PER_WIDE_INT > 64 |
10698 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
10699 | #endif | |
0ba1b2ff | 10700 | i = 64; |
a260abc9 | 10701 | } |
0ba1b2ff | 10702 | else /* Clear Right */ |
a260abc9 | 10703 | { |
0ba1b2ff | 10704 | uval = ~uval; |
f099d360 GK |
10705 | #if HOST_BITS_PER_WIDE_INT > 64 |
10706 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
10707 | #endif | |
0ba1b2ff | 10708 | i = 63; |
a260abc9 | 10709 | } |
0ba1b2ff AM |
10710 | while (uval != 0) |
10711 | --i, uval >>= 1; | |
10712 | if (i < 0) | |
10713 | abort (); | |
10714 | fprintf (file, "%d", i); | |
10715 | return; | |
a260abc9 | 10716 | |
a3170dc6 AH |
10717 | case 't': |
10718 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
10719 | if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) | |
10720 | abort (); | |
10721 | ||
10722 | /* Bit 3 is OV bit. */ | |
10723 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
10724 | ||
10725 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
10726 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
10727 | return; | |
10728 | ||
cccf3bdc DE |
10729 | case 'T': |
10730 | /* Print the symbolic name of a branch target register. */ | |
10731 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
10732 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
10733 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 10734 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
10735 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
10736 | else | |
10737 | fputs ("ctr", file); | |
10738 | return; | |
10739 | ||
9854d9ed | 10740 | case 'u': |
802a0058 | 10741 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
10742 | if (! INT_P (x)) |
10743 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 | 10744 | else |
f676971a | 10745 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
e2c953b6 | 10746 | (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
10747 | return; |
10748 | ||
802a0058 MM |
10749 | case 'v': |
10750 | /* High-order 16 bits of constant for use in signed operand. */ | |
10751 | if (! INT_P (x)) | |
10752 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 10753 | else |
134c32f6 DE |
10754 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
10755 | (INT_LOWPART (x) >> 16) & 0xffff); | |
10756 | return; | |
802a0058 | 10757 | |
9854d9ed RK |
10758 | case 'U': |
10759 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
10760 | if (GET_CODE (x) == MEM | |
10761 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
10762 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 10763 | putc ('u', file); |
9854d9ed | 10764 | return; |
9878760c | 10765 | |
e0cd0770 JC |
10766 | case 'V': |
10767 | /* Print the trap code for this operand. */ | |
10768 | switch (GET_CODE (x)) | |
10769 | { | |
10770 | case EQ: | |
10771 | fputs ("eq", file); /* 4 */ | |
10772 | break; | |
10773 | case NE: | |
10774 | fputs ("ne", file); /* 24 */ | |
10775 | break; | |
10776 | case LT: | |
10777 | fputs ("lt", file); /* 16 */ | |
10778 | break; | |
10779 | case LE: | |
10780 | fputs ("le", file); /* 20 */ | |
10781 | break; | |
10782 | case GT: | |
10783 | fputs ("gt", file); /* 8 */ | |
10784 | break; | |
10785 | case GE: | |
10786 | fputs ("ge", file); /* 12 */ | |
10787 | break; | |
10788 | case LTU: | |
10789 | fputs ("llt", file); /* 2 */ | |
10790 | break; | |
10791 | case LEU: | |
10792 | fputs ("lle", file); /* 6 */ | |
10793 | break; | |
10794 | case GTU: | |
10795 | fputs ("lgt", file); /* 1 */ | |
10796 | break; | |
10797 | case GEU: | |
10798 | fputs ("lge", file); /* 5 */ | |
10799 | break; | |
10800 | default: | |
10801 | abort (); | |
10802 | } | |
10803 | break; | |
10804 | ||
9854d9ed RK |
10805 | case 'w': |
10806 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
10807 | normally. */ | |
10808 | if (INT_P (x)) | |
f676971a | 10809 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5f59ecb7 | 10810 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); |
9854d9ed RK |
10811 | else |
10812 | print_operand (file, x, 0); | |
9878760c RK |
10813 | return; |
10814 | ||
9854d9ed | 10815 | case 'W': |
e2c953b6 | 10816 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
10817 | val = (GET_CODE (x) == CONST_INT |
10818 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
10819 | ||
10820 | if (val < 0) | |
10821 | i = -1; | |
9854d9ed | 10822 | else |
e2c953b6 DE |
10823 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
10824 | if ((val <<= 1) < 0) | |
10825 | break; | |
10826 | ||
10827 | #if HOST_BITS_PER_WIDE_INT == 32 | |
10828 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
10829 | i += 32; /* zero-extend high-part was all 0's */ | |
10830 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
10831 | { | |
10832 | val = CONST_DOUBLE_LOW (x); | |
10833 | ||
10834 | if (val == 0) | |
a4f6c312 | 10835 | abort (); |
e2c953b6 DE |
10836 | else if (val < 0) |
10837 | --i; | |
10838 | else | |
10839 | for ( ; i < 64; i++) | |
10840 | if ((val <<= 1) < 0) | |
10841 | break; | |
10842 | } | |
10843 | #endif | |
10844 | ||
10845 | fprintf (file, "%d", i + 1); | |
9854d9ed | 10846 | return; |
9878760c | 10847 | |
9854d9ed RK |
10848 | case 'X': |
10849 | if (GET_CODE (x) == MEM | |
4d588c14 | 10850 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 10851 | putc ('x', file); |
9854d9ed | 10852 | return; |
9878760c | 10853 | |
9854d9ed RK |
10854 | case 'Y': |
10855 | /* Like 'L', for third word of TImode */ | |
10856 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10857 | fputs (reg_names[REGNO (x) + 2], file); |
9854d9ed | 10858 | else if (GET_CODE (x) == MEM) |
9878760c | 10859 | { |
9854d9ed RK |
10860 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
10861 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10862 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 10863 | else |
d7624dc0 | 10864 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 10865 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10866 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10867 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
10868 | } |
10869 | return; | |
f676971a | 10870 | |
9878760c | 10871 | case 'z': |
b4ac57ab RS |
10872 | /* X is a SYMBOL_REF. Write out the name preceded by a |
10873 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
10874 | names. If we are configured for System V (or the embedded ABI) on |
10875 | the PowerPC, do not emit the period, since those systems do not use | |
10876 | TOCs and the like. */ | |
9878760c RK |
10877 | if (GET_CODE (x) != SYMBOL_REF) |
10878 | abort (); | |
10879 | ||
c4ad648e AM |
10880 | /* Mark the decl as referenced so that cgraph will output the |
10881 | function. */ | |
9bf6462a | 10882 | if (SYMBOL_REF_DECL (x)) |
c4ad648e | 10883 | mark_decl_referenced (SYMBOL_REF_DECL (x)); |
9bf6462a | 10884 | |
85b776df | 10885 | /* For macho, check to see if we need a stub. */ |
f9da97f0 AP |
10886 | if (TARGET_MACHO) |
10887 | { | |
10888 | const char *name = XSTR (x, 0); | |
a031e781 | 10889 | #if TARGET_MACHO |
3b48085e | 10890 | if (MACHOPIC_INDIRECT |
11abc112 MM |
10891 | && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION) |
10892 | name = machopic_indirection_name (x, /*stub_p=*/true); | |
f9da97f0 AP |
10893 | #endif |
10894 | assemble_name (file, name); | |
10895 | } | |
85b776df | 10896 | else if (!DOT_SYMBOLS) |
9739c90c | 10897 | assemble_name (file, XSTR (x, 0)); |
85b776df AM |
10898 | else |
10899 | rs6000_output_function_entry (file, XSTR (x, 0)); | |
9878760c RK |
10900 | return; |
10901 | ||
9854d9ed RK |
10902 | case 'Z': |
10903 | /* Like 'L', for last word of TImode. */ | |
10904 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10905 | fputs (reg_names[REGNO (x) + 3], file); |
9854d9ed RK |
10906 | else if (GET_CODE (x) == MEM) |
10907 | { | |
10908 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
10909 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10910 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 10911 | else |
d7624dc0 | 10912 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 10913 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10914 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10915 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 10916 | } |
5c23c401 | 10917 | return; |
0ac081f6 | 10918 | |
a3170dc6 | 10919 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
10920 | case 'y': |
10921 | { | |
10922 | rtx tmp; | |
10923 | ||
10924 | if (GET_CODE (x) != MEM) | |
10925 | abort (); | |
10926 | ||
10927 | tmp = XEXP (x, 0); | |
10928 | ||
993f19a8 | 10929 | if (TARGET_E500) |
a3170dc6 AH |
10930 | { |
10931 | /* Handle [reg]. */ | |
10932 | if (GET_CODE (tmp) == REG) | |
10933 | { | |
10934 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
10935 | break; | |
10936 | } | |
10937 | /* Handle [reg+UIMM]. */ | |
10938 | else if (GET_CODE (tmp) == PLUS && | |
10939 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
10940 | { | |
10941 | int x; | |
10942 | ||
10943 | if (GET_CODE (XEXP (tmp, 0)) != REG) | |
10944 | abort (); | |
10945 | ||
10946 | x = INTVAL (XEXP (tmp, 1)); | |
10947 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
10948 | break; | |
10949 | } | |
10950 | ||
10951 | /* Fall through. Must be [reg+reg]. */ | |
10952 | } | |
850e8d3d DN |
10953 | if (TARGET_ALTIVEC |
10954 | && GET_CODE (tmp) == AND | |
10955 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT | |
10956 | && INTVAL (XEXP (tmp, 1)) == -16) | |
10957 | tmp = XEXP (tmp, 0); | |
0ac081f6 | 10958 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 10959 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
10960 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
10961 | { | |
10962 | if (REGNO (XEXP (tmp, 0)) == 0) | |
10963 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
10964 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
10965 | else | |
10966 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
10967 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
10968 | } | |
10969 | else | |
10970 | abort (); | |
10971 | break; | |
10972 | } | |
f676971a | 10973 | |
9878760c RK |
10974 | case 0: |
10975 | if (GET_CODE (x) == REG) | |
10976 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
10977 | else if (GET_CODE (x) == MEM) | |
10978 | { | |
10979 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
10980 | know the width from the mode. */ | |
10981 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
10982 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
10983 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10984 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
10985 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
10986 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10987 | else |
a54d04b7 | 10988 | output_address (XEXP (x, 0)); |
9878760c RK |
10989 | } |
10990 | else | |
a54d04b7 | 10991 | output_addr_const (file, x); |
a85d226b | 10992 | return; |
9878760c | 10993 | |
c4501e62 JJ |
10994 | case '&': |
10995 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
10996 | return; | |
10997 | ||
9878760c RK |
10998 | default: |
10999 | output_operand_lossage ("invalid %%xn code"); | |
11000 | } | |
11001 | } | |
11002 | \f | |
11003 | /* Print the address of an operand. */ | |
11004 | ||
11005 | void | |
a2369ed3 | 11006 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
11007 | { |
11008 | if (GET_CODE (x) == REG) | |
4697a36c | 11009 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
11010 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
11011 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
11012 | { |
11013 | output_addr_const (file, x); | |
ba5e43aa | 11014 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
11015 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
11016 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 11017 | else if (TARGET_TOC) |
a4f6c312 | 11018 | abort (); |
9878760c RK |
11019 | } |
11020 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
11021 | { | |
11022 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
11023 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
11024 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 11025 | else |
4697a36c MM |
11026 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
11027 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
11028 | } |
11029 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
11030 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
11031 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
11032 | #if TARGET_ELF |
11033 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 11034 | && CONSTANT_P (XEXP (x, 1))) |
4697a36c MM |
11035 | { |
11036 | output_addr_const (file, XEXP (x, 1)); | |
11037 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
11038 | } | |
c859cda6 DJ |
11039 | #endif |
11040 | #if TARGET_MACHO | |
11041 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 11042 | && CONSTANT_P (XEXP (x, 1))) |
c859cda6 DJ |
11043 | { |
11044 | fprintf (file, "lo16("); | |
11045 | output_addr_const (file, XEXP (x, 1)); | |
11046 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
11047 | } | |
3cb999d8 | 11048 | #endif |
4d588c14 | 11049 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 11050 | { |
2bfcf297 | 11051 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 11052 | { |
2bfcf297 DB |
11053 | rtx contains_minus = XEXP (x, 1); |
11054 | rtx minus, symref; | |
11055 | const char *name; | |
f676971a | 11056 | |
9ebbca7d | 11057 | /* Find the (minus (sym) (toc)) buried in X, and temporarily |
a4f6c312 | 11058 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
11059 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
11060 | contains_minus = XEXP (contains_minus, 0); | |
11061 | ||
2bfcf297 DB |
11062 | minus = XEXP (contains_minus, 0); |
11063 | symref = XEXP (minus, 0); | |
11064 | XEXP (contains_minus, 0) = symref; | |
11065 | if (TARGET_ELF) | |
11066 | { | |
11067 | char *newname; | |
11068 | ||
11069 | name = XSTR (symref, 0); | |
11070 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
11071 | strcpy (newname, name); | |
11072 | strcat (newname, "@toc"); | |
11073 | XSTR (symref, 0) = newname; | |
11074 | } | |
11075 | output_addr_const (file, XEXP (x, 1)); | |
11076 | if (TARGET_ELF) | |
11077 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
11078 | XEXP (contains_minus, 0) = minus; |
11079 | } | |
11080 | else | |
11081 | output_addr_const (file, XEXP (x, 1)); | |
11082 | ||
11083 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
11084 | } | |
9878760c RK |
11085 | else |
11086 | abort (); | |
11087 | } | |
11088 | \f | |
88cad84b | 11089 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
11090 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
11091 | is defined. It also needs to handle DI-mode objects on 64-bit | |
11092 | targets. */ | |
11093 | ||
11094 | static bool | |
a2369ed3 | 11095 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
11096 | { |
11097 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
11098 | /* Special handling for SI values. */ | |
11099 | if (size == 4 && aligned_p) | |
11100 | { | |
a2369ed3 | 11101 | extern int in_toc_section (void); |
301d03af | 11102 | static int recurse = 0; |
f676971a | 11103 | |
301d03af RS |
11104 | /* For -mrelocatable, we mark all addresses that need to be fixed up |
11105 | in the .fixup section. */ | |
11106 | if (TARGET_RELOCATABLE | |
11107 | && !in_toc_section () | |
11108 | && !in_text_section () | |
642af3be | 11109 | && !in_unlikely_text_section () |
301d03af RS |
11110 | && !recurse |
11111 | && GET_CODE (x) != CONST_INT | |
11112 | && GET_CODE (x) != CONST_DOUBLE | |
11113 | && CONSTANT_P (x)) | |
11114 | { | |
11115 | char buf[256]; | |
11116 | ||
11117 | recurse = 1; | |
11118 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
11119 | fixuplabelno++; | |
11120 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
11121 | fprintf (asm_out_file, "\t.long\t("); | |
11122 | output_addr_const (asm_out_file, x); | |
11123 | fprintf (asm_out_file, ")@fixup\n"); | |
11124 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
11125 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
11126 | fprintf (asm_out_file, "\t.long\t"); | |
11127 | assemble_name (asm_out_file, buf); | |
11128 | fprintf (asm_out_file, "\n\t.previous\n"); | |
11129 | recurse = 0; | |
11130 | return true; | |
11131 | } | |
11132 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
11133 | address into the address of the descriptor, not the function | |
11134 | itself. */ | |
11135 | else if (GET_CODE (x) == SYMBOL_REF | |
11136 | && XSTR (x, 0)[0] == '.' | |
11137 | && DEFAULT_ABI == ABI_AIX) | |
11138 | { | |
11139 | const char *name = XSTR (x, 0); | |
11140 | while (*name == '.') | |
11141 | name++; | |
11142 | ||
11143 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
11144 | return true; | |
11145 | } | |
11146 | } | |
11147 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
11148 | return default_assemble_integer (x, size, aligned_p); | |
11149 | } | |
93638d7a AM |
11150 | |
11151 | #ifdef HAVE_GAS_HIDDEN | |
11152 | /* Emit an assembler directive to set symbol visibility for DECL to | |
11153 | VISIBILITY_TYPE. */ | |
11154 | ||
5add3202 | 11155 | static void |
a2369ed3 | 11156 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 11157 | { |
93638d7a AM |
11158 | /* Functions need to have their entry point symbol visibility set as |
11159 | well as their descriptor symbol visibility. */ | |
85b776df AM |
11160 | if (DEFAULT_ABI == ABI_AIX |
11161 | && DOT_SYMBOLS | |
11162 | && TREE_CODE (decl) == FUNCTION_DECL) | |
93638d7a | 11163 | { |
25fdb4dc | 11164 | static const char * const visibility_types[] = { |
c4ad648e | 11165 | NULL, "internal", "hidden", "protected" |
25fdb4dc RH |
11166 | }; |
11167 | ||
11168 | const char *name, *type; | |
93638d7a AM |
11169 | |
11170 | name = ((* targetm.strip_name_encoding) | |
11171 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 11172 | type = visibility_types[vis]; |
93638d7a | 11173 | |
25fdb4dc RH |
11174 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
11175 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 11176 | } |
25fdb4dc RH |
11177 | else |
11178 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
11179 | } |
11180 | #endif | |
301d03af | 11181 | \f |
39a10a29 | 11182 | enum rtx_code |
a2369ed3 | 11183 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
11184 | { |
11185 | /* Reversal of FP compares takes care -- an ordered compare | |
11186 | becomes an unordered compare and vice versa. */ | |
f676971a | 11187 | if (mode == CCFPmode |
bc9ec0e0 GK |
11188 | && (!flag_finite_math_only |
11189 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
11190 | || code == UNEQ || code == LTGT)) | |
bab6226b | 11191 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 11192 | else |
bab6226b | 11193 | return reverse_condition (code); |
39a10a29 GK |
11194 | } |
11195 | ||
39a10a29 GK |
11196 | /* Generate a compare for CODE. Return a brand-new rtx that |
11197 | represents the result of the compare. */ | |
a4f6c312 | 11198 | |
39a10a29 | 11199 | static rtx |
a2369ed3 | 11200 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
11201 | { |
11202 | enum machine_mode comp_mode; | |
11203 | rtx compare_result; | |
11204 | ||
11205 | if (rs6000_compare_fp_p) | |
11206 | comp_mode = CCFPmode; | |
11207 | else if (code == GTU || code == LTU | |
c4ad648e | 11208 | || code == GEU || code == LEU) |
39a10a29 | 11209 | comp_mode = CCUNSmode; |
60934f9c NS |
11210 | else if ((code == EQ || code == NE) |
11211 | && GET_CODE (rs6000_compare_op0) == SUBREG | |
11212 | && GET_CODE (rs6000_compare_op1) == SUBREG | |
11213 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0) | |
11214 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1)) | |
11215 | /* These are unsigned values, perhaps there will be a later | |
11216 | ordering compare that can be shared with this one. | |
11217 | Unfortunately we cannot detect the signedness of the operands | |
11218 | for non-subregs. */ | |
11219 | comp_mode = CCUNSmode; | |
39a10a29 GK |
11220 | else |
11221 | comp_mode = CCmode; | |
11222 | ||
11223 | /* First, the compare. */ | |
11224 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
11225 | |
11226 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
11227 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
11228 | && rs6000_compare_fp_p) | |
a3170dc6 AH |
11229 | { |
11230 | rtx cmp, or1, or2, or_result, compare_result2; | |
4d4cbc0e AH |
11231 | enum machine_mode op_mode = GET_MODE (rs6000_compare_op0); |
11232 | ||
11233 | if (op_mode == VOIDmode) | |
11234 | op_mode = GET_MODE (rs6000_compare_op1); | |
a3170dc6 | 11235 | |
423c1189 AH |
11236 | /* Note: The E500 comparison instructions set the GT bit (x + |
11237 | 1), on success. This explains the mess. */ | |
11238 | ||
a3170dc6 AH |
11239 | switch (code) |
11240 | { | |
423c1189 | 11241 | case EQ: case UNEQ: case NE: case LTGT: |
4d4cbc0e AH |
11242 | if (op_mode == SFmode) |
11243 | cmp = flag_finite_math_only | |
11244 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, | |
11245 | rs6000_compare_op1) | |
11246 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
11247 | rs6000_compare_op1); | |
11248 | else if (op_mode == DFmode) | |
11249 | cmp = flag_finite_math_only | |
11250 | ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, | |
11251 | rs6000_compare_op1) | |
11252 | : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, | |
11253 | rs6000_compare_op1); | |
11254 | else abort (); | |
a3170dc6 | 11255 | break; |
423c1189 | 11256 | case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: |
4d4cbc0e AH |
11257 | if (op_mode == SFmode) |
11258 | cmp = flag_finite_math_only | |
11259 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, | |
11260 | rs6000_compare_op1) | |
11261 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
11262 | rs6000_compare_op1); | |
11263 | else if (op_mode == DFmode) | |
11264 | cmp = flag_finite_math_only | |
11265 | ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, | |
11266 | rs6000_compare_op1) | |
11267 | : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, | |
11268 | rs6000_compare_op1); | |
11269 | else abort (); | |
a3170dc6 | 11270 | break; |
423c1189 | 11271 | case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: |
4d4cbc0e AH |
11272 | if (op_mode == SFmode) |
11273 | cmp = flag_finite_math_only | |
11274 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, | |
11275 | rs6000_compare_op1) | |
11276 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
11277 | rs6000_compare_op1); | |
11278 | else if (op_mode == DFmode) | |
11279 | cmp = flag_finite_math_only | |
11280 | ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, | |
11281 | rs6000_compare_op1) | |
11282 | : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, | |
11283 | rs6000_compare_op1); | |
11284 | else abort (); | |
a3170dc6 | 11285 | break; |
4d4cbc0e AH |
11286 | default: |
11287 | abort (); | |
a3170dc6 AH |
11288 | } |
11289 | ||
11290 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
11291 | if (code == LE || code == GE || code == LEU || code == GEU) | |
11292 | { | |
a3170dc6 AH |
11293 | emit_insn (cmp); |
11294 | ||
11295 | switch (code) | |
11296 | { | |
11297 | case LE: code = LT; break; | |
11298 | case GE: code = GT; break; | |
11299 | case LEU: code = LT; break; | |
11300 | case GEU: code = GT; break; | |
11301 | default: abort (); | |
11302 | } | |
11303 | ||
11304 | or1 = gen_reg_rtx (SImode); | |
11305 | or2 = gen_reg_rtx (SImode); | |
11306 | or_result = gen_reg_rtx (CCEQmode); | |
11307 | compare_result2 = gen_reg_rtx (CCFPmode); | |
11308 | ||
11309 | /* Do the EQ. */ | |
4d4cbc0e AH |
11310 | if (op_mode == SFmode) |
11311 | cmp = flag_finite_math_only | |
11312 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, | |
11313 | rs6000_compare_op1) | |
11314 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
11315 | rs6000_compare_op1); | |
11316 | else if (op_mode == DFmode) | |
11317 | cmp = flag_finite_math_only | |
11318 | ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, | |
11319 | rs6000_compare_op1) | |
11320 | : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, | |
11321 | rs6000_compare_op1); | |
11322 | else abort (); | |
a3170dc6 AH |
11323 | emit_insn (cmp); |
11324 | ||
423c1189 AH |
11325 | or1 = gen_rtx_GT (SImode, compare_result, const0_rtx); |
11326 | or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx); | |
a3170dc6 AH |
11327 | |
11328 | /* OR them together. */ | |
11329 | cmp = gen_rtx_SET (VOIDmode, or_result, | |
11330 | gen_rtx_COMPARE (CCEQmode, | |
11331 | gen_rtx_IOR (SImode, or1, or2), | |
11332 | const_true_rtx)); | |
11333 | compare_result = or_result; | |
11334 | code = EQ; | |
11335 | } | |
11336 | else | |
11337 | { | |
a3170dc6 | 11338 | if (code == NE || code == LTGT) |
a3170dc6 | 11339 | code = NE; |
423c1189 AH |
11340 | else |
11341 | code = EQ; | |
a3170dc6 AH |
11342 | } |
11343 | ||
11344 | emit_insn (cmp); | |
11345 | } | |
11346 | else | |
11347 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
11348 | gen_rtx_COMPARE (comp_mode, | |
f676971a | 11349 | rs6000_compare_op0, |
a3170dc6 | 11350 | rs6000_compare_op1))); |
f676971a | 11351 | |
ca5adc63 | 11352 | /* Some kinds of FP comparisons need an OR operation; |
bc9ec0e0 | 11353 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 11354 | if (rs6000_compare_fp_p |
bc9ec0e0 | 11355 | && ! flag_finite_math_only |
993f19a8 | 11356 | && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) |
39a10a29 GK |
11357 | && (code == LE || code == GE |
11358 | || code == UNEQ || code == LTGT | |
11359 | || code == UNGT || code == UNLT)) | |
11360 | { | |
11361 | enum rtx_code or1, or2; | |
11362 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
11363 | rtx or_result = gen_reg_rtx (CCEQmode); | |
f676971a | 11364 | |
39a10a29 GK |
11365 | switch (code) |
11366 | { | |
11367 | case LE: or1 = LT; or2 = EQ; break; | |
11368 | case GE: or1 = GT; or2 = EQ; break; | |
11369 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
11370 | case LTGT: or1 = LT; or2 = GT; break; | |
11371 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
11372 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
11373 | default: abort (); | |
11374 | } | |
11375 | validate_condition_mode (or1, comp_mode); | |
11376 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
11377 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
11378 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
11379 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
11380 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
11381 | const_true_rtx); | |
11382 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
11383 | ||
11384 | compare_result = or_result; | |
11385 | code = EQ; | |
11386 | } | |
11387 | ||
11388 | validate_condition_mode (code, GET_MODE (compare_result)); | |
f676971a | 11389 | |
1c563bed | 11390 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
11391 | } |
11392 | ||
11393 | ||
11394 | /* Emit the RTL for an sCOND pattern. */ | |
11395 | ||
11396 | void | |
a2369ed3 | 11397 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
11398 | { |
11399 | rtx condition_rtx; | |
11400 | enum machine_mode op_mode; | |
b7053a3f | 11401 | enum rtx_code cond_code; |
39a10a29 GK |
11402 | |
11403 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
11404 | cond_code = GET_CODE (condition_rtx); |
11405 | ||
423c1189 AH |
11406 | if (TARGET_E500 && rs6000_compare_fp_p |
11407 | && !TARGET_FPRS && TARGET_HARD_FLOAT) | |
11408 | { | |
11409 | rtx t; | |
11410 | ||
11411 | PUT_MODE (condition_rtx, SImode); | |
11412 | t = XEXP (condition_rtx, 0); | |
11413 | ||
11414 | if (cond_code != NE && cond_code != EQ) | |
11415 | abort (); | |
11416 | ||
11417 | if (cond_code == NE) | |
6b1fedc3 | 11418 | emit_insn (gen_e500_flip_eq_bit (t, t)); |
423c1189 | 11419 | |
6b1fedc3 | 11420 | emit_insn (gen_move_from_CR_eq_bit (result, t)); |
423c1189 AH |
11421 | return; |
11422 | } | |
11423 | ||
b7053a3f GK |
11424 | if (cond_code == NE |
11425 | || cond_code == GE || cond_code == LE | |
11426 | || cond_code == GEU || cond_code == LEU | |
11427 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
11428 | { | |
11429 | rtx not_result = gen_reg_rtx (CCEQmode); | |
11430 | rtx not_op, rev_cond_rtx; | |
11431 | enum machine_mode cc_mode; | |
f676971a | 11432 | |
b7053a3f GK |
11433 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); |
11434 | ||
1c563bed | 11435 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 11436 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
11437 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
11438 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
11439 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
11440 | } | |
39a10a29 GK |
11441 | |
11442 | op_mode = GET_MODE (rs6000_compare_op0); | |
11443 | if (op_mode == VOIDmode) | |
11444 | op_mode = GET_MODE (rs6000_compare_op1); | |
11445 | ||
11446 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
11447 | { | |
11448 | PUT_MODE (condition_rtx, DImode); | |
11449 | convert_move (result, condition_rtx, 0); | |
11450 | } | |
11451 | else | |
11452 | { | |
11453 | PUT_MODE (condition_rtx, SImode); | |
11454 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
11455 | } | |
11456 | } | |
11457 | ||
39a10a29 GK |
11458 | /* Emit a branch of kind CODE to location LOC. */ |
11459 | ||
11460 | void | |
a2369ed3 | 11461 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
11462 | { |
11463 | rtx condition_rtx, loc_ref; | |
11464 | ||
11465 | condition_rtx = rs6000_generate_compare (code); | |
11466 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
11467 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
11468 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
11469 | loc_ref, pc_rtx))); | |
11470 | } | |
11471 | ||
12a4e8c5 GK |
11472 | /* Return the string to output a conditional branch to LABEL, which is |
11473 | the operand number of the label, or -1 if the branch is really a | |
f676971a | 11474 | conditional return. |
12a4e8c5 GK |
11475 | |
11476 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
11477 | condition code register and its mode specifies what kind of | |
11478 | comparison we made. | |
11479 | ||
a0ab749a | 11480 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
11481 | |
11482 | INSN is the insn. */ | |
11483 | ||
11484 | char * | |
a2369ed3 | 11485 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
11486 | { |
11487 | static char string[64]; | |
11488 | enum rtx_code code = GET_CODE (op); | |
11489 | rtx cc_reg = XEXP (op, 0); | |
11490 | enum machine_mode mode = GET_MODE (cc_reg); | |
11491 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 11492 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
11493 | int really_reversed = reversed ^ need_longbranch; |
11494 | char *s = string; | |
11495 | const char *ccode; | |
11496 | const char *pred; | |
11497 | rtx note; | |
11498 | ||
39a10a29 GK |
11499 | validate_condition_mode (code, mode); |
11500 | ||
11501 | /* Work out which way this really branches. We could use | |
11502 | reverse_condition_maybe_unordered here always but this | |
11503 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 11504 | if (really_reversed) |
de40e1df DJ |
11505 | { |
11506 | /* Reversal of FP compares takes care -- an ordered compare | |
11507 | becomes an unordered compare and vice versa. */ | |
11508 | if (mode == CCFPmode) | |
11509 | code = reverse_condition_maybe_unordered (code); | |
11510 | else | |
11511 | code = reverse_condition (code); | |
11512 | } | |
12a4e8c5 | 11513 | |
993f19a8 | 11514 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
11515 | { |
11516 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
11517 | to the GT bit. */ | |
11518 | if (code == EQ) | |
11519 | /* Opposite of GT. */ | |
a3170dc6 | 11520 | code = GT; |
423c1189 AH |
11521 | else if (code == NE) |
11522 | code = UNLE; | |
a3170dc6 AH |
11523 | else |
11524 | abort (); | |
11525 | } | |
11526 | ||
39a10a29 | 11527 | switch (code) |
12a4e8c5 GK |
11528 | { |
11529 | /* Not all of these are actually distinct opcodes, but | |
11530 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
11531 | case NE: case LTGT: |
11532 | ccode = "ne"; break; | |
11533 | case EQ: case UNEQ: | |
11534 | ccode = "eq"; break; | |
f676971a | 11535 | case GE: case GEU: |
50a0b056 | 11536 | ccode = "ge"; break; |
f676971a | 11537 | case GT: case GTU: case UNGT: |
50a0b056 | 11538 | ccode = "gt"; break; |
f676971a | 11539 | case LE: case LEU: |
50a0b056 | 11540 | ccode = "le"; break; |
f676971a | 11541 | case LT: case LTU: case UNLT: |
50a0b056 | 11542 | ccode = "lt"; break; |
12a4e8c5 GK |
11543 | case UNORDERED: ccode = "un"; break; |
11544 | case ORDERED: ccode = "nu"; break; | |
11545 | case UNGE: ccode = "nl"; break; | |
11546 | case UNLE: ccode = "ng"; break; | |
11547 | default: | |
a4f6c312 | 11548 | abort (); |
12a4e8c5 | 11549 | } |
f676971a EC |
11550 | |
11551 | /* Maybe we have a guess as to how likely the branch is. | |
94a54f47 | 11552 | The old mnemonics don't have a way to specify this information. */ |
f4857b9b | 11553 | pred = ""; |
12a4e8c5 GK |
11554 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
11555 | if (note != NULL_RTX) | |
11556 | { | |
11557 | /* PROB is the difference from 50%. */ | |
11558 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
11559 | |
11560 | /* Only hint for highly probable/improbable branches on newer | |
11561 | cpus as static prediction overrides processor dynamic | |
11562 | prediction. For older cpus we may as well always hint, but | |
11563 | assume not taken for branches that are very close to 50% as a | |
11564 | mispredicted taken branch is more expensive than a | |
f676971a | 11565 | mispredicted not-taken branch. */ |
ec507f2d | 11566 | if (rs6000_always_hint |
f4857b9b AM |
11567 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) |
11568 | { | |
11569 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
11570 | && ((prob > 0) ^ need_longbranch)) | |
c4ad648e | 11571 | pred = "+"; |
f4857b9b AM |
11572 | else |
11573 | pred = "-"; | |
11574 | } | |
12a4e8c5 | 11575 | } |
12a4e8c5 GK |
11576 | |
11577 | if (label == NULL) | |
94a54f47 | 11578 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 11579 | else |
94a54f47 | 11580 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 11581 | |
37c67319 | 11582 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 11583 | Assume they'd only be the first character.... */ |
37c67319 GK |
11584 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
11585 | *s++ = '%'; | |
94a54f47 | 11586 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
11587 | |
11588 | if (label != NULL) | |
11589 | { | |
11590 | /* If the branch distance was too far, we may have to use an | |
11591 | unconditional branch to go the distance. */ | |
11592 | if (need_longbranch) | |
44518ddd | 11593 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
11594 | else |
11595 | s += sprintf (s, ",%s", label); | |
11596 | } | |
11597 | ||
11598 | return string; | |
11599 | } | |
50a0b056 | 11600 | |
6b1fedc3 | 11601 | /* Return the string to flip the EQ bit on a CR. */ |
423c1189 | 11602 | char * |
6b1fedc3 | 11603 | output_e500_flip_eq_bit (rtx dst, rtx src) |
423c1189 AH |
11604 | { |
11605 | static char string[64]; | |
11606 | int a, b; | |
11607 | ||
11608 | if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst)) | |
11609 | || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src))) | |
11610 | abort (); | |
11611 | ||
6b1fedc3 AH |
11612 | /* EQ bit. */ |
11613 | a = 4 * (REGNO (dst) - CR0_REGNO) + 2; | |
11614 | b = 4 * (REGNO (src) - CR0_REGNO) + 2; | |
423c1189 AH |
11615 | |
11616 | sprintf (string, "crnot %d,%d", a, b); | |
11617 | return string; | |
11618 | } | |
11619 | ||
21213b4c DP |
11620 | /* Return insn index for the vector compare instruction for given CODE, |
11621 | and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is | |
11622 | not available. */ | |
11623 | ||
11624 | static int | |
94ff898d | 11625 | get_vec_cmp_insn (enum rtx_code code, |
21213b4c DP |
11626 | enum machine_mode dest_mode, |
11627 | enum machine_mode op_mode) | |
11628 | { | |
11629 | if (!TARGET_ALTIVEC) | |
11630 | return INSN_NOT_AVAILABLE; | |
11631 | ||
11632 | switch (code) | |
11633 | { | |
11634 | case EQ: | |
11635 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
11636 | return UNSPEC_VCMPEQUB; | |
11637 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
11638 | return UNSPEC_VCMPEQUH; | |
11639 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
11640 | return UNSPEC_VCMPEQUW; | |
11641 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
11642 | return UNSPEC_VCMPEQFP; | |
11643 | break; | |
11644 | case GE: | |
11645 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
11646 | return UNSPEC_VCMPGEFP; | |
11647 | case GT: | |
11648 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
11649 | return UNSPEC_VCMPGTSB; | |
11650 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
11651 | return UNSPEC_VCMPGTSH; | |
11652 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
11653 | return UNSPEC_VCMPGTSW; | |
11654 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
11655 | return UNSPEC_VCMPGTFP; | |
11656 | break; | |
11657 | case GTU: | |
11658 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
11659 | return UNSPEC_VCMPGTUB; | |
11660 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
11661 | return UNSPEC_VCMPGTUH; | |
11662 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
11663 | return UNSPEC_VCMPGTUW; | |
11664 | break; | |
11665 | default: | |
11666 | break; | |
11667 | } | |
11668 | return INSN_NOT_AVAILABLE; | |
11669 | } | |
11670 | ||
11671 | /* Emit vector compare for operands OP0 and OP1 using code RCODE. | |
11672 | DMODE is expected destination mode. This is a recursive function. */ | |
11673 | ||
11674 | static rtx | |
11675 | rs6000_emit_vector_compare (enum rtx_code rcode, | |
11676 | rtx op0, rtx op1, | |
11677 | enum machine_mode dmode) | |
11678 | { | |
11679 | int vec_cmp_insn; | |
11680 | rtx mask; | |
11681 | enum machine_mode dest_mode; | |
11682 | enum machine_mode op_mode = GET_MODE (op1); | |
11683 | ||
11684 | #ifdef ENABLE_CHECKING | |
11685 | if (!TARGET_ALTIVEC) | |
11686 | abort (); | |
11687 | ||
11688 | if (GET_MODE (op0) != GET_MODE (op1)) | |
11689 | abort (); | |
11690 | #endif | |
11691 | ||
11692 | /* Floating point vector compare instructions uses destination V4SImode. | |
11693 | Move destination to appropriate mode later. */ | |
11694 | if (dmode == V4SFmode) | |
11695 | dest_mode = V4SImode; | |
11696 | else | |
11697 | dest_mode = dmode; | |
11698 | ||
11699 | mask = gen_reg_rtx (dest_mode); | |
11700 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
11701 | ||
11702 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
11703 | { | |
11704 | bool swap_operands = false; | |
11705 | bool try_again = false; | |
11706 | switch (rcode) | |
11707 | { | |
11708 | case LT: | |
11709 | rcode = GT; | |
11710 | swap_operands = true; | |
11711 | try_again = true; | |
11712 | break; | |
11713 | case LTU: | |
11714 | rcode = GTU; | |
11715 | swap_operands = true; | |
11716 | try_again = true; | |
11717 | break; | |
11718 | case NE: | |
11719 | /* Treat A != B as ~(A==B). */ | |
11720 | { | |
11721 | enum insn_code nor_code; | |
11722 | rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
11723 | dest_mode); | |
94ff898d | 11724 | |
21213b4c DP |
11725 | nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code; |
11726 | if (nor_code == CODE_FOR_nothing) | |
11727 | abort (); | |
11728 | emit_insn (GEN_FCN (nor_code) (mask, eq_rtx)); | |
11729 | ||
11730 | if (dmode != dest_mode) | |
11731 | { | |
11732 | rtx temp = gen_reg_rtx (dest_mode); | |
11733 | convert_move (temp, mask, 0); | |
11734 | return temp; | |
11735 | } | |
11736 | return mask; | |
11737 | } | |
11738 | break; | |
11739 | case GE: | |
11740 | case GEU: | |
11741 | case LE: | |
11742 | case LEU: | |
11743 | /* Try GT/GTU/LT/LTU OR EQ */ | |
11744 | { | |
11745 | rtx c_rtx, eq_rtx; | |
11746 | enum insn_code ior_code; | |
11747 | enum rtx_code new_code; | |
11748 | ||
11749 | if (rcode == GE) | |
11750 | new_code = GT; | |
11751 | else if (rcode == GEU) | |
11752 | new_code = GTU; | |
11753 | else if (rcode == LE) | |
11754 | new_code = LT; | |
11755 | else if (rcode == LEU) | |
11756 | new_code = LTU; | |
11757 | else | |
11758 | abort (); | |
11759 | ||
11760 | c_rtx = rs6000_emit_vector_compare (new_code, | |
11761 | op0, op1, dest_mode); | |
11762 | eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
11763 | dest_mode); | |
11764 | ||
11765 | ior_code = ior_optab->handlers[(int)dest_mode].insn_code; | |
11766 | if (ior_code == CODE_FOR_nothing) | |
11767 | abort (); | |
11768 | emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx)); | |
11769 | if (dmode != dest_mode) | |
11770 | { | |
11771 | rtx temp = gen_reg_rtx (dest_mode); | |
11772 | convert_move (temp, mask, 0); | |
11773 | return temp; | |
11774 | } | |
11775 | return mask; | |
11776 | } | |
11777 | break; | |
11778 | default: | |
11779 | abort (); | |
11780 | } | |
11781 | ||
11782 | if (try_again) | |
11783 | { | |
11784 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
11785 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
11786 | /* You only get two chances. */ | |
11787 | abort (); | |
11788 | } | |
11789 | ||
11790 | if (swap_operands) | |
11791 | { | |
11792 | rtx tmp; | |
11793 | tmp = op0; | |
11794 | op0 = op1; | |
11795 | op1 = tmp; | |
11796 | } | |
11797 | } | |
11798 | ||
11799 | emit_insn (gen_rtx_fmt_ee (SET, | |
11800 | VOIDmode, | |
11801 | mask, | |
11802 | gen_rtx_fmt_Ei (UNSPEC, dest_mode, | |
11803 | gen_rtvec (2, op0, op1), | |
11804 | vec_cmp_insn))); | |
11805 | if (dmode != dest_mode) | |
11806 | { | |
11807 | rtx temp = gen_reg_rtx (dest_mode); | |
11808 | convert_move (temp, mask, 0); | |
11809 | return temp; | |
11810 | } | |
11811 | return mask; | |
11812 | } | |
11813 | ||
11814 | /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if | |
11815 | valid insn doesn exist for given mode. */ | |
11816 | ||
11817 | static int | |
11818 | get_vsel_insn (enum machine_mode mode) | |
11819 | { | |
11820 | switch (mode) | |
11821 | { | |
11822 | case V4SImode: | |
11823 | return UNSPEC_VSEL4SI; | |
11824 | break; | |
11825 | case V4SFmode: | |
11826 | return UNSPEC_VSEL4SF; | |
11827 | break; | |
11828 | case V8HImode: | |
11829 | return UNSPEC_VSEL8HI; | |
11830 | break; | |
11831 | case V16QImode: | |
11832 | return UNSPEC_VSEL16QI; | |
11833 | break; | |
11834 | default: | |
11835 | return INSN_NOT_AVAILABLE; | |
11836 | break; | |
11837 | } | |
11838 | return INSN_NOT_AVAILABLE; | |
11839 | } | |
11840 | ||
11841 | /* Emit vector select insn where DEST is destination using | |
11842 | operands OP1, OP2 and MASK. */ | |
11843 | ||
11844 | static void | |
11845 | rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask) | |
11846 | { | |
11847 | rtx t, temp; | |
11848 | enum machine_mode dest_mode = GET_MODE (dest); | |
11849 | int vsel_insn_index = get_vsel_insn (GET_MODE (dest)); | |
11850 | ||
11851 | temp = gen_reg_rtx (dest_mode); | |
94ff898d | 11852 | |
21213b4c DP |
11853 | t = gen_rtx_fmt_ee (SET, VOIDmode, temp, |
11854 | gen_rtx_fmt_Ei (UNSPEC, dest_mode, | |
11855 | gen_rtvec (3, op1, op2, mask), | |
11856 | vsel_insn_index)); | |
11857 | emit_insn (t); | |
11858 | emit_move_insn (dest, temp); | |
11859 | return; | |
11860 | } | |
11861 | ||
94ff898d | 11862 | /* Emit vector conditional expression. |
21213b4c DP |
11863 | DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands. |
11864 | CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */ | |
11865 | ||
11866 | int | |
11867 | rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2, | |
11868 | rtx cond, rtx cc_op0, rtx cc_op1) | |
11869 | { | |
11870 | enum machine_mode dest_mode = GET_MODE (dest); | |
11871 | enum rtx_code rcode = GET_CODE (cond); | |
11872 | rtx mask; | |
11873 | ||
11874 | if (!TARGET_ALTIVEC) | |
11875 | return 0; | |
11876 | ||
11877 | /* Get the vector mask for the given relational operations. */ | |
11878 | mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode); | |
11879 | ||
11880 | rs6000_emit_vector_select (dest, op1, op2, mask); | |
11881 | ||
11882 | return 1; | |
11883 | } | |
11884 | ||
50a0b056 GK |
11885 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the |
11886 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
11887 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 11888 | |
50a0b056 | 11889 | int |
a2369ed3 | 11890 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
11891 | { |
11892 | enum rtx_code code = GET_CODE (op); | |
11893 | rtx op0 = rs6000_compare_op0; | |
11894 | rtx op1 = rs6000_compare_op1; | |
11895 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
11896 | enum machine_mode compare_mode = GET_MODE (op0); |
11897 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 | 11898 | rtx temp; |
add2402e | 11899 | bool is_against_zero; |
50a0b056 | 11900 | |
a3c9585f | 11901 | /* These modes should always match. */ |
a3170dc6 AH |
11902 | if (GET_MODE (op1) != compare_mode |
11903 | /* In the isel case however, we can use a compare immediate, so | |
11904 | op1 may be a small constant. */ | |
11905 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 11906 | return 0; |
178c3eff | 11907 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 11908 | return 0; |
178c3eff | 11909 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
11910 | return 0; |
11911 | ||
50a0b056 | 11912 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 11913 | if it's too slow.... */ |
50a0b056 | 11914 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
11915 | { |
11916 | if (TARGET_ISEL) | |
11917 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
11918 | return 0; | |
11919 | } | |
fef98bf2 AH |
11920 | else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS |
11921 | && GET_MODE_CLASS (compare_mode) == MODE_FLOAT) | |
11922 | return 0; | |
50a0b056 | 11923 | |
add2402e | 11924 | is_against_zero = op1 == CONST0_RTX (compare_mode); |
94ff898d | 11925 | |
add2402e GK |
11926 | /* A floating-point subtract might overflow, underflow, or produce |
11927 | an inexact result, thus changing the floating-point flags, so it | |
11928 | can't be generated if we care about that. It's safe if one side | |
11929 | of the construct is zero, since then no subtract will be | |
11930 | generated. */ | |
11931 | if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT | |
11932 | && flag_trapping_math && ! is_against_zero) | |
11933 | return 0; | |
11934 | ||
50a0b056 GK |
11935 | /* Eliminate half of the comparisons by switching operands, this |
11936 | makes the remaining code simpler. */ | |
11937 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 11938 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
11939 | { |
11940 | code = reverse_condition_maybe_unordered (code); | |
11941 | temp = true_cond; | |
11942 | true_cond = false_cond; | |
11943 | false_cond = temp; | |
11944 | } | |
11945 | ||
11946 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
11947 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 11948 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 | 11949 | return 0; |
f676971a | 11950 | |
50a0b056 GK |
11951 | if (GET_CODE (op1) == CONST_DOUBLE) |
11952 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
f676971a | 11953 | |
b6d08ca1 | 11954 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
11955 | a subtract, then comparing against zero. Unfortunately, |
11956 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 11957 | know that the operand is finite and the comparison |
50a0b056 | 11958 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 11959 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 11960 | && code != GT && code != UNGE |
045572c7 | 11961 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
11962 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
11963 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
f676971a | 11964 | || (! rtx_equal_p (op0, true_cond) |
50a0b056 GK |
11965 | && ! rtx_equal_p (op1, true_cond)))) |
11966 | return 0; | |
add2402e | 11967 | |
50a0b056 GK |
11968 | /* At this point we know we can use fsel. */ |
11969 | ||
11970 | /* Reduce the comparison to a comparison against zero. */ | |
add2402e GK |
11971 | if (! is_against_zero) |
11972 | { | |
11973 | temp = gen_reg_rtx (compare_mode); | |
11974 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
11975 | gen_rtx_MINUS (compare_mode, op0, op1))); | |
11976 | op0 = temp; | |
11977 | op1 = CONST0_RTX (compare_mode); | |
11978 | } | |
50a0b056 GK |
11979 | |
11980 | /* If we don't care about NaNs we can reduce some of the comparisons | |
11981 | down to faster ones. */ | |
bc9ec0e0 | 11982 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
11983 | switch (code) |
11984 | { | |
11985 | case GT: | |
11986 | code = LE; | |
11987 | temp = true_cond; | |
11988 | true_cond = false_cond; | |
11989 | false_cond = temp; | |
11990 | break; | |
11991 | case UNGE: | |
11992 | code = GE; | |
11993 | break; | |
11994 | case UNEQ: | |
11995 | code = EQ; | |
11996 | break; | |
11997 | default: | |
11998 | break; | |
11999 | } | |
12000 | ||
12001 | /* Now, reduce everything down to a GE. */ | |
12002 | switch (code) | |
12003 | { | |
12004 | case GE: | |
12005 | break; | |
12006 | ||
12007 | case LE: | |
3148ad6d DJ |
12008 | temp = gen_reg_rtx (compare_mode); |
12009 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
12010 | op0 = temp; |
12011 | break; | |
12012 | ||
12013 | case ORDERED: | |
3148ad6d DJ |
12014 | temp = gen_reg_rtx (compare_mode); |
12015 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
12016 | op0 = temp; |
12017 | break; | |
12018 | ||
12019 | case EQ: | |
3148ad6d | 12020 | temp = gen_reg_rtx (compare_mode); |
f676971a | 12021 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
12022 | gen_rtx_NEG (compare_mode, |
12023 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
12024 | op0 = temp; |
12025 | break; | |
12026 | ||
12027 | case UNGE: | |
bc9ec0e0 | 12028 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 12029 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 12030 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 12031 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
12032 | gen_rtx_GE (VOIDmode, |
12033 | op0, op1), | |
12034 | true_cond, false_cond))); | |
bc9ec0e0 GK |
12035 | false_cond = true_cond; |
12036 | true_cond = temp; | |
50a0b056 | 12037 | |
3148ad6d DJ |
12038 | temp = gen_reg_rtx (compare_mode); |
12039 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
12040 | op0 = temp; |
12041 | break; | |
12042 | ||
12043 | case GT: | |
bc9ec0e0 | 12044 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 12045 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 12046 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
f676971a | 12047 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
12048 | gen_rtx_GE (VOIDmode, |
12049 | op0, op1), | |
12050 | true_cond, false_cond))); | |
bc9ec0e0 GK |
12051 | true_cond = false_cond; |
12052 | false_cond = temp; | |
50a0b056 | 12053 | |
3148ad6d DJ |
12054 | temp = gen_reg_rtx (compare_mode); |
12055 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
12056 | op0 = temp; |
12057 | break; | |
12058 | ||
12059 | default: | |
12060 | abort (); | |
12061 | } | |
12062 | ||
12063 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 12064 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
12065 | gen_rtx_GE (VOIDmode, |
12066 | op0, op1), | |
12067 | true_cond, false_cond))); | |
12068 | return 1; | |
12069 | } | |
12070 | ||
a3170dc6 AH |
12071 | /* Same as above, but for ints (isel). */ |
12072 | ||
12073 | static int | |
a2369ed3 | 12074 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
12075 | { |
12076 | rtx condition_rtx, cr; | |
12077 | ||
12078 | /* All isel implementations thus far are 32-bits. */ | |
12079 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
12080 | return 0; | |
12081 | ||
12082 | /* We still have to do the compare, because isel doesn't do a | |
12083 | compare, it just looks at the CRx bits set by a previous compare | |
12084 | instruction. */ | |
12085 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
12086 | cr = XEXP (condition_rtx, 0); | |
12087 | ||
12088 | if (GET_MODE (cr) == CCmode) | |
12089 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
12090 | true_cond, false_cond, cr)); | |
12091 | else | |
12092 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
12093 | true_cond, false_cond, cr)); | |
12094 | ||
12095 | return 1; | |
12096 | } | |
12097 | ||
12098 | const char * | |
a2369ed3 | 12099 | output_isel (rtx *operands) |
a3170dc6 AH |
12100 | { |
12101 | enum rtx_code code; | |
12102 | ||
12103 | code = GET_CODE (operands[1]); | |
12104 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
12105 | { | |
12106 | PUT_CODE (operands[1], reverse_condition (code)); | |
12107 | return "isel %0,%3,%2,%j1"; | |
12108 | } | |
12109 | else | |
12110 | return "isel %0,%2,%3,%j1"; | |
12111 | } | |
12112 | ||
50a0b056 | 12113 | void |
a2369ed3 | 12114 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
12115 | { |
12116 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 12117 | enum rtx_code c; |
50a0b056 | 12118 | rtx target; |
5dc8d536 AH |
12119 | |
12120 | if (code == SMAX || code == SMIN) | |
12121 | c = GE; | |
12122 | else | |
12123 | c = GEU; | |
12124 | ||
50a0b056 | 12125 | if (code == SMAX || code == UMAX) |
f676971a | 12126 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
12127 | op0, op1, mode, 0); |
12128 | else | |
f676971a | 12129 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
12130 | op1, op0, mode, 0); |
12131 | if (target == NULL_RTX) | |
12132 | abort (); | |
12133 | if (target != dest) | |
12134 | emit_move_insn (dest, target); | |
12135 | } | |
46c07df8 | 12136 | |
a9baceb1 GK |
12137 | /* Emit instructions to move SRC to DST. Called by splitters for |
12138 | multi-register moves. It will emit at most one instruction for | |
12139 | each register that is accessed; that is, it won't emit li/lis pairs | |
12140 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
12141 | register. */ | |
46c07df8 | 12142 | |
46c07df8 | 12143 | void |
a9baceb1 | 12144 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 12145 | { |
a9baceb1 GK |
12146 | /* The register number of the first register being moved. */ |
12147 | int reg; | |
12148 | /* The mode that is to be moved. */ | |
12149 | enum machine_mode mode; | |
12150 | /* The mode that the move is being done in, and its size. */ | |
12151 | enum machine_mode reg_mode; | |
12152 | int reg_mode_size; | |
12153 | /* The number of registers that will be moved. */ | |
12154 | int nregs; | |
12155 | ||
12156 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
12157 | mode = GET_MODE (dst); | |
12158 | nregs = HARD_REGNO_NREGS (reg, mode); | |
12159 | if (FP_REGNO_P (reg)) | |
12160 | reg_mode = DFmode; | |
12161 | else if (ALTIVEC_REGNO_P (reg)) | |
12162 | reg_mode = V16QImode; | |
12163 | else | |
12164 | reg_mode = word_mode; | |
12165 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
f676971a | 12166 | |
a9baceb1 GK |
12167 | if (reg_mode_size * nregs != GET_MODE_SIZE (mode)) |
12168 | abort (); | |
f676971a | 12169 | |
a9baceb1 GK |
12170 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) |
12171 | { | |
12172 | /* Move register range backwards, if we might have destructive | |
12173 | overlap. */ | |
12174 | int i; | |
12175 | for (i = nregs - 1; i >= 0; i--) | |
f676971a | 12176 | emit_insn (gen_rtx_SET (VOIDmode, |
a9baceb1 GK |
12177 | simplify_gen_subreg (reg_mode, dst, mode, |
12178 | i * reg_mode_size), | |
12179 | simplify_gen_subreg (reg_mode, src, mode, | |
12180 | i * reg_mode_size))); | |
12181 | } | |
46c07df8 HP |
12182 | else |
12183 | { | |
a9baceb1 GK |
12184 | int i; |
12185 | int j = -1; | |
12186 | bool used_update = false; | |
46c07df8 | 12187 | |
c1e55850 | 12188 | if (MEM_P (src) && INT_REGNO_P (reg)) |
c4ad648e AM |
12189 | { |
12190 | rtx breg; | |
3a1f863f | 12191 | |
a9baceb1 GK |
12192 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
12193 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
12194 | { |
12195 | rtx delta_rtx; | |
a9baceb1 | 12196 | breg = XEXP (XEXP (src, 0), 0); |
c4ad648e AM |
12197 | delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC |
12198 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
12199 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)))); | |
a9baceb1 GK |
12200 | emit_insn (TARGET_32BIT |
12201 | ? gen_addsi3 (breg, breg, delta_rtx) | |
12202 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
12203 | src = gen_rtx_MEM (mode, breg); |
12204 | } | |
c1e55850 GK |
12205 | else if (! offsettable_memref_p (src)) |
12206 | { | |
12207 | rtx newsrc, basereg; | |
12208 | basereg = gen_rtx_REG (Pmode, reg); | |
12209 | emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0))); | |
12210 | newsrc = gen_rtx_MEM (GET_MODE (src), basereg); | |
12211 | MEM_COPY_ATTRIBUTES (newsrc, src); | |
12212 | src = newsrc; | |
12213 | } | |
3a1f863f | 12214 | |
0423421f AM |
12215 | breg = XEXP (src, 0); |
12216 | if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM) | |
12217 | breg = XEXP (breg, 0); | |
12218 | ||
12219 | /* If the base register we are using to address memory is | |
12220 | also a destination reg, then change that register last. */ | |
12221 | if (REG_P (breg) | |
12222 | && REGNO (breg) >= REGNO (dst) | |
3a1f863f DE |
12223 | && REGNO (breg) < REGNO (dst) + nregs) |
12224 | j = REGNO (breg) - REGNO (dst); | |
c4ad648e | 12225 | } |
46c07df8 | 12226 | |
a9baceb1 | 12227 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
12228 | { |
12229 | rtx breg; | |
12230 | ||
a9baceb1 GK |
12231 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
12232 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
12233 | { |
12234 | rtx delta_rtx; | |
a9baceb1 | 12235 | breg = XEXP (XEXP (dst, 0), 0); |
c4ad648e AM |
12236 | delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC |
12237 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
12238 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)))); | |
3a1f863f DE |
12239 | |
12240 | /* We have to update the breg before doing the store. | |
12241 | Use store with update, if available. */ | |
12242 | ||
12243 | if (TARGET_UPDATE) | |
12244 | { | |
a9baceb1 | 12245 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
c4ad648e AM |
12246 | emit_insn (TARGET_32BIT |
12247 | ? (TARGET_POWERPC64 | |
12248 | ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc) | |
12249 | : gen_movsi_update (breg, breg, delta_rtx, nsrc)) | |
12250 | : gen_movdi_di_update (breg, breg, delta_rtx, nsrc)); | |
a9baceb1 | 12251 | used_update = true; |
3a1f863f DE |
12252 | } |
12253 | else | |
a9baceb1 GK |
12254 | emit_insn (TARGET_32BIT |
12255 | ? gen_addsi3 (breg, breg, delta_rtx) | |
12256 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
12257 | dst = gen_rtx_MEM (mode, breg); |
12258 | } | |
c1e55850 | 12259 | else if (! offsettable_memref_p (dst)) |
112ccb83 | 12260 | abort (); |
3a1f863f DE |
12261 | } |
12262 | ||
46c07df8 | 12263 | for (i = 0; i < nregs; i++) |
f676971a | 12264 | { |
3a1f863f DE |
12265 | /* Calculate index to next subword. */ |
12266 | ++j; | |
f676971a | 12267 | if (j == nregs) |
3a1f863f | 12268 | j = 0; |
46c07df8 | 12269 | |
112cdef5 | 12270 | /* If compiler already emitted move of first word by |
a9baceb1 | 12271 | store with update, no need to do anything. */ |
3a1f863f | 12272 | if (j == 0 && used_update) |
a9baceb1 | 12273 | continue; |
f676971a | 12274 | |
a9baceb1 GK |
12275 | emit_insn (gen_rtx_SET (VOIDmode, |
12276 | simplify_gen_subreg (reg_mode, dst, mode, | |
12277 | j * reg_mode_size), | |
12278 | simplify_gen_subreg (reg_mode, src, mode, | |
12279 | j * reg_mode_size))); | |
3a1f863f | 12280 | } |
46c07df8 HP |
12281 | } |
12282 | } | |
12283 | ||
12a4e8c5 | 12284 | \f |
a4f6c312 SS |
12285 | /* This page contains routines that are used to determine what the |
12286 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 12287 | |
a4f6c312 SS |
12288 | /* Return the first fixed-point register that is required to be |
12289 | saved. 32 if none. */ | |
9878760c RK |
12290 | |
12291 | int | |
863d938c | 12292 | first_reg_to_save (void) |
9878760c RK |
12293 | { |
12294 | int first_reg; | |
12295 | ||
12296 | /* Find lowest numbered live register. */ | |
12297 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
f676971a | 12298 | if (regs_ever_live[first_reg] |
a38d360d | 12299 | && (! call_used_regs[first_reg] |
1db02437 | 12300 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 12301 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
b4db40bf JJ |
12302 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) |
12303 | || (TARGET_TOC && TARGET_MINIMAL_TOC))))) | |
9878760c RK |
12304 | break; |
12305 | ||
ee890fe2 | 12306 | #if TARGET_MACHO |
93638d7a AM |
12307 | if (flag_pic |
12308 | && current_function_uses_pic_offset_table | |
12309 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 12310 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
12311 | #endif |
12312 | ||
9878760c RK |
12313 | return first_reg; |
12314 | } | |
12315 | ||
12316 | /* Similar, for FP regs. */ | |
12317 | ||
12318 | int | |
863d938c | 12319 | first_fp_reg_to_save (void) |
9878760c RK |
12320 | { |
12321 | int first_reg; | |
12322 | ||
12323 | /* Find lowest numbered live register. */ | |
12324 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
12325 | if (regs_ever_live[first_reg]) | |
12326 | break; | |
12327 | ||
12328 | return first_reg; | |
12329 | } | |
00b960c7 AH |
12330 | |
12331 | /* Similar, for AltiVec regs. */ | |
12332 | ||
12333 | static int | |
863d938c | 12334 | first_altivec_reg_to_save (void) |
00b960c7 AH |
12335 | { |
12336 | int i; | |
12337 | ||
12338 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
12339 | if (! TARGET_ALTIVEC_ABI) | |
12340 | return LAST_ALTIVEC_REGNO + 1; | |
12341 | ||
12342 | /* Find lowest numbered live register. */ | |
12343 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
12344 | if (regs_ever_live[i]) | |
12345 | break; | |
12346 | ||
12347 | return i; | |
12348 | } | |
12349 | ||
12350 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
12351 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
12352 | the 32-bit word is 0. */ | |
12353 | ||
12354 | static unsigned int | |
863d938c | 12355 | compute_vrsave_mask (void) |
00b960c7 AH |
12356 | { |
12357 | unsigned int i, mask = 0; | |
12358 | ||
12359 | /* First, find out if we use _any_ altivec registers. */ | |
12360 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
12361 | if (regs_ever_live[i]) | |
12362 | mask |= ALTIVEC_REG_BIT (i); | |
12363 | ||
12364 | if (mask == 0) | |
12365 | return mask; | |
12366 | ||
00b960c7 AH |
12367 | /* Next, remove the argument registers from the set. These must |
12368 | be in the VRSAVE mask set by the caller, so we don't need to add | |
12369 | them in again. More importantly, the mask we compute here is | |
12370 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
12371 | wish the argument registers to die. */ | |
a6cf80f2 | 12372 | for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
12373 | mask &= ~ALTIVEC_REG_BIT (i); |
12374 | ||
12375 | /* Similarly, remove the return value from the set. */ | |
12376 | { | |
12377 | bool yes = false; | |
12378 | diddle_return_value (is_altivec_return_reg, &yes); | |
12379 | if (yes) | |
12380 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
12381 | } | |
12382 | ||
12383 | return mask; | |
12384 | } | |
12385 | ||
d62294f5 FJ |
12386 | /* For a very restricted set of circumstances, we can cut down the |
12387 | size of prologs/epilogs by calling our own save/restore-the-world | |
12388 | routines. */ | |
12389 | ||
12390 | static void | |
12391 | compute_save_world_info(rs6000_stack_t *info_ptr) | |
12392 | { | |
12393 | info_ptr->world_save_p = | |
12394 | (DEFAULT_ABI == ABI_DARWIN) | |
12395 | && ! (current_function_calls_setjmp && flag_exceptions) | |
12396 | && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO | |
12397 | && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO | |
12398 | && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO | |
12399 | && info_ptr->cr_save_p; | |
f676971a | 12400 | |
d62294f5 FJ |
12401 | /* This will not work in conjunction with sibcalls. Make sure there |
12402 | are none. (This check is expensive, but seldom executed.) */ | |
12403 | if ( info_ptr->world_save_p ) | |
f676971a | 12404 | { |
d62294f5 FJ |
12405 | rtx insn; |
12406 | for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) | |
c4ad648e AM |
12407 | if ( GET_CODE (insn) == CALL_INSN |
12408 | && SIBLING_CALL_P (insn)) | |
12409 | { | |
12410 | info_ptr->world_save_p = 0; | |
12411 | break; | |
12412 | } | |
d62294f5 | 12413 | } |
f676971a | 12414 | |
d62294f5 FJ |
12415 | if (info_ptr->world_save_p) |
12416 | { | |
12417 | /* Even if we're not touching VRsave, make sure there's room on the | |
12418 | stack for it, if it looks like we're calling SAVE_WORLD, which | |
c4ad648e | 12419 | will attempt to save it. */ |
d62294f5 FJ |
12420 | info_ptr->vrsave_size = 4; |
12421 | ||
12422 | /* "Save" the VRsave register too if we're saving the world. */ | |
12423 | if (info_ptr->vrsave_mask == 0) | |
c4ad648e | 12424 | info_ptr->vrsave_mask = compute_vrsave_mask (); |
d62294f5 FJ |
12425 | |
12426 | /* Because the Darwin register save/restore routines only handle | |
c4ad648e AM |
12427 | F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency |
12428 | check and abort if there's something worng. */ | |
f676971a | 12429 | if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO |
c4ad648e AM |
12430 | || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO) |
12431 | abort (); | |
d62294f5 | 12432 | } |
f676971a | 12433 | return; |
d62294f5 FJ |
12434 | } |
12435 | ||
12436 | ||
00b960c7 | 12437 | static void |
a2369ed3 | 12438 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
12439 | { |
12440 | bool *yes = (bool *) xyes; | |
12441 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
12442 | *yes = true; | |
12443 | } | |
12444 | ||
4697a36c MM |
12445 | \f |
12446 | /* Calculate the stack information for the current function. This is | |
12447 | complicated by having two separate calling sequences, the AIX calling | |
12448 | sequence and the V.4 calling sequence. | |
12449 | ||
592696dd | 12450 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 12451 | 32-bit 64-bit |
4697a36c | 12452 | SP----> +---------------------------------------+ |
a260abc9 | 12453 | | back chain to caller | 0 0 |
4697a36c | 12454 | +---------------------------------------+ |
a260abc9 | 12455 | | saved CR | 4 8 (8-11) |
4697a36c | 12456 | +---------------------------------------+ |
a260abc9 | 12457 | | saved LR | 8 16 |
4697a36c | 12458 | +---------------------------------------+ |
a260abc9 | 12459 | | reserved for compilers | 12 24 |
4697a36c | 12460 | +---------------------------------------+ |
a260abc9 | 12461 | | reserved for binders | 16 32 |
4697a36c | 12462 | +---------------------------------------+ |
a260abc9 | 12463 | | saved TOC pointer | 20 40 |
4697a36c | 12464 | +---------------------------------------+ |
a260abc9 | 12465 | | Parameter save area (P) | 24 48 |
4697a36c | 12466 | +---------------------------------------+ |
a260abc9 | 12467 | | Alloca space (A) | 24+P etc. |
802a0058 | 12468 | +---------------------------------------+ |
a7df97e6 | 12469 | | Local variable space (L) | 24+P+A |
4697a36c | 12470 | +---------------------------------------+ |
a7df97e6 | 12471 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 12472 | +---------------------------------------+ |
00b960c7 AH |
12473 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
12474 | +---------------------------------------+ | |
12475 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
12476 | +---------------------------------------+ | |
12477 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 12478 | +---------------------------------------+ |
00b960c7 AH |
12479 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
12480 | +---------------------------------------+ | |
12481 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
12482 | +---------------------------------------+ |
12483 | old SP->| back chain to caller's caller | | |
12484 | +---------------------------------------+ | |
12485 | ||
5376a30c KR |
12486 | The required alignment for AIX configurations is two words (i.e., 8 |
12487 | or 16 bytes). | |
12488 | ||
12489 | ||
4697a36c MM |
12490 | V.4 stack frames look like: |
12491 | ||
12492 | SP----> +---------------------------------------+ | |
12493 | | back chain to caller | 0 | |
12494 | +---------------------------------------+ | |
5eb387b8 | 12495 | | caller's saved LR | 4 |
4697a36c MM |
12496 | +---------------------------------------+ |
12497 | | Parameter save area (P) | 8 | |
12498 | +---------------------------------------+ | |
a7df97e6 | 12499 | | Alloca space (A) | 8+P |
f676971a | 12500 | +---------------------------------------+ |
a7df97e6 | 12501 | | Varargs save area (V) | 8+P+A |
f676971a | 12502 | +---------------------------------------+ |
a7df97e6 | 12503 | | Local variable space (L) | 8+P+A+V |
f676971a | 12504 | +---------------------------------------+ |
a7df97e6 | 12505 | | Float/int conversion temporary (X) | 8+P+A+V+L |
4697a36c | 12506 | +---------------------------------------+ |
00b960c7 AH |
12507 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
12508 | +---------------------------------------+ | |
12509 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
12510 | +---------------------------------------+ | |
12511 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
12512 | +---------------------------------------+ | |
c4ad648e AM |
12513 | | SPE: area for 64-bit GP registers | |
12514 | +---------------------------------------+ | |
12515 | | SPE alignment padding | | |
12516 | +---------------------------------------+ | |
00b960c7 | 12517 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
f676971a | 12518 | +---------------------------------------+ |
00b960c7 | 12519 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
f676971a | 12520 | +---------------------------------------+ |
00b960c7 | 12521 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
12522 | +---------------------------------------+ |
12523 | old SP->| back chain to caller's caller | | |
12524 | +---------------------------------------+ | |
b6c9286a | 12525 | |
5376a30c KR |
12526 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
12527 | given. (But note below and in sysv4.h that we require only 8 and | |
12528 | may round up the size of our stack frame anyways. The historical | |
12529 | reason is early versions of powerpc-linux which didn't properly | |
12530 | align the stack at program startup. A happy side-effect is that | |
12531 | -mno-eabi libraries can be used with -meabi programs.) | |
12532 | ||
50d440bc | 12533 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
12534 | the stack alignment requirements may differ. If -mno-eabi is not |
12535 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
12536 | given, the required alignment is 16 bytes. (But see V.4 comment | |
12537 | above.) */ | |
4697a36c | 12538 | |
61b2fbe7 MM |
12539 | #ifndef ABI_STACK_BOUNDARY |
12540 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
12541 | #endif | |
12542 | ||
d1d0c603 | 12543 | static rs6000_stack_t * |
863d938c | 12544 | rs6000_stack_info (void) |
4697a36c MM |
12545 | { |
12546 | static rs6000_stack_t info, zero_info; | |
12547 | rs6000_stack_t *info_ptr = &info; | |
327e5343 | 12548 | int reg_size = TARGET_32BIT ? 4 : 8; |
83720594 | 12549 | int ehrd_size; |
64045029 | 12550 | int save_align; |
44688022 | 12551 | HOST_WIDE_INT non_fixed_size; |
4697a36c | 12552 | |
a4f6c312 | 12553 | /* Zero all fields portably. */ |
4697a36c MM |
12554 | info = zero_info; |
12555 | ||
c19de7aa AH |
12556 | if (TARGET_SPE) |
12557 | { | |
12558 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f AH |
12559 | if (cfun->machine->insn_chain_scanned_p == 0) |
12560 | { | |
12561 | cfun->machine->insn_chain_scanned_p = 1; | |
12562 | info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p (); | |
12563 | } | |
c19de7aa AH |
12564 | } |
12565 | ||
a4f6c312 | 12566 | /* Select which calling sequence. */ |
178274da | 12567 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 12568 | |
a4f6c312 | 12569 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 12570 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
f676971a | 12571 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 12572 | even if it currently looks like we won't. */ |
2bfcf297 | 12573 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
12574 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
12575 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
12576 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
12577 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
12578 | else |
12579 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 12580 | |
a3170dc6 AH |
12581 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
12582 | Ideally we should save the entire 64-bits only when the upper | |
12583 | half is used in SIMD instructions. Since we only record | |
12584 | registers live (not the size they are used in), this proves | |
12585 | difficult because we'd have to traverse the instruction chain at | |
12586 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
12587 | so we opt to save the GPRs in 64-bits always if but one register |
12588 | gets used in 64-bits. Otherwise, all the registers in the frame | |
12589 | get saved in 32-bits. | |
a3170dc6 | 12590 | |
c19de7aa | 12591 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 12592 | traditional GP save area will be empty. */ |
c19de7aa | 12593 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12594 | info_ptr->gp_size = 0; |
12595 | ||
4697a36c MM |
12596 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
12597 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
12598 | ||
00b960c7 AH |
12599 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
12600 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
12601 | - info_ptr->first_altivec_reg_save); | |
12602 | ||
592696dd | 12603 | /* Does this function call anything? */ |
71f123ca FS |
12604 | info_ptr->calls_p = (! current_function_is_leaf |
12605 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 12606 | |
a4f6c312 | 12607 | /* Determine if we need to save the link register. */ |
71f123ca | 12608 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
12609 | || (DEFAULT_ABI == ABI_AIX |
12610 | && current_function_profile | |
12611 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
12612 | #ifdef TARGET_RELOCATABLE |
12613 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
12614 | #endif | |
12615 | || (info_ptr->first_fp_reg_save != 64 | |
12616 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 12617 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 12618 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
12619 | || (DEFAULT_ABI == ABI_DARWIN |
12620 | && flag_pic | |
12621 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
12622 | || info_ptr->calls_p) |
12623 | { | |
12624 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 12625 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
12626 | } |
12627 | ||
9ebbca7d | 12628 | /* Determine if we need to save the condition code registers. */ |
f676971a | 12629 | if (regs_ever_live[CR2_REGNO] |
9ebbca7d GK |
12630 | || regs_ever_live[CR3_REGNO] |
12631 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
12632 | { |
12633 | info_ptr->cr_save_p = 1; | |
178274da | 12634 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
12635 | info_ptr->cr_size = reg_size; |
12636 | } | |
12637 | ||
83720594 RH |
12638 | /* If the current function calls __builtin_eh_return, then we need |
12639 | to allocate stack space for registers that will hold data for | |
12640 | the exception handler. */ | |
12641 | if (current_function_calls_eh_return) | |
12642 | { | |
12643 | unsigned int i; | |
12644 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
12645 | continue; | |
a3170dc6 AH |
12646 | |
12647 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
12648 | ehrd_size = i * (TARGET_SPE_ABI |
12649 | && info_ptr->spe_64bit_regs_used != 0 | |
12650 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
12651 | } |
12652 | else | |
12653 | ehrd_size = 0; | |
12654 | ||
592696dd | 12655 | /* Determine various sizes. */ |
4697a36c MM |
12656 | info_ptr->reg_size = reg_size; |
12657 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
12658 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 12659 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 | 12660 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
03e007d7 | 12661 | TARGET_ALTIVEC ? 16 : 8); |
00b960c7 | 12662 | |
c19de7aa | 12663 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12664 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
12665 | else | |
12666 | info_ptr->spe_gp_size = 0; | |
12667 | ||
4d774ff8 HP |
12668 | if (TARGET_ALTIVEC_ABI) |
12669 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 12670 | else |
4d774ff8 HP |
12671 | info_ptr->vrsave_mask = 0; |
12672 | ||
12673 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
12674 | info_ptr->vrsave_size = 4; | |
12675 | else | |
12676 | info_ptr->vrsave_size = 0; | |
b6c9286a | 12677 | |
d62294f5 FJ |
12678 | compute_save_world_info (info_ptr); |
12679 | ||
592696dd | 12680 | /* Calculate the offsets. */ |
178274da | 12681 | switch (DEFAULT_ABI) |
4697a36c | 12682 | { |
b6c9286a | 12683 | case ABI_NONE: |
24d304eb | 12684 | default: |
b6c9286a MM |
12685 | abort (); |
12686 | ||
12687 | case ABI_AIX: | |
ee890fe2 | 12688 | case ABI_DARWIN: |
b6c9286a MM |
12689 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
12690 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
12691 | |
12692 | if (TARGET_ALTIVEC_ABI) | |
12693 | { | |
12694 | info_ptr->vrsave_save_offset | |
12695 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
12696 | ||
12697 | /* Align stack so vector save area is on a quadword boundary. */ | |
12698 | if (info_ptr->altivec_size != 0) | |
12699 | info_ptr->altivec_padding_size | |
12700 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
12701 | else | |
12702 | info_ptr->altivec_padding_size = 0; | |
12703 | ||
12704 | info_ptr->altivec_save_offset | |
12705 | = info_ptr->vrsave_save_offset | |
12706 | - info_ptr->altivec_padding_size | |
12707 | - info_ptr->altivec_size; | |
12708 | ||
12709 | /* Adjust for AltiVec case. */ | |
12710 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
12711 | } | |
12712 | else | |
12713 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
12714 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
12715 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
12716 | break; |
12717 | ||
12718 | case ABI_V4: | |
b6c9286a MM |
12719 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
12720 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 12721 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 12722 | |
c19de7aa | 12723 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
c4ad648e AM |
12724 | { |
12725 | /* Align stack so SPE GPR save area is aligned on a | |
12726 | double-word boundary. */ | |
12727 | if (info_ptr->spe_gp_size != 0) | |
12728 | info_ptr->spe_padding_size | |
12729 | = 8 - (-info_ptr->cr_save_offset % 8); | |
12730 | else | |
12731 | info_ptr->spe_padding_size = 0; | |
12732 | ||
12733 | info_ptr->spe_gp_save_offset | |
12734 | = info_ptr->cr_save_offset | |
12735 | - info_ptr->spe_padding_size | |
12736 | - info_ptr->spe_gp_size; | |
12737 | ||
12738 | /* Adjust for SPE case. */ | |
12739 | info_ptr->toc_save_offset | |
12740 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
12741 | } | |
a3170dc6 | 12742 | else if (TARGET_ALTIVEC_ABI) |
00b960c7 AH |
12743 | { |
12744 | info_ptr->vrsave_save_offset | |
12745 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
12746 | ||
12747 | /* Align stack so vector save area is on a quadword boundary. */ | |
12748 | if (info_ptr->altivec_size != 0) | |
12749 | info_ptr->altivec_padding_size | |
12750 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
12751 | else | |
12752 | info_ptr->altivec_padding_size = 0; | |
12753 | ||
12754 | info_ptr->altivec_save_offset | |
12755 | = info_ptr->vrsave_save_offset | |
12756 | - info_ptr->altivec_padding_size | |
12757 | - info_ptr->altivec_size; | |
12758 | ||
12759 | /* Adjust for AltiVec case. */ | |
12760 | info_ptr->toc_save_offset | |
12761 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
12762 | } | |
12763 | else | |
12764 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 12765 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
12766 | info_ptr->lr_save_offset = reg_size; |
12767 | break; | |
4697a36c MM |
12768 | } |
12769 | ||
64045029 | 12770 | save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8; |
00b960c7 AH |
12771 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
12772 | + info_ptr->gp_size | |
12773 | + info_ptr->altivec_size | |
12774 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
12775 | + info_ptr->spe_gp_size |
12776 | + info_ptr->spe_padding_size | |
00b960c7 AH |
12777 | + ehrd_size |
12778 | + info_ptr->cr_size | |
12779 | + info_ptr->lr_size | |
12780 | + info_ptr->vrsave_size | |
12781 | + info_ptr->toc_size, | |
64045029 | 12782 | save_align); |
00b960c7 | 12783 | |
44688022 | 12784 | non_fixed_size = (info_ptr->vars_size |
ff381587 | 12785 | + info_ptr->parm_size |
ff381587 | 12786 | + info_ptr->save_size |
44688022 | 12787 | + info_ptr->varargs_size); |
ff381587 | 12788 | |
44688022 AM |
12789 | info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, |
12790 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
12791 | |
12792 | /* Determine if we need to allocate any stack frame: | |
12793 | ||
a4f6c312 SS |
12794 | For AIX we need to push the stack if a frame pointer is needed |
12795 | (because the stack might be dynamically adjusted), if we are | |
12796 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
12797 | and local variables are more than the space needed to save all | |
12798 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
12799 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 12800 | |
a4f6c312 SS |
12801 | For V.4 we don't have the stack cushion that AIX uses, but assume |
12802 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
12803 | |
12804 | if (info_ptr->calls_p) | |
12805 | info_ptr->push_p = 1; | |
12806 | ||
178274da | 12807 | else if (DEFAULT_ABI == ABI_V4) |
44688022 | 12808 | info_ptr->push_p = non_fixed_size != 0; |
ff381587 | 12809 | |
178274da AM |
12810 | else if (frame_pointer_needed) |
12811 | info_ptr->push_p = 1; | |
12812 | ||
12813 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
12814 | info_ptr->push_p = 1; | |
12815 | ||
ff381587 | 12816 | else |
44688022 | 12817 | info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); |
ff381587 | 12818 | |
a4f6c312 | 12819 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 12820 | if (info_ptr->fp_size == 0) |
4697a36c MM |
12821 | info_ptr->fp_save_offset = 0; |
12822 | ||
8dda1a21 | 12823 | if (info_ptr->gp_size == 0) |
4697a36c MM |
12824 | info_ptr->gp_save_offset = 0; |
12825 | ||
00b960c7 AH |
12826 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
12827 | info_ptr->altivec_save_offset = 0; | |
12828 | ||
12829 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
12830 | info_ptr->vrsave_save_offset = 0; | |
12831 | ||
c19de7aa AH |
12832 | if (! TARGET_SPE_ABI |
12833 | || info_ptr->spe_64bit_regs_used == 0 | |
12834 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
12835 | info_ptr->spe_gp_save_offset = 0; |
12836 | ||
c81fc13e | 12837 | if (! info_ptr->lr_save_p) |
4697a36c MM |
12838 | info_ptr->lr_save_offset = 0; |
12839 | ||
c81fc13e | 12840 | if (! info_ptr->cr_save_p) |
4697a36c MM |
12841 | info_ptr->cr_save_offset = 0; |
12842 | ||
c81fc13e | 12843 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
12844 | info_ptr->toc_save_offset = 0; |
12845 | ||
4697a36c MM |
12846 | return info_ptr; |
12847 | } | |
12848 | ||
c19de7aa AH |
12849 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
12850 | mode. */ | |
12851 | ||
12852 | static bool | |
863d938c | 12853 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
12854 | { |
12855 | rtx insns, insn; | |
12856 | ||
12857 | /* Functions that save and restore all the call-saved registers will | |
12858 | need to save/restore the registers in 64-bits. */ | |
12859 | if (current_function_calls_eh_return | |
12860 | || current_function_calls_setjmp | |
12861 | || current_function_has_nonlocal_goto) | |
12862 | return true; | |
12863 | ||
12864 | insns = get_insns (); | |
12865 | ||
12866 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
12867 | { | |
12868 | if (INSN_P (insn)) | |
12869 | { | |
12870 | rtx i; | |
12871 | ||
12872 | i = PATTERN (insn); | |
f82f556d AH |
12873 | if (GET_CODE (i) == SET) |
12874 | { | |
12875 | enum machine_mode mode = GET_MODE (SET_SRC (i)); | |
12876 | ||
12877 | if (SPE_VECTOR_MODE (mode)) | |
12878 | return true; | |
12879 | if (TARGET_E500_DOUBLE && mode == DFmode) | |
12880 | return true; | |
12881 | } | |
c19de7aa AH |
12882 | } |
12883 | } | |
12884 | ||
12885 | return false; | |
12886 | } | |
12887 | ||
d1d0c603 | 12888 | static void |
a2369ed3 | 12889 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 12890 | { |
d330fd93 | 12891 | const char *abi_string; |
24d304eb | 12892 | |
c81fc13e | 12893 | if (! info) |
4697a36c MM |
12894 | info = rs6000_stack_info (); |
12895 | ||
12896 | fprintf (stderr, "\nStack information for function %s:\n", | |
12897 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
12898 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
12899 | : "<unknown>")); | |
12900 | ||
24d304eb RK |
12901 | switch (info->abi) |
12902 | { | |
b6c9286a MM |
12903 | default: abi_string = "Unknown"; break; |
12904 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 12905 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 12906 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 12907 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
12908 | } |
12909 | ||
12910 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
12911 | ||
00b960c7 AH |
12912 | if (TARGET_ALTIVEC_ABI) |
12913 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
12914 | ||
a3170dc6 AH |
12915 | if (TARGET_SPE_ABI) |
12916 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
12917 | ||
4697a36c MM |
12918 | if (info->first_gp_reg_save != 32) |
12919 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
12920 | ||
12921 | if (info->first_fp_reg_save != 64) | |
12922 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 12923 | |
00b960c7 AH |
12924 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
12925 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
12926 | info->first_altivec_reg_save); | |
12927 | ||
4697a36c MM |
12928 | if (info->lr_save_p) |
12929 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 12930 | |
4697a36c MM |
12931 | if (info->cr_save_p) |
12932 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
12933 | ||
b6c9286a MM |
12934 | if (info->toc_save_p) |
12935 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
12936 | ||
00b960c7 AH |
12937 | if (info->vrsave_mask) |
12938 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
12939 | ||
4697a36c MM |
12940 | if (info->push_p) |
12941 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
12942 | ||
12943 | if (info->calls_p) | |
12944 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
12945 | ||
4697a36c MM |
12946 | if (info->gp_save_offset) |
12947 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
12948 | ||
12949 | if (info->fp_save_offset) | |
12950 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
12951 | ||
00b960c7 AH |
12952 | if (info->altivec_save_offset) |
12953 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
12954 | info->altivec_save_offset); | |
12955 | ||
a3170dc6 AH |
12956 | if (info->spe_gp_save_offset) |
12957 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
12958 | info->spe_gp_save_offset); | |
12959 | ||
00b960c7 AH |
12960 | if (info->vrsave_save_offset) |
12961 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
12962 | info->vrsave_save_offset); | |
12963 | ||
4697a36c MM |
12964 | if (info->lr_save_offset) |
12965 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
12966 | ||
12967 | if (info->cr_save_offset) | |
12968 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
12969 | ||
b6c9286a MM |
12970 | if (info->toc_save_offset) |
12971 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
12972 | ||
4697a36c MM |
12973 | if (info->varargs_save_offset) |
12974 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
12975 | ||
12976 | if (info->total_size) | |
d1d0c603 JJ |
12977 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
12978 | info->total_size); | |
4697a36c MM |
12979 | |
12980 | if (info->varargs_size) | |
12981 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
12982 | ||
12983 | if (info->vars_size) | |
d1d0c603 JJ |
12984 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
12985 | info->vars_size); | |
4697a36c MM |
12986 | |
12987 | if (info->parm_size) | |
12988 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
12989 | ||
12990 | if (info->fixed_size) | |
12991 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
12992 | ||
12993 | if (info->gp_size) | |
12994 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
12995 | ||
a3170dc6 AH |
12996 | if (info->spe_gp_size) |
12997 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
12998 | ||
4697a36c MM |
12999 | if (info->fp_size) |
13000 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
13001 | ||
00b960c7 AH |
13002 | if (info->altivec_size) |
13003 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
13004 | ||
13005 | if (info->vrsave_size) | |
13006 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
13007 | ||
13008 | if (info->altivec_padding_size) | |
13009 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
13010 | info->altivec_padding_size); | |
13011 | ||
a3170dc6 AH |
13012 | if (info->spe_padding_size) |
13013 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
13014 | info->spe_padding_size); | |
13015 | ||
a4f6c312 | 13016 | if (info->lr_size) |
ed947a96 | 13017 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 13018 | |
4697a36c MM |
13019 | if (info->cr_size) |
13020 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
13021 | ||
a4f6c312 | 13022 | if (info->toc_size) |
b6c9286a MM |
13023 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
13024 | ||
4697a36c MM |
13025 | if (info->save_size) |
13026 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
13027 | ||
13028 | if (info->reg_size != 4) | |
13029 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
13030 | ||
13031 | fprintf (stderr, "\n"); | |
9878760c | 13032 | } |
71f123ca FS |
13033 | |
13034 | rtx | |
a2369ed3 | 13035 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 13036 | { |
a4f6c312 SS |
13037 | /* Currently we don't optimize very well between prolog and body |
13038 | code and for PIC code the code can be actually quite bad, so | |
13039 | don't try to be too clever here. */ | |
f1384257 | 13040 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
13041 | { |
13042 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
13043 | |
13044 | return | |
13045 | gen_rtx_MEM | |
13046 | (Pmode, | |
13047 | memory_address | |
13048 | (Pmode, | |
13049 | plus_constant (copy_to_reg | |
13050 | (gen_rtx_MEM (Pmode, | |
13051 | memory_address (Pmode, frame))), | |
13052 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
13053 | } |
13054 | ||
8c29550d | 13055 | cfun->machine->ra_need_lr = 1; |
9e2f7ec7 | 13056 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
13057 | } |
13058 | ||
5e1bf043 DJ |
13059 | /* Say whether a function is a candidate for sibcall handling or not. |
13060 | We do not allow indirect calls to be optimized into sibling calls. | |
13061 | Also, we can't do it if there are any vector parameters; there's | |
13062 | nowhere to put the VRsave code so it works; note that functions with | |
13063 | vector parameters are required to have a prototype, so the argument | |
13064 | type info must be available here. (The tail recursion case can work | |
13065 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 13066 | static bool |
a2369ed3 | 13067 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
13068 | { |
13069 | tree type; | |
4977bab6 | 13070 | if (decl) |
5e1bf043 DJ |
13071 | { |
13072 | if (TARGET_ALTIVEC_VRSAVE) | |
c4ad648e | 13073 | { |
4977bab6 | 13074 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
13075 | type; type = TREE_CHAIN (type)) |
13076 | { | |
c15b529f | 13077 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 13078 | return false; |
5e1bf043 | 13079 | } |
c4ad648e | 13080 | } |
5e1bf043 | 13081 | if (DEFAULT_ABI == ABI_DARWIN |
4977bab6 | 13082 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 13083 | { |
4977bab6 | 13084 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
13085 | |
13086 | if (!lookup_attribute ("longcall", attr_list) | |
13087 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 13088 | return true; |
2bcc50d0 | 13089 | } |
5e1bf043 | 13090 | } |
4977bab6 | 13091 | return false; |
5e1bf043 DJ |
13092 | } |
13093 | ||
71f123ca | 13094 | static int |
863d938c | 13095 | rs6000_ra_ever_killed (void) |
71f123ca FS |
13096 | { |
13097 | rtx top; | |
5e1bf043 DJ |
13098 | rtx reg; |
13099 | rtx insn; | |
71f123ca | 13100 | |
dd292d0a | 13101 | if (current_function_is_thunk) |
71f123ca | 13102 | return 0; |
eb0424da | 13103 | |
36f7e964 AH |
13104 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
13105 | but this should not force saving and restoring in the | |
13106 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 13107 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 13108 | |
5e1bf043 DJ |
13109 | /* Also, the prologue can generate a store into LR that |
13110 | doesn't really count, like this: | |
36f7e964 | 13111 | |
5e1bf043 DJ |
13112 | move LR->R0 |
13113 | bcl to set PIC register | |
13114 | move LR->R31 | |
13115 | move R0->LR | |
36f7e964 AH |
13116 | |
13117 | When we're called from the epilogue, we need to avoid counting | |
13118 | this as a store. */ | |
f676971a | 13119 | |
71f123ca FS |
13120 | push_topmost_sequence (); |
13121 | top = get_insns (); | |
13122 | pop_topmost_sequence (); | |
5e1bf043 | 13123 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 13124 | |
5e1bf043 DJ |
13125 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
13126 | { | |
13127 | if (INSN_P (insn)) | |
13128 | { | |
13129 | if (FIND_REG_INC_NOTE (insn, reg)) | |
13130 | return 1; | |
f676971a | 13131 | else if (GET_CODE (insn) == CALL_INSN |
c15b529f | 13132 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 13133 | return 1; |
36f7e964 AH |
13134 | else if (set_of (reg, insn) != NULL_RTX |
13135 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
13136 | return 1; |
13137 | } | |
13138 | } | |
13139 | return 0; | |
71f123ca | 13140 | } |
4697a36c | 13141 | \f |
8cd8f856 GK |
13142 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
13143 | static void | |
a2369ed3 | 13144 | rs6000_maybe_dead (rtx insn) |
8cd8f856 GK |
13145 | { |
13146 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
13147 | const0_rtx, | |
13148 | REG_NOTES (insn)); | |
13149 | } | |
13150 | ||
9ebbca7d | 13151 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 13152 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 13153 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
13154 | |
13155 | void | |
a2369ed3 | 13156 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 13157 | { |
027fbf43 | 13158 | rtx dest, insn; |
1db02437 | 13159 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 13160 | |
20b71b17 AM |
13161 | if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
13162 | { | |
13163 | rtx temp = (fromprolog | |
13164 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
13165 | : gen_reg_rtx (Pmode)); | |
027fbf43 JJ |
13166 | insn = emit_insn (gen_load_toc_v4_pic_si (temp)); |
13167 | if (fromprolog) | |
13168 | rs6000_maybe_dead (insn); | |
13169 | insn = emit_move_insn (dest, temp); | |
13170 | if (fromprolog) | |
13171 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
13172 | } |
13173 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
13174 | { | |
13175 | char buf[30]; | |
13176 | rtx tempLR = (fromprolog | |
13177 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
13178 | : gen_reg_rtx (Pmode)); | |
13179 | rtx temp0 = (fromprolog | |
13180 | ? gen_rtx_REG (Pmode, 0) | |
13181 | : gen_reg_rtx (Pmode)); | |
13182 | rtx symF; | |
13183 | ||
13184 | /* possibly create the toc section */ | |
13185 | if (! toc_initialized) | |
38c1f2d7 | 13186 | { |
20b71b17 AM |
13187 | toc_section (); |
13188 | function_section (current_function_decl); | |
38c1f2d7 | 13189 | } |
9ebbca7d | 13190 | |
20b71b17 AM |
13191 | if (fromprolog) |
13192 | { | |
13193 | rtx symL; | |
38c1f2d7 | 13194 | |
20b71b17 AM |
13195 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
13196 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 13197 | |
20b71b17 AM |
13198 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
13199 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
13200 | ||
13201 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
13202 | symF))); | |
13203 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
13204 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
13205 | symL, | |
13206 | symF))); | |
9ebbca7d GK |
13207 | } |
13208 | else | |
20b71b17 AM |
13209 | { |
13210 | rtx tocsym; | |
13211 | static int reload_toc_labelno = 0; | |
13212 | ||
13213 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
13214 | ||
13215 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); | |
13216 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
13217 | ||
027fbf43 JJ |
13218 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym)); |
13219 | emit_move_insn (dest, tempLR); | |
13220 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 13221 | } |
027fbf43 JJ |
13222 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
13223 | if (fromprolog) | |
13224 | rs6000_maybe_dead (insn); | |
9ebbca7d | 13225 | } |
20b71b17 AM |
13226 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
13227 | { | |
13228 | /* This is for AIX code running in non-PIC ELF32. */ | |
13229 | char buf[30]; | |
13230 | rtx realsym; | |
13231 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
13232 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
13233 | ||
027fbf43 JJ |
13234 | insn = emit_insn (gen_elf_high (dest, realsym)); |
13235 | if (fromprolog) | |
13236 | rs6000_maybe_dead (insn); | |
13237 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
13238 | if (fromprolog) | |
13239 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
13240 | } |
13241 | else if (DEFAULT_ABI == ABI_AIX) | |
9ebbca7d GK |
13242 | { |
13243 | if (TARGET_32BIT) | |
027fbf43 | 13244 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 13245 | else |
027fbf43 JJ |
13246 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
13247 | if (fromprolog) | |
13248 | rs6000_maybe_dead (insn); | |
9ebbca7d | 13249 | } |
20b71b17 AM |
13250 | else |
13251 | abort (); | |
9ebbca7d GK |
13252 | } |
13253 | ||
d1d0c603 JJ |
13254 | /* Emit instructions to restore the link register after determining where |
13255 | its value has been stored. */ | |
13256 | ||
13257 | void | |
13258 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
13259 | { | |
13260 | rs6000_stack_t *info = rs6000_stack_info (); | |
13261 | rtx operands[2]; | |
13262 | ||
13263 | operands[0] = source; | |
13264 | operands[1] = scratch; | |
13265 | ||
13266 | if (info->lr_save_p) | |
13267 | { | |
13268 | rtx frame_rtx = stack_pointer_rtx; | |
13269 | HOST_WIDE_INT sp_offset = 0; | |
13270 | rtx tmp; | |
13271 | ||
13272 | if (frame_pointer_needed | |
13273 | || current_function_calls_alloca | |
13274 | || info->total_size > 32767) | |
13275 | { | |
13276 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
13277 | frame_rtx = operands[1]; | |
13278 | } | |
13279 | else if (info->push_p) | |
13280 | sp_offset = info->total_size; | |
13281 | ||
13282 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
13283 | tmp = gen_rtx_MEM (Pmode, tmp); | |
13284 | emit_move_insn (tmp, operands[0]); | |
13285 | } | |
13286 | else | |
13287 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
13288 | } | |
13289 | ||
f103e34d GK |
13290 | static GTY(()) int set = -1; |
13291 | ||
f676971a | 13292 | int |
863d938c | 13293 | get_TOC_alias_set (void) |
9ebbca7d | 13294 | { |
f103e34d GK |
13295 | if (set == -1) |
13296 | set = new_alias_set (); | |
13297 | return set; | |
f676971a | 13298 | } |
9ebbca7d | 13299 | |
c1207243 | 13300 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
13301 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
13302 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 13303 | #if TARGET_ELF |
3c9eb5f4 | 13304 | static int |
f676971a | 13305 | uses_TOC (void) |
9ebbca7d | 13306 | { |
c4501e62 | 13307 | rtx insn; |
38c1f2d7 | 13308 | |
c4501e62 JJ |
13309 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
13310 | if (INSN_P (insn)) | |
13311 | { | |
13312 | rtx pat = PATTERN (insn); | |
13313 | int i; | |
9ebbca7d | 13314 | |
f676971a | 13315 | if (GET_CODE (pat) == PARALLEL) |
c4501e62 JJ |
13316 | for (i = 0; i < XVECLEN (pat, 0); i++) |
13317 | { | |
13318 | rtx sub = XVECEXP (pat, 0, i); | |
13319 | if (GET_CODE (sub) == USE) | |
13320 | { | |
13321 | sub = XEXP (sub, 0); | |
13322 | if (GET_CODE (sub) == UNSPEC | |
13323 | && XINT (sub, 1) == UNSPEC_TOC) | |
13324 | return 1; | |
13325 | } | |
13326 | } | |
13327 | } | |
13328 | return 0; | |
9ebbca7d | 13329 | } |
c954844a | 13330 | #endif |
38c1f2d7 | 13331 | |
9ebbca7d | 13332 | rtx |
f676971a | 13333 | create_TOC_reference (rtx symbol) |
9ebbca7d | 13334 | { |
f676971a | 13335 | return gen_rtx_PLUS (Pmode, |
a8a05998 | 13336 | gen_rtx_REG (Pmode, TOC_REGISTER), |
f676971a EC |
13337 | gen_rtx_CONST (Pmode, |
13338 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 13339 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 13340 | } |
38c1f2d7 | 13341 | |
fc4767bb JJ |
13342 | /* If _Unwind_* has been called from within the same module, |
13343 | toc register is not guaranteed to be saved to 40(1) on function | |
13344 | entry. Save it there in that case. */ | |
c7ca610e | 13345 | |
9ebbca7d | 13346 | void |
863d938c | 13347 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
13348 | { |
13349 | rtx mem; | |
13350 | rtx stack_top = gen_reg_rtx (Pmode); | |
13351 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
13352 | rtx opcode = gen_reg_rtx (SImode); |
13353 | rtx tocompare = gen_reg_rtx (SImode); | |
13354 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d GK |
13355 | |
13356 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
13357 | emit_move_insn (stack_top, mem); | |
13358 | ||
fc4767bb JJ |
13359 | mem = gen_rtx_MEM (Pmode, |
13360 | gen_rtx_PLUS (Pmode, stack_top, | |
9ebbca7d GK |
13361 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); |
13362 | emit_move_insn (opcode_addr, mem); | |
fc4767bb JJ |
13363 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
13364 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 13365 | : 0xE8410028, SImode)); |
9ebbca7d | 13366 | |
fc4767bb | 13367 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 13368 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 13369 | no_toc_save_needed); |
9ebbca7d | 13370 | |
fc4767bb JJ |
13371 | mem = gen_rtx_MEM (Pmode, |
13372 | gen_rtx_PLUS (Pmode, stack_top, | |
13373 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
13374 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); | |
13375 | emit_label (no_toc_save_needed); | |
9ebbca7d | 13376 | } |
38c1f2d7 | 13377 | \f |
ba4828e0 RK |
13378 | /* This ties together stack memory (MEM with an alias set of |
13379 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
13380 | ||
9ebbca7d | 13381 | static void |
863d938c | 13382 | rs6000_emit_stack_tie (void) |
9ebbca7d | 13383 | { |
ba4828e0 RK |
13384 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
13385 | ||
13386 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
13387 | emit_insn (gen_stack_tie (mem)); |
13388 | } | |
38c1f2d7 | 13389 | |
9ebbca7d GK |
13390 | /* Emit the correct code for allocating stack space, as insns. |
13391 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
13392 | The generated code may use hard register 0 as a temporary. */ | |
13393 | ||
13394 | static void | |
a2369ed3 | 13395 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) |
38c1f2d7 | 13396 | { |
9ebbca7d GK |
13397 | rtx insn; |
13398 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
13399 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
61168ff1 RS |
13400 | rtx todec = gen_int_mode (-size, Pmode); |
13401 | ||
13402 | if (INTVAL (todec) != -size) | |
13403 | { | |
13404 | warning("stack frame too large"); | |
13405 | emit_insn (gen_trap ()); | |
13406 | return; | |
13407 | } | |
a157febd GK |
13408 | |
13409 | if (current_function_limit_stack) | |
13410 | { | |
13411 | if (REG_P (stack_limit_rtx) | |
f676971a | 13412 | && REGNO (stack_limit_rtx) > 1 |
a157febd GK |
13413 | && REGNO (stack_limit_rtx) <= 31) |
13414 | { | |
5b71a4e7 | 13415 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
13416 | ? gen_addsi3 (tmp_reg, |
13417 | stack_limit_rtx, | |
13418 | GEN_INT (size)) | |
13419 | : gen_adddi3 (tmp_reg, | |
13420 | stack_limit_rtx, | |
13421 | GEN_INT (size))); | |
5b71a4e7 | 13422 | |
9ebbca7d GK |
13423 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
13424 | const0_rtx)); | |
a157febd GK |
13425 | } |
13426 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 13427 | && TARGET_32BIT |
f607bc57 | 13428 | && DEFAULT_ABI == ABI_V4) |
a157febd | 13429 | { |
9ebbca7d | 13430 | rtx toload = gen_rtx_CONST (VOIDmode, |
f676971a EC |
13431 | gen_rtx_PLUS (Pmode, |
13432 | stack_limit_rtx, | |
9ebbca7d | 13433 | GEN_INT (size))); |
5b71a4e7 | 13434 | |
9ebbca7d GK |
13435 | emit_insn (gen_elf_high (tmp_reg, toload)); |
13436 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
13437 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
13438 | const0_rtx)); | |
a157febd GK |
13439 | } |
13440 | else | |
13441 | warning ("stack limit expression is not supported"); | |
13442 | } | |
13443 | ||
9ebbca7d GK |
13444 | if (copy_r12 || ! TARGET_UPDATE) |
13445 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
13446 | ||
38c1f2d7 MM |
13447 | if (TARGET_UPDATE) |
13448 | { | |
9ebbca7d | 13449 | if (size > 32767) |
38c1f2d7 | 13450 | { |
9ebbca7d GK |
13451 | /* Need a note here so that try_split doesn't get confused. */ |
13452 | if (get_last_insn() == NULL_RTX) | |
2e040219 | 13453 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d GK |
13454 | insn = emit_move_insn (tmp_reg, todec); |
13455 | try_split (PATTERN (insn), insn, 0); | |
13456 | todec = tmp_reg; | |
38c1f2d7 | 13457 | } |
5b71a4e7 DE |
13458 | |
13459 | insn = emit_insn (TARGET_32BIT | |
13460 | ? gen_movsi_update (stack_reg, stack_reg, | |
13461 | todec, stack_reg) | |
c4ad648e | 13462 | : gen_movdi_di_update (stack_reg, stack_reg, |
9ebbca7d | 13463 | todec, stack_reg)); |
38c1f2d7 MM |
13464 | } |
13465 | else | |
13466 | { | |
5b71a4e7 DE |
13467 | insn = emit_insn (TARGET_32BIT |
13468 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
13469 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
13470 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
13471 | gen_rtx_REG (Pmode, 12)); | |
13472 | } | |
f676971a | 13473 | |
9ebbca7d | 13474 | RTX_FRAME_RELATED_P (insn) = 1; |
f676971a | 13475 | REG_NOTES (insn) = |
9ebbca7d | 13476 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, |
f676971a | 13477 | gen_rtx_SET (VOIDmode, stack_reg, |
9ebbca7d GK |
13478 | gen_rtx_PLUS (Pmode, stack_reg, |
13479 | GEN_INT (-size))), | |
13480 | REG_NOTES (insn)); | |
13481 | } | |
13482 | ||
a4f6c312 SS |
13483 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
13484 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
13485 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
13486 | deduce these equivalences by itself so it wasn't necessary to hold | |
13487 | its hand so much. */ | |
9ebbca7d GK |
13488 | |
13489 | static void | |
f676971a | 13490 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
a2369ed3 | 13491 | rtx reg2, rtx rreg) |
9ebbca7d GK |
13492 | { |
13493 | rtx real, temp; | |
13494 | ||
e56c4463 JL |
13495 | /* copy_rtx will not make unique copies of registers, so we need to |
13496 | ensure we don't have unwanted sharing here. */ | |
13497 | if (reg == reg2) | |
13498 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
13499 | ||
13500 | if (reg == rreg) | |
13501 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
13502 | ||
9ebbca7d GK |
13503 | real = copy_rtx (PATTERN (insn)); |
13504 | ||
89e7058f AH |
13505 | if (reg2 != NULL_RTX) |
13506 | real = replace_rtx (real, reg2, rreg); | |
f676971a EC |
13507 | |
13508 | real = replace_rtx (real, reg, | |
9ebbca7d GK |
13509 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, |
13510 | STACK_POINTER_REGNUM), | |
13511 | GEN_INT (val))); | |
f676971a | 13512 | |
9ebbca7d GK |
13513 | /* We expect that 'real' is either a SET or a PARALLEL containing |
13514 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
13515 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
13516 | ||
13517 | if (GET_CODE (real) == SET) | |
13518 | { | |
13519 | rtx set = real; | |
f676971a | 13520 | |
9ebbca7d GK |
13521 | temp = simplify_rtx (SET_SRC (set)); |
13522 | if (temp) | |
13523 | SET_SRC (set) = temp; | |
13524 | temp = simplify_rtx (SET_DEST (set)); | |
13525 | if (temp) | |
13526 | SET_DEST (set) = temp; | |
13527 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 13528 | { |
9ebbca7d GK |
13529 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
13530 | if (temp) | |
13531 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 13532 | } |
38c1f2d7 | 13533 | } |
9ebbca7d GK |
13534 | else if (GET_CODE (real) == PARALLEL) |
13535 | { | |
13536 | int i; | |
13537 | for (i = 0; i < XVECLEN (real, 0); i++) | |
13538 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
13539 | { | |
13540 | rtx set = XVECEXP (real, 0, i); | |
f676971a | 13541 | |
9ebbca7d GK |
13542 | temp = simplify_rtx (SET_SRC (set)); |
13543 | if (temp) | |
13544 | SET_SRC (set) = temp; | |
13545 | temp = simplify_rtx (SET_DEST (set)); | |
13546 | if (temp) | |
13547 | SET_DEST (set) = temp; | |
13548 | if (GET_CODE (SET_DEST (set)) == MEM) | |
13549 | { | |
13550 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
13551 | if (temp) | |
13552 | XEXP (SET_DEST (set), 0) = temp; | |
13553 | } | |
13554 | RTX_FRAME_RELATED_P (set) = 1; | |
13555 | } | |
13556 | } | |
13557 | else | |
a4f6c312 | 13558 | abort (); |
c19de7aa AH |
13559 | |
13560 | if (TARGET_SPE) | |
13561 | real = spe_synthesize_frame_save (real); | |
13562 | ||
9ebbca7d GK |
13563 | RTX_FRAME_RELATED_P (insn) = 1; |
13564 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13565 | real, | |
13566 | REG_NOTES (insn)); | |
38c1f2d7 MM |
13567 | } |
13568 | ||
c19de7aa AH |
13569 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
13570 | original note, plus a synthetic register save. */ | |
13571 | ||
13572 | static rtx | |
a2369ed3 | 13573 | spe_synthesize_frame_save (rtx real) |
c19de7aa AH |
13574 | { |
13575 | rtx synth, offset, reg, real2; | |
13576 | ||
13577 | if (GET_CODE (real) != SET | |
13578 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
13579 | return real; | |
13580 | ||
13581 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
13582 | frame related note. The parallel contains a set of the register | |
41f3a930 | 13583 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
13584 | This is so we can differentiate between 64-bit and 32-bit saves. |
13585 | Words cannot describe this nastiness. */ | |
13586 | ||
13587 | if (GET_CODE (SET_DEST (real)) != MEM | |
13588 | || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS | |
13589 | || GET_CODE (SET_SRC (real)) != REG) | |
13590 | abort (); | |
13591 | ||
13592 | /* Transform: | |
13593 | (set (mem (plus (reg x) (const y))) | |
13594 | (reg z)) | |
13595 | into: | |
13596 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 13597 | (reg z+1200)) |
c19de7aa AH |
13598 | */ |
13599 | ||
13600 | real2 = copy_rtx (real); | |
13601 | PUT_MODE (SET_DEST (real2), SImode); | |
13602 | reg = SET_SRC (real2); | |
13603 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
13604 | synth = copy_rtx (real2); | |
13605 | ||
13606 | if (BYTES_BIG_ENDIAN) | |
13607 | { | |
13608 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
13609 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
13610 | } | |
13611 | ||
13612 | reg = SET_SRC (synth); | |
41f3a930 | 13613 | |
c19de7aa | 13614 | synth = replace_rtx (synth, reg, |
41f3a930 | 13615 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
13616 | |
13617 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
13618 | synth = replace_rtx (synth, offset, | |
13619 | GEN_INT (INTVAL (offset) | |
13620 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
13621 | ||
13622 | RTX_FRAME_RELATED_P (synth) = 1; | |
13623 | RTX_FRAME_RELATED_P (real2) = 1; | |
13624 | if (BYTES_BIG_ENDIAN) | |
13625 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
13626 | else | |
13627 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
13628 | ||
13629 | return real; | |
13630 | } | |
13631 | ||
00b960c7 AH |
13632 | /* Returns an insn that has a vrsave set operation with the |
13633 | appropriate CLOBBERs. */ | |
13634 | ||
13635 | static rtx | |
a2369ed3 | 13636 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
13637 | { |
13638 | int nclobs, i; | |
13639 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 13640 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 13641 | |
a004eb82 AH |
13642 | clobs[0] |
13643 | = gen_rtx_SET (VOIDmode, | |
13644 | vrsave, | |
13645 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
13646 | gen_rtvec (2, reg, vrsave), | |
13647 | 30)); | |
00b960c7 AH |
13648 | |
13649 | nclobs = 1; | |
13650 | ||
9aa86737 AH |
13651 | /* We need to clobber the registers in the mask so the scheduler |
13652 | does not move sets to VRSAVE before sets of AltiVec registers. | |
13653 | ||
13654 | However, if the function receives nonlocal gotos, reload will set | |
13655 | all call saved registers live. We will end up with: | |
13656 | ||
13657 | (set (reg 999) (mem)) | |
13658 | (parallel [ (set (reg vrsave) (unspec blah)) | |
13659 | (clobber (reg 999))]) | |
13660 | ||
13661 | The clobber will cause the store into reg 999 to be dead, and | |
13662 | flow will attempt to delete an epilogue insn. In this case, we | |
13663 | need an unspec use/set of the register. */ | |
00b960c7 AH |
13664 | |
13665 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
44688022 | 13666 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) |
9aa86737 AH |
13667 | { |
13668 | if (!epiloguep || call_used_regs [i]) | |
13669 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
13670 | gen_rtx_REG (V4SImode, i)); | |
13671 | else | |
13672 | { | |
13673 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
13674 | |
13675 | clobs[nclobs++] | |
a004eb82 AH |
13676 | = gen_rtx_SET (VOIDmode, |
13677 | reg, | |
13678 | gen_rtx_UNSPEC (V4SImode, | |
13679 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
13680 | } |
13681 | } | |
00b960c7 AH |
13682 | |
13683 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
13684 | ||
13685 | for (i = 0; i < nclobs; ++i) | |
13686 | XVECEXP (insn, 0, i) = clobs[i]; | |
13687 | ||
13688 | return insn; | |
13689 | } | |
13690 | ||
89e7058f AH |
13691 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
13692 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
13693 | ||
13694 | static void | |
f676971a | 13695 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 13696 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
13697 | { |
13698 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
13699 | rtx replacea, replaceb; | |
13700 | ||
13701 | int_rtx = GEN_INT (offset); | |
13702 | ||
13703 | /* Some cases that need register indexed addressing. */ | |
13704 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
4d4cbc0e | 13705 | || (TARGET_E500_DOUBLE && mode == DFmode) |
a3170dc6 AH |
13706 | || (TARGET_SPE_ABI |
13707 | && SPE_VECTOR_MODE (mode) | |
13708 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
13709 | { |
13710 | /* Whomever calls us must make sure r11 is available in the | |
c4ad648e | 13711 | flow path of instructions in the prologue. */ |
89e7058f AH |
13712 | offset_rtx = gen_rtx_REG (Pmode, 11); |
13713 | emit_move_insn (offset_rtx, int_rtx); | |
13714 | ||
13715 | replacea = offset_rtx; | |
13716 | replaceb = int_rtx; | |
13717 | } | |
13718 | else | |
13719 | { | |
13720 | offset_rtx = int_rtx; | |
13721 | replacea = NULL_RTX; | |
13722 | replaceb = NULL_RTX; | |
13723 | } | |
13724 | ||
13725 | reg = gen_rtx_REG (mode, regno); | |
13726 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
13727 | mem = gen_rtx_MEM (mode, addr); | |
13728 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13729 | ||
13730 | insn = emit_move_insn (mem, reg); | |
13731 | ||
13732 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
13733 | } | |
13734 | ||
a3170dc6 AH |
13735 | /* Emit an offset memory reference suitable for a frame store, while |
13736 | converting to a valid addressing mode. */ | |
13737 | ||
13738 | static rtx | |
a2369ed3 | 13739 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
13740 | { |
13741 | rtx int_rtx, offset_rtx; | |
13742 | ||
13743 | int_rtx = GEN_INT (offset); | |
13744 | ||
4d4cbc0e AH |
13745 | if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) |
13746 | || (TARGET_E500_DOUBLE && mode == DFmode)) | |
a3170dc6 AH |
13747 | { |
13748 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13749 | emit_move_insn (offset_rtx, int_rtx); | |
13750 | } | |
13751 | else | |
13752 | offset_rtx = int_rtx; | |
13753 | ||
13754 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
13755 | } | |
13756 | ||
699c914a MS |
13757 | #ifndef TARGET_FIX_AND_CONTINUE |
13758 | #define TARGET_FIX_AND_CONTINUE 0 | |
13759 | #endif | |
13760 | ||
9ebbca7d GK |
13761 | /* Emit function prologue as insns. */ |
13762 | ||
9878760c | 13763 | void |
863d938c | 13764 | rs6000_emit_prologue (void) |
9878760c | 13765 | { |
4697a36c | 13766 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a | 13767 | enum machine_mode reg_mode = Pmode; |
327e5343 | 13768 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
13769 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
13770 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
13771 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 13772 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d GK |
13773 | rtx insn; |
13774 | int saving_FPRs_inline; | |
13775 | int using_store_multiple; | |
13776 | HOST_WIDE_INT sp_offset = 0; | |
f676971a | 13777 | |
699c914a MS |
13778 | if (TARGET_FIX_AND_CONTINUE) |
13779 | { | |
13780 | /* gdb on darwin arranges to forward a function from the old | |
13781 | address by modifying the first 4 instructions of the function | |
13782 | to branch to the overriding function. This is necessary to | |
13783 | permit function pointers that point to the old function to | |
13784 | actually forward to the new function. */ | |
13785 | emit_insn (gen_nop ()); | |
13786 | emit_insn (gen_nop ()); | |
13787 | emit_insn (gen_nop ()); | |
13788 | emit_insn (gen_nop ()); | |
13789 | } | |
13790 | ||
13791 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
13792 | { | |
13793 | reg_mode = V2SImode; | |
13794 | reg_size = 8; | |
13795 | } | |
a3170dc6 | 13796 | |
9ebbca7d | 13797 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
13798 | && (!TARGET_SPE_ABI |
13799 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
13800 | && info->first_gp_reg_save < 31); |
13801 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8c29550d | 13802 | || FP_SAVE_INLINE (info->first_fp_reg_save) |
acd0b319 | 13803 | || current_function_calls_eh_return |
8c29550d | 13804 | || cfun->machine->ra_need_lr); |
9ebbca7d GK |
13805 | |
13806 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
fc4767bb | 13807 | if (info->push_p |
acd0b319 AM |
13808 | && (DEFAULT_ABI == ABI_V4 |
13809 | || current_function_calls_eh_return)) | |
9ebbca7d GK |
13810 | { |
13811 | if (info->total_size < 32767) | |
13812 | sp_offset = info->total_size; | |
13813 | else | |
13814 | frame_reg_rtx = frame_ptr_rtx; | |
f676971a | 13815 | rs6000_emit_allocate_stack (info->total_size, |
9ebbca7d GK |
13816 | (frame_reg_rtx != sp_reg_rtx |
13817 | && (info->cr_save_p | |
13818 | || info->lr_save_p | |
13819 | || info->first_fp_reg_save < 64 | |
13820 | || info->first_gp_reg_save < 32 | |
13821 | ))); | |
13822 | if (frame_reg_rtx != sp_reg_rtx) | |
13823 | rs6000_emit_stack_tie (); | |
13824 | } | |
13825 | ||
d62294f5 FJ |
13826 | /* Handle world saves specially here. */ |
13827 | if (info->world_save_p) | |
13828 | { | |
13829 | int i, j, sz; | |
13830 | rtx treg; | |
13831 | rtvec p; | |
13832 | ||
13833 | /* save_world expects lr in r0. */ | |
13834 | if (info->lr_save_p) | |
c4ad648e AM |
13835 | { |
13836 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
13837 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
13838 | RTX_FRAME_RELATED_P (insn) = 1; | |
13839 | } | |
d62294f5 FJ |
13840 | |
13841 | /* The SAVE_WORLD and RESTORE_WORLD routines make a number of | |
c4ad648e AM |
13842 | assumptions about the offsets of various bits of the stack |
13843 | frame. Abort if things aren't what they should be. */ | |
d62294f5 | 13844 | if (info->gp_save_offset != -220 |
c4ad648e AM |
13845 | || info->fp_save_offset != -144 |
13846 | || info->lr_save_offset != 8 | |
13847 | || info->cr_save_offset != 4 | |
13848 | || !info->push_p | |
13849 | || !info->lr_save_p | |
13850 | || (current_function_calls_eh_return && info->ehrd_offset != -432) | |
13851 | || (info->vrsave_save_offset != -224 | |
13852 | || info->altivec_save_offset != (-224 -16 -192))) | |
13853 | abort (); | |
d62294f5 FJ |
13854 | |
13855 | treg = gen_rtx_REG (SImode, 11); | |
13856 | emit_move_insn (treg, GEN_INT (-info->total_size)); | |
13857 | ||
13858 | /* SAVE_WORLD takes the caller's LR in R0 and the frame size | |
c4ad648e | 13859 | in R11. It also clobbers R12, so beware! */ |
d62294f5 FJ |
13860 | |
13861 | /* Preserve CR2 for save_world prologues */ | |
13862 | sz = 6; | |
13863 | sz += 32 - info->first_gp_reg_save; | |
13864 | sz += 64 - info->first_fp_reg_save; | |
13865 | sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1; | |
13866 | p = rtvec_alloc (sz); | |
13867 | j = 0; | |
13868 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, | |
c4ad648e AM |
13869 | gen_rtx_REG (Pmode, |
13870 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 13871 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, |
c4ad648e AM |
13872 | gen_rtx_SYMBOL_REF (Pmode, |
13873 | "*save_world")); | |
d62294f5 | 13874 | /* We do floats first so that the instruction pattern matches |
c4ad648e AM |
13875 | properly. */ |
13876 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
13877 | { | |
13878 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
13879 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13880 | GEN_INT (info->fp_save_offset | |
13881 | + sp_offset + 8 * i)); | |
13882 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
13883 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13884 | ||
13885 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13886 | } | |
d62294f5 | 13887 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
13888 | { |
13889 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
13890 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13891 | GEN_INT (info->altivec_save_offset | |
13892 | + sp_offset + 16 * i)); | |
13893 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
13894 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13895 | ||
13896 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13897 | } | |
d62294f5 | 13898 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
c4ad648e AM |
13899 | { |
13900 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
13901 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13902 | GEN_INT (info->gp_save_offset | |
13903 | + sp_offset + reg_size * i)); | |
13904 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13905 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13906 | ||
13907 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13908 | } | |
13909 | ||
13910 | { | |
13911 | /* CR register traditionally saved as CR2. */ | |
13912 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
13913 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13914 | GEN_INT (info->cr_save_offset | |
13915 | + sp_offset)); | |
13916 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13917 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13918 | ||
13919 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13920 | } | |
d62294f5 FJ |
13921 | /* Prevent any attempt to delete the setting of r0 and treg! */ |
13922 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0)); | |
13923 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg); | |
13924 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx); | |
13925 | ||
13926 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
13927 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
c4ad648e | 13928 | NULL_RTX, NULL_RTX); |
d62294f5 FJ |
13929 | |
13930 | if (current_function_calls_eh_return) | |
c4ad648e AM |
13931 | { |
13932 | unsigned int i; | |
13933 | for (i = 0; ; ++i) | |
13934 | { | |
13935 | unsigned int regno = EH_RETURN_DATA_REGNO (i); | |
13936 | if (regno == INVALID_REGNUM) | |
13937 | break; | |
13938 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, | |
13939 | info->ehrd_offset + sp_offset | |
13940 | + reg_size * (int) i, | |
13941 | info->total_size); | |
13942 | } | |
13943 | } | |
d62294f5 FJ |
13944 | } |
13945 | ||
9aa86737 | 13946 | /* Save AltiVec registers if needed. */ |
d62294f5 | 13947 | if (! info->world_save_p && TARGET_ALTIVEC_ABI && info->altivec_size != 0) |
9aa86737 AH |
13948 | { |
13949 | int i; | |
13950 | ||
13951 | /* There should be a non inline version of this, for when we | |
13952 | are saving lots of vector registers. */ | |
13953 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
13954 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
13955 | { | |
13956 | rtx areg, savereg, mem; | |
13957 | int offset; | |
13958 | ||
13959 | offset = info->altivec_save_offset + sp_offset | |
13960 | + 16 * (i - info->first_altivec_reg_save); | |
13961 | ||
13962 | savereg = gen_rtx_REG (V4SImode, i); | |
13963 | ||
13964 | areg = gen_rtx_REG (Pmode, 0); | |
13965 | emit_move_insn (areg, GEN_INT (offset)); | |
13966 | ||
13967 | /* AltiVec addressing mode is [reg+reg]. */ | |
13968 | mem = gen_rtx_MEM (V4SImode, | |
13969 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
f676971a | 13970 | |
9aa86737 AH |
13971 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
13972 | ||
13973 | insn = emit_move_insn (mem, savereg); | |
13974 | ||
5c242421 SB |
13975 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
13976 | areg, GEN_INT (offset)); | |
9aa86737 AH |
13977 | } |
13978 | } | |
13979 | ||
13980 | /* VRSAVE is a bit vector representing which AltiVec registers | |
13981 | are used. The OS uses this to determine which vector | |
13982 | registers to save on a context switch. We need to save | |
13983 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
13984 | used in this function, and do the corresponding magic in the | |
13985 | epilogue. */ | |
13986 | ||
4d774ff8 | 13987 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
d62294f5 | 13988 | && ! info->world_save_p && info->vrsave_mask != 0) |
9aa86737 | 13989 | { |
a004eb82 | 13990 | rtx reg, mem, vrsave; |
9aa86737 AH |
13991 | int offset; |
13992 | ||
13993 | /* Get VRSAVE onto a GPR. */ | |
13994 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 | 13995 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
13996 | if (TARGET_MACHO) |
13997 | emit_insn (gen_get_vrsave_internal (reg)); | |
13998 | else | |
13999 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
14000 | |
14001 | /* Save VRSAVE. */ | |
14002 | offset = info->vrsave_save_offset + sp_offset; | |
14003 | mem | |
14004 | = gen_rtx_MEM (SImode, | |
14005 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
14006 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14007 | insn = emit_move_insn (mem, reg); | |
14008 | ||
14009 | /* Include the registers in the mask. */ | |
14010 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
14011 | ||
14012 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
14013 | } | |
14014 | ||
9ebbca7d | 14015 | /* If we use the link register, get it into r0. */ |
d62294f5 | 14016 | if (! info->world_save_p && info->lr_save_p) |
f8a57be8 GK |
14017 | { |
14018 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
14019 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
14020 | RTX_FRAME_RELATED_P (insn) = 1; | |
14021 | } | |
9ebbca7d GK |
14022 | |
14023 | /* If we need to save CR, put it into r12. */ | |
d62294f5 | 14024 | if (! info->world_save_p && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) |
9ebbca7d | 14025 | { |
f8a57be8 | 14026 | rtx set; |
f676971a | 14027 | |
9ebbca7d | 14028 | cr_save_rtx = gen_rtx_REG (SImode, 12); |
f8a57be8 GK |
14029 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
14030 | RTX_FRAME_RELATED_P (insn) = 1; | |
14031 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
14032 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. | |
14033 | But that's OK. All we have to do is specify that _one_ condition | |
14034 | code register is saved in this stack slot. The thrower's epilogue | |
14035 | will then restore all the call-saved registers. | |
14036 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
14037 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, | |
14038 | gen_rtx_REG (SImode, CR2_REGNO)); | |
14039 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
14040 | set, | |
14041 | REG_NOTES (insn)); | |
9ebbca7d GK |
14042 | } |
14043 | ||
a4f6c312 SS |
14044 | /* Do any required saving of fpr's. If only one or two to save, do |
14045 | it ourselves. Otherwise, call function. */ | |
d62294f5 | 14046 | if (! info->world_save_p && saving_FPRs_inline) |
9ebbca7d GK |
14047 | { |
14048 | int i; | |
14049 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 14050 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d | 14051 | && ! call_used_regs[info->first_fp_reg_save+i])) |
89e7058f AH |
14052 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
14053 | info->first_fp_reg_save + i, | |
14054 | info->fp_save_offset + sp_offset + 8 * i, | |
14055 | info->total_size); | |
9ebbca7d | 14056 | } |
d62294f5 | 14057 | else if (! info->world_save_p && info->first_fp_reg_save != 64) |
9ebbca7d GK |
14058 | { |
14059 | int i; | |
14060 | char rname[30]; | |
520a57c8 | 14061 | const char *alloc_rname; |
9ebbca7d GK |
14062 | rtvec p; |
14063 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
f676971a EC |
14064 | |
14065 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
14066 | gen_rtx_REG (Pmode, | |
9ebbca7d GK |
14067 | LINK_REGISTER_REGNUM)); |
14068 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
14069 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 14070 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
14071 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
14072 | gen_rtx_SYMBOL_REF (Pmode, | |
14073 | alloc_rname)); | |
14074 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
14075 | { | |
14076 | rtx addr, reg, mem; | |
14077 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
14078 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a | 14079 | GEN_INT (info->fp_save_offset |
9ebbca7d GK |
14080 | + sp_offset + 8*i)); |
14081 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 14082 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
14083 | |
14084 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
14085 | } | |
14086 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 14087 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d GK |
14088 | NULL_RTX, NULL_RTX); |
14089 | } | |
b6c9286a | 14090 | |
9ebbca7d GK |
14091 | /* Save GPRs. This is done as a PARALLEL if we are using |
14092 | the store-multiple instructions. */ | |
d62294f5 | 14093 | if (! info->world_save_p && using_store_multiple) |
b6c9286a | 14094 | { |
308c142a | 14095 | rtvec p; |
9ebbca7d GK |
14096 | int i; |
14097 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
14098 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
14099 | { | |
14100 | rtx addr, reg, mem; | |
14101 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
f676971a EC |
14102 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14103 | GEN_INT (info->gp_save_offset | |
14104 | + sp_offset | |
9ebbca7d GK |
14105 | + reg_size * i)); |
14106 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 14107 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
14108 | |
14109 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
14110 | } | |
14111 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 14112 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d | 14113 | NULL_RTX, NULL_RTX); |
b6c9286a | 14114 | } |
d62294f5 | 14115 | else if (! info->world_save_p) |
b6c9286a | 14116 | { |
9ebbca7d GK |
14117 | int i; |
14118 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
f676971a | 14119 | if ((regs_ever_live[info->first_gp_reg_save+i] |
b4db40bf JJ |
14120 | && (! call_used_regs[info->first_gp_reg_save+i] |
14121 | || (i+info->first_gp_reg_save | |
14122 | == RS6000_PIC_OFFSET_TABLE_REGNUM | |
14123 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 14124 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 14125 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 14126 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
14127 | { |
14128 | rtx addr, reg, mem; | |
14129 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
14130 | ||
c19de7aa | 14131 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
14132 | { |
14133 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
14134 | rtx b; | |
14135 | ||
14136 | if (!SPE_CONST_OFFSET_OK (offset)) | |
14137 | { | |
14138 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
14139 | emit_move_insn (b, GEN_INT (offset)); | |
14140 | } | |
14141 | else | |
14142 | b = GEN_INT (offset); | |
14143 | ||
14144 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
14145 | mem = gen_rtx_MEM (V2SImode, addr); | |
14146 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14147 | insn = emit_move_insn (mem, reg); | |
14148 | ||
14149 | if (GET_CODE (b) == CONST_INT) | |
14150 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
14151 | NULL_RTX, NULL_RTX); | |
14152 | else | |
14153 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
14154 | b, GEN_INT (offset)); | |
14155 | } | |
14156 | else | |
14157 | { | |
f676971a EC |
14158 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14159 | GEN_INT (info->gp_save_offset | |
14160 | + sp_offset | |
a3170dc6 AH |
14161 | + reg_size * i)); |
14162 | mem = gen_rtx_MEM (reg_mode, addr); | |
14163 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14164 | ||
14165 | insn = emit_move_insn (mem, reg); | |
f676971a | 14166 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a3170dc6 AH |
14167 | NULL_RTX, NULL_RTX); |
14168 | } | |
14169 | } | |
9ebbca7d GK |
14170 | } |
14171 | ||
83720594 RH |
14172 | /* ??? There's no need to emit actual instructions here, but it's the |
14173 | easiest way to get the frame unwind information emitted. */ | |
d62294f5 | 14174 | if (! info->world_save_p && current_function_calls_eh_return) |
83720594 | 14175 | { |
78e1b90d DE |
14176 | unsigned int i, regno; |
14177 | ||
fc4767bb JJ |
14178 | /* In AIX ABI we need to pretend we save r2 here. */ |
14179 | if (TARGET_AIX) | |
14180 | { | |
14181 | rtx addr, reg, mem; | |
14182 | ||
14183 | reg = gen_rtx_REG (reg_mode, 2); | |
14184 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14185 | GEN_INT (sp_offset + 5 * reg_size)); | |
14186 | mem = gen_rtx_MEM (reg_mode, addr); | |
14187 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14188 | ||
14189 | insn = emit_move_insn (mem, reg); | |
f676971a | 14190 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
fc4767bb JJ |
14191 | NULL_RTX, NULL_RTX); |
14192 | PATTERN (insn) = gen_blockage (); | |
14193 | } | |
14194 | ||
83720594 RH |
14195 | for (i = 0; ; ++i) |
14196 | { | |
83720594 RH |
14197 | regno = EH_RETURN_DATA_REGNO (i); |
14198 | if (regno == INVALID_REGNUM) | |
14199 | break; | |
14200 | ||
89e7058f AH |
14201 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
14202 | info->ehrd_offset + sp_offset | |
14203 | + reg_size * (int) i, | |
14204 | info->total_size); | |
83720594 RH |
14205 | } |
14206 | } | |
14207 | ||
9ebbca7d | 14208 | /* Save lr if we used it. */ |
d62294f5 | 14209 | if (! info->world_save_p && info->lr_save_p) |
9ebbca7d GK |
14210 | { |
14211 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14212 | GEN_INT (info->lr_save_offset + sp_offset)); | |
14213 | rtx reg = gen_rtx_REG (Pmode, 0); | |
14214 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
14215 | /* This should not be of rs6000_sr_alias_set, because of | |
14216 | __builtin_return_address. */ | |
f676971a | 14217 | |
9ebbca7d | 14218 | insn = emit_move_insn (mem, reg); |
f676971a | 14219 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 14220 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
14221 | } |
14222 | ||
14223 | /* Save CR if we use any that must be preserved. */ | |
d62294f5 | 14224 | if (! info->world_save_p && info->cr_save_p) |
9ebbca7d GK |
14225 | { |
14226 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14227 | GEN_INT (info->cr_save_offset + sp_offset)); | |
14228 | rtx mem = gen_rtx_MEM (SImode, addr); | |
f8a57be8 GK |
14229 | /* See the large comment above about why CR2_REGNO is used. */ |
14230 | rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); | |
ba4828e0 RK |
14231 | |
14232 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
14233 | |
14234 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
14235 | that it's free. */ | |
14236 | if (REGNO (frame_reg_rtx) == 12) | |
14237 | { | |
f8a57be8 GK |
14238 | rtx set; |
14239 | ||
9ebbca7d | 14240 | cr_save_rtx = gen_rtx_REG (SImode, 0); |
f8a57be8 GK |
14241 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
14242 | RTX_FRAME_RELATED_P (insn) = 1; | |
14243 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); | |
14244 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
14245 | set, | |
14246 | REG_NOTES (insn)); | |
f676971a | 14247 | |
9ebbca7d GK |
14248 | } |
14249 | insn = emit_move_insn (mem, cr_save_rtx); | |
14250 | ||
f676971a | 14251 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 14252 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
14253 | } |
14254 | ||
f676971a | 14255 | /* Update stack and set back pointer unless this is V.4, |
9ebbca7d | 14256 | for which it was done previously. */ |
d62294f5 | 14257 | if (! info->world_save_p && info->push_p |
fc4767bb | 14258 | && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) |
9ebbca7d GK |
14259 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
14260 | ||
14261 | /* Set frame pointer, if needed. */ | |
14262 | if (frame_pointer_needed) | |
14263 | { | |
f676971a | 14264 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
14265 | sp_reg_rtx); |
14266 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 14267 | } |
9878760c | 14268 | |
1db02437 | 14269 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 14270 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
f607bc57 | 14271 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
1db02437 | 14272 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
c4ad648e AM |
14273 | { |
14274 | /* If emit_load_toc_table will use the link register, we need to save | |
14275 | it. We use R12 for this purpose because emit_load_toc_table | |
14276 | can use register 0. This allows us to use a plain 'blr' to return | |
14277 | from the procedure more often. */ | |
14278 | int save_LR_around_toc_setup = (TARGET_ELF | |
14279 | && DEFAULT_ABI != ABI_AIX | |
14280 | && flag_pic | |
14281 | && ! info->lr_save_p | |
14282 | && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); | |
14283 | if (save_LR_around_toc_setup) | |
14284 | { | |
14285 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f8a57be8 | 14286 | |
c4ad648e AM |
14287 | insn = emit_move_insn (frame_ptr_rtx, lr); |
14288 | rs6000_maybe_dead (insn); | |
14289 | RTX_FRAME_RELATED_P (insn) = 1; | |
f8a57be8 | 14290 | |
c4ad648e | 14291 | rs6000_emit_load_toc_table (TRUE); |
f8a57be8 | 14292 | |
c4ad648e AM |
14293 | insn = emit_move_insn (lr, frame_ptr_rtx); |
14294 | rs6000_maybe_dead (insn); | |
14295 | RTX_FRAME_RELATED_P (insn) = 1; | |
14296 | } | |
14297 | else | |
14298 | rs6000_emit_load_toc_table (TRUE); | |
14299 | } | |
ee890fe2 | 14300 | |
fcce224d | 14301 | #if TARGET_MACHO |
ee890fe2 SS |
14302 | if (DEFAULT_ABI == ABI_DARWIN |
14303 | && flag_pic && current_function_uses_pic_offset_table) | |
14304 | { | |
f8a57be8 | 14305 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
11abc112 | 14306 | rtx src = machopic_function_base_sym (); |
ee890fe2 | 14307 | |
f8a57be8 | 14308 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); |
ee890fe2 | 14309 | |
f676971a | 14310 | insn = emit_move_insn (gen_rtx_REG (Pmode, |
f8a57be8 GK |
14311 | RS6000_PIC_OFFSET_TABLE_REGNUM), |
14312 | lr); | |
14313 | rs6000_maybe_dead (insn); | |
ee890fe2 | 14314 | } |
fcce224d | 14315 | #endif |
9ebbca7d GK |
14316 | } |
14317 | ||
9ebbca7d | 14318 | /* Write function prologue. */ |
a4f6c312 | 14319 | |
08c148a8 | 14320 | static void |
f676971a | 14321 | rs6000_output_function_prologue (FILE *file, |
a2369ed3 | 14322 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9ebbca7d GK |
14323 | { |
14324 | rs6000_stack_t *info = rs6000_stack_info (); | |
14325 | ||
4697a36c MM |
14326 | if (TARGET_DEBUG_STACK) |
14327 | debug_stack_info (info); | |
9878760c | 14328 | |
a4f6c312 SS |
14329 | /* Write .extern for any function we will call to save and restore |
14330 | fp values. */ | |
14331 | if (info->first_fp_reg_save < 64 | |
14332 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 14333 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 14334 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
14335 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
14336 | RESTORE_FP_SUFFIX); | |
9878760c | 14337 | |
c764f757 RK |
14338 | /* Write .extern for AIX common mode routines, if needed. */ |
14339 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
14340 | { | |
f6709c70 JW |
14341 | fputs ("\t.extern __mulh\n", file); |
14342 | fputs ("\t.extern __mull\n", file); | |
14343 | fputs ("\t.extern __divss\n", file); | |
14344 | fputs ("\t.extern __divus\n", file); | |
14345 | fputs ("\t.extern __quoss\n", file); | |
14346 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
14347 | common_mode_defined = 1; |
14348 | } | |
9878760c | 14349 | |
9ebbca7d | 14350 | if (! HAVE_prologue) |
979721f8 | 14351 | { |
9ebbca7d | 14352 | start_sequence (); |
9dda4cc8 | 14353 | |
a4f6c312 SS |
14354 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
14355 | the "toplevel" insn chain. */ | |
2e040219 | 14356 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 14357 | rs6000_emit_prologue (); |
2e040219 | 14358 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 14359 | |
a3c9585f | 14360 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
14361 | { |
14362 | rtx insn; | |
14363 | unsigned addr = 0; | |
14364 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
14365 | { | |
14366 | INSN_ADDRESSES_NEW (insn, addr); | |
14367 | addr += 4; | |
14368 | } | |
14369 | } | |
9dda4cc8 | 14370 | |
9ebbca7d | 14371 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
14372 | debug_rtx_list (get_insns (), 100); |
14373 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 14374 | end_sequence (); |
979721f8 MM |
14375 | } |
14376 | ||
9ebbca7d GK |
14377 | rs6000_pic_labelno++; |
14378 | } | |
f676971a | 14379 | |
9ebbca7d | 14380 | /* Emit function epilogue as insns. |
9878760c | 14381 | |
9ebbca7d GK |
14382 | At present, dwarf2out_frame_debug_expr doesn't understand |
14383 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
14384 | anywhere in the epilogue. Most of the insns below would in any case | |
14385 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 14386 | |
9ebbca7d | 14387 | void |
a2369ed3 | 14388 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
14389 | { |
14390 | rs6000_stack_t *info; | |
14391 | int restoring_FPRs_inline; | |
14392 | int using_load_multiple; | |
14393 | int using_mfcr_multiple; | |
14394 | int use_backchain_to_restore_sp; | |
14395 | int sp_offset = 0; | |
14396 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
14397 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a | 14398 | enum machine_mode reg_mode = Pmode; |
327e5343 | 14399 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
14400 | int i; |
14401 | ||
c19de7aa AH |
14402 | info = rs6000_stack_info (); |
14403 | ||
14404 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
14405 | { |
14406 | reg_mode = V2SImode; | |
14407 | reg_size = 8; | |
14408 | } | |
14409 | ||
9ebbca7d | 14410 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
14411 | && (!TARGET_SPE_ABI |
14412 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
14413 | && info->first_gp_reg_save < 31); |
14414 | restoring_FPRs_inline = (sibcall | |
83720594 | 14415 | || current_function_calls_eh_return |
9ebbca7d GK |
14416 | || info->first_fp_reg_save == 64 |
14417 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
f676971a | 14418 | use_backchain_to_restore_sp = (frame_pointer_needed |
9ebbca7d GK |
14419 | || current_function_calls_alloca |
14420 | || info->total_size > 32767); | |
14421 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
14422 | || rs6000_cpu == PROCESSOR_PPC603 | |
14423 | || rs6000_cpu == PROCESSOR_PPC750 | |
14424 | || optimize_size); | |
14425 | ||
d62294f5 FJ |
14426 | if (info->world_save_p) |
14427 | { | |
14428 | int i, j; | |
14429 | char rname[30]; | |
14430 | const char *alloc_rname; | |
14431 | rtvec p; | |
14432 | ||
14433 | /* eh_rest_world_r10 will return to the location saved in the LR | |
c4ad648e AM |
14434 | stack slot (which is not likely to be our caller.) |
14435 | Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8. | |
14436 | rest_world is similar, except any R10 parameter is ignored. | |
14437 | The exception-handling stuff that was here in 2.95 is no | |
14438 | longer necessary. */ | |
d62294f5 FJ |
14439 | |
14440 | p = rtvec_alloc (9 | |
14441 | + 1 | |
f676971a | 14442 | + 32 - info->first_gp_reg_save |
c4ad648e AM |
14443 | + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save |
14444 | + 63 + 1 - info->first_fp_reg_save); | |
d62294f5 | 14445 | |
c4ad648e AM |
14446 | strcpy (rname, ((current_function_calls_eh_return) ? |
14447 | "*eh_rest_world_r10" : "*rest_world")); | |
d62294f5 FJ |
14448 | alloc_rname = ggc_strdup (rname); |
14449 | ||
14450 | j = 0; | |
14451 | RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); | |
14452 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, | |
c4ad648e AM |
14453 | gen_rtx_REG (Pmode, |
14454 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 14455 | RTVEC_ELT (p, j++) |
c4ad648e | 14456 | = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname)); |
d62294f5 | 14457 | /* The instruction pattern requires a clobber here; |
c4ad648e | 14458 | it is shared with the restVEC helper. */ |
d62294f5 | 14459 | RTVEC_ELT (p, j++) |
c4ad648e | 14460 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11)); |
d62294f5 FJ |
14461 | |
14462 | { | |
c4ad648e AM |
14463 | /* CR register traditionally saved as CR2. */ |
14464 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
14465 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14466 | GEN_INT (info->cr_save_offset)); | |
14467 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
14468 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14469 | ||
14470 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
d62294f5 FJ |
14471 | } |
14472 | ||
14473 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
c4ad648e AM |
14474 | { |
14475 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
14476 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14477 | GEN_INT (info->gp_save_offset | |
14478 | + reg_size * i)); | |
14479 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
14480 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14481 | ||
14482 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14483 | } | |
d62294f5 | 14484 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
14485 | { |
14486 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
14487 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14488 | GEN_INT (info->altivec_save_offset | |
14489 | + 16 * i)); | |
14490 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
14491 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14492 | ||
14493 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14494 | } | |
d62294f5 | 14495 | for (i = 0; info->first_fp_reg_save + i <= 63; i++) |
c4ad648e AM |
14496 | { |
14497 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
14498 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14499 | GEN_INT (info->fp_save_offset | |
14500 | + 8 * i)); | |
14501 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
14502 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14503 | ||
14504 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14505 | } | |
d62294f5 | 14506 | RTVEC_ELT (p, j++) |
c4ad648e | 14507 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0)); |
d62294f5 | 14508 | RTVEC_ELT (p, j++) |
c4ad648e | 14509 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12)); |
d62294f5 | 14510 | RTVEC_ELT (p, j++) |
c4ad648e | 14511 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7)); |
d62294f5 | 14512 | RTVEC_ELT (p, j++) |
c4ad648e | 14513 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8)); |
d62294f5 | 14514 | RTVEC_ELT (p, j++) |
c4ad648e | 14515 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10)); |
d62294f5 FJ |
14516 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
14517 | ||
14518 | return; | |
14519 | } | |
14520 | ||
9ebbca7d GK |
14521 | /* If we have a frame pointer, a call to alloca, or a large stack |
14522 | frame, restore the old stack pointer using the backchain. Otherwise, | |
14523 | we know what size to update it with. */ | |
14524 | if (use_backchain_to_restore_sp) | |
bacbde18 | 14525 | { |
9ebbca7d GK |
14526 | /* Under V.4, don't reset the stack pointer until after we're done |
14527 | loading the saved registers. */ | |
f607bc57 | 14528 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 14529 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 14530 | |
9ebbca7d GK |
14531 | emit_move_insn (frame_reg_rtx, |
14532 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
f676971a | 14533 | |
bacbde18 | 14534 | } |
9ebbca7d | 14535 | else if (info->push_p) |
85638c0d | 14536 | { |
fc4767bb JJ |
14537 | if (DEFAULT_ABI == ABI_V4 |
14538 | || current_function_calls_eh_return) | |
9ebbca7d GK |
14539 | sp_offset = info->total_size; |
14540 | else | |
14541 | { | |
14542 | emit_insn (TARGET_32BIT | |
14543 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
14544 | GEN_INT (info->total_size)) | |
14545 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
14546 | GEN_INT (info->total_size))); | |
14547 | } | |
85638c0d | 14548 | } |
f676971a | 14549 | |
9aa86737 AH |
14550 | /* Restore AltiVec registers if needed. */ |
14551 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
14552 | { | |
14553 | int i; | |
14554 | ||
14555 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
14556 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
14557 | { | |
14558 | rtx addr, areg, mem; | |
14559 | ||
14560 | areg = gen_rtx_REG (Pmode, 0); | |
14561 | emit_move_insn | |
14562 | (areg, GEN_INT (info->altivec_save_offset | |
14563 | + sp_offset | |
14564 | + 16 * (i - info->first_altivec_reg_save))); | |
14565 | ||
14566 | /* AltiVec addressing mode is [reg+reg]. */ | |
14567 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
14568 | mem = gen_rtx_MEM (V4SImode, addr); | |
14569 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14570 | ||
14571 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
14572 | } | |
14573 | } | |
14574 | ||
14575 | /* Restore VRSAVE if needed. */ | |
44688022 | 14576 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
4d774ff8 | 14577 | && info->vrsave_mask != 0) |
9aa86737 AH |
14578 | { |
14579 | rtx addr, mem, reg; | |
14580 | ||
14581 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14582 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
14583 | mem = gen_rtx_MEM (SImode, addr); | |
14584 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14585 | reg = gen_rtx_REG (SImode, 12); | |
14586 | emit_move_insn (reg, mem); | |
14587 | ||
14588 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
14589 | } | |
14590 | ||
9ebbca7d GK |
14591 | /* Get the old lr if we saved it. */ |
14592 | if (info->lr_save_p) | |
b6c9286a | 14593 | { |
a3170dc6 AH |
14594 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
14595 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
14596 | |
14597 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 14598 | |
9ebbca7d | 14599 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 14600 | } |
f676971a | 14601 | |
9ebbca7d GK |
14602 | /* Get the old cr if we saved it. */ |
14603 | if (info->cr_save_p) | |
14604 | { | |
14605 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14606 | GEN_INT (info->cr_save_offset + sp_offset)); | |
14607 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
14608 | |
14609 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 14610 | |
9ebbca7d GK |
14611 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
14612 | } | |
f676971a | 14613 | |
9ebbca7d | 14614 | /* Set LR here to try to overlap restores below. */ |
4697a36c | 14615 | if (info->lr_save_p) |
9ebbca7d GK |
14616 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
14617 | gen_rtx_REG (Pmode, 0)); | |
f676971a | 14618 | |
83720594 RH |
14619 | /* Load exception handler data registers, if needed. */ |
14620 | if (current_function_calls_eh_return) | |
14621 | { | |
78e1b90d DE |
14622 | unsigned int i, regno; |
14623 | ||
fc4767bb JJ |
14624 | if (TARGET_AIX) |
14625 | { | |
14626 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14627 | GEN_INT (sp_offset + 5 * reg_size)); | |
14628 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
14629 | ||
14630 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14631 | ||
14632 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
14633 | } | |
14634 | ||
83720594 RH |
14635 | for (i = 0; ; ++i) |
14636 | { | |
a3170dc6 | 14637 | rtx mem; |
83720594 RH |
14638 | |
14639 | regno = EH_RETURN_DATA_REGNO (i); | |
14640 | if (regno == INVALID_REGNUM) | |
14641 | break; | |
14642 | ||
a3170dc6 AH |
14643 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
14644 | info->ehrd_offset + sp_offset | |
14645 | + reg_size * (int) i); | |
ba4828e0 | 14646 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
14647 | |
14648 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
14649 | } | |
14650 | } | |
f676971a | 14651 | |
9ebbca7d GK |
14652 | /* Restore GPRs. This is done as a PARALLEL if we are using |
14653 | the load-multiple instructions. */ | |
14654 | if (using_load_multiple) | |
979721f8 | 14655 | { |
9ebbca7d GK |
14656 | rtvec p; |
14657 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
14658 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 14659 | { |
f676971a EC |
14660 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14661 | GEN_INT (info->gp_save_offset | |
14662 | + sp_offset | |
9ebbca7d GK |
14663 | + reg_size * i)); |
14664 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
14665 | |
14666 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d | 14667 | |
f676971a | 14668 | RTVEC_ELT (p, i) = |
9ebbca7d GK |
14669 | gen_rtx_SET (VOIDmode, |
14670 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
14671 | mem); | |
979721f8 | 14672 | } |
9ebbca7d | 14673 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 14674 | } |
9ebbca7d GK |
14675 | else |
14676 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
f676971a | 14677 | if ((regs_ever_live[info->first_gp_reg_save+i] |
b4db40bf JJ |
14678 | && (! call_used_regs[info->first_gp_reg_save+i] |
14679 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM | |
14680 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 14681 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 14682 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 14683 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d | 14684 | { |
f676971a EC |
14685 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14686 | GEN_INT (info->gp_save_offset | |
14687 | + sp_offset | |
9ebbca7d GK |
14688 | + reg_size * i)); |
14689 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 14690 | |
a3170dc6 | 14691 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 14692 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
14693 | { |
14694 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
14695 | rtx b; | |
14696 | ||
14697 | if (!SPE_CONST_OFFSET_OK (offset)) | |
14698 | { | |
14699 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
14700 | emit_move_insn (b, GEN_INT (offset)); | |
14701 | } | |
14702 | else | |
14703 | b = GEN_INT (offset); | |
14704 | ||
14705 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
14706 | mem = gen_rtx_MEM (V2SImode, addr); | |
14707 | } | |
14708 | ||
ba4828e0 | 14709 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 14710 | |
f676971a | 14711 | emit_move_insn (gen_rtx_REG (reg_mode, |
a3170dc6 | 14712 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 14713 | } |
9878760c | 14714 | |
9ebbca7d GK |
14715 | /* Restore fpr's if we need to do it without calling a function. */ |
14716 | if (restoring_FPRs_inline) | |
14717 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 14718 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d GK |
14719 | && ! call_used_regs[info->first_fp_reg_save+i])) |
14720 | { | |
14721 | rtx addr, mem; | |
14722 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a EC |
14723 | GEN_INT (info->fp_save_offset |
14724 | + sp_offset | |
a4f6c312 | 14725 | + 8 * i)); |
9ebbca7d | 14726 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 14727 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 14728 | |
f676971a | 14729 | emit_move_insn (gen_rtx_REG (DFmode, |
9ebbca7d GK |
14730 | info->first_fp_reg_save + i), |
14731 | mem); | |
14732 | } | |
8d30c4ee | 14733 | |
9ebbca7d GK |
14734 | /* If we saved cr, restore it here. Just those that were used. */ |
14735 | if (info->cr_save_p) | |
979721f8 | 14736 | { |
9ebbca7d | 14737 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 14738 | int count = 0; |
f676971a | 14739 | |
9ebbca7d | 14740 | if (using_mfcr_multiple) |
979721f8 | 14741 | { |
9ebbca7d GK |
14742 | for (i = 0; i < 8; i++) |
14743 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 14744 | count++; |
9ebbca7d | 14745 | if (count == 0) |
e35b9579 GK |
14746 | abort (); |
14747 | } | |
14748 | ||
14749 | if (using_mfcr_multiple && count > 1) | |
14750 | { | |
14751 | rtvec p; | |
14752 | int ndx; | |
f676971a | 14753 | |
e35b9579 | 14754 | p = rtvec_alloc (count); |
9ebbca7d | 14755 | |
e35b9579 | 14756 | ndx = 0; |
9ebbca7d GK |
14757 | for (i = 0; i < 8; i++) |
14758 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
14759 | { | |
14760 | rtvec r = rtvec_alloc (2); | |
14761 | RTVEC_ELT (r, 0) = r12_rtx; | |
14762 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 14763 | RTVEC_ELT (p, ndx) = |
f676971a | 14764 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 14765 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 14766 | ndx++; |
9ebbca7d GK |
14767 | } |
14768 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
14769 | if (ndx != count) |
14770 | abort (); | |
979721f8 MM |
14771 | } |
14772 | else | |
9ebbca7d GK |
14773 | for (i = 0; i < 8; i++) |
14774 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 14775 | { |
f676971a | 14776 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
9ebbca7d GK |
14777 | CR0_REGNO+i), |
14778 | r12_rtx)); | |
979721f8 | 14779 | } |
979721f8 MM |
14780 | } |
14781 | ||
9ebbca7d GK |
14782 | /* If this is V.4, unwind the stack pointer after all of the loads |
14783 | have been done. We need to emit a block here so that sched | |
14784 | doesn't decide to move the sp change before the register restores | |
14785 | (which may not have any obvious dependency on the stack). This | |
14786 | doesn't hurt performance, because there is no scheduling that can | |
14787 | be done after this point. */ | |
fc4767bb JJ |
14788 | if (DEFAULT_ABI == ABI_V4 |
14789 | || current_function_calls_eh_return) | |
b6c9286a | 14790 | { |
9ebbca7d | 14791 | if (frame_reg_rtx != sp_reg_rtx) |
c4ad648e | 14792 | rs6000_emit_stack_tie (); |
b6c9286a | 14793 | |
9ebbca7d | 14794 | if (use_backchain_to_restore_sp) |
b6c9286a | 14795 | { |
9ebbca7d | 14796 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 14797 | } |
9ebbca7d | 14798 | else if (sp_offset != 0) |
13f1623b | 14799 | { |
5b71a4e7 | 14800 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
14801 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
14802 | GEN_INT (sp_offset)) | |
14803 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
14804 | GEN_INT (sp_offset))); | |
13f1623b | 14805 | } |
9ebbca7d | 14806 | } |
b6c9286a | 14807 | |
83720594 RH |
14808 | if (current_function_calls_eh_return) |
14809 | { | |
14810 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 14811 | emit_insn (TARGET_32BIT |
83720594 RH |
14812 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
14813 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
14814 | } | |
14815 | ||
9ebbca7d GK |
14816 | if (!sibcall) |
14817 | { | |
14818 | rtvec p; | |
14819 | if (! restoring_FPRs_inline) | |
14820 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
14821 | else | |
14822 | p = rtvec_alloc (2); | |
b6c9286a | 14823 | |
e35b9579 | 14824 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
f676971a EC |
14825 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
14826 | gen_rtx_REG (Pmode, | |
9ebbca7d | 14827 | LINK_REGISTER_REGNUM)); |
9ebbca7d GK |
14828 | |
14829 | /* If we have to restore more than two FP registers, branch to the | |
14830 | restore function. It will return to our caller. */ | |
14831 | if (! restoring_FPRs_inline) | |
14832 | { | |
14833 | int i; | |
14834 | char rname[30]; | |
520a57c8 | 14835 | const char *alloc_rname; |
979721f8 | 14836 | |
f676971a | 14837 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
9ebbca7d | 14838 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); |
a8a05998 | 14839 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
14840 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
14841 | gen_rtx_SYMBOL_REF (Pmode, | |
14842 | alloc_rname)); | |
b6c9286a | 14843 | |
9ebbca7d GK |
14844 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
14845 | { | |
14846 | rtx addr, mem; | |
14847 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
14848 | GEN_INT (info->fp_save_offset + 8*i)); | |
14849 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 14850 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 14851 | |
f676971a | 14852 | RTVEC_ELT (p, i+3) = |
9ebbca7d GK |
14853 | gen_rtx_SET (VOIDmode, |
14854 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
14855 | mem); | |
b6c9286a MM |
14856 | } |
14857 | } | |
f676971a | 14858 | |
9ebbca7d | 14859 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
3daf36a4 | 14860 | } |
9878760c RK |
14861 | } |
14862 | ||
14863 | /* Write function epilogue. */ | |
14864 | ||
08c148a8 | 14865 | static void |
f676971a | 14866 | rs6000_output_function_epilogue (FILE *file, |
a2369ed3 | 14867 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9878760c | 14868 | { |
4697a36c | 14869 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 14870 | |
9ebbca7d | 14871 | if (! HAVE_epilogue) |
9878760c | 14872 | { |
9ebbca7d GK |
14873 | rtx insn = get_last_insn (); |
14874 | /* If the last insn was a BARRIER, we don't have to write anything except | |
14875 | the trace table. */ | |
14876 | if (GET_CODE (insn) == NOTE) | |
14877 | insn = prev_nonnote_insn (insn); | |
14878 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 14879 | { |
9ebbca7d GK |
14880 | /* This is slightly ugly, but at least we don't have two |
14881 | copies of the epilogue-emitting code. */ | |
14882 | start_sequence (); | |
14883 | ||
14884 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
14885 | and end of the "toplevel" insn chain. */ | |
2e040219 | 14886 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 14887 | rs6000_emit_epilogue (FALSE); |
2e040219 | 14888 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 14889 | |
a3c9585f | 14890 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
14891 | { |
14892 | rtx insn; | |
14893 | unsigned addr = 0; | |
14894 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
14895 | { | |
14896 | INSN_ADDRESSES_NEW (insn, addr); | |
14897 | addr += 4; | |
14898 | } | |
14899 | } | |
14900 | ||
9ebbca7d | 14901 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
14902 | debug_rtx_list (get_insns (), 100); |
14903 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 14904 | end_sequence (); |
4697a36c | 14905 | } |
9878760c | 14906 | } |
b4ac57ab | 14907 | |
efdba735 SH |
14908 | #if TARGET_MACHO |
14909 | macho_branch_islands (); | |
0e5da0be GK |
14910 | /* Mach-O doesn't support labels at the end of objects, so if |
14911 | it looks like we might want one, insert a NOP. */ | |
14912 | { | |
14913 | rtx insn = get_last_insn (); | |
14914 | while (insn | |
14915 | && NOTE_P (insn) | |
14916 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) | |
14917 | insn = PREV_INSN (insn); | |
f676971a EC |
14918 | if (insn |
14919 | && (LABEL_P (insn) | |
0e5da0be GK |
14920 | || (NOTE_P (insn) |
14921 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) | |
14922 | fputs ("\tnop\n", file); | |
14923 | } | |
14924 | #endif | |
14925 | ||
9b30bae2 | 14926 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
14927 | on its format. |
14928 | ||
14929 | We don't output a traceback table if -finhibit-size-directive was | |
14930 | used. The documentation for -finhibit-size-directive reads | |
14931 | ``don't output a @code{.size} assembler directive, or anything | |
14932 | else that would cause trouble if the function is split in the | |
14933 | middle, and the two halves are placed at locations far apart in | |
14934 | memory.'' The traceback table has this property, since it | |
14935 | includes the offset from the start of the function to the | |
4d30c363 MM |
14936 | traceback table itself. |
14937 | ||
14938 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 14939 | different traceback table. */ |
57ac7be9 AM |
14940 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
14941 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 14942 | { |
69c75916 | 14943 | const char *fname = NULL; |
3ac88239 | 14944 | const char *language_string = lang_hooks.name; |
6041bf2f | 14945 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 14946 | int i; |
57ac7be9 AM |
14947 | int optional_tbtab; |
14948 | ||
14949 | if (rs6000_traceback == traceback_full) | |
14950 | optional_tbtab = 1; | |
14951 | else if (rs6000_traceback == traceback_part) | |
14952 | optional_tbtab = 0; | |
14953 | else | |
14954 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 14955 | |
69c75916 AM |
14956 | if (optional_tbtab) |
14957 | { | |
14958 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
14959 | while (*fname == '.') /* V.4 encodes . in the name */ | |
14960 | fname++; | |
14961 | ||
14962 | /* Need label immediately before tbtab, so we can compute | |
14963 | its offset from the function start. */ | |
14964 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
14965 | ASM_OUTPUT_LABEL (file, fname); | |
14966 | } | |
314fc5a9 ILT |
14967 | |
14968 | /* The .tbtab pseudo-op can only be used for the first eight | |
14969 | expressions, since it can't handle the possibly variable | |
14970 | length fields that follow. However, if you omit the optional | |
14971 | fields, the assembler outputs zeros for all optional fields | |
14972 | anyways, giving each variable length field is minimum length | |
14973 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
14974 | pseudo-op at all. */ | |
14975 | ||
14976 | /* An all-zero word flags the start of the tbtab, for debuggers | |
14977 | that have to find it by searching forward from the entry | |
14978 | point or from the current pc. */ | |
19d2d16f | 14979 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
14980 | |
14981 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 14982 | fputs ("\t.byte 0,", file); |
314fc5a9 | 14983 | |
5fc921c1 DE |
14984 | /* Language type. Unfortunately, there does not seem to be any |
14985 | official way to discover the language being compiled, so we | |
14986 | use language_string. | |
14987 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
14988 | Java is 13. Objective-C is 14. */ | |
14989 | if (! strcmp (language_string, "GNU C")) | |
314fc5a9 | 14990 | i = 0; |
6de9cd9a DN |
14991 | else if (! strcmp (language_string, "GNU F77") |
14992 | || ! strcmp (language_string, "GNU F95")) | |
314fc5a9 | 14993 | i = 1; |
8b83775b | 14994 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 14995 | i = 2; |
5fc921c1 DE |
14996 | else if (! strcmp (language_string, "GNU Ada")) |
14997 | i = 3; | |
314fc5a9 ILT |
14998 | else if (! strcmp (language_string, "GNU C++")) |
14999 | i = 9; | |
9517ead8 AG |
15000 | else if (! strcmp (language_string, "GNU Java")) |
15001 | i = 13; | |
5fc921c1 DE |
15002 | else if (! strcmp (language_string, "GNU Objective-C")) |
15003 | i = 14; | |
314fc5a9 ILT |
15004 | else |
15005 | abort (); | |
15006 | fprintf (file, "%d,", i); | |
15007 | ||
15008 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
15009 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
15010 | from start of procedure stored in tbtab, internal function, function | |
15011 | has controlled storage, function has no toc, function uses fp, | |
15012 | function logs/aborts fp operations. */ | |
15013 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
15014 | fprintf (file, "%d,", |
15015 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
15016 | |
15017 | /* 6 bitfields: function is interrupt handler, name present in | |
15018 | proc table, function calls alloca, on condition directives | |
15019 | (controls stack walks, 3 bits), saves condition reg, saves | |
15020 | link reg. */ | |
15021 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
15022 | set up as a frame pointer, even when there is no alloca call. */ | |
15023 | fprintf (file, "%d,", | |
6041bf2f DE |
15024 | ((optional_tbtab << 6) |
15025 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
15026 | | (info->cr_save_p << 1) | |
15027 | | (info->lr_save_p))); | |
314fc5a9 | 15028 | |
6041bf2f | 15029 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
15030 | (6 bits). */ |
15031 | fprintf (file, "%d,", | |
4697a36c | 15032 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
15033 | |
15034 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
15035 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
15036 | ||
6041bf2f DE |
15037 | if (optional_tbtab) |
15038 | { | |
15039 | /* Compute the parameter info from the function decl argument | |
15040 | list. */ | |
15041 | tree decl; | |
15042 | int next_parm_info_bit = 31; | |
314fc5a9 | 15043 | |
6041bf2f DE |
15044 | for (decl = DECL_ARGUMENTS (current_function_decl); |
15045 | decl; decl = TREE_CHAIN (decl)) | |
15046 | { | |
15047 | rtx parameter = DECL_INCOMING_RTL (decl); | |
15048 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 15049 | |
6041bf2f DE |
15050 | if (GET_CODE (parameter) == REG) |
15051 | { | |
15052 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
15053 | { | |
15054 | int bits; | |
15055 | ||
15056 | float_parms++; | |
15057 | ||
15058 | if (mode == SFmode) | |
15059 | bits = 0x2; | |
fcce224d | 15060 | else if (mode == DFmode || mode == TFmode) |
6041bf2f DE |
15061 | bits = 0x3; |
15062 | else | |
15063 | abort (); | |
15064 | ||
15065 | /* If only one bit will fit, don't or in this entry. */ | |
15066 | if (next_parm_info_bit > 0) | |
15067 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
15068 | next_parm_info_bit -= 2; | |
15069 | } | |
15070 | else | |
15071 | { | |
15072 | fixed_parms += ((GET_MODE_SIZE (mode) | |
15073 | + (UNITS_PER_WORD - 1)) | |
15074 | / UNITS_PER_WORD); | |
15075 | next_parm_info_bit -= 1; | |
15076 | } | |
15077 | } | |
15078 | } | |
15079 | } | |
314fc5a9 ILT |
15080 | |
15081 | /* Number of fixed point parameters. */ | |
15082 | /* This is actually the number of words of fixed point parameters; thus | |
15083 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
15084 | fprintf (file, "%d,", fixed_parms); | |
15085 | ||
15086 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
15087 | all on stack. */ | |
15088 | /* This is actually the number of fp registers that hold parameters; | |
15089 | and thus the maximum value is 13. */ | |
15090 | /* Set parameters on stack bit if parameters are not in their original | |
15091 | registers, regardless of whether they are on the stack? Xlc | |
15092 | seems to set the bit when not optimizing. */ | |
15093 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
15094 | ||
6041bf2f DE |
15095 | if (! optional_tbtab) |
15096 | return; | |
15097 | ||
314fc5a9 ILT |
15098 | /* Optional fields follow. Some are variable length. */ |
15099 | ||
15100 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
15101 | 11 double float. */ | |
15102 | /* There is an entry for each parameter in a register, in the order that | |
15103 | they occur in the parameter list. Any intervening arguments on the | |
15104 | stack are ignored. If the list overflows a long (max possible length | |
15105 | 34 bits) then completely leave off all elements that don't fit. */ | |
15106 | /* Only emit this long if there was at least one parameter. */ | |
15107 | if (fixed_parms || float_parms) | |
15108 | fprintf (file, "\t.long %d\n", parm_info); | |
15109 | ||
15110 | /* Offset from start of code to tb table. */ | |
19d2d16f | 15111 | fputs ("\t.long ", file); |
314fc5a9 | 15112 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
85b776df AM |
15113 | if (TARGET_AIX) |
15114 | RS6000_OUTPUT_BASENAME (file, fname); | |
15115 | else | |
15116 | assemble_name (file, fname); | |
15117 | putc ('-', file); | |
15118 | rs6000_output_function_entry (file, fname); | |
19d2d16f | 15119 | putc ('\n', file); |
314fc5a9 ILT |
15120 | |
15121 | /* Interrupt handler mask. */ | |
15122 | /* Omit this long, since we never set the interrupt handler bit | |
15123 | above. */ | |
15124 | ||
15125 | /* Number of CTL (controlled storage) anchors. */ | |
15126 | /* Omit this long, since the has_ctl bit is never set above. */ | |
15127 | ||
15128 | /* Displacement into stack of each CTL anchor. */ | |
15129 | /* Omit this list of longs, because there are no CTL anchors. */ | |
15130 | ||
15131 | /* Length of function name. */ | |
69c75916 AM |
15132 | if (*fname == '*') |
15133 | ++fname; | |
296b8152 | 15134 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
15135 | |
15136 | /* Function name. */ | |
15137 | assemble_string (fname, strlen (fname)); | |
15138 | ||
15139 | /* Register for alloca automatic storage; this is always reg 31. | |
15140 | Only emit this if the alloca bit was set above. */ | |
15141 | if (frame_pointer_needed) | |
19d2d16f | 15142 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
15143 | |
15144 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 15145 | } |
9878760c | 15146 | } |
17167fd8 | 15147 | \f |
a4f6c312 SS |
15148 | /* A C compound statement that outputs the assembler code for a thunk |
15149 | function, used to implement C++ virtual function calls with | |
15150 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
15151 | function, adjusting the implicit object parameter before handing | |
15152 | control off to the real function. | |
15153 | ||
15154 | First, emit code to add the integer DELTA to the location that | |
15155 | contains the incoming first argument. Assume that this argument | |
15156 | contains a pointer, and is the one used to pass the `this' pointer | |
15157 | in C++. This is the incoming argument *before* the function | |
15158 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
15159 | values of all other incoming arguments. | |
17167fd8 MM |
15160 | |
15161 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
15162 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
15163 | not touch the return address. Hence returning from FUNCTION will | |
15164 | return to whoever called the current `thunk'. | |
17167fd8 | 15165 | |
a4f6c312 SS |
15166 | The effect must be as if FUNCTION had been called directly with the |
15167 | adjusted first argument. This macro is responsible for emitting | |
15168 | all of the code for a thunk function; output_function_prologue() | |
15169 | and output_function_epilogue() are not invoked. | |
17167fd8 | 15170 | |
a4f6c312 SS |
15171 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
15172 | been extracted from it.) It might possibly be useful on some | |
15173 | targets, but probably not. | |
17167fd8 | 15174 | |
a4f6c312 SS |
15175 | If you do not define this macro, the target-independent code in the |
15176 | C++ frontend will generate a less efficient heavyweight thunk that | |
15177 | calls FUNCTION instead of jumping to it. The generic approach does | |
15178 | not support varargs. */ | |
17167fd8 | 15179 | |
3961e8fe | 15180 | static void |
f676971a EC |
15181 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
15182 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
a2369ed3 | 15183 | tree function) |
17167fd8 | 15184 | { |
5b71a4e7 | 15185 | rtx this, insn, funexp; |
17167fd8 | 15186 | |
5b71a4e7 | 15187 | reload_completed = 1; |
fe3ad572 | 15188 | epilogue_completed = 1; |
5b71a4e7 | 15189 | no_new_pseudos = 1; |
6429e3be | 15190 | reset_block_changes (); |
56a7189a | 15191 | |
5b71a4e7 | 15192 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 15193 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 15194 | |
5b71a4e7 DE |
15195 | /* Find the "this" pointer. If the function returns a structure, |
15196 | the structure return pointer is in r3. */ | |
61f71b34 | 15197 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
5b71a4e7 | 15198 | this = gen_rtx_REG (Pmode, 4); |
56a7189a | 15199 | else |
5b71a4e7 | 15200 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 15201 | |
5b71a4e7 DE |
15202 | /* Apply the constant offset, if required. */ |
15203 | if (delta) | |
15204 | { | |
15205 | rtx delta_rtx = GEN_INT (delta); | |
15206 | emit_insn (TARGET_32BIT | |
15207 | ? gen_addsi3 (this, this, delta_rtx) | |
15208 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
15209 | } |
15210 | ||
5b71a4e7 DE |
15211 | /* Apply the offset from the vtable, if required. */ |
15212 | if (vcall_offset) | |
17167fd8 | 15213 | { |
5b71a4e7 DE |
15214 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
15215 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 15216 | |
5b71a4e7 | 15217 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
eeff9307 JJ |
15218 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
15219 | { | |
15220 | emit_insn (TARGET_32BIT | |
15221 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
15222 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
15223 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
15224 | } | |
15225 | else | |
15226 | { | |
15227 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
15228 | ||
15229 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
15230 | } | |
5b71a4e7 DE |
15231 | emit_insn (TARGET_32BIT |
15232 | ? gen_addsi3 (this, this, tmp) | |
15233 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
15234 | } |
15235 | ||
5b71a4e7 DE |
15236 | /* Generate a tail call to the target function. */ |
15237 | if (!TREE_USED (function)) | |
15238 | { | |
15239 | assemble_external (function); | |
15240 | TREE_USED (function) = 1; | |
15241 | } | |
15242 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 15243 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
15244 | |
15245 | #if TARGET_MACHO | |
ab82a49f | 15246 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 15247 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 15248 | #endif |
5b71a4e7 DE |
15249 | |
15250 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
15251 | generate sibcall RTL explicitly to avoid constraint abort. */ | |
15252 | insn = emit_call_insn ( | |
15253 | gen_rtx_PARALLEL (VOIDmode, | |
15254 | gen_rtvec (4, | |
15255 | gen_rtx_CALL (VOIDmode, | |
15256 | funexp, const0_rtx), | |
15257 | gen_rtx_USE (VOIDmode, const0_rtx), | |
15258 | gen_rtx_USE (VOIDmode, | |
15259 | gen_rtx_REG (SImode, | |
15260 | LINK_REGISTER_REGNUM)), | |
15261 | gen_rtx_RETURN (VOIDmode)))); | |
15262 | SIBLING_CALL_P (insn) = 1; | |
15263 | emit_barrier (); | |
15264 | ||
15265 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
15266 | There's not really enough bulk here to make other passes such as | |
15267 | instruction scheduling worth while. Note that use_thunk calls | |
15268 | assemble_start_function and assemble_end_function. */ | |
15269 | insn = get_insns (); | |
a2855205 | 15270 | insn_locators_initialize (); |
5b71a4e7 DE |
15271 | shorten_branches (insn); |
15272 | final_start_function (insn, file, 1); | |
15273 | final (insn, file, 1, 0); | |
15274 | final_end_function (); | |
15275 | ||
15276 | reload_completed = 0; | |
fe3ad572 | 15277 | epilogue_completed = 0; |
5b71a4e7 | 15278 | no_new_pseudos = 0; |
9ebbca7d | 15279 | } |
9ebbca7d GK |
15280 | \f |
15281 | /* A quick summary of the various types of 'constant-pool tables' | |
15282 | under PowerPC: | |
15283 | ||
f676971a | 15284 | Target Flags Name One table per |
9ebbca7d GK |
15285 | AIX (none) AIX TOC object file |
15286 | AIX -mfull-toc AIX TOC object file | |
15287 | AIX -mminimal-toc AIX minimal TOC translation unit | |
15288 | SVR4/EABI (none) SVR4 SDATA object file | |
15289 | SVR4/EABI -fpic SVR4 pic object file | |
15290 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
15291 | SVR4/EABI -mrelocatable EABI TOC function | |
15292 | SVR4/EABI -maix AIX TOC object file | |
f676971a | 15293 | SVR4/EABI -maix -mminimal-toc |
9ebbca7d GK |
15294 | AIX minimal TOC translation unit |
15295 | ||
15296 | Name Reg. Set by entries contains: | |
15297 | made by addrs? fp? sum? | |
15298 | ||
15299 | AIX TOC 2 crt0 as Y option option | |
15300 | AIX minimal TOC 30 prolog gcc Y Y option | |
15301 | SVR4 SDATA 13 crt0 gcc N Y N | |
15302 | SVR4 pic 30 prolog ld Y not yet N | |
15303 | SVR4 PIC 30 prolog gcc Y option option | |
15304 | EABI TOC 30 prolog gcc Y option option | |
15305 | ||
15306 | */ | |
15307 | ||
9ebbca7d GK |
15308 | /* Hash functions for the hash table. */ |
15309 | ||
15310 | static unsigned | |
a2369ed3 | 15311 | rs6000_hash_constant (rtx k) |
9ebbca7d | 15312 | { |
46b33600 RH |
15313 | enum rtx_code code = GET_CODE (k); |
15314 | enum machine_mode mode = GET_MODE (k); | |
15315 | unsigned result = (code << 3) ^ mode; | |
15316 | const char *format; | |
15317 | int flen, fidx; | |
f676971a | 15318 | |
46b33600 RH |
15319 | format = GET_RTX_FORMAT (code); |
15320 | flen = strlen (format); | |
15321 | fidx = 0; | |
9ebbca7d | 15322 | |
46b33600 RH |
15323 | switch (code) |
15324 | { | |
15325 | case LABEL_REF: | |
15326 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
15327 | ||
15328 | case CONST_DOUBLE: | |
15329 | if (mode != VOIDmode) | |
15330 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
15331 | flen = 2; | |
15332 | break; | |
15333 | ||
15334 | case CODE_LABEL: | |
15335 | fidx = 3; | |
15336 | break; | |
15337 | ||
15338 | default: | |
15339 | break; | |
15340 | } | |
9ebbca7d GK |
15341 | |
15342 | for (; fidx < flen; fidx++) | |
15343 | switch (format[fidx]) | |
15344 | { | |
15345 | case 's': | |
15346 | { | |
15347 | unsigned i, len; | |
15348 | const char *str = XSTR (k, fidx); | |
15349 | len = strlen (str); | |
15350 | result = result * 613 + len; | |
15351 | for (i = 0; i < len; i++) | |
15352 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
15353 | break; |
15354 | } | |
9ebbca7d GK |
15355 | case 'u': |
15356 | case 'e': | |
15357 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
15358 | break; | |
15359 | case 'i': | |
15360 | case 'n': | |
15361 | result = result * 613 + (unsigned) XINT (k, fidx); | |
15362 | break; | |
15363 | case 'w': | |
15364 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
15365 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
15366 | else | |
15367 | { | |
15368 | size_t i; | |
15369 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
15370 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
15371 | >> CHAR_BIT * i); | |
15372 | } | |
15373 | break; | |
09501938 DE |
15374 | case '0': |
15375 | break; | |
9ebbca7d | 15376 | default: |
a4f6c312 | 15377 | abort (); |
9ebbca7d | 15378 | } |
46b33600 | 15379 | |
9ebbca7d GK |
15380 | return result; |
15381 | } | |
15382 | ||
15383 | static unsigned | |
a2369ed3 | 15384 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 15385 | { |
f676971a | 15386 | const struct toc_hash_struct *thc = |
a9098fd0 GK |
15387 | (const struct toc_hash_struct *) hash_entry; |
15388 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
15389 | } |
15390 | ||
15391 | /* Compare H1 and H2 for equivalence. */ | |
15392 | ||
15393 | static int | |
a2369ed3 | 15394 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
15395 | { |
15396 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
15397 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
15398 | ||
a9098fd0 GK |
15399 | if (((const struct toc_hash_struct *) h1)->key_mode |
15400 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
15401 | return 0; | |
15402 | ||
5692c7bc | 15403 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
15404 | } |
15405 | ||
28e510bd MM |
15406 | /* These are the names given by the C++ front-end to vtables, and |
15407 | vtable-like objects. Ideally, this logic should not be here; | |
15408 | instead, there should be some programmatic way of inquiring as | |
15409 | to whether or not an object is a vtable. */ | |
15410 | ||
15411 | #define VTABLE_NAME_P(NAME) \ | |
15412 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
15413 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
15414 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
26be75db | 15415 | || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ |
f676971a | 15416 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) |
28e510bd MM |
15417 | |
15418 | void | |
a2369ed3 | 15419 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
15420 | { |
15421 | /* Currently C++ toc references to vtables can be emitted before it | |
15422 | is decided whether the vtable is public or private. If this is | |
15423 | the case, then the linker will eventually complain that there is | |
f676971a | 15424 | a reference to an unknown section. Thus, for vtables only, |
28e510bd MM |
15425 | we emit the TOC reference to reference the symbol and not the |
15426 | section. */ | |
15427 | const char *name = XSTR (x, 0); | |
54ee9799 | 15428 | |
f676971a | 15429 | if (VTABLE_NAME_P (name)) |
54ee9799 DE |
15430 | { |
15431 | RS6000_OUTPUT_BASENAME (file, name); | |
15432 | } | |
15433 | else | |
15434 | assemble_name (file, name); | |
28e510bd MM |
15435 | } |
15436 | ||
a4f6c312 SS |
15437 | /* Output a TOC entry. We derive the entry name from what is being |
15438 | written. */ | |
9878760c RK |
15439 | |
15440 | void | |
a2369ed3 | 15441 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
15442 | { |
15443 | char buf[256]; | |
3cce094d | 15444 | const char *name = buf; |
ec940faa | 15445 | const char *real_name; |
9878760c RK |
15446 | rtx base = x; |
15447 | int offset = 0; | |
15448 | ||
4697a36c MM |
15449 | if (TARGET_NO_TOC) |
15450 | abort (); | |
15451 | ||
9ebbca7d GK |
15452 | /* When the linker won't eliminate them, don't output duplicate |
15453 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
15454 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
15455 | CODE_LABELs. */ | |
15456 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
15457 | { |
15458 | struct toc_hash_struct *h; | |
15459 | void * * found; | |
f676971a | 15460 | |
17211ab5 | 15461 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
c4ad648e | 15462 | time because GGC is not initialized at that point. */ |
17211ab5 | 15463 | if (toc_hash_table == NULL) |
f676971a | 15464 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, |
17211ab5 GK |
15465 | toc_hash_eq, NULL); |
15466 | ||
9ebbca7d GK |
15467 | h = ggc_alloc (sizeof (*h)); |
15468 | h->key = x; | |
a9098fd0 | 15469 | h->key_mode = mode; |
9ebbca7d | 15470 | h->labelno = labelno; |
f676971a | 15471 | |
9ebbca7d GK |
15472 | found = htab_find_slot (toc_hash_table, h, 1); |
15473 | if (*found == NULL) | |
15474 | *found = h; | |
f676971a | 15475 | else /* This is indeed a duplicate. |
9ebbca7d GK |
15476 | Set this label equal to that label. */ |
15477 | { | |
15478 | fputs ("\t.set ", file); | |
15479 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
15480 | fprintf (file, "%d,", labelno); | |
15481 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
f676971a | 15482 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) |
9ebbca7d GK |
15483 | found)->labelno)); |
15484 | return; | |
15485 | } | |
15486 | } | |
15487 | ||
15488 | /* If we're going to put a double constant in the TOC, make sure it's | |
15489 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
15490 | if (GET_CODE (x) == CONST_DOUBLE |
15491 | && STRICT_ALIGNMENT | |
a9098fd0 | 15492 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
15493 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
15494 | ASM_OUTPUT_ALIGN (file, 3); | |
15495 | } | |
15496 | ||
4977bab6 | 15497 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 15498 | |
37c37a57 RK |
15499 | /* Handle FP constants specially. Note that if we have a minimal |
15500 | TOC, things we put here aren't actually in the TOC, so we can allow | |
15501 | FP constants. */ | |
fcce224d DE |
15502 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
15503 | { | |
15504 | REAL_VALUE_TYPE rv; | |
15505 | long k[4]; | |
15506 | ||
15507 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
15508 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
15509 | ||
15510 | if (TARGET_64BIT) | |
15511 | { | |
15512 | if (TARGET_MINIMAL_TOC) | |
15513 | fputs (DOUBLE_INT_ASM_OP, file); | |
15514 | else | |
15515 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
15516 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15517 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15518 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
15519 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15520 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15521 | return; | |
15522 | } | |
15523 | else | |
15524 | { | |
15525 | if (TARGET_MINIMAL_TOC) | |
15526 | fputs ("\t.long ", file); | |
15527 | else | |
15528 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
15529 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15530 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15531 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
15532 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15533 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15534 | return; | |
15535 | } | |
15536 | } | |
15537 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 15538 | { |
042259f2 DE |
15539 | REAL_VALUE_TYPE rv; |
15540 | long k[2]; | |
0adc764e | 15541 | |
042259f2 DE |
15542 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
15543 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 15544 | |
13ded975 DE |
15545 | if (TARGET_64BIT) |
15546 | { | |
15547 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15548 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 15549 | else |
2f0552b6 AM |
15550 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
15551 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
15552 | fprintf (file, "0x%lx%08lx\n", | |
15553 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
15554 | return; |
15555 | } | |
1875cc88 | 15556 | else |
13ded975 DE |
15557 | { |
15558 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15559 | fputs ("\t.long ", file); |
13ded975 | 15560 | else |
2f0552b6 AM |
15561 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
15562 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
15563 | fprintf (file, "0x%lx,0x%lx\n", | |
15564 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
15565 | return; |
15566 | } | |
9878760c | 15567 | } |
a9098fd0 | 15568 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 15569 | { |
042259f2 DE |
15570 | REAL_VALUE_TYPE rv; |
15571 | long l; | |
9878760c | 15572 | |
042259f2 DE |
15573 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
15574 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
15575 | ||
31bfaa0b DE |
15576 | if (TARGET_64BIT) |
15577 | { | |
15578 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15579 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 15580 | else |
2f0552b6 AM |
15581 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
15582 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
15583 | return; |
15584 | } | |
042259f2 | 15585 | else |
31bfaa0b DE |
15586 | { |
15587 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15588 | fputs ("\t.long ", file); |
31bfaa0b | 15589 | else |
2f0552b6 AM |
15590 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
15591 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
15592 | return; |
15593 | } | |
042259f2 | 15594 | } |
f176e826 | 15595 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 15596 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 15597 | { |
e2c953b6 | 15598 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
15599 | HOST_WIDE_INT high; |
15600 | ||
15601 | if (GET_CODE (x) == CONST_DOUBLE) | |
15602 | { | |
15603 | low = CONST_DOUBLE_LOW (x); | |
15604 | high = CONST_DOUBLE_HIGH (x); | |
15605 | } | |
15606 | else | |
15607 | #if HOST_BITS_PER_WIDE_INT == 32 | |
15608 | { | |
15609 | low = INTVAL (x); | |
0858c623 | 15610 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
15611 | } |
15612 | #else | |
15613 | { | |
c4ad648e AM |
15614 | low = INTVAL (x) & 0xffffffff; |
15615 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; | |
042259f2 DE |
15616 | } |
15617 | #endif | |
9878760c | 15618 | |
a9098fd0 GK |
15619 | /* TOC entries are always Pmode-sized, but since this |
15620 | is a bigendian machine then if we're putting smaller | |
15621 | integer constants in the TOC we have to pad them. | |
15622 | (This is still a win over putting the constants in | |
15623 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
15624 | to have both a TOC entry _and_ the actual constant.) |
15625 | ||
15626 | For a 32-bit target, CONST_INT values are loaded and shifted | |
15627 | entirely within `low' and can be stored in one TOC entry. */ | |
15628 | ||
15629 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 15630 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
15631 | |
15632 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
15633 | { |
15634 | #if HOST_BITS_PER_WIDE_INT == 32 | |
15635 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
15636 | POINTER_SIZE, &low, &high, 0); | |
15637 | #else | |
15638 | low |= high << 32; | |
15639 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
15640 | high = (HOST_WIDE_INT) low >> 32; | |
15641 | low &= 0xffffffff; | |
15642 | #endif | |
15643 | } | |
a9098fd0 | 15644 | |
13ded975 DE |
15645 | if (TARGET_64BIT) |
15646 | { | |
15647 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15648 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 15649 | else |
2f0552b6 AM |
15650 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
15651 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
15652 | fprintf (file, "0x%lx%08lx\n", | |
15653 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
15654 | return; |
15655 | } | |
1875cc88 | 15656 | else |
13ded975 | 15657 | { |
02a4ec28 FS |
15658 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
15659 | { | |
15660 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15661 | fputs ("\t.long ", file); |
02a4ec28 | 15662 | else |
2bfcf297 | 15663 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
15664 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
15665 | fprintf (file, "0x%lx,0x%lx\n", | |
15666 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 15667 | } |
13ded975 | 15668 | else |
02a4ec28 FS |
15669 | { |
15670 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15671 | fputs ("\t.long ", file); |
02a4ec28 | 15672 | else |
2f0552b6 AM |
15673 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
15674 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 15675 | } |
13ded975 DE |
15676 | return; |
15677 | } | |
9878760c RK |
15678 | } |
15679 | ||
15680 | if (GET_CODE (x) == CONST) | |
15681 | { | |
2bfcf297 DB |
15682 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
15683 | abort (); | |
15684 | ||
9878760c RK |
15685 | base = XEXP (XEXP (x, 0), 0); |
15686 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
15687 | } | |
f676971a | 15688 | |
9878760c RK |
15689 | if (GET_CODE (base) == SYMBOL_REF) |
15690 | name = XSTR (base, 0); | |
15691 | else if (GET_CODE (base) == LABEL_REF) | |
15692 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
15693 | else if (GET_CODE (base) == CODE_LABEL) | |
15694 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
15695 | else | |
15696 | abort (); | |
15697 | ||
772c5265 | 15698 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 15699 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 15700 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
15701 | else |
15702 | { | |
b6c9286a | 15703 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 15704 | |
1875cc88 JW |
15705 | if (offset < 0) |
15706 | fprintf (file, ".N%d", - offset); | |
15707 | else if (offset) | |
15708 | fprintf (file, ".P%d", offset); | |
9878760c | 15709 | |
19d2d16f | 15710 | fputs ("[TC],", file); |
1875cc88 | 15711 | } |
581bc4de MM |
15712 | |
15713 | /* Currently C++ toc references to vtables can be emitted before it | |
15714 | is decided whether the vtable is public or private. If this is | |
15715 | the case, then the linker will eventually complain that there is | |
15716 | a TOC reference to an unknown section. Thus, for vtables only, | |
15717 | we emit the TOC reference to reference the symbol and not the | |
15718 | section. */ | |
28e510bd | 15719 | if (VTABLE_NAME_P (name)) |
581bc4de | 15720 | { |
54ee9799 | 15721 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
15722 | if (offset < 0) |
15723 | fprintf (file, "%d", offset); | |
15724 | else if (offset > 0) | |
15725 | fprintf (file, "+%d", offset); | |
15726 | } | |
15727 | else | |
15728 | output_addr_const (file, x); | |
19d2d16f | 15729 | putc ('\n', file); |
9878760c RK |
15730 | } |
15731 | \f | |
15732 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
15733 | starting at P to FILE. | |
15734 | ||
15735 | On the RS/6000, we have to do this using the .byte operation and | |
15736 | write out special characters outside the quoted string. | |
15737 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 15738 | so we must artificially break them up early. */ |
9878760c RK |
15739 | |
15740 | void | |
a2369ed3 | 15741 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
15742 | { |
15743 | char c; | |
15744 | int i, count_string; | |
d330fd93 KG |
15745 | const char *for_string = "\t.byte \""; |
15746 | const char *for_decimal = "\t.byte "; | |
15747 | const char *to_close = NULL; | |
9878760c RK |
15748 | |
15749 | count_string = 0; | |
15750 | for (i = 0; i < n; i++) | |
15751 | { | |
15752 | c = *p++; | |
15753 | if (c >= ' ' && c < 0177) | |
15754 | { | |
15755 | if (for_string) | |
15756 | fputs (for_string, file); | |
15757 | putc (c, file); | |
15758 | ||
15759 | /* Write two quotes to get one. */ | |
15760 | if (c == '"') | |
15761 | { | |
15762 | putc (c, file); | |
15763 | ++count_string; | |
15764 | } | |
15765 | ||
15766 | for_string = NULL; | |
15767 | for_decimal = "\"\n\t.byte "; | |
15768 | to_close = "\"\n"; | |
15769 | ++count_string; | |
15770 | ||
15771 | if (count_string >= 512) | |
15772 | { | |
15773 | fputs (to_close, file); | |
15774 | ||
15775 | for_string = "\t.byte \""; | |
15776 | for_decimal = "\t.byte "; | |
15777 | to_close = NULL; | |
15778 | count_string = 0; | |
15779 | } | |
15780 | } | |
15781 | else | |
15782 | { | |
15783 | if (for_decimal) | |
15784 | fputs (for_decimal, file); | |
15785 | fprintf (file, "%d", c); | |
15786 | ||
15787 | for_string = "\n\t.byte \""; | |
15788 | for_decimal = ", "; | |
15789 | to_close = "\n"; | |
15790 | count_string = 0; | |
15791 | } | |
15792 | } | |
15793 | ||
15794 | /* Now close the string if we have written one. Then end the line. */ | |
15795 | if (to_close) | |
9ebbca7d | 15796 | fputs (to_close, file); |
9878760c RK |
15797 | } |
15798 | \f | |
15799 | /* Generate a unique section name for FILENAME for a section type | |
15800 | represented by SECTION_DESC. Output goes into BUF. | |
15801 | ||
15802 | SECTION_DESC can be any string, as long as it is different for each | |
15803 | possible section type. | |
15804 | ||
15805 | We name the section in the same manner as xlc. The name begins with an | |
15806 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
15807 | names) with the last period replaced by the string SECTION_DESC. If |
15808 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
15809 | the name. */ | |
9878760c RK |
15810 | |
15811 | void | |
f676971a | 15812 | rs6000_gen_section_name (char **buf, const char *filename, |
c4ad648e | 15813 | const char *section_desc) |
9878760c | 15814 | { |
9ebbca7d | 15815 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
15816 | char *p; |
15817 | int len; | |
9878760c RK |
15818 | |
15819 | after_last_slash = filename; | |
15820 | for (q = filename; *q; q++) | |
11e5fe42 RK |
15821 | { |
15822 | if (*q == '/') | |
15823 | after_last_slash = q + 1; | |
15824 | else if (*q == '.') | |
15825 | last_period = q; | |
15826 | } | |
9878760c | 15827 | |
11e5fe42 | 15828 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 15829 | *buf = (char *) xmalloc (len); |
9878760c RK |
15830 | |
15831 | p = *buf; | |
15832 | *p++ = '_'; | |
15833 | ||
15834 | for (q = after_last_slash; *q; q++) | |
15835 | { | |
11e5fe42 | 15836 | if (q == last_period) |
c4ad648e | 15837 | { |
9878760c RK |
15838 | strcpy (p, section_desc); |
15839 | p += strlen (section_desc); | |
e3981aab | 15840 | break; |
c4ad648e | 15841 | } |
9878760c | 15842 | |
e9a780ec | 15843 | else if (ISALNUM (*q)) |
c4ad648e | 15844 | *p++ = *q; |
9878760c RK |
15845 | } |
15846 | ||
11e5fe42 | 15847 | if (last_period == 0) |
9878760c RK |
15848 | strcpy (p, section_desc); |
15849 | else | |
15850 | *p = '\0'; | |
15851 | } | |
e165f3f0 | 15852 | \f |
a4f6c312 | 15853 | /* Emit profile function. */ |
411707f4 | 15854 | |
411707f4 | 15855 | void |
a2369ed3 | 15856 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 15857 | { |
ffcfcb5f AM |
15858 | if (TARGET_PROFILE_KERNEL) |
15859 | return; | |
15860 | ||
8480e480 CC |
15861 | if (DEFAULT_ABI == ABI_AIX) |
15862 | { | |
9739c90c JJ |
15863 | #ifndef NO_PROFILE_COUNTERS |
15864 | # define NO_PROFILE_COUNTERS 0 | |
15865 | #endif | |
f676971a | 15866 | if (NO_PROFILE_COUNTERS) |
9739c90c JJ |
15867 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); |
15868 | else | |
15869 | { | |
15870 | char buf[30]; | |
15871 | const char *label_name; | |
15872 | rtx fun; | |
411707f4 | 15873 | |
9739c90c JJ |
15874 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
15875 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
15876 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 15877 | |
9739c90c JJ |
15878 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
15879 | fun, Pmode); | |
15880 | } | |
8480e480 | 15881 | } |
ee890fe2 SS |
15882 | else if (DEFAULT_ABI == ABI_DARWIN) |
15883 | { | |
d5fa86ba | 15884 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
15885 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
15886 | ||
15887 | /* Be conservative and always set this, at least for now. */ | |
15888 | current_function_uses_pic_offset_table = 1; | |
15889 | ||
15890 | #if TARGET_MACHO | |
15891 | /* For PIC code, set up a stub and collect the caller's address | |
15892 | from r0, which is where the prologue puts it. */ | |
11abc112 MM |
15893 | if (MACHOPIC_INDIRECT |
15894 | && current_function_uses_pic_offset_table) | |
15895 | caller_addr_regno = 0; | |
ee890fe2 SS |
15896 | #endif |
15897 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
15898 | 0, VOIDmode, 1, | |
15899 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
15900 | } | |
411707f4 CC |
15901 | } |
15902 | ||
a4f6c312 | 15903 | /* Write function profiler code. */ |
e165f3f0 RK |
15904 | |
15905 | void | |
a2369ed3 | 15906 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 15907 | { |
3daf36a4 | 15908 | char buf[100]; |
09eeeacb | 15909 | int save_lr = 8; |
e165f3f0 | 15910 | |
38c1f2d7 | 15911 | switch (DEFAULT_ABI) |
3daf36a4 | 15912 | { |
38c1f2d7 MM |
15913 | default: |
15914 | abort (); | |
15915 | ||
15916 | case ABI_V4: | |
09eeeacb | 15917 | save_lr = 4; |
09eeeacb AM |
15918 | if (!TARGET_32BIT) |
15919 | { | |
15920 | warning ("no profiling of 64-bit code for this ABI"); | |
15921 | return; | |
15922 | } | |
ffcfcb5f | 15923 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 MM |
15924 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
15925 | if (flag_pic == 1) | |
15926 | { | |
dfdfa60f | 15927 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
09eeeacb AM |
15928 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
15929 | reg_names[0], save_lr, reg_names[1]); | |
17167fd8 | 15930 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 15931 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 15932 | assemble_name (file, buf); |
17167fd8 | 15933 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 15934 | } |
9ebbca7d | 15935 | else if (flag_pic > 1) |
38c1f2d7 | 15936 | { |
09eeeacb AM |
15937 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
15938 | reg_names[0], save_lr, reg_names[1]); | |
9ebbca7d GK |
15939 | /* Now, we need to get the address of the label. */ |
15940 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 15941 | assemble_name (file, buf); |
9ebbca7d GK |
15942 | fputs ("-.\n1:", file); |
15943 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
f676971a | 15944 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", |
9ebbca7d GK |
15945 | reg_names[0], reg_names[11]); |
15946 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
15947 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 15948 | } |
38c1f2d7 MM |
15949 | else |
15950 | { | |
17167fd8 | 15951 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 15952 | assemble_name (file, buf); |
dfdfa60f | 15953 | fputs ("@ha\n", file); |
09eeeacb AM |
15954 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
15955 | reg_names[0], save_lr, reg_names[1]); | |
a260abc9 | 15956 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 15957 | assemble_name (file, buf); |
17167fd8 | 15958 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
15959 | } |
15960 | ||
50d440bc | 15961 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
3b6ce0af DE |
15962 | fprintf (file, "\tbl %s%s\n", |
15963 | RS6000_MCOUNT, flag_pic ? "@plt" : ""); | |
38c1f2d7 MM |
15964 | break; |
15965 | ||
15966 | case ABI_AIX: | |
ee890fe2 | 15967 | case ABI_DARWIN: |
ffcfcb5f AM |
15968 | if (!TARGET_PROFILE_KERNEL) |
15969 | { | |
a3c9585f | 15970 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
15971 | } |
15972 | else | |
15973 | { | |
15974 | if (TARGET_32BIT) | |
15975 | abort (); | |
15976 | ||
15977 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
15978 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
15979 | ||
6de9cd9a | 15980 | if (cfun->static_chain_decl != NULL) |
ffcfcb5f AM |
15981 | { |
15982 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
15983 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
15984 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
15985 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
15986 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
15987 | } | |
15988 | else | |
15989 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
15990 | } | |
38c1f2d7 MM |
15991 | break; |
15992 | } | |
e165f3f0 | 15993 | } |
a251ffd0 | 15994 | |
b54cf83a | 15995 | \f |
b54cf83a DE |
15996 | /* Power4 load update and store update instructions are cracked into a |
15997 | load or store and an integer insn which are executed in the same cycle. | |
15998 | Branches have their own dispatch slot which does not count against the | |
15999 | GCC issue rate, but it changes the program flow so there are no other | |
16000 | instructions to issue in this cycle. */ | |
16001 | ||
16002 | static int | |
f676971a EC |
16003 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
16004 | int verbose ATTRIBUTE_UNUSED, | |
a2369ed3 | 16005 | rtx insn, int more) |
b54cf83a DE |
16006 | { |
16007 | if (GET_CODE (PATTERN (insn)) == USE | |
16008 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16009 | return more; | |
16010 | ||
ec507f2d | 16011 | if (rs6000_sched_groups) |
b54cf83a | 16012 | { |
cbe26ab8 | 16013 | if (is_microcoded_insn (insn)) |
c4ad648e | 16014 | return 0; |
cbe26ab8 | 16015 | else if (is_cracked_insn (insn)) |
c4ad648e | 16016 | return more > 2 ? more - 2 : 0; |
b54cf83a | 16017 | } |
165b263e DE |
16018 | |
16019 | return more - 1; | |
b54cf83a DE |
16020 | } |
16021 | ||
a251ffd0 TG |
16022 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
16023 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
16024 | ||
c237e94a | 16025 | static int |
0a4f0294 | 16026 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
a251ffd0 TG |
16027 | { |
16028 | if (! recog_memoized (insn)) | |
16029 | return 0; | |
16030 | ||
16031 | if (REG_NOTE_KIND (link) != 0) | |
16032 | return 0; | |
16033 | ||
16034 | if (REG_NOTE_KIND (link) == 0) | |
16035 | { | |
ed947a96 DJ |
16036 | /* Data dependency; DEP_INSN writes a register that INSN reads |
16037 | some cycles later. */ | |
c9dbf840 DE |
16038 | |
16039 | /* Separate a load from a narrower, dependent store. */ | |
16040 | if (rs6000_sched_groups | |
16041 | && GET_CODE (PATTERN (insn)) == SET | |
16042 | && GET_CODE (PATTERN (dep_insn)) == SET | |
16043 | && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM | |
16044 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM | |
16045 | && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1))) | |
16046 | > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0))))) | |
16047 | return cost + 14; | |
16048 | ||
ed947a96 DJ |
16049 | switch (get_attr_type (insn)) |
16050 | { | |
16051 | case TYPE_JMPREG: | |
309323c2 | 16052 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
16053 | a mtctr and bctr (and mtlr and br/blr). The first |
16054 | scheduling pass will not know about this latency since | |
16055 | the mtctr instruction, which has the latency associated | |
16056 | to it, will be generated by reload. */ | |
309323c2 | 16057 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
16058 | case TYPE_BRANCH: |
16059 | /* Leave some extra cycles between a compare and its | |
16060 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
16061 | if ((rs6000_cpu_attr == CPU_PPC603 |
16062 | || rs6000_cpu_attr == CPU_PPC604 | |
16063 | || rs6000_cpu_attr == CPU_PPC604E | |
16064 | || rs6000_cpu_attr == CPU_PPC620 | |
16065 | || rs6000_cpu_attr == CPU_PPC630 | |
16066 | || rs6000_cpu_attr == CPU_PPC750 | |
16067 | || rs6000_cpu_attr == CPU_PPC7400 | |
16068 | || rs6000_cpu_attr == CPU_PPC7450 | |
ec507f2d DE |
16069 | || rs6000_cpu_attr == CPU_POWER4 |
16070 | || rs6000_cpu_attr == CPU_POWER5) | |
ed947a96 DJ |
16071 | && recog_memoized (dep_insn) |
16072 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
16073 | && (get_attr_type (dep_insn) == TYPE_CMP |
16074 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 16075 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
16076 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
16077 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 16078 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
16079 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
16080 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
16081 | return cost + 2; |
16082 | default: | |
16083 | break; | |
16084 | } | |
a251ffd0 TG |
16085 | /* Fall out to return default cost. */ |
16086 | } | |
16087 | ||
16088 | return cost; | |
16089 | } | |
b6c9286a | 16090 | |
cbe26ab8 | 16091 | /* The function returns a true if INSN is microcoded. |
839a4992 | 16092 | Return false otherwise. */ |
cbe26ab8 DN |
16093 | |
16094 | static bool | |
16095 | is_microcoded_insn (rtx insn) | |
16096 | { | |
16097 | if (!insn || !INSN_P (insn) | |
16098 | || GET_CODE (PATTERN (insn)) == USE | |
16099 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16100 | return false; | |
16101 | ||
ec507f2d | 16102 | if (rs6000_sched_groups) |
cbe26ab8 DN |
16103 | { |
16104 | enum attr_type type = get_attr_type (insn); | |
16105 | if (type == TYPE_LOAD_EXT_U | |
16106 | || type == TYPE_LOAD_EXT_UX | |
16107 | || type == TYPE_LOAD_UX | |
16108 | || type == TYPE_STORE_UX | |
16109 | || type == TYPE_MFCR) | |
c4ad648e | 16110 | return true; |
cbe26ab8 DN |
16111 | } |
16112 | ||
16113 | return false; | |
16114 | } | |
16115 | ||
5c425df5 | 16116 | /* The function returns a nonzero value if INSN can be scheduled only |
cbe26ab8 DN |
16117 | as the first insn in a dispatch group ("dispatch-slot restricted"). |
16118 | In this case, the returned value indicates how many dispatch slots | |
16119 | the insn occupies (at the beginning of the group). | |
79ae11c4 DN |
16120 | Return 0 otherwise. */ |
16121 | ||
cbe26ab8 | 16122 | static int |
79ae11c4 DN |
16123 | is_dispatch_slot_restricted (rtx insn) |
16124 | { | |
16125 | enum attr_type type; | |
16126 | ||
ec507f2d | 16127 | if (!rs6000_sched_groups) |
79ae11c4 DN |
16128 | return 0; |
16129 | ||
16130 | if (!insn | |
16131 | || insn == NULL_RTX | |
16132 | || GET_CODE (insn) == NOTE | |
16133 | || GET_CODE (PATTERN (insn)) == USE | |
16134 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16135 | return 0; | |
16136 | ||
16137 | type = get_attr_type (insn); | |
16138 | ||
ec507f2d DE |
16139 | switch (type) |
16140 | { | |
16141 | case TYPE_MFCR: | |
16142 | case TYPE_MFCRF: | |
16143 | case TYPE_MTCR: | |
16144 | case TYPE_DELAYED_CR: | |
16145 | case TYPE_CR_LOGICAL: | |
16146 | case TYPE_MTJMPR: | |
16147 | case TYPE_MFJMPR: | |
16148 | return 1; | |
16149 | case TYPE_IDIV: | |
16150 | case TYPE_LDIV: | |
16151 | return 2; | |
16152 | default: | |
16153 | if (rs6000_cpu == PROCESSOR_POWER5 | |
16154 | && is_cracked_insn (insn)) | |
16155 | return 2; | |
16156 | return 0; | |
16157 | } | |
79ae11c4 DN |
16158 | } |
16159 | ||
cbe26ab8 DN |
16160 | /* The function returns true if INSN is cracked into 2 instructions |
16161 | by the processor (and therefore occupies 2 issue slots). */ | |
16162 | ||
16163 | static bool | |
16164 | is_cracked_insn (rtx insn) | |
16165 | { | |
16166 | if (!insn || !INSN_P (insn) | |
16167 | || GET_CODE (PATTERN (insn)) == USE | |
16168 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16169 | return false; | |
16170 | ||
ec507f2d | 16171 | if (rs6000_sched_groups) |
cbe26ab8 DN |
16172 | { |
16173 | enum attr_type type = get_attr_type (insn); | |
16174 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
c4ad648e AM |
16175 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U |
16176 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
16177 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
16178 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
16179 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
16180 | || type == TYPE_IDIV || type == TYPE_LDIV | |
16181 | || type == TYPE_INSERT_WORD) | |
16182 | return true; | |
cbe26ab8 DN |
16183 | } |
16184 | ||
16185 | return false; | |
16186 | } | |
16187 | ||
16188 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 16189 | the branch slot. */ |
cbe26ab8 DN |
16190 | |
16191 | static bool | |
16192 | is_branch_slot_insn (rtx insn) | |
16193 | { | |
16194 | if (!insn || !INSN_P (insn) | |
16195 | || GET_CODE (PATTERN (insn)) == USE | |
16196 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
16197 | return false; | |
16198 | ||
ec507f2d | 16199 | if (rs6000_sched_groups) |
cbe26ab8 DN |
16200 | { |
16201 | enum attr_type type = get_attr_type (insn); | |
16202 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
f676971a | 16203 | return true; |
cbe26ab8 DN |
16204 | return false; |
16205 | } | |
16206 | ||
16207 | return false; | |
16208 | } | |
79ae11c4 | 16209 | |
a4f6c312 | 16210 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
16211 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
16212 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
16213 | define this macro if you do not need to adjust the scheduling |
16214 | priorities of insns. */ | |
bef84347 | 16215 | |
c237e94a | 16216 | static int |
a2369ed3 | 16217 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 16218 | { |
a4f6c312 SS |
16219 | /* On machines (like the 750) which have asymmetric integer units, |
16220 | where one integer unit can do multiply and divides and the other | |
16221 | can't, reduce the priority of multiply/divide so it is scheduled | |
16222 | before other integer operations. */ | |
bef84347 VM |
16223 | |
16224 | #if 0 | |
2c3c49de | 16225 | if (! INSN_P (insn)) |
bef84347 VM |
16226 | return priority; |
16227 | ||
16228 | if (GET_CODE (PATTERN (insn)) == USE) | |
16229 | return priority; | |
16230 | ||
16231 | switch (rs6000_cpu_attr) { | |
16232 | case CPU_PPC750: | |
16233 | switch (get_attr_type (insn)) | |
16234 | { | |
16235 | default: | |
16236 | break; | |
16237 | ||
16238 | case TYPE_IMUL: | |
16239 | case TYPE_IDIV: | |
3cb999d8 DE |
16240 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
16241 | priority, priority); | |
bef84347 VM |
16242 | if (priority >= 0 && priority < 0x01000000) |
16243 | priority >>= 3; | |
16244 | break; | |
16245 | } | |
16246 | } | |
16247 | #endif | |
16248 | ||
79ae11c4 DN |
16249 | if (is_dispatch_slot_restricted (insn) |
16250 | && reload_completed | |
f676971a | 16251 | && current_sched_info->sched_max_insns_priority |
79ae11c4 DN |
16252 | && rs6000_sched_restricted_insns_priority) |
16253 | { | |
16254 | ||
c4ad648e AM |
16255 | /* Prioritize insns that can be dispatched only in the first |
16256 | dispatch slot. */ | |
79ae11c4 | 16257 | if (rs6000_sched_restricted_insns_priority == 1) |
f676971a EC |
16258 | /* Attach highest priority to insn. This means that in |
16259 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
79ae11c4 | 16260 | precede 'priority' (critical path) considerations. */ |
f676971a | 16261 | return current_sched_info->sched_max_insns_priority; |
79ae11c4 | 16262 | else if (rs6000_sched_restricted_insns_priority == 2) |
f676971a | 16263 | /* Increase priority of insn by a minimal amount. This means that in |
c4ad648e AM |
16264 | haifa-sched.c:ready_sort(), only 'priority' (critical path) |
16265 | considerations precede dispatch-slot restriction considerations. */ | |
f676971a EC |
16266 | return (priority + 1); |
16267 | } | |
79ae11c4 | 16268 | |
bef84347 VM |
16269 | return priority; |
16270 | } | |
16271 | ||
a4f6c312 SS |
16272 | /* Return how many instructions the machine can issue per cycle. */ |
16273 | ||
c237e94a | 16274 | static int |
863d938c | 16275 | rs6000_issue_rate (void) |
b6c9286a | 16276 | { |
3317bab1 DE |
16277 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
16278 | if (!reload_completed) | |
16279 | return 1; | |
16280 | ||
b6c9286a | 16281 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
16282 | case CPU_RIOS1: /* ? */ |
16283 | case CPU_RS64A: | |
16284 | case CPU_PPC601: /* ? */ | |
ed947a96 | 16285 | case CPU_PPC7450: |
3cb999d8 | 16286 | return 3; |
b54cf83a | 16287 | case CPU_PPC440: |
b6c9286a | 16288 | case CPU_PPC603: |
bef84347 | 16289 | case CPU_PPC750: |
ed947a96 | 16290 | case CPU_PPC7400: |
be12c2b0 | 16291 | case CPU_PPC8540: |
f676971a | 16292 | return 2; |
3cb999d8 | 16293 | case CPU_RIOS2: |
b6c9286a | 16294 | case CPU_PPC604: |
19684119 | 16295 | case CPU_PPC604E: |
b6c9286a | 16296 | case CPU_PPC620: |
3cb999d8 | 16297 | case CPU_PPC630: |
b6c9286a | 16298 | return 4; |
cbe26ab8 | 16299 | case CPU_POWER4: |
ec507f2d | 16300 | case CPU_POWER5: |
cbe26ab8 | 16301 | return 5; |
b6c9286a MM |
16302 | default: |
16303 | return 1; | |
16304 | } | |
16305 | } | |
16306 | ||
be12c2b0 VM |
16307 | /* Return how many instructions to look ahead for better insn |
16308 | scheduling. */ | |
16309 | ||
16310 | static int | |
863d938c | 16311 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
16312 | { |
16313 | if (rs6000_cpu_attr == CPU_PPC8540) | |
16314 | return 4; | |
16315 | return 0; | |
16316 | } | |
16317 | ||
569fa502 DN |
16318 | /* Determine is PAT refers to memory. */ |
16319 | ||
16320 | static bool | |
16321 | is_mem_ref (rtx pat) | |
16322 | { | |
16323 | const char * fmt; | |
16324 | int i, j; | |
16325 | bool ret = false; | |
16326 | ||
16327 | if (GET_CODE (pat) == MEM) | |
16328 | return true; | |
16329 | ||
16330 | /* Recursively process the pattern. */ | |
16331 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
16332 | ||
16333 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
16334 | { | |
16335 | if (fmt[i] == 'e') | |
16336 | ret |= is_mem_ref (XEXP (pat, i)); | |
16337 | else if (fmt[i] == 'E') | |
16338 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
16339 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
16340 | } | |
16341 | ||
16342 | return ret; | |
16343 | } | |
16344 | ||
16345 | /* Determine if PAT is a PATTERN of a load insn. */ | |
f676971a | 16346 | |
569fa502 DN |
16347 | static bool |
16348 | is_load_insn1 (rtx pat) | |
16349 | { | |
16350 | if (!pat || pat == NULL_RTX) | |
16351 | return false; | |
16352 | ||
16353 | if (GET_CODE (pat) == SET) | |
16354 | return is_mem_ref (SET_SRC (pat)); | |
16355 | ||
16356 | if (GET_CODE (pat) == PARALLEL) | |
16357 | { | |
16358 | int i; | |
16359 | ||
16360 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
16361 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
16362 | return true; | |
16363 | } | |
16364 | ||
16365 | return false; | |
16366 | } | |
16367 | ||
16368 | /* Determine if INSN loads from memory. */ | |
16369 | ||
16370 | static bool | |
16371 | is_load_insn (rtx insn) | |
16372 | { | |
16373 | if (!insn || !INSN_P (insn)) | |
16374 | return false; | |
16375 | ||
16376 | if (GET_CODE (insn) == CALL_INSN) | |
16377 | return false; | |
16378 | ||
16379 | return is_load_insn1 (PATTERN (insn)); | |
16380 | } | |
16381 | ||
16382 | /* Determine if PAT is a PATTERN of a store insn. */ | |
16383 | ||
16384 | static bool | |
16385 | is_store_insn1 (rtx pat) | |
16386 | { | |
16387 | if (!pat || pat == NULL_RTX) | |
16388 | return false; | |
16389 | ||
16390 | if (GET_CODE (pat) == SET) | |
16391 | return is_mem_ref (SET_DEST (pat)); | |
16392 | ||
16393 | if (GET_CODE (pat) == PARALLEL) | |
16394 | { | |
16395 | int i; | |
16396 | ||
16397 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
16398 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
16399 | return true; | |
16400 | } | |
16401 | ||
16402 | return false; | |
16403 | } | |
16404 | ||
16405 | /* Determine if INSN stores to memory. */ | |
16406 | ||
16407 | static bool | |
16408 | is_store_insn (rtx insn) | |
16409 | { | |
16410 | if (!insn || !INSN_P (insn)) | |
16411 | return false; | |
16412 | ||
16413 | return is_store_insn1 (PATTERN (insn)); | |
16414 | } | |
16415 | ||
16416 | /* Returns whether the dependence between INSN and NEXT is considered | |
16417 | costly by the given target. */ | |
16418 | ||
16419 | static bool | |
c4ad648e AM |
16420 | rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, |
16421 | int distance) | |
f676971a | 16422 | { |
569fa502 | 16423 | /* If the flag is not enbled - no dependence is considered costly; |
f676971a | 16424 | allow all dependent insns in the same group. |
569fa502 DN |
16425 | This is the most aggressive option. */ |
16426 | if (rs6000_sched_costly_dep == no_dep_costly) | |
16427 | return false; | |
16428 | ||
f676971a | 16429 | /* If the flag is set to 1 - a dependence is always considered costly; |
569fa502 DN |
16430 | do not allow dependent instructions in the same group. |
16431 | This is the most conservative option. */ | |
16432 | if (rs6000_sched_costly_dep == all_deps_costly) | |
f676971a | 16433 | return true; |
569fa502 | 16434 | |
f676971a EC |
16435 | if (rs6000_sched_costly_dep == store_to_load_dep_costly |
16436 | && is_load_insn (next) | |
569fa502 DN |
16437 | && is_store_insn (insn)) |
16438 | /* Prevent load after store in the same group. */ | |
16439 | return true; | |
16440 | ||
16441 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
f676971a | 16442 | && is_load_insn (next) |
569fa502 DN |
16443 | && is_store_insn (insn) |
16444 | && (!link || (int) REG_NOTE_KIND (link) == 0)) | |
c4ad648e AM |
16445 | /* Prevent load after store in the same group if it is a true |
16446 | dependence. */ | |
569fa502 | 16447 | return true; |
f676971a EC |
16448 | |
16449 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
569fa502 DN |
16450 | and will not be scheduled in the same group. */ |
16451 | if (rs6000_sched_costly_dep <= max_dep_latency | |
16452 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
16453 | return true; | |
16454 | ||
16455 | return false; | |
16456 | } | |
16457 | ||
f676971a | 16458 | /* Return the next insn after INSN that is found before TAIL is reached, |
cbe26ab8 DN |
16459 | skipping any "non-active" insns - insns that will not actually occupy |
16460 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
16461 | ||
16462 | static rtx | |
16463 | get_next_active_insn (rtx insn, rtx tail) | |
16464 | { | |
16465 | rtx next_insn; | |
16466 | ||
16467 | if (!insn || insn == tail) | |
16468 | return NULL_RTX; | |
16469 | ||
16470 | next_insn = NEXT_INSN (insn); | |
16471 | ||
16472 | while (next_insn | |
16473 | && next_insn != tail | |
16474 | && (GET_CODE(next_insn) == NOTE | |
16475 | || GET_CODE (PATTERN (next_insn)) == USE | |
16476 | || GET_CODE (PATTERN (next_insn)) == CLOBBER)) | |
16477 | { | |
16478 | next_insn = NEXT_INSN (next_insn); | |
16479 | } | |
16480 | ||
16481 | if (!next_insn || next_insn == tail) | |
16482 | return NULL_RTX; | |
16483 | ||
16484 | return next_insn; | |
16485 | } | |
16486 | ||
839a4992 | 16487 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
16488 | of group WHICH_GROUP. |
16489 | ||
16490 | If WHICH_GROUP == current_group, this function will return true if INSN | |
16491 | causes the termination of the current group (i.e, the dispatch group to | |
16492 | which INSN belongs). This means that INSN will be the last insn in the | |
16493 | group it belongs to. | |
16494 | ||
16495 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
16496 | causes the termination of the previous group (i.e, the dispatch group that | |
16497 | precedes the group to which INSN belongs). This means that INSN will be | |
16498 | the first insn in the group it belongs to). */ | |
16499 | ||
16500 | static bool | |
16501 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
16502 | { | |
16503 | enum attr_type type; | |
16504 | ||
16505 | if (! insn) | |
16506 | return false; | |
569fa502 | 16507 | |
cbe26ab8 DN |
16508 | type = get_attr_type (insn); |
16509 | ||
16510 | if (is_microcoded_insn (insn)) | |
16511 | return true; | |
16512 | ||
16513 | if (which_group == current_group) | |
16514 | { | |
16515 | if (is_branch_slot_insn (insn)) | |
c4ad648e | 16516 | return true; |
cbe26ab8 DN |
16517 | return false; |
16518 | } | |
16519 | else if (which_group == previous_group) | |
16520 | { | |
16521 | if (is_dispatch_slot_restricted (insn)) | |
c4ad648e | 16522 | return true; |
cbe26ab8 DN |
16523 | return false; |
16524 | } | |
16525 | ||
16526 | return false; | |
16527 | } | |
16528 | ||
839a4992 | 16529 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
16530 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
16531 | ||
16532 | static bool | |
16533 | is_costly_group (rtx *group_insns, rtx next_insn) | |
16534 | { | |
16535 | int i; | |
16536 | rtx link; | |
16537 | int cost; | |
16538 | int issue_rate = rs6000_issue_rate (); | |
16539 | ||
16540 | for (i = 0; i < issue_rate; i++) | |
16541 | { | |
16542 | rtx insn = group_insns[i]; | |
16543 | if (!insn) | |
c4ad648e | 16544 | continue; |
cbe26ab8 | 16545 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) |
c4ad648e AM |
16546 | { |
16547 | rtx next = XEXP (link, 0); | |
16548 | if (next == next_insn) | |
16549 | { | |
16550 | cost = insn_cost (insn, link, next_insn); | |
16551 | if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) | |
16552 | return true; | |
16553 | } | |
16554 | } | |
cbe26ab8 DN |
16555 | } |
16556 | ||
16557 | return false; | |
16558 | } | |
16559 | ||
f676971a | 16560 | /* Utility of the function redefine_groups. |
cbe26ab8 DN |
16561 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS |
16562 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
16563 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
16564 | one of the following schemes, depending on the value of the flag | |
16565 | -minsert_sched_nops = X: | |
16566 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 16567 | in order to force NEXT_INSN into a separate group. |
f676971a EC |
16568 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
16569 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
cbe26ab8 DN |
16570 | insertion (has a group just ended, how many vacant issue slots remain in the |
16571 | last group, and how many dispatch groups were encountered so far). */ | |
16572 | ||
f676971a | 16573 | static int |
c4ad648e AM |
16574 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, |
16575 | rtx next_insn, bool *group_end, int can_issue_more, | |
16576 | int *group_count) | |
cbe26ab8 DN |
16577 | { |
16578 | rtx nop; | |
16579 | bool force; | |
16580 | int issue_rate = rs6000_issue_rate (); | |
16581 | bool end = *group_end; | |
16582 | int i; | |
16583 | ||
16584 | if (next_insn == NULL_RTX) | |
16585 | return can_issue_more; | |
16586 | ||
16587 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
16588 | return can_issue_more; | |
16589 | ||
16590 | force = is_costly_group (group_insns, next_insn); | |
16591 | if (!force) | |
16592 | return can_issue_more; | |
16593 | ||
16594 | if (sched_verbose > 6) | |
16595 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
c4ad648e | 16596 | *group_count ,can_issue_more); |
cbe26ab8 DN |
16597 | |
16598 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
16599 | { | |
16600 | if (*group_end) | |
c4ad648e | 16601 | can_issue_more = 0; |
cbe26ab8 DN |
16602 | |
16603 | /* Since only a branch can be issued in the last issue_slot, it is | |
16604 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
16605 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
c4ad648e AM |
16606 | in this case the last nop will start a new group and the branch |
16607 | will be forced to the new group. */ | |
cbe26ab8 | 16608 | if (can_issue_more && !is_branch_slot_insn (next_insn)) |
c4ad648e | 16609 | can_issue_more--; |
cbe26ab8 DN |
16610 | |
16611 | while (can_issue_more > 0) | |
c4ad648e AM |
16612 | { |
16613 | nop = gen_nop(); | |
16614 | emit_insn_before (nop, next_insn); | |
16615 | can_issue_more--; | |
16616 | } | |
cbe26ab8 DN |
16617 | |
16618 | *group_end = true; | |
16619 | return 0; | |
f676971a | 16620 | } |
cbe26ab8 DN |
16621 | |
16622 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
16623 | { | |
16624 | int n_nops = rs6000_sched_insert_nops; | |
16625 | ||
f676971a | 16626 | /* Nops can't be issued from the branch slot, so the effective |
c4ad648e | 16627 | issue_rate for nops is 'issue_rate - 1'. */ |
cbe26ab8 | 16628 | if (can_issue_more == 0) |
c4ad648e | 16629 | can_issue_more = issue_rate; |
cbe26ab8 DN |
16630 | can_issue_more--; |
16631 | if (can_issue_more == 0) | |
c4ad648e AM |
16632 | { |
16633 | can_issue_more = issue_rate - 1; | |
16634 | (*group_count)++; | |
16635 | end = true; | |
16636 | for (i = 0; i < issue_rate; i++) | |
16637 | { | |
16638 | group_insns[i] = 0; | |
16639 | } | |
16640 | } | |
cbe26ab8 DN |
16641 | |
16642 | while (n_nops > 0) | |
c4ad648e AM |
16643 | { |
16644 | nop = gen_nop (); | |
16645 | emit_insn_before (nop, next_insn); | |
16646 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
16647 | end = false; | |
16648 | can_issue_more--; | |
16649 | if (can_issue_more == 0) | |
16650 | { | |
16651 | can_issue_more = issue_rate - 1; | |
16652 | (*group_count)++; | |
16653 | end = true; | |
16654 | for (i = 0; i < issue_rate; i++) | |
16655 | { | |
16656 | group_insns[i] = 0; | |
16657 | } | |
16658 | } | |
16659 | n_nops--; | |
16660 | } | |
cbe26ab8 DN |
16661 | |
16662 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
f676971a | 16663 | can_issue_more++; |
cbe26ab8 | 16664 | |
c4ad648e AM |
16665 | /* Is next_insn going to start a new group? */ |
16666 | *group_end | |
16667 | = (end | |
cbe26ab8 DN |
16668 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) |
16669 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
16670 | || (can_issue_more < issue_rate && | |
c4ad648e | 16671 | insn_terminates_group_p (next_insn, previous_group))); |
cbe26ab8 | 16672 | if (*group_end && end) |
c4ad648e | 16673 | (*group_count)--; |
cbe26ab8 DN |
16674 | |
16675 | if (sched_verbose > 6) | |
c4ad648e AM |
16676 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", |
16677 | *group_count, can_issue_more); | |
f676971a EC |
16678 | return can_issue_more; |
16679 | } | |
cbe26ab8 DN |
16680 | |
16681 | return can_issue_more; | |
16682 | } | |
16683 | ||
16684 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
f676971a | 16685 | with the dispatch groups that the processor dispatcher is expected to |
cbe26ab8 DN |
16686 | form in practice. It tries to achieve this synchronization by forcing the |
16687 | estimated processor grouping on the compiler (as opposed to the function | |
16688 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
16689 | ||
16690 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
16691 | examines the (estimated) dispatch groups that will be formed by the processor | |
16692 | dispatcher. It marks these group boundaries to reflect the estimated | |
16693 | processor grouping, overriding the grouping that the scheduler had marked. | |
16694 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
16695 | force certain insns into separate groups or force a certain distance between | |
16696 | them by inserting nops, for example, if there exists a "costly dependence" | |
16697 | between the insns. | |
16698 | ||
16699 | The function estimates the group boundaries that the processor will form as | |
16700 | folllows: It keeps track of how many vacant issue slots are available after | |
16701 | each insn. A subsequent insn will start a new group if one of the following | |
16702 | 4 cases applies: | |
16703 | - no more vacant issue slots remain in the current dispatch group. | |
16704 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
16705 | insn is not a branch. | |
16706 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
16707 | which means that a cracked insn (which occupies two issue slots) can't be | |
16708 | issued in this group. | |
f676971a | 16709 | - less than 'issue_rate' slots are vacant, and the next insn always needs to |
cbe26ab8 DN |
16710 | start a new group. */ |
16711 | ||
16712 | static int | |
16713 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
16714 | { | |
16715 | rtx insn, next_insn; | |
16716 | int issue_rate; | |
16717 | int can_issue_more; | |
16718 | int slot, i; | |
16719 | bool group_end; | |
16720 | int group_count = 0; | |
16721 | rtx *group_insns; | |
16722 | ||
16723 | /* Initialize. */ | |
16724 | issue_rate = rs6000_issue_rate (); | |
16725 | group_insns = alloca (issue_rate * sizeof (rtx)); | |
f676971a | 16726 | for (i = 0; i < issue_rate; i++) |
cbe26ab8 DN |
16727 | { |
16728 | group_insns[i] = 0; | |
16729 | } | |
16730 | can_issue_more = issue_rate; | |
16731 | slot = 0; | |
16732 | insn = get_next_active_insn (prev_head_insn, tail); | |
16733 | group_end = false; | |
16734 | ||
16735 | while (insn != NULL_RTX) | |
16736 | { | |
16737 | slot = (issue_rate - can_issue_more); | |
16738 | group_insns[slot] = insn; | |
16739 | can_issue_more = | |
c4ad648e | 16740 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); |
cbe26ab8 | 16741 | if (insn_terminates_group_p (insn, current_group)) |
c4ad648e | 16742 | can_issue_more = 0; |
cbe26ab8 DN |
16743 | |
16744 | next_insn = get_next_active_insn (insn, tail); | |
16745 | if (next_insn == NULL_RTX) | |
c4ad648e | 16746 | return group_count + 1; |
cbe26ab8 | 16747 | |
c4ad648e AM |
16748 | /* Is next_insn going to start a new group? */ |
16749 | group_end | |
16750 | = (can_issue_more == 0 | |
16751 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
16752 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
16753 | || (can_issue_more < issue_rate && | |
16754 | insn_terminates_group_p (next_insn, previous_group))); | |
cbe26ab8 | 16755 | |
f676971a | 16756 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, |
c4ad648e AM |
16757 | next_insn, &group_end, can_issue_more, |
16758 | &group_count); | |
cbe26ab8 DN |
16759 | |
16760 | if (group_end) | |
c4ad648e AM |
16761 | { |
16762 | group_count++; | |
16763 | can_issue_more = 0; | |
16764 | for (i = 0; i < issue_rate; i++) | |
16765 | { | |
16766 | group_insns[i] = 0; | |
16767 | } | |
16768 | } | |
cbe26ab8 DN |
16769 | |
16770 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
c4ad648e | 16771 | PUT_MODE(next_insn, VOIDmode); |
cbe26ab8 | 16772 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) |
c4ad648e | 16773 | PUT_MODE (next_insn, TImode); |
cbe26ab8 DN |
16774 | |
16775 | insn = next_insn; | |
16776 | if (can_issue_more == 0) | |
c4ad648e AM |
16777 | can_issue_more = issue_rate; |
16778 | } /* while */ | |
cbe26ab8 DN |
16779 | |
16780 | return group_count; | |
16781 | } | |
16782 | ||
16783 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
16784 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
16785 | any dispatch groups which have vacant issue slots, in order to force the | |
16786 | scheduler's grouping on the processor dispatcher. The function | |
16787 | returns the number of dispatch groups found. */ | |
16788 | ||
16789 | static int | |
16790 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
16791 | { | |
16792 | rtx insn, next_insn; | |
16793 | rtx nop; | |
16794 | int issue_rate; | |
16795 | int can_issue_more; | |
16796 | int group_end; | |
16797 | int group_count = 0; | |
16798 | ||
16799 | /* Initialize issue_rate. */ | |
16800 | issue_rate = rs6000_issue_rate (); | |
16801 | can_issue_more = issue_rate; | |
16802 | ||
16803 | insn = get_next_active_insn (prev_head_insn, tail); | |
16804 | next_insn = get_next_active_insn (insn, tail); | |
16805 | ||
16806 | while (insn != NULL_RTX) | |
16807 | { | |
16808 | can_issue_more = | |
16809 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
16810 | ||
16811 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
16812 | ||
16813 | if (next_insn == NULL_RTX) | |
c4ad648e | 16814 | break; |
cbe26ab8 DN |
16815 | |
16816 | if (group_end) | |
c4ad648e AM |
16817 | { |
16818 | /* If the scheduler had marked group termination at this location | |
16819 | (between insn and next_indn), and neither insn nor next_insn will | |
16820 | force group termination, pad the group with nops to force group | |
16821 | termination. */ | |
16822 | if (can_issue_more | |
16823 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
16824 | && !insn_terminates_group_p (insn, current_group) | |
16825 | && !insn_terminates_group_p (next_insn, previous_group)) | |
16826 | { | |
16827 | if (!is_branch_slot_insn(next_insn)) | |
16828 | can_issue_more--; | |
16829 | ||
16830 | while (can_issue_more) | |
16831 | { | |
16832 | nop = gen_nop (); | |
16833 | emit_insn_before (nop, next_insn); | |
16834 | can_issue_more--; | |
16835 | } | |
16836 | } | |
16837 | ||
16838 | can_issue_more = issue_rate; | |
16839 | group_count++; | |
16840 | } | |
cbe26ab8 DN |
16841 | |
16842 | insn = next_insn; | |
16843 | next_insn = get_next_active_insn (insn, tail); | |
16844 | } | |
16845 | ||
16846 | return group_count; | |
16847 | } | |
16848 | ||
16849 | /* The following function is called at the end of scheduling BB. | |
16850 | After reload, it inserts nops at insn group bundling. */ | |
16851 | ||
16852 | static void | |
38f391a5 | 16853 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
16854 | { |
16855 | int n_groups; | |
16856 | ||
16857 | if (sched_verbose) | |
16858 | fprintf (dump, "=== Finishing schedule.\n"); | |
16859 | ||
ec507f2d | 16860 | if (reload_completed && rs6000_sched_groups) |
cbe26ab8 DN |
16861 | { |
16862 | if (rs6000_sched_insert_nops == sched_finish_none) | |
c4ad648e | 16863 | return; |
cbe26ab8 DN |
16864 | |
16865 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
c4ad648e AM |
16866 | n_groups = pad_groups (dump, sched_verbose, |
16867 | current_sched_info->prev_head, | |
16868 | current_sched_info->next_tail); | |
cbe26ab8 | 16869 | else |
c4ad648e AM |
16870 | n_groups = redefine_groups (dump, sched_verbose, |
16871 | current_sched_info->prev_head, | |
16872 | current_sched_info->next_tail); | |
cbe26ab8 DN |
16873 | |
16874 | if (sched_verbose >= 6) | |
16875 | { | |
16876 | fprintf (dump, "ngroups = %d\n", n_groups); | |
16877 | print_rtl (dump, current_sched_info->prev_head); | |
16878 | fprintf (dump, "Done finish_sched\n"); | |
16879 | } | |
16880 | } | |
16881 | } | |
b6c9286a | 16882 | \f |
b6c9286a MM |
16883 | /* Length in units of the trampoline for entering a nested function. */ |
16884 | ||
16885 | int | |
863d938c | 16886 | rs6000_trampoline_size (void) |
b6c9286a MM |
16887 | { |
16888 | int ret = 0; | |
16889 | ||
16890 | switch (DEFAULT_ABI) | |
16891 | { | |
16892 | default: | |
16893 | abort (); | |
16894 | ||
16895 | case ABI_AIX: | |
8f802bfb | 16896 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
16897 | break; |
16898 | ||
4dabc42d | 16899 | case ABI_DARWIN: |
b6c9286a | 16900 | case ABI_V4: |
03a7e1a5 | 16901 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 16902 | break; |
b6c9286a MM |
16903 | } |
16904 | ||
16905 | return ret; | |
16906 | } | |
16907 | ||
16908 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
16909 | FNADDR is an RTX for the address of the function's pure code. | |
16910 | CXT is an RTX for the static chain value for the function. */ | |
16911 | ||
16912 | void | |
a2369ed3 | 16913 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 16914 | { |
ac2a93a1 | 16915 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
16916 | int regsize = (TARGET_32BIT) ? 4 : 8; |
16917 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
16918 | |
16919 | switch (DEFAULT_ABI) | |
16920 | { | |
16921 | default: | |
16922 | abort (); | |
16923 | ||
8bd04c56 | 16924 | /* Macros to shorten the code expansions below. */ |
39403d82 | 16925 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
16926 | #define MEM_PLUS(addr,offset) \ |
16927 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 16928 | |
b6c9286a MM |
16929 | /* Under AIX, just build the 3 word function descriptor */ |
16930 | case ABI_AIX: | |
8bd04c56 MM |
16931 | { |
16932 | rtx fn_reg = gen_reg_rtx (pmode); | |
16933 | rtx toc_reg = gen_reg_rtx (pmode); | |
16934 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 16935 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
16936 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
16937 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
16938 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
16939 | } | |
b6c9286a MM |
16940 | break; |
16941 | ||
4dabc42d TC |
16942 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
16943 | case ABI_DARWIN: | |
b6c9286a | 16944 | case ABI_V4: |
39403d82 | 16945 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
16946 | FALSE, VOIDmode, 4, |
16947 | addr, pmode, | |
16948 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
16949 | fnaddr, pmode, | |
16950 | ctx_reg, pmode); | |
b6c9286a | 16951 | break; |
b6c9286a MM |
16952 | } |
16953 | ||
16954 | return; | |
16955 | } | |
7509c759 MM |
16956 | |
16957 | \f | |
91d231cb | 16958 | /* Table of valid machine attributes. */ |
a4f6c312 | 16959 | |
91d231cb | 16960 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 16961 | { |
91d231cb | 16962 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8bb418a3 | 16963 | { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, |
a5c76ee6 ZW |
16964 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
16965 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
005c1a13 GK |
16966 | #ifdef SUBTARGET_ATTRIBUTE_TABLE |
16967 | SUBTARGET_ATTRIBUTE_TABLE, | |
16968 | #endif | |
a5c76ee6 | 16969 | { NULL, 0, 0, false, false, false, NULL } |
91d231cb | 16970 | }; |
7509c759 | 16971 | |
8bb418a3 ZL |
16972 | /* Handle the "altivec" attribute. The attribute may have |
16973 | arguments as follows: | |
f676971a | 16974 | |
8bb418a3 ZL |
16975 | __attribute__((altivec(vector__))) |
16976 | __attribute__((altivec(pixel__))) (always followed by 'unsigned short') | |
16977 | __attribute__((altivec(bool__))) (always followed by 'unsigned') | |
16978 | ||
16979 | and may appear more than once (e.g., 'vector bool char') in a | |
16980 | given declaration. */ | |
16981 | ||
16982 | static tree | |
16983 | rs6000_handle_altivec_attribute (tree *node, tree name, tree args, | |
16984 | int flags ATTRIBUTE_UNUSED, | |
16985 | bool *no_add_attrs) | |
16986 | { | |
16987 | tree type = *node, result = NULL_TREE; | |
16988 | enum machine_mode mode; | |
16989 | int unsigned_p; | |
16990 | char altivec_type | |
16991 | = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) | |
16992 | && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) | |
16993 | ? *IDENTIFIER_POINTER (TREE_VALUE (args)) | |
f676971a | 16994 | : '?'); |
8bb418a3 ZL |
16995 | |
16996 | while (POINTER_TYPE_P (type) | |
16997 | || TREE_CODE (type) == FUNCTION_TYPE | |
16998 | || TREE_CODE (type) == METHOD_TYPE | |
16999 | || TREE_CODE (type) == ARRAY_TYPE) | |
17000 | type = TREE_TYPE (type); | |
17001 | ||
17002 | mode = TYPE_MODE (type); | |
17003 | ||
17004 | if (rs6000_warn_altivec_long | |
17005 | && (type == long_unsigned_type_node || type == long_integer_type_node)) | |
17006 | warning ("use of 'long' in AltiVec types is deprecated; use 'int'"); | |
17007 | ||
17008 | switch (altivec_type) | |
17009 | { | |
17010 | case 'v': | |
8df83eae | 17011 | unsigned_p = TYPE_UNSIGNED (type); |
8bb418a3 ZL |
17012 | switch (mode) |
17013 | { | |
c4ad648e AM |
17014 | case SImode: |
17015 | result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); | |
17016 | break; | |
17017 | case HImode: | |
17018 | result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); | |
17019 | break; | |
17020 | case QImode: | |
17021 | result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); | |
17022 | break; | |
17023 | case SFmode: result = V4SF_type_node; break; | |
17024 | /* If the user says 'vector int bool', we may be handed the 'bool' | |
17025 | attribute _before_ the 'vector' attribute, and so select the | |
17026 | proper type in the 'b' case below. */ | |
17027 | case V4SImode: case V8HImode: case V16QImode: case V4SFmode: | |
17028 | result = type; | |
17029 | default: break; | |
8bb418a3 ZL |
17030 | } |
17031 | break; | |
17032 | case 'b': | |
17033 | switch (mode) | |
17034 | { | |
c4ad648e AM |
17035 | case SImode: case V4SImode: result = bool_V4SI_type_node; break; |
17036 | case HImode: case V8HImode: result = bool_V8HI_type_node; break; | |
17037 | case QImode: case V16QImode: result = bool_V16QI_type_node; | |
17038 | default: break; | |
8bb418a3 ZL |
17039 | } |
17040 | break; | |
17041 | case 'p': | |
17042 | switch (mode) | |
17043 | { | |
c4ad648e AM |
17044 | case V8HImode: result = pixel_V8HI_type_node; |
17045 | default: break; | |
8bb418a3 ZL |
17046 | } |
17047 | default: break; | |
17048 | } | |
17049 | ||
7958a2a6 FJ |
17050 | if (result && result != type && TYPE_READONLY (type)) |
17051 | result = build_qualified_type (result, TYPE_QUAL_CONST); | |
17052 | ||
8bb418a3 ZL |
17053 | *no_add_attrs = true; /* No need to hang on to the attribute. */ |
17054 | ||
17055 | if (!result) | |
9e637a26 | 17056 | warning ("%qs attribute ignored", IDENTIFIER_POINTER (name)); |
8bb418a3 ZL |
17057 | else |
17058 | *node = reconstruct_complex_type (*node, result); | |
17059 | ||
17060 | return NULL_TREE; | |
17061 | } | |
17062 | ||
f18eca82 ZL |
17063 | /* AltiVec defines four built-in scalar types that serve as vector |
17064 | elements; we must teach the compiler how to mangle them. */ | |
17065 | ||
17066 | static const char * | |
17067 | rs6000_mangle_fundamental_type (tree type) | |
17068 | { | |
17069 | if (type == bool_char_type_node) return "U6__boolc"; | |
17070 | if (type == bool_short_type_node) return "U6__bools"; | |
17071 | if (type == pixel_type_node) return "u7__pixel"; | |
17072 | if (type == bool_int_type_node) return "U6__booli"; | |
17073 | ||
17074 | /* For all other types, use normal C++ mangling. */ | |
17075 | return NULL; | |
17076 | } | |
17077 | ||
a5c76ee6 ZW |
17078 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
17079 | struct attribute_spec.handler. */ | |
a4f6c312 | 17080 | |
91d231cb | 17081 | static tree |
f676971a EC |
17082 | rs6000_handle_longcall_attribute (tree *node, tree name, |
17083 | tree args ATTRIBUTE_UNUSED, | |
17084 | int flags ATTRIBUTE_UNUSED, | |
a2369ed3 | 17085 | bool *no_add_attrs) |
91d231cb JM |
17086 | { |
17087 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
17088 | && TREE_CODE (*node) != FIELD_DECL | |
17089 | && TREE_CODE (*node) != TYPE_DECL) | |
17090 | { | |
9e637a26 | 17091 | warning ("%qs attribute only applies to functions", |
91d231cb JM |
17092 | IDENTIFIER_POINTER (name)); |
17093 | *no_add_attrs = true; | |
17094 | } | |
6a4cee5f | 17095 | |
91d231cb | 17096 | return NULL_TREE; |
7509c759 MM |
17097 | } |
17098 | ||
a5c76ee6 ZW |
17099 | /* Set longcall attributes on all functions declared when |
17100 | rs6000_default_long_calls is true. */ | |
17101 | static void | |
a2369ed3 | 17102 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
17103 | { |
17104 | if (rs6000_default_long_calls | |
17105 | && (TREE_CODE (type) == FUNCTION_TYPE | |
17106 | || TREE_CODE (type) == METHOD_TYPE)) | |
17107 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
17108 | NULL_TREE, | |
17109 | TYPE_ATTRIBUTES (type)); | |
17110 | } | |
17111 | ||
3cb999d8 DE |
17112 | /* Return a reference suitable for calling a function with the |
17113 | longcall attribute. */ | |
a4f6c312 | 17114 | |
6a4cee5f | 17115 | struct rtx_def * |
a2369ed3 | 17116 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 17117 | { |
d330fd93 | 17118 | const char *call_name; |
6a4cee5f MM |
17119 | tree node; |
17120 | ||
17121 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
17122 | return call_ref; | |
17123 | ||
17124 | /* System V adds '.' to the internal name, so skip them. */ | |
17125 | call_name = XSTR (call_ref, 0); | |
17126 | if (*call_name == '.') | |
17127 | { | |
17128 | while (*call_name == '.') | |
17129 | call_name++; | |
17130 | ||
17131 | node = get_identifier (call_name); | |
39403d82 | 17132 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
17133 | } |
17134 | ||
17135 | return force_reg (Pmode, call_ref); | |
17136 | } | |
7509c759 | 17137 | \f |
b64a1b53 RH |
17138 | #ifdef USING_ELFOS_H |
17139 | ||
7509c759 MM |
17140 | /* A C statement or statements to switch to the appropriate section |
17141 | for output of RTX in mode MODE. You can assume that RTX is some | |
17142 | kind of constant in RTL. The argument MODE is redundant except in | |
17143 | the case of a `const_int' rtx. Select the section by calling | |
17144 | `text_section' or one of the alternatives for other sections. | |
17145 | ||
17146 | Do not define this macro if you put all constants in the read-only | |
17147 | data section. */ | |
17148 | ||
b64a1b53 | 17149 | static void |
f676971a | 17150 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
a2369ed3 | 17151 | unsigned HOST_WIDE_INT align) |
7509c759 | 17152 | { |
a9098fd0 | 17153 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 17154 | toc_section (); |
7509c759 | 17155 | else |
b64a1b53 | 17156 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
17157 | } |
17158 | ||
17159 | /* A C statement or statements to switch to the appropriate | |
17160 | section for output of DECL. DECL is either a `VAR_DECL' node | |
17161 | or a constant of some sort. RELOC indicates whether forming | |
17162 | the initial value of DECL requires link-time relocations. */ | |
17163 | ||
ae46c4e0 | 17164 | static void |
f676971a | 17165 | rs6000_elf_select_section (tree decl, int reloc, |
a2369ed3 | 17166 | unsigned HOST_WIDE_INT align) |
7509c759 | 17167 | { |
f1384257 AM |
17168 | /* Pretend that we're always building for a shared library when |
17169 | ABI_AIX, because otherwise we end up with dynamic relocations | |
17170 | in read-only sections. This happens for function pointers, | |
17171 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
17172 | default_elf_select_section_1 (decl, reloc, align, |
17173 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
17174 | } |
17175 | ||
17176 | /* A C statement to build up a unique section name, expressed as a | |
17177 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
17178 | RELOC indicates whether the initial value of EXP requires | |
17179 | link-time relocations. If you do not define this macro, GCC will use | |
17180 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 17181 | macro can now be called for uninitialized data items as well as |
4912a07c | 17182 | initialized data and functions. */ |
63019373 | 17183 | |
ae46c4e0 | 17184 | static void |
a2369ed3 | 17185 | rs6000_elf_unique_section (tree decl, int reloc) |
63019373 | 17186 | { |
f1384257 AM |
17187 | /* As above, pretend that we're always building for a shared library |
17188 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
17189 | default_unique_section_1 (decl, reloc, |
17190 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 17191 | } |
d9407988 | 17192 | \f |
d1908feb JJ |
17193 | /* For a SYMBOL_REF, set generic flags and then perform some |
17194 | target-specific processing. | |
17195 | ||
d1908feb JJ |
17196 | When the AIX ABI is requested on a non-AIX system, replace the |
17197 | function name with the real name (with a leading .) rather than the | |
17198 | function descriptor name. This saves a lot of overriding code to | |
17199 | read the prefixes. */ | |
d9407988 | 17200 | |
fb49053f | 17201 | static void |
a2369ed3 | 17202 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 17203 | { |
d1908feb | 17204 | default_encode_section_info (decl, rtl, first); |
b2003250 | 17205 | |
d1908feb JJ |
17206 | if (first |
17207 | && TREE_CODE (decl) == FUNCTION_DECL | |
17208 | && !TARGET_AIX | |
17209 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 17210 | { |
c6a2438a | 17211 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
17212 | size_t len = strlen (XSTR (sym_ref, 0)); |
17213 | char *str = alloca (len + 2); | |
17214 | str[0] = '.'; | |
17215 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
17216 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 17217 | } |
d9407988 MM |
17218 | } |
17219 | ||
0e5dbd9b | 17220 | static bool |
a2369ed3 | 17221 | rs6000_elf_in_small_data_p (tree decl) |
0e5dbd9b DE |
17222 | { |
17223 | if (rs6000_sdata == SDATA_NONE) | |
17224 | return false; | |
17225 | ||
17226 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) | |
17227 | { | |
17228 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
17229 | if (strcmp (section, ".sdata") == 0 | |
17230 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
17231 | || strcmp (section, ".sbss") == 0 |
17232 | || strcmp (section, ".sbss2") == 0 | |
17233 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
17234 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
17235 | return true; |
17236 | } | |
17237 | else | |
17238 | { | |
17239 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
17240 | ||
17241 | if (size > 0 | |
307b599c | 17242 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
17243 | /* If it's not public, and we're not going to reference it there, |
17244 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
17245 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
17246 | return true; | |
17247 | } | |
17248 | ||
17249 | return false; | |
17250 | } | |
17251 | ||
b91da81f | 17252 | #endif /* USING_ELFOS_H */ |
000034eb | 17253 | |
a6c2a102 | 17254 | \f |
000034eb | 17255 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
17256 | ADDR can be effectively incremented by incrementing REG. |
17257 | ||
17258 | r0 is special and we must not select it as an address | |
17259 | register by this routine since our caller will try to | |
17260 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
17261 | |
17262 | struct rtx_def * | |
a2369ed3 | 17263 | find_addr_reg (rtx addr) |
000034eb DE |
17264 | { |
17265 | while (GET_CODE (addr) == PLUS) | |
17266 | { | |
02441cd6 JL |
17267 | if (GET_CODE (XEXP (addr, 0)) == REG |
17268 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 17269 | addr = XEXP (addr, 0); |
02441cd6 JL |
17270 | else if (GET_CODE (XEXP (addr, 1)) == REG |
17271 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
17272 | addr = XEXP (addr, 1); |
17273 | else if (CONSTANT_P (XEXP (addr, 0))) | |
17274 | addr = XEXP (addr, 1); | |
17275 | else if (CONSTANT_P (XEXP (addr, 1))) | |
17276 | addr = XEXP (addr, 0); | |
17277 | else | |
17278 | abort (); | |
17279 | } | |
02441cd6 | 17280 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
17281 | return addr; |
17282 | abort (); | |
17283 | } | |
17284 | ||
a6c2a102 | 17285 | void |
a2369ed3 | 17286 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
17287 | { |
17288 | fatal_insn ("bad address", op); | |
17289 | } | |
c8023011 | 17290 | |
ee890fe2 SS |
17291 | #if TARGET_MACHO |
17292 | ||
efdba735 | 17293 | static tree branch_island_list = 0; |
ee890fe2 | 17294 | |
efdba735 SH |
17295 | /* Remember to generate a branch island for far calls to the given |
17296 | function. */ | |
ee890fe2 | 17297 | |
f676971a | 17298 | static void |
c4ad648e AM |
17299 | add_compiler_branch_island (tree label_name, tree function_name, |
17300 | int line_number) | |
ee890fe2 | 17301 | { |
efdba735 | 17302 | tree branch_island = build_tree_list (function_name, label_name); |
7d60be94 | 17303 | TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number); |
efdba735 SH |
17304 | TREE_CHAIN (branch_island) = branch_island_list; |
17305 | branch_island_list = branch_island; | |
ee890fe2 SS |
17306 | } |
17307 | ||
efdba735 SH |
17308 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
17309 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
17310 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
17311 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 17312 | |
efdba735 SH |
17313 | /* Generate far-jump branch islands for everything on the |
17314 | branch_island_list. Invoked immediately after the last instruction | |
17315 | of the epilogue has been emitted; the branch-islands must be | |
17316 | appended to, and contiguous with, the function body. Mach-O stubs | |
17317 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 17318 | |
efdba735 SH |
17319 | static void |
17320 | macho_branch_islands (void) | |
17321 | { | |
17322 | char tmp_buf[512]; | |
17323 | tree branch_island; | |
17324 | ||
17325 | for (branch_island = branch_island_list; | |
17326 | branch_island; | |
17327 | branch_island = TREE_CHAIN (branch_island)) | |
17328 | { | |
17329 | const char *label = | |
17330 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
17331 | const char *name = | |
11abc112 | 17332 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)); |
efdba735 SH |
17333 | char name_buf[512]; |
17334 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
17335 | if (name[0] == '*' || name[0] == '&') | |
17336 | strcpy (name_buf, name+1); | |
17337 | else | |
17338 | { | |
17339 | name_buf[0] = '_'; | |
17340 | strcpy (name_buf+1, name); | |
17341 | } | |
17342 | strcpy (tmp_buf, "\n"); | |
17343 | strcat (tmp_buf, label); | |
ee890fe2 | 17344 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 17345 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 17346 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 17347 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
17348 | if (flag_pic) |
17349 | { | |
17350 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
17351 | strcat (tmp_buf, label); | |
17352 | strcat (tmp_buf, "_pic\n"); | |
17353 | strcat (tmp_buf, label); | |
17354 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
f676971a | 17355 | |
efdba735 SH |
17356 | strcat (tmp_buf, "\taddis r11,r11,ha16("); |
17357 | strcat (tmp_buf, name_buf); | |
17358 | strcat (tmp_buf, " - "); | |
17359 | strcat (tmp_buf, label); | |
17360 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 17361 | |
efdba735 | 17362 | strcat (tmp_buf, "\tmtlr r0\n"); |
f676971a | 17363 | |
efdba735 SH |
17364 | strcat (tmp_buf, "\taddi r12,r11,lo16("); |
17365 | strcat (tmp_buf, name_buf); | |
17366 | strcat (tmp_buf, " - "); | |
17367 | strcat (tmp_buf, label); | |
17368 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 17369 | |
efdba735 SH |
17370 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); |
17371 | } | |
17372 | else | |
17373 | { | |
17374 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
17375 | strcat (tmp_buf, name_buf); | |
17376 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
17377 | strcat (tmp_buf, name_buf); | |
17378 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
17379 | } | |
17380 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 17381 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 17382 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 17383 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 17384 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 17385 | } |
ee890fe2 | 17386 | |
efdba735 | 17387 | branch_island_list = 0; |
ee890fe2 SS |
17388 | } |
17389 | ||
17390 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
17391 | already there or not. */ | |
17392 | ||
efdba735 | 17393 | static int |
a2369ed3 | 17394 | no_previous_def (tree function_name) |
ee890fe2 | 17395 | { |
efdba735 SH |
17396 | tree branch_island; |
17397 | for (branch_island = branch_island_list; | |
17398 | branch_island; | |
17399 | branch_island = TREE_CHAIN (branch_island)) | |
17400 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
17401 | return 0; |
17402 | return 1; | |
17403 | } | |
17404 | ||
17405 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
17406 | the function. */ | |
17407 | ||
efdba735 | 17408 | static tree |
a2369ed3 | 17409 | get_prev_label (tree function_name) |
ee890fe2 | 17410 | { |
efdba735 SH |
17411 | tree branch_island; |
17412 | for (branch_island = branch_island_list; | |
17413 | branch_island; | |
17414 | branch_island = TREE_CHAIN (branch_island)) | |
17415 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
17416 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
17417 | return 0; |
17418 | } | |
17419 | ||
17420 | /* INSN is either a function call or a millicode call. It may have an | |
f676971a | 17421 | unconditional jump in its delay slot. |
ee890fe2 SS |
17422 | |
17423 | CALL_DEST is the routine we are calling. */ | |
17424 | ||
17425 | char * | |
c4ad648e AM |
17426 | output_call (rtx insn, rtx *operands, int dest_operand_number, |
17427 | int cookie_operand_number) | |
ee890fe2 SS |
17428 | { |
17429 | static char buf[256]; | |
efdba735 SH |
17430 | if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF |
17431 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) | |
ee890fe2 SS |
17432 | { |
17433 | tree labelname; | |
efdba735 | 17434 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
f676971a | 17435 | |
ee890fe2 SS |
17436 | if (no_previous_def (funname)) |
17437 | { | |
308c142a | 17438 | int line_number = 0; |
ee890fe2 SS |
17439 | rtx label_rtx = gen_label_rtx (); |
17440 | char *label_buf, temp_buf[256]; | |
17441 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
17442 | CODE_LABEL_NUMBER (label_rtx)); | |
17443 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
17444 | labelname = get_identifier (label_buf); | |
17445 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
17446 | if (insn) | |
17447 | line_number = NOTE_LINE_NUMBER (insn); | |
efdba735 | 17448 | add_compiler_branch_island (labelname, funname, line_number); |
ee890fe2 SS |
17449 | } |
17450 | else | |
17451 | labelname = get_prev_label (funname); | |
17452 | ||
efdba735 SH |
17453 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
17454 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
17455 | "L42" should be a 'branch island', that will do a far jump to | |
17456 | 'foo'. Branch islands are generated in | |
17457 | macho_branch_islands(). */ | |
ee890fe2 | 17458 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 17459 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
17460 | } |
17461 | else | |
efdba735 SH |
17462 | sprintf (buf, "bl %%z%d", dest_operand_number); |
17463 | return buf; | |
ee890fe2 SS |
17464 | } |
17465 | ||
ee890fe2 SS |
17466 | /* Generate PIC and indirect symbol stubs. */ |
17467 | ||
17468 | void | |
a2369ed3 | 17469 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
17470 | { |
17471 | unsigned int length; | |
a4f6c312 SS |
17472 | char *symbol_name, *lazy_ptr_name; |
17473 | char *local_label_0; | |
ee890fe2 SS |
17474 | static int label = 0; |
17475 | ||
df56a27f | 17476 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 17477 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 17478 | |
ee890fe2 | 17479 | |
ee890fe2 SS |
17480 | length = strlen (symb); |
17481 | symbol_name = alloca (length + 32); | |
17482 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
17483 | ||
17484 | lazy_ptr_name = alloca (length + 32); | |
17485 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
17486 | ||
ee890fe2 | 17487 | if (flag_pic == 2) |
d3c300d2 | 17488 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 17489 | else |
d3c300d2 | 17490 | machopic_symbol_stub1_section (); |
ee890fe2 SS |
17491 | |
17492 | if (flag_pic == 2) | |
17493 | { | |
d974312d DJ |
17494 | fprintf (file, "\t.align 5\n"); |
17495 | ||
17496 | fprintf (file, "%s:\n", stub); | |
17497 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
17498 | ||
876455fa AP |
17499 | label++; |
17500 | local_label_0 = alloca (sizeof("\"L0000000000$spb\"")); | |
17501 | sprintf (local_label_0, "\"L%011d$spb\"", label); | |
f676971a | 17502 | |
ee890fe2 SS |
17503 | fprintf (file, "\tmflr r0\n"); |
17504 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
17505 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
17506 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
17507 | lazy_ptr_name, local_label_0); | |
17508 | fprintf (file, "\tmtlr r0\n"); | |
3d0e2d58 SS |
17509 | fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n", |
17510 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
ee890fe2 SS |
17511 | lazy_ptr_name, local_label_0); |
17512 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
17513 | fprintf (file, "\tbctr\n"); |
17514 | } | |
17515 | else | |
d974312d DJ |
17516 | { |
17517 | fprintf (file, "\t.align 4\n"); | |
17518 | ||
17519 | fprintf (file, "%s:\n", stub); | |
17520 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
17521 | ||
17522 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
17523 | fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name); | |
17524 | fprintf (file, "\tmtctr r12\n"); | |
17525 | fprintf (file, "\tbctr\n"); | |
17526 | } | |
f676971a | 17527 | |
ee890fe2 SS |
17528 | machopic_lazy_symbol_ptr_section (); |
17529 | fprintf (file, "%s:\n", lazy_ptr_name); | |
17530 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
49bd1d27 SS |
17531 | fprintf (file, "%sdyld_stub_binding_helper\n", |
17532 | (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t")); | |
ee890fe2 SS |
17533 | } |
17534 | ||
17535 | /* Legitimize PIC addresses. If the address is already | |
17536 | position-independent, we return ORIG. Newly generated | |
17537 | position-independent addresses go into a reg. This is REG if non | |
17538 | zero, otherwise we allocate register(s) as necessary. */ | |
17539 | ||
c859cda6 | 17540 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
17541 | |
17542 | rtx | |
f676971a | 17543 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
a2369ed3 | 17544 | rtx reg) |
ee890fe2 SS |
17545 | { |
17546 | rtx base, offset; | |
17547 | ||
17548 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
17549 | reg = gen_reg_rtx (Pmode); | |
17550 | ||
17551 | if (GET_CODE (orig) == CONST) | |
17552 | { | |
17553 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
17554 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
17555 | return orig; | |
17556 | ||
17557 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
17558 | { | |
2cf520bf | 17559 | /* Use a different reg for the intermediate value, as |
a3c9585f | 17560 | it will be marked UNCHANGING. */ |
2cf520bf GK |
17561 | rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); |
17562 | ||
a4f6c312 SS |
17563 | base = |
17564 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
2cf520bf | 17565 | Pmode, reg_temp); |
a4f6c312 SS |
17566 | offset = |
17567 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
17568 | Pmode, reg); | |
ee890fe2 SS |
17569 | } |
17570 | else | |
17571 | abort (); | |
17572 | ||
17573 | if (GET_CODE (offset) == CONST_INT) | |
17574 | { | |
17575 | if (SMALL_INT (offset)) | |
ed8908e7 | 17576 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
17577 | else if (! reload_in_progress && ! reload_completed) |
17578 | offset = force_reg (Pmode, offset); | |
17579 | else | |
c859cda6 DJ |
17580 | { |
17581 | rtx mem = force_const_mem (Pmode, orig); | |
17582 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
17583 | } | |
ee890fe2 | 17584 | } |
f1c25d3b | 17585 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
17586 | } |
17587 | ||
17588 | /* Fall back on generic machopic code. */ | |
17589 | return machopic_legitimize_pic_address (orig, mode, reg); | |
17590 | } | |
17591 | ||
17592 | /* This is just a placeholder to make linking work without having to | |
17593 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
17594 | ever needed for Darwin (not too likely!) this would have to get a | |
17595 | real definition. */ | |
17596 | ||
17597 | void | |
863d938c | 17598 | toc_section (void) |
ee890fe2 SS |
17599 | { |
17600 | } | |
17601 | ||
c4e18b1c GK |
17602 | /* Output a .machine directive for the Darwin assembler, and call |
17603 | the generic start_file routine. */ | |
17604 | ||
17605 | static void | |
17606 | rs6000_darwin_file_start (void) | |
17607 | { | |
94ff898d | 17608 | static const struct |
c4e18b1c GK |
17609 | { |
17610 | const char *arg; | |
17611 | const char *name; | |
17612 | int if_set; | |
17613 | } mapping[] = { | |
55dbfb48 | 17614 | { "ppc64", "ppc64", MASK_64BIT }, |
c4e18b1c GK |
17615 | { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, |
17616 | { "power4", "ppc970", 0 }, | |
17617 | { "G5", "ppc970", 0 }, | |
17618 | { "7450", "ppc7450", 0 }, | |
17619 | { "7400", "ppc7400", MASK_ALTIVEC }, | |
17620 | { "G4", "ppc7400", 0 }, | |
17621 | { "750", "ppc750", 0 }, | |
17622 | { "740", "ppc750", 0 }, | |
17623 | { "G3", "ppc750", 0 }, | |
17624 | { "604e", "ppc604e", 0 }, | |
17625 | { "604", "ppc604", 0 }, | |
17626 | { "603e", "ppc603", 0 }, | |
17627 | { "603", "ppc603", 0 }, | |
17628 | { "601", "ppc601", 0 }, | |
17629 | { NULL, "ppc", 0 } }; | |
17630 | const char *cpu_id = ""; | |
17631 | size_t i; | |
94ff898d | 17632 | |
c4e18b1c GK |
17633 | rs6000_file_start(); |
17634 | ||
17635 | /* Determine the argument to -mcpu=. Default to G3 if not specified. */ | |
17636 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) | |
17637 | if (rs6000_select[i].set_arch_p && rs6000_select[i].string | |
17638 | && rs6000_select[i].string[0] != '\0') | |
17639 | cpu_id = rs6000_select[i].string; | |
17640 | ||
17641 | /* Look through the mapping array. Pick the first name that either | |
17642 | matches the argument, has a bit set in IF_SET that is also set | |
17643 | in the target flags, or has a NULL name. */ | |
17644 | ||
17645 | i = 0; | |
17646 | while (mapping[i].arg != NULL | |
17647 | && strcmp (mapping[i].arg, cpu_id) != 0 | |
17648 | && (mapping[i].if_set & target_flags) == 0) | |
17649 | i++; | |
17650 | ||
17651 | fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); | |
17652 | } | |
17653 | ||
ee890fe2 | 17654 | #endif /* TARGET_MACHO */ |
7c262518 RH |
17655 | |
17656 | #if TARGET_ELF | |
17657 | static unsigned int | |
a2369ed3 | 17658 | rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) |
7c262518 | 17659 | { |
1ff8f81a AM |
17660 | return default_section_type_flags_1 (decl, name, reloc, |
17661 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 17662 | } |
d9f6800d RH |
17663 | |
17664 | /* Record an element in the table of global constructors. SYMBOL is | |
17665 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
17666 | between 0 and MAX_INIT_PRIORITY. | |
17667 | ||
17668 | This differs from default_named_section_asm_out_constructor in | |
17669 | that we have special handling for -mrelocatable. */ | |
17670 | ||
17671 | static void | |
a2369ed3 | 17672 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
17673 | { |
17674 | const char *section = ".ctors"; | |
17675 | char buf[16]; | |
17676 | ||
17677 | if (priority != DEFAULT_INIT_PRIORITY) | |
17678 | { | |
17679 | sprintf (buf, ".ctors.%.5u", | |
c4ad648e AM |
17680 | /* Invert the numbering so the linker puts us in the proper |
17681 | order; constructors are run from right to left, and the | |
17682 | linker sorts in increasing order. */ | |
17683 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
17684 | section = buf; |
17685 | } | |
17686 | ||
715bdd29 RH |
17687 | named_section_flags (section, SECTION_WRITE); |
17688 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
17689 | |
17690 | if (TARGET_RELOCATABLE) | |
17691 | { | |
17692 | fputs ("\t.long (", asm_out_file); | |
17693 | output_addr_const (asm_out_file, symbol); | |
17694 | fputs (")@fixup\n", asm_out_file); | |
17695 | } | |
17696 | else | |
c8af3574 | 17697 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
17698 | } |
17699 | ||
17700 | static void | |
a2369ed3 | 17701 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
17702 | { |
17703 | const char *section = ".dtors"; | |
17704 | char buf[16]; | |
17705 | ||
17706 | if (priority != DEFAULT_INIT_PRIORITY) | |
17707 | { | |
17708 | sprintf (buf, ".dtors.%.5u", | |
c4ad648e AM |
17709 | /* Invert the numbering so the linker puts us in the proper |
17710 | order; constructors are run from right to left, and the | |
17711 | linker sorts in increasing order. */ | |
17712 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
17713 | section = buf; |
17714 | } | |
17715 | ||
715bdd29 RH |
17716 | named_section_flags (section, SECTION_WRITE); |
17717 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
17718 | |
17719 | if (TARGET_RELOCATABLE) | |
17720 | { | |
17721 | fputs ("\t.long (", asm_out_file); | |
17722 | output_addr_const (asm_out_file, symbol); | |
17723 | fputs (")@fixup\n", asm_out_file); | |
17724 | } | |
17725 | else | |
c8af3574 | 17726 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 17727 | } |
9739c90c JJ |
17728 | |
17729 | void | |
a2369ed3 | 17730 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
17731 | { |
17732 | if (TARGET_64BIT) | |
17733 | { | |
17734 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
17735 | ASM_OUTPUT_LABEL (file, name); | |
17736 | fputs (DOUBLE_INT_ASM_OP, file); | |
85b776df AM |
17737 | rs6000_output_function_entry (file, name); |
17738 | fputs (",.TOC.@tocbase,0\n\t.previous\n", file); | |
17739 | if (DOT_SYMBOLS) | |
9739c90c | 17740 | { |
85b776df | 17741 | fputs ("\t.size\t", file); |
9739c90c | 17742 | assemble_name (file, name); |
85b776df AM |
17743 | fputs (",24\n\t.type\t.", file); |
17744 | assemble_name (file, name); | |
17745 | fputs (",@function\n", file); | |
17746 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
17747 | { | |
17748 | fputs ("\t.globl\t.", file); | |
17749 | assemble_name (file, name); | |
17750 | putc ('\n', file); | |
17751 | } | |
9739c90c | 17752 | } |
85b776df AM |
17753 | else |
17754 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
9739c90c | 17755 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); |
85b776df AM |
17756 | rs6000_output_function_entry (file, name); |
17757 | fputs (":\n", file); | |
9739c90c JJ |
17758 | return; |
17759 | } | |
17760 | ||
17761 | if (TARGET_RELOCATABLE | |
17762 | && (get_pool_size () != 0 || current_function_profile) | |
3c9eb5f4 | 17763 | && uses_TOC ()) |
9739c90c JJ |
17764 | { |
17765 | char buf[256]; | |
17766 | ||
17767 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
17768 | ||
17769 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
17770 | fprintf (file, "\t.long "); | |
17771 | assemble_name (file, buf); | |
17772 | putc ('-', file); | |
17773 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
17774 | assemble_name (file, buf); | |
17775 | putc ('\n', file); | |
17776 | } | |
17777 | ||
17778 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
17779 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
17780 | ||
17781 | if (DEFAULT_ABI == ABI_AIX) | |
17782 | { | |
17783 | const char *desc_name, *orig_name; | |
17784 | ||
17785 | orig_name = (*targetm.strip_name_encoding) (name); | |
17786 | desc_name = orig_name; | |
17787 | while (*desc_name == '.') | |
17788 | desc_name++; | |
17789 | ||
17790 | if (TREE_PUBLIC (decl)) | |
17791 | fprintf (file, "\t.globl %s\n", desc_name); | |
17792 | ||
17793 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
17794 | fprintf (file, "%s:\n", desc_name); | |
17795 | fprintf (file, "\t.long %s\n", orig_name); | |
17796 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
17797 | if (DEFAULT_ABI == ABI_AIX) | |
17798 | fputs ("\t.long 0\n", file); | |
17799 | fprintf (file, "\t.previous\n"); | |
17800 | } | |
17801 | ASM_OUTPUT_LABEL (file, name); | |
17802 | } | |
7c262518 RH |
17803 | #endif |
17804 | ||
cbaaba19 | 17805 | #if TARGET_XCOFF |
7c262518 | 17806 | static void |
a2369ed3 | 17807 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
17808 | { |
17809 | fputs (GLOBAL_ASM_OP, stream); | |
17810 | RS6000_OUTPUT_BASENAME (stream, name); | |
17811 | putc ('\n', stream); | |
17812 | } | |
17813 | ||
17814 | static void | |
c18a5b6c MM |
17815 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags, |
17816 | tree decl ATTRIBUTE_UNUSED) | |
7c262518 | 17817 | { |
0e5dbd9b DE |
17818 | int smclass; |
17819 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
17820 | ||
17821 | if (flags & SECTION_CODE) | |
17822 | smclass = 0; | |
17823 | else if (flags & SECTION_WRITE) | |
17824 | smclass = 2; | |
17825 | else | |
17826 | smclass = 1; | |
17827 | ||
5b5198f7 | 17828 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 17829 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 17830 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 17831 | } |
ae46c4e0 RH |
17832 | |
17833 | static void | |
f676971a | 17834 | rs6000_xcoff_select_section (tree decl, int reloc, |
c4ad648e | 17835 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
ae46c4e0 | 17836 | { |
5add3202 | 17837 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 17838 | { |
0e5dbd9b | 17839 | if (TREE_PUBLIC (decl)) |
c4ad648e | 17840 | read_only_data_section (); |
ae46c4e0 | 17841 | else |
c4ad648e | 17842 | read_only_private_data_section (); |
ae46c4e0 RH |
17843 | } |
17844 | else | |
17845 | { | |
0e5dbd9b | 17846 | if (TREE_PUBLIC (decl)) |
c4ad648e | 17847 | data_section (); |
ae46c4e0 | 17848 | else |
c4ad648e | 17849 | private_data_section (); |
ae46c4e0 RH |
17850 | } |
17851 | } | |
17852 | ||
17853 | static void | |
a2369ed3 | 17854 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
17855 | { |
17856 | const char *name; | |
ae46c4e0 | 17857 | |
5b5198f7 DE |
17858 | /* Use select_section for private and uninitialized data. */ |
17859 | if (!TREE_PUBLIC (decl) | |
17860 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
17861 | || DECL_INITIAL (decl) == NULL_TREE |
17862 | || DECL_INITIAL (decl) == error_mark_node | |
17863 | || (flag_zero_initialized_in_bss | |
17864 | && initializer_zerop (DECL_INITIAL (decl)))) | |
17865 | return; | |
17866 | ||
17867 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
17868 | name = (*targetm.strip_name_encoding) (name); | |
17869 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 17870 | } |
b64a1b53 | 17871 | |
fb49053f RH |
17872 | /* Select section for constant in constant pool. |
17873 | ||
17874 | On RS/6000, all constants are in the private read-only data area. | |
17875 | However, if this is being placed in the TOC it must be output as a | |
17876 | toc entry. */ | |
17877 | ||
b64a1b53 | 17878 | static void |
f676971a | 17879 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
c4ad648e | 17880 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
b64a1b53 RH |
17881 | { |
17882 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
17883 | toc_section (); | |
17884 | else | |
17885 | read_only_private_data_section (); | |
17886 | } | |
772c5265 RH |
17887 | |
17888 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
17889 | ||
17890 | static const char * | |
a2369ed3 | 17891 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
17892 | { |
17893 | size_t len; | |
17894 | if (*name == '*') | |
17895 | name++; | |
17896 | len = strlen (name); | |
17897 | if (name[len - 1] == ']') | |
17898 | return ggc_alloc_string (name, len - 4); | |
17899 | else | |
17900 | return name; | |
17901 | } | |
17902 | ||
5add3202 DE |
17903 | /* Section attributes. AIX is always PIC. */ |
17904 | ||
17905 | static unsigned int | |
a2369ed3 | 17906 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 17907 | { |
5b5198f7 DE |
17908 | unsigned int align; |
17909 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
17910 | ||
17911 | /* Align to at least UNIT size. */ | |
17912 | if (flags & SECTION_CODE) | |
17913 | align = MIN_UNITS_PER_WORD; | |
17914 | else | |
17915 | /* Increase alignment of large objects if not already stricter. */ | |
17916 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
17917 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
17918 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
17919 | ||
17920 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 17921 | } |
a5fe455b | 17922 | |
1bc7c5b6 ZW |
17923 | /* Output at beginning of assembler file. |
17924 | ||
17925 | Initialize the section names for the RS/6000 at this point. | |
17926 | ||
17927 | Specify filename, including full path, to assembler. | |
17928 | ||
17929 | We want to go into the TOC section so at least one .toc will be emitted. | |
17930 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
17931 | [RW] section emitted. | |
17932 | ||
17933 | Finally, declare mcount when profiling to make the assembler happy. */ | |
17934 | ||
17935 | static void | |
863d938c | 17936 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
17937 | { |
17938 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
17939 | main_input_filename, ".bss_"); | |
17940 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
17941 | main_input_filename, ".rw_"); | |
17942 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
17943 | main_input_filename, ".ro_"); | |
17944 | ||
17945 | fputs ("\t.file\t", asm_out_file); | |
17946 | output_quoted_string (asm_out_file, main_input_filename); | |
17947 | fputc ('\n', asm_out_file); | |
17948 | toc_section (); | |
17949 | if (write_symbols != NO_DEBUG) | |
17950 | private_data_section (); | |
17951 | text_section (); | |
17952 | if (profile_flag) | |
17953 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
17954 | rs6000_file_start (); | |
17955 | } | |
17956 | ||
a5fe455b ZW |
17957 | /* Output at end of assembler file. |
17958 | On the RS/6000, referencing data should automatically pull in text. */ | |
17959 | ||
17960 | static void | |
863d938c | 17961 | rs6000_xcoff_file_end (void) |
a5fe455b ZW |
17962 | { |
17963 | text_section (); | |
17964 | fputs ("_section_.text:\n", asm_out_file); | |
17965 | data_section (); | |
17966 | fputs (TARGET_32BIT | |
17967 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
17968 | asm_out_file); | |
17969 | } | |
f1384257 | 17970 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 17971 | |
f1384257 AM |
17972 | #if TARGET_MACHO |
17973 | /* Cross-module name binding. Darwin does not support overriding | |
7f3d8013 | 17974 | functions at dynamic-link time. */ |
0e5dbd9b | 17975 | |
2bcc50d0 | 17976 | static bool |
a2369ed3 | 17977 | rs6000_binds_local_p (tree decl) |
0e5dbd9b | 17978 | { |
f1384257 | 17979 | return default_binds_local_p_1 (decl, 0); |
0e5dbd9b | 17980 | } |
f1384257 | 17981 | #endif |
34bb030a | 17982 | |
3c50106f RH |
17983 | /* Compute a (partial) cost for rtx X. Return true if the complete |
17984 | cost has been computed, and false if subexpressions should be | |
17985 | scanned. In either case, *TOTAL contains the cost result. */ | |
17986 | ||
17987 | static bool | |
1494c534 | 17988 | rs6000_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f | 17989 | { |
f0517163 RS |
17990 | enum machine_mode mode = GET_MODE (x); |
17991 | ||
3c50106f RH |
17992 | switch (code) |
17993 | { | |
30a555d9 | 17994 | /* On the RS/6000, if it is valid in the insn, it is free. */ |
3c50106f | 17995 | case CONST_INT: |
066cd967 DE |
17996 | if (((outer_code == SET |
17997 | || outer_code == PLUS | |
17998 | || outer_code == MINUS) | |
17999 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
18000 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))) | |
18001 | || ((outer_code == IOR || outer_code == XOR) | |
18002 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
18003 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))) | |
627b6fe2 DJ |
18004 | || ((outer_code == DIV || outer_code == UDIV |
18005 | || outer_code == MOD || outer_code == UMOD) | |
18006 | && exact_log2 (INTVAL (x)) >= 0) | |
066cd967 DE |
18007 | || (outer_code == AND |
18008 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
18009 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L') | |
d5861a7a | 18010 | || mask_operand (x, VOIDmode))) |
066cd967 DE |
18011 | || outer_code == ASHIFT |
18012 | || outer_code == ASHIFTRT | |
18013 | || outer_code == LSHIFTRT | |
18014 | || outer_code == ROTATE | |
18015 | || outer_code == ROTATERT | |
d5861a7a | 18016 | || outer_code == ZERO_EXTRACT |
066cd967 DE |
18017 | || (outer_code == MULT |
18018 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
18019 | || (outer_code == COMPARE | |
18020 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
18021 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))) | |
18022 | { | |
18023 | *total = 0; | |
18024 | return true; | |
18025 | } | |
18026 | else if ((outer_code == PLUS | |
18027 | && reg_or_add_cint64_operand (x, VOIDmode)) | |
18028 | || (outer_code == MINUS | |
18029 | && reg_or_sub_cint64_operand (x, VOIDmode)) | |
18030 | || ((outer_code == SET | |
18031 | || outer_code == IOR | |
18032 | || outer_code == XOR) | |
18033 | && (INTVAL (x) | |
18034 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0)) | |
18035 | { | |
18036 | *total = COSTS_N_INSNS (1); | |
18037 | return true; | |
18038 | } | |
18039 | /* FALLTHRU */ | |
18040 | ||
18041 | case CONST_DOUBLE: | |
18042 | if (mode == DImode | |
18043 | && ((outer_code == AND | |
18044 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
18045 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L') | |
d5861a7a | 18046 | || mask64_operand (x, DImode))) |
066cd967 DE |
18047 | || ((outer_code == IOR || outer_code == XOR) |
18048 | && CONST_DOUBLE_HIGH (x) == 0 | |
18049 | && (CONST_DOUBLE_LOW (x) | |
18050 | & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0))) | |
18051 | { | |
18052 | *total = 0; | |
18053 | return true; | |
18054 | } | |
18055 | else if (mode == DImode | |
18056 | && (outer_code == SET | |
18057 | || outer_code == IOR | |
18058 | || outer_code == XOR) | |
18059 | && CONST_DOUBLE_HIGH (x) == 0) | |
18060 | { | |
18061 | *total = COSTS_N_INSNS (1); | |
18062 | return true; | |
18063 | } | |
18064 | /* FALLTHRU */ | |
18065 | ||
3c50106f | 18066 | case CONST: |
066cd967 | 18067 | case HIGH: |
3c50106f | 18068 | case SYMBOL_REF: |
066cd967 DE |
18069 | case MEM: |
18070 | /* When optimizing for size, MEM should be slightly more expensive | |
18071 | than generating address, e.g., (plus (reg) (const)). | |
c112cf2b | 18072 | L1 cache latency is about two instructions. */ |
066cd967 | 18073 | *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); |
3c50106f RH |
18074 | return true; |
18075 | ||
30a555d9 DE |
18076 | case LABEL_REF: |
18077 | *total = 0; | |
18078 | return true; | |
18079 | ||
3c50106f | 18080 | case PLUS: |
f0517163 | 18081 | if (mode == DFmode) |
066cd967 DE |
18082 | { |
18083 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
18084 | { | |
18085 | /* FNMA accounted in outer NEG. */ | |
18086 | if (outer_code == NEG) | |
18087 | *total = rs6000_cost->dmul - rs6000_cost->fp; | |
18088 | else | |
18089 | *total = rs6000_cost->dmul; | |
18090 | } | |
18091 | else | |
18092 | *total = rs6000_cost->fp; | |
18093 | } | |
f0517163 | 18094 | else if (mode == SFmode) |
066cd967 DE |
18095 | { |
18096 | /* FNMA accounted in outer NEG. */ | |
18097 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
18098 | *total = 0; | |
18099 | else | |
18100 | *total = rs6000_cost->fp; | |
18101 | } | |
938bf747 RS |
18102 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
18103 | { | |
18104 | /* The rs6000 doesn't have shift-and-add instructions. */ | |
18105 | rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total); | |
18106 | *total += COSTS_N_INSNS (1); | |
18107 | } | |
f0517163 | 18108 | else |
066cd967 DE |
18109 | *total = COSTS_N_INSNS (1); |
18110 | return false; | |
3c50106f | 18111 | |
52190329 | 18112 | case MINUS: |
f0517163 | 18113 | if (mode == DFmode) |
066cd967 DE |
18114 | { |
18115 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
18116 | { | |
18117 | /* FNMA accounted in outer NEG. */ | |
18118 | if (outer_code == NEG) | |
18119 | *total = 0; | |
18120 | else | |
18121 | *total = rs6000_cost->dmul; | |
18122 | } | |
18123 | else | |
18124 | *total = rs6000_cost->fp; | |
18125 | } | |
f0517163 | 18126 | else if (mode == SFmode) |
066cd967 DE |
18127 | { |
18128 | /* FNMA accounted in outer NEG. */ | |
18129 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
18130 | *total = 0; | |
18131 | else | |
18132 | *total = rs6000_cost->fp; | |
18133 | } | |
938bf747 RS |
18134 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
18135 | { | |
18136 | /* The rs6000 doesn't have shift-and-sub instructions. */ | |
18137 | rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total); | |
18138 | *total += COSTS_N_INSNS (1); | |
18139 | } | |
f0517163 | 18140 | else |
c4ad648e | 18141 | *total = COSTS_N_INSNS (1); |
066cd967 | 18142 | return false; |
3c50106f RH |
18143 | |
18144 | case MULT: | |
c9dbf840 DE |
18145 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
18146 | && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I')) | |
3c50106f | 18147 | { |
8b897cfa RS |
18148 | if (INTVAL (XEXP (x, 1)) >= -256 |
18149 | && INTVAL (XEXP (x, 1)) <= 255) | |
06a67bdd | 18150 | *total = rs6000_cost->mulsi_const9; |
8b897cfa | 18151 | else |
06a67bdd | 18152 | *total = rs6000_cost->mulsi_const; |
3c50106f | 18153 | } |
066cd967 DE |
18154 | /* FMA accounted in outer PLUS/MINUS. */ |
18155 | else if ((mode == DFmode || mode == SFmode) | |
18156 | && (outer_code == PLUS || outer_code == MINUS)) | |
18157 | *total = 0; | |
f0517163 | 18158 | else if (mode == DFmode) |
06a67bdd | 18159 | *total = rs6000_cost->dmul; |
f0517163 | 18160 | else if (mode == SFmode) |
06a67bdd | 18161 | *total = rs6000_cost->fp; |
f0517163 | 18162 | else if (mode == DImode) |
06a67bdd | 18163 | *total = rs6000_cost->muldi; |
8b897cfa | 18164 | else |
06a67bdd | 18165 | *total = rs6000_cost->mulsi; |
066cd967 | 18166 | return false; |
3c50106f RH |
18167 | |
18168 | case DIV: | |
18169 | case MOD: | |
f0517163 RS |
18170 | if (FLOAT_MODE_P (mode)) |
18171 | { | |
06a67bdd RS |
18172 | *total = mode == DFmode ? rs6000_cost->ddiv |
18173 | : rs6000_cost->sdiv; | |
066cd967 | 18174 | return false; |
f0517163 | 18175 | } |
5efb1046 | 18176 | /* FALLTHRU */ |
3c50106f RH |
18177 | |
18178 | case UDIV: | |
18179 | case UMOD: | |
627b6fe2 DJ |
18180 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
18181 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
18182 | { | |
18183 | if (code == DIV || code == MOD) | |
18184 | /* Shift, addze */ | |
18185 | *total = COSTS_N_INSNS (2); | |
18186 | else | |
18187 | /* Shift */ | |
18188 | *total = COSTS_N_INSNS (1); | |
18189 | } | |
c4ad648e | 18190 | else |
627b6fe2 DJ |
18191 | { |
18192 | if (GET_MODE (XEXP (x, 1)) == DImode) | |
18193 | *total = rs6000_cost->divdi; | |
18194 | else | |
18195 | *total = rs6000_cost->divsi; | |
18196 | } | |
18197 | /* Add in shift and subtract for MOD. */ | |
18198 | if (code == MOD || code == UMOD) | |
18199 | *total += COSTS_N_INSNS (2); | |
066cd967 | 18200 | return false; |
3c50106f RH |
18201 | |
18202 | case FFS: | |
18203 | *total = COSTS_N_INSNS (4); | |
066cd967 | 18204 | return false; |
3c50106f | 18205 | |
06a67bdd | 18206 | case NOT: |
066cd967 DE |
18207 | if (outer_code == AND || outer_code == IOR || outer_code == XOR) |
18208 | { | |
18209 | *total = 0; | |
18210 | return false; | |
18211 | } | |
18212 | /* FALLTHRU */ | |
18213 | ||
18214 | case AND: | |
18215 | case IOR: | |
18216 | case XOR: | |
d5861a7a DE |
18217 | case ZERO_EXTRACT: |
18218 | *total = COSTS_N_INSNS (1); | |
18219 | return false; | |
18220 | ||
066cd967 DE |
18221 | case ASHIFT: |
18222 | case ASHIFTRT: | |
18223 | case LSHIFTRT: | |
18224 | case ROTATE: | |
18225 | case ROTATERT: | |
d5861a7a | 18226 | /* Handle mul_highpart. */ |
066cd967 DE |
18227 | if (outer_code == TRUNCATE |
18228 | && GET_CODE (XEXP (x, 0)) == MULT) | |
18229 | { | |
18230 | if (mode == DImode) | |
18231 | *total = rs6000_cost->muldi; | |
18232 | else | |
18233 | *total = rs6000_cost->mulsi; | |
18234 | return true; | |
18235 | } | |
d5861a7a DE |
18236 | else if (outer_code == AND) |
18237 | *total = 0; | |
18238 | else | |
18239 | *total = COSTS_N_INSNS (1); | |
18240 | return false; | |
18241 | ||
18242 | case SIGN_EXTEND: | |
18243 | case ZERO_EXTEND: | |
18244 | if (GET_CODE (XEXP (x, 0)) == MEM) | |
18245 | *total = 0; | |
18246 | else | |
18247 | *total = COSTS_N_INSNS (1); | |
066cd967 | 18248 | return false; |
06a67bdd | 18249 | |
066cd967 DE |
18250 | case COMPARE: |
18251 | case NEG: | |
18252 | case ABS: | |
18253 | if (!FLOAT_MODE_P (mode)) | |
18254 | { | |
18255 | *total = COSTS_N_INSNS (1); | |
18256 | return false; | |
18257 | } | |
18258 | /* FALLTHRU */ | |
18259 | ||
18260 | case FLOAT: | |
18261 | case UNSIGNED_FLOAT: | |
18262 | case FIX: | |
18263 | case UNSIGNED_FIX: | |
18264 | case FLOAT_EXTEND: | |
06a67bdd RS |
18265 | case FLOAT_TRUNCATE: |
18266 | *total = rs6000_cost->fp; | |
066cd967 | 18267 | return false; |
06a67bdd RS |
18268 | |
18269 | case UNSPEC: | |
18270 | switch (XINT (x, 1)) | |
18271 | { | |
18272 | case UNSPEC_FRSP: | |
18273 | *total = rs6000_cost->fp; | |
18274 | return true; | |
18275 | ||
18276 | default: | |
18277 | break; | |
18278 | } | |
18279 | break; | |
18280 | ||
18281 | case CALL: | |
18282 | case IF_THEN_ELSE: | |
18283 | if (optimize_size) | |
18284 | { | |
18285 | *total = COSTS_N_INSNS (1); | |
18286 | return true; | |
18287 | } | |
066cd967 DE |
18288 | else if (FLOAT_MODE_P (mode) |
18289 | && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS) | |
18290 | { | |
18291 | *total = rs6000_cost->fp; | |
18292 | return false; | |
18293 | } | |
06a67bdd RS |
18294 | break; |
18295 | ||
c0600ecd DE |
18296 | case EQ: |
18297 | case GTU: | |
18298 | case LTU: | |
18299 | if (mode == Pmode) | |
18300 | { | |
18301 | switch (outer_code) | |
18302 | { | |
18303 | case PLUS: | |
18304 | case NEG: | |
18305 | /* PLUS or NEG already counted so only add one more. */ | |
18306 | *total = COSTS_N_INSNS (1); | |
18307 | break; | |
18308 | case SET: | |
18309 | *total = COSTS_N_INSNS (3); | |
18310 | break; | |
18311 | case COMPARE: | |
18312 | *total = 0; | |
18313 | return true; | |
18314 | default: | |
18315 | break; | |
18316 | } | |
18317 | return false; | |
18318 | } | |
18319 | ||
3c50106f | 18320 | default: |
06a67bdd | 18321 | break; |
3c50106f | 18322 | } |
06a67bdd RS |
18323 | |
18324 | return false; | |
3c50106f RH |
18325 | } |
18326 | ||
34bb030a DE |
18327 | /* A C expression returning the cost of moving data from a register of class |
18328 | CLASS1 to one of CLASS2. */ | |
18329 | ||
18330 | int | |
f676971a | 18331 | rs6000_register_move_cost (enum machine_mode mode, |
a2369ed3 | 18332 | enum reg_class from, enum reg_class to) |
34bb030a DE |
18333 | { |
18334 | /* Moves from/to GENERAL_REGS. */ | |
18335 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
18336 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
18337 | { | |
18338 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
18339 | from = to; | |
18340 | ||
18341 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
18342 | return (rs6000_memory_move_cost (mode, from, 0) | |
18343 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
18344 | ||
c4ad648e AM |
18345 | /* It's more expensive to move CR_REGS than CR0_REGS because of the |
18346 | shift. */ | |
34bb030a DE |
18347 | else if (from == CR_REGS) |
18348 | return 4; | |
18349 | ||
18350 | else | |
c4ad648e | 18351 | /* A move will cost one instruction per GPR moved. */ |
34bb030a DE |
18352 | return 2 * HARD_REGNO_NREGS (0, mode); |
18353 | } | |
18354 | ||
c4ad648e | 18355 | /* Moving between two similar registers is just one instruction. */ |
34bb030a DE |
18356 | else if (reg_classes_intersect_p (to, from)) |
18357 | return mode == TFmode ? 4 : 2; | |
18358 | ||
c4ad648e | 18359 | /* Everything else has to go through GENERAL_REGS. */ |
34bb030a | 18360 | else |
f676971a | 18361 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) |
34bb030a DE |
18362 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); |
18363 | } | |
18364 | ||
18365 | /* A C expressions returning the cost of moving data of MODE from a register to | |
18366 | or from memory. */ | |
18367 | ||
18368 | int | |
f676971a | 18369 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, |
a2369ed3 | 18370 | int in ATTRIBUTE_UNUSED) |
34bb030a DE |
18371 | { |
18372 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
18373 | return 4 * HARD_REGNO_NREGS (0, mode); | |
18374 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) | |
18375 | return 4 * HARD_REGNO_NREGS (32, mode); | |
18376 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) | |
18377 | return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); | |
18378 | else | |
18379 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
18380 | } | |
18381 | ||
ded9bf77 AH |
18382 | /* Return an RTX representing where to find the function value of a |
18383 | function returning MODE. */ | |
18384 | static rtx | |
18385 | rs6000_complex_function_value (enum machine_mode mode) | |
18386 | { | |
18387 | unsigned int regno; | |
18388 | rtx r1, r2; | |
18389 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 18390 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 | 18391 | |
18f63bfa AH |
18392 | if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
18393 | regno = FP_ARG_RETURN; | |
354ed18f AH |
18394 | else |
18395 | { | |
18f63bfa | 18396 | regno = GP_ARG_RETURN; |
ded9bf77 | 18397 | |
18f63bfa AH |
18398 | /* 32-bit is OK since it'll go in r3/r4. */ |
18399 | if (TARGET_32BIT && inner_bytes >= 4) | |
ded9bf77 AH |
18400 | return gen_rtx_REG (mode, regno); |
18401 | } | |
18402 | ||
18f63bfa AH |
18403 | if (inner_bytes >= 8) |
18404 | return gen_rtx_REG (mode, regno); | |
18405 | ||
ded9bf77 AH |
18406 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
18407 | const0_rtx); | |
18408 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 18409 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
18410 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
18411 | } | |
18412 | ||
594a51fe SS |
18413 | /* Compose a PARALLEL for a darwin64 struct being returned by |
18414 | value. */ | |
18415 | ||
18416 | static rtx | |
18417 | rs6000_darwin64_function_value (CUMULATIVE_ARGS *cum, tree valtype) | |
18418 | { | |
18419 | tree f, ftype; | |
18420 | rtx rvec[FIRST_PSEUDO_REGISTER], sub, roffset, suboff; | |
18421 | int k = 0, bytepos, tot, elt, i, subbytepos; | |
18422 | enum machine_mode fmode; | |
18423 | ||
18424 | switch (TREE_CODE (valtype)) | |
18425 | { | |
18426 | case RECORD_TYPE: | |
18427 | for (f = TYPE_FIELDS (valtype); f ; f = TREE_CHAIN (f)) | |
18428 | if (TREE_CODE (f) == FIELD_DECL) | |
18429 | { | |
18430 | ftype = TREE_TYPE (f); | |
18431 | fmode = TYPE_MODE (ftype); | |
18432 | bytepos = int_bit_position (f) / BITS_PER_UNIT; | |
18433 | if (USE_FP_FOR_ARG_P (cum, fmode, ftype)) | |
18434 | { | |
18435 | sub = gen_rtx_REG (fmode, cum->fregno++); | |
18436 | cum->sysv_gregno++; | |
18437 | } | |
18438 | else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1)) | |
18439 | { | |
18440 | sub = gen_rtx_REG (fmode, cum->vregno++); | |
18441 | cum->sysv_gregno++; | |
18442 | } | |
18443 | else if (fmode == BLKmode | |
18444 | && (TREE_CODE (ftype) == RECORD_TYPE | |
18445 | || TREE_CODE (ftype) == ARRAY_TYPE)) | |
18446 | sub = rs6000_darwin64_function_value (cum, ftype); | |
18447 | else | |
18448 | sub = gen_rtx_REG (fmode, cum->sysv_gregno++); | |
18449 | if (sub == NULL_RTX) | |
18450 | return sub; | |
18451 | else if (GET_CODE (sub) == PARALLEL) | |
18452 | { | |
18453 | for (i = 0; i < XVECLEN (sub, 0); i++) | |
18454 | { | |
18455 | rtx subsub = XVECEXP (sub, 0, i); | |
18456 | ||
18457 | suboff = XEXP (subsub, 1); | |
18458 | subbytepos = INTVAL (suboff); | |
18459 | subbytepos += bytepos; | |
18460 | roffset = gen_rtx_CONST_INT (SImode, subbytepos); | |
18461 | subsub = XEXP (subsub, 0); | |
18462 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset); | |
18463 | } | |
18464 | } | |
18465 | else | |
18466 | { | |
18467 | roffset = gen_rtx_CONST_INT (SImode, bytepos); | |
18468 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset); | |
18469 | } | |
18470 | } | |
18471 | if (k > 0) | |
18472 | return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec)); | |
18473 | else | |
18474 | return NULL_RTX; | |
18475 | ||
18476 | case ARRAY_TYPE: | |
18477 | /* If passing by value won't work, give up. */ | |
18478 | if (int_size_in_bytes (valtype) <= 0) | |
18479 | return NULL_RTX; | |
18480 | ftype = TREE_TYPE (valtype); | |
18481 | fmode = TYPE_MODE (ftype); | |
18482 | tot = int_size_in_bytes (valtype) / int_size_in_bytes (ftype); | |
18483 | bytepos = 0; | |
18484 | for (elt = 0; elt < tot; ++elt) | |
18485 | { | |
18486 | if (USE_FP_FOR_ARG_P (cum, fmode, ftype)) | |
18487 | { | |
18488 | sub = gen_rtx_REG (fmode, cum->fregno++); | |
18489 | cum->sysv_gregno++; | |
18490 | } | |
18491 | else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1)) | |
18492 | { | |
18493 | sub = gen_rtx_REG (fmode, cum->vregno++); | |
18494 | cum->sysv_gregno++; | |
18495 | } | |
18496 | else if (fmode == BLKmode | |
18497 | && (TREE_CODE (ftype) == RECORD_TYPE | |
18498 | || TREE_CODE (ftype) == ARRAY_TYPE)) | |
18499 | sub = rs6000_darwin64_function_value (cum, ftype); | |
18500 | else | |
18501 | sub = gen_rtx_REG (fmode, cum->sysv_gregno++); | |
18502 | if (sub == NULL_RTX) | |
18503 | return sub; | |
18504 | else if (GET_CODE (sub) == PARALLEL) | |
18505 | { | |
18506 | for (i = 0; i < XVECLEN (sub, 0); i++) | |
18507 | { | |
18508 | rtx subsub = XVECEXP (sub, 0, i); | |
18509 | ||
18510 | suboff = XEXP (subsub, 1); | |
18511 | subbytepos = INTVAL (suboff); | |
18512 | subbytepos += bytepos; | |
18513 | roffset = gen_rtx_CONST_INT (SImode, subbytepos); | |
18514 | subsub = XEXP (subsub, 0); | |
18515 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset); | |
18516 | } | |
18517 | } | |
18518 | else | |
18519 | { | |
18520 | roffset = gen_rtx_CONST_INT (SImode, bytepos); | |
18521 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset); | |
18522 | } | |
18523 | bytepos += int_size_in_bytes (ftype); | |
18524 | } | |
18525 | if (k > 0) | |
18526 | return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec)); | |
18527 | else | |
18528 | return NULL_RTX; | |
18529 | ||
18530 | default: | |
18531 | abort (); | |
18532 | } | |
18533 | } | |
18534 | ||
a6ebc39a AH |
18535 | /* Define how to find the value returned by a function. |
18536 | VALTYPE is the data type of the value (as a tree). | |
18537 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
18538 | otherwise, FUNC is 0. | |
18539 | ||
18540 | On the SPE, both FPs and vectors are returned in r3. | |
18541 | ||
18542 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
18543 | fp1, unless -msoft-float. */ | |
18544 | ||
18545 | rtx | |
18546 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
18547 | { | |
18548 | enum machine_mode mode; | |
2a8fa26c | 18549 | unsigned int regno; |
a6ebc39a | 18550 | |
594a51fe SS |
18551 | /* Special handling for structs in darwin64. */ |
18552 | if (rs6000_darwin64_abi | |
18553 | && TYPE_MODE (valtype) == BLKmode | |
18554 | && (TREE_CODE (valtype) == RECORD_TYPE | |
18555 | || TREE_CODE (valtype) == ARRAY_TYPE)) | |
18556 | { | |
18557 | CUMULATIVE_ARGS valcum; | |
18558 | rtx valret; | |
18559 | ||
18560 | valcum.sysv_gregno = GP_ARG_RETURN; | |
18561 | valcum.fregno = FP_ARG_MIN_REG; | |
18562 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
18563 | valret = rs6000_darwin64_function_value (&valcum, valtype); | |
18564 | if (valret) | |
18565 | return valret; | |
18566 | /* Otherwise fall through to standard ABI rules. */ | |
18567 | } | |
18568 | ||
0e67400a FJ |
18569 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
18570 | { | |
18571 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
18572 | return gen_rtx_PARALLEL (DImode, | |
18573 | gen_rtvec (2, | |
18574 | gen_rtx_EXPR_LIST (VOIDmode, | |
18575 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
18576 | const0_rtx), | |
18577 | gen_rtx_EXPR_LIST (VOIDmode, | |
18578 | gen_rtx_REG (SImode, | |
18579 | GP_ARG_RETURN + 1), | |
18580 | GEN_INT (4)))); | |
18581 | } | |
18582 | ||
a6ebc39a AH |
18583 | if ((INTEGRAL_TYPE_P (valtype) |
18584 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
18585 | || POINTER_TYPE_P (valtype)) | |
b78d48dd | 18586 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a AH |
18587 | else |
18588 | mode = TYPE_MODE (valtype); | |
18589 | ||
4ed78545 | 18590 | if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) |
2a8fa26c | 18591 | regno = FP_ARG_RETURN; |
ded9bf77 | 18592 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
42ba5130 | 18593 | && targetm.calls.split_complex_arg) |
ded9bf77 | 18594 | return rs6000_complex_function_value (mode); |
44688022 | 18595 | else if (TREE_CODE (valtype) == VECTOR_TYPE |
d0b2079e FJ |
18596 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI |
18597 | && ALTIVEC_VECTOR_MODE(mode)) | |
a6ebc39a | 18598 | regno = ALTIVEC_ARG_RETURN; |
18f63bfa AH |
18599 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
18600 | && (mode == DFmode || mode == DCmode)) | |
18601 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
a6ebc39a AH |
18602 | else |
18603 | regno = GP_ARG_RETURN; | |
18604 | ||
18605 | return gen_rtx_REG (mode, regno); | |
18606 | } | |
18607 | ||
ded9bf77 AH |
18608 | /* Define how to find the value returned by a library function |
18609 | assuming the value has mode MODE. */ | |
18610 | rtx | |
18611 | rs6000_libcall_value (enum machine_mode mode) | |
18612 | { | |
18613 | unsigned int regno; | |
18614 | ||
2e6c9641 FJ |
18615 | if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode) |
18616 | { | |
18617 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
18618 | return gen_rtx_PARALLEL (DImode, | |
18619 | gen_rtvec (2, | |
18620 | gen_rtx_EXPR_LIST (VOIDmode, | |
18621 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
18622 | const0_rtx), | |
18623 | gen_rtx_EXPR_LIST (VOIDmode, | |
18624 | gen_rtx_REG (SImode, | |
18625 | GP_ARG_RETURN + 1), | |
18626 | GEN_INT (4)))); | |
18627 | } | |
18628 | ||
ded9bf77 AH |
18629 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
18630 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
18631 | regno = FP_ARG_RETURN; | |
44688022 AM |
18632 | else if (ALTIVEC_VECTOR_MODE (mode) |
18633 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
ded9bf77 | 18634 | regno = ALTIVEC_ARG_RETURN; |
42ba5130 | 18635 | else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) |
ded9bf77 | 18636 | return rs6000_complex_function_value (mode); |
18f63bfa AH |
18637 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
18638 | && (mode == DFmode || mode == DCmode)) | |
18639 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
ded9bf77 AH |
18640 | else |
18641 | regno = GP_ARG_RETURN; | |
18642 | ||
18643 | return gen_rtx_REG (mode, regno); | |
18644 | } | |
18645 | ||
d1d0c603 JJ |
18646 | /* Define the offset between two registers, FROM to be eliminated and its |
18647 | replacement TO, at the start of a routine. */ | |
18648 | HOST_WIDE_INT | |
18649 | rs6000_initial_elimination_offset (int from, int to) | |
18650 | { | |
18651 | rs6000_stack_t *info = rs6000_stack_info (); | |
18652 | HOST_WIDE_INT offset; | |
18653 | ||
18654 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
18655 | offset = info->push_p ? 0 : -info->total_size; | |
18656 | else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
18657 | offset = info->total_size; | |
18658 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
18659 | offset = info->push_p ? info->total_size : 0; | |
18660 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
18661 | offset = 0; | |
18662 | else | |
18663 | abort (); | |
18664 | ||
18665 | return offset; | |
18666 | } | |
18667 | ||
62e1dfcf NC |
18668 | /* Return true if TYPE is of type __ev64_opaque__. */ |
18669 | ||
c8e4f0e9 | 18670 | static bool |
a2369ed3 | 18671 | is_ev64_opaque_type (tree type) |
62e1dfcf | 18672 | { |
c8e4f0e9 | 18673 | return (TARGET_SPE |
2abe3e28 AH |
18674 | && (type == opaque_V2SI_type_node |
18675 | || type == opaque_V2SF_type_node | |
36252949 | 18676 | || type == opaque_p_V2SI_type_node)); |
62e1dfcf NC |
18677 | } |
18678 | ||
96714395 | 18679 | static rtx |
a2369ed3 | 18680 | rs6000_dwarf_register_span (rtx reg) |
96714395 AH |
18681 | { |
18682 | unsigned regno; | |
18683 | ||
4d4cbc0e AH |
18684 | if (TARGET_SPE |
18685 | && (SPE_VECTOR_MODE (GET_MODE (reg)) | |
18686 | || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode))) | |
18687 | ; | |
18688 | else | |
96714395 AH |
18689 | return NULL_RTX; |
18690 | ||
18691 | regno = REGNO (reg); | |
18692 | ||
18693 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
18694 | This is a way of distinguishing r0 in 32-bits from r0 in | |
18695 | 64-bits. */ | |
18696 | return | |
18697 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
18698 | BYTES_BIG_ENDIAN |
18699 | ? gen_rtvec (2, | |
18700 | gen_rtx_REG (SImode, regno + 1200), | |
18701 | gen_rtx_REG (SImode, regno)) | |
18702 | : gen_rtvec (2, | |
18703 | gen_rtx_REG (SImode, regno), | |
18704 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
18705 | } |
18706 | ||
93c9d1ba AM |
18707 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
18708 | ||
18709 | unsigned int | |
18710 | rs6000_dbx_register_number (unsigned int regno) | |
18711 | { | |
18712 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
18713 | return regno; | |
18714 | if (regno == MQ_REGNO) | |
18715 | return 100; | |
18716 | if (regno == LINK_REGISTER_REGNUM) | |
18717 | return 108; | |
18718 | if (regno == COUNT_REGISTER_REGNUM) | |
18719 | return 109; | |
18720 | if (CR_REGNO_P (regno)) | |
18721 | return regno - CR0_REGNO + 86; | |
18722 | if (regno == XER_REGNO) | |
18723 | return 101; | |
18724 | if (ALTIVEC_REGNO_P (regno)) | |
18725 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
18726 | if (regno == VRSAVE_REGNO) | |
18727 | return 356; | |
18728 | if (regno == VSCR_REGNO) | |
18729 | return 67; | |
18730 | if (regno == SPE_ACC_REGNO) | |
18731 | return 99; | |
18732 | if (regno == SPEFSCR_REGNO) | |
18733 | return 612; | |
18734 | /* SPE high reg number. We get these values of regno from | |
18735 | rs6000_dwarf_register_span. */ | |
18736 | if (regno >= 1200 && regno < 1232) | |
18737 | return regno; | |
18738 | ||
18739 | abort (); | |
18740 | } | |
18741 | ||
93f90be6 | 18742 | /* target hook eh_return_filter_mode */ |
f676971a | 18743 | static enum machine_mode |
93f90be6 FJ |
18744 | rs6000_eh_return_filter_mode (void) |
18745 | { | |
18746 | return TARGET_32BIT ? SImode : word_mode; | |
18747 | } | |
18748 | ||
f676971a EC |
18749 | /* Target hook for vector_mode_supported_p. */ |
18750 | static bool | |
18751 | rs6000_vector_mode_supported_p (enum machine_mode mode) | |
18752 | { | |
18753 | ||
18754 | if (TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
18755 | return true; | |
18756 | ||
18757 | else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
18758 | return true; | |
18759 | ||
18760 | else | |
18761 | return false; | |
18762 | } | |
18763 | ||
17211ab5 | 18764 | #include "gt-rs6000.h" |