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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d GK |
2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
3 | 2000 Free Software Foundation, Inc. | |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
31 | #include "insn-flags.h" | |
9878760c RK |
32 | #include "insn-attr.h" |
33 | #include "flags.h" | |
34 | #include "recog.h" | |
9878760c | 35 | #include "obstack.h" |
9b30bae2 | 36 | #include "tree.h" |
dfafc897 | 37 | #include "expr.h" |
2a430ec1 | 38 | #include "except.h" |
a7df97e6 | 39 | #include "function.h" |
296b8152 KG |
40 | #include "output.h" |
41 | #include "toplev.h" | |
c8023011 | 42 | #include "ggc.h" |
9ebbca7d GK |
43 | #include "hashtab.h" |
44 | #include "tm_p.h" | |
9b30bae2 | 45 | |
7509c759 MM |
46 | #ifndef TARGET_NO_PROTOTYPE |
47 | #define TARGET_NO_PROTOTYPE 0 | |
48 | #endif | |
49 | ||
5248c961 | 50 | extern int profile_block_flag; |
9878760c RK |
51 | |
52 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
53 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
54 | ||
5248c961 RK |
55 | /* Target cpu type */ |
56 | ||
57 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
58 | struct rs6000_cpu_select rs6000_select[3] = |
59 | { | |
815cdc52 MM |
60 | /* switch name, tune arch */ |
61 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
62 | { (const char *)0, "-mcpu=", 1, 1 }, | |
63 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 64 | }; |
5248c961 | 65 | |
9878760c RK |
66 | /* Set to non-zero by "fix" operation to indicate that itrunc and |
67 | uitrunc must be defined. */ | |
68 | ||
69 | int rs6000_trunc_used; | |
70 | ||
71 | /* Set to non-zero once they have been defined. */ | |
72 | ||
73 | static int trunc_defined; | |
74 | ||
c764f757 RK |
75 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
76 | static int common_mode_defined; | |
c81bebd7 | 77 | |
9878760c RK |
78 | /* Save information from a "cmpxx" operation until the branch or scc is |
79 | emitted. */ | |
9878760c RK |
80 | rtx rs6000_compare_op0, rs6000_compare_op1; |
81 | int rs6000_compare_fp_p; | |
874a0744 | 82 | |
874a0744 MM |
83 | /* Label number of label created for -mrelocatable, to call to so we can |
84 | get the address of the GOT section */ | |
85 | int rs6000_pic_labelno; | |
c81bebd7 | 86 | |
9ebbca7d | 87 | #ifdef USING_SVR4_H |
c81bebd7 | 88 | /* Which abi to adhere to */ |
815cdc52 | 89 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
90 | |
91 | /* Semantics of the small data area */ | |
92 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
93 | ||
94 | /* Which small data model to use */ | |
815cdc52 | 95 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
96 | |
97 | /* Counter for labels which are to be placed in .fixup. */ | |
98 | int fixuplabelno = 0; | |
874a0744 | 99 | #endif |
4697a36c MM |
100 | |
101 | /* Whether a System V.4 varargs area was created. */ | |
102 | int rs6000_sysv_varargs_p; | |
8f75773e | 103 | |
b6c9286a MM |
104 | /* ABI enumeration available for subtarget to use. */ |
105 | enum rs6000_abi rs6000_current_abi; | |
106 | ||
38c1f2d7 | 107 | /* Debug flags */ |
815cdc52 | 108 | const char *rs6000_debug_name; |
38c1f2d7 MM |
109 | int rs6000_debug_stack; /* debug stack applications */ |
110 | int rs6000_debug_arg; /* debug argument handling */ | |
111 | ||
112 | /* Flag to say the TOC is initialized */ | |
113 | int toc_initialized; | |
9ebbca7d | 114 | char toc_label_name[10]; |
38c1f2d7 | 115 | |
9ebbca7d GK |
116 | /* Alias set for saves and restores from the rs6000 stack. */ |
117 | static int rs6000_sr_alias_set; | |
c8023011 | 118 | |
9ebbca7d GK |
119 | static void rs6000_add_gc_roots PARAMS ((void)); |
120 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
121 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
122 | static void validate_condition_mode |
123 | PARAMS ((enum rtx_code, enum machine_mode)); | |
124 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 125 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
126 | static void rs6000_emit_stack_tie PARAMS ((void)); |
127 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
128 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
129 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
130 | static unsigned toc_hash_function PARAMS ((const void *)); | |
131 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 132 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
133 | static void toc_hash_mark_table PARAMS ((void *)); |
134 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
c81bebd7 MM |
135 | \f |
136 | /* Default register names. */ | |
137 | char rs6000_reg_names[][8] = | |
138 | { | |
802a0058 MM |
139 | "0", "1", "2", "3", "4", "5", "6", "7", |
140 | "8", "9", "10", "11", "12", "13", "14", "15", | |
141 | "16", "17", "18", "19", "20", "21", "22", "23", | |
142 | "24", "25", "26", "27", "28", "29", "30", "31", | |
143 | "0", "1", "2", "3", "4", "5", "6", "7", | |
144 | "8", "9", "10", "11", "12", "13", "14", "15", | |
145 | "16", "17", "18", "19", "20", "21", "22", "23", | |
146 | "24", "25", "26", "27", "28", "29", "30", "31", | |
147 | "mq", "lr", "ctr","ap", | |
148 | "0", "1", "2", "3", "4", "5", "6", "7", | |
9ebbca7d | 149 | "xer" |
c81bebd7 MM |
150 | }; |
151 | ||
152 | #ifdef TARGET_REGNAMES | |
153 | static char alt_reg_names[][8] = | |
154 | { | |
802a0058 MM |
155 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
156 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
157 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
158 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
159 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
160 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
161 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
162 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
163 | "mq", "lr", "ctr", "ap", | |
164 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
9ebbca7d | 165 | "xer" |
c81bebd7 MM |
166 | }; |
167 | #endif | |
9878760c | 168 | \f |
daf11973 MM |
169 | #ifndef MASK_STRICT_ALIGN |
170 | #define MASK_STRICT_ALIGN 0 | |
171 | #endif | |
172 | ||
5248c961 RK |
173 | /* Override command line options. Mostly we process the processor |
174 | type and sometimes adjust other TARGET_ options. */ | |
175 | ||
176 | void | |
8e3f41e7 | 177 | rs6000_override_options (default_cpu) |
d330fd93 | 178 | const char *default_cpu; |
5248c961 | 179 | { |
c4d38ccb | 180 | size_t i, j; |
8e3f41e7 | 181 | struct rs6000_cpu_select *ptr; |
5248c961 | 182 | |
85638c0d RK |
183 | /* Simplify the entries below by making a mask for any POWER |
184 | variant and any PowerPC variant. */ | |
185 | ||
938937d8 | 186 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
187 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
188 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
189 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 190 | |
5248c961 RK |
191 | static struct ptt |
192 | { | |
d330fd93 | 193 | const char *name; /* Canonical processor name. */ |
5248c961 RK |
194 | enum processor_type processor; /* Processor type enum value. */ |
195 | int target_enable; /* Target flags to enable. */ | |
196 | int target_disable; /* Target flags to disable. */ | |
197 | } processor_target_table[] | |
cf27b467 MM |
198 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
199 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 200 | {"power", PROCESSOR_POWER, |
938937d8 | 201 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 202 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
203 | {"power2", PROCESSOR_POWER, |
204 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
205 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
206 | {"power3", PROCESSOR_PPC630, |
207 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
208 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
209 | {"powerpc", PROCESSOR_POWERPC, |
210 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 211 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
212 | {"powerpc64", PROCESSOR_POWERPC64, |
213 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
214 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 215 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 216 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
217 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
218 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 219 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
220 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
221 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 222 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
223 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
224 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 225 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
226 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
227 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 228 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 229 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
230 | {"rs64a", PROCESSOR_RS64A, |
231 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
232 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
233 | {"401", PROCESSOR_PPC403, |
234 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
235 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 236 | {"403", PROCESSOR_PPC403, |
daf11973 | 237 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 238 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
cf27b467 MM |
239 | {"505", PROCESSOR_MPCCORE, |
240 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
241 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 242 | {"601", PROCESSOR_PPC601, |
938937d8 | 243 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 244 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 245 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
246 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
247 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 248 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
249 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
250 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
251 | {"603e", PROCESSOR_PPC603, |
252 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
253 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 254 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
255 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
256 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 257 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
258 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
259 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 260 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
261 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
262 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 263 | {"620", PROCESSOR_PPC620, |
68c49ffa | 264 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 265 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
266 | {"630", PROCESSOR_PPC630, |
267 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
268 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
269 | {"740", PROCESSOR_PPC750, |
270 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
271 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
272 | {"750", PROCESSOR_PPC750, | |
273 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
274 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
275 | {"801", PROCESSOR_MPCCORE, |
276 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
277 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
278 | {"821", PROCESSOR_MPCCORE, |
279 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
280 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
281 | {"823", PROCESSOR_MPCCORE, |
282 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
283 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
284 | {"860", PROCESSOR_MPCCORE, |
285 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
286 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 287 | |
c4d38ccb | 288 | size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); |
5248c961 | 289 | |
8a61d227 | 290 | int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */ |
938937d8 | 291 | int string = TARGET_STRING; /* save current -mstring/-mno-string status */ |
8a61d227 | 292 | |
5248c961 RK |
293 | profile_block_flag = 0; |
294 | ||
295 | /* Identify the processor type */ | |
8e3f41e7 | 296 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 297 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 298 | |
b6a1cbae | 299 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 300 | { |
8e3f41e7 MM |
301 | ptr = &rs6000_select[i]; |
302 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 303 | { |
8e3f41e7 MM |
304 | for (j = 0; j < ptt_size; j++) |
305 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
306 | { | |
307 | if (ptr->set_tune_p) | |
308 | rs6000_cpu = processor_target_table[j].processor; | |
309 | ||
310 | if (ptr->set_arch_p) | |
311 | { | |
312 | target_flags |= processor_target_table[j].target_enable; | |
313 | target_flags &= ~processor_target_table[j].target_disable; | |
314 | } | |
315 | break; | |
316 | } | |
317 | ||
4406229e | 318 | if (j == ptt_size) |
8e3f41e7 | 319 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
320 | } |
321 | } | |
8a61d227 | 322 | |
ef792183 MM |
323 | /* If we are optimizing big endian systems for space, use the |
324 | store multiple instructions. */ | |
325 | if (BYTES_BIG_ENDIAN && optimize_size) | |
326 | target_flags |= MASK_MULTIPLE; | |
327 | ||
8a61d227 MM |
328 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
329 | override with the processor default */ | |
330 | if (TARGET_MULTIPLE_SET) | |
331 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 332 | |
938937d8 MM |
333 | /* If -mstring or -mno-string was explicitly used, don't |
334 | override with the processor default */ | |
335 | if (TARGET_STRING_SET) | |
1f5515bf | 336 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 337 | |
bef84347 VM |
338 | /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu |
339 | is a 750, because the hardware doesn't support the instructions used in | |
340 | little endian mode, and causes an alignment trap. The 750 does not cause | |
341 | an alignment trap (except when the target is unaligned). */ | |
342 | ||
bfc79d3b | 343 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
344 | { |
345 | if (TARGET_MULTIPLE) | |
346 | { | |
347 | target_flags &= ~MASK_MULTIPLE; | |
348 | if (TARGET_MULTIPLE_SET) | |
349 | warning ("-mmultiple is not supported on little endian systems"); | |
350 | } | |
351 | ||
352 | if (TARGET_STRING) | |
353 | { | |
354 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
355 | if (TARGET_STRING_SET) |
356 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
357 | } |
358 | } | |
3933e0e1 | 359 | |
a260abc9 DE |
360 | if (flag_pic && (DEFAULT_ABI == ABI_AIX)) |
361 | { | |
362 | warning ("-f%s ignored for AIX (all code is position independent)", | |
363 | (flag_pic > 1) ? "PIC" : "pic"); | |
364 | flag_pic = 0; | |
365 | } | |
366 | ||
9861b0c9 DE |
367 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
368 | && (DEFAULT_ABI == ABI_AIX)) | |
369 | { | |
370 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
371 | flag_function_sections = 0; | |
372 | } | |
373 | ||
374 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
375 | { | |
376 | warning ("-fdata-sections not supported on AIX"); | |
377 | flag_data_sections = 0; | |
378 | } | |
379 | ||
38c1f2d7 MM |
380 | /* Set debug flags */ |
381 | if (rs6000_debug_name) | |
382 | { | |
bfc79d3b | 383 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 384 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 385 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 386 | rs6000_debug_stack = 1; |
bfc79d3b | 387 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
388 | rs6000_debug_arg = 1; |
389 | else | |
390 | error ("Unknown -mdebug-%s switch", rs6000_debug_name); | |
391 | } | |
392 | ||
c81bebd7 MM |
393 | #ifdef TARGET_REGNAMES |
394 | /* If the user desires alternate register names, copy in the alternate names | |
395 | now. */ | |
396 | if (TARGET_REGNAMES) | |
bfc79d3b DE |
397 | bcopy ((char *)alt_reg_names, (char *)rs6000_reg_names, |
398 | sizeof (rs6000_reg_names)); | |
c81bebd7 MM |
399 | #endif |
400 | ||
3933e0e1 MM |
401 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
402 | SUBTARGET_OVERRIDE_OPTIONS; | |
403 | #endif | |
c8023011 MM |
404 | |
405 | /* Register global variables with the garbage collector. */ | |
406 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
407 | |
408 | /* Allocate an alias set for register saves & restores from stack. */ | |
409 | rs6000_sr_alias_set = new_alias_set (); | |
410 | ||
411 | if (TARGET_TOC) | |
412 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
5248c961 | 413 | } |
5accd822 DE |
414 | |
415 | void | |
416 | optimization_options (level, size) | |
e2c953b6 | 417 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
418 | int size ATTRIBUTE_UNUSED; |
419 | { | |
5accd822 | 420 | } |
3cfa4909 MM |
421 | \f |
422 | /* Do anything needed at the start of the asm file. */ | |
423 | ||
424 | void | |
425 | rs6000_file_start (file, default_cpu) | |
426 | FILE *file; | |
d330fd93 | 427 | const char *default_cpu; |
3cfa4909 | 428 | { |
c4d38ccb | 429 | size_t i; |
3cfa4909 | 430 | char buffer[80]; |
d330fd93 | 431 | const char *start = buffer; |
3cfa4909 MM |
432 | struct rs6000_cpu_select *ptr; |
433 | ||
434 | if (flag_verbose_asm) | |
435 | { | |
436 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
437 | rs6000_select[0].string = default_cpu; | |
438 | ||
b6a1cbae | 439 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
440 | { |
441 | ptr = &rs6000_select[i]; | |
442 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
443 | { | |
444 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
445 | start = ""; | |
446 | } | |
447 | } | |
448 | ||
449 | #ifdef USING_SVR4_H | |
450 | switch (rs6000_sdata) | |
451 | { | |
452 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
453 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
454 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
455 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
456 | } | |
457 | ||
458 | if (rs6000_sdata && g_switch_value) | |
459 | { | |
460 | fprintf (file, "%s -G %d", start, g_switch_value); | |
461 | start = ""; | |
462 | } | |
463 | #endif | |
464 | ||
465 | if (*start == '\0') | |
949ea356 | 466 | putc ('\n', file); |
3cfa4909 MM |
467 | } |
468 | } | |
469 | ||
24d304eb RK |
470 | \f |
471 | /* Create a CONST_DOUBLE from a string. */ | |
472 | ||
473 | struct rtx_def * | |
474 | rs6000_float_const (string, mode) | |
d330fd93 | 475 | const char *string; |
24d304eb RK |
476 | enum machine_mode mode; |
477 | { | |
478 | REAL_VALUE_TYPE value = REAL_VALUE_ATOF (string, mode); | |
479 | return immed_real_const_1 (value, mode); | |
480 | } | |
5248c961 | 481 | \f |
9878760c RK |
482 | /* Return non-zero if this function is known to have a null epilogue. */ |
483 | ||
484 | int | |
485 | direct_return () | |
486 | { | |
4697a36c MM |
487 | if (reload_completed) |
488 | { | |
489 | rs6000_stack_t *info = rs6000_stack_info (); | |
490 | ||
491 | if (info->first_gp_reg_save == 32 | |
492 | && info->first_fp_reg_save == 64 | |
c81fc13e DE |
493 | && ! info->lr_save_p |
494 | && ! info->cr_save_p | |
495 | && ! info->push_p) | |
4697a36c MM |
496 | return 1; |
497 | } | |
498 | ||
499 | return 0; | |
9878760c RK |
500 | } |
501 | ||
502 | /* Returns 1 always. */ | |
503 | ||
504 | int | |
505 | any_operand (op, mode) | |
296b8152 KG |
506 | register rtx op ATTRIBUTE_UNUSED; |
507 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
9878760c RK |
508 | { |
509 | return 1; | |
510 | } | |
511 | ||
b6c9286a | 512 | /* Returns 1 if op is the count register */ |
38c1f2d7 MM |
513 | int |
514 | count_register_operand(op, mode) | |
b6c9286a | 515 | register rtx op; |
296b8152 | 516 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
517 | { |
518 | if (GET_CODE (op) != REG) | |
519 | return 0; | |
520 | ||
521 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
522 | return 1; | |
523 | ||
524 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
525 | return 1; | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
38c1f2d7 | 530 | int |
9ebbca7d | 531 | xer_operand(op, mode) |
802a0058 | 532 | register rtx op; |
296b8152 | 533 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
534 | { |
535 | if (GET_CODE (op) != REG) | |
536 | return 0; | |
537 | ||
9ebbca7d | 538 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
539 | return 1; |
540 | ||
802a0058 MM |
541 | return 0; |
542 | } | |
543 | ||
9878760c RK |
544 | /* Return 1 if OP is a constant that can fit in a D field. */ |
545 | ||
546 | int | |
547 | short_cint_operand (op, mode) | |
548 | register rtx op; | |
296b8152 | 549 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 550 | { |
5f59ecb7 DE |
551 | return (GET_CODE (op) == CONST_INT |
552 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
553 | } |
554 | ||
555 | /* Similar for a unsigned D field. */ | |
556 | ||
557 | int | |
558 | u_short_cint_operand (op, mode) | |
559 | register rtx op; | |
296b8152 | 560 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 561 | { |
19684119 | 562 | return (GET_CODE (op) == CONST_INT |
5f59ecb7 | 563 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')); |
9878760c RK |
564 | } |
565 | ||
dcfedcd0 RK |
566 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
567 | ||
568 | int | |
569 | non_short_cint_operand (op, mode) | |
570 | register rtx op; | |
296b8152 | 571 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
572 | { |
573 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 574 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
575 | } |
576 | ||
9878760c RK |
577 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
578 | ctr, or lr). */ | |
579 | ||
580 | int | |
cd2b37d9 | 581 | gpc_reg_operand (op, mode) |
9878760c RK |
582 | register rtx op; |
583 | enum machine_mode mode; | |
584 | { | |
585 | return (register_operand (op, mode) | |
802a0058 | 586 | && (GET_CODE (op) != REG |
9ebbca7d GK |
587 | || (REGNO (op) >= ARG_POINTER_REGNUM |
588 | && !XER_REGNO_P (REGNO (op))) | |
589 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
590 | } |
591 | ||
592 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
593 | CR field. */ | |
594 | ||
595 | int | |
596 | cc_reg_operand (op, mode) | |
597 | register rtx op; | |
598 | enum machine_mode mode; | |
599 | { | |
600 | return (register_operand (op, mode) | |
601 | && (GET_CODE (op) != REG | |
602 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
603 | || CR_REGNO_P (REGNO (op)))); | |
604 | } | |
605 | ||
815cdc52 MM |
606 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
607 | CR field that isn't CR0. */ | |
608 | ||
609 | int | |
610 | cc_reg_not_cr0_operand (op, mode) | |
611 | register rtx op; | |
612 | enum machine_mode mode; | |
613 | { | |
614 | return (register_operand (op, mode) | |
615 | && (GET_CODE (op) != REG | |
616 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
617 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
618 | } | |
619 | ||
9878760c RK |
620 | /* Returns 1 if OP is either a constant integer valid for a D-field or a |
621 | non-special register. If a register, it must be in the proper mode unless | |
622 | MODE is VOIDmode. */ | |
623 | ||
624 | int | |
625 | reg_or_short_operand (op, mode) | |
626 | register rtx op; | |
627 | enum machine_mode mode; | |
628 | { | |
f5a28898 | 629 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
630 | } |
631 | ||
632 | /* Similar, except check if the negation of the constant would be valid for | |
633 | a D-field. */ | |
634 | ||
635 | int | |
636 | reg_or_neg_short_operand (op, mode) | |
637 | register rtx op; | |
638 | enum machine_mode mode; | |
639 | { | |
640 | if (GET_CODE (op) == CONST_INT) | |
641 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
642 | ||
cd2b37d9 | 643 | return gpc_reg_operand (op, mode); |
9878760c RK |
644 | } |
645 | ||
646 | /* Return 1 if the operand is either a register or an integer whose high-order | |
647 | 16 bits are zero. */ | |
648 | ||
649 | int | |
650 | reg_or_u_short_operand (op, mode) | |
651 | register rtx op; | |
652 | enum machine_mode mode; | |
653 | { | |
e675f625 | 654 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
655 | } |
656 | ||
657 | /* Return 1 is the operand is either a non-special register or ANY | |
658 | constant integer. */ | |
659 | ||
660 | int | |
661 | reg_or_cint_operand (op, mode) | |
662 | register rtx op; | |
663 | enum machine_mode mode; | |
664 | { | |
f6bf7de2 DE |
665 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
666 | } | |
667 | ||
668 | /* Return 1 is the operand is either a non-special register or ANY | |
669 | 32-bit signed constant integer. */ | |
670 | ||
671 | int | |
672 | reg_or_arith_cint_operand (op, mode) | |
673 | register rtx op; | |
674 | enum machine_mode mode; | |
675 | { | |
676 | return (gpc_reg_operand (op, mode) | |
677 | || (GET_CODE (op) == CONST_INT | |
678 | #if HOST_BITS_PER_WIDE_INT != 32 | |
679 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) | |
680 | < 0x100000000u) | |
681 | #endif | |
682 | )); | |
9878760c RK |
683 | } |
684 | ||
9ebbca7d GK |
685 | /* Return 1 is the operand is either a non-special register or ANY |
686 | 32-bit unsigned constant integer. */ | |
687 | ||
688 | int | |
1d328b19 | 689 | reg_or_logical_cint_operand (op, mode) |
9ebbca7d GK |
690 | register rtx op; |
691 | enum machine_mode mode; | |
692 | { | |
1d328b19 GK |
693 | if (GET_CODE (op) == CONST_INT) |
694 | { | |
695 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
696 | { | |
697 | if (GET_MODE_BITSIZE (mode) <= 32) | |
698 | abort(); | |
699 | ||
700 | if (INTVAL (op) < 0) | |
701 | return 0; | |
702 | } | |
703 | ||
704 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 705 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
706 | } |
707 | else if (GET_CODE (op) == CONST_DOUBLE) | |
708 | { | |
709 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
710 | || mode != DImode) | |
711 | abort(); | |
712 | ||
713 | return CONST_DOUBLE_HIGH (op) == 0; | |
714 | } | |
715 | else | |
716 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
717 | } |
718 | ||
766a866c MM |
719 | /* Return 1 if the operand is an operand that can be loaded via the GOT */ |
720 | ||
721 | int | |
722 | got_operand (op, mode) | |
723 | register rtx op; | |
296b8152 | 724 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
725 | { |
726 | return (GET_CODE (op) == SYMBOL_REF | |
727 | || GET_CODE (op) == CONST | |
728 | || GET_CODE (op) == LABEL_REF); | |
729 | } | |
730 | ||
38c1f2d7 MM |
731 | /* Return 1 if the operand is a simple references that can be loaded via |
732 | the GOT (labels involving addition aren't allowed). */ | |
733 | ||
734 | int | |
735 | got_no_const_operand (op, mode) | |
736 | register rtx op; | |
296b8152 | 737 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
738 | { |
739 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
740 | } | |
741 | ||
4e74d8ec MM |
742 | /* Return the number of instructions it takes to form a constant in an |
743 | integer register. */ | |
744 | ||
745 | static int | |
746 | num_insns_constant_wide (value) | |
747 | HOST_WIDE_INT value; | |
748 | { | |
749 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 750 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
751 | return 1; |
752 | ||
4e74d8ec | 753 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 754 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
755 | return 1; |
756 | ||
5f59ecb7 | 757 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 758 | else if (TARGET_POWERPC64) |
4e74d8ec | 759 | { |
0858c623 | 760 | unsigned HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
761 | HOST_WIDE_INT high = value >> 32; |
762 | ||
0858c623 | 763 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
764 | return 2; |
765 | ||
0858c623 | 766 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
767 | return 2; |
768 | ||
c81fc13e | 769 | else if (! low) |
4e74d8ec MM |
770 | return num_insns_constant_wide (high) + 1; |
771 | ||
772 | else | |
773 | return (num_insns_constant_wide (high) | |
e396202a | 774 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
775 | } |
776 | #endif | |
777 | ||
778 | else | |
779 | return 2; | |
780 | } | |
781 | ||
782 | int | |
783 | num_insns_constant (op, mode) | |
784 | rtx op; | |
785 | enum machine_mode mode; | |
786 | { | |
4e74d8ec MM |
787 | if (GET_CODE (op) == CONST_INT) |
788 | return num_insns_constant_wide (INTVAL (op)); | |
789 | ||
6fc48950 MM |
790 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
791 | { | |
792 | long l; | |
793 | REAL_VALUE_TYPE rv; | |
794 | ||
795 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
796 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
797 | return num_insns_constant_wide ((HOST_WIDE_INT)l); | |
798 | } | |
799 | ||
47ad8c61 | 800 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 801 | { |
47ad8c61 MM |
802 | HOST_WIDE_INT low; |
803 | HOST_WIDE_INT high; | |
804 | long l[2]; | |
805 | REAL_VALUE_TYPE rv; | |
806 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 807 | |
47ad8c61 MM |
808 | if (mode == VOIDmode || mode == DImode) |
809 | { | |
810 | high = CONST_DOUBLE_HIGH (op); | |
811 | low = CONST_DOUBLE_LOW (op); | |
812 | } | |
813 | else | |
814 | { | |
815 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
816 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
817 | high = l[endian]; | |
818 | low = l[1 - endian]; | |
819 | } | |
4e74d8ec | 820 | |
47ad8c61 MM |
821 | if (TARGET_32BIT) |
822 | return (num_insns_constant_wide (low) | |
823 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
824 | |
825 | else | |
47ad8c61 | 826 | { |
0858c623 | 827 | if (high == 0 && (low & 0x80000000) == 0) |
47ad8c61 MM |
828 | return num_insns_constant_wide (low); |
829 | ||
0858c623 | 830 | else if (high == -1 && (low & 0x80000000) != 0) |
47ad8c61 MM |
831 | return num_insns_constant_wide (low); |
832 | ||
a260abc9 DE |
833 | else if (mask64_operand (op, mode)) |
834 | return 2; | |
835 | ||
47ad8c61 MM |
836 | else if (low == 0) |
837 | return num_insns_constant_wide (high) + 1; | |
838 | ||
839 | else | |
840 | return (num_insns_constant_wide (high) | |
841 | + num_insns_constant_wide (low) + 1); | |
842 | } | |
4e74d8ec MM |
843 | } |
844 | ||
845 | else | |
846 | abort (); | |
847 | } | |
848 | ||
6f2f8311 RK |
849 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register |
850 | with one instruction per word. We only do this if we can safely read | |
851 | CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
852 | |
853 | int | |
854 | easy_fp_constant (op, mode) | |
855 | register rtx op; | |
856 | register enum machine_mode mode; | |
857 | { | |
9878760c RK |
858 | if (GET_CODE (op) != CONST_DOUBLE |
859 | || GET_MODE (op) != mode | |
4e74d8ec | 860 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
861 | return 0; |
862 | ||
b6c9286a | 863 | /* Consider all constants with -msoft-float to be easy */ |
4e74d8ec | 864 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
865 | return 1; |
866 | ||
a7273471 MM |
867 | /* If we are using V.4 style PIC, consider all constants to be hard */ |
868 | if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) | |
869 | return 0; | |
870 | ||
5ae4759c MM |
871 | #ifdef TARGET_RELOCATABLE |
872 | /* Similarly if we are using -mrelocatable, consider all constants to be hard */ | |
873 | if (TARGET_RELOCATABLE) | |
874 | return 0; | |
875 | #endif | |
876 | ||
042259f2 DE |
877 | if (mode == DFmode) |
878 | { | |
879 | long k[2]; | |
880 | REAL_VALUE_TYPE rv; | |
881 | ||
882 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
883 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 884 | |
4e74d8ec MM |
885 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
886 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 887 | } |
4e74d8ec MM |
888 | |
889 | else if (mode == SFmode) | |
042259f2 DE |
890 | { |
891 | long l; | |
892 | REAL_VALUE_TYPE rv; | |
893 | ||
894 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
895 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 896 | |
4e74d8ec | 897 | return num_insns_constant_wide (l) == 1; |
042259f2 | 898 | } |
4e74d8ec | 899 | |
a260abc9 | 900 | else if (mode == DImode) |
c81fc13e | 901 | return ((TARGET_POWERPC64 |
a260abc9 DE |
902 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
903 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 904 | |
a9098fd0 GK |
905 | else if (mode == SImode) |
906 | return 1; | |
4e74d8ec MM |
907 | else |
908 | abort (); | |
9878760c | 909 | } |
8f75773e | 910 | |
b6c9286a MM |
911 | /* Return 1 if the operand is in volatile memory. Note that during the |
912 | RTL generation phase, memory_operand does not return TRUE for | |
913 | volatile memory references. So this function allows us to | |
914 | recognize volatile references where its safe. */ | |
915 | ||
916 | int | |
917 | volatile_mem_operand (op, mode) | |
918 | register rtx op; | |
919 | enum machine_mode mode; | |
920 | { | |
921 | if (GET_CODE (op) != MEM) | |
922 | return 0; | |
923 | ||
924 | if (!MEM_VOLATILE_P (op)) | |
925 | return 0; | |
926 | ||
927 | if (mode != GET_MODE (op)) | |
928 | return 0; | |
929 | ||
930 | if (reload_completed) | |
931 | return memory_operand (op, mode); | |
932 | ||
933 | if (reload_in_progress) | |
934 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
935 | ||
936 | return memory_address_p (mode, XEXP (op, 0)); | |
937 | } | |
938 | ||
97f6e72f | 939 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
940 | |
941 | int | |
97f6e72f | 942 | offsettable_mem_operand (op, mode) |
914c2e77 RK |
943 | register rtx op; |
944 | enum machine_mode mode; | |
945 | { | |
97f6e72f | 946 | return ((GET_CODE (op) == MEM) |
677a9668 | 947 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 948 | mode, XEXP (op, 0))); |
914c2e77 RK |
949 | } |
950 | ||
9878760c RK |
951 | /* Return 1 if the operand is either an easy FP constant (see above) or |
952 | memory. */ | |
953 | ||
954 | int | |
955 | mem_or_easy_const_operand (op, mode) | |
956 | register rtx op; | |
957 | enum machine_mode mode; | |
958 | { | |
959 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
960 | } | |
961 | ||
962 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 963 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
964 | |
965 | int | |
966 | add_operand (op, mode) | |
967 | register rtx op; | |
968 | enum machine_mode mode; | |
969 | { | |
970 | return (reg_or_short_operand (op, mode) | |
19684119 | 971 | || (GET_CODE (op) == CONST_INT |
5f59ecb7 | 972 | && CONST_OK_FOR_LETTER_P (INTVAL(op), 'L'))); |
9878760c RK |
973 | } |
974 | ||
dcfedcd0 RK |
975 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
976 | ||
977 | int | |
978 | non_add_cint_operand (op, mode) | |
979 | register rtx op; | |
296b8152 | 980 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
981 | { |
982 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 983 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000 |
5f59ecb7 | 984 | && ! CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')); |
dcfedcd0 RK |
985 | } |
986 | ||
9878760c RK |
987 | /* Return 1 if the operand is a non-special register or a constant that |
988 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
989 | ||
990 | int | |
991 | logical_operand (op, mode) | |
992 | register rtx op; | |
993 | enum machine_mode mode; | |
994 | { | |
1d328b19 GK |
995 | /* an unsigned representation of 'op'. */ |
996 | unsigned HOST_WIDE_INT opl, oph; | |
997 | ||
dfbdccdb GK |
998 | if (gpc_reg_operand (op, mode)) |
999 | return 1; | |
1d328b19 | 1000 | |
dfbdccdb GK |
1001 | if (GET_CODE (op) == CONST_INT) |
1002 | { | |
1d328b19 GK |
1003 | opl = INTVAL (op) & GET_MODE_MASK (mode); |
1004 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1005 | oph = 0; | |
1006 | else | |
1007 | oph = INTVAL (op) >> (HOST_BITS_PER_WIDE_INT - 1); | |
dfbdccdb GK |
1008 | } |
1009 | else if (GET_CODE (op) == CONST_DOUBLE) | |
1010 | { | |
1d328b19 GK |
1011 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
1012 | abort(); | |
1013 | ||
1014 | opl = CONST_DOUBLE_LOW (op); | |
1015 | oph = CONST_DOUBLE_HIGH (op); | |
dfbdccdb GK |
1016 | } |
1017 | else | |
1018 | return 0; | |
1d328b19 GK |
1019 | |
1020 | return (oph == 0 | |
1021 | && ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 | |
0858c623 | 1022 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0)); |
9878760c RK |
1023 | } |
1024 | ||
dcfedcd0 | 1025 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1026 | above), but could be split into one. */ |
dcfedcd0 RK |
1027 | |
1028 | int | |
1029 | non_logical_cint_operand (op, mode) | |
1030 | register rtx op; | |
5f59ecb7 | 1031 | enum machine_mode mode; |
dcfedcd0 | 1032 | { |
dfbdccdb | 1033 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1034 | && ! logical_operand (op, mode) |
1035 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1036 | } |
1037 | ||
19ba8161 | 1038 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1039 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1040 | Reject all ones and all zeros, since these should have been optimized | |
1041 | away and confuse the making of MB and ME. */ | |
1042 | ||
1043 | int | |
19ba8161 DE |
1044 | mask_operand (op, mode) |
1045 | register rtx op; | |
1046 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
9878760c | 1047 | { |
19ba8161 | 1048 | HOST_WIDE_INT c; |
9878760c RK |
1049 | int i; |
1050 | int last_bit_value; | |
1051 | int transitions = 0; | |
1052 | ||
19ba8161 DE |
1053 | if (GET_CODE (op) != CONST_INT) |
1054 | return 0; | |
1055 | ||
1056 | c = INTVAL (op); | |
1057 | ||
9878760c RK |
1058 | if (c == 0 || c == ~0) |
1059 | return 0; | |
1060 | ||
1061 | last_bit_value = c & 1; | |
1062 | ||
1063 | for (i = 1; i < 32; i++) | |
1064 | if (((c >>= 1) & 1) != last_bit_value) | |
1065 | last_bit_value ^= 1, transitions++; | |
1066 | ||
1067 | return transitions <= 2; | |
1068 | } | |
1069 | ||
a260abc9 DE |
1070 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1071 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1072 | Reject all ones and all zeros, since these should have been optimized | |
1073 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1074 | |
1075 | int | |
a260abc9 DE |
1076 | mask64_operand (op, mode) |
1077 | register rtx op; | |
1078 | enum machine_mode mode; | |
1079 | { | |
1080 | if (GET_CODE (op) == CONST_INT) | |
1081 | { | |
1082 | HOST_WIDE_INT c = INTVAL (op); | |
1083 | int i; | |
1084 | int last_bit_value; | |
1085 | int transitions = 0; | |
1086 | ||
1087 | if (c == 0 || c == ~0) | |
1088 | return 0; | |
1089 | ||
1090 | last_bit_value = c & 1; | |
1091 | ||
1092 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1093 | if (((c >>= 1) & 1) != last_bit_value) | |
1094 | last_bit_value ^= 1, transitions++; | |
1095 | ||
e2c953b6 DE |
1096 | return transitions <= 1; |
1097 | } | |
1098 | else if (GET_CODE (op) == CONST_DOUBLE | |
1099 | && (mode == VOIDmode || mode == DImode)) | |
1100 | { | |
1101 | HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); | |
1102 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1103 | HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); | |
1104 | #endif | |
1105 | int i; | |
1106 | int last_bit_value; | |
1107 | int transitions = 0; | |
1108 | ||
1109 | if ((low == 0 | |
1110 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1111 | && high == 0 | |
1112 | #endif | |
1113 | ) | |
1114 | || (low == ~0 | |
1115 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1116 | && high == ~0 | |
1117 | #endif | |
1118 | )) | |
1119 | return 0; | |
1120 | ||
1121 | last_bit_value = low & 1; | |
1122 | ||
1123 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1124 | if (((low >>= 1) & 1) != last_bit_value) | |
1125 | last_bit_value ^= 1, transitions++; | |
1126 | ||
a238cd8b | 1127 | #if HOST_BITS_PER_WIDE_INT == 32 |
e2c953b6 DE |
1128 | if ((high & 1) != last_bit_value) |
1129 | last_bit_value ^= 1, transitions++; | |
1130 | ||
1131 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1132 | if (((high >>= 1) & 1) != last_bit_value) | |
1133 | last_bit_value ^= 1, transitions++; | |
a260abc9 DE |
1134 | #endif |
1135 | ||
1136 | return transitions <= 1; | |
1137 | } | |
e2c953b6 DE |
1138 | else |
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. | |
1143 | It is if there are no more than two 1->0 or 0->1 transitions. | |
1144 | Reject all ones and all zeros, since these should have been optimized | |
1145 | away and confuse the making of MB and ME. */ | |
1146 | ||
1147 | int | |
1148 | rldic_operand (op, mode) | |
1149 | register rtx op; | |
1150 | enum machine_mode mode; | |
1151 | { | |
1152 | if (GET_CODE (op) == CONST_INT) | |
1153 | { | |
1154 | HOST_WIDE_INT c = INTVAL (op); | |
1155 | int i; | |
1156 | int last_bit_value; | |
1157 | int transitions = 0; | |
1158 | ||
1159 | if (c == 0 || c == ~0) | |
1160 | return 0; | |
1161 | ||
1162 | last_bit_value = c & 1; | |
1163 | ||
1164 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1165 | if (((c >>= 1) & 1) != last_bit_value) | |
1166 | last_bit_value ^= 1, transitions++; | |
1167 | ||
1168 | return transitions <= 2; | |
1169 | } | |
a260abc9 DE |
1170 | else if (GET_CODE (op) == CONST_DOUBLE |
1171 | && (mode == VOIDmode || mode == DImode)) | |
1172 | { | |
1173 | HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); | |
a238cd8b | 1174 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1175 | HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); |
1176 | #endif | |
1177 | int i; | |
1178 | int last_bit_value; | |
1179 | int transitions = 0; | |
1180 | ||
1181 | if ((low == 0 | |
a238cd8b | 1182 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1183 | && high == 0 |
1184 | #endif | |
1185 | ) | |
1186 | || (low == ~0 | |
a238cd8b | 1187 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1188 | && high == ~0 |
1189 | #endif | |
1190 | )) | |
1191 | return 0; | |
1192 | ||
1193 | last_bit_value = low & 1; | |
1194 | ||
1195 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1196 | if (((low >>= 1) & 1) != last_bit_value) | |
1197 | last_bit_value ^= 1, transitions++; | |
1198 | ||
a238cd8b | 1199 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1200 | if ((high & 1) != last_bit_value) |
1201 | last_bit_value ^= 1, transitions++; | |
1202 | ||
1203 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1204 | if (((high >>= 1) & 1) != last_bit_value) | |
1205 | last_bit_value ^= 1, transitions++; | |
1206 | #endif | |
1207 | ||
e2c953b6 | 1208 | return transitions <= 2; |
a260abc9 DE |
1209 | } |
1210 | else | |
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | /* Return 1 if the operand is either a non-special register or a constant | |
1215 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1216 | ||
1217 | int | |
1218 | and64_operand (op, mode) | |
9878760c RK |
1219 | register rtx op; |
1220 | enum machine_mode mode; | |
1221 | { | |
9ebbca7d | 1222 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1223 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1224 | ||
1225 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1226 | } |
1227 | ||
a260abc9 DE |
1228 | /* Return 1 if the operand is either a non-special register or a |
1229 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1230 | |
1231 | int | |
a260abc9 DE |
1232 | and_operand (op, mode) |
1233 | register rtx op; | |
1234 | enum machine_mode mode; | |
dcfedcd0 | 1235 | { |
9ebbca7d | 1236 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1237 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1238 | ||
1239 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1240 | } |
1241 | ||
9878760c RK |
1242 | /* Return 1 if the operand is a general register or memory operand. */ |
1243 | ||
1244 | int | |
1245 | reg_or_mem_operand (op, mode) | |
1246 | register rtx op; | |
1247 | register enum machine_mode mode; | |
1248 | { | |
b6c9286a MM |
1249 | return (gpc_reg_operand (op, mode) |
1250 | || memory_operand (op, mode) | |
1251 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1252 | } |
1253 | ||
a7a813f7 | 1254 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1255 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1256 | instruction. */ |
1257 | ||
1258 | int | |
1259 | lwa_operand (op, mode) | |
1260 | register rtx op; | |
1261 | register enum machine_mode mode; | |
1262 | { | |
1263 | rtx inner = op; | |
1264 | ||
1265 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1266 | inner = SUBREG_REG (inner); | |
1267 | ||
1268 | return gpc_reg_operand (inner, mode) | |
1269 | || (memory_operand (inner, mode) | |
1270 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
1271 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC); | |
1272 | } | |
1273 | ||
9878760c RK |
1274 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1275 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1276 | forced to lr. */ | |
1277 | ||
1278 | int | |
1279 | call_operand (op, mode) | |
1280 | register rtx op; | |
1281 | enum machine_mode mode; | |
1282 | { | |
1283 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1284 | return 0; | |
1285 | ||
1286 | return (GET_CODE (op) == SYMBOL_REF | |
1287 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1288 | } | |
1289 | ||
2af3d377 RK |
1290 | |
1291 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
8f1b829e | 1292 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1293 | |
1294 | int | |
1295 | current_file_function_operand (op, mode) | |
1296 | register rtx op; | |
296b8152 | 1297 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1298 | { |
1299 | return (GET_CODE (op) == SYMBOL_REF | |
1300 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1301 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1302 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1303 | } |
1304 | ||
1305 | ||
9878760c RK |
1306 | /* Return 1 if this operand is a valid input for a move insn. */ |
1307 | ||
1308 | int | |
1309 | input_operand (op, mode) | |
1310 | register rtx op; | |
1311 | enum machine_mode mode; | |
1312 | { | |
eb4e8003 | 1313 | /* Memory is always valid. */ |
9878760c RK |
1314 | if (memory_operand (op, mode)) |
1315 | return 1; | |
1316 | ||
34792e82 | 1317 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1318 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1319 | return 1; |
1320 | ||
eb4e8003 RK |
1321 | /* For floating-point, easy constants are valid. */ |
1322 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1323 | && CONSTANT_P (op) | |
1324 | && easy_fp_constant (op, mode)) | |
1325 | return 1; | |
1326 | ||
4e74d8ec MM |
1327 | /* Allow any integer constant. */ |
1328 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1329 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1330 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1331 | return 1; |
1332 | ||
eb4e8003 RK |
1333 | /* For floating-point or multi-word mode, the only remaining valid type |
1334 | is a register. */ | |
9878760c RK |
1335 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1336 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1337 | return register_operand (op, mode); |
9878760c | 1338 | |
88fe15a1 RK |
1339 | /* The only cases left are integral modes one word or smaller (we |
1340 | do not get called for MODE_CC values). These can be in any | |
1341 | register. */ | |
1342 | if (register_operand (op, mode)) | |
a8b3aeda | 1343 | return 1; |
88fe15a1 | 1344 | |
84cf9dda | 1345 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1346 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1347 | return 1; |
1348 | ||
9ebbca7d GK |
1349 | /* A constant pool expression (relative to the TOC) is valid */ |
1350 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1351 | return 1; |
1352 | ||
88228c4b MM |
1353 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1354 | to be valid. */ | |
c81bebd7 | 1355 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b MM |
1356 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1357 | && small_data_operand (op, Pmode)) | |
1358 | return 1; | |
1359 | ||
042259f2 | 1360 | return 0; |
9878760c | 1361 | } |
7509c759 MM |
1362 | |
1363 | /* Return 1 for an operand in small memory on V.4/eabi */ | |
1364 | ||
1365 | int | |
1366 | small_data_operand (op, mode) | |
296b8152 KG |
1367 | rtx op ATTRIBUTE_UNUSED; |
1368 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1369 | { |
38c1f2d7 | 1370 | #if TARGET_ELF |
5f59ecb7 | 1371 | rtx sym_ref; |
7509c759 | 1372 | |
d9407988 | 1373 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1374 | return 0; |
a54d04b7 | 1375 | |
5b9d9a0c | 1376 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
7509c759 MM |
1377 | return 0; |
1378 | ||
88228c4b MM |
1379 | if (GET_CODE (op) == SYMBOL_REF) |
1380 | sym_ref = op; | |
1381 | ||
1382 | else if (GET_CODE (op) != CONST | |
1383 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1384 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1385 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1386 | return 0; |
1387 | ||
88228c4b | 1388 | else |
dbf55e53 MM |
1389 | { |
1390 | rtx sum = XEXP (op, 0); | |
1391 | HOST_WIDE_INT summand; | |
1392 | ||
1393 | /* We have to be careful here, because it is the referenced address | |
1394 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1395 | summand = INTVAL (XEXP (sum, 1)); | |
1396 | if (summand < 0 || summand > g_switch_value) | |
1397 | return 0; | |
1398 | ||
1399 | sym_ref = XEXP (sum, 0); | |
1400 | } | |
88228c4b MM |
1401 | |
1402 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1403 | return 0; |
1404 | ||
1405 | return 1; | |
d9407988 MM |
1406 | |
1407 | #else | |
1408 | return 0; | |
1409 | #endif | |
7509c759 | 1410 | } |
9ebbca7d GK |
1411 | \f |
1412 | static int | |
1413 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1414 | rtx op; | |
1415 | int *have_sym; | |
1416 | int *have_toc; | |
1417 | { | |
1418 | switch (GET_CODE(op)) | |
1419 | { | |
1420 | case SYMBOL_REF: | |
1421 | if (CONSTANT_POOL_ADDRESS_P (op)) | |
1422 | { | |
a9098fd0 | 1423 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) |
9ebbca7d GK |
1424 | { |
1425 | *have_sym = 1; | |
1426 | return 1; | |
1427 | } | |
1428 | else | |
1429 | return 0; | |
1430 | } | |
1431 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1432 | { | |
1433 | *have_toc = 1; | |
1434 | return 1; | |
1435 | } | |
1436 | else | |
1437 | return 0; | |
1438 | case PLUS: | |
1439 | case MINUS: | |
1440 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) && | |
1441 | constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc); | |
1442 | case CONST: | |
1443 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); | |
1444 | case CONST_INT: | |
1445 | return 1; | |
1446 | default: | |
1447 | return 0; | |
1448 | } | |
1449 | } | |
1450 | ||
1451 | int | |
1452 | constant_pool_expr_p (op) | |
1453 | rtx op; | |
1454 | { | |
1455 | int have_sym = 0; | |
1456 | int have_toc = 0; | |
1457 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1458 | } | |
1459 | ||
1460 | int | |
1461 | toc_relative_expr_p (op) | |
1462 | rtx op; | |
1463 | { | |
1464 | int have_sym = 0; | |
1465 | int have_toc = 0; | |
1466 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1467 | } | |
1468 | ||
1469 | /* Try machine-dependent ways of modifying an illegitimate address | |
1470 | to be legitimate. If we find one, return the new, valid address. | |
1471 | This is used from only one place: `memory_address' in explow.c. | |
1472 | ||
1473 | OLDX is the address as it was before break_out_memory_refs was called. | |
1474 | In some cases it is useful to look at this to decide what needs to be done. | |
1475 | ||
1476 | MODE is passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. | |
1477 | ||
1478 | It is always safe for this macro to do nothing. It exists to recognize | |
1479 | opportunities to optimize the output. | |
1480 | ||
1481 | On RS/6000, first check for the sum of a register with a constant | |
1482 | integer that is out of range. If so, generate code to add the | |
1483 | constant with the low-order 16 bits masked to the register and force | |
1484 | this result into another register (this can be done with `cau'). | |
1485 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1486 | possibility of bit 16 being a one. | |
1487 | ||
1488 | Then check for the sum of a register and something not constant, try to | |
1489 | load the other things into a register and return the sum. */ | |
1490 | rtx | |
1491 | rs6000_legitimize_address (x, oldx, mode) | |
1492 | rtx x; | |
1493 | rtx oldx ATTRIBUTE_UNUSED; | |
1494 | enum machine_mode mode; | |
1495 | { | |
1496 | if (GET_CODE (x) == PLUS | |
1497 | && GET_CODE (XEXP (x, 0)) == REG | |
1498 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1499 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1500 | { | |
1501 | HOST_WIDE_INT high_int, low_int; | |
1502 | rtx sum; | |
1503 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1504 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1505 | if (low_int & 0x8000) | |
1506 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1507 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1508 | GEN_INT (high_int)), 0); | |
1509 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1510 | } | |
1511 | else if (GET_CODE (x) == PLUS | |
1512 | && GET_CODE (XEXP (x, 0)) == REG | |
1513 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
1514 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1515 | && (TARGET_POWERPC64 || mode != DImode) | |
1516 | && mode != TImode) | |
1517 | { | |
1518 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1519 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1520 | } | |
1521 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic | |
1522 | && GET_CODE (x) != CONST_INT | |
1523 | && GET_CODE (x) != CONST_DOUBLE | |
1524 | && CONSTANT_P (x) | |
1525 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1526 | && mode != DImode | |
1527 | && mode != TImode) | |
1528 | { | |
1529 | rtx reg = gen_reg_rtx (Pmode); | |
1530 | emit_insn (gen_elf_high (reg, (x))); | |
1531 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1532 | } | |
1533 | else if (TARGET_TOC | |
1534 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1535 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1536 | { |
1537 | return create_TOC_reference (x); | |
1538 | } | |
1539 | else | |
1540 | return NULL_RTX; | |
1541 | } | |
fb4d4348 GK |
1542 | \f |
1543 | /* Emit a move from SOURCE to DEST in mode MODE. */ | |
1544 | void | |
1545 | rs6000_emit_move (dest, source, mode) | |
1546 | rtx dest; | |
1547 | rtx source; | |
1548 | enum machine_mode mode; | |
1549 | { | |
1550 | rtx operands[2]; | |
1551 | operands[0] = dest; | |
1552 | operands[1] = source; | |
1553 | ||
1554 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
1555 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1556 | && ! FLOAT_MODE_P (mode) | |
1557 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1558 | { | |
1559 | /* FIXME. This should never happen. */ | |
1560 | /* Since it seems that it does, do the safe thing and convert | |
1561 | to a CONST_INT. */ | |
1562 | operands[1] = | |
1563 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
1564 | } | |
1565 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1566 | && ! FLOAT_MODE_P (mode) | |
1567 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
1568 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
1569 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
1570 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
1571 | abort (); | |
1572 | ||
1573 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
1574 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 1575 | |
ffc14f31 GK |
1576 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
1577 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 1578 | { |
ffc14f31 GK |
1579 | int regnum; |
1580 | ||
1581 | if (reload_in_progress || reload_completed) | |
1582 | regnum = true_regnum (operands[1]); | |
1583 | else if (GET_CODE (operands[1]) == REG) | |
1584 | regnum = REGNO (operands[1]); | |
1585 | else | |
1586 | regnum = -1; | |
fb4d4348 GK |
1587 | |
1588 | /* If operands[1] is a register, on POWER it may have | |
1589 | double-precision data in it, so truncate it to single | |
1590 | precision. */ | |
1591 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
1592 | { | |
1593 | rtx newreg; | |
1594 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
1595 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
1596 | operands[1] = newreg; | |
1597 | } | |
1598 | } | |
1599 | ||
a9098fd0 GK |
1600 | /* Handle the case where reload calls us with an invalid address; |
1601 | and the case of CONSTANT_P_RTX. */ | |
1602 | if (! general_operand (operands[1], mode) | |
1603 | || ! nonimmediate_operand (operands[0], mode) | |
1604 | || GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
fb4d4348 GK |
1605 | { |
1606 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1607 | return; | |
1608 | } | |
a9098fd0 | 1609 | |
fb4d4348 GK |
1610 | /* FIXME: In the long term, this switch statement should go away |
1611 | and be replaced by a sequence of tests based on things like | |
1612 | mode == Pmode. */ | |
1613 | switch (mode) | |
1614 | { | |
1615 | case HImode: | |
1616 | case QImode: | |
1617 | if (CONSTANT_P (operands[1]) | |
1618 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 1619 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1620 | break; |
1621 | ||
1622 | case DFmode: | |
1623 | case SFmode: | |
1624 | if (CONSTANT_P (operands[1]) | |
1625 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 1626 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1627 | break; |
1628 | ||
1629 | case SImode: | |
a9098fd0 | 1630 | case DImode: |
fb4d4348 GK |
1631 | /* Use default pattern for address of ELF small data */ |
1632 | if (TARGET_ELF | |
a9098fd0 | 1633 | && mode == Pmode |
fb4d4348 | 1634 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
a9098fd0 GK |
1635 | && (GET_CODE (operands[1]) == SYMBOL_REF |
1636 | || GET_CODE (operands[1]) == CONST) | |
1637 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
1638 | { |
1639 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1640 | return; | |
1641 | } | |
1642 | ||
1643 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
a9098fd0 GK |
1644 | && mode == Pmode && mode == SImode |
1645 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
1646 | { |
1647 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
1648 | return; | |
1649 | } | |
1650 | ||
a9098fd0 GK |
1651 | if (TARGET_ELF && TARGET_NO_TOC && ! flag_pic |
1652 | && mode == Pmode | |
fb4d4348 GK |
1653 | && CONSTANT_P (operands[1]) |
1654 | && GET_CODE (operands[1]) != HIGH | |
1655 | && GET_CODE (operands[1]) != CONST_INT) | |
1656 | { | |
a9098fd0 | 1657 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
1658 | |
1659 | /* If this is a function address on -mcall-aixdesc, | |
1660 | convert it to the address of the descriptor. */ | |
1661 | if (DEFAULT_ABI == ABI_AIX | |
1662 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1663 | && XSTR (operands[1], 0)[0] == '.') | |
1664 | { | |
1665 | const char *name = XSTR (operands[1], 0); | |
1666 | rtx new_ref; | |
1667 | while (*name == '.') | |
1668 | name++; | |
1669 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
1670 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
1671 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
1672 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
1673 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
1674 | operands[1] = new_ref; | |
1675 | } | |
7509c759 | 1676 | |
fb4d4348 GK |
1677 | emit_insn (gen_elf_high (target, operands[1])); |
1678 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
1679 | return; | |
1680 | } | |
1681 | ||
a9098fd0 GK |
1682 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
1683 | and we have put it in the TOC, we just need to make a TOC-relative | |
1684 | reference to it. */ | |
1685 | if (TARGET_TOC | |
1686 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1687 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
1688 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
1689 | get_pool_mode (operands[1]))) | |
fb4d4348 | 1690 | { |
a9098fd0 | 1691 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 1692 | } |
a9098fd0 GK |
1693 | else if (mode == Pmode |
1694 | && CONSTANT_P (operands[1]) | |
1695 | && (((HOST_BITS_PER_WIDE_INT != 32 | |
1696 | || GET_CODE (operands[1]) != CONST_INT) | |
1697 | && ! easy_fp_constant (operands[1], mode)) | |
1698 | || (GET_CODE (operands[0]) == REG | |
1699 | && FP_REGNO_P (REGNO (operands[0])))) | |
1700 | && GET_CODE (operands[1]) != HIGH | |
1701 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1702 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 | 1703 | { |
a9098fd0 GK |
1704 | int special_constant_p = 0; |
1705 | ||
fb4d4348 GK |
1706 | /* Emit a USE operation so that the constant isn't deleted if |
1707 | expensive optimizations are turned on because nobody | |
1708 | references it. This should only be done for operands that | |
1709 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
1710 | This should not be done for operands that contain LABEL_REFs. | |
1711 | For now, we just handle the obvious case. */ | |
1712 | if (GET_CODE (operands[1]) != LABEL_REF) | |
1713 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
1714 | ||
1715 | /* If we are to limit the number of things we put in the TOC and | |
1716 | this is a symbol plus a constant we can add in one insn, | |
1717 | just put the symbol in the TOC and add the constant. Don't do | |
1718 | this if reload is in progress. */ | |
1719 | if (GET_CODE (operands[1]) == CONST | |
1720 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
1721 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 1722 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
1723 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
1724 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
1725 | && ! side_effects_p (operands[0])) | |
1726 | { | |
a9098fd0 | 1727 | rtx sym = force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); |
fb4d4348 GK |
1728 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
1729 | ||
a9098fd0 GK |
1730 | sym = force_reg (mode, sym); |
1731 | if (mode == SImode) | |
1732 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
1733 | else | |
1734 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
1735 | return; |
1736 | } | |
1737 | ||
a9098fd0 | 1738 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1739 | |
1740 | if (TARGET_TOC | |
a9098fd0 | 1741 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0))) |
fb4d4348 | 1742 | { |
a9098fd0 GK |
1743 | rtx constant; |
1744 | enum machine_mode cmode; | |
fb4d4348 | 1745 | |
a9098fd0 GK |
1746 | constant = get_pool_constant (XEXP (operands[1], 0)); |
1747 | cmode = get_pool_mode (XEXP (operands[1], 0)); | |
1748 | special_constant_p = | |
1749 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (constant, cmode); | |
1750 | } | |
1751 | ||
1752 | if (special_constant_p) | |
1753 | { | |
1754 | operands[1] = gen_rtx_MEM (mode, | |
1755 | create_TOC_reference (XEXP (operands[1], 0))); | |
fb4d4348 GK |
1756 | MEM_ALIAS_SET (operands[1]) = get_TOC_alias_set (); |
1757 | RTX_UNCHANGING_P (operands[1]) = 1; | |
a9098fd0 | 1758 | } |
fb4d4348 GK |
1759 | } |
1760 | break; | |
a9098fd0 | 1761 | |
fb4d4348 GK |
1762 | case TImode: |
1763 | if (GET_CODE (operands[0]) == MEM | |
1764 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
1765 | && ! reload_in_progress) | |
1766 | operands[0] = change_address (operands[0], TImode, | |
1767 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
1768 | ||
1769 | if (GET_CODE (operands[1]) == MEM | |
1770 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
1771 | && ! reload_in_progress) | |
1772 | operands[1] = change_address (operands[1], TImode, | |
1773 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
1774 | break; | |
1775 | ||
1776 | default: | |
1777 | abort (); | |
1778 | } | |
1779 | ||
a9098fd0 GK |
1780 | /* Above, we may have called force_const_mem which may have returned |
1781 | an invalid address. If we can, fix this up; otherwise, reload will | |
1782 | have to deal with it. */ | |
1783 | if (GET_CODE (operands[1]) == MEM | |
1784 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
1785 | && ! reload_in_progress) | |
1786 | operands[1] = change_address (operands[1], mode, | |
1787 | XEXP (operands[1], 0)); | |
1788 | ||
fb4d4348 GK |
1789 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
1790 | } | |
4697a36c MM |
1791 | \f |
1792 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1793 | for a call to a function whose data type is FNTYPE. | |
1794 | For a library call, FNTYPE is 0. | |
1795 | ||
1796 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 1797 | so we never return a PARALLEL. */ |
4697a36c MM |
1798 | |
1799 | void | |
1800 | init_cumulative_args (cum, fntype, libname, incoming) | |
1801 | CUMULATIVE_ARGS *cum; | |
1802 | tree fntype; | |
296b8152 | 1803 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
1804 | int incoming; |
1805 | { | |
1806 | static CUMULATIVE_ARGS zero_cumulative; | |
1807 | ||
1808 | *cum = zero_cumulative; | |
1809 | cum->words = 0; | |
1810 | cum->fregno = FP_ARG_MIN_REG; | |
1811 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); | |
7509c759 | 1812 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 1813 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
1814 | |
1815 | if (incoming) | |
bd227acc | 1816 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
1817 | |
1818 | else if (cum->prototype) | |
1819 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
1820 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
1821 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
1822 | ||
1823 | else | |
1824 | cum->nargs_prototype = 0; | |
1825 | ||
1826 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 1827 | |
9ebbca7d GK |
1828 | /* Check for longcall's */ |
1829 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
1830 | cum->call_cookie = CALL_LONG; |
1831 | ||
4697a36c MM |
1832 | if (TARGET_DEBUG_ARG) |
1833 | { | |
1834 | fprintf (stderr, "\ninit_cumulative_args:"); | |
1835 | if (fntype) | |
1836 | { | |
1837 | tree ret_type = TREE_TYPE (fntype); | |
1838 | fprintf (stderr, " ret code = %s,", | |
1839 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
1840 | } | |
1841 | ||
6a4cee5f MM |
1842 | if (cum->call_cookie & CALL_LONG) |
1843 | fprintf (stderr, " longcall,"); | |
1844 | ||
4697a36c MM |
1845 | fprintf (stderr, " proto = %d, nargs = %d\n", |
1846 | cum->prototype, cum->nargs_prototype); | |
1847 | } | |
1848 | } | |
1849 | \f | |
c229cba9 DE |
1850 | /* If defined, a C expression which determines whether, and in which |
1851 | direction, to pad out an argument with extra space. The value | |
1852 | should be of type `enum direction': either `upward' to pad above | |
1853 | the argument, `downward' to pad below, or `none' to inhibit | |
1854 | padding. | |
1855 | ||
1856 | For the AIX ABI structs are always stored left shifted in their | |
1857 | argument slot. */ | |
1858 | ||
9ebbca7d | 1859 | enum direction |
c229cba9 DE |
1860 | function_arg_padding (mode, type) |
1861 | enum machine_mode mode; | |
1862 | tree type; | |
1863 | { | |
c85f7c16 | 1864 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 1865 | return upward; |
c229cba9 DE |
1866 | |
1867 | /* This is the default definition. */ | |
1868 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 1869 | ? upward |
c229cba9 DE |
1870 | : ((mode == BLKmode |
1871 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
1872 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
1873 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 1874 | ? downward : upward)); |
c229cba9 DE |
1875 | } |
1876 | ||
b6c9286a MM |
1877 | /* If defined, a C expression that gives the alignment boundary, in bits, |
1878 | of an argument with the specified mode and type. If it is not defined, | |
1879 | PARM_BOUNDARY is used for all arguments. | |
1880 | ||
2310f99a | 1881 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
1882 | |
1883 | int | |
1884 | function_arg_boundary (mode, type) | |
1885 | enum machine_mode mode; | |
9ebbca7d | 1886 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 1887 | { |
4cc833b7 RH |
1888 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
1889 | && (mode == DImode || mode == DFmode)) | |
e1f83b4d | 1890 | return 64; |
9ebbca7d | 1891 | else |
b6c9286a | 1892 | return PARM_BOUNDARY; |
b6c9286a MM |
1893 | } |
1894 | \f | |
4697a36c MM |
1895 | /* Update the data in CUM to advance over an argument |
1896 | of mode MODE and data type TYPE. | |
1897 | (TYPE is null for libcalls where that information may not be available.) */ | |
1898 | ||
1899 | void | |
1900 | function_arg_advance (cum, mode, type, named) | |
1901 | CUMULATIVE_ARGS *cum; | |
1902 | enum machine_mode mode; | |
1903 | tree type; | |
1904 | int named; | |
1905 | { | |
1906 | cum->nargs_prototype--; | |
1907 | ||
c81bebd7 | 1908 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 1909 | { |
4cc833b7 RH |
1910 | if (TARGET_HARD_FLOAT |
1911 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 1912 | { |
4cc833b7 RH |
1913 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
1914 | cum->fregno++; | |
1915 | else | |
1916 | { | |
1917 | if (mode == DFmode) | |
1918 | cum->words += cum->words & 1; | |
1919 | cum->words += RS6000_ARG_SIZE (mode, type, 1); | |
1920 | } | |
4697a36c | 1921 | } |
4cc833b7 RH |
1922 | else |
1923 | { | |
1924 | int n_words; | |
1925 | int gregno = cum->sysv_gregno; | |
1926 | ||
1927 | /* Aggregates and IEEE quad get passed by reference. */ | |
1928 | if ((type && AGGREGATE_TYPE_P (type)) | |
1929 | || mode == TFmode) | |
1930 | n_words = 1; | |
1931 | else | |
1932 | n_words = RS6000_ARG_SIZE (mode, type, 1); | |
1933 | ||
1934 | /* Long long is put in odd registers. */ | |
1935 | if (n_words == 2 && (gregno & 1) == 0) | |
1936 | gregno += 1; | |
1937 | ||
1938 | /* Long long is not split between registers and stack. */ | |
1939 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
1940 | { | |
1941 | /* Long long is aligned on the stack. */ | |
1942 | if (n_words == 2) | |
1943 | cum->words += cum->words & 1; | |
1944 | cum->words += n_words; | |
1945 | } | |
4697a36c | 1946 | |
4cc833b7 RH |
1947 | /* Note: continuing to accumulate gregno past when we've started |
1948 | spilling to the stack indicates the fact that we've started | |
1949 | spilling to the stack to expand_builtin_saveregs. */ | |
1950 | cum->sysv_gregno = gregno + n_words; | |
1951 | } | |
4697a36c | 1952 | |
4cc833b7 RH |
1953 | if (TARGET_DEBUG_ARG) |
1954 | { | |
1955 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
1956 | cum->words, cum->fregno); | |
1957 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
1958 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
1959 | fprintf (stderr, "mode = %4s, named = %d\n", | |
1960 | GET_MODE_NAME (mode), named); | |
1961 | } | |
4697a36c MM |
1962 | } |
1963 | else | |
4cc833b7 RH |
1964 | { |
1965 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
1966 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
1967 | cum->words += align; | |
4697a36c | 1968 | |
4cc833b7 RH |
1969 | if (named) |
1970 | { | |
1971 | cum->words += RS6000_ARG_SIZE (mode, type, named); | |
1972 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) | |
1973 | cum->fregno++; | |
1974 | } | |
1975 | ||
1976 | if (TARGET_DEBUG_ARG) | |
1977 | { | |
1978 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
1979 | cum->words, cum->fregno); | |
1980 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
1981 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
1982 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
1983 | } | |
1984 | } | |
4697a36c MM |
1985 | } |
1986 | \f | |
1987 | /* Determine where to put an argument to a function. | |
1988 | Value is zero to push the argument on the stack, | |
1989 | or a hard register in which to store the argument. | |
1990 | ||
1991 | MODE is the argument's machine mode. | |
1992 | TYPE is the data type of the argument (as a tree). | |
1993 | This is null for libcalls where that information may | |
1994 | not be available. | |
1995 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1996 | the preceding args and about the function being called. | |
1997 | NAMED is nonzero if this argument is a named parameter | |
1998 | (otherwise it is an extra parameter matching an ellipsis). | |
1999 | ||
2000 | On RS/6000 the first eight words of non-FP are normally in registers | |
2001 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2002 | Under V.4, the first 8 FP args are in registers. | |
2003 | ||
2004 | If this is floating-point and no prototype is specified, we use | |
2005 | both an FP and integer register (or possibly FP reg and stack). Library | |
2006 | functions (when TYPE is zero) always have the proper types for args, | |
2007 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2008 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2009 | |
2010 | struct rtx_def * | |
2011 | function_arg (cum, mode, type, named) | |
2012 | CUMULATIVE_ARGS *cum; | |
2013 | enum machine_mode mode; | |
2014 | tree type; | |
2015 | int named; | |
2016 | { | |
4cc833b7 | 2017 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2018 | |
4cc833b7 RH |
2019 | /* Return a marker to indicate whether CR1 needs to set or clear the bit |
2020 | that V.4 uses to say fp args were passed in registers. Assume that we | |
2021 | don't need the marker for software floating point, or compiler generated | |
2022 | library calls. */ | |
4697a36c MM |
2023 | if (mode == VOIDmode) |
2024 | { | |
c81bebd7 | 2025 | if ((abi == ABI_V4 || abi == ABI_SOLARIS) |
7509c759 MM |
2026 | && TARGET_HARD_FLOAT |
2027 | && cum->nargs_prototype < 0 | |
4697a36c | 2028 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2029 | { |
6a4cee5f MM |
2030 | return GEN_INT (cum->call_cookie |
2031 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2032 | ? CALL_V4_SET_FP_ARGS | |
2033 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2034 | } |
4697a36c | 2035 | |
7509c759 | 2036 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2037 | } |
2038 | ||
4cc833b7 | 2039 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c | 2040 | { |
4cc833b7 RH |
2041 | if (TARGET_HARD_FLOAT |
2042 | && (mode == SFmode || mode == DFmode)) | |
2043 | { | |
2044 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2045 | return gen_rtx_REG (mode, cum->fregno); | |
2046 | else | |
2047 | return NULL; | |
2048 | } | |
2049 | else | |
2050 | { | |
2051 | int n_words; | |
2052 | int gregno = cum->sysv_gregno; | |
2053 | ||
2054 | /* Aggregates and IEEE quad get passed by reference. */ | |
2055 | if ((type && AGGREGATE_TYPE_P (type)) | |
2056 | || mode == TFmode) | |
2057 | n_words = 1; | |
2058 | else | |
2059 | n_words = RS6000_ARG_SIZE (mode, type, 1); | |
2060 | ||
2061 | /* Long long is put in odd registers. */ | |
2062 | if (n_words == 2 && (gregno & 1) == 0) | |
2063 | gregno += 1; | |
2064 | ||
2065 | /* Long long is not split between registers and stack. */ | |
2066 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2067 | return gen_rtx_REG (mode, gregno); | |
2068 | else | |
2069 | return NULL; | |
2070 | } | |
4697a36c | 2071 | } |
4cc833b7 RH |
2072 | else |
2073 | { | |
2074 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2075 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2076 | int align_words = cum->words + align; | |
4697a36c | 2077 | |
c81fc13e | 2078 | if (! named) |
4cc833b7 | 2079 | return NULL_RTX; |
4697a36c | 2080 | |
4cc833b7 RH |
2081 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2082 | return NULL_RTX; | |
2083 | ||
2084 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2085 | { | |
2086 | if (! type | |
2087 | || ((cum->nargs_prototype > 0) | |
2088 | /* IBM AIX extended its linkage convention definition always | |
2089 | to require FP args after register save area hole on the | |
2090 | stack. */ | |
2091 | && (DEFAULT_ABI != ABI_AIX | |
2092 | || ! TARGET_XL_CALL | |
2093 | || (align_words < GP_ARG_NUM_REG)))) | |
2094 | return gen_rtx_REG (mode, cum->fregno); | |
2095 | ||
2096 | return gen_rtx_PARALLEL (mode, | |
2097 | gen_rtvec (2, | |
39403d82 | 2098 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2099 | ((align_words >= GP_ARG_NUM_REG) |
2100 | ? NULL_RTX | |
2101 | : (align_words | |
2102 | + RS6000_ARG_SIZE (mode, type, named) | |
2103 | > GP_ARG_NUM_REG | |
2104 | /* If this is partially on the stack, then | |
2105 | we only include the portion actually | |
2106 | in registers here. */ | |
39403d82 | 2107 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2108 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2109 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2110 | GP_ARG_MIN_REG + align_words))), |
2111 | const0_rtx), | |
39403d82 DE |
2112 | gen_rtx_EXPR_LIST (VOIDmode, |
2113 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2114 | const0_rtx))); |
4cc833b7 RH |
2115 | } |
2116 | else if (align_words < GP_ARG_NUM_REG) | |
2117 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2118 | else | |
2119 | return NULL_RTX; | |
4697a36c | 2120 | } |
4697a36c MM |
2121 | } |
2122 | \f | |
2123 | /* For an arg passed partly in registers and partly in memory, | |
2124 | this is the number of registers used. | |
2125 | For args passed entirely in registers or entirely in memory, zero. */ | |
2126 | ||
2127 | int | |
2128 | function_arg_partial_nregs (cum, mode, type, named) | |
2129 | CUMULATIVE_ARGS *cum; | |
2130 | enum machine_mode mode; | |
2131 | tree type; | |
2132 | int named; | |
2133 | { | |
2134 | if (! named) | |
2135 | return 0; | |
2136 | ||
c81bebd7 | 2137 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2138 | return 0; |
4697a36c MM |
2139 | |
2140 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2141 | { | |
2142 | if (cum->nargs_prototype >= 0) | |
2143 | return 0; | |
2144 | } | |
2145 | ||
2146 | if (cum->words < GP_ARG_NUM_REG | |
2147 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named))) | |
2148 | { | |
2149 | int ret = GP_ARG_NUM_REG - cum->words; | |
2150 | if (ret && TARGET_DEBUG_ARG) | |
2151 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2152 | ||
2153 | return ret; | |
2154 | } | |
2155 | ||
2156 | return 0; | |
2157 | } | |
2158 | \f | |
2159 | /* A C expression that indicates when an argument must be passed by | |
2160 | reference. If nonzero for an argument, a copy of that argument is | |
2161 | made in memory and a pointer to the argument is passed instead of | |
2162 | the argument itself. The pointer is passed in whatever way is | |
2163 | appropriate for passing a pointer to that type. | |
2164 | ||
2165 | Under V.4, structures and unions are passed by reference. */ | |
2166 | ||
2167 | int | |
2168 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2169 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2170 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2171 | tree type; |
296b8152 | 2172 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2173 | { |
c81bebd7 | 2174 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4cc833b7 RH |
2175 | && ((type && AGGREGATE_TYPE_P (type)) |
2176 | || mode == TFmode)) | |
4697a36c MM |
2177 | { |
2178 | if (TARGET_DEBUG_ARG) | |
2179 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2180 | ||
2181 | return 1; | |
2182 | } | |
4697a36c MM |
2183 | |
2184 | return 0; | |
2185 | } | |
4697a36c MM |
2186 | \f |
2187 | /* Perform any needed actions needed for a function that is receiving a | |
2188 | variable number of arguments. | |
2189 | ||
2190 | CUM is as above. | |
2191 | ||
2192 | MODE and TYPE are the mode and type of the current parameter. | |
2193 | ||
2194 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2195 | that must be pushed by the prolog to pretend that our caller pushed | |
2196 | it. | |
2197 | ||
2198 | Normally, this macro will push all remaining incoming registers on the | |
2199 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2200 | ||
2201 | void | |
2202 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2203 | CUMULATIVE_ARGS *cum; | |
2204 | enum machine_mode mode; | |
2205 | tree type; | |
2206 | int *pretend_size; | |
2207 | int no_rtl; | |
2208 | ||
2209 | { | |
4cc833b7 RH |
2210 | CUMULATIVE_ARGS next_cum; |
2211 | int reg_size = TARGET_32BIT ? 4 : 8; | |
dfafc897 FS |
2212 | rtx save_area, mem; |
2213 | int first_reg_offset, set; | |
4697a36c | 2214 | |
60e2d0ca | 2215 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2216 | { |
4cc833b7 RH |
2217 | tree fntype; |
2218 | int stdarg_p; | |
2219 | ||
2220 | fntype = TREE_TYPE (current_function_decl); | |
2221 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2222 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2223 | != void_type_node)); | |
2224 | ||
2225 | /* For varargs, we do not want to skip the dummy va_dcl argument. | |
2226 | For stdargs, we do want to skip the last named argument. */ | |
2227 | next_cum = *cum; | |
2228 | if (stdarg_p) | |
2229 | function_arg_advance (&next_cum, mode, type, 1); | |
2230 | ||
2231 | /* Indicate to allocate space on the stack for varargs save area. */ | |
2232 | /* ??? Does this really have to be located at a magic spot on the | |
2233 | stack, or can we allocate this with assign_stack_local instead. */ | |
4697a36c | 2234 | rs6000_sysv_varargs_p = 1; |
60e2d0ca | 2235 | if (! no_rtl) |
2c4974b7 | 2236 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2237 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2238 | |
2239 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2240 | } |
60e2d0ca | 2241 | else |
4697a36c | 2242 | { |
4cc833b7 RH |
2243 | save_area = virtual_incoming_args_rtx; |
2244 | rs6000_sysv_varargs_p = 0; | |
4697a36c | 2245 | |
4cc833b7 | 2246 | first_reg_offset = cum->words; |
4697a36c MM |
2247 | if (MUST_PASS_IN_STACK (mode, type)) |
2248 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1); | |
4cc833b7 | 2249 | } |
4697a36c | 2250 | |
dfafc897 | 2251 | set = get_varargs_alias_set (); |
c81fc13e | 2252 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2253 | { |
dfafc897 FS |
2254 | mem = gen_rtx_MEM (BLKmode, |
2255 | plus_constant (save_area, | |
2256 | first_reg_offset * reg_size)), | |
2257 | MEM_ALIAS_SET (mem) = set; | |
2258 | ||
4cc833b7 | 2259 | move_block_from_reg |
dfafc897 | 2260 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2261 | GP_ARG_NUM_REG - first_reg_offset, |
2262 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2263 | ||
2264 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2265 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2266 | } | |
2267 | ||
4697a36c | 2268 | /* Save FP registers if needed. */ |
4cc833b7 | 2269 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
c81fc13e | 2270 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2271 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2272 | { |
4cc833b7 | 2273 | int fregno = next_cum.fregno; |
9ebbca7d | 2274 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2275 | rtx lab = gen_label_rtx (); |
2276 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2277 | |
4cc833b7 | 2278 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2279 | pc_rtx, |
39403d82 | 2280 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2281 | gen_rtx_NE (VOIDmode, cr1, |
2282 | const0_rtx), | |
39403d82 | 2283 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2284 | pc_rtx))); |
2285 | ||
4cc833b7 RH |
2286 | while (fregno <= FP_ARG_V4_MAX_REG) |
2287 | { | |
dfafc897 FS |
2288 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
2289 | MEM_ALIAS_SET (mem) = set; | |
2290 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); | |
4cc833b7 RH |
2291 | fregno++; |
2292 | off += 8; | |
4697a36c | 2293 | } |
4cc833b7 RH |
2294 | |
2295 | emit_label (lab); | |
4697a36c | 2296 | } |
4697a36c | 2297 | } |
4697a36c | 2298 | |
dfafc897 | 2299 | /* Create the va_list data type. */ |
2c4974b7 | 2300 | |
dfafc897 FS |
2301 | tree |
2302 | rs6000_build_va_list () | |
2303 | { | |
bab45a51 | 2304 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2305 | |
9ebbca7d GK |
2306 | /* For AIX, prefer 'char *' because that's what the system |
2307 | header files like. */ | |
dfafc897 | 2308 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d | 2309 | return build_pointer_type (char_type_node); |
dfafc897 | 2310 | |
0f4fd75d | 2311 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2312 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2313 | |
9ebbca7d GK |
2314 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2315 | unsigned_char_type_node); | |
2316 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2317 | unsigned_char_type_node); | |
dfafc897 FS |
2318 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2319 | ptr_type_node); | |
2320 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
2321 | ptr_type_node); | |
2322 | ||
2323 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
2324 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
2325 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
2326 | DECL_FIELD_CONTEXT (f_sav) = record; | |
2327 | ||
bab45a51 FS |
2328 | TREE_CHAIN (record) = type_decl; |
2329 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
2330 | TYPE_FIELDS (record) = f_gpr; |
2331 | TREE_CHAIN (f_gpr) = f_fpr; | |
2332 | TREE_CHAIN (f_fpr) = f_ovf; | |
2333 | TREE_CHAIN (f_ovf) = f_sav; | |
2334 | ||
2335 | layout_type (record); | |
2336 | ||
2337 | /* The correct type is an array type of one element. */ | |
2338 | return build_array_type (record, build_index_type (size_zero_node)); | |
2339 | } | |
2340 | ||
2341 | /* Implement va_start. */ | |
2342 | ||
2343 | void | |
2344 | rs6000_va_start (stdarg_p, valist, nextarg) | |
2345 | int stdarg_p; | |
2346 | tree valist; | |
2347 | rtx nextarg; | |
4697a36c | 2348 | { |
dfafc897 FS |
2349 | HOST_WIDE_INT words, n_gpr, n_fpr; |
2350 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2351 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 2352 | |
dfafc897 | 2353 | /* Only SVR4 needs something special. */ |
2c4974b7 | 2354 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
dfafc897 FS |
2355 | { |
2356 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
2357 | return; | |
2358 | } | |
2359 | ||
973a648b | 2360 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2361 | f_fpr = TREE_CHAIN (f_gpr); |
2362 | f_ovf = TREE_CHAIN (f_fpr); | |
2363 | f_sav = TREE_CHAIN (f_ovf); | |
2364 | ||
8ebecc3b | 2365 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2366 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2367 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2368 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2369 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2370 | ||
2371 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 2372 | words = current_function_args_info.words; |
dfafc897 FS |
2373 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
2374 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
2375 | ||
2376 | if (TARGET_DEBUG_ARG) | |
2377 | fprintf (stderr, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n", | |
2378 | words, n_gpr, n_fpr); | |
2379 | ||
2380 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
2381 | TREE_SIDE_EFFECTS (t) = 1; | |
2382 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2383 | ||
2384 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
2385 | TREE_SIDE_EFFECTS (t) = 1; | |
2386 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2387 | ||
2388 | /* Find the overflow area. */ | |
2389 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
2390 | if (words != 0) | |
2391 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
2392 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
2393 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2394 | TREE_SIDE_EFFECTS (t) = 1; | |
2395 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2396 | ||
2397 | /* Find the register save area. */ | |
2398 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
2399 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
2400 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
2401 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
2402 | TREE_SIDE_EFFECTS (t) = 1; | |
2403 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2404 | } | |
2405 | ||
2406 | /* Implement va_arg. */ | |
2407 | ||
2408 | rtx | |
2409 | rs6000_va_arg (valist, type) | |
2410 | tree valist, type; | |
2411 | { | |
2412 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2413 | tree gpr, fpr, ovf, sav, reg, t, u; | |
2414 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
2415 | rtx lab_false, lab_over, addr_rtx, r; | |
2416 | ||
9ebbca7d GK |
2417 | /* For AIX, the rule is that structures are passed left-aligned in |
2418 | their stack slot. However, GCC does not presently do this: | |
2419 | structures which are the same size as integer types are passed | |
2420 | right-aligned, as if they were in fact integers. This only | |
2421 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
dfafc897 | 2422 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d GK |
2423 | { |
2424 | HOST_WIDE_INT align, rounded_size; | |
2425 | enum machine_mode mode; | |
2426 | tree addr_tree; | |
2427 | ||
2428 | /* Compute the rounded size of the type. */ | |
2429 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
2430 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
2431 | * align); | |
2432 | ||
2433 | addr_tree = valist; | |
2434 | ||
2435 | mode = TYPE_MODE (type); | |
2436 | if (mode != BLKmode) | |
2437 | { | |
2438 | HOST_WIDE_INT adj; | |
2439 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
2440 | if (rounded_size > align) | |
2441 | adj = rounded_size; | |
2442 | ||
2443 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
2444 | build_int_2 (rounded_size - adj, 0)); | |
2445 | } | |
2446 | ||
2447 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
2448 | addr_rtx = copy_to_reg (addr_rtx); | |
2449 | ||
2450 | /* Compute new value for AP. */ | |
2451 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2452 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
2453 | build_int_2 (rounded_size, 0))); | |
2454 | TREE_SIDE_EFFECTS (t) = 1; | |
2455 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2456 | ||
2457 | return addr_rtx; | |
2458 | } | |
dfafc897 | 2459 | |
973a648b | 2460 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2461 | f_fpr = TREE_CHAIN (f_gpr); |
2462 | f_ovf = TREE_CHAIN (f_fpr); | |
2463 | f_sav = TREE_CHAIN (f_ovf); | |
2464 | ||
8ebecc3b | 2465 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2466 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2467 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2468 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2469 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2470 | ||
2471 | size = int_size_in_bytes (type); | |
2472 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 2473 | |
dfafc897 | 2474 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 2475 | { |
dfafc897 FS |
2476 | /* Aggregates and long doubles are passed by reference. */ |
2477 | indirect_p = 1; | |
2478 | reg = gpr; | |
2479 | n_reg = 1; | |
2480 | sav_ofs = 0; | |
2481 | sav_scale = 4; | |
2482 | size = rsize = UNITS_PER_WORD; | |
2483 | } | |
2484 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
2485 | { | |
2486 | /* FP args go in FP registers, if present. */ | |
2487 | indirect_p = 0; | |
2488 | reg = fpr; | |
2489 | n_reg = 1; | |
2490 | sav_ofs = 8*4; | |
2491 | sav_scale = 8; | |
4cc833b7 | 2492 | } |
dfafc897 FS |
2493 | else |
2494 | { | |
2495 | /* Otherwise into GP registers. */ | |
2496 | indirect_p = 0; | |
2497 | reg = gpr; | |
2498 | n_reg = rsize; | |
2499 | sav_ofs = 0; | |
2500 | sav_scale = 4; | |
2501 | } | |
2502 | ||
2503 | /* | |
2504 | * Pull the value out of the saved registers ... | |
2505 | */ | |
2506 | ||
2507 | lab_false = gen_label_rtx (); | |
2508 | lab_over = gen_label_rtx (); | |
2509 | addr_rtx = gen_reg_rtx (Pmode); | |
2510 | ||
2511 | emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
2512 | GEN_INT (8 - n_reg + 1), | |
2513 | GE, const1_rtx, QImode, 1, 1, lab_false); | |
2c4974b7 | 2514 | |
dfafc897 FS |
2515 | /* Long long is aligned in the registers. */ |
2516 | if (n_reg > 1) | |
2c4974b7 | 2517 | { |
dfafc897 FS |
2518 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, |
2519 | build_int_2 (n_reg - 1, 0)); | |
2520 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
2521 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
2522 | TREE_SIDE_EFFECTS (u) = 1; | |
2523 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2c4974b7 | 2524 | } |
dfafc897 FS |
2525 | |
2526 | if (sav_ofs) | |
2527 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
2c4974b7 | 2528 | else |
dfafc897 | 2529 | t = sav; |
2c4974b7 | 2530 | |
dfafc897 FS |
2531 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0)); |
2532 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2533 | |
dfafc897 FS |
2534 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
2535 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2536 | |
dfafc897 FS |
2537 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
2538 | TREE_SIDE_EFFECTS (u) = 1; | |
2539 | ||
2540 | t = build (PLUS_EXPR, ptr_type_node, t, u); | |
2541 | TREE_SIDE_EFFECTS (t) = 1; | |
2542 | ||
2543 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2544 | if (r != addr_rtx) | |
2545 | emit_move_insn (addr_rtx, r); | |
2546 | ||
2547 | emit_jump_insn (gen_jump (lab_over)); | |
2548 | emit_barrier (); | |
2549 | emit_label (lab_false); | |
2550 | ||
2551 | /* | |
2552 | * ... otherwise out of the overflow area. | |
2553 | */ | |
2554 | ||
2555 | /* Make sure we don't find reg 7 for the next int arg. */ | |
2556 | if (n_reg > 1) | |
2557 | { | |
2558 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
2559 | TREE_SIDE_EFFECTS (t) = 1; | |
2560 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2561 | } | |
2562 | ||
2563 | /* Care for on-stack alignment if needed. */ | |
2564 | if (rsize <= 1) | |
2565 | t = ovf; | |
2566 | else | |
2567 | { | |
2568 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0)); | |
2569 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1)); | |
2570 | } | |
2571 | t = save_expr (t); | |
2572 | ||
2573 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2574 | if (r != addr_rtx) | |
2575 | emit_move_insn (addr_rtx, r); | |
2576 | ||
2577 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
2578 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2579 | TREE_SIDE_EFFECTS (t) = 1; | |
2580 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2581 | ||
2582 | emit_label (lab_over); | |
2583 | ||
2584 | if (indirect_p) | |
2585 | { | |
2586 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
2587 | MEM_ALIAS_SET (r) = get_varargs_alias_set (); | |
2588 | emit_move_insn (addr_rtx, r); | |
2589 | } | |
2590 | ||
2591 | return addr_rtx; | |
4697a36c | 2592 | } |
5b5040b9 RK |
2593 | \f |
2594 | /* Generate a memory reference for expand_block_move, copying volatile, | |
2595 | and other bits from an original memory reference. */ | |
2596 | ||
2597 | static rtx | |
2598 | expand_block_move_mem (mode, addr, orig_mem) | |
2599 | enum machine_mode mode; | |
2600 | rtx addr; | |
2601 | rtx orig_mem; | |
2602 | { | |
39403d82 | 2603 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 2604 | |
c6df88cb | 2605 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
b6c9286a MM |
2606 | #ifdef MEM_UNALIGNED_P |
2607 | MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem); | |
2608 | #endif | |
5b5040b9 RK |
2609 | return mem; |
2610 | } | |
2611 | ||
7e69e155 MM |
2612 | /* Expand a block move operation, and return 1 if successful. Return 0 |
2613 | if we should let the compiler generate normal code. | |
2614 | ||
2615 | operands[0] is the destination | |
2616 | operands[1] is the source | |
2617 | operands[2] is the length | |
2618 | operands[3] is the alignment */ | |
2619 | ||
3933e0e1 MM |
2620 | #define MAX_MOVE_REG 4 |
2621 | ||
7e69e155 MM |
2622 | int |
2623 | expand_block_move (operands) | |
2624 | rtx operands[]; | |
2625 | { | |
b6c9286a MM |
2626 | rtx orig_dest = operands[0]; |
2627 | rtx orig_src = operands[1]; | |
7e69e155 | 2628 | rtx bytes_rtx = operands[2]; |
7e69e155 | 2629 | rtx align_rtx = operands[3]; |
3933e0e1 | 2630 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 2631 | int align; |
3933e0e1 MM |
2632 | int bytes; |
2633 | int offset; | |
2634 | int num_reg; | |
2635 | int i; | |
7e69e155 MM |
2636 | rtx src_reg; |
2637 | rtx dest_reg; | |
3933e0e1 MM |
2638 | rtx src_addr; |
2639 | rtx dest_addr; | |
7e69e155 | 2640 | rtx tmp_reg; |
3933e0e1 | 2641 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
2642 | int move_bytes; |
2643 | ||
3933e0e1 | 2644 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 2645 | if (! constp) |
3933e0e1 MM |
2646 | return 0; |
2647 | ||
5ee95df6 FS |
2648 | /* If this is not a fixed size alignment, abort */ |
2649 | if (GET_CODE (align_rtx) != CONST_INT) | |
2650 | abort (); | |
2651 | align = INTVAL (align_rtx); | |
2652 | ||
7e69e155 | 2653 | /* Anything to move? */ |
3933e0e1 MM |
2654 | bytes = INTVAL (bytes_rtx); |
2655 | if (bytes <= 0) | |
7e69e155 MM |
2656 | return 1; |
2657 | ||
3933e0e1 MM |
2658 | /* Don't support real large moves. If string instructions are not used, |
2659 | then don't generate more than 8 loads. */ | |
2660 | if (TARGET_STRING) | |
2661 | { | |
c81fc13e | 2662 | if (bytes > 8*4) |
3933e0e1 MM |
2663 | return 0; |
2664 | } | |
cc0d9ba8 | 2665 | else if (! STRICT_ALIGNMENT) |
3933e0e1 | 2666 | { |
c81fc13e DE |
2667 | if (TARGET_POWERPC64 && align >= 4) |
2668 | { | |
2669 | if (bytes > 8*8) | |
2670 | return 0; | |
2671 | } | |
2672 | else | |
2673 | if (bytes > 8*4) | |
2674 | return 0; | |
3933e0e1 MM |
2675 | } |
2676 | else if (bytes > 8*align) | |
7e69e155 MM |
2677 | return 0; |
2678 | ||
2679 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
2680 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
2681 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 2682 | |
3933e0e1 | 2683 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 2684 | { |
3933e0e1 | 2685 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 2686 | { |
3933e0e1 | 2687 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
2688 | && ! fixed_regs[5] |
2689 | && ! fixed_regs[6] | |
2690 | && ! fixed_regs[7] | |
2691 | && ! fixed_regs[8] | |
2692 | && ! fixed_regs[9] | |
2693 | && ! fixed_regs[10] | |
2694 | && ! fixed_regs[11] | |
2695 | && ! fixed_regs[12]) | |
3933e0e1 MM |
2696 | { |
2697 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
2698 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
2699 | dest_reg, | |
2700 | orig_dest), | |
2701 | expand_block_move_mem (BLKmode, | |
2702 | src_reg, | |
2703 | orig_src), | |
2704 | GEN_INT ((move_bytes == 32) | |
2705 | ? 0 : move_bytes), | |
4c64a852 | 2706 | align_rtx)); |
3933e0e1 MM |
2707 | } |
2708 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
2709 | && ! fixed_regs[5] |
2710 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
2711 | && ! fixed_regs[7] |
2712 | && ! fixed_regs[8] | |
2713 | && ! fixed_regs[9] | |
f9562f27 | 2714 | && ! fixed_regs[10]) |
3933e0e1 MM |
2715 | { |
2716 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
2717 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
2718 | dest_reg, | |
2719 | orig_dest), | |
2720 | expand_block_move_mem (BLKmode, | |
2721 | src_reg, | |
2722 | orig_src), | |
3933e0e1 | 2723 | GEN_INT (move_bytes), |
4c64a852 | 2724 | align_rtx)); |
3933e0e1 MM |
2725 | } |
2726 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
2727 | && ! fixed_regs[5] |
2728 | && ! fixed_regs[6] | |
2729 | && ! fixed_regs[7] | |
2730 | && ! fixed_regs[8]) | |
3933e0e1 MM |
2731 | { |
2732 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
2733 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
2734 | dest_reg, | |
2735 | orig_dest), | |
2736 | expand_block_move_mem (BLKmode, | |
2737 | src_reg, | |
2738 | orig_src), | |
3933e0e1 | 2739 | GEN_INT (move_bytes), |
4c64a852 | 2740 | align_rtx)); |
3933e0e1 | 2741 | } |
acad7ed3 DE |
2742 | else if (bytes >= 8 && TARGET_POWERPC64 |
2743 | /* 64-bit loads and stores require word-aligned displacements. */ | |
2744 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
2745 | { | |
2746 | move_bytes = 8; | |
2747 | tmp_reg = gen_reg_rtx (DImode); | |
2748 | emit_move_insn (tmp_reg, | |
2749 | expand_block_move_mem (DImode, | |
2eba1afa | 2750 | src_reg, orig_src)); |
acad7ed3 | 2751 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 2752 | dest_reg, orig_dest), |
acad7ed3 DE |
2753 | tmp_reg); |
2754 | } | |
2755 | else if (bytes > 4) | |
3933e0e1 MM |
2756 | { /* move up to 8 bytes at a time */ |
2757 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
2758 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
2759 | dest_reg, | |
2760 | orig_dest), | |
2761 | expand_block_move_mem (BLKmode, | |
2762 | src_reg, | |
2763 | orig_src), | |
3933e0e1 | 2764 | GEN_INT (move_bytes), |
4c64a852 | 2765 | align_rtx)); |
3933e0e1 | 2766 | } |
cc0d9ba8 | 2767 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
2768 | { /* move 4 bytes */ |
2769 | move_bytes = 4; | |
2770 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
2771 | emit_move_insn (tmp_reg, |
2772 | expand_block_move_mem (SImode, | |
2773 | src_reg, orig_src)); | |
2774 | emit_move_insn (expand_block_move_mem (SImode, | |
2775 | dest_reg, orig_dest), | |
2776 | tmp_reg); | |
3933e0e1 | 2777 | } |
cc0d9ba8 | 2778 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
2779 | { /* move 2 bytes */ |
2780 | move_bytes = 2; | |
2781 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
2782 | emit_move_insn (tmp_reg, |
2783 | expand_block_move_mem (HImode, | |
2784 | src_reg, orig_src)); | |
2785 | emit_move_insn (expand_block_move_mem (HImode, | |
2786 | dest_reg, orig_dest), | |
2787 | tmp_reg); | |
3933e0e1 MM |
2788 | } |
2789 | else if (bytes == 1) /* move 1 byte */ | |
2790 | { | |
2791 | move_bytes = 1; | |
2792 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
2793 | emit_move_insn (tmp_reg, |
2794 | expand_block_move_mem (QImode, | |
2795 | src_reg, orig_src)); | |
2796 | emit_move_insn (expand_block_move_mem (QImode, | |
2797 | dest_reg, orig_dest), | |
2798 | tmp_reg); | |
3933e0e1 MM |
2799 | } |
2800 | else | |
2801 | { /* move up to 4 bytes at a time */ | |
2802 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
2803 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
2804 | dest_reg, | |
2805 | orig_dest), | |
2806 | expand_block_move_mem (BLKmode, | |
2807 | src_reg, | |
2808 | orig_src), | |
3933e0e1 | 2809 | GEN_INT (move_bytes), |
4c64a852 | 2810 | align_rtx)); |
3933e0e1 | 2811 | } |
4c64a852 | 2812 | |
015892ee RK |
2813 | if (bytes > move_bytes) |
2814 | { | |
cc0d9ba8 DE |
2815 | if (! TARGET_POWERPC64) |
2816 | { | |
2817 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
2818 | GEN_INT (move_bytes))); | |
2819 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
2820 | GEN_INT (move_bytes))); | |
2821 | } | |
2822 | else | |
2823 | { | |
2824 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
2825 | GEN_INT (move_bytes))); | |
2826 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
2827 | GEN_INT (move_bytes))); | |
2828 | } | |
015892ee | 2829 | } |
4c64a852 | 2830 | } |
3933e0e1 MM |
2831 | } |
2832 | ||
2833 | else /* string instructions not available */ | |
2834 | { | |
2835 | num_reg = offset = 0; | |
2836 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 2837 | { |
3933e0e1 MM |
2838 | /* Calculate the correct offset for src/dest */ |
2839 | if (offset == 0) | |
7e69e155 | 2840 | { |
3933e0e1 MM |
2841 | src_addr = src_reg; |
2842 | dest_addr = dest_reg; | |
2843 | } | |
2844 | else | |
2845 | { | |
c5c76735 JL |
2846 | src_addr = plus_constant (src_reg, offset); |
2847 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
2848 | } |
2849 | ||
cc0d9ba8 DE |
2850 | /* Generate the appropriate load and store, saving the stores |
2851 | for later. */ | |
2852 | if (bytes >= 8 && TARGET_POWERPC64 | |
2853 | /* 64-bit loads and stores require word-aligned displacements. */ | |
2854 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
b6c9286a MM |
2855 | { |
2856 | move_bytes = 8; | |
2857 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
2858 | emit_insn (gen_movdi (tmp_reg, |
2859 | expand_block_move_mem (DImode, | |
2860 | src_addr, | |
2861 | orig_src))); | |
2862 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
2863 | dest_addr, | |
2864 | orig_dest), | |
2865 | tmp_reg); | |
b6c9286a | 2866 | } |
cc0d9ba8 | 2867 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
2868 | { |
2869 | move_bytes = 4; | |
2870 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
2871 | emit_insn (gen_movsi (tmp_reg, |
2872 | expand_block_move_mem (SImode, | |
2873 | src_addr, | |
2874 | orig_src))); | |
2875 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
2876 | dest_addr, | |
2877 | orig_dest), | |
2878 | tmp_reg); | |
3933e0e1 | 2879 | } |
cc0d9ba8 | 2880 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
2881 | { |
2882 | move_bytes = 2; | |
2883 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 2884 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
2885 | expand_block_move_mem (HImode, |
2886 | src_addr, | |
2887 | orig_src))); | |
2888 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
2889 | dest_addr, | |
2890 | orig_dest), | |
2891 | tmp_reg); | |
3933e0e1 MM |
2892 | } |
2893 | else | |
2894 | { | |
2895 | move_bytes = 1; | |
2896 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 2897 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
2898 | expand_block_move_mem (QImode, |
2899 | src_addr, | |
2900 | orig_src))); | |
2901 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
2902 | dest_addr, | |
2903 | orig_dest), | |
2904 | tmp_reg); | |
3933e0e1 MM |
2905 | } |
2906 | ||
2907 | if (num_reg >= MAX_MOVE_REG) | |
2908 | { | |
2909 | for (i = 0; i < num_reg; i++) | |
2910 | emit_insn (stores[i]); | |
2911 | num_reg = 0; | |
7e69e155 MM |
2912 | } |
2913 | } | |
3933e0e1 | 2914 | |
b6c9286a MM |
2915 | for (i = 0; i < num_reg; i++) |
2916 | emit_insn (stores[i]); | |
7e69e155 MM |
2917 | } |
2918 | ||
2919 | return 1; | |
2920 | } | |
2921 | ||
9878760c RK |
2922 | \f |
2923 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
2924 | PARALLEL and the first section will be tested. */ | |
2925 | ||
2926 | int | |
2927 | load_multiple_operation (op, mode) | |
2928 | rtx op; | |
296b8152 | 2929 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
2930 | { |
2931 | int count = XVECLEN (op, 0); | |
e2c953b6 | 2932 | unsigned int dest_regno; |
9878760c RK |
2933 | rtx src_addr; |
2934 | int i; | |
2935 | ||
2936 | /* Perform a quick check so we don't blow up below. */ | |
2937 | if (count <= 1 | |
2938 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
2939 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
2940 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
2941 | return 0; | |
2942 | ||
2943 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
2944 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
2945 | ||
2946 | for (i = 1; i < count; i++) | |
2947 | { | |
2948 | rtx elt = XVECEXP (op, 0, i); | |
2949 | ||
2950 | if (GET_CODE (elt) != SET | |
2951 | || GET_CODE (SET_DEST (elt)) != REG | |
2952 | || GET_MODE (SET_DEST (elt)) != SImode | |
2953 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
2954 | || GET_CODE (SET_SRC (elt)) != MEM | |
2955 | || GET_MODE (SET_SRC (elt)) != SImode | |
2956 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
2957 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
2958 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
2959 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
2960 | return 0; | |
2961 | } | |
2962 | ||
2963 | return 1; | |
2964 | } | |
2965 | ||
2966 | /* Similar, but tests for store multiple. Here, the second vector element | |
2967 | is a CLOBBER. It will be tested later. */ | |
2968 | ||
2969 | int | |
2970 | store_multiple_operation (op, mode) | |
2971 | rtx op; | |
296b8152 | 2972 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
2973 | { |
2974 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 2975 | unsigned int src_regno; |
9878760c RK |
2976 | rtx dest_addr; |
2977 | int i; | |
2978 | ||
2979 | /* Perform a quick check so we don't blow up below. */ | |
2980 | if (count <= 1 | |
2981 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
2982 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
2983 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
2984 | return 0; | |
2985 | ||
2986 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
2987 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
2988 | ||
2989 | for (i = 1; i < count; i++) | |
2990 | { | |
2991 | rtx elt = XVECEXP (op, 0, i + 1); | |
2992 | ||
2993 | if (GET_CODE (elt) != SET | |
2994 | || GET_CODE (SET_SRC (elt)) != REG | |
2995 | || GET_MODE (SET_SRC (elt)) != SImode | |
2996 | || REGNO (SET_SRC (elt)) != src_regno + i | |
2997 | || GET_CODE (SET_DEST (elt)) != MEM | |
2998 | || GET_MODE (SET_DEST (elt)) != SImode | |
2999 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
3000 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
3001 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
3002 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
3003 | return 0; | |
3004 | } | |
3005 | ||
3006 | return 1; | |
3007 | } | |
9ebbca7d GK |
3008 | |
3009 | /* Return 1 for an PARALLEL suitable for mtcrf. */ | |
3010 | ||
3011 | int | |
3012 | mtcrf_operation (op, mode) | |
3013 | rtx op; | |
3014 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3015 | { | |
3016 | int count = XVECLEN (op, 0); | |
3017 | int i; | |
3018 | int bitmap = 0; | |
3019 | rtx src_reg; | |
3020 | ||
3021 | /* Perform a quick check so we don't blow up below. */ | |
3022 | if (count < 2 | |
3023 | || GET_CODE (XVECEXP (op, 0, 0)) != USE | |
3024 | || GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) != CONST_INT | |
3025 | || GET_CODE (XVECEXP (op, 0, 1)) != SET | |
3026 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) != UNSPEC | |
3027 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 1)), 0) != 2) | |
3028 | return 0; | |
3029 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 1)), 0, 0); | |
3030 | ||
3031 | if (GET_CODE (src_reg) != REG | |
3032 | || GET_MODE (src_reg) != SImode | |
3033 | || ! INT_REGNO_P (REGNO (src_reg))) | |
3034 | return 0; | |
3035 | ||
3036 | for (i = 1; i < count; i++) | |
3037 | { | |
3038 | rtx exp = XVECEXP (op, 0, i); | |
3039 | rtx unspec; | |
3040 | int maskval; | |
3041 | ||
3042 | if (GET_CODE (exp) != SET | |
3043 | || GET_CODE (SET_DEST (exp)) != REG | |
3044 | || GET_MODE (SET_DEST (exp)) != CCmode | |
3045 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
3046 | return 0; | |
3047 | unspec = SET_SRC (exp); | |
3048 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
3049 | bitmap |= maskval; | |
3050 | ||
3051 | if (GET_CODE (unspec) != UNSPEC | |
3052 | || XINT (unspec, 1) != 20 | |
3053 | || XVECLEN (unspec, 0) != 2 | |
3054 | || XVECEXP (unspec, 0, 0) != src_reg | |
3055 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
3056 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
3057 | return 0; | |
3058 | } | |
3059 | return INTVAL (XEXP (XVECEXP (op, 0, 0), 0)) == bitmap; | |
3060 | } | |
3061 | ||
3062 | /* Return 1 for an PARALLEL suitable for lmw. */ | |
3063 | ||
3064 | int | |
3065 | lmw_operation (op, mode) | |
3066 | rtx op; | |
3067 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3068 | { | |
3069 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3070 | unsigned int dest_regno; |
9ebbca7d | 3071 | rtx src_addr; |
e2c953b6 | 3072 | unsigned int base_regno; |
9ebbca7d GK |
3073 | HOST_WIDE_INT offset; |
3074 | int i; | |
3075 | ||
3076 | /* Perform a quick check so we don't blow up below. */ | |
3077 | if (count <= 1 | |
3078 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3079 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3080 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3081 | return 0; | |
3082 | ||
3083 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3084 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3085 | ||
3086 | if (dest_regno > 31 | |
e2c953b6 | 3087 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
3088 | return 0; |
3089 | ||
3090 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr)) | |
3091 | { | |
3092 | offset = 0; | |
3093 | base_regno = REGNO (src_addr); | |
3094 | if (base_regno == 0) | |
3095 | return 0; | |
3096 | } | |
3097 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr)) | |
3098 | { | |
3099 | offset = INTVAL (XEXP (src_addr, 1)); | |
3100 | base_regno = REGNO (XEXP (src_addr, 0)); | |
3101 | } | |
3102 | else | |
3103 | return 0; | |
3104 | ||
3105 | for (i = 0; i < count; i++) | |
3106 | { | |
3107 | rtx elt = XVECEXP (op, 0, i); | |
3108 | rtx newaddr; | |
3109 | rtx addr_reg; | |
3110 | HOST_WIDE_INT newoffset; | |
3111 | ||
3112 | if (GET_CODE (elt) != SET | |
3113 | || GET_CODE (SET_DEST (elt)) != REG | |
3114 | || GET_MODE (SET_DEST (elt)) != SImode | |
3115 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3116 | || GET_CODE (SET_SRC (elt)) != MEM | |
3117 | || GET_MODE (SET_SRC (elt)) != SImode) | |
3118 | return 0; | |
3119 | newaddr = XEXP (SET_SRC (elt), 0); | |
3120 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr)) | |
3121 | { | |
3122 | newoffset = 0; | |
3123 | addr_reg = newaddr; | |
3124 | } | |
3125 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr)) | |
3126 | { | |
3127 | addr_reg = XEXP (newaddr, 0); | |
3128 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3129 | } | |
3130 | else | |
3131 | return 0; | |
3132 | if (REGNO (addr_reg) != base_regno | |
3133 | || newoffset != offset + 4 * i) | |
3134 | return 0; | |
3135 | } | |
3136 | ||
3137 | return 1; | |
3138 | } | |
3139 | ||
3140 | /* Return 1 for an PARALLEL suitable for stmw. */ | |
3141 | ||
3142 | int | |
3143 | stmw_operation (op, mode) | |
3144 | rtx op; | |
3145 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3146 | { | |
3147 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3148 | unsigned int src_regno; |
9ebbca7d | 3149 | rtx dest_addr; |
e2c953b6 | 3150 | unsigned int base_regno; |
9ebbca7d GK |
3151 | HOST_WIDE_INT offset; |
3152 | int i; | |
3153 | ||
3154 | /* Perform a quick check so we don't blow up below. */ | |
3155 | if (count <= 1 | |
3156 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3157 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3158 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3159 | return 0; | |
3160 | ||
3161 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3162 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3163 | ||
3164 | if (src_regno > 31 | |
e2c953b6 | 3165 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
3166 | return 0; |
3167 | ||
3168 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr)) | |
3169 | { | |
3170 | offset = 0; | |
3171 | base_regno = REGNO (dest_addr); | |
3172 | if (base_regno == 0) | |
3173 | return 0; | |
3174 | } | |
3175 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr)) | |
3176 | { | |
3177 | offset = INTVAL (XEXP (dest_addr, 1)); | |
3178 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
3179 | } | |
3180 | else | |
3181 | return 0; | |
3182 | ||
3183 | for (i = 0; i < count; i++) | |
3184 | { | |
3185 | rtx elt = XVECEXP (op, 0, i); | |
3186 | rtx newaddr; | |
3187 | rtx addr_reg; | |
3188 | HOST_WIDE_INT newoffset; | |
3189 | ||
3190 | if (GET_CODE (elt) != SET | |
3191 | || GET_CODE (SET_SRC (elt)) != REG | |
3192 | || GET_MODE (SET_SRC (elt)) != SImode | |
3193 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3194 | || GET_CODE (SET_DEST (elt)) != MEM | |
3195 | || GET_MODE (SET_DEST (elt)) != SImode) | |
3196 | return 0; | |
3197 | newaddr = XEXP (SET_DEST (elt), 0); | |
3198 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr)) | |
3199 | { | |
3200 | newoffset = 0; | |
3201 | addr_reg = newaddr; | |
3202 | } | |
3203 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr)) | |
3204 | { | |
3205 | addr_reg = XEXP (newaddr, 0); | |
3206 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3207 | } | |
3208 | else | |
3209 | return 0; | |
3210 | if (REGNO (addr_reg) != base_regno | |
3211 | || newoffset != offset + 4 * i) | |
3212 | return 0; | |
3213 | } | |
3214 | ||
3215 | return 1; | |
3216 | } | |
9878760c | 3217 | \f |
39a10a29 GK |
3218 | |
3219 | /* A validation routine: say whether CODE, a condition code, | |
3220 | and MODE match. The other alternatives either don't make | |
3221 | sense or should never be generated. */ | |
3222 | static void | |
3223 | validate_condition_mode (code, mode) | |
3224 | enum rtx_code code; | |
3225 | enum machine_mode mode; | |
3226 | { | |
3227 | if (GET_RTX_CLASS (code) != '<' | |
3228 | || GET_MODE_CLASS (mode) != MODE_CC) | |
3229 | abort (); | |
3230 | ||
3231 | /* These don't make sense. */ | |
3232 | if ((code == GT || code == LT || code == GE || code == LE) | |
3233 | && mode == CCUNSmode) | |
3234 | abort (); | |
3235 | ||
3236 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
3237 | && mode != CCUNSmode) | |
3238 | abort (); | |
3239 | ||
3240 | if (mode != CCFPmode | |
3241 | && (code == ORDERED || code == UNORDERED | |
3242 | || code == UNEQ || code == LTGT | |
3243 | || code == UNGT || code == UNLT | |
3244 | || code == UNGE || code == UNLE)) | |
3245 | abort(); | |
3246 | ||
3247 | /* These should never be generated. */ | |
3248 | if (mode == CCFPmode | |
3249 | && (code == LE || code == GE | |
3250 | || code == UNEQ || code == LTGT | |
3251 | || code == UNGT || code == UNLT)) | |
3252 | abort (); | |
3253 | ||
3254 | /* These are invalid; the information is not there. */ | |
3255 | if (mode == CCEQmode | |
3256 | && code != EQ && code != NE) | |
3257 | abort (); | |
3258 | } | |
3259 | ||
9878760c RK |
3260 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
3261 | We only check the opcode against the mode of the CC value here. */ | |
3262 | ||
3263 | int | |
3264 | branch_comparison_operator (op, mode) | |
3265 | register rtx op; | |
296b8152 | 3266 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3267 | { |
3268 | enum rtx_code code = GET_CODE (op); | |
3269 | enum machine_mode cc_mode; | |
3270 | ||
3271 | if (GET_RTX_CLASS (code) != '<') | |
3272 | return 0; | |
3273 | ||
3274 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3275 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3276 | return 0; | |
3277 | ||
39a10a29 | 3278 | validate_condition_mode (code, cc_mode); |
9878760c | 3279 | |
39a10a29 GK |
3280 | return 1; |
3281 | } | |
3282 | ||
3283 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
3284 | insn and which is true if the corresponding bit in the CC register | |
3285 | is set. */ | |
3286 | ||
3287 | int | |
3288 | branch_positive_comparison_operator (op, mode) | |
3289 | register rtx op; | |
3290 | enum machine_mode mode; | |
3291 | { | |
3292 | enum rtx_code code; | |
3293 | ||
3294 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
3295 | return 0; |
3296 | ||
39a10a29 GK |
3297 | code = GET_CODE (op); |
3298 | return (code == EQ || code == LT || code == GT | |
3299 | || code == LTU || code == GTU | |
3300 | || code == UNORDERED); | |
9878760c RK |
3301 | } |
3302 | ||
39a10a29 | 3303 | |
9878760c RK |
3304 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. |
3305 | We check the opcode against the mode of the CC value and disallow EQ or | |
3306 | NE comparisons for integers. */ | |
3307 | ||
3308 | int | |
3309 | scc_comparison_operator (op, mode) | |
3310 | register rtx op; | |
3311 | enum machine_mode mode; | |
3312 | { | |
3313 | enum rtx_code code = GET_CODE (op); | |
3314 | enum machine_mode cc_mode; | |
3315 | ||
3316 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3317 | return 0; | |
3318 | ||
3319 | if (GET_RTX_CLASS (code) != '<') | |
3320 | return 0; | |
3321 | ||
3322 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3323 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3324 | return 0; | |
3325 | ||
39a10a29 | 3326 | validate_condition_mode (code, cc_mode); |
9878760c | 3327 | |
39a10a29 | 3328 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
3329 | return 0; |
3330 | ||
9878760c RK |
3331 | return 1; |
3332 | } | |
e0cd0770 JC |
3333 | |
3334 | int | |
3335 | trap_comparison_operator (op, mode) | |
3336 | rtx op; | |
3337 | enum machine_mode mode; | |
3338 | { | |
3339 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
3340 | return 0; | |
39a10a29 | 3341 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 3342 | } |
dfbdccdb GK |
3343 | |
3344 | int | |
3345 | boolean_operator (op, mode) | |
3346 | rtx op; | |
3347 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3348 | { | |
3349 | enum rtx_code code = GET_CODE (op); | |
3350 | return (code == AND || code == IOR || code == XOR); | |
3351 | } | |
1d328b19 GK |
3352 | |
3353 | int | |
3354 | boolean_or_operator (op, mode) | |
3355 | rtx op; | |
3356 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3357 | { | |
3358 | enum rtx_code code = GET_CODE (op); | |
3359 | return (code == IOR || code == XOR); | |
3360 | } | |
9878760c RK |
3361 | \f |
3362 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
3363 | mask required to convert the result of a rotate insn into a shift | |
3364 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
3365 | ||
3366 | int | |
3367 | includes_lshift_p (shiftop, andop) | |
3368 | register rtx shiftop; | |
3369 | register rtx andop; | |
3370 | { | |
e2c953b6 DE |
3371 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
3372 | ||
3373 | shift_mask <<= INTVAL (shiftop); | |
9878760c RK |
3374 | |
3375 | return (INTVAL (andop) & ~shift_mask) == 0; | |
3376 | } | |
3377 | ||
3378 | /* Similar, but for right shift. */ | |
3379 | ||
3380 | int | |
3381 | includes_rshift_p (shiftop, andop) | |
3382 | register rtx shiftop; | |
3383 | register rtx andop; | |
3384 | { | |
a7653a2c | 3385 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
3386 | |
3387 | shift_mask >>= INTVAL (shiftop); | |
3388 | ||
e2c953b6 DE |
3389 | return (INTVAL (andop) & ~shift_mask) == 0; |
3390 | } | |
3391 | ||
3392 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
3393 | mask required to convert the result of a rotate insn into a shift | |
3394 | left insn of SHIFTOP bits. */ | |
3395 | ||
3396 | int | |
3397 | includes_lshift64_p (shiftop, andop) | |
3398 | register rtx shiftop; | |
3399 | register rtx andop; | |
3400 | { | |
3401 | #if HOST_BITS_PER_WIDE_INT == 64 | |
3402 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; | |
3403 | ||
3404 | shift_mask <<= INTVAL (shiftop); | |
3405 | ||
3406 | return (INTVAL (andop) & ~shift_mask) == 0; | |
3407 | #else | |
3408 | unsigned HOST_WIDE_INT shift_mask_low = ~(unsigned HOST_WIDE_INT) 0; | |
3409 | unsigned HOST_WIDE_INT shift_mask_high = ~(unsigned HOST_WIDE_INT) 0; | |
3410 | ||
3411 | shift_mask_low <<= INTVAL (shiftop); | |
3412 | ||
3413 | if (INTVAL (shiftop) > 32) | |
3414 | shift_mask_high <<= (INTVAL (shiftop) - 32); | |
3415 | ||
3416 | if (GET_CODE (andop) == CONST_INT) | |
3417 | return (INTVAL (andop) & ~shift_mask_low) == 0; | |
3418 | else | |
3419 | return ((CONST_DOUBLE_HIGH (andop) & ~shift_mask_high) == 0 | |
3420 | && (CONST_DOUBLE_LOW (andop) & ~shift_mask_low) == 0); | |
3421 | #endif | |
9878760c | 3422 | } |
35068b43 RK |
3423 | |
3424 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
3425 | for lfq and stfq insns. | |
3426 | ||
3427 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
3428 | abort if we are passed pseudo registers. */ | |
3429 | ||
3430 | int | |
3431 | registers_ok_for_quad_peep (reg1, reg2) | |
3432 | rtx reg1, reg2; | |
3433 | { | |
3434 | /* We might have been passed a SUBREG. */ | |
3435 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
3436 | return 0; | |
3437 | ||
3438 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
3439 | } | |
3440 | ||
3441 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and | |
3442 | addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */ | |
3443 | ||
3444 | int | |
3445 | addrs_ok_for_quad_peep (addr1, addr2) | |
3446 | register rtx addr1; | |
3447 | register rtx addr2; | |
3448 | { | |
e2c953b6 | 3449 | unsigned int reg1; |
35068b43 RK |
3450 | int offset1; |
3451 | ||
3452 | /* Extract an offset (if used) from the first addr. */ | |
3453 | if (GET_CODE (addr1) == PLUS) | |
3454 | { | |
3455 | /* If not a REG, return zero. */ | |
3456 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
3457 | return 0; | |
3458 | else | |
3459 | { | |
3460 | reg1 = REGNO (XEXP (addr1, 0)); | |
3461 | /* The offset must be constant! */ | |
3462 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
3463 | return 0; | |
3464 | offset1 = INTVAL (XEXP (addr1, 1)); | |
3465 | } | |
3466 | } | |
3467 | else if (GET_CODE (addr1) != REG) | |
3468 | return 0; | |
3469 | else | |
3470 | { | |
3471 | reg1 = REGNO (addr1); | |
3472 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
3473 | offset1 = 0; | |
3474 | } | |
3475 | ||
acad7ed3 | 3476 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
3477 | if (GET_CODE (addr2) != PLUS) |
3478 | return 0; | |
3479 | ||
3480 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
3481 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
3482 | return 0; | |
3483 | ||
3484 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
3485 | return 0; | |
3486 | ||
3487 | /* The offset for the second addr must be 8 more than the first addr. */ | |
3488 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
3489 | return 0; | |
3490 | ||
3491 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
3492 | instructions. */ | |
3493 | return 1; | |
3494 | } | |
9878760c RK |
3495 | \f |
3496 | /* Return the register class of a scratch register needed to copy IN into | |
3497 | or out of a register in CLASS in MODE. If it can be done directly, | |
3498 | NO_REGS is returned. */ | |
3499 | ||
3500 | enum reg_class | |
3501 | secondary_reload_class (class, mode, in) | |
3502 | enum reg_class class; | |
296b8152 | 3503 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3504 | rtx in; |
3505 | { | |
5accd822 | 3506 | int regno; |
9878760c | 3507 | |
3cb999d8 | 3508 | #if TARGET_ELF |
1427100a | 3509 | /* We can not copy a symbolic operand directly into anything other than |
e7b7998a JL |
3510 | BASE_REGS for TARGET_ELF. So indicate that a register from BASE_REGS |
3511 | is needed as an intermediate register. */ | |
3cb999d8 | 3512 | if (class != BASE_REGS |
e7b7998a | 3513 | && (GET_CODE (in) == SYMBOL_REF |
201b6183 | 3514 | || GET_CODE (in) == HIGH |
e7b7998a JL |
3515 | || GET_CODE (in) == LABEL_REF |
3516 | || GET_CODE (in) == CONST)) | |
3517 | return BASE_REGS; | |
3cb999d8 | 3518 | #endif |
e7b7998a | 3519 | |
5accd822 DE |
3520 | if (GET_CODE (in) == REG) |
3521 | { | |
3522 | regno = REGNO (in); | |
3523 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3524 | { | |
3525 | regno = true_regnum (in); | |
3526 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3527 | regno = -1; | |
3528 | } | |
3529 | } | |
3530 | else if (GET_CODE (in) == SUBREG) | |
3531 | { | |
3532 | regno = true_regnum (in); | |
3533 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3534 | regno = -1; | |
3535 | } | |
3536 | else | |
3537 | regno = -1; | |
3538 | ||
9878760c RK |
3539 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
3540 | into anything. */ | |
3541 | if (class == GENERAL_REGS || class == BASE_REGS | |
3542 | || (regno >= 0 && INT_REGNO_P (regno))) | |
3543 | return NO_REGS; | |
3544 | ||
3545 | /* Constants, memory, and FP registers can go into FP registers. */ | |
3546 | if ((regno == -1 || FP_REGNO_P (regno)) | |
3547 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
3548 | return NO_REGS; | |
3549 | ||
3550 | /* We can copy among the CR registers. */ | |
3551 | if ((class == CR_REGS || class == CR0_REGS) | |
3552 | && regno >= 0 && CR_REGNO_P (regno)) | |
3553 | return NO_REGS; | |
3554 | ||
3555 | /* Otherwise, we need GENERAL_REGS. */ | |
3556 | return GENERAL_REGS; | |
3557 | } | |
3558 | \f | |
3559 | /* Given a comparison operation, return the bit number in CCR to test. We | |
3560 | know this is a valid comparison. | |
3561 | ||
3562 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
3563 | used instead of %C, so the bits will be in different places. | |
3564 | ||
b4ac57ab | 3565 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
3566 | |
3567 | int | |
3568 | ccr_bit (op, scc_p) | |
3569 | register rtx op; | |
3570 | int scc_p; | |
3571 | { | |
3572 | enum rtx_code code = GET_CODE (op); | |
3573 | enum machine_mode cc_mode; | |
3574 | int cc_regnum; | |
3575 | int base_bit; | |
9ebbca7d | 3576 | rtx reg; |
9878760c RK |
3577 | |
3578 | if (GET_RTX_CLASS (code) != '<') | |
3579 | return -1; | |
3580 | ||
9ebbca7d GK |
3581 | reg = XEXP (op, 0); |
3582 | ||
3583 | if (GET_CODE (reg) != REG | |
3584 | || ! CR_REGNO_P (REGNO (reg))) | |
3585 | abort (); | |
3586 | ||
3587 | cc_mode = GET_MODE (reg); | |
3588 | cc_regnum = REGNO (reg); | |
3589 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 3590 | |
39a10a29 | 3591 | validate_condition_mode (code, cc_mode); |
c5defebb | 3592 | |
9878760c RK |
3593 | switch (code) |
3594 | { | |
3595 | case NE: | |
3596 | return scc_p ? base_bit + 3 : base_bit + 2; | |
3597 | case EQ: | |
3598 | return base_bit + 2; | |
1c882ea4 | 3599 | case GT: case GTU: case UNLE: |
9878760c | 3600 | return base_bit + 1; |
1c882ea4 | 3601 | case LT: case LTU: case UNGE: |
9878760c | 3602 | return base_bit; |
1c882ea4 GK |
3603 | case ORDERED: case UNORDERED: |
3604 | return base_bit + 3; | |
9878760c RK |
3605 | |
3606 | case GE: case GEU: | |
39a10a29 | 3607 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
3608 | unordered position. So test that bit. For integer, this is ! LT |
3609 | unless this is an scc insn. */ | |
39a10a29 | 3610 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
3611 | |
3612 | case LE: case LEU: | |
39a10a29 | 3613 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 3614 | |
9878760c RK |
3615 | default: |
3616 | abort (); | |
3617 | } | |
3618 | } | |
1ff7789b | 3619 | \f |
8d30c4ee | 3620 | /* Return the GOT register. */ |
1ff7789b MM |
3621 | |
3622 | struct rtx_def * | |
3623 | rs6000_got_register (value) | |
5f59ecb7 | 3624 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 3625 | { |
8d30c4ee FS |
3626 | /* The second flow pass currently (June 1999) can't update regs_ever_live |
3627 | without disturbing other parts of the compiler, so update it here to | |
3628 | make the prolog/epilogue code happy. */ | |
3cb999d8 | 3629 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 3630 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 3631 | |
8d30c4ee | 3632 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 3633 | |
1ff7789b MM |
3634 | return pic_offset_table_rtx; |
3635 | } | |
a7df97e6 MM |
3636 | \f |
3637 | /* Define the structure for the machine field in struct function. */ | |
3638 | struct machine_function | |
3639 | { | |
3640 | int sysv_varargs_p; | |
a7df97e6 MM |
3641 | }; |
3642 | ||
9ebbca7d | 3643 | /* Functions to save and restore sysv_varargs_p. |
a7df97e6 MM |
3644 | These will be called, via pointer variables, |
3645 | from push_function_context and pop_function_context. */ | |
3646 | ||
3647 | void | |
3648 | rs6000_save_machine_status (p) | |
3649 | struct function *p; | |
3650 | { | |
3651 | struct machine_function *machine = | |
3652 | (struct machine_function *) xmalloc (sizeof (struct machine_function)); | |
3653 | ||
3654 | p->machine = machine; | |
3655 | machine->sysv_varargs_p = rs6000_sysv_varargs_p; | |
a7df97e6 MM |
3656 | } |
3657 | ||
3658 | void | |
3659 | rs6000_restore_machine_status (p) | |
3660 | struct function *p; | |
3661 | { | |
3662 | struct machine_function *machine = p->machine; | |
3663 | ||
3664 | rs6000_sysv_varargs_p = machine->sysv_varargs_p; | |
a7df97e6 MM |
3665 | |
3666 | free (machine); | |
3667 | p->machine = (struct machine_function *)0; | |
3668 | } | |
3669 | ||
3670 | /* Do anything needed before RTL is emitted for each function. */ | |
3671 | ||
3672 | void | |
3673 | rs6000_init_expanders () | |
3674 | { | |
9ebbca7d | 3675 | /* Reset varargs */ |
a7df97e6 | 3676 | rs6000_sysv_varargs_p = 0; |
a7df97e6 MM |
3677 | |
3678 | /* Arrange to save and restore machine status around nested functions. */ | |
3679 | save_machine_status = rs6000_save_machine_status; | |
3680 | restore_machine_status = rs6000_restore_machine_status; | |
3681 | } | |
3682 | ||
9878760c RK |
3683 | \f |
3684 | /* Print an operand. Recognize special options, documented below. */ | |
3685 | ||
38c1f2d7 | 3686 | #if TARGET_ELF |
d9407988 | 3687 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 3688 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
3689 | #else |
3690 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 3691 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
3692 | #endif |
3693 | ||
9878760c RK |
3694 | void |
3695 | print_operand (file, x, code) | |
3696 | FILE *file; | |
3697 | rtx x; | |
9ebbca7d | 3698 | int code; |
9878760c RK |
3699 | { |
3700 | int i; | |
a260abc9 | 3701 | HOST_WIDE_INT val; |
9878760c RK |
3702 | |
3703 | /* These macros test for integers and extract the low-order bits. */ | |
3704 | #define INT_P(X) \ | |
3705 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
3706 | && GET_MODE (X) == VOIDmode) | |
3707 | ||
3708 | #define INT_LOWPART(X) \ | |
3709 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
3710 | ||
3711 | switch (code) | |
3712 | { | |
a8b3aeda | 3713 | case '.': |
a85d226b RK |
3714 | /* Write out an instruction after the call which may be replaced |
3715 | with glue code by the loader. This depends on the AIX version. */ | |
3716 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
3717 | return; |
3718 | ||
c81bebd7 MM |
3719 | case '$': |
3720 | /* Write out either a '.' or '$' for the current location, depending | |
3721 | on whether this is Solaris or not. */ | |
3722 | putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file); | |
3723 | return; | |
3724 | ||
81eace42 GK |
3725 | /* %a is output_address. */ |
3726 | ||
9854d9ed RK |
3727 | case 'A': |
3728 | /* If X is a constant integer whose low-order 5 bits are zero, | |
3729 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 3730 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
3731 | write a trash instruction. */ |
3732 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 3733 | putc ('l', file); |
9854d9ed | 3734 | else |
76229ac8 | 3735 | putc ('r', file); |
9854d9ed RK |
3736 | return; |
3737 | ||
3738 | case 'b': | |
e2c953b6 DE |
3739 | /* If constant, low-order 16 bits of constant, unsigned. |
3740 | Otherwise, write normally. */ | |
3741 | if (INT_P (x)) | |
3742 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
3743 | else | |
3744 | print_operand (file, x, 0); | |
cad12a8d RK |
3745 | return; |
3746 | ||
a260abc9 DE |
3747 | case 'B': |
3748 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
3749 | for 64-bit mask direction. */ | |
296b8152 | 3750 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 3751 | return; |
a260abc9 | 3752 | |
81eace42 GK |
3753 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
3754 | output_operand. */ | |
3755 | ||
9854d9ed | 3756 | case 'D': |
39a10a29 GK |
3757 | /* There used to be a comment for 'C' reading "This is an |
3758 | optional cror needed for certain floating-point | |
3759 | comparisons. Otherwise write nothing." */ | |
3760 | ||
9854d9ed RK |
3761 | /* Similar, except that this is for an scc, so we must be able to |
3762 | encode the test in a single bit that is one. We do the above | |
3763 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
3764 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
3765 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
3766 | { | |
9ebbca7d | 3767 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
3768 | |
3769 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
3770 | base_bit + 2, | |
3771 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
3772 | } | |
3773 | ||
3774 | else if (GET_CODE (x) == NE) | |
3775 | { | |
9ebbca7d | 3776 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
3777 | |
3778 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
3779 | base_bit + 2, base_bit + 2); | |
3780 | } | |
3781 | return; | |
3782 | ||
3783 | case 'E': | |
39a10a29 | 3784 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
3785 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
3786 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 3787 | else |
39a10a29 | 3788 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 3789 | return; |
9854d9ed RK |
3790 | |
3791 | case 'f': | |
3792 | /* X is a CR register. Print the shift count needed to move it | |
3793 | to the high-order four bits. */ | |
3794 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
3795 | output_operand_lossage ("invalid %%f value"); | |
3796 | else | |
9ebbca7d | 3797 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
3798 | return; |
3799 | ||
3800 | case 'F': | |
3801 | /* Similar, but print the count for the rotate in the opposite | |
3802 | direction. */ | |
3803 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
3804 | output_operand_lossage ("invalid %%F value"); | |
3805 | else | |
9ebbca7d | 3806 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
3807 | return; |
3808 | ||
3809 | case 'G': | |
3810 | /* X is a constant integer. If it is negative, print "m", | |
3811 | otherwise print "z". This is to make a aze or ame insn. */ | |
3812 | if (GET_CODE (x) != CONST_INT) | |
3813 | output_operand_lossage ("invalid %%G value"); | |
3814 | else if (INTVAL (x) >= 0) | |
76229ac8 | 3815 | putc ('z', file); |
9854d9ed | 3816 | else |
76229ac8 | 3817 | putc ('m', file); |
9854d9ed | 3818 | return; |
e2c953b6 | 3819 | |
9878760c | 3820 | case 'h': |
df3d94ed RK |
3821 | /* If constant, output low-order five bits. Otherwise, |
3822 | write normally. */ | |
9878760c | 3823 | if (INT_P (x)) |
5f59ecb7 | 3824 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
3825 | else |
3826 | print_operand (file, x, 0); | |
3827 | return; | |
3828 | ||
64305719 DE |
3829 | case 'H': |
3830 | /* If constant, output low-order six bits. Otherwise, | |
3831 | write normally. */ | |
3832 | if (INT_P (x)) | |
5f59ecb7 | 3833 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
3834 | else |
3835 | print_operand (file, x, 0); | |
3836 | return; | |
3837 | ||
9854d9ed RK |
3838 | case 'I': |
3839 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 3840 | if (INT_P (x)) |
76229ac8 | 3841 | putc ('i', file); |
9878760c RK |
3842 | return; |
3843 | ||
9854d9ed RK |
3844 | case 'j': |
3845 | /* Write the bit number in CCR for jump. */ | |
3846 | i = ccr_bit (x, 0); | |
3847 | if (i == -1) | |
3848 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 3849 | else |
9854d9ed | 3850 | fprintf (file, "%d", i); |
9878760c RK |
3851 | return; |
3852 | ||
9854d9ed RK |
3853 | case 'J': |
3854 | /* Similar, but add one for shift count in rlinm for scc and pass | |
3855 | scc flag to `ccr_bit'. */ | |
3856 | i = ccr_bit (x, 1); | |
3857 | if (i == -1) | |
3858 | output_operand_lossage ("invalid %%J code"); | |
3859 | else | |
a0466a68 RK |
3860 | /* If we want bit 31, write a shift count of zero, not 32. */ |
3861 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
3862 | return; |
3863 | ||
9854d9ed RK |
3864 | case 'k': |
3865 | /* X must be a constant. Write the 1's complement of the | |
3866 | constant. */ | |
9878760c | 3867 | if (! INT_P (x)) |
9854d9ed | 3868 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
3869 | else |
3870 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
3871 | return; |
3872 | ||
81eace42 | 3873 | case 'K': |
9ebbca7d GK |
3874 | /* X must be a symbolic constant on ELF. Write an |
3875 | expression suitable for an 'addi' that adds in the low 16 | |
3876 | bits of the MEM. */ | |
3877 | if (GET_CODE (x) != CONST) | |
3878 | { | |
3879 | print_operand_address (file, x); | |
3880 | fputs ("@l", file); | |
3881 | } | |
3882 | else | |
3883 | { | |
3884 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
3885 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
3886 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
3887 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 3888 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
3889 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
3890 | fputs ("@l", file); | |
3891 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
3892 | } | |
81eace42 GK |
3893 | return; |
3894 | ||
3895 | /* %l is output_asm_label. */ | |
9ebbca7d | 3896 | |
9854d9ed RK |
3897 | case 'L': |
3898 | /* Write second word of DImode or DFmode reference. Works on register | |
3899 | or non-indexed memory only. */ | |
3900 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 3901 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
3902 | else if (GET_CODE (x) == MEM) |
3903 | { | |
3904 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 3905 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
3906 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
3907 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
19087b1c DE |
3908 | output_address (plus_constant_for_output (XEXP (XEXP (x, 0), 0), |
3909 | UNITS_PER_WORD)); | |
9854d9ed | 3910 | else |
19087b1c DE |
3911 | output_address (plus_constant_for_output (XEXP (x, 0), |
3912 | UNITS_PER_WORD)); | |
ba5e43aa | 3913 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
3914 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
3915 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 3916 | } |
9878760c | 3917 | return; |
9854d9ed | 3918 | |
9878760c RK |
3919 | case 'm': |
3920 | /* MB value for a mask operand. */ | |
3921 | if (! mask_operand (x, VOIDmode)) | |
3922 | output_operand_lossage ("invalid %%m value"); | |
3923 | ||
3924 | val = INT_LOWPART (x); | |
3925 | ||
3926 | /* If the high bit is set and the low bit is not, the value is zero. | |
3927 | If the high bit is zero, the value is the first 1 bit we find from | |
3928 | the left. */ | |
0858c623 | 3929 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 3930 | { |
19d2d16f | 3931 | putc ('0', file); |
9878760c RK |
3932 | return; |
3933 | } | |
0858c623 | 3934 | else if ((val & 0x80000000) == 0) |
9878760c RK |
3935 | { |
3936 | for (i = 1; i < 32; i++) | |
0858c623 | 3937 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
3938 | break; |
3939 | fprintf (file, "%d", i); | |
3940 | return; | |
3941 | } | |
3942 | ||
3943 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
3944 | number plus 1. We know the low-order bit is one. */ | |
3945 | for (i = 0; i < 32; i++) | |
3946 | if (((val >>= 1) & 1) == 0) | |
3947 | break; | |
3948 | ||
a260abc9 | 3949 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
3950 | we want 31 - i. */ |
3951 | fprintf (file, "%d", 31 - i); | |
3952 | return; | |
3953 | ||
3954 | case 'M': | |
3955 | /* ME value for a mask operand. */ | |
3956 | if (! mask_operand (x, VOIDmode)) | |
a260abc9 | 3957 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
3958 | |
3959 | val = INT_LOWPART (x); | |
3960 | ||
3961 | /* If the low bit is set and the high bit is not, the value is 31. | |
3962 | If the low bit is zero, the value is the first 1 bit we find from | |
3963 | the right. */ | |
0858c623 | 3964 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 3965 | { |
76229ac8 | 3966 | fputs ("31", file); |
9878760c RK |
3967 | return; |
3968 | } | |
3969 | else if ((val & 1) == 0) | |
3970 | { | |
3971 | for (i = 0; i < 32; i++) | |
3972 | if ((val >>= 1) & 1) | |
3973 | break; | |
3974 | ||
a260abc9 | 3975 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
3976 | 30, so we need 30 - i. */ |
3977 | fprintf (file, "%d", 30 - i); | |
3978 | return; | |
3979 | } | |
3980 | ||
3981 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
3982 | number minus 1. We know the high-order bit is one. */ | |
3983 | for (i = 0; i < 32; i++) | |
0858c623 | 3984 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
3985 | break; |
3986 | ||
3987 | fprintf (file, "%d", i); | |
3988 | return; | |
3989 | ||
81eace42 GK |
3990 | /* %n outputs the negative of its operand. */ |
3991 | ||
9878760c RK |
3992 | case 'N': |
3993 | /* Write the number of elements in the vector times 4. */ | |
3994 | if (GET_CODE (x) != PARALLEL) | |
3995 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
3996 | else |
3997 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
3998 | return; |
3999 | ||
4000 | case 'O': | |
4001 | /* Similar, but subtract 1 first. */ | |
4002 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 4003 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
4004 | else |
4005 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
4006 | return; |
4007 | ||
9854d9ed RK |
4008 | case 'p': |
4009 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
4010 | if (! INT_P (x) | |
4011 | || (i = exact_log2 (INT_LOWPART (x))) < 0) | |
4012 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
4013 | else |
4014 | fprintf (file, "%d", i); | |
9854d9ed RK |
4015 | return; |
4016 | ||
9878760c RK |
4017 | case 'P': |
4018 | /* The operand must be an indirect memory reference. The result | |
4019 | is the register number. */ | |
4020 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG | |
4021 | || REGNO (XEXP (x, 0)) >= 32) | |
4022 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
4023 | else |
4024 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
4025 | return; |
4026 | ||
dfbdccdb GK |
4027 | case 'q': |
4028 | /* This outputs the logical code corresponding to a boolean | |
4029 | expression. The expression may have one or both operands | |
39a10a29 GK |
4030 | negated (if one, only the first one). For condition register |
4031 | logical operations, it will also treat the negated | |
4032 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 4033 | { |
63bc1d05 | 4034 | const char *const *t = 0; |
dfbdccdb GK |
4035 | const char *s; |
4036 | enum rtx_code code = GET_CODE (x); | |
4037 | static const char * const tbl[3][3] = { | |
4038 | { "and", "andc", "nor" }, | |
4039 | { "or", "orc", "nand" }, | |
4040 | { "xor", "eqv", "xor" } }; | |
4041 | ||
4042 | if (code == AND) | |
4043 | t = tbl[0]; | |
4044 | else if (code == IOR) | |
4045 | t = tbl[1]; | |
4046 | else if (code == XOR) | |
4047 | t = tbl[2]; | |
4048 | else | |
4049 | output_operand_lossage ("invalid %%q value"); | |
4050 | ||
4051 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
4052 | s = t[0]; | |
4053 | else | |
4054 | { | |
4055 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
4056 | s = t[2]; | |
4057 | else | |
4058 | s = t[1]; | |
4059 | } | |
4060 | ||
4061 | fputs (s, file); | |
4062 | } | |
4063 | return; | |
4064 | ||
9854d9ed RK |
4065 | case 'R': |
4066 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
4067 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4068 | output_operand_lossage ("invalid %%R value"); | |
4069 | else | |
9ebbca7d | 4070 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 4071 | return; |
9854d9ed RK |
4072 | |
4073 | case 's': | |
4074 | /* Low 5 bits of 32 - value */ | |
4075 | if (! INT_P (x)) | |
4076 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
4077 | else |
4078 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 4079 | return; |
9854d9ed | 4080 | |
a260abc9 DE |
4081 | case 'S': |
4082 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
4083 | CONST_INT 32-bit mask is considered sign-extended so any | |
4084 | transition must occur within the CONST_INT, not on the boundary. */ | |
4085 | if (! mask64_operand (x, VOIDmode)) | |
4086 | output_operand_lossage ("invalid %%S value"); | |
4087 | ||
4088 | val = INT_LOWPART (x); | |
4089 | ||
4090 | if (val & 1) /* Clear Left */ | |
4091 | { | |
a238cd8b DE |
4092 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4093 | if (!((val >>= 1) & 1)) | |
4094 | break; | |
a260abc9 | 4095 | |
a238cd8b DE |
4096 | #if HOST_BITS_PER_WIDE_INT == 32 |
4097 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4098 | { | |
4099 | val = CONST_DOUBLE_HIGH (x); | |
4100 | ||
4101 | if (val == 0) | |
4102 | --i; | |
4103 | else | |
4104 | for (i = 32; i < 64; i++) | |
4105 | if (!((val >>= 1) & 1)) | |
4106 | break; | |
4107 | } | |
a260abc9 | 4108 | #endif |
a238cd8b DE |
4109 | /* i = index of last set bit from right |
4110 | mask begins at 63 - i from left */ | |
4111 | if (i > 63) | |
4112 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 4113 | |
a260abc9 DE |
4114 | fprintf (file, "%d", 63 - i); |
4115 | return; | |
4116 | } | |
4117 | else /* Clear Right */ | |
4118 | { | |
a238cd8b DE |
4119 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4120 | if ((val >>= 1) & 1) | |
4121 | break; | |
a260abc9 | 4122 | |
a238cd8b | 4123 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
4124 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
4125 | { | |
a238cd8b | 4126 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 4127 | |
a238cd8b | 4128 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 4129 | --i; |
a260abc9 | 4130 | else |
a238cd8b DE |
4131 | for (i = 32; i < 64; i++) |
4132 | if ((val >>= 1) & 1) | |
a260abc9 DE |
4133 | break; |
4134 | } | |
4135 | #endif | |
a238cd8b DE |
4136 | /* i = index of last clear bit from right |
4137 | mask ends at 62 - i from left */ | |
4138 | if (i > 62) | |
4139 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 4140 | |
a238cd8b | 4141 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
4142 | return; |
4143 | } | |
4144 | ||
cccf3bdc DE |
4145 | case 'T': |
4146 | /* Print the symbolic name of a branch target register. */ | |
4147 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
4148 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
4149 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 4150 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
4151 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
4152 | else | |
4153 | fputs ("ctr", file); | |
4154 | return; | |
4155 | ||
9854d9ed | 4156 | case 'u': |
802a0058 | 4157 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
4158 | if (! INT_P (x)) |
4159 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
4160 | else |
4161 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
4162 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
4163 | return; |
4164 | ||
802a0058 MM |
4165 | case 'v': |
4166 | /* High-order 16 bits of constant for use in signed operand. */ | |
4167 | if (! INT_P (x)) | |
4168 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 DE |
4169 | else |
4170 | { | |
4171 | int value = (INT_LOWPART (x) >> 16) & 0xffff; | |
802a0058 | 4172 | |
e2c953b6 DE |
4173 | /* Solaris assembler doesn't like lis 0,0x8000 */ |
4174 | if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0) | |
4175 | fprintf (file, "%d", value | (~0 << 16)); | |
4176 | else | |
4177 | fprintf (file, "0x%x", value); | |
4178 | return; | |
4179 | } | |
802a0058 | 4180 | |
9854d9ed RK |
4181 | case 'U': |
4182 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
4183 | if (GET_CODE (x) == MEM | |
4184 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4185 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 4186 | putc ('u', file); |
9854d9ed | 4187 | return; |
9878760c | 4188 | |
e0cd0770 JC |
4189 | case 'V': |
4190 | /* Print the trap code for this operand. */ | |
4191 | switch (GET_CODE (x)) | |
4192 | { | |
4193 | case EQ: | |
4194 | fputs ("eq", file); /* 4 */ | |
4195 | break; | |
4196 | case NE: | |
4197 | fputs ("ne", file); /* 24 */ | |
4198 | break; | |
4199 | case LT: | |
4200 | fputs ("lt", file); /* 16 */ | |
4201 | break; | |
4202 | case LE: | |
4203 | fputs ("le", file); /* 20 */ | |
4204 | break; | |
4205 | case GT: | |
4206 | fputs ("gt", file); /* 8 */ | |
4207 | break; | |
4208 | case GE: | |
4209 | fputs ("ge", file); /* 12 */ | |
4210 | break; | |
4211 | case LTU: | |
4212 | fputs ("llt", file); /* 2 */ | |
4213 | break; | |
4214 | case LEU: | |
4215 | fputs ("lle", file); /* 6 */ | |
4216 | break; | |
4217 | case GTU: | |
4218 | fputs ("lgt", file); /* 1 */ | |
4219 | break; | |
4220 | case GEU: | |
4221 | fputs ("lge", file); /* 5 */ | |
4222 | break; | |
4223 | default: | |
4224 | abort (); | |
4225 | } | |
4226 | break; | |
4227 | ||
9854d9ed RK |
4228 | case 'w': |
4229 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
4230 | normally. */ | |
4231 | if (INT_P (x)) | |
5f59ecb7 DE |
4232 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
4233 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
4234 | else |
4235 | print_operand (file, x, 0); | |
9878760c RK |
4236 | return; |
4237 | ||
9854d9ed | 4238 | case 'W': |
e2c953b6 DE |
4239 | /* MB value for a PowerPC64 rldic operand. */ |
4240 | if (! rldic_operand (x, VOIDmode)) | |
4241 | output_operand_lossage ("invalid %%W value"); | |
4242 | ||
4243 | val = (GET_CODE (x) == CONST_INT | |
4244 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
4245 | ||
4246 | if (val < 0) | |
4247 | i = -1; | |
9854d9ed | 4248 | else |
e2c953b6 DE |
4249 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4250 | if ((val <<= 1) < 0) | |
4251 | break; | |
4252 | ||
4253 | #if HOST_BITS_PER_WIDE_INT == 32 | |
4254 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
4255 | i += 32; /* zero-extend high-part was all 0's */ | |
4256 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4257 | { | |
4258 | val = CONST_DOUBLE_LOW (x); | |
4259 | ||
4260 | if (val == 0) | |
4261 | abort(); | |
4262 | else if (val < 0) | |
4263 | --i; | |
4264 | else | |
4265 | for ( ; i < 64; i++) | |
4266 | if ((val <<= 1) < 0) | |
4267 | break; | |
4268 | } | |
4269 | #endif | |
4270 | ||
4271 | fprintf (file, "%d", i + 1); | |
9854d9ed | 4272 | return; |
9878760c | 4273 | |
9854d9ed RK |
4274 | case 'X': |
4275 | if (GET_CODE (x) == MEM | |
4276 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0))) | |
76229ac8 | 4277 | putc ('x', file); |
9854d9ed | 4278 | return; |
9878760c | 4279 | |
9854d9ed RK |
4280 | case 'Y': |
4281 | /* Like 'L', for third word of TImode */ | |
4282 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4283 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 4284 | else if (GET_CODE (x) == MEM) |
9878760c | 4285 | { |
9854d9ed RK |
4286 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
4287 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4288 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 4289 | else |
a54d04b7 | 4290 | output_address (plus_constant (XEXP (x, 0), 8)); |
ba5e43aa | 4291 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4292 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4293 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
4294 | } |
4295 | return; | |
9854d9ed | 4296 | |
9878760c | 4297 | case 'z': |
b4ac57ab RS |
4298 | /* X is a SYMBOL_REF. Write out the name preceded by a |
4299 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
4300 | names. If we are configured for System V (or the embedded ABI) on |
4301 | the PowerPC, do not emit the period, since those systems do not use | |
4302 | TOCs and the like. */ | |
9878760c RK |
4303 | if (GET_CODE (x) != SYMBOL_REF) |
4304 | abort (); | |
4305 | ||
b6c9286a MM |
4306 | if (XSTR (x, 0)[0] != '.') |
4307 | { | |
4308 | switch (DEFAULT_ABI) | |
4309 | { | |
4310 | default: | |
4311 | abort (); | |
4312 | ||
4313 | case ABI_AIX: | |
4314 | putc ('.', file); | |
4315 | break; | |
4316 | ||
4317 | case ABI_V4: | |
4318 | case ABI_AIX_NODESC: | |
c81bebd7 | 4319 | case ABI_SOLARIS: |
b6c9286a | 4320 | break; |
b6c9286a MM |
4321 | } |
4322 | } | |
9ebbca7d | 4323 | #if TARGET_AIX |
9878760c | 4324 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
9ebbca7d GK |
4325 | #else |
4326 | assemble_name (file, XSTR (x, 0)); | |
4327 | #endif | |
9878760c RK |
4328 | return; |
4329 | ||
9854d9ed RK |
4330 | case 'Z': |
4331 | /* Like 'L', for last word of TImode. */ | |
4332 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4333 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
4334 | else if (GET_CODE (x) == MEM) |
4335 | { | |
4336 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4337 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4338 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 4339 | else |
a54d04b7 | 4340 | output_address (plus_constant (XEXP (x, 0), 12)); |
ba5e43aa | 4341 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4342 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4343 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4344 | } |
5c23c401 | 4345 | return; |
9854d9ed | 4346 | |
9878760c RK |
4347 | case 0: |
4348 | if (GET_CODE (x) == REG) | |
4349 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
4350 | else if (GET_CODE (x) == MEM) | |
4351 | { | |
4352 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
4353 | know the width from the mode. */ | |
4354 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
4355 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
4356 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4357 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
4358 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
4359 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4360 | else |
a54d04b7 | 4361 | output_address (XEXP (x, 0)); |
9878760c RK |
4362 | } |
4363 | else | |
a54d04b7 | 4364 | output_addr_const (file, x); |
a85d226b | 4365 | return; |
9878760c RK |
4366 | |
4367 | default: | |
4368 | output_operand_lossage ("invalid %%xn code"); | |
4369 | } | |
4370 | } | |
4371 | \f | |
4372 | /* Print the address of an operand. */ | |
4373 | ||
4374 | void | |
4375 | print_operand_address (file, x) | |
4376 | FILE *file; | |
4377 | register rtx x; | |
4378 | { | |
4379 | if (GET_CODE (x) == REG) | |
4697a36c | 4380 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
4381 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
4382 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
4383 | { |
4384 | output_addr_const (file, x); | |
ba5e43aa | 4385 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4386 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4387 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d GK |
4388 | else if (TARGET_TOC) |
4389 | abort(); | |
9878760c RK |
4390 | } |
4391 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
4392 | { | |
4393 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
4394 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
4395 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 4396 | else |
4697a36c MM |
4397 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
4398 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
4399 | } |
4400 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
4401 | { |
4402 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
4403 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4404 | } | |
3cb999d8 DE |
4405 | #if TARGET_ELF |
4406 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
4407 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
4408 | { |
4409 | output_addr_const (file, XEXP (x, 1)); | |
4410 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4411 | } | |
3cb999d8 | 4412 | #endif |
9ebbca7d GK |
4413 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
4414 | { | |
4415 | if (TARGET_AIX) | |
4416 | { | |
4417 | rtx contains_minus = XEXP (x, 1); | |
4418 | rtx minus; | |
4419 | ||
4420 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
4421 | turn it into (sym) for output_addr_const. */ | |
4422 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) | |
4423 | contains_minus = XEXP (contains_minus, 0); | |
4424 | ||
4425 | minus = XEXP (contains_minus, 0); | |
4426 | XEXP (contains_minus, 0) = XEXP (minus, 0); | |
4427 | output_addr_const (file, XEXP (x, 1)); | |
4428 | XEXP (contains_minus, 0) = minus; | |
4429 | } | |
4430 | else | |
4431 | output_addr_const (file, XEXP (x, 1)); | |
4432 | ||
4433 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
4434 | } | |
9878760c RK |
4435 | else |
4436 | abort (); | |
4437 | } | |
4438 | \f | |
39a10a29 GK |
4439 | enum rtx_code |
4440 | rs6000_reverse_condition (mode, code) | |
4441 | enum machine_mode mode; | |
4442 | enum rtx_code code; | |
4443 | { | |
4444 | /* Reversal of FP compares takes care -- an ordered compare | |
4445 | becomes an unordered compare and vice versa. */ | |
4446 | if (mode == CCFPmode) | |
4447 | code = reverse_condition_maybe_unordered (code); | |
4448 | else | |
4449 | code = reverse_condition (code); | |
4450 | } | |
4451 | ||
4452 | ||
4453 | /* Generate a compare for CODE. Return a brand-new rtx that | |
4454 | represents the result of the compare. */ | |
4455 | static rtx | |
4456 | rs6000_generate_compare (code) | |
4457 | enum rtx_code code; | |
4458 | { | |
4459 | enum machine_mode comp_mode; | |
4460 | rtx compare_result; | |
4461 | ||
4462 | if (rs6000_compare_fp_p) | |
4463 | comp_mode = CCFPmode; | |
4464 | else if (code == GTU || code == LTU | |
4465 | || code == GEU || code == LEU) | |
4466 | comp_mode = CCUNSmode; | |
4467 | else | |
4468 | comp_mode = CCmode; | |
4469 | ||
4470 | /* First, the compare. */ | |
4471 | compare_result = gen_reg_rtx (comp_mode); | |
4472 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
4473 | gen_rtx_COMPARE (comp_mode, | |
4474 | rs6000_compare_op0, | |
4475 | rs6000_compare_op1))); | |
4476 | ||
4477 | /* Some kinds of FP comparisons need an OR operation. */ | |
4478 | if (rs6000_compare_fp_p | |
4479 | && (code == LE || code == GE | |
4480 | || code == UNEQ || code == LTGT | |
4481 | || code == UNGT || code == UNLT)) | |
4482 | { | |
4483 | enum rtx_code or1, or2; | |
4484 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
4485 | rtx or_result = gen_reg_rtx (CCEQmode); | |
4486 | ||
4487 | switch (code) | |
4488 | { | |
4489 | case LE: or1 = LT; or2 = EQ; break; | |
4490 | case GE: or1 = GT; or2 = EQ; break; | |
4491 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
4492 | case LTGT: or1 = LT; or2 = GT; break; | |
4493 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
4494 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
4495 | default: abort (); | |
4496 | } | |
4497 | validate_condition_mode (or1, comp_mode); | |
4498 | validate_condition_mode (or2, comp_mode); | |
4499 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
4500 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
4501 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
4502 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
4503 | const_true_rtx); | |
4504 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
4505 | ||
4506 | compare_result = or_result; | |
4507 | code = EQ; | |
4508 | } | |
4509 | ||
4510 | validate_condition_mode (code, GET_MODE (compare_result)); | |
4511 | ||
4512 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
4513 | } | |
4514 | ||
4515 | ||
4516 | /* Emit the RTL for an sCOND pattern. */ | |
4517 | ||
4518 | void | |
4519 | rs6000_emit_sCOND (code, result) | |
4520 | enum rtx_code code; | |
4521 | rtx result; | |
4522 | { | |
4523 | rtx condition_rtx; | |
4524 | enum machine_mode op_mode; | |
4525 | ||
4526 | condition_rtx = rs6000_generate_compare (code); | |
4527 | ||
4528 | op_mode = GET_MODE (rs6000_compare_op0); | |
4529 | if (op_mode == VOIDmode) | |
4530 | op_mode = GET_MODE (rs6000_compare_op1); | |
4531 | ||
4532 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
4533 | { | |
4534 | PUT_MODE (condition_rtx, DImode); | |
4535 | convert_move (result, condition_rtx, 0); | |
4536 | } | |
4537 | else | |
4538 | { | |
4539 | PUT_MODE (condition_rtx, SImode); | |
4540 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
4541 | } | |
4542 | } | |
4543 | ||
4544 | ||
4545 | /* Emit a branch of kind CODE to location LOC. */ | |
4546 | ||
4547 | void | |
4548 | rs6000_emit_cbranch (code, loc) | |
4549 | enum rtx_code code; | |
4550 | rtx loc; | |
4551 | { | |
4552 | rtx condition_rtx, loc_ref; | |
4553 | ||
4554 | condition_rtx = rs6000_generate_compare (code); | |
4555 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
4556 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
4557 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
4558 | loc_ref, pc_rtx))); | |
4559 | } | |
4560 | ||
4561 | ||
12a4e8c5 GK |
4562 | /* Return the string to output a conditional branch to LABEL, which is |
4563 | the operand number of the label, or -1 if the branch is really a | |
4564 | conditional return. | |
4565 | ||
4566 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
4567 | condition code register and its mode specifies what kind of | |
4568 | comparison we made. | |
4569 | ||
4570 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
4571 | ||
4572 | INSN is the insn. */ | |
4573 | ||
4574 | char * | |
4575 | output_cbranch (op, label, reversed, insn) | |
4576 | rtx op; | |
4577 | const char * label; | |
4578 | int reversed; | |
4579 | rtx insn; | |
4580 | { | |
4581 | static char string[64]; | |
4582 | enum rtx_code code = GET_CODE (op); | |
4583 | rtx cc_reg = XEXP (op, 0); | |
4584 | enum machine_mode mode = GET_MODE (cc_reg); | |
4585 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 4586 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
4587 | int really_reversed = reversed ^ need_longbranch; |
4588 | char *s = string; | |
4589 | const char *ccode; | |
4590 | const char *pred; | |
4591 | rtx note; | |
4592 | ||
39a10a29 GK |
4593 | validate_condition_mode (code, mode); |
4594 | ||
4595 | /* Work out which way this really branches. We could use | |
4596 | reverse_condition_maybe_unordered here always but this | |
4597 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 4598 | if (really_reversed) |
39a10a29 | 4599 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 4600 | |
39a10a29 | 4601 | switch (code) |
12a4e8c5 GK |
4602 | { |
4603 | /* Not all of these are actually distinct opcodes, but | |
4604 | we distinguish them for clarity of the resulting assembler. */ | |
4605 | case NE: ccode = "ne"; break; | |
4606 | case EQ: ccode = "eq"; break; | |
4607 | case GE: case GEU: ccode = "ge"; break; | |
4608 | case GT: case GTU: ccode = "gt"; break; | |
4609 | case LE: case LEU: ccode = "le"; break; | |
4610 | case LT: case LTU: ccode = "lt"; break; | |
4611 | case UNORDERED: ccode = "un"; break; | |
4612 | case ORDERED: ccode = "nu"; break; | |
4613 | case UNGE: ccode = "nl"; break; | |
4614 | case UNLE: ccode = "ng"; break; | |
4615 | default: | |
4616 | abort(); | |
4617 | } | |
4618 | ||
94a54f47 GK |
4619 | /* Maybe we have a guess as to how likely the branch is. |
4620 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
4621 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
4622 | if (note != NULL_RTX) | |
4623 | { | |
4624 | /* PROB is the difference from 50%. */ | |
4625 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
4626 | ||
4627 | /* For branches that are very close to 50%, assume not-taken. */ | |
4628 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
4629 | && ((prob > 0) ^ need_longbranch)) | |
4630 | pred = "+"; | |
4631 | else | |
4632 | pred = "-"; | |
4633 | } | |
4634 | else | |
4635 | pred = ""; | |
4636 | ||
4637 | if (label == NULL) | |
94a54f47 | 4638 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 4639 | else |
94a54f47 | 4640 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 4641 | |
37c67319 GK |
4642 | /* We need to escape any '%' characters in the reg_names string. |
4643 | Assume they'd only be the first character... */ | |
4644 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
4645 | *s++ = '%'; | |
94a54f47 | 4646 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
4647 | |
4648 | if (label != NULL) | |
4649 | { | |
4650 | /* If the branch distance was too far, we may have to use an | |
4651 | unconditional branch to go the distance. */ | |
4652 | if (need_longbranch) | |
4653 | s += sprintf (s, ",%c$+8 ; b %s", '%', label); | |
4654 | else | |
4655 | s += sprintf (s, ",%s", label); | |
4656 | } | |
4657 | ||
4658 | return string; | |
4659 | } | |
4660 | \f | |
9878760c RK |
4661 | /* This page contains routines that are used to determine what the function |
4662 | prologue and epilogue code will do and write them out. */ | |
4663 | ||
4664 | /* Return the first fixed-point register that is required to be saved. 32 if | |
4665 | none. */ | |
4666 | ||
4667 | int | |
4668 | first_reg_to_save () | |
4669 | { | |
4670 | int first_reg; | |
4671 | ||
4672 | /* Find lowest numbered live register. */ | |
4673 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
4674 | if (regs_ever_live[first_reg] |
4675 | && (! call_used_regs[first_reg] | |
4676 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
4677 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
4678 | && flag_pic == 1))) | |
9878760c RK |
4679 | break; |
4680 | ||
b5253831 DE |
4681 | if (profile_flag) |
4682 | { | |
4683 | /* AIX must save/restore every register that contains a parameter | |
4684 | before/after the .__mcount call plus an additional register | |
4685 | for the static chain, if needed; use registers from 30 down to 22 | |
4686 | to do this. */ | |
4687 | if (DEFAULT_ABI == ABI_AIX) | |
4688 | { | |
4689 | int last_parm_reg, profile_first_reg; | |
4690 | ||
4691 | /* Figure out last used parameter register. The proper thing | |
4692 | to do is to walk incoming args of the function. A function | |
4693 | might have live parameter registers even if it has no | |
4694 | incoming args. */ | |
4695 | for (last_parm_reg = 10; | |
4696 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
4697 | last_parm_reg--) | |
4698 | ; | |
4699 | ||
4700 | /* Calculate first reg for saving parameter registers | |
4701 | and static chain. | |
4702 | Skip reg 31 which may contain the frame pointer. */ | |
4703 | profile_first_reg = (33 - last_parm_reg | |
4704 | - (current_function_needs_context ? 1 : 0)); | |
4705 | /* Do not save frame pointer if no parameters needs to be saved. */ | |
4706 | if (profile_first_reg == 31) | |
4707 | profile_first_reg = 32; | |
4708 | ||
4709 | if (first_reg > profile_first_reg) | |
4710 | first_reg = profile_first_reg; | |
4711 | } | |
e165f3f0 | 4712 | |
b5253831 DE |
4713 | /* SVR4 may need one register to preserve the static chain. */ |
4714 | else if (current_function_needs_context) | |
4715 | { | |
4716 | /* Skip reg 31 which may contain the frame pointer. */ | |
4717 | if (first_reg > 30) | |
4718 | first_reg = 30; | |
4719 | } | |
4720 | } | |
e165f3f0 | 4721 | |
9878760c RK |
4722 | return first_reg; |
4723 | } | |
4724 | ||
4725 | /* Similar, for FP regs. */ | |
4726 | ||
4727 | int | |
4728 | first_fp_reg_to_save () | |
4729 | { | |
4730 | int first_reg; | |
4731 | ||
4732 | /* Find lowest numbered live register. */ | |
4733 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
4734 | if (regs_ever_live[first_reg]) | |
4735 | break; | |
4736 | ||
4737 | return first_reg; | |
4738 | } | |
4697a36c MM |
4739 | \f |
4740 | /* Calculate the stack information for the current function. This is | |
4741 | complicated by having two separate calling sequences, the AIX calling | |
4742 | sequence and the V.4 calling sequence. | |
4743 | ||
4744 | AIX stack frames look like: | |
a260abc9 | 4745 | 32-bit 64-bit |
4697a36c | 4746 | SP----> +---------------------------------------+ |
a260abc9 | 4747 | | back chain to caller | 0 0 |
4697a36c | 4748 | +---------------------------------------+ |
a260abc9 | 4749 | | saved CR | 4 8 (8-11) |
4697a36c | 4750 | +---------------------------------------+ |
a260abc9 | 4751 | | saved LR | 8 16 |
4697a36c | 4752 | +---------------------------------------+ |
a260abc9 | 4753 | | reserved for compilers | 12 24 |
4697a36c | 4754 | +---------------------------------------+ |
a260abc9 | 4755 | | reserved for binders | 16 32 |
4697a36c | 4756 | +---------------------------------------+ |
a260abc9 | 4757 | | saved TOC pointer | 20 40 |
4697a36c | 4758 | +---------------------------------------+ |
a260abc9 | 4759 | | Parameter save area (P) | 24 48 |
4697a36c | 4760 | +---------------------------------------+ |
a260abc9 | 4761 | | Alloca space (A) | 24+P etc. |
802a0058 | 4762 | +---------------------------------------+ |
a7df97e6 | 4763 | | Local variable space (L) | 24+P+A |
4697a36c | 4764 | +---------------------------------------+ |
a7df97e6 | 4765 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 4766 | +---------------------------------------+ |
a7df97e6 | 4767 | | Save area for GP registers (G) | 24+P+A+X+L |
4697a36c | 4768 | +---------------------------------------+ |
a7df97e6 | 4769 | | Save area for FP registers (F) | 24+P+A+X+L+G |
4697a36c MM |
4770 | +---------------------------------------+ |
4771 | old SP->| back chain to caller's caller | | |
4772 | +---------------------------------------+ | |
4773 | ||
5376a30c KR |
4774 | The required alignment for AIX configurations is two words (i.e., 8 |
4775 | or 16 bytes). | |
4776 | ||
4777 | ||
4697a36c MM |
4778 | V.4 stack frames look like: |
4779 | ||
4780 | SP----> +---------------------------------------+ | |
4781 | | back chain to caller | 0 | |
4782 | +---------------------------------------+ | |
5eb387b8 | 4783 | | caller's saved LR | 4 |
4697a36c MM |
4784 | +---------------------------------------+ |
4785 | | Parameter save area (P) | 8 | |
4786 | +---------------------------------------+ | |
a7df97e6 MM |
4787 | | Alloca space (A) | 8+P |
4788 | +---------------------------------------+ | |
4789 | | Varargs save area (V) | 8+P+A | |
4790 | +---------------------------------------+ | |
4791 | | Local variable space (L) | 8+P+A+V | |
4792 | +---------------------------------------+ | |
4793 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 4794 | +---------------------------------------+ |
a7df97e6 MM |
4795 | | saved CR (C) | 8+P+A+V+L+X |
4796 | +---------------------------------------+ | |
4797 | | Save area for GP registers (G) | 8+P+A+V+L+X+C | |
4798 | +---------------------------------------+ | |
4799 | | Save area for FP registers (F) | 8+P+A+V+L+X+C+G | |
4697a36c MM |
4800 | +---------------------------------------+ |
4801 | old SP->| back chain to caller's caller | | |
4802 | +---------------------------------------+ | |
b6c9286a | 4803 | |
5376a30c KR |
4804 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
4805 | given. (But note below and in sysv4.h that we require only 8 and | |
4806 | may round up the size of our stack frame anyways. The historical | |
4807 | reason is early versions of powerpc-linux which didn't properly | |
4808 | align the stack at program startup. A happy side-effect is that | |
4809 | -mno-eabi libraries can be used with -meabi programs.) | |
4810 | ||
b6c9286a | 4811 | |
5376a30c KR |
4812 | The EABI configuration defaults to the V.4 layout, unless |
4813 | -mcall-aix is used, in which case the AIX layout is used. However, | |
4814 | the stack alignment requirements may differ. If -mno-eabi is not | |
4815 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
4816 | given, the required alignment is 16 bytes. (But see V.4 comment | |
4817 | above.) */ | |
4697a36c | 4818 | |
61b2fbe7 MM |
4819 | #ifndef ABI_STACK_BOUNDARY |
4820 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
4821 | #endif | |
4822 | ||
4697a36c MM |
4823 | rs6000_stack_t * |
4824 | rs6000_stack_info () | |
4825 | { | |
4826 | static rs6000_stack_t info, zero_info; | |
4827 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 4828 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 4829 | enum rs6000_abi abi; |
b6c9286a | 4830 | int total_raw_size; |
4697a36c MM |
4831 | |
4832 | /* Zero all fields portably */ | |
4833 | info = zero_info; | |
4834 | ||
4835 | /* Select which calling sequence */ | |
b6c9286a | 4836 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 4837 | |
4697a36c MM |
4838 | /* Calculate which registers need to be saved & save area size */ |
4839 | info_ptr->first_gp_reg_save = first_reg_to_save (); | |
906fb125 GK |
4840 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
4841 | even if it currently looks like we won't. */ | |
4842 | if (flag_pic == 1 | |
4843 | && (abi == ABI_V4 || abi == ABI_SOLARIS) | |
4844 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) | |
4845 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
4846 | else | |
4847 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
4848 | |
4849 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
4850 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
4851 | ||
4852 | /* Does this function call anything? */ | |
9ebbca7d | 4853 | info_ptr->calls_p = ! current_function_is_leaf; |
b6c9286a | 4854 | |
4697a36c | 4855 | /* Determine if we need to save the link register */ |
9ebbca7d | 4856 | if (regs_ever_live[LINK_REGISTER_REGNUM] |
38c1f2d7 | 4857 | || (DEFAULT_ABI == ABI_AIX && profile_flag) |
4697a36c MM |
4858 | #ifdef TARGET_RELOCATABLE |
4859 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
4860 | #endif | |
4861 | || (info_ptr->first_fp_reg_save != 64 | |
4862 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
24d304eb | 4863 | || (abi == ABI_V4 && current_function_calls_alloca) |
c81bebd7 | 4864 | || (abi == ABI_SOLARIS && current_function_calls_alloca) |
4697a36c MM |
4865 | || info_ptr->calls_p) |
4866 | { | |
4867 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 4868 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
4869 | } |
4870 | ||
9ebbca7d GK |
4871 | /* Determine if we need to save the condition code registers. */ |
4872 | if (regs_ever_live[CR2_REGNO] | |
4873 | || regs_ever_live[CR3_REGNO] | |
4874 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
4875 | { |
4876 | info_ptr->cr_save_p = 1; | |
9ebbca7d | 4877 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c MM |
4878 | info_ptr->cr_size = reg_size; |
4879 | } | |
4880 | ||
4881 | /* Determine various sizes */ | |
4882 | info_ptr->reg_size = reg_size; | |
4883 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
4884 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 DE |
4885 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
4886 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, 8); | |
189e03e3 | 4887 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
b6c9286a MM |
4888 | + info_ptr->gp_size |
4889 | + info_ptr->cr_size | |
4890 | + info_ptr->lr_size | |
9ebbca7d | 4891 | + info_ptr->toc_size, 8); |
b6c9286a | 4892 | |
4697a36c | 4893 | /* Calculate the offsets */ |
24d304eb | 4894 | switch (abi) |
4697a36c | 4895 | { |
b6c9286a | 4896 | case ABI_NONE: |
24d304eb | 4897 | default: |
b6c9286a MM |
4898 | abort (); |
4899 | ||
4900 | case ABI_AIX: | |
4901 | case ABI_AIX_NODESC: | |
4902 | info_ptr->fp_save_offset = - info_ptr->fp_size; | |
4903 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a260abc9 DE |
4904 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
4905 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
4906 | break; |
4907 | ||
4908 | case ABI_V4: | |
c81bebd7 | 4909 | case ABI_SOLARIS: |
b6c9286a MM |
4910 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
4911 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 MM |
4912 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
4913 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
b6c9286a MM |
4914 | info_ptr->lr_save_offset = reg_size; |
4915 | break; | |
4697a36c MM |
4916 | } |
4917 | ||
ff381587 MM |
4918 | total_raw_size = (info_ptr->vars_size |
4919 | + info_ptr->parm_size | |
ff381587 MM |
4920 | + info_ptr->save_size |
4921 | + info_ptr->varargs_size | |
4922 | + info_ptr->fixed_size); | |
4923 | ||
4924 | info_ptr->total_size = RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
4925 | ||
4926 | /* Determine if we need to allocate any stack frame: | |
4927 | ||
4928 | For AIX we need to push the stack if a frame pointer is needed (because | |
4929 | the stack might be dynamically adjusted), if we are debugging, if we | |
9ebbca7d | 4930 | make calls, or if the sum of fp_save, gp_save, and local variables |
ff381587 | 4931 | are more than the space needed to save all non-volatile registers: |
bfc79d3b | 4932 | 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 + 18*8 = 288 (GPR13 reserved). |
ff381587 MM |
4933 | |
4934 | For V.4 we don't have the stack cushion that AIX uses, but assume that | |
4935 | the debugger can handle stackless frames. */ | |
4936 | ||
4937 | if (info_ptr->calls_p) | |
4938 | info_ptr->push_p = 1; | |
4939 | ||
9ebbca7d | 4940 | else if (abi == ABI_V4 || abi == ABI_SOLARIS) |
ff381587 | 4941 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
9ebbca7d | 4942 | || info_ptr->calls_p); |
ff381587 MM |
4943 | |
4944 | else | |
4945 | info_ptr->push_p = (frame_pointer_needed | |
4946 | || write_symbols != NO_DEBUG | |
4947 | || ((total_raw_size - info_ptr->fixed_size) | |
bfc79d3b | 4948 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 4949 | |
4697a36c | 4950 | /* Zero offsets if we're not saving those registers */ |
8dda1a21 | 4951 | if (info_ptr->fp_size == 0) |
4697a36c MM |
4952 | info_ptr->fp_save_offset = 0; |
4953 | ||
8dda1a21 | 4954 | if (info_ptr->gp_size == 0) |
4697a36c MM |
4955 | info_ptr->gp_save_offset = 0; |
4956 | ||
c81fc13e | 4957 | if (! info_ptr->lr_save_p) |
4697a36c MM |
4958 | info_ptr->lr_save_offset = 0; |
4959 | ||
c81fc13e | 4960 | if (! info_ptr->cr_save_p) |
4697a36c MM |
4961 | info_ptr->cr_save_offset = 0; |
4962 | ||
c81fc13e | 4963 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
4964 | info_ptr->toc_save_offset = 0; |
4965 | ||
4697a36c MM |
4966 | return info_ptr; |
4967 | } | |
4968 | ||
4969 | void | |
4970 | debug_stack_info (info) | |
4971 | rs6000_stack_t *info; | |
9878760c | 4972 | { |
d330fd93 | 4973 | const char *abi_string; |
24d304eb | 4974 | |
c81fc13e | 4975 | if (! info) |
4697a36c MM |
4976 | info = rs6000_stack_info (); |
4977 | ||
4978 | fprintf (stderr, "\nStack information for function %s:\n", | |
4979 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
4980 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
4981 | : "<unknown>")); | |
4982 | ||
24d304eb RK |
4983 | switch (info->abi) |
4984 | { | |
b6c9286a MM |
4985 | default: abi_string = "Unknown"; break; |
4986 | case ABI_NONE: abi_string = "NONE"; break; | |
4987 | case ABI_AIX: abi_string = "AIX"; break; | |
4988 | case ABI_AIX_NODESC: abi_string = "AIX"; break; | |
4989 | case ABI_V4: abi_string = "V.4"; break; | |
c81bebd7 | 4990 | case ABI_SOLARIS: abi_string = "Solaris"; break; |
24d304eb RK |
4991 | } |
4992 | ||
4993 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
4994 | ||
4697a36c MM |
4995 | if (info->first_gp_reg_save != 32) |
4996 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
4997 | ||
4998 | if (info->first_fp_reg_save != 64) | |
4999 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 5000 | |
4697a36c MM |
5001 | if (info->lr_save_p) |
5002 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 5003 | |
4697a36c MM |
5004 | if (info->cr_save_p) |
5005 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
5006 | ||
b6c9286a MM |
5007 | if (info->toc_save_p) |
5008 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
5009 | ||
4697a36c MM |
5010 | if (info->push_p) |
5011 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
5012 | ||
5013 | if (info->calls_p) | |
5014 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
5015 | ||
4697a36c MM |
5016 | if (info->gp_save_offset) |
5017 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
5018 | ||
5019 | if (info->fp_save_offset) | |
5020 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
5021 | ||
5022 | if (info->lr_save_offset) | |
5023 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
5024 | ||
5025 | if (info->cr_save_offset) | |
5026 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
5027 | ||
b6c9286a MM |
5028 | if (info->toc_save_offset) |
5029 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
5030 | ||
4697a36c MM |
5031 | if (info->varargs_save_offset) |
5032 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
5033 | ||
5034 | if (info->total_size) | |
5035 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
5036 | ||
5037 | if (info->varargs_size) | |
5038 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
5039 | ||
5040 | if (info->vars_size) | |
5041 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
5042 | ||
5043 | if (info->parm_size) | |
5044 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
5045 | ||
5046 | if (info->fixed_size) | |
5047 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
5048 | ||
5049 | if (info->gp_size) | |
5050 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
5051 | ||
5052 | if (info->fp_size) | |
5053 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
5054 | ||
b6c9286a MM |
5055 | if (info->lr_size) |
5056 | fprintf (stderr, "\tlr_size = %5d\n", info->cr_size); | |
5057 | ||
4697a36c MM |
5058 | if (info->cr_size) |
5059 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
5060 | ||
b6c9286a MM |
5061 | if (info->toc_size) |
5062 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); | |
5063 | ||
4697a36c MM |
5064 | if (info->save_size) |
5065 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
5066 | ||
5067 | if (info->reg_size != 4) | |
5068 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
5069 | ||
5070 | fprintf (stderr, "\n"); | |
9878760c | 5071 | } |
4697a36c | 5072 | \f |
8cd8f856 GK |
5073 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
5074 | static void | |
5075 | rs6000_maybe_dead (insn) | |
5076 | rtx insn; | |
5077 | { | |
5078 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
5079 | const0_rtx, | |
5080 | REG_NOTES (insn)); | |
5081 | } | |
5082 | ||
9ebbca7d | 5083 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 5084 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 5085 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
5086 | |
5087 | void | |
9ebbca7d GK |
5088 | rs6000_emit_load_toc_table (fromprolog) |
5089 | int fromprolog; | |
c7ca610e | 5090 | { |
9ebbca7d GK |
5091 | rtx dest; |
5092 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 5093 | |
9ebbca7d | 5094 | if (TARGET_ELF) |
c7ca610e | 5095 | { |
9ebbca7d GK |
5096 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5097 | && flag_pic == 1) | |
38c1f2d7 | 5098 | { |
9ebbca7d GK |
5099 | rtx temp = (fromprolog |
5100 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5101 | : gen_reg_rtx (Pmode)); | |
5102 | if (TARGET_32BIT) | |
8cd8f856 | 5103 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
9ebbca7d | 5104 | else |
8cd8f856 GK |
5105 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_di (temp))); |
5106 | rs6000_maybe_dead (emit_move_insn (dest, temp)); | |
38c1f2d7 | 5107 | } |
9ebbca7d GK |
5108 | else if (flag_pic == 2) |
5109 | { | |
5110 | char buf[30]; | |
5111 | rtx tempLR = (fromprolog | |
5112 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5113 | : gen_reg_rtx (Pmode)); | |
5114 | rtx temp0 = (fromprolog | |
5115 | ? gen_rtx_REG (Pmode, 0) | |
5116 | : gen_reg_rtx (Pmode)); | |
5117 | rtx symF; | |
5118 | ||
5119 | /* possibly create the toc section */ | |
5120 | if (! toc_initialized) | |
5121 | { | |
5122 | toc_section (); | |
5123 | function_section (current_function_decl); | |
5124 | } | |
5125 | ||
5126 | if (fromprolog) | |
5127 | { | |
5128 | rtx symL; | |
5129 | ||
5130 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
5131 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (buf, -1)); | |
38c1f2d7 | 5132 | |
9ebbca7d GK |
5133 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
5134 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (buf, -1)); | |
38c1f2d7 | 5135 | |
8cd8f856 GK |
5136 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
5137 | symF))); | |
5138 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5139 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
5140 | symL, | |
5141 | symF))); | |
9ebbca7d GK |
5142 | } |
5143 | else | |
5144 | { | |
5145 | rtx tocsym; | |
5146 | static int reload_toc_labelno = 0; | |
5147 | ||
5148 | tocsym = gen_rtx_SYMBOL_REF (Pmode, | |
5149 | ggc_alloc_string (toc_label_name, -1)); | |
38c1f2d7 | 5150 | |
9ebbca7d GK |
5151 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
5152 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (buf, -1)); | |
5153 | ||
8cd8f856 GK |
5154 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
5155 | symF, | |
5156 | tocsym))); | |
5157 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5158 | rs6000_maybe_dead (emit_move_insn (temp0, | |
5159 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 5160 | } |
8cd8f856 | 5161 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
5162 | } |
5163 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
5164 | { | |
5165 | /* This is for AIX code running in non-PIC ELF. */ | |
5166 | char buf[30]; | |
5167 | rtx realsym; | |
38c1f2d7 | 5168 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
9ebbca7d GK |
5169 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (buf, -1)); |
5170 | ||
8cd8f856 GK |
5171 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
5172 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
5173 | } |
5174 | else | |
5175 | abort(); | |
5176 | } | |
5177 | else | |
5178 | { | |
5179 | if (TARGET_32BIT) | |
8cd8f856 | 5180 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 5181 | else |
8cd8f856 | 5182 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
5183 | } |
5184 | } | |
5185 | ||
5186 | int | |
5187 | get_TOC_alias_set () | |
5188 | { | |
5189 | static int set = -1; | |
5190 | if (set == -1) | |
5191 | set = new_alias_set (); | |
5192 | return set; | |
5193 | } | |
5194 | ||
5195 | /* This retuns nonzero if the current function uses the TOC. This is | |
5196 | determined by the presence of (unspec ... 7), which is generated by | |
5197 | the various load_toc_* patterns. */ | |
5198 | int | |
5199 | uses_TOC () | |
5200 | { | |
5201 | rtx insn; | |
38c1f2d7 | 5202 | |
9ebbca7d | 5203 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 5204 | if (INSN_P (insn)) |
9ebbca7d GK |
5205 | { |
5206 | rtx pat = PATTERN (insn); | |
5207 | int i; | |
5208 | ||
8cd8f856 | 5209 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
5210 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
5211 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
5212 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
5213 | return 1; | |
38c1f2d7 | 5214 | } |
9ebbca7d GK |
5215 | return 0; |
5216 | } | |
38c1f2d7 | 5217 | |
9ebbca7d GK |
5218 | rtx |
5219 | create_TOC_reference(symbol) | |
5220 | rtx symbol; | |
5221 | { | |
5222 | return gen_rtx_PLUS (Pmode, | |
5223 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
5224 | gen_rtx_CONST (Pmode, | |
5225 | gen_rtx_MINUS (Pmode, symbol, | |
5226 | gen_rtx_SYMBOL_REF (Pmode, | |
5227 | ggc_alloc_string (toc_label_name, -1))))); | |
5228 | } | |
38c1f2d7 | 5229 | |
9ebbca7d GK |
5230 | #if TARGET_AIX |
5231 | /* __throw will restore its own return address to be the same as the | |
5232 | return address of the function that the throw is being made to. | |
5233 | This is unfortunate, because we want to check the original | |
5234 | return address to see if we need to restore the TOC. | |
5235 | So we have to squirrel it away here. | |
5236 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 5237 | |
9ebbca7d GK |
5238 | Most of this code should be removed by CSE. */ |
5239 | static rtx insn_after_throw; | |
c7ca610e | 5240 | |
9ebbca7d GK |
5241 | /* This does the saving... */ |
5242 | void | |
5243 | rs6000_aix_emit_builtin_unwind_init () | |
5244 | { | |
5245 | rtx mem; | |
5246 | rtx stack_top = gen_reg_rtx (Pmode); | |
5247 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5248 | ||
5249 | insn_after_throw = gen_reg_rtx (SImode); | |
5250 | ||
5251 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
5252 | emit_move_insn (stack_top, mem); | |
5253 | ||
5254 | mem = gen_rtx_MEM (Pmode, | |
5255 | gen_rtx_PLUS (Pmode, stack_top, | |
5256 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
5257 | emit_move_insn (opcode_addr, mem); | |
5258 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
5259 | } |
5260 | ||
9ebbca7d GK |
5261 | /* Emit insns to _restore_ the TOC register, at runtime (specifically in _eh.o). |
5262 | Only used on AIX. | |
5263 | ||
5264 | The idea is that on AIX, function calls look like this: | |
5265 | bl somefunction-trampoline | |
5266 | lwz r2,20(sp) | |
5267 | ||
5268 | and later, | |
5269 | somefunction-trampoline: | |
5270 | stw r2,20(sp) | |
5271 | ... load function address in the count register ... | |
5272 | bctr | |
5273 | or like this, if the linker determines that this is not a cross-module call | |
5274 | and so the TOC need not be restored: | |
5275 | bl somefunction | |
5276 | nop | |
5277 | or like this, if the compiler could determine that this is not a | |
5278 | cross-module call: | |
5279 | bl somefunction | |
5280 | now, the tricky bit here is that register 2 is saved and restored | |
5281 | by the _linker_, so we can't readily generate debugging information | |
5282 | for it. So we need to go back up the call chain looking at the | |
5283 | insns at return addresses to see which calls saved the TOC register | |
5284 | and so see where it gets restored from. | |
5285 | ||
5286 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
5287 | just before the actual epilogue. | |
5288 | ||
5289 | On the bright side, this incurs no space or time overhead unless an | |
5290 | exception is thrown, except for the extra code in libgcc.a. | |
5291 | ||
5292 | The parameter STACKSIZE is a register containing (at runtime) | |
5293 | the amount to be popped off the stack in addition to the stack frame | |
5294 | of this routine (which will be __throw or __rethrow, and so is | |
5295 | guaranteed to have a stack frame). */ | |
5296 | void | |
5297 | rs6000_emit_eh_toc_restore (stacksize) | |
5298 | rtx stacksize; | |
5299 | { | |
5300 | rtx top_of_stack; | |
5301 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
5302 | rtx tocompare = gen_reg_rtx (SImode); | |
5303 | rtx opcode = gen_reg_rtx (SImode); | |
5304 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5305 | rtx mem; | |
5306 | rtx loop_start = gen_label_rtx (); | |
5307 | rtx no_toc_restore_needed = gen_label_rtx (); | |
5308 | rtx loop_exit = gen_label_rtx (); | |
5309 | ||
5310 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
5311 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5312 | emit_move_insn (bottom_of_stack, mem); | |
5313 | ||
5314 | top_of_stack = expand_binop (Pmode, add_optab, | |
5315 | bottom_of_stack, stacksize, | |
5316 | NULL_RTX, 1, OPTAB_WIDEN); | |
5317 | ||
5318 | emit_move_insn (tocompare, | |
5319 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
5320 | ? 0x80410014 | |
5321 | : 0xE8410028, SImode))); | |
5322 | ||
5323 | if (insn_after_throw == NULL_RTX) | |
5324 | abort(); | |
5325 | emit_move_insn (opcode, insn_after_throw); | |
5326 | ||
5327 | emit_note (NULL_PTR, NOTE_INSN_LOOP_BEG); | |
5328 | emit_label (loop_start); | |
5329 | ||
5330 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
5331 | SImode, NULL_RTX, 0, NULL_RTX, | |
5332 | no_toc_restore_needed); | |
5333 | ||
5334 | mem = gen_rtx_MEM (Pmode, | |
5335 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
5336 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
5337 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
5338 | ||
5339 | emit_label (no_toc_restore_needed); | |
5340 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
5341 | Pmode, NULL_RTX, 0, NULL_RTX, | |
5342 | loop_exit); | |
5343 | ||
5344 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
5345 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5346 | emit_move_insn (bottom_of_stack, mem); | |
5347 | ||
5348 | mem = gen_rtx_MEM (Pmode, | |
5349 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
5350 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
5351 | emit_move_insn (opcode_addr, mem); | |
5352 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
5353 | ||
5354 | emit_note (NULL_PTR, NOTE_INSN_LOOP_CONT); | |
5355 | emit_jump (loop_start); | |
5356 | emit_note (NULL_PTR, NOTE_INSN_LOOP_END); | |
5357 | emit_label (loop_exit); | |
5358 | } | |
5359 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 5360 | \f |
9ebbca7d GK |
5361 | /* This ties together stack memory |
5362 | (MEM with an alias set of rs6000_sr_alias_set) | |
5363 | and the change to the stack pointer. */ | |
5364 | static void | |
5365 | rs6000_emit_stack_tie () | |
5366 | { | |
5367 | rtx mem; | |
5368 | mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); | |
5369 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5370 | emit_insn (gen_stack_tie (mem)); | |
5371 | } | |
38c1f2d7 | 5372 | |
9ebbca7d GK |
5373 | /* Emit the correct code for allocating stack space, as insns. |
5374 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
5375 | The generated code may use hard register 0 as a temporary. */ | |
5376 | ||
5377 | static void | |
5378 | rs6000_emit_allocate_stack (size, copy_r12) | |
5379 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
5380 | int copy_r12; |
5381 | { | |
9ebbca7d GK |
5382 | rtx insn; |
5383 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
5384 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
5385 | rtx todec = GEN_INT (-size); | |
a157febd GK |
5386 | |
5387 | if (current_function_limit_stack) | |
5388 | { | |
5389 | if (REG_P (stack_limit_rtx) | |
5390 | && REGNO (stack_limit_rtx) > 1 | |
5391 | && REGNO (stack_limit_rtx) <= 31) | |
5392 | { | |
9ebbca7d GK |
5393 | emit_insn (Pmode == SImode |
5394 | ? gen_addsi3 (tmp_reg, | |
5395 | stack_limit_rtx, | |
5396 | GEN_INT (size)) | |
5397 | : gen_adddi3 (tmp_reg, | |
5398 | stack_limit_rtx, | |
5399 | GEN_INT (size))); | |
5400 | ||
5401 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
5402 | const0_rtx)); | |
a157febd GK |
5403 | } |
5404 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 5405 | && TARGET_32BIT |
a157febd GK |
5406 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) |
5407 | { | |
9ebbca7d GK |
5408 | rtx toload = gen_rtx_CONST (VOIDmode, |
5409 | gen_rtx_PLUS (Pmode, | |
5410 | stack_limit_rtx, | |
5411 | GEN_INT (size))); | |
5412 | ||
5413 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
5414 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
5415 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
5416 | const0_rtx)); | |
a157febd GK |
5417 | } |
5418 | else | |
5419 | warning ("stack limit expression is not supported"); | |
5420 | } | |
5421 | ||
9ebbca7d GK |
5422 | if (copy_r12 || ! TARGET_UPDATE) |
5423 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
5424 | ||
38c1f2d7 MM |
5425 | if (TARGET_UPDATE) |
5426 | { | |
9ebbca7d | 5427 | if (size > 32767) |
38c1f2d7 | 5428 | { |
9ebbca7d GK |
5429 | /* Need a note here so that try_split doesn't get confused. */ |
5430 | if (get_last_insn() == NULL_RTX) | |
5431 | emit_note (0, NOTE_INSN_DELETED); | |
5432 | insn = emit_move_insn (tmp_reg, todec); | |
5433 | try_split (PATTERN (insn), insn, 0); | |
5434 | todec = tmp_reg; | |
38c1f2d7 | 5435 | } |
9ebbca7d GK |
5436 | |
5437 | if (Pmode == SImode) | |
5438 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
5439 | todec, stack_reg)); | |
5440 | else | |
5441 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
5442 | todec, stack_reg)); | |
38c1f2d7 MM |
5443 | } |
5444 | else | |
5445 | { | |
9ebbca7d GK |
5446 | if (Pmode == SImode) |
5447 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 5448 | else |
9ebbca7d GK |
5449 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
5450 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
5451 | gen_rtx_REG (Pmode, 12)); | |
5452 | } | |
5453 | ||
5454 | RTX_FRAME_RELATED_P (insn) = 1; | |
5455 | REG_NOTES (insn) = | |
5456 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
5457 | gen_rtx_SET (VOIDmode, stack_reg, | |
5458 | gen_rtx_PLUS (Pmode, stack_reg, | |
5459 | GEN_INT (-size))), | |
5460 | REG_NOTES (insn)); | |
5461 | } | |
5462 | ||
5463 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced with | |
5464 | (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 is not | |
5465 | NULL. | |
5466 | It would be nice if dwarf2out_frame_debug_expr could deduce these | |
5467 | equivalences by itself so it wasn't necessary to hold its hand so much. */ | |
5468 | ||
5469 | static void | |
5470 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
5471 | rtx insn; | |
5472 | rtx reg; | |
5473 | HOST_WIDE_INT val; | |
5474 | rtx reg2; | |
5475 | rtx rreg; | |
5476 | { | |
5477 | rtx real, temp; | |
5478 | ||
5479 | real = copy_rtx (PATTERN (insn)); | |
5480 | ||
5481 | real = replace_rtx (real, reg, | |
5482 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
5483 | STACK_POINTER_REGNUM), | |
5484 | GEN_INT (val))); | |
5485 | ||
5486 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
5487 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
5488 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
5489 | ||
5490 | if (GET_CODE (real) == SET) | |
5491 | { | |
5492 | rtx set = real; | |
5493 | ||
5494 | temp = simplify_rtx (SET_SRC (set)); | |
5495 | if (temp) | |
5496 | SET_SRC (set) = temp; | |
5497 | temp = simplify_rtx (SET_DEST (set)); | |
5498 | if (temp) | |
5499 | SET_DEST (set) = temp; | |
5500 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 5501 | { |
9ebbca7d GK |
5502 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
5503 | if (temp) | |
5504 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 5505 | } |
38c1f2d7 | 5506 | } |
9ebbca7d GK |
5507 | else if (GET_CODE (real) == PARALLEL) |
5508 | { | |
5509 | int i; | |
5510 | for (i = 0; i < XVECLEN (real, 0); i++) | |
5511 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
5512 | { | |
5513 | rtx set = XVECEXP (real, 0, i); | |
5514 | ||
5515 | temp = simplify_rtx (SET_SRC (set)); | |
5516 | if (temp) | |
5517 | SET_SRC (set) = temp; | |
5518 | temp = simplify_rtx (SET_DEST (set)); | |
5519 | if (temp) | |
5520 | SET_DEST (set) = temp; | |
5521 | if (GET_CODE (SET_DEST (set)) == MEM) | |
5522 | { | |
5523 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
5524 | if (temp) | |
5525 | XEXP (SET_DEST (set), 0) = temp; | |
5526 | } | |
5527 | RTX_FRAME_RELATED_P (set) = 1; | |
5528 | } | |
5529 | } | |
5530 | else | |
5531 | abort(); | |
5532 | ||
5533 | if (reg2 != NULL_RTX) | |
5534 | real = replace_rtx (real, reg2, rreg); | |
5535 | ||
5536 | RTX_FRAME_RELATED_P (insn) = 1; | |
5537 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
5538 | real, | |
5539 | REG_NOTES (insn)); | |
38c1f2d7 MM |
5540 | } |
5541 | ||
9ebbca7d GK |
5542 | /* Emit function prologue as insns. */ |
5543 | ||
9878760c | 5544 | void |
9ebbca7d | 5545 | rs6000_emit_prologue() |
9878760c | 5546 | { |
4697a36c | 5547 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
5548 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
5549 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
5550 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
5551 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
5552 | rtx frame_reg_rtx = sp_reg_rtx; | |
5553 | rtx cr_save_rtx = NULL; | |
5554 | rtx insn; | |
5555 | int saving_FPRs_inline; | |
5556 | int using_store_multiple; | |
5557 | HOST_WIDE_INT sp_offset = 0; | |
5558 | ||
5559 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
5560 | && info->first_gp_reg_save < 31); | |
5561 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
5562 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
5563 | ||
5564 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
5565 | if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) | |
5566 | { | |
5567 | if (info->total_size < 32767) | |
5568 | sp_offset = info->total_size; | |
5569 | else | |
5570 | frame_reg_rtx = frame_ptr_rtx; | |
5571 | rs6000_emit_allocate_stack (info->total_size, | |
5572 | (frame_reg_rtx != sp_reg_rtx | |
5573 | && (info->cr_save_p | |
5574 | || info->lr_save_p | |
5575 | || info->first_fp_reg_save < 64 | |
5576 | || info->first_gp_reg_save < 32 | |
5577 | ))); | |
5578 | if (frame_reg_rtx != sp_reg_rtx) | |
5579 | rs6000_emit_stack_tie (); | |
5580 | } | |
5581 | ||
5582 | /* If we use the link register, get it into r0. */ | |
5583 | if (info->lr_save_p) | |
5584 | emit_move_insn (gen_rtx_REG (Pmode, 0), | |
5585 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
5586 | ||
5587 | /* If we need to save CR, put it into r12. */ | |
5588 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
5589 | { | |
5590 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
5591 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
5592 | } | |
5593 | ||
5594 | /* Do any required saving of fpr's. If only one or two to save, do it | |
5595 | ourself. Otherwise, call function. */ | |
5596 | if (saving_FPRs_inline) | |
5597 | { | |
5598 | int i; | |
5599 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
5600 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
5601 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
5602 | { | |
5603 | rtx addr, reg, mem; | |
5604 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
5605 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5606 | GEN_INT (info->fp_save_offset | |
5607 | + sp_offset | |
5608 | + 8*i)); | |
5609 | mem = gen_rtx_MEM (DFmode, addr); | |
5610 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5611 | ||
5612 | insn = emit_move_insn (mem, reg); | |
5613 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
5614 | NULL_RTX, NULL_RTX); | |
5615 | } | |
5616 | } | |
5617 | else if (info->first_fp_reg_save != 64) | |
5618 | { | |
5619 | int i; | |
5620 | char rname[30]; | |
5621 | char *alloc_rname; | |
5622 | rtvec p; | |
5623 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
5624 | ||
5625 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
5626 | gen_rtx_REG (Pmode, | |
5627 | LINK_REGISTER_REGNUM)); | |
5628 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
5629 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
5630 | alloc_rname = ggc_alloc_string (rname, -1); | |
5631 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
5632 | gen_rtx_SYMBOL_REF (Pmode, | |
5633 | alloc_rname)); | |
5634 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
5635 | { | |
5636 | rtx addr, reg, mem; | |
5637 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
5638 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5639 | GEN_INT (info->fp_save_offset | |
5640 | + sp_offset + 8*i)); | |
5641 | mem = gen_rtx_MEM (DFmode, addr); | |
5642 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5643 | ||
5644 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
5645 | } | |
5646 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
5647 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
5648 | NULL_RTX, NULL_RTX); | |
5649 | } | |
b6c9286a | 5650 | |
9ebbca7d GK |
5651 | /* Save GPRs. This is done as a PARALLEL if we are using |
5652 | the store-multiple instructions. */ | |
5653 | if (using_store_multiple) | |
b6c9286a | 5654 | { |
9ebbca7d GK |
5655 | rtvec p, dwarfp; |
5656 | int i; | |
5657 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
5658 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
5659 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
5660 | { | |
5661 | rtx addr, reg, mem; | |
5662 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
5663 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5664 | GEN_INT (info->gp_save_offset | |
5665 | + sp_offset | |
5666 | + reg_size * i)); | |
5667 | mem = gen_rtx_MEM (reg_mode, addr); | |
5668 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5669 | ||
5670 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
5671 | } | |
5672 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
5673 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
5674 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
5675 | } |
5676 | else | |
5677 | { | |
9ebbca7d GK |
5678 | int i; |
5679 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
5680 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
5681 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
5682 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
5683 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
5684 | && flag_pic == 1)) | |
5685 | { | |
5686 | rtx addr, reg, mem; | |
5687 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
5688 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5689 | GEN_INT (info->gp_save_offset | |
5690 | + sp_offset | |
5691 | + reg_size * i)); | |
5692 | mem = gen_rtx_MEM (reg_mode, addr); | |
5693 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5694 | ||
5695 | insn = emit_move_insn (mem, reg); | |
5696 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
5697 | NULL_RTX, NULL_RTX); | |
5698 | } | |
5699 | } | |
5700 | ||
5701 | /* Save lr if we used it. */ | |
5702 | if (info->lr_save_p) | |
5703 | { | |
5704 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5705 | GEN_INT (info->lr_save_offset + sp_offset)); | |
5706 | rtx reg = gen_rtx_REG (Pmode, 0); | |
5707 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
5708 | /* This should not be of rs6000_sr_alias_set, because of | |
5709 | __builtin_return_address. */ | |
5710 | ||
5711 | insn = emit_move_insn (mem, reg); | |
5712 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
5713 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
5714 | } | |
5715 | ||
5716 | /* Save CR if we use any that must be preserved. */ | |
5717 | if (info->cr_save_p) | |
5718 | { | |
5719 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5720 | GEN_INT (info->cr_save_offset + sp_offset)); | |
5721 | rtx mem = gen_rtx_MEM (SImode, addr); | |
5722 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5723 | ||
5724 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
5725 | that it's free. */ | |
5726 | if (REGNO (frame_reg_rtx) == 12) | |
5727 | { | |
5728 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
5729 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
5730 | } | |
5731 | insn = emit_move_insn (mem, cr_save_rtx); | |
5732 | ||
5733 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
5734 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
5735 | OK. All we have to do is specify that _one_ condition code | |
5736 | register is saved in this stack slot. The thrower's epilogue | |
5737 | will then restore all the call-saved registers. */ | |
5738 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
5739 | cr_save_rtx, gen_rtx_REG (SImode, CR0_REGNO)); | |
5740 | } | |
5741 | ||
5742 | /* Update stack and set back pointer unless this is V.4, | |
5743 | for which it was done previously. */ | |
5744 | if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) | |
5745 | rs6000_emit_allocate_stack (info->total_size, FALSE); | |
5746 | ||
5747 | /* Set frame pointer, if needed. */ | |
5748 | if (frame_pointer_needed) | |
5749 | { | |
5750 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
5751 | sp_reg_rtx); | |
5752 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 5753 | } |
9878760c | 5754 | |
9ebbca7d GK |
5755 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
5756 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
5757 | || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
5758 | && flag_pic == 1 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
5759 | { | |
5760 | /* If emit_load_toc_table will use the link register, we need to save | |
5761 | it. We use R11 for this purpose because emit_load_toc_table | |
5762 | can use register 0. This allows us to use a plain 'blr' to return | |
5763 | from the procedure more often. */ | |
5764 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 && | |
5765 | ! info->lr_save_p); | |
5766 | if (save_LR_around_toc_setup) | |
5767 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
5768 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
5769 | ||
5770 | rs6000_emit_load_toc_table (TRUE); | |
5771 | ||
5772 | if (save_LR_around_toc_setup) | |
5773 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
5774 | gen_rtx_REG (Pmode, 11)); | |
5775 | } | |
5776 | } | |
5777 | ||
5778 | ||
5779 | /* Write function prologue. */ | |
5780 | void | |
5781 | output_prolog (file, size) | |
5782 | FILE *file; | |
5783 | int size ATTRIBUTE_UNUSED; | |
5784 | { | |
5785 | rs6000_stack_t *info = rs6000_stack_info (); | |
5786 | ||
4697a36c MM |
5787 | if (TARGET_DEBUG_STACK) |
5788 | debug_stack_info (info); | |
9878760c RK |
5789 | |
5790 | /* Write .extern for any function we will call to save and restore fp | |
5791 | values. */ | |
b6c9286a | 5792 | if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) |
4d30c363 | 5793 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c MM |
5794 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
5795 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
9878760c RK |
5796 | |
5797 | /* Write .extern for truncation routines, if needed. */ | |
5798 | if (rs6000_trunc_used && ! trunc_defined) | |
5799 | { | |
e138174b ILT |
5800 | fprintf (file, "\t.extern .%s\n\t.extern .%s\n", |
5801 | RS6000_ITRUNC, RS6000_UITRUNC); | |
9878760c RK |
5802 | trunc_defined = 1; |
5803 | } | |
4697a36c | 5804 | |
c764f757 RK |
5805 | /* Write .extern for AIX common mode routines, if needed. */ |
5806 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
5807 | { | |
f6709c70 JW |
5808 | fputs ("\t.extern __mulh\n", file); |
5809 | fputs ("\t.extern __mull\n", file); | |
5810 | fputs ("\t.extern __divss\n", file); | |
5811 | fputs ("\t.extern __divus\n", file); | |
5812 | fputs ("\t.extern __quoss\n", file); | |
5813 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
5814 | common_mode_defined = 1; |
5815 | } | |
9878760c | 5816 | |
9ebbca7d | 5817 | if (! HAVE_prologue) |
979721f8 | 5818 | { |
9ebbca7d GK |
5819 | start_sequence (); |
5820 | ||
5821 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
5822 | and end of the "toplevel" insn chain. */ | |
5823 | emit_note (0, NOTE_INSN_DELETED); | |
5824 | rs6000_emit_prologue (); | |
5825 | emit_note (0, NOTE_INSN_DELETED); | |
5826 | ||
5827 | if (TARGET_DEBUG_STACK) | |
5828 | debug_rtx_list (get_insns(), 100); | |
5829 | final (get_insns(), file, FALSE, FALSE); | |
5830 | end_sequence (); | |
979721f8 MM |
5831 | } |
5832 | ||
9ebbca7d GK |
5833 | rs6000_pic_labelno++; |
5834 | } | |
5835 | ||
5836 | /* Emit function epilogue as insns. | |
9878760c | 5837 | |
9ebbca7d GK |
5838 | At present, dwarf2out_frame_debug_expr doesn't understand |
5839 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
5840 | anywhere in the epilogue. Most of the insns below would in any case | |
5841 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 5842 | |
9ebbca7d GK |
5843 | void |
5844 | rs6000_emit_epilogue(sibcall) | |
5845 | int sibcall; | |
5846 | { | |
5847 | rs6000_stack_t *info; | |
5848 | int restoring_FPRs_inline; | |
5849 | int using_load_multiple; | |
5850 | int using_mfcr_multiple; | |
5851 | int use_backchain_to_restore_sp; | |
5852 | int sp_offset = 0; | |
5853 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
5854 | rtx frame_reg_rtx = sp_reg_rtx; | |
5855 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
5856 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
5857 | int i; | |
5858 | ||
5859 | info = rs6000_stack_info (); | |
5860 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
5861 | && info->first_gp_reg_save < 31); | |
5862 | restoring_FPRs_inline = (sibcall | |
5863 | || info->first_fp_reg_save == 64 | |
5864 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
5865 | use_backchain_to_restore_sp = (frame_pointer_needed | |
5866 | || current_function_calls_alloca | |
5867 | || info->total_size > 32767); | |
5868 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
5869 | || rs6000_cpu == PROCESSOR_PPC603 | |
5870 | || rs6000_cpu == PROCESSOR_PPC750 | |
5871 | || optimize_size); | |
5872 | ||
5873 | /* If we have a frame pointer, a call to alloca, or a large stack | |
5874 | frame, restore the old stack pointer using the backchain. Otherwise, | |
5875 | we know what size to update it with. */ | |
5876 | if (use_backchain_to_restore_sp) | |
bacbde18 | 5877 | { |
9ebbca7d GK |
5878 | /* Under V.4, don't reset the stack pointer until after we're done |
5879 | loading the saved registers. */ | |
5880 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
5881 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
4697a36c | 5882 | |
9ebbca7d GK |
5883 | emit_move_insn (frame_reg_rtx, |
5884 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
5885 | ||
bacbde18 | 5886 | } |
9ebbca7d | 5887 | else if (info->push_p) |
85638c0d | 5888 | { |
9ebbca7d GK |
5889 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5890 | sp_offset = info->total_size; | |
5891 | else | |
5892 | { | |
5893 | emit_insn (TARGET_32BIT | |
5894 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
5895 | GEN_INT (info->total_size)) | |
5896 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
5897 | GEN_INT (info->total_size))); | |
5898 | } | |
85638c0d | 5899 | } |
9ebbca7d GK |
5900 | |
5901 | /* Get the old lr if we saved it. */ | |
5902 | if (info->lr_save_p) | |
b6c9286a | 5903 | { |
9ebbca7d GK |
5904 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
5905 | GEN_INT (info->lr_save_offset + sp_offset)); | |
5906 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
5907 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
b6c9286a | 5908 | |
9ebbca7d | 5909 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 5910 | } |
9ebbca7d GK |
5911 | |
5912 | /* Get the old cr if we saved it. */ | |
5913 | if (info->cr_save_p) | |
5914 | { | |
5915 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5916 | GEN_INT (info->cr_save_offset + sp_offset)); | |
5917 | rtx mem = gen_rtx_MEM (SImode, addr); | |
5918 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
b6c9286a | 5919 | |
9ebbca7d GK |
5920 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
5921 | } | |
5922 | ||
5923 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 5924 | if (info->lr_save_p) |
9ebbca7d GK |
5925 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
5926 | gen_rtx_REG (Pmode, 0)); | |
5927 | ||
5928 | ||
5929 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
5930 | the load-multiple instructions. */ | |
5931 | if (using_load_multiple) | |
979721f8 | 5932 | { |
9ebbca7d GK |
5933 | rtvec p; |
5934 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
5935 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 5936 | { |
9ebbca7d GK |
5937 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
5938 | GEN_INT (info->gp_save_offset | |
5939 | + sp_offset | |
5940 | + reg_size * i)); | |
5941 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
5942 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5943 | ||
5944 | RTVEC_ELT (p, i) = | |
5945 | gen_rtx_SET (VOIDmode, | |
5946 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
5947 | mem); | |
979721f8 | 5948 | } |
9ebbca7d | 5949 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 5950 | } |
9ebbca7d GK |
5951 | else |
5952 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
5953 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
5954 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
5955 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
5956 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
5957 | && flag_pic == 1)) | |
5958 | { | |
5959 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5960 | GEN_INT (info->gp_save_offset | |
5961 | + sp_offset | |
5962 | + reg_size * i)); | |
5963 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
5964 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5965 | ||
5966 | emit_move_insn (gen_rtx_REG (reg_mode, | |
5967 | info->first_gp_reg_save + i), | |
5968 | mem); | |
5969 | } | |
9878760c | 5970 | |
9ebbca7d GK |
5971 | /* Restore fpr's if we need to do it without calling a function. */ |
5972 | if (restoring_FPRs_inline) | |
5973 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
5974 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
5975 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
5976 | { | |
5977 | rtx addr, mem; | |
5978 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5979 | GEN_INT (info->fp_save_offset | |
5980 | + sp_offset | |
5981 | + 8*i)); | |
5982 | mem = gen_rtx_MEM (DFmode, addr); | |
5983 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5984 | ||
5985 | emit_move_insn (gen_rtx_REG (DFmode, | |
5986 | info->first_fp_reg_save + i), | |
5987 | mem); | |
5988 | } | |
8d30c4ee | 5989 | |
9ebbca7d GK |
5990 | /* If we saved cr, restore it here. Just those that were used. */ |
5991 | if (info->cr_save_p) | |
979721f8 | 5992 | { |
9ebbca7d GK |
5993 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
5994 | ||
5995 | if (using_mfcr_multiple) | |
979721f8 | 5996 | { |
9ebbca7d GK |
5997 | rtvec p; |
5998 | int mask = 0; | |
5999 | int count = 0; | |
6000 | ||
6001 | for (i = 0; i < 8; i++) | |
6002 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
6003 | { | |
6004 | mask |= 1 << (7-i); | |
6005 | count++; | |
6006 | } | |
6007 | if (count == 0) | |
6008 | abort(); | |
6009 | ||
6010 | p = rtvec_alloc (count + 1); | |
6011 | ||
6012 | RTVEC_ELT (p, 0) = gen_rtx_USE (VOIDmode, GEN_INT (mask)); | |
6013 | count = 1; | |
6014 | for (i = 0; i < 8; i++) | |
6015 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
6016 | { | |
6017 | rtvec r = rtvec_alloc (2); | |
6018 | RTVEC_ELT (r, 0) = r12_rtx; | |
6019 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
6020 | RTVEC_ELT (p, count) = | |
6021 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), | |
6022 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
6023 | count++; | |
6024 | } | |
6025 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
979721f8 MM |
6026 | } |
6027 | else | |
9ebbca7d GK |
6028 | for (i = 0; i < 8; i++) |
6029 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 6030 | { |
9ebbca7d GK |
6031 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
6032 | CR0_REGNO+i), | |
6033 | r12_rtx)); | |
979721f8 | 6034 | } |
979721f8 MM |
6035 | } |
6036 | ||
9ebbca7d GK |
6037 | /* If this is V.4, unwind the stack pointer after all of the loads |
6038 | have been done. We need to emit a block here so that sched | |
6039 | doesn't decide to move the sp change before the register restores | |
6040 | (which may not have any obvious dependency on the stack). This | |
6041 | doesn't hurt performance, because there is no scheduling that can | |
6042 | be done after this point. */ | |
6043 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
b6c9286a | 6044 | { |
9ebbca7d GK |
6045 | if (frame_reg_rtx != sp_reg_rtx) |
6046 | rs6000_emit_stack_tie (); | |
b6c9286a | 6047 | |
9ebbca7d | 6048 | if (use_backchain_to_restore_sp) |
b6c9286a | 6049 | { |
9ebbca7d | 6050 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 6051 | } |
9ebbca7d | 6052 | else if (sp_offset != 0) |
13f1623b | 6053 | { |
9ebbca7d GK |
6054 | emit_insn (Pmode == SImode |
6055 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
6056 | GEN_INT (sp_offset)) | |
6057 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
6058 | GEN_INT (sp_offset))); | |
13f1623b | 6059 | } |
9ebbca7d | 6060 | } |
b6c9286a | 6061 | |
9ebbca7d GK |
6062 | if (!sibcall) |
6063 | { | |
6064 | rtvec p; | |
6065 | if (! restoring_FPRs_inline) | |
6066 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
6067 | else | |
6068 | p = rtvec_alloc (2); | |
b6c9286a | 6069 | |
9ebbca7d GK |
6070 | RTVEC_ELT (p, 0) = gen_rtx_USE (VOIDmode, |
6071 | gen_rtx_REG (Pmode, | |
6072 | LINK_REGISTER_REGNUM)); | |
6073 | RTVEC_ELT (p, 1) = gen_rtx_RETURN (VOIDmode); | |
6074 | ||
6075 | /* If we have to restore more than two FP registers, branch to the | |
6076 | restore function. It will return to our caller. */ | |
6077 | if (! restoring_FPRs_inline) | |
6078 | { | |
6079 | int i; | |
6080 | char rname[30]; | |
6081 | char *alloc_rname; | |
979721f8 | 6082 | |
9ebbca7d GK |
6083 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
6084 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
6085 | alloc_rname = ggc_alloc_string (rname, -1); | |
6086 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, | |
6087 | gen_rtx_SYMBOL_REF (Pmode, | |
6088 | alloc_rname)); | |
b6c9286a | 6089 | |
9ebbca7d GK |
6090 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
6091 | { | |
6092 | rtx addr, mem; | |
6093 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
6094 | GEN_INT (info->fp_save_offset + 8*i)); | |
6095 | mem = gen_rtx_MEM (DFmode, addr); | |
6096 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6097 | ||
6098 | RTVEC_ELT (p, i+3) = | |
6099 | gen_rtx_SET (VOIDmode, | |
6100 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
6101 | mem); | |
b6c9286a MM |
6102 | } |
6103 | } | |
9ebbca7d GK |
6104 | |
6105 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 6106 | } |
9878760c RK |
6107 | } |
6108 | ||
6109 | /* Write function epilogue. */ | |
6110 | ||
6111 | void | |
6112 | output_epilog (file, size) | |
6113 | FILE *file; | |
296b8152 | 6114 | int size ATTRIBUTE_UNUSED; |
9878760c | 6115 | { |
4697a36c | 6116 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 6117 | |
9ebbca7d | 6118 | if (! HAVE_epilogue) |
9878760c | 6119 | { |
9ebbca7d GK |
6120 | rtx insn = get_last_insn (); |
6121 | /* If the last insn was a BARRIER, we don't have to write anything except | |
6122 | the trace table. */ | |
6123 | if (GET_CODE (insn) == NOTE) | |
6124 | insn = prev_nonnote_insn (insn); | |
6125 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 6126 | { |
9ebbca7d GK |
6127 | /* This is slightly ugly, but at least we don't have two |
6128 | copies of the epilogue-emitting code. */ | |
6129 | start_sequence (); | |
6130 | ||
6131 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
6132 | and end of the "toplevel" insn chain. */ | |
6133 | emit_note (0, NOTE_INSN_DELETED); | |
6134 | rs6000_emit_epilogue (FALSE); | |
6135 | emit_note (0, NOTE_INSN_DELETED); | |
6136 | ||
6137 | if (TARGET_DEBUG_STACK) | |
6138 | debug_rtx_list (get_insns(), 100); | |
6139 | final (get_insns(), file, FALSE, FALSE); | |
6140 | end_sequence (); | |
4697a36c | 6141 | } |
9878760c | 6142 | } |
b4ac57ab | 6143 | |
9b30bae2 | 6144 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
6145 | on its format. |
6146 | ||
6147 | We don't output a traceback table if -finhibit-size-directive was | |
6148 | used. The documentation for -finhibit-size-directive reads | |
6149 | ``don't output a @code{.size} assembler directive, or anything | |
6150 | else that would cause trouble if the function is split in the | |
6151 | middle, and the two halves are placed at locations far apart in | |
6152 | memory.'' The traceback table has this property, since it | |
6153 | includes the offset from the start of the function to the | |
4d30c363 MM |
6154 | traceback table itself. |
6155 | ||
6156 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
6157 | different traceback table. */ |
6158 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 6159 | { |
3cce094d | 6160 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
314fc5a9 ILT |
6161 | int fixed_parms, float_parms, parm_info; |
6162 | int i; | |
6163 | ||
b6c9286a MM |
6164 | while (*fname == '.') /* V.4 encodes . in the name */ |
6165 | fname++; | |
6166 | ||
314fc5a9 ILT |
6167 | /* Need label immediately before tbtab, so we can compute its offset |
6168 | from the function start. */ | |
6169 | if (*fname == '*') | |
6170 | ++fname; | |
6171 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
6172 | ASM_OUTPUT_LABEL (file, fname); | |
6173 | ||
6174 | /* The .tbtab pseudo-op can only be used for the first eight | |
6175 | expressions, since it can't handle the possibly variable | |
6176 | length fields that follow. However, if you omit the optional | |
6177 | fields, the assembler outputs zeros for all optional fields | |
6178 | anyways, giving each variable length field is minimum length | |
6179 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
6180 | pseudo-op at all. */ | |
6181 | ||
6182 | /* An all-zero word flags the start of the tbtab, for debuggers | |
6183 | that have to find it by searching forward from the entry | |
6184 | point or from the current pc. */ | |
19d2d16f | 6185 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
6186 | |
6187 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 6188 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
6189 | |
6190 | /* Language type. Unfortunately, there doesn't seem to be any | |
6191 | official way to get this info, so we use language_string. C | |
6192 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 6193 | value for C for now. There is no official value for Java, |
6f573ff9 JL |
6194 | although IBM appears to be using 13. There is no official value |
6195 | for Chill, so we've choosen 44 pseudo-randomly. */ | |
314fc5a9 | 6196 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 6197 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
6198 | i = 0; |
6199 | else if (! strcmp (language_string, "GNU F77")) | |
6200 | i = 1; | |
6201 | else if (! strcmp (language_string, "GNU Ada")) | |
6202 | i = 3; | |
8b83775b | 6203 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
6204 | i = 2; |
6205 | else if (! strcmp (language_string, "GNU C++")) | |
6206 | i = 9; | |
9517ead8 AG |
6207 | else if (! strcmp (language_string, "GNU Java")) |
6208 | i = 13; | |
6f573ff9 JL |
6209 | else if (! strcmp (language_string, "GNU CHILL")) |
6210 | i = 44; | |
314fc5a9 ILT |
6211 | else |
6212 | abort (); | |
6213 | fprintf (file, "%d,", i); | |
6214 | ||
6215 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
6216 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
6217 | from start of procedure stored in tbtab, internal function, function | |
6218 | has controlled storage, function has no toc, function uses fp, | |
6219 | function logs/aborts fp operations. */ | |
6220 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 6221 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
6222 | |
6223 | /* 6 bitfields: function is interrupt handler, name present in | |
6224 | proc table, function calls alloca, on condition directives | |
6225 | (controls stack walks, 3 bits), saves condition reg, saves | |
6226 | link reg. */ | |
6227 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
6228 | set up as a frame pointer, even when there is no alloca call. */ | |
6229 | fprintf (file, "%d,", | |
6230 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 6231 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
6232 | |
6233 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
6234 | (6 bits). */ | |
6235 | fprintf (file, "%d,", | |
4697a36c | 6236 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
6237 | |
6238 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
6239 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
6240 | ||
6241 | { | |
6242 | /* Compute the parameter info from the function decl argument | |
6243 | list. */ | |
6244 | tree decl; | |
6245 | int next_parm_info_bit; | |
6246 | ||
6247 | next_parm_info_bit = 31; | |
6248 | parm_info = 0; | |
6249 | fixed_parms = 0; | |
6250 | float_parms = 0; | |
6251 | ||
6252 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
6253 | decl; decl = TREE_CHAIN (decl)) | |
6254 | { | |
6255 | rtx parameter = DECL_INCOMING_RTL (decl); | |
6256 | enum machine_mode mode = GET_MODE (parameter); | |
6257 | ||
6258 | if (GET_CODE (parameter) == REG) | |
6259 | { | |
6260 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
6261 | { | |
6262 | int bits; | |
6263 | ||
6264 | float_parms++; | |
6265 | ||
6266 | if (mode == SFmode) | |
6267 | bits = 0x2; | |
6268 | else if (mode == DFmode) | |
6269 | bits = 0x3; | |
6270 | else | |
6271 | abort (); | |
6272 | ||
6273 | /* If only one bit will fit, don't or in this entry. */ | |
6274 | if (next_parm_info_bit > 0) | |
6275 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
6276 | next_parm_info_bit -= 2; | |
6277 | } | |
6278 | else | |
6279 | { | |
6280 | fixed_parms += ((GET_MODE_SIZE (mode) | |
6281 | + (UNITS_PER_WORD - 1)) | |
6282 | / UNITS_PER_WORD); | |
6283 | next_parm_info_bit -= 1; | |
6284 | } | |
6285 | } | |
6286 | } | |
6287 | } | |
6288 | ||
6289 | /* Number of fixed point parameters. */ | |
6290 | /* This is actually the number of words of fixed point parameters; thus | |
6291 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
6292 | fprintf (file, "%d,", fixed_parms); | |
6293 | ||
6294 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
6295 | all on stack. */ | |
6296 | /* This is actually the number of fp registers that hold parameters; | |
6297 | and thus the maximum value is 13. */ | |
6298 | /* Set parameters on stack bit if parameters are not in their original | |
6299 | registers, regardless of whether they are on the stack? Xlc | |
6300 | seems to set the bit when not optimizing. */ | |
6301 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
6302 | ||
6303 | /* Optional fields follow. Some are variable length. */ | |
6304 | ||
6305 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
6306 | 11 double float. */ | |
6307 | /* There is an entry for each parameter in a register, in the order that | |
6308 | they occur in the parameter list. Any intervening arguments on the | |
6309 | stack are ignored. If the list overflows a long (max possible length | |
6310 | 34 bits) then completely leave off all elements that don't fit. */ | |
6311 | /* Only emit this long if there was at least one parameter. */ | |
6312 | if (fixed_parms || float_parms) | |
6313 | fprintf (file, "\t.long %d\n", parm_info); | |
6314 | ||
6315 | /* Offset from start of code to tb table. */ | |
19d2d16f | 6316 | fputs ("\t.long ", file); |
314fc5a9 | 6317 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
9ebbca7d | 6318 | #if TARGET_AIX |
314fc5a9 | 6319 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
6320 | #else |
6321 | assemble_name (file, fname); | |
6322 | #endif | |
19d2d16f | 6323 | fputs ("-.", file); |
9ebbca7d | 6324 | #if TARGET_AIX |
314fc5a9 | 6325 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
6326 | #else |
6327 | assemble_name (file, fname); | |
6328 | #endif | |
19d2d16f | 6329 | putc ('\n', file); |
314fc5a9 ILT |
6330 | |
6331 | /* Interrupt handler mask. */ | |
6332 | /* Omit this long, since we never set the interrupt handler bit | |
6333 | above. */ | |
6334 | ||
6335 | /* Number of CTL (controlled storage) anchors. */ | |
6336 | /* Omit this long, since the has_ctl bit is never set above. */ | |
6337 | ||
6338 | /* Displacement into stack of each CTL anchor. */ | |
6339 | /* Omit this list of longs, because there are no CTL anchors. */ | |
6340 | ||
6341 | /* Length of function name. */ | |
296b8152 | 6342 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
6343 | |
6344 | /* Function name. */ | |
6345 | assemble_string (fname, strlen (fname)); | |
6346 | ||
6347 | /* Register for alloca automatic storage; this is always reg 31. | |
6348 | Only emit this if the alloca bit was set above. */ | |
6349 | if (frame_pointer_needed) | |
19d2d16f | 6350 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 6351 | } |
9878760c | 6352 | } |
17167fd8 MM |
6353 | \f |
6354 | /* A C compound statement that outputs the assembler code for a thunk function, | |
6355 | used to implement C++ virtual function calls with multiple inheritance. The | |
6356 | thunk acts as a wrapper around a virtual function, adjusting the implicit | |
6357 | object parameter before handing control off to the real function. | |
6358 | ||
6359 | First, emit code to add the integer DELTA to the location that contains the | |
6360 | incoming first argument. Assume that this argument contains a pointer, and | |
6361 | is the one used to pass the `this' pointer in C++. This is the incoming | |
6362 | argument *before* the function prologue, e.g. `%o0' on a sparc. The | |
6363 | addition must preserve the values of all other incoming arguments. | |
6364 | ||
6365 | After the addition, emit code to jump to FUNCTION, which is a | |
6366 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch | |
6367 | the return address. Hence returning from FUNCTION will return to whoever | |
6368 | called the current `thunk'. | |
6369 | ||
6370 | The effect must be as if FUNCTION had been called directly with the adjusted | |
6371 | first argument. This macro is responsible for emitting all of the code for | |
6372 | a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not | |
6373 | invoked. | |
6374 | ||
6375 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been | |
6376 | extracted from it.) It might possibly be useful on some targets, but | |
6377 | probably not. | |
6378 | ||
6379 | If you do not define this macro, the target-independent code in the C++ | |
6380 | frontend will generate a less efficient heavyweight thunk that calls | |
6381 | FUNCTION instead of jumping to it. The generic approach does not support | |
6382 | varargs. */ | |
6383 | ||
6384 | void | |
6385 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
6386 | FILE *file; | |
d330fd93 | 6387 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
6388 | int delta; |
6389 | tree function; | |
6390 | { | |
d330fd93 KG |
6391 | const char *this_reg = reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; |
6392 | const char *prefix; | |
3cce094d | 6393 | const char *fname; |
d330fd93 | 6394 | const char *r0 = reg_names[0]; |
d330fd93 KG |
6395 | const char *toc = reg_names[2]; |
6396 | const char *schain = reg_names[11]; | |
6397 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
6398 | char buf[512]; |
6399 | static int labelno = 0; | |
6400 | ||
6401 | /* Small constants that can be done by one add instruction */ | |
6402 | if (delta >= -32768 && delta <= 32767) | |
6403 | { | |
22b4a3b0 | 6404 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
6405 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
6406 | else | |
6407 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
6408 | } | |
6409 | ||
6410 | /* Large constants that can be done by one addis instruction */ | |
6411 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) | |
6412 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
6413 | delta >> 16); | |
6414 | ||
6415 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
6416 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
6417 | { | |
22b4a3b0 | 6418 | /* Break into two pieces, propagating the sign bit from the low word to |
17167fd8 MM |
6419 | the upper word. */ |
6420 | int delta_high = delta >> 16; | |
6421 | int delta_low = delta & 0xffff; | |
6422 | if ((delta_low & 0x8000) != 0) | |
6423 | { | |
6424 | delta_high++; | |
6425 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
6426 | } | |
6427 | ||
6428 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
6429 | delta_high); | |
6430 | ||
22b4a3b0 | 6431 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
6432 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
6433 | else | |
6434 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
6435 | } | |
6436 | ||
6437 | /* 64-bit constants, fixme */ | |
6438 | else | |
6439 | abort (); | |
6440 | ||
6441 | /* Get the prefix in front of the names. */ | |
6442 | switch (DEFAULT_ABI) | |
6443 | { | |
6444 | default: | |
6445 | abort (); | |
6446 | ||
6447 | case ABI_AIX: | |
6448 | prefix = "."; | |
6449 | break; | |
6450 | ||
6451 | case ABI_V4: | |
6452 | case ABI_AIX_NODESC: | |
6453 | case ABI_SOLARIS: | |
6454 | prefix = ""; | |
6455 | break; | |
17167fd8 MM |
6456 | } |
6457 | ||
6458 | /* If the function is compiled in this module, jump to it directly. | |
6459 | Otherwise, load up its address and jump to it. */ | |
6460 | ||
6461 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 6462 | |
9ebbca7d | 6463 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
6464 | && ! lookup_attribute ("longcall", |
6465 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
6466 | { |
6467 | fprintf (file, "\tb %s", prefix); | |
6468 | assemble_name (file, fname); | |
22b4a3b0 | 6469 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 6470 | putc ('\n', file); |
17167fd8 MM |
6471 | } |
6472 | ||
6473 | else | |
6474 | { | |
6475 | switch (DEFAULT_ABI) | |
6476 | { | |
6477 | default: | |
17167fd8 MM |
6478 | abort (); |
6479 | ||
6480 | case ABI_AIX: | |
6481 | /* Set up a TOC entry for the function. */ | |
6482 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
6483 | toc_section (); | |
6484 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
6485 | labelno++; | |
6486 | ||
6487 | /* Note, MINIMAL_TOC doesn't make sense in the case of a thunk, since | |
6488 | there will be only one TOC entry for this function. */ | |
6489 | fputs ("\t.tc\t", file); | |
6490 | assemble_name (file, buf); | |
6491 | fputs ("[TC],", file); | |
6492 | assemble_name (file, buf); | |
6493 | putc ('\n', file); | |
6494 | text_section (); | |
6495 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s", r12); | |
6496 | assemble_name (file, buf); | |
6497 | asm_fprintf (file, "(%s)\n", reg_names[2]); | |
6498 | asm_fprintf (file, | |
6499 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
6500 | r0, r12); | |
6501 | ||
6502 | asm_fprintf (file, | |
6503 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
6504 | toc, r12); | |
6505 | ||
6506 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
6507 | asm_fprintf (file, | |
6508 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
6509 | schain, r12); | |
6510 | ||
6511 | asm_fprintf (file, "\tbctr\n"); | |
6512 | break; | |
6513 | ||
9ebbca7d GK |
6514 | case ABI_AIX_NODESC: |
6515 | case ABI_SOLARIS: | |
17167fd8 | 6516 | case ABI_V4: |
22b4a3b0 FS |
6517 | fprintf (file, "\tb %s", prefix); |
6518 | assemble_name (file, fname); | |
6519 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 6520 | putc ('\n', file); |
22b4a3b0 | 6521 | break; |
9ebbca7d GK |
6522 | } |
6523 | } | |
6524 | } | |
42820a49 | 6525 | |
9ebbca7d GK |
6526 | \f |
6527 | /* A quick summary of the various types of 'constant-pool tables' | |
6528 | under PowerPC: | |
6529 | ||
6530 | Target Flags Name One table per | |
6531 | AIX (none) AIX TOC object file | |
6532 | AIX -mfull-toc AIX TOC object file | |
6533 | AIX -mminimal-toc AIX minimal TOC translation unit | |
6534 | SVR4/EABI (none) SVR4 SDATA object file | |
6535 | SVR4/EABI -fpic SVR4 pic object file | |
6536 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
6537 | SVR4/EABI -mrelocatable EABI TOC function | |
6538 | SVR4/EABI -maix AIX TOC object file | |
6539 | SVR4/EABI -maix -mminimal-toc | |
6540 | AIX minimal TOC translation unit | |
6541 | ||
6542 | Name Reg. Set by entries contains: | |
6543 | made by addrs? fp? sum? | |
6544 | ||
6545 | AIX TOC 2 crt0 as Y option option | |
6546 | AIX minimal TOC 30 prolog gcc Y Y option | |
6547 | SVR4 SDATA 13 crt0 gcc N Y N | |
6548 | SVR4 pic 30 prolog ld Y not yet N | |
6549 | SVR4 PIC 30 prolog gcc Y option option | |
6550 | EABI TOC 30 prolog gcc Y option option | |
6551 | ||
6552 | */ | |
6553 | ||
6554 | /* Hash table stuff for keeping track of TOC entries. */ | |
6555 | ||
6556 | struct toc_hash_struct | |
6557 | { | |
6558 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
6559 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
6560 | rtx key; | |
a9098fd0 | 6561 | enum machine_mode key_mode; |
9ebbca7d GK |
6562 | int labelno; |
6563 | }; | |
17167fd8 | 6564 | |
9ebbca7d GK |
6565 | static htab_t toc_hash_table; |
6566 | ||
6567 | /* Hash functions for the hash table. */ | |
6568 | ||
6569 | static unsigned | |
6570 | rs6000_hash_constant (k) | |
6571 | rtx k; | |
6572 | { | |
a9098fd0 | 6573 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
6574 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
6575 | int flen = strlen (format); | |
6576 | int fidx; | |
6577 | ||
6578 | if (GET_CODE (k) == LABEL_REF) | |
6579 | return result * 1231 + XINT (XEXP (k, 0), 3); | |
6580 | ||
6581 | if (GET_CODE (k) == CONST_DOUBLE) | |
6582 | fidx = 2; | |
6583 | else if (GET_CODE (k) == CODE_LABEL) | |
6584 | fidx = 3; | |
6585 | else | |
6586 | fidx = 0; | |
6587 | ||
6588 | for (; fidx < flen; fidx++) | |
6589 | switch (format[fidx]) | |
6590 | { | |
6591 | case 's': | |
6592 | { | |
6593 | unsigned i, len; | |
6594 | const char *str = XSTR (k, fidx); | |
6595 | len = strlen (str); | |
6596 | result = result * 613 + len; | |
6597 | for (i = 0; i < len; i++) | |
6598 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
6599 | break; |
6600 | } | |
9ebbca7d GK |
6601 | case 'u': |
6602 | case 'e': | |
6603 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
6604 | break; | |
6605 | case 'i': | |
6606 | case 'n': | |
6607 | result = result * 613 + (unsigned) XINT (k, fidx); | |
6608 | break; | |
6609 | case 'w': | |
6610 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
6611 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
6612 | else | |
6613 | { | |
6614 | size_t i; | |
6615 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
6616 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
6617 | >> CHAR_BIT * i); | |
6618 | } | |
6619 | break; | |
6620 | default: | |
6621 | abort(); | |
6622 | } | |
6623 | return result; | |
6624 | } | |
6625 | ||
6626 | static unsigned | |
6627 | toc_hash_function (hash_entry) | |
6628 | const void * hash_entry; | |
6629 | { | |
a9098fd0 GK |
6630 | const struct toc_hash_struct *thc = |
6631 | (const struct toc_hash_struct *) hash_entry; | |
6632 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
6633 | } |
6634 | ||
6635 | /* Compare H1 and H2 for equivalence. */ | |
6636 | ||
6637 | static int | |
6638 | toc_hash_eq (h1, h2) | |
6639 | const void * h1; | |
6640 | const void * h2; | |
6641 | { | |
6642 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
6643 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
6644 | ||
a9098fd0 GK |
6645 | if (((const struct toc_hash_struct *) h1)->key_mode |
6646 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
6647 | return 0; | |
6648 | ||
9ebbca7d GK |
6649 | /* Gotcha: One of these const_doubles will be in memory. |
6650 | The other may be on the constant-pool chain. | |
6651 | So rtx_equal_p will think they are different... */ | |
6652 | if (r1 == r2) | |
6653 | return 1; | |
6654 | if (GET_CODE (r1) != GET_CODE (r2) | |
6655 | || GET_MODE (r1) != GET_MODE (r2)) | |
6656 | return 0; | |
6657 | if (GET_CODE (r1) == CONST_DOUBLE) | |
6658 | { | |
6659 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
6660 | int i; | |
6661 | for (i = 2; i < format_len; i++) | |
6662 | if (XWINT (r1, i) != XWINT (r2, i)) | |
6663 | return 0; | |
6664 | ||
6665 | return 1; | |
17167fd8 | 6666 | } |
9ebbca7d | 6667 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
6668 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
6669 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
6670 | else |
6671 | return rtx_equal_p (r1, r2); | |
6672 | } | |
6673 | ||
6674 | /* Mark the hash table-entry HASH_ENTRY. */ | |
6675 | ||
6676 | static int | |
6677 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 6678 | void ** hash_slot; |
9ebbca7d GK |
6679 | void * unused ATTRIBUTE_UNUSED; |
6680 | { | |
6681 | const struct toc_hash_struct * hash_entry = | |
6682 | *(const struct toc_hash_struct **) hash_slot; | |
6683 | rtx r = hash_entry->key; | |
6684 | ggc_set_mark (hash_entry); | |
6685 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ | |
6686 | if (GET_CODE (r) == LABEL_REF) | |
6687 | { | |
6688 | ggc_set_mark (r); | |
6689 | ggc_set_mark (XEXP (r, 0)); | |
6690 | } | |
6691 | else | |
6692 | ggc_mark_rtx (r); | |
6693 | return 1; | |
6694 | } | |
6695 | ||
6696 | /* Mark all the elements of the TOC hash-table *HT. */ | |
6697 | ||
6698 | static void | |
6699 | toc_hash_mark_table (vht) | |
6700 | void *vht; | |
6701 | { | |
6702 | htab_t *ht = vht; | |
6703 | ||
6704 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
6705 | } |
6706 | ||
9878760c RK |
6707 | /* Output a TOC entry. We derive the entry name from what is |
6708 | being written. */ | |
6709 | ||
6710 | void | |
a9098fd0 | 6711 | output_toc (file, x, labelno, mode) |
9878760c RK |
6712 | FILE *file; |
6713 | rtx x; | |
6714 | int labelno; | |
a9098fd0 | 6715 | enum machine_mode mode; |
9878760c RK |
6716 | { |
6717 | char buf[256]; | |
3cce094d | 6718 | const char *name = buf; |
ec940faa | 6719 | const char *real_name; |
9878760c RK |
6720 | rtx base = x; |
6721 | int offset = 0; | |
6722 | ||
4697a36c MM |
6723 | if (TARGET_NO_TOC) |
6724 | abort (); | |
6725 | ||
9ebbca7d GK |
6726 | /* When the linker won't eliminate them, don't output duplicate |
6727 | TOC entries (this happens on AIX if there is any kind of TOC, | |
6728 | and on SVR4 under -fPIC or -mrelocatable). | |
6729 | This won't work if we are not garbage collecting, so | |
6730 | we don't do it, sorry. */ | |
6731 | if (TARGET_TOC && ggc_p) | |
6732 | { | |
6733 | struct toc_hash_struct *h; | |
6734 | void * * found; | |
6735 | ||
6736 | h = ggc_alloc (sizeof (*h)); | |
6737 | h->key = x; | |
a9098fd0 | 6738 | h->key_mode = mode; |
9ebbca7d GK |
6739 | h->labelno = labelno; |
6740 | ||
6741 | found = htab_find_slot (toc_hash_table, h, 1); | |
6742 | if (*found == NULL) | |
6743 | *found = h; | |
6744 | else /* This is indeed a duplicate. | |
6745 | Set this label equal to that label. */ | |
6746 | { | |
6747 | fputs ("\t.set ", file); | |
6748 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
6749 | fprintf (file, "%d,", labelno); | |
6750 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
6751 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
6752 | found)->labelno)); | |
6753 | return; | |
6754 | } | |
6755 | } | |
6756 | ||
6757 | /* If we're going to put a double constant in the TOC, make sure it's | |
6758 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
6759 | if (GET_CODE (x) == CONST_DOUBLE |
6760 | && STRICT_ALIGNMENT | |
a9098fd0 | 6761 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
6762 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
6763 | ASM_OUTPUT_ALIGN (file, 3); | |
6764 | } | |
6765 | ||
9ebbca7d | 6766 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 6767 | |
37c37a57 RK |
6768 | /* Handle FP constants specially. Note that if we have a minimal |
6769 | TOC, things we put here aren't actually in the TOC, so we can allow | |
6770 | FP constants. */ | |
a9098fd0 | 6771 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 6772 | { |
042259f2 DE |
6773 | REAL_VALUE_TYPE rv; |
6774 | long k[2]; | |
0adc764e | 6775 | |
042259f2 DE |
6776 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
6777 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 6778 | |
13ded975 DE |
6779 | if (TARGET_64BIT) |
6780 | { | |
6781 | if (TARGET_MINIMAL_TOC) | |
6782 | fprintf (file, "\t.llong 0x%lx%08lx\n", k[0], k[1]); | |
6783 | else | |
6784 | fprintf (file, "\t.tc FD_%lx_%lx[TC],0x%lx%08lx\n", | |
0858c623 | 6785 | k[0], k[1], k[0] & 0xffffffff, k[1] & 0xffffffff); |
13ded975 DE |
6786 | return; |
6787 | } | |
1875cc88 | 6788 | else |
13ded975 DE |
6789 | { |
6790 | if (TARGET_MINIMAL_TOC) | |
31bfaa0b | 6791 | fprintf (file, "\t.long 0x%lx\n\t.long 0x%lx\n", k[0], k[1]); |
13ded975 | 6792 | else |
31bfaa0b | 6793 | fprintf (file, "\t.tc FD_%lx_%lx[TC],0x%lx,0x%lx\n", |
13ded975 DE |
6794 | k[0], k[1], k[0], k[1]); |
6795 | return; | |
6796 | } | |
9878760c | 6797 | } |
a9098fd0 | 6798 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 6799 | { |
042259f2 DE |
6800 | REAL_VALUE_TYPE rv; |
6801 | long l; | |
9878760c | 6802 | |
042259f2 DE |
6803 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
6804 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
6805 | ||
31bfaa0b DE |
6806 | if (TARGET_64BIT) |
6807 | { | |
6808 | if (TARGET_MINIMAL_TOC) | |
6809 | fprintf (file, "\t.llong 0x%lx00000000\n", l); | |
6810 | else | |
6811 | fprintf (file, "\t.tc FS_%lx[TC],0x%lx00000000\n", l, l); | |
6812 | return; | |
6813 | } | |
042259f2 | 6814 | else |
31bfaa0b DE |
6815 | { |
6816 | if (TARGET_MINIMAL_TOC) | |
6817 | fprintf (file, "\t.long 0x%lx\n", l); | |
6818 | else | |
6819 | fprintf (file, "\t.tc FS_%lx[TC],0x%lx\n", l, l); | |
6820 | return; | |
6821 | } | |
042259f2 | 6822 | } |
f176e826 | 6823 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 6824 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 6825 | { |
e2c953b6 | 6826 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
6827 | HOST_WIDE_INT high; |
6828 | ||
6829 | if (GET_CODE (x) == CONST_DOUBLE) | |
6830 | { | |
6831 | low = CONST_DOUBLE_LOW (x); | |
6832 | high = CONST_DOUBLE_HIGH (x); | |
6833 | } | |
6834 | else | |
6835 | #if HOST_BITS_PER_WIDE_INT == 32 | |
6836 | { | |
6837 | low = INTVAL (x); | |
0858c623 | 6838 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
6839 | } |
6840 | #else | |
6841 | { | |
0858c623 | 6842 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
6843 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
6844 | } | |
6845 | #endif | |
9878760c | 6846 | |
a9098fd0 GK |
6847 | /* TOC entries are always Pmode-sized, but since this |
6848 | is a bigendian machine then if we're putting smaller | |
6849 | integer constants in the TOC we have to pad them. | |
6850 | (This is still a win over putting the constants in | |
6851 | a separate constant pool, because then we'd have | |
6852 | to have both a TOC entry _and_ the actual constant.) */ | |
6853 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
6854 | abort ();/* It would be easy to make this work, but it doesn't now. */ | |
6855 | if (mode != Pmode) | |
6856 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
6857 | POINTER_SIZE, &low, &high, 0); | |
6858 | ||
13ded975 DE |
6859 | if (TARGET_64BIT) |
6860 | { | |
6861 | if (TARGET_MINIMAL_TOC) | |
6862 | fprintf (file, "\t.llong 0x%lx%08lx\n", (long)high, (long)low); | |
6863 | else | |
6864 | fprintf (file, "\t.tc ID_%lx_%lx[TC],0x%lx%08lx\n", | |
6865 | (long)high, (long)low, (long)high, (long)low); | |
6866 | return; | |
6867 | } | |
1875cc88 | 6868 | else |
13ded975 DE |
6869 | { |
6870 | if (TARGET_MINIMAL_TOC) | |
3cb999d8 | 6871 | fprintf (file, "\t.long 0x%lx\n\t.long 0x%lx\n", |
13ded975 DE |
6872 | (long)high, (long)low); |
6873 | else | |
3cb999d8 | 6874 | fprintf (file, "\t.tc ID_%lx_%lx[TC],0x%lx,0x%lx\n", |
13ded975 DE |
6875 | (long)high, (long)low, (long)high, (long)low); |
6876 | return; | |
6877 | } | |
9878760c RK |
6878 | } |
6879 | ||
6880 | if (GET_CODE (x) == CONST) | |
6881 | { | |
6882 | base = XEXP (XEXP (x, 0), 0); | |
6883 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
6884 | } | |
6885 | ||
6886 | if (GET_CODE (base) == SYMBOL_REF) | |
6887 | name = XSTR (base, 0); | |
6888 | else if (GET_CODE (base) == LABEL_REF) | |
6889 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
6890 | else if (GET_CODE (base) == CODE_LABEL) | |
6891 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
6892 | else | |
6893 | abort (); | |
6894 | ||
2e4eb9b0 | 6895 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 6896 | if (TARGET_MINIMAL_TOC) |
13ded975 | 6897 | fputs (TARGET_32BIT ? "\t.long " : "\t.llong ", file); |
1875cc88 JW |
6898 | else |
6899 | { | |
b6c9286a | 6900 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 6901 | |
1875cc88 JW |
6902 | if (offset < 0) |
6903 | fprintf (file, ".N%d", - offset); | |
6904 | else if (offset) | |
6905 | fprintf (file, ".P%d", offset); | |
9878760c | 6906 | |
19d2d16f | 6907 | fputs ("[TC],", file); |
1875cc88 | 6908 | } |
581bc4de MM |
6909 | |
6910 | /* Currently C++ toc references to vtables can be emitted before it | |
6911 | is decided whether the vtable is public or private. If this is | |
6912 | the case, then the linker will eventually complain that there is | |
6913 | a TOC reference to an unknown section. Thus, for vtables only, | |
6914 | we emit the TOC reference to reference the symbol and not the | |
6915 | section. */ | |
89c01f0e | 6916 | if (strncmp ("_vt.", name, 4) == 0) |
581bc4de | 6917 | { |
89c01f0e | 6918 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
6919 | if (offset < 0) |
6920 | fprintf (file, "%d", offset); | |
6921 | else if (offset > 0) | |
6922 | fprintf (file, "+%d", offset); | |
6923 | } | |
6924 | else | |
6925 | output_addr_const (file, x); | |
19d2d16f | 6926 | putc ('\n', file); |
9878760c RK |
6927 | } |
6928 | \f | |
6929 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
6930 | starting at P to FILE. | |
6931 | ||
6932 | On the RS/6000, we have to do this using the .byte operation and | |
6933 | write out special characters outside the quoted string. | |
6934 | Also, the assembler is broken; very long strings are truncated, | |
6935 | so we must artificially break them up early. */ | |
6936 | ||
6937 | void | |
6938 | output_ascii (file, p, n) | |
6939 | FILE *file; | |
d330fd93 | 6940 | const char *p; |
9878760c RK |
6941 | int n; |
6942 | { | |
6943 | char c; | |
6944 | int i, count_string; | |
d330fd93 KG |
6945 | const char *for_string = "\t.byte \""; |
6946 | const char *for_decimal = "\t.byte "; | |
6947 | const char *to_close = NULL; | |
9878760c RK |
6948 | |
6949 | count_string = 0; | |
6950 | for (i = 0; i < n; i++) | |
6951 | { | |
6952 | c = *p++; | |
6953 | if (c >= ' ' && c < 0177) | |
6954 | { | |
6955 | if (for_string) | |
6956 | fputs (for_string, file); | |
6957 | putc (c, file); | |
6958 | ||
6959 | /* Write two quotes to get one. */ | |
6960 | if (c == '"') | |
6961 | { | |
6962 | putc (c, file); | |
6963 | ++count_string; | |
6964 | } | |
6965 | ||
6966 | for_string = NULL; | |
6967 | for_decimal = "\"\n\t.byte "; | |
6968 | to_close = "\"\n"; | |
6969 | ++count_string; | |
6970 | ||
6971 | if (count_string >= 512) | |
6972 | { | |
6973 | fputs (to_close, file); | |
6974 | ||
6975 | for_string = "\t.byte \""; | |
6976 | for_decimal = "\t.byte "; | |
6977 | to_close = NULL; | |
6978 | count_string = 0; | |
6979 | } | |
6980 | } | |
6981 | else | |
6982 | { | |
6983 | if (for_decimal) | |
6984 | fputs (for_decimal, file); | |
6985 | fprintf (file, "%d", c); | |
6986 | ||
6987 | for_string = "\n\t.byte \""; | |
6988 | for_decimal = ", "; | |
6989 | to_close = "\n"; | |
6990 | count_string = 0; | |
6991 | } | |
6992 | } | |
6993 | ||
6994 | /* Now close the string if we have written one. Then end the line. */ | |
6995 | if (to_close) | |
9ebbca7d | 6996 | fputs (to_close, file); |
9878760c RK |
6997 | } |
6998 | \f | |
6999 | /* Generate a unique section name for FILENAME for a section type | |
7000 | represented by SECTION_DESC. Output goes into BUF. | |
7001 | ||
7002 | SECTION_DESC can be any string, as long as it is different for each | |
7003 | possible section type. | |
7004 | ||
7005 | We name the section in the same manner as xlc. The name begins with an | |
7006 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
7007 | names) with the last period replaced by the string SECTION_DESC. If |
7008 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
7009 | the name. */ | |
9878760c RK |
7010 | |
7011 | void | |
7012 | rs6000_gen_section_name (buf, filename, section_desc) | |
7013 | char **buf; | |
9ebbca7d GK |
7014 | const char *filename; |
7015 | const char *section_desc; | |
9878760c | 7016 | { |
9ebbca7d | 7017 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
7018 | char *p; |
7019 | int len; | |
9878760c RK |
7020 | |
7021 | after_last_slash = filename; | |
7022 | for (q = filename; *q; q++) | |
11e5fe42 RK |
7023 | { |
7024 | if (*q == '/') | |
7025 | after_last_slash = q + 1; | |
7026 | else if (*q == '.') | |
7027 | last_period = q; | |
7028 | } | |
9878760c | 7029 | |
11e5fe42 | 7030 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
7031 | *buf = (char *) permalloc (len); |
7032 | ||
7033 | p = *buf; | |
7034 | *p++ = '_'; | |
7035 | ||
7036 | for (q = after_last_slash; *q; q++) | |
7037 | { | |
11e5fe42 | 7038 | if (q == last_period) |
9878760c RK |
7039 | { |
7040 | strcpy (p, section_desc); | |
7041 | p += strlen (section_desc); | |
9878760c RK |
7042 | } |
7043 | ||
e9a780ec | 7044 | else if (ISALNUM (*q)) |
9878760c RK |
7045 | *p++ = *q; |
7046 | } | |
7047 | ||
11e5fe42 | 7048 | if (last_period == 0) |
9878760c RK |
7049 | strcpy (p, section_desc); |
7050 | else | |
7051 | *p = '\0'; | |
7052 | } | |
e165f3f0 RK |
7053 | \f |
7054 | /* Write function profiler code. */ | |
7055 | ||
7056 | void | |
7057 | output_function_profiler (file, labelno) | |
7058 | FILE *file; | |
7059 | int labelno; | |
7060 | { | |
7061 | /* The last used parameter register. */ | |
7062 | int last_parm_reg; | |
7063 | int i, j; | |
3daf36a4 | 7064 | char buf[100]; |
e165f3f0 | 7065 | |
3daf36a4 | 7066 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 7067 | switch (DEFAULT_ABI) |
3daf36a4 | 7068 | { |
38c1f2d7 MM |
7069 | default: |
7070 | abort (); | |
7071 | ||
7072 | case ABI_V4: | |
7073 | case ABI_SOLARIS: | |
7074 | case ABI_AIX_NODESC: | |
7075 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
7076 | if (flag_pic == 1) | |
7077 | { | |
dfdfa60f DE |
7078 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
7079 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
7080 | reg_names[0], reg_names[1]); | |
17167fd8 | 7081 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 7082 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 7083 | assemble_name (file, buf); |
17167fd8 | 7084 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 7085 | } |
9ebbca7d | 7086 | else if (flag_pic > 1) |
38c1f2d7 | 7087 | { |
dfdfa60f DE |
7088 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7089 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
7090 | /* Now, we need to get the address of the label. */ |
7091 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 7092 | assemble_name (file, buf); |
9ebbca7d GK |
7093 | fputs ("-.\n1:", file); |
7094 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
7095 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
7096 | reg_names[0], reg_names[11]); | |
7097 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
7098 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 7099 | } |
38c1f2d7 MM |
7100 | else |
7101 | { | |
17167fd8 | 7102 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 7103 | assemble_name (file, buf); |
dfdfa60f | 7104 | fputs ("@ha\n", file); |
b5253831 DE |
7105 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7106 | reg_names[0], reg_names[1]); | |
a260abc9 | 7107 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 7108 | assemble_name (file, buf); |
17167fd8 | 7109 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
7110 | } |
7111 | ||
b5253831 DE |
7112 | if (current_function_needs_context) |
7113 | asm_fprintf (file, "\tmr %s,%s\n", | |
7114 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 7115 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
7116 | if (current_function_needs_context) |
7117 | asm_fprintf (file, "\tmr %s,%s\n", | |
7118 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
7119 | break; |
7120 | ||
7121 | case ABI_AIX: | |
7122 | /* Set up a TOC entry for the profiler label. */ | |
7123 | toc_section (); | |
7124 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno); | |
7125 | if (TARGET_MINIMAL_TOC) | |
7126 | { | |
13ded975 | 7127 | fputs (TARGET_32BIT ? "\t.long " : "\t.llong ", file); |
38c1f2d7 MM |
7128 | assemble_name (file, buf); |
7129 | putc ('\n', file); | |
7130 | } | |
7131 | else | |
7132 | { | |
7133 | fputs ("\t.tc\t", file); | |
7134 | assemble_name (file, buf); | |
7135 | fputs ("[TC],", file); | |
7136 | assemble_name (file, buf); | |
7137 | putc ('\n', file); | |
7138 | } | |
7139 | text_section (); | |
e165f3f0 RK |
7140 | |
7141 | /* Figure out last used parameter register. The proper thing to do is | |
7142 | to walk incoming args of the function. A function might have live | |
7143 | parameter registers even if it has no incoming args. */ | |
7144 | ||
38c1f2d7 MM |
7145 | for (last_parm_reg = 10; |
7146 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
7147 | last_parm_reg--) | |
7148 | ; | |
e165f3f0 | 7149 | |
b5253831 DE |
7150 | /* Save parameter registers in regs 23-30 and static chain in r22. |
7151 | Don't overwrite reg 31, since it might be set up as the frame pointer. */ | |
e165f3f0 | 7152 | |
38c1f2d7 MM |
7153 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) |
7154 | asm_fprintf (file, "\tmr %d,%d\n", j, i); | |
b5253831 DE |
7155 | if (current_function_needs_context) |
7156 | asm_fprintf (file, "\tmr %d,%d\n", j, STATIC_CHAIN_REGNUM); | |
e165f3f0 RK |
7157 | |
7158 | /* Load location address into r3, and call mcount. */ | |
7159 | ||
38c1f2d7 | 7160 | ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno); |
13ded975 DE |
7161 | asm_fprintf (file, TARGET_32BIT ? "\t{l|lwz} %s," : "\tld %s,", |
7162 | reg_names[3]); | |
38c1f2d7 | 7163 | assemble_name (file, buf); |
13f1623b DE |
7164 | asm_fprintf (file, "(%s)\n\tbl %s\n\t", reg_names[2], RS6000_MCOUNT); |
7165 | asm_fprintf (file, RS6000_CALL_GLUE); | |
7166 | putc('\n', file); | |
e165f3f0 | 7167 | |
b5253831 | 7168 | /* Restore parameter registers and static chain. */ |
e165f3f0 | 7169 | |
38c1f2d7 MM |
7170 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) |
7171 | asm_fprintf (file, "\tmr %d,%d\n", i, j); | |
b5253831 DE |
7172 | if (current_function_needs_context) |
7173 | asm_fprintf (file, "\tmr %d,%d\n", STATIC_CHAIN_REGNUM, j); | |
7174 | ||
38c1f2d7 MM |
7175 | break; |
7176 | } | |
e165f3f0 | 7177 | } |
a251ffd0 TG |
7178 | |
7179 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7180 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7181 | ||
7182 | int | |
a06faf84 | 7183 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
7184 | rtx insn; |
7185 | rtx link; | |
296b8152 | 7186 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
7187 | int cost; |
7188 | { | |
7189 | if (! recog_memoized (insn)) | |
7190 | return 0; | |
7191 | ||
7192 | if (REG_NOTE_KIND (link) != 0) | |
7193 | return 0; | |
7194 | ||
7195 | if (REG_NOTE_KIND (link) == 0) | |
7196 | { | |
7197 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7198 | cycles later. */ | |
7199 | ||
7200 | /* Tell the first scheduling pass about the latency between a mtctr | |
7201 | and bctr (and mtlr and br/blr). The first scheduling pass will not | |
7202 | know about this latency since the mtctr instruction, which has the | |
7203 | latency associated to it, will be generated by reload. */ | |
7204 | if (get_attr_type (insn) == TYPE_JMPREG) | |
7205 | return TARGET_POWER ? 5 : 4; | |
7206 | ||
7207 | /* Fall out to return default cost. */ | |
7208 | } | |
7209 | ||
7210 | return cost; | |
7211 | } | |
b6c9286a | 7212 | |
bef84347 VM |
7213 | /* A C statement (sans semicolon) to update the integer scheduling priority |
7214 | INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier, | |
7215 | increase the priority to execute INSN later. Do not define this macro if | |
7216 | you do not need to adjust the scheduling priorities of insns. */ | |
7217 | ||
7218 | int | |
7219 | rs6000_adjust_priority (insn, priority) | |
d330fd93 | 7220 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
7221 | int priority; |
7222 | { | |
7223 | /* On machines (like the 750) which have asymetric integer units, where one | |
7224 | integer unit can do multiply and divides and the other can't, reduce the | |
7225 | priority of multiply/divide so it is scheduled before other integer | |
7226 | operationss. */ | |
7227 | ||
7228 | #if 0 | |
2c3c49de | 7229 | if (! INSN_P (insn)) |
bef84347 VM |
7230 | return priority; |
7231 | ||
7232 | if (GET_CODE (PATTERN (insn)) == USE) | |
7233 | return priority; | |
7234 | ||
7235 | switch (rs6000_cpu_attr) { | |
7236 | case CPU_PPC750: | |
7237 | switch (get_attr_type (insn)) | |
7238 | { | |
7239 | default: | |
7240 | break; | |
7241 | ||
7242 | case TYPE_IMUL: | |
7243 | case TYPE_IDIV: | |
3cb999d8 DE |
7244 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
7245 | priority, priority); | |
bef84347 VM |
7246 | if (priority >= 0 && priority < 0x01000000) |
7247 | priority >>= 3; | |
7248 | break; | |
7249 | } | |
7250 | } | |
7251 | #endif | |
7252 | ||
7253 | return priority; | |
7254 | } | |
7255 | ||
b6c9286a MM |
7256 | /* Return how many instructions the machine can issue per cycle */ |
7257 | int get_issue_rate() | |
7258 | { | |
7259 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
7260 | case CPU_RIOS1: /* ? */ |
7261 | case CPU_RS64A: | |
7262 | case CPU_PPC601: /* ? */ | |
7263 | return 3; | |
b6c9286a | 7264 | case CPU_PPC603: |
bef84347 VM |
7265 | case CPU_PPC750: |
7266 | return 2; | |
3cb999d8 | 7267 | case CPU_RIOS2: |
b6c9286a | 7268 | case CPU_PPC604: |
19684119 | 7269 | case CPU_PPC604E: |
b6c9286a | 7270 | case CPU_PPC620: |
3cb999d8 | 7271 | case CPU_PPC630: |
b6c9286a MM |
7272 | return 4; |
7273 | default: | |
7274 | return 1; | |
7275 | } | |
7276 | } | |
7277 | ||
b6c9286a | 7278 | \f |
b6c9286a MM |
7279 | /* Length in units of the trampoline for entering a nested function. */ |
7280 | ||
7281 | int | |
7282 | rs6000_trampoline_size () | |
7283 | { | |
7284 | int ret = 0; | |
7285 | ||
7286 | switch (DEFAULT_ABI) | |
7287 | { | |
7288 | default: | |
7289 | abort (); | |
7290 | ||
7291 | case ABI_AIX: | |
8f802bfb | 7292 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
7293 | break; |
7294 | ||
7295 | case ABI_V4: | |
c81bebd7 | 7296 | case ABI_SOLARIS: |
b6c9286a | 7297 | case ABI_AIX_NODESC: |
03a7e1a5 | 7298 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 7299 | break; |
b6c9286a MM |
7300 | } |
7301 | ||
7302 | return ret; | |
7303 | } | |
7304 | ||
7305 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
7306 | FNADDR is an RTX for the address of the function's pure code. | |
7307 | CXT is an RTX for the static chain value for the function. */ | |
7308 | ||
7309 | void | |
7310 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
7311 | rtx addr; | |
7312 | rtx fnaddr; | |
7313 | rtx cxt; | |
7314 | { | |
ac2a93a1 | 7315 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
7316 | int regsize = (TARGET_32BIT) ? 4 : 8; |
7317 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
7318 | |
7319 | switch (DEFAULT_ABI) | |
7320 | { | |
7321 | default: | |
7322 | abort (); | |
7323 | ||
8bd04c56 | 7324 | /* Macros to shorten the code expansions below. */ |
39403d82 | 7325 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
7326 | #define MEM_PLUS(addr,offset) \ |
7327 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 7328 | |
b6c9286a MM |
7329 | /* Under AIX, just build the 3 word function descriptor */ |
7330 | case ABI_AIX: | |
8bd04c56 MM |
7331 | { |
7332 | rtx fn_reg = gen_reg_rtx (pmode); | |
7333 | rtx toc_reg = gen_reg_rtx (pmode); | |
7334 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
7335 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, 4)); | |
7336 | emit_move_insn (MEM_DEREF (addr), fn_reg); | |
7337 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
7338 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
7339 | } | |
b6c9286a MM |
7340 | break; |
7341 | ||
eaf1bcf1 | 7342 | /* Under V.4/eabi, call __trampoline_setup to do the real work. */ |
b6c9286a | 7343 | case ABI_V4: |
c81bebd7 | 7344 | case ABI_SOLARIS: |
b6c9286a | 7345 | case ABI_AIX_NODESC: |
39403d82 | 7346 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
7347 | FALSE, VOIDmode, 4, |
7348 | addr, pmode, | |
7349 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
7350 | fnaddr, pmode, | |
7351 | ctx_reg, pmode); | |
b6c9286a | 7352 | break; |
b6c9286a MM |
7353 | } |
7354 | ||
7355 | return; | |
7356 | } | |
7509c759 MM |
7357 | |
7358 | \f | |
7359 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
7360 | with arguments ARGS is a valid machine specific attribute for DECL. | |
7361 | The attributes in ATTRIBUTES have previously been assigned to DECL. */ | |
7362 | ||
7363 | int | |
7364 | rs6000_valid_decl_attribute_p (decl, attributes, identifier, args) | |
296b8152 KG |
7365 | tree decl ATTRIBUTE_UNUSED; |
7366 | tree attributes ATTRIBUTE_UNUSED; | |
7367 | tree identifier ATTRIBUTE_UNUSED; | |
7368 | tree args ATTRIBUTE_UNUSED; | |
7509c759 MM |
7369 | { |
7370 | return 0; | |
7371 | } | |
7372 | ||
7373 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
7374 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
7375 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
7376 | ||
7377 | int | |
7378 | rs6000_valid_type_attribute_p (type, attributes, identifier, args) | |
7379 | tree type; | |
296b8152 | 7380 | tree attributes ATTRIBUTE_UNUSED; |
7509c759 MM |
7381 | tree identifier; |
7382 | tree args; | |
7383 | { | |
7384 | if (TREE_CODE (type) != FUNCTION_TYPE | |
7385 | && TREE_CODE (type) != FIELD_DECL | |
7386 | && TREE_CODE (type) != TYPE_DECL) | |
7387 | return 0; | |
7388 | ||
6a4cee5f MM |
7389 | /* Longcall attribute says that the function is not within 2**26 bytes |
7390 | of the current function, and to do an indirect call. */ | |
7391 | if (is_attribute_p ("longcall", identifier)) | |
7392 | return (args == NULL_TREE); | |
7393 | ||
7509c759 MM |
7394 | return 0; |
7395 | } | |
7396 | ||
7397 | /* If defined, a C expression whose value is zero if the attributes on | |
7398 | TYPE1 and TYPE2 are incompatible, one if they are compatible, and | |
7399 | two if they are nearly compatible (which causes a warning to be | |
7400 | generated). */ | |
7401 | ||
7402 | int | |
7403 | rs6000_comp_type_attributes (type1, type2) | |
296b8152 KG |
7404 | tree type1 ATTRIBUTE_UNUSED; |
7405 | tree type2 ATTRIBUTE_UNUSED; | |
7509c759 MM |
7406 | { |
7407 | return 1; | |
7408 | } | |
7409 | ||
7410 | /* If defined, a C statement that assigns default attributes to newly | |
7411 | defined TYPE. */ | |
7412 | ||
7413 | void | |
7414 | rs6000_set_default_type_attributes (type) | |
296b8152 | 7415 | tree type ATTRIBUTE_UNUSED; |
7509c759 | 7416 | { |
3cb999d8 | 7417 | return; |
7509c759 MM |
7418 | } |
7419 | ||
3cb999d8 DE |
7420 | /* Return a reference suitable for calling a function with the |
7421 | longcall attribute. */ | |
6a4cee5f MM |
7422 | struct rtx_def * |
7423 | rs6000_longcall_ref (call_ref) | |
7424 | rtx call_ref; | |
7425 | { | |
d330fd93 | 7426 | const char *call_name; |
6a4cee5f MM |
7427 | tree node; |
7428 | ||
7429 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
7430 | return call_ref; | |
7431 | ||
7432 | /* System V adds '.' to the internal name, so skip them. */ | |
7433 | call_name = XSTR (call_ref, 0); | |
7434 | if (*call_name == '.') | |
7435 | { | |
7436 | while (*call_name == '.') | |
7437 | call_name++; | |
7438 | ||
7439 | node = get_identifier (call_name); | |
39403d82 | 7440 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
7441 | } |
7442 | ||
7443 | return force_reg (Pmode, call_ref); | |
7444 | } | |
7445 | ||
7509c759 MM |
7446 | \f |
7447 | /* A C statement or statements to switch to the appropriate section | |
7448 | for output of RTX in mode MODE. You can assume that RTX is some | |
7449 | kind of constant in RTL. The argument MODE is redundant except in | |
7450 | the case of a `const_int' rtx. Select the section by calling | |
7451 | `text_section' or one of the alternatives for other sections. | |
7452 | ||
7453 | Do not define this macro if you put all constants in the read-only | |
7454 | data section. */ | |
7455 | ||
7456 | #ifdef USING_SVR4_H | |
7457 | ||
7458 | void | |
7459 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 7460 | enum machine_mode mode; |
7509c759 MM |
7461 | rtx x; |
7462 | { | |
a9098fd0 | 7463 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 7464 | toc_section (); |
7509c759 MM |
7465 | else |
7466 | const_section (); | |
7467 | } | |
7468 | ||
7469 | /* A C statement or statements to switch to the appropriate | |
7470 | section for output of DECL. DECL is either a `VAR_DECL' node | |
7471 | or a constant of some sort. RELOC indicates whether forming | |
7472 | the initial value of DECL requires link-time relocations. */ | |
7473 | ||
7474 | void | |
7475 | rs6000_select_section (decl, reloc) | |
7476 | tree decl; | |
7477 | int reloc; | |
7478 | { | |
7479 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
7480 | int needs_sdata; |
7481 | int readonly; | |
7482 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
7483 | &const_section, | |
7484 | &sdata2_section, | |
7485 | &data_section, | |
7486 | &sdata_section | |
7487 | }; | |
7488 | ||
7489 | needs_sdata = (size > 0 | |
7490 | && size <= g_switch_value | |
7491 | && rs6000_sdata != SDATA_NONE | |
7492 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
7493 | |
7494 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 7495 | readonly = ! flag_writable_strings; |
a9098fd0 | 7496 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
7497 | readonly = (! (flag_pic && reloc) |
7498 | && TREE_READONLY (decl) | |
7499 | && ! TREE_SIDE_EFFECTS (decl) | |
7500 | && DECL_INITIAL (decl) | |
7501 | && DECL_INITIAL (decl) != error_mark_node | |
7502 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
7509c759 | 7503 | else |
63019373 GK |
7504 | readonly = 1; |
7505 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
7506 | readonly = 0; | |
7507 | ||
7508 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
7509 | } | |
7510 | ||
7511 | /* A C statement to build up a unique section name, expressed as a | |
7512 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
7513 | RELOC indicates whether the initial value of EXP requires | |
7514 | link-time relocations. If you do not define this macro, GCC will use | |
7515 | the symbol name prefixed by `.' as the section name. Note - this | |
7516 | macro can now be called for unitialised data items as well as | |
7517 | initialised data and functions. */ | |
7518 | ||
7519 | void | |
7520 | rs6000_unique_section (decl, reloc) | |
7521 | tree decl; | |
7522 | int reloc; | |
7523 | { | |
7524 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
7525 | int needs_sdata; | |
7526 | int readonly; | |
7527 | int len; | |
7528 | int sec; | |
7529 | const char *name; | |
7530 | char *string; | |
7531 | const char *prefix; | |
7532 | ||
7533 | static const char *const prefixes[7][2] = | |
7534 | { | |
7535 | { ".text.", ".gnu.linkonce.t." }, | |
7536 | { ".rodata.", ".gnu.linkonce.r." }, | |
7537 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
7538 | { ".data.", ".gnu.linkonce.d." }, | |
7539 | { ".sdata.", ".gnu.linkonce.s." }, | |
7540 | { ".bss.", ".gnu.linkonce.b." }, | |
7541 | { ".sbss.", ".gnu.linkonce.sb." } | |
7542 | }; | |
7543 | ||
7544 | needs_sdata = (TREE_CODE (decl) != FUNCTION_DECL | |
7545 | && size > 0 | |
7546 | && size <= g_switch_value | |
7547 | && rs6000_sdata != SDATA_NONE | |
7548 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7549 | ||
7550 | if (TREE_CODE (decl) == STRING_CST) | |
7551 | readonly = ! flag_writable_strings; | |
7552 | else if (TREE_CODE (decl) == VAR_DECL) | |
7553 | readonly = (! (flag_pic && reloc) | |
7554 | && TREE_READONLY (decl) | |
7555 | && ! TREE_SIDE_EFFECTS (decl) | |
7556 | && DECL_INITIAL (decl) | |
7557 | && DECL_INITIAL (decl) != error_mark_node | |
7558 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
7559 | else | |
7560 | readonly = 1; | |
7561 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
7562 | readonly = 0; | |
7563 | ||
7564 | sec = ((TREE_CODE (decl) == FUNCTION_DECL ? 0 : 1) | |
7565 | + (readonly ? 0 : 2) | |
7566 | + (needs_sdata ? 1 : 0) | |
7567 | + (DECL_INITIAL (decl) == 0 | |
7568 | || DECL_INITIAL (decl) == error_mark_node) ? 4 : 0); | |
7569 | ||
7570 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
7571 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; | |
7572 | len = strlen (name) + strlen (prefix); | |
7573 | string = alloca (len + 1); | |
7574 | ||
7575 | sprintf (string, "%s%s", prefix, name); | |
7576 | ||
7577 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 7578 | } |
d9407988 MM |
7579 | |
7580 | \f | |
d9407988 MM |
7581 | /* If we are referencing a function that is static or is known to be |
7582 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
7583 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 7584 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
7585 | function name with the real name (1 or 2 leading .'s), rather than |
7586 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 7587 | to read the prefixes. */ |
d9407988 MM |
7588 | |
7589 | void | |
7590 | rs6000_encode_section_info (decl) | |
7591 | tree decl; | |
7592 | { | |
7593 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
7594 | { | |
7595 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 7596 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 7597 | && ! DECL_WEAK (decl)) |
d9407988 MM |
7598 | SYMBOL_REF_FLAG (sym_ref) = 1; |
7599 | ||
9ebbca7d | 7600 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 7601 | { |
ff669a6c RH |
7602 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
7603 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
7604 | char *str; | |
7605 | ||
7606 | if (ggc_p) | |
7607 | str = ggc_alloc_string (NULL, len1 + len2); | |
7608 | else | |
7609 | str = permalloc (len1 + len2 + 1); | |
7610 | ||
7611 | str[0] = '.'; | |
7612 | str[1] = '.'; | |
7613 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
7614 | ||
d9407988 MM |
7615 | XSTR (sym_ref, 0) = str; |
7616 | } | |
7617 | } | |
7618 | else if (rs6000_sdata != SDATA_NONE | |
7619 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
7620 | && TREE_CODE (decl) == VAR_DECL) | |
7621 | { | |
7622 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
7623 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 7624 | const char *name = (char *)0; |
d9407988 MM |
7625 | int len = 0; |
7626 | ||
7627 | if (section_name) | |
7628 | { | |
7629 | if (TREE_CODE (section_name) == STRING_CST) | |
7630 | { | |
7631 | name = TREE_STRING_POINTER (section_name); | |
7632 | len = TREE_STRING_LENGTH (section_name); | |
7633 | } | |
7634 | else | |
7635 | abort (); | |
7636 | } | |
7637 | ||
7638 | if ((size > 0 && size <= g_switch_value) | |
7639 | || (name | |
5f59ecb7 | 7640 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 7641 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 7642 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 7643 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 7644 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 7645 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 7646 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 7647 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 7648 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 7649 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 7650 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 7651 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
7652 | { |
7653 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c RH |
7654 | size_t len = strlen (XSTR (sym_ref, 0)); |
7655 | char *str; | |
7656 | ||
7657 | if (ggc_p) | |
7658 | str = ggc_alloc_string (NULL, len + 1); | |
7659 | else | |
7660 | str = permalloc (len + 2); | |
7661 | str[0] = '@'; | |
7662 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
7663 | ||
d9407988 MM |
7664 | XSTR (sym_ref, 0) = str; |
7665 | } | |
7666 | } | |
7667 | } | |
7668 | ||
7509c759 | 7669 | #endif /* USING_SVR4_H */ |
000034eb | 7670 | |
a6c2a102 | 7671 | \f |
000034eb | 7672 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
7673 | ADDR can be effectively incremented by incrementing REG. |
7674 | ||
7675 | r0 is special and we must not select it as an address | |
7676 | register by this routine since our caller will try to | |
7677 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
7678 | |
7679 | struct rtx_def * | |
7680 | find_addr_reg (addr) | |
7681 | rtx addr; | |
7682 | { | |
7683 | while (GET_CODE (addr) == PLUS) | |
7684 | { | |
02441cd6 JL |
7685 | if (GET_CODE (XEXP (addr, 0)) == REG |
7686 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 7687 | addr = XEXP (addr, 0); |
02441cd6 JL |
7688 | else if (GET_CODE (XEXP (addr, 1)) == REG |
7689 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
7690 | addr = XEXP (addr, 1); |
7691 | else if (CONSTANT_P (XEXP (addr, 0))) | |
7692 | addr = XEXP (addr, 1); | |
7693 | else if (CONSTANT_P (XEXP (addr, 1))) | |
7694 | addr = XEXP (addr, 0); | |
7695 | else | |
7696 | abort (); | |
7697 | } | |
02441cd6 | 7698 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
7699 | return addr; |
7700 | abort (); | |
7701 | } | |
7702 | ||
a6c2a102 DE |
7703 | void |
7704 | rs6000_fatal_bad_address (op) | |
7705 | rtx op; | |
7706 | { | |
7707 | fatal_insn ("bad address", op); | |
7708 | } | |
c8023011 MM |
7709 | |
7710 | /* Called to register all of our global variables with the garbage | |
7711 | collector. */ | |
7712 | ||
7713 | static void | |
7714 | rs6000_add_gc_roots () | |
7715 | { | |
7716 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
7717 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
7718 | |
7719 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
7720 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
7721 | toc_hash_mark_table); | |
c8023011 | 7722 | } |